mirror of https://github.com/RT-Thread/rt-thread
[bsp][stm32]: add NUCLEO-H563ZI (#7987)
This commit is contained in:
yuanzihao
GitHub
parent
6db430bde6
commit
32d479321b
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@ -135,7 +135,7 @@ jobs:
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- "stm32/stm32f429-st-disco"
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- "stm32/stm32f446-st-nucleo"
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- "stm32/stm32f469-st-disco"
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- RTT_BSP: "stm32_f7_g0_h7_mp15_u5_wb5"
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- RTT_BSP: "stm32_f7_g0_h7_mp15_u5_h5_wb5"
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RTT_TOOL_CHAIN: "sourcery-arm"
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SUB_RTT_BSP:
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- "stm32/stm32f746-st-disco"
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@ -149,6 +149,7 @@ jobs:
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- "stm32/stm32g071-st-nucleo"
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- "stm32/stm32g431-st-nucleo"
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- "stm32/stm32g474-st-nucleo"
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- "stm32/stm32h563-st-nucleo"
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- "stm32/stm32h743-armfly-v7"
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- "stm32/stm32h743-atk-apollo"
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- "stm32/stm32h743-openmv-h7plus"
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@ -1,108 +1,109 @@
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# STM32 BSP 说明
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STM32 系列 BSP 目前支持情况如下表所示：
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| **BSP 文件夹名称** | **开发板名称** |
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|:------------------------- |:-------------------------- |
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| **F0 系列** | |
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| [stm32f072-st-nucleo](stm32f072-st-nucleo) | ST 官方 STM32F072-nucleo 开发板 |
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| [stm32f091-st-nucleo](stm32f091-st-nucleo) | ST 官方 STM32F091-nucleo 开发板 |
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| **F1 系列** | |
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| [stm32f103-100ask-mini](stm32f103-100ask-mini) | 百问网F103 Mini开发板 |
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| [stm32f103-100ask-pro](stm32f103-100ask-pro) | 百问网F103 Pro开发板 |
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| [stm32f103-atk-nano](stm32f103-atk-nano) | 正点原子 F103 NANO 开发板 |
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| [stm32f103-atk-warshipv3](stm32f103-atk-warshipv3) | 正点原子 F103 战舰V3 开发板 |
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| [stm32f103-blue-pill](stm32f103-blue-pill) | STM32F103C8T6蓝色最小系统板 |
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| [stm32f103-dofly-lyc8](stm32f103-dofly-lyc8) | 德飞莱 STM32F103 开发板 |
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| [stm32f103-dofly-M3S](stm32f103-dofly-M3S) | 德飞莱 STM32F103 开发板 |
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| [stm32f103-fire-arbitrary](stm32f103-fire-arbitrary/) | 野火 F103 霸道开发板 |
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| [stm32f103-gizwits-gokitv21](stm32f103-gizwits-gokitv21) | GoKit V2.1开发板 |
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| [stm32f103-hw100k-ibox](stm32f103-hw100k-ibox) | 硬件十万个为什么 STM32F103 iBox 开发板 |
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| [stm32f103-onenet-nbiot](stm32f103-onenet-nbiot) | STM32F103 OneNET NB-IoT 开发板 |
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| [stm32f103-yf-ufun](stm32f103-yf-ufun) | STM32F103 yf-ufun 开发板 |
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| [stm32f107-uc-eval](stm32f107-uc-eval) | uC/Eval STM32F107 评估板（中国版） |
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| **F2 系列** | |
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| [stm32f207-st-nucleo](stm32f207-st-nucleo) | ST 官方 STM32F207-nucleo 开发板 |
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| **F3 系列** | |
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| [stm32f302-st-nucleo](stm32f302-st-nucleo) | ST 官方 STM32F302-nucleo 开发板 |
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| [stm32f334-st-nucleo](stm32f334-st-nucleo) | ST 官方 STM32F334-nucleo 开发板 |
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| **F4 系列** | |
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| [stm32f407-rt-spark](stm32f407-rt-spark) | 睿赛德官方 F407 星火一号开发板 |
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| [stm32f401-st-nucleo](stm32f401-st-nucleo) | ST 官方 STM32F401 Nucleo-64 开发板 |
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| [stm32f405-smdz-breadfruit](stm32f405-smdz-breadfruit) | 三木电子 SM1432F405 开发板 |
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| [stm32f407-atk-explorer](stm32f407-atk-explorer) | 正点原子 F407 探索者开发板 |
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| [stm32f407-robomaster-c](stm32f407-robomaster-c) | 大疆公司 RoboMaster C型开发板 |
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| [stm32f407-st-discovery](stm32f407-st-discovery) | ST 官方 STM32F407-discovery 开发板 |
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| [stm32f410-st-nucleo](stm32f410-st-nucleo) | ST 官方 STM32F410-Nucleo-64 开发板 |
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| [stm32f411-atk-nano](stm32f411-atk-nano/) | 正点原子 F411 NANO 开发板 |
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| [stm32f411-st-nucleo](stm32f411-st-nucleo/) | ST 官方 STM32F411-Nucleo-64 开发板 |
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| [stm32f411-weact-MiniF4](stm32f411-weact-MiniF4/) | F401/F411最小系统开发板（Black Pill） |
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| [stm32f412-st-nucleo](stm32f412-st-nucleo/) | ST 官方 STM32F412-Nucleo-144 开发板 |
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| [stm32f413-st-nucleo](stm32f413-st-nucleo/) | ST 官方 STM32F413-Nucleo-144 开发板 |
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| [stm32f427-robomaster-a](stm32f427-robomaster-a/) |大疆公司 RoboMaster A型开发板|
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| [stm32f429-armfly-v6](stm32f429-armfly-v6) |安富莱 F429-v6 开发板|
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| [stm32f429-atk-apollo](stm32f429-atk-apollo) |正点原子 F429 阿波罗开发板|
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| [stm32f429-fire-challenger](stm32f429-fire-challenger/) |野火 F429 挑战者开发板|
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| [stm32f429-st-disco](stm32f429-st-disco) | ST 官方 STM32F429-discovery 开发板 |
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| [stm32f446-st-nucleo](stm32f446-st-nucleo) | ST 官方 STM32F446-nucleo 开发板 |
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| [stm32f469-st-disco](stm32f469-st-disco) | ST 官方 STM32F469-discovery 开发板 |
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| **F7 系列** | |
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| [stm32f746-st-disco](stm32f746-st-disco) | ST 官方 STM32F746-discovery 开发板 |
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| [stm32f767-atk-apollo](stm32f767-atk-apollo) | 正点原子 F767 阿波罗开发板 |
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| [stm32f767-fire-challenger-v1](stm32f767-fire-challenger-v1/) | 野火 F767-V1 挑战者开发板 |
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| [stm32f767-st-nucleo](stm32f767-st-nucleo) | ST 官方 STM32F767-nucleo 开发板 |
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| [stm32f769-st-disco](stm32f769-st-disco) | ST 官方 STM32f769-discovery 开发板 |
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| **G0 系列** | |
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| [stm32g070-st-nucleo](stm32g070-st-nucleo) | ST 官方 STM32G070-nucleo 开发板 |
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| [stm32g071-st-nucleo](stm32g071-st-nucleo) | ST 官方 STM32G071-nucleo 开发板 |
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| **G4 系列** | |
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| [stm32g431-st-nucleo](stm32g431-st-nucleo) | ST 官方 STM32G431-nucleo 开发板 |
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| **H7 系列** | |
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| [stm32h743-armfly-v7](stm32h743-armfly-v7) | 安富莱 STM32H743 v7 开发板 |
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| [stm32h743-atk-apollo](stm32h743-atk-apollo) | 正点原子 h743 阿波罗开发板 |
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| [stm32h743-openmv-h7plus](stm32h743-openmv-h7plus) | OPENMV 官方 H7-PLUS 开发板 |
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| [stm32h743-st-nucleo](stm32h743-st-nucleo) | ST 官方 STM32H743-nucleo 开发板 |
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| [stm32h747-st-discovery](stm32h747-st-discovery) | ST 官方 STM32H747I-discovery 开发板 |
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| [stm32h750-armfly-h7-tool](stm32h750-armfly-h7-tool) | 安富莱 STM32H750 Tool 开发板 |
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| [stm32h750-artpi](stm32h750-artpi) | RT-Thread 官方 STM32H750-artpi 开发板 |
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| [stm32h750-fk750m1-vbt6](stm32h750-fk750m1-vbt6) | 反客科技 FK750M1-VBT6 开发板 |
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| [stm32h750-weact-ministm32h7xx](stm32h750-weact-ministm32h7xx) | 微行电子 STM32H7xx 核心板 |
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| **L0 系列** | |
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| [stm32l010-st-nucleo](stm32l010-st-nucleo) | ST 官方 STM32L010-nucleo 开发板 |
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| [stm32l053-st-nucleo](stm32l053-st-nucleo) | ST 官方 STM32L053-nucleo 开发板 |
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| **L4 系列** | |
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| [stm32l4r5-st-nucleo](stm32l4r5-st-nucleo) | ST 官方 STM32L4R5-Nucleo 开发板 |
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| [stm32l4r9-st-eval](stm32l4r9-st-eval) | ST 官方 STM32L4R9I-EVAL 开发板 |
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| [stm32l412-st-nucleo](stm32l412-st-nucleo) | ST 官方 STM32L412-Nucleo 开发板 |
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| [stm32l431-BearPi](stm32l431-BearPi) | STM32L431 小熊派 开发板 |
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| [stm32l432-st-nucleo](stm32l432-st-nucleo) | ST 官方 STM32L432-Nucleo 开发板 |
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| [stm32l433-st-nucleo](stm32l433-st-nucleo) | ST 官方 STM32L433-Nucleo 开发板 |
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| [stm32l452-st-nucleo](stm32l452-st-nucleo) | ST 官方 STM32L452-Nucleo 开发板 |
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| [stm32l475-atk-pandora](stm32l475-atk-pandora) | 正点原子 L475 潘多拉 IoT 开发板 |
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| [stm32l475-st-discovery](stm32l475-st-discovery) | ST 官方 stm32l475-discovery 开发板 |
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| [stm32l476-st-nucleo](stm32l476-st-nucleo) | ST 官方 STM32L476-Nucleo 开发板 |
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| [stm32l433-ali-startkit](stm32l433-ali-startkit) | 诺行 STM32L433 Ali Start Kit 开发板 |
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| [stm32l496-ali-developer](stm32l496-ali-developer) | 诺行 STM32L496 Ali Developer Kit 开发板 |
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| [stm32l496-st-nucleo](stm32l496-st-nucleo) | ST 官方 STM32L496-Nucleo 开发板 |
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| [stm32l496-st-discovery](stm32l496-st-discovery) | ST 官方 STM32L496G discovery 开发板 |
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| **L5 系列** | |
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| [stm32l552-st-nucleo](stm32l552-st-nucleo) | ST 官方 STM32L552-Nucleo 开发板 |
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| **U5 系列** | |
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| [stm32u575-st-nucleo](stm32u575-st-nucleo) | ST 官方 STM32U575ZI-Nucleo 开发板 |
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| **MP1 系列** | |
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| [stm32mp157a-st-discovery](stm32mp157a-st-discovery) | ST 官方 STM32MP157A-DK1 开发板 |
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| [stm32mp157a-st-ev1](stm32mp157a-st-ev1) | ST 官方 STM32MP157A-EV1 开发板 |
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| **WB 系列** | |
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| [stm32wb55-st-nucleo](stm32wb55-st-nucleo) | ST 官方 STM32WB55-Nucleo 开发板 |
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| [stm32wl55-st-nucleo](stm32wl55-st-nucleo) | ST 官方 STM32WL55-Nucleo 开发板 |
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| **BSP 文件夹名称** | **开发板名称** |
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|:-------------------------------------------------------------- |:---------------------------------- |
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| **F0 系列** | |
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| [stm32f072-st-nucleo](stm32f072-st-nucleo) | ST 官方 STM32F072-nucleo 开发板 |
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| [stm32f091-st-nucleo](stm32f091-st-nucleo) | ST 官方 STM32F091-nucleo 开发板 |
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| **F1 系列** | |
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| [stm32f103-100ask-mini](stm32f103-100ask-mini) | 百问网F103 Mini开发板 |
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| [stm32f103-100ask-pro](stm32f103-100ask-pro) | 百问网F103 Pro开发板 |
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| [stm32f103-atk-nano](stm32f103-atk-nano) | 正点原子 F103 NANO 开发板 |
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| [stm32f103-atk-warshipv3](stm32f103-atk-warshipv3) | 正点原子 F103 战舰V3 开发板 |
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| [stm32f103-blue-pill](stm32f103-blue-pill) | STM32F103C8T6蓝色最小系统板 |
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| [stm32f103-dofly-lyc8](stm32f103-dofly-lyc8) | 德飞莱 STM32F103 开发板 |
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| [stm32f103-dofly-M3S](stm32f103-dofly-M3S) | 德飞莱 STM32F103 开发板 |
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| [stm32f103-fire-arbitrary](stm32f103-fire-arbitrary/) | 野火 F103 霸道开发板 |
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| [stm32f103-gizwits-gokitv21](stm32f103-gizwits-gokitv21) | GoKit V2.1开发板 |
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| [stm32f103-hw100k-ibox](stm32f103-hw100k-ibox) | 硬件十万个为什么 STM32F103 iBox 开发板 |
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| [stm32f103-onenet-nbiot](stm32f103-onenet-nbiot) | STM32F103 OneNET NB-IoT 开发板 |
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| [stm32f103-yf-ufun](stm32f103-yf-ufun) | STM32F103 yf-ufun 开发板 |
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| [stm32f107-uc-eval](stm32f107-uc-eval) | uC/Eval STM32F107 评估板（中国版） |
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| **F2 系列** | |
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| [stm32f207-st-nucleo](stm32f207-st-nucleo) | ST 官方 STM32F207-nucleo 开发板 |
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| **F3 系列** | |
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| [stm32f302-st-nucleo](stm32f302-st-nucleo) | ST 官方 STM32F302-nucleo 开发板 |
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| [stm32f334-st-nucleo](stm32f334-st-nucleo) | ST 官方 STM32F334-nucleo 开发板 |
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| **F4 系列** | |
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| [stm32f407-rt-spark](stm32f407-rt-spark) | 睿赛德官方 F407 星火一号开发板 |
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| [stm32f401-st-nucleo](stm32f401-st-nucleo) | ST 官方 STM32F401 Nucleo-64 开发板 |
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| [stm32f405-smdz-breadfruit](stm32f405-smdz-breadfruit) | 三木电子 SM1432F405 开发板 |
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| [stm32f407-atk-explorer](stm32f407-atk-explorer) | 正点原子 F407 探索者开发板 |
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| [stm32f407-robomaster-c](stm32f407-robomaster-c) | 大疆公司 RoboMaster C型开发板 |
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| [stm32f407-st-discovery](stm32f407-st-discovery) | ST 官方 STM32F407-discovery 开发板 |
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| [stm32f410-st-nucleo](stm32f410-st-nucleo) | ST 官方 STM32F410-Nucleo-64 开发板 |
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| [stm32f411-atk-nano](stm32f411-atk-nano/) | 正点原子 F411 NANO 开发板 |
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| [stm32f411-st-nucleo](stm32f411-st-nucleo/) | ST 官方 STM32F411-Nucleo-64 开发板 |
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| [stm32f411-weact-MiniF4](stm32f411-weact-MiniF4/) | F401/F411最小系统开发板（Black Pill） |
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| [stm32f412-st-nucleo](stm32f412-st-nucleo/) | ST 官方 STM32F412-Nucleo-144 开发板 |
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| [stm32f413-st-nucleo](stm32f413-st-nucleo/) | ST 官方 STM32F413-Nucleo-144 开发板 |
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| [stm32f427-robomaster-a](stm32f427-robomaster-a/) | 大疆公司 RoboMaster A型开发板 |
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| [stm32f429-armfly-v6](stm32f429-armfly-v6) | 安富莱 F429-v6 开发板 |
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| [stm32f429-atk-apollo](stm32f429-atk-apollo) | 正点原子 F429 阿波罗开发板 |
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| [stm32f429-fire-challenger](stm32f429-fire-challenger/) | 野火 F429 挑战者开发板 |
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| [stm32f429-st-disco](stm32f429-st-disco) | ST 官方 STM32F429-discovery 开发板 |
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| [stm32f446-st-nucleo](stm32f446-st-nucleo) | ST 官方 STM32F446-nucleo 开发板 |
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| [stm32f469-st-disco](stm32f469-st-disco) | ST 官方 STM32F469-discovery 开发板 |
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| **F7 系列** | |
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| [stm32f746-st-disco](stm32f746-st-disco) | ST 官方 STM32F746-discovery 开发板 |
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| [stm32f767-atk-apollo](stm32f767-atk-apollo) | 正点原子 F767 阿波罗开发板 |
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| [stm32f767-fire-challenger-v1](stm32f767-fire-challenger-v1/) | 野火 F767-V1 挑战者开发板 |
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| [stm32f767-st-nucleo](stm32f767-st-nucleo) | ST 官方 STM32F767-nucleo 开发板 |
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| [stm32f769-st-disco](stm32f769-st-disco) | ST 官方 STM32f769-discovery 开发板 |
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| **G0 系列** | |
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| [stm32g070-st-nucleo](stm32g070-st-nucleo) | ST 官方 STM32G070-nucleo 开发板 |
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| [stm32g071-st-nucleo](stm32g071-st-nucleo) | ST 官方 STM32G071-nucleo 开发板 |
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| **G4 系列** | |
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| [stm32g431-st-nucleo](stm32g431-st-nucleo) | ST 官方 STM32G431-nucleo 开发板 |
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| **H7 系列** | |
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| [stm32h743-armfly-v7](stm32h743-armfly-v7) | 安富莱 STM32H743 v7 开发板 |
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| [stm32h743-atk-apollo](stm32h743-atk-apollo) | 正点原子 h743 阿波罗开发板 |
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| [stm32h743-openmv-h7plus](stm32h743-openmv-h7plus) | OPENMV 官方 H7-PLUS 开发板 |
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| [stm32h743-st-nucleo](stm32h743-st-nucleo) | ST 官方 STM32H743-nucleo 开发板 |
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| [stm32h747-st-discovery](stm32h747-st-discovery) | ST 官方 STM32H747I-discovery 开发板 |
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| [stm32h750-armfly-h7-tool](stm32h750-armfly-h7-tool) | 安富莱 STM32H750 Tool 开发板 |
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| [stm32h750-artpi](stm32h750-artpi) | RT-Thread 官方 STM32H750-artpi 开发板 |
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| [stm32h750-fk750m1-vbt6](stm32h750-fk750m1-vbt6) | 反客科技 FK750M1-VBT6 开发板 |
|
||||
| [stm32h750-weact-ministm32h7xx](stm32h750-weact-ministm32h7xx) | 微行电子 STM32H7xx 核心板 |
|
||||
| **L0 系列** | |
|
||||
| [stm32l010-st-nucleo](stm32l010-st-nucleo) | ST 官方 STM32L010-nucleo 开发板 |
|
||||
| [stm32l053-st-nucleo](stm32l053-st-nucleo) | ST 官方 STM32L053-nucleo 开发板 |
|
||||
| **L4 系列** | |
|
||||
| [stm32l4r5-st-nucleo](stm32l4r5-st-nucleo) | ST 官方 STM32L4R5-Nucleo 开发板 |
|
||||
| [stm32l4r9-st-eval](stm32l4r9-st-eval) | ST 官方 STM32L4R9I-EVAL 开发板 |
|
||||
| [stm32l412-st-nucleo](stm32l412-st-nucleo) | ST 官方 STM32L412-Nucleo 开发板 |
|
||||
| [stm32l431-BearPi](stm32l431-BearPi) | STM32L431 小熊派 开发板 |
|
||||
| [stm32l432-st-nucleo](stm32l432-st-nucleo) | ST 官方 STM32L432-Nucleo 开发板 |
|
||||
| [stm32l433-st-nucleo](stm32l433-st-nucleo) | ST 官方 STM32L433-Nucleo 开发板 |
|
||||
| [stm32l452-st-nucleo](stm32l452-st-nucleo) | ST 官方 STM32L452-Nucleo 开发板 |
|
||||
| [stm32l475-atk-pandora](stm32l475-atk-pandora) | 正点原子 L475 潘多拉 IoT 开发板 |
|
||||
| [stm32l475-st-discovery](stm32l475-st-discovery) | ST 官方 stm32l475-discovery 开发板 |
|
||||
| [stm32l476-st-nucleo](stm32l476-st-nucleo) | ST 官方 STM32L476-Nucleo 开发板 |
|
||||
| [stm32l433-ali-startkit](stm32l433-ali-startkit) | 诺行 STM32L433 Ali Start Kit 开发板 |
|
||||
| [stm32l496-ali-developer](stm32l496-ali-developer) | 诺行 STM32L496 Ali Developer Kit 开发板 |
|
||||
| [stm32l496-st-nucleo](stm32l496-st-nucleo) | ST 官方 STM32L496-Nucleo 开发板 |
|
||||
| [stm32l496-st-discovery](stm32l496-st-discovery) | ST 官方 STM32L496G discovery 开发板 |
|
||||
| **L5 系列** | |
|
||||
| [stm32l552-st-nucleo](stm32l552-st-nucleo) | ST 官方 STM32L552-Nucleo 开发板 |
|
||||
| **U5 系列** | |
|
||||
| [stm32u575-st-nucleo](stm32u575-st-nucleo) | ST 官方 STM32U575ZI-Nucleo 开发板 |
|
||||
| **H5 系列** | |
|
||||
| [stm32h563-st-nucleo](stm32h563-st-nucleo) | ST 官方 STM32H563ZI-Nucleo 开发板 |
|
||||
| **MP1 系列** | |
|
||||
| [stm32mp157a-st-discovery](stm32mp157a-st-discovery) | ST 官方 STM32MP157A-DK1 开发板 |
|
||||
| [stm32mp157a-st-ev1](stm32mp157a-st-ev1) | ST 官方 STM32MP157A-EV1 开发板 |
|
||||
| **WB 系列** | |
|
||||
| [stm32wb55-st-nucleo](stm32wb55-st-nucleo) | ST 官方 STM32WB55-Nucleo 开发板 |
|
||||
| [stm32wl55-st-nucleo](stm32wl55-st-nucleo) | ST 官方 STM32WL55-Nucleo 开发板 |
|
||||
|
||||
可以通过阅读相应 BSP 下的 README 来快速上手，如果想要使用 BSP 更多功能可参考 docs 文件夹下提供的说明文档，如下表所示：
|
||||
|
||||
| **BSP 使用教程** | **简介** |
|
||||
|:-------------------- |:------------------------------------------------- |
|
||||
| [外设驱动使用教程](docs/STM32系列BSP外设驱动使用教程.md) | 讲解 BSP 上更多外设驱动的使用方法 |
|
||||
| [外设驱动介绍与应用](docs/STM32系列驱动介绍.md) | 讲解 STM32 系列 BSP 驱动的支持情况，以及如何利用驱动框架开发应用程序 |
|
||||
| **BSP 制作与提交** | **简介** |
|
||||
| [BSP 制作教程](docs/STM32系列BSP制作教程.md) | 讲解 STM32 系列 BSP 的制作方法，以及在制作 BSP 和提交 BSP 时应当遵守的规范，视频教程请观看 ：[《RT-Thread STM32 系列 BSP 制作视频教程》](https://url.cn/5qqxJMU?sf=uri) |
|
||||
| [外设驱动添加指南](docs/STM32系列外设驱动添加指南.md) | 讲解 BSP 添加更多设备驱动的方法 |
|
||||
| **BSP 使用教程** | **简介** |
|
||||
|:-------------------------------------- |:-------------------------------------------------------------------------------------------------------------------------- |
|
||||
| [外设驱动使用教程](docs/STM32系列BSP外设驱动使用教程.md) | 讲解 BSP 上更多外设驱动的使用方法 |
|
||||
| [外设驱动介绍与应用](docs/STM32系列驱动介绍.md) | 讲解 STM32 系列 BSP 驱动的支持情况，以及如何利用驱动框架开发应用程序 |
|
||||
| **BSP 制作与提交** | **简介** |
|
||||
| [BSP 制作教程](docs/STM32系列BSP制作教程.md) | 讲解 STM32 系列 BSP 的制作方法，以及在制作 BSP 和提交 BSP 时应当遵守的规范，视频教程请观看 ：[《RT-Thread STM32 系列 BSP 制作视频教程》](https://url.cn/5qqxJMU?sf=uri) |
|
||||
| [外设驱动添加指南](docs/STM32系列外设驱动添加指南.md) | 讲解 BSP 添加更多设备驱动的方法 |
|
||||
|
|
|
|||
|
|
@ -18,5 +18,6 @@ dir_path:
|
|||
- STM32L5xx_HAL
|
||||
- STM32MPxx_HAL
|
||||
- STM32U5xx_HAL
|
||||
- STM32H5xx_HAL
|
||||
- STM32WBxx_HAL
|
||||
- STM32WLxx_HAL
|
||||
|
|
|
|||
|
|
@ -0,0 +1,151 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-11-06 SummerGift first version
|
||||
*/
|
||||
|
||||
#ifndef __UART_CONFIG_H__
|
||||
#define __UART_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_LPUART1)
|
||||
#ifndef LPUART1_CONFIG
|
||||
#define LPUART1_CONFIG \
|
||||
{ \
|
||||
.name = "lpuart1", \
|
||||
.Instance = LPUART1, \
|
||||
.irq_type = LPUART1_IRQn, \
|
||||
}
|
||||
#endif /* LPUART1_CONFIG */
|
||||
#if defined(BSP_LPUART1_RX_USING_DMA)
|
||||
#ifndef LPUART1_DMA_CONFIG
|
||||
#define LPUART1_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = LPUART1_RX_DMA_INSTANCE, \
|
||||
.request = LPUART1_RX_DMA_REQUEST, \
|
||||
.dma_rcc = LPUART1_RX_DMA_RCC, \
|
||||
.dma_irq = LPUART1_RX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* LPUART1_DMA_CONFIG */
|
||||
#endif /* BSP_LPUART1_RX_USING_DMA */
|
||||
#endif /* BSP_USING_LPUART1 */
|
||||
|
||||
#if defined(BSP_USING_UART1)
|
||||
#ifndef UART1_CONFIG
|
||||
#define UART1_CONFIG \
|
||||
{ \
|
||||
.name = "uart1", \
|
||||
.Instance = USART1, \
|
||||
.irq_type = USART1_IRQn, \
|
||||
}
|
||||
#endif /* UART1_CONFIG */
|
||||
#endif /* BSP_USING_UART1 */
|
||||
|
||||
#if defined(BSP_UART1_RX_USING_DMA)
|
||||
#ifndef UART1_DMA_RX_CONFIG
|
||||
#define UART1_DMA_RX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART1_RX_DMA_INSTANCE, \
|
||||
.request = UART1_RX_DMA_REQUEST, \
|
||||
.dma_rcc = UART1_RX_DMA_RCC, \
|
||||
.dma_irq = UART1_RX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* UART1_DMA_RX_CONFIG */
|
||||
#endif /* BSP_UART1_RX_USING_DMA */
|
||||
|
||||
#if defined(BSP_UART1_TX_USING_DMA)
|
||||
#ifndef UART1_DMA_TX_CONFIG
|
||||
#define UART1_DMA_TX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART1_TX_DMA_INSTANCE, \
|
||||
.request = UART1_TX_DMA_REQUEST, \
|
||||
.dma_rcc = UART1_TX_DMA_RCC, \
|
||||
.dma_irq = UART1_TX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* UART1_DMA_TX_CONFIG */
|
||||
#endif /* BSP_UART1_TX_USING_DMA */
|
||||
|
||||
#if defined(BSP_USING_UART2)
|
||||
#ifndef UART2_CONFIG
|
||||
#define UART2_CONFIG \
|
||||
{ \
|
||||
.name = "uart2", \
|
||||
.Instance = USART2, \
|
||||
.irq_type = USART2_IRQn, \
|
||||
}
|
||||
#endif /* UART2_CONFIG */
|
||||
#endif /* BSP_USING_UART2 */
|
||||
|
||||
#if defined(BSP_UART2_RX_USING_DMA)
|
||||
#ifndef UART2_DMA_RX_CONFIG
|
||||
#define UART2_DMA_RX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART2_RX_DMA_INSTANCE, \
|
||||
.request = UART2_RX_DMA_REQUEST, \
|
||||
.dma_rcc = UART2_RX_DMA_RCC, \
|
||||
.dma_irq = UART2_RX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* UART2_DMA_RX_CONFIG */
|
||||
#endif /* BSP_UART2_RX_USING_DMA */
|
||||
|
||||
#if defined(BSP_UART2_TX_USING_DMA)
|
||||
#ifndef UART2_DMA_TX_CONFIG
|
||||
#define UART2_DMA_TX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART2_TX_DMA_INSTANCE, \
|
||||
.request = UART2_TX_DMA_REQUEST, \
|
||||
.dma_rcc = UART2_TX_DMA_RCC, \
|
||||
.dma_irq = UART2_TX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* UART2_DMA_TX_CONFIG */
|
||||
#endif /* BSP_UART2_TX_USING_DMA */
|
||||
|
||||
#if defined(BSP_USING_UART3)
|
||||
#ifndef UART3_CONFIG
|
||||
#define UART3_CONFIG \
|
||||
{ \
|
||||
.name = "uart3", \
|
||||
.Instance = USART3, \
|
||||
.irq_type = USART3_IRQn, \
|
||||
}
|
||||
#endif /* UART3_CONFIG */
|
||||
#endif /* BSP_USING_UART3 */
|
||||
|
||||
#if defined(BSP_UART3_RX_USING_DMA)
|
||||
#ifndef UART3_DMA_RX_CONFIG
|
||||
#define UART3_DMA_RX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART3_RX_DMA_INSTANCE, \
|
||||
.request = UART3_RX_DMA_REQUEST, \
|
||||
.dma_rcc = UART3_RX_DMA_RCC, \
|
||||
.dma_irq = UART3_RX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* UART3_DMA_RX_CONFIG */
|
||||
#endif /* BSP_UART3_RX_USING_DMA */
|
||||
|
||||
#if defined(BSP_UART3_TX_USING_DMA)
|
||||
#ifndef UART3_DMA_TX_CONFIG
|
||||
#define UART3_DMA_TX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART3_TX_DMA_INSTANCE, \
|
||||
.request = UART3_TX_DMA_REQUEST, \
|
||||
.dma_rcc = UART3_TX_DMA_RCC, \
|
||||
.dma_irq = UART3_TX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* UART3_DMA_TX_CONFIG */
|
||||
#endif /* BSP_UART3_TX_USING_DMA */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -135,6 +135,8 @@ extern "C" {
|
|||
#include "u5/sdio_config.h"
|
||||
#include "u5/pwm_config.h"
|
||||
#include "u5/usbd_config.h"
|
||||
#elif defined(SOC_SERIES_STM32H5)
|
||||
#include "h5/uart_config.h"
|
||||
#elif defined(SOC_SERIES_STM32MP1)
|
||||
#include "mp1/dma_config.h"
|
||||
#include "mp1/uart_config.h"
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@ extern "C" {
|
|||
#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32L5)\
|
||||
|| defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0) \
|
||||
|| defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)|| defined(SOC_SERIES_STM32F3) \
|
||||
|| defined(SOC_SERIES_STM32U5)
|
||||
|| defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5)
|
||||
#define DMA_INSTANCE_TYPE DMA_Channel_TypeDef
|
||||
#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)\
|
||||
|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
|
||||
|
|
|
|||
|
|
@ -17,14 +17,14 @@
|
|||
|
||||
#ifdef BSP_USING_GPIO
|
||||
|
||||
#define PIN_NUM(port, no) (((((port) & 0xFu) << 4) | ((no) & 0xFu)))
|
||||
#define PIN_NUM(port, no) (((((port)&0xFu) << 4) | ((no)&0xFu)))
|
||||
#define PIN_PORT(pin) ((uint8_t)(((pin) >> 4) & 0xFu))
|
||||
#define PIN_NO(pin) ((uint8_t)((pin) & 0xFu))
|
||||
#define PIN_NO(pin) ((uint8_t)((pin)&0xFu))
|
||||
|
||||
#if defined(SOC_SERIES_STM32MP1)
|
||||
#if defined(GPIOZ)
|
||||
#define gpioz_port_base (175) /* PIN_STPORT_MAX * 16 - 16 */
|
||||
#define PIN_STPORT(pin) ((pin > gpioz_port_base) ? ((GPIO_TypeDef *)(GPIOZ_BASE )) : ((GPIO_TypeDef *)(GPIOA_BASE + (0x1000u * PIN_PORT(pin)))))
|
||||
#define PIN_STPORT(pin) ((pin > gpioz_port_base) ? ((GPIO_TypeDef *)(GPIOZ_BASE)) : ((GPIO_TypeDef *)(GPIOA_BASE + (0x1000u * PIN_PORT(pin)))))
|
||||
#else
|
||||
#define PIN_STPORT(pin) ((GPIO_TypeDef *)(GPIOA_BASE + (0x1000u * PIN_PORT(pin))))
|
||||
#endif /* GPIOZ */
|
||||
|
|
@ -66,96 +66,96 @@
|
|||
#define PIN_STPORT_MAX __STM32_PORT_MAX
|
||||
|
||||
static const struct pin_irq_map pin_irq_map[] =
|
||||
{
|
||||
{
|
||||
#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0)
|
||||
{GPIO_PIN_0, EXTI0_1_IRQn},
|
||||
{GPIO_PIN_1, EXTI0_1_IRQn},
|
||||
{GPIO_PIN_2, EXTI2_3_IRQn},
|
||||
{GPIO_PIN_3, EXTI2_3_IRQn},
|
||||
{GPIO_PIN_4, EXTI4_15_IRQn},
|
||||
{GPIO_PIN_5, EXTI4_15_IRQn},
|
||||
{GPIO_PIN_6, EXTI4_15_IRQn},
|
||||
{GPIO_PIN_7, EXTI4_15_IRQn},
|
||||
{GPIO_PIN_8, EXTI4_15_IRQn},
|
||||
{GPIO_PIN_9, EXTI4_15_IRQn},
|
||||
{GPIO_PIN_10, EXTI4_15_IRQn},
|
||||
{GPIO_PIN_11, EXTI4_15_IRQn},
|
||||
{GPIO_PIN_12, EXTI4_15_IRQn},
|
||||
{GPIO_PIN_13, EXTI4_15_IRQn},
|
||||
{GPIO_PIN_14, EXTI4_15_IRQn},
|
||||
{GPIO_PIN_15, EXTI4_15_IRQn},
|
||||
#elif defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32L5) || defined(SOC_SERIES_STM32U5)
|
||||
{GPIO_PIN_0, EXTI0_IRQn},
|
||||
{GPIO_PIN_1, EXTI1_IRQn},
|
||||
{GPIO_PIN_2, EXTI2_IRQn},
|
||||
{GPIO_PIN_3, EXTI3_IRQn},
|
||||
{GPIO_PIN_4, EXTI4_IRQn},
|
||||
{GPIO_PIN_5, EXTI5_IRQn},
|
||||
{GPIO_PIN_6, EXTI6_IRQn},
|
||||
{GPIO_PIN_7, EXTI7_IRQn},
|
||||
{GPIO_PIN_8, EXTI8_IRQn},
|
||||
{GPIO_PIN_9, EXTI9_IRQn},
|
||||
{GPIO_PIN_10, EXTI10_IRQn},
|
||||
{GPIO_PIN_11, EXTI11_IRQn},
|
||||
{GPIO_PIN_12, EXTI12_IRQn},
|
||||
{GPIO_PIN_13, EXTI13_IRQn},
|
||||
{GPIO_PIN_14, EXTI14_IRQn},
|
||||
{GPIO_PIN_15, EXTI15_IRQn},
|
||||
{GPIO_PIN_0, EXTI0_1_IRQn},
|
||||
{GPIO_PIN_1, EXTI0_1_IRQn},
|
||||
{GPIO_PIN_2, EXTI2_3_IRQn},
|
||||
{GPIO_PIN_3, EXTI2_3_IRQn},
|
||||
{GPIO_PIN_4, EXTI4_15_IRQn},
|
||||
{GPIO_PIN_5, EXTI4_15_IRQn},
|
||||
{GPIO_PIN_6, EXTI4_15_IRQn},
|
||||
{GPIO_PIN_7, EXTI4_15_IRQn},
|
||||
{GPIO_PIN_8, EXTI4_15_IRQn},
|
||||
{GPIO_PIN_9, EXTI4_15_IRQn},
|
||||
{GPIO_PIN_10, EXTI4_15_IRQn},
|
||||
{GPIO_PIN_11, EXTI4_15_IRQn},
|
||||
{GPIO_PIN_12, EXTI4_15_IRQn},
|
||||
{GPIO_PIN_13, EXTI4_15_IRQn},
|
||||
{GPIO_PIN_14, EXTI4_15_IRQn},
|
||||
{GPIO_PIN_15, EXTI4_15_IRQn},
|
||||
#elif defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32L5) || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5)
|
||||
{GPIO_PIN_0, EXTI0_IRQn},
|
||||
{GPIO_PIN_1, EXTI1_IRQn},
|
||||
{GPIO_PIN_2, EXTI2_IRQn},
|
||||
{GPIO_PIN_3, EXTI3_IRQn},
|
||||
{GPIO_PIN_4, EXTI4_IRQn},
|
||||
{GPIO_PIN_5, EXTI5_IRQn},
|
||||
{GPIO_PIN_6, EXTI6_IRQn},
|
||||
{GPIO_PIN_7, EXTI7_IRQn},
|
||||
{GPIO_PIN_8, EXTI8_IRQn},
|
||||
{GPIO_PIN_9, EXTI9_IRQn},
|
||||
{GPIO_PIN_10, EXTI10_IRQn},
|
||||
{GPIO_PIN_11, EXTI11_IRQn},
|
||||
{GPIO_PIN_12, EXTI12_IRQn},
|
||||
{GPIO_PIN_13, EXTI13_IRQn},
|
||||
{GPIO_PIN_14, EXTI14_IRQn},
|
||||
{GPIO_PIN_15, EXTI15_IRQn},
|
||||
#elif defined(SOC_SERIES_STM32F3)
|
||||
{GPIO_PIN_0, EXTI0_IRQn},
|
||||
{GPIO_PIN_1, EXTI1_IRQn},
|
||||
{GPIO_PIN_2, EXTI2_TSC_IRQn},
|
||||
{GPIO_PIN_3, EXTI3_IRQn},
|
||||
{GPIO_PIN_4, EXTI4_IRQn},
|
||||
{GPIO_PIN_5, EXTI9_5_IRQn},
|
||||
{GPIO_PIN_6, EXTI9_5_IRQn},
|
||||
{GPIO_PIN_7, EXTI9_5_IRQn},
|
||||
{GPIO_PIN_8, EXTI9_5_IRQn},
|
||||
{GPIO_PIN_9, EXTI9_5_IRQn},
|
||||
{GPIO_PIN_10, EXTI15_10_IRQn},
|
||||
{GPIO_PIN_11, EXTI15_10_IRQn},
|
||||
{GPIO_PIN_12, EXTI15_10_IRQn},
|
||||
{GPIO_PIN_13, EXTI15_10_IRQn},
|
||||
{GPIO_PIN_14, EXTI15_10_IRQn},
|
||||
{GPIO_PIN_15, EXTI15_10_IRQn},
|
||||
{GPIO_PIN_0, EXTI0_IRQn},
|
||||
{GPIO_PIN_1, EXTI1_IRQn},
|
||||
{GPIO_PIN_2, EXTI2_TSC_IRQn},
|
||||
{GPIO_PIN_3, EXTI3_IRQn},
|
||||
{GPIO_PIN_4, EXTI4_IRQn},
|
||||
{GPIO_PIN_5, EXTI9_5_IRQn},
|
||||
{GPIO_PIN_6, EXTI9_5_IRQn},
|
||||
{GPIO_PIN_7, EXTI9_5_IRQn},
|
||||
{GPIO_PIN_8, EXTI9_5_IRQn},
|
||||
{GPIO_PIN_9, EXTI9_5_IRQn},
|
||||
{GPIO_PIN_10, EXTI15_10_IRQn},
|
||||
{GPIO_PIN_11, EXTI15_10_IRQn},
|
||||
{GPIO_PIN_12, EXTI15_10_IRQn},
|
||||
{GPIO_PIN_13, EXTI15_10_IRQn},
|
||||
{GPIO_PIN_14, EXTI15_10_IRQn},
|
||||
{GPIO_PIN_15, EXTI15_10_IRQn},
|
||||
#else
|
||||
{GPIO_PIN_0, EXTI0_IRQn},
|
||||
{GPIO_PIN_1, EXTI1_IRQn},
|
||||
{GPIO_PIN_2, EXTI2_IRQn},
|
||||
{GPIO_PIN_3, EXTI3_IRQn},
|
||||
{GPIO_PIN_4, EXTI4_IRQn},
|
||||
{GPIO_PIN_5, EXTI9_5_IRQn},
|
||||
{GPIO_PIN_6, EXTI9_5_IRQn},
|
||||
{GPIO_PIN_7, EXTI9_5_IRQn},
|
||||
{GPIO_PIN_8, EXTI9_5_IRQn},
|
||||
{GPIO_PIN_9, EXTI9_5_IRQn},
|
||||
{GPIO_PIN_10, EXTI15_10_IRQn},
|
||||
{GPIO_PIN_11, EXTI15_10_IRQn},
|
||||
{GPIO_PIN_12, EXTI15_10_IRQn},
|
||||
{GPIO_PIN_13, EXTI15_10_IRQn},
|
||||
{GPIO_PIN_14, EXTI15_10_IRQn},
|
||||
{GPIO_PIN_15, EXTI15_10_IRQn},
|
||||
{GPIO_PIN_0, EXTI0_IRQn},
|
||||
{GPIO_PIN_1, EXTI1_IRQn},
|
||||
{GPIO_PIN_2, EXTI2_IRQn},
|
||||
{GPIO_PIN_3, EXTI3_IRQn},
|
||||
{GPIO_PIN_4, EXTI4_IRQn},
|
||||
{GPIO_PIN_5, EXTI9_5_IRQn},
|
||||
{GPIO_PIN_6, EXTI9_5_IRQn},
|
||||
{GPIO_PIN_7, EXTI9_5_IRQn},
|
||||
{GPIO_PIN_8, EXTI9_5_IRQn},
|
||||
{GPIO_PIN_9, EXTI9_5_IRQn},
|
||||
{GPIO_PIN_10, EXTI15_10_IRQn},
|
||||
{GPIO_PIN_11, EXTI15_10_IRQn},
|
||||
{GPIO_PIN_12, EXTI15_10_IRQn},
|
||||
{GPIO_PIN_13, EXTI15_10_IRQn},
|
||||
{GPIO_PIN_14, EXTI15_10_IRQn},
|
||||
{GPIO_PIN_15, EXTI15_10_IRQn},
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
|
||||
{
|
||||
{-1, 0, RT_NULL, RT_NULL},
|
||||
{-1, 0, RT_NULL, RT_NULL},
|
||||
{-1, 0, RT_NULL, RT_NULL},
|
||||
{-1, 0, RT_NULL, RT_NULL},
|
||||
{-1, 0, RT_NULL, RT_NULL},
|
||||
{-1, 0, RT_NULL, RT_NULL},
|
||||
{-1, 0, RT_NULL, RT_NULL},
|
||||
{-1, 0, RT_NULL, RT_NULL},
|
||||
{-1, 0, RT_NULL, RT_NULL},
|
||||
{-1, 0, RT_NULL, RT_NULL},
|
||||
{-1, 0, RT_NULL, RT_NULL},
|
||||
{-1, 0, RT_NULL, RT_NULL},
|
||||
{-1, 0, RT_NULL, RT_NULL},
|
||||
{-1, 0, RT_NULL, RT_NULL},
|
||||
{-1, 0, RT_NULL, RT_NULL},
|
||||
{-1, 0, RT_NULL, RT_NULL},
|
||||
{
|
||||
{-1, 0, RT_NULL, RT_NULL},
|
||||
{-1, 0, RT_NULL, RT_NULL},
|
||||
{-1, 0, RT_NULL, RT_NULL},
|
||||
{-1, 0, RT_NULL, RT_NULL},
|
||||
{-1, 0, RT_NULL, RT_NULL},
|
||||
{-1, 0, RT_NULL, RT_NULL},
|
||||
{-1, 0, RT_NULL, RT_NULL},
|
||||
{-1, 0, RT_NULL, RT_NULL},
|
||||
{-1, 0, RT_NULL, RT_NULL},
|
||||
{-1, 0, RT_NULL, RT_NULL},
|
||||
{-1, 0, RT_NULL, RT_NULL},
|
||||
{-1, 0, RT_NULL, RT_NULL},
|
||||
{-1, 0, RT_NULL, RT_NULL},
|
||||
{-1, 0, RT_NULL, RT_NULL},
|
||||
{-1, 0, RT_NULL, RT_NULL},
|
||||
{-1, 0, RT_NULL, RT_NULL},
|
||||
};
|
||||
static uint32_t pin_irq_enable_mask = 0;
|
||||
|
||||
|
|
@ -221,7 +221,7 @@ static rt_int8_t stm32_pin_read(rt_device_t dev, rt_base_t pin)
|
|||
{
|
||||
GPIO_TypeDef *gpio_port;
|
||||
uint16_t gpio_pin;
|
||||
GPIO_PinState state;
|
||||
GPIO_PinState state = PIN_LOW;
|
||||
|
||||
if (PIN_PORT(pin) < PIN_STPORT_MAX)
|
||||
{
|
||||
|
|
@ -306,7 +306,7 @@ rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
|
|||
};
|
||||
|
||||
static rt_err_t stm32_pin_attach_irq(struct rt_device *device, rt_base_t pin,
|
||||
rt_uint8_t mode, void (*hdr)(void *args), void *args)
|
||||
rt_uint8_t mode, void (*hdr)(void *args), void *args)
|
||||
{
|
||||
rt_base_t level;
|
||||
rt_int32_t irqindex = -1;
|
||||
|
|
@ -377,7 +377,7 @@ static rt_err_t stm32_pin_dettach_irq(struct rt_device *device, rt_base_t pin)
|
|||
}
|
||||
|
||||
static rt_err_t stm32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
|
||||
rt_uint8_t enabled)
|
||||
rt_uint8_t enabled)
|
||||
{
|
||||
const struct pin_irq_map *irqmap;
|
||||
rt_base_t level;
|
||||
|
|
@ -503,14 +503,14 @@ static rt_err_t stm32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
|
|||
return RT_EOK;
|
||||
}
|
||||
static const struct rt_pin_ops _stm32_pin_ops =
|
||||
{
|
||||
stm32_pin_mode,
|
||||
stm32_pin_write,
|
||||
stm32_pin_read,
|
||||
stm32_pin_attach_irq,
|
||||
stm32_pin_dettach_irq,
|
||||
stm32_pin_irq_enable,
|
||||
stm32_pin_get,
|
||||
{
|
||||
stm32_pin_mode,
|
||||
stm32_pin_write,
|
||||
stm32_pin_read,
|
||||
stm32_pin_attach_irq,
|
||||
stm32_pin_dettach_irq,
|
||||
stm32_pin_irq_enable,
|
||||
stm32_pin_get,
|
||||
};
|
||||
|
||||
rt_inline void pin_irq_hdr(int irqno)
|
||||
|
|
@ -773,9 +773,9 @@ int rt_hw_pin_init(void)
|
|||
#endif
|
||||
|
||||
#if defined(__HAL_RCC_GPIOG_CLK_ENABLE)
|
||||
#ifdef SOC_SERIES_STM32L4
|
||||
HAL_PWREx_EnableVddIO2();
|
||||
#endif
|
||||
#ifdef SOC_SERIES_STM32L4
|
||||
HAL_PWREx_EnableVddIO2();
|
||||
#endif
|
||||
__HAL_RCC_GPIOG_CLK_ENABLE();
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -317,7 +317,7 @@ static int stm32_putc(struct rt_serial_device *serial, char c)
|
|||
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) \
|
||||
|| defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32L5) \
|
||||
|| defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32F3) \
|
||||
|| defined(SOC_SERIES_STM32U5)
|
||||
|| defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5)
|
||||
uart->handle.Instance->TDR = c;
|
||||
#else
|
||||
uart->handle.Instance->DR = c;
|
||||
|
|
@ -339,7 +339,7 @@ static int stm32_getc(struct rt_serial_device *serial)
|
|||
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) \
|
||||
|| defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32L5) \
|
||||
|| defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB)|| defined(SOC_SERIES_STM32F3) \
|
||||
|| defined(SOC_SERIES_STM32U5)
|
||||
|| defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5)
|
||||
ch = uart->handle.Instance->RDR & uart->DR_mask;
|
||||
#else
|
||||
ch = uart->handle.Instance->DR & uart->DR_mask;
|
||||
|
|
@ -477,7 +477,7 @@ static void uart_isr(struct rt_serial_device *serial)
|
|||
#if !defined(SOC_SERIES_STM32L4) && !defined(SOC_SERIES_STM32WL) && !defined(SOC_SERIES_STM32F7) && !defined(SOC_SERIES_STM32F0) \
|
||||
&& !defined(SOC_SERIES_STM32L0) && !defined(SOC_SERIES_STM32G0) && !defined(SOC_SERIES_STM32H7) \
|
||||
&& !defined(SOC_SERIES_STM32G4) && !defined(SOC_SERIES_STM32MP1) && !defined(SOC_SERIES_STM32WB) \
|
||||
&& !defined(SOC_SERIES_STM32L5) && !defined(SOC_SERIES_STM32U5)
|
||||
&& !defined(SOC_SERIES_STM32L5) && !defined(SOC_SERIES_STM32U5) && !defined(SOC_SERIES_STM32H5)
|
||||
#ifdef SOC_SERIES_STM32F3
|
||||
if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_LBDF) != RESET)
|
||||
{
|
||||
|
|
@ -1003,7 +1003,7 @@ static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
|
|||
__HAL_LINKDMA(&(uart->handle), hdmatx, uart->dma_tx.handle);
|
||||
}
|
||||
|
||||
#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32L0)|| defined(SOC_SERIES_STM32F3) || defined(SOC_SERIES_STM32L1) || defined(SOC_SERIES_STM32U5)
|
||||
#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32L0)|| defined(SOC_SERIES_STM32F3) || defined(SOC_SERIES_STM32L1) || defined(SOC_SERIES_STM32U5) || defined(SOC_SERIES_STM32H5)
|
||||
DMA_Handle->Instance = dma_config->Instance;
|
||||
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
|
||||
DMA_Handle->Instance = dma_config->Instance;
|
||||
|
|
|
|||
|
|
@ -31,7 +31,8 @@ int rt_hw_usart_init(void);
|
|||
|
||||
#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32L5) || defined(SOC_SERIES_STM32WL) \
|
||||
|| defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) \
|
||||
|| defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)|| defined(SOC_SERIES_STM32F3) || defined(SOC_SERIES_STM32U5)
|
||||
|| defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)|| defined(SOC_SERIES_STM32F3) || defined(SOC_SERIES_STM32U5) \
|
||||
|| defined(SOC_SERIES_STM32H5)
|
||||
#define UART_INSTANCE_CLEAR_FUNCTION __HAL_UART_CLEAR_FLAG
|
||||
#elif defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) \
|
||||
|| defined(SOC_SERIES_STM32MP1)
|
||||
|
|
|
|||
|
|
@ -71,6 +71,11 @@ config SOC_SERIES_STM32U5
|
|||
select ARCH_ARM_CORTEX_M33
|
||||
select SOC_FAMILY_STM32
|
||||
|
||||
config SOC_SERIES_STM32H5
|
||||
bool
|
||||
select ARCH_ARM_CORTEX_M33
|
||||
select SOC_FAMILY_STM32
|
||||
|
||||
config SOC_SERIES_STM32MP1
|
||||
bool
|
||||
select ARCH_ARM_CORTEX_M4
|
||||
|
|
|
|||
|
|
@ -0,0 +1,649 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file partition_stm32h562xx.h
|
||||
* @author MCD Application Team
|
||||
* @brief CMSIS STM32H562xx Device Header File for Initial Setup for Secure /
|
||||
* Non-Secure Zones for ARMCM33 based on CMSIS CORE partition_ARMCM33.h
|
||||
* Template.
|
||||
*
|
||||
* This file contains:
|
||||
* - Initialize Security Attribution Unit (SAU) CTRL register
|
||||
* - Setup behavior of Sleep and Exception Handling
|
||||
* - Setup behavior of Floating Point Unit
|
||||
* - Setup Interrupt Target
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef PARTITION_STM32H562XX_H
|
||||
#define PARTITION_STM32H562XX_H
|
||||
|
||||
/*
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize Security Attribution Unit (SAU) CTRL register
|
||||
*/
|
||||
#define SAU_INIT_CTRL 1
|
||||
|
||||
/*
|
||||
// <q> Enable SAU
|
||||
// <i> Value for SAU->CTRL register bit ENABLE
|
||||
*/
|
||||
#define SAU_INIT_CTRL_ENABLE 0
|
||||
|
||||
/*
|
||||
// <o> When SAU is disabled
|
||||
// <0=> All Memory is Secure
|
||||
// <1=> All Memory is Non-Secure
|
||||
// <i> Value for SAU->CTRL register bit ALLNS
|
||||
// <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
|
||||
*/
|
||||
#define SAU_INIT_CTRL_ALLNS 1
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <h>Initialize Security Attribution Unit (SAU) Address Regions
|
||||
// <i>SAU configuration specifies regions to be one of:
|
||||
// <i> - Secure and Non-Secure Callable
|
||||
// <i> - Non-Secure
|
||||
// <i>Note: All memory regions not configured by SAU are Secure
|
||||
*/
|
||||
#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 0
|
||||
// <i> Setup SAU Region 0 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION0 0
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START0 0x0C0FE000 /* start address of SAU region 0 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END0 0x0C0FFFFF /* end address of SAU region 0 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC0 1
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 1
|
||||
// <i> Setup SAU Region 1 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION1 0
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START1 0x08100000 /* start address of SAU region 1 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END1 0x081FFFFF /* end address of SAU region 1 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC1 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 2
|
||||
// <i> Setup SAU Region 2 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION2 0
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START2 0x20050000 /* start address of SAU region 2 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END2 0x2009FFFF /* end address of SAU region 2 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC2 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 3
|
||||
// <i> Setup SAU Region 3 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION3 0
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START3 0x40000000 /* start address of SAU region 3 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END3 0x4FFFFFFF /* end address of SAU region 3 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC3 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 4
|
||||
// <i> Setup SAU Region 4 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION4 0
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START4 0x60000000 /* start address of SAU region 4 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END4 0x9FFFFFFF /* end address of SAU region 4 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC4 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 5
|
||||
// <i> Setup SAU Region 5 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION5 0
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START5 0x0BF90000 /* start address of SAU region 5 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END5 0x0BFA8FFF /* end address of SAU region 5 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC5 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 6
|
||||
// <i> Setup SAU Region 6 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION6 0
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC6 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 7
|
||||
// <i> Setup SAU Region 7 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION7 0
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC7 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// </h>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Setup behaviour of Sleep and Exception Handling
|
||||
*/
|
||||
#define SCB_CSR_AIRCR_INIT 0
|
||||
|
||||
/*
|
||||
// <o> Deep Sleep can be enabled by
|
||||
// <0=>Secure and Non-Secure state
|
||||
// <1=>Secure state only
|
||||
// <i> Value for SCB->CSR register bit DEEPSLEEPS
|
||||
*/
|
||||
#define SCB_CSR_DEEPSLEEPS_VAL 0
|
||||
|
||||
/*
|
||||
// <o>System reset request accessible from
|
||||
// <0=> Secure and Non-Secure state
|
||||
// <1=> Secure state only
|
||||
// <i> Value for SCB->AIRCR register bit SYSRESETREQS
|
||||
*/
|
||||
#define SCB_AIRCR_SYSRESETREQS_VAL 0
|
||||
|
||||
/*
|
||||
// <o>Priority of Non-Secure exceptions is
|
||||
// <0=> Not altered
|
||||
// <1=> Lowered to 0x04-0x07
|
||||
// <i> Value for SCB->AIRCR register bit PRIS
|
||||
*/
|
||||
#define SCB_AIRCR_PRIS_VAL 0
|
||||
|
||||
/*
|
||||
// <o>BusFault, HardFault, and NMI target
|
||||
// <0=> Secure state
|
||||
// <1=> Non-Secure state
|
||||
// <i> Value for SCB->AIRCR register bit BFHFNMINS
|
||||
*/
|
||||
#define SCB_AIRCR_BFHFNMINS_VAL 0
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Setup behaviour of Floating Point Unit
|
||||
*/
|
||||
#define TZ_FPU_NS_USAGE 1
|
||||
|
||||
/*
|
||||
// <o>Floating Point Unit usage
|
||||
// <0=> Secure state only
|
||||
// <3=> Secure and Non-Secure state
|
||||
// <i> Value for SCB->NSACR register bits CP10, CP11
|
||||
*/
|
||||
#define SCB_NSACR_CP10_11_VAL 3
|
||||
|
||||
/*
|
||||
// <o>Treat floating-point registers as Secure
|
||||
// <0=> Disabled
|
||||
// <1=> Enabled
|
||||
// <i> Value for FPU->FPCCR register bit TS
|
||||
*/
|
||||
#define FPU_FPCCR_TS_VAL 0
|
||||
|
||||
/*
|
||||
// <o>Clear on return (CLRONRET) accessibility
|
||||
// <0=> Secure and Non-Secure state
|
||||
// <1=> Secure state only
|
||||
// <i> Value for FPU->FPCCR register bit CLRONRETS
|
||||
*/
|
||||
#define FPU_FPCCR_CLRONRETS_VAL 0
|
||||
|
||||
/*
|
||||
// <o>Clear floating-point caller saved registers on exception return
|
||||
// <0=> Disabled
|
||||
// <1=> Enabled
|
||||
// <i> Value for FPU->FPCCR register bit CLRONRET
|
||||
*/
|
||||
#define FPU_FPCCR_CLRONRET_VAL 1
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <h>Setup Interrupt Target
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize ITNS 0 (Interrupts 0..31)
|
||||
*/
|
||||
#define NVIC_INIT_ITNS0 1
|
||||
|
||||
/*
|
||||
// Interrupts 0..31
|
||||
// <o.0> WWDG_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.1> PVD_AVD_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.2> RTC_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.3> RTC_S_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.4> TAMP_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.5> RAMCFG_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.6> FLASH_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.7> FLASH_S_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.8> GTZC_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.9> RCC_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.10> RCC_S_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.11> EXTI0_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.12> EXTI1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.13> EXTI2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.14> EXTI3_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.15> EXTI4_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.16> EXTI5_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.17> EXTI6_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.18> EXTI7_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.19> EXTI8_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.20> EXTI9_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.21> EXTI10_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.22> EXTI11_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.23> EXTI12_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.24> EXTI13_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.25> EXTI14_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.26> EXTI15_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.27> GPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.28> GPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.29> GPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.30> GPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.31> GPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
*/
|
||||
#define NVIC_INIT_ITNS0_VAL 0x00000000
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize ITNS 1 (Interrupts 32..63)
|
||||
*/
|
||||
#define NVIC_INIT_ITNS1 1
|
||||
|
||||
/*
|
||||
// Interrupts 32..63
|
||||
// <o.0> GPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.1> GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.2> GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.3> IWDG_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.4> ADC1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.5> DAC1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.6> FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.7> FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.8> TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.9> TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.10> TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.11> TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.12> TIM2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.13> TIM3_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.14> TIM4_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.15> TIM5_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.16> TIM6_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.17> TIM7_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.18> I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.19> I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.20> I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.21> I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.22> SPI1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.23> SPI2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.24> SPI3_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.25> USART1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.26> USART2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.27> USART3_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.28> UART4_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.29> UART5_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.30> LPUART1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.31> LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
*/
|
||||
#define NVIC_INIT_ITNS1_VAL 0x00000000
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize ITNS 2 (Interrupts 64..95)
|
||||
*/
|
||||
#define NVIC_INIT_ITNS2 1
|
||||
|
||||
/*
|
||||
// Interrupts 64..95
|
||||
// <o.0> TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.1> TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.2> TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.3> TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.4> ADC2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.5> LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.6> TIM15_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.7> TIM16_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.8> TIM17_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.9> USB_DRD_FS_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.10> CRS_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.11> UCPD1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.12> FMC_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.13> OCTOSPI1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.14> SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.15> I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.16> I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.17> SPI4_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.18> SPI5_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.19> SPI6_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.20> USART6_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.21> USART10_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.22> USART11_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.23> SAI1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.24> SAI2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.25> GPDMA2_Channel0_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.26> GPDMA2_Channel1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.27> GPDMA2_Channel2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.28> GPDMA2_Channel3_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.29> GPDMA2_Channel4_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.30> GPDMA2_Channel5_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.31> GPDMA2_Channel6_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
*/
|
||||
#define NVIC_INIT_ITNS2_VAL 0x00000000
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize ITNS 3 (Interrupts 96..121)
|
||||
*/
|
||||
#define NVIC_INIT_ITNS3 1
|
||||
|
||||
/*
|
||||
// Interrupts 96..121
|
||||
// <o.0> GPDMA2_Channel7_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.1> UART7_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.2> UART8_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.3> UART9_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.4> UART12_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.5> FPU_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.6> ICACHE_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.7> DCACHE_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.8> DCMI_PSSI_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.9> CORDIC_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.10> FMAC_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.11> DTS_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.12> RNG_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.13> HASH_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.14> CEC_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.15> TIM12_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.16> TIM13_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.17> TIM14_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.18> I3C1_EV_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.19> I3C1_ER_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.20> I2C4_EV_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.21> I2C4_ER_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.22> LPTIM3_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.23> LPTIM4_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.24> LPTIM5_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.25> LPTIM6_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
*/
|
||||
#define NVIC_INIT_ITNS3_VAL 0x00000000
|
||||
|
||||
/*
|
||||
// </h>
|
||||
*/
|
||||
|
||||
/*
|
||||
max 8 SAU regions.
|
||||
SAU regions are defined in partition.h
|
||||
*/
|
||||
|
||||
#define SAU_INIT_REGION(n) \
|
||||
SAU->RNR = (n & SAU_RNR_REGION_Msk); \
|
||||
SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
|
||||
SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
|
||||
((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
|
||||
|
||||
/**
|
||||
\brief Setup a SAU Region
|
||||
\details Writes the region information contained in SAU_Region to the
|
||||
registers SAU_RNR, SAU_RBAR, and SAU_RLAR
|
||||
*/
|
||||
__STATIC_INLINE void TZ_SAU_Setup (void)
|
||||
{
|
||||
|
||||
#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
|
||||
|
||||
#if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
|
||||
SAU_INIT_REGION(0);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
|
||||
SAU_INIT_REGION(1);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
|
||||
SAU_INIT_REGION(2);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
|
||||
SAU_INIT_REGION(3);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
|
||||
SAU_INIT_REGION(4);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
|
||||
SAU_INIT_REGION(5);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
|
||||
SAU_INIT_REGION(6);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
|
||||
SAU_INIT_REGION(7);
|
||||
#endif
|
||||
|
||||
/* repeat this for all possible SAU regions */
|
||||
|
||||
#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
|
||||
|
||||
|
||||
#if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
|
||||
SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
|
||||
((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;
|
||||
#endif
|
||||
|
||||
#if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
|
||||
SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) |
|
||||
((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);
|
||||
|
||||
SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk |
|
||||
SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) |
|
||||
((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) |
|
||||
((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
|
||||
((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) |
|
||||
((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk);
|
||||
#endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
|
||||
|
||||
#if defined (__FPU_USED) && (__FPU_USED == 1U) && \
|
||||
defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)
|
||||
|
||||
SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |
|
||||
((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
|
||||
|
||||
FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
|
||||
((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) |
|
||||
((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
|
||||
((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
|
||||
#endif
|
||||
|
||||
#if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
|
||||
NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
|
||||
#endif
|
||||
|
||||
#if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
|
||||
NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
|
||||
#endif
|
||||
|
||||
#if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
|
||||
NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
|
||||
#endif
|
||||
|
||||
#if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
|
||||
NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
#endif /* PARTITION_STM32H562XX_H */
|
||||
|
|
@ -0,0 +1,654 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file partition_stm32h563xx.h
|
||||
* @author MCD Application Team
|
||||
* @brief CMSIS STM32H563xx Device Header File for Initial Setup for Secure /
|
||||
* Non-Secure Zones for ARMCM33 based on CMSIS CORE partition_ARMCM33.h
|
||||
* Template.
|
||||
*
|
||||
* This file contains:
|
||||
* - Initialize Security Attribution Unit (SAU) CTRL register
|
||||
* - Setup behavior of Sleep and Exception Handling
|
||||
* - Setup behavior of Floating Point Unit
|
||||
* - Setup Interrupt Target
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef PARTITION_STM32H563XX_H
|
||||
#define PARTITION_STM32H563XX_H
|
||||
|
||||
/*
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize Security Attribution Unit (SAU) CTRL register
|
||||
*/
|
||||
#define SAU_INIT_CTRL 1
|
||||
|
||||
/*
|
||||
// <q> Enable SAU
|
||||
// <i> Value for SAU->CTRL register bit ENABLE
|
||||
*/
|
||||
#define SAU_INIT_CTRL_ENABLE 0
|
||||
|
||||
/*
|
||||
// <o> When SAU is disabled
|
||||
// <0=> All Memory is Secure
|
||||
// <1=> All Memory is Non-Secure
|
||||
// <i> Value for SAU->CTRL register bit ALLNS
|
||||
// <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
|
||||
*/
|
||||
#define SAU_INIT_CTRL_ALLNS 1
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <h>Initialize Security Attribution Unit (SAU) Address Regions
|
||||
// <i>SAU configuration specifies regions to be one of:
|
||||
// <i> - Secure and Non-Secure Callable
|
||||
// <i> - Non-Secure
|
||||
// <i>Note: All memory regions not configured by SAU are Secure
|
||||
*/
|
||||
#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 0
|
||||
// <i> Setup SAU Region 0 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION0 0
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START0 0x0C0FE000 /* start address of SAU region 0 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END0 0x0C0FFFFF /* end address of SAU region 0 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC0 1
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 1
|
||||
// <i> Setup SAU Region 1 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION1 0
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START1 0x08100000 /* start address of SAU region 1 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END1 0x081FFFFF /* end address of SAU region 1 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC1 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 2
|
||||
// <i> Setup SAU Region 2 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION2 0
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START2 0x20050000 /* start address of SAU region 2 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END2 0x2009FFFF /* end address of SAU region 2 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC2 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 3
|
||||
// <i> Setup SAU Region 3 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION3 0
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START3 0x40000000 /* start address of SAU region 3 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END3 0x4FFFFFFF /* end address of SAU region 3 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC3 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 4
|
||||
// <i> Setup SAU Region 4 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION4 0
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START4 0x60000000 /* start address of SAU region 4 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END4 0x9FFFFFFF /* end address of SAU region 4 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC4 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 5
|
||||
// <i> Setup SAU Region 5 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION5 0
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START5 0x0BF90000 /* start address of SAU region 5 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END5 0x0BFA8FFF /* end address of SAU region 5 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC5 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 6
|
||||
// <i> Setup SAU Region 6 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION6 0
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC6 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 7
|
||||
// <i> Setup SAU Region 7 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION7 0
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC7 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// </h>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Setup behaviour of Sleep and Exception Handling
|
||||
*/
|
||||
#define SCB_CSR_AIRCR_INIT 0
|
||||
|
||||
/*
|
||||
// <o> Deep Sleep can be enabled by
|
||||
// <0=>Secure and Non-Secure state
|
||||
// <1=>Secure state only
|
||||
// <i> Value for SCB->CSR register bit DEEPSLEEPS
|
||||
*/
|
||||
#define SCB_CSR_DEEPSLEEPS_VAL 0
|
||||
|
||||
/*
|
||||
// <o>System reset request accessible from
|
||||
// <0=> Secure and Non-Secure state
|
||||
// <1=> Secure state only
|
||||
// <i> Value for SCB->AIRCR register bit SYSRESETREQS
|
||||
*/
|
||||
#define SCB_AIRCR_SYSRESETREQS_VAL 0
|
||||
|
||||
/*
|
||||
// <o>Priority of Non-Secure exceptions is
|
||||
// <0=> Not altered
|
||||
// <1=> Lowered to 0x04-0x07
|
||||
// <i> Value for SCB->AIRCR register bit PRIS
|
||||
*/
|
||||
#define SCB_AIRCR_PRIS_VAL 0
|
||||
|
||||
/*
|
||||
// <o>BusFault, HardFault, and NMI target
|
||||
// <0=> Secure state
|
||||
// <1=> Non-Secure state
|
||||
// <i> Value for SCB->AIRCR register bit BFHFNMINS
|
||||
*/
|
||||
#define SCB_AIRCR_BFHFNMINS_VAL 0
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Setup behaviour of Floating Point Unit
|
||||
*/
|
||||
#define TZ_FPU_NS_USAGE 1
|
||||
|
||||
/*
|
||||
// <o>Floating Point Unit usage
|
||||
// <0=> Secure state only
|
||||
// <3=> Secure and Non-Secure state
|
||||
// <i> Value for SCB->NSACR register bits CP10, CP11
|
||||
*/
|
||||
#define SCB_NSACR_CP10_11_VAL 3
|
||||
|
||||
/*
|
||||
// <o>Treat floating-point registers as Secure
|
||||
// <0=> Disabled
|
||||
// <1=> Enabled
|
||||
// <i> Value for FPU->FPCCR register bit TS
|
||||
*/
|
||||
#define FPU_FPCCR_TS_VAL 0
|
||||
|
||||
/*
|
||||
// <o>Clear on return (CLRONRET) accessibility
|
||||
// <0=> Secure and Non-Secure state
|
||||
// <1=> Secure state only
|
||||
// <i> Value for FPU->FPCCR register bit CLRONRETS
|
||||
*/
|
||||
#define FPU_FPCCR_CLRONRETS_VAL 0
|
||||
|
||||
/*
|
||||
// <o>Clear floating-point caller saved registers on exception return
|
||||
// <0=> Disabled
|
||||
// <1=> Enabled
|
||||
// <i> Value for FPU->FPCCR register bit CLRONRET
|
||||
*/
|
||||
#define FPU_FPCCR_CLRONRET_VAL 1
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <h>Setup Interrupt Target
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize ITNS 0 (Interrupts 0..31)
|
||||
*/
|
||||
#define NVIC_INIT_ITNS0 1
|
||||
|
||||
/*
|
||||
// Interrupts 0..31
|
||||
// <o.0> WWDG_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.1> PVD_AVD_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.2> RTC_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.3> RTC_S_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.4> TAMP_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.5> RAMCFG_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.6> FLASH_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.7> FLASH_S_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.8> GTZC_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.9> RCC_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.10> RCC_S_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.11> EXTI0_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.12> EXTI1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.13> EXTI2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.14> EXTI3_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.15> EXTI4_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.16> EXTI5_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.17> EXTI6_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.18> EXTI7_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.19> EXTI8_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.20> EXTI9_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.21> EXTI10_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.22> EXTI11_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.23> EXTI12_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.24> EXTI13_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.25> EXTI14_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.26> EXTI15_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.27> GPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.28> GPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.29> GPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.30> GPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.31> GPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
*/
|
||||
#define NVIC_INIT_ITNS0_VAL 0x00000000
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize ITNS 1 (Interrupts 32..63)
|
||||
*/
|
||||
#define NVIC_INIT_ITNS1 1
|
||||
|
||||
/*
|
||||
// Interrupts 32..63
|
||||
// <o.0> GPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.1> GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.2> GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.3> IWDG_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.4> ADC1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.5> DAC1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.6> FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.7> FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.8> TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.9> TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.10> TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.11> TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.12> TIM2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.13> TIM3_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.14> TIM4_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.15> TIM5_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.16> TIM6_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.17> TIM7_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.18> I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.19> I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.20> I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.21> I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.22> SPI1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.23> SPI2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.24> SPI3_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.25> USART1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.26> USART2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.27> USART3_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.28> UART4_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.29> UART5_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.30> LPUART1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.31> LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
*/
|
||||
#define NVIC_INIT_ITNS1_VAL 0x00000000
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize ITNS 2 (Interrupts 64..95)
|
||||
*/
|
||||
#define NVIC_INIT_ITNS2 1
|
||||
|
||||
/*
|
||||
// Interrupts 64..95
|
||||
// <o.0> TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.1> TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.2> TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.3> TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.4> ADC2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.5> LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.6> TIM15_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.7> TIM16_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.8> TIM17_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.9> USB_DRD_FS_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.10> CRS_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.11> UCPD1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.12> FMC_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.13> OCTOSPI1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.14> SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.15> I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.16> I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.17> SPI4_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.18> SPI5_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.19> SPI6_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.20> USART6_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.21> USART10_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.22> USART11_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.23> SAI1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.24> SAI2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.25> GPDMA2_Channel0_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.26> GPDMA2_Channel1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.27> GPDMA2_Channel2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.28> GPDMA2_Channel3_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.29> GPDMA2_Channel4_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.30> GPDMA2_Channel5_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.31> GPDMA2_Channel6_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
*/
|
||||
#define NVIC_INIT_ITNS2_VAL 0x00000000
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize ITNS 3 (Interrupts 96..126)
|
||||
*/
|
||||
#define NVIC_INIT_ITNS3 1
|
||||
|
||||
/*
|
||||
// Interrupts 96..126
|
||||
// <o.0> GPDMA2_Channel7_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.1> UART7_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.2> UART8_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.3> UART9_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.4> UART12_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.5> SDMMC2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.6> FPU_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.7> ICACHE_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.8> DCACHE_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.9> ETH_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.10> ETH_WKUP_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.11> DCMI_PSSI_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.12> FDCAN2_IT0_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.13> FDCAN2_IT1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.14> CORDIC_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.15> FMAC_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.16> DTS_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.17> RNG_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.18> HASH_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.19> CEC_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.20> TIM12_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.21> TIM13_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.22> TIM14_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.23> I3C1_EV_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.24> I3C1_ER_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.25> I2C4_EV_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.26> I2C4_ER_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.27> LPTIM3_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.28> LPTIM4_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.29> LPTIM5_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.30> LPTIM6_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
*/
|
||||
#define NVIC_INIT_ITNS3_VAL 0x00000000
|
||||
|
||||
/*
|
||||
// </h>
|
||||
*/
|
||||
|
||||
/*
|
||||
max 8 SAU regions.
|
||||
SAU regions are defined in partition.h
|
||||
*/
|
||||
|
||||
#define SAU_INIT_REGION(n) \
|
||||
SAU->RNR = (n & SAU_RNR_REGION_Msk); \
|
||||
SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
|
||||
SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
|
||||
((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
|
||||
|
||||
/**
|
||||
\brief Setup a SAU Region
|
||||
\details Writes the region information contained in SAU_Region to the
|
||||
registers SAU_RNR, SAU_RBAR, and SAU_RLAR
|
||||
*/
|
||||
__STATIC_INLINE void TZ_SAU_Setup (void)
|
||||
{
|
||||
|
||||
#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
|
||||
|
||||
#if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
|
||||
SAU_INIT_REGION(0);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
|
||||
SAU_INIT_REGION(1);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
|
||||
SAU_INIT_REGION(2);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
|
||||
SAU_INIT_REGION(3);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
|
||||
SAU_INIT_REGION(4);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
|
||||
SAU_INIT_REGION(5);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
|
||||
SAU_INIT_REGION(6);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
|
||||
SAU_INIT_REGION(7);
|
||||
#endif
|
||||
|
||||
/* repeat this for all possible SAU regions */
|
||||
|
||||
#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
|
||||
|
||||
|
||||
#if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
|
||||
SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
|
||||
((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;
|
||||
#endif
|
||||
|
||||
#if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
|
||||
SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) |
|
||||
((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);
|
||||
|
||||
SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk |
|
||||
SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) |
|
||||
((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) |
|
||||
((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
|
||||
((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) |
|
||||
((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk);
|
||||
#endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
|
||||
|
||||
#if defined (__FPU_USED) && (__FPU_USED == 1U) && \
|
||||
defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)
|
||||
|
||||
SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |
|
||||
((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
|
||||
|
||||
FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
|
||||
((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) |
|
||||
((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
|
||||
((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
|
||||
#endif
|
||||
|
||||
#if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
|
||||
NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
|
||||
#endif
|
||||
|
||||
#if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
|
||||
NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
|
||||
#endif
|
||||
|
||||
#if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
|
||||
NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
|
||||
#endif
|
||||
|
||||
#if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
|
||||
NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
#endif /* PARTITION_STM32H563XX_H */
|
||||
|
|
@ -0,0 +1,680 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file partition_stm32h573xx.h
|
||||
* @author MCD Application Team
|
||||
* @brief CMSIS STM32H573xx Device Header File for Initial Setup for Secure /
|
||||
* Non-Secure Zones for ARMCM33 based on CMSIS CORE partition_ARMCM33.h
|
||||
* Template.
|
||||
*
|
||||
* This file contains:
|
||||
* - Initialize Security Attribution Unit (SAU) CTRL register
|
||||
* - Setup behavior of Sleep and Exception Handling
|
||||
* - Setup behavior of Floating Point Unit
|
||||
* - Setup Interrupt Target
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef PARTITION_STM32H573XX_H
|
||||
#define PARTITION_STM32H573XX_H
|
||||
|
||||
/*
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize Security Attribution Unit (SAU) CTRL register
|
||||
*/
|
||||
#define SAU_INIT_CTRL 1
|
||||
|
||||
/*
|
||||
// <q> Enable SAU
|
||||
// <i> Value for SAU->CTRL register bit ENABLE
|
||||
*/
|
||||
#define SAU_INIT_CTRL_ENABLE 0
|
||||
|
||||
/*
|
||||
// <o> When SAU is disabled
|
||||
// <0=> All Memory is Secure
|
||||
// <1=> All Memory is Non-Secure
|
||||
// <i> Value for SAU->CTRL register bit ALLNS
|
||||
// <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
|
||||
*/
|
||||
#define SAU_INIT_CTRL_ALLNS 1
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <h>Initialize Security Attribution Unit (SAU) Address Regions
|
||||
// <i>SAU configuration specifies regions to be one of:
|
||||
// <i> - Secure and Non-Secure Callable
|
||||
// <i> - Non-Secure
|
||||
// <i>Note: All memory regions not configured by SAU are Secure
|
||||
*/
|
||||
#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 0
|
||||
// <i> Setup SAU Region 0 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION0 0
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START0 0x0C0FE000 /* start address of SAU region 0 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END0 0x0C0FFFFF /* end address of SAU region 0 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC0 1
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 1
|
||||
// <i> Setup SAU Region 1 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION1 0
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START1 0x08100000 /* start address of SAU region 1 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END1 0x081FFFFF /* end address of SAU region 1 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC1 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 2
|
||||
// <i> Setup SAU Region 2 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION2 0
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START2 0x20050000 /* start address of SAU region 2 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END2 0x2009FFFF /* end address of SAU region 2 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC2 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 3
|
||||
// <i> Setup SAU Region 3 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION3 0
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START3 0x40000000 /* start address of SAU region 3 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END3 0x4FFFFFFF /* end address of SAU region 3 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC3 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 4
|
||||
// <i> Setup SAU Region 4 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION4 0
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START4 0x60000000 /* start address of SAU region 4 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END4 0x9FFFFFFF /* end address of SAU region 4 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC4 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 5
|
||||
// <i> Setup SAU Region 5 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION5 0
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START5 0x0BF90000 /* start address of SAU region 5 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END5 0x0BFA8FFF /* end address of SAU region 5 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC5 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 6
|
||||
// <i> Setup SAU Region 6 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION6 0
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC6 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 7
|
||||
// <i> Setup SAU Region 7 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION7 0
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC7 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// </h>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Setup behaviour of Sleep and Exception Handling
|
||||
*/
|
||||
#define SCB_CSR_AIRCR_INIT 0
|
||||
|
||||
/*
|
||||
// <o> Deep Sleep can be enabled by
|
||||
// <0=>Secure and Non-Secure state
|
||||
// <1=>Secure state only
|
||||
// <i> Value for SCB->CSR register bit DEEPSLEEPS
|
||||
*/
|
||||
#define SCB_CSR_DEEPSLEEPS_VAL 0
|
||||
|
||||
/*
|
||||
// <o>System reset request accessible from
|
||||
// <0=> Secure and Non-Secure state
|
||||
// <1=> Secure state only
|
||||
// <i> Value for SCB->AIRCR register bit SYSRESETREQS
|
||||
*/
|
||||
#define SCB_AIRCR_SYSRESETREQS_VAL 0
|
||||
|
||||
/*
|
||||
// <o>Priority of Non-Secure exceptions is
|
||||
// <0=> Not altered
|
||||
// <1=> Lowered to 0x04-0x07
|
||||
// <i> Value for SCB->AIRCR register bit PRIS
|
||||
*/
|
||||
#define SCB_AIRCR_PRIS_VAL 0
|
||||
|
||||
/*
|
||||
// <o>BusFault, HardFault, and NMI target
|
||||
// <0=> Secure state
|
||||
// <1=> Non-Secure state
|
||||
// <i> Value for SCB->AIRCR register bit BFHFNMINS
|
||||
*/
|
||||
#define SCB_AIRCR_BFHFNMINS_VAL 0
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Setup behaviour of Floating Point Unit
|
||||
*/
|
||||
#define TZ_FPU_NS_USAGE 1
|
||||
|
||||
/*
|
||||
// <o>Floating Point Unit usage
|
||||
// <0=> Secure state only
|
||||
// <3=> Secure and Non-Secure state
|
||||
// <i> Value for SCB->NSACR register bits CP10, CP11
|
||||
*/
|
||||
#define SCB_NSACR_CP10_11_VAL 3
|
||||
|
||||
/*
|
||||
// <o>Treat floating-point registers as Secure
|
||||
// <0=> Disabled
|
||||
// <1=> Enabled
|
||||
// <i> Value for FPU->FPCCR register bit TS
|
||||
*/
|
||||
#define FPU_FPCCR_TS_VAL 0
|
||||
|
||||
/*
|
||||
// <o>Clear on return (CLRONRET) accessibility
|
||||
// <0=> Secure and Non-Secure state
|
||||
// <1=> Secure state only
|
||||
// <i> Value for FPU->FPCCR register bit CLRONRETS
|
||||
*/
|
||||
#define FPU_FPCCR_CLRONRETS_VAL 0
|
||||
|
||||
/*
|
||||
// <o>Clear floating-point caller saved registers on exception return
|
||||
// <0=> Disabled
|
||||
// <1=> Enabled
|
||||
// <i> Value for FPU->FPCCR register bit CLRONRET
|
||||
*/
|
||||
#define FPU_FPCCR_CLRONRET_VAL 1
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <h>Setup Interrupt Target
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize ITNS 0 (Interrupts 0..31)
|
||||
*/
|
||||
#define NVIC_INIT_ITNS0 1
|
||||
|
||||
/*
|
||||
// Interrupts 0..31
|
||||
// <o.0> WWDG_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.1> PVD_AVD_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.2> RTC_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.3> RTC_S_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.4> TAMP_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.5> RAMCFG_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.6> FLASH_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.7> FLASH_S_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.8> GTZC_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.9> RCC_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.10> RCC_S_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.11> EXTI0_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.12> EXTI1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.13> EXTI2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.14> EXTI3_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.15> EXTI4_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.16> EXTI5_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.17> EXTI6_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.18> EXTI7_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.19> EXTI8_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.20> EXTI9_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.21> EXTI10_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.22> EXTI11_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.23> EXTI12_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.24> EXTI13_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.25> EXTI14_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.26> EXTI15_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.27> GPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.28> GPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.29> GPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.30> GPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.31> GPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
*/
|
||||
#define NVIC_INIT_ITNS0_VAL 0x00000000
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize ITNS 1 (Interrupts 32..63)
|
||||
*/
|
||||
#define NVIC_INIT_ITNS1 1
|
||||
|
||||
/*
|
||||
// Interrupts 32..63
|
||||
// <o.0> GPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.1> GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.2> GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.3> IWDG_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.4> SAES_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.5> ADC1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.6> DAC1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.7> FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.8> FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.9> TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.10> TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.11> TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.12> TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.13> TIM2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.14> TIM3_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.15> TIM4_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.16> TIM5_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.17> TIM6_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.18> TIM7_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.19> I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.20> I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.21> I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.22> I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.23> SPI1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.24> SPI2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.25> SPI3_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.26> USART1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.27> USART2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.28> USART3_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.29> UART4_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.30> UART5_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.31> LPUART1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
*/
|
||||
#define NVIC_INIT_ITNS1_VAL 0x00000000
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize ITNS 2 (Interrupts 64..95)
|
||||
*/
|
||||
#define NVIC_INIT_ITNS2 1
|
||||
|
||||
/*
|
||||
// Interrupts 64..95
|
||||
// <o.0> LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.1> TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.2> TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.3> TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.4> TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.5> ADC2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.6> LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.7> TIM15_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.8> TIM16_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.9> TIM17_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.10> USB_DRD_FS_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.11> CRS_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.12> UCPD1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.13> FMC_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.14> OCTOSPI1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.15> SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.16> I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.17> I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.18> SPI4_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.19> SPI5_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.20> SPI6_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.21> USART6_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.22> USART10_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.23> USART11_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.24> SAI1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.25> SAI2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.26> GPDMA2_Channel0_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.27> GPDMA2_Channel1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.28> GPDMA2_Channel2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.29> GPDMA2_Channel3_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.30> GPDMA2_Channel4_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.31> GPDMA2_Channel5_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
*/
|
||||
#define NVIC_INIT_ITNS2_VAL 0x00000000
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize ITNS 3 (Interrupts 96..127)
|
||||
*/
|
||||
#define NVIC_INIT_ITNS3 1
|
||||
|
||||
/*
|
||||
// Interrupts 96..127
|
||||
// <o.0> GPDMA2_Channel6_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.1> GPDMA2_Channel7_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.2> UART7_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.3> UART8_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.4> UART9_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.5> UART12_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.6> SDMMC2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.7> FPU_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.8> ICACHE_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.9> DCACHE_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.10> ETH_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.11> ETH_WKUP_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.12> DCMI_PSSI_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.13> FDCAN2_IT0_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.14> FDCAN2_IT1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.15> CORDIC_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.16> FMAC_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.17> DTS_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.18> RNG_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.19> OTFDEC1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.20> AES_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.21> HASH_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.22> PKA_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.23> CEC_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.24> TIM12_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.25> TIM13_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.26> TIM14_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.27> I3C1_EV_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.28> I3C1_ER_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.29> I2C4_EV_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.30> I2C4_ER_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.31> LPTIM3_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
*/
|
||||
#define NVIC_INIT_ITNS3_VAL 0x00000000
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize ITNS 4 (Interrupts 128..130)
|
||||
*/
|
||||
#define NVIC_INIT_ITNS4 1
|
||||
|
||||
/*
|
||||
// Interrupts 128..130
|
||||
// <o.0> LPTIM4_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.1> LPTIM5_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.2> LPTIM6_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
*/
|
||||
#define NVIC_INIT_ITNS4_VAL 0x00000000
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// </h>
|
||||
*/
|
||||
|
||||
/*
|
||||
max 8 SAU regions.
|
||||
SAU regions are defined in partition.h
|
||||
*/
|
||||
|
||||
#define SAU_INIT_REGION(n) \
|
||||
SAU->RNR = (n & SAU_RNR_REGION_Msk); \
|
||||
SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
|
||||
SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
|
||||
((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
|
||||
|
||||
/**
|
||||
\brief Setup a SAU Region
|
||||
\details Writes the region information contained in SAU_Region to the
|
||||
registers SAU_RNR, SAU_RBAR, and SAU_RLAR
|
||||
*/
|
||||
__STATIC_INLINE void TZ_SAU_Setup (void)
|
||||
{
|
||||
|
||||
#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
|
||||
|
||||
#if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
|
||||
SAU_INIT_REGION(0);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
|
||||
SAU_INIT_REGION(1);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
|
||||
SAU_INIT_REGION(2);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
|
||||
SAU_INIT_REGION(3);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
|
||||
SAU_INIT_REGION(4);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
|
||||
SAU_INIT_REGION(5);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
|
||||
SAU_INIT_REGION(6);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
|
||||
SAU_INIT_REGION(7);
|
||||
#endif
|
||||
|
||||
/* repeat this for all possible SAU regions */
|
||||
|
||||
#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
|
||||
|
||||
|
||||
#if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
|
||||
SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
|
||||
((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;
|
||||
#endif
|
||||
|
||||
#if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
|
||||
SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) |
|
||||
((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);
|
||||
|
||||
SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk |
|
||||
SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) |
|
||||
((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) |
|
||||
((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
|
||||
((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) |
|
||||
((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk);
|
||||
#endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
|
||||
|
||||
#if defined (__FPU_USED) && (__FPU_USED == 1U) && \
|
||||
defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)
|
||||
|
||||
SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |
|
||||
((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
|
||||
|
||||
FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
|
||||
((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) |
|
||||
((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
|
||||
((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
|
||||
#endif
|
||||
|
||||
#if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
|
||||
NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
|
||||
#endif
|
||||
|
||||
#if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
|
||||
NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
|
||||
#endif
|
||||
|
||||
#if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
|
||||
NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
|
||||
#endif
|
||||
|
||||
#if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
|
||||
NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
|
||||
#endif
|
||||
|
||||
#if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)
|
||||
NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
#endif /* PARTITION_STM32H573XX_H */
|
||||
|
|
@ -0,0 +1,68 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file partition_stm32h5xx.h
|
||||
* @author MCD Application Team
|
||||
* @brief CMSIS STM32H5xx Device Header File for Initial Setup for Secure /
|
||||
* Non-Secure Zones for ARMCM33 based on CMSIS CORE partition_ARMCM33.h
|
||||
* Template.
|
||||
*
|
||||
* The file is included in system_stm32h5xx_s.c in secure application.
|
||||
* It includes the configuration section that allows to select the
|
||||
* STM32H5xx device partitioning file for system core secure attributes
|
||||
* and interrupt secure and non-secure assignment.
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32h5xx
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef PARTITION_STM32H5XX_H
|
||||
#define PARTITION_STM32H5XX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/** @addtogroup Secure_configuration_section
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32H573xx)
|
||||
#include "partition_stm32h573xx.h"
|
||||
#elif defined(STM32H563xx)
|
||||
#include "partition_stm32h563xx.h"
|
||||
#elif defined(STM32H562xx)
|
||||
#include "partition_stm32h562xx.h"
|
||||
#else
|
||||
#error "Please select first the target STM32H5xx device used in your application (in stm32h5xx.h file)"
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* PARTITION_STM32H5XX_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,238 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h5xx.h
|
||||
* @author MCD Application Team
|
||||
* @brief CMSIS STM32H5xx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* The file is the unique include file that the application programmer
|
||||
* is using in the C source code, usually in main.c. This file contains:
|
||||
* - Configuration section that allows to select:
|
||||
* - The STM32H5xx device used in the target application
|
||||
* - To use or not the peripheral’s drivers in application code(i.e.
|
||||
* code will be based on direct access to peripheral’s registers
|
||||
* rather than drivers API), this option is controlled by
|
||||
* "#define USE_HAL_DRIVER"
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32h5xx
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef STM32H5xx_H
|
||||
#define STM32H5xx_H
|
||||
#include "math.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/** @addtogroup Library_configuration_section
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief STM32 Family
|
||||
*/
|
||||
#if !defined (STM32H5)
|
||||
#define STM32H5
|
||||
#endif /* STM32H5 */
|
||||
|
||||
/* Uncomment the line below according to the target STM32H5 device used in your
|
||||
application
|
||||
*/
|
||||
|
||||
#if !defined (STM32H573xx) && !defined (STM32H563xx) \
|
||||
&& !defined (STM32H562xx) && !defined (STM32H503xx)
|
||||
/* #define STM32H573xx */ /*!< STM32H5753xx Devices */
|
||||
/* #define STM32H563xx */ /*!< STM32H563xx Devices */
|
||||
/* #define STM32H562xx */ /*!< STM32H562xx Devices */
|
||||
/* #define STM32H503xx */ /*!< STM32H503xx Devices */
|
||||
#endif
|
||||
|
||||
/* Tip: To avoid modifying this file each time you need to switch between these
|
||||
devices, you can define the device in your toolchain compiler preprocessor.
|
||||
*/
|
||||
#if !defined (USE_HAL_DRIVER)
|
||||
/**
|
||||
* @brief Comment the line below if you will not use the peripherals drivers.
|
||||
In this case, these drivers will not be included and the application code will
|
||||
be based on direct access to peripherals registers
|
||||
*/
|
||||
/*#define USE_HAL_DRIVER */
|
||||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
/**
|
||||
* @brief CMSIS Device version number 1.1.0
|
||||
*/
|
||||
#define __STM32H5_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
|
||||
#define __STM32H5_CMSIS_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
|
||||
#define __STM32H5_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
|
||||
#define __STM32H5_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32H5_CMSIS_VERSION ((__STM32H5_CMSIS_VERSION_MAIN << 24U)\
|
||||
|(__STM32H5_CMSIS_VERSION_SUB1 << 16U)\
|
||||
|(__STM32H5_CMSIS_VERSION_SUB2 << 8U )\
|
||||
|(__STM32H5_CMSIS_VERSION_RC))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Device_Included
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32H573xx)
|
||||
#include "stm32h573xx.h"
|
||||
#elif defined(STM32H563xx)
|
||||
#include "stm32h563xx.h"
|
||||
#elif defined(STM32H562xx)
|
||||
#include "stm32h562xx.h"
|
||||
#elif defined(STM32H503xx)
|
||||
#include "stm32h503xx.h"
|
||||
#else
|
||||
#error "Please select first the target STM32H5xx device used in your application (in stm32h5xx.h file)"
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Exported_types
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
RESET = 0,
|
||||
SET = !RESET
|
||||
} FlagStatus, ITStatus;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
DISABLE = 0,
|
||||
ENABLE = !DISABLE
|
||||
} FunctionalState;
|
||||
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
|
||||
|
||||
typedef enum
|
||||
{
|
||||
SUCCESS = 0,
|
||||
ERROR = !SUCCESS
|
||||
} ErrorStatus;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup Exported_macros
|
||||
* @{
|
||||
*/
|
||||
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
|
||||
|
||||
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
|
||||
|
||||
#define READ_BIT(REG, BIT) ((REG) & (BIT))
|
||||
|
||||
#define CLEAR_REG(REG) ((REG) = (0x0))
|
||||
|
||||
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
|
||||
|
||||
#define READ_REG(REG) ((REG))
|
||||
|
||||
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
|
||||
|
||||
/* Use of CMSIS compiler intrinsics for register exclusive access */
|
||||
/* Atomic 32-bit register access macro to set one or several bits */
|
||||
#define ATOMIC_SET_BIT(REG, BIT) \
|
||||
do { \
|
||||
uint32_t val; \
|
||||
do { \
|
||||
val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \
|
||||
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
|
||||
} while(0)
|
||||
|
||||
/* Atomic 32-bit register access macro to clear one or several bits */
|
||||
#define ATOMIC_CLEAR_BIT(REG, BIT) \
|
||||
do { \
|
||||
uint32_t val; \
|
||||
do { \
|
||||
val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \
|
||||
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
|
||||
} while(0)
|
||||
|
||||
/* Atomic 32-bit register access macro to clear and set one or several bits */
|
||||
#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
|
||||
do { \
|
||||
uint32_t val; \
|
||||
do { \
|
||||
val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
|
||||
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
|
||||
} while(0)
|
||||
|
||||
/* Atomic 16-bit register access macro to set one or several bits */
|
||||
#define ATOMIC_SETH_BIT(REG, BIT) \
|
||||
do { \
|
||||
uint16_t val; \
|
||||
do { \
|
||||
val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \
|
||||
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
|
||||
} while(0)
|
||||
|
||||
/* Atomic 16-bit register access macro to clear one or several bits */
|
||||
#define ATOMIC_CLEARH_BIT(REG, BIT) \
|
||||
do { \
|
||||
uint16_t val; \
|
||||
do { \
|
||||
val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \
|
||||
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
|
||||
} while(0)
|
||||
|
||||
/* Atomic 16-bit register access macro to clear and set one or several bits */
|
||||
#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \
|
||||
do { \
|
||||
uint16_t val; \
|
||||
do { \
|
||||
val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
|
||||
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
|
||||
} while(0)
|
||||
|
||||
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined (USE_HAL_DRIVER)
|
||||
#include "stm32h5xx_hal.h"
|
||||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* STM32H5xx_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -0,0 +1,107 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32h5xx.h
|
||||
* @author MCD Application Team
|
||||
* @brief CMSIS Cortex-M33 Device System Source File for STM32H5xx devices.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32h5xx_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef SYSTEM_STM32H5XX_H
|
||||
#define SYSTEM_STM32H5XX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @addtogroup STM32H5xx_System_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H5xx_System_Exported_Variables
|
||||
* @{
|
||||
*/
|
||||
/* The SystemCoreClock variable is updated in three ways:
|
||||
1) by calling CMSIS function SystemCoreClockUpdate()
|
||||
2) by calling HAL API function HAL_RCC_GetSysClockFreq()
|
||||
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
|
||||
Note: If you use this function to configure the system clock; then there
|
||||
is no need to call the 2 first functions listed above, since SystemCoreClock
|
||||
variable is updated automatically.
|
||||
*/
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
|
||||
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup STM32H5xx_System_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system.
|
||||
*
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
extern void SystemInit (void);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock variable.
|
||||
*
|
||||
* Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
|
||||
*/
|
||||
extern void SystemCoreClockUpdate (void);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock variable from secure application and return its value
|
||||
* when security is implemented in the system (Non-secure callable function).
|
||||
*
|
||||
* Returns the SystemCoreClock value with current core Clock retrieved from cpu registers.
|
||||
*/
|
||||
extern uint32_t SECURE_SystemCoreClockUpdate(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* SYSTEM_STM32H5XX_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
This software component is provided to you as part of a software package and
|
||||
applicable license terms are in the Package_license file. If you received this
|
||||
software component outside of a package or without applicable license terms,
|
||||
the terms of the Apache-2.0 license shall apply.
|
||||
You may obtain a copy of the Apache-2.0 at:
|
||||
https://opensource.org/licenses/Apache-2.0
|
||||
|
|
@ -0,0 +1,479 @@
|
|||
;*******************************************************************************
|
||||
;* File Name : startup_stm32h503xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : STM32H503xx Non Crypto devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M33 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;*******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* Copyright (c) 2023 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;*******************************************************************************
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection Interrupt
|
||||
DCD RTC_IRQHandler ; RTC non-secure interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD TAMP_IRQHandler ; Tamper non-secure interrupt
|
||||
DCD RAMCFG_IRQHandler ; RAMCFG global
|
||||
DCD FLASH_IRQHandler ; FLASH non-secure global interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD GTZC_IRQHandler ; Global TrustZone Controller interrupt
|
||||
DCD RCC_IRQHandler ; RCC non-secure global interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD EXTI0_IRQHandler ; EXTI Line0 interrupt
|
||||
DCD EXTI1_IRQHandler ; EXTI Line1 interrupt
|
||||
DCD EXTI2_IRQHandler ; EXTI Line2 interrupt
|
||||
DCD EXTI3_IRQHandler ; EXTI Line3 interrupt
|
||||
DCD EXTI4_IRQHandler ; EXTI Line4 interrupt
|
||||
DCD EXTI5_IRQHandler ; EXTI Line5 interrupt
|
||||
DCD EXTI6_IRQHandler ; EXTI Line6 interrupt
|
||||
DCD EXTI7_IRQHandler ; EXTI Line7 interrupt
|
||||
DCD EXTI8_IRQHandler ; EXTI Line8 interrupt
|
||||
DCD EXTI9_IRQHandler ; EXTI Line9 interrupt
|
||||
DCD EXTI10_IRQHandler ; EXTI Line10 interrupt
|
||||
DCD EXTI11_IRQHandler ; EXTI Line11 interrupt
|
||||
DCD EXTI12_IRQHandler ; EXTI Line12 interrupt
|
||||
DCD EXTI13_IRQHandler ; EXTI Line13 interrupt
|
||||
DCD EXTI14_IRQHandler ; EXTI Line14 interrupt
|
||||
DCD EXTI15_IRQHandler ; EXTI Line15 interrupt
|
||||
DCD GPDMA1_Channel0_IRQHandler ; GPDMA1 Channel 0 global interrupt
|
||||
DCD GPDMA1_Channel1_IRQHandler ; GPDMA1 Channel 1 global interrupt
|
||||
DCD GPDMA1_Channel2_IRQHandler ; GPDMA1 Channel 2 global interrupt
|
||||
DCD GPDMA1_Channel3_IRQHandler ; GPDMA1 Channel 3 global interrupt
|
||||
DCD GPDMA1_Channel4_IRQHandler ; GPDMA1 Channel 4 global interrupt
|
||||
DCD GPDMA1_Channel5_IRQHandler ; GPDMA1 Channel 5 global interrupt
|
||||
DCD GPDMA1_Channel6_IRQHandler ; GPDMA1 Channel 6 global interrupt
|
||||
DCD GPDMA1_Channel7_IRQHandler ; GPDMA1 Channel 7 global interrupt
|
||||
DCD IWDG_IRQHandler ; IWDG global interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD ADC1_IRQHandler ; ADC1 global interrupt
|
||||
DCD DAC1_IRQHandler ; DAC1 global interrupt
|
||||
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt 0
|
||||
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt 1
|
||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
|
||||
DCD TIM1_UP_IRQHandler ; TIM1 Update interrupt
|
||||
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation interrupt
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare interrupt
|
||||
DCD TIM2_IRQHandler ; TIM2 global interrupt
|
||||
DCD TIM3_IRQHandler ; TIM3 global interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM6_IRQHandler ; TIM6 global interrupt
|
||||
DCD TIM7_IRQHandler ; TIM7 global interrupt
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event interrupt
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error interrupt
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event interrupt
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error interrupt
|
||||
DCD SPI1_IRQHandler ; SPI1 global interrupt
|
||||
DCD SPI2_IRQHandler ; SPI2 global interrupt
|
||||
DCD SPI3_IRQHandler ; SPI3 global interrupt
|
||||
DCD USART1_IRQHandler ; USART1 global interrupt
|
||||
DCD USART2_IRQHandler ; USART2 global interrupt
|
||||
DCD USART3_IRQHandler ; USART3 global interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD LPUART1_IRQHandler ; LPUART1 global interrupt
|
||||
DCD LPTIM1_IRQHandler ; LPTIM1 global interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD LPTIM2_IRQHandler ; LPTIM2 global interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD USB_DRD_FS_IRQHandler ; USB DRD FS global interrupt
|
||||
DCD CRS_IRQHandler ; CRS global interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD GPDMA2_Channel0_IRQHandler ; GPDMA2 Channel 0 global interrupt
|
||||
DCD GPDMA2_Channel1_IRQHandler ; GPDMA2 Channel 1 global interrupt
|
||||
DCD GPDMA2_Channel2_IRQHandler ; GPDMA2 Channel 2 global interrupt
|
||||
DCD GPDMA2_Channel3_IRQHandler ; GPDMA2 Channel 3 global interrupt
|
||||
DCD GPDMA2_Channel4_IRQHandler ; GPDMA2 Channel 4 global interrupt
|
||||
DCD GPDMA2_Channel5_IRQHandler ; GPDMA2 Channel 5 global interrupt
|
||||
DCD GPDMA2_Channel6_IRQHandler ; GPDMA2 Channel 6 global interrupt
|
||||
DCD GPDMA2_Channel7_IRQHandler ; GPDMA2 Channel 7 global interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD FPU_IRQHandler ; FPU global interrupt
|
||||
DCD ICACHE_IRQHandler ; Instruction cache global interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD DTS_IRQHandler ; DTS global interrupt
|
||||
DCD RNG_IRQHandler ; RNG global interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD HASH_IRQHandler ; HASH global interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD I3C1_EV_IRQHandler ; I3C1 Event interrupt
|
||||
DCD I3C1_ER_IRQHandler ; I3C1 Error interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD I3C2_EV_IRQHandler ; I3C2 Event interrupt
|
||||
DCD I3C2_ER_IRQHandler ; I3C2 Error interrupt
|
||||
DCD COMP1_IRQHandler ; COMP1 global interrupt
|
||||
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler\
|
||||
PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SecureFault_Handler\
|
||||
PROC
|
||||
EXPORT SecureFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler\
|
||||
PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler\
|
||||
PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler\
|
||||
PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK]
|
||||
EXPORT PVD_AVD_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT TAMP_IRQHandler [WEAK]
|
||||
EXPORT RAMCFG_IRQHandler [WEAK]
|
||||
EXPORT FLASH_IRQHandler [WEAK]
|
||||
EXPORT GTZC_IRQHandler [WEAK]
|
||||
EXPORT RCC_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT EXTI5_IRQHandler [WEAK]
|
||||
EXPORT EXTI6_IRQHandler [WEAK]
|
||||
EXPORT EXTI7_IRQHandler [WEAK]
|
||||
EXPORT EXTI8_IRQHandler [WEAK]
|
||||
EXPORT EXTI9_IRQHandler [WEAK]
|
||||
EXPORT EXTI10_IRQHandler [WEAK]
|
||||
EXPORT EXTI11_IRQHandler [WEAK]
|
||||
EXPORT EXTI12_IRQHandler [WEAK]
|
||||
EXPORT EXTI13_IRQHandler [WEAK]
|
||||
EXPORT EXTI14_IRQHandler [WEAK]
|
||||
EXPORT EXTI15_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel0_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel1_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel2_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel3_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel4_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel5_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel6_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel7_IRQHandler [WEAK]
|
||||
EXPORT IWDG_IRQHandler [WEAK]
|
||||
EXPORT ADC1_IRQHandler [WEAK]
|
||||
EXPORT DAC1_IRQHandler [WEAK]
|
||||
EXPORT FDCAN1_IT0_IRQHandler [WEAK]
|
||||
EXPORT FDCAN1_IT1_IRQHandler [WEAK]
|
||||
EXPORT TIM1_BRK_IRQHandler [WEAK]
|
||||
EXPORT TIM1_UP_IRQHandler [WEAK]
|
||||
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
|
||||
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT TIM3_IRQHandler [WEAK]
|
||||
EXPORT TIM6_IRQHandler [WEAK]
|
||||
EXPORT TIM7_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT SPI3_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT USART2_IRQHandler [WEAK]
|
||||
EXPORT USART3_IRQHandler [WEAK]
|
||||
EXPORT LPUART1_IRQHandler [WEAK]
|
||||
EXPORT LPTIM1_IRQHandler [WEAK]
|
||||
EXPORT LPTIM2_IRQHandler [WEAK]
|
||||
EXPORT USB_DRD_FS_IRQHandler [WEAK]
|
||||
EXPORT CRS_IRQHandler [WEAK]
|
||||
EXPORT GPDMA2_Channel0_IRQHandler [WEAK]
|
||||
EXPORT GPDMA2_Channel1_IRQHandler [WEAK]
|
||||
EXPORT GPDMA2_Channel2_IRQHandler [WEAK]
|
||||
EXPORT GPDMA2_Channel3_IRQHandler [WEAK]
|
||||
EXPORT GPDMA2_Channel4_IRQHandler [WEAK]
|
||||
EXPORT GPDMA2_Channel5_IRQHandler [WEAK]
|
||||
EXPORT GPDMA2_Channel6_IRQHandler [WEAK]
|
||||
EXPORT GPDMA2_Channel7_IRQHandler [WEAK]
|
||||
EXPORT COMP1_IRQHandler [WEAK]
|
||||
EXPORT I3C2_EV_IRQHandler [WEAK]
|
||||
EXPORT I3C2_ER_IRQHandler [WEAK]
|
||||
EXPORT FPU_IRQHandler [WEAK]
|
||||
EXPORT ICACHE_IRQHandler [WEAK]
|
||||
EXPORT DTS_IRQHandler [WEAK]
|
||||
EXPORT RNG_IRQHandler [WEAK]
|
||||
EXPORT HASH_IRQHandler [WEAK]
|
||||
EXPORT I3C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I3C1_ER_IRQHandler [WEAK]
|
||||
|
||||
WWDG_IRQHandler
|
||||
PVD_AVD_IRQHandler
|
||||
RTC_IRQHandler
|
||||
TAMP_IRQHandler
|
||||
RAMCFG_IRQHandler
|
||||
FLASH_IRQHandler
|
||||
GTZC_IRQHandler
|
||||
RCC_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
EXTI5_IRQHandler
|
||||
EXTI6_IRQHandler
|
||||
EXTI7_IRQHandler
|
||||
EXTI8_IRQHandler
|
||||
EXTI9_IRQHandler
|
||||
EXTI10_IRQHandler
|
||||
EXTI11_IRQHandler
|
||||
EXTI12_IRQHandler
|
||||
EXTI13_IRQHandler
|
||||
EXTI14_IRQHandler
|
||||
EXTI15_IRQHandler
|
||||
GPDMA1_Channel0_IRQHandler
|
||||
GPDMA1_Channel1_IRQHandler
|
||||
GPDMA1_Channel2_IRQHandler
|
||||
GPDMA1_Channel3_IRQHandler
|
||||
GPDMA1_Channel4_IRQHandler
|
||||
GPDMA1_Channel5_IRQHandler
|
||||
GPDMA1_Channel6_IRQHandler
|
||||
GPDMA1_Channel7_IRQHandler
|
||||
IWDG_IRQHandler
|
||||
ADC1_IRQHandler
|
||||
DAC1_IRQHandler
|
||||
FDCAN1_IT0_IRQHandler
|
||||
FDCAN1_IT1_IRQHandler
|
||||
TIM1_BRK_IRQHandler
|
||||
TIM1_UP_IRQHandler
|
||||
TIM1_TRG_COM_IRQHandler
|
||||
TIM1_CC_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
TIM3_IRQHandler
|
||||
TIM6_IRQHandler
|
||||
TIM7_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
I2C2_EV_IRQHandler
|
||||
I2C2_ER_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
SPI3_IRQHandler
|
||||
USART1_IRQHandler
|
||||
USART2_IRQHandler
|
||||
USART3_IRQHandler
|
||||
LPUART1_IRQHandler
|
||||
LPTIM1_IRQHandler
|
||||
LPTIM2_IRQHandler
|
||||
USB_DRD_FS_IRQHandler
|
||||
CRS_IRQHandler
|
||||
GPDMA2_Channel0_IRQHandler
|
||||
GPDMA2_Channel1_IRQHandler
|
||||
GPDMA2_Channel2_IRQHandler
|
||||
GPDMA2_Channel3_IRQHandler
|
||||
GPDMA2_Channel4_IRQHandler
|
||||
GPDMA2_Channel5_IRQHandler
|
||||
GPDMA2_Channel6_IRQHandler
|
||||
GPDMA2_Channel7_IRQHandler
|
||||
COMP1_IRQHandler
|
||||
I3C2_EV_IRQHandler
|
||||
I3C2_ER_IRQHandler
|
||||
FPU_IRQHandler
|
||||
ICACHE_IRQHandler
|
||||
DTS_IRQHandler
|
||||
RNG_IRQHandler
|
||||
HASH_IRQHandler
|
||||
I3C1_EV_IRQHandler
|
||||
I3C1_ER_IRQHandler
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
|
||||
|
|
@ -0,0 +1,563 @@
|
|||
;*******************************************************************************
|
||||
;* File Name : startup_stm32h562xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : STM32H562xx Non Crypto devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M33 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;*******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* Copyright (c) 2023 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;*******************************************************************************
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD SecureFault_Handler ; Secure Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection Interrupt
|
||||
DCD RTC_IRQHandler ; RTC non-secure interrupt
|
||||
DCD RTC_S_IRQHandler ; RTC secure interrupt
|
||||
DCD TAMP_IRQHandler ; Tamper non-secure interrupt
|
||||
DCD RAMCFG_IRQHandler ; RAMCFG global
|
||||
DCD FLASH_IRQHandler ; FLASH non-secure global interrupt
|
||||
DCD FLASH_S_IRQHandler ; FLASH secure global interrupt
|
||||
DCD GTZC_IRQHandler ; Global TrustZone Controller interrupt
|
||||
DCD RCC_IRQHandler ; RCC non-secure global interrupt
|
||||
DCD RCC_S_IRQHandler ; RCC secure global interrupt
|
||||
DCD EXTI0_IRQHandler ; EXTI Line0 interrupt
|
||||
DCD EXTI1_IRQHandler ; EXTI Line1 interrupt
|
||||
DCD EXTI2_IRQHandler ; EXTI Line2 interrupt
|
||||
DCD EXTI3_IRQHandler ; EXTI Line3 interrupt
|
||||
DCD EXTI4_IRQHandler ; EXTI Line4 interrupt
|
||||
DCD EXTI5_IRQHandler ; EXTI Line5 interrupt
|
||||
DCD EXTI6_IRQHandler ; EXTI Line6 interrupt
|
||||
DCD EXTI7_IRQHandler ; EXTI Line7 interrupt
|
||||
DCD EXTI8_IRQHandler ; EXTI Line8 interrupt
|
||||
DCD EXTI9_IRQHandler ; EXTI Line9 interrupt
|
||||
DCD EXTI10_IRQHandler ; EXTI Line10 interrupt
|
||||
DCD EXTI11_IRQHandler ; EXTI Line11 interrupt
|
||||
DCD EXTI12_IRQHandler ; EXTI Line12 interrupt
|
||||
DCD EXTI13_IRQHandler ; EXTI Line13 interrupt
|
||||
DCD EXTI14_IRQHandler ; EXTI Line14 interrupt
|
||||
DCD EXTI15_IRQHandler ; EXTI Line15 interrupt
|
||||
DCD GPDMA1_Channel0_IRQHandler ; GPDMA1 Channel 0 global interrupt
|
||||
DCD GPDMA1_Channel1_IRQHandler ; GPDMA1 Channel 1 global interrupt
|
||||
DCD GPDMA1_Channel2_IRQHandler ; GPDMA1 Channel 2 global interrupt
|
||||
DCD GPDMA1_Channel3_IRQHandler ; GPDMA1 Channel 3 global interrupt
|
||||
DCD GPDMA1_Channel4_IRQHandler ; GPDMA1 Channel 4 global interrupt
|
||||
DCD GPDMA1_Channel5_IRQHandler ; GPDMA1 Channel 5 global interrupt
|
||||
DCD GPDMA1_Channel6_IRQHandler ; GPDMA1 Channel 6 global interrupt
|
||||
DCD GPDMA1_Channel7_IRQHandler ; GPDMA1 Channel 7 global interrupt
|
||||
DCD IWDG_IRQHandler ; IWDG global interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD ADC1_IRQHandler ; ADC1 global interrupt
|
||||
DCD DAC1_IRQHandler ; DAC1 global interrupt
|
||||
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt 0
|
||||
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt 1
|
||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
|
||||
DCD TIM1_UP_IRQHandler ; TIM1 Update interrupt
|
||||
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation interrupt
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare interrupt
|
||||
DCD TIM2_IRQHandler ; TIM2 global interrupt
|
||||
DCD TIM3_IRQHandler ; TIM3 global interrupt
|
||||
DCD TIM4_IRQHandler ; TIM4 global interrupt
|
||||
DCD TIM5_IRQHandler ; TIM5 global interrupt
|
||||
DCD TIM6_IRQHandler ; TIM6 global interrupt
|
||||
DCD TIM7_IRQHandler ; TIM7 global interrupt
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event interrupt
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error interrupt
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event interrupt
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error interrupt
|
||||
DCD SPI1_IRQHandler ; SPI1 global interrupt
|
||||
DCD SPI2_IRQHandler ; SPI2 global interrupt
|
||||
DCD SPI3_IRQHandler ; SPI3 global interrupt
|
||||
DCD USART1_IRQHandler ; USART1 global interrupt
|
||||
DCD USART2_IRQHandler ; USART2 global interrupt
|
||||
DCD USART3_IRQHandler ; USART3 global interrupt
|
||||
DCD UART4_IRQHandler ; UART4 global interrupt
|
||||
DCD UART5_IRQHandler ; UART5 global interrupt
|
||||
DCD LPUART1_IRQHandler ; LPUART1 global interrupt
|
||||
DCD LPTIM1_IRQHandler ; LPTIM1 global interrupt
|
||||
DCD TIM8_BRK_IRQHandler ; TIM8 Break interrupt
|
||||
DCD TIM8_UP_IRQHandler ; TIM8 Update interrupt
|
||||
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation interrupt
|
||||
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare interrupt
|
||||
DCD ADC2_IRQHandler ; ADC2 global interrupt
|
||||
DCD LPTIM2_IRQHandler ; LPTIM2 global interrupt
|
||||
DCD TIM15_IRQHandler ; TIM15 global interrupt
|
||||
DCD TIM16_IRQHandler ; TIM16 global interrupt
|
||||
DCD TIM17_IRQHandler ; TIM17 global interrupt
|
||||
DCD USB_DRD_FS_IRQHandler ; USB DRD FS global interrupt
|
||||
DCD CRS_IRQHandler ; CRS global interrupt
|
||||
DCD UCPD1_IRQHandler ; UCPD1 global interrupt
|
||||
DCD FMC_IRQHandler ; FMC global interrupt
|
||||
DCD OCTOSPI1_IRQHandler ; OctoSPI1 global interrupt
|
||||
DCD SDMMC1_IRQHandler ; SDMMC1 global interrupt
|
||||
DCD I2C3_EV_IRQHandler ; I2C2 Event interrupt
|
||||
DCD I2C3_ER_IRQHandler ; I2C2 Error interrupt
|
||||
DCD SPI4_IRQHandler ; SPI4 global interrupt
|
||||
DCD SPI5_IRQHandler ; SPI5 global interrupt
|
||||
DCD SPI6_IRQHandler ; SPI6 global interrupt
|
||||
DCD USART6_IRQHandler ; USART6 global interrupt
|
||||
DCD USART10_IRQHandler ; USART10 global interrupt
|
||||
DCD USART11_IRQHandler ; USART11 global interrupt
|
||||
DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt
|
||||
DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt
|
||||
DCD GPDMA2_Channel0_IRQHandler ; GPDMA2 Channel 0 global interrupt
|
||||
DCD GPDMA2_Channel1_IRQHandler ; GPDMA2 Channel 1 global interrupt
|
||||
DCD GPDMA2_Channel2_IRQHandler ; GPDMA2 Channel 2 global interrupt
|
||||
DCD GPDMA2_Channel3_IRQHandler ; GPDMA2 Channel 3 global interrupt
|
||||
DCD GPDMA2_Channel4_IRQHandler ; GPDMA2 Channel 4 global interrupt
|
||||
DCD GPDMA2_Channel5_IRQHandler ; GPDMA2 Channel 5 global interrupt
|
||||
DCD GPDMA2_Channel6_IRQHandler ; GPDMA2 Channel 6 global interrupt
|
||||
DCD GPDMA2_Channel7_IRQHandler ; GPDMA2 Channel 7 global interrupt
|
||||
DCD UART7_IRQHandler ; UART7 global interrupt
|
||||
DCD UART8_IRQHandler ; UART8 global interrupt
|
||||
DCD UART9_IRQHandler ; UART9 global interrupt
|
||||
DCD UART12_IRQHandler ; UART12 global interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD FPU_IRQHandler ; FPU global interrupt
|
||||
DCD ICACHE_IRQHandler ; Instruction cache global interrupt
|
||||
DCD DCACHE1_IRQHandler ; DCACHE1 global interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD DCMI_PSSI_IRQHandler ; DCMI PSSI global interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD CORDIC_IRQHandler ; CORDIC global interrupt
|
||||
DCD FMAC_IRQHandler ; FMAC global interrupt
|
||||
DCD DTS_IRQHandler ; DTS global interrupt
|
||||
DCD RNG_IRQHandler ; RNG global interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD HASH_IRQHandler ; HASH global interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD CEC_IRQHandler ; CEC global interrupt
|
||||
DCD TIM12_IRQHandler ; TIM12 global interrupt
|
||||
DCD TIM13_IRQHandler ; TIM13 global interrupt
|
||||
DCD TIM14_IRQHandler ; TIM14 global interrupt
|
||||
DCD I3C1_EV_IRQHandler ; I3C1 Event interrupt
|
||||
DCD I3C1_ER_IRQHandler ; I3C1 Error interrupt
|
||||
DCD I2C4_EV_IRQHandler ; I2C4 Event interrupt
|
||||
DCD I2C4_ER_IRQHandler ; I2C4 Error interrupt
|
||||
DCD LPTIM3_IRQHandler ; LPTIM3 global interrupt
|
||||
DCD LPTIM4_IRQHandler ; LPTIM4 global interrupt
|
||||
DCD LPTIM5_IRQHandler ; LPTIM5 global interrupt
|
||||
DCD LPTIM6_IRQHandler ; LPTIM6 global interrupt
|
||||
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler\
|
||||
PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SecureFault_Handler\
|
||||
PROC
|
||||
EXPORT SecureFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler\
|
||||
PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler\
|
||||
PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler\
|
||||
PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK]
|
||||
EXPORT PVD_AVD_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT RTC_S_IRQHandler [WEAK]
|
||||
EXPORT TAMP_IRQHandler [WEAK]
|
||||
EXPORT RAMCFG_IRQHandler [WEAK]
|
||||
EXPORT FLASH_IRQHandler [WEAK]
|
||||
EXPORT FLASH_S_IRQHandler [WEAK]
|
||||
EXPORT GTZC_IRQHandler [WEAK]
|
||||
EXPORT RCC_IRQHandler [WEAK]
|
||||
EXPORT RCC_S_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT EXTI5_IRQHandler [WEAK]
|
||||
EXPORT EXTI6_IRQHandler [WEAK]
|
||||
EXPORT EXTI7_IRQHandler [WEAK]
|
||||
EXPORT EXTI8_IRQHandler [WEAK]
|
||||
EXPORT EXTI9_IRQHandler [WEAK]
|
||||
EXPORT EXTI10_IRQHandler [WEAK]
|
||||
EXPORT EXTI11_IRQHandler [WEAK]
|
||||
EXPORT EXTI12_IRQHandler [WEAK]
|
||||
EXPORT EXTI13_IRQHandler [WEAK]
|
||||
EXPORT EXTI14_IRQHandler [WEAK]
|
||||
EXPORT EXTI15_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel0_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel1_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel2_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel3_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel4_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel5_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel6_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel7_IRQHandler [WEAK]
|
||||
EXPORT IWDG_IRQHandler [WEAK]
|
||||
EXPORT ADC1_IRQHandler [WEAK]
|
||||
EXPORT DAC1_IRQHandler [WEAK]
|
||||
EXPORT FDCAN1_IT0_IRQHandler [WEAK]
|
||||
EXPORT FDCAN1_IT1_IRQHandler [WEAK]
|
||||
EXPORT TIM1_BRK_IRQHandler [WEAK]
|
||||
EXPORT TIM1_UP_IRQHandler [WEAK]
|
||||
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
|
||||
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT TIM3_IRQHandler [WEAK]
|
||||
EXPORT TIM4_IRQHandler [WEAK]
|
||||
EXPORT TIM5_IRQHandler [WEAK]
|
||||
EXPORT TIM6_IRQHandler [WEAK]
|
||||
EXPORT TIM7_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT SPI3_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT USART2_IRQHandler [WEAK]
|
||||
EXPORT USART3_IRQHandler [WEAK]
|
||||
EXPORT UART4_IRQHandler [WEAK]
|
||||
EXPORT UART5_IRQHandler [WEAK]
|
||||
EXPORT LPUART1_IRQHandler [WEAK]
|
||||
EXPORT LPTIM1_IRQHandler [WEAK]
|
||||
EXPORT TIM8_BRK_IRQHandler [WEAK]
|
||||
EXPORT TIM8_UP_IRQHandler [WEAK]
|
||||
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
|
||||
EXPORT TIM8_CC_IRQHandler [WEAK]
|
||||
EXPORT ADC2_IRQHandler [WEAK]
|
||||
EXPORT LPTIM2_IRQHandler [WEAK]
|
||||
EXPORT TIM15_IRQHandler [WEAK]
|
||||
EXPORT TIM16_IRQHandler [WEAK]
|
||||
EXPORT TIM17_IRQHandler [WEAK]
|
||||
EXPORT USB_DRD_FS_IRQHandler [WEAK]
|
||||
EXPORT CRS_IRQHandler [WEAK]
|
||||
EXPORT UCPD1_IRQHandler [WEAK]
|
||||
EXPORT FMC_IRQHandler [WEAK]
|
||||
EXPORT OCTOSPI1_IRQHandler [WEAK]
|
||||
EXPORT SDMMC1_IRQHandler [WEAK]
|
||||
EXPORT I2C3_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C3_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI4_IRQHandler [WEAK]
|
||||
EXPORT SPI5_IRQHandler [WEAK]
|
||||
EXPORT SPI6_IRQHandler [WEAK]
|
||||
EXPORT USART6_IRQHandler [WEAK]
|
||||
EXPORT USART10_IRQHandler [WEAK]
|
||||
EXPORT USART11_IRQHandler [WEAK]
|
||||
EXPORT SAI1_IRQHandler [WEAK]
|
||||
EXPORT SAI2_IRQHandler [WEAK]
|
||||
EXPORT GPDMA2_Channel0_IRQHandler [WEAK]
|
||||
EXPORT GPDMA2_Channel1_IRQHandler [WEAK]
|
||||
EXPORT GPDMA2_Channel2_IRQHandler [WEAK]
|
||||
EXPORT GPDMA2_Channel3_IRQHandler [WEAK]
|
||||
EXPORT GPDMA2_Channel4_IRQHandler [WEAK]
|
||||
EXPORT GPDMA2_Channel5_IRQHandler [WEAK]
|
||||
EXPORT GPDMA2_Channel6_IRQHandler [WEAK]
|
||||
EXPORT GPDMA2_Channel7_IRQHandler [WEAK]
|
||||
EXPORT UART7_IRQHandler [WEAK]
|
||||
EXPORT UART8_IRQHandler [WEAK]
|
||||
EXPORT UART9_IRQHandler [WEAK]
|
||||
EXPORT UART12_IRQHandler [WEAK]
|
||||
EXPORT FPU_IRQHandler [WEAK]
|
||||
EXPORT ICACHE_IRQHandler [WEAK]
|
||||
EXPORT DCACHE1_IRQHandler [WEAK]
|
||||
EXPORT DCMI_PSSI_IRQHandler [WEAK]
|
||||
EXPORT CORDIC_IRQHandler [WEAK]
|
||||
EXPORT FMAC_IRQHandler [WEAK]
|
||||
EXPORT DTS_IRQHandler [WEAK]
|
||||
EXPORT RNG_IRQHandler [WEAK]
|
||||
EXPORT HASH_IRQHandler [WEAK]
|
||||
EXPORT CEC_IRQHandler [WEAK]
|
||||
EXPORT TIM12_IRQHandler [WEAK]
|
||||
EXPORT TIM13_IRQHandler [WEAK]
|
||||
EXPORT TIM14_IRQHandler [WEAK]
|
||||
EXPORT I3C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I3C1_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C4_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C4_ER_IRQHandler [WEAK]
|
||||
EXPORT LPTIM3_IRQHandler [WEAK]
|
||||
EXPORT LPTIM4_IRQHandler [WEAK]
|
||||
EXPORT LPTIM5_IRQHandler [WEAK]
|
||||
EXPORT LPTIM6_IRQHandler [WEAK]
|
||||
|
||||
WWDG_IRQHandler
|
||||
PVD_AVD_IRQHandler
|
||||
RTC_IRQHandler
|
||||
RTC_S_IRQHandler
|
||||
TAMP_IRQHandler
|
||||
RAMCFG_IRQHandler
|
||||
FLASH_IRQHandler
|
||||
FLASH_S_IRQHandler
|
||||
GTZC_IRQHandler
|
||||
RCC_IRQHandler
|
||||
RCC_S_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
EXTI5_IRQHandler
|
||||
EXTI6_IRQHandler
|
||||
EXTI7_IRQHandler
|
||||
EXTI8_IRQHandler
|
||||
EXTI9_IRQHandler
|
||||
EXTI10_IRQHandler
|
||||
EXTI11_IRQHandler
|
||||
EXTI12_IRQHandler
|
||||
EXTI13_IRQHandler
|
||||
EXTI14_IRQHandler
|
||||
EXTI15_IRQHandler
|
||||
GPDMA1_Channel0_IRQHandler
|
||||
GPDMA1_Channel1_IRQHandler
|
||||
GPDMA1_Channel2_IRQHandler
|
||||
GPDMA1_Channel3_IRQHandler
|
||||
GPDMA1_Channel4_IRQHandler
|
||||
GPDMA1_Channel5_IRQHandler
|
||||
GPDMA1_Channel6_IRQHandler
|
||||
GPDMA1_Channel7_IRQHandler
|
||||
IWDG_IRQHandler
|
||||
ADC1_IRQHandler
|
||||
DAC1_IRQHandler
|
||||
FDCAN1_IT0_IRQHandler
|
||||
FDCAN1_IT1_IRQHandler
|
||||
TIM1_BRK_IRQHandler
|
||||
TIM1_UP_IRQHandler
|
||||
TIM1_TRG_COM_IRQHandler
|
||||
TIM1_CC_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
TIM3_IRQHandler
|
||||
TIM4_IRQHandler
|
||||
TIM5_IRQHandler
|
||||
TIM6_IRQHandler
|
||||
TIM7_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
I2C2_EV_IRQHandler
|
||||
I2C2_ER_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
SPI3_IRQHandler
|
||||
USART1_IRQHandler
|
||||
USART2_IRQHandler
|
||||
USART3_IRQHandler
|
||||
UART4_IRQHandler
|
||||
UART5_IRQHandler
|
||||
LPUART1_IRQHandler
|
||||
LPTIM1_IRQHandler
|
||||
TIM8_BRK_IRQHandler
|
||||
TIM8_UP_IRQHandler
|
||||
TIM8_TRG_COM_IRQHandler
|
||||
TIM8_CC_IRQHandler
|
||||
ADC2_IRQHandler
|
||||
LPTIM2_IRQHandler
|
||||
TIM15_IRQHandler
|
||||
TIM16_IRQHandler
|
||||
TIM17_IRQHandler
|
||||
USB_DRD_FS_IRQHandler
|
||||
CRS_IRQHandler
|
||||
UCPD1_IRQHandler
|
||||
FMC_IRQHandler
|
||||
OCTOSPI1_IRQHandler
|
||||
SDMMC1_IRQHandler
|
||||
I2C3_EV_IRQHandler
|
||||
I2C3_ER_IRQHandler
|
||||
SPI4_IRQHandler
|
||||
SPI5_IRQHandler
|
||||
SPI6_IRQHandler
|
||||
USART6_IRQHandler
|
||||
USART10_IRQHandler
|
||||
USART11_IRQHandler
|
||||
SAI1_IRQHandler
|
||||
SAI2_IRQHandler
|
||||
GPDMA2_Channel0_IRQHandler
|
||||
GPDMA2_Channel1_IRQHandler
|
||||
GPDMA2_Channel2_IRQHandler
|
||||
GPDMA2_Channel3_IRQHandler
|
||||
GPDMA2_Channel4_IRQHandler
|
||||
GPDMA2_Channel5_IRQHandler
|
||||
GPDMA2_Channel6_IRQHandler
|
||||
GPDMA2_Channel7_IRQHandler
|
||||
UART7_IRQHandler
|
||||
UART8_IRQHandler
|
||||
UART9_IRQHandler
|
||||
UART12_IRQHandler
|
||||
FPU_IRQHandler
|
||||
ICACHE_IRQHandler
|
||||
DCACHE1_IRQHandler
|
||||
DCMI_PSSI_IRQHandler
|
||||
CORDIC_IRQHandler
|
||||
FMAC_IRQHandler
|
||||
DTS_IRQHandler
|
||||
RNG_IRQHandler
|
||||
HASH_IRQHandler
|
||||
CEC_IRQHandler
|
||||
TIM12_IRQHandler
|
||||
TIM13_IRQHandler
|
||||
TIM14_IRQHandler
|
||||
I3C1_EV_IRQHandler
|
||||
I3C1_ER_IRQHandler
|
||||
I2C4_EV_IRQHandler
|
||||
I2C4_ER_IRQHandler
|
||||
LPTIM3_IRQHandler
|
||||
LPTIM4_IRQHandler
|
||||
LPTIM5_IRQHandler
|
||||
LPTIM6_IRQHandler
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
|
|
@ -0,0 +1,573 @@
|
|||
;*******************************************************************************
|
||||
;* File Name : startup_stm32h563xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : STM32H563xx Non Crypto devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M33 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;*******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* Copyright (c) 2023 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;*******************************************************************************
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD SecureFault_Handler ; Secure Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection Interrupt
|
||||
DCD RTC_IRQHandler ; RTC non-secure interrupt
|
||||
DCD RTC_S_IRQHandler ; RTC secure interrupt
|
||||
DCD TAMP_IRQHandler ; Tamper non-secure interrupt
|
||||
DCD RAMCFG_IRQHandler ; RAMCFG global
|
||||
DCD FLASH_IRQHandler ; FLASH non-secure global interrupt
|
||||
DCD FLASH_S_IRQHandler ; FLASH secure global interrupt
|
||||
DCD GTZC_IRQHandler ; Global TrustZone Controller interrupt
|
||||
DCD RCC_IRQHandler ; RCC non-secure global interrupt
|
||||
DCD RCC_S_IRQHandler ; RCC secure global interrupt
|
||||
DCD EXTI0_IRQHandler ; EXTI Line0 interrupt
|
||||
DCD EXTI1_IRQHandler ; EXTI Line1 interrupt
|
||||
DCD EXTI2_IRQHandler ; EXTI Line2 interrupt
|
||||
DCD EXTI3_IRQHandler ; EXTI Line3 interrupt
|
||||
DCD EXTI4_IRQHandler ; EXTI Line4 interrupt
|
||||
DCD EXTI5_IRQHandler ; EXTI Line5 interrupt
|
||||
DCD EXTI6_IRQHandler ; EXTI Line6 interrupt
|
||||
DCD EXTI7_IRQHandler ; EXTI Line7 interrupt
|
||||
DCD EXTI8_IRQHandler ; EXTI Line8 interrupt
|
||||
DCD EXTI9_IRQHandler ; EXTI Line9 interrupt
|
||||
DCD EXTI10_IRQHandler ; EXTI Line10 interrupt
|
||||
DCD EXTI11_IRQHandler ; EXTI Line11 interrupt
|
||||
DCD EXTI12_IRQHandler ; EXTI Line12 interrupt
|
||||
DCD EXTI13_IRQHandler ; EXTI Line13 interrupt
|
||||
DCD EXTI14_IRQHandler ; EXTI Line14 interrupt
|
||||
DCD EXTI15_IRQHandler ; EXTI Line15 interrupt
|
||||
DCD GPDMA1_Channel0_IRQHandler ; GPDMA1 Channel 0 global interrupt
|
||||
DCD GPDMA1_Channel1_IRQHandler ; GPDMA1 Channel 1 global interrupt
|
||||
DCD GPDMA1_Channel2_IRQHandler ; GPDMA1 Channel 2 global interrupt
|
||||
DCD GPDMA1_Channel3_IRQHandler ; GPDMA1 Channel 3 global interrupt
|
||||
DCD GPDMA1_Channel4_IRQHandler ; GPDMA1 Channel 4 global interrupt
|
||||
DCD GPDMA1_Channel5_IRQHandler ; GPDMA1 Channel 5 global interrupt
|
||||
DCD GPDMA1_Channel6_IRQHandler ; GPDMA1 Channel 6 global interrupt
|
||||
DCD GPDMA1_Channel7_IRQHandler ; GPDMA1 Channel 7 global interrupt
|
||||
DCD IWDG_IRQHandler ; IWDG global interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD ADC1_IRQHandler ; ADC1 global interrupt
|
||||
DCD DAC1_IRQHandler ; DAC1 global interrupt
|
||||
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt 0
|
||||
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt 1
|
||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
|
||||
DCD TIM1_UP_IRQHandler ; TIM1 Update interrupt
|
||||
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation interrupt
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare interrupt
|
||||
DCD TIM2_IRQHandler ; TIM2 global interrupt
|
||||
DCD TIM3_IRQHandler ; TIM3 global interrupt
|
||||
DCD TIM4_IRQHandler ; TIM4 global interrupt
|
||||
DCD TIM5_IRQHandler ; TIM5 global interrupt
|
||||
DCD TIM6_IRQHandler ; TIM6 global interrupt
|
||||
DCD TIM7_IRQHandler ; TIM7 global interrupt
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event interrupt
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error interrupt
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event interrupt
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error interrupt
|
||||
DCD SPI1_IRQHandler ; SPI1 global interrupt
|
||||
DCD SPI2_IRQHandler ; SPI2 global interrupt
|
||||
DCD SPI3_IRQHandler ; SPI3 global interrupt
|
||||
DCD USART1_IRQHandler ; USART1 global interrupt
|
||||
DCD USART2_IRQHandler ; USART2 global interrupt
|
||||
DCD USART3_IRQHandler ; USART3 global interrupt
|
||||
DCD UART4_IRQHandler ; UART4 global interrupt
|
||||
DCD UART5_IRQHandler ; UART5 global interrupt
|
||||
DCD LPUART1_IRQHandler ; LPUART1 global interrupt
|
||||
DCD LPTIM1_IRQHandler ; LPTIM1 global interrupt
|
||||
DCD TIM8_BRK_IRQHandler ; TIM8 Break interrupt
|
||||
DCD TIM8_UP_IRQHandler ; TIM8 Update interrupt
|
||||
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation interrupt
|
||||
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare interrupt
|
||||
DCD ADC2_IRQHandler ; ADC2 global interrupt
|
||||
DCD LPTIM2_IRQHandler ; LPTIM2 global interrupt
|
||||
DCD TIM15_IRQHandler ; TIM15 global interrupt
|
||||
DCD TIM16_IRQHandler ; TIM16 global interrupt
|
||||
DCD TIM17_IRQHandler ; TIM17 global interrupt
|
||||
DCD USB_DRD_FS_IRQHandler ; USB DRD FS global interrupt
|
||||
DCD CRS_IRQHandler ; CRS global interrupt
|
||||
DCD UCPD1_IRQHandler ; UCPD1 global interrupt
|
||||
DCD FMC_IRQHandler ; FMC global interrupt
|
||||
DCD OCTOSPI1_IRQHandler ; OctoSPI1 global interrupt
|
||||
DCD SDMMC1_IRQHandler ; SDMMC1 global interrupt
|
||||
DCD I2C3_EV_IRQHandler ; I2C2 Event interrupt
|
||||
DCD I2C3_ER_IRQHandler ; I2C2 Error interrupt
|
||||
DCD SPI4_IRQHandler ; SPI4 global interrupt
|
||||
DCD SPI5_IRQHandler ; SPI5 global interrupt
|
||||
DCD SPI6_IRQHandler ; SPI6 global interrupt
|
||||
DCD USART6_IRQHandler ; USART6 global interrupt
|
||||
DCD USART10_IRQHandler ; USART10 global interrupt
|
||||
DCD USART11_IRQHandler ; USART11 global interrupt
|
||||
DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt
|
||||
DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt
|
||||
DCD GPDMA2_Channel0_IRQHandler ; GPDMA2 Channel 0 global interrupt
|
||||
DCD GPDMA2_Channel1_IRQHandler ; GPDMA2 Channel 1 global interrupt
|
||||
DCD GPDMA2_Channel2_IRQHandler ; GPDMA2 Channel 2 global interrupt
|
||||
DCD GPDMA2_Channel3_IRQHandler ; GPDMA2 Channel 3 global interrupt
|
||||
DCD GPDMA2_Channel4_IRQHandler ; GPDMA2 Channel 4 global interrupt
|
||||
DCD GPDMA2_Channel5_IRQHandler ; GPDMA2 Channel 5 global interrupt
|
||||
DCD GPDMA2_Channel6_IRQHandler ; GPDMA2 Channel 6 global interrupt
|
||||
DCD GPDMA2_Channel7_IRQHandler ; GPDMA2 Channel 7 global interrupt
|
||||
DCD UART7_IRQHandler ; UART7 global interrupt
|
||||
DCD UART8_IRQHandler ; UART8 global interrupt
|
||||
DCD UART9_IRQHandler ; UART9 global interrupt
|
||||
DCD UART12_IRQHandler ; UART12 global interrupt
|
||||
DCD SDMMC2_IRQHandler ; SDMMC2 global interrupt
|
||||
DCD FPU_IRQHandler ; FPU global interrupt
|
||||
DCD ICACHE_IRQHandler ; Instruction cache global interrupt
|
||||
DCD DCACHE1_IRQHandler ; DCACHE1 global interrupt
|
||||
DCD ETH_IRQHandler ; Ethernet global interrupt
|
||||
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup global interrupt
|
||||
DCD DCMI_PSSI_IRQHandler ; DCMI PSSI global interrupt
|
||||
DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt 0
|
||||
DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt 1
|
||||
DCD CORDIC_IRQHandler ; CORDIC global interrupt
|
||||
DCD FMAC_IRQHandler ; FMAC global interrupt
|
||||
DCD DTS_IRQHandler ; DTS global interrupt
|
||||
DCD RNG_IRQHandler ; RNG global interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD HASH_IRQHandler ; HASH global interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD CEC_IRQHandler ; CEC global interrupt
|
||||
DCD TIM12_IRQHandler ; TIM12 global interrupt
|
||||
DCD TIM13_IRQHandler ; TIM13 global interrupt
|
||||
DCD TIM14_IRQHandler ; TIM14 global interrupt
|
||||
DCD I3C1_EV_IRQHandler ; I3C1 Event interrupt
|
||||
DCD I3C1_ER_IRQHandler ; I3C1 Error interrupt
|
||||
DCD I2C4_EV_IRQHandler ; I2C4 Event interrupt
|
||||
DCD I2C4_ER_IRQHandler ; I2C4 Error interrupt
|
||||
DCD LPTIM3_IRQHandler ; LPTIM3 global interrupt
|
||||
DCD LPTIM4_IRQHandler ; LPTIM4 global interrupt
|
||||
DCD LPTIM5_IRQHandler ; LPTIM5 global interrupt
|
||||
DCD LPTIM6_IRQHandler ; LPTIM6 global interrupt
|
||||
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler\
|
||||
PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SecureFault_Handler\
|
||||
PROC
|
||||
EXPORT SecureFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler\
|
||||
PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler\
|
||||
PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler\
|
||||
PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK]
|
||||
EXPORT PVD_AVD_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT RTC_S_IRQHandler [WEAK]
|
||||
EXPORT TAMP_IRQHandler [WEAK]
|
||||
EXPORT RAMCFG_IRQHandler [WEAK]
|
||||
EXPORT FLASH_IRQHandler [WEAK]
|
||||
EXPORT FLASH_S_IRQHandler [WEAK]
|
||||
EXPORT GTZC_IRQHandler [WEAK]
|
||||
EXPORT RCC_IRQHandler [WEAK]
|
||||
EXPORT RCC_S_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT EXTI5_IRQHandler [WEAK]
|
||||
EXPORT EXTI6_IRQHandler [WEAK]
|
||||
EXPORT EXTI7_IRQHandler [WEAK]
|
||||
EXPORT EXTI8_IRQHandler [WEAK]
|
||||
EXPORT EXTI9_IRQHandler [WEAK]
|
||||
EXPORT EXTI10_IRQHandler [WEAK]
|
||||
EXPORT EXTI11_IRQHandler [WEAK]
|
||||
EXPORT EXTI12_IRQHandler [WEAK]
|
||||
EXPORT EXTI13_IRQHandler [WEAK]
|
||||
EXPORT EXTI14_IRQHandler [WEAK]
|
||||
EXPORT EXTI15_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel0_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel1_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel2_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel3_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel4_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel5_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel6_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel7_IRQHandler [WEAK]
|
||||
EXPORT IWDG_IRQHandler [WEAK]
|
||||
EXPORT ADC1_IRQHandler [WEAK]
|
||||
EXPORT DAC1_IRQHandler [WEAK]
|
||||
EXPORT FDCAN1_IT0_IRQHandler [WEAK]
|
||||
EXPORT FDCAN1_IT1_IRQHandler [WEAK]
|
||||
EXPORT TIM1_BRK_IRQHandler [WEAK]
|
||||
EXPORT TIM1_UP_IRQHandler [WEAK]
|
||||
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
|
||||
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT TIM3_IRQHandler [WEAK]
|
||||
EXPORT TIM4_IRQHandler [WEAK]
|
||||
EXPORT TIM5_IRQHandler [WEAK]
|
||||
EXPORT TIM6_IRQHandler [WEAK]
|
||||
EXPORT TIM7_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT SPI3_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT USART2_IRQHandler [WEAK]
|
||||
EXPORT USART3_IRQHandler [WEAK]
|
||||
EXPORT UART4_IRQHandler [WEAK]
|
||||
EXPORT UART5_IRQHandler [WEAK]
|
||||
EXPORT LPUART1_IRQHandler [WEAK]
|
||||
EXPORT LPTIM1_IRQHandler [WEAK]
|
||||
EXPORT TIM8_BRK_IRQHandler [WEAK]
|
||||
EXPORT TIM8_UP_IRQHandler [WEAK]
|
||||
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
|
||||
EXPORT TIM8_CC_IRQHandler [WEAK]
|
||||
EXPORT ADC2_IRQHandler [WEAK]
|
||||
EXPORT LPTIM2_IRQHandler [WEAK]
|
||||
EXPORT TIM15_IRQHandler [WEAK]
|
||||
EXPORT TIM16_IRQHandler [WEAK]
|
||||
EXPORT TIM17_IRQHandler [WEAK]
|
||||
EXPORT USB_DRD_FS_IRQHandler [WEAK]
|
||||
EXPORT CRS_IRQHandler [WEAK]
|
||||
EXPORT UCPD1_IRQHandler [WEAK]
|
||||
EXPORT FMC_IRQHandler [WEAK]
|
||||
EXPORT OCTOSPI1_IRQHandler [WEAK]
|
||||
EXPORT SDMMC1_IRQHandler [WEAK]
|
||||
EXPORT I2C3_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C3_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI4_IRQHandler [WEAK]
|
||||
EXPORT SPI5_IRQHandler [WEAK]
|
||||
EXPORT SPI6_IRQHandler [WEAK]
|
||||
EXPORT USART6_IRQHandler [WEAK]
|
||||
EXPORT USART10_IRQHandler [WEAK]
|
||||
EXPORT USART11_IRQHandler [WEAK]
|
||||
EXPORT SAI1_IRQHandler [WEAK]
|
||||
EXPORT SAI2_IRQHandler [WEAK]
|
||||
EXPORT GPDMA2_Channel0_IRQHandler [WEAK]
|
||||
EXPORT GPDMA2_Channel1_IRQHandler [WEAK]
|
||||
EXPORT GPDMA2_Channel2_IRQHandler [WEAK]
|
||||
EXPORT GPDMA2_Channel3_IRQHandler [WEAK]
|
||||
EXPORT GPDMA2_Channel4_IRQHandler [WEAK]
|
||||
EXPORT GPDMA2_Channel5_IRQHandler [WEAK]
|
||||
EXPORT GPDMA2_Channel6_IRQHandler [WEAK]
|
||||
EXPORT GPDMA2_Channel7_IRQHandler [WEAK]
|
||||
EXPORT UART7_IRQHandler [WEAK]
|
||||
EXPORT UART8_IRQHandler [WEAK]
|
||||
EXPORT UART9_IRQHandler [WEAK]
|
||||
EXPORT UART12_IRQHandler [WEAK]
|
||||
EXPORT SDMMC2_IRQHandler [WEAK]
|
||||
EXPORT FPU_IRQHandler [WEAK]
|
||||
EXPORT ICACHE_IRQHandler [WEAK]
|
||||
EXPORT DCACHE1_IRQHandler [WEAK]
|
||||
EXPORT ETH_IRQHandler [WEAK]
|
||||
EXPORT ETH_WKUP_IRQHandler [WEAK]
|
||||
EXPORT DCMI_PSSI_IRQHandler [WEAK]
|
||||
EXPORT FDCAN2_IT0_IRQHandler [WEAK]
|
||||
EXPORT FDCAN2_IT1_IRQHandler [WEAK]
|
||||
EXPORT CORDIC_IRQHandler [WEAK]
|
||||
EXPORT FMAC_IRQHandler [WEAK]
|
||||
EXPORT DTS_IRQHandler [WEAK]
|
||||
EXPORT RNG_IRQHandler [WEAK]
|
||||
EXPORT HASH_IRQHandler [WEAK]
|
||||
EXPORT CEC_IRQHandler [WEAK]
|
||||
EXPORT TIM12_IRQHandler [WEAK]
|
||||
EXPORT TIM13_IRQHandler [WEAK]
|
||||
EXPORT TIM14_IRQHandler [WEAK]
|
||||
EXPORT I3C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I3C1_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C4_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C4_ER_IRQHandler [WEAK]
|
||||
EXPORT LPTIM3_IRQHandler [WEAK]
|
||||
EXPORT LPTIM4_IRQHandler [WEAK]
|
||||
EXPORT LPTIM5_IRQHandler [WEAK]
|
||||
EXPORT LPTIM6_IRQHandler [WEAK]
|
||||
|
||||
WWDG_IRQHandler
|
||||
PVD_AVD_IRQHandler
|
||||
RTC_IRQHandler
|
||||
RTC_S_IRQHandler
|
||||
TAMP_IRQHandler
|
||||
RAMCFG_IRQHandler
|
||||
FLASH_IRQHandler
|
||||
FLASH_S_IRQHandler
|
||||
GTZC_IRQHandler
|
||||
RCC_IRQHandler
|
||||
RCC_S_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
EXTI5_IRQHandler
|
||||
EXTI6_IRQHandler
|
||||
EXTI7_IRQHandler
|
||||
EXTI8_IRQHandler
|
||||
EXTI9_IRQHandler
|
||||
EXTI10_IRQHandler
|
||||
EXTI11_IRQHandler
|
||||
EXTI12_IRQHandler
|
||||
EXTI13_IRQHandler
|
||||
EXTI14_IRQHandler
|
||||
EXTI15_IRQHandler
|
||||
GPDMA1_Channel0_IRQHandler
|
||||
GPDMA1_Channel1_IRQHandler
|
||||
GPDMA1_Channel2_IRQHandler
|
||||
GPDMA1_Channel3_IRQHandler
|
||||
GPDMA1_Channel4_IRQHandler
|
||||
GPDMA1_Channel5_IRQHandler
|
||||
GPDMA1_Channel6_IRQHandler
|
||||
GPDMA1_Channel7_IRQHandler
|
||||
IWDG_IRQHandler
|
||||
ADC1_IRQHandler
|
||||
DAC1_IRQHandler
|
||||
FDCAN1_IT0_IRQHandler
|
||||
FDCAN1_IT1_IRQHandler
|
||||
TIM1_BRK_IRQHandler
|
||||
TIM1_UP_IRQHandler
|
||||
TIM1_TRG_COM_IRQHandler
|
||||
TIM1_CC_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
TIM3_IRQHandler
|
||||
TIM4_IRQHandler
|
||||
TIM5_IRQHandler
|
||||
TIM6_IRQHandler
|
||||
TIM7_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
I2C2_EV_IRQHandler
|
||||
I2C2_ER_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
SPI3_IRQHandler
|
||||
USART1_IRQHandler
|
||||
USART2_IRQHandler
|
||||
USART3_IRQHandler
|
||||
UART4_IRQHandler
|
||||
UART5_IRQHandler
|
||||
LPUART1_IRQHandler
|
||||
LPTIM1_IRQHandler
|
||||
TIM8_BRK_IRQHandler
|
||||
TIM8_UP_IRQHandler
|
||||
TIM8_TRG_COM_IRQHandler
|
||||
TIM8_CC_IRQHandler
|
||||
ADC2_IRQHandler
|
||||
LPTIM2_IRQHandler
|
||||
TIM15_IRQHandler
|
||||
TIM16_IRQHandler
|
||||
TIM17_IRQHandler
|
||||
USB_DRD_FS_IRQHandler
|
||||
CRS_IRQHandler
|
||||
UCPD1_IRQHandler
|
||||
FMC_IRQHandler
|
||||
OCTOSPI1_IRQHandler
|
||||
SDMMC1_IRQHandler
|
||||
I2C3_EV_IRQHandler
|
||||
I2C3_ER_IRQHandler
|
||||
SPI4_IRQHandler
|
||||
SPI5_IRQHandler
|
||||
SPI6_IRQHandler
|
||||
USART6_IRQHandler
|
||||
USART10_IRQHandler
|
||||
USART11_IRQHandler
|
||||
SAI1_IRQHandler
|
||||
SAI2_IRQHandler
|
||||
GPDMA2_Channel0_IRQHandler
|
||||
GPDMA2_Channel1_IRQHandler
|
||||
GPDMA2_Channel2_IRQHandler
|
||||
GPDMA2_Channel3_IRQHandler
|
||||
GPDMA2_Channel4_IRQHandler
|
||||
GPDMA2_Channel5_IRQHandler
|
||||
GPDMA2_Channel6_IRQHandler
|
||||
GPDMA2_Channel7_IRQHandler
|
||||
UART7_IRQHandler
|
||||
UART8_IRQHandler
|
||||
UART9_IRQHandler
|
||||
UART12_IRQHandler
|
||||
SDMMC2_IRQHandler
|
||||
FPU_IRQHandler
|
||||
ICACHE_IRQHandler
|
||||
DCACHE1_IRQHandler
|
||||
ETH_IRQHandler
|
||||
ETH_WKUP_IRQHandler
|
||||
DCMI_PSSI_IRQHandler
|
||||
FDCAN2_IT0_IRQHandler
|
||||
FDCAN2_IT1_IRQHandler
|
||||
CORDIC_IRQHandler
|
||||
FMAC_IRQHandler
|
||||
DTS_IRQHandler
|
||||
RNG_IRQHandler
|
||||
HASH_IRQHandler
|
||||
CEC_IRQHandler
|
||||
TIM12_IRQHandler
|
||||
TIM13_IRQHandler
|
||||
TIM14_IRQHandler
|
||||
I3C1_EV_IRQHandler
|
||||
I3C1_ER_IRQHandler
|
||||
I2C4_EV_IRQHandler
|
||||
I2C4_ER_IRQHandler
|
||||
LPTIM3_IRQHandler
|
||||
LPTIM4_IRQHandler
|
||||
LPTIM5_IRQHandler
|
||||
LPTIM6_IRQHandler
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
|
|
@ -0,0 +1,581 @@
|
|||
;*******************************************************************************
|
||||
;* File Name : startup_stm32h573xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : STM32H573xx Crypto devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M33 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;*******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* Copyright (c) 2023 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;*******************************************************************************
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD SecureFault_Handler ; Secure Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection Interrupt
|
||||
DCD RTC_IRQHandler ; RTC non-secure interrupt
|
||||
DCD RTC_S_IRQHandler ; RTC secure interrupt
|
||||
DCD TAMP_IRQHandler ; Tamper non-secure interrupt
|
||||
DCD RAMCFG_IRQHandler ; RAMCFG global
|
||||
DCD FLASH_IRQHandler ; FLASH non-secure global interrupt
|
||||
DCD FLASH_S_IRQHandler ; FLASH secure global interrupt
|
||||
DCD GTZC_IRQHandler ; Global TrustZone Controller interrupt
|
||||
DCD RCC_IRQHandler ; RCC non-secure global interrupt
|
||||
DCD RCC_S_IRQHandler ; RCC secure global interrupt
|
||||
DCD EXTI0_IRQHandler ; EXTI Line0 interrupt
|
||||
DCD EXTI1_IRQHandler ; EXTI Line1 interrupt
|
||||
DCD EXTI2_IRQHandler ; EXTI Line2 interrupt
|
||||
DCD EXTI3_IRQHandler ; EXTI Line3 interrupt
|
||||
DCD EXTI4_IRQHandler ; EXTI Line4 interrupt
|
||||
DCD EXTI5_IRQHandler ; EXTI Line5 interrupt
|
||||
DCD EXTI6_IRQHandler ; EXTI Line6 interrupt
|
||||
DCD EXTI7_IRQHandler ; EXTI Line7 interrupt
|
||||
DCD EXTI8_IRQHandler ; EXTI Line8 interrupt
|
||||
DCD EXTI9_IRQHandler ; EXTI Line9 interrupt
|
||||
DCD EXTI10_IRQHandler ; EXTI Line10 interrupt
|
||||
DCD EXTI11_IRQHandler ; EXTI Line11 interrupt
|
||||
DCD EXTI12_IRQHandler ; EXTI Line12 interrupt
|
||||
DCD EXTI13_IRQHandler ; EXTI Line13 interrupt
|
||||
DCD EXTI14_IRQHandler ; EXTI Line14 interrupt
|
||||
DCD EXTI15_IRQHandler ; EXTI Line15 interrupt
|
||||
DCD GPDMA1_Channel0_IRQHandler ; GPDMA1 Channel 0 global interrupt
|
||||
DCD GPDMA1_Channel1_IRQHandler ; GPDMA1 Channel 1 global interrupt
|
||||
DCD GPDMA1_Channel2_IRQHandler ; GPDMA1 Channel 2 global interrupt
|
||||
DCD GPDMA1_Channel3_IRQHandler ; GPDMA1 Channel 3 global interrupt
|
||||
DCD GPDMA1_Channel4_IRQHandler ; GPDMA1 Channel 4 global interrupt
|
||||
DCD GPDMA1_Channel5_IRQHandler ; GPDMA1 Channel 5 global interrupt
|
||||
DCD GPDMA1_Channel6_IRQHandler ; GPDMA1 Channel 6 global interrupt
|
||||
DCD GPDMA1_Channel7_IRQHandler ; GPDMA1 Channel 7 global interrupt
|
||||
DCD IWDG_IRQHandler ; IWDG global interrupt
|
||||
DCD SAES_IRQHandler ; SAES global interrupt
|
||||
DCD ADC1_IRQHandler ; ADC1 global interrupt
|
||||
DCD DAC1_IRQHandler ; DAC1 global interrupt
|
||||
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt 0
|
||||
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt 1
|
||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
|
||||
DCD TIM1_UP_IRQHandler ; TIM1 Update interrupt
|
||||
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation interrupt
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare interrupt
|
||||
DCD TIM2_IRQHandler ; TIM2 global interrupt
|
||||
DCD TIM3_IRQHandler ; TIM3 global interrupt
|
||||
DCD TIM4_IRQHandler ; TIM4 global interrupt
|
||||
DCD TIM5_IRQHandler ; TIM5 global interrupt
|
||||
DCD TIM6_IRQHandler ; TIM6 global interrupt
|
||||
DCD TIM7_IRQHandler ; TIM7 global interrupt
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event interrupt
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error interrupt
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event interrupt
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error interrupt
|
||||
DCD SPI1_IRQHandler ; SPI1 global interrupt
|
||||
DCD SPI2_IRQHandler ; SPI2 global interrupt
|
||||
DCD SPI3_IRQHandler ; SPI3 global interrupt
|
||||
DCD USART1_IRQHandler ; USART1 global interrupt
|
||||
DCD USART2_IRQHandler ; USART2 global interrupt
|
||||
DCD USART3_IRQHandler ; USART3 global interrupt
|
||||
DCD UART4_IRQHandler ; UART4 global interrupt
|
||||
DCD UART5_IRQHandler ; UART5 global interrupt
|
||||
DCD LPUART1_IRQHandler ; LPUART1 global interrupt
|
||||
DCD LPTIM1_IRQHandler ; LPTIM1 global interrupt
|
||||
DCD TIM8_BRK_IRQHandler ; TIM8 Break interrupt
|
||||
DCD TIM8_UP_IRQHandler ; TIM8 Update interrupt
|
||||
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation interrupt
|
||||
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare interrupt
|
||||
DCD ADC2_IRQHandler ; ADC2 global interrupt
|
||||
DCD LPTIM2_IRQHandler ; LPTIM2 global interrupt
|
||||
DCD TIM15_IRQHandler ; TIM15 global interrupt
|
||||
DCD TIM16_IRQHandler ; TIM16 global interrupt
|
||||
DCD TIM17_IRQHandler ; TIM17 global interrupt
|
||||
DCD USB_DRD_FS_IRQHandler ; USB DRD FS global interrupt
|
||||
DCD CRS_IRQHandler ; CRS global interrupt
|
||||
DCD UCPD1_IRQHandler ; UCPD1 global interrupt
|
||||
DCD FMC_IRQHandler ; FMC global interrupt
|
||||
DCD OCTOSPI1_IRQHandler ; OctoSPI1 global interrupt
|
||||
DCD SDMMC1_IRQHandler ; SDMMC1 global interrupt
|
||||
DCD I2C3_EV_IRQHandler ; I2C2 Event interrupt
|
||||
DCD I2C3_ER_IRQHandler ; I2C2 Error interrupt
|
||||
DCD SPI4_IRQHandler ; SPI4 global interrupt
|
||||
DCD SPI5_IRQHandler ; SPI5 global interrupt
|
||||
DCD SPI6_IRQHandler ; SPI6 global interrupt
|
||||
DCD USART6_IRQHandler ; USART6 global interrupt
|
||||
DCD USART10_IRQHandler ; USART10 global interrupt
|
||||
DCD USART11_IRQHandler ; USART11 global interrupt
|
||||
DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt
|
||||
DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt
|
||||
DCD GPDMA2_Channel0_IRQHandler ; GPDMA2 Channel 0 global interrupt
|
||||
DCD GPDMA2_Channel1_IRQHandler ; GPDMA2 Channel 1 global interrupt
|
||||
DCD GPDMA2_Channel2_IRQHandler ; GPDMA2 Channel 2 global interrupt
|
||||
DCD GPDMA2_Channel3_IRQHandler ; GPDMA2 Channel 3 global interrupt
|
||||
DCD GPDMA2_Channel4_IRQHandler ; GPDMA2 Channel 4 global interrupt
|
||||
DCD GPDMA2_Channel5_IRQHandler ; GPDMA2 Channel 5 global interrupt
|
||||
DCD GPDMA2_Channel6_IRQHandler ; GPDMA2 Channel 6 global interrupt
|
||||
DCD GPDMA2_Channel7_IRQHandler ; GPDMA2 Channel 7 global interrupt
|
||||
DCD UART7_IRQHandler ; UART7 global interrupt
|
||||
DCD UART8_IRQHandler ; UART8 global interrupt
|
||||
DCD UART9_IRQHandler ; UART9 global interrupt
|
||||
DCD UART12_IRQHandler ; UART12 global interrupt
|
||||
DCD SDMMC2_IRQHandler ; SDMMC2 global interrupt
|
||||
DCD FPU_IRQHandler ; FPU global interrupt
|
||||
DCD ICACHE_IRQHandler ; Instruction cache global interrupt
|
||||
DCD DCACHE1_IRQHandler ; DCACHE1 global interrupt
|
||||
DCD ETH_IRQHandler ; Ethernet global interrupt
|
||||
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup global interrupt
|
||||
DCD DCMI_PSSI_IRQHandler ; DCMI PSSI global interrupt
|
||||
DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt 0
|
||||
DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt 1
|
||||
DCD CORDIC_IRQHandler ; CORDIC global interrupt
|
||||
DCD FMAC_IRQHandler ; FMAC global interrupt
|
||||
DCD DTS_IRQHandler ; DTS global interrupt
|
||||
DCD RNG_IRQHandler ; RNG global interrupt
|
||||
DCD OTFDEC1_IRQHandler ; OTFDEC1 global interrupt
|
||||
DCD AES_IRQHandler ; AES global interrupt
|
||||
DCD HASH_IRQHandler ; HASH global interrupt
|
||||
DCD PKA_IRQHandler ; PKA global interrupt
|
||||
DCD CEC_IRQHandler ; CEC global interrupt
|
||||
DCD TIM12_IRQHandler ; TIM12 global interrupt
|
||||
DCD TIM13_IRQHandler ; TIM13 global interrupt
|
||||
DCD TIM14_IRQHandler ; TIM14 global interrupt
|
||||
DCD I3C1_EV_IRQHandler ; I3C1 Event interrupt
|
||||
DCD I3C1_ER_IRQHandler ; I3C1 Error interrupt
|
||||
DCD I2C4_EV_IRQHandler ; I2C4 Event interrupt
|
||||
DCD I2C4_ER_IRQHandler ; I2C4 Error interrupt
|
||||
DCD LPTIM3_IRQHandler ; LPTIM3 global interrupt
|
||||
DCD LPTIM4_IRQHandler ; LPTIM4 global interrupt
|
||||
DCD LPTIM5_IRQHandler ; LPTIM5 global interrupt
|
||||
DCD LPTIM6_IRQHandler ; LPTIM6 global interrupt
|
||||
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler\
|
||||
PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SecureFault_Handler\
|
||||
PROC
|
||||
EXPORT SecureFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler\
|
||||
PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler\
|
||||
PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler\
|
||||
PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK]
|
||||
EXPORT PVD_AVD_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT RTC_S_IRQHandler [WEAK]
|
||||
EXPORT TAMP_IRQHandler [WEAK]
|
||||
EXPORT RAMCFG_IRQHandler [WEAK]
|
||||
EXPORT FLASH_IRQHandler [WEAK]
|
||||
EXPORT FLASH_S_IRQHandler [WEAK]
|
||||
EXPORT GTZC_IRQHandler [WEAK]
|
||||
EXPORT RCC_IRQHandler [WEAK]
|
||||
EXPORT RCC_S_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT EXTI5_IRQHandler [WEAK]
|
||||
EXPORT EXTI6_IRQHandler [WEAK]
|
||||
EXPORT EXTI7_IRQHandler [WEAK]
|
||||
EXPORT EXTI8_IRQHandler [WEAK]
|
||||
EXPORT EXTI9_IRQHandler [WEAK]
|
||||
EXPORT EXTI10_IRQHandler [WEAK]
|
||||
EXPORT EXTI11_IRQHandler [WEAK]
|
||||
EXPORT EXTI12_IRQHandler [WEAK]
|
||||
EXPORT EXTI13_IRQHandler [WEAK]
|
||||
EXPORT EXTI14_IRQHandler [WEAK]
|
||||
EXPORT EXTI15_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel0_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel1_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel2_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel3_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel4_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel5_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel6_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel7_IRQHandler [WEAK]
|
||||
EXPORT IWDG_IRQHandler [WEAK]
|
||||
EXPORT SAES_IRQHandler [WEAK]
|
||||
EXPORT ADC1_IRQHandler [WEAK]
|
||||
EXPORT DAC1_IRQHandler [WEAK]
|
||||
EXPORT FDCAN1_IT0_IRQHandler [WEAK]
|
||||
EXPORT FDCAN1_IT1_IRQHandler [WEAK]
|
||||
EXPORT TIM1_BRK_IRQHandler [WEAK]
|
||||
EXPORT TIM1_UP_IRQHandler [WEAK]
|
||||
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
|
||||
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT TIM3_IRQHandler [WEAK]
|
||||
EXPORT TIM4_IRQHandler [WEAK]
|
||||
EXPORT TIM5_IRQHandler [WEAK]
|
||||
EXPORT TIM6_IRQHandler [WEAK]
|
||||
EXPORT TIM7_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT SPI3_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT USART2_IRQHandler [WEAK]
|
||||
EXPORT USART3_IRQHandler [WEAK]
|
||||
EXPORT UART4_IRQHandler [WEAK]
|
||||
EXPORT UART5_IRQHandler [WEAK]
|
||||
EXPORT LPUART1_IRQHandler [WEAK]
|
||||
EXPORT LPTIM1_IRQHandler [WEAK]
|
||||
EXPORT TIM8_BRK_IRQHandler [WEAK]
|
||||
EXPORT TIM8_UP_IRQHandler [WEAK]
|
||||
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
|
||||
EXPORT TIM8_CC_IRQHandler [WEAK]
|
||||
EXPORT ADC2_IRQHandler [WEAK]
|
||||
EXPORT LPTIM2_IRQHandler [WEAK]
|
||||
EXPORT TIM15_IRQHandler [WEAK]
|
||||
EXPORT TIM16_IRQHandler [WEAK]
|
||||
EXPORT TIM17_IRQHandler [WEAK]
|
||||
EXPORT USB_DRD_FS_IRQHandler [WEAK]
|
||||
EXPORT CRS_IRQHandler [WEAK]
|
||||
EXPORT UCPD1_IRQHandler [WEAK]
|
||||
EXPORT FMC_IRQHandler [WEAK]
|
||||
EXPORT OCTOSPI1_IRQHandler [WEAK]
|
||||
EXPORT SDMMC1_IRQHandler [WEAK]
|
||||
EXPORT I2C3_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C3_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI4_IRQHandler [WEAK]
|
||||
EXPORT SPI5_IRQHandler [WEAK]
|
||||
EXPORT SPI6_IRQHandler [WEAK]
|
||||
EXPORT USART6_IRQHandler [WEAK]
|
||||
EXPORT USART10_IRQHandler [WEAK]
|
||||
EXPORT USART11_IRQHandler [WEAK]
|
||||
EXPORT SAI1_IRQHandler [WEAK]
|
||||
EXPORT SAI2_IRQHandler [WEAK]
|
||||
EXPORT GPDMA2_Channel0_IRQHandler [WEAK]
|
||||
EXPORT GPDMA2_Channel1_IRQHandler [WEAK]
|
||||
EXPORT GPDMA2_Channel2_IRQHandler [WEAK]
|
||||
EXPORT GPDMA2_Channel3_IRQHandler [WEAK]
|
||||
EXPORT GPDMA2_Channel4_IRQHandler [WEAK]
|
||||
EXPORT GPDMA2_Channel5_IRQHandler [WEAK]
|
||||
EXPORT GPDMA2_Channel6_IRQHandler [WEAK]
|
||||
EXPORT GPDMA2_Channel7_IRQHandler [WEAK]
|
||||
EXPORT UART7_IRQHandler [WEAK]
|
||||
EXPORT UART8_IRQHandler [WEAK]
|
||||
EXPORT UART9_IRQHandler [WEAK]
|
||||
EXPORT UART12_IRQHandler [WEAK]
|
||||
EXPORT SDMMC2_IRQHandler [WEAK]
|
||||
EXPORT FPU_IRQHandler [WEAK]
|
||||
EXPORT ICACHE_IRQHandler [WEAK]
|
||||
EXPORT DCACHE1_IRQHandler [WEAK]
|
||||
EXPORT ETH_IRQHandler [WEAK]
|
||||
EXPORT ETH_WKUP_IRQHandler [WEAK]
|
||||
EXPORT DCMI_PSSI_IRQHandler [WEAK]
|
||||
EXPORT FDCAN2_IT0_IRQHandler [WEAK]
|
||||
EXPORT FDCAN2_IT1_IRQHandler [WEAK]
|
||||
EXPORT CORDIC_IRQHandler [WEAK]
|
||||
EXPORT FMAC_IRQHandler [WEAK]
|
||||
EXPORT DTS_IRQHandler [WEAK]
|
||||
EXPORT RNG_IRQHandler [WEAK]
|
||||
EXPORT OTFDEC1_IRQHandler [WEAK]
|
||||
EXPORT AES_IRQHandler [WEAK]
|
||||
EXPORT HASH_IRQHandler [WEAK]
|
||||
EXPORT PKA_IRQHandler [WEAK]
|
||||
EXPORT CEC_IRQHandler [WEAK]
|
||||
EXPORT TIM12_IRQHandler [WEAK]
|
||||
EXPORT TIM13_IRQHandler [WEAK]
|
||||
EXPORT TIM14_IRQHandler [WEAK]
|
||||
EXPORT I3C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I3C1_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C4_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C4_ER_IRQHandler [WEAK]
|
||||
EXPORT LPTIM3_IRQHandler [WEAK]
|
||||
EXPORT LPTIM4_IRQHandler [WEAK]
|
||||
EXPORT LPTIM5_IRQHandler [WEAK]
|
||||
EXPORT LPTIM6_IRQHandler [WEAK]
|
||||
|
||||
WWDG_IRQHandler
|
||||
PVD_AVD_IRQHandler
|
||||
RTC_IRQHandler
|
||||
RTC_S_IRQHandler
|
||||
TAMP_IRQHandler
|
||||
RAMCFG_IRQHandler
|
||||
FLASH_IRQHandler
|
||||
FLASH_S_IRQHandler
|
||||
GTZC_IRQHandler
|
||||
RCC_IRQHandler
|
||||
RCC_S_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
EXTI5_IRQHandler
|
||||
EXTI6_IRQHandler
|
||||
EXTI7_IRQHandler
|
||||
EXTI8_IRQHandler
|
||||
EXTI9_IRQHandler
|
||||
EXTI10_IRQHandler
|
||||
EXTI11_IRQHandler
|
||||
EXTI12_IRQHandler
|
||||
EXTI13_IRQHandler
|
||||
EXTI14_IRQHandler
|
||||
EXTI15_IRQHandler
|
||||
GPDMA1_Channel0_IRQHandler
|
||||
GPDMA1_Channel1_IRQHandler
|
||||
GPDMA1_Channel2_IRQHandler
|
||||
GPDMA1_Channel3_IRQHandler
|
||||
GPDMA1_Channel4_IRQHandler
|
||||
GPDMA1_Channel5_IRQHandler
|
||||
GPDMA1_Channel6_IRQHandler
|
||||
GPDMA1_Channel7_IRQHandler
|
||||
IWDG_IRQHandler
|
||||
SAES_IRQHandler
|
||||
ADC1_IRQHandler
|
||||
DAC1_IRQHandler
|
||||
FDCAN1_IT0_IRQHandler
|
||||
FDCAN1_IT1_IRQHandler
|
||||
TIM1_BRK_IRQHandler
|
||||
TIM1_UP_IRQHandler
|
||||
TIM1_TRG_COM_IRQHandler
|
||||
TIM1_CC_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
TIM3_IRQHandler
|
||||
TIM4_IRQHandler
|
||||
TIM5_IRQHandler
|
||||
TIM6_IRQHandler
|
||||
TIM7_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
I2C2_EV_IRQHandler
|
||||
I2C2_ER_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
SPI3_IRQHandler
|
||||
USART1_IRQHandler
|
||||
USART2_IRQHandler
|
||||
USART3_IRQHandler
|
||||
UART4_IRQHandler
|
||||
UART5_IRQHandler
|
||||
LPUART1_IRQHandler
|
||||
LPTIM1_IRQHandler
|
||||
TIM8_BRK_IRQHandler
|
||||
TIM8_UP_IRQHandler
|
||||
TIM8_TRG_COM_IRQHandler
|
||||
TIM8_CC_IRQHandler
|
||||
ADC2_IRQHandler
|
||||
LPTIM2_IRQHandler
|
||||
TIM15_IRQHandler
|
||||
TIM16_IRQHandler
|
||||
TIM17_IRQHandler
|
||||
USB_DRD_FS_IRQHandler
|
||||
CRS_IRQHandler
|
||||
UCPD1_IRQHandler
|
||||
FMC_IRQHandler
|
||||
OCTOSPI1_IRQHandler
|
||||
SDMMC1_IRQHandler
|
||||
I2C3_EV_IRQHandler
|
||||
I2C3_ER_IRQHandler
|
||||
SPI4_IRQHandler
|
||||
SPI5_IRQHandler
|
||||
SPI6_IRQHandler
|
||||
USART6_IRQHandler
|
||||
USART10_IRQHandler
|
||||
USART11_IRQHandler
|
||||
SAI1_IRQHandler
|
||||
SAI2_IRQHandler
|
||||
GPDMA2_Channel0_IRQHandler
|
||||
GPDMA2_Channel1_IRQHandler
|
||||
GPDMA2_Channel2_IRQHandler
|
||||
GPDMA2_Channel3_IRQHandler
|
||||
GPDMA2_Channel4_IRQHandler
|
||||
GPDMA2_Channel5_IRQHandler
|
||||
GPDMA2_Channel6_IRQHandler
|
||||
GPDMA2_Channel7_IRQHandler
|
||||
UART7_IRQHandler
|
||||
UART8_IRQHandler
|
||||
UART9_IRQHandler
|
||||
UART12_IRQHandler
|
||||
SDMMC2_IRQHandler
|
||||
FPU_IRQHandler
|
||||
ICACHE_IRQHandler
|
||||
DCACHE1_IRQHandler
|
||||
ETH_IRQHandler
|
||||
ETH_WKUP_IRQHandler
|
||||
DCMI_PSSI_IRQHandler
|
||||
FDCAN2_IT0_IRQHandler
|
||||
FDCAN2_IT1_IRQHandler
|
||||
CORDIC_IRQHandler
|
||||
FMAC_IRQHandler
|
||||
DTS_IRQHandler
|
||||
RNG_IRQHandler
|
||||
OTFDEC1_IRQHandler
|
||||
AES_IRQHandler
|
||||
HASH_IRQHandler
|
||||
PKA_IRQHandler
|
||||
CEC_IRQHandler
|
||||
TIM12_IRQHandler
|
||||
TIM13_IRQHandler
|
||||
TIM14_IRQHandler
|
||||
I3C1_EV_IRQHandler
|
||||
I3C1_ER_IRQHandler
|
||||
I2C4_EV_IRQHandler
|
||||
I2C4_ER_IRQHandler
|
||||
LPTIM3_IRQHandler
|
||||
LPTIM4_IRQHandler
|
||||
LPTIM5_IRQHandler
|
||||
LPTIM6_IRQHandler
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
|
|
@ -0,0 +1,547 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file startup_stm32h503xx.s
|
||||
* @author MCD Application Team
|
||||
* @brief STM32H503xx devices vector table GCC toolchain.
|
||||
* This module performs:
|
||||
* - Set the initial SP
|
||||
* - Set the initial PC == Reset_Handler,
|
||||
* - Set the vector table entries with the exceptions ISR address,
|
||||
* - Configure the clock system
|
||||
* - Branches to main in the C library (which eventually
|
||||
* calls main()).
|
||||
* After Reset the Cortex-M33 processor is in Thread mode,
|
||||
* priority is Privileged, and the Stack is set to Main.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m33
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global g_pfnVectors
|
||||
.global Default_Handler
|
||||
|
||||
/* start address for the initialization values of the .data section.
|
||||
defined in linker script */
|
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */
|
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */
|
||||
.word _edata
|
||||
/* start address for the .bss section. defined in linker script */
|
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */
|
||||
.word _ebss
|
||||
|
||||
.equ BootRAM, 0xF1E0F85F
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor first
|
||||
* starts execution following a reset event. Only the absolutely
|
||||
* necessary set is performed, after which the application
|
||||
* supplied main() routine is called.
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
ldr sp, =_estack /* set stack pointer */
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
movs r1, #0
|
||||
b LoopCopyDataInit
|
||||
|
||||
CopyDataInit:
|
||||
ldr r3, =_sidata
|
||||
ldr r3, [r3, r1]
|
||||
str r3, [r0, r1]
|
||||
adds r1, r1, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
ldr r0, =_sdata
|
||||
ldr r3, =_edata
|
||||
adds r2, r0, r1
|
||||
cmp r2, r3
|
||||
bcc CopyDataInit
|
||||
ldr r2, =_sbss
|
||||
b LoopFillZerobss
|
||||
/* Zero fill the bss segment. */
|
||||
FillZerobss:
|
||||
movs r3, #0
|
||||
str r3, [r2], #4
|
||||
|
||||
LoopFillZerobss:
|
||||
ldr r3, = _ebss
|
||||
cmp r2, r3
|
||||
bcc FillZerobss
|
||||
|
||||
/* Call the clock system initialization function.*/
|
||||
bl SystemInit
|
||||
/* Call static constructors */
|
||||
bl __libc_init_array
|
||||
/* Call the application's entry point.*/
|
||||
bl main
|
||||
|
||||
LoopForever:
|
||||
b LoopForever
|
||||
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||
* the system state for examination by a debugger.
|
||||
*
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
/******************************************************************************
|
||||
*
|
||||
* The minimal vector table for a Cortex-M33. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*
|
||||
******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
.word _estack
|
||||
.word Reset_Handler
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word MemManage_Handler
|
||||
.word BusFault_Handler
|
||||
.word UsageFault_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word SVC_Handler
|
||||
.word DebugMon_Handler
|
||||
.word 0
|
||||
.word PendSV_Handler
|
||||
.word SysTick_Handler
|
||||
.word WWDG_IRQHandler
|
||||
.word PVD_AVD_IRQHandler
|
||||
.word RTC_IRQHandler
|
||||
.word 0
|
||||
.word TAMP_IRQHandler
|
||||
.word RAMCFG_IRQHandler
|
||||
.word FLASH_IRQHandler
|
||||
.word 0
|
||||
.word GTZC_IRQHandler
|
||||
.word RCC_IRQHandler
|
||||
.word 0
|
||||
.word EXTI0_IRQHandler
|
||||
.word EXTI1_IRQHandler
|
||||
.word EXTI2_IRQHandler
|
||||
.word EXTI3_IRQHandler
|
||||
.word EXTI4_IRQHandler
|
||||
.word EXTI5_IRQHandler
|
||||
.word EXTI6_IRQHandler
|
||||
.word EXTI7_IRQHandler
|
||||
.word EXTI8_IRQHandler
|
||||
.word EXTI9_IRQHandler
|
||||
.word EXTI10_IRQHandler
|
||||
.word EXTI11_IRQHandler
|
||||
.word EXTI12_IRQHandler
|
||||
.word EXTI13_IRQHandler
|
||||
.word EXTI14_IRQHandler
|
||||
.word EXTI15_IRQHandler
|
||||
.word GPDMA1_Channel0_IRQHandler
|
||||
.word GPDMA1_Channel1_IRQHandler
|
||||
.word GPDMA1_Channel2_IRQHandler
|
||||
.word GPDMA1_Channel3_IRQHandler
|
||||
.word GPDMA1_Channel4_IRQHandler
|
||||
.word GPDMA1_Channel5_IRQHandler
|
||||
.word GPDMA1_Channel6_IRQHandler
|
||||
.word GPDMA1_Channel7_IRQHandler
|
||||
.word IWDG_IRQHandler
|
||||
.word 0
|
||||
.word ADC1_IRQHandler
|
||||
.word DAC1_IRQHandler
|
||||
.word FDCAN1_IT0_IRQHandler
|
||||
.word FDCAN1_IT1_IRQHandler
|
||||
.word TIM1_BRK_IRQHandler
|
||||
.word TIM1_UP_IRQHandler
|
||||
.word TIM1_TRG_COM_IRQHandler
|
||||
.word TIM1_CC_IRQHandler
|
||||
.word TIM2_IRQHandler
|
||||
.word TIM3_IRQHandler
|
||||
.word 0
|
||||
.word 0
|
||||
.word TIM6_IRQHandler
|
||||
.word TIM7_IRQHandler
|
||||
.word I2C1_EV_IRQHandler
|
||||
.word I2C1_ER_IRQHandler
|
||||
.word I2C2_EV_IRQHandler
|
||||
.word I2C2_ER_IRQHandler
|
||||
.word SPI1_IRQHandler
|
||||
.word SPI2_IRQHandler
|
||||
.word SPI3_IRQHandler
|
||||
.word USART1_IRQHandler
|
||||
.word USART2_IRQHandler
|
||||
.word USART3_IRQHandler
|
||||
.word 0
|
||||
.word 0
|
||||
.word LPUART1_IRQHandler
|
||||
.word LPTIM1_IRQHandler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word LPTIM2_IRQHandler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word USB_DRD_FS_IRQHandler
|
||||
.word CRS_IRQHandler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word GPDMA2_Channel0_IRQHandler
|
||||
.word GPDMA2_Channel1_IRQHandler
|
||||
.word GPDMA2_Channel2_IRQHandler
|
||||
.word GPDMA2_Channel3_IRQHandler
|
||||
.word GPDMA2_Channel4_IRQHandler
|
||||
.word GPDMA2_Channel5_IRQHandler
|
||||
.word GPDMA2_Channel6_IRQHandler
|
||||
.word GPDMA2_Channel7_IRQHandler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word FPU_IRQHandler
|
||||
.word ICACHE_IRQHandler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word DTS_IRQHandler
|
||||
.word RNG_IRQHandler
|
||||
.word 0
|
||||
.word 0
|
||||
.word HASH_IRQHandler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word I3C1_EV_IRQHandler
|
||||
.word I3C1_ER_IRQHandler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word I3C2_EV_IRQHandler
|
||||
.word I3C2_ER_IRQHandler
|
||||
.word COMP1_IRQHandler
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDG_IRQHandler
|
||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak PVD_AVD_IRQHandler
|
||||
.thumb_set PVD_AVD_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_IRQHandler
|
||||
.thumb_set RTC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMP_IRQHandler
|
||||
.thumb_set TAMP_IRQHandler,Default_Handler
|
||||
|
||||
.weak RAMCFG_IRQHandler
|
||||
.thumb_set RAMCFG_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak GTZC_IRQHandler
|
||||
.thumb_set GTZC_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_IRQHandler
|
||||
.thumb_set RCC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI5_IRQHandler
|
||||
.thumb_set EXTI5_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI6_IRQHandler
|
||||
.thumb_set EXTI6_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI7_IRQHandler
|
||||
.thumb_set EXTI7_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI8_IRQHandler
|
||||
.thumb_set EXTI8_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI9_IRQHandler
|
||||
.thumb_set EXTI9_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI10_IRQHandler
|
||||
.thumb_set EXTI10_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI11_IRQHandler
|
||||
.thumb_set EXTI11_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI12_IRQHandler
|
||||
.thumb_set EXTI12_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI13_IRQHandler
|
||||
.thumb_set EXTI13_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI14_IRQHandler
|
||||
.thumb_set EXTI14_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI15_IRQHandler
|
||||
.thumb_set EXTI15_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel0_IRQHandler
|
||||
.thumb_set GPDMA1_Channel0_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel1_IRQHandler
|
||||
.thumb_set GPDMA1_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel2_IRQHandler
|
||||
.thumb_set GPDMA1_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel3_IRQHandler
|
||||
.thumb_set GPDMA1_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel4_IRQHandler
|
||||
.thumb_set GPDMA1_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel5_IRQHandler
|
||||
.thumb_set GPDMA1_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel6_IRQHandler
|
||||
.thumb_set GPDMA1_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel7_IRQHandler
|
||||
.thumb_set GPDMA1_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak IWDG_IRQHandler
|
||||
.thumb_set IWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC1_IRQHandler
|
||||
.thumb_set ADC1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DAC1_IRQHandler
|
||||
.thumb_set DAC1_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN1_IT0_IRQHandler
|
||||
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN1_IT1_IRQHandler
|
||||
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_BRK_IRQHandler
|
||||
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_UP_IRQHandler
|
||||
.thumb_set TIM1_UP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_TRG_COM_IRQHandler
|
||||
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_CC_IRQHandler
|
||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM2_IRQHandler
|
||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM3_IRQHandler
|
||||
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM6_IRQHandler
|
||||
.thumb_set TIM6_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM7_IRQHandler
|
||||
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_EV_IRQHandler
|
||||
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_ER_IRQHandler
|
||||
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI3_IRQHandler
|
||||
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART2_IRQHandler
|
||||
.thumb_set USART2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART3_IRQHandler
|
||||
.thumb_set USART3_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPUART1_IRQHandler
|
||||
.thumb_set LPUART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM1_IRQHandler
|
||||
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM2_IRQHandler
|
||||
.thumb_set LPTIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USB_DRD_FS_IRQHandler
|
||||
.thumb_set USB_DRD_FS_IRQHandler,Default_Handler
|
||||
|
||||
.weak CRS_IRQHandler
|
||||
.thumb_set CRS_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA2_Channel0_IRQHandler
|
||||
.thumb_set GPDMA2_Channel0_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA2_Channel1_IRQHandler
|
||||
.thumb_set GPDMA2_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA2_Channel2_IRQHandler
|
||||
.thumb_set GPDMA2_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA2_Channel3_IRQHandler
|
||||
.thumb_set GPDMA2_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA2_Channel4_IRQHandler
|
||||
.thumb_set GPDMA2_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA2_Channel5_IRQHandler
|
||||
.thumb_set GPDMA2_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA2_Channel6_IRQHandler
|
||||
.thumb_set GPDMA2_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA2_Channel7_IRQHandler
|
||||
.thumb_set GPDMA2_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak FPU_IRQHandler
|
||||
.thumb_set FPU_IRQHandler,Default_Handler
|
||||
.weak ICACHE_IRQHandler
|
||||
.thumb_set ICACHE_IRQHandler,Default_Handler
|
||||
|
||||
.weak DTS_IRQHandler
|
||||
.thumb_set DTS_IRQHandler,Default_Handler
|
||||
|
||||
.weak RNG_IRQHandler
|
||||
.thumb_set RNG_IRQHandler,Default_Handler
|
||||
|
||||
.weak HASH_IRQHandler
|
||||
.thumb_set HASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak I3C1_EV_IRQHandler
|
||||
.thumb_set I3C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I3C1_ER_IRQHandler
|
||||
.thumb_set I3C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I3C2_EV_IRQHandler
|
||||
.thumb_set I3C2_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I3C2_ER_IRQHandler
|
||||
.thumb_set I3C2_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak COMP1_IRQHandler
|
||||
.thumb_set COMP1_IRQHandler,Default_Handler
|
||||
|
|
@ -0,0 +1,680 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file startup_stm32h573xx.s
|
||||
* @author MCD Application Team
|
||||
* @brief STM32H563xx devices vector table GCC toolchain.
|
||||
* This module performs:
|
||||
* - Set the initial SP
|
||||
* - Set the initial PC == Reset_Handler,
|
||||
* - Set the vector table entries with the exceptions ISR address,
|
||||
* - Configure the clock system
|
||||
* - Branches to main in the C library (which eventually
|
||||
* calls main()).
|
||||
* After Reset the Cortex-M33 processor is in Thread mode,
|
||||
* priority is Privileged, and the Stack is set to Main.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m33
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global g_pfnVectors
|
||||
.global Default_Handler
|
||||
|
||||
/* start address for the initialization values of the .data section.
|
||||
defined in linker script */
|
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */
|
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */
|
||||
.word _edata
|
||||
/* start address for the .bss section. defined in linker script */
|
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */
|
||||
.word _ebss
|
||||
|
||||
.equ BootRAM, 0xF1E0F85F
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor first
|
||||
* starts execution following a reset event. Only the absolutely
|
||||
* necessary set is performed, after which the application
|
||||
* supplied main() routine is called.
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
ldr sp, =_estack /* set stack pointer */
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
movs r1, #0
|
||||
b LoopCopyDataInit
|
||||
|
||||
CopyDataInit:
|
||||
ldr r3, =_sidata
|
||||
ldr r3, [r3, r1]
|
||||
str r3, [r0, r1]
|
||||
adds r1, r1, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
ldr r0, =_sdata
|
||||
ldr r3, =_edata
|
||||
adds r2, r0, r1
|
||||
cmp r2, r3
|
||||
bcc CopyDataInit
|
||||
ldr r2, =_sbss
|
||||
b LoopFillZerobss
|
||||
/* Zero fill the bss segment. */
|
||||
FillZerobss:
|
||||
movs r3, #0
|
||||
str r3, [r2], #4
|
||||
|
||||
LoopFillZerobss:
|
||||
ldr r3, = _ebss
|
||||
cmp r2, r3
|
||||
bcc FillZerobss
|
||||
|
||||
/* Call the clock system initialization function.*/
|
||||
bl SystemInit
|
||||
/* Call static constructors */
|
||||
bl __libc_init_array
|
||||
/* Call the application's entry point.*/
|
||||
bl main
|
||||
|
||||
LoopForever:
|
||||
b LoopForever
|
||||
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||
* the system state for examination by a debugger.
|
||||
*
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
/******************************************************************************
|
||||
*
|
||||
* The minimal vector table for a Cortex-M33. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*
|
||||
******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
.word _estack
|
||||
.word Reset_Handler
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word MemManage_Handler
|
||||
.word BusFault_Handler
|
||||
.word UsageFault_Handler
|
||||
.word SecureFault_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word SVC_Handler
|
||||
.word DebugMon_Handler
|
||||
.word 0
|
||||
.word PendSV_Handler
|
||||
.word SysTick_Handler
|
||||
.word WWDG_IRQHandler
|
||||
.word PVD_AVD_IRQHandler
|
||||
.word RTC_IRQHandler
|
||||
.word RTC_S_IRQHandler
|
||||
.word TAMP_IRQHandler
|
||||
.word RAMCFG_IRQHandler
|
||||
.word FLASH_IRQHandler
|
||||
.word FLASH_S_IRQHandler
|
||||
.word GTZC_IRQHandler
|
||||
.word RCC_IRQHandler
|
||||
.word RCC_S_IRQHandler
|
||||
.word EXTI0_IRQHandler
|
||||
.word EXTI1_IRQHandler
|
||||
.word EXTI2_IRQHandler
|
||||
.word EXTI3_IRQHandler
|
||||
.word EXTI4_IRQHandler
|
||||
.word EXTI5_IRQHandler
|
||||
.word EXTI6_IRQHandler
|
||||
.word EXTI7_IRQHandler
|
||||
.word EXTI8_IRQHandler
|
||||
.word EXTI9_IRQHandler
|
||||
.word EXTI10_IRQHandler
|
||||
.word EXTI11_IRQHandler
|
||||
.word EXTI12_IRQHandler
|
||||
.word EXTI13_IRQHandler
|
||||
.word EXTI14_IRQHandler
|
||||
.word EXTI15_IRQHandler
|
||||
.word GPDMA1_Channel0_IRQHandler
|
||||
.word GPDMA1_Channel1_IRQHandler
|
||||
.word GPDMA1_Channel2_IRQHandler
|
||||
.word GPDMA1_Channel3_IRQHandler
|
||||
.word GPDMA1_Channel4_IRQHandler
|
||||
.word GPDMA1_Channel5_IRQHandler
|
||||
.word GPDMA1_Channel6_IRQHandler
|
||||
.word GPDMA1_Channel7_IRQHandler
|
||||
.word IWDG_IRQHandler
|
||||
.word 0
|
||||
.word ADC1_IRQHandler
|
||||
.word DAC1_IRQHandler
|
||||
.word FDCAN1_IT0_IRQHandler
|
||||
.word FDCAN1_IT1_IRQHandler
|
||||
.word TIM1_BRK_IRQHandler
|
||||
.word TIM1_UP_IRQHandler
|
||||
.word TIM1_TRG_COM_IRQHandler
|
||||
.word TIM1_CC_IRQHandler
|
||||
.word TIM2_IRQHandler
|
||||
.word TIM3_IRQHandler
|
||||
.word TIM4_IRQHandler
|
||||
.word TIM5_IRQHandler
|
||||
.word TIM6_IRQHandler
|
||||
.word TIM7_IRQHandler
|
||||
.word I2C1_EV_IRQHandler
|
||||
.word I2C1_ER_IRQHandler
|
||||
.word I2C2_EV_IRQHandler
|
||||
.word I2C2_ER_IRQHandler
|
||||
.word SPI1_IRQHandler
|
||||
.word SPI2_IRQHandler
|
||||
.word SPI3_IRQHandler
|
||||
.word USART1_IRQHandler
|
||||
.word USART2_IRQHandler
|
||||
.word USART3_IRQHandler
|
||||
.word UART4_IRQHandler
|
||||
.word UART5_IRQHandler
|
||||
.word LPUART1_IRQHandler
|
||||
.word LPTIM1_IRQHandler
|
||||
.word TIM8_BRK_IRQHandler
|
||||
.word TIM8_UP_IRQHandler
|
||||
.word TIM8_TRG_COM_IRQHandler
|
||||
.word TIM8_CC_IRQHandler
|
||||
.word ADC2_IRQHandler
|
||||
.word LPTIM2_IRQHandler
|
||||
.word TIM15_IRQHandler
|
||||
.word TIM16_IRQHandler
|
||||
.word TIM17_IRQHandler
|
||||
.word USB_DRD_FS_IRQHandler
|
||||
.word CRS_IRQHandler
|
||||
.word UCPD1_IRQHandler
|
||||
.word FMC_IRQHandler
|
||||
.word OCTOSPI1_IRQHandler
|
||||
.word SDMMC1_IRQHandler
|
||||
.word I2C3_EV_IRQHandler
|
||||
.word I2C3_ER_IRQHandler
|
||||
.word SPI4_IRQHandler
|
||||
.word SPI5_IRQHandler
|
||||
.word SPI6_IRQHandler
|
||||
.word USART6_IRQHandler
|
||||
.word USART10_IRQHandler
|
||||
.word USART11_IRQHandler
|
||||
.word SAI1_IRQHandler
|
||||
.word SAI2_IRQHandler
|
||||
.word GPDMA2_Channel0_IRQHandler
|
||||
.word GPDMA2_Channel1_IRQHandler
|
||||
.word GPDMA2_Channel2_IRQHandler
|
||||
.word GPDMA2_Channel3_IRQHandler
|
||||
.word GPDMA2_Channel4_IRQHandler
|
||||
.word GPDMA2_Channel5_IRQHandler
|
||||
.word GPDMA2_Channel6_IRQHandler
|
||||
.word GPDMA2_Channel7_IRQHandler
|
||||
.word UART7_IRQHandler
|
||||
.word UART8_IRQHandler
|
||||
.word UART9_IRQHandler
|
||||
.word UART12_IRQHandler
|
||||
.word 0
|
||||
.word FPU_IRQHandler
|
||||
.word ICACHE_IRQHandler
|
||||
.word DCACHE1_IRQHandler
|
||||
.word 0
|
||||
.word 0
|
||||
.word DCMI_PSSI_IRQHandler
|
||||
.word 0
|
||||
.word 0
|
||||
.word CORDIC_IRQHandler
|
||||
.word FMAC_IRQHandler
|
||||
.word DTS_IRQHandler
|
||||
.word RNG_IRQHandler
|
||||
.word 0
|
||||
.word 0
|
||||
.word HASH_IRQHandler
|
||||
.word 0
|
||||
.word CEC_IRQHandler
|
||||
.word TIM12_IRQHandler
|
||||
.word TIM13_IRQHandler
|
||||
.word TIM14_IRQHandler
|
||||
.word I3C1_EV_IRQHandler
|
||||
.word I3C1_ER_IRQHandler
|
||||
.word I2C4_EV_IRQHandler
|
||||
.word I2C4_ER_IRQHandler
|
||||
.word LPTIM3_IRQHandler
|
||||
.word LPTIM4_IRQHandler
|
||||
.word LPTIM5_IRQHandler
|
||||
.word LPTIM6_IRQHandler
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SecureFault_Handler
|
||||
.thumb_set SecureFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDG_IRQHandler
|
||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak PVD_AVD_IRQHandler
|
||||
.thumb_set PVD_AVD_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_IRQHandler
|
||||
.thumb_set RTC_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_S_IRQHandler
|
||||
.thumb_set RTC_S_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMP_IRQHandler
|
||||
.thumb_set TAMP_IRQHandler,Default_Handler
|
||||
|
||||
.weak RAMCFG_IRQHandler
|
||||
.thumb_set RAMCFG_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_S_IRQHandler
|
||||
.thumb_set FLASH_S_IRQHandler,Default_Handler
|
||||
|
||||
.weak GTZC_IRQHandler
|
||||
.thumb_set GTZC_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_IRQHandler
|
||||
.thumb_set RCC_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_S_IRQHandler
|
||||
.thumb_set RCC_S_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI5_IRQHandler
|
||||
.thumb_set EXTI5_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI6_IRQHandler
|
||||
.thumb_set EXTI6_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI7_IRQHandler
|
||||
.thumb_set EXTI7_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI8_IRQHandler
|
||||
.thumb_set EXTI8_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI9_IRQHandler
|
||||
.thumb_set EXTI9_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI10_IRQHandler
|
||||
.thumb_set EXTI10_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI11_IRQHandler
|
||||
.thumb_set EXTI11_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI12_IRQHandler
|
||||
.thumb_set EXTI12_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI13_IRQHandler
|
||||
.thumb_set EXTI13_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI14_IRQHandler
|
||||
.thumb_set EXTI14_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI15_IRQHandler
|
||||
.thumb_set EXTI15_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel0_IRQHandler
|
||||
.thumb_set GPDMA1_Channel0_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel1_IRQHandler
|
||||
.thumb_set GPDMA1_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel2_IRQHandler
|
||||
.thumb_set GPDMA1_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel3_IRQHandler
|
||||
.thumb_set GPDMA1_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel4_IRQHandler
|
||||
.thumb_set GPDMA1_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel5_IRQHandler
|
||||
.thumb_set GPDMA1_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel6_IRQHandler
|
||||
.thumb_set GPDMA1_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel7_IRQHandler
|
||||
.thumb_set GPDMA1_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak IWDG_IRQHandler
|
||||
.thumb_set IWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC1_IRQHandler
|
||||
.thumb_set ADC1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DAC1_IRQHandler
|
||||
.thumb_set DAC1_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN1_IT0_IRQHandler
|
||||
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN1_IT1_IRQHandler
|
||||
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_BRK_IRQHandler
|
||||
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_UP_IRQHandler
|
||||
.thumb_set TIM1_UP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_TRG_COM_IRQHandler
|
||||
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_CC_IRQHandler
|
||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM2_IRQHandler
|
||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM3_IRQHandler
|
||||
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM4_IRQHandler
|
||||
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM5_IRQHandler
|
||||
.thumb_set TIM5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM6_IRQHandler
|
||||
.thumb_set TIM6_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM7_IRQHandler
|
||||
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_EV_IRQHandler
|
||||
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_ER_IRQHandler
|
||||
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI3_IRQHandler
|
||||
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART2_IRQHandler
|
||||
.thumb_set USART2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART3_IRQHandler
|
||||
.thumb_set USART3_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART4_IRQHandler
|
||||
.thumb_set UART4_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART5_IRQHandler
|
||||
.thumb_set UART5_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPUART1_IRQHandler
|
||||
.thumb_set LPUART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM1_IRQHandler
|
||||
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_BRK_IRQHandler
|
||||
.thumb_set TIM8_BRK_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_UP_IRQHandler
|
||||
.thumb_set TIM8_UP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_TRG_COM_IRQHandler
|
||||
.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_CC_IRQHandler
|
||||
.thumb_set TIM8_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC2_IRQHandler
|
||||
.thumb_set ADC2_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM2_IRQHandler
|
||||
.thumb_set LPTIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM15_IRQHandler
|
||||
.thumb_set TIM15_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM16_IRQHandler
|
||||
.thumb_set TIM16_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM17_IRQHandler
|
||||
.thumb_set TIM17_IRQHandler,Default_Handler
|
||||
|
||||
.weak USB_DRD_FS_IRQHandler
|
||||
.thumb_set USB_DRD_FS_IRQHandler,Default_Handler
|
||||
|
||||
.weak CRS_IRQHandler
|
||||
.thumb_set CRS_IRQHandler,Default_Handler
|
||||
|
||||
.weak UCPD1_IRQHandler
|
||||
.thumb_set UCPD1_IRQHandler,Default_Handler
|
||||
|
||||
.weak FMC_IRQHandler
|
||||
.thumb_set FMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak OCTOSPI1_IRQHandler
|
||||
.thumb_set OCTOSPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDMMC1_IRQHandler
|
||||
.thumb_set SDMMC1_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_EV_IRQHandler
|
||||
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_ER_IRQHandler
|
||||
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI4_IRQHandler
|
||||
.thumb_set SPI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI5_IRQHandler
|
||||
.thumb_set SPI5_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI6_IRQHandler
|
||||
.thumb_set SPI6_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART6_IRQHandler
|
||||
.thumb_set USART6_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART10_IRQHandler
|
||||
.thumb_set USART10_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART11_IRQHandler
|
||||
.thumb_set USART11_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI1_IRQHandler
|
||||
.thumb_set SAI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI2_IRQHandler
|
||||
.thumb_set SAI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA2_Channel0_IRQHandler
|
||||
.thumb_set GPDMA2_Channel0_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA2_Channel1_IRQHandler
|
||||
.thumb_set GPDMA2_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA2_Channel2_IRQHandler
|
||||
.thumb_set GPDMA2_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA2_Channel3_IRQHandler
|
||||
.thumb_set GPDMA2_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA2_Channel4_IRQHandler
|
||||
.thumb_set GPDMA2_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA2_Channel5_IRQHandler
|
||||
.thumb_set GPDMA2_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA2_Channel6_IRQHandler
|
||||
.thumb_set GPDMA2_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA2_Channel7_IRQHandler
|
||||
.thumb_set GPDMA2_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART7_IRQHandler
|
||||
.thumb_set UART7_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART8_IRQHandler
|
||||
.thumb_set UART8_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART9_IRQHandler
|
||||
.thumb_set UART9_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART12_IRQHandler
|
||||
.thumb_set UART12_IRQHandler,Default_Handler
|
||||
|
||||
.weak FPU_IRQHandler
|
||||
.thumb_set FPU_IRQHandler,Default_Handler
|
||||
|
||||
.weak ICACHE_IRQHandler
|
||||
.thumb_set ICACHE_IRQHandler,Default_Handler
|
||||
|
||||
.weak DCACHE1_IRQHandler
|
||||
.thumb_set DCACHE1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DCMI_PSSI_IRQHandler
|
||||
.thumb_set DCMI_PSSI_IRQHandler,Default_Handler
|
||||
|
||||
.weak CORDIC_IRQHandler
|
||||
.thumb_set CORDIC_IRQHandler,Default_Handler
|
||||
|
||||
.weak FMAC_IRQHandler
|
||||
.thumb_set FMAC_IRQHandler,Default_Handler
|
||||
|
||||
.weak DTS_IRQHandler
|
||||
.thumb_set DTS_IRQHandler,Default_Handler
|
||||
|
||||
.weak RNG_IRQHandler
|
||||
.thumb_set RNG_IRQHandler,Default_Handler
|
||||
|
||||
.weak HASH_IRQHandler
|
||||
.thumb_set HASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak CEC_IRQHandler
|
||||
.thumb_set CEC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM12_IRQHandler
|
||||
.thumb_set TIM12_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM13_IRQHandler
|
||||
.thumb_set TIM13_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM14_IRQHandler
|
||||
.thumb_set TIM14_IRQHandler,Default_Handler
|
||||
|
||||
.weak I3C1_EV_IRQHandler
|
||||
.thumb_set I3C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I3C1_ER_IRQHandler
|
||||
.thumb_set I3C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C4_EV_IRQHandler
|
||||
.thumb_set I2C4_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C4_ER_IRQHandler
|
||||
.thumb_set I2C4_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM3_IRQHandler
|
||||
.thumb_set LPTIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM4_IRQHandler
|
||||
.thumb_set LPTIM4_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM5_IRQHandler
|
||||
.thumb_set LPTIM5_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM6_IRQHandler
|
||||
.thumb_set LPTIM6_IRQHandler,Default_Handler
|
||||
|
|
@ -0,0 +1,696 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file startup_stm32h563xx.s
|
||||
* @author MCD Application Team
|
||||
* @brief STM32H563xx devices vector table GCC toolchain.
|
||||
* This module performs:
|
||||
* - Set the initial SP
|
||||
* - Set the initial PC == Reset_Handler,
|
||||
* - Set the vector table entries with the exceptions ISR address,
|
||||
* - Configure the clock system
|
||||
* - Branches to main in the C library (which eventually
|
||||
* calls main()).
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m33
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global g_pfnVectors
|
||||
.global Default_Handler
|
||||
|
||||
/* start address for the initialization values of the .data section.
|
||||
defined in linker script */
|
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */
|
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */
|
||||
.word _edata
|
||||
/* start address for the .bss section. defined in linker script */
|
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */
|
||||
.word _ebss
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor first
|
||||
* starts execution following a reset event. Only the absolutely
|
||||
* necessary set is performed, after which the application
|
||||
* supplied main() routine is called.
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
ldr r0, =_estack
|
||||
mov sp, r0 /* set stack pointer */
|
||||
/* Call the clock system initialization function.*/
|
||||
bl SystemInit
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
ldr r0, =_sdata
|
||||
ldr r1, =_edata
|
||||
ldr r2, =_sidata
|
||||
movs r3, #0
|
||||
b LoopCopyDataInit
|
||||
|
||||
CopyDataInit:
|
||||
ldr r4, [r2, r3]
|
||||
str r4, [r0, r3]
|
||||
adds r3, r3, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
adds r4, r0, r3
|
||||
cmp r4, r1
|
||||
bcc CopyDataInit
|
||||
|
||||
/* Zero fill the bss segment. */
|
||||
ldr r2, =_sbss
|
||||
ldr r4, =_ebss
|
||||
movs r3, #0
|
||||
b LoopFillZerobss
|
||||
|
||||
FillZerobss:
|
||||
str r3, [r2]
|
||||
adds r2, r2, #4
|
||||
|
||||
LoopFillZerobss:
|
||||
cmp r2, r4
|
||||
bcc FillZerobss
|
||||
|
||||
/* Call static constructors */
|
||||
bl __libc_init_array
|
||||
/* Call the application's entry point.*/
|
||||
bl main
|
||||
|
||||
LoopForever:
|
||||
b LoopForever
|
||||
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||
* the system state for examination by a debugger.
|
||||
*
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* The STM32H563xx vector table. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*
|
||||
******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
g_pfnVectors:
|
||||
.word _estack
|
||||
.word Reset_Handler
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word MemManage_Handler
|
||||
.word BusFault_Handler
|
||||
.word UsageFault_Handler
|
||||
.word SecureFault_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word SVC_Handler
|
||||
.word DebugMon_Handler
|
||||
.word 0
|
||||
.word PendSV_Handler
|
||||
.word SysTick_Handler
|
||||
.word WWDG_IRQHandler
|
||||
.word PVD_AVD_IRQHandler
|
||||
.word RTC_IRQHandler
|
||||
.word RTC_S_IRQHandler
|
||||
.word TAMP_IRQHandler
|
||||
.word RAMCFG_IRQHandler
|
||||
.word FLASH_IRQHandler
|
||||
.word FLASH_S_IRQHandler
|
||||
.word GTZC_IRQHandler
|
||||
.word RCC_IRQHandler
|
||||
.word RCC_S_IRQHandler
|
||||
.word EXTI0_IRQHandler
|
||||
.word EXTI1_IRQHandler
|
||||
.word EXTI2_IRQHandler
|
||||
.word EXTI3_IRQHandler
|
||||
.word EXTI4_IRQHandler
|
||||
.word EXTI5_IRQHandler
|
||||
.word EXTI6_IRQHandler
|
||||
.word EXTI7_IRQHandler
|
||||
.word EXTI8_IRQHandler
|
||||
.word EXTI9_IRQHandler
|
||||
.word EXTI10_IRQHandler
|
||||
.word EXTI11_IRQHandler
|
||||
.word EXTI12_IRQHandler
|
||||
.word EXTI13_IRQHandler
|
||||
.word EXTI14_IRQHandler
|
||||
.word EXTI15_IRQHandler
|
||||
.word GPDMA1_Channel0_IRQHandler
|
||||
.word GPDMA1_Channel1_IRQHandler
|
||||
.word GPDMA1_Channel2_IRQHandler
|
||||
.word GPDMA1_Channel3_IRQHandler
|
||||
.word GPDMA1_Channel4_IRQHandler
|
||||
.word GPDMA1_Channel5_IRQHandler
|
||||
.word GPDMA1_Channel6_IRQHandler
|
||||
.word GPDMA1_Channel7_IRQHandler
|
||||
.word IWDG_IRQHandler
|
||||
.word 0
|
||||
.word ADC1_IRQHandler
|
||||
.word DAC1_IRQHandler
|
||||
.word FDCAN1_IT0_IRQHandler
|
||||
.word FDCAN1_IT1_IRQHandler
|
||||
.word TIM1_BRK_IRQHandler
|
||||
.word TIM1_UP_IRQHandler
|
||||
.word TIM1_TRG_COM_IRQHandler
|
||||
.word TIM1_CC_IRQHandler
|
||||
.word TIM2_IRQHandler
|
||||
.word TIM3_IRQHandler
|
||||
.word TIM4_IRQHandler
|
||||
.word TIM5_IRQHandler
|
||||
.word TIM6_IRQHandler
|
||||
.word TIM7_IRQHandler
|
||||
.word I2C1_EV_IRQHandler
|
||||
.word I2C1_ER_IRQHandler
|
||||
.word I2C2_EV_IRQHandler
|
||||
.word I2C2_ER_IRQHandler
|
||||
.word SPI1_IRQHandler
|
||||
.word SPI2_IRQHandler
|
||||
.word SPI3_IRQHandler
|
||||
.word USART1_IRQHandler
|
||||
.word USART2_IRQHandler
|
||||
.word USART3_IRQHandler
|
||||
.word UART4_IRQHandler
|
||||
.word UART5_IRQHandler
|
||||
.word LPUART1_IRQHandler
|
||||
.word LPTIM1_IRQHandler
|
||||
.word TIM8_BRK_IRQHandler
|
||||
.word TIM8_UP_IRQHandler
|
||||
.word TIM8_TRG_COM_IRQHandler
|
||||
.word TIM8_CC_IRQHandler
|
||||
.word ADC2_IRQHandler
|
||||
.word LPTIM2_IRQHandler
|
||||
.word TIM15_IRQHandler
|
||||
.word TIM16_IRQHandler
|
||||
.word TIM17_IRQHandler
|
||||
.word USB_DRD_FS_IRQHandler
|
||||
.word CRS_IRQHandler
|
||||
.word UCPD1_IRQHandler
|
||||
.word FMC_IRQHandler
|
||||
.word OCTOSPI1_IRQHandler
|
||||
.word SDMMC1_IRQHandler
|
||||
.word I2C3_EV_IRQHandler
|
||||
.word I2C3_ER_IRQHandler
|
||||
.word SPI4_IRQHandler
|
||||
.word SPI5_IRQHandler
|
||||
.word SPI6_IRQHandler
|
||||
.word USART6_IRQHandler
|
||||
.word USART10_IRQHandler
|
||||
.word USART11_IRQHandler
|
||||
.word SAI1_IRQHandler
|
||||
.word SAI2_IRQHandler
|
||||
.word GPDMA2_Channel0_IRQHandler
|
||||
.word GPDMA2_Channel1_IRQHandler
|
||||
.word GPDMA2_Channel2_IRQHandler
|
||||
.word GPDMA2_Channel3_IRQHandler
|
||||
.word GPDMA2_Channel4_IRQHandler
|
||||
.word GPDMA2_Channel5_IRQHandler
|
||||
.word GPDMA2_Channel6_IRQHandler
|
||||
.word GPDMA2_Channel7_IRQHandler
|
||||
.word UART7_IRQHandler
|
||||
.word UART8_IRQHandler
|
||||
.word UART9_IRQHandler
|
||||
.word UART12_IRQHandler
|
||||
.word SDMMC2_IRQHandler
|
||||
.word FPU_IRQHandler
|
||||
.word ICACHE_IRQHandler
|
||||
.word DCACHE1_IRQHandler
|
||||
.word ETH_IRQHandler
|
||||
.word ETH_WKUP_IRQHandler
|
||||
.word DCMI_PSSI_IRQHandler
|
||||
.word FDCAN2_IT0_IRQHandler
|
||||
.word FDCAN2_IT1_IRQHandler
|
||||
.word CORDIC_IRQHandler
|
||||
.word FMAC_IRQHandler
|
||||
.word DTS_IRQHandler
|
||||
.word RNG_IRQHandler
|
||||
.word 0
|
||||
.word 0
|
||||
.word HASH_IRQHandler
|
||||
.word 0
|
||||
.word CEC_IRQHandler
|
||||
.word TIM12_IRQHandler
|
||||
.word TIM13_IRQHandler
|
||||
.word TIM14_IRQHandler
|
||||
.word I3C1_EV_IRQHandler
|
||||
.word I3C1_ER_IRQHandler
|
||||
.word I2C4_EV_IRQHandler
|
||||
.word I2C4_ER_IRQHandler
|
||||
.word LPTIM3_IRQHandler
|
||||
.word LPTIM4_IRQHandler
|
||||
.word LPTIM5_IRQHandler
|
||||
.word LPTIM6_IRQHandler
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SecureFault_Handler
|
||||
.thumb_set SecureFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDG_IRQHandler
|
||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak PVD_AVD_IRQHandler
|
||||
.thumb_set PVD_AVD_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_IRQHandler
|
||||
.thumb_set RTC_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_S_IRQHandler
|
||||
.thumb_set RTC_S_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMP_IRQHandler
|
||||
.thumb_set TAMP_IRQHandler,Default_Handler
|
||||
|
||||
.weak RAMCFG_IRQHandler
|
||||
.thumb_set RAMCFG_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_S_IRQHandler
|
||||
.thumb_set FLASH_S_IRQHandler,Default_Handler
|
||||
|
||||
.weak GTZC_IRQHandler
|
||||
.thumb_set GTZC_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_IRQHandler
|
||||
.thumb_set RCC_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_S_IRQHandler
|
||||
.thumb_set RCC_S_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI5_IRQHandler
|
||||
.thumb_set EXTI5_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI6_IRQHandler
|
||||
.thumb_set EXTI6_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI7_IRQHandler
|
||||
.thumb_set EXTI7_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI8_IRQHandler
|
||||
.thumb_set EXTI8_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI9_IRQHandler
|
||||
.thumb_set EXTI9_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI10_IRQHandler
|
||||
.thumb_set EXTI10_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI11_IRQHandler
|
||||
.thumb_set EXTI11_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI12_IRQHandler
|
||||
.thumb_set EXTI12_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI13_IRQHandler
|
||||
.thumb_set EXTI13_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI14_IRQHandler
|
||||
.thumb_set EXTI14_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI15_IRQHandler
|
||||
.thumb_set EXTI15_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel0_IRQHandler
|
||||
.thumb_set GPDMA1_Channel0_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel1_IRQHandler
|
||||
.thumb_set GPDMA1_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel2_IRQHandler
|
||||
.thumb_set GPDMA1_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel3_IRQHandler
|
||||
.thumb_set GPDMA1_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel4_IRQHandler
|
||||
.thumb_set GPDMA1_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel5_IRQHandler
|
||||
.thumb_set GPDMA1_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel6_IRQHandler
|
||||
.thumb_set GPDMA1_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel7_IRQHandler
|
||||
.thumb_set GPDMA1_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak IWDG_IRQHandler
|
||||
.thumb_set IWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC1_IRQHandler
|
||||
.thumb_set ADC1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DAC1_IRQHandler
|
||||
.thumb_set DAC1_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN1_IT0_IRQHandler
|
||||
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN1_IT1_IRQHandler
|
||||
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_BRK_IRQHandler
|
||||
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_UP_IRQHandler
|
||||
.thumb_set TIM1_UP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_TRG_COM_IRQHandler
|
||||
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_CC_IRQHandler
|
||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM2_IRQHandler
|
||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM3_IRQHandler
|
||||
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM4_IRQHandler
|
||||
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM5_IRQHandler
|
||||
.thumb_set TIM5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM6_IRQHandler
|
||||
.thumb_set TIM6_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM7_IRQHandler
|
||||
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_EV_IRQHandler
|
||||
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_ER_IRQHandler
|
||||
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI3_IRQHandler
|
||||
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART2_IRQHandler
|
||||
.thumb_set USART2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART3_IRQHandler
|
||||
.thumb_set USART3_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART4_IRQHandler
|
||||
.thumb_set UART4_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART5_IRQHandler
|
||||
.thumb_set UART5_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPUART1_IRQHandler
|
||||
.thumb_set LPUART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM1_IRQHandler
|
||||
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_BRK_IRQHandler
|
||||
.thumb_set TIM8_BRK_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_UP_IRQHandler
|
||||
.thumb_set TIM8_UP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_TRG_COM_IRQHandler
|
||||
.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_CC_IRQHandler
|
||||
.thumb_set TIM8_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC2_IRQHandler
|
||||
.thumb_set ADC2_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM2_IRQHandler
|
||||
.thumb_set LPTIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM15_IRQHandler
|
||||
.thumb_set TIM15_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM16_IRQHandler
|
||||
.thumb_set TIM16_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM17_IRQHandler
|
||||
.thumb_set TIM17_IRQHandler,Default_Handler
|
||||
|
||||
.weak USB_DRD_FS_IRQHandler
|
||||
.thumb_set USB_DRD_FS_IRQHandler,Default_Handler
|
||||
|
||||
.weak CRS_IRQHandler
|
||||
.thumb_set CRS_IRQHandler,Default_Handler
|
||||
|
||||
.weak UCPD1_IRQHandler
|
||||
.thumb_set UCPD1_IRQHandler,Default_Handler
|
||||
|
||||
.weak FMC_IRQHandler
|
||||
.thumb_set FMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak OCTOSPI1_IRQHandler
|
||||
.thumb_set OCTOSPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDMMC1_IRQHandler
|
||||
.thumb_set SDMMC1_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_EV_IRQHandler
|
||||
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_ER_IRQHandler
|
||||
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI4_IRQHandler
|
||||
.thumb_set SPI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI5_IRQHandler
|
||||
.thumb_set SPI5_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI6_IRQHandler
|
||||
.thumb_set SPI6_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART6_IRQHandler
|
||||
.thumb_set USART6_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART10_IRQHandler
|
||||
.thumb_set USART10_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART11_IRQHandler
|
||||
.thumb_set USART11_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI1_IRQHandler
|
||||
.thumb_set SAI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI2_IRQHandler
|
||||
.thumb_set SAI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA2_Channel0_IRQHandler
|
||||
.thumb_set GPDMA2_Channel0_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA2_Channel1_IRQHandler
|
||||
.thumb_set GPDMA2_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA2_Channel2_IRQHandler
|
||||
.thumb_set GPDMA2_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA2_Channel3_IRQHandler
|
||||
.thumb_set GPDMA2_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA2_Channel4_IRQHandler
|
||||
.thumb_set GPDMA2_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA2_Channel5_IRQHandler
|
||||
.thumb_set GPDMA2_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA2_Channel6_IRQHandler
|
||||
.thumb_set GPDMA2_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA2_Channel7_IRQHandler
|
||||
.thumb_set GPDMA2_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART7_IRQHandler
|
||||
.thumb_set UART7_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART8_IRQHandler
|
||||
.thumb_set UART8_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART9_IRQHandler
|
||||
.thumb_set UART9_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART12_IRQHandler
|
||||
.thumb_set UART12_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDMMC2_IRQHandler
|
||||
.thumb_set SDMMC2_IRQHandler,Default_Handler
|
||||
|
||||
.weak FPU_IRQHandler
|
||||
.thumb_set FPU_IRQHandler,Default_Handler
|
||||
|
||||
.weak ICACHE_IRQHandler
|
||||
.thumb_set ICACHE_IRQHandler,Default_Handler
|
||||
|
||||
.weak DCACHE1_IRQHandler
|
||||
.thumb_set DCACHE1_IRQHandler,Default_Handler
|
||||
|
||||
.weak ETH_IRQHandler
|
||||
.thumb_set ETH_IRQHandler,Default_Handler
|
||||
|
||||
.weak ETH_WKUP_IRQHandler
|
||||
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak DCMI_PSSI_IRQHandler
|
||||
.thumb_set DCMI_PSSI_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN2_IT0_IRQHandler
|
||||
.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN2_IT1_IRQHandler
|
||||
.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CORDIC_IRQHandler
|
||||
.thumb_set CORDIC_IRQHandler,Default_Handler
|
||||
|
||||
.weak FMAC_IRQHandler
|
||||
.thumb_set FMAC_IRQHandler,Default_Handler
|
||||
|
||||
.weak DTS_IRQHandler
|
||||
.thumb_set DTS_IRQHandler,Default_Handler
|
||||
|
||||
.weak RNG_IRQHandler
|
||||
.thumb_set RNG_IRQHandler,Default_Handler
|
||||
|
||||
.weak HASH_IRQHandler
|
||||
.thumb_set HASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak CEC_IRQHandler
|
||||
.thumb_set CEC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM12_IRQHandler
|
||||
.thumb_set TIM12_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM13_IRQHandler
|
||||
.thumb_set TIM13_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM14_IRQHandler
|
||||
.thumb_set TIM14_IRQHandler,Default_Handler
|
||||
|
||||
.weak I3C1_EV_IRQHandler
|
||||
.thumb_set I3C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I3C1_ER_IRQHandler
|
||||
.thumb_set I3C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C4_EV_IRQHandler
|
||||
.thumb_set I2C4_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C4_ER_IRQHandler
|
||||
.thumb_set I2C4_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM3_IRQHandler
|
||||
.thumb_set LPTIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM4_IRQHandler
|
||||
.thumb_set LPTIM4_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM5_IRQHandler
|
||||
.thumb_set LPTIM5_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM6_IRQHandler
|
||||
.thumb_set LPTIM6_IRQHandler,Default_Handler
|
||||
|
|
@ -0,0 +1,712 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file startup_stm32h573xx.s
|
||||
* @author MCD Application Team
|
||||
* @brief STM32H573xx devices vector table GCC toolchain.
|
||||
* This module performs:
|
||||
* - Set the initial SP
|
||||
* - Set the initial PC == Reset_Handler,
|
||||
* - Set the vector table entries with the exceptions ISR address,
|
||||
* - Configure the clock system
|
||||
* - Branches to main in the C library (which eventually
|
||||
* calls main()).
|
||||
* After Reset the Cortex-M33 processor is in Thread mode,
|
||||
* priority is Privileged, and the Stack is set to Main.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m33
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global g_pfnVectors
|
||||
.global Default_Handler
|
||||
|
||||
/* start address for the initialization values of the .data section.
|
||||
defined in linker script */
|
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */
|
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */
|
||||
.word _edata
|
||||
/* start address for the .bss section. defined in linker script */
|
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */
|
||||
.word _ebss
|
||||
|
||||
.equ BootRAM, 0xF1E0F85F
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor first
|
||||
* starts execution following a reset event. Only the absolutely
|
||||
* necessary set is performed, after which the application
|
||||
* supplied main() routine is called.
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
ldr r0, =_estack
|
||||
mov sp, r0 /* set stack pointer */
|
||||
/* Call the clock system initialization function.*/
|
||||
bl SystemInit
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
ldr r0, =_sdata
|
||||
ldr r1, =_edata
|
||||
ldr r2, =_sidata
|
||||
movs r3, #0
|
||||
b LoopCopyDataInit
|
||||
|
||||
CopyDataInit:
|
||||
ldr r4, [r2, r3]
|
||||
str r4, [r0, r3]
|
||||
adds r3, r3, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
adds r4, r0, r3
|
||||
cmp r4, r1
|
||||
bcc CopyDataInit
|
||||
|
||||
/* Zero fill the bss segment. */
|
||||
ldr r2, =_sbss
|
||||
ldr r4, =_ebss
|
||||
movs r3, #0
|
||||
b LoopFillZerobss
|
||||
|
||||
FillZerobss:
|
||||
str r3, [r2]
|
||||
adds r2, r2, #4
|
||||
|
||||
LoopFillZerobss:
|
||||
cmp r2, r4
|
||||
bcc FillZerobss
|
||||
|
||||
/* Call static constructors */
|
||||
bl __libc_init_array
|
||||
/* Call the application's entry point.*/
|
||||
bl main
|
||||
|
||||
LoopForever:
|
||||
b LoopForever
|
||||
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||
* the system state for examination by a debugger.
|
||||
*
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* The STM32H573xx vector table. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*
|
||||
******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
.word _estack
|
||||
.word Reset_Handler
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word MemManage_Handler
|
||||
.word BusFault_Handler
|
||||
.word UsageFault_Handler
|
||||
.word SecureFault_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word SVC_Handler
|
||||
.word DebugMon_Handler
|
||||
.word 0
|
||||
.word PendSV_Handler
|
||||
.word SysTick_Handler
|
||||
.word WWDG_IRQHandler
|
||||
.word PVD_AVD_IRQHandler
|
||||
.word RTC_IRQHandler
|
||||
.word RTC_S_IRQHandler
|
||||
.word TAMP_IRQHandler
|
||||
.word RAMCFG_IRQHandler
|
||||
.word FLASH_IRQHandler
|
||||
.word FLASH_S_IRQHandler
|
||||
.word GTZC_IRQHandler
|
||||
.word RCC_IRQHandler
|
||||
.word RCC_S_IRQHandler
|
||||
.word EXTI0_IRQHandler
|
||||
.word EXTI1_IRQHandler
|
||||
.word EXTI2_IRQHandler
|
||||
.word EXTI3_IRQHandler
|
||||
.word EXTI4_IRQHandler
|
||||
.word EXTI5_IRQHandler
|
||||
.word EXTI6_IRQHandler
|
||||
.word EXTI7_IRQHandler
|
||||
.word EXTI8_IRQHandler
|
||||
.word EXTI9_IRQHandler
|
||||
.word EXTI10_IRQHandler
|
||||
.word EXTI11_IRQHandler
|
||||
.word EXTI12_IRQHandler
|
||||
.word EXTI13_IRQHandler
|
||||
.word EXTI14_IRQHandler
|
||||
.word EXTI15_IRQHandler
|
||||
.word GPDMA1_Channel0_IRQHandler
|
||||
.word GPDMA1_Channel1_IRQHandler
|
||||
.word GPDMA1_Channel2_IRQHandler
|
||||
.word GPDMA1_Channel3_IRQHandler
|
||||
.word GPDMA1_Channel4_IRQHandler
|
||||
.word GPDMA1_Channel5_IRQHandler
|
||||
.word GPDMA1_Channel6_IRQHandler
|
||||
.word GPDMA1_Channel7_IRQHandler
|
||||
.word IWDG_IRQHandler
|
||||
.word SAES_IRQHandler
|
||||
.word ADC1_IRQHandler
|
||||
.word DAC1_IRQHandler
|
||||
.word FDCAN1_IT0_IRQHandler
|
||||
.word FDCAN1_IT1_IRQHandler
|
||||
.word TIM1_BRK_IRQHandler
|
||||
.word TIM1_UP_IRQHandler
|
||||
.word TIM1_TRG_COM_IRQHandler
|
||||
.word TIM1_CC_IRQHandler
|
||||
.word TIM2_IRQHandler
|
||||
.word TIM3_IRQHandler
|
||||
.word TIM4_IRQHandler
|
||||
.word TIM5_IRQHandler
|
||||
.word TIM6_IRQHandler
|
||||
.word TIM7_IRQHandler
|
||||
.word I2C1_EV_IRQHandler
|
||||
.word I2C1_ER_IRQHandler
|
||||
.word I2C2_EV_IRQHandler
|
||||
.word I2C2_ER_IRQHandler
|
||||
.word SPI1_IRQHandler
|
||||
.word SPI2_IRQHandler
|
||||
.word SPI3_IRQHandler
|
||||
.word USART1_IRQHandler
|
||||
.word USART2_IRQHandler
|
||||
.word USART3_IRQHandler
|
||||
.word UART4_IRQHandler
|
||||
.word UART5_IRQHandler
|
||||
.word LPUART1_IRQHandler
|
||||
.word LPTIM1_IRQHandler
|
||||
.word TIM8_BRK_IRQHandler
|
||||
.word TIM8_UP_IRQHandler
|
||||
.word TIM8_TRG_COM_IRQHandler
|
||||
.word TIM8_CC_IRQHandler
|
||||
.word ADC2_IRQHandler
|
||||
.word LPTIM2_IRQHandler
|
||||
.word TIM15_IRQHandler
|
||||
.word TIM16_IRQHandler
|
||||
.word TIM17_IRQHandler
|
||||
.word USB_DRD_FS_IRQHandler
|
||||
.word CRS_IRQHandler
|
||||
.word UCPD1_IRQHandler
|
||||
.word FMC_IRQHandler
|
||||
.word OCTOSPI1_IRQHandler
|
||||
.word SDMMC1_IRQHandler
|
||||
.word I2C3_EV_IRQHandler
|
||||
.word I2C3_ER_IRQHandler
|
||||
.word SPI4_IRQHandler
|
||||
.word SPI5_IRQHandler
|
||||
.word SPI6_IRQHandler
|
||||
.word USART6_IRQHandler
|
||||
.word USART10_IRQHandler
|
||||
.word USART11_IRQHandler
|
||||
.word SAI1_IRQHandler
|
||||
.word SAI2_IRQHandler
|
||||
.word GPDMA2_Channel0_IRQHandler
|
||||
.word GPDMA2_Channel1_IRQHandler
|
||||
.word GPDMA2_Channel2_IRQHandler
|
||||
.word GPDMA2_Channel3_IRQHandler
|
||||
.word GPDMA2_Channel4_IRQHandler
|
||||
.word GPDMA2_Channel5_IRQHandler
|
||||
.word GPDMA2_Channel6_IRQHandler
|
||||
.word GPDMA2_Channel7_IRQHandler
|
||||
.word UART7_IRQHandler
|
||||
.word UART8_IRQHandler
|
||||
.word UART9_IRQHandler
|
||||
.word UART12_IRQHandler
|
||||
.word SDMMC2_IRQHandler
|
||||
.word FPU_IRQHandler
|
||||
.word ICACHE_IRQHandler
|
||||
.word DCACHE1_IRQHandler
|
||||
.word ETH_IRQHandler
|
||||
.word ETH_WKUP_IRQHandler
|
||||
.word DCMI_PSSI_IRQHandler
|
||||
.word FDCAN2_IT0_IRQHandler
|
||||
.word FDCAN2_IT1_IRQHandler
|
||||
.word CORDIC_IRQHandler
|
||||
.word FMAC_IRQHandler
|
||||
.word DTS_IRQHandler
|
||||
.word RNG_IRQHandler
|
||||
.word OTFDEC1_IRQHandler
|
||||
.word AES_IRQHandler
|
||||
.word HASH_IRQHandler
|
||||
.word PKA_IRQHandler
|
||||
.word CEC_IRQHandler
|
||||
.word TIM12_IRQHandler
|
||||
.word TIM13_IRQHandler
|
||||
.word TIM14_IRQHandler
|
||||
.word I3C1_EV_IRQHandler
|
||||
.word I3C1_ER_IRQHandler
|
||||
.word I2C4_EV_IRQHandler
|
||||
.word I2C4_ER_IRQHandler
|
||||
.word LPTIM3_IRQHandler
|
||||
.word LPTIM4_IRQHandler
|
||||
.word LPTIM5_IRQHandler
|
||||
.word LPTIM6_IRQHandler
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SecureFault_Handler
|
||||
.thumb_set SecureFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDG_IRQHandler
|
||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak PVD_AVD_IRQHandler
|
||||
.thumb_set PVD_AVD_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_IRQHandler
|
||||
.thumb_set RTC_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_S_IRQHandler
|
||||
.thumb_set RTC_S_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMP_IRQHandler
|
||||
.thumb_set TAMP_IRQHandler,Default_Handler
|
||||
|
||||
.weak RAMCFG_IRQHandler
|
||||
.thumb_set RAMCFG_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_S_IRQHandler
|
||||
.thumb_set FLASH_S_IRQHandler,Default_Handler
|
||||
|
||||
.weak GTZC_IRQHandler
|
||||
.thumb_set GTZC_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_IRQHandler
|
||||
.thumb_set RCC_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_S_IRQHandler
|
||||
.thumb_set RCC_S_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI5_IRQHandler
|
||||
.thumb_set EXTI5_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI6_IRQHandler
|
||||
.thumb_set EXTI6_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI7_IRQHandler
|
||||
.thumb_set EXTI7_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI8_IRQHandler
|
||||
.thumb_set EXTI8_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI9_IRQHandler
|
||||
.thumb_set EXTI9_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI10_IRQHandler
|
||||
.thumb_set EXTI10_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI11_IRQHandler
|
||||
.thumb_set EXTI11_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI12_IRQHandler
|
||||
.thumb_set EXTI12_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI13_IRQHandler
|
||||
.thumb_set EXTI13_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI14_IRQHandler
|
||||
.thumb_set EXTI14_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI15_IRQHandler
|
||||
.thumb_set EXTI15_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel0_IRQHandler
|
||||
.thumb_set GPDMA1_Channel0_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel1_IRQHandler
|
||||
.thumb_set GPDMA1_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel2_IRQHandler
|
||||
.thumb_set GPDMA1_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel3_IRQHandler
|
||||
.thumb_set GPDMA1_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel4_IRQHandler
|
||||
.thumb_set GPDMA1_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel5_IRQHandler
|
||||
.thumb_set GPDMA1_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel6_IRQHandler
|
||||
.thumb_set GPDMA1_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel7_IRQHandler
|
||||
.thumb_set GPDMA1_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak IWDG_IRQHandler
|
||||
.thumb_set IWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAES_IRQHandler
|
||||
.thumb_set SAES_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC1_IRQHandler
|
||||
.thumb_set ADC1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DAC1_IRQHandler
|
||||
.thumb_set DAC1_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN1_IT0_IRQHandler
|
||||
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN1_IT1_IRQHandler
|
||||
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_BRK_IRQHandler
|
||||
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_UP_IRQHandler
|
||||
.thumb_set TIM1_UP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_TRG_COM_IRQHandler
|
||||
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_CC_IRQHandler
|
||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM2_IRQHandler
|
||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM3_IRQHandler
|
||||
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM4_IRQHandler
|
||||
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM5_IRQHandler
|
||||
.thumb_set TIM5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM6_IRQHandler
|
||||
.thumb_set TIM6_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM7_IRQHandler
|
||||
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_EV_IRQHandler
|
||||
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_ER_IRQHandler
|
||||
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI3_IRQHandler
|
||||
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART2_IRQHandler
|
||||
.thumb_set USART2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART3_IRQHandler
|
||||
.thumb_set USART3_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART4_IRQHandler
|
||||
.thumb_set UART4_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART5_IRQHandler
|
||||
.thumb_set UART5_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPUART1_IRQHandler
|
||||
.thumb_set LPUART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM1_IRQHandler
|
||||
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_BRK_IRQHandler
|
||||
.thumb_set TIM8_BRK_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_UP_IRQHandler
|
||||
.thumb_set TIM8_UP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_TRG_COM_IRQHandler
|
||||
.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_CC_IRQHandler
|
||||
.thumb_set TIM8_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC2_IRQHandler
|
||||
.thumb_set ADC2_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM2_IRQHandler
|
||||
.thumb_set LPTIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM15_IRQHandler
|
||||
.thumb_set TIM15_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM16_IRQHandler
|
||||
.thumb_set TIM16_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM17_IRQHandler
|
||||
.thumb_set TIM17_IRQHandler,Default_Handler
|
||||
|
||||
.weak USB_DRD_FS_IRQHandler
|
||||
.thumb_set USB_DRD_FS_IRQHandler,Default_Handler
|
||||
|
||||
.weak CRS_IRQHandler
|
||||
.thumb_set CRS_IRQHandler,Default_Handler
|
||||
|
||||
.weak UCPD1_IRQHandler
|
||||
.thumb_set UCPD1_IRQHandler,Default_Handler
|
||||
|
||||
.weak FMC_IRQHandler
|
||||
.thumb_set FMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak OCTOSPI1_IRQHandler
|
||||
.thumb_set OCTOSPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDMMC1_IRQHandler
|
||||
.thumb_set SDMMC1_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_EV_IRQHandler
|
||||
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_ER_IRQHandler
|
||||
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI4_IRQHandler
|
||||
.thumb_set SPI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI5_IRQHandler
|
||||
.thumb_set SPI5_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI6_IRQHandler
|
||||
.thumb_set SPI6_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART6_IRQHandler
|
||||
.thumb_set USART6_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART10_IRQHandler
|
||||
.thumb_set USART10_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART11_IRQHandler
|
||||
.thumb_set USART11_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI1_IRQHandler
|
||||
.thumb_set SAI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI2_IRQHandler
|
||||
.thumb_set SAI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA2_Channel0_IRQHandler
|
||||
.thumb_set GPDMA2_Channel0_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA2_Channel1_IRQHandler
|
||||
.thumb_set GPDMA2_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA2_Channel2_IRQHandler
|
||||
.thumb_set GPDMA2_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA2_Channel3_IRQHandler
|
||||
.thumb_set GPDMA2_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA2_Channel4_IRQHandler
|
||||
.thumb_set GPDMA2_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA2_Channel5_IRQHandler
|
||||
.thumb_set GPDMA2_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA2_Channel6_IRQHandler
|
||||
.thumb_set GPDMA2_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA2_Channel7_IRQHandler
|
||||
.thumb_set GPDMA2_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART7_IRQHandler
|
||||
.thumb_set UART7_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART8_IRQHandler
|
||||
.thumb_set UART8_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART9_IRQHandler
|
||||
.thumb_set UART9_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART12_IRQHandler
|
||||
.thumb_set UART12_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDMMC2_IRQHandler
|
||||
.thumb_set SDMMC2_IRQHandler,Default_Handler
|
||||
|
||||
.weak FPU_IRQHandler
|
||||
.thumb_set FPU_IRQHandler,Default_Handler
|
||||
|
||||
.weak ICACHE_IRQHandler
|
||||
.thumb_set ICACHE_IRQHandler,Default_Handler
|
||||
|
||||
.weak DCACHE1_IRQHandler
|
||||
.thumb_set DCACHE1_IRQHandler,Default_Handler
|
||||
|
||||
.weak ETH_IRQHandler
|
||||
.thumb_set ETH_IRQHandler,Default_Handler
|
||||
|
||||
.weak ETH_WKUP_IRQHandler
|
||||
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak DCMI_PSSI_IRQHandler
|
||||
.thumb_set DCMI_PSSI_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN2_IT0_IRQHandler
|
||||
.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN2_IT1_IRQHandler
|
||||
.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CORDIC_IRQHandler
|
||||
.thumb_set CORDIC_IRQHandler,Default_Handler
|
||||
|
||||
.weak FMAC_IRQHandler
|
||||
.thumb_set FMAC_IRQHandler,Default_Handler
|
||||
|
||||
.weak DTS_IRQHandler
|
||||
.thumb_set DTS_IRQHandler,Default_Handler
|
||||
|
||||
.weak RNG_IRQHandler
|
||||
.thumb_set RNG_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTFDEC1_IRQHandler
|
||||
.thumb_set OTFDEC1_IRQHandler,Default_Handler
|
||||
|
||||
.weak AES_IRQHandler
|
||||
.thumb_set AES_IRQHandler,Default_Handler
|
||||
|
||||
.weak HASH_IRQHandler
|
||||
.thumb_set HASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak PKA_IRQHandler
|
||||
.thumb_set PKA_IRQHandler,Default_Handler
|
||||
|
||||
.weak CEC_IRQHandler
|
||||
.thumb_set CEC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM12_IRQHandler
|
||||
.thumb_set TIM12_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM13_IRQHandler
|
||||
.thumb_set TIM13_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM14_IRQHandler
|
||||
.thumb_set TIM14_IRQHandler,Default_Handler
|
||||
|
||||
.weak I3C1_EV_IRQHandler
|
||||
.thumb_set I3C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I3C1_ER_IRQHandler
|
||||
.thumb_set I3C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C4_EV_IRQHandler
|
||||
.thumb_set I2C4_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C4_ER_IRQHandler
|
||||
.thumb_set I2C4_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM3_IRQHandler
|
||||
.thumb_set LPTIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM4_IRQHandler
|
||||
.thumb_set LPTIM4_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM5_IRQHandler
|
||||
.thumb_set LPTIM5_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM6_IRQHandler
|
||||
.thumb_set LPTIM6_IRQHandler,Default_Handler
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x20000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x20003FFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20004000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2009FFFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08100000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08100000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20050000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2009FFFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x0C000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x0C000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0C0FDFFF;
|
||||
define symbol __ICFEDIT_region_ROM_NSC_start__ = 0x0C0FE000;
|
||||
define symbol __ICFEDIT_region_ROM_NSC_end__ = 0x0C0FFFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x30000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x3004FFFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define symbol __region_ROM_NS_start__ = 0x08100000;
|
||||
define symbol __region_ROM_NS_end__ = 0x081FFFFF;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region ROM_NSC_region = mem:[from __ICFEDIT_region_ROM_NSC_start__ to __ICFEDIT_region_ROM_NSC_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define exported symbol __VTOR_TABLE_start = __ICFEDIT_intvec_start__;
|
||||
define exported symbol __VTOR_TABLE_NS_start = __region_ROM_NS_start__;
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in ROM_NSC_region { section Veneer$$CMSE };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x20000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x2004FFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20050000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2009FFFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x20060000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x20050000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x2007FFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20080000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2009FFFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x30000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x30000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x30037FFF;
|
||||
define symbol __ICFEDIT_region_ROM_NSC_start__ = 0x30038000;
|
||||
define symbol __ICFEDIT_region_ROM_NSC_end__ = 0x3003FFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x30040000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x3004FFFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define symbol __region_RAM_NS_start__ = 0x20050000;
|
||||
define symbol __region_RAM_NS_end__ = 0x2009FFFF;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region ROM_NSC_region = mem:[from __ICFEDIT_region_ROM_NSC_start__ to __ICFEDIT_region_ROM_NSC_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define exported symbol __VTOR_TABLE_start = __ICFEDIT_intvec_start__;
|
||||
define exported symbol __VTOR_TABLE_NS_start = __region_RAM_NS_start__;
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in ROM_NSC_region { section Veneer$$CMSE };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2009FFFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08100000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08100000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20050000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2009FFFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x0C000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x0C000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0C0FDFFF;
|
||||
define symbol __ICFEDIT_region_ROM_NSC_start__ = 0x0C0FE000;
|
||||
define symbol __ICFEDIT_region_ROM_NSC_end__ = 0x0C0FFFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x30000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x3004FFFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define symbol __region_ROM_NS_start__ = 0x08100000;
|
||||
define symbol __region_ROM_NS_end__ = 0x081FFFFF;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region ROM_NSC_region = mem:[from __ICFEDIT_region_ROM_NSC_start__ to __ICFEDIT_region_ROM_NSC_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define exported symbol __VTOR_TABLE_start = __ICFEDIT_intvec_start__;
|
||||
define exported symbol __VTOR_TABLE_NS_start = __region_ROM_NS_start__;
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in ROM_NSC_region { section Veneer$$CMSE };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x20000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x2004FFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20050000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2009FFFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x20060000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x20050000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x2007FFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20080000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2009FFFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x30000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x30000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x30037FFF;
|
||||
define symbol __ICFEDIT_region_ROM_NSC_start__ = 0x30038000;
|
||||
define symbol __ICFEDIT_region_ROM_NSC_end__ = 0x3003FFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x30040000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x3004FFFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define symbol __region_RAM_NS_start__ = 0x20050000;
|
||||
define symbol __region_RAM_NS_end__ = 0x2009FFFF;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region ROM_NSC_region = mem:[from __ICFEDIT_region_ROM_NSC_start__ to __ICFEDIT_region_ROM_NSC_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define exported symbol __VTOR_TABLE_start = __ICFEDIT_intvec_start__;
|
||||
define exported symbol __VTOR_TABLE_NS_start = __region_RAM_NS_start__;
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in ROM_NSC_region { section Veneer$$CMSE };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2009FFFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08100000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08100000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20050000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2009FFFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x0C000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x0C000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0C0FDFFF;
|
||||
define symbol __ICFEDIT_region_ROM_NSC_start__ = 0x0C0FE000;
|
||||
define symbol __ICFEDIT_region_ROM_NSC_end__ = 0x0C0FFFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x30000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x3004FFFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define symbol __region_ROM_NS_start__ = 0x08100000;
|
||||
define symbol __region_ROM_NS_end__ = 0x081FFFFF;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region ROM_NSC_region = mem:[from __ICFEDIT_region_ROM_NSC_start__ to __ICFEDIT_region_ROM_NSC_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define exported symbol __VTOR_TABLE_start = __ICFEDIT_intvec_start__;
|
||||
define exported symbol __VTOR_TABLE_NS_start = __region_ROM_NS_start__;
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in ROM_NSC_region { section Veneer$$CMSE };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x20000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x2004FFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20050000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2009FFFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x20060000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x20050000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x2007FFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20080000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2009FFFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x30000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x30000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x30037FFF;
|
||||
define symbol __ICFEDIT_region_ROM_NSC_start__ = 0x30038000;
|
||||
define symbol __ICFEDIT_region_ROM_NSC_end__ = 0x3003FFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x30040000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x3004FFFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define symbol __region_RAM_NS_start__ = 0x20050000;
|
||||
define symbol __region_RAM_NS_end__ = 0x2009FFFF;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region ROM_NSC_region = mem:[from __ICFEDIT_region_ROM_NSC_start__ to __ICFEDIT_region_ROM_NSC_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define exported symbol __VTOR_TABLE_start = __ICFEDIT_intvec_start__;
|
||||
define exported symbol __VTOR_TABLE_NS_start = __region_RAM_NS_start__;
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in ROM_NSC_region { section Veneer$$CMSE };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
|
|
@ -0,0 +1,670 @@
|
|||
;********************************************************************************
|
||||
;* File Name : startup_stm32h503xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : STM32H503xx Non Crypto Devices vector
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == _iar_program_start,
|
||||
;* - Set the vector table entries with the exceptions ISR
|
||||
;* address.
|
||||
;* - Branches to main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M33 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* Copyright (c) 2023 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;*******************************************************************************
|
||||
;
|
||||
;
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
;
|
||||
; Cortex-M version
|
||||
;
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
PUBLIC __Vectors
|
||||
PUBLIC __Vectors_End
|
||||
PUBLIC __Vectors_Size
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection Interrupt
|
||||
DCD RTC_IRQHandler ; RTC non-secure interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD TAMP_IRQHandler ; Tamper non-secure interrupt
|
||||
DCD RAMCFG_IRQHandler ; RAMCFG global
|
||||
DCD FLASH_IRQHandler ; FLASH non-secure global interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD GTZC_IRQHandler ; Global TrustZone Controller interrupt
|
||||
DCD RCC_IRQHandler ; RCC non-secure global interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD EXTI0_IRQHandler ; EXTI Line0 interrupt
|
||||
DCD EXTI1_IRQHandler ; EXTI Line1 interrupt
|
||||
DCD EXTI2_IRQHandler ; EXTI Line2 interrupt
|
||||
DCD EXTI3_IRQHandler ; EXTI Line3 interrupt
|
||||
DCD EXTI4_IRQHandler ; EXTI Line4 interrupt
|
||||
DCD EXTI5_IRQHandler ; EXTI Line5 interrupt
|
||||
DCD EXTI6_IRQHandler ; EXTI Line6 interrupt
|
||||
DCD EXTI7_IRQHandler ; EXTI Line7 interrupt
|
||||
DCD EXTI8_IRQHandler ; EXTI Line8 interrupt
|
||||
DCD EXTI9_IRQHandler ; EXTI Line9 interrupt
|
||||
DCD EXTI10_IRQHandler ; EXTI Line10 interrupt
|
||||
DCD EXTI11_IRQHandler ; EXTI Line11 interrupt
|
||||
DCD EXTI12_IRQHandler ; EXTI Line12 interrupt
|
||||
DCD EXTI13_IRQHandler ; EXTI Line13 interrupt
|
||||
DCD EXTI14_IRQHandler ; EXTI Line14 interrupt
|
||||
DCD EXTI15_IRQHandler ; EXTI Line15 interrupt
|
||||
DCD GPDMA1_Channel0_IRQHandler ; GPDMA1 Channel 0 global interrupt
|
||||
DCD GPDMA1_Channel1_IRQHandler ; GPDMA1 Channel 1 global interrupt
|
||||
DCD GPDMA1_Channel2_IRQHandler ; GPDMA1 Channel 2 global interrupt
|
||||
DCD GPDMA1_Channel3_IRQHandler ; GPDMA1 Channel 3 global interrupt
|
||||
DCD GPDMA1_Channel4_IRQHandler ; GPDMA1 Channel 4 global interrupt
|
||||
DCD GPDMA1_Channel5_IRQHandler ; GPDMA1 Channel 5 global interrupt
|
||||
DCD GPDMA1_Channel6_IRQHandler ; GPDMA1 Channel 6 global interrupt
|
||||
DCD GPDMA1_Channel7_IRQHandler ; GPDMA1 Channel 7 global interrupt
|
||||
DCD IWDG_IRQHandler ; IWDG global interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD ADC1_IRQHandler ; ADC1 global interrupt
|
||||
DCD DAC1_IRQHandler ; DAC1 global interrupt
|
||||
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt 0
|
||||
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt 1
|
||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
|
||||
DCD TIM1_UP_IRQHandler ; TIM1 Update interrupt
|
||||
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation interrupt
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare interrupt
|
||||
DCD TIM2_IRQHandler ; TIM2 global interrupt
|
||||
DCD TIM3_IRQHandler ; TIM3 global interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM6_IRQHandler ; TIM6 global interrupt
|
||||
DCD TIM7_IRQHandler ; TIM7 global interrupt
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event interrupt
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error interrupt
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event interrupt
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error interrupt
|
||||
DCD SPI1_IRQHandler ; SPI1 global interrupt
|
||||
DCD SPI2_IRQHandler ; SPI2 global interrupt
|
||||
DCD SPI3_IRQHandler ; SPI3 global interrupt
|
||||
DCD USART1_IRQHandler ; USART1 global interrupt
|
||||
DCD USART2_IRQHandler ; USART2 global interrupt
|
||||
DCD USART3_IRQHandler ; USART3 global interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD LPUART1_IRQHandler ; LPUART1 global interrupt
|
||||
DCD LPTIM1_IRQHandler ; LPTIM1 global interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD LPTIM2_IRQHandler ; LPTIM2 global interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD USB_DRD_FS_IRQHandler ; USB DRD FS global interrupt
|
||||
DCD CRS_IRQHandler ; CRS global interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD GPDMA2_Channel0_IRQHandler ; GPDMA2 Channel 0 global interrupt
|
||||
DCD GPDMA2_Channel1_IRQHandler ; GPDMA2 Channel 1 global interrupt
|
||||
DCD GPDMA2_Channel2_IRQHandler ; GPDMA2 Channel 2 global interrupt
|
||||
DCD GPDMA2_Channel3_IRQHandler ; GPDMA2 Channel 3 global interrupt
|
||||
DCD GPDMA2_Channel4_IRQHandler ; GPDMA2 Channel 4 global interrupt
|
||||
DCD GPDMA2_Channel5_IRQHandler ; GPDMA2 Channel 5 global interrupt
|
||||
DCD GPDMA2_Channel6_IRQHandler ; GPDMA2 Channel 6 global interrupt
|
||||
DCD GPDMA2_Channel7_IRQHandler ; GPDMA2 Channel 7 global interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD FPU_IRQHandler ; FPU global interrupt
|
||||
DCD ICACHE_IRQHandler ; Instruction cache global interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD DTS_IRQHandler ; DTS global interrupt
|
||||
DCD RNG_IRQHandler ; RNG global interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD HASH_IRQHandler ; HASH global interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD I3C1_EV_IRQHandler ; I3C1 Event interrupt
|
||||
DCD I3C1_ER_IRQHandler ; I3C1 Error interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD I3C2_EV_IRQHandler ; I3C2 Event interrupt
|
||||
DCD I3C2_ER_IRQHandler ; I3C2 Error interrupt
|
||||
DCD COMP1_IRQHandler ; COMP1 global interrupt
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors EQU __vector_table
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||
Reset_Handler
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
NMI_Handler
|
||||
B NMI_Handler
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HardFault_Handler
|
||||
B HardFault_Handler
|
||||
|
||||
PUBWEAK MemManage_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
MemManage_Handler
|
||||
B MemManage_Handler
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
BusFault_Handler
|
||||
B BusFault_Handler
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UsageFault_Handler
|
||||
B UsageFault_Handler
|
||||
|
||||
PUBWEAK SecureFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SecureFault_Handler
|
||||
B SecureFault_Handler
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SVC_Handler
|
||||
B SVC_Handler
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DebugMon_Handler
|
||||
B DebugMon_Handler
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PendSV_Handler
|
||||
B PendSV_Handler
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SysTick_Handler
|
||||
B SysTick_Handler
|
||||
|
||||
PUBWEAK WWDG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
WWDG_IRQHandler
|
||||
B WWDG_IRQHandler
|
||||
|
||||
PUBWEAK PVD_AVD_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PVD_AVD_IRQHandler
|
||||
B PVD_AVD_IRQHandler
|
||||
|
||||
PUBWEAK RTC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_IRQHandler
|
||||
B RTC_IRQHandler
|
||||
|
||||
PUBWEAK TAMP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TAMP_IRQHandler
|
||||
B TAMP_IRQHandler
|
||||
|
||||
PUBWEAK RAMCFG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RAMCFG_IRQHandler
|
||||
B RAMCFG_IRQHandler
|
||||
|
||||
PUBWEAK FLASH_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FLASH_IRQHandler
|
||||
B FLASH_IRQHandler
|
||||
|
||||
PUBWEAK GTZC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GTZC_IRQHandler
|
||||
B GTZC_IRQHandler
|
||||
|
||||
PUBWEAK RCC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RCC_IRQHandler
|
||||
B RCC_IRQHandler
|
||||
|
||||
PUBWEAK EXTI0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI0_IRQHandler
|
||||
B EXTI0_IRQHandler
|
||||
|
||||
PUBWEAK EXTI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI1_IRQHandler
|
||||
B EXTI1_IRQHandler
|
||||
|
||||
PUBWEAK EXTI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI2_IRQHandler
|
||||
B EXTI2_IRQHandler
|
||||
|
||||
PUBWEAK EXTI3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI3_IRQHandler
|
||||
B EXTI3_IRQHandler
|
||||
|
||||
PUBWEAK EXTI4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI4_IRQHandler
|
||||
B EXTI4_IRQHandler
|
||||
|
||||
PUBWEAK EXTI5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI5_IRQHandler
|
||||
B EXTI5_IRQHandler
|
||||
|
||||
PUBWEAK EXTI6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI6_IRQHandler
|
||||
B EXTI6_IRQHandler
|
||||
|
||||
PUBWEAK EXTI7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI7_IRQHandler
|
||||
B EXTI7_IRQHandler
|
||||
|
||||
PUBWEAK EXTI8_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI8_IRQHandler
|
||||
B EXTI8_IRQHandler
|
||||
|
||||
PUBWEAK EXTI9_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI9_IRQHandler
|
||||
B EXTI9_IRQHandler
|
||||
|
||||
PUBWEAK EXTI10_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI10_IRQHandler
|
||||
B EXTI10_IRQHandler
|
||||
|
||||
PUBWEAK EXTI11_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI11_IRQHandler
|
||||
B EXTI11_IRQHandler
|
||||
|
||||
PUBWEAK EXTI12_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI12_IRQHandler
|
||||
B EXTI12_IRQHandler
|
||||
|
||||
PUBWEAK EXTI13_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI13_IRQHandler
|
||||
B EXTI13_IRQHandler
|
||||
|
||||
PUBWEAK EXTI14_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI14_IRQHandler
|
||||
B EXTI14_IRQHandler
|
||||
|
||||
PUBWEAK EXTI15_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI15_IRQHandler
|
||||
B EXTI15_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA1_Channel0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA1_Channel0_IRQHandler
|
||||
B GPDMA1_Channel0_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA1_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA1_Channel1_IRQHandler
|
||||
B GPDMA1_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA1_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA1_Channel2_IRQHandler
|
||||
B GPDMA1_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA1_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA1_Channel3_IRQHandler
|
||||
B GPDMA1_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA1_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA1_Channel4_IRQHandler
|
||||
B GPDMA1_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA1_Channel5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA1_Channel5_IRQHandler
|
||||
B GPDMA1_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA1_Channel6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA1_Channel6_IRQHandler
|
||||
B GPDMA1_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA1_Channel7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA1_Channel7_IRQHandler
|
||||
B GPDMA1_Channel7_IRQHandler
|
||||
|
||||
PUBWEAK IWDG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IWDG_IRQHandler
|
||||
B IWDG_IRQHandler
|
||||
|
||||
PUBWEAK ADC1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ADC1_IRQHandler
|
||||
B ADC1_IRQHandler
|
||||
|
||||
PUBWEAK DAC1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DAC1_IRQHandler
|
||||
B DAC1_IRQHandler
|
||||
|
||||
PUBWEAK FDCAN1_IT0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FDCAN1_IT0_IRQHandler
|
||||
B FDCAN1_IT0_IRQHandler
|
||||
|
||||
PUBWEAK FDCAN1_IT1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FDCAN1_IT1_IRQHandler
|
||||
B FDCAN1_IT1_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_BRK_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_BRK_IRQHandler
|
||||
B TIM1_BRK_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_UP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_UP_IRQHandler
|
||||
B TIM1_UP_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_TRG_COM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_TRG_COM_IRQHandler
|
||||
B TIM1_TRG_COM_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_CC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_CC_IRQHandler
|
||||
B TIM1_CC_IRQHandler
|
||||
|
||||
PUBWEAK TIM2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM2_IRQHandler
|
||||
B TIM2_IRQHandler
|
||||
|
||||
PUBWEAK TIM3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM3_IRQHandler
|
||||
B TIM3_IRQHandler
|
||||
|
||||
PUBWEAK TIM6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM6_IRQHandler
|
||||
B TIM6_IRQHandler
|
||||
|
||||
PUBWEAK TIM7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM7_IRQHandler
|
||||
B TIM7_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_EV_IRQHandler
|
||||
B I2C1_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_ER_IRQHandler
|
||||
B I2C1_ER_IRQHandler
|
||||
|
||||
PUBWEAK I2C2_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C2_EV_IRQHandler
|
||||
B I2C2_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C2_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C2_ER_IRQHandler
|
||||
B I2C2_ER_IRQHandler
|
||||
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI1_IRQHandler
|
||||
B SPI1_IRQHandler
|
||||
|
||||
PUBWEAK SPI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI2_IRQHandler
|
||||
B SPI2_IRQHandler
|
||||
|
||||
PUBWEAK SPI3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI3_IRQHandler
|
||||
B SPI3_IRQHandler
|
||||
|
||||
PUBWEAK USART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART1_IRQHandler
|
||||
B USART1_IRQHandler
|
||||
|
||||
PUBWEAK USART2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART2_IRQHandler
|
||||
B USART2_IRQHandler
|
||||
|
||||
PUBWEAK USART3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART3_IRQHandler
|
||||
B USART3_IRQHandler
|
||||
|
||||
PUBWEAK LPUART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPUART1_IRQHandler
|
||||
B LPUART1_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM1_IRQHandler
|
||||
B LPTIM1_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM2_IRQHandler
|
||||
B LPTIM2_IRQHandler
|
||||
|
||||
PUBWEAK USB_DRD_FS_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USB_DRD_FS_IRQHandler
|
||||
B USB_DRD_FS_IRQHandler
|
||||
|
||||
PUBWEAK CRS_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CRS_IRQHandler
|
||||
B CRS_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA2_Channel0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA2_Channel0_IRQHandler
|
||||
B GPDMA2_Channel0_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA2_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA2_Channel1_IRQHandler
|
||||
B GPDMA2_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA2_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA2_Channel2_IRQHandler
|
||||
B GPDMA2_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA2_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA2_Channel3_IRQHandler
|
||||
B GPDMA2_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA2_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA2_Channel4_IRQHandler
|
||||
B GPDMA2_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA2_Channel5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA2_Channel5_IRQHandler
|
||||
B GPDMA2_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA2_Channel6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA2_Channel6_IRQHandler
|
||||
B GPDMA2_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA2_Channel7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA2_Channel7_IRQHandler
|
||||
B GPDMA2_Channel7_IRQHandler
|
||||
|
||||
PUBWEAK COMP1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
COMP1_IRQHandler
|
||||
B COMP1_IRQHandler
|
||||
|
||||
PUBWEAK I3C2_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I3C2_EV_IRQHandler
|
||||
B I3C2_EV_IRQHandler
|
||||
|
||||
PUBWEAK I3C2_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I3C2_ER_IRQHandler
|
||||
B I3C2_ER_IRQHandler
|
||||
|
||||
PUBWEAK FPU_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FPU_IRQHandler
|
||||
B FPU_IRQHandler
|
||||
|
||||
PUBWEAK ICACHE_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ICACHE_IRQHandler
|
||||
B ICACHE_IRQHandler
|
||||
|
||||
PUBWEAK DTS_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DTS_IRQHandler
|
||||
B DTS_IRQHandler
|
||||
|
||||
PUBWEAK RNG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RNG_IRQHandler
|
||||
B RNG_IRQHandler
|
||||
|
||||
PUBWEAK HASH_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HASH_IRQHandler
|
||||
B HASH_IRQHandler
|
||||
|
||||
PUBWEAK I3C1_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I3C1_EV_IRQHandler
|
||||
B I3C1_EV_IRQHandler
|
||||
|
||||
PUBWEAK I3C1_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I3C1_ER_IRQHandler
|
||||
B I3C1_ER_IRQHandler
|
||||
|
||||
END
|
||||
|
|
@ -0,0 +1,887 @@
|
|||
;********************************************************************************
|
||||
;* File Name : startup_stm32h562xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : STM32H562xx Non Crypto Devices vector
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == _iar_program_start,
|
||||
;* - Set the vector table entries with the exceptions ISR
|
||||
;* address.
|
||||
;* - Branches to main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M33 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* Copyright (c) 2023 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;*******************************************************************************
|
||||
;
|
||||
;
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
;
|
||||
; Cortex-M version
|
||||
;
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
PUBLIC __Vectors
|
||||
PUBLIC __Vectors_End
|
||||
PUBLIC __Vectors_Size
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD SecureFault_Handler ; Secure Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection Interrupt
|
||||
DCD RTC_IRQHandler ; RTC non-secure interrupt
|
||||
DCD RTC_S_IRQHandler ; RTC secure interrupt
|
||||
DCD TAMP_IRQHandler ; Tamper non-secure interrupt
|
||||
DCD RAMCFG_IRQHandler ; RAMCFG global
|
||||
DCD FLASH_IRQHandler ; FLASH non-secure global interrupt
|
||||
DCD FLASH_S_IRQHandler ; FLASH secure global interrupt
|
||||
DCD GTZC_IRQHandler ; Global TrustZone Controller interrupt
|
||||
DCD RCC_IRQHandler ; RCC non-secure global interrupt
|
||||
DCD RCC_S_IRQHandler ; RCC secure global interrupt
|
||||
DCD EXTI0_IRQHandler ; EXTI Line0 interrupt
|
||||
DCD EXTI1_IRQHandler ; EXTI Line1 interrupt
|
||||
DCD EXTI2_IRQHandler ; EXTI Line2 interrupt
|
||||
DCD EXTI3_IRQHandler ; EXTI Line3 interrupt
|
||||
DCD EXTI4_IRQHandler ; EXTI Line4 interrupt
|
||||
DCD EXTI5_IRQHandler ; EXTI Line5 interrupt
|
||||
DCD EXTI6_IRQHandler ; EXTI Line6 interrupt
|
||||
DCD EXTI7_IRQHandler ; EXTI Line7 interrupt
|
||||
DCD EXTI8_IRQHandler ; EXTI Line8 interrupt
|
||||
DCD EXTI9_IRQHandler ; EXTI Line9 interrupt
|
||||
DCD EXTI10_IRQHandler ; EXTI Line10 interrupt
|
||||
DCD EXTI11_IRQHandler ; EXTI Line11 interrupt
|
||||
DCD EXTI12_IRQHandler ; EXTI Line12 interrupt
|
||||
DCD EXTI13_IRQHandler ; EXTI Line13 interrupt
|
||||
DCD EXTI14_IRQHandler ; EXTI Line14 interrupt
|
||||
DCD EXTI15_IRQHandler ; EXTI Line15 interrupt
|
||||
DCD GPDMA1_Channel0_IRQHandler ; GPDMA1 Channel 0 global interrupt
|
||||
DCD GPDMA1_Channel1_IRQHandler ; GPDMA1 Channel 1 global interrupt
|
||||
DCD GPDMA1_Channel2_IRQHandler ; GPDMA1 Channel 2 global interrupt
|
||||
DCD GPDMA1_Channel3_IRQHandler ; GPDMA1 Channel 3 global interrupt
|
||||
DCD GPDMA1_Channel4_IRQHandler ; GPDMA1 Channel 4 global interrupt
|
||||
DCD GPDMA1_Channel5_IRQHandler ; GPDMA1 Channel 5 global interrupt
|
||||
DCD GPDMA1_Channel6_IRQHandler ; GPDMA1 Channel 6 global interrupt
|
||||
DCD GPDMA1_Channel7_IRQHandler ; GPDMA1 Channel 7 global interrupt
|
||||
DCD IWDG_IRQHandler ; IWDG global interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD ADC1_IRQHandler ; ADC1 global interrupt
|
||||
DCD DAC1_IRQHandler ; DAC1 global interrupt
|
||||
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt 0
|
||||
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt 1
|
||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
|
||||
DCD TIM1_UP_IRQHandler ; TIM1 Update interrupt
|
||||
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation interrupt
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare interrupt
|
||||
DCD TIM2_IRQHandler ; TIM2 global interrupt
|
||||
DCD TIM3_IRQHandler ; TIM3 global interrupt
|
||||
DCD TIM4_IRQHandler ; TIM4 global interrupt
|
||||
DCD TIM5_IRQHandler ; TIM5 global interrupt
|
||||
DCD TIM6_IRQHandler ; TIM6 global interrupt
|
||||
DCD TIM7_IRQHandler ; TIM7 global interrupt
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event interrupt
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error interrupt
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event interrupt
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error interrupt
|
||||
DCD SPI1_IRQHandler ; SPI1 global interrupt
|
||||
DCD SPI2_IRQHandler ; SPI2 global interrupt
|
||||
DCD SPI3_IRQHandler ; SPI3 global interrupt
|
||||
DCD USART1_IRQHandler ; USART1 global interrupt
|
||||
DCD USART2_IRQHandler ; USART2 global interrupt
|
||||
DCD USART3_IRQHandler ; USART3 global interrupt
|
||||
DCD UART4_IRQHandler ; UART4 global interrupt
|
||||
DCD UART5_IRQHandler ; UART5 global interrupt
|
||||
DCD LPUART1_IRQHandler ; LPUART1 global interrupt
|
||||
DCD LPTIM1_IRQHandler ; LPTIM1 global interrupt
|
||||
DCD TIM8_BRK_IRQHandler ; TIM8 Break interrupt
|
||||
DCD TIM8_UP_IRQHandler ; TIM8 Update interrupt
|
||||
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation interrupt
|
||||
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare interrupt
|
||||
DCD ADC2_IRQHandler ; ADC2 global interrupt
|
||||
DCD LPTIM2_IRQHandler ; LPTIM2 global interrupt
|
||||
DCD TIM15_IRQHandler ; TIM15 global interrupt
|
||||
DCD TIM16_IRQHandler ; TIM16 global interrupt
|
||||
DCD TIM17_IRQHandler ; TIM17 global interrupt
|
||||
DCD USB_DRD_FS_IRQHandler ; USB DRD FS global interrupt
|
||||
DCD CRS_IRQHandler ; CRS global interrupt
|
||||
DCD UCPD1_IRQHandler ; UCPD1 global interrupt
|
||||
DCD FMC_IRQHandler ; FMC global interrupt
|
||||
DCD OCTOSPI1_IRQHandler ; OctoSPI1 global interrupt
|
||||
DCD SDMMC1_IRQHandler ; SDMMC1 global interrupt
|
||||
DCD I2C3_EV_IRQHandler ; I2C2 Event interrupt
|
||||
DCD I2C3_ER_IRQHandler ; I2C2 Error interrupt
|
||||
DCD SPI4_IRQHandler ; SPI4 global interrupt
|
||||
DCD SPI5_IRQHandler ; SPI5 global interrupt
|
||||
DCD SPI6_IRQHandler ; SPI6 global interrupt
|
||||
DCD USART6_IRQHandler ; USART6 global interrupt
|
||||
DCD USART10_IRQHandler ; USART10 global interrupt
|
||||
DCD USART11_IRQHandler ; USART11 global interrupt
|
||||
DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt
|
||||
DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt
|
||||
DCD GPDMA2_Channel0_IRQHandler ; GPDMA2 Channel 0 global interrupt
|
||||
DCD GPDMA2_Channel1_IRQHandler ; GPDMA2 Channel 1 global interrupt
|
||||
DCD GPDMA2_Channel2_IRQHandler ; GPDMA2 Channel 2 global interrupt
|
||||
DCD GPDMA2_Channel3_IRQHandler ; GPDMA2 Channel 3 global interrupt
|
||||
DCD GPDMA2_Channel4_IRQHandler ; GPDMA2 Channel 4 global interrupt
|
||||
DCD GPDMA2_Channel5_IRQHandler ; GPDMA2 Channel 5 global interrupt
|
||||
DCD GPDMA2_Channel6_IRQHandler ; GPDMA2 Channel 6 global interrupt
|
||||
DCD GPDMA2_Channel7_IRQHandler ; GPDMA2 Channel 7 global interrupt
|
||||
DCD UART7_IRQHandler ; UART7 global interrupt
|
||||
DCD UART8_IRQHandler ; UART8 global interrupt
|
||||
DCD UART9_IRQHandler ; UART9 global interrupt
|
||||
DCD UART12_IRQHandler ; UART12 global interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD FPU_IRQHandler ; FPU global interrupt
|
||||
DCD ICACHE_IRQHandler ; Instruction cache global interrupt
|
||||
DCD DCACHE1_IRQHandler ; DCACHE1 global interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD DCMI_PSSI_IRQHandler ; DCMI PSSI global interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD CORDIC_IRQHandler ; CORDIC global interrupt
|
||||
DCD FMAC_IRQHandler ; FMAC global interrupt
|
||||
DCD DTS_IRQHandler ; DTS global interrupt
|
||||
DCD RNG_IRQHandler ; RNG global interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD HASH_IRQHandler ; HASH global interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD CEC_IRQHandler ; CEC global interrupt
|
||||
DCD TIM12_IRQHandler ; TIM12 global interrupt
|
||||
DCD TIM13_IRQHandler ; TIM13 global interrupt
|
||||
DCD TIM14_IRQHandler ; TIM14 global interrupt
|
||||
DCD I3C1_EV_IRQHandler ; I3C1 Event interrupt
|
||||
DCD I3C1_ER_IRQHandler ; I3C1 Error interrupt
|
||||
DCD I2C4_EV_IRQHandler ; I2C4 Event interrupt
|
||||
DCD I2C4_ER_IRQHandler ; I2C4 Error interrupt
|
||||
DCD LPTIM3_IRQHandler ; LPTIM3 global interrupt
|
||||
DCD LPTIM4_IRQHandler ; LPTIM4 global interrupt
|
||||
DCD LPTIM5_IRQHandler ; LPTIM5 global interrupt
|
||||
DCD LPTIM6_IRQHandler ; LPTIM6 global interrupt
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors EQU __vector_table
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||
Reset_Handler
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
NMI_Handler
|
||||
B NMI_Handler
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HardFault_Handler
|
||||
B HardFault_Handler
|
||||
|
||||
PUBWEAK MemManage_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
MemManage_Handler
|
||||
B MemManage_Handler
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
BusFault_Handler
|
||||
B BusFault_Handler
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UsageFault_Handler
|
||||
B UsageFault_Handler
|
||||
|
||||
PUBWEAK SecureFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SecureFault_Handler
|
||||
B SecureFault_Handler
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SVC_Handler
|
||||
B SVC_Handler
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DebugMon_Handler
|
||||
B DebugMon_Handler
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PendSV_Handler
|
||||
B PendSV_Handler
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SysTick_Handler
|
||||
B SysTick_Handler
|
||||
|
||||
PUBWEAK WWDG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
WWDG_IRQHandler
|
||||
B WWDG_IRQHandler
|
||||
|
||||
PUBWEAK PVD_AVD_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PVD_AVD_IRQHandler
|
||||
B PVD_AVD_IRQHandler
|
||||
|
||||
PUBWEAK RTC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_IRQHandler
|
||||
B RTC_IRQHandler
|
||||
|
||||
PUBWEAK RTC_S_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_S_IRQHandler
|
||||
B RTC_S_IRQHandler
|
||||
|
||||
PUBWEAK TAMP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TAMP_IRQHandler
|
||||
B TAMP_IRQHandler
|
||||
|
||||
PUBWEAK RAMCFG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RAMCFG_IRQHandler
|
||||
B RAMCFG_IRQHandler
|
||||
|
||||
PUBWEAK FLASH_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FLASH_IRQHandler
|
||||
B FLASH_IRQHandler
|
||||
|
||||
PUBWEAK FLASH_S_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FLASH_S_IRQHandler
|
||||
B FLASH_S_IRQHandler
|
||||
|
||||
PUBWEAK GTZC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GTZC_IRQHandler
|
||||
B GTZC_IRQHandler
|
||||
|
||||
PUBWEAK RCC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RCC_IRQHandler
|
||||
B RCC_IRQHandler
|
||||
|
||||
PUBWEAK RCC_S_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RCC_S_IRQHandler
|
||||
B RCC_S_IRQHandler
|
||||
|
||||
PUBWEAK EXTI0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI0_IRQHandler
|
||||
B EXTI0_IRQHandler
|
||||
|
||||
PUBWEAK EXTI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI1_IRQHandler
|
||||
B EXTI1_IRQHandler
|
||||
|
||||
PUBWEAK EXTI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI2_IRQHandler
|
||||
B EXTI2_IRQHandler
|
||||
|
||||
PUBWEAK EXTI3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI3_IRQHandler
|
||||
B EXTI3_IRQHandler
|
||||
|
||||
PUBWEAK EXTI4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI4_IRQHandler
|
||||
B EXTI4_IRQHandler
|
||||
|
||||
PUBWEAK EXTI5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI5_IRQHandler
|
||||
B EXTI5_IRQHandler
|
||||
|
||||
PUBWEAK EXTI6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI6_IRQHandler
|
||||
B EXTI6_IRQHandler
|
||||
|
||||
PUBWEAK EXTI7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI7_IRQHandler
|
||||
B EXTI7_IRQHandler
|
||||
|
||||
PUBWEAK EXTI8_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI8_IRQHandler
|
||||
B EXTI8_IRQHandler
|
||||
|
||||
PUBWEAK EXTI9_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI9_IRQHandler
|
||||
B EXTI9_IRQHandler
|
||||
|
||||
PUBWEAK EXTI10_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI10_IRQHandler
|
||||
B EXTI10_IRQHandler
|
||||
|
||||
PUBWEAK EXTI11_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI11_IRQHandler
|
||||
B EXTI11_IRQHandler
|
||||
|
||||
PUBWEAK EXTI12_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI12_IRQHandler
|
||||
B EXTI12_IRQHandler
|
||||
|
||||
PUBWEAK EXTI13_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI13_IRQHandler
|
||||
B EXTI13_IRQHandler
|
||||
|
||||
PUBWEAK EXTI14_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI14_IRQHandler
|
||||
B EXTI14_IRQHandler
|
||||
|
||||
PUBWEAK EXTI15_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI15_IRQHandler
|
||||
B EXTI15_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA1_Channel0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA1_Channel0_IRQHandler
|
||||
B GPDMA1_Channel0_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA1_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA1_Channel1_IRQHandler
|
||||
B GPDMA1_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA1_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA1_Channel2_IRQHandler
|
||||
B GPDMA1_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA1_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA1_Channel3_IRQHandler
|
||||
B GPDMA1_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA1_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA1_Channel4_IRQHandler
|
||||
B GPDMA1_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA1_Channel5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA1_Channel5_IRQHandler
|
||||
B GPDMA1_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA1_Channel6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA1_Channel6_IRQHandler
|
||||
B GPDMA1_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA1_Channel7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA1_Channel7_IRQHandler
|
||||
B GPDMA1_Channel7_IRQHandler
|
||||
|
||||
PUBWEAK IWDG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IWDG_IRQHandler
|
||||
B IWDG_IRQHandler
|
||||
|
||||
PUBWEAK ADC1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ADC1_IRQHandler
|
||||
B ADC1_IRQHandler
|
||||
|
||||
PUBWEAK DAC1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DAC1_IRQHandler
|
||||
B DAC1_IRQHandler
|
||||
|
||||
PUBWEAK FDCAN1_IT0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FDCAN1_IT0_IRQHandler
|
||||
B FDCAN1_IT0_IRQHandler
|
||||
|
||||
PUBWEAK FDCAN1_IT1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FDCAN1_IT1_IRQHandler
|
||||
B FDCAN1_IT1_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_BRK_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_BRK_IRQHandler
|
||||
B TIM1_BRK_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_UP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_UP_IRQHandler
|
||||
B TIM1_UP_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_TRG_COM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_TRG_COM_IRQHandler
|
||||
B TIM1_TRG_COM_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_CC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_CC_IRQHandler
|
||||
B TIM1_CC_IRQHandler
|
||||
|
||||
PUBWEAK TIM2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM2_IRQHandler
|
||||
B TIM2_IRQHandler
|
||||
|
||||
PUBWEAK TIM3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM3_IRQHandler
|
||||
B TIM3_IRQHandler
|
||||
|
||||
PUBWEAK TIM4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM4_IRQHandler
|
||||
B TIM4_IRQHandler
|
||||
|
||||
PUBWEAK TIM5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM5_IRQHandler
|
||||
B TIM5_IRQHandler
|
||||
|
||||
PUBWEAK TIM6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM6_IRQHandler
|
||||
B TIM6_IRQHandler
|
||||
|
||||
PUBWEAK TIM7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM7_IRQHandler
|
||||
B TIM7_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_EV_IRQHandler
|
||||
B I2C1_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_ER_IRQHandler
|
||||
B I2C1_ER_IRQHandler
|
||||
|
||||
PUBWEAK I2C2_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C2_EV_IRQHandler
|
||||
B I2C2_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C2_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C2_ER_IRQHandler
|
||||
B I2C2_ER_IRQHandler
|
||||
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI1_IRQHandler
|
||||
B SPI1_IRQHandler
|
||||
|
||||
PUBWEAK SPI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI2_IRQHandler
|
||||
B SPI2_IRQHandler
|
||||
|
||||
PUBWEAK SPI3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI3_IRQHandler
|
||||
B SPI3_IRQHandler
|
||||
|
||||
PUBWEAK USART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART1_IRQHandler
|
||||
B USART1_IRQHandler
|
||||
|
||||
PUBWEAK USART2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART2_IRQHandler
|
||||
B USART2_IRQHandler
|
||||
|
||||
PUBWEAK USART3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART3_IRQHandler
|
||||
B USART3_IRQHandler
|
||||
|
||||
PUBWEAK UART4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART4_IRQHandler
|
||||
B UART4_IRQHandler
|
||||
|
||||
PUBWEAK UART5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART5_IRQHandler
|
||||
B UART5_IRQHandler
|
||||
|
||||
PUBWEAK LPUART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPUART1_IRQHandler
|
||||
B LPUART1_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM1_IRQHandler
|
||||
B LPTIM1_IRQHandler
|
||||
|
||||
PUBWEAK TIM8_BRK_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM8_BRK_IRQHandler
|
||||
B TIM8_BRK_IRQHandler
|
||||
|
||||
PUBWEAK TIM8_UP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM8_UP_IRQHandler
|
||||
B TIM8_UP_IRQHandler
|
||||
|
||||
PUBWEAK TIM8_TRG_COM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM8_TRG_COM_IRQHandler
|
||||
B TIM8_TRG_COM_IRQHandler
|
||||
|
||||
PUBWEAK TIM8_CC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM8_CC_IRQHandler
|
||||
B TIM8_CC_IRQHandler
|
||||
|
||||
PUBWEAK ADC2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ADC2_IRQHandler
|
||||
B ADC2_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM2_IRQHandler
|
||||
B LPTIM2_IRQHandler
|
||||
|
||||
PUBWEAK TIM15_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM15_IRQHandler
|
||||
B TIM15_IRQHandler
|
||||
|
||||
PUBWEAK TIM16_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM16_IRQHandler
|
||||
B TIM16_IRQHandler
|
||||
|
||||
PUBWEAK TIM17_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM17_IRQHandler
|
||||
B TIM17_IRQHandler
|
||||
|
||||
PUBWEAK USB_DRD_FS_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USB_DRD_FS_IRQHandler
|
||||
B USB_DRD_FS_IRQHandler
|
||||
|
||||
PUBWEAK CRS_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CRS_IRQHandler
|
||||
B CRS_IRQHandler
|
||||
|
||||
PUBWEAK UCPD1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UCPD1_IRQHandler
|
||||
B UCPD1_IRQHandler
|
||||
|
||||
PUBWEAK FMC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FMC_IRQHandler
|
||||
B FMC_IRQHandler
|
||||
|
||||
PUBWEAK OCTOSPI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
OCTOSPI1_IRQHandler
|
||||
B OCTOSPI1_IRQHandler
|
||||
|
||||
PUBWEAK SDMMC1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SDMMC1_IRQHandler
|
||||
B SDMMC1_IRQHandler
|
||||
|
||||
PUBWEAK I2C3_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C3_EV_IRQHandler
|
||||
B I2C3_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C3_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C3_ER_IRQHandler
|
||||
B I2C3_ER_IRQHandler
|
||||
|
||||
PUBWEAK SPI4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI4_IRQHandler
|
||||
B SPI4_IRQHandler
|
||||
|
||||
PUBWEAK SPI5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI5_IRQHandler
|
||||
B SPI5_IRQHandler
|
||||
|
||||
PUBWEAK SPI6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI6_IRQHandler
|
||||
B SPI6_IRQHandler
|
||||
|
||||
PUBWEAK USART6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART6_IRQHandler
|
||||
B USART6_IRQHandler
|
||||
|
||||
PUBWEAK USART10_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART10_IRQHandler
|
||||
B USART10_IRQHandler
|
||||
|
||||
PUBWEAK USART11_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART11_IRQHandler
|
||||
B USART11_IRQHandler
|
||||
|
||||
PUBWEAK SAI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SAI1_IRQHandler
|
||||
B SAI1_IRQHandler
|
||||
|
||||
PUBWEAK SAI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SAI2_IRQHandler
|
||||
B SAI2_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA2_Channel0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA2_Channel0_IRQHandler
|
||||
B GPDMA2_Channel0_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA2_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA2_Channel1_IRQHandler
|
||||
B GPDMA2_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA2_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA2_Channel2_IRQHandler
|
||||
B GPDMA2_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA2_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA2_Channel3_IRQHandler
|
||||
B GPDMA2_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA2_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA2_Channel4_IRQHandler
|
||||
B GPDMA2_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA2_Channel5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA2_Channel5_IRQHandler
|
||||
B GPDMA2_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA2_Channel6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA2_Channel6_IRQHandler
|
||||
B GPDMA2_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA2_Channel7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA2_Channel7_IRQHandler
|
||||
B GPDMA2_Channel7_IRQHandler
|
||||
|
||||
PUBWEAK UART7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART7_IRQHandler
|
||||
B UART7_IRQHandler
|
||||
|
||||
PUBWEAK UART8_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART8_IRQHandler
|
||||
B UART8_IRQHandler
|
||||
|
||||
PUBWEAK UART9_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART9_IRQHandler
|
||||
B UART9_IRQHandler
|
||||
|
||||
PUBWEAK UART12_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART12_IRQHandler
|
||||
B UART12_IRQHandler
|
||||
|
||||
PUBWEAK FPU_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FPU_IRQHandler
|
||||
B FPU_IRQHandler
|
||||
|
||||
PUBWEAK ICACHE_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ICACHE_IRQHandler
|
||||
B ICACHE_IRQHandler
|
||||
|
||||
PUBWEAK DCACHE1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DCACHE1_IRQHandler
|
||||
B DCACHE1_IRQHandler
|
||||
|
||||
PUBWEAK DCMI_PSSI_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DCMI_PSSI_IRQHandler
|
||||
B DCMI_PSSI_IRQHandler
|
||||
|
||||
PUBWEAK CORDIC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CORDIC_IRQHandler
|
||||
B CORDIC_IRQHandler
|
||||
|
||||
PUBWEAK FMAC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FMAC_IRQHandler
|
||||
B FMAC_IRQHandler
|
||||
|
||||
PUBWEAK DTS_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DTS_IRQHandler
|
||||
B DTS_IRQHandler
|
||||
|
||||
PUBWEAK RNG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RNG_IRQHandler
|
||||
B RNG_IRQHandler
|
||||
|
||||
PUBWEAK HASH_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HASH_IRQHandler
|
||||
B HASH_IRQHandler
|
||||
|
||||
PUBWEAK CEC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CEC_IRQHandler
|
||||
B CEC_IRQHandler
|
||||
|
||||
PUBWEAK TIM12_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM12_IRQHandler
|
||||
B TIM12_IRQHandler
|
||||
|
||||
PUBWEAK TIM13_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM13_IRQHandler
|
||||
B TIM13_IRQHandler
|
||||
|
||||
PUBWEAK TIM14_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM14_IRQHandler
|
||||
B TIM14_IRQHandler
|
||||
|
||||
PUBWEAK I3C1_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I3C1_EV_IRQHandler
|
||||
B I3C1_EV_IRQHandler
|
||||
|
||||
PUBWEAK I3C1_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I3C1_ER_IRQHandler
|
||||
B I3C1_ER_IRQHandler
|
||||
|
||||
PUBWEAK I2C4_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C4_EV_IRQHandler
|
||||
B I2C4_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C4_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C4_ER_IRQHandler
|
||||
B I2C4_ER_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM3_IRQHandler
|
||||
B LPTIM3_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM4_IRQHandler
|
||||
B LPTIM4_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM5_IRQHandler
|
||||
B LPTIM5_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM6_IRQHandler
|
||||
B LPTIM6_IRQHandler
|
||||
|
||||
END
|
||||
|
|
@ -0,0 +1,912 @@
|
|||
;********************************************************************************
|
||||
;* File Name : startup_stm32h563xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : STM32H563xx Non Crypto Devices vector
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == _iar_program_start,
|
||||
;* - Set the vector table entries with the exceptions ISR
|
||||
;* address.
|
||||
;* - Branches to main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M33 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* Copyright (c) 2023 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;*******************************************************************************
|
||||
;
|
||||
;
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
;
|
||||
; Cortex-M version
|
||||
;
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
PUBLIC __Vectors
|
||||
PUBLIC __Vectors_End
|
||||
PUBLIC __Vectors_Size
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD SecureFault_Handler ; Secure Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection Interrupt
|
||||
DCD RTC_IRQHandler ; RTC non-secure interrupt
|
||||
DCD RTC_S_IRQHandler ; RTC secure interrupt
|
||||
DCD TAMP_IRQHandler ; Tamper non-secure interrupt
|
||||
DCD RAMCFG_IRQHandler ; RAMCFG global
|
||||
DCD FLASH_IRQHandler ; FLASH non-secure global interrupt
|
||||
DCD FLASH_S_IRQHandler ; FLASH secure global interrupt
|
||||
DCD GTZC_IRQHandler ; Global TrustZone Controller interrupt
|
||||
DCD RCC_IRQHandler ; RCC non-secure global interrupt
|
||||
DCD RCC_S_IRQHandler ; RCC secure global interrupt
|
||||
DCD EXTI0_IRQHandler ; EXTI Line0 interrupt
|
||||
DCD EXTI1_IRQHandler ; EXTI Line1 interrupt
|
||||
DCD EXTI2_IRQHandler ; EXTI Line2 interrupt
|
||||
DCD EXTI3_IRQHandler ; EXTI Line3 interrupt
|
||||
DCD EXTI4_IRQHandler ; EXTI Line4 interrupt
|
||||
DCD EXTI5_IRQHandler ; EXTI Line5 interrupt
|
||||
DCD EXTI6_IRQHandler ; EXTI Line6 interrupt
|
||||
DCD EXTI7_IRQHandler ; EXTI Line7 interrupt
|
||||
DCD EXTI8_IRQHandler ; EXTI Line8 interrupt
|
||||
DCD EXTI9_IRQHandler ; EXTI Line9 interrupt
|
||||
DCD EXTI10_IRQHandler ; EXTI Line10 interrupt
|
||||
DCD EXTI11_IRQHandler ; EXTI Line11 interrupt
|
||||
DCD EXTI12_IRQHandler ; EXTI Line12 interrupt
|
||||
DCD EXTI13_IRQHandler ; EXTI Line13 interrupt
|
||||
DCD EXTI14_IRQHandler ; EXTI Line14 interrupt
|
||||
DCD EXTI15_IRQHandler ; EXTI Line15 interrupt
|
||||
DCD GPDMA1_Channel0_IRQHandler ; GPDMA1 Channel 0 global interrupt
|
||||
DCD GPDMA1_Channel1_IRQHandler ; GPDMA1 Channel 1 global interrupt
|
||||
DCD GPDMA1_Channel2_IRQHandler ; GPDMA1 Channel 2 global interrupt
|
||||
DCD GPDMA1_Channel3_IRQHandler ; GPDMA1 Channel 3 global interrupt
|
||||
DCD GPDMA1_Channel4_IRQHandler ; GPDMA1 Channel 4 global interrupt
|
||||
DCD GPDMA1_Channel5_IRQHandler ; GPDMA1 Channel 5 global interrupt
|
||||
DCD GPDMA1_Channel6_IRQHandler ; GPDMA1 Channel 6 global interrupt
|
||||
DCD GPDMA1_Channel7_IRQHandler ; GPDMA1 Channel 7 global interrupt
|
||||
DCD IWDG_IRQHandler ; IWDG global interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD ADC1_IRQHandler ; ADC1 global interrupt
|
||||
DCD DAC1_IRQHandler ; DAC1 global interrupt
|
||||
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt 0
|
||||
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt 1
|
||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
|
||||
DCD TIM1_UP_IRQHandler ; TIM1 Update interrupt
|
||||
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation interrupt
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare interrupt
|
||||
DCD TIM2_IRQHandler ; TIM2 global interrupt
|
||||
DCD TIM3_IRQHandler ; TIM3 global interrupt
|
||||
DCD TIM4_IRQHandler ; TIM4 global interrupt
|
||||
DCD TIM5_IRQHandler ; TIM5 global interrupt
|
||||
DCD TIM6_IRQHandler ; TIM6 global interrupt
|
||||
DCD TIM7_IRQHandler ; TIM7 global interrupt
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event interrupt
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error interrupt
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event interrupt
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error interrupt
|
||||
DCD SPI1_IRQHandler ; SPI1 global interrupt
|
||||
DCD SPI2_IRQHandler ; SPI2 global interrupt
|
||||
DCD SPI3_IRQHandler ; SPI3 global interrupt
|
||||
DCD USART1_IRQHandler ; USART1 global interrupt
|
||||
DCD USART2_IRQHandler ; USART2 global interrupt
|
||||
DCD USART3_IRQHandler ; USART3 global interrupt
|
||||
DCD UART4_IRQHandler ; UART4 global interrupt
|
||||
DCD UART5_IRQHandler ; UART5 global interrupt
|
||||
DCD LPUART1_IRQHandler ; LPUART1 global interrupt
|
||||
DCD LPTIM1_IRQHandler ; LPTIM1 global interrupt
|
||||
DCD TIM8_BRK_IRQHandler ; TIM8 Break interrupt
|
||||
DCD TIM8_UP_IRQHandler ; TIM8 Update interrupt
|
||||
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation interrupt
|
||||
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare interrupt
|
||||
DCD ADC2_IRQHandler ; ADC2 global interrupt
|
||||
DCD LPTIM2_IRQHandler ; LPTIM2 global interrupt
|
||||
DCD TIM15_IRQHandler ; TIM15 global interrupt
|
||||
DCD TIM16_IRQHandler ; TIM16 global interrupt
|
||||
DCD TIM17_IRQHandler ; TIM17 global interrupt
|
||||
DCD USB_DRD_FS_IRQHandler ; USB DRD FS global interrupt
|
||||
DCD CRS_IRQHandler ; CRS global interrupt
|
||||
DCD UCPD1_IRQHandler ; UCPD1 global interrupt
|
||||
DCD FMC_IRQHandler ; FMC global interrupt
|
||||
DCD OCTOSPI1_IRQHandler ; OctoSPI1 global interrupt
|
||||
DCD SDMMC1_IRQHandler ; SDMMC1 global interrupt
|
||||
DCD I2C3_EV_IRQHandler ; I2C2 Event interrupt
|
||||
DCD I2C3_ER_IRQHandler ; I2C2 Error interrupt
|
||||
DCD SPI4_IRQHandler ; SPI4 global interrupt
|
||||
DCD SPI5_IRQHandler ; SPI5 global interrupt
|
||||
DCD SPI6_IRQHandler ; SPI6 global interrupt
|
||||
DCD USART6_IRQHandler ; USART6 global interrupt
|
||||
DCD USART10_IRQHandler ; USART10 global interrupt
|
||||
DCD USART11_IRQHandler ; USART11 global interrupt
|
||||
DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt
|
||||
DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt
|
||||
DCD GPDMA2_Channel0_IRQHandler ; GPDMA2 Channel 0 global interrupt
|
||||
DCD GPDMA2_Channel1_IRQHandler ; GPDMA2 Channel 1 global interrupt
|
||||
DCD GPDMA2_Channel2_IRQHandler ; GPDMA2 Channel 2 global interrupt
|
||||
DCD GPDMA2_Channel3_IRQHandler ; GPDMA2 Channel 3 global interrupt
|
||||
DCD GPDMA2_Channel4_IRQHandler ; GPDMA2 Channel 4 global interrupt
|
||||
DCD GPDMA2_Channel5_IRQHandler ; GPDMA2 Channel 5 global interrupt
|
||||
DCD GPDMA2_Channel6_IRQHandler ; GPDMA2 Channel 6 global interrupt
|
||||
DCD GPDMA2_Channel7_IRQHandler ; GPDMA2 Channel 7 global interrupt
|
||||
DCD UART7_IRQHandler ; UART7 global interrupt
|
||||
DCD UART8_IRQHandler ; UART8 global interrupt
|
||||
DCD UART9_IRQHandler ; UART9 global interrupt
|
||||
DCD UART12_IRQHandler ; UART12 global interrupt
|
||||
DCD SDMMC2_IRQHandler ; SDMMC2 global interrupt
|
||||
DCD FPU_IRQHandler ; FPU global interrupt
|
||||
DCD ICACHE_IRQHandler ; Instruction cache global interrupt
|
||||
DCD DCACHE1_IRQHandler ; DCACHE1 global interrupt
|
||||
DCD ETH_IRQHandler ; Ethernet global interrupt
|
||||
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup global interrupt
|
||||
DCD DCMI_PSSI_IRQHandler ; DCMI PSSI global interrupt
|
||||
DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt 0
|
||||
DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt 1
|
||||
DCD CORDIC_IRQHandler ; CORDIC global interrupt
|
||||
DCD FMAC_IRQHandler ; FMAC global interrupt
|
||||
DCD DTS_IRQHandler ; DTS global interrupt
|
||||
DCD RNG_IRQHandler ; RNG global interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD HASH_IRQHandler ; HASH global interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD CEC_IRQHandler ; CEC global interrupt
|
||||
DCD TIM12_IRQHandler ; TIM12 global interrupt
|
||||
DCD TIM13_IRQHandler ; TIM13 global interrupt
|
||||
DCD TIM14_IRQHandler ; TIM14 global interrupt
|
||||
DCD I3C1_EV_IRQHandler ; I3C1 Event interrupt
|
||||
DCD I3C1_ER_IRQHandler ; I3C1 Error interrupt
|
||||
DCD I2C4_EV_IRQHandler ; I2C4 Event interrupt
|
||||
DCD I2C4_ER_IRQHandler ; I2C4 Error interrupt
|
||||
DCD LPTIM3_IRQHandler ; LPTIM3 global interrupt
|
||||
DCD LPTIM4_IRQHandler ; LPTIM4 global interrupt
|
||||
DCD LPTIM5_IRQHandler ; LPTIM5 global interrupt
|
||||
DCD LPTIM6_IRQHandler ; LPTIM6 global interrupt
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors EQU __vector_table
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||
Reset_Handler
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
NMI_Handler
|
||||
B NMI_Handler
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HardFault_Handler
|
||||
B HardFault_Handler
|
||||
|
||||
PUBWEAK MemManage_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
MemManage_Handler
|
||||
B MemManage_Handler
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
BusFault_Handler
|
||||
B BusFault_Handler
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UsageFault_Handler
|
||||
B UsageFault_Handler
|
||||
|
||||
PUBWEAK SecureFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SecureFault_Handler
|
||||
B SecureFault_Handler
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SVC_Handler
|
||||
B SVC_Handler
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DebugMon_Handler
|
||||
B DebugMon_Handler
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PendSV_Handler
|
||||
B PendSV_Handler
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SysTick_Handler
|
||||
B SysTick_Handler
|
||||
|
||||
PUBWEAK WWDG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
WWDG_IRQHandler
|
||||
B WWDG_IRQHandler
|
||||
|
||||
PUBWEAK PVD_AVD_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PVD_AVD_IRQHandler
|
||||
B PVD_AVD_IRQHandler
|
||||
|
||||
PUBWEAK RTC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_IRQHandler
|
||||
B RTC_IRQHandler
|
||||
|
||||
PUBWEAK RTC_S_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_S_IRQHandler
|
||||
B RTC_S_IRQHandler
|
||||
|
||||
PUBWEAK TAMP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TAMP_IRQHandler
|
||||
B TAMP_IRQHandler
|
||||
|
||||
PUBWEAK RAMCFG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RAMCFG_IRQHandler
|
||||
B RAMCFG_IRQHandler
|
||||
|
||||
PUBWEAK FLASH_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FLASH_IRQHandler
|
||||
B FLASH_IRQHandler
|
||||
|
||||
PUBWEAK FLASH_S_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FLASH_S_IRQHandler
|
||||
B FLASH_S_IRQHandler
|
||||
|
||||
PUBWEAK GTZC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GTZC_IRQHandler
|
||||
B GTZC_IRQHandler
|
||||
|
||||
PUBWEAK RCC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RCC_IRQHandler
|
||||
B RCC_IRQHandler
|
||||
|
||||
PUBWEAK RCC_S_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RCC_S_IRQHandler
|
||||
B RCC_S_IRQHandler
|
||||
|
||||
PUBWEAK EXTI0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI0_IRQHandler
|
||||
B EXTI0_IRQHandler
|
||||
|
||||
PUBWEAK EXTI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI1_IRQHandler
|
||||
B EXTI1_IRQHandler
|
||||
|
||||
PUBWEAK EXTI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI2_IRQHandler
|
||||
B EXTI2_IRQHandler
|
||||
|
||||
PUBWEAK EXTI3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI3_IRQHandler
|
||||
B EXTI3_IRQHandler
|
||||
|
||||
PUBWEAK EXTI4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI4_IRQHandler
|
||||
B EXTI4_IRQHandler
|
||||
|
||||
PUBWEAK EXTI5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI5_IRQHandler
|
||||
B EXTI5_IRQHandler
|
||||
|
||||
PUBWEAK EXTI6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI6_IRQHandler
|
||||
B EXTI6_IRQHandler
|
||||
|
||||
PUBWEAK EXTI7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI7_IRQHandler
|
||||
B EXTI7_IRQHandler
|
||||
|
||||
PUBWEAK EXTI8_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI8_IRQHandler
|
||||
B EXTI8_IRQHandler
|
||||
|
||||
PUBWEAK EXTI9_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI9_IRQHandler
|
||||
B EXTI9_IRQHandler
|
||||
|
||||
PUBWEAK EXTI10_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI10_IRQHandler
|
||||
B EXTI10_IRQHandler
|
||||
|
||||
PUBWEAK EXTI11_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI11_IRQHandler
|
||||
B EXTI11_IRQHandler
|
||||
|
||||
PUBWEAK EXTI12_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI12_IRQHandler
|
||||
B EXTI12_IRQHandler
|
||||
|
||||
PUBWEAK EXTI13_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI13_IRQHandler
|
||||
B EXTI13_IRQHandler
|
||||
|
||||
PUBWEAK EXTI14_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI14_IRQHandler
|
||||
B EXTI14_IRQHandler
|
||||
|
||||
PUBWEAK EXTI15_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI15_IRQHandler
|
||||
B EXTI15_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA1_Channel0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA1_Channel0_IRQHandler
|
||||
B GPDMA1_Channel0_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA1_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA1_Channel1_IRQHandler
|
||||
B GPDMA1_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA1_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA1_Channel2_IRQHandler
|
||||
B GPDMA1_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA1_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA1_Channel3_IRQHandler
|
||||
B GPDMA1_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA1_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA1_Channel4_IRQHandler
|
||||
B GPDMA1_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA1_Channel5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA1_Channel5_IRQHandler
|
||||
B GPDMA1_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA1_Channel6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA1_Channel6_IRQHandler
|
||||
B GPDMA1_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA1_Channel7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA1_Channel7_IRQHandler
|
||||
B GPDMA1_Channel7_IRQHandler
|
||||
|
||||
PUBWEAK IWDG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IWDG_IRQHandler
|
||||
B IWDG_IRQHandler
|
||||
|
||||
PUBWEAK ADC1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ADC1_IRQHandler
|
||||
B ADC1_IRQHandler
|
||||
|
||||
PUBWEAK DAC1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DAC1_IRQHandler
|
||||
B DAC1_IRQHandler
|
||||
|
||||
PUBWEAK FDCAN1_IT0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FDCAN1_IT0_IRQHandler
|
||||
B FDCAN1_IT0_IRQHandler
|
||||
|
||||
PUBWEAK FDCAN1_IT1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FDCAN1_IT1_IRQHandler
|
||||
B FDCAN1_IT1_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_BRK_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_BRK_IRQHandler
|
||||
B TIM1_BRK_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_UP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_UP_IRQHandler
|
||||
B TIM1_UP_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_TRG_COM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_TRG_COM_IRQHandler
|
||||
B TIM1_TRG_COM_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_CC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_CC_IRQHandler
|
||||
B TIM1_CC_IRQHandler
|
||||
|
||||
PUBWEAK TIM2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM2_IRQHandler
|
||||
B TIM2_IRQHandler
|
||||
|
||||
PUBWEAK TIM3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM3_IRQHandler
|
||||
B TIM3_IRQHandler
|
||||
|
||||
PUBWEAK TIM4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM4_IRQHandler
|
||||
B TIM4_IRQHandler
|
||||
|
||||
PUBWEAK TIM5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM5_IRQHandler
|
||||
B TIM5_IRQHandler
|
||||
|
||||
PUBWEAK TIM6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM6_IRQHandler
|
||||
B TIM6_IRQHandler
|
||||
|
||||
PUBWEAK TIM7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM7_IRQHandler
|
||||
B TIM7_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_EV_IRQHandler
|
||||
B I2C1_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_ER_IRQHandler
|
||||
B I2C1_ER_IRQHandler
|
||||
|
||||
PUBWEAK I2C2_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C2_EV_IRQHandler
|
||||
B I2C2_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C2_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C2_ER_IRQHandler
|
||||
B I2C2_ER_IRQHandler
|
||||
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI1_IRQHandler
|
||||
B SPI1_IRQHandler
|
||||
|
||||
PUBWEAK SPI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI2_IRQHandler
|
||||
B SPI2_IRQHandler
|
||||
|
||||
PUBWEAK SPI3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI3_IRQHandler
|
||||
B SPI3_IRQHandler
|
||||
|
||||
PUBWEAK USART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART1_IRQHandler
|
||||
B USART1_IRQHandler
|
||||
|
||||
PUBWEAK USART2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART2_IRQHandler
|
||||
B USART2_IRQHandler
|
||||
|
||||
PUBWEAK USART3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART3_IRQHandler
|
||||
B USART3_IRQHandler
|
||||
|
||||
PUBWEAK UART4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART4_IRQHandler
|
||||
B UART4_IRQHandler
|
||||
|
||||
PUBWEAK UART5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART5_IRQHandler
|
||||
B UART5_IRQHandler
|
||||
|
||||
PUBWEAK LPUART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPUART1_IRQHandler
|
||||
B LPUART1_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM1_IRQHandler
|
||||
B LPTIM1_IRQHandler
|
||||
|
||||
PUBWEAK TIM8_BRK_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM8_BRK_IRQHandler
|
||||
B TIM8_BRK_IRQHandler
|
||||
|
||||
PUBWEAK TIM8_UP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM8_UP_IRQHandler
|
||||
B TIM8_UP_IRQHandler
|
||||
|
||||
PUBWEAK TIM8_TRG_COM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM8_TRG_COM_IRQHandler
|
||||
B TIM8_TRG_COM_IRQHandler
|
||||
|
||||
PUBWEAK TIM8_CC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM8_CC_IRQHandler
|
||||
B TIM8_CC_IRQHandler
|
||||
|
||||
PUBWEAK ADC2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ADC2_IRQHandler
|
||||
B ADC2_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM2_IRQHandler
|
||||
B LPTIM2_IRQHandler
|
||||
|
||||
PUBWEAK TIM15_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM15_IRQHandler
|
||||
B TIM15_IRQHandler
|
||||
|
||||
PUBWEAK TIM16_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM16_IRQHandler
|
||||
B TIM16_IRQHandler
|
||||
|
||||
PUBWEAK TIM17_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM17_IRQHandler
|
||||
B TIM17_IRQHandler
|
||||
|
||||
PUBWEAK USB_DRD_FS_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USB_DRD_FS_IRQHandler
|
||||
B USB_DRD_FS_IRQHandler
|
||||
|
||||
PUBWEAK CRS_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CRS_IRQHandler
|
||||
B CRS_IRQHandler
|
||||
|
||||
PUBWEAK UCPD1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UCPD1_IRQHandler
|
||||
B UCPD1_IRQHandler
|
||||
|
||||
PUBWEAK FMC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FMC_IRQHandler
|
||||
B FMC_IRQHandler
|
||||
|
||||
PUBWEAK OCTOSPI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
OCTOSPI1_IRQHandler
|
||||
B OCTOSPI1_IRQHandler
|
||||
|
||||
PUBWEAK SDMMC1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SDMMC1_IRQHandler
|
||||
B SDMMC1_IRQHandler
|
||||
|
||||
PUBWEAK I2C3_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C3_EV_IRQHandler
|
||||
B I2C3_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C3_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C3_ER_IRQHandler
|
||||
B I2C3_ER_IRQHandler
|
||||
|
||||
PUBWEAK SPI4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI4_IRQHandler
|
||||
B SPI4_IRQHandler
|
||||
|
||||
PUBWEAK SPI5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI5_IRQHandler
|
||||
B SPI5_IRQHandler
|
||||
|
||||
PUBWEAK SPI6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI6_IRQHandler
|
||||
B SPI6_IRQHandler
|
||||
|
||||
PUBWEAK USART6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART6_IRQHandler
|
||||
B USART6_IRQHandler
|
||||
|
||||
PUBWEAK USART10_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART10_IRQHandler
|
||||
B USART10_IRQHandler
|
||||
|
||||
PUBWEAK USART11_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART11_IRQHandler
|
||||
B USART11_IRQHandler
|
||||
|
||||
PUBWEAK SAI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SAI1_IRQHandler
|
||||
B SAI1_IRQHandler
|
||||
|
||||
PUBWEAK SAI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SAI2_IRQHandler
|
||||
B SAI2_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA2_Channel0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA2_Channel0_IRQHandler
|
||||
B GPDMA2_Channel0_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA2_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA2_Channel1_IRQHandler
|
||||
B GPDMA2_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA2_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA2_Channel2_IRQHandler
|
||||
B GPDMA2_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA2_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA2_Channel3_IRQHandler
|
||||
B GPDMA2_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA2_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA2_Channel4_IRQHandler
|
||||
B GPDMA2_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA2_Channel5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA2_Channel5_IRQHandler
|
||||
B GPDMA2_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA2_Channel6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA2_Channel6_IRQHandler
|
||||
B GPDMA2_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA2_Channel7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA2_Channel7_IRQHandler
|
||||
B GPDMA2_Channel7_IRQHandler
|
||||
|
||||
PUBWEAK UART7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART7_IRQHandler
|
||||
B UART7_IRQHandler
|
||||
|
||||
PUBWEAK UART8_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART8_IRQHandler
|
||||
B UART8_IRQHandler
|
||||
|
||||
PUBWEAK UART9_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART9_IRQHandler
|
||||
B UART9_IRQHandler
|
||||
|
||||
PUBWEAK UART12_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART12_IRQHandler
|
||||
B UART12_IRQHandler
|
||||
|
||||
PUBWEAK SDMMC2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SDMMC2_IRQHandler
|
||||
B SDMMC2_IRQHandler
|
||||
|
||||
PUBWEAK FPU_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FPU_IRQHandler
|
||||
B FPU_IRQHandler
|
||||
|
||||
PUBWEAK ICACHE_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ICACHE_IRQHandler
|
||||
B ICACHE_IRQHandler
|
||||
|
||||
PUBWEAK DCACHE1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DCACHE1_IRQHandler
|
||||
B DCACHE1_IRQHandler
|
||||
|
||||
PUBWEAK ETH_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ETH_IRQHandler
|
||||
B ETH_IRQHandler
|
||||
|
||||
PUBWEAK ETH_WKUP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ETH_WKUP_IRQHandler
|
||||
B ETH_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK DCMI_PSSI_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DCMI_PSSI_IRQHandler
|
||||
B DCMI_PSSI_IRQHandler
|
||||
|
||||
PUBWEAK FDCAN2_IT0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FDCAN2_IT0_IRQHandler
|
||||
B FDCAN2_IT0_IRQHandler
|
||||
|
||||
PUBWEAK FDCAN2_IT1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FDCAN2_IT1_IRQHandler
|
||||
B FDCAN2_IT1_IRQHandler
|
||||
|
||||
PUBWEAK CORDIC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CORDIC_IRQHandler
|
||||
B CORDIC_IRQHandler
|
||||
|
||||
PUBWEAK FMAC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FMAC_IRQHandler
|
||||
B FMAC_IRQHandler
|
||||
|
||||
PUBWEAK DTS_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DTS_IRQHandler
|
||||
B DTS_IRQHandler
|
||||
|
||||
PUBWEAK RNG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RNG_IRQHandler
|
||||
B RNG_IRQHandler
|
||||
|
||||
PUBWEAK HASH_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HASH_IRQHandler
|
||||
B HASH_IRQHandler
|
||||
|
||||
PUBWEAK CEC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CEC_IRQHandler
|
||||
B CEC_IRQHandler
|
||||
|
||||
PUBWEAK TIM12_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM12_IRQHandler
|
||||
B TIM12_IRQHandler
|
||||
|
||||
PUBWEAK TIM13_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM13_IRQHandler
|
||||
B TIM13_IRQHandler
|
||||
|
||||
PUBWEAK TIM14_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM14_IRQHandler
|
||||
B TIM14_IRQHandler
|
||||
|
||||
PUBWEAK I3C1_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I3C1_EV_IRQHandler
|
||||
B I3C1_EV_IRQHandler
|
||||
|
||||
PUBWEAK I3C1_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I3C1_ER_IRQHandler
|
||||
B I3C1_ER_IRQHandler
|
||||
|
||||
PUBWEAK I2C4_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C4_EV_IRQHandler
|
||||
B I2C4_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C4_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C4_ER_IRQHandler
|
||||
B I2C4_ER_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM3_IRQHandler
|
||||
B LPTIM3_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM4_IRQHandler
|
||||
B LPTIM4_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM5_IRQHandler
|
||||
B LPTIM5_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM6_IRQHandler
|
||||
B LPTIM6_IRQHandler
|
||||
|
||||
END
|
||||
|
|
@ -0,0 +1,932 @@
|
|||
;********************************************************************************
|
||||
;* File Name : startup_stm32h573xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : STM32H573xx Crypto Devices vector
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == _iar_program_start,
|
||||
;* - Set the vector table entries with the exceptions ISR
|
||||
;* address.
|
||||
;* - Branches to main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M33 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* Copyright (c) 2023 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;*******************************************************************************
|
||||
;
|
||||
;
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
;
|
||||
; Cortex-M version
|
||||
;
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
PUBLIC __Vectors
|
||||
PUBLIC __Vectors_End
|
||||
PUBLIC __Vectors_Size
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD SecureFault_Handler ; Secure Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection Interrupt
|
||||
DCD RTC_IRQHandler ; RTC non-secure interrupt
|
||||
DCD RTC_S_IRQHandler ; RTC secure interrupt
|
||||
DCD TAMP_IRQHandler ; Tamper non-secure interrupt
|
||||
DCD RAMCFG_IRQHandler ; RAMCFG global
|
||||
DCD FLASH_IRQHandler ; FLASH non-secure global interrupt
|
||||
DCD FLASH_S_IRQHandler ; FLASH secure global interrupt
|
||||
DCD GTZC_IRQHandler ; Global TrustZone Controller interrupt
|
||||
DCD RCC_IRQHandler ; RCC non-secure global interrupt
|
||||
DCD RCC_S_IRQHandler ; RCC secure global interrupt
|
||||
DCD EXTI0_IRQHandler ; EXTI Line0 interrupt
|
||||
DCD EXTI1_IRQHandler ; EXTI Line1 interrupt
|
||||
DCD EXTI2_IRQHandler ; EXTI Line2 interrupt
|
||||
DCD EXTI3_IRQHandler ; EXTI Line3 interrupt
|
||||
DCD EXTI4_IRQHandler ; EXTI Line4 interrupt
|
||||
DCD EXTI5_IRQHandler ; EXTI Line5 interrupt
|
||||
DCD EXTI6_IRQHandler ; EXTI Line6 interrupt
|
||||
DCD EXTI7_IRQHandler ; EXTI Line7 interrupt
|
||||
DCD EXTI8_IRQHandler ; EXTI Line8 interrupt
|
||||
DCD EXTI9_IRQHandler ; EXTI Line9 interrupt
|
||||
DCD EXTI10_IRQHandler ; EXTI Line10 interrupt
|
||||
DCD EXTI11_IRQHandler ; EXTI Line11 interrupt
|
||||
DCD EXTI12_IRQHandler ; EXTI Line12 interrupt
|
||||
DCD EXTI13_IRQHandler ; EXTI Line13 interrupt
|
||||
DCD EXTI14_IRQHandler ; EXTI Line14 interrupt
|
||||
DCD EXTI15_IRQHandler ; EXTI Line15 interrupt
|
||||
DCD GPDMA1_Channel0_IRQHandler ; GPDMA1 Channel 0 global interrupt
|
||||
DCD GPDMA1_Channel1_IRQHandler ; GPDMA1 Channel 1 global interrupt
|
||||
DCD GPDMA1_Channel2_IRQHandler ; GPDMA1 Channel 2 global interrupt
|
||||
DCD GPDMA1_Channel3_IRQHandler ; GPDMA1 Channel 3 global interrupt
|
||||
DCD GPDMA1_Channel4_IRQHandler ; GPDMA1 Channel 4 global interrupt
|
||||
DCD GPDMA1_Channel5_IRQHandler ; GPDMA1 Channel 5 global interrupt
|
||||
DCD GPDMA1_Channel6_IRQHandler ; GPDMA1 Channel 6 global interrupt
|
||||
DCD GPDMA1_Channel7_IRQHandler ; GPDMA1 Channel 7 global interrupt
|
||||
DCD IWDG_IRQHandler ; IWDG global interrupt
|
||||
DCD SAES_IRQHandler ; SAES global interrupt
|
||||
DCD ADC1_IRQHandler ; ADC1 global interrupt
|
||||
DCD DAC1_IRQHandler ; DAC1 global interrupt
|
||||
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt 0
|
||||
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt 1
|
||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
|
||||
DCD TIM1_UP_IRQHandler ; TIM1 Update interrupt
|
||||
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation interrupt
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare interrupt
|
||||
DCD TIM2_IRQHandler ; TIM2 global interrupt
|
||||
DCD TIM3_IRQHandler ; TIM3 global interrupt
|
||||
DCD TIM4_IRQHandler ; TIM4 global interrupt
|
||||
DCD TIM5_IRQHandler ; TIM5 global interrupt
|
||||
DCD TIM6_IRQHandler ; TIM6 global interrupt
|
||||
DCD TIM7_IRQHandler ; TIM7 global interrupt
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event interrupt
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error interrupt
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event interrupt
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error interrupt
|
||||
DCD SPI1_IRQHandler ; SPI1 global interrupt
|
||||
DCD SPI2_IRQHandler ; SPI2 global interrupt
|
||||
DCD SPI3_IRQHandler ; SPI3 global interrupt
|
||||
DCD USART1_IRQHandler ; USART1 global interrupt
|
||||
DCD USART2_IRQHandler ; USART2 global interrupt
|
||||
DCD USART3_IRQHandler ; USART3 global interrupt
|
||||
DCD UART4_IRQHandler ; UART4 global interrupt
|
||||
DCD UART5_IRQHandler ; UART5 global interrupt
|
||||
DCD LPUART1_IRQHandler ; LPUART1 global interrupt
|
||||
DCD LPTIM1_IRQHandler ; LPTIM1 global interrupt
|
||||
DCD TIM8_BRK_IRQHandler ; TIM8 Break interrupt
|
||||
DCD TIM8_UP_IRQHandler ; TIM8 Update interrupt
|
||||
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation interrupt
|
||||
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare interrupt
|
||||
DCD ADC2_IRQHandler ; ADC2 global interrupt
|
||||
DCD LPTIM2_IRQHandler ; LPTIM2 global interrupt
|
||||
DCD TIM15_IRQHandler ; TIM15 global interrupt
|
||||
DCD TIM16_IRQHandler ; TIM16 global interrupt
|
||||
DCD TIM17_IRQHandler ; TIM17 global interrupt
|
||||
DCD USB_DRD_FS_IRQHandler ; USB DRD FS global interrupt
|
||||
DCD CRS_IRQHandler ; CRS global interrupt
|
||||
DCD UCPD1_IRQHandler ; UCPD1 global interrupt
|
||||
DCD FMC_IRQHandler ; FMC global interrupt
|
||||
DCD OCTOSPI1_IRQHandler ; OctoSPI1 global interrupt
|
||||
DCD SDMMC1_IRQHandler ; SDMMC1 global interrupt
|
||||
DCD I2C3_EV_IRQHandler ; I2C2 Event interrupt
|
||||
DCD I2C3_ER_IRQHandler ; I2C2 Error interrupt
|
||||
DCD SPI4_IRQHandler ; SPI4 global interrupt
|
||||
DCD SPI5_IRQHandler ; SPI5 global interrupt
|
||||
DCD SPI6_IRQHandler ; SPI6 global interrupt
|
||||
DCD USART6_IRQHandler ; USART6 global interrupt
|
||||
DCD USART10_IRQHandler ; USART10 global interrupt
|
||||
DCD USART11_IRQHandler ; USART11 global interrupt
|
||||
DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt
|
||||
DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt
|
||||
DCD GPDMA2_Channel0_IRQHandler ; GPDMA2 Channel 0 global interrupt
|
||||
DCD GPDMA2_Channel1_IRQHandler ; GPDMA2 Channel 1 global interrupt
|
||||
DCD GPDMA2_Channel2_IRQHandler ; GPDMA2 Channel 2 global interrupt
|
||||
DCD GPDMA2_Channel3_IRQHandler ; GPDMA2 Channel 3 global interrupt
|
||||
DCD GPDMA2_Channel4_IRQHandler ; GPDMA2 Channel 4 global interrupt
|
||||
DCD GPDMA2_Channel5_IRQHandler ; GPDMA2 Channel 5 global interrupt
|
||||
DCD GPDMA2_Channel6_IRQHandler ; GPDMA2 Channel 6 global interrupt
|
||||
DCD GPDMA2_Channel7_IRQHandler ; GPDMA2 Channel 7 global interrupt
|
||||
DCD UART7_IRQHandler ; UART7 global interrupt
|
||||
DCD UART8_IRQHandler ; UART8 global interrupt
|
||||
DCD UART9_IRQHandler ; UART9 global interrupt
|
||||
DCD UART12_IRQHandler ; UART12 global interrupt
|
||||
DCD SDMMC2_IRQHandler ; SDMMC2 global interrupt
|
||||
DCD FPU_IRQHandler ; FPU global interrupt
|
||||
DCD ICACHE_IRQHandler ; Instruction cache global interrupt
|
||||
DCD DCACHE1_IRQHandler ; DCACHE1 global interrupt
|
||||
DCD ETH_IRQHandler ; Ethernet global interrupt
|
||||
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup global interrupt
|
||||
DCD DCMI_PSSI_IRQHandler ; DCMI PSSI global interrupt
|
||||
DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt 0
|
||||
DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt 1
|
||||
DCD CORDIC_IRQHandler ; CORDIC global interrupt
|
||||
DCD FMAC_IRQHandler ; FMAC global interrupt
|
||||
DCD DTS_IRQHandler ; DTS global interrupt
|
||||
DCD RNG_IRQHandler ; RNG global interrupt
|
||||
DCD OTFDEC1_IRQHandler ; OTFDEC1 global interrupt
|
||||
DCD AES_IRQHandler ; AES global interrupt
|
||||
DCD HASH_IRQHandler ; HASH global interrupt
|
||||
DCD PKA_IRQHandler ; PKA global interrupt
|
||||
DCD CEC_IRQHandler ; CEC global interrupt
|
||||
DCD TIM12_IRQHandler ; TIM12 global interrupt
|
||||
DCD TIM13_IRQHandler ; TIM13 global interrupt
|
||||
DCD TIM14_IRQHandler ; TIM14 global interrupt
|
||||
DCD I3C1_EV_IRQHandler ; I3C1 Event interrupt
|
||||
DCD I3C1_ER_IRQHandler ; I3C1 Error interrupt
|
||||
DCD I2C4_EV_IRQHandler ; I2C4 Event interrupt
|
||||
DCD I2C4_ER_IRQHandler ; I2C4 Error interrupt
|
||||
DCD LPTIM3_IRQHandler ; LPTIM3 global interrupt
|
||||
DCD LPTIM4_IRQHandler ; LPTIM4 global interrupt
|
||||
DCD LPTIM5_IRQHandler ; LPTIM5 global interrupt
|
||||
DCD LPTIM6_IRQHandler ; LPTIM6 global interrupt
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors EQU __vector_table
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||
Reset_Handler
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
NMI_Handler
|
||||
B NMI_Handler
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HardFault_Handler
|
||||
B HardFault_Handler
|
||||
|
||||
PUBWEAK MemManage_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
MemManage_Handler
|
||||
B MemManage_Handler
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
BusFault_Handler
|
||||
B BusFault_Handler
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UsageFault_Handler
|
||||
B UsageFault_Handler
|
||||
|
||||
PUBWEAK SecureFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SecureFault_Handler
|
||||
B SecureFault_Handler
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SVC_Handler
|
||||
B SVC_Handler
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DebugMon_Handler
|
||||
B DebugMon_Handler
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PendSV_Handler
|
||||
B PendSV_Handler
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SysTick_Handler
|
||||
B SysTick_Handler
|
||||
|
||||
PUBWEAK WWDG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
WWDG_IRQHandler
|
||||
B WWDG_IRQHandler
|
||||
|
||||
PUBWEAK PVD_AVD_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PVD_AVD_IRQHandler
|
||||
B PVD_AVD_IRQHandler
|
||||
|
||||
PUBWEAK RTC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_IRQHandler
|
||||
B RTC_IRQHandler
|
||||
|
||||
PUBWEAK RTC_S_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_S_IRQHandler
|
||||
B RTC_S_IRQHandler
|
||||
|
||||
PUBWEAK TAMP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TAMP_IRQHandler
|
||||
B TAMP_IRQHandler
|
||||
|
||||
PUBWEAK RAMCFG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RAMCFG_IRQHandler
|
||||
B RAMCFG_IRQHandler
|
||||
|
||||
PUBWEAK FLASH_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FLASH_IRQHandler
|
||||
B FLASH_IRQHandler
|
||||
|
||||
PUBWEAK FLASH_S_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FLASH_S_IRQHandler
|
||||
B FLASH_S_IRQHandler
|
||||
|
||||
PUBWEAK GTZC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GTZC_IRQHandler
|
||||
B GTZC_IRQHandler
|
||||
|
||||
PUBWEAK RCC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RCC_IRQHandler
|
||||
B RCC_IRQHandler
|
||||
|
||||
PUBWEAK RCC_S_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RCC_S_IRQHandler
|
||||
B RCC_S_IRQHandler
|
||||
|
||||
PUBWEAK EXTI0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI0_IRQHandler
|
||||
B EXTI0_IRQHandler
|
||||
|
||||
PUBWEAK EXTI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI1_IRQHandler
|
||||
B EXTI1_IRQHandler
|
||||
|
||||
PUBWEAK EXTI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI2_IRQHandler
|
||||
B EXTI2_IRQHandler
|
||||
|
||||
PUBWEAK EXTI3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI3_IRQHandler
|
||||
B EXTI3_IRQHandler
|
||||
|
||||
PUBWEAK EXTI4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI4_IRQHandler
|
||||
B EXTI4_IRQHandler
|
||||
|
||||
PUBWEAK EXTI5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI5_IRQHandler
|
||||
B EXTI5_IRQHandler
|
||||
|
||||
PUBWEAK EXTI6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI6_IRQHandler
|
||||
B EXTI6_IRQHandler
|
||||
|
||||
PUBWEAK EXTI7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI7_IRQHandler
|
||||
B EXTI7_IRQHandler
|
||||
|
||||
PUBWEAK EXTI8_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI8_IRQHandler
|
||||
B EXTI8_IRQHandler
|
||||
|
||||
PUBWEAK EXTI9_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI9_IRQHandler
|
||||
B EXTI9_IRQHandler
|
||||
|
||||
PUBWEAK EXTI10_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI10_IRQHandler
|
||||
B EXTI10_IRQHandler
|
||||
|
||||
PUBWEAK EXTI11_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI11_IRQHandler
|
||||
B EXTI11_IRQHandler
|
||||
|
||||
PUBWEAK EXTI12_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI12_IRQHandler
|
||||
B EXTI12_IRQHandler
|
||||
|
||||
PUBWEAK EXTI13_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI13_IRQHandler
|
||||
B EXTI13_IRQHandler
|
||||
|
||||
PUBWEAK EXTI14_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI14_IRQHandler
|
||||
B EXTI14_IRQHandler
|
||||
|
||||
PUBWEAK EXTI15_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI15_IRQHandler
|
||||
B EXTI15_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA1_Channel0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA1_Channel0_IRQHandler
|
||||
B GPDMA1_Channel0_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA1_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA1_Channel1_IRQHandler
|
||||
B GPDMA1_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA1_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA1_Channel2_IRQHandler
|
||||
B GPDMA1_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA1_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA1_Channel3_IRQHandler
|
||||
B GPDMA1_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA1_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA1_Channel4_IRQHandler
|
||||
B GPDMA1_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA1_Channel5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA1_Channel5_IRQHandler
|
||||
B GPDMA1_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA1_Channel6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA1_Channel6_IRQHandler
|
||||
B GPDMA1_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA1_Channel7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA1_Channel7_IRQHandler
|
||||
B GPDMA1_Channel7_IRQHandler
|
||||
|
||||
PUBWEAK IWDG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IWDG_IRQHandler
|
||||
B IWDG_IRQHandler
|
||||
|
||||
PUBWEAK SAES_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SAES_IRQHandler
|
||||
B SAES_IRQHandler
|
||||
|
||||
PUBWEAK ADC1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ADC1_IRQHandler
|
||||
B ADC1_IRQHandler
|
||||
|
||||
PUBWEAK DAC1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DAC1_IRQHandler
|
||||
B DAC1_IRQHandler
|
||||
|
||||
PUBWEAK FDCAN1_IT0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FDCAN1_IT0_IRQHandler
|
||||
B FDCAN1_IT0_IRQHandler
|
||||
|
||||
PUBWEAK FDCAN1_IT1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FDCAN1_IT1_IRQHandler
|
||||
B FDCAN1_IT1_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_BRK_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_BRK_IRQHandler
|
||||
B TIM1_BRK_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_UP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_UP_IRQHandler
|
||||
B TIM1_UP_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_TRG_COM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_TRG_COM_IRQHandler
|
||||
B TIM1_TRG_COM_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_CC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_CC_IRQHandler
|
||||
B TIM1_CC_IRQHandler
|
||||
|
||||
PUBWEAK TIM2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM2_IRQHandler
|
||||
B TIM2_IRQHandler
|
||||
|
||||
PUBWEAK TIM3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM3_IRQHandler
|
||||
B TIM3_IRQHandler
|
||||
|
||||
PUBWEAK TIM4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM4_IRQHandler
|
||||
B TIM4_IRQHandler
|
||||
|
||||
PUBWEAK TIM5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM5_IRQHandler
|
||||
B TIM5_IRQHandler
|
||||
|
||||
PUBWEAK TIM6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM6_IRQHandler
|
||||
B TIM6_IRQHandler
|
||||
|
||||
PUBWEAK TIM7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM7_IRQHandler
|
||||
B TIM7_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_EV_IRQHandler
|
||||
B I2C1_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_ER_IRQHandler
|
||||
B I2C1_ER_IRQHandler
|
||||
|
||||
PUBWEAK I2C2_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C2_EV_IRQHandler
|
||||
B I2C2_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C2_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C2_ER_IRQHandler
|
||||
B I2C2_ER_IRQHandler
|
||||
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI1_IRQHandler
|
||||
B SPI1_IRQHandler
|
||||
|
||||
PUBWEAK SPI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI2_IRQHandler
|
||||
B SPI2_IRQHandler
|
||||
|
||||
PUBWEAK SPI3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI3_IRQHandler
|
||||
B SPI3_IRQHandler
|
||||
|
||||
PUBWEAK USART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART1_IRQHandler
|
||||
B USART1_IRQHandler
|
||||
|
||||
PUBWEAK USART2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART2_IRQHandler
|
||||
B USART2_IRQHandler
|
||||
|
||||
PUBWEAK USART3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART3_IRQHandler
|
||||
B USART3_IRQHandler
|
||||
|
||||
PUBWEAK UART4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART4_IRQHandler
|
||||
B UART4_IRQHandler
|
||||
|
||||
PUBWEAK UART5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART5_IRQHandler
|
||||
B UART5_IRQHandler
|
||||
|
||||
PUBWEAK LPUART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPUART1_IRQHandler
|
||||
B LPUART1_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM1_IRQHandler
|
||||
B LPTIM1_IRQHandler
|
||||
|
||||
PUBWEAK TIM8_BRK_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM8_BRK_IRQHandler
|
||||
B TIM8_BRK_IRQHandler
|
||||
|
||||
PUBWEAK TIM8_UP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM8_UP_IRQHandler
|
||||
B TIM8_UP_IRQHandler
|
||||
|
||||
PUBWEAK TIM8_TRG_COM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM8_TRG_COM_IRQHandler
|
||||
B TIM8_TRG_COM_IRQHandler
|
||||
|
||||
PUBWEAK TIM8_CC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM8_CC_IRQHandler
|
||||
B TIM8_CC_IRQHandler
|
||||
|
||||
PUBWEAK ADC2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ADC2_IRQHandler
|
||||
B ADC2_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM2_IRQHandler
|
||||
B LPTIM2_IRQHandler
|
||||
|
||||
PUBWEAK TIM15_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM15_IRQHandler
|
||||
B TIM15_IRQHandler
|
||||
|
||||
PUBWEAK TIM16_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM16_IRQHandler
|
||||
B TIM16_IRQHandler
|
||||
|
||||
PUBWEAK TIM17_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM17_IRQHandler
|
||||
B TIM17_IRQHandler
|
||||
|
||||
PUBWEAK USB_DRD_FS_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USB_DRD_FS_IRQHandler
|
||||
B USB_DRD_FS_IRQHandler
|
||||
|
||||
PUBWEAK CRS_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CRS_IRQHandler
|
||||
B CRS_IRQHandler
|
||||
|
||||
PUBWEAK UCPD1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UCPD1_IRQHandler
|
||||
B UCPD1_IRQHandler
|
||||
|
||||
PUBWEAK FMC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FMC_IRQHandler
|
||||
B FMC_IRQHandler
|
||||
|
||||
PUBWEAK OCTOSPI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
OCTOSPI1_IRQHandler
|
||||
B OCTOSPI1_IRQHandler
|
||||
|
||||
PUBWEAK SDMMC1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SDMMC1_IRQHandler
|
||||
B SDMMC1_IRQHandler
|
||||
|
||||
PUBWEAK I2C3_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C3_EV_IRQHandler
|
||||
B I2C3_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C3_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C3_ER_IRQHandler
|
||||
B I2C3_ER_IRQHandler
|
||||
|
||||
PUBWEAK SPI4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI4_IRQHandler
|
||||
B SPI4_IRQHandler
|
||||
|
||||
PUBWEAK SPI5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI5_IRQHandler
|
||||
B SPI5_IRQHandler
|
||||
|
||||
PUBWEAK SPI6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI6_IRQHandler
|
||||
B SPI6_IRQHandler
|
||||
|
||||
PUBWEAK USART6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART6_IRQHandler
|
||||
B USART6_IRQHandler
|
||||
|
||||
PUBWEAK USART10_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART10_IRQHandler
|
||||
B USART10_IRQHandler
|
||||
|
||||
PUBWEAK USART11_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART11_IRQHandler
|
||||
B USART11_IRQHandler
|
||||
|
||||
PUBWEAK SAI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SAI1_IRQHandler
|
||||
B SAI1_IRQHandler
|
||||
|
||||
PUBWEAK SAI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SAI2_IRQHandler
|
||||
B SAI2_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA2_Channel0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA2_Channel0_IRQHandler
|
||||
B GPDMA2_Channel0_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA2_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA2_Channel1_IRQHandler
|
||||
B GPDMA2_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA2_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA2_Channel2_IRQHandler
|
||||
B GPDMA2_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA2_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA2_Channel3_IRQHandler
|
||||
B GPDMA2_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA2_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA2_Channel4_IRQHandler
|
||||
B GPDMA2_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA2_Channel5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA2_Channel5_IRQHandler
|
||||
B GPDMA2_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA2_Channel6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA2_Channel6_IRQHandler
|
||||
B GPDMA2_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA2_Channel7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA2_Channel7_IRQHandler
|
||||
B GPDMA2_Channel7_IRQHandler
|
||||
|
||||
PUBWEAK UART7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART7_IRQHandler
|
||||
B UART7_IRQHandler
|
||||
|
||||
PUBWEAK UART8_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART8_IRQHandler
|
||||
B UART8_IRQHandler
|
||||
|
||||
PUBWEAK UART9_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART9_IRQHandler
|
||||
B UART9_IRQHandler
|
||||
|
||||
PUBWEAK UART12_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART12_IRQHandler
|
||||
B UART12_IRQHandler
|
||||
|
||||
PUBWEAK SDMMC2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SDMMC2_IRQHandler
|
||||
B SDMMC2_IRQHandler
|
||||
|
||||
PUBWEAK FPU_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FPU_IRQHandler
|
||||
B FPU_IRQHandler
|
||||
|
||||
PUBWEAK ICACHE_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ICACHE_IRQHandler
|
||||
B ICACHE_IRQHandler
|
||||
|
||||
PUBWEAK DCACHE1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DCACHE1_IRQHandler
|
||||
B DCACHE1_IRQHandler
|
||||
|
||||
PUBWEAK ETH_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ETH_IRQHandler
|
||||
B ETH_IRQHandler
|
||||
|
||||
PUBWEAK ETH_WKUP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ETH_WKUP_IRQHandler
|
||||
B ETH_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK DCMI_PSSI_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DCMI_PSSI_IRQHandler
|
||||
B DCMI_PSSI_IRQHandler
|
||||
|
||||
PUBWEAK FDCAN2_IT0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FDCAN2_IT0_IRQHandler
|
||||
B FDCAN2_IT0_IRQHandler
|
||||
|
||||
PUBWEAK FDCAN2_IT1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FDCAN2_IT1_IRQHandler
|
||||
B FDCAN2_IT1_IRQHandler
|
||||
|
||||
PUBWEAK CORDIC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CORDIC_IRQHandler
|
||||
B CORDIC_IRQHandler
|
||||
|
||||
PUBWEAK FMAC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FMAC_IRQHandler
|
||||
B FMAC_IRQHandler
|
||||
|
||||
PUBWEAK DTS_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DTS_IRQHandler
|
||||
B DTS_IRQHandler
|
||||
|
||||
PUBWEAK RNG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RNG_IRQHandler
|
||||
B RNG_IRQHandler
|
||||
|
||||
PUBWEAK OTFDEC1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
OTFDEC1_IRQHandler
|
||||
B OTFDEC1_IRQHandler
|
||||
|
||||
PUBWEAK AES_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
AES_IRQHandler
|
||||
B AES_IRQHandler
|
||||
|
||||
PUBWEAK HASH_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HASH_IRQHandler
|
||||
B HASH_IRQHandler
|
||||
|
||||
PUBWEAK PKA_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PKA_IRQHandler
|
||||
B PKA_IRQHandler
|
||||
|
||||
PUBWEAK CEC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CEC_IRQHandler
|
||||
B CEC_IRQHandler
|
||||
|
||||
PUBWEAK TIM12_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM12_IRQHandler
|
||||
B TIM12_IRQHandler
|
||||
|
||||
PUBWEAK TIM13_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM13_IRQHandler
|
||||
B TIM13_IRQHandler
|
||||
|
||||
PUBWEAK TIM14_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM14_IRQHandler
|
||||
B TIM14_IRQHandler
|
||||
|
||||
PUBWEAK I3C1_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I3C1_EV_IRQHandler
|
||||
B I3C1_EV_IRQHandler
|
||||
|
||||
PUBWEAK I3C1_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I3C1_ER_IRQHandler
|
||||
B I3C1_ER_IRQHandler
|
||||
|
||||
PUBWEAK I2C4_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C4_EV_IRQHandler
|
||||
B I2C4_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C4_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C4_ER_IRQHandler
|
||||
B I2C4_ER_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM3_IRQHandler
|
||||
B LPTIM3_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM4_IRQHandler
|
||||
B LPTIM4_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM5_IRQHandler
|
||||
B LPTIM5_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM6_IRQHandler
|
||||
B LPTIM6_IRQHandler
|
||||
|
||||
END
|
||||
|
|
@ -0,0 +1,401 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32h5xx.c
|
||||
* @author MCD Application Team
|
||||
* @brief CMSIS Cortex-M33 Device Peripheral Access Layer System Source File
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
* This file provides two functions and one global variable to be called from
|
||||
* user application:
|
||||
* - SystemInit(): This function is called at startup just after reset and
|
||||
* before branch to main program. This call is made inside
|
||||
* the "startup_stm32h5xx.s" file.
|
||||
*
|
||||
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
|
||||
* by the user application to setup the SysTick
|
||||
* timer or configure other parameters.
|
||||
*
|
||||
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
|
||||
* be called whenever the core clock is changed
|
||||
* during program execution.
|
||||
*
|
||||
* After each device reset the HSI (64 MHz) is used as system clock source.
|
||||
* Then SystemInit() function is called, in "startup_stm32h5xx.s" file, to
|
||||
* configure the system clock before to branch to main program.
|
||||
*
|
||||
* This file configures the system clock as follows:
|
||||
*=============================================================================
|
||||
*-----------------------------------------------------------------------------
|
||||
* System Clock source | HSI
|
||||
*-----------------------------------------------------------------------------
|
||||
* SYSCLK(Hz) | 64000000
|
||||
*-----------------------------------------------------------------------------
|
||||
* HCLK(Hz) | 64000000
|
||||
*-----------------------------------------------------------------------------
|
||||
* AHB Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB1 Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB2 Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB3 Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* HSI Division factor | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL1_SRC | No clock
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL1_M | Prescaler disabled
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL1_N | 129
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL1_P | 2
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL1_Q | 2
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL1_R | 2
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL1_FRACN | 0
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL2_SRC | No clock
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL2_M | Prescaler disabled
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL2_N | 129
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL2_P | 2
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL2_Q | 2
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL2_R | 2
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL2_FRACN | 0
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL3_SRC | No clock
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL3_M | Prescaler disabled
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL3_N | 129
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL3_P | 2
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL3_Q | 2
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL3_R | 2
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL3_FRACN | 0
|
||||
*-----------------------------------------------------------------------------
|
||||
*=============================================================================
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H5xx_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H5xx_System_Private_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "stm32h5xx.h"
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H5xx_System_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H5xx_System_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if !defined (HSE_VALUE)
|
||||
#define HSE_VALUE (25000000UL) /*!< Value of the External oscillator in Hz */
|
||||
#endif /* HSE_VALUE */
|
||||
|
||||
#if !defined (CSI_VALUE)
|
||||
#define CSI_VALUE (4000000UL) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* CSI_VALUE */
|
||||
|
||||
#if !defined (HSI_VALUE)
|
||||
#define HSI_VALUE (64000000UL) /*!< Value of the Internal oscillator in Hz */
|
||||
#endif /* HSI_VALUE */
|
||||
|
||||
/************************* Miscellaneous Configuration ************************/
|
||||
/*!< Uncomment the following line if you need to relocate your vector Table in
|
||||
Internal SRAM. */
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#define VECT_TAB_OFFSET 0x00U /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H5xx_System_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H5xx_System_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
/* The SystemCoreClock variable is updated in three ways:
|
||||
1) by calling CMSIS function SystemCoreClockUpdate()
|
||||
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
|
||||
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
|
||||
Note: If you use this function to configure the system clock; then there
|
||||
is no need to call the 2 first functions listed above, since SystemCoreClock
|
||||
variable is updated automatically.
|
||||
*/
|
||||
uint32_t SystemCoreClock = 64000000U;
|
||||
|
||||
const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
|
||||
const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H5xx_System_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H5xx_System_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void SystemInit(void)
|
||||
{
|
||||
uint32_t reg_opsr;
|
||||
|
||||
/* FPU settings ------------------------------------------------------------*/
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */
|
||||
#endif
|
||||
|
||||
/* Reset the RCC clock configuration to the default reset state ------------*/
|
||||
/* Set HSION bit */
|
||||
RCC->CR = RCC_CR_HSION;
|
||||
|
||||
/* Reset CFGR register */
|
||||
RCC->CFGR1 = 0U;
|
||||
RCC->CFGR2 = 0U;
|
||||
|
||||
/* Reset HSEON, HSECSSON, HSEBYP, HSEEXT, HSIDIV, HSIKERON, CSION, CSIKERON, HSI48 and PLLxON bits */
|
||||
#if defined(RCC_CR_PLL3ON)
|
||||
RCC->CR &= ~(RCC_CR_HSEON | RCC_CR_HSECSSON | RCC_CR_HSEBYP | RCC_CR_HSEEXT | RCC_CR_HSIDIV | RCC_CR_HSIKERON | \
|
||||
RCC_CR_CSION | RCC_CR_CSIKERON |RCC_CR_HSI48ON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON);
|
||||
#else
|
||||
RCC->CR &= ~(RCC_CR_HSEON | RCC_CR_HSECSSON | RCC_CR_HSEBYP | RCC_CR_HSEEXT | RCC_CR_HSIDIV | RCC_CR_HSIKERON | \
|
||||
RCC_CR_CSION | RCC_CR_CSIKERON |RCC_CR_HSI48ON | RCC_CR_PLL1ON | RCC_CR_PLL2ON);
|
||||
#endif
|
||||
|
||||
/* Reset PLLxCFGR register */
|
||||
RCC->PLL1CFGR = 0U;
|
||||
RCC->PLL2CFGR = 0U;
|
||||
#if defined(RCC_CR_PLL3ON)
|
||||
RCC->PLL3CFGR = 0U;
|
||||
#endif /* RCC_CR_PLL3ON */
|
||||
|
||||
/* Reset PLL1DIVR register */
|
||||
RCC->PLL1DIVR = 0x01010280U;
|
||||
/* Reset PLL1FRACR register */
|
||||
RCC->PLL1FRACR = 0x00000000U;
|
||||
/* Reset PLL2DIVR register */
|
||||
RCC->PLL2DIVR = 0x01010280U;
|
||||
/* Reset PLL2FRACR register */
|
||||
RCC->PLL2FRACR = 0x00000000U;
|
||||
#if defined(RCC_CR_PLL3ON)
|
||||
/* Reset PLL3DIVR register */
|
||||
RCC->PLL3DIVR = 0x01010280U;
|
||||
/* Reset PLL3FRACR register */
|
||||
RCC->PLL3FRACR = 0x00000000U;
|
||||
#endif /* RCC_CR_PLL3ON */
|
||||
|
||||
/* Reset HSEBYP bit */
|
||||
RCC->CR &= ~(RCC_CR_HSEBYP);
|
||||
|
||||
/* Disable all interrupts */
|
||||
RCC->CIER = 0U;
|
||||
|
||||
/* Configure the Vector Table location add offset address ------------------*/
|
||||
#ifdef VECT_TAB_SRAM
|
||||
SCB->VTOR = SRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
||||
#else
|
||||
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
|
||||
#endif /* VECT_TAB_SRAM */
|
||||
|
||||
/* Check OPSR register to verify if there is an ongoing swap or option bytes update interrupted by a reset */
|
||||
reg_opsr = FLASH->OPSR & FLASH_OPSR_CODE_OP;
|
||||
if ((reg_opsr == FLASH_OPSR_CODE_OP) || (reg_opsr == (FLASH_OPSR_CODE_OP_2 | FLASH_OPSR_CODE_OP_1)))
|
||||
{
|
||||
/* Check FLASH Option Control Register access */
|
||||
if ((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != 0U)
|
||||
{
|
||||
/* Authorizes the Option Byte registers programming */
|
||||
FLASH->OPTKEYR = 0x08192A3BU;
|
||||
FLASH->OPTKEYR = 0x4C5D6E7FU;
|
||||
}
|
||||
/* Launch the option bytes change operation */
|
||||
FLASH->OPTCR |= FLASH_OPTCR_OPTSTART;
|
||||
|
||||
/* Lock the FLASH Option Control Register access */
|
||||
FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
* The SystemCoreClock variable contains the core clock (HCLK), it can
|
||||
* be used by the user application to setup the SysTick timer or configure
|
||||
* other parameters.
|
||||
*
|
||||
* @note Each time the core clock (HCLK) changes, this function must be called
|
||||
* to update SystemCoreClock variable value. Otherwise, any configuration
|
||||
* based on this variable will be incorrect.
|
||||
*
|
||||
* @note - The system frequency computed by this function is not the real
|
||||
* frequency in the chip. It is calculated based on the predefined
|
||||
* constant and the selected clock source:
|
||||
*
|
||||
* - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*)
|
||||
*
|
||||
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
|
||||
*
|
||||
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
|
||||
*
|
||||
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
|
||||
* or HSI_VALUE(**) or CSI_VALUE(*) multiplied/divided by the PLL factors.
|
||||
*
|
||||
* (*) CSI_VALUE is a constant defined in stm32h5xx_hal.h file (default value
|
||||
* 4 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (**) HSI_VALUE is a constant defined in stm32h5xx_hal.h file (default value
|
||||
* 64 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (***) HSE_VALUE is a constant defined in stm32h5xx_hal.h file (default value
|
||||
* 25 MHz), user has to ensure that HSE_VALUE is same as the real
|
||||
* frequency of the crystal used. Otherwise, this function may
|
||||
* have wrong result.
|
||||
*
|
||||
* - The result of this function could be not correct when using fractional
|
||||
* value for HSE crystal.
|
||||
*
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
|
||||
float_t fracn1, pllvco;
|
||||
|
||||
/* Get SYSCLK source -------------------------------------------------------*/
|
||||
switch (RCC->CFGR1 & RCC_CFGR1_SWS)
|
||||
{
|
||||
case 0x00UL: /* HSI used as system clock source */
|
||||
SystemCoreClock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
|
||||
break;
|
||||
|
||||
case 0x08UL: /* CSI used as system clock source */
|
||||
SystemCoreClock = CSI_VALUE;
|
||||
break;
|
||||
|
||||
case 0x10UL: /* HSE used as system clock source */
|
||||
SystemCoreClock = HSE_VALUE;
|
||||
break;
|
||||
|
||||
case 0x18UL: /* PLL1 used as system clock source */
|
||||
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
|
||||
SYSCLK = PLL_VCO / PLLR
|
||||
*/
|
||||
pllsource = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC);
|
||||
pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M)>> RCC_PLL1CFGR_PLL1M_Pos);
|
||||
pllfracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN)>>RCC_PLL1CFGR_PLL1FRACEN_Pos);
|
||||
fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN)>> RCC_PLL1FRACR_PLL1FRACN_Pos));
|
||||
|
||||
switch (pllsource)
|
||||
{
|
||||
case 0x01UL: /* HSI used as PLL clock source */
|
||||
hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
|
||||
pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \
|
||||
(fracn1/(float_t)0x2000) +(float_t)1 );
|
||||
break;
|
||||
|
||||
case 0x02UL: /* CSI used as PLL clock source */
|
||||
pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \
|
||||
(fracn1/(float_t)0x2000) +(float_t)1 );
|
||||
break;
|
||||
|
||||
case 0x03UL: /* HSE used as PLL clock source */
|
||||
pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \
|
||||
(fracn1/(float_t)0x2000) +(float_t)1 );
|
||||
break;
|
||||
|
||||
default: /* No clock sent to PLL*/
|
||||
pllvco = (float_t) 0U;
|
||||
break;
|
||||
}
|
||||
|
||||
pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1P) >>RCC_PLL1DIVR_PLL1P_Pos) + 1U ) ;
|
||||
SystemCoreClock = (uint32_t)(float_t)(pllvco/(float_t)pllp);
|
||||
|
||||
break;
|
||||
|
||||
default:
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
}
|
||||
/* Compute HCLK clock frequency --------------------------------------------*/
|
||||
/* Get HCLK prescaler */
|
||||
tmp = AHBPrescTable[((RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos)];
|
||||
/* HCLK clock frequency */
|
||||
SystemCoreClock >>= tmp;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
|
@ -0,0 +1,208 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32h5xx_ns.c
|
||||
* @author MCD Application Team
|
||||
* @brief CMSIS Cortex-M33 Device Peripheral Access Layer System Source File
|
||||
* to be used in non-secure application when the system implements
|
||||
* the TrustZone-M security.
|
||||
*
|
||||
* This file provides two functions and one global variable to be called from
|
||||
* user application:
|
||||
* - SystemInit(): This function is called at non-secure startup before
|
||||
* branch to non-secure main program.
|
||||
* This call is made inside the "startup_stm32h5xx.s" file.
|
||||
*
|
||||
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
|
||||
* by the user application to setup the SysTick
|
||||
* timer or configure other parameters.
|
||||
*
|
||||
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
|
||||
* be called whenever the core clock is changed
|
||||
* during program execution.
|
||||
*
|
||||
* After each device reset the HSI (64 MHz) is used as system clock source.
|
||||
* Then SystemInit() function is called, in "startup_stm32h5xx.s" file, to
|
||||
* configure the system clock before to branch to main secure program.
|
||||
* Later, when non-secure SystemInit() function is called, in "startup_stm32h5xx.s"
|
||||
* file, the system clock may have been updated from reset value by the main
|
||||
* secure program.
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H5xx_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H5xx_System_Private_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "stm32h5xx.h"
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H5xx_System_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H5xx_System_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if !defined (HSE_VALUE)
|
||||
#define HSE_VALUE (25000000UL) /*!< Value of the External oscillator in Hz */
|
||||
#endif /* HSE_VALUE */
|
||||
|
||||
#if !defined (CSI_VALUE)
|
||||
#define CSI_VALUE (4000000UL) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* CSI_VALUE */
|
||||
|
||||
#if !defined (HSI_VALUE)
|
||||
#define HSI_VALUE (64000000UL) /*!< Value of the Internal oscillator in Hz */
|
||||
#endif /* HSI_VALUE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H5xx_System_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H5xx_System_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
/* The SystemCoreClock variable is updated in three ways:
|
||||
1) by calling CMSIS function SystemCoreClockUpdate()
|
||||
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
|
||||
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
|
||||
Note: If you use this function to configure the system clock; then there
|
||||
is no need to call the 2 first functions listed above, since SystemCoreClock
|
||||
variable is updated automatically.
|
||||
*/
|
||||
uint32_t SystemCoreClock = 64000000U;
|
||||
|
||||
const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
|
||||
const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H5xx_System_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H5xx_System_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* Nothing done in non-secure */
|
||||
|
||||
/* Non-secure main application shall call SystemCoreClockUpdate() to update */
|
||||
/* the SystemCoreClock variable to insure non-secure application relies on */
|
||||
/* the initial clock reference set by secure application. */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
* The SystemCoreClock variable contains the core clock (HCLK), it can
|
||||
* be used by the user application to setup the SysTick timer or configure
|
||||
* other parameters.
|
||||
*
|
||||
* @note From the non-secure application, the SystemCoreClock value is
|
||||
* retrieved from the secure domain via a Non-Secure Callable function
|
||||
* since the RCC peripheral may be protected with security attributes
|
||||
* that prevent to compute the SystemCoreClock variable from the RCC
|
||||
* peripheral registers.
|
||||
*
|
||||
* @note Each time the core clock (HCLK) changes, this function must be called
|
||||
* to update SystemCoreClock variable value. Otherwise, any configuration
|
||||
* based on this variable will be incorrect.
|
||||
*
|
||||
* @note - The system frequency computed by this function is not the real
|
||||
* frequency in the chip. It is calculated based on the predefined
|
||||
* constant and the selected clock source:
|
||||
*
|
||||
* - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*)
|
||||
*
|
||||
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
|
||||
*
|
||||
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
|
||||
*
|
||||
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
|
||||
* or HSI_VALUE(**) or CSI_VALUE(*) multiplied/divided by the PLL factors.
|
||||
*
|
||||
* (*) CSI_VALUE is a constant defined in stm32h5xx_hal.h file (default value
|
||||
* 4 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (**) HSI_VALUE is a constant defined in stm32h5xx_hal.h file (default value
|
||||
* 64 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (***) HSE_VALUE is a constant defined in stm32h5xx_hal.h file (default value
|
||||
* 25 MHz), user has to ensure that HSE_VALUE is same as the real
|
||||
* frequency of the crystal used. Otherwise, this function may
|
||||
* have wrong result.
|
||||
*
|
||||
* - The result of this function could be not correct when using fractional
|
||||
* value for HSE crystal.
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
/* Get the SystemCoreClock value from the secure domain */
|
||||
SystemCoreClock = SECURE_SystemCoreClockUpdate();
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
|
@ -0,0 +1,430 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32h5xx_s.c
|
||||
* @author MCD Application Team
|
||||
* @brief CMSIS Cortex-M33 Device Peripheral Access Layer System Source File
|
||||
* to be used in secure application when the system implements
|
||||
* the security.
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
* This file provides two functions and one global variable to be called from
|
||||
* user application:
|
||||
* - SystemInit(): This function is called at startup just after reset and
|
||||
* before branch to main program. This call is made inside
|
||||
* the "startup_stm32h5xx.s" file.
|
||||
*
|
||||
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
|
||||
* by the user application to setup the SysTick
|
||||
* timer or configure other parameters.
|
||||
*
|
||||
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
|
||||
* be called whenever the core clock is changed
|
||||
* during program execution.
|
||||
*
|
||||
* - SECURE_SystemCoreClockUpdate(): Non-secure callable function to update
|
||||
* the variable SystemCoreClock and return
|
||||
* its value to the non-secure calling
|
||||
* application. It must be called whenever
|
||||
* the core clock is changed during program
|
||||
* execution.
|
||||
*
|
||||
* After each device reset the HSI (64 MHz) is used as system clock source.
|
||||
* Then SystemInit() function is called, in "startup_stm32h5xx.s" file, to
|
||||
* configure the system clock before to branch to main program.
|
||||
*
|
||||
* This file configures the system clock as follows:
|
||||
*=============================================================================
|
||||
*-----------------------------------------------------------------------------
|
||||
* System Clock source | HSI
|
||||
*-----------------------------------------------------------------------------
|
||||
* SYSCLK(Hz) | 64000000
|
||||
*-----------------------------------------------------------------------------
|
||||
* HCLK(Hz) | 64000000
|
||||
*-----------------------------------------------------------------------------
|
||||
* AHB Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB1 Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB2 Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB3 Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* HSI Division factor | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL1_SRC | No clock
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL1_M | Prescaler disabled
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL1_N | 129
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL1_P | 2
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL1_Q | 2
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL1_R | 2
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL1_FRACN | 0
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL2_SRC | No clock
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL2_M | Prescaler disabled
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL2_N | 129
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL2_P | 2
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL2_Q | 2
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL2_R | 2
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL2_FRACN | 0
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL3_SRC | No clock
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL3_M | Prescaler disabled
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL3_N | 129
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL3_P | 2
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL3_Q | 2
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL3_R | 2
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL3_FRACN | 0
|
||||
*-----------------------------------------------------------------------------
|
||||
*=============================================================================
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H5xx_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H5xx_System_Private_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "stm32h5xx.h"
|
||||
#include "partition_stm32h5xx.h" /* Trustzone-M core secure attributes */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H5xx_System_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
# define CMSE_NS_ENTRY __cmse_nonsecure_entry
|
||||
#else
|
||||
# define CMSE_NS_ENTRY __attribute((cmse_nonsecure_entry))
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H5xx_System_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
#if !defined (HSE_VALUE)
|
||||
#define HSE_VALUE (25000000UL) /*!< Value of the External oscillator in Hz */
|
||||
#endif /* HSE_VALUE */
|
||||
|
||||
#if !defined (CSI_VALUE)
|
||||
#define CSI_VALUE (4000000UL) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* CSI_VALUE */
|
||||
|
||||
#if !defined (HSI_VALUE)
|
||||
#define HSI_VALUE (64000000UL) /*!< Value of the Internal oscillator in Hz */
|
||||
#endif /* HSI_VALUE */
|
||||
|
||||
/************************* Miscellaneous Configuration ************************/
|
||||
/*!< Uncomment the following line if you need to relocate your vector Table in
|
||||
Internal SRAM. */
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#define VECT_TAB_OFFSET 0x00U /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H5xx_System_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H5xx_System_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
/* The SystemCoreClock variable is updated in three ways:
|
||||
1) by calling CMSIS function SystemCoreClockUpdate()
|
||||
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
|
||||
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
|
||||
Note: If you use this function to configure the system clock; then there
|
||||
is no need to call the 2 first functions listed above, since SystemCoreClock
|
||||
variable is updated automatically.
|
||||
*/
|
||||
uint32_t SystemCoreClock = 64000000U;
|
||||
|
||||
const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
|
||||
const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H5xx_System_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H5xx_System_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void SystemInit(void)
|
||||
{
|
||||
uint32_t reg_opsr;
|
||||
|
||||
/* SAU/IDAU, FPU and Interrupts secure/non-secure allocation settings */
|
||||
TZ_SAU_Setup();
|
||||
|
||||
/* FPU settings ------------------------------------------------------------*/
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */
|
||||
|
||||
SCB_NS->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */
|
||||
#endif
|
||||
|
||||
/* Reset the RCC clock configuration to the default reset state ------------*/
|
||||
/* Set HSION bit */
|
||||
RCC->CR = RCC_CR_HSION;
|
||||
|
||||
/* Reset CFGR register */
|
||||
RCC->CFGR1 = 0U;
|
||||
RCC->CFGR2 = 0U;
|
||||
|
||||
/* Reset HSEON, HSECSSON, HSEBYP, HSEEXT, HSIDIV, HSIKERON, CSION, CSIKERON, HSI48 and PLLxON bits */
|
||||
RCC->CR &= ~(RCC_CR_HSEON | RCC_CR_HSECSSON | RCC_CR_HSEBYP | RCC_CR_HSEEXT | RCC_CR_HSIDIV | RCC_CR_HSIKERON | \
|
||||
RCC_CR_CSION | RCC_CR_CSIKERON |RCC_CR_HSI48ON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON);
|
||||
|
||||
/* Reset PLLxCFGR register */
|
||||
RCC->PLL1CFGR = 0U;
|
||||
RCC->PLL2CFGR = 0U;
|
||||
RCC->PLL3CFGR = 0U;
|
||||
|
||||
/* Reset PLL1DIVR register */
|
||||
RCC->PLL1DIVR = 0x01010280U;
|
||||
/* Reset PLL1FRACR register */
|
||||
RCC->PLL1FRACR = 0x00000000U;
|
||||
/* Reset PLL2DIVR register */
|
||||
RCC->PLL2DIVR = 0x01010280U;
|
||||
/* Reset PLL2FRACR register */
|
||||
RCC->PLL2FRACR = 0x00000000U;
|
||||
/* Reset PLL3DIVR register */
|
||||
RCC->PLL3DIVR = 0x01010280U;
|
||||
/* Reset PLL3FRACR register */
|
||||
RCC->PLL3FRACR = 0x00000000U;
|
||||
|
||||
/* Reset HSEBYP bit */
|
||||
RCC->CR &= ~(RCC_CR_HSEBYP);
|
||||
|
||||
/* Disable all interrupts */
|
||||
RCC->CIER = 0U;
|
||||
|
||||
/* Configure the Vector Table location add offset address ------------------*/
|
||||
#ifdef VECT_TAB_SRAM
|
||||
SCB->VTOR = SRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
||||
#else
|
||||
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
|
||||
#endif /* VECT_TAB_SRAM */
|
||||
|
||||
/* Check OPSR register to verify if there is an ongoing swap or option bytes update interrupted by a reset */
|
||||
reg_opsr = FLASH->OPSR & FLASH_OPSR_CODE_OP;
|
||||
if ((reg_opsr == FLASH_OPSR_CODE_OP) || (reg_opsr == (FLASH_OPSR_CODE_OP_2 | FLASH_OPSR_CODE_OP_1)))
|
||||
{
|
||||
/* Check FLASH Option Control Registers access */
|
||||
if ((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != 0U)
|
||||
{
|
||||
/* Authorizes the Option Byte register programming */
|
||||
FLASH->OPTKEYR = 0x08192A3BU;
|
||||
FLASH->OPTKEYR = 0x4C5D6E7FU;
|
||||
}
|
||||
/* Launch the option bytes change operation */
|
||||
FLASH->OPTCR |= FLASH_OPTCR_OPTSTART;
|
||||
|
||||
/* Lock the FLASH Option Control Register access */
|
||||
FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
* The SystemCoreClock variable contains the core clock (HCLK), it can
|
||||
* be used by the user application to setup the SysTick timer or configure
|
||||
* other parameters.
|
||||
*
|
||||
* @note Depending on secure or non-secure compilation, the adequate RCC peripheral
|
||||
* memory are is accessed thanks to RCC alias defined in stm32h5xxxx.h device file
|
||||
* so either from RCC_S peripheral register mapped memory in secure or from
|
||||
* RCC_NS peripheral register mapped memory in non-secure.
|
||||
*
|
||||
* @note Each time the core clock (HCLK) changes, this function must be called
|
||||
* to update SystemCoreClock variable value. Otherwise, any configuration
|
||||
* based on this variable will be incorrect.
|
||||
*
|
||||
* @note - The system frequency computed by this function is not the real
|
||||
* frequency in the chip. It is calculated based on the predefined
|
||||
* constant and the selected clock source:
|
||||
*
|
||||
* - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*)
|
||||
*
|
||||
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
|
||||
*
|
||||
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
|
||||
*
|
||||
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
|
||||
* or HSI_VALUE(**) or CSI_VALUE(*) multiplied/divided by the PLL factors.
|
||||
*
|
||||
* (*) CSI_VALUE is a constant defined in stm32h5xx_hal.h file (default value
|
||||
* 4 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (**) HSI_VALUE is a constant defined in stm32h5xx_hal.h file (default value
|
||||
* 64 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (***) HSE_VALUE is a constant defined in stm32h5xx_hal.h file (default value
|
||||
* 25 MHz), user has to ensure that HSE_VALUE is same as the real
|
||||
* frequency of the crystal used. Otherwise, this function may
|
||||
* have wrong result.
|
||||
*
|
||||
* - The result of this function could be not correct when using fractional
|
||||
* value for HSE crystal.
|
||||
*
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
|
||||
float_t fracn1, pllvco;
|
||||
|
||||
/* Get SYSCLK source -------------------------------------------------------*/
|
||||
switch (RCC->CFGR1 & RCC_CFGR1_SWS)
|
||||
{
|
||||
case 0x00UL: /* HSI used as system clock source */
|
||||
SystemCoreClock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
|
||||
break;
|
||||
|
||||
case 0x08UL: /* CSI used as system clock source */
|
||||
SystemCoreClock = CSI_VALUE;
|
||||
break;
|
||||
|
||||
case 0x10UL: /* HSE used as system clock source */
|
||||
SystemCoreClock = HSE_VALUE;
|
||||
break;
|
||||
|
||||
case 0x18UL: /* PLL1 used as system clock source */
|
||||
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
|
||||
SYSCLK = PLL_VCO / PLLR
|
||||
*/
|
||||
pllsource = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC);
|
||||
pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M)>> RCC_PLL1CFGR_PLL1M_Pos);
|
||||
pllfracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN)>>RCC_PLL1CFGR_PLL1FRACEN_Pos);
|
||||
fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN)>> RCC_PLL1FRACR_PLL1FRACN_Pos));
|
||||
|
||||
switch (pllsource)
|
||||
{
|
||||
case 0x01UL: /* HSI used as PLL clock source */
|
||||
hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
|
||||
pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \
|
||||
(fracn1/(float_t)0x2000) +(float_t)1 );
|
||||
break;
|
||||
|
||||
case 0x02UL: /* CSI used as PLL clock source */
|
||||
pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \
|
||||
(fracn1/(float_t)0x2000) +(float_t)1 );
|
||||
break;
|
||||
|
||||
case 0x03UL: /* HSE used as PLL clock source */
|
||||
pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \
|
||||
(fracn1/(float_t)0x2000) +(float_t)1 );
|
||||
break;
|
||||
|
||||
default: /* No clock sent to PLL*/
|
||||
pllvco = (float_t) 0U;
|
||||
break;
|
||||
}
|
||||
|
||||
pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1P) >>RCC_PLL1DIVR_PLL1P_Pos) + 1U ) ;
|
||||
SystemCoreClock = (uint32_t)(float_t)(pllvco/(float_t)pllp);
|
||||
|
||||
break;
|
||||
|
||||
default:
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
}
|
||||
/* Compute HCLK clock frequency --------------------------------------------*/
|
||||
/* Get HCLK prescaler */
|
||||
tmp = AHBPrescTable[((RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos)];
|
||||
/* HCLK clock frequency */
|
||||
SystemCoreClock >>= tmp;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Secure Non-Secure-Callable function to return the current
|
||||
* SystemCoreClock value after SystemCoreClock update.
|
||||
* The SystemCoreClock variable contains the core clock (HCLK), it can
|
||||
* be used by the user application to setup the SysTick timer or configure
|
||||
* other parameters.
|
||||
* @retval SystemCoreClock value (HCLK)
|
||||
*/
|
||||
CMSE_NS_ENTRY uint32_t SECURE_SystemCoreClockUpdate(void)
|
||||
{
|
||||
SystemCoreClockUpdate();
|
||||
|
||||
return SystemCoreClock;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
|
@ -0,0 +1,119 @@
|
|||
import rtconfig
|
||||
from building import *
|
||||
|
||||
# get current directory
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
# The set of source files associated with this SConscript file.
|
||||
|
||||
src = Split('''
|
||||
CMSIS/Device/ST/STM32H5xx/Source/Templates/system_stm32h5xx.c
|
||||
STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c
|
||||
STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_comp.c
|
||||
STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cortex.c
|
||||
STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_crc.c
|
||||
STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_crc_ex.c
|
||||
STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cryp.c
|
||||
STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cryp_ex.c
|
||||
STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma.c
|
||||
STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma_ex.c
|
||||
STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_exti.c
|
||||
STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr.c
|
||||
STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr_ex.c
|
||||
STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc.c
|
||||
STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc_ex.c
|
||||
STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rng.c
|
||||
STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gpio.c
|
||||
STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_icache.c
|
||||
''')
|
||||
|
||||
if GetDepend(['RT_USING_SERIAL']):
|
||||
src += ['STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart.c']
|
||||
src += ['STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart_ex.c']
|
||||
src += ['STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_usart.c']
|
||||
src += ['STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_usart_ex.c']
|
||||
|
||||
if GetDepend(['RT_USING_I2C']):
|
||||
src += ['STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2c.c']
|
||||
src += ['STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2c_ex.c']
|
||||
|
||||
if GetDepend(['RT_USING_SPI']):
|
||||
src += ['STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_spi.c']
|
||||
src += ['STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_spi_ex.c']
|
||||
|
||||
if GetDepend(['RT_USING_USB']):
|
||||
src += ['STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_hcd.c']
|
||||
src += ['STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pcd.c']
|
||||
src += ['STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pcd_ex.c']
|
||||
src += ['STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_usb.c']
|
||||
|
||||
if GetDepend(['RT_USING_CAN']):
|
||||
src += ['STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_can.c']
|
||||
|
||||
if GetDepend(['RT_USING_HWTIMER']) or GetDepend(['RT_USING_PWM']):
|
||||
src += ['STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_lptim.c']
|
||||
src += ['STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_tim.c']
|
||||
src += ['STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_tim_ex.c']
|
||||
|
||||
if GetDepend(['RT_USING_ADC']):
|
||||
src += ['STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_adc.c']
|
||||
src += ['STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_adc_ex.c']
|
||||
|
||||
if GetDepend(['RT_USING_DAC']):
|
||||
src += ['STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dac.c']
|
||||
src += ['STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dac_ex.c']
|
||||
|
||||
if GetDepend(['RT_USING_RTC']):
|
||||
src += ['STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rtc.c']
|
||||
src += ['STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rtc_ex.c']
|
||||
|
||||
if GetDepend(['RT_USING_WDT']):
|
||||
src += ['STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_iwdg.c']
|
||||
src += ['STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_wwdg.c']
|
||||
|
||||
if GetDepend(['RT_USING_SDIO']):
|
||||
src += ['STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sd.c']
|
||||
src += ['STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sd_ex.c']
|
||||
src += ['STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_sdmmc.c']
|
||||
|
||||
if GetDepend(['RT_USING_AUDIO']):
|
||||
src += ['STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sai.c']
|
||||
src += ['STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sai_ex.c']
|
||||
|
||||
if GetDepend(['RT_USING_MTD_NOR']):
|
||||
src += ['STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_nor.c']
|
||||
|
||||
if GetDepend(['RT_USING_MTD_NAND']):
|
||||
src += ['STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_nand.c']
|
||||
|
||||
if GetDepend(['RT_USING_PM']):
|
||||
src += ['STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_lptim.c']
|
||||
|
||||
if GetDepend(['BSP_USING_ON_CHIP_FLASH']):
|
||||
src += ['STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash.c']
|
||||
src += ['STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash_ex.c']
|
||||
src += ['STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash_ramfunc.c']
|
||||
|
||||
if GetDepend(['BSP_USING_FMC']):
|
||||
src += ['STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_fmc.c']
|
||||
|
||||
if GetDepend(['BSP_USING_GFXMMU']):
|
||||
src += ['STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gfxmmu.c']
|
||||
|
||||
if GetDepend(['BSP_USING_DSI']):
|
||||
src += ['STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dsi.c']
|
||||
src += ['STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma2d.c']
|
||||
src += ['STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_dma2d.c']
|
||||
src += ['STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_ltdc.c']
|
||||
src += ['STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_ltdc_ex.c']
|
||||
|
||||
if GetDepend(['BSP_USING_SRAM']):
|
||||
src += ['STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_sram.c']
|
||||
|
||||
path = [cwd + '/STM32H5xx_HAL_Driver/Inc',
|
||||
cwd + '/CMSIS/Device/ST/STM32H5xx/Include']
|
||||
|
||||
CPPDEFINES = ['USE_HAL_DRIVER']
|
||||
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
|
||||
|
||||
Return('group')
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,54 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32_assert.h
|
||||
* @author MCD Application Team
|
||||
* @brief STM32 assert template file.
|
||||
* This file should be copied to the application folder and renamed
|
||||
* to stm32_assert.h.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32_ASSERT_H
|
||||
#define __STM32_ASSERT_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#ifdef USE_FULL_ASSERT
|
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check.
|
||||
* @param expr If expr is false, it calls assert_failed function
|
||||
* which reports the name of the source file and the source
|
||||
* line number of the call that failed.
|
||||
* If expr is true, it returns no value.
|
||||
* @retval None
|
||||
*/
|
||||
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void assert_failed(uint8_t *file, uint32_t line);
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32_ASSERT_H */
|
||||
|
||||
|
|
@ -0,0 +1,897 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h5xx_hal.h
|
||||
* @author MCD Application Team
|
||||
* @brief This file contains all the functions prototypes for the HAL
|
||||
* module driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32H5xx_HAL_H
|
||||
#define __STM32H5xx_HAL_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h5xx_hal_conf.h"
|
||||
|
||||
/** @addtogroup STM32H5xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup HAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup HAL_Exported_Types HAL Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_TICK_FREQ Tick Frequency
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_TICK_FREQ_10HZ = 100U,
|
||||
HAL_TICK_FREQ_100HZ = 10U,
|
||||
HAL_TICK_FREQ_1KHZ = 1U,
|
||||
HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
|
||||
} HAL_TickFreqTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported variables --------------------------------------------------------*/
|
||||
/** @defgroup HAL_Exported_Variables HAL Exported Variables
|
||||
* @{
|
||||
*/
|
||||
extern __IO uint32_t uwTick;
|
||||
extern uint32_t uwTickPrio;
|
||||
extern HAL_TickFreqTypeDef uwTickFreq;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup SBS_Exported_Constants SBS Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SBS_FPU_Interrupts FPU Interrupts
|
||||
* @{
|
||||
*/
|
||||
#define SBS_IT_FPU_IOC SBS_FPUIMR_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt */
|
||||
#define SBS_IT_FPU_DZC SBS_FPUIMR_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */
|
||||
#define SBS_IT_FPU_UFC SBS_FPUIMR_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */
|
||||
#define SBS_IT_FPU_OFC SBS_FPUIMR_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */
|
||||
#define SBS_IT_FPU_IDC SBS_FPUIMR_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */
|
||||
#define SBS_IT_FPU_IXC SBS_FPUIMR_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SBS_BREAK_CONFIG SBS Break Config
|
||||
* @{
|
||||
*/
|
||||
#define SBS_BREAK_FLASH_ECC SBS_CFGR2_ECCL /*!< Enable and lock the FLASH ECC double error with TIM1/8/15/16/17
|
||||
Break inputs.*/
|
||||
#define SBS_BREAK_PVD SBS_CFGR2_PVDL /*!< Enable and lock the PVD connection with TIM1/8/15/16/17
|
||||
Break inputs. */
|
||||
#define SBS_BREAK_SRAM_ECC SBS_CFGR2_SEL /*!< Enable and lock the SRAM ECC double error signal with
|
||||
TIM1/8/15/16/17 Break inputs.*/
|
||||
#define SBS_BREAK_LOCKUP SBS_CFGR2_CLL /*!< Enable and lock the connection of Cortex-M33 LOCKUP (hardfault)
|
||||
output to TIM1/8/15/16/17 Break inputs.*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(VREFBUF)
|
||||
/** @defgroup VREFBUF_VoltageScale VREFBUF Voltage Scale
|
||||
* @{
|
||||
*/
|
||||
#define VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */
|
||||
#define VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_0 /*!< Voltage reference scale 1 (VREF_OUT2) */
|
||||
#define VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1 /*!< Voltage reference scale 2 (VREF_OUT3) */
|
||||
#define VREFBUF_VOLTAGE_SCALE3 (VREFBUF_CSR_VRS_0 | VREFBUF_CSR_VRS_1) /*!< Voltage reference scale 3 (VREF_OUT4) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup VREFBUF_HighImpedance VREFBUF High Impedance
|
||||
* @{
|
||||
*/
|
||||
#define VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to
|
||||
Voltage reference buffer output */
|
||||
#define VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* VREFBUF */
|
||||
|
||||
/** @defgroup SBS_FastModePlus_GPIO Fast-mode Plus on GPIO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Fast-mode Plus driving capability on a specific GPIO
|
||||
*/
|
||||
#define SBS_FASTMODEPLUS_PB6 SBS_PMCR_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */
|
||||
#define SBS_FASTMODEPLUS_PB7 SBS_PMCR_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */
|
||||
#define SBS_FASTMODEPLUS_PB8 SBS_PMCR_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */
|
||||
#if defined(SBS_PMCR_PB9_FMP)
|
||||
#define SBS_FASTMODEPLUS_PB9 SBS_PMCR_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */
|
||||
#endif /* SBS_PMCR_PB9_FMP */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(SBS_PMCR_ETH_SEL_PHY)
|
||||
/** @defgroup SBS_Ethernet_Config Ethernet Config
|
||||
* @{
|
||||
*/
|
||||
#define SBS_ETH_MII ((uint32_t)0x00000000) /*!< Select the Media Independent Interface (MII) or GMII */
|
||||
#define SBS_ETH_RMII SBS_PMCR_ETH_SEL_PHY_2 /*!< Select the Reduced Media Independent Interface (RMII) */
|
||||
|
||||
#define IS_SBS_ETHERNET_CONFIG(CONFIG) (((CONFIG) == SBS_ETH_MII) || \
|
||||
((CONFIG) == SBS_ETH_RMII))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* SBS_PMCR_ETH_SEL_PHY */
|
||||
|
||||
/** @defgroup SBS_Memories_Erase_Flag_Status Memory Erase Flags Status
|
||||
* @{
|
||||
*/
|
||||
#define SBS_MEMORIES_ERASE_FLAG_IPMEE SBS_MESR_IPMEE /*!< Select the Status of End Of Erase for ICACHE
|
||||
and PKA RAMs */
|
||||
#define SBS_MEMORIES_ERASE_FLAG_MCLR SBS_MESR_MCLR /*!< Select the Status of Erase after Power-on Reset
|
||||
(SRAM2, BKPRAM, ICACHE, DCACHE, PKA rams) */
|
||||
|
||||
#define IS_SBS_MEMORIES_ERASE_FLAG(FLAG) (((FLAG) == SBS_MEMORIES_ERASE_FLAG_IPMEE) || \
|
||||
((FLAG) == SBS_MEMORIES_ERASE_FLAG_MCLR))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SBS_IOCompenstionCell_Config IOCompenstionCell Config
|
||||
* @{
|
||||
*/
|
||||
#define SBS_VDD_CELL_CODE ((uint32_t)0x00000000) /*!< Select Code from the cell */
|
||||
#define SBS_VDD_REGISTER_CODE SBS_CCCSR_CS1 /*!< Code from the SBS compensation cell code register */
|
||||
|
||||
#define IS_SBS_VDD_CODE_SELECT(SELECT) (((SELECT) == SBS_VDD_CELL_CODE)|| \
|
||||
((SELECT) == SBS_VDD_REGISTER_CODE))
|
||||
|
||||
#define SBS_VDDIO_CELL_CODE ((uint32_t)0x00000000) /*!< Select Code from the cell */
|
||||
#define SBS_VDDIO_REGISTER_CODE SBS_CCCSR_CS2 /*!< Code from the SBS compensation cell code register */
|
||||
|
||||
#define IS_SBS_VDDIO_CODE_SELECT(SELECT) (((SELECT) == SBS_VDDIO_CELL_CODE)|| \
|
||||
((SELECT) == SBS_VDDIO_REGISTER_CODE))
|
||||
|
||||
#define IS_SBS_CODE_CONFIG(CONFIG) ((CONFIG) < (0x10UL))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(SBS_EPOCHSELCR_EPOCH_SEL)
|
||||
/** @defgroup SBS_EPOCH_Selection EPOCH Selection
|
||||
* @{
|
||||
*/
|
||||
#define SBS_EPOCH_SEL_SECURE 0x0UL /*!< EPOCH secure selected */
|
||||
#define SBS_EPOCH_SEL_NONSECURE SBS_EPOCHSELCR_EPOCH_SEL_0 /*!< EPOCH non secure selected */
|
||||
#define SBS_EPOCH_SEL_PUFCHECK SBS_EPOCHSELCR_EPOCH_SEL_1 /*!< EPOCH all zeros for PUF integrity check */
|
||||
|
||||
#define IS_SBS_EPOCH_SELECTION(SELECT) (((SELECT) == SBS_EPOCH_SEL_SECURE) || \
|
||||
((SELECT) == SBS_EPOCH_SEL_NONSECURE) || \
|
||||
((SELECT) == SBS_EPOCH_SEL_PUFCHECK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* SBS_EPOCHSELCR_EPOCH_SEL */
|
||||
|
||||
#if defined(SBS_NEXTHDPLCR_NEXTHDPL)
|
||||
/** @defgroup SBS_NextHDPL_Selection Next HDPL Selection
|
||||
* @{
|
||||
*/
|
||||
#define SBS_OBKHDPL_INCR_0 0x00U /*!< Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas */
|
||||
#define SBS_OBKHDPL_INCR_1 SBS_NEXTHDPLCR_NEXTHDPL_0 /*!< Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas */
|
||||
#define SBS_OBKHDPL_INCR_2 SBS_NEXTHDPLCR_NEXTHDPL_1 /*!< Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas */
|
||||
#define SBS_OBKHDPL_INCR_3 SBS_NEXTHDPLCR_NEXTHDPL /*!< Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* SBS_NEXTHDPLCR_NEXTHDPL */
|
||||
|
||||
/** @defgroup SBS_HDPL_Value HDPL Value
|
||||
* @{
|
||||
*/
|
||||
#define SBS_HDPL_VALUE_0 0x000000B4U /*!< Hide protection level 0 */
|
||||
#define SBS_HDPL_VALUE_1 0x00000051U /*!< Hide protection level 0 */
|
||||
#define SBS_HDPL_VALUE_2 0x0000008AU /*!< Hide protection level 0 */
|
||||
#define SBS_HDPL_VALUE_3 0x0000006FU /*!< Hide protection level 0 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(SBS_DBGCR_DBG_AUTH_SEC)
|
||||
/** @defgroup SBS_DEBUG_SEC_Value Debug sec Value
|
||||
* @{
|
||||
*/
|
||||
#define SBS_DEBUG_SEC_NSEC 0x000000B4U /*!< Debug opening for secure and non-secure */
|
||||
#define SBS_DEBUG_NSEC 0x0000003CU /*!< Debug opening for non-secure only */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* SBS_DBGCR_DBG_AUTH_SEC */
|
||||
|
||||
/** @defgroup SBS_Lock_items SBS Lock items
|
||||
* @brief SBS items to set lock on
|
||||
* @{
|
||||
*/
|
||||
#define SBS_MPU_NSEC SBS_CNSLCKR_LOCKNSMPU /*!< Non-secure MPU lock (privileged secure or
|
||||
non-secure only) */
|
||||
#define SBS_VTOR_NSEC SBS_CNSLCKR_LOCKNSVTOR /*!< Non-secure VTOR lock (privileged secure or
|
||||
non-secure only) */
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
#define SBS_SAU (SBS_CSLCKR_LOCKSAU << 16U) /*!< SAU lock (privileged secure code only) */
|
||||
#define SBS_MPU_SEC (SBS_CSLCKR_LOCKSMPU << 16U) /*!< Secure MPU lock (privileged secure code only)
|
||||
*/
|
||||
#define SBS_VTOR_AIRCR_SEC (SBS_CSLCKR_LOCKSVTAIRCR << 16U) /*!< VTOR_S and AIRCR lock (privileged secure
|
||||
code only) */
|
||||
#define SBS_LOCK_ALL (SBS_MPU_NSEC|SBS_VTOR_NSEC|SBS_SAU|SBS_MPU_SEC|SBS_VTOR_AIRCR_SEC) /*!< All */
|
||||
#else
|
||||
#define SBS_LOCK_ALL (SBS_MPU_NSEC|SBS_VTOR_NSEC) /*!< All (privileged secure or non-secure only) */
|
||||
#endif /* __ARM_FEATURE_CMSE */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SBS_Attributes_items SBS Attributes items
|
||||
* @brief SBS items to configure secure or non-secure attributes on
|
||||
* @{
|
||||
*/
|
||||
#define SBS_CLK SBS_SECCFGR_SBSSEC /*!< SBS clock control */
|
||||
#define SBS_CLASSB SBS_SECCFGR_CLASSBSEC /*!< Class B */
|
||||
#define SBS_FPU SBS_SECCFGR_FPUSEC /*!< FPU */
|
||||
#define SBS_SMPS SBS_SECCFGR_SDCE_SEC_EN /*!< SMPS */
|
||||
#define SBS_ALL (SBS_CLK | SBS_CLASSB | SBS_FPU | SBS_SMPS) /*!< All */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SBS_attributes SBS attributes
|
||||
* @brief SBS secure or non-secure attributes
|
||||
* @{
|
||||
*/
|
||||
#define SBS_SEC 0x00000001U /*!< Secure attribute */
|
||||
#define SBS_NSEC 0x00000000U /*!< Non-secure attribute */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Freeze/Unfreeze Peripherals in Debug mode
|
||||
*/
|
||||
#if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
|
||||
#endif /* DBGMCU_APB1FZR1_DBG_TIM2_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
|
||||
#endif /* DBGMCU_APB1FZR1_DBG_TIM3_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
|
||||
#endif /* DBGMCU_APB1FZR1_DBG_TIM4_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
|
||||
#endif /* DBGMCU_APB1FZR1_DBG_TIM4_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
|
||||
#endif /* DBGMCU_APB1FZR1_DBG_TIM6_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
|
||||
#endif /* DBGMCU_APB1FZR1_DBG_TIM7_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1FZR1_DBG_TIM12_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM12_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM12_STOP)
|
||||
#endif /* DBGMCU_APB1FZR1_DBG_TIM12_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1FZR1_DBG_TIM13_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM13_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM13_STOP)
|
||||
#endif /* DBGMCU_APB1FZR1_DBG_TIM13_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1FZR1_DBG_TIM14_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM14_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM14_STOP)
|
||||
#endif /* DBGMCU_APB1FZR1_DBG_TIM14_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
|
||||
#endif /* DBGMCU_APB1FZR1_DBG_WWDG_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
|
||||
#endif /* DBGMCU_APB1FZR1_DBG_IWDG_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_I2C1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_I2C1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
|
||||
#endif /* DBGMCU_APB1FZR1_DBG_I2C1_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_I2C2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_I2C2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
|
||||
#endif /* DBGMCU_APB1FZR1_DBG_I2C2_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1FZR1_DBG_I3C1_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_I3C1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I3C1_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_I3C1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I3C1_STOP)
|
||||
#endif /* DBGMCU_APB1FZR1_DBG_I3C1_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
|
||||
#endif /* DBGMCU_APB1FZR2_DBG_LPTIM2_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB2FZR_DBG_TIM1_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP)
|
||||
#endif /* DBGMCU_APB2FZR_DBG_TIM1_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB2FZR_DBG_TIM8_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM8_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM8_STOP)
|
||||
#endif /* DBGMCU_APB2FZR_DBG_TIM8_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB2FZR_DBG_TIM15_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM15_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM15_STOP)
|
||||
#endif /* DBGMCU_APB2FZR_DBG_TIM15_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB2FZR_DBG_TIM16_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM16_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM16_STOP)
|
||||
#endif /* DBGMCU_APB2FZR_DBG_TIM16_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB2FZR_DBG_TIM17_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM17_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM17_STOP)
|
||||
#endif /* DBGMCU_APB2FZR_DBG_TIM17_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB3FZR_DBG_I2C3_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_I2C3() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I2C3_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_I2C3() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I2C3_STOP)
|
||||
#endif /* DBGMCU_APB3FZR_DBG_I2C3_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB3FZR_DBG_I2C4_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_I2C4() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I2C4_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_I2C4() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I2C4_STOP)
|
||||
#endif /* DBGMCU_APB3FZR_DBG_I2C4_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB3FZR_DBG_I3C2_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_I3C2() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I3C2_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_I3C2() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I3C2_STOP)
|
||||
#endif /* DBGMCU_APB3FZR_DBG_I3C2_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB3FZR_DBG_LPTIM1_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM1_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM1_STOP)
|
||||
#endif /* DBGMCU_APB3FZR_DBG_LPTIM1_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB3FZR_DBG_LPTIM3_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_LPTIM3() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM3_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_LPTIM3() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM3_STOP)
|
||||
#endif /* DBGMCU_APB3FZR_DBG_LPTIM3_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB3FZR_DBG_LPTIM4_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_LPTIM4() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM4_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_LPTIM4() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM4_STOP)
|
||||
#endif /* DBGMCU_APB3FZR_DBG_LPTIM4_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB3FZR_DBG_LPTIM5_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_LPTIM5() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM5_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_LPTIM5() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM5_STOP)
|
||||
#endif /* DBGMCU_APB3FZR_DBG_LPTIM5_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB3FZR_DBG_LPTIM6_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_LPTIM6() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM6_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_LPTIM6() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM6_STOP)
|
||||
#endif /* DBGMCU_APB3FZR_DBG_LPTIM6_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB3FZR_DBG_RTC_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_RTC_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_RTC_STOP)
|
||||
#endif /* DBGMCU_APB3FZR_DBG_RTC_STOP */
|
||||
|
||||
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_GPDMA1_0() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_GPDMA1_0() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP)
|
||||
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP */
|
||||
|
||||
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_GPDMA1_1() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_GPDMA1_1() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP)
|
||||
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP */
|
||||
|
||||
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_GPDMA1_2() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_GPDMA1_2() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP)
|
||||
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP */
|
||||
|
||||
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_GPDMA1_3() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_GPDMA1_3() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP)
|
||||
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP */
|
||||
|
||||
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_GPDMA1_4() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_GPDMA1_4() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP)
|
||||
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP */
|
||||
|
||||
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_GPDMA1_5() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_GPDMA1_5() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP)
|
||||
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP */
|
||||
|
||||
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_GPDMA1_6() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_GPDMA1_6() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP)
|
||||
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP */
|
||||
|
||||
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_GPDMA1_7() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_GPDMA1_7() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP)
|
||||
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP */
|
||||
|
||||
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH0_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_GPDMA2_0() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH0_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_GPDMA2_0() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH0_STOP)
|
||||
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH0_STOP */
|
||||
|
||||
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH1_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_GPDMA2_1() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH1_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_GPDMA2_1() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH1_STOP)
|
||||
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH1_STOP */
|
||||
|
||||
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH2_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_GPDMA2_2() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH2_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_GPDMA2_2() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH2_STOP)
|
||||
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH2_STOP */
|
||||
|
||||
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH3_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_GPDMA2_3() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH3_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_GPDMA2_3() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH3_STOP)
|
||||
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH3_STOP */
|
||||
|
||||
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH4_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_GPDMA2_4() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH4_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_GPDMA2_4() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH4_STOP)
|
||||
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH4_STOP */
|
||||
|
||||
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH5_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_GPDMA2_5() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH5_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_GPDMA2_5() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH5_STOP)
|
||||
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH5_STOP */
|
||||
|
||||
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH6_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_GPDMA2_6() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH6_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_GPDMA2_6() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH6_STOP)
|
||||
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH6_STOP */
|
||||
|
||||
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH7_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_GPDMA2_7() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH7_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_GPDMA2_7() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH7_STOP)
|
||||
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH7_STOP */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SBS_Exported_Macros SBS Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Floating Point Unit interrupt enable/disable macros
|
||||
* @param __INTERRUPT__: This parameter can be a value of @ref SBS_FPU_Interrupts
|
||||
*/
|
||||
#define __HAL_SBS_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SBS_FPU_INTERRUPT((__INTERRUPT__)));\
|
||||
SET_BIT(SBS->FPUIMR, (__INTERRUPT__));\
|
||||
}while(0)
|
||||
|
||||
#define __HAL_SBS_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SBS_FPU_INTERRUPT((__INTERRUPT__)));\
|
||||
CLEAR_BIT(SBS->FPUIMR, (__INTERRUPT__));\
|
||||
}while(0)
|
||||
|
||||
/** @brief SBS Break ECC lock.
|
||||
* Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input.
|
||||
* @note The selected configuration is locked and can be unlocked only by system reset.
|
||||
*/
|
||||
#define __HAL_SBS_BREAK_ECC_LOCK() SET_BIT(SBS->CFGR2, SBS_CFGR2_ECCL)
|
||||
|
||||
/** @brief SBS Break Cortex-M33 Lockup lock.
|
||||
* Enable and lock the connection of Cortex-M33 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input.
|
||||
* @note The selected configuration is locked and can be unlocked only by system reset.
|
||||
*/
|
||||
#define __HAL_SBS_BREAK_LOCKUP_LOCK() SET_BIT(SBS->CFGR2, SBS_CFGR2_CLL)
|
||||
|
||||
/** @brief SBS Break PVD lock.
|
||||
* Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0]
|
||||
* in the PWR_CR2 register.
|
||||
* @note The selected configuration is locked and can be unlocked only by system reset.
|
||||
*/
|
||||
#define __HAL_SBS_BREAK_PVD_LOCK() SET_BIT(SBS->CFGR2, SBS_CFGR2_PVDL)
|
||||
|
||||
/** @brief SBS Break SRAM double ECC lock.
|
||||
* Enable and lock the connection of SRAM double ECC error to TIM1/8/15/16/17 Break input.
|
||||
* @note The selected configuration is locked and can be unlocked only by system reset.
|
||||
*/
|
||||
#define __HAL_SBS_BREAK_SRAM_ECC_LOCK() SET_BIT(SBS->CFGR2, SBS_CFGR2_SEL)
|
||||
|
||||
/** @brief Fast-mode Plus driving capability enable/disable macros
|
||||
* @param __FASTMODEPLUS__: This parameter can be a value of :
|
||||
* @arg @ref SBS_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6
|
||||
* @arg @ref SBS_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7
|
||||
* @arg @ref SBS_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8
|
||||
* @arg @ref SBS_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9
|
||||
*/
|
||||
#define __HAL_SBS_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SBS_FASTMODEPLUS((__FASTMODEPLUS__)));\
|
||||
SET_BIT(SBS->PMCR, (__FASTMODEPLUS__));\
|
||||
}while(0)
|
||||
|
||||
#define __HAL_SBS_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SBS_FASTMODEPLUS((__FASTMODEPLUS__)));\
|
||||
CLEAR_BIT(SBS->PMCR, (__FASTMODEPLUS__));\
|
||||
}while(0)
|
||||
|
||||
/** @brief Check SBS Memories Erase Status Flags.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref SBS_MEMORIES_ERASE_FLAG_IPMEE Status of End Of Erase for ICACHE and PKA RAMs
|
||||
* @arg @ref SBS_MEMORIES_ERASE_FLAG_MCLR Status of Erase after Power-on Reset ((SRAM2, BKPRAM,
|
||||
* ICACHE, DCACHE, PKA RAMs)
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_SBS_GET_MEMORIES_ERASE_STATUS(__FLAG__) ((((SBS->MESR) & (__FLAG__))!= 0) ? 1 : 0)
|
||||
|
||||
/** @brief Clear SBS Memories Erase Status Flags.
|
||||
* @param __FLAG__: specifies the flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref SBS_MEMORIES_ERASE_FLAG_IPMEE Status of End Of Erase for ICACHE and PKA RAMs
|
||||
* @arg @ref SBS_MEMORIES_ERASE_FLAG_MCLR Status of Erase after Power-on Reset ((SRAM2, BKPRAM,
|
||||
* ICACHE, DCACHE, PKA RAMs)
|
||||
*/
|
||||
#define __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS(__FLAG__) do {assert_param(IS_SBS_MEMORIES_ERASE_FLAG((__FLAG__)));\
|
||||
WRITE_REG(SBS->MESR, (__FLAG__));\
|
||||
}while(0)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SBS_Private_Macros SBS Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_SBS_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SBS_IT_FPU_IOC) == SBS_IT_FPU_IOC) || \
|
||||
(((__INTERRUPT__) & SBS_IT_FPU_DZC) == SBS_IT_FPU_DZC) || \
|
||||
(((__INTERRUPT__) & SBS_IT_FPU_UFC) == SBS_IT_FPU_UFC) || \
|
||||
(((__INTERRUPT__) & SBS_IT_FPU_OFC) == SBS_IT_FPU_OFC) || \
|
||||
(((__INTERRUPT__) & SBS_IT_FPU_IDC) == SBS_IT_FPU_IDC) || \
|
||||
(((__INTERRUPT__) & SBS_IT_FPU_IXC) == SBS_IT_FPU_IXC))
|
||||
|
||||
#define IS_SBS_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SBS_BREAK_FLASH_ECC) || \
|
||||
((__CONFIG__) == SBS_BREAK_PVD) || \
|
||||
((__CONFIG__) == SBS_BREAK_SRAM_ECC) || \
|
||||
((__CONFIG__) == SBS_BREAK_LOCKUP))
|
||||
|
||||
#if defined(VREFBUF)
|
||||
#define IS_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == VREFBUF_VOLTAGE_SCALE0) || \
|
||||
((__SCALE__) == VREFBUF_VOLTAGE_SCALE1) || \
|
||||
((__SCALE__) == VREFBUF_VOLTAGE_SCALE2) || \
|
||||
((__SCALE__) == VREFBUF_VOLTAGE_SCALE3))
|
||||
|
||||
#define IS_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
|
||||
((__VALUE__) == VREFBUF_HIGH_IMPEDANCE_ENABLE))
|
||||
|
||||
#define IS_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
|
||||
#endif /* VREFBUF*/
|
||||
|
||||
#if defined(SBS_FASTMODEPLUS_PB9)
|
||||
#define IS_SBS_FASTMODEPLUS(__PIN__) ((((__PIN__) & SBS_FASTMODEPLUS_PB6) == SBS_FASTMODEPLUS_PB6) || \
|
||||
(((__PIN__) & SBS_FASTMODEPLUS_PB7) == SBS_FASTMODEPLUS_PB7) || \
|
||||
(((__PIN__) & SBS_FASTMODEPLUS_PB8) == SBS_FASTMODEPLUS_PB8) || \
|
||||
(((__PIN__) & SBS_FASTMODEPLUS_PB9) == SBS_FASTMODEPLUS_PB9))
|
||||
#else
|
||||
#define IS_SBS_FASTMODEPLUS(__PIN__) ((((__PIN__) & SBS_FASTMODEPLUS_PB6) == SBS_FASTMODEPLUS_PB6) || \
|
||||
(((__PIN__) & SBS_FASTMODEPLUS_PB7) == SBS_FASTMODEPLUS_PB7) || \
|
||||
(((__PIN__) & SBS_FASTMODEPLUS_PB8) == SBS_FASTMODEPLUS_PB8))
|
||||
#endif /* SBS_FASTMODEPLUS_PB9 */
|
||||
|
||||
#define IS_SBS_HDPL(__LEVEL__) (((__LEVEL__) == SBS_HDPL_VALUE_0) || ((__LEVEL__) == SBS_HDPL_VALUE_1) || \
|
||||
((__LEVEL__) == SBS_HDPL_VALUE_2) || ((__LEVEL__) == SBS_HDPL_VALUE_3))
|
||||
|
||||
#define IS_SBS_OBKHDPL_SELECTION(__SELECT__) (((__SELECT__) == SBS_OBKHDPL_INCR_0) || \
|
||||
((__SELECT__) == SBS_OBKHDPL_INCR_1) || \
|
||||
((__SELECT__) == SBS_OBKHDPL_INCR_2) || \
|
||||
((__SELECT__) == SBS_OBKHDPL_INCR_3))
|
||||
|
||||
#define IS_SBS_ITEMS_ATTRIBUTES(__ITEM__) ((((__ITEM__) & SBS_CLK) == SBS_CLK) || \
|
||||
(((__ITEM__) & SBS_CLASSB) == SBS_CLASSB) || \
|
||||
(((__ITEM__) & SBS_FPU) == SBS_FPU) || \
|
||||
(((__ITEM__) & SBS_SMPS) == SBS_SMPS) || \
|
||||
(((__ITEM__) & ~(SBS_ALL)) == 0U))
|
||||
|
||||
#define IS_SBS_ATTRIBUTES(__ATTRIBUTES__) (((__ATTRIBUTES__) == SBS_SEC) ||\
|
||||
((__ATTRIBUTES__) == SBS_NSEC))
|
||||
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
|
||||
#define IS_SBS_LOCK_ITEMS(__ITEM__) ((((__ITEM__) & SBS_MPU_NSEC) == SBS_MPU_NSEC) || \
|
||||
(((__ITEM__) & SBS_VTOR_NSEC) == SBS_VTOR_NSEC) || \
|
||||
(((__ITEM__) & SBS_SAU) == SBS_SAU) || \
|
||||
(((__ITEM__) & SBS_MPU_SEC) == SBS_MPU_SEC) || \
|
||||
(((__ITEM__) & SBS_VTOR_AIRCR_SEC) == SBS_VTOR_AIRCR_SEC) || \
|
||||
(((__ITEM__) & ~(SBS_LOCK_ALL)) == 0U))
|
||||
|
||||
#else
|
||||
|
||||
#define IS_SBS_LOCK_ITEMS(__ITEM__) ((((__ITEM__) & SBS_MPU_NSEC) == SBS_MPU_NSEC) || \
|
||||
(((__ITEM__) & SBS_VTOR_NSEC) == SBS_VTOR_NSEC) || \
|
||||
(((__ITEM__) & ~(SBS_LOCK_ALL)) == 0U))
|
||||
|
||||
|
||||
#endif /* __ARM_FEATURE_CMSE */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_Private_Macros HAL Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \
|
||||
((FREQ) == HAL_TICK_FREQ_100HZ) || \
|
||||
((FREQ) == HAL_TICK_FREQ_1KHZ))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup HAL_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup HAL_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions ******************************/
|
||||
HAL_StatusTypeDef HAL_Init(void);
|
||||
HAL_StatusTypeDef HAL_DeInit(void);
|
||||
void HAL_MspInit(void);
|
||||
void HAL_MspDeInit(void);
|
||||
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HAL_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions ************************************************/
|
||||
void HAL_IncTick(void);
|
||||
void HAL_Delay(uint32_t Delay);
|
||||
uint32_t HAL_GetTick(void);
|
||||
uint32_t HAL_GetTickPrio(void);
|
||||
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
|
||||
HAL_TickFreqTypeDef HAL_GetTickFreq(void);
|
||||
void HAL_SuspendTick(void);
|
||||
void HAL_ResumeTick(void);
|
||||
uint32_t HAL_GetHalVersion(void);
|
||||
uint32_t HAL_GetREVID(void);
|
||||
uint32_t HAL_GetDEVID(void);
|
||||
uint32_t HAL_GetUIDw0(void);
|
||||
uint32_t HAL_GetUIDw1(void);
|
||||
uint32_t HAL_GetUIDw2(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HAL_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* DBGMCU Peripheral Control functions *****************************************/
|
||||
void HAL_DBGMCU_EnableDBGStopMode(void);
|
||||
void HAL_DBGMCU_DisableDBGStopMode(void);
|
||||
void HAL_DBGMCU_EnableDBGStandbyMode(void);
|
||||
void HAL_DBGMCU_DisableDBGStandbyMode(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HAL_Exported_Functions_Group4
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* VREFBUF Control functions ****************************************************/
|
||||
#if defined(VREFBUF)
|
||||
void HAL_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
|
||||
void HAL_VREFBUF_HighImpedanceConfig(uint32_t Mode);
|
||||
void HAL_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
|
||||
HAL_StatusTypeDef HAL_EnableVREFBUF(void);
|
||||
void HAL_DisableVREFBUF(void);
|
||||
#endif /* VREFBUF */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HAL_Exported_Functions_Group5
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* SBS System Configuration functions *******************************************/
|
||||
void HAL_SBS_ETHInterfaceSelect(uint32_t SBS_ETHInterface);
|
||||
void HAL_SBS_EnableVddIO1CompensationCell(void);
|
||||
void HAL_SBS_DisableVddIO1CompensationCell(void);
|
||||
void HAL_SBS_EnableVddIO2CompensationCell(void);
|
||||
void HAL_SBS_DisableVddIO2CompensationCell(void);
|
||||
void HAL_SBS_VDDCompensationCodeSelect(uint32_t SBS_CompCode);
|
||||
void HAL_SBS_VDDIOCompensationCodeSelect(uint32_t SBS_CompCode);
|
||||
uint32_t HAL_SBS_GetVddIO1CompensationCellReadyFlag(void);
|
||||
uint32_t HAL_SBS_GetVddIO2CompensationCellReadyFlag(void);
|
||||
void HAL_SBS_VDDCompensationCodeConfig(uint32_t SBS_PMOSCode, uint32_t SBS_NMOSCode);
|
||||
void HAL_SBS_VDDIOCompensationCodeConfig(uint32_t SBS_PMOSCode, uint32_t SBS_NMOSCode);
|
||||
uint32_t HAL_SBS_GetNMOSVddCompensationValue(void);
|
||||
uint32_t HAL_SBS_GetPMOSVddCompensationValue(void);
|
||||
uint32_t HAL_SBS_GetNMOSVddIO2CompensationValue(void);
|
||||
uint32_t HAL_SBS_GetPMOSVddIO2CompensationValue(void);
|
||||
void HAL_SBS_FLASH_EnableECCNMI(void);
|
||||
void HAL_SBS_FLASH_DisableECCNMI(void);
|
||||
uint32_t HAL_SBS_FLASH_ECCNMI_IsDisabled(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HAL_Exported_Functions_Group6
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* SBS Boot control functions ***************************************************/
|
||||
void HAL_SBS_IncrementHDPLValue(void);
|
||||
uint32_t HAL_SBS_GetHDPLValue(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HAL_Exported_Functions_Group7
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* SBS Hardware secure storage control functions ********************************/
|
||||
void HAL_SBS_EPOCHSelection(uint32_t Epoch_Selection);
|
||||
uint32_t HAL_SBS_GetEPOCHSelection(void);
|
||||
void HAL_SBS_SetOBKHDPL(uint32_t OBKHDPL_Value);
|
||||
uint32_t HAL_SBS_GetOBKHDPL(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HAL_Exported_Functions_Group8
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* SBS Debug control functions ***************************************************/
|
||||
void HAL_SBS_OpenAccessPort(void);
|
||||
void HAL_SBS_OpenDebug(void);
|
||||
HAL_StatusTypeDef HAL_SBS_ConfigDebugLevel(uint32_t Level);
|
||||
uint32_t HAL_SBS_GetDebugLevel(void);
|
||||
void HAL_SBS_LockDebugConfig(void);
|
||||
void HAL_SBS_ConfigDebugSecurity(uint32_t Security);
|
||||
uint32_t HAL_SBS_GetDebugSecurity(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup HAL_Exported_Functions_Group9
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* SBS Lock functions ********************************************/
|
||||
void HAL_SBS_Lock(uint32_t Item);
|
||||
HAL_StatusTypeDef HAL_SBS_GetLock(uint32_t *pItem);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HAL_Exported_Functions_Group10
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* SBS Attributes functions ********************************************/
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
void HAL_SBS_ConfigAttributes(uint32_t Item, uint32_t Attributes);
|
||||
HAL_StatusTypeDef HAL_SBS_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes);
|
||||
#endif /* __ARM_FEATURE_CMSE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* __STM32H5xx_HAL_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,804 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h5xx_hal_cec.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CEC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H5xx_HAL_CEC_H
|
||||
#define STM32H5xx_HAL_CEC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h5xx_hal_def.h"
|
||||
|
||||
#if defined (CEC)
|
||||
|
||||
/** @addtogroup STM32H5xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CEC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup CEC_Exported_Types CEC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief CEC Init Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SignalFreeTime; /*!< Set SFT field, specifies the Signal Free Time.
|
||||
It can be one of CEC_Signal_Free_Time
|
||||
and belongs to the set {0,...,7} where
|
||||
0x0 is the default configuration
|
||||
else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */
|
||||
|
||||
uint32_t Tolerance; /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms,
|
||||
it can be a value of CEC_Tolerance :
|
||||
it is either CEC_STANDARD_TOLERANCE or CEC_EXTENDED_TOLERANCE */
|
||||
|
||||
uint32_t BRERxStop; /*!< Set BRESTP bit CEC_BRERxStop : specifies whether or not a Bit Rising
|
||||
Error stops the reception.
|
||||
CEC_NO_RX_STOP_ON_BRE: reception is not stopped.
|
||||
CEC_RX_STOP_ON_BRE: reception is stopped. */
|
||||
|
||||
uint32_t BREErrorBitGen; /*!< Set BREGEN bit CEC_BREErrorBitGen : specifies whether or not an
|
||||
Error-Bit is generated on the
|
||||
CEC line upon Bit Rising Error detection.
|
||||
CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation.
|
||||
CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */
|
||||
|
||||
uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit CEC_LBPEErrorBitGen : specifies whether or not an
|
||||
Error-Bit is generated on the
|
||||
CEC line upon Long Bit Period Error detection.
|
||||
CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation.
|
||||
CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */
|
||||
|
||||
uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit CEC_BroadCastMsgErrorBitGen : allows to avoid an
|
||||
Error-Bit generation on the CEC line
|
||||
upon an error detected on a broadcast message.
|
||||
|
||||
It supersedes BREGEN and LBPEGEN bits for a broadcast message error
|
||||
handling. It can take two values:
|
||||
|
||||
1) CEC_BROADCASTERROR_ERRORBIT_GENERATION.
|
||||
a) BRE detection: error-bit generation on the CEC line if
|
||||
BRESTP=CEC_RX_STOP_ON_BRE and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.
|
||||
b) LBPE detection: error-bit generation on the CEC line
|
||||
if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.
|
||||
|
||||
2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION.
|
||||
no error-bit generation in case neither a) nor b) are satisfied.
|
||||
Additionally, there is no error-bit generation in case of Short Bit
|
||||
Period Error detection in a broadcast message while LSTN bit is set. */
|
||||
|
||||
uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit CEC_SFT_Option : specifies when SFT timer starts.
|
||||
CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software.
|
||||
CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end
|
||||
of message transmission/reception. */
|
||||
|
||||
uint32_t ListenMode; /*!< Set LSTN bit CEC_Listening_Mode : specifies device listening mode.
|
||||
It can take two values:
|
||||
|
||||
CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed
|
||||
to its own address (OAR). Messages addressed to different destination
|
||||
are ignored.
|
||||
Broadcast messages are always received.
|
||||
|
||||
CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its
|
||||
own address (OAR) with positive acknowledge. Messages addressed to
|
||||
different destination are received, but without interfering with the
|
||||
CEC bus: no acknowledge sent. */
|
||||
|
||||
uint16_t OwnAddress; /*!< Own addresses configuration
|
||||
This parameter can be a value of CEC_OWN_ADDRESS */
|
||||
|
||||
uint8_t *RxBuffer; /*!< CEC Rx buffer pointer */
|
||||
|
||||
|
||||
} CEC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL CEC State definition
|
||||
* @note HAL CEC State value is a combination of 2 different substates: gState and RxState
|
||||
(see CEC_State_Definition).
|
||||
* - gState contains CEC state information related to global Handle management
|
||||
* and also information related to Tx operations.
|
||||
* gState value coding follow below described bitmap :
|
||||
* b7 (not used)
|
||||
* x : Should be set to 0
|
||||
* b6 Error information
|
||||
* 0 : No Error
|
||||
* 1 : Error
|
||||
* b5 CEC peripheral initialization status
|
||||
* 0 : Reset (peripheral not initialized)
|
||||
* 1 : Init done (peripheral initialized. HAL CEC Init function already called)
|
||||
* b4-b3 (not used)
|
||||
* xx : Should be set to 00
|
||||
* b2 Intrinsic process state
|
||||
* 0 : Ready
|
||||
* 1 : Busy (peripheral busy with some configuration or internal operations)
|
||||
* b1 (not used)
|
||||
* x : Should be set to 0
|
||||
* b0 Tx state
|
||||
* 0 : Ready (no Tx operation ongoing)
|
||||
* 1 : Busy (Tx operation ongoing)
|
||||
* - RxState contains information related to Rx operations.
|
||||
* RxState value coding follow below described bitmap :
|
||||
* b7-b6 (not used)
|
||||
* xx : Should be set to 00
|
||||
* b5 CEC peripheral initialization status
|
||||
* 0 : Reset (peripheral not initialized)
|
||||
* 1 : Init done (peripheral initialized)
|
||||
* b4-b2 (not used)
|
||||
* xxx : Should be set to 000
|
||||
* b1 Rx state
|
||||
* 0 : Ready (no Rx operation ongoing)
|
||||
* 1 : Busy (Rx operation ongoing)
|
||||
* b0 (not used)
|
||||
* x : Should be set to 0.
|
||||
*/
|
||||
typedef uint32_t HAL_CEC_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CEC handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __CEC_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
|
||||
{
|
||||
CEC_TypeDef *Instance; /*!< CEC registers base address */
|
||||
|
||||
CEC_InitTypeDef Init; /*!< CEC communication parameters */
|
||||
|
||||
const uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */
|
||||
|
||||
uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */
|
||||
|
||||
uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||
|
||||
HAL_CEC_StateTypeDef gState; /*!< CEC state information related to global Handle management
|
||||
and also related to Tx operations.
|
||||
This parameter can be a value of HAL_CEC_StateTypeDef */
|
||||
|
||||
HAL_CEC_StateTypeDef RxState; /*!< CEC state information related to Rx operations.
|
||||
This parameter can be a value of HAL_CEC_StateTypeDef */
|
||||
|
||||
uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register
|
||||
in case error is reported */
|
||||
|
||||
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
|
||||
void (* TxCpltCallback)(struct __CEC_HandleTypeDef
|
||||
*hcec); /*!< CEC Tx Transfer completed callback */
|
||||
void (* RxCpltCallback)(struct __CEC_HandleTypeDef *hcec,
|
||||
uint32_t RxFrameSize); /*!< CEC Rx Transfer completed callback */
|
||||
void (* ErrorCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC error callback */
|
||||
|
||||
void (* MspInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp DeInit callback */
|
||||
|
||||
#endif /* (USE_HAL_CEC_REGISTER_CALLBACKS) */
|
||||
} CEC_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL CEC Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CEC_TX_CPLT_CB_ID = 0x00U, /*!< CEC Tx Transfer completed callback ID */
|
||||
HAL_CEC_RX_CPLT_CB_ID = 0x01U, /*!< CEC Rx Transfer completed callback ID */
|
||||
HAL_CEC_ERROR_CB_ID = 0x02U, /*!< CEC error callback ID */
|
||||
HAL_CEC_MSPINIT_CB_ID = 0x03U, /*!< CEC Msp Init callback ID */
|
||||
HAL_CEC_MSPDEINIT_CB_ID = 0x04U /*!< CEC Msp DeInit callback ID */
|
||||
} HAL_CEC_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL CEC Callback pointer definition
|
||||
*/
|
||||
typedef void (*pCEC_CallbackTypeDef)(CEC_HandleTypeDef *hcec); /*!< pointer to an CEC callback function */
|
||||
typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec,
|
||||
uint32_t RxFrameSize); /*!< pointer to an Rx Transfer completed
|
||||
callback function */
|
||||
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CEC_Exported_Constants CEC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup CEC_State_Definition CEC State Code Definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_CEC_STATE_RESET ((uint32_t)0x00000000) /*!< Peripheral is not yet Initialized
|
||||
Value is allowed for gState and RxState */
|
||||
#define HAL_CEC_STATE_READY ((uint32_t)0x00000020) /*!< Peripheral Initialized and ready for use
|
||||
Value is allowed for gState and RxState */
|
||||
#define HAL_CEC_STATE_BUSY ((uint32_t)0x00000024) /*!< an internal process is ongoing
|
||||
Value is allowed for gState only */
|
||||
#define HAL_CEC_STATE_BUSY_RX ((uint32_t)0x00000022) /*!< Data Reception process is ongoing
|
||||
Value is allowed for RxState only */
|
||||
#define HAL_CEC_STATE_BUSY_TX ((uint32_t)0x00000021) /*!< Data Transmission process is ongoing
|
||||
Value is allowed for gState only */
|
||||
#define HAL_CEC_STATE_BUSY_RX_TX ((uint32_t)0x00000023) /*!< an internal process is ongoing
|
||||
Value is allowed for gState only */
|
||||
#define HAL_CEC_STATE_ERROR ((uint32_t)0x00000050) /*!< Error Value is allowed for gState only */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup CEC_Error_Code CEC Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_CEC_ERROR_NONE (uint32_t) 0x0000U /*!< no error */
|
||||
#define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR /*!< CEC Rx-Overrun */
|
||||
#define HAL_CEC_ERROR_BRE CEC_ISR_BRE /*!< CEC Rx Bit Rising Error */
|
||||
#define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE /*!< CEC Rx Short Bit period Error */
|
||||
#define HAL_CEC_ERROR_LBPE CEC_ISR_LBPE /*!< CEC Rx Long Bit period Error */
|
||||
#define HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE /*!< CEC Rx Missing Acknowledge */
|
||||
#define HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST /*!< CEC Arbitration Lost */
|
||||
#define HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR /*!< CEC Tx-Buffer Underrun */
|
||||
#define HAL_CEC_ERROR_TXERR CEC_ISR_TXERR /*!< CEC Tx-Error */
|
||||
#define HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE /*!< CEC Tx Missing Acknowledge */
|
||||
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_CEC_ERROR_INVALID_CALLBACK ((uint32_t)0x00002000U) /*!< Invalid Callback Error */
|
||||
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Signal_Free_Time CEC Signal Free Time setting parameter
|
||||
* @{
|
||||
*/
|
||||
#define CEC_DEFAULT_SFT ((uint32_t)0x00000000U)
|
||||
#define CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001U)
|
||||
#define CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002U)
|
||||
#define CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003U)
|
||||
#define CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004U)
|
||||
#define CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005U)
|
||||
#define CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006U)
|
||||
#define CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Tolerance CEC Receiver Tolerance
|
||||
* @{
|
||||
*/
|
||||
#define CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000U)
|
||||
#define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_BRERxStop CEC Reception Stop on Error
|
||||
* @{
|
||||
*/
|
||||
#define CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000U)
|
||||
#define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_BREErrorBitGen CEC Error Bit Generation if Bit Rise Error reported
|
||||
* @{
|
||||
*/
|
||||
#define CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)
|
||||
#define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_LBPEErrorBitGen CEC Error Bit Generation if Long Bit Period Error reported
|
||||
* @{
|
||||
*/
|
||||
#define CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)
|
||||
#define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_BroadCastMsgErrorBitGen CEC Error Bit Generation on Broadcast message
|
||||
* @{
|
||||
*/
|
||||
#define CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000U)
|
||||
#define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_SFT_Option CEC Signal Free Time start option
|
||||
* @{
|
||||
*/
|
||||
#define CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000U)
|
||||
#define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Listening_Mode CEC Listening mode option
|
||||
* @{
|
||||
*/
|
||||
#define CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000U)
|
||||
#define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_OAR_Position CEC Device Own Address position in CEC CFGR register
|
||||
* @{
|
||||
*/
|
||||
#define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Initiator_Position CEC Initiator logical address position in message header
|
||||
* @{
|
||||
*/
|
||||
#define CEC_INITIATOR_LSB_POS ((uint32_t) 4U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_OWN_ADDRESS CEC Own Address
|
||||
* @{
|
||||
*/
|
||||
#define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */
|
||||
#define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0 */
|
||||
#define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1 */
|
||||
#define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2 */
|
||||
#define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3 */
|
||||
#define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4 */
|
||||
#define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5 */
|
||||
#define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6 */
|
||||
#define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7 */
|
||||
#define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9 */
|
||||
#define CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) /* Logical Address 10 */
|
||||
#define CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) /* Logical Address 11 */
|
||||
#define CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) /* Logical Address 12 */
|
||||
#define CEC_OWN_ADDRESS_12 ((uint16_t) 0x1000U) /* Logical Address 13 */
|
||||
#define CEC_OWN_ADDRESS_13 ((uint16_t) 0x2000U) /* Logical Address 14 */
|
||||
#define CEC_OWN_ADDRESS_14 ((uint16_t) 0x4000U) /* Logical Address 15 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Interrupts_Definitions CEC Interrupts definition
|
||||
* @{
|
||||
*/
|
||||
#define CEC_IT_TXACKE CEC_IER_TXACKEIE
|
||||
#define CEC_IT_TXERR CEC_IER_TXERRIE
|
||||
#define CEC_IT_TXUDR CEC_IER_TXUDRIE
|
||||
#define CEC_IT_TXEND CEC_IER_TXENDIE
|
||||
#define CEC_IT_TXBR CEC_IER_TXBRIE
|
||||
#define CEC_IT_ARBLST CEC_IER_ARBLSTIE
|
||||
#define CEC_IT_RXACKE CEC_IER_RXACKEIE
|
||||
#define CEC_IT_LBPE CEC_IER_LBPEIE
|
||||
#define CEC_IT_SBPE CEC_IER_SBPEIE
|
||||
#define CEC_IT_BRE CEC_IER_BREIE
|
||||
#define CEC_IT_RXOVR CEC_IER_RXOVRIE
|
||||
#define CEC_IT_RXEND CEC_IER_RXENDIE
|
||||
#define CEC_IT_RXBR CEC_IER_RXBRIE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Flags_Definitions CEC Flags definition
|
||||
* @{
|
||||
*/
|
||||
#define CEC_FLAG_TXACKE CEC_ISR_TXACKE
|
||||
#define CEC_FLAG_TXERR CEC_ISR_TXERR
|
||||
#define CEC_FLAG_TXUDR CEC_ISR_TXUDR
|
||||
#define CEC_FLAG_TXEND CEC_ISR_TXEND
|
||||
#define CEC_FLAG_TXBR CEC_ISR_TXBR
|
||||
#define CEC_FLAG_ARBLST CEC_ISR_ARBLST
|
||||
#define CEC_FLAG_RXACKE CEC_ISR_RXACKE
|
||||
#define CEC_FLAG_LBPE CEC_ISR_LBPE
|
||||
#define CEC_FLAG_SBPE CEC_ISR_SBPE
|
||||
#define CEC_FLAG_BRE CEC_ISR_BRE
|
||||
#define CEC_FLAG_RXOVR CEC_ISR_RXOVR
|
||||
#define CEC_FLAG_RXEND CEC_ISR_RXEND
|
||||
#define CEC_FLAG_RXBR CEC_ISR_RXBR
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags
|
||||
* @{
|
||||
*/
|
||||
#define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
|
||||
CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag
|
||||
* @{
|
||||
*/
|
||||
#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag
|
||||
* @{
|
||||
*/
|
||||
#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup CEC_Exported_Macros CEC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset CEC handle gstate & RxState
|
||||
* @param __HANDLE__ CEC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->gState = HAL_CEC_STATE_RESET; \
|
||||
(__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->gState = HAL_CEC_STATE_RESET; \
|
||||
(__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \
|
||||
} while(0)
|
||||
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
|
||||
/** @brief Checks whether or not the specified CEC interrupt flag is set.
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
|
||||
* @arg CEC_FLAG_TXERR: Tx Error.
|
||||
* @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
|
||||
* @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
|
||||
* @arg CEC_FLAG_TXBR: Tx-Byte Request.
|
||||
* @arg CEC_FLAG_ARBLST: Arbitration Lost
|
||||
* @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
|
||||
* @arg CEC_FLAG_LBPE: Rx Long period Error
|
||||
* @arg CEC_FLAG_SBPE: Rx Short period Error
|
||||
* @arg CEC_FLAG_BRE: Rx Bit Rising Error
|
||||
* @arg CEC_FLAG_RXOVR: Rx Overrun.
|
||||
* @arg CEC_FLAG_RXEND: End Of Reception.
|
||||
* @arg CEC_FLAG_RXBR: Rx-Byte Received.
|
||||
* @retval ITStatus
|
||||
*/
|
||||
#define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
|
||||
|
||||
/** @brief Clears the interrupt or status flag when raised (write at 1)
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @param __FLAG__ specifies the interrupt/status flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
|
||||
* @arg CEC_FLAG_TXERR: Tx Error.
|
||||
* @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
|
||||
* @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
|
||||
* @arg CEC_FLAG_TXBR: Tx-Byte Request.
|
||||
* @arg CEC_FLAG_ARBLST: Arbitration Lost
|
||||
* @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
|
||||
* @arg CEC_FLAG_LBPE: Rx Long period Error
|
||||
* @arg CEC_FLAG_SBPE: Rx Short period Error
|
||||
* @arg CEC_FLAG_BRE: Rx Bit Rising Error
|
||||
* @arg CEC_FLAG_RXOVR: Rx Overrun.
|
||||
* @arg CEC_FLAG_RXEND: End Of Reception.
|
||||
* @arg CEC_FLAG_RXBR: Rx-Byte Received.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__))
|
||||
|
||||
/** @brief Enables the specified CEC interrupt.
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @param __INTERRUPT__ specifies the CEC interrupt to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
|
||||
* @arg CEC_IT_TXERR: Tx Error IT Enable
|
||||
* @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
|
||||
* @arg CEC_IT_TXEND: End of transmission IT Enable
|
||||
* @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
|
||||
* @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
|
||||
* @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
|
||||
* @arg CEC_IT_LBPE: Rx Long period Error IT Enable
|
||||
* @arg CEC_IT_SBPE: Rx Short period Error IT Enable
|
||||
* @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
|
||||
* @arg CEC_IT_RXOVR: Rx Overrun IT Enable
|
||||
* @arg CEC_IT_RXEND: End Of Reception IT Enable
|
||||
* @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
|
||||
|
||||
/** @brief Disables the specified CEC interrupt.
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @param __INTERRUPT__ specifies the CEC interrupt to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
|
||||
* @arg CEC_IT_TXERR: Tx Error IT Enable
|
||||
* @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
|
||||
* @arg CEC_IT_TXEND: End of transmission IT Enable
|
||||
* @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
|
||||
* @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
|
||||
* @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
|
||||
* @arg CEC_IT_LBPE: Rx Long period Error IT Enable
|
||||
* @arg CEC_IT_SBPE: Rx Short period Error IT Enable
|
||||
* @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
|
||||
* @arg CEC_IT_RXOVR: Rx Overrun IT Enable
|
||||
* @arg CEC_IT_RXEND: End Of Reception IT Enable
|
||||
* @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
|
||||
|
||||
/** @brief Checks whether or not the specified CEC interrupt is enabled.
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @param __INTERRUPT__ specifies the CEC interrupt to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
|
||||
* @arg CEC_IT_TXERR: Tx Error IT Enable
|
||||
* @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
|
||||
* @arg CEC_IT_TXEND: End of transmission IT Enable
|
||||
* @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
|
||||
* @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
|
||||
* @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
|
||||
* @arg CEC_IT_LBPE: Rx Long period Error IT Enable
|
||||
* @arg CEC_IT_SBPE: Rx Short period Error IT Enable
|
||||
* @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
|
||||
* @arg CEC_IT_RXOVR: Rx Overrun IT Enable
|
||||
* @arg CEC_IT_RXEND: End Of Reception IT Enable
|
||||
* @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
|
||||
* @retval FlagStatus
|
||||
*/
|
||||
#define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
|
||||
|
||||
/** @brief Enables the CEC device
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN)
|
||||
|
||||
/** @brief Disables the CEC device
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN)
|
||||
|
||||
/** @brief Set Transmission Start flag
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM)
|
||||
|
||||
/** @brief Set Transmission End flag
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @retval none
|
||||
* If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.
|
||||
*/
|
||||
#define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM)
|
||||
|
||||
/** @brief Get Transmission Start flag
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @retval FlagStatus
|
||||
*/
|
||||
#define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
|
||||
|
||||
/** @brief Get Transmission End flag
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @retval FlagStatus
|
||||
*/
|
||||
#define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
|
||||
|
||||
/** @brief Clear OAR register
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
|
||||
|
||||
/** @brief Set OAR register (without resetting previously set address in case of multi-address mode)
|
||||
* To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @param __ADDRESS__ Own Address value (CEC logical address is identified by bit position)
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, \
|
||||
(__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup CEC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CEC_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
|
||||
HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
|
||||
HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress);
|
||||
void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
|
||||
void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
|
||||
|
||||
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID,
|
||||
pCEC_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_CEC_UnRegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID);
|
||||
|
||||
HAL_StatusTypeDef HAL_CEC_RegisterRxCpltCallback(CEC_HandleTypeDef *hcec, pCEC_RxCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec);
|
||||
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CEC_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* I/O operation functions ***************************************************/
|
||||
HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress,
|
||||
const uint8_t *pData, uint32_t Size);
|
||||
uint32_t HAL_CEC_GetLastReceivedFrameSize(const CEC_HandleTypeDef *hcec);
|
||||
void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer);
|
||||
void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
|
||||
void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
|
||||
void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize);
|
||||
void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CEC_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions ************************************************/
|
||||
HAL_CEC_StateTypeDef HAL_CEC_GetState(const CEC_HandleTypeDef *hcec);
|
||||
uint32_t HAL_CEC_GetError(const CEC_HandleTypeDef *hcec);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/** @defgroup CEC_Private_Types CEC Private Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup CEC_Private_Variables CEC Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup CEC_Private_Constants CEC Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup CEC_Private_Macros CEC Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT)
|
||||
|
||||
#define IS_CEC_TOLERANCE(__RXTOL__) (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \
|
||||
((__RXTOL__) == CEC_EXTENDED_TOLERANCE))
|
||||
|
||||
#define IS_CEC_BRERXSTOP(__BRERXSTOP__) (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \
|
||||
((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE))
|
||||
|
||||
#define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \
|
||||
((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION))
|
||||
|
||||
#define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \
|
||||
((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION))
|
||||
|
||||
#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) \
|
||||
(((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
|
||||
((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))
|
||||
|
||||
#define IS_CEC_SFTOP(__SFTOP__) (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \
|
||||
((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END))
|
||||
|
||||
#define IS_CEC_LISTENING_MODE(__MODE__) (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \
|
||||
((__MODE__) == CEC_FULL_LISTENING_MODE))
|
||||
|
||||
/** @brief Check CEC message size.
|
||||
* The message size is the payload size: without counting the header,
|
||||
* it varies from 0 byte (ping operation, one header only, no payload) to
|
||||
* 15 bytes (1 opcode and up to 14 operands following the header).
|
||||
* @param __SIZE__ CEC message size.
|
||||
* @retval Test result (TRUE or FALSE).
|
||||
*/
|
||||
#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U)
|
||||
|
||||
/** @brief Check CEC device Own Address Register (OAR) setting.
|
||||
* OAR address is written in a 15-bit field within CEC_CFGR register.
|
||||
* @param __ADDRESS__ CEC own address.
|
||||
* @retval Test result (TRUE or FALSE).
|
||||
*/
|
||||
#define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFFU)
|
||||
|
||||
/** @brief Check CEC initiator or destination logical address setting.
|
||||
* Initiator and destination addresses are coded over 4 bits.
|
||||
* @param __ADDRESS__ CEC initiator or logical address.
|
||||
* @retval Test result (TRUE or FALSE).
|
||||
*/
|
||||
#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xFU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup CEC_Private_Functions CEC Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* CEC */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H5xxHAL_CEC_H */
|
||||
|
|
@ -0,0 +1,622 @@
|
|||
/**
|
||||
**********************************************************************************************************************
|
||||
* @file stm32h5xx_hal_comp.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of COMP HAL module.
|
||||
**********************************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
**********************************************************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/
|
||||
#ifndef STM32H5xx_HAL_COMP_H
|
||||
#define STM32H5xx_HAL_COMP_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ----------------------------------------------------------------------------------------------------------*/
|
||||
#include "stm32h5xx_hal_def.h"
|
||||
#include "stm32h5xx_ll_exti.h"
|
||||
|
||||
/** @addtogroup STM32H5xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
#if defined (COMP1)
|
||||
|
||||
/** @addtogroup COMP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ----------------------------------------------------------------------------------------------------*/
|
||||
/** @defgroup COMP_Exported_Types COMP Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief COMP Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Mode; /*!< Set comparator operating mode to adjust power and speed.
|
||||
Note: For the characteristics of comparator power modes
|
||||
(propagation delay and power consumption), refer to device datasheet.
|
||||
This parameter can be a value of @ref COMP_PowerMode */
|
||||
|
||||
uint32_t InputPlus; /*!< Set comparator input plus (non-inverting input).
|
||||
This parameter can be a value of @ref COMP_InputPlus */
|
||||
|
||||
uint32_t InputMinus; /*!< Set comparator input minus (inverting input).
|
||||
This parameter can be a value of @ref COMP_InputMinus */
|
||||
|
||||
uint32_t Hysteresis; /*!< Set comparator hysteresis mode of the input minus.
|
||||
This parameter can be a value of @ref COMP_Hysteresis */
|
||||
|
||||
uint32_t OutputPol; /*!< Set comparator output polarity.
|
||||
This parameter can be a value of @ref COMP_OutputPolarity
|
||||
Note: Specific to comparator of this STM32 series: comparator output
|
||||
triggers interruption on high level. HAL_COMP_Start_x functions
|
||||
can change output polarity depending on initial output level. */
|
||||
|
||||
uint32_t BlankingSrce; /*!< Set comparator blanking source.
|
||||
This parameter can be a value of @ref COMP_BlankingSrce */
|
||||
|
||||
uint32_t TriggerMode; /*!< Set the comparator output triggering External Interrupt Line (EXTI).
|
||||
This parameter can be a value of @ref COMP_EXTI_TriggerMode */
|
||||
|
||||
} COMP_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL COMP state machine: HAL COMP states definition
|
||||
*/
|
||||
#define COMP_STATE_BITFIELD_LOCK (0x10U)
|
||||
typedef enum
|
||||
{
|
||||
HAL_COMP_STATE_RESET = 0x00, /*!< COMP not yet initialized */
|
||||
HAL_COMP_STATE_RESET_LOCKED = (HAL_COMP_STATE_RESET | \
|
||||
COMP_STATE_BITFIELD_LOCK), /*!< COMP not yet initialized and configuration is locked */
|
||||
HAL_COMP_STATE_READY = 0x01, /*!< COMP initialized and ready for use */
|
||||
HAL_COMP_STATE_READY_LOCKED = (HAL_COMP_STATE_READY | \
|
||||
COMP_STATE_BITFIELD_LOCK), /*!< COMP initialized but configuration is locked */
|
||||
HAL_COMP_STATE_BUSY = 0x02, /*!< COMP is running */
|
||||
HAL_COMP_STATE_BUSY_LOCKED = (HAL_COMP_STATE_BUSY | \
|
||||
COMP_STATE_BITFIELD_LOCK) /*!< COMP is running and configuration is locked */
|
||||
|
||||
} HAL_COMP_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief COMP Handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1U)
|
||||
typedef struct __COMP_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
|
||||
{
|
||||
COMP_TypeDef *Instance; /*!< Register base address */
|
||||
COMP_InitTypeDef Init; /*!< COMP required parameters */
|
||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||
__IO HAL_COMP_StateTypeDef State; /*!< COMP communication state */
|
||||
__IO uint32_t ErrorCode; /*!< COMP error code */
|
||||
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1U)
|
||||
void (* TriggerCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP trigger callback */
|
||||
void (* MspInitCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP Msp DeInit callback */
|
||||
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
|
||||
uint8_t InterruptAutoRearm; /*!< COMP interrupt auto rearm setting */
|
||||
} COMP_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1U)
|
||||
/**
|
||||
* @brief HAL COMP Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_COMP_TRIGGER_CB_ID = 0x00U, /*!< COMP trigger callback ID */
|
||||
HAL_COMP_MSPINIT_CB_ID = 0x01U, /*!< COMP Msp Init callback ID */
|
||||
HAL_COMP_MSPDEINIT_CB_ID = 0x02U /*!< COMP Msp DeInit callback ID */
|
||||
|
||||
} HAL_COMP_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL COMP Callback pointer definition
|
||||
*/
|
||||
typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer to a COMP callback function */
|
||||
|
||||
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants ------------------------------------------------------------------------------------------------*/
|
||||
/** @defgroup COMP_Exported_Constants COMP Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Error_Code COMP Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_COMP_ERROR_NONE (0x00UL) /*!< No error */
|
||||
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1U)
|
||||
#define HAL_COMP_ERROR_INVALID_CALLBACK (0x01U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_PowerMode COMP power mode
|
||||
* @{
|
||||
*/
|
||||
/* Note: For the characteristics of comparator power modes */
|
||||
/* (propagation delay and power consumption), */
|
||||
/* refer to device datasheet. */
|
||||
#define COMP_POWERMODE_HIGHSPEED (0x00000000UL) /*!< High Speed */
|
||||
#define COMP_POWERMODE_MEDIUMSPEED (COMP_CFGR1_PWRMODE_0) /*!< Medium Speed */
|
||||
#define COMP_POWERMODE_ULTRALOWPOWER (COMP_CFGR1_PWRMODE) /*!< Ultra-low power mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_InputPlus COMP input plus (non-inverting input)
|
||||
* @{
|
||||
*/
|
||||
#define COMP_INPUT_PLUS_IO1 (0x00000000UL) /*!< Comparator input plus connected to IO1 (pin PB0) */
|
||||
#define COMP_INPUT_PLUS_IO2 (COMP_CFGR2_INPSEL0) /*!< Comparator input plus connected to IO2 (pin PA0) */
|
||||
#define COMP_INPUT_PLUS_IO3 (COMP_CFGR1_INPSEL1) /*!< Comparator input plus connected to IO3 (pin PB2) */
|
||||
#define COMP_INPUT_PLUS_DAC1_CH1 (COMP_CFGR1_INPSEL2) /*!< Comparator input plus connected to (DAC1_CH1) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_InputMinus COMP input minus (inverting input)
|
||||
* @{
|
||||
*/
|
||||
#define COMP_INPUT_MINUS_1_4VREFINT (COMP_CFGR1_SCALEN |\
|
||||
COMP_CFGR1_BRGEN) /*!< Comparator input minus connected to 1/4 VrefInt */
|
||||
#define COMP_INPUT_MINUS_1_2VREFINT (COMP_CFGR1_INMSEL_0 |\
|
||||
COMP_CFGR1_SCALEN |\
|
||||
COMP_CFGR1_BRGEN) /*!< Comparator input minus connected to 1/2 VrefInt */
|
||||
#define COMP_INPUT_MINUS_3_4VREFINT (COMP_CFGR1_INMSEL_1 |\
|
||||
COMP_CFGR1_SCALEN |\
|
||||
COMP_CFGR1_BRGEN) /*!< Comparator input minus connected to 3/4 VrefInt */
|
||||
#define COMP_INPUT_MINUS_VREFINT (COMP_CFGR1_INMSEL_1 |\
|
||||
COMP_CFGR1_INMSEL_0 |\
|
||||
COMP_CFGR1_SCALEN) /*!< Comparator input minus connected to VrefInt */
|
||||
#define COMP_INPUT_MINUS_DAC1_CH1 (COMP_CFGR1_INMSEL_2) /*!< Comparator input minus connected to DAC1 channel 1 */
|
||||
#define COMP_INPUT_MINUS_IO1 (COMP_CFGR1_INMSEL_2 |\
|
||||
COMP_CFGR1_INMSEL_0) /*!< Comparator input minus connected to IO1 (pin PC4) */
|
||||
#define COMP_INPUT_MINUS_IO2 (COMP_CFGR1_INMSEL_2 |\
|
||||
COMP_CFGR1_INMSEL_1) /*!< Comparator input minus connected to IO2 (pin PB1) */
|
||||
#define COMP_INPUT_MINUS_IO3 (COMP_CFGR1_INMSEL_2 |\
|
||||
COMP_CFGR1_INMSEL_1 |\
|
||||
COMP_CFGR1_INMSEL_0) /*!< Comparator input minus connected to IO3 (pin PA5) */
|
||||
#define COMP_INPUT_MINUS_TEMPSENSOR (COMP_CFGR1_INMSEL_3) /*!< Comparator input minus connected to internal
|
||||
temperature sensor (also accessible through ADC peripheral) */
|
||||
#define COMP_INPUT_MINUS_VBAT (COMP_CFGR1_INMSEL_3 |\
|
||||
COMP_CFGR1_INMSEL_0) /*!< Comparator input minus connected to Vbat/4:
|
||||
Vbat voltage through a divider ladder of factor 1/4 to have input voltage
|
||||
always below Vdda. */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Hysteresis COMP hysteresis
|
||||
* @{
|
||||
*/
|
||||
#define COMP_HYSTERESIS_NONE (0x00000000UL) /*!< No hysteresis */
|
||||
#define COMP_HYSTERESIS_LOW (COMP_CFGR1_HYST_0) /*!< Hysteresis level low */
|
||||
#define COMP_HYSTERESIS_MEDIUM (COMP_CFGR1_HYST_1) /*!< Hysteresis level medium */
|
||||
#define COMP_HYSTERESIS_HIGH (COMP_CFGR1_HYST_0 | COMP_CFGR1_HYST_1) /*!< Hysteresis level high */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_OutputPolarity COMP output Polarity
|
||||
* @{
|
||||
*/
|
||||
#define COMP_OUTPUTPOL_NONINVERTED (0x00000000UL) /*!< COMP output level is not inverted (comparator output
|
||||
is high when the input plus is at a higher voltage
|
||||
than the input minus) */
|
||||
#define COMP_OUTPUTPOL_INVERTED (COMP_CFGR1_POLARITY) /*!< COMP output level is inverted (comparator output is
|
||||
low when the input plus is at a higher voltage than
|
||||
the input minus) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_BlankingSrce COMP blanking source
|
||||
* @{
|
||||
*/
|
||||
#define COMP_BLANKINGSRC_NONE (0x00000000UL) /*!< Comparator output without blanking */
|
||||
#define COMP_BLANKINGSRC_TIM1_OC5 (COMP_CFGR1_BLANKING_0) /*!< TIM1 OC5 selected as blanking source */
|
||||
#define COMP_BLANKINGSRC_TIM2_OC3 (COMP_CFGR1_BLANKING_1) /*!< TIM2 OC3 selected as blanking source */
|
||||
#define COMP_BLANKINGSRC_TIM3_OC3 (COMP_CFGR1_BLANKING_0 |\
|
||||
COMP_CFGR1_BLANKING_1) /*!< TIM3 OC3 selected as blanking source */
|
||||
#define COMP_BLANKINGSRC_TIM3_OC4 (COMP_CFGR1_BLANKING_2) /*!< TIM3 OC4 selected as blanking source */
|
||||
#define COMP_BLANKINGSRC_LPTIM1_OC2 (COMP_CFGR1_BLANKING_2 |\
|
||||
COMP_CFGR1_BLANKING_0) /*!< LPTIM1 OC2 selected as blanking source */
|
||||
#define COMP_BLANKINGSRC_LPTIM2_OC2 (COMP_CFGR1_BLANKING_2 |\
|
||||
COMP_CFGR1_BLANKING_1) /*!< LPTIM2 OC2 selected as blanking source */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_OutputLevel COMP Output Level
|
||||
* @{
|
||||
*/
|
||||
/* Note: Comparator output level values are fixed to "0" and "1", */
|
||||
/* corresponding COMP register bit is managed by HAL function to match */
|
||||
/* with these values (independently of bit position in register). */
|
||||
|
||||
/* When output polarity is not inverted, comparator output is low when
|
||||
the input plus is at a lower voltage than the input minus */
|
||||
#define COMP_OUTPUT_LEVEL_LOW (0x00000000UL)
|
||||
/* When output polarity is not inverted, comparator output is high when
|
||||
the input plus is at a higher voltage than the input minus */
|
||||
#define COMP_OUTPUT_LEVEL_HIGH (0x00000001UL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_EXTI_TriggerMode COMP output to EXTI
|
||||
* @{
|
||||
*/
|
||||
#define COMP_TRIGGERMODE_NONE (0x00000000UL) /*!< Comparator output triggering no External
|
||||
Interrupt Line */
|
||||
#define COMP_TRIGGERMODE_IT_RISING_FALLING (COMP_EXTI_IT |\
|
||||
COMP_EXTI_RISING |\
|
||||
COMP_EXTI_FALLING) /*!< Comparator output triggering interrupt
|
||||
on rising and falling edges.
|
||||
Note: Specific to comparator of this STM32 series: comparator output
|
||||
triggers interruption on high level. HAL_COMP_Start_x functions
|
||||
can change output polarity depending on initial output level. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Flag COMP Flag
|
||||
* @{
|
||||
*/
|
||||
#define COMP_FLAG_C1I COMP_SR_C1IF /*!< Comparator 1 Interrupt Flag */
|
||||
#define COMP_FLAG_LOCK COMP_CFGR1_LOCK /*!< Lock flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_IT_CLEAR_Flags COMP Interruption Clear Flags
|
||||
* @{
|
||||
*/
|
||||
#define COMP_CLEAR_C1IF COMP_ICFR_CC1IF /*!< Clear Comparator 1 Interrupt Flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Interrupts_Definitions COMP Interrupts Definitions
|
||||
* @{
|
||||
*/
|
||||
#define COMP_IT_EN COMP_CFGR1_ITEN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ----------------------------------------------------------------------------------------------------*/
|
||||
/** @defgroup COMP_Exported_Macros COMP Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Handle_Management COMP Handle Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset COMP handle state.
|
||||
* @param __HANDLE__ COMP handle
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1U)
|
||||
#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_COMP_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
|
||||
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @brief Clear COMP error code (set it to no error code "HAL_COMP_ERROR_NONE").
|
||||
* @param __HANDLE__ COMP handle
|
||||
* @retval None
|
||||
*/
|
||||
#define COMP_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE)
|
||||
|
||||
/**
|
||||
* @brief Enable the specified comparator.
|
||||
* @param __HANDLE__ COMP handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CFGR1, COMP_CFGR1_EN)
|
||||
|
||||
/**
|
||||
* @brief Disable the specified comparator.
|
||||
* @param __HANDLE__ COMP handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR1, COMP_CFGR1_EN)
|
||||
|
||||
/**
|
||||
* @brief Lock the specified comparator configuration.
|
||||
* @note Using this macro induce HAL COMP handle state machine being no
|
||||
* more in line with COMP instance state.
|
||||
* To keep HAL COMP handle state machine updated, it is recommended
|
||||
* to use function "HAL_COMP_Lock')".
|
||||
* @param __HANDLE__ COMP handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_LOCK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CFGR1, COMP_CFGR1_LOCK)
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified comparator is locked.
|
||||
* @param __HANDLE__ COMP handle
|
||||
* @retval Value 0 if COMP instance is not locked, value 1 if COMP instance is locked
|
||||
*/
|
||||
#define __HAL_COMP_IS_LOCKED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CFGR1, COMP_CFGR1_LOCK) == COMP_CFGR1_LOCK)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Exti_Management COMP external interrupt line management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Checks if the specified COMP interrupt source is enabled or disabled.
|
||||
* @param __HANDLE__ specifies the COMP Handle.
|
||||
* This parameter can be COMP1.
|
||||
* @param __INTERRUPT__ specifies the COMP interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg COMP_IT_EN Comparator interrupt enable
|
||||
*
|
||||
* @retval State of interruption (TRUE or FALSE)
|
||||
*/
|
||||
#define __HAL_COMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
|
||||
((((__HANDLE__)->Instance->CFGR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Checks whether the specified COMP flag is set or not.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg COMP_FLAG_C1I Comparator 1 Interrupt Flag
|
||||
* @retval State of flag (TRUE or FALSE)
|
||||
*/
|
||||
#define __HAL_COMP_GET_FLAG(__FLAG__) ((COMP1->SR & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clears the specified COMP pending flag.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg COMP_CLEAR_C1IF Clear Comparator 1 Interrupt Flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_CLEAR_FLAG(__FLAG__) (COMP1->ICFR = (__FLAG__))
|
||||
|
||||
/** @brief Clear the COMP C1I flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_CLEAR_C1IFLAG() __HAL_COMP_CLEAR_FLAG( COMP_CLEAR_C1IF)
|
||||
|
||||
/** @brief Enable the specified COMP interrupt.
|
||||
* @param __HANDLE__ specifies the COMP Handle.
|
||||
* @param __INTERRUPT__ specifies the COMP interrupt source to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg COMP_CFGR1_ITEN Comparator interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFGR1) |= (__INTERRUPT__) )
|
||||
|
||||
/** @brief Disable the specified COMP interrupt.
|
||||
* @param __HANDLE__ specifies the COMP Handle.
|
||||
* @param __INTERRUPT__ specifies the COMP interrupt source to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg COMP_CFGR1_ITEN Comparator interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_DISABLE_IT(__HANDLE__,__INTERRUPT__) (((__HANDLE__)->Instance->CFGR1) &= ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -----------------------------------------------------------------------------------------------------*/
|
||||
/* Private constants -------------------------------------------------------------------------------------------------*/
|
||||
/** @defgroup COMP_Private_Constants COMP Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_ExtiLine COMP EXTI Lines
|
||||
* @{
|
||||
*/
|
||||
#define COMP_EXTI_LINE_COMP1 (EXTI_IMR1_IM29) /*!< EXTI line 29 connected to COMP1 output */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_ExtiLine COMP EXTI Lines
|
||||
* @{
|
||||
*/
|
||||
#define COMP_EXTI_IT (0x00000001UL) /*!< EXTI line event with interruption */
|
||||
#define COMP_EXTI_RISING (0x00000010UL) /*!< EXTI line event on rising edge */
|
||||
#define COMP_EXTI_FALLING (0x00000020UL) /*!< EXTI line event on falling edge */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ----------------------------------------------------------------------------------------------------*/
|
||||
/** @defgroup COMP_Private_Macros COMP Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_GET_EXTI_LINE COMP private macros to get EXTI line associated with comparators
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Get the specified EXTI line for a comparator instance.
|
||||
* @param __INSTANCE__ specifies the COMP instance.
|
||||
* @retval value of @ref COMP_ExtiLine
|
||||
*/
|
||||
#define COMP_GET_EXTI_LINE(__INSTANCE__) (COMP_EXTI_LINE_COMP1)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_IS_COMP_Private_Definitions COMP private macros to check input parameters
|
||||
* @{
|
||||
*/
|
||||
#define IS_COMP_POWERMODE(__POWERMODE__) (((__POWERMODE__) == COMP_POWERMODE_HIGHSPEED) || \
|
||||
((__POWERMODE__) == COMP_POWERMODE_MEDIUMSPEED) || \
|
||||
((__POWERMODE__) == COMP_POWERMODE_ULTRALOWPOWER) )
|
||||
|
||||
#define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) (((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) || \
|
||||
((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2) || \
|
||||
((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO3) || \
|
||||
((__INPUT_PLUS__) == COMP_INPUT_PLUS_DAC1_CH1))
|
||||
|
||||
#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO3) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_TEMPSENSOR) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_VBAT))
|
||||
|
||||
#define IS_COMP_HYSTERESIS(__HYSTERESIS__) (((__HYSTERESIS__) == COMP_HYSTERESIS_NONE) || \
|
||||
((__HYSTERESIS__) == COMP_HYSTERESIS_LOW) || \
|
||||
((__HYSTERESIS__) == COMP_HYSTERESIS_MEDIUM) || \
|
||||
((__HYSTERESIS__) == COMP_HYSTERESIS_HIGH))
|
||||
|
||||
#define IS_COMP_OUTPUTPOL(__POL__) (((__POL__) == COMP_OUTPUTPOL_NONINVERTED) || \
|
||||
((__POL__) == COMP_OUTPUTPOL_INVERTED))
|
||||
|
||||
#define IS_COMP_BLANKINGSRCE(__SOURCE__) (((__SOURCE__) == COMP_BLANKINGSRC_NONE) || \
|
||||
((__SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5) || \
|
||||
((__SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3) || \
|
||||
((__SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3) || \
|
||||
((__SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4) || \
|
||||
((__SOURCE__) == COMP_BLANKINGSRC_LPTIM1_OC2) || \
|
||||
((__SOURCE__) == COMP_BLANKINGSRC_LPTIM2_OC2))
|
||||
|
||||
|
||||
#define IS_COMP_TRIGGERMODE(__MODE__) (((__MODE__) == COMP_TRIGGERMODE_NONE) || \
|
||||
((__MODE__) == COMP_TRIGGERMODE_IT_RISING_FALLING))
|
||||
|
||||
#define IS_COMP_OUTPUT_LEVEL(__OUTPUT_LEVEL__) (((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_LOW) || \
|
||||
((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_HIGH))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions ------------------------------------------------------------------------------------------------*/
|
||||
/** @addtogroup COMP_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup COMP_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions */
|
||||
HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp);
|
||||
HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp);
|
||||
void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp);
|
||||
void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp);
|
||||
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1U)
|
||||
/* Callbacks Register/UnRegister functions */
|
||||
HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID,
|
||||
pCOMP_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* IO operation functions */
|
||||
/** @addtogroup COMP_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp);
|
||||
HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp);
|
||||
HAL_StatusTypeDef HAL_COMP_Start_IT_OneShot(COMP_HandleTypeDef *hcomp);
|
||||
HAL_StatusTypeDef HAL_COMP_Start_IT_AutoRearm(COMP_HandleTypeDef *hcomp);
|
||||
HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp);
|
||||
void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions */
|
||||
/** @addtogroup COMP_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp);
|
||||
uint32_t HAL_COMP_GetOutputLevel(const COMP_HandleTypeDef *hcomp);
|
||||
/* Callback in interrupt mode */
|
||||
void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral State functions */
|
||||
/** @addtogroup COMP_Exported_Functions_Group4
|
||||
* @{
|
||||
*/
|
||||
HAL_COMP_StateTypeDef HAL_COMP_GetState(const COMP_HandleTypeDef *hcomp);
|
||||
uint32_t HAL_COMP_GetError(const COMP_HandleTypeDef *hcomp);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* COMP1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H5xx_HAL_COMP_H */
|
||||
|
|
@ -0,0 +1,488 @@
|
|||
/**
|
||||
**********************************************************************************************************************
|
||||
* @file stm32h5xx_hal_conf_template.h
|
||||
* @author MCD Application Team
|
||||
* @brief HAL configuration template file.
|
||||
* This file should be copied to the application folder and renamed
|
||||
* to stm32h5xx_hal_conf.h.
|
||||
**********************************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
**********************************************************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/
|
||||
#ifndef STM32H5xx_HAL_CONF_H
|
||||
#define STM32H5xx_HAL_CONF_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Exported types ----------------------------------------------------------------------------------------------------*/
|
||||
/* Exported constants ------------------------------------------------------------------------------------------------*/
|
||||
|
||||
/* ########################################### Module Selection ##################################################### */
|
||||
/**
|
||||
* @brief This is the list of modules to be used in the HAL driver
|
||||
*/
|
||||
#define HAL_MODULE_ENABLED
|
||||
#define HAL_ADC_MODULE_ENABLED
|
||||
#define HAL_CEC_MODULE_ENABLED
|
||||
#define HAL_COMP_MODULE_ENABLED
|
||||
#define HAL_CORDIC_MODULE_ENABLED
|
||||
#define HAL_CORTEX_MODULE_ENABLED
|
||||
#define HAL_CRC_MODULE_ENABLED
|
||||
#define HAL_CRYP_MODULE_ENABLED
|
||||
#define HAL_DAC_MODULE_ENABLED
|
||||
#define HAL_DCACHE_MODULE_ENABLED
|
||||
#define HAL_DCMI_MODULE_ENABLED
|
||||
#define HAL_DMA_MODULE_ENABLED
|
||||
#define HAL_DTS_MODULE_ENABLED
|
||||
#define HAL_EXTI_MODULE_ENABLED
|
||||
#define HAL_ETH_MODULE_ENABLED
|
||||
#define HAL_FDCAN_MODULE_ENABLED
|
||||
#define HAL_FLASH_MODULE_ENABLED
|
||||
#define HAL_FMAC_MODULE_ENABLED
|
||||
#define HAL_GPIO_MODULE_ENABLED
|
||||
#define HAL_GTZC_MODULE_ENABLED
|
||||
#define HAL_HASH_MODULE_ENABLED
|
||||
#define HAL_HCD_MODULE_ENABLED
|
||||
#define HAL_I2C_MODULE_ENABLED
|
||||
#define HAL_I2S_MODULE_ENABLED
|
||||
#define HAL_I3C_MODULE_ENABLED
|
||||
#define HAL_ICACHE_MODULE_ENABLED
|
||||
#define HAL_IRDA_MODULE_ENABLED
|
||||
#define HAL_IWDG_MODULE_ENABLED
|
||||
#define HAL_LPTIM_MODULE_ENABLED
|
||||
#define HAL_MMC_MODULE_ENABLED
|
||||
#define HAL_NAND_MODULE_ENABLED
|
||||
#define HAL_NOR_MODULE_ENABLED
|
||||
#define HAL_OTFDEC_MODULE_ENABLED
|
||||
#define HAL_OPAMP_MODULE_ENABLED
|
||||
#define HAL_PCD_MODULE_ENABLED
|
||||
#define HAL_PKA_MODULE_ENABLED
|
||||
#define HAL_PSSI_MODULE_ENABLED
|
||||
#define HAL_PWR_MODULE_ENABLED
|
||||
#define HAL_RAMCFG_MODULE_ENABLED
|
||||
#define HAL_RCC_MODULE_ENABLED
|
||||
#define HAL_RNG_MODULE_ENABLED
|
||||
#define HAL_RTC_MODULE_ENABLED
|
||||
#define HAL_SAI_MODULE_ENABLED
|
||||
#define HAL_SD_MODULE_ENABLED
|
||||
#define HAL_SDRAM_MODULE_ENABLED
|
||||
#define HAL_SMARTCARD_MODULE_ENABLED
|
||||
#define HAL_SMBUS_MODULE_ENABLED
|
||||
#define HAL_SPI_MODULE_ENABLED
|
||||
#define HAL_SRAM_MODULE_ENABLED
|
||||
#define HAL_TIM_MODULE_ENABLED
|
||||
#define HAL_UART_MODULE_ENABLED
|
||||
#define HAL_USART_MODULE_ENABLED
|
||||
#define HAL_WWDG_MODULE_ENABLED
|
||||
#define HAL_XSPI_MODULE_ENABLED
|
||||
|
||||
/* ####################################### Oscillator Values adaptation ##############################################*/
|
||||
/**
|
||||
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSE is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
#if !defined (HSE_VALUE)
|
||||
#define HSE_VALUE 25000000UL /*!< Value of the External oscillator in Hz */
|
||||
#endif /* HSE_VALUE */
|
||||
|
||||
#if !defined (HSE_STARTUP_TIMEOUT)
|
||||
#define HSE_STARTUP_TIMEOUT 100UL /*!< Time out for HSE start up, in ms */
|
||||
#endif /* HSE_STARTUP_TIMEOUT */
|
||||
|
||||
/**
|
||||
* @brief Internal Core Speed oscillator (CSI) value.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when CSI is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
#if !defined (CSI_VALUE)
|
||||
#define CSI_VALUE 4000000UL /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* CSI_VALUE */
|
||||
|
||||
/**
|
||||
* @brief Internal High Speed oscillator (HSI) value.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSI is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
#if !defined (HSI_VALUE)
|
||||
#define HSI_VALUE 64000000UL /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* HSI_VALUE */
|
||||
|
||||
/**
|
||||
* @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG.
|
||||
* This internal oscillator is mainly dedicated to provide a high precision clock to
|
||||
* the USB peripheral by means of a special Clock Recovery System (CRS) circuitry.
|
||||
* When the CRS is not used, the HSI48 RC oscillator runs on it default frequency
|
||||
* which is subject to manufacturing process variations.
|
||||
*/
|
||||
#if !defined (HSI48_VALUE)
|
||||
#define HSI48_VALUE 48000000UL /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz.
|
||||
The real value my vary depending on manufacturing process variations.*/
|
||||
#endif /* HSI48_VALUE */
|
||||
|
||||
/**
|
||||
* @brief Internal Low Speed oscillator (LSI) value.
|
||||
*/
|
||||
#if !defined (LSI_VALUE)
|
||||
#define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz*/
|
||||
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
|
||||
The real value may vary depending on the variations
|
||||
in voltage and temperature.*/
|
||||
|
||||
#if !defined (LSI_STARTUP_TIME)
|
||||
#define LSI_STARTUP_TIME 130UL /*!< Time out for LSI start up, in ms */
|
||||
#endif /* LSI_STARTUP_TIME */
|
||||
|
||||
/**
|
||||
* @brief External Low Speed oscillator (LSE) value.
|
||||
* This value is used by the UART, RTC HAL module to compute the system frequency
|
||||
*/
|
||||
#if !defined (LSE_VALUE)
|
||||
#define LSE_VALUE 32768UL /*!< Value of the External oscillator in Hz*/
|
||||
#endif /* LSE_VALUE */
|
||||
|
||||
#if !defined (LSE_STARTUP_TIMEOUT)
|
||||
#define LSE_STARTUP_TIMEOUT 5000UL /*!< Time out for LSE start up, in ms */
|
||||
#endif /* LSE_STARTUP_TIMEOUT */
|
||||
|
||||
|
||||
/**
|
||||
* @brief External clock source for SPI/SAI peripheral
|
||||
* This value is used by the SPI/SAI HAL module to compute the SPI/SAI clock source
|
||||
* frequency, this source is inserted directly through I2S_CKIN pad.
|
||||
*/
|
||||
#if !defined (EXTERNAL_CLOCK_VALUE)
|
||||
#define EXTERNAL_CLOCK_VALUE 12288000UL /*!< Value of the External clock in Hz*/
|
||||
#endif /* EXTERNAL_CLOCK_VALUE */
|
||||
|
||||
/* Tip: To avoid modifying this file each time you need to use different HSE,
|
||||
=== you can define the HSE value in your toolchain compiler preprocessor. */
|
||||
|
||||
/* ############################################ System Configuration ################################################ */
|
||||
/**
|
||||
* @brief This is the HAL system configuration section
|
||||
*/
|
||||
#define VDD_VALUE 3300UL /*!< Value of VDD in mv */
|
||||
#define TICK_INT_PRIORITY ((1UL<<__NVIC_PRIO_BITS) - 1UL) /*!< tick interrupt priority (lowest by default) */
|
||||
#define USE_RTOS 0U
|
||||
#define PREFETCH_ENABLE 0U /*!< Enable prefetch */
|
||||
|
||||
/* ############################################ Assert Selection #################################################### */
|
||||
/**
|
||||
* @brief Uncomment the line below to expanse the "assert_param" macro in the
|
||||
* HAL drivers code
|
||||
*/
|
||||
/* #define USE_FULL_ASSERT 1U */
|
||||
|
||||
/* ############################################ Register callback feature configuration ############################# */
|
||||
/**
|
||||
* @brief Set below the peripheral configuration to "1U" to add the support
|
||||
* of HAL callback registration/unregistration feature for the HAL
|
||||
* driver(s). This allows user application to provide specific callback
|
||||
* functions thanks to HAL_PPP_RegisterCallback() rather than overwriting
|
||||
* the default weak callback functions (see each stm32h5xx_hal_ppp.h file
|
||||
* for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef
|
||||
* for each PPP peripheral).
|
||||
*/
|
||||
#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
|
||||
#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */
|
||||
#define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */
|
||||
#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U /* CORDIC register callback disabled */
|
||||
#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */
|
||||
#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */
|
||||
#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */
|
||||
#define USE_HAL_DTS_REGISTER_CALLBACKS 0U /* DTS register callback disabled */
|
||||
#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */
|
||||
#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U /* FDCAN register callback disabled */
|
||||
#define USE_HAL_FMAC_REGISTER_CALLBACKS 0U /* FMAC register callback disabled */
|
||||
#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */
|
||||
#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */
|
||||
#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */
|
||||
#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */
|
||||
#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */
|
||||
#define USE_HAL_I3C_REGISTER_CALLBACKS 0U /* I3C register callback disabled */
|
||||
#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */
|
||||
#define USE_HAL_IWDG_REGISTER_CALLBACKS 0U /* IWDG register callback disabled */
|
||||
#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */
|
||||
#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */
|
||||
#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */
|
||||
#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U /* OTFDEC register callback disabled */
|
||||
#define USE_HAL_OTFDEC_REGISTER_CALLBACKS 0U /* OPAMP register callback disabled */
|
||||
#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */
|
||||
#define USE_HAL_PKA_REGISTER_CALLBACKS 0U /* PKA register callback disabled */
|
||||
#define USE_HAL_RAMCFG_REGISTER_CALLBACKS 0U /* RAMCFG register callback disabled */
|
||||
#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */
|
||||
#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */
|
||||
#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */
|
||||
#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */
|
||||
#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */
|
||||
#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */
|
||||
#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */
|
||||
#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */
|
||||
#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */
|
||||
#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */
|
||||
#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */
|
||||
#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */
|
||||
#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */
|
||||
#define USE_HAL_XSPI_REGISTER_CALLBACKS 0U /* XSPI register callback disabled */
|
||||
|
||||
/* ############################################ SPI peripheral configuration ######################################## */
|
||||
|
||||
/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
|
||||
* Activated: CRC code is present inside driver
|
||||
* Deactivated: CRC code cleaned from driver
|
||||
*/
|
||||
#define USE_SPI_CRC 1U
|
||||
|
||||
|
||||
/* Includes ----------------------------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Include module's header file
|
||||
*/
|
||||
|
||||
#ifdef HAL_RCC_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_rcc.h"
|
||||
#endif /* HAL_RCC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_GPIO_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_gpio.h"
|
||||
#endif /* HAL_GPIO_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_ICACHE_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_icache.h"
|
||||
#endif /* HAL_ICACHE_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DCACHE_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_dcache.h"
|
||||
#endif /* HAL_DCACHE_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_GTZC_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_gtzc.h"
|
||||
#endif /* HAL_GTZC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DMA_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_dma.h"
|
||||
#endif /* HAL_DMA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DTS_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_dts.h"
|
||||
#endif /* HAL_DTS_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CORTEX_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_cortex.h"
|
||||
#endif /* HAL_CORTEX_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PKA_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_pka.h"
|
||||
#endif /* HAL_PKA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_ADC_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_adc.h"
|
||||
#endif /* HAL_ADC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CRC_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_crc.h"
|
||||
#endif /* HAL_CRC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CRYP_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_cryp.h"
|
||||
#endif /* HAL_CRYP_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DAC_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_dac.h"
|
||||
#endif /* HAL_DAC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_FLASH_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_flash.h"
|
||||
#endif /* HAL_FLASH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_HASH_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_hash.h"
|
||||
#endif /* HAL_HASH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SRAM_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_sram.h"
|
||||
#endif /* HAL_SRAM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SDRAM_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_sdram.h"
|
||||
#endif /* HAL_SDRAM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_MMC_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_mmc.h"
|
||||
#endif /* HAL_MMC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_NOR_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_nor.h"
|
||||
#endif /* HAL_NOR_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_NAND_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_nand.h"
|
||||
#endif /* HAL_NAND_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I2C_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_i2c.h"
|
||||
#endif /* HAL_I2C_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I2S_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_i2s.h"
|
||||
#endif /* HAL_I2S_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I3C_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_i3c.h"
|
||||
#endif /* HAL_I3C_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IWDG_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_iwdg.h"
|
||||
#endif /* HAL_IWDG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_LPTIM_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_lptim.h"
|
||||
#endif /* HAL_LPTIM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PWR_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_pwr.h"
|
||||
#endif /* HAL_PWR_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_XSPI_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_xspi.h"
|
||||
#endif /* HAL_XSPI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RNG_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_rng.h"
|
||||
#endif /* HAL_RNG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RTC_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_rtc.h"
|
||||
#endif /* HAL_RTC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SAI_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_sai.h"
|
||||
#endif /* HAL_SAI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SD_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_sd.h"
|
||||
#endif /* HAL_SD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SMBUS_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_smbus.h"
|
||||
#endif /* HAL_SMBUS_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SPI_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_spi.h"
|
||||
#endif /* HAL_SPI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_TIM_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_tim.h"
|
||||
#endif /* HAL_TIM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_UART_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_uart.h"
|
||||
#endif /* HAL_UART_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_USART_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_usart.h"
|
||||
#endif /* HAL_USART_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IRDA_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_irda.h"
|
||||
#endif /* HAL_IRDA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SMARTCARD_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_smartcard.h"
|
||||
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_WWDG_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_wwdg.h"
|
||||
#endif /* HAL_WWDG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PCD_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_pcd.h"
|
||||
#endif /* HAL_PCD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_HCD_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_hcd.h"
|
||||
#endif /* HAL_HCD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_COMP_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_comp.h"
|
||||
#endif /* HAL_COMP_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CORDIC_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_cordic.h"
|
||||
#endif /* HAL_CORDIC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DCMI_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_dcmi.h"
|
||||
#endif /* HAL_DCMI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_EXTI_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_exti.h"
|
||||
#endif /* HAL_EXTI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_ETH_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_eth.h"
|
||||
#endif /* HAL_ETH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_FDCAN_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_fdcan.h"
|
||||
#endif /* HAL_FDCAN_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CEC_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_cec.h"
|
||||
#endif /* HAL_CEC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_FMAC_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_fmac.h"
|
||||
#endif /* HAL_FMAC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_OPAMP_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_opamp.h"
|
||||
#endif /* HAL_OPAMP_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_OTFDEC_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_otfdec.h"
|
||||
#endif /* HAL_OTFDEC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PSSI_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_pssi.h"
|
||||
#endif /* HAL_PSSI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RAMCFG_MODULE_ENABLED
|
||||
#include "stm32h5xx_hal_ramcfg.h"
|
||||
#endif /* HAL_RAMCFG_MODULE_ENABLED */
|
||||
|
||||
/* Exported macro ----------------------------------------------------------------------------------------------------*/
|
||||
#ifdef USE_FULL_ASSERT
|
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check.
|
||||
* @param expr: If expr is false, it calls assert_failed function
|
||||
* which reports the name of the source file and the source
|
||||
* line number of the call that failed.
|
||||
* If expr is true, it returns no value.
|
||||
* @retval None
|
||||
*/
|
||||
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||
/* Exported functions ----------------------------------------------------------------------------------------------- */
|
||||
void assert_failed(uint8_t *file, uint32_t line);
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H5xx_HAL_CONF_H */
|
||||
|
|
@ -0,0 +1,609 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h5xx_hal_cordic.h
|
||||
* @author MCD Application Team
|
||||
* @brief This file contains all the functions prototypes for the CORDIC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H5xx_HAL_CORDIC_H
|
||||
#define STM32H5xx_HAL_CORDIC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h5xx_hal_def.h"
|
||||
|
||||
#if defined(CORDIC)
|
||||
/** @addtogroup STM32H5xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CORDIC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup CORDIC_Exported_Types CORDIC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief CORDIC HAL State Structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CORDIC_STATE_RESET = 0x00U, /*!< CORDIC not yet initialized or disabled */
|
||||
HAL_CORDIC_STATE_READY = 0x01U, /*!< CORDIC initialized and ready for use */
|
||||
HAL_CORDIC_STATE_BUSY = 0x02U, /*!< CORDIC internal process is ongoing */
|
||||
HAL_CORDIC_STATE_ERROR = 0x03U /*!< CORDIC error state */
|
||||
} HAL_CORDIC_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CORDIC Handle Structure definition
|
||||
*/
|
||||
#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
|
||||
typedef struct __CORDIC_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
|
||||
{
|
||||
CORDIC_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
const int32_t *pInBuff; /*!< Pointer to CORDIC input data buffer */
|
||||
|
||||
int32_t *pOutBuff; /*!< Pointer to CORDIC output data buffer */
|
||||
|
||||
uint32_t NbCalcToOrder; /*!< Remaining number of calculation to order */
|
||||
|
||||
uint32_t NbCalcToGet; /*!< Remaining number of calculation result to get */
|
||||
|
||||
uint32_t DMADirection; /*!< Direction of CORDIC DMA transfers */
|
||||
|
||||
DMA_HandleTypeDef *hdmaIn; /*!< CORDIC peripheral input data DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmaOut; /*!< CORDIC peripheral output data DMA handle parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< CORDIC locking object */
|
||||
|
||||
__IO HAL_CORDIC_StateTypeDef State; /*!< CORDIC state */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< CORDIC peripheral error code
|
||||
This parameter can be a value of @ref CORDIC_Error_Code */
|
||||
|
||||
#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
|
||||
void (* ErrorCallback)(struct __CORDIC_HandleTypeDef *hcordic); /*!< CORDIC error callback */
|
||||
void (* CalculateCpltCallback)(struct __CORDIC_HandleTypeDef *hcordic); /*!< CORDIC calculate complete callback */
|
||||
|
||||
void (* MspInitCallback)(struct __CORDIC_HandleTypeDef *hcordic); /*!< CORDIC Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __CORDIC_HandleTypeDef *hcordic); /*!< CORDIC Msp DeInit callback */
|
||||
|
||||
#endif /* (USE_HAL_CORDIC_REGISTER_CALLBACKS) */
|
||||
|
||||
} CORDIC_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CORDIC Config Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Function; /*!< Function
|
||||
This parameter can be a value of @ref CORDIC_Function */
|
||||
|
||||
uint32_t Scale; /*!< Scaling factor
|
||||
This parameter can be a value of @ref CORDIC_Scale */
|
||||
|
||||
uint32_t InSize; /*!< Width of input data
|
||||
This parameter can be a value of @ref CORDIC_In_Size */
|
||||
|
||||
uint32_t OutSize; /*!< Width of output data
|
||||
This parameter can be a value of @ref CORDIC_Out_Size */
|
||||
|
||||
uint32_t NbWrite; /*!< Number of 32-bit write expected for one calculation
|
||||
This parameter can be a value of @ref CORDIC_Nb_Write */
|
||||
|
||||
uint32_t NbRead; /*!< Number of 32-bit read expected after one calculation
|
||||
This parameter can be a value of @ref CORDIC_Nb_Read */
|
||||
|
||||
uint32_t Precision; /*!< Number of cycles for calculation
|
||||
This parameter can be a value of @ref CORDIC_Precision_In_Cycles_Number */
|
||||
|
||||
} CORDIC_ConfigTypeDef;
|
||||
|
||||
#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
|
||||
/**
|
||||
* @brief HAL CORDIC Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CORDIC_ERROR_CB_ID = 0x00U, /*!< CORDIC error callback ID */
|
||||
HAL_CORDIC_CALCULATE_CPLT_CB_ID = 0x01U, /*!< CORDIC calculate complete callback ID */
|
||||
|
||||
HAL_CORDIC_MSPINIT_CB_ID = 0x02U, /*!< CORDIC MspInit callback ID */
|
||||
HAL_CORDIC_MSPDEINIT_CB_ID = 0x03U, /*!< CORDIC MspDeInit callback ID */
|
||||
|
||||
} HAL_CORDIC_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL CORDIC Callback pointer definition
|
||||
*/
|
||||
typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< pointer to a CORDIC callback function */
|
||||
|
||||
#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CORDIC_Exported_Constants CORDIC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CORDIC_Error_Code CORDIC Error code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_CORDIC_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
|
||||
#define HAL_CORDIC_ERROR_PARAM ((uint32_t)0x00000001U) /*!< Wrong parameter error */
|
||||
#define HAL_CORDIC_ERROR_NOT_READY ((uint32_t)0x00000002U) /*!< Peripheral not ready */
|
||||
#define HAL_CORDIC_ERROR_TIMEOUT ((uint32_t)0x00000004U) /*!< Timeout error */
|
||||
#define HAL_CORDIC_ERROR_DMA ((uint32_t)0x00000008U) /*!< DMA error */
|
||||
#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
|
||||
#define HAL_CORDIC_ERROR_INVALID_CALLBACK ((uint32_t)0x00000010U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORDIC_Function CORDIC Function
|
||||
* @{
|
||||
*/
|
||||
#define CORDIC_FUNCTION_COSINE (0x00000000U) /*!< Cosine */
|
||||
#define CORDIC_FUNCTION_SINE ((uint32_t)(CORDIC_CSR_FUNC_0)) /*!< Sine */
|
||||
#define CORDIC_FUNCTION_PHASE ((uint32_t)(CORDIC_CSR_FUNC_1)) /*!< Phase */
|
||||
#define CORDIC_FUNCTION_MODULUS ((uint32_t)(CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0)) /*!< Modulus */
|
||||
#define CORDIC_FUNCTION_ARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2)) /*!< Arctangent */
|
||||
#define CORDIC_FUNCTION_HCOSINE ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_0)) /*!< Hyperbolic Cosine */
|
||||
#define CORDIC_FUNCTION_HSINE ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1)) /*!< Hyperbolic Sine */
|
||||
#define CORDIC_FUNCTION_HARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0))/*!< Hyperbolic Arctangent */
|
||||
#define CORDIC_FUNCTION_NATURALLOG ((uint32_t)(CORDIC_CSR_FUNC_3)) /*!< Natural Logarithm */
|
||||
#define CORDIC_FUNCTION_SQUAREROOT ((uint32_t)(CORDIC_CSR_FUNC_3 | CORDIC_CSR_FUNC_0)) /*!< Square Root */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORDIC_Precision_In_Cycles_Number CORDIC Precision in Cycles Number
|
||||
* @{
|
||||
*/
|
||||
/* Note: 1 cycle corresponds to 4 algorithm iterations */
|
||||
#define CORDIC_PRECISION_1CYCLE ((uint32_t)(CORDIC_CSR_PRECISION_0))
|
||||
#define CORDIC_PRECISION_2CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_1))
|
||||
#define CORDIC_PRECISION_3CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
|
||||
#define CORDIC_PRECISION_4CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2))
|
||||
#define CORDIC_PRECISION_5CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0))
|
||||
#define CORDIC_PRECISION_6CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1))
|
||||
#define CORDIC_PRECISION_7CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2\
|
||||
| CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
|
||||
#define CORDIC_PRECISION_8CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3))
|
||||
#define CORDIC_PRECISION_9CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_0))
|
||||
#define CORDIC_PRECISION_10CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_1))
|
||||
#define CORDIC_PRECISION_11CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
|
||||
| CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
|
||||
#define CORDIC_PRECISION_12CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2))
|
||||
#define CORDIC_PRECISION_13CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
|
||||
| CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0))
|
||||
#define CORDIC_PRECISION_14CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
|
||||
| CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1))
|
||||
#define CORDIC_PRECISION_15CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
|
||||
| CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1\
|
||||
|CORDIC_CSR_PRECISION_0))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORDIC_Scale CORDIC Scaling factor
|
||||
* @{
|
||||
*/
|
||||
/* Scale factor value 'n' implies that the input data have been multiplied
|
||||
by a factor 2exp(-n), and/or the output data need to be multiplied by 2exp(n). */
|
||||
#define CORDIC_SCALE_0 (0x00000000U)
|
||||
#define CORDIC_SCALE_1 ((uint32_t)(CORDIC_CSR_SCALE_0))
|
||||
#define CORDIC_SCALE_2 ((uint32_t)(CORDIC_CSR_SCALE_1))
|
||||
#define CORDIC_SCALE_3 ((uint32_t)(CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0))
|
||||
#define CORDIC_SCALE_4 ((uint32_t)(CORDIC_CSR_SCALE_2))
|
||||
#define CORDIC_SCALE_5 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_0))
|
||||
#define CORDIC_SCALE_6 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1))
|
||||
#define CORDIC_SCALE_7 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORDIC_Interrupts_Enable CORDIC Interrupts Enable bit
|
||||
* @{
|
||||
*/
|
||||
#define CORDIC_IT_IEN CORDIC_CSR_IEN /*!< Result ready interrupt enable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORDIC_DMAR DMA Read Request Enable bit
|
||||
* @{
|
||||
*/
|
||||
#define CORDIC_DMA_REN CORDIC_CSR_DMAREN /*!< DMA Read requests enable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORDIC_DMAW DMA Write Request Enable bit
|
||||
* @{
|
||||
*/
|
||||
#define CORDIC_DMA_WEN CORDIC_CSR_DMAWEN /*!< DMA Write channel enable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORDIC_Nb_Write CORDIC Number of 32-bit write required for one calculation
|
||||
* @{
|
||||
*/
|
||||
#define CORDIC_NBWRITE_1 (0x00000000U) /*!< One 32-bits write containing either only one
|
||||
32-bit data input (Q1.31 format), or two 16-bit
|
||||
data input (Q1.15 format) packed in one 32 bits
|
||||
Data */
|
||||
#define CORDIC_NBWRITE_2 CORDIC_CSR_NARGS /*!< Two 32-bit write containing two 32-bits data input
|
||||
(Q1.31 format) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORDIC_Nb_Read CORDIC Number of 32-bit read required after one calculation
|
||||
* @{
|
||||
*/
|
||||
#define CORDIC_NBREAD_1 (0x00000000U) /*!< One 32-bits read containing either only one
|
||||
32-bit data output (Q1.31 format), or two 16-bit
|
||||
data output (Q1.15 format) packed in one 32 bits
|
||||
Data */
|
||||
#define CORDIC_NBREAD_2 CORDIC_CSR_NRES /*!< Two 32-bit Data containing two 32-bits data output
|
||||
(Q1.31 format) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORDIC_In_Size CORDIC input data size
|
||||
* @{
|
||||
*/
|
||||
#define CORDIC_INSIZE_32BITS (0x00000000U) /*!< 32 bits input data size (Q1.31 format) */
|
||||
#define CORDIC_INSIZE_16BITS CORDIC_CSR_ARGSIZE /*!< 16 bits input data size (Q1.15 format) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORDIC_Out_Size CORDIC Results Size
|
||||
* @{
|
||||
*/
|
||||
#define CORDIC_OUTSIZE_32BITS (0x00000000U) /*!< 32 bits output data size (Q1.31 format) */
|
||||
#define CORDIC_OUTSIZE_16BITS CORDIC_CSR_RESSIZE /*!< 16 bits output data size (Q1.15 format) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORDIC_Flags CORDIC status flags
|
||||
* @{
|
||||
*/
|
||||
#define CORDIC_FLAG_RRDY CORDIC_CSR_RRDY /*!< Result Ready Flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORDIC_DMA_Direction CORDIC DMA direction
|
||||
* @{
|
||||
*/
|
||||
#define CORDIC_DMA_DIR_NONE ((uint32_t)0x00000000U) /*!< DMA direction : none */
|
||||
#define CORDIC_DMA_DIR_IN ((uint32_t)0x00000001U) /*!< DMA direction : Input of CORDIC */
|
||||
#define CORDIC_DMA_DIR_OUT ((uint32_t)0x00000002U) /*!< DMA direction : Output of CORDIC */
|
||||
#define CORDIC_DMA_DIR_IN_OUT ((uint32_t)0x00000003U) /*!< DMA direction : Input and Output of CORDIC */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup CORDIC_Exported_Macros CORDIC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset CORDIC handle state.
|
||||
* @param __HANDLE__ CORDIC handle
|
||||
* @retval None
|
||||
*/
|
||||
#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
|
||||
#define __HAL_CORDIC_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_CORDIC_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_CORDIC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CORDIC_STATE_RESET)
|
||||
#endif /*USE_HAL_CORDIC_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @brief Enable the CORDIC interrupt when result is ready
|
||||
* @param __HANDLE__ CORDIC handle.
|
||||
* @param __INTERRUPT__ CORDIC Interrupt.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref CORDIC_IT_IEN Enable Interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CORDIC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
|
||||
(((__HANDLE__)->Instance->CSR) |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the CORDIC interrupt
|
||||
* @param __HANDLE__ CORDIC handle.
|
||||
* @param __INTERRUPT__ CORDIC Interrupt.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref CORDIC_IT_IEN Enable Interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CORDIC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
|
||||
(((__HANDLE__)->Instance->CSR) &= ~(__INTERRUPT__))
|
||||
|
||||
/** @brief Check whether the specified CORDIC interrupt occurred or not.
|
||||
Dummy macro as no interrupt status flag.
|
||||
* @param __HANDLE__ CORDIC handle.
|
||||
* @param __INTERRUPT__ CORDIC interrupt to check
|
||||
* @retval SET (interrupt occurred) or RESET (interrupt did not occurred)
|
||||
*/
|
||||
#define __HAL_CORDIC_GET_IT(__HANDLE__, __INTERRUPT__) /* Dummy macro */
|
||||
|
||||
/** @brief Clear specified CORDIC interrupt status. Dummy macro as no
|
||||
interrupt status flag.
|
||||
* @param __HANDLE__ CORDIC handle.
|
||||
* @param __INTERRUPT__ CORDIC interrupt to clear
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CORDIC_CLEAR_IT(__HANDLE__, __INTERRUPT__) /* Dummy macro */
|
||||
|
||||
/** @brief Check whether the specified CORDIC status flag is set or not.
|
||||
* @param __HANDLE__ CORDIC handle.
|
||||
* @param __FLAG__ CORDIC flag to check
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref CORDIC_FLAG_RRDY Result Ready Flag
|
||||
* @retval SET (flag is set) or RESET (flag is reset)
|
||||
*/
|
||||
#define __HAL_CORDIC_GET_FLAG(__HANDLE__, __FLAG__) \
|
||||
((((__HANDLE__)->Instance->CSR) & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clear specified CORDIC status flag. Dummy macro as no
|
||||
flag can be cleared.
|
||||
* @param __HANDLE__ CORDIC handle.
|
||||
* @param __FLAG__ CORDIC flag to clear
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref CORDIC_FLAG_RRDY Result Ready Flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CORDIC_CLEAR_FLAG(__HANDLE__, __FLAG__) /* Dummy macro */
|
||||
|
||||
/** @brief Check whether the specified CORDIC interrupt is enabled or not.
|
||||
* @param __HANDLE__ CORDIC handle.
|
||||
* @param __INTERRUPT__ CORDIC interrupt to check
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref CORDIC_IT_IEN Enable Interrupt
|
||||
* @retval FlagStatus
|
||||
*/
|
||||
#define __HAL_CORDIC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
|
||||
(((__HANDLE__)->Instance->CSR) & (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros --------------------------------------------------------*/
|
||||
/** @defgroup CORDIC_Private_Macros CORDIC Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Verify the CORDIC function.
|
||||
* @param __FUNCTION__ Name of the function.
|
||||
* @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
|
||||
*/
|
||||
#define IS_CORDIC_FUNCTION(__FUNCTION__) (((__FUNCTION__) == CORDIC_FUNCTION_COSINE) || \
|
||||
((__FUNCTION__) == CORDIC_FUNCTION_SINE) || \
|
||||
((__FUNCTION__) == CORDIC_FUNCTION_PHASE) || \
|
||||
((__FUNCTION__) == CORDIC_FUNCTION_MODULUS) || \
|
||||
((__FUNCTION__) == CORDIC_FUNCTION_ARCTANGENT) || \
|
||||
((__FUNCTION__) == CORDIC_FUNCTION_HCOSINE) || \
|
||||
((__FUNCTION__) == CORDIC_FUNCTION_HSINE) || \
|
||||
((__FUNCTION__) == CORDIC_FUNCTION_HARCTANGENT) || \
|
||||
((__FUNCTION__) == CORDIC_FUNCTION_NATURALLOG) || \
|
||||
((__FUNCTION__) == CORDIC_FUNCTION_SQUAREROOT))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Verify the CORDIC precision.
|
||||
* @param __PRECISION__ CORDIC Precision in Cycles Number.
|
||||
* @retval SET (__PRECISION__ is a valid value) or RESET (__PRECISION__ is invalid)
|
||||
*/
|
||||
#define IS_CORDIC_PRECISION(__PRECISION__) (((__PRECISION__) == CORDIC_PRECISION_1CYCLE) || \
|
||||
((__PRECISION__) == CORDIC_PRECISION_2CYCLES) || \
|
||||
((__PRECISION__) == CORDIC_PRECISION_3CYCLES) || \
|
||||
((__PRECISION__) == CORDIC_PRECISION_4CYCLES) || \
|
||||
((__PRECISION__) == CORDIC_PRECISION_5CYCLES) || \
|
||||
((__PRECISION__) == CORDIC_PRECISION_6CYCLES) || \
|
||||
((__PRECISION__) == CORDIC_PRECISION_7CYCLES) || \
|
||||
((__PRECISION__) == CORDIC_PRECISION_8CYCLES) || \
|
||||
((__PRECISION__) == CORDIC_PRECISION_9CYCLES) || \
|
||||
((__PRECISION__) == CORDIC_PRECISION_10CYCLES) || \
|
||||
((__PRECISION__) == CORDIC_PRECISION_11CYCLES) || \
|
||||
((__PRECISION__) == CORDIC_PRECISION_12CYCLES) || \
|
||||
((__PRECISION__) == CORDIC_PRECISION_13CYCLES) || \
|
||||
((__PRECISION__) == CORDIC_PRECISION_14CYCLES) || \
|
||||
((__PRECISION__) == CORDIC_PRECISION_15CYCLES))
|
||||
|
||||
/**
|
||||
* @brief Verify the CORDIC scaling factor.
|
||||
* @param __SCALE__ Number of cycles for calculation, 1 cycle corresponding to 4 algorithm iterations.
|
||||
* @retval SET (__SCALE__ is a valid value) or RESET (__SCALE__ is invalid)
|
||||
*/
|
||||
#define IS_CORDIC_SCALE(__SCALE__) (((__SCALE__) == CORDIC_SCALE_0) || \
|
||||
((__SCALE__) == CORDIC_SCALE_1) || \
|
||||
((__SCALE__) == CORDIC_SCALE_2) || \
|
||||
((__SCALE__) == CORDIC_SCALE_3) || \
|
||||
((__SCALE__) == CORDIC_SCALE_4) || \
|
||||
((__SCALE__) == CORDIC_SCALE_5) || \
|
||||
((__SCALE__) == CORDIC_SCALE_6) || \
|
||||
((__SCALE__) == CORDIC_SCALE_7))
|
||||
|
||||
/**
|
||||
* @brief Verify the CORDIC number of 32-bits write expected for one calculation.
|
||||
* @param __NBWRITE__ Number of 32-bits write expected for one calculation.
|
||||
* @retval SET (__NBWRITE__ is a valid value) or RESET (__NBWRITE__ is invalid)
|
||||
*/
|
||||
#define IS_CORDIC_NBWRITE(__NBWRITE__) (((__NBWRITE__) == CORDIC_NBWRITE_1) || \
|
||||
((__NBWRITE__) == CORDIC_NBWRITE_2))
|
||||
|
||||
/**
|
||||
* @brief Verify the CORDIC number of 32-bits read expected after one calculation.
|
||||
* @param __NBREAD__ Number of 32-bits read expected after one calculation.
|
||||
* @retval SET (__NBREAD__ is a valid value) or RESET (__NBREAD__ is invalid)
|
||||
*/
|
||||
#define IS_CORDIC_NBREAD(__NBREAD__) (((__NBREAD__) == CORDIC_NBREAD_1) || \
|
||||
((__NBREAD__) == CORDIC_NBREAD_2))
|
||||
|
||||
/**
|
||||
* @brief Verify the CORDIC input data size for one calculation.
|
||||
* @param __INSIZE__ input data size for one calculation.
|
||||
* @retval SET (__INSIZE__ is a valid value) or RESET (__INSIZE__ is invalid)
|
||||
*/
|
||||
#define IS_CORDIC_INSIZE(__INSIZE__) (((__INSIZE__) == CORDIC_INSIZE_32BITS) || \
|
||||
((__INSIZE__) == CORDIC_INSIZE_16BITS))
|
||||
|
||||
/**
|
||||
* @brief Verify the CORDIC output data size for one calculation.
|
||||
* @param __OUTSIZE__ output data size for one calculation.
|
||||
* @retval SET (__OUTSIZE__ is a valid value) or RESET (__OUTSIZE__ is invalid)
|
||||
*/
|
||||
#define IS_CORDIC_OUTSIZE(__OUTSIZE__) (((__OUTSIZE__) == CORDIC_OUTSIZE_32BITS) || \
|
||||
((__OUTSIZE__) == CORDIC_OUTSIZE_16BITS))
|
||||
|
||||
/**
|
||||
* @brief Verify the CORDIC DMA transfer Direction.
|
||||
* @param __DMADIR__ DMA transfer direction.
|
||||
* @retval SET (__DMADIR__ is a valid value) or RESET (__DMADIR__ is invalid)
|
||||
*/
|
||||
#define IS_CORDIC_DMA_DIRECTION(__DMADIR__) (((__DMADIR__) == CORDIC_DMA_DIR_IN) || \
|
||||
((__DMADIR__) == CORDIC_DMA_DIR_OUT) || \
|
||||
((__DMADIR__) == CORDIC_DMA_DIR_IN_OUT))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CORDIC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/** @addtogroup CORDIC_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions ******************************/
|
||||
HAL_StatusTypeDef HAL_CORDIC_Init(CORDIC_HandleTypeDef *hcordic);
|
||||
HAL_StatusTypeDef HAL_CORDIC_DeInit(CORDIC_HandleTypeDef *hcordic);
|
||||
void HAL_CORDIC_MspInit(CORDIC_HandleTypeDef *hcordic);
|
||||
void HAL_CORDIC_MspDeInit(CORDIC_HandleTypeDef *hcordic);
|
||||
|
||||
#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
HAL_StatusTypeDef HAL_CORDIC_RegisterCallback(CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID,
|
||||
pCORDIC_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_CORDIC_UnRegisterCallback(CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CORDIC_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_CORDIC_Configure(CORDIC_HandleTypeDef *hcordic, const CORDIC_ConfigTypeDef *sConfig);
|
||||
HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff,
|
||||
uint32_t NbCalc, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff,
|
||||
uint32_t NbCalc, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff,
|
||||
uint32_t NbCalc);
|
||||
HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff,
|
||||
uint32_t NbCalc, uint32_t DMADirection);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CORDIC_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Callback functions *********************************************************/
|
||||
void HAL_CORDIC_ErrorCallback(CORDIC_HandleTypeDef *hcordic);
|
||||
void HAL_CORDIC_CalculateCpltCallback(CORDIC_HandleTypeDef *hcordic);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CORDIC_Exported_Functions_Group4
|
||||
* @{
|
||||
*/
|
||||
/* IRQ handler management *****************************************************/
|
||||
void HAL_CORDIC_IRQHandler(CORDIC_HandleTypeDef *hcordic);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CORDIC_Exported_Functions_Group5
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions *************************************************/
|
||||
HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(const CORDIC_HandleTypeDef *hcordic);
|
||||
uint32_t HAL_CORDIC_GetError(const CORDIC_HandleTypeDef *hcordic);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* CORDIC */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H5xx_HAL_CORDIC_H */
|
||||
|
|
@ -0,0 +1,411 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h5xx_hal_cortex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CORTEX HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32H5xx_HAL_CORTEX_H
|
||||
#define __STM32H5xx_HAL_CORTEX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h5xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H5xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX CORTEX
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup CORTEX_Exported_Types CORTEX Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t Enable; /*!< Specifies the status of the region.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
|
||||
uint8_t Number; /*!< Specifies the index of the region to protect.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Number */
|
||||
uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
|
||||
uint32_t LimitAddress; /*!< Specifies the limit address of the region to protect. */
|
||||
uint8_t AttributesIndex; /*!< Specifies the memory attributes index.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Attributes_Number */
|
||||
uint8_t AccessPermission; /*!< Specifies the region access permission type. This parameter
|
||||
can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
|
||||
uint8_t DisableExec; /*!< Specifies the instruction access status.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
|
||||
uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
|
||||
} MPU_Region_InitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Attributes_Initialization_Structure_definition MPU Attributes
|
||||
* Initialization Structure Definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t Number; /*!< Specifies the number of the memory attributes to configure.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Attributes_Number */
|
||||
|
||||
uint8_t Attributes; /*!< Specifies the memory attributes value. Attributes This parameter
|
||||
can be a combination of @ref CORTEX_MPU_Attributes */
|
||||
|
||||
} MPU_Attributes_InitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
|
||||
* @{
|
||||
*/
|
||||
#define NVIC_PRIORITYGROUP_0 0x7U /*!< 0 bit for pre-emption priority,
|
||||
4 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_1 0x6U /*!< 1 bit for pre-emption priority,
|
||||
3 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_2 0x5U /*!< 2 bits for pre-emption priority,
|
||||
2 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_3 0x4U /*!< 3 bits for pre-emption priority,
|
||||
1 bit for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_4 0x3U /*!< 4 bits for pre-emption priority,
|
||||
0 bit for subpriority */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
|
||||
* @{
|
||||
*/
|
||||
#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x0U /*!< AHB clock divided by 8 selected as SysTick clock source */
|
||||
#define SYSTICK_CLKSOURCE_LSI 0x1U /*!< LSI clock selected as SysTick clock source */
|
||||
#define SYSTICK_CLKSOURCE_LSE 0x2U /*!< LSE clock selected as SysTick clock source */
|
||||
#define SYSTICK_CLKSOURCE_HCLK 0x4U /*!< AHB clock selected as SysTick clock source */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control
|
||||
* @{
|
||||
*/
|
||||
#define MPU_HFNMI_PRIVDEF_NONE 0U /*!< MPU is disabled during HardFault and NMI handlers,
|
||||
privileged software access to the default memory map is disabled */
|
||||
#define MPU_HARDFAULT_NMI 2U /*!< MPU is enabled during HardFault and NMI handlers,
|
||||
privileged software access to the default memory map is disabled */
|
||||
#define MPU_PRIVILEGED_DEFAULT 4U /*!< MPU is disabled during HardFault and NMI handlers,
|
||||
privileged software access to the default memory map is enabled */
|
||||
#define MPU_HFNMI_PRIVDEF 6U /*!< MPU is enabled during HardFault and NMI handlers,
|
||||
privileged software access to the default memory map is enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
|
||||
* @{
|
||||
*/
|
||||
#define MPU_REGION_ENABLE 1U /*!< MPU region enabled */
|
||||
#define MPU_REGION_DISABLE 0U /*!< MPU region disabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
|
||||
* @{
|
||||
*/
|
||||
#define MPU_INSTRUCTION_ACCESS_ENABLE 0U /*!< MPU region execution permitted (if read permitted) */
|
||||
#define MPU_INSTRUCTION_ACCESS_DISABLE 1U /*!< MPU region execution not permitted */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
|
||||
* @{
|
||||
*/
|
||||
#define MPU_ACCESS_NOT_SHAREABLE 0U /*!< MPU region not shareable */
|
||||
#define MPU_ACCESS_OUTER_SHAREABLE 1U /*!< MPU region outer shareable */
|
||||
#define MPU_ACCESS_INNER_SHAREABLE 3U /*!< MPU region inner shareable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
|
||||
* @{
|
||||
*/
|
||||
#define MPU_REGION_PRIV_RW 0U /*!< MPU region Read/write by privileged code only */
|
||||
#define MPU_REGION_ALL_RW 1U /*!< MPU region Read/write by any privilege level */
|
||||
#define MPU_REGION_PRIV_RO 2U /*!< MPU region Read-only by privileged code only */
|
||||
#define MPU_REGION_ALL_RO 3U /*!< MPU region Read-only by any privilege level */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
|
||||
* @{
|
||||
*/
|
||||
#define MPU_REGION_NUMBER0 0U /*!< MPU region number 0 */
|
||||
#define MPU_REGION_NUMBER1 1U /*!< MPU region number 1 */
|
||||
#define MPU_REGION_NUMBER2 2U /*!< MPU region number 2 */
|
||||
#define MPU_REGION_NUMBER3 3U /*!< MPU region number 3 */
|
||||
#define MPU_REGION_NUMBER4 4U /*!< MPU region number 4 */
|
||||
#define MPU_REGION_NUMBER5 5U /*!< MPU region number 5 */
|
||||
#define MPU_REGION_NUMBER6 6U /*!< MPU region number 6 */
|
||||
#define MPU_REGION_NUMBER7 7U /*!< MPU region number 7 */
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
#define MPU_REGION_NUMBER8 8U /*!< MPU region number 8 */
|
||||
#define MPU_REGION_NUMBER9 9U /*!< MPU region number 9 */
|
||||
#define MPU_REGION_NUMBER10 10U /*!< MPU region number 10 */
|
||||
#define MPU_REGION_NUMBER11 11U /*!< MPU region number 11 */
|
||||
#endif /* __ARM_FEATURE_CMSE */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Attributes_Number CORTEX MPU Memory Attributes Number
|
||||
* @{
|
||||
*/
|
||||
#define MPU_ATTRIBUTES_NUMBER0 0U /*!< MPU attribute number 0 */
|
||||
#define MPU_ATTRIBUTES_NUMBER1 1U /*!< MPU attribute number 1 */
|
||||
#define MPU_ATTRIBUTES_NUMBER2 2U /*!< MPU attribute number 2 */
|
||||
#define MPU_ATTRIBUTES_NUMBER3 3U /*!< MPU attribute number 3 */
|
||||
#define MPU_ATTRIBUTES_NUMBER4 4U /*!< MPU attribute number 4 */
|
||||
#define MPU_ATTRIBUTES_NUMBER5 5U /*!< MPU attribute number 5 */
|
||||
#define MPU_ATTRIBUTES_NUMBER6 6U /*!< MPU attribute number 6 */
|
||||
#define MPU_ATTRIBUTES_NUMBER7 7U /*!< MPU attribute number 7 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Attributes CORTEX MPU Attributes
|
||||
* @{
|
||||
*/
|
||||
#define MPU_DEVICE_nGnRnE 0x0U /*!< Device, noGather, noReorder, noEarly acknowledge. */
|
||||
#define MPU_DEVICE_nGnRE 0x4U /*!< Device, noGather, noReorder, Early acknowledge. */
|
||||
#define MPU_DEVICE_nGRE 0x8U /*!< Device, noGather, Reorder, Early acknowledge. */
|
||||
#define MPU_DEVICE_GRE 0xCU /*!< Device, Gather, Reorder, Early acknowledge. */
|
||||
|
||||
#define MPU_WRITE_THROUGH 0x0U /*!< Normal memory, write-through. */
|
||||
#define MPU_NOT_CACHEABLE 0x4U /*!< Normal memory, non-cacheable. */
|
||||
#define MPU_WRITE_BACK 0x4U /*!< Normal memory, write-back. */
|
||||
|
||||
#define MPU_TRANSIENT 0x0U /*!< Normal memory, transient. */
|
||||
#define MPU_NON_TRANSIENT 0x8U /*!< Normal memory, non-transient. */
|
||||
|
||||
#define MPU_NO_ALLOCATE 0x0U /*!< Normal memory, no allocate. */
|
||||
#define MPU_W_ALLOCATE 0x1U /*!< Normal memory, write allocate. */
|
||||
#define MPU_R_ALLOCATE 0x2U /*!< Normal memory, read allocate. */
|
||||
#define MPU_RW_ALLOCATE 0x3U /*!< Normal memory, read/write allocate. */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
|
||||
* @{
|
||||
*/
|
||||
#define OUTER(__ATTR__) ((__ATTR__) << 4U)
|
||||
#define INNER_OUTER(__ATTR__) ((__ATTR__) | ((__ATTR__) << 4U))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_Exported_Functions_Group1 NVIC functions
|
||||
* @brief NVIC functions
|
||||
* @{
|
||||
*/
|
||||
/* NVIC functions *****************************/
|
||||
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
|
||||
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
|
||||
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_SystemReset(void);
|
||||
uint32_t HAL_NVIC_GetPriorityGrouping(void);
|
||||
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *const pPreemptPriority,
|
||||
uint32_t *const pSubPriority);
|
||||
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
|
||||
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_Exported_Functions_Group2 SYSTICK functions
|
||||
* @brief SYSTICK functions
|
||||
* @{
|
||||
*/
|
||||
/* SYSTICK functions ***********************************************/
|
||||
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
|
||||
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
|
||||
void HAL_SYSTICK_IRQHandler(void);
|
||||
void HAL_SYSTICK_Callback(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_Exported_Functions_Group3 MPU functions
|
||||
* @brief MPU functions
|
||||
* @{
|
||||
*/
|
||||
/* MPU functions ***********************************************/
|
||||
void HAL_MPU_Enable(uint32_t MPU_Control);
|
||||
void HAL_MPU_Disable(void);
|
||||
void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *const pMPU_RegionInit);
|
||||
void HAL_MPU_ConfigMemoryAttributes(const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit);
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
/* MPU_NS Control functions ***********************************************/
|
||||
void HAL_MPU_Enable_NS(uint32_t MPU_Control);
|
||||
void HAL_MPU_Disable_NS(void);
|
||||
void HAL_MPU_ConfigRegion_NS(const MPU_Region_InitTypeDef *const pMPU_RegionInit);
|
||||
void HAL_MPU_ConfigMemoryAttributes_NS(const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit);
|
||||
#endif /* __ARM_FEATURE_CMSE */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_1) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_2) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_3) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_4))
|
||||
|
||||
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < (1UL<<__NVIC_PRIO_BITS))
|
||||
|
||||
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < (1UL<<__NVIC_PRIO_BITS))
|
||||
|
||||
#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) > SysTick_IRQn)
|
||||
|
||||
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_LSI) || \
|
||||
((SOURCE) == SYSTICK_CLKSOURCE_LSE) || \
|
||||
((SOURCE) == SYSTICK_CLKSOURCE_HCLK)|| \
|
||||
((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
|
||||
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
#define IS_MPU_INSTANCE(INSTANCE) (((INSTANCE) == MPU) || ((INSTANCE) == MPU_NS))
|
||||
#endif /* __ARM_FEATURE_CMSE */
|
||||
|
||||
#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
|
||||
((STATE) == MPU_REGION_DISABLE))
|
||||
|
||||
#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
|
||||
((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
|
||||
|
||||
#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_OUTER_SHAREABLE) || \
|
||||
((STATE) == MPU_ACCESS_INNER_SHAREABLE) || \
|
||||
((STATE) == MPU_ACCESS_NOT_SHAREABLE))
|
||||
|
||||
#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_PRIV_RW) || \
|
||||
((TYPE) == MPU_REGION_ALL_RW) || \
|
||||
((TYPE) == MPU_REGION_PRIV_RO) || \
|
||||
((TYPE) == MPU_REGION_ALL_RO))
|
||||
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER1) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER2) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER3) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER4) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER5) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER6) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER7) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER8) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER9) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER10)|| \
|
||||
((NUMBER) == MPU_REGION_NUMBER11))
|
||||
#else
|
||||
#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER1) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER2) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER3) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER4) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER5) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER6) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER7))
|
||||
#endif /* __ARM_FEATURE_CMSE */
|
||||
|
||||
#define IS_MPU_ATTRIBUTES_NUMBER(NUMBER) (((NUMBER) == MPU_ATTRIBUTES_NUMBER0) || \
|
||||
((NUMBER) == MPU_ATTRIBUTES_NUMBER1) || \
|
||||
((NUMBER) == MPU_ATTRIBUTES_NUMBER2) || \
|
||||
((NUMBER) == MPU_ATTRIBUTES_NUMBER3) || \
|
||||
((NUMBER) == MPU_ATTRIBUTES_NUMBER4) || \
|
||||
((NUMBER) == MPU_ATTRIBUTES_NUMBER5) || \
|
||||
((NUMBER) == MPU_ATTRIBUTES_NUMBER6) || \
|
||||
((NUMBER) == MPU_ATTRIBUTES_NUMBER7))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32H5xx_HAL_CORTEX_H */
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,342 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h5xx_hal_crc.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CRC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H5xx_HAL_CRC_H
|
||||
#define STM32H5xx_HAL_CRC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h5xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H5xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup CRC_Exported_Types CRC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief CRC HAL State Structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CRC_STATE_RESET = 0x00U, /*!< CRC not yet initialized or disabled */
|
||||
HAL_CRC_STATE_READY = 0x01U, /*!< CRC initialized and ready for use */
|
||||
HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */
|
||||
HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */
|
||||
HAL_CRC_STATE_ERROR = 0x04U /*!< CRC error state */
|
||||
} HAL_CRC_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CRC Init Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.
|
||||
If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default
|
||||
X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 +
|
||||
X^4 + X^2+ X +1.
|
||||
In that case, there is no need to set GeneratingPolynomial field.
|
||||
If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and
|
||||
CRCLength fields must be set. */
|
||||
|
||||
uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used.
|
||||
If set to DEFAULT_INIT_VALUE_ENABLE, resort to default
|
||||
0xFFFFFFFF value. In that case, there is no need to set InitValue field. If
|
||||
otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */
|
||||
|
||||
uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree
|
||||
respectively equal to 7, 8, 16 or 32. This field is written in normal,
|
||||
representation e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1
|
||||
is written 0x65. No need to specify it if DefaultPolynomialUse is set to
|
||||
DEFAULT_POLYNOMIAL_ENABLE. */
|
||||
|
||||
uint32_t CRCLength; /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length.
|
||||
Value can be either one of
|
||||
@arg @ref CRC_POLYLENGTH_32B (32-bit CRC),
|
||||
@arg @ref CRC_POLYLENGTH_16B (16-bit CRC),
|
||||
@arg @ref CRC_POLYLENGTH_8B (8-bit CRC),
|
||||
@arg @ref CRC_POLYLENGTH_7B (7-bit CRC). */
|
||||
|
||||
uint32_t InitValue; /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse
|
||||
is set to DEFAULT_INIT_VALUE_ENABLE. */
|
||||
|
||||
uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode.
|
||||
Can be either one of the following values
|
||||
@arg @ref CRC_INPUTDATA_INVERSION_NONE no input data inversion
|
||||
@arg @ref CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D
|
||||
becomes 0x58D43CB2
|
||||
@arg @ref CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion,
|
||||
0x1A2B3C4D becomes 0xD458B23C
|
||||
@arg @ref CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D
|
||||
becomes 0xB23CD458 */
|
||||
|
||||
uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
|
||||
Can be either
|
||||
@arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion,
|
||||
@arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted
|
||||
into 0x22CC4488 */
|
||||
} CRC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CRC Handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
CRC_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
CRC_InitTypeDef Init; /*!< CRC configuration parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< CRC Locking object */
|
||||
|
||||
__IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */
|
||||
|
||||
uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format.
|
||||
Can be either
|
||||
@arg @ref CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes
|
||||
(8-bit data)
|
||||
@arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of
|
||||
half-words (16-bit data)
|
||||
@arg @ref CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words
|
||||
(32-bit data)
|
||||
|
||||
Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization
|
||||
error must occur if InputBufferFormat is not one of the three values listed
|
||||
above */
|
||||
} CRC_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CRC_Exported_Constants CRC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Default_Polynomial_Value Default CRC generating polynomial
|
||||
* @{
|
||||
*/
|
||||
#define DEFAULT_CRC32_POLY 0x04C11DB7U /*!< X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Default_InitValue Default CRC computation initialization value
|
||||
* @{
|
||||
*/
|
||||
#define DEFAULT_CRC_INITVALUE 0xFFFFFFFFU /*!< Initial CRC default value */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used
|
||||
* @{
|
||||
*/
|
||||
#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U) /*!< Enable default generating polynomial 0x04C11DB7 */
|
||||
#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U) /*!< Disable default generating polynomial 0x04C11DB7 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Default_InitValue_Use Indicates whether or not default init value is used
|
||||
* @{
|
||||
*/
|
||||
#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U) /*!< Enable initial CRC default value */
|
||||
#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U) /*!< Disable initial CRC default value */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the peripheral
|
||||
* @{
|
||||
*/
|
||||
#define CRC_POLYLENGTH_32B 0x00000000U /*!< Resort to a 32-bit long generating polynomial */
|
||||
#define CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0 /*!< Resort to a 16-bit long generating polynomial */
|
||||
#define CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1 /*!< Resort to a 8-bit long generating polynomial */
|
||||
#define CRC_POLYLENGTH_7B CRC_CR_POLYSIZE /*!< Resort to a 7-bit long generating polynomial */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions
|
||||
* @{
|
||||
*/
|
||||
#define HAL_CRC_LENGTH_32B 32U /*!< 32-bit long CRC */
|
||||
#define HAL_CRC_LENGTH_16B 16U /*!< 16-bit long CRC */
|
||||
#define HAL_CRC_LENGTH_8B 8U /*!< 8-bit long CRC */
|
||||
#define HAL_CRC_LENGTH_7B 7U /*!< 7-bit long CRC */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Input_Buffer_Format Input Buffer Format
|
||||
* @{
|
||||
*/
|
||||
/* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but
|
||||
* an error is triggered in HAL_CRC_Init() if InputDataFormat field is set
|
||||
* to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for
|
||||
* the CRC APIs to provide a correct result */
|
||||
#define CRC_INPUTDATA_FORMAT_UNDEFINED 0x00000000U /*!< Undefined input data format */
|
||||
#define CRC_INPUTDATA_FORMAT_BYTES 0x00000001U /*!< Input data in byte format */
|
||||
#define CRC_INPUTDATA_FORMAT_HALFWORDS 0x00000002U /*!< Input data in half-word format */
|
||||
#define CRC_INPUTDATA_FORMAT_WORDS 0x00000003U /*!< Input data in word format */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup CRC_Exported_Macros CRC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset CRC handle state.
|
||||
* @param __HANDLE__ CRC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @brief Reset CRC Data Register.
|
||||
* @param __HANDLE__ CRC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
|
||||
|
||||
/**
|
||||
* @brief Set CRC INIT non-default value
|
||||
* @param __HANDLE__ CRC handle
|
||||
* @param __INIT__ 32-bit initial value
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
|
||||
|
||||
/**
|
||||
* @brief Store data in the Independent Data (ID) register.
|
||||
* @param __HANDLE__ CRC handle
|
||||
* @param __VALUE__ Value to be stored in the ID register
|
||||
* @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
|
||||
|
||||
/**
|
||||
* @brief Return the data stored in the Independent Data (ID) register.
|
||||
* @param __HANDLE__ CRC handle
|
||||
* @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits
|
||||
* @retval Value of the ID register
|
||||
*/
|
||||
#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private macros --------------------------------------------------------*/
|
||||
/** @defgroup CRC_Private_Macros CRC Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
|
||||
((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))
|
||||
|
||||
#define IS_DEFAULT_INIT_VALUE(VALUE) (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
|
||||
((VALUE) == DEFAULT_INIT_VALUE_DISABLE))
|
||||
|
||||
#define IS_CRC_POL_LENGTH(LENGTH) (((LENGTH) == CRC_POLYLENGTH_32B) || \
|
||||
((LENGTH) == CRC_POLYLENGTH_16B) || \
|
||||
((LENGTH) == CRC_POLYLENGTH_8B) || \
|
||||
((LENGTH) == CRC_POLYLENGTH_7B))
|
||||
|
||||
#define IS_CRC_INPUTDATA_FORMAT(FORMAT) (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES) || \
|
||||
((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
|
||||
((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include CRC HAL Extended module */
|
||||
#include "stm32h5xx_hal_crc_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup CRC_Exported_Functions CRC Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
|
||||
HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc);
|
||||
void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
|
||||
void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
|
||||
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H5xx_HAL_CRC_H */
|
||||
|
|
@ -0,0 +1,150 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h5xx_hal_crc_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CRC HAL extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H5xx_HAL_CRC_EX_H
|
||||
#define STM32H5xx_HAL_CRC_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h5xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H5xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRCEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CRCEx_Exported_Constants CRC Extended Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRCEx_Input_Data_Inversion Input Data Inversion Modes
|
||||
* @{
|
||||
*/
|
||||
#define CRC_INPUTDATA_INVERSION_NONE 0x00000000U /*!< No input data inversion */
|
||||
#define CRC_INPUTDATA_INVERSION_BYTE CRC_CR_REV_IN_0 /*!< Byte-wise input data inversion */
|
||||
#define CRC_INPUTDATA_INVERSION_HALFWORD CRC_CR_REV_IN_1 /*!< HalfWord-wise input data inversion */
|
||||
#define CRC_INPUTDATA_INVERSION_WORD CRC_CR_REV_IN /*!< Word-wise input data inversion */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes
|
||||
* @{
|
||||
*/
|
||||
#define CRC_OUTPUTDATA_INVERSION_DISABLE 0x00000000U /*!< No output data inversion */
|
||||
#define CRC_OUTPUTDATA_INVERSION_ENABLE CRC_CR_REV_OUT /*!< Bit-wise output data inversion */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup CRCEx_Exported_Macros CRC Extended Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set CRC output reversal
|
||||
* @param __HANDLE__ CRC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
|
||||
|
||||
/**
|
||||
* @brief Unset CRC output reversal
|
||||
* @param __HANDLE__ CRC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
|
||||
|
||||
/**
|
||||
* @brief Set CRC non-default polynomial
|
||||
* @param __HANDLE__ CRC handle
|
||||
* @param __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros --------------------------------------------------------*/
|
||||
/** @defgroup CRCEx_Private_Macros CRC Extended Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_CRC_INPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_INPUTDATA_INVERSION_NONE) || \
|
||||
((MODE) == CRC_INPUTDATA_INVERSION_BYTE) || \
|
||||
((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
|
||||
((MODE) == CRC_INPUTDATA_INVERSION_WORD))
|
||||
|
||||
#define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
|
||||
((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup CRCEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRCEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
|
||||
HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);
|
||||
HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H5xx_HAL_CRC_EX_H */
|
||||
|
|
@ -0,0 +1,724 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h5xx_hal_cryp.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CRYP HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H5xx_HAL_CRYP_H
|
||||
#define STM32H5xx_HAL_CRYP_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h5xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H5xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(AES)
|
||||
|
||||
/** @defgroup CRYP CRYP
|
||||
* @brief CRYP HAL module driver.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CRYP_Exported_Types CRYP Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief CRYP Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
|
||||
This parameter can be a value of @ref CRYP_Data_Type */
|
||||
uint32_t KeySize; /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1.
|
||||
128 or 256 bit key length in TinyAES This parameter can be a value
|
||||
of @ref CRYP_Key_Size */
|
||||
uint32_t *pKey; /*!< The key used for encryption/decryption */
|
||||
uint32_t *pInitVect; /*!< The initialization vector used also as initialization
|
||||
counter in CTR mode */
|
||||
uint32_t Algorithm; /*!< DES/ TDES Algorithm ECB/CBC
|
||||
AES Algorithm ECB/CBC/CTR/GCM or CCM
|
||||
This parameter can be a value of @ref CRYP_Algorithm_Mode */
|
||||
uint32_t *Header; /*!< used only in AES GCM and CCM Algorithm for authentication,
|
||||
GCM : also known as Additional Authentication Data
|
||||
CCM : named B1 composed of the associated data length and Associated Data. */
|
||||
uint32_t HeaderSize; /*!< The size of header buffer */
|
||||
uint32_t *B0; /*!< B0 is first authentication block used only in AES CCM mode */
|
||||
uint32_t DataWidthUnit; /*!< Payload Data Width Unit, this parameter can be value of @ref CRYP_Data_Width_Unit */
|
||||
uint32_t HeaderWidthUnit; /*!< Header Width Unit, this parameter can be value of @ref CRYP_Header_Width_Unit */
|
||||
uint32_t KeyIVConfigSkip; /*!< CRYP peripheral Key and IV configuration skip, to config Key and Initialization
|
||||
Vector only once and to skip configuration for consecutive processings.
|
||||
This parameter can be a value of @ref CRYP_Configuration_Skip */
|
||||
uint32_t KeyMode; /*!< Key mode selection, this parameter can be value of @ref CRYP_Key_Mode */
|
||||
uint32_t KeySelect; /*!< Only for SAES : Key selection, this parameter can be value of @ref CRYP_Key_Select */
|
||||
uint32_t KeyProtection; /*!< Only for SAES : Key protection, this parameter can be value of @ref CRYP_Key_Protection */
|
||||
|
||||
} CRYP_ConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CRYP State Structure definition
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
HAL_CRYP_STATE_RESET = 0x00U, /*!< CRYP not yet initialized or disabled */
|
||||
HAL_CRYP_STATE_READY = 0x01U, /*!< CRYP initialized and ready for use */
|
||||
HAL_CRYP_STATE_BUSY = 0x02U, /*!< CRYP BUSY, internal processing is ongoing */
|
||||
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
|
||||
HAL_CRYP_STATE_SUSPENDED = 0x03U, /*!< CRYP suspended */
|
||||
#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
|
||||
} HAL_CRYP_STATETypeDef;
|
||||
|
||||
/**
|
||||
* @brief CRYP Context Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DataType; /*!< This parameter can be a value of @ref CRYP_Data_Type */
|
||||
uint32_t KeySize; /*!< This parameter can be a value of @ref CRYP_Key_Size */
|
||||
uint32_t *pKey; /*!< The key used for encryption/decryption */
|
||||
uint32_t *pInitVect; /*!< The initialization vector, counter with CBC and CTR Algorithm */
|
||||
uint32_t Algorithm; /*!< This parameter can be a value of @ref CRYP_Algorithm_Mode */
|
||||
uint32_t DataWidthUnit; /*!< This parameter can be value of @ref CRYP_Data_Width_Unit */
|
||||
uint32_t KeyIVConfigSkip; /*!< This parameter can be a value of @ref CRYP_Configuration_Skip */
|
||||
uint32_t KeyMode; /*!< This parameter can be value of @ref CRYP_Key_Mode */
|
||||
uint32_t Phase; /*!< CRYP peripheral phase */
|
||||
uint32_t KeyIVConfig; /*!< CRYP peripheral Key and IV configuration flag */
|
||||
uint32_t CR_Reg; /*!< CRYP CR register */
|
||||
uint32_t IER_Reg; /*!< CRYP IER register */
|
||||
uint32_t IVR0_Reg; /*!< CRYP IVR0 register */
|
||||
uint32_t IVR1_Reg; /*!< CRYP IVR1 register */
|
||||
uint32_t IVR2_Reg; /*!< CRYP IVR2 register */
|
||||
uint32_t IVR3_Reg; /*!< CRYP IVR3 register */
|
||||
|
||||
} CRYP_ContextTypeDef;
|
||||
|
||||
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
|
||||
/**
|
||||
* @brief HAL CRYP mode suspend definitions
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CRYP_SUSPEND_NONE = 0x00U, /*!< CRYP processing suspension not requested */
|
||||
HAL_CRYP_SUSPEND = 0x01U /*!< CRYP processing suspension requested */
|
||||
} HAL_SuspendTypeDef;
|
||||
#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
|
||||
|
||||
/**
|
||||
* @brief CRYP handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __CRYP_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
|
||||
{
|
||||
AES_TypeDef *Instance; /*!< AES Register base address */
|
||||
|
||||
CRYP_ConfigTypeDef Init; /*!< CRYP required parameters */
|
||||
uint32_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
|
||||
|
||||
uint32_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
|
||||
|
||||
__IO uint16_t CrypHeaderCount; /*!< Counter of header data in words */
|
||||
|
||||
__IO uint16_t CrypInCount; /*!< Counter of input data in words */
|
||||
|
||||
__IO uint16_t CrypOutCount; /*!< Counter of output data in words */
|
||||
|
||||
uint16_t Size; /*!< length of input data in word or in byte, according to DataWidthUnit */
|
||||
|
||||
uint32_t Phase; /*!< CRYP peripheral phase */
|
||||
|
||||
DMA_HandleTypeDef *hdmain; /*!< CRYP In DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmaout; /*!< CRYP Out DMA handle parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< CRYP locking object */
|
||||
|
||||
__IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< CRYP peripheral error code */
|
||||
|
||||
uint32_t KeyIVConfig; /*!< CRYP peripheral Key and IV configuration flag, used when
|
||||
configuration can be skipped */
|
||||
|
||||
uint32_t SizesSum; /*!< Sum of successive payloads lengths (in bytes), stored
|
||||
for a single signature computation after several
|
||||
messages processing */
|
||||
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
|
||||
void (*InCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Input FIFO transfer completed callback */
|
||||
void (*OutCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Output FIFO transfer completed callback */
|
||||
void (*ErrorCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Error callback */
|
||||
|
||||
void (* MspInitCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Msp DeInit callback */
|
||||
|
||||
#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
|
||||
|
||||
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
|
||||
|
||||
__IO HAL_SuspendTypeDef SuspendRequest; /*!< CRYP peripheral suspension request flag */
|
||||
|
||||
CRYP_ConfigTypeDef Init_saved; /*!< copy of CRYP required parameters when processing is suspended */
|
||||
|
||||
uint32_t *pCrypInBuffPtr_saved; /*!< copy of CRYP input pointer when processing is suspended */
|
||||
|
||||
uint32_t *pCrypOutBuffPtr_saved; /*!< copy of CRYP output pointer when processing is suspended */
|
||||
|
||||
uint32_t CrypInCount_saved; /*!< copy of CRYP input data counter when processing is suspended */
|
||||
|
||||
uint32_t CrypOutCount_saved; /*!< copy of CRYP output data counter when processing is suspended */
|
||||
|
||||
uint32_t Phase_saved; /*!< copy of CRYP authentication phase when processing is suspended */
|
||||
|
||||
__IO HAL_CRYP_STATETypeDef State_saved; /*!< copy of CRYP peripheral state when processing is suspended */
|
||||
|
||||
uint32_t IV_saved[4]; /*!< copy of Initialisation Vector registers */
|
||||
|
||||
uint32_t SUSPxR_saved[8]; /*!< copy of suspension registers */
|
||||
|
||||
uint32_t CR_saved; /*!< copy of CRYP control register when processing is suspended*/
|
||||
|
||||
uint32_t Key_saved[8]; /*!< copy of key registers */
|
||||
|
||||
uint16_t Size_saved; /*!< copy of input buffer size */
|
||||
|
||||
uint16_t CrypHeaderCount_saved; /*!< copy of CRYP header data counter when processing is suspended */
|
||||
|
||||
uint32_t SizesSum_saved; /*!< copy of SizesSum when processing is suspended */
|
||||
|
||||
uint32_t ResumingFlag; /*!< resumption flag to bypass steps already carried out */
|
||||
#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
|
||||
|
||||
} CRYP_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
|
||||
|
||||
/**
|
||||
* @brief HAL CRYP Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CRYP_MSPINIT_CB_ID = 0x00U, /*!< CRYP MspInit callback ID */
|
||||
HAL_CRYP_MSPDEINIT_CB_ID = 0x01U, /*!< CRYP MspDeInit callback ID */
|
||||
HAL_CRYP_INPUT_COMPLETE_CB_ID = 0x02U, /*!< CRYP Input FIFO transfer completed callback ID */
|
||||
HAL_CRYP_OUTPUT_COMPLETE_CB_ID = 0x03U, /*!< CRYP Output FIFO transfer completed callback ID */
|
||||
HAL_CRYP_ERROR_CB_ID = 0x04U, /*!< CRYP Error callback ID */
|
||||
} HAL_CRYP_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL CRYP Callback pointer definition
|
||||
*/
|
||||
typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< pointer to a common CRYP callback function */
|
||||
|
||||
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Exported_Constants CRYP Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Error_Definition CRYP Error Definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_CRYP_ERROR_NONE 0x00000000U /*!< No error */
|
||||
#define HAL_CRYP_ERROR_WRITE 0x00000001U /*!< Write error */
|
||||
#define HAL_CRYP_ERROR_READ 0x00000002U /*!< Read error */
|
||||
#define HAL_CRYP_ERROR_DMA 0x00000004U /*!< DMA error */
|
||||
#define HAL_CRYP_ERROR_BUSY 0x00000008U /*!< Busy flag error */
|
||||
#define HAL_CRYP_ERROR_TIMEOUT 0x00000010U /*!< Timeout error */
|
||||
#define HAL_CRYP_ERROR_NOT_SUPPORTED 0x00000020U /*!< Not supported mode */
|
||||
#define HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE 0x00000040U /*!< Sequence are not respected only for GCM or CCM */
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
|
||||
#define HAL_CRYP_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
|
||||
#define HAL_CRYP_ERROR_KEY 0x00000100U /*!< Key error */
|
||||
#define HAL_CRYP_ERROR_RNG 0x00000200U /*!< Rng error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Data_Width_Unit CRYP Data Width Unit
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_DATAWIDTHUNIT_WORD 0x00000000U /*!< By default, size unit is word */
|
||||
#define CRYP_DATAWIDTHUNIT_BYTE 0x00000001U /*!< By default, size unit is byte */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Header_Width_Unit CRYP Header Width Unit
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_HEADERWIDTHUNIT_WORD 0x00000000U /*!< By default, header size unit is word */
|
||||
#define CRYP_HEADERWIDTHUNIT_BYTE 0x00000001U /*!< By default, header size unit is byte */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Algorithm_Mode CRYP Algorithm Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_AES_ECB 0x00000000U /*!< Electronic codebook chaining algorithm */
|
||||
#define CRYP_AES_CBC AES_CR_CHMOD_0 /*!< Cipher block chaining algorithm */
|
||||
#define CRYP_AES_CTR AES_CR_CHMOD_1 /*!< Counter mode chaining algorithm */
|
||||
#define CRYP_AES_GCM_GMAC (AES_CR_CHMOD_0 | AES_CR_CHMOD_1) /*!< Galois counter mode - Galois message authentication code */
|
||||
#define CRYP_AES_CCM AES_CR_CHMOD_2 /*!< Counter with Cipher Mode */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Key_Size CRYP Key Size
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_KEYSIZE_128B 0x00000000U /*!< 128-bit long key */
|
||||
#define CRYP_KEYSIZE_256B AES_CR_KEYSIZE /*!< 256-bit long key */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Key_Mode CRYP Key Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_KEYMODE_NORMAL 0x00000000U /*!< Normal key usage, Key registers are freely usable */
|
||||
#define CRYP_KEYMODE_SHARED AES_CR_KMOD_1 /*!< Shared key */
|
||||
#define CRYP_KEYMODE_WRAPPED AES_CR_KMOD_0 /*!< Only for SAES, Wrapped key: to encrypt or decrypt AES keys */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Key_Select CRYP Key Select
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_KEYSEL_NORMAL 0x00000000U /*!< Normal key, key registers SAES_KEYx or CRYP_KEYx */
|
||||
#define CRYP_KEYSEL_HW AES_CR_KEYSEL_0 /*!< Only for SAES, Hardware key : derived hardware unique key (DHUK 256-bit) */
|
||||
#define CRYP_KEYSEL_SW AES_CR_KEYSEL_1 /*!< Only for SAES, Software key : boot hardware key BHK (256-bit) */
|
||||
#define CRYP_KEYSEL_HSW AES_CR_KEYSEL_2 /*!< Only for SAES, DHUK XOR BHK Hardware unique key XOR software key */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Key_ShareID CRYP Key Share ID
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_KSHAREID_AES 0x00000000U /*!< Share SAES Key with AES peripheral */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Key_Protection CRYP Key Protection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_KEYPROT_ENABLE AES_CR_KEYPROT /*!< Only for SAES, Key protection between 2 applications with different security contexts */
|
||||
#define CRYP_KEYPROT_DISABLE 0x00000000U /*!< Only for SAES, Key not protected between 2 applications with different security contexts */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CRYP_Data_Type CRYP Data Type
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_DATATYPE_32B 0x00000000U
|
||||
#define CRYP_DATATYPE_16B AES_CR_DATATYPE_0
|
||||
#define CRYP_DATATYPE_8B AES_CR_DATATYPE_1
|
||||
#define CRYP_DATATYPE_1B AES_CR_DATATYPE
|
||||
|
||||
#define CRYP_NO_SWAP CRYP_DATATYPE_32B /*!< 32-bit data type (no swapping) */
|
||||
#define CRYP_HALFWORD_SWAP CRYP_DATATYPE_16B /*!< 16-bit data type (half-word swapping) */
|
||||
#define CRYP_BYTE_SWAP CRYP_DATATYPE_8B /*!< 8-bit data type (byte swapping) */
|
||||
#define CRYP_BIT_SWAP CRYP_DATATYPE_1B /*!< 1-bit data type (bit swapping) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Interrupt CRYP Interrupt
|
||||
* @{
|
||||
*/
|
||||
#define CRYP_IT_CCFIE AES_IER_CCFIE /*!< Computation Complete interrupt enable */
|
||||
#define CRYP_IT_RWEIE AES_IER_RWEIE /*!< Read or write Error interrupt enable */
|
||||
#define CRYP_IT_KEIE AES_IER_KEIE /*!< Key error interrupt enable */
|
||||
#define CRYP_IT_RNGEIE AES_IER_RNGEIE /*!< Rng error interrupt enable */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Flags CRYP Flags
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_FLAG_BUSY AES_SR_BUSY /*!< GCM process suspension forbidden also set when
|
||||
transferring a shared key from SAES peripheral */
|
||||
#define CRYP_FLAG_WRERR (AES_SR_WRERR | 0x80000000U) /*!< Write Error flag */
|
||||
#define CRYP_FLAG_RDERR (AES_SR_RDERR | 0x80000000U) /*!< Read error flag */
|
||||
#define CRYP_FLAG_CCF AES_ISR_CCF /*!< Computation completed flag as AES_ISR_CCF */
|
||||
#define CRYP_FLAG_KEYVALID AES_SR_KEYVALID /*!< Key Valid flag */
|
||||
#define CRYP_FLAG_KEIF AES_ISR_KEIF /*!<Key error interrupt flag */
|
||||
#define CRYP_FLAG_RWEIF AES_ISR_RWEIF /*!<Read or write error Interrupt flag */
|
||||
#define CRYP_FLAG_RNGEIF AES_ISR_RNGEIF /*!<RNG error interrupt flag */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_CLEAR_Flags CRYP CLEAR Flags
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_CLEAR_CCF AES_ICR_CCF /*!< Computation Complete Flag Clear */
|
||||
#define CRYP_CLEAR_RWEIF AES_ICR_RWEIF /*!< Clear Error Flag : RWEIF in AES_ISR and
|
||||
both RDERR and WRERR flags in AES_SR */
|
||||
#define CRYP_CLEAR_KEIF AES_ICR_KEIF /*!< Clear Key Error Flag: KEIF in AES_ISR */
|
||||
#define CRYP_CLEAR_RNGEIF AES_ICR_RNGEIF /*!< Clear rng Error Flag: RNGEIF in AES_ISR */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Configuration_Skip CRYP Key and IV Configuration Skip Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_KEYIVCONFIG_ALWAYS 0x00000000U /*!< Peripheral Key and IV configuration to do systematically */
|
||||
#define CRYP_KEYIVCONFIG_ONCE 0x00000001U /*!< Peripheral Key and IV configuration to do only once */
|
||||
#define CRYP_KEYNOCONFIG 0x00000002U /*!< Peripheral Key configuration to not do */
|
||||
#define CRYP_IVCONFIG_ONCE 0x00000004U /*!< Peripheral IV configuration do once for interleave mode */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Exported_Macros CRYP Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset CRYP handle state
|
||||
* @param __HANDLE__ specifies the CRYP handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
|
||||
#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) do{\
|
||||
(__HANDLE__)->State = HAL_CRYP_STATE_RESET;\
|
||||
(__HANDLE__)->MspInitCallback = NULL;\
|
||||
(__HANDLE__)->MspDeInitCallback = NULL;\
|
||||
}while(0U)
|
||||
#else
|
||||
#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_CRYP_STATE_RESET)
|
||||
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @brief Enable/Disable the CRYP peripheral.
|
||||
* @param __HANDLE__ specifies the CRYP handle.
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
#define __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= AES_CR_EN)
|
||||
#define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~AES_CR_EN)
|
||||
|
||||
|
||||
/** @brief Check whether the specified CRYP status flag is set or not.
|
||||
* @param __HANDLE__ specifies the CRYP handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values for TinyAES:
|
||||
* @arg @ref CRYP_FLAG_KEYVALID Key valid flag
|
||||
* @arg @ref CRYP_FLAG_BUSY GCM process suspension forbidden or
|
||||
* transferring a shared key from SAES IP.
|
||||
* @arg @ref CRYP_FLAG_WRERR Write Error flag
|
||||
* @arg @ref CRYP_FLAG_RDERR Read Error flag
|
||||
* @arg @ref CRYP_FLAG_CCF Computation Complete flag
|
||||
* @arg @ref CRYP_FLAG_KEIF Key error flag
|
||||
* @arg @ref CRYP_FLAG_RWEIF Read/write Error flag
|
||||
|
||||
* @retval The state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
|
||||
#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) (\
|
||||
((__FLAG__) == CRYP_FLAG_KEYVALID )?(((__HANDLE__)->Instance->SR \
|
||||
& (CRYP_FLAG_KEYVALID)) == (CRYP_FLAG_KEYVALID)) : \
|
||||
((__FLAG__) == CRYP_FLAG_BUSY )?(((__HANDLE__)->Instance->SR \
|
||||
& (CRYP_FLAG_BUSY)) == (CRYP_FLAG_BUSY)) : \
|
||||
((__FLAG__) == CRYP_FLAG_WRERR )?(((__HANDLE__)->Instance->SR \
|
||||
& (CRYP_FLAG_WRERR & 0x7FFFFFFFU)) == \
|
||||
(CRYP_FLAG_WRERR & 0x7FFFFFFFU)) : \
|
||||
((__FLAG__) == CRYP_FLAG_RDERR )?(((__HANDLE__)->Instance->SR \
|
||||
& (CRYP_FLAG_RDERR & 0x7FFFFFFFU)) == \
|
||||
(CRYP_FLAG_RDERR & 0x7FFFFFFFU)) : \
|
||||
((__FLAG__) == CRYP_FLAG_KEIF )?(((__HANDLE__)->Instance->ISR \
|
||||
& (CRYP_FLAG_KEIF)) == (CRYP_FLAG_KEIF)) : \
|
||||
((__FLAG__) == CRYP_FLAG_RWEIF )?(((__HANDLE__)->Instance->ISR \
|
||||
& (CRYP_FLAG_RWEIF)) == (CRYP_FLAG_RWEIF)) : \
|
||||
(((__HANDLE__)->Instance->ISR & (CRYP_FLAG_CCF)) == (CRYP_FLAG_CCF)))
|
||||
|
||||
/** @brief Clear the CRYP pending status flag.
|
||||
* @param __HANDLE__ specifies the CRYP handle.
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref CRYP_CLEAR_RWEIF Read (RDERR), Write (WRERR) or Read/write (RWEIF) Error Flag Clear
|
||||
* @arg @ref CRYP_CLEAR_CCF Computation Complete Flag (CCF) Clear
|
||||
* @arg @ref CRYP_CLEAR_KEIF Key error interrupt flag clear
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
#define __HAL_CRYP_CLEAR_FLAG(__HANDLE__, __FLAG__) SET_BIT((__HANDLE__)->Instance->ICR, (__FLAG__))
|
||||
|
||||
|
||||
/** @brief Check whether the specified CRYP interrupt source is enabled or not.
|
||||
* @param __HANDLE__ specifies the CRYP handle.
|
||||
* @param __INTERRUPT__ CRYP interrupt source to check
|
||||
* This parameter can be one of the following values for TinyAES:
|
||||
* @arg @ref CRYP_IT_RWEIE Error interrupt (used for RDERR and WRERR)
|
||||
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
|
||||
* @arg @ref CRYP_IT_KEIE Key error interrupt
|
||||
* @retval State of interruption (TRUE or FALSE).
|
||||
*/
|
||||
|
||||
#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER\
|
||||
& (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Enable the CRYP interrupt.
|
||||
* @param __HANDLE__ specifies the CRYP handle.
|
||||
* @param __INTERRUPT__ CRYP Interrupt.
|
||||
* This parameter can be one of the following values for TinyAES:
|
||||
* @arg @ref CRYP_IT_RWEIE Error interrupt (used for RDERR and WRERR)
|
||||
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
|
||||
* @arg @ref CRYP_IT_KEIE Key error interrupt
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the CRYP interrupt.
|
||||
* @param __HANDLE__ specifies the CRYP handle.
|
||||
* @param __INTERRUPT__ CRYP Interrupt.
|
||||
* This parameter can be one of the following values for TinyAES:
|
||||
* @arg @ref CRYP_IT_RWEIE Error interrupt (used for RDERR and WRERR)
|
||||
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
|
||||
* @arg @ref CRYP_IT_KEIE Key error interrupt
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include CRYP HAL Extended module */
|
||||
#include "stm32h5xx_hal_cryp_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Exported_Functions CRYP Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRYP_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
|
||||
HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
|
||||
void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
|
||||
void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
|
||||
HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf);
|
||||
HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf);
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
|
||||
HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID,
|
||||
pCRYP_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
|
||||
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
|
||||
void HAL_CRYP_ProcessSuspend(CRYP_HandleTypeDef *hcryp);
|
||||
HAL_StatusTypeDef HAL_CRYP_Suspend(CRYP_HandleTypeDef *hcryp);
|
||||
HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp);
|
||||
#endif /* defined (USE_HAL_CRYP_SUSPEND_RESUME) */
|
||||
HAL_StatusTypeDef HAL_CRYP_SaveContext(CRYP_HandleTypeDef *hcryp, CRYP_ContextTypeDef *pcont);
|
||||
HAL_StatusTypeDef HAL_CRYP_RestoreContext(CRYP_HandleTypeDef *hcryp, CRYP_ContextTypeDef *pcont);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CRYP_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* encryption/decryption ***********************************/
|
||||
HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint16_t Size, uint32_t *pOutput,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint16_t Size, uint32_t *pOutput,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint16_t Size, uint32_t *pOutput);
|
||||
HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint16_t Size, uint32_t *pOutput);
|
||||
HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint16_t Size, uint32_t *pOutput);
|
||||
HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint16_t Size, uint32_t *pOutput);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup CRYP_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Interrupt Handler functions **********************************************/
|
||||
void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
|
||||
HAL_CRYP_STATETypeDef HAL_CRYP_GetState(const CRYP_HandleTypeDef *hcryp);
|
||||
void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
|
||||
void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
|
||||
void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
|
||||
uint32_t HAL_CRYP_GetError(const CRYP_HandleTypeDef *hcryp);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros --------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Private_Macros CRYP Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_CRYP_INSTANCE(INSTANCE)(((INSTANCE) == AES) || \
|
||||
((INSTANCE) == SAES))
|
||||
|
||||
#define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_AES_ECB) || \
|
||||
((ALGORITHM) == CRYP_AES_CBC) || \
|
||||
((ALGORITHM) == CRYP_AES_CTR) || \
|
||||
((ALGORITHM) == CRYP_AES_GCM_GMAC)|| \
|
||||
((ALGORITHM) == CRYP_AES_CCM))
|
||||
|
||||
|
||||
#define IS_CRYP_KEYSIZE(KEYSIZE)(((KEYSIZE) == CRYP_KEYSIZE_128B) || \
|
||||
((KEYSIZE) == CRYP_KEYSIZE_256B))
|
||||
|
||||
#define IS_CRYP_DATATYPE(DATATYPE)(((DATATYPE) == CRYP_NO_SWAP) || \
|
||||
((DATATYPE) == CRYP_HALFWORD_SWAP) || \
|
||||
((DATATYPE) == CRYP_BYTE_SWAP) || \
|
||||
((DATATYPE) == CRYP_BIT_SWAP))
|
||||
|
||||
#define IS_CRYP_INIT(CONFIG)(((CONFIG) == CRYP_KEYIVCONFIG_ALWAYS) || \
|
||||
((CONFIG) == CRYP_KEYNOCONFIG) || \
|
||||
((CONFIG) == CRYP_IVCONFIG_ONCE) || \
|
||||
((CONFIG) == CRYP_KEYIVCONFIG_ONCE))
|
||||
|
||||
#define IS_CRYP_BUFFERSIZE(ALGO, DATAWIDTH, SIZE) \
|
||||
(((((ALGO) == CRYP_AES_CTR)) && \
|
||||
((((DATAWIDTH) == CRYP_DATAWIDTHUNIT_WORD) && (((SIZE) % 4U) == 0U)) || \
|
||||
(((DATAWIDTH) == CRYP_DATAWIDTHUNIT_BYTE) && (((SIZE) % 16U) == 0U)))) || \
|
||||
(((ALGO) == CRYP_AES_ECB) || ((ALGO) == CRYP_AES_CBC) || \
|
||||
((ALGO)== CRYP_AES_GCM_GMAC) || ((ALGO) == CRYP_AES_CCM)))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Private_Constants CRYP Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private defines -----------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Private_Defines CRYP Private Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Private_Variables CRYP Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Private_Functions CRYP Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* AES */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H5xx_HAL_CRYP_H */
|
||||
|
|
@ -0,0 +1,154 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h5xx_hal_cryp_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CRYPEx HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H5xx_HAL_CRYP_EX_H
|
||||
#define STM32H5xx_HAL_CRYP_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h5xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H5xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(AES)
|
||||
|
||||
/** @defgroup CRYPEx CRYPEx
|
||||
* @brief CRYP Extension HAL module driver.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup CRYPEx_Exported_Types CRYPEx Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CRYPEx_Exported_Constants CRYPEx Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/** @defgroup CRYPEx_Private_Types CRYPEx Private Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup CRYPEx_Private_Variables CRYPEx Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup CRYPEx_Private_Constants CRYPEx Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup CRYPEx_Private_Macros CRYPEx Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRYPEx_Exported_Functions_Group1 Extended AES processing functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, const uint32_t *pAuthTag,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, const uint32_t *pAuthTag,
|
||||
uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CRYPEx_Exported_Functions_Group2 Wrap and Unwrap key functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRYPEx_UnwrapKey(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CRYPEx_WrapKey(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint32_t *pOutput, uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CRYPEx_Exported_Functions_Group3 Encrypt and Decrypt Shared key functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRYPEx_EncryptSharedKey(CRYP_HandleTypeDef *hcryp, uint32_t *pKey, uint32_t *pOutput, uint32_t ID,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CRYPEx_DecryptSharedKey(CRYP_HandleTypeDef *hcryp, uint32_t *pKey, uint32_t ID, uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* AES */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H5xx_HAL_CRYP_EX_H */
|
||||
|
|
@ -0,0 +1,593 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h5xx_hal_dac.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of DAC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H5xx_HAL_DAC_H
|
||||
#define STM32H5xx_HAL_DAC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @addtogroup STM32H5xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h5xx_hal_def.h"
|
||||
|
||||
#if defined(DAC1)
|
||||
|
||||
/** @addtogroup DAC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DAC_Exported_Types DAC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DAC_STATE_RESET = 0x00U, /*!< DAC not yet initialized or disabled */
|
||||
HAL_DAC_STATE_READY = 0x01U, /*!< DAC initialized and ready for use */
|
||||
HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */
|
||||
HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */
|
||||
HAL_DAC_STATE_ERROR = 0x04U /*!< DAC error state */
|
||||
|
||||
} HAL_DAC_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DAC handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __DAC_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
{
|
||||
DAC_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
__IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< DAC locking object */
|
||||
|
||||
DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */
|
||||
|
||||
DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< DAC Error code */
|
||||
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
void (* ConvCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* ConvHalfCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* ErrorCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* DMAUnderrunCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
|
||||
|
||||
void (* ConvCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* ConvHalfCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* ErrorCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* DMAUnderrunCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
|
||||
|
||||
|
||||
void (* MspInitCallback)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* MspDeInitCallback)(struct __DAC_HandleTypeDef *hdac);
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
|
||||
} DAC_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DAC Configuration sample and hold Channel structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DAC_SampleTime ; /*!< Specifies the Sample time for the selected channel.
|
||||
This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */
|
||||
|
||||
uint32_t DAC_HoldTime ; /*!< Specifies the hold time for the selected channel
|
||||
This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */
|
||||
|
||||
uint32_t DAC_RefreshTime ; /*!< Specifies the refresh time for the selected channel
|
||||
This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 255 */
|
||||
} DAC_SampleAndHoldConfTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DAC Configuration regular Channel structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DAC_HighFrequency; /*!< Specifies the frequency interface mode
|
||||
This parameter can be a value of @ref DAC_HighFrequency */
|
||||
|
||||
FunctionalState DAC_DMADoubleDataMode; /*!< Specifies if DMA double data mode should be enabled or not for the selected channel.
|
||||
This parameter can be ENABLE or DISABLE */
|
||||
|
||||
FunctionalState DAC_SignedFormat; /*!< Specifies if signed format should be used or not for the selected channel.
|
||||
This parameter can be ENABLE or DISABLE */
|
||||
|
||||
uint32_t DAC_SampleAndHold; /*!< Specifies whether the DAC mode.
|
||||
This parameter can be a value of @ref DAC_SampleAndHold */
|
||||
|
||||
uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
|
||||
This parameter can be a value of @ref DAC_trigger_selection */
|
||||
|
||||
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
|
||||
This parameter can be a value of @ref DAC_output_buffer */
|
||||
|
||||
uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral.
|
||||
This parameter can be a value of @ref DAC_ConnectOnChipPeripheral */
|
||||
|
||||
uint32_t DAC_UserTrimming; /*!< Specifies the trimming mode
|
||||
This parameter must be a value of @ref DAC_UserTrimming
|
||||
DAC_UserTrimming is either factory or user trimming */
|
||||
|
||||
uint32_t DAC_TrimmingValue; /*!< Specifies the offset trimming value
|
||||
i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
|
||||
DAC_SampleAndHoldConfTypeDef DAC_SampleAndHoldConfig; /*!< Sample and Hold settings */
|
||||
} DAC_ChannelConfTypeDef;
|
||||
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL DAC Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DAC_CH1_COMPLETE_CB_ID = 0x00U, /*!< DAC CH1 Complete Callback ID */
|
||||
HAL_DAC_CH1_HALF_COMPLETE_CB_ID = 0x01U, /*!< DAC CH1 half Complete Callback ID */
|
||||
HAL_DAC_CH1_ERROR_ID = 0x02U, /*!< DAC CH1 error Callback ID */
|
||||
HAL_DAC_CH1_UNDERRUN_CB_ID = 0x03U, /*!< DAC CH1 underrun Callback ID */
|
||||
|
||||
HAL_DAC_CH2_COMPLETE_CB_ID = 0x04U, /*!< DAC CH2 Complete Callback ID */
|
||||
HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, /*!< DAC CH2 half Complete Callback ID */
|
||||
HAL_DAC_CH2_ERROR_ID = 0x06U, /*!< DAC CH2 error Callback ID */
|
||||
HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U, /*!< DAC CH2 underrun Callback ID */
|
||||
|
||||
HAL_DAC_MSPINIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */
|
||||
HAL_DAC_MSPDEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */
|
||||
HAL_DAC_ALL_CB_ID = 0x0AU /*!< DAC All ID */
|
||||
} HAL_DAC_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DAC Callback pointer definition
|
||||
*/
|
||||
typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DAC_Exported_Constants DAC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Error_Code DAC Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DAC_ERROR_NONE 0x00U /*!< No error */
|
||||
#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DMA underrun error */
|
||||
#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DMA underrun error */
|
||||
#define HAL_DAC_ERROR_DMA 0x04U /*!< DMA error */
|
||||
#define HAL_DAC_ERROR_TIMEOUT 0x08U /*!< Timeout error */
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_DAC_ERROR_INVALID_CALLBACK 0x10U /*!< Invalid callback error */
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
#define HAL_DAC_ERROR_INVALID_CONFIG 0x20U /*!< Invalid configuration error */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_trigger_selection DAC trigger selection
|
||||
* @{
|
||||
*/
|
||||
/* Triggers common to all devices of STM32H5 series */
|
||||
#define DAC_TRIGGER_NONE 0x00000000UL /*!< conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger */
|
||||
#define DAC_TRIGGER_SOFTWARE ( DAC_CR_TEN1) /*!< conversion started by software trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T1_TRGO ( DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM1 TRGO selected as external conversion trigger for DAC channel. */
|
||||
#define DAC_TRIGGER_T2_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_LPTIM1_CH1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< LPTIM1 CH1 selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_LPTIM2_CH1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< LPTIM2 CH1 selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
|
||||
|
||||
/* Triggers specific to some devices of STM32H5 series */
|
||||
#if defined(TIM8)
|
||||
/* Devices STM32H563/H573xx */
|
||||
#define DAC_TRIGGER_T4_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T5_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T8_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T15_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TEN1) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */
|
||||
#else
|
||||
/* Devices STM32H503xx */
|
||||
#define DAC_TRIGGER_T3_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
|
||||
|
||||
#endif /* Devices STM32H563/H573xx or STM32H503xx */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_output_buffer DAC output buffer
|
||||
* @{
|
||||
*/
|
||||
#define DAC_OUTPUTBUFFER_ENABLE 0x00000000U
|
||||
#define DAC_OUTPUTBUFFER_DISABLE (DAC_MCR_MODE1_1)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Channel_selection DAC Channel selection
|
||||
* @{
|
||||
*/
|
||||
#define DAC_CHANNEL_1 0x00000000U
|
||||
|
||||
#define DAC_CHANNEL_2 0x00000010U
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_data_alignment DAC data alignment
|
||||
* @{
|
||||
*/
|
||||
#define DAC_ALIGN_12B_R 0x00000000U
|
||||
#define DAC_ALIGN_12B_L 0x00000004U
|
||||
#define DAC_ALIGN_8B_R 0x00000008U
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_flags_definition DAC flags definition
|
||||
* @{
|
||||
*/
|
||||
#define DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1)
|
||||
|
||||
#define DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2)
|
||||
|
||||
#define DAC_FLAG_DAC1RDY (DAC_SR_DAC1RDY)
|
||||
|
||||
#define DAC_FLAG_DAC2RDY (DAC_SR_DAC2RDY)
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_IT_definition DAC IT definition
|
||||
* @{
|
||||
*/
|
||||
#define DAC_IT_DMAUDR1 (DAC_SR_DMAUDR1)
|
||||
|
||||
#define DAC_IT_DMAUDR2 (DAC_SR_DMAUDR2)
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral
|
||||
* @{
|
||||
*/
|
||||
#define DAC_CHIPCONNECT_EXTERNAL (1UL << 0)
|
||||
#define DAC_CHIPCONNECT_INTERNAL (1UL << 1)
|
||||
#define DAC_CHIPCONNECT_BOTH (1UL << 2)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_UserTrimming DAC User Trimming
|
||||
* @{
|
||||
*/
|
||||
#define DAC_TRIMMING_FACTORY (0x00000000UL) /*!< Factory trimming */
|
||||
#define DAC_TRIMMING_USER (0x00000001UL) /*!< User trimming */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_SampleAndHold DAC power mode
|
||||
* @{
|
||||
*/
|
||||
#define DAC_SAMPLEANDHOLD_DISABLE (0x00000000UL)
|
||||
#define DAC_SAMPLEANDHOLD_ENABLE (DAC_MCR_MODE1_2)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup DAC_HighFrequency DAC high frequency interface mode
|
||||
* @{
|
||||
*/
|
||||
#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE 0x00000000UL /*!< High frequency interface mode disabled */
|
||||
#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ (DAC_MCR_HFSEL_0) /*!< High frequency interface mode compatible to AHB>80MHz enabled */
|
||||
#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_160MHZ (DAC_MCR_HFSEL_1) /*!< High frequency interface mode compatible to AHB>160MHz enabled */
|
||||
#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC 0x00000002UL /*!< High frequency interface mode automatic */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Delay for DAC channel voltage settling time from DAC channel startup */
|
||||
/* (transition from disable to enable). */
|
||||
/* Note: DAC channel startup time depends on board application environment: */
|
||||
/* impedance connected to DAC channel output. */
|
||||
/* The delay below is specified under conditions: */
|
||||
/* - voltage maximum transition (lowest to highest value) */
|
||||
/* - until voltage reaches final value +-1LSB */
|
||||
/* - DAC channel output buffer enabled */
|
||||
/* - load impedance of 5kOhm (min), 50pF (max) */
|
||||
/* Literal set to maximum value (refer to device datasheet, */
|
||||
/* parameter "tWAKEUP"). */
|
||||
/* Unit: us */
|
||||
#define DAC_DELAY_STARTUP_US (15UL) /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DAC_Exported_Macros DAC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset DAC handle state.
|
||||
* @param __HANDLE__ specifies the DAC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do { \
|
||||
(__HANDLE__)->State = HAL_DAC_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
|
||||
/** @brief Enable the DAC channel.
|
||||
* @param __HANDLE__ specifies the DAC handle.
|
||||
* @param __DAC_Channel__ specifies the DAC channel
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
|
||||
((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
|
||||
|
||||
/** @brief Disable the DAC channel.
|
||||
* @param __HANDLE__ specifies the DAC handle
|
||||
* @param __DAC_Channel__ specifies the DAC channel.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
|
||||
((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
|
||||
|
||||
/** @brief Set DHR12R1 alignment.
|
||||
* @param __ALIGNMENT__ specifies the DAC alignment
|
||||
* @retval None
|
||||
*/
|
||||
#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008UL + (__ALIGNMENT__))
|
||||
|
||||
|
||||
/** @brief Set DHR12R2 alignment.
|
||||
* @param __ALIGNMENT__ specifies the DAC alignment
|
||||
* @retval None
|
||||
*/
|
||||
#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014UL + (__ALIGNMENT__))
|
||||
|
||||
|
||||
/** @brief Set DHR12RD alignment.
|
||||
* @param __ALIGNMENT__ specifies the DAC alignment
|
||||
* @retval None
|
||||
*/
|
||||
#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020UL + (__ALIGNMENT__))
|
||||
|
||||
/** @brief Enable the DAC interrupt.
|
||||
* @param __HANDLE__ specifies the DAC handle
|
||||
* @param __INTERRUPT__ specifies the DAC interrupt.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
|
||||
* @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
|
||||
|
||||
/** @brief Disable the DAC interrupt.
|
||||
* @param __HANDLE__ specifies the DAC handle
|
||||
* @param __INTERRUPT__ specifies the DAC interrupt.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
|
||||
* @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
|
||||
|
||||
/** @brief Check whether the specified DAC interrupt source is enabled or not.
|
||||
* @param __HANDLE__ DAC handle
|
||||
* @param __INTERRUPT__ DAC interrupt source to check
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
|
||||
* @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
|
||||
* @retval State of interruption (SET or RESET)
|
||||
*/
|
||||
#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR\
|
||||
& (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
/** @brief Get the selected DAC's flag status.
|
||||
* @param __HANDLE__ specifies the DAC handle.
|
||||
* @param __FLAG__ specifies the DAC flag to get.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
|
||||
* @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag
|
||||
* @arg DAC_FLAG_DAC1RDY DAC channel 1 ready status flag
|
||||
* @arg DAC_FLAG_DAC2RDY DAC channel 2 ready status flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clear the DAC's flag.
|
||||
* @param __HANDLE__ specifies the DAC handle.
|
||||
* @param __FLAG__ specifies the DAC flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
|
||||
* @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DAC_Private_Macros DAC Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
|
||||
((STATE) == DAC_OUTPUTBUFFER_DISABLE))
|
||||
|
||||
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
|
||||
((CHANNEL) == DAC_CHANNEL_2))
|
||||
|
||||
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
|
||||
((ALIGN) == DAC_ALIGN_12B_L) || \
|
||||
((ALIGN) == DAC_ALIGN_8B_R))
|
||||
|
||||
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0UL)
|
||||
|
||||
#define IS_DAC_REFRESHTIME(TIME) ((TIME) <= 0x000000FFUL)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include DAC HAL Extended module */
|
||||
#include "stm32h5xx_hal_dac_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup DAC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac);
|
||||
HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length,
|
||||
uint32_t Alignment);
|
||||
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac);
|
||||
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
|
||||
|
||||
void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
|
||||
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
/* DAC callback registering/unregistering */
|
||||
HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID,
|
||||
pDAC_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac,
|
||||
const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC_Exported_Functions_Group4
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_DAC_StateTypeDef HAL_DAC_GetState(const DAC_HandleTypeDef *hdac);
|
||||
uint32_t HAL_DAC_GetError(const DAC_HandleTypeDef *hdac);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Private_Functions DAC Private Functions
|
||||
* @{
|
||||
*/
|
||||
void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
|
||||
void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
|
||||
void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* DAC1 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* STM32H5xx_HAL_DAC_H */
|
||||
|
|
@ -0,0 +1,256 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h5xx_hal_dac_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of DAC HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H5xx_HAL_DAC_EX_H
|
||||
#define STM32H5xx_HAL_DAC_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @addtogroup STM32H5xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h5xx_hal_def.h"
|
||||
|
||||
#if defined(DAC1)
|
||||
|
||||
/** @addtogroup DACEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DACEx_Exported_Constants DACEx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangle amplitude
|
||||
* @{
|
||||
*/
|
||||
#define DAC_LFSRUNMASK_BIT0 0x00000000UL /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
|
||||
#define DAC_TRIANGLEAMPLITUDE_1 0x00000000UL /*!< Select max triangle amplitude of 1 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 7 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Select max triangle amplitude of 31 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 127 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Select max triangle amplitude of 511 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 2047 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DACEx_Private_Macros DACEx Private Macros
|
||||
* @{
|
||||
*/
|
||||
#if defined(TIM8)
|
||||
/* Devices STM32H563/H573xx */
|
||||
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T1_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_LPTIM1_CH1) || \
|
||||
((TRIGGER) == DAC_TRIGGER_LPTIM2_CH1) || \
|
||||
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
|
||||
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
|
||||
#else
|
||||
/* Devices STM32H503xx */
|
||||
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T1_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_LPTIM1_CH1) || \
|
||||
((TRIGGER) == DAC_TRIGGER_LPTIM2_CH1) || \
|
||||
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
|
||||
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
|
||||
#endif /* Devices STM32H563/H573xx or STM32H503xx */
|
||||
|
||||
#define IS_DAC_HIGH_FREQUENCY_MODE(MODE) (((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE) || \
|
||||
((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ) || \
|
||||
((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_160MHZ) || \
|
||||
((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC))
|
||||
|
||||
#define IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x000003FFU)
|
||||
|
||||
#define IS_DAC_HOLDTIME(TIME) ((TIME) <= 0x000003FFU)
|
||||
|
||||
#define IS_DAC_SAMPLEANDHOLD(MODE) (((MODE) == DAC_SAMPLEANDHOLD_DISABLE) || \
|
||||
((MODE) == DAC_SAMPLEANDHOLD_ENABLE))
|
||||
|
||||
#define IS_DAC_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
|
||||
|
||||
#define IS_DAC_NEWTRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
|
||||
|
||||
#define IS_DAC_CHIP_CONNECTION(CONNECT) (((CONNECT) == DAC_CHIPCONNECT_EXTERNAL) || \
|
||||
((CONNECT) == DAC_CHIPCONNECT_INTERNAL) || \
|
||||
((CONNECT) == DAC_CHIPCONNECT_BOTH))
|
||||
|
||||
#define IS_DAC_TRIMMING(TRIMMING) (((TRIMMING) == DAC_TRIMMING_FACTORY) || \
|
||||
((TRIMMING) == DAC_TRIMMING_USER))
|
||||
|
||||
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/* Extended features functions ***********************************************/
|
||||
|
||||
/** @addtogroup DACEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DACEx_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
|
||||
HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
|
||||
HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
|
||||
|
||||
HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac);
|
||||
HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac);
|
||||
HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel,
|
||||
const uint32_t *pData, uint32_t Length, uint32_t Alignment);
|
||||
HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
|
||||
uint32_t HAL_DACEx_DualGetValue(const DAC_HandleTypeDef *hdac);
|
||||
|
||||
void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac);
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DACEx_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
|
||||
HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel,
|
||||
uint32_t NewTrimmingValue);
|
||||
uint32_t HAL_DACEx_GetTrimOffset(const DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DACEx_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* DAC_DMAConvCpltCh2 / DAC_DMAErrorCh2 / DAC_DMAHalfConvCpltCh2 */
|
||||
/* are called by HAL_DAC_Start_DMA */
|
||||
void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
|
||||
void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
|
||||
void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* DAC1 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H5xx_HAL_DAC_EX_H */
|
||||
|
|
@ -0,0 +1,355 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h5xx_hal_dcache.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of DCACHE HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion ------------------------------------*/
|
||||
#ifndef STM32H5xx_HAL_DCACHE_H
|
||||
#define STM32H5xx_HAL_DCACHE_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes -----------------------------------------------------------------*/
|
||||
#include "stm32h5xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H5xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (DCACHE1)
|
||||
|
||||
/** @addtogroup DCACHE
|
||||
* @{
|
||||
*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DCACHE_Exported_Types DCACHE Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief DCACHE Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ReadBurstType; /*!< Burst type to be applied for Data Cache
|
||||
This parameter can be a value of @ref DCACHE_Read_Burst_Type*/
|
||||
} DCACHE_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DCACHE_STATE_RESET = 0x00U, /*!< DCACHE not yet initialized or disabled */
|
||||
HAL_DCACHE_STATE_READY = 0x01U, /*!< Peripheral initialized and ready for use */
|
||||
HAL_DCACHE_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
|
||||
HAL_DCACHE_STATE_TIMEOUT = 0x05U, /*!< Timeout state */
|
||||
HAL_DCACHE_STATE_ERROR = 0x06U, /*!< DCACHE state error */
|
||||
} HAL_DCACHE_StateTypeDef;
|
||||
|
||||
/** @defgroup DCACHE_Configuration_Structure_definition DCACHE Configuration Structure definition
|
||||
* @brief DCACHE Configuration Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct __DCACHE_HandleTypeDef
|
||||
{
|
||||
DCACHE_TypeDef *Instance; /*!< DCACHE register base address. */
|
||||
DCACHE_InitTypeDef Init; /*!< DCACHE Initialization Structure. */
|
||||
|
||||
void (* ErrorCallback)(struct __DCACHE_HandleTypeDef *hdcache);
|
||||
void (* CleanByAddrCallback)(struct __DCACHE_HandleTypeDef *hdcache);
|
||||
void (* InvalidateByAddrCallback)(struct __DCACHE_HandleTypeDef *hdcache);
|
||||
void (* InvalidateCompleteCallback)(struct __DCACHE_HandleTypeDef *hdcache);
|
||||
void (* CleanAndInvalidateByAddrCallback)(struct __DCACHE_HandleTypeDef *hdcache);
|
||||
|
||||
void (* MspInitCallback)(struct __DCACHE_HandleTypeDef *hdcache);
|
||||
void (* MspDeInitCallback)(struct __DCACHE_HandleTypeDef *hdcache);
|
||||
|
||||
__IO HAL_DCACHE_StateTypeDef State;
|
||||
__IO uint32_t ErrorCode;
|
||||
} DCACHE_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DCACHE Callback pointer definition
|
||||
*/
|
||||
/*!< Pointer to a DCACHE common callback function */
|
||||
typedef void (*pDCACHE_CallbackTypeDef)(DCACHE_HandleTypeDef *hdcache);
|
||||
|
||||
/**
|
||||
* @brief HAL DCACHE Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DCACHE_CLEAN_BY_ADDRESS_CB_ID = 0x00U, /*!< DCACHE Clean By Address callback ID */
|
||||
HAL_DCACHE_INVALIDATE_BY_ADDRESS_CB_ID = 0x01U, /*!< DCACHE Invalidate By Address callback ID */
|
||||
HAL_DCACHE_CLEAN_AND_INVALIDATE_BY_ADDRESS_CB_ID = 0x02U, /*!< DCACHE Clean And Invalidate By Address callback ID */
|
||||
HAL_DCACHE_INVALIDATE_COMPLETE_CB_ID = 0x03U, /*!< DCACHE Invalidate Complete ID */
|
||||
HAL_DCACHE_ERROR_CB_ID = 0x04U, /*!< DCACHE Error callback ID */
|
||||
|
||||
HAL_DCACHE_MSPINIT_CB_ID = 0x05U, /*!< DCACHE Msp Init callback ID */
|
||||
HAL_DCACHE_MSPDEINIT_CB_ID = 0x06U /*!< DCACHE Msp DeInit callback ID */
|
||||
} HAL_DCACHE_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants -------------------------------------------------------*/
|
||||
/** @defgroup DCACHE_Exported_Constants DCACHE Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DCACHE_Error_Code DCACHE Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DCACHE_ERROR_NONE 0x00000000U /*!< No error */
|
||||
#define HAL_DCACHE_ERROR_TIMEOUT 0x00000010U /*!< Timeout error */
|
||||
#define HAL_DCACHE_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid callback error */
|
||||
#define HAL_DCACHE_ERROR_EVICTION_CLEAN 0x00000040U /*!< Eviction or clean operation write-back error */
|
||||
#define HAL_DCACHE_ERROR_INVALID_OPERATION 0x00000080U /*!< Invalid operation */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCACHE_Monitor_Type Monitor type
|
||||
* @{
|
||||
*/
|
||||
#define DCACHE_MONITOR_READ_HIT DCACHE_CR_RHITMEN /*!< Read Hit monitoring */
|
||||
#define DCACHE_MONITOR_READ_MISS DCACHE_CR_RMISSMEN /*!< Read Miss monitoring */
|
||||
#define DCACHE_MONITOR_WRITE_HIT DCACHE_CR_WHITMEN /*!< Write Hit monitoring */
|
||||
#define DCACHE_MONITOR_WRITE_MISS DCACHE_CR_WMISSMEN /*!< Write Miss monitoring */
|
||||
#define DCACHE_MONITOR_ALL (DCACHE_CR_RHITMEN | DCACHE_CR_RMISSMEN | \
|
||||
DCACHE_CR_WHITMEN | DCACHE_CR_WMISSMEN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCACHE_Read_Burst_Type Remapped Output burst type
|
||||
* @{
|
||||
*/
|
||||
#define DCACHE_READ_BURST_WRAP 0U /*!< WRAP */
|
||||
#define DCACHE_READ_BURST_INCR DCACHE_CR_HBURST /*!< INCR */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCACHE_Interrupts Interrupts
|
||||
* @{
|
||||
*/
|
||||
#define DCACHE_IT_BUSYEND DCACHE_IER_BSYENDIE /*!< Busy end interrupt */
|
||||
#define DCACHE_IT_ERROR DCACHE_IER_ERRIE /*!< Cache error interrupt */
|
||||
#define DCACHE_IT_CMDEND DCACHE_IER_CMDENDIE /*!< Command end interrupt */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCACHE_Flags Flags
|
||||
* @{
|
||||
*/
|
||||
#define DCACHE_FLAG_BUSY DCACHE_SR_BUSYF /*!< Busy flag */
|
||||
#define DCACHE_FLAG_BUSYEND DCACHE_SR_BSYENDF /*!< Busy end flag */
|
||||
#define DCACHE_FLAG_ERROR DCACHE_SR_ERRF /*!< Cache error flag */
|
||||
#define DCACHE_FLAG_BUSYCMD DCACHE_SR_BUSYCMDF /*!< Busy command flag */
|
||||
#define DCACHE_FLAG_CMDEND DCACHE_SR_CMDENDF /*!< Command end flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros ----------------------------------------------------------*/
|
||||
/** @defgroup DCACHE_Exported_Macros DCACHE Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Enable DCACHE interrupts.
|
||||
* @param __HANDLE__ specifies the DCACHE handle.
|
||||
* @param __INTERRUPT__ specifies the DCACHE interrupt sources to be enabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref DCACHE_IT_BUSYEND Busy end interrupt
|
||||
* @arg @ref DCACHE_IT_ERROR Cache error interrupt
|
||||
* @arg @ref DCACHE_IT_CMDEND Cache Command end interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DCACHE_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))
|
||||
|
||||
/** @brief Disable DCACHE interrupts.
|
||||
* @param __HANDLE__ specifies the DCACHE handle.
|
||||
* @param __INTERRUPT__ specifies the DCACHE interrupt sources to be disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref DCACHE_IT_BUSYEND Busy end interrupt
|
||||
* @arg @ref DCACHE_IT_ERROR Cache error interrupt
|
||||
* @arg @ref DCACHE_IT_CMDEND Cache Command end interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DCACHE_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))
|
||||
|
||||
/** @brief Check whether the specified DCACHE interrupt source is enabled or not.
|
||||
* @param __HANDLE__ specifies the DCACHE handle.
|
||||
* @param __INTERRUPT__ specifies the DCACHE interrupt source to check.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref DCACHE_IT_BUSYEND Busy end interrupt
|
||||
* @arg @ref DCACHE_IT_ERROR Cache error interrupt
|
||||
* @arg @ref DCACHE_IT_CMDEND Cache Command end interrupt
|
||||
*
|
||||
* @retval The state of __INTERRUPT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_DCACHE_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
|
||||
((READ_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the selected DCACHE flag is set or not.
|
||||
* @param __HANDLE__ specifies the DCACHE handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref DCACHE_FLAG_BUSY Busy flag
|
||||
* @arg @ref DCACHE_FLAG_BUSYEND Busy end flag
|
||||
* @arg @ref DCACHE_FLAG_ERROR Cache error flag
|
||||
* @arg @ref DCACHE_FLAG_BUSYCMD Cache Busy command flag
|
||||
* @arg @ref DCACHE_FLAG_CMDEND Cache command end flag
|
||||
* @retval The state of __FLAG__ (0 or 1).
|
||||
*/
|
||||
#define __HAL_DCACHE_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? 1U : 0U)
|
||||
|
||||
/** @brief Clear the selected DCACHE flags.
|
||||
* @param __HANDLE__ specifies the DCACHE handle.
|
||||
* @param __FLAG__ specifies the DCACHE flags to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref DCACHE_FLAG_BUSYEND Busy end flag
|
||||
* @arg @ref DCACHE_FLAG_ERROR Cache error flag
|
||||
* @arg @ref DCACHE_FLAG_CMDEND Cache command end flag
|
||||
*/
|
||||
#define __HAL_DCACHE_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions -------------------------------------------------------*/
|
||||
/** @defgroup DCACHE_Exported_Functions DCACHE Exported Functions
|
||||
* @brief DCACHE Exported functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DCACHE_Exported_Functions_Group1 Initialization and De-Initialization Functions
|
||||
* @brief Initialization and De-Initialization Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DCACHE_Init(DCACHE_HandleTypeDef *hdcache);
|
||||
HAL_StatusTypeDef HAL_DCACHE_DeInit(DCACHE_HandleTypeDef *hdcache);
|
||||
void HAL_DCACHE_MspInit(DCACHE_HandleTypeDef *hdcache);
|
||||
void HAL_DCACHE_MspDeInit(DCACHE_HandleTypeDef *hdcache);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCACHE_Exported_Functions_Group2 I/O Operation Functions
|
||||
* @brief I/O Operation Functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***/
|
||||
HAL_StatusTypeDef HAL_DCACHE_Enable(DCACHE_HandleTypeDef *hdcache);
|
||||
HAL_StatusTypeDef HAL_DCACHE_Disable(DCACHE_HandleTypeDef *hdcache);
|
||||
uint32_t HAL_DCACHE_IsEnabled(const DCACHE_HandleTypeDef *hdcache);
|
||||
HAL_StatusTypeDef HAL_DCACHE_SetReadBurstType(DCACHE_HandleTypeDef *hdcache, uint32_t ReadBurstType);
|
||||
|
||||
/*** Cache maintenance in blocking mode (Polling) ***/
|
||||
HAL_StatusTypeDef HAL_DCACHE_Invalidate(DCACHE_HandleTypeDef *hdcache);
|
||||
HAL_StatusTypeDef HAL_DCACHE_InvalidateByAddr(DCACHE_HandleTypeDef *hdcache, const uint32_t *const pAddr,
|
||||
uint32_t dSize);
|
||||
HAL_StatusTypeDef HAL_DCACHE_CleanByAddr(DCACHE_HandleTypeDef *hdcache, const uint32_t *const pAddr, uint32_t dSize);
|
||||
HAL_StatusTypeDef HAL_DCACHE_CleanInvalidByAddr(DCACHE_HandleTypeDef *hdcache, const uint32_t *const pAddr,
|
||||
uint32_t dSize);
|
||||
|
||||
/*** Cache maintenance in non-blocking mode (Interrupt) ***/
|
||||
HAL_StatusTypeDef HAL_DCACHE_Invalidate_IT(DCACHE_HandleTypeDef *hdcache);
|
||||
HAL_StatusTypeDef HAL_DCACHE_InvalidateByAddr_IT(DCACHE_HandleTypeDef *hdcache, const uint32_t *const pAddr,
|
||||
uint32_t dSize);
|
||||
HAL_StatusTypeDef HAL_DCACHE_CleanByAddr_IT(DCACHE_HandleTypeDef *hdcache, const uint32_t *const pAddr,
|
||||
uint32_t dSize);
|
||||
HAL_StatusTypeDef HAL_DCACHE_CleanInvalidByAddr_IT(DCACHE_HandleTypeDef *hdcache, const uint32_t *const pAddr,
|
||||
uint32_t dSize);
|
||||
|
||||
/*** IRQHandler and Callbacks ***/
|
||||
void HAL_DCACHE_IRQHandler(DCACHE_HandleTypeDef *hdcache);
|
||||
void HAL_DCACHE_ErrorCallback(DCACHE_HandleTypeDef *hdcache);
|
||||
void HAL_DCACHE_CleanByAddrCallback(DCACHE_HandleTypeDef *hdcache);
|
||||
void HAL_DCACHE_InvalidateByAddrCallback(DCACHE_HandleTypeDef *hdcache);
|
||||
void HAL_DCACHE_InvalidateCompleteCallback(DCACHE_HandleTypeDef *hdcache);
|
||||
void HAL_DCACHE_CleanAndInvalidateByAddrCallback(DCACHE_HandleTypeDef *hdcache);
|
||||
|
||||
/* Callbacks Register/UnRegister functions ***/
|
||||
HAL_StatusTypeDef HAL_DCACHE_RegisterCallback(DCACHE_HandleTypeDef *hdcache, HAL_DCACHE_CallbackIDTypeDef CallbackID,
|
||||
pDCACHE_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_DCACHE_UnRegisterCallback(DCACHE_HandleTypeDef *hdcache, HAL_DCACHE_CallbackIDTypeDef CallbackID);
|
||||
|
||||
/*** Performance instruction cache monitoring functions ***/
|
||||
uint32_t HAL_DCACHE_Monitor_GetReadHitValue(const DCACHE_HandleTypeDef *hdcache);
|
||||
uint32_t HAL_DCACHE_Monitor_GetReadMissValue(const DCACHE_HandleTypeDef *hdcache);
|
||||
uint32_t HAL_DCACHE_Monitor_GetWriteHitValue(const DCACHE_HandleTypeDef *hdcache);
|
||||
uint32_t HAL_DCACHE_Monitor_GetWriteMissValue(const DCACHE_HandleTypeDef *hdcache);
|
||||
HAL_StatusTypeDef HAL_DCACHE_Monitor_Reset(DCACHE_HandleTypeDef *hdcache, uint32_t MonitorType);
|
||||
HAL_StatusTypeDef HAL_DCACHE_Monitor_Start(DCACHE_HandleTypeDef *hdcache, uint32_t MonitorType);
|
||||
HAL_StatusTypeDef HAL_DCACHE_Monitor_Stop(DCACHE_HandleTypeDef *hdcache, uint32_t MonitorType);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCACHE_Exported_Functions_Group3 State and Error Functions
|
||||
* @brief State and Error Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_DCACHE_StateTypeDef HAL_DCACHE_GetState(const DCACHE_HandleTypeDef *hdcache);
|
||||
uint32_t HAL_DCACHE_GetError(const DCACHE_HandleTypeDef *hdcache);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* DCACHE1 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H5xx_HAL_DCACHE_H */
|
||||
|
|
@ -0,0 +1,698 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h5xx_hal_dcmi.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of DCMI HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H5xx_HAL_DCMI_H
|
||||
#define STM32H5xx_HAL_DCMI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h5xx_hal_def.h"
|
||||
|
||||
#if defined (DCMI)
|
||||
|
||||
/** @addtogroup STM32H5xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DCMI DCMI
|
||||
* @brief DCMI HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup DCMI_Exported_Types DCMI Exported Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief HAL DCMI State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DCMI_STATE_RESET = 0x00U, /*!< DCMI not yet initialized or disabled */
|
||||
HAL_DCMI_STATE_READY = 0x01U, /*!< DCMI initialized and ready for use */
|
||||
HAL_DCMI_STATE_BUSY = 0x02U, /*!< DCMI internal processing is ongoing */
|
||||
HAL_DCMI_STATE_TIMEOUT = 0x03U, /*!< DCMI timeout state */
|
||||
HAL_DCMI_STATE_ERROR = 0x04U, /*!< DCMI error state */
|
||||
HAL_DCMI_STATE_SUSPENDED = 0x05U /*!< DCMI suspend state */
|
||||
} HAL_DCMI_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DCMI Embedded Synchronisation CODE Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t FrameStartCode; /*!< Specifies the code of the frame start delimiter. */
|
||||
uint8_t LineStartCode; /*!< Specifies the code of the line start delimiter. */
|
||||
uint8_t LineEndCode; /*!< Specifies the code of the line end delimiter. */
|
||||
uint8_t FrameEndCode; /*!< Specifies the code of the frame end delimiter. */
|
||||
} DCMI_CodesInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DCMI Embedded Synchronisation UNMASK Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t FrameStartUnmask; /*!< Specifies the frame start delimiter unmask. */
|
||||
uint8_t LineStartUnmask; /*!< Specifies the line start delimiter unmask. */
|
||||
uint8_t LineEndUnmask; /*!< Specifies the line end delimiter unmask. */
|
||||
uint8_t FrameEndUnmask; /*!< Specifies the frame end delimiter unmask. */
|
||||
} DCMI_SyncUnmaskTypeDef;
|
||||
/**
|
||||
* @brief DCMI Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SynchroMode; /*!< Specifies the Synchronization Mode: Hardware or Embedded.
|
||||
This parameter can be a value of @ref DCMI_Synchronization_Mode */
|
||||
|
||||
uint32_t PCKPolarity; /*!< Specifies the Pixel clock polarity: Falling or Rising.
|
||||
This parameter can be a value of @ref DCMI_PIXCK_Polarity */
|
||||
|
||||
uint32_t VSPolarity; /*!< Specifies the Vertical synchronization polarity: High or Low.
|
||||
This parameter can be a value of @ref DCMI_VSYNC_Polarity */
|
||||
|
||||
uint32_t HSPolarity; /*!< Specifies the Horizontal synchronization polarity: High or Low.
|
||||
This parameter can be a value of @ref DCMI_HSYNC_Polarity */
|
||||
|
||||
uint32_t CaptureRate; /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4.
|
||||
This parameter can be a value of @ref DCMI_Capture_Rate */
|
||||
|
||||
uint32_t ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit.
|
||||
This parameter can be a value of @ref DCMI_Extended_Data_Mode */
|
||||
|
||||
DCMI_CodesInitTypeDef SyncroCode; /*!< Specifies the code of the line/frame start delimiter and the
|
||||
line/frame end delimiter */
|
||||
|
||||
uint32_t JPEGMode; /*!< Enable or Disable the JPEG mode.
|
||||
This parameter can be a value of @ref DCMI_MODE_JPEG */
|
||||
|
||||
uint32_t ByteSelectMode; /*!< Specifies the data to be captured by the interface
|
||||
This parameter can be a value of @ref DCMI_Byte_Select_Mode */
|
||||
|
||||
uint32_t ByteSelectStart; /*!< Specifies if the data to be captured by the interface is even or odd
|
||||
This parameter can be a value of @ref DCMI_Byte_Select_Start */
|
||||
|
||||
uint32_t LineSelectMode; /*!< Specifies the line of data to be captured by the interface
|
||||
This parameter can be a value of @ref DCMI_Line_Select_Mode */
|
||||
|
||||
uint32_t LineSelectStart; /*!< Specifies if the line of data to be captured by the interface is even or odd
|
||||
This parameter can be a value of @ref DCMI_Line_Select_Start */
|
||||
} DCMI_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DCMI handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __DCMI_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
|
||||
{
|
||||
DCMI_TypeDef *Instance; /*!< DCMI Register base address */
|
||||
|
||||
DCMI_InitTypeDef Init; /*!< DCMI parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< DCMI locking object */
|
||||
|
||||
__IO HAL_DCMI_StateTypeDef State; /*!< DCMI state */
|
||||
|
||||
__IO uint32_t XferCount; /*!< DMA transfer counter */
|
||||
|
||||
__IO uint32_t XferSize; /*!< DMA transfer size */
|
||||
|
||||
uint32_t XferTransferNumber; /*!< DMA transfer number */
|
||||
|
||||
uint32_t pBuffPtr; /*!< Pointer to DMA output buffer */
|
||||
|
||||
DMA_HandleTypeDef *DMA_Handle; /*!< Pointer to the DMA handler */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< DCMI Error code */
|
||||
|
||||
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
|
||||
void (* FrameEventCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Frame Event Callback */
|
||||
void (* VsyncEventCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Vsync Event Callback */
|
||||
void (* LineEventCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Line Event Callback */
|
||||
void (* ErrorCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Error Callback */
|
||||
void (* MspInitCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Msp DeInit callback */
|
||||
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
|
||||
} DCMI_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL DCMI Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DCMI_FRAME_EVENT_CB_ID = 0x00U, /*!< DCMI Frame Event Callback ID */
|
||||
HAL_DCMI_VSYNC_EVENT_CB_ID = 0x01U, /*!< DCMI Vsync Event Callback ID */
|
||||
HAL_DCMI_LINE_EVENT_CB_ID = 0x02U, /*!< DCMI Line Event Callback ID */
|
||||
HAL_DCMI_ERROR_CB_ID = 0x03U, /*!< DCMI Error Callback ID */
|
||||
HAL_DCMI_MSPINIT_CB_ID = 0x04U, /*!< DCMI MspInit callback ID */
|
||||
HAL_DCMI_MSPDEINIT_CB_ID = 0x05U /*!< DCMI MspDeInit callback ID */
|
||||
|
||||
} HAL_DCMI_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DCMI Callback pointer definition
|
||||
*/
|
||||
typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi); /*!< pointer to a DCMI callback function */
|
||||
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DCMI_Exported_Constants DCMI Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_Error_Code DCMI Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DCMI_ERROR_NONE (0x00000000U) /*!< No error */
|
||||
#define HAL_DCMI_ERROR_OVR (0x00000001U) /*!< Overrun error */
|
||||
#define HAL_DCMI_ERROR_SYNC (0x00000002U) /*!< Synchronization error */
|
||||
#define HAL_DCMI_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
|
||||
#define HAL_DCMI_ERROR_DMA (0x00000040U) /*!< DMA error */
|
||||
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_DCMI_ERROR_INVALID_CALLBACK (0x00000080U) /*!< Invalid callback error */
|
||||
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_Capture_Mode DCMI Capture Mode
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_MODE_CONTINUOUS (0x00000000U) /*!< The received data are transferred continuously
|
||||
into the destination memory through the DMA */
|
||||
#define DCMI_MODE_SNAPSHOT ((uint32_t)DCMI_CR_CM) /*!< Once activated, the interface waits for the start of
|
||||
frame and then transfers a single frame
|
||||
through the DMA */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_Synchronization_Mode DCMI Synchronization Mode
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_SYNCHRO_HARDWARE (0x00000000U) /*!< Hardware synchronization data capture (frame/line start/stop)
|
||||
is synchronized with the HSYNC/VSYNC signals */
|
||||
#define DCMI_SYNCHRO_EMBEDDED ((uint32_t)DCMI_CR_ESS) /*!< Embedded synchronization data capture is synchronized
|
||||
with synchronization codes embedded in the data flow */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_PIXCK_Polarity DCMI PIXCK Polarity
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_PCKPOLARITY_FALLING (0x00000000U) /*!< Pixel clock active on Falling edge */
|
||||
#define DCMI_PCKPOLARITY_RISING ((uint32_t)DCMI_CR_PCKPOL) /*!< Pixel clock active on Rising edge */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_VSYNC_Polarity DCMI VSYNC Polarity
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_VSPOLARITY_LOW (0x00000000U) /*!< Vertical synchronization active Low */
|
||||
#define DCMI_VSPOLARITY_HIGH ((uint32_t)DCMI_CR_VSPOL) /*!< Vertical synchronization active High */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_HSYNC_Polarity DCMI HSYNC Polarity
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_HSPOLARITY_LOW (0x00000000U) /*!< Horizontal synchronization active Low */
|
||||
#define DCMI_HSPOLARITY_HIGH ((uint32_t)DCMI_CR_HSPOL) /*!< Horizontal synchronization active High */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_MODE_JPEG DCMI MODE JPEG
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_JPEG_DISABLE (0x00000000U) /*!< Mode JPEG Disabled */
|
||||
#define DCMI_JPEG_ENABLE ((uint32_t)DCMI_CR_JPEG) /*!< Mode JPEG Enabled */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_Capture_Rate DCMI Capture Rate
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_CR_ALL_FRAME (0x00000000U) /*!< All frames are captured */
|
||||
#define DCMI_CR_ALTERNATE_2_FRAME ((uint32_t)DCMI_CR_FCRC_0) /*!< Every alternate frame captured */
|
||||
#define DCMI_CR_ALTERNATE_4_FRAME ((uint32_t)DCMI_CR_FCRC_1) /*!< One frame in 4 frames captured */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_Extended_Data_Mode DCMI Extended Data Mode
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_EXTEND_DATA_8B (0x00000000U) /*!< Interface captures 8-bit data on every pixel clock */
|
||||
#define DCMI_EXTEND_DATA_10B ((uint32_t)DCMI_CR_EDM_0) /*!< Interface captures 10-bit data on every pixel clock */
|
||||
#define DCMI_EXTEND_DATA_12B ((uint32_t)DCMI_CR_EDM_1) /*!< Interface captures 12-bit data on every pixel clock */
|
||||
#define DCMI_EXTEND_DATA_14B ((uint32_t)(DCMI_CR_EDM_0 |\
|
||||
DCMI_CR_EDM_1)) /*!< Interface captures 14-bit data on every pixel clock */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_Window_Coordinate DCMI Window Coordinate
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_WINDOW_COORDINATE (0x3FFFU) /*!< Window coordinate */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_Window_Height DCMI Window Height
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_WINDOW_HEIGHT (0x1FFFU) /*!< Window Height */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_interrupt_sources DCMI interrupt sources
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_IT_FRAME ((uint32_t)DCMI_IER_FRAME_IE) /*!< Capture complete interrupt */
|
||||
#define DCMI_IT_OVR ((uint32_t)DCMI_IER_OVR_IE) /*!< Overrun interrupt */
|
||||
#define DCMI_IT_ERR ((uint32_t)DCMI_IER_ERR_IE) /*!< Synchronization error interrupt */
|
||||
#define DCMI_IT_VSYNC ((uint32_t)DCMI_IER_VSYNC_IE) /*!< VSYNC interrupt */
|
||||
#define DCMI_IT_LINE ((uint32_t)DCMI_IER_LINE_IE) /*!< Line interrupt */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_Flags DCMI Flags
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief DCMI SR register
|
||||
*/
|
||||
#define DCMI_FLAG_HSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_HSYNC) /*!< HSYNC pin state (active line / synchronization
|
||||
between lines) */
|
||||
#define DCMI_FLAG_VSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_VSYNC) /*!< VSYNC pin state (active frame / synchronization
|
||||
between frames) */
|
||||
#define DCMI_FLAG_FNE ((uint32_t)DCMI_SR_INDEX|DCMI_SR_FNE) /*!< FIFO not empty flag */
|
||||
/**
|
||||
* @brief DCMI RIS register
|
||||
*/
|
||||
#define DCMI_FLAG_FRAMERI ((uint32_t)DCMI_RIS_FRAME_RIS) /*!< Frame capture complete interrupt flag */
|
||||
#define DCMI_FLAG_OVRRI ((uint32_t)DCMI_RIS_OVR_RIS) /*!< Overrun interrupt flag */
|
||||
#define DCMI_FLAG_ERRRI ((uint32_t)DCMI_RIS_ERR_RIS) /*!< Synchronization error interrupt flag */
|
||||
#define DCMI_FLAG_VSYNCRI ((uint32_t)DCMI_RIS_VSYNC_RIS) /*!< VSYNC interrupt flag */
|
||||
#define DCMI_FLAG_LINERI ((uint32_t)DCMI_RIS_LINE_RIS) /*!< Line interrupt flag */
|
||||
/**
|
||||
* @brief DCMI MIS register
|
||||
*/
|
||||
#define DCMI_FLAG_FRAMEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_FRAME_MIS) /*!< DCMI Frame capture complete masked
|
||||
interrupt status */
|
||||
#define DCMI_FLAG_OVRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_OVR_MIS ) /*!< DCMI Overrun masked interrupt status */
|
||||
#define DCMI_FLAG_ERRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_ERR_MIS ) /*!< DCMI Synchronization error masked interrupt status */
|
||||
#define DCMI_FLAG_VSYNCMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_VSYNC_MIS) /*!< DCMI VSYNC masked interrupt status */
|
||||
#define DCMI_FLAG_LINEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_LINE_MIS ) /*!< DCMI Line masked interrupt status */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_Byte_Select_Mode DCMI Byte Select Mode
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_BSM_ALL (0x00000000U) /*!< Interface captures all received data */
|
||||
#define DCMI_BSM_OTHER ((uint32_t)DCMI_CR_BSM_0) /*!< Interface captures every other byte
|
||||
from the received data */
|
||||
#define DCMI_BSM_ALTERNATE_4 ((uint32_t)DCMI_CR_BSM_1) /*!< Interface captures one byte out of four */
|
||||
#define DCMI_BSM_ALTERNATE_2 ((uint32_t)(DCMI_CR_BSM_0 |\
|
||||
DCMI_CR_BSM_1)) /*!< Interface captures two bytes out of four */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_Byte_Select_Start DCMI Byte Select Start
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_OEBS_ODD (0x00000000U) /*!< Interface captures first data from the frame/line start,
|
||||
second one being dropped */
|
||||
#define DCMI_OEBS_EVEN ((uint32_t)DCMI_CR_OEBS) /*!< Interface captures second data from
|
||||
the frame/line start, first one being dropped */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_Line_Select_Mode DCMI Line Select Mode
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_LSM_ALL (0x00000000U) /*!< Interface captures all received lines */
|
||||
#define DCMI_LSM_ALTERNATE_2 ((uint32_t)DCMI_CR_LSM) /*!< Interface captures one line out of two */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_Line_Select_Start DCMI Line Select Start
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_OELS_ODD (0x00000000U) /*!< Interface captures first line from the frame start,
|
||||
second one being dropped */
|
||||
#define DCMI_OELS_EVEN ((uint32_t)DCMI_CR_OELS) /*!< Interface captures second line from the frame start,
|
||||
first one being dropped */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup DCMI_Exported_Macros DCMI Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset DCMI handle state
|
||||
* @param __HANDLE__ specifies the DCMI handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_DCMI_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET)
|
||||
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @brief Enable the DCMI.
|
||||
* @param __HANDLE__ DCMI handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DCMI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DCMI_CR_ENABLE)
|
||||
|
||||
/**
|
||||
* @brief Disable the DCMI.
|
||||
* @param __HANDLE__ DCMI handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DCMI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(DCMI_CR_ENABLE))
|
||||
|
||||
/* Interrupt & Flag management */
|
||||
/**
|
||||
* @brief Get the DCMI pending flag.
|
||||
* @param __HANDLE__ DCMI handle
|
||||
* @param __FLAG__ Get the specified flag.
|
||||
* This parameter can be one of the following values (no combination allowed)
|
||||
* @arg DCMI_FLAG_HSYNC: HSYNC pin state (active line / synchronization between lines)
|
||||
* @arg DCMI_FLAG_VSYNC: VSYNC pin state (active frame / synchronization between frames)
|
||||
* @arg DCMI_FLAG_FNE: FIFO empty flag
|
||||
* @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask
|
||||
* @arg DCMI_FLAG_OVRRI: Overrun flag mask
|
||||
* @arg DCMI_FLAG_ERRRI: Synchronization error flag mask
|
||||
* @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask
|
||||
* @arg DCMI_FLAG_LINERI: Line flag mask
|
||||
* @arg DCMI_FLAG_FRAMEMI: DCMI Capture complete masked interrupt status
|
||||
* @arg DCMI_FLAG_OVRMI: DCMI Overrun masked interrupt status
|
||||
* @arg DCMI_FLAG_ERRMI: DCMI Synchronization error masked interrupt status
|
||||
* @arg DCMI_FLAG_VSYNCMI: DCMI VSYNC masked interrupt status
|
||||
* @arg DCMI_FLAG_LINEMI: DCMI Line masked interrupt status
|
||||
* @retval The state of FLAG.
|
||||
*/
|
||||
#define __HAL_DCMI_GET_FLAG(__HANDLE__, __FLAG__)\
|
||||
((((__FLAG__) & (DCMI_SR_INDEX|DCMI_MIS_INDEX)) == 0x0)? ((__HANDLE__)->Instance->RIS & (__FLAG__)) :\
|
||||
(((__FLAG__) & DCMI_SR_INDEX) == 0x0)? ((__HANDLE__)->Instance->MIS & (__FLAG__)) :\
|
||||
((__HANDLE__)->Instance->SR & (__FLAG__)))
|
||||
|
||||
/**
|
||||
* @brief Clear the DCMI pending flags.
|
||||
* @param __HANDLE__ DCMI handle
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask
|
||||
* @arg DCMI_FLAG_OVFRI: Overflow flag mask
|
||||
* @arg DCMI_FLAG_ERRRI: Synchronization error flag mask
|
||||
* @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask
|
||||
* @arg DCMI_FLAG_LINERI: Line flag mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DCMI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Enable the specified DCMI interrupts.
|
||||
* @param __HANDLE__ DCMI handle
|
||||
* @param __INTERRUPT__ specifies the DCMI interrupt sources to be enabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
|
||||
* @arg DCMI_IT_OVF: Overflow interrupt mask
|
||||
* @arg DCMI_IT_ERR: Synchronization error interrupt mask
|
||||
* @arg DCMI_IT_VSYNC: VSYNC interrupt mask
|
||||
* @arg DCMI_IT_LINE: Line interrupt mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DCMI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the specified DCMI interrupts.
|
||||
* @param __HANDLE__ DCMI handle
|
||||
* @param __INTERRUPT__ specifies the DCMI interrupt sources to be enabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
|
||||
* @arg DCMI_IT_OVF: Overflow interrupt mask
|
||||
* @arg DCMI_IT_ERR: Synchronization error interrupt mask
|
||||
* @arg DCMI_IT_VSYNC: VSYNC interrupt mask
|
||||
* @arg DCMI_IT_LINE: Line interrupt mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DCMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified DCMI interrupt has occurred or not.
|
||||
* @param __HANDLE__ DCMI handle
|
||||
* @param __INTERRUPT__ specifies the DCMI interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
|
||||
* @arg DCMI_IT_OVF: Overflow interrupt mask
|
||||
* @arg DCMI_IT_ERR: Synchronization error interrupt mask
|
||||
* @arg DCMI_IT_VSYNC: VSYNC interrupt mask
|
||||
* @arg DCMI_IT_LINE: Line interrupt mask
|
||||
* @retval The state of INTERRUPT.
|
||||
*/
|
||||
#define __HAL_DCMI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MISR & (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup DCMI_Exported_Functions DCMI Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi);
|
||||
HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi);
|
||||
void HAL_DCMI_MspInit(DCMI_HandleTypeDef *hdcmi);
|
||||
void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef *hdcmi);
|
||||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID,
|
||||
pDCMI_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DCMI_Exported_Functions_Group2 IO operation functions
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef *hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length);
|
||||
HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef *hdcmi);
|
||||
HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef *hdcmi);
|
||||
HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef *hdcmi);
|
||||
void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi);
|
||||
void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi);
|
||||
void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi);
|
||||
void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi);
|
||||
void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DCMI_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize,
|
||||
uint32_t YSize);
|
||||
HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi);
|
||||
HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi);
|
||||
HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_SyncUnmaskTypeDef *SyncUnmask);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DCMI_Exported_Functions_Group4 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions *************************************************/
|
||||
HAL_DCMI_StateTypeDef HAL_DCMI_GetState(const DCMI_HandleTypeDef *hdcmi);
|
||||
uint32_t HAL_DCMI_GetError(const DCMI_HandleTypeDef *hdcmi);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup DCMI_Private_Constants DCMI Private Constants
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup DCMI_MIS_INDEX DCMI Mis Index
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_MIS_INDEX ((uint32_t)0x1000) /*!< DCMI MIS register index */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_SR_INDEX DCMI SR Index
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_SR_INDEX ((uint32_t)0x2000) /*!< DCMI SR register index */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/** @defgroup DCMI_Private_Macros DCMI Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_MODE_CONTINUOUS) || \
|
||||
((MODE) == DCMI_MODE_SNAPSHOT))
|
||||
|
||||
#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SYNCHRO_HARDWARE) || \
|
||||
((MODE) == DCMI_SYNCHRO_EMBEDDED))
|
||||
|
||||
#define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPOLARITY_FALLING) || \
|
||||
((POLARITY) == DCMI_PCKPOLARITY_RISING))
|
||||
|
||||
#define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPOLARITY_LOW) || \
|
||||
((POLARITY) == DCMI_VSPOLARITY_HIGH))
|
||||
|
||||
#define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPOLARITY_LOW) || \
|
||||
((POLARITY) == DCMI_HSPOLARITY_HIGH))
|
||||
|
||||
#define IS_DCMI_MODE_JPEG(JPEG_MODE)(((JPEG_MODE) == DCMI_JPEG_DISABLE) || \
|
||||
((JPEG_MODE) == DCMI_JPEG_ENABLE))
|
||||
|
||||
#define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CR_ALL_FRAME) || \
|
||||
((RATE) == DCMI_CR_ALTERNATE_2_FRAME) || \
|
||||
((RATE) == DCMI_CR_ALTERNATE_4_FRAME))
|
||||
|
||||
#define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_EXTEND_DATA_8B) || \
|
||||
((DATA) == DCMI_EXTEND_DATA_10B) || \
|
||||
((DATA) == DCMI_EXTEND_DATA_12B) || \
|
||||
((DATA) == DCMI_EXTEND_DATA_14B))
|
||||
|
||||
#define IS_DCMI_WINDOW_COORDINATE(COORDINATE) ((COORDINATE) <= DCMI_WINDOW_COORDINATE)
|
||||
|
||||
#define IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT)
|
||||
|
||||
#define IS_DCMI_BYTE_SELECT_MODE(MODE)(((MODE) == DCMI_BSM_ALL) || \
|
||||
((MODE) == DCMI_BSM_OTHER) || \
|
||||
((MODE) == DCMI_BSM_ALTERNATE_4) || \
|
||||
((MODE) == DCMI_BSM_ALTERNATE_2))
|
||||
|
||||
#define IS_DCMI_BYTE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OEBS_ODD) || \
|
||||
((POLARITY) == DCMI_OEBS_EVEN))
|
||||
|
||||
#define IS_DCMI_LINE_SELECT_MODE(MODE)(((MODE) == DCMI_LSM_ALL) || \
|
||||
((MODE) == DCMI_LSM_ALTERNATE_2))
|
||||
|
||||
#define IS_DCMI_LINE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OELS_ODD) || \
|
||||
((POLARITY) == DCMI_OELS_EVEN))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @addtogroup DCMI_Private_Functions DCMI Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* DCMI */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H5xx_HAL_DCMI_H */
|
||||
|
|
@ -0,0 +1,231 @@
|
|||
/**
|
||||
**********************************************************************************************************************
|
||||
* @file stm32h5xx_hal_def.h
|
||||
* @author MCD Application Team
|
||||
* @brief This file contains HAL common defines, enumeration, macros and
|
||||
* structures definitions.
|
||||
**********************************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
**********************************************************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/
|
||||
#ifndef __STM32H5xx_HAL_DEF
|
||||
#define __STM32H5xx_HAL_DEF
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/* Includes ----------------------------------------------------------------------------------------------------------*/
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
#include <arm_cmse.h>
|
||||
#endif /* __ARM_FEATURE_CMSE */
|
||||
|
||||
#include "stm32h5xx.h"
|
||||
#include "Legacy/stm32_hal_legacy.h" /* Aliases file for old names compatibility */
|
||||
#include <stddef.h>
|
||||
#include <math.h>
|
||||
|
||||
/* Exported types ----------------------------------------------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief HAL Status structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_OK = 0x00,
|
||||
HAL_ERROR = 0x01,
|
||||
HAL_BUSY = 0x02,
|
||||
HAL_TIMEOUT = 0x03
|
||||
} HAL_StatusTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL Lock structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_UNLOCKED = 0x00,
|
||||
HAL_LOCKED = 0x01
|
||||
} HAL_LockTypeDef;
|
||||
|
||||
/* Exported macros ---------------------------------------------------------------------------------------------------*/
|
||||
|
||||
#define HAL_MAX_DELAY 0xFFFFFFFFU
|
||||
#define ARMCC_MIN_VERSION 6010050
|
||||
|
||||
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT))
|
||||
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
|
||||
|
||||
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
|
||||
do{ \
|
||||
(__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
|
||||
(__DMA_HANDLE__).Parent = (__HANDLE__); \
|
||||
} while(0)
|
||||
|
||||
#if !defined(UNUSED)
|
||||
#define UNUSED(x) ((void)(x))
|
||||
#endif /* UNUSED */
|
||||
|
||||
/** @brief Reset the Handle's State field.
|
||||
* @param __HANDLE__: specifies the Peripheral Handle.
|
||||
* @note This macro can be used for the following purpose:
|
||||
* - When the Handle is declared as local variable; before passing it as parameter
|
||||
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro
|
||||
* to set to 0 the Handle's "State" field.
|
||||
* Otherwise, "State" field may have any random value and the first time the function
|
||||
* HAL_PPP_Init() is called, the low level hardware initialization will be missed
|
||||
* (i.e. HAL_PPP_MspInit() will not be executed).
|
||||
* - When there is a need to reconfigure the low level hardware: instead of calling
|
||||
* HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
|
||||
* In this later function, when the Handle's "State" field is set to 0, it will execute the function
|
||||
* HAL_PPP_MspInit() which will reconfigure the low level hardware.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
|
||||
|
||||
#if (USE_RTOS == 1)
|
||||
/* Reserved for future use */
|
||||
#error " USE_RTOS should be 0 in the current HAL release "
|
||||
#else
|
||||
#define __HAL_LOCK(__HANDLE__) \
|
||||
do{ \
|
||||
if((__HANDLE__)->Lock == HAL_LOCKED) \
|
||||
{ \
|
||||
return HAL_BUSY; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Lock = HAL_LOCKED; \
|
||||
} \
|
||||
}while (0)
|
||||
|
||||
#define __HAL_UNLOCK(__HANDLE__) \
|
||||
do{ \
|
||||
(__HANDLE__)->Lock = HAL_UNLOCKED; \
|
||||
}while (0)
|
||||
#endif /* USE_RTOS */
|
||||
|
||||
#if defined ( __GNUC__ )
|
||||
#ifndef __weak
|
||||
#define __weak __attribute__((weak))
|
||||
#endif /* __weak */
|
||||
#ifndef __packed
|
||||
#define __packed __attribute__((__packed__))
|
||||
#endif /* __packed */
|
||||
#endif /* __GNUC__ */
|
||||
|
||||
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= ARMCC_MIN_VERSION)
|
||||
#ifndef __weak
|
||||
#define __weak __WEAK
|
||||
#endif /* __weak */
|
||||
#ifndef __packed
|
||||
#define __packed __PACKED
|
||||
#endif /* __packed */
|
||||
#endif
|
||||
|
||||
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4"
|
||||
must be used instead */
|
||||
#if defined (__GNUC__) /* GNU Compiler */
|
||||
#ifndef __ALIGN_END
|
||||
#define __ALIGN_END __attribute__ ((aligned (4)))
|
||||
#endif /* __ALIGN_END */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#define __ALIGN_BEGIN
|
||||
#endif /* __ALIGN_BEGIN */
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= ARMCC_MIN_VERSION)
|
||||
#ifndef __ALIGN_END
|
||||
#define __ALIGN_END __ALIGNED(4)
|
||||
#endif /* __ALIGN_END */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#define __ALIGN_BEGIN
|
||||
#endif /* __ALIGN_BEGIN */
|
||||
#else
|
||||
#ifndef __ALIGN_END
|
||||
#define __ALIGN_END
|
||||
#endif /* __ALIGN_END */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#if defined (__CC_ARM) /* ARM Compiler */
|
||||
#define __ALIGN_BEGIN __align(4)
|
||||
#elif defined (__ICCARM__) /* IAR Compiler */
|
||||
#define __ALIGN_BEGIN
|
||||
#endif /* __CC_ARM */
|
||||
#endif /* __ALIGN_BEGIN */
|
||||
#endif /* __GNUC__ */
|
||||
|
||||
/* Macro to get variable aligned on 32-bytes,needed for cache maintenance purpose */
|
||||
#if defined (__GNUC__) /* GNU Compiler */
|
||||
#define ALIGN_32BYTES(buf) buf __attribute__ ((aligned (32)))
|
||||
#elif defined (__ICCARM__) /* IAR Compiler */
|
||||
#define ALIGN_32BYTES(buf) _Pragma("data_alignment=32") buf
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= ARMCC_MIN_VERSION)
|
||||
#define ALIGN_32BYTES(buf) __ALIGNED(32) buf
|
||||
#elif defined (__CC_ARM) /* ARM Compiler */
|
||||
#define ALIGN_32BYTES(buf) __align(32) buf
|
||||
#endif /* __GNUC__ */
|
||||
|
||||
/**
|
||||
* @brief __RAM_FUNC definition
|
||||
*/
|
||||
#if defined ( __CC_ARM ) || ((__ARMCC_VERSION) && (__ARMCC_VERSION >= ARMCC_MIN_VERSION))
|
||||
|
||||
/* ARM Compiler
|
||||
|
||||
RAM functions are defined using the toolchain options.
|
||||
Functions that are executed in RAM should reside in a separate source module.
|
||||
Using the 'Options for File' dialog you can simply change the 'Code / Const'
|
||||
area of a module to a memory space in physical RAM.
|
||||
Available memory areas are declared in the 'Target' tab of the 'Options for Target'
|
||||
dialog.
|
||||
*/
|
||||
#define __RAM_FUNC HAL_StatusTypeDef
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
/* ICCARM Compiler
|
||||
|
||||
RAM functions are defined using a specific toolchain keyword "__ramfunc".
|
||||
*/
|
||||
#define __RAM_FUNC __ramfunc HAL_StatusTypeDef
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
/* GNU Compiler
|
||||
|
||||
RAM functions are defined using a specific toolchain attribute
|
||||
"__attribute__((section(".RamFunc")))".
|
||||
*/
|
||||
#define __RAM_FUNC HAL_StatusTypeDef __attribute__((section(".RamFunc")))
|
||||
|
||||
#endif /* defined ( __CC_ARM ) || ((__ARMCC_VERSION) && (__ARMCC_VERSION >= ARMCC_MIN_VERSION)) */
|
||||
|
||||
/**
|
||||
* @brief __NOINLINE definition
|
||||
*/
|
||||
#if defined ( __CC_ARM ) || ((__ARMCC_VERSION) && (__ARMCC_VERSION >= ARMCC_MIN_VERSION)) || defined ( __GNUC__ )
|
||||
/* ARM & GNUCompiler
|
||||
|
||||
*/
|
||||
#define __NOINLINE __attribute__ ( (noinline) )
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
/* ICCARM Compiler
|
||||
|
||||
*/
|
||||
#define __NOINLINE _Pragma("optimize = no_inline")
|
||||
|
||||
#endif /* ( __CC_ARM ) || ((__ARMCC_VERSION) && (__ARMCC_VERSION >= ARMCC_MIN_VERSION)) || defined ( __GNUC__ ) */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* ___STM32H5xx_HAL_DEF */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,737 @@
|
|||
/**
|
||||
**********************************************************************************************************************
|
||||
* @file stm32h5xx_hal_dma_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of DMA HAL extension module.
|
||||
**********************************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
**********************************************************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/
|
||||
#ifndef STM32H5xx_HAL_DMA_EX_H
|
||||
#define STM32H5xx_HAL_DMA_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ----------------------------------------------------------------------------------------------------------*/
|
||||
#include "stm32h5xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H5xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMAEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ----------------------------------------------------------------------------------------------------*/
|
||||
/** @defgroup DMAEx_Exported_Types DMAEx Exported Types
|
||||
* @brief DMAEx Exported types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief DMAEx Data Handling Configuration Structure Definition.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DataExchange; /*!< Specifies the DMA channel data exchange mode.
|
||||
This parameter can be a value of @ref DMAEx_Data_Exchange */
|
||||
|
||||
uint32_t DataAlignment; /*!< Specifies the DMA channel data padding and alignment mode
|
||||
This parameter can be a value of @ref DMAEx_Data_Alignment */
|
||||
|
||||
} DMA_DataHandlingConfTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DMAEx Trigger Configuration Structure Definition.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t TriggerMode; /*!< Specifies the DMA channel trigger mode.
|
||||
This parameter can be a value of @ref DMAEx_Trigger_Mode */
|
||||
|
||||
uint32_t TriggerPolarity; /*!< Specifies the DMA channel trigger event polarity.
|
||||
This parameter can be a value of @ref DMAEx_Trigger_Polarity */
|
||||
|
||||
uint32_t TriggerSelection; /*!< Specifies the DMA channel trigger event selection.
|
||||
This parameter can be a value of @ref DMAEx_Trigger_Selection */
|
||||
|
||||
} DMA_TriggerConfTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DMAEx Repeated Block Configuration Structure Definition.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t RepeatCount; /*!< Specifies the DMA channel repeat count (the number of repetitions of block).
|
||||
This parameter can be a value between 1 and 2048 */
|
||||
|
||||
int32_t SrcAddrOffset; /*!< Specifies the DMA channel single/burst source address offset :
|
||||
This parameter can be a value between -8191 and 8191.
|
||||
* If source address offset > 0 => Increment the source address by offset from where
|
||||
the last single/burst transfer ends.
|
||||
* If source address offset < 0 => Decrement the source address by offset from where
|
||||
the last single/burst transfer ends.
|
||||
* If source address offset == 0 => The next single/burst source address starts from
|
||||
where the last transfer ends */
|
||||
|
||||
int32_t DestAddrOffset; /*!< Specifies the DMA channel single/burst destination address offset signed value :
|
||||
This parameter can be a value between -8191 and 8191.
|
||||
* If destination address offset > 0 => Increment the destination address by offset
|
||||
from where the last single/burst transfer ends.
|
||||
* If destination address offset < 0 => Decrement the destination address by offset
|
||||
from where the last single/burst transfer ends.
|
||||
* If destination address offset == 0 => The next single/burst destination address
|
||||
starts from where the last transfer ends. */
|
||||
|
||||
int32_t BlkSrcAddrOffset; /*!< Specifies the DMA channel block source address offset signed value :
|
||||
This parameter can be a value between -65535 and 65535.
|
||||
* If block source address offset > 0 => Increment the block source address by offset
|
||||
from where the last block ends.
|
||||
* If block source address offset < 0 => Decrement the next block source address by
|
||||
offset from where the last block ends.
|
||||
* If block source address offset == 0 => the next block source address starts from
|
||||
where the last block ends */
|
||||
|
||||
int32_t BlkDestAddrOffset; /*!< Specifies the DMA channel block destination address offset signed value :
|
||||
This parameter can be a value between -65535 and 65535.
|
||||
* If block destination address offset > 0 => Increment the block destination address
|
||||
by offset from where the last block ends.
|
||||
* If block destination address offset < 0 => Decrement the next block destination
|
||||
address by offset from where the last block ends.
|
||||
* If block destination address offset == 0 => the next block destination address
|
||||
starts from where the last block ends */
|
||||
|
||||
} DMA_RepeatBlockConfTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DMAEx Queue State Enumeration Definition.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DMA_QUEUE_STATE_RESET = 0x00U, /*!< DMA queue empty */
|
||||
HAL_DMA_QUEUE_STATE_READY = 0x01U, /*!< DMA queue ready for use */
|
||||
HAL_DMA_QUEUE_STATE_BUSY = 0x02U /*!< DMA queue execution on going */
|
||||
|
||||
} HAL_DMA_QStateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DMAEx Linked-List Node Configuration Structure Definition.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t NodeType; /*!< Specifies the DMA channel node type.
|
||||
This parameter can be a value of @ref DMAEx_Node_Type */
|
||||
|
||||
DMA_InitTypeDef Init; /*!< Specifies the DMA channel basic configuration */
|
||||
|
||||
DMA_DataHandlingConfTypeDef DataHandlingConfig; /*!< Specifies the DMA channel data handling channel configuration */
|
||||
|
||||
DMA_TriggerConfTypeDef TriggerConfig; /*!< Specifies the DMA channel trigger configuration */
|
||||
|
||||
DMA_RepeatBlockConfTypeDef RepeatBlockConfig; /*!< Specifies the DMA channel repeated block configuration */
|
||||
|
||||
uint32_t SrcAddress; /*!< Specifies the source memory address */
|
||||
uint32_t DstAddress; /*!< Specifies the destination memory address */
|
||||
uint32_t DataSize; /*!< Specifies the source data size in bytes */
|
||||
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
uint32_t SrcSecure; /*!< Specifies the source security attribute */
|
||||
uint32_t DestSecure; /*!< Specifies the destination security attribute */
|
||||
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
|
||||
|
||||
} DMA_NodeConfTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DMAEx Linked-List Node Structure Definition.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t LinkRegisters[8U]; /*!< Physical Node register description */
|
||||
uint32_t NodeInfo; /*!< Node information */
|
||||
|
||||
} DMA_NodeTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DMAEx Linked-List Queue Structure Definition.
|
||||
*/
|
||||
typedef struct __DMA_QListTypeDef
|
||||
{
|
||||
DMA_NodeTypeDef *Head; /*!< Specifies the queue head node */
|
||||
|
||||
DMA_NodeTypeDef *FirstCircularNode; /*!< Specifies the queue first circular node */
|
||||
|
||||
uint32_t NodeNumber; /*!< Specifies the queue node number */
|
||||
|
||||
__IO HAL_DMA_QStateTypeDef State; /*!< Specifies the queue state */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< Specifies the queue error code */
|
||||
|
||||
__IO uint32_t Type; /*!< Specifies whether the queue is static or dynamic */
|
||||
|
||||
} DMA_QListTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants ------------------------------------------------------------------------------------------------*/
|
||||
/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants
|
||||
* @brief DMAEx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup Queue_Error_Codes Queue Error Codes
|
||||
* @brief Queue Error Codes
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DMA_QUEUE_ERROR_NONE (0x00U) /*!< No error */
|
||||
#define HAL_DMA_QUEUE_ERROR_BUSY (0x01U) /*!< Error busy */
|
||||
#define HAL_DMA_QUEUE_ERROR_EMPTY (0x02U) /*!< Error unallowed operation for empty queue */
|
||||
#define HAL_DMA_QUEUE_ERROR_UNSUPPORTED (0x03U) /*!< Error unsupported feature */
|
||||
#define HAL_DMA_QUEUE_ERROR_INVALIDTYPE (0x04U) /*!< Error incompatible node type or circular initialization
|
||||
and queue circular types are incompatible */
|
||||
#define HAL_DMA_QUEUE_ERROR_OUTOFRANGE (0x05U) /*!< Error out of range node memory */
|
||||
#define HAL_DMA_QUEUE_ERROR_NOTFOUND (0x06U) /*!< Error node not found in queue */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_LinkedList_Mode DMAEx LinkedList Mode
|
||||
* @brief DMAEx LinkedList Mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_LINKEDLIST_NORMAL DMA_LINKEDLIST /*!< Linear linked-list DMA channel transfer */
|
||||
#define DMA_LINKEDLIST_CIRCULAR (DMA_LINKEDLIST | (0x01U)) /*!< Circular linked-list DMA channel transfer */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_Data_Alignment DMAEx Data Alignment
|
||||
* @brief DMAEx Data Alignment
|
||||
* @{
|
||||
*/
|
||||
#define DMA_DATA_RIGHTALIGN_ZEROPADDED 0x00000000U /*!< If source data width < destination data width
|
||||
=> Right aligned padded with 0 up to destination data
|
||||
width */
|
||||
#define DMA_DATA_RIGHTALIGN_LEFTTRUNC 0x00000000U /*!< If source data width > destination data width
|
||||
=> Right aligned left Truncated down to destination
|
||||
data width */
|
||||
#define DMA_DATA_RIGHTALIGN_SIGNEXT DMA_CTR1_PAM_0 /*!< If source data width < destination data width
|
||||
=> Right Aligned padded with sign extended up to
|
||||
destination data width */
|
||||
#define DMA_DATA_LEFTALIGN_RIGHTTRUNC DMA_CTR1_PAM_0 /*!< If source data width > destination data width
|
||||
=> Left Aligned Right Truncated down to the
|
||||
destination data width */
|
||||
#define DMA_DATA_PACK DMA_CTR1_PAM_1 /*!< If source data width < destination data width
|
||||
=> Packed at the destination data width
|
||||
(Available only for GPDMA) */
|
||||
#define DMA_DATA_UNPACK DMA_CTR1_PAM_1 /*!< If source data width > destination data width
|
||||
=> Unpacked at the destination data width
|
||||
(Available only for GPDMA) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_Data_Exchange DMAEx Data Exchange
|
||||
* @brief DMAEx Data Exchange
|
||||
* @{
|
||||
*/
|
||||
#define DMA_EXCHANGE_NONE 0x00000000U /*!< No data exchange */
|
||||
#define DMA_EXCHANGE_DEST_BYTE DMA_CTR1_DBX /*!< Destination Byte exchange when destination data width is > Byte */
|
||||
#define DMA_EXCHANGE_DEST_HALFWORD DMA_CTR1_DHX /*!< Destination Half-Word exchange when destination data width is > Half-Word */
|
||||
#define DMA_EXCHANGE_SRC_BYTE DMA_CTR1_SBX /*!< Source Byte endianness exchange when source data width is word */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_Trigger_Polarity DMAEx Trigger Polarity
|
||||
* @brief DMAEx Trigger Polarity
|
||||
* @{
|
||||
*/
|
||||
#define DMA_TRIG_POLARITY_MASKED 0x00000000U /*!< No trigger of the selected DMA request. Masked trigger event */
|
||||
#define DMA_TRIG_POLARITY_RISING DMA_CTR2_TRIGPOL_0 /*!< Trigger of the selected DMA request on the rising edge of the selected trigger event input */
|
||||
#define DMA_TRIG_POLARITY_FALLING DMA_CTR2_TRIGPOL_1 /*!< Trigger of the selected DMA request on the falling edge of the selected trigger event input */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_Trigger_Mode DMAEx Trigger Mode
|
||||
* @brief DMAEx Trigger Mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_TRIGM_BLOCK_TRANSFER 0x00000000U /*!< A block transfer is conditioned by (at least) one hit trigger */
|
||||
#define DMA_TRIGM_REPEATED_BLOCK_TRANSFER DMA_CTR2_TRIGM_0 /*!< A repeated block transfer is conditioned by (at least) one hit trigger */
|
||||
#define DMA_TRIGM_LLI_LINK_TRANSFER DMA_CTR2_TRIGM_1 /*!< A LLI link transfer is conditioned by (at least) one hit trigger */
|
||||
#define DMA_TRIGM_SINGLE_BURST_TRANSFER DMA_CTR2_TRIGM /*!< A single/burst transfer is conditioned by (at least) one hit trigger */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_Trigger_Selection DMAEx Trigger Selection
|
||||
* @brief DMAEx Trigger Selection
|
||||
* @{
|
||||
*/
|
||||
/* GPDMA1 triggers */
|
||||
#define GPDMA1_TRIGGER_EXTI_LINE0 0U /*!< GPDMA1 HW Trigger signal is EXTI_LINE0 */
|
||||
#define GPDMA1_TRIGGER_EXTI_LINE1 1U /*!< GPDMA1 HW Trigger signal is EXTI_LINE1 */
|
||||
#define GPDMA1_TRIGGER_EXTI_LINE2 2U /*!< GPDMA1 HW Trigger signal is EXTI_LINE2 */
|
||||
#define GPDMA1_TRIGGER_EXTI_LINE3 3U /*!< GPDMA1 HW Trigger signal is EXTI_LINE3 */
|
||||
#define GPDMA1_TRIGGER_EXTI_LINE4 4U /*!< GPDMA1 HW Trigger signal is EXTI_LINE4 */
|
||||
#define GPDMA1_TRIGGER_EXTI_LINE5 5U /*!< GPDMA1 HW Trigger signal is EXTI_LINE5 */
|
||||
#define GPDMA1_TRIGGER_EXTI_LINE6 6U /*!< GPDMA1 HW Trigger signal is EXTI_LINE6 */
|
||||
#define GPDMA1_TRIGGER_EXTI_LINE7 7U /*!< GPDMA1 HW Trigger signal is EXTI_LINE7 */
|
||||
#define GPDMA1_TRIGGER_TAMP_TRG1 8U /*!< GPDMA1 HW Trigger signal is TAMP_TRG1 */
|
||||
#define GPDMA1_TRIGGER_TAMP_TRG2 9U /*!< GPDMA1 HW Trigger signal is TAMP_TRG2 */
|
||||
#if defined (TAMP_CR1_TAMP3E)
|
||||
#define GPDMA1_TRIGGER_TAMP_TRG3 10U /*!< GPDMA1 HW Trigger signal is TAMP_TRG3 */
|
||||
#endif /* TAMP_CR1_TAMP3E */
|
||||
#define GPDMA1_TRIGGER_LPTIM1_CH1 11U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH1 */
|
||||
#define GPDMA1_TRIGGER_LPTIM1_CH2 12U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH2 */
|
||||
#define GPDMA1_TRIGGER_LPTIM2_CH1 13U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH1 */
|
||||
#define GPDMA1_TRIGGER_LPTIM2_CH2 14U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH2 */
|
||||
#define GPDMA1_TRIGGER_RTC_ALRA_TRG 15U /*!< GPDMA1 HW Trigger signal is RTC_ALRA_TRG */
|
||||
#define GPDMA1_TRIGGER_RTC_ALRB_TRG 16U /*!< GPDMA1 HW Trigger signal is RTC_ALRB_TRG */
|
||||
#define GPDMA1_TRIGGER_RTC_WUT_TRG 17U /*!< GPDMA1 HW Trigger signal is RTC_WUT_TRG */
|
||||
#define GPDMA1_TRIGGER_GPDMA1_CH0_TCF 18U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH0_TCF */
|
||||
#define GPDMA1_TRIGGER_GPDMA1_CH1_TCF 19U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */
|
||||
#define GPDMA1_TRIGGER_GPDMA1_CH2_TCF 20U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH2_TCF */
|
||||
#define GPDMA1_TRIGGER_GPDMA1_CH3_TCF 21U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH3_TCF */
|
||||
#define GPDMA1_TRIGGER_GPDMA1_CH4_TCF 22U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH4_TCF */
|
||||
#define GPDMA1_TRIGGER_GPDMA1_CH5_TCF 23U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH5_TCF */
|
||||
#define GPDMA1_TRIGGER_GPDMA1_CH6_TCF 24U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH6_TCF */
|
||||
#define GPDMA1_TRIGGER_GPDMA1_CH7_TCF 25U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH7_TCF */
|
||||
#define GPDMA1_TRIGGER_GPDMA2_CH0_TCF 26U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH0_TCF */
|
||||
#define GPDMA1_TRIGGER_GPDMA2_CH1_TCF 27U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH1_TCF */
|
||||
#define GPDMA1_TRIGGER_GPDMA2_CH2_TCF 28U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH2_TCF */
|
||||
#define GPDMA1_TRIGGER_GPDMA2_CH3_TCF 29U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH3_TCF */
|
||||
#define GPDMA1_TRIGGER_GPDMA2_CH4_TCF 30U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH4_TCF */
|
||||
#define GPDMA1_TRIGGER_GPDMA2_CH5_TCF 31U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH5_TCF */
|
||||
#define GPDMA1_TRIGGER_GPDMA2_CH6_TCF 32U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH6_TCF */
|
||||
#define GPDMA1_TRIGGER_GPDMA2_CH7_TCF 33U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH7_TCF */
|
||||
#define GPDMA1_TRIGGER_TIM2_TRGO 34U /*!< GPDMA1 HW Trigger signal is TIM2_TRGO */
|
||||
#if defined (TIM15)
|
||||
#define GPDMA1_TRIGGER_TIM15_TRGO 35U /*!< GPDMA1 HW Trigger signal is TIM15_TRGO */
|
||||
#endif /* TIM15 */
|
||||
#if defined (TIM12)
|
||||
#define GPDMA1_TRIGGER_TIM12_TRGO 36U /*!< GPDMA1 HW Trigger signal is TIM12_TRGO */
|
||||
#endif /* TIM12 */
|
||||
#if defined (LPTIM3)
|
||||
#define GPDMA1_TRIGGER_LPTIM3_CH1 37U /*!< GPDMA1 HW Trigger signal is LPTIM3_CH1 */
|
||||
#define GPDMA1_TRIGGER_LPTIM3_CH2 38U /*!< GPDMA1 HW Trigger signal is LPTIM3_CH2 */
|
||||
#endif /* LPTIM3 */
|
||||
#if defined (LPTIM4)
|
||||
#define GPDMA1_TRIGGER_LPTIM4_AIT 39U /*!< GPDMA1 HW Trigger signal is LPTIM4_AIT */
|
||||
#endif /* LPTIM4 */
|
||||
#if defined (LPTIM5)
|
||||
#define GPDMA1_TRIGGER_LPTIM5_CH1 40U /*!< GPDMA1 HW Trigger signal is LPTIM5_CH1 */
|
||||
#define GPDMA1_TRIGGER_LPTIM5_CH2 41U /*!< GPDMA1 HW Trigger signal is LPTIM5_CH2 */
|
||||
#endif /* LPTIM5 */
|
||||
#if defined (LPTIM6)
|
||||
#define GPDMA1_TRIGGER_LPTIM6_CH1 42U /*!< GPDMA1 HW Trigger signal is LPTIM6_CH1 */
|
||||
#define GPDMA1_TRIGGER_LPTIM6_CH2 43U /*!< GPDMA1 HW Trigger signal is LPTIM6_CH2 */
|
||||
#endif /* LPTIM6 */
|
||||
#if defined (COMP1)
|
||||
#define GPDMA1_TRIGGER_COMP1_OUT 44U /*!< GPDMA1 HW Trigger signal is COMP1_OUT */
|
||||
#endif /* COMP1 */
|
||||
#if defined (STM32H503xx)
|
||||
#define GPDMA1_TRIGGER_EVENTOUT 45U /*!< GPDMA1 HW Trigger signal is COMP1_OUT */
|
||||
#endif /* STM32H503xx */
|
||||
|
||||
/* GPDMA2 triggers */
|
||||
#define GPDMA2_TRIGGER_EXTI_LINE0 0U /*!< GPDMA2 HW Trigger signal is EXTI_LINE0 */
|
||||
#define GPDMA2_TRIGGER_EXTI_LINE1 1U /*!< GPDMA2 HW Trigger signal is EXTI_LINE1 */
|
||||
#define GPDMA2_TRIGGER_EXTI_LINE2 2U /*!< GPDMA2 HW Trigger signal is EXTI_LINE2 */
|
||||
#define GPDMA2_TRIGGER_EXTI_LINE3 3U /*!< GPDMA2 HW Trigger signal is EXTI_LINE3 */
|
||||
#define GPDMA2_TRIGGER_EXTI_LINE4 4U /*!< GPDMA2 HW Trigger signal is EXTI_LINE4 */
|
||||
#define GPDMA2_TRIGGER_EXTI_LINE5 5U /*!< GPDMA2 HW Trigger signal is EXTI_LINE5 */
|
||||
#define GPDMA2_TRIGGER_EXTI_LINE6 6U /*!< GPDMA2 HW Trigger signal is EXTI_LINE6 */
|
||||
#define GPDMA2_TRIGGER_EXTI_LINE7 7U /*!< GPDMA2 HW Trigger signal is EXTI_LINE7 */
|
||||
#define GPDMA2_TRIGGER_TAMP_TRG1 8U /*!< GPDMA2 HW Trigger signal is TAMP_TRG1 */
|
||||
#define GPDMA2_TRIGGER_TAMP_TRG2 9U /*!< GPDMA2 HW Trigger signal is TAMP_TRG2 */
|
||||
#define GPDMA2_TRIGGER_TAMP_TRG3 10U /*!< GPDMA2 HW Trigger signal is TAMP_TRG3 */
|
||||
#define GPDMA2_TRIGGER_LPTIM1_CH1 11U /*!< GPDMA2 HW Trigger signal is LPTIM1_CH1 */
|
||||
#define GPDMA2_TRIGGER_LPTIM1_CH2 12U /*!< GPDMA2 HW Trigger signal is LPTIM1_CH2 */
|
||||
#define GPDMA2_TRIGGER_LPTIM2_CH1 13U /*!< GPDMA2 HW Trigger signal is LPTIM2_CH1 */
|
||||
#define GPDMA2_TRIGGER_LPTIM2_CH2 14U /*!< GPDMA2 HW Trigger signal is LPTIM2_CH2 */
|
||||
#define GPDMA2_TRIGGER_RTC_ALRA_TRG 15U /*!< GPDMA2 HW Trigger signal is RTC_ALRA_TRG */
|
||||
#define GPDMA2_TRIGGER_RTC_ALRB_TRG 16U /*!< GPDMA2 HW Trigger signal is RTC_ALRB_TRG */
|
||||
#define GPDMA2_TRIGGER_RTC_WUT_TRG 17U /*!< GPDMA2 HW Trigger signal is RTC_WUT_TRG */
|
||||
#define GPDMA2_TRIGGER_GPDMA1_CH0_TCF 18U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH0_TCF */
|
||||
#define GPDMA2_TRIGGER_GPDMA1_CH1_TCF 19U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH1_TCF */
|
||||
#define GPDMA2_TRIGGER_GPDMA1_CH2_TCF 20U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH2_TCF */
|
||||
#define GPDMA2_TRIGGER_GPDMA1_CH3_TCF 21U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH3_TCF */
|
||||
#define GPDMA2_TRIGGER_GPDMA1_CH4_TCF 22U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH4_TCF */
|
||||
#define GPDMA2_TRIGGER_GPDMA1_CH5_TCF 23U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH5_TCF */
|
||||
#define GPDMA2_TRIGGER_GPDMA1_CH6_TCF 24U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH6_TCF */
|
||||
#define GPDMA2_TRIGGER_GPDMA1_CH7_TCF 25U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH7_TCF */
|
||||
#define GPDMA2_TRIGGER_GPDMA2_CH0_TCF 26U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH0_TCF */
|
||||
#define GPDMA2_TRIGGER_GPDMA2_CH1_TCF 27U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH1_TCF */
|
||||
#define GPDMA2_TRIGGER_GPDMA2_CH2_TCF 28U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH2_TCF */
|
||||
#define GPDMA2_TRIGGER_GPDMA2_CH3_TCF 29U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH3_TCF */
|
||||
#define GPDMA2_TRIGGER_GPDMA2_CH4_TCF 30U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH4_TCF */
|
||||
#define GPDMA2_TRIGGER_GPDMA2_CH5_TCF 31U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH5_TCF */
|
||||
#define GPDMA2_TRIGGER_GPDMA2_CH6_TCF 32U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH6_TCF */
|
||||
#define GPDMA2_TRIGGER_GPDMA2_CH7_TCF 33U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH7_TCF */
|
||||
#define GPDMA2_TRIGGER_TIM2_TRGO 34U /*!< GPDMA2 HW Trigger signal is TIM2_TRGO */
|
||||
#if defined (TIM15)
|
||||
#define GPDMA2_TRIGGER_TIM15_TRGO 35U /*!< GPDMA2 HW Trigger signal is TIM15_TRGO */
|
||||
#endif /* TIM15 */
|
||||
#if defined (TIM12)
|
||||
#define GPDMA2_TRIGGER_TIM12_TRGO 36U /*!< GPDMA2 HW Trigger signal is TIM12_TRGO */
|
||||
#endif /* TIM12 */
|
||||
#if defined (LPTIM3)
|
||||
#define GPDMA2_TRIGGER_LPTIM3_CH1 37U /*!< GPDMA2 HW Trigger signal is LPTIM3_CH1 */
|
||||
#define GPDMA2_TRIGGER_LPTIM3_CH2 38U /*!< GPDMA2 HW Trigger signal is LPTIM3_CH2 */
|
||||
#endif /* LPTIM3 */
|
||||
#if defined (LPTIM4)
|
||||
#define GPDMA2_TRIGGER_LPTIM4_AIT 39U /*!< GPDMA2 HW Trigger signal is LPTIM4_AIT */
|
||||
#endif /* LPTIM4 */
|
||||
#if defined (LPTIM5)
|
||||
#define GPDMA2_TRIGGER_LPTIM5_CH1 40U /*!< GPDMA2 HW Trigger signal is LPTIM5_CH1 */
|
||||
#define GPDMA2_TRIGGER_LPTIM5_CH2 41U /*!< GPDMA2 HW Trigger signal is LPTIM5_CH2 */
|
||||
#endif /* LPTIM5 */
|
||||
#if defined (LPTIM6)
|
||||
#define GPDMA2_TRIGGER_LPTIM6_CH1 42U /*!< GPDMA2 HW Trigger signal is LPTIM6_CH1 */
|
||||
#define GPDMA2_TRIGGER_LPTIM6_CH2 43U /*!< GPDMA2 HW Trigger signal is LPTIM6_CH2 */
|
||||
#endif /* LPTIM6 */
|
||||
#if defined (COMP1)
|
||||
#define GPDMA2_TRIGGER_COMP1_OUT 44U /*!< GPDMA2 HW Trigger signal is COMP1_OUT */
|
||||
#endif /* COMP1 */
|
||||
#if defined (STM32H503xx)
|
||||
#define GPDMA2_TRIGGER_EVENTOUT 45U /*!< GPDMA2 HW Trigger signal is COMP1_OUT */
|
||||
#endif /* STM32H503xx */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_Node_Type DMAEx Node Type
|
||||
* @brief DMAEx Node Type
|
||||
* @{
|
||||
*/
|
||||
#define DMA_GPDMA_LINEAR_NODE (DMA_CHANNEL_TYPE_GPDMA | DMA_CHANNEL_TYPE_LINEAR_ADDR) /*!< Defines the GPDMA linear addressing node type */
|
||||
#define DMA_GPDMA_2D_NODE (DMA_CHANNEL_TYPE_GPDMA | DMA_CHANNEL_TYPE_2D_ADDR) /*!< Defines the GPDMA 2 dimension addressing node type */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_Link_Allocated_Port DMAEx Linked-List Allocated Port
|
||||
* @brief DMAEx Linked-List Allocated Port
|
||||
* @{
|
||||
*/
|
||||
#define DMA_LINK_ALLOCATED_PORT0 0x00000000U /*!< Link allocated port 0 */
|
||||
#define DMA_LINK_ALLOCATED_PORT1 DMA_CCR_LAP /*!< Link allocated port 1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_Link_Step_Mode DMAEx Link Step Mode
|
||||
* @brief DMAEx Link Step Mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_LSM_FULL_EXECUTION 0x00000000U /*!< Channel is executed for the full linked-list */
|
||||
#define DMA_LSM_1LINK_EXECUTION DMA_CCR_LSM /*!< Channel is executed once for the current LLI */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions ------------------------------------------------------------------------------------------------*/
|
||||
/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
|
||||
* @brief DMAEx Exported functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_Exported_Functions_Group1 Linked-List Initialization and De-Initialization Functions
|
||||
* @brief Linked-List Initialization and De-Initialization Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_Init(DMA_HandleTypeDef *const hdma);
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_Exported_Functions_Group2 Linked-List IO Operation Functions
|
||||
* @brief Linked-List IO Operation Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_Start(DMA_HandleTypeDef *const hdma);
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_Start_IT(DMA_HandleTypeDef *const hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_Exported_Functions_Group3 Linked-List Management Functions
|
||||
* @brief Linked-List Management Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig,
|
||||
DMA_NodeTypeDef *const pNode);
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig,
|
||||
DMA_NodeTypeDef const *const pNode);
|
||||
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_InsertNode(DMA_QListTypeDef *const pQList,
|
||||
DMA_NodeTypeDef *const pPrevNode,
|
||||
DMA_NodeTypeDef *const pNewNode);
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Head(DMA_QListTypeDef *const pQList,
|
||||
DMA_NodeTypeDef *const pNewNode);
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Tail(DMA_QListTypeDef *const pQList,
|
||||
DMA_NodeTypeDef *const pNewNode);
|
||||
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode(DMA_QListTypeDef *const pQList,
|
||||
DMA_NodeTypeDef *const pNode);
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Head(DMA_QListTypeDef *const pQList);
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Tail(DMA_QListTypeDef *const pQList);
|
||||
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode(DMA_QListTypeDef *const pQList,
|
||||
DMA_NodeTypeDef *const pOldNode,
|
||||
DMA_NodeTypeDef *const pNewNode);
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Head(DMA_QListTypeDef *const pQList,
|
||||
DMA_NodeTypeDef *const pNewNode);
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Tail(DMA_QListTypeDef *const pQList,
|
||||
DMA_NodeTypeDef *const pNewNode);
|
||||
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_ResetQ(DMA_QListTypeDef *const pQList);
|
||||
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_InsertQ(DMA_QListTypeDef *const pSrcQList,
|
||||
DMA_NodeTypeDef const *const pPrevNode,
|
||||
DMA_QListTypeDef *const pDestQList);
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Head(DMA_QListTypeDef *const pSrcQList,
|
||||
DMA_QListTypeDef *const pDestQList);
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Tail(DMA_QListTypeDef *const pSrcQList,
|
||||
DMA_QListTypeDef *const pDestQList);
|
||||
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_SetCircularModeConfig(DMA_QListTypeDef *const pQList,
|
||||
DMA_NodeTypeDef *const pFirstCircularNode);
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_SetCircularMode(DMA_QListTypeDef *const pQList);
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_ClearCircularMode(DMA_QListTypeDef *const pQList);
|
||||
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToDynamic(DMA_QListTypeDef *const pQList);
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToStatic(DMA_QListTypeDef *const pQList);
|
||||
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_LinkQ(DMA_HandleTypeDef *const hdma,
|
||||
DMA_QListTypeDef *const pQList);
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_UnLinkQ(DMA_HandleTypeDef *const hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_Exported_Functions_Group4 Data Handling, Repeated Block and Trigger Configuration Functions
|
||||
* @brief Data Handling, Repeated Block and Trigger Configuration Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMAEx_ConfigDataHandling(DMA_HandleTypeDef *const hdma,
|
||||
DMA_DataHandlingConfTypeDef const *const pConfigDataHandling);
|
||||
HAL_StatusTypeDef HAL_DMAEx_ConfigTrigger(DMA_HandleTypeDef *const hdma,
|
||||
DMA_TriggerConfTypeDef const *const pConfigTrigger);
|
||||
HAL_StatusTypeDef HAL_DMAEx_ConfigRepeatBlock(DMA_HandleTypeDef *const hdma,
|
||||
DMA_RepeatBlockConfTypeDef const *const pConfigRepeatBlock);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_Exported_Functions_Group5 Suspend and Resume Operation Functions
|
||||
* @brief Suspend and Resume Operation Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMAEx_Suspend(DMA_HandleTypeDef *const hdma);
|
||||
HAL_StatusTypeDef HAL_DMAEx_Suspend_IT(DMA_HandleTypeDef *const hdma);
|
||||
HAL_StatusTypeDef HAL_DMAEx_Resume(DMA_HandleTypeDef *const hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_Exported_Functions_Group6 FIFO Status Function
|
||||
* @brief FIFO Status Function
|
||||
* @{
|
||||
*/
|
||||
uint32_t HAL_DMAEx_GetFifoLevel(DMA_HandleTypeDef const *const hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -----------------------------------------------------------------------------------------------------*/
|
||||
/** @defgroup DMAEx_Private_Types DMAEx Private Types
|
||||
* @brief DMAEx Private Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief DMA Node in Queue Information Structure Definition.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t cllr_offset; /* CLLR register offset */
|
||||
|
||||
uint32_t previousnode_addr; /* Previous node address */
|
||||
|
||||
uint32_t currentnode_pos; /* Current node position */
|
||||
|
||||
uint32_t currentnode_addr; /* Current node address */
|
||||
|
||||
uint32_t nextnode_addr; /* Next node address */
|
||||
|
||||
} DMA_NodeInQInfoTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants -------------------------------------------------------------------------------------------------*/
|
||||
/** @defgroup DMAEx_Private_Constants DMAEx Private Constants
|
||||
* @brief DMAEx Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define DMA_LINKEDLIST (0x0080U) /* DMA channel linked-list mode */
|
||||
|
||||
#define DMA_CHANNEL_TYPE_LINEAR_ADDR (0x0001U) /* DMA channel linear addressing mode */
|
||||
#define DMA_CHANNEL_TYPE_2D_ADDR (0x0002U) /* DMA channel 2D addressing mode */
|
||||
#define DMA_CHANNEL_TYPE_GPDMA (0x0020U) /* GPDMA channel node */
|
||||
|
||||
#define NODE_TYPE_MASK (0x00FFU) /* DMA channel node type */
|
||||
#define NODE_CLLR_IDX (0x0700U) /* DMA channel node CLLR index mask */
|
||||
#define NODE_CLLR_IDX_POS (0x0008U) /* DMA channel node CLLR index position */
|
||||
|
||||
#define NODE_MAXIMUM_SIZE (0x0008U) /* Amount of registers of the node */
|
||||
|
||||
#define NODE_STATIC_FORMAT (0x0000U) /* DMA channel node static format */
|
||||
#define NODE_DYNAMIC_FORMAT (0x0001U) /* DMA channel node dynamic format */
|
||||
|
||||
#define UPDATE_CLLR_POSITION (0x0000U) /* DMA channel update CLLR position */
|
||||
#define UPDATE_CLLR_VALUE (0x0001U) /* DMA channel update CLLR value */
|
||||
|
||||
#define LASTNODE_ISNOT_CIRCULAR (0x0000U) /* Last node is not first circular node */
|
||||
#define LASTNODE_IS_CIRCULAR (0x0001U) /* Last node is first circular node */
|
||||
|
||||
#define QUEUE_TYPE_STATIC (0x0000U) /* DMA channel static queue */
|
||||
#define QUEUE_TYPE_DYNAMIC (0x0001U) /* DMA channel dynamic queue */
|
||||
|
||||
#define NODE_CTR1_DEFAULT_OFFSET (0x0000U) /* CTR1 default offset */
|
||||
#define NODE_CTR2_DEFAULT_OFFSET (0x0001U) /* CTR2 default offset */
|
||||
#define NODE_CBR1_DEFAULT_OFFSET (0x0002U) /* CBR1 default offset */
|
||||
#define NODE_CSAR_DEFAULT_OFFSET (0x0003U) /* CSAR default offset */
|
||||
#define NODE_CDAR_DEFAULT_OFFSET (0x0004U) /* CDAR default offset */
|
||||
#define NODE_CTR3_DEFAULT_OFFSET (0x0005U) /* CTR3 2D addressing default offset */
|
||||
#define NODE_CBR2_DEFAULT_OFFSET (0x0006U) /* CBR2 2D addressing default offset */
|
||||
#define NODE_CLLR_2D_DEFAULT_OFFSET (0x0007U) /* CLLR 2D addressing default offset */
|
||||
#define NODE_CLLR_LINEAR_DEFAULT_OFFSET (0x0005U) /* CLLR linear addressing default offset */
|
||||
|
||||
#define DMA_BURST_ADDR_OFFSET_MIN (-8192L) /* DMA burst minimum address offset */
|
||||
#define DMA_BURST_ADDR_OFFSET_MAX (8192L) /* DMA burst maximum address offset */
|
||||
#define DMA_BLOCK_ADDR_OFFSET_MIN (-65536L) /* DMA block minimum address offset */
|
||||
#define DMA_BLOCK_ADDR_OFFSET_MAX (65536L) /* DMA block maximum address offset */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ----------------------------------------------------------------------------------------------------*/
|
||||
/** @defgroup DMAEx_Private_Macros DMAEx Private Macros
|
||||
* @brief DMAEx Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_DMA_DATA_ALIGNMENT(ALIGNMENT) \
|
||||
(((ALIGNMENT) == DMA_DATA_RIGHTALIGN_ZEROPADDED) || \
|
||||
((ALIGNMENT) == DMA_DATA_RIGHTALIGN_SIGNEXT) || \
|
||||
((ALIGNMENT) == DMA_DATA_PACK))
|
||||
|
||||
#define IS_DMA_DATA_EXCHANGE(EXCHANGE) \
|
||||
(((EXCHANGE) & (~(DMA_EXCHANGE_SRC_BYTE | DMA_EXCHANGE_DEST_BYTE | DMA_EXCHANGE_DEST_HALFWORD))) == 0U)
|
||||
|
||||
#define IS_DMA_REPEAT_COUNT(COUNT) \
|
||||
(((COUNT) > 0U) && ((COUNT) <= (DMA_CBR1_BRC >> DMA_CBR1_BRC_Pos)))
|
||||
|
||||
#define IS_DMA_BURST_ADDR_OFFSET(BURST_ADDR_OFFSET) \
|
||||
(((BURST_ADDR_OFFSET) > DMA_BURST_ADDR_OFFSET_MIN) && \
|
||||
((BURST_ADDR_OFFSET) < DMA_BURST_ADDR_OFFSET_MAX))
|
||||
|
||||
#define IS_DMA_BLOCK_ADDR_OFFSET(BLOCK_ADDR_OFFSET) \
|
||||
(((BLOCK_ADDR_OFFSET) > DMA_BLOCK_ADDR_OFFSET_MIN) && \
|
||||
((BLOCK_ADDR_OFFSET) < DMA_BLOCK_ADDR_OFFSET_MAX))
|
||||
|
||||
#define IS_DMA_LINK_ALLOCATED_PORT(LINK_ALLOCATED_PORT) \
|
||||
(((LINK_ALLOCATED_PORT) & (~(DMA_CCR_LAP))) == 0U)
|
||||
|
||||
#define IS_DMA_LINK_STEP_MODE(MODE) \
|
||||
(((MODE) == DMA_LSM_FULL_EXECUTION) || \
|
||||
((MODE) == DMA_LSM_1LINK_EXECUTION))
|
||||
|
||||
#define IS_DMA_TRIGGER_MODE(MODE) \
|
||||
(((MODE) == DMA_TRIGM_BLOCK_TRANSFER) || \
|
||||
((MODE) == DMA_TRIGM_REPEATED_BLOCK_TRANSFER) || \
|
||||
((MODE) == DMA_TRIGM_LLI_LINK_TRANSFER) || \
|
||||
((MODE) == DMA_TRIGM_SINGLE_BURST_TRANSFER))
|
||||
|
||||
#define IS_DMA_TCEM_LINKEDLIST_EVENT_MODE(MODE) \
|
||||
(((MODE) == DMA_TCEM_BLOCK_TRANSFER) || \
|
||||
((MODE) == DMA_TCEM_REPEATED_BLOCK_TRANSFER) || \
|
||||
((MODE) == DMA_TCEM_EACH_LL_ITEM_TRANSFER) || \
|
||||
((MODE) == DMA_TCEM_LAST_LL_ITEM_TRANSFER))
|
||||
|
||||
#define IS_DMA_LINKEDLIST_MODE(MODE) \
|
||||
(((MODE) == DMA_LINKEDLIST_NORMAL) || \
|
||||
((MODE) == DMA_LINKEDLIST_CIRCULAR))
|
||||
|
||||
#define IS_DMA_TRIGGER_POLARITY(POLARITY) \
|
||||
(((POLARITY) == DMA_TRIG_POLARITY_MASKED) || \
|
||||
((POLARITY) == DMA_TRIG_POLARITY_RISING) || \
|
||||
((POLARITY) == DMA_TRIG_POLARITY_FALLING))
|
||||
|
||||
#if defined (I3C2)
|
||||
#define IS_DMA_TRIGGER_SELECTION(TRIGGER) ((TRIGGER) <= GPDMA1_TRIGGER_EVENTOUT)
|
||||
#else
|
||||
#define IS_DMA_TRIGGER_SELECTION(TRIGGER) ((TRIGGER) <= GPDMA1_TRIGGER_LPTIM6_CH2)
|
||||
#endif /* I3C2 */
|
||||
|
||||
#define IS_DMA_NODE_TYPE(TYPE) \
|
||||
(((TYPE) == DMA_GPDMA_LINEAR_NODE) || \
|
||||
((TYPE) == DMA_GPDMA_2D_NODE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private functions -------------------------------------------------------------------------------------------------*/
|
||||
/** @defgroup DMAEx_Private_Functions DMAEx Private Functions
|
||||
* @brief DMAEx Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* STM32H5xx_HAL_DMA_EX_H */
|
||||
|
|
@ -0,0 +1,551 @@
|
|||
/**
|
||||
**********************************************************************************************************************
|
||||
* @file stm32h5xx_hal_dts.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of DTS HAL module.
|
||||
**********************************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
**********************************************************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/
|
||||
#ifndef STM32H5xx_HAL_DTS_H
|
||||
#define STM32H5xx_HAL_DTS_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ----------------------------------------------------------------------------------------------------------*/
|
||||
#include "stm32h5xx_hal_def.h"
|
||||
#if defined(DTS)
|
||||
|
||||
/** @addtogroup STM32H5xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DTS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ----------------------------------------------------------------------------------------------------*/
|
||||
/** @defgroup DTS_Exported_Types DTS Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief DTS Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t QuickMeasure; /*!< Specifies the quick measure option selection of the DTS sensor.
|
||||
This parameter can be a value of @ref DTS_Quick_Measurement */
|
||||
|
||||
uint32_t RefClock; /*!< Specifies the reference clock selection of the DTS sensor.
|
||||
This parameter can be a value of @ref DTS_Reference_Clock_Selection */
|
||||
|
||||
uint32_t TriggerInput; /*!< Specifies the trigger input of the DTS sensor.
|
||||
This parameter can be a value of @ref DTS_TriggerConfig */
|
||||
|
||||
uint32_t SamplingTime; /*!< Specifies the sampling time configuration.
|
||||
This parameter can be a value of @ref DTS_Sampling_Time */
|
||||
|
||||
uint32_t Divider; /*!< Specifies the high speed clock divider ratio.
|
||||
This parameter can be a value from 0 to 127 */
|
||||
|
||||
uint32_t HighThreshold; /*!< Specifies the high threshold of the DTS sensor */
|
||||
|
||||
uint32_t LowThreshold; /*!< Specifies the low threshold of the DTS sensor */
|
||||
|
||||
} DTS_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DTS_STATE_RESET = 0x00UL, /*!< DTS not yet initialized or disabled */
|
||||
HAL_DTS_STATE_READY = 0x01UL, /*!< DTS initialized and ready for use */
|
||||
HAL_DTS_STATE_BUSY = 0x02UL, /*!< DTS is running */
|
||||
HAL_DTS_STATE_TIMEOUT = 0x03UL, /*!< Timeout state */
|
||||
HAL_DTS_STATE_ERROR = 0x04UL /*!< Internal Process error */
|
||||
|
||||
} HAL_DTS_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DTS Handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1U)
|
||||
typedef struct __DTS_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
|
||||
{
|
||||
DTS_TypeDef *Instance; /*!< Register base address */
|
||||
DTS_InitTypeDef Init; /*!< DTS required parameters */
|
||||
HAL_LockTypeDef Lock; /*!< DTS Locking object */
|
||||
__IO HAL_DTS_StateTypeDef State; /*!< DTS peripheral state */
|
||||
|
||||
#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1U)
|
||||
void (* MspInitCallback)(struct __DTS_HandleTypeDef *hdts); /*!< DTS Base Msp Init Callback */
|
||||
void (* MspDeInitCallback)(struct __DTS_HandleTypeDef *hdts); /*!< DTS Base Msp DeInit Callback */
|
||||
void (* EndCallback)(struct __DTS_HandleTypeDef *hdts); /*!< End measure Callback */
|
||||
void (* LowCallback)(struct __DTS_HandleTypeDef *hdts); /*!< low threshold Callback */
|
||||
void (* HighCallback)(struct __DTS_HandleTypeDef *hdts); /*!< high threshold Callback */
|
||||
void (* AsyncEndCallback)(struct __DTS_HandleTypeDef *hdts); /*!< Asynchronous end of measure Callback */
|
||||
void (* AsyncLowCallback)(struct __DTS_HandleTypeDef *hdts); /*!< Asynchronous low threshold Callback */
|
||||
void (* AsyncHighCallback)(struct __DTS_HandleTypeDef *hdts); /*!< Asynchronous high threshold Callback */
|
||||
#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
|
||||
} DTS_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1U)
|
||||
/**
|
||||
* @brief DTS callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DTS_MEAS_COMPLETE_CB_ID = 0x00U, /*!< Measure complete callback ID */
|
||||
HAL_DTS_ASYNC_MEAS_COMPLETE_CB_ID = 0x01U, /*!< Asynchronous measure complete callback ID */
|
||||
HAL_DTS_LOW_THRESHOLD_CB_ID = 0x02U, /*!< Low threshold detection callback ID */
|
||||
HAL_DTS_ASYNC_LOW_THRESHOLD_CB_ID = 0x03U, /*!< Asynchronous low threshold detection callback ID */
|
||||
HAL_DTS_HIGH_THRESHOLD_CB_ID = 0x04U, /*!< High threshold detection callback ID */
|
||||
HAL_DTS_ASYNC_HIGH_THRESHOLD_CB_ID = 0x05U, /*!< Asynchronous high threshold detection callback ID */
|
||||
HAL_DTS_MSPINIT_CB_ID = 0x06U, /*!< MSP init callback ID */
|
||||
HAL_DTS_MSPDEINIT_CB_ID = 0x07U /*!< MSP de-init callback ID */
|
||||
} HAL_DTS_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DTS callback pointers definition
|
||||
*/
|
||||
typedef void (*pDTS_CallbackTypeDef)(DTS_HandleTypeDef *hdts);
|
||||
#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants ------------------------------------------------------------------------------------------------*/
|
||||
/** @defgroup DTS_Exported_Constants DTS Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DTS_TriggerConfig DTS Trigger Configuration
|
||||
* @{
|
||||
*/
|
||||
/* @brief No Hardware trigger detection */
|
||||
#define DTS_TRIGGER_HW_NONE (0UL)
|
||||
|
||||
/* @brief External Interrupt Mode with LPTIMER1 trigger detection */
|
||||
#define DTS_TRIGGER_LPTIMER1 DTS_CFGR1_TS1_INTRIG_SEL_0
|
||||
|
||||
/* @brief External Interrupt Mode with LPTIMER2 trigger detection */
|
||||
#define DTS_TRIGGER_LPTIMER2 DTS_CFGR1_TS1_INTRIG_SEL_1
|
||||
|
||||
#if defined(LPTIM3)
|
||||
/* @brief External Interrupt Mode with LPTIMER3 trigger detection */
|
||||
#define DTS_TRIGGER_LPTIMER3 (DTS_CFGR1_TS1_INTRIG_SEL_0 | DTS_CFGR1_TS1_INTRIG_SEL_1)
|
||||
#endif /* defined(LPTIM3) */
|
||||
|
||||
/* @brief External Interrupt Mode with EXTI13 trigger detection */
|
||||
#define DTS_TRIGGER_EXTI13 DTS_CFGR1_TS1_INTRIG_SEL_2
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DTS_Quick_Measurement DTS Quick Measurement
|
||||
* @{
|
||||
*/
|
||||
#define DTS_QUICKMEAS_ENABLE DTS_CFGR1_Q_MEAS_OPT /*!< Enable the Quick Measure (Measure without calibration) */
|
||||
#define DTS_QUICKMEAS_DISABLE (0x0UL) /*!< Disable the Quick Measure (Measure with calibration) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DTS_Reference_Clock_Selection DTS Reference Clock Selection
|
||||
* @{
|
||||
*/
|
||||
#define DTS_REFCLKSEL_LSE DTS_CFGR1_REFCLK_SEL /*!< Low speed REF clock (LSE) */
|
||||
#define DTS_REFCLKSEL_PCLK (0UL) /*!< High speed REF clock (PCLK) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DTS_Sampling_Time DTS Sampling Time
|
||||
* @{
|
||||
*/
|
||||
#define DTS_SMP_TIME_1_CYCLE DTS_CFGR1_TS1_SMP_TIME_0 /*!< 1 clock cycle for the sampling time */
|
||||
#define DTS_SMP_TIME_2_CYCLE DTS_CFGR1_TS1_SMP_TIME_1 /*!< 2 clock cycle for the sampling time */
|
||||
#define DTS_SMP_TIME_3_CYCLE (DTS_CFGR1_TS1_SMP_TIME_0 |\
|
||||
DTS_CFGR1_TS1_SMP_TIME_1) /*!< 3 clock cycle for the sampling time */
|
||||
#define DTS_SMP_TIME_4_CYCLE (DTS_CFGR1_TS1_SMP_TIME_2) /*!< 4 clock cycle for the sampling time */
|
||||
#define DTS_SMP_TIME_5_CYCLE (DTS_CFGR1_TS1_SMP_TIME_0 |\
|
||||
DTS_CFGR1_TS1_SMP_TIME_2) /*!< 5 clock cycle for the sampling time */
|
||||
#define DTS_SMP_TIME_6_CYCLE (DTS_CFGR1_TS1_SMP_TIME_1 |\
|
||||
DTS_CFGR1_TS1_SMP_TIME_2) /*!< 6 clock cycle for the sampling time */
|
||||
#define DTS_SMP_TIME_7_CYCLE (DTS_CFGR1_TS1_SMP_TIME_0 |\
|
||||
DTS_CFGR1_TS1_SMP_TIME_1 |\
|
||||
DTS_CFGR1_TS1_SMP_TIME_2) /*!< 7 clock cycle for the sampling time */
|
||||
#define DTS_SMP_TIME_8_CYCLE (DTS_CFGR1_TS1_SMP_TIME_3) /*!< 8 clock cycle for the sampling time */
|
||||
#define DTS_SMP_TIME_9_CYCLE (DTS_CFGR1_TS1_SMP_TIME_0 |\
|
||||
DTS_CFGR1_TS1_SMP_TIME_3) /*!< 9 clock cycle for the sampling time */
|
||||
#define DTS_SMP_TIME_10_CYCLE (DTS_CFGR1_TS1_SMP_TIME_1 |\
|
||||
DTS_CFGR1_TS1_SMP_TIME_3) /*!< 10 clock cycle for the sampling time */
|
||||
#define DTS_SMP_TIME_11_CYCLE (DTS_CFGR1_TS1_SMP_TIME_0 |\
|
||||
DTS_CFGR1_TS1_SMP_TIME_1 |\
|
||||
DTS_CFGR1_TS1_SMP_TIME_3) /*!< 11 clock cycle for the sampling time */
|
||||
#define DTS_SMP_TIME_12_CYCLE (DTS_CFGR1_TS1_SMP_TIME_2 |\
|
||||
DTS_CFGR1_TS1_SMP_TIME_3) /*!< 12 clock cycle for the sampling time */
|
||||
#define DTS_SMP_TIME_13_CYCLE (DTS_CFGR1_TS1_SMP_TIME_0 |\
|
||||
DTS_CFGR1_TS1_SMP_TIME_2 |\
|
||||
DTS_CFGR1_TS1_SMP_TIME_3) /*!< 13 clock cycle for the sampling time */
|
||||
#define DTS_SMP_TIME_14_CYCLE (DTS_CFGR1_TS1_SMP_TIME_1 |\
|
||||
DTS_CFGR1_TS1_SMP_TIME_2 |\
|
||||
DTS_CFGR1_TS1_SMP_TIME_3) /*!< 14 clock cycle for the sampling time */
|
||||
#define DTS_SMP_TIME_15_CYCLE (DTS_CFGR1_TS1_SMP_TIME_0 |\
|
||||
DTS_CFGR1_TS1_SMP_TIME_1 |\
|
||||
DTS_CFGR1_TS1_SMP_TIME_2 |\
|
||||
DTS_CFGR1_TS1_SMP_TIME_3) /*!< 15 clock cycle for the sampling time */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DTS_Flag_Definitions DTS Flag Definitions
|
||||
* @{
|
||||
*/
|
||||
#define DTS_FLAG_TS1_ITE DTS_SR_TS1_ITEF /*!< Interrupt flag for end of measure for DTS1 */
|
||||
#define DTS_FLAG_TS1_ITL DTS_SR_TS1_ITLF /*!< Interrupt flag for low threshold for DTS1 */
|
||||
#define DTS_FLAG_TS1_ITH DTS_SR_TS1_ITHF /*!< Interrupt flag for high threshold for DTS1 */
|
||||
#define DTS_FLAG_TS1_AITE DTS_SR_TS1_AITEF /*!< Asynchronous Interrupt flag for end of measure for DTS1 */
|
||||
#define DTS_FLAG_TS1_AITL DTS_SR_TS1_AITLF /*!< Asynchronous Interrupt flag for low threshold for DTS1 */
|
||||
#define DTS_FLAG_TS1_AITH DTS_SR_TS1_AITHF /*!< Asynchronous Interrupt flag for high threshold for DTS1 */
|
||||
#define DTS_FLAG_TS1_RDY DTS_SR_TS1_RDY /*!< Ready flag for DTS1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DTS_Interrupts_Definitions DTS Interrupts Definitions
|
||||
* @{
|
||||
*/
|
||||
#define DTS_IT_TS1_ITE DTS_ITENR_TS1_ITEEN /*!< Enable interrupt flag for end of measure for DTS1 */
|
||||
#define DTS_IT_TS1_ITL DTS_ITENR_TS1_ITLEN /*!< Enable interrupt flag for low threshold for DTS1 */
|
||||
#define DTS_IT_TS1_ITH DTS_ITENR_TS1_ITHEN /*!< Enable interrupt flag for high threshold for DTS1 */
|
||||
#define DTS_IT_TS1_AITE DTS_ITENR_TS1_AITEEN /*!< Enable asynchronous interrupt flag for end of measure for DTS1 */
|
||||
#define DTS_IT_TS1_AITL DTS_ITENR_TS1_AITLEN /*!< Enable asynchronous interrupt flag for low threshold for DTS1 */
|
||||
#define DTS_IT_TS1_AITH DTS_ITENR_TS1_AITHEN /*!< Enable asynchronous interrupt flag for high threshold for DTS1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported macros ---------------------------------------------------------------------------------------------------*/
|
||||
/** @defgroup DTS_Exported_Macros DTS Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset DTS handle state
|
||||
* @param __HANDLE__ DTS handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1U)
|
||||
#define __HAL_DTS_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_DTS_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else /* USE_HAL_DTS_REGISTER_CALLBACKS */
|
||||
#define __HAL_DTS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DTS_STATE_RESET)
|
||||
#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @brief Enable the specified DTS sensor
|
||||
* @param __HANDLE__ DTS handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DTS_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CFGR1, DTS_CFGR1_TS1_EN)
|
||||
|
||||
/**
|
||||
* @brief Disable the specified DTS sensor
|
||||
* @param __HANDLE__ DTS handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DTS_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR1, DTS_CFGR1_TS1_EN)
|
||||
|
||||
/**
|
||||
* @brief Enable the DTS EXTI line in interrupt mode
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DTS_EXTI_WAKEUP_ENABLE_IT() SET_BIT(EXTI->IMR2, DTS_EXTI_LINE_DTS1)
|
||||
|
||||
/**
|
||||
* @brief Disable the DTS EXTI line in interrupt mode
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DTS_EXTI_WAKEUP_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, DTS_EXTI_LINE_DTS1)
|
||||
|
||||
/**
|
||||
* @brief Enable the DTS EXTI Line in event mode
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DTS_EXTI_WAKEUP_ENABLE_EVENT() SET_BIT(EXTI->EMR2, DTS_EXTI_LINE_DTS1)
|
||||
|
||||
/**
|
||||
* @brief Disable the DTS EXTI Line in event mode
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DTS_EXTI_WAKEUP_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, DTS_EXTI_LINE_DTS1)
|
||||
|
||||
/** @brief Checks whether the specified DTS flag is set or not.
|
||||
* @param __HANDLE__ specifies the DTS Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DTS_FLAG_TS1_ITE : interrupt flag for end of measure for DTS1
|
||||
* @arg DTS_FLAG_TS1_ITL : interrupt flag for low threshold for DTS1
|
||||
* @arg DTS_FLAG_TS1_ITH : interrupt flag for high threshold for DTS1
|
||||
* @arg DTS_FLAG_TS1_AITE: asynchronous interrupt flag for end of measure for DTS1
|
||||
* @arg DTS_FLAG_TS1_AITL: asynchronous interrupt flag for low threshold for DTS1
|
||||
* @arg DTS_FLAG_TS1_AITH: asynchronous interrupt flag for high threshold for DTS1
|
||||
* @arg DTS_FLAG_TS1_RDY : Ready flag for DTS1
|
||||
* @retval The new state of __FLAG__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_DTS_GET_FLAG(__HANDLE__, __FLAG__) \
|
||||
(((((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)))? SET : RESET)
|
||||
|
||||
|
||||
/** @brief Clears the specified DTS pending flag.
|
||||
* @param __HANDLE__ specifies the DTS Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DTS_FLAG_TS1_ITE : interrupt flag for end of measure for DTS1
|
||||
* @arg DTS_FLAG_TS1_ITL : interrupt flag for low threshold for DTS1
|
||||
* @arg DTS_FLAG_TS1_ITH : interrupt flag for high threshold for DTS1
|
||||
* @arg DTS_FLAG_TS1_AITE: asynchronous interrupt flag for end of measure for DTS1
|
||||
* @arg DTS_FLAG_TS1_AITL: asynchronous interrupt flag for low threshold for DTS1
|
||||
* @arg DTS_FLAG_TS1_AITH: asynchronous interrupt flag for high threshold for DTS1
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DTS_CLEAR_FLAG(__HANDLE__, __FLAG__) \
|
||||
((__HANDLE__)->Instance->ICIFR = (__FLAG__))
|
||||
|
||||
|
||||
/** @brief Enable the specified DTS interrupt.
|
||||
* @param __HANDLE__ specifies the DTS Handle.
|
||||
* @param __INTERRUPT__ specifies the DTS interrupt source to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DTS_IT_TS1_ITE : interrupt flag for end of measure for DTS1
|
||||
* @arg DTS_IT_TS1_ITL : interrupt flag for low of measure for DTS1
|
||||
* @arg DTS_IT_TS1_ITH : interrupt flag for high of measure for DTS1
|
||||
* @arg DTS_IT_TS1_AITE : asynchronous interrupt flag for end of measure for DTS1
|
||||
* @arg DTS_IT_TS1_AITL : asynchronous interrupt flag for low of measure for DTS1
|
||||
* @arg DTS_IT_TS1_AITH : asynchronous interrupt flag for high of measure for DTS1
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DTS_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
|
||||
SET_BIT((__HANDLE__)->Instance->ITENR, __INTERRUPT__)
|
||||
|
||||
|
||||
/** @brief Disable the specified DTS interrupt.
|
||||
* @param __HANDLE__ specifies the DTS Handle.
|
||||
* @param __INTERRUPT__ specifies the DTS interrupt source to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DTS_IT_TS1_ITE : interrupt flag for end of measure for DTS1
|
||||
* @arg DTS_IT_TS1_ITL : interrupt flag for low of measure for DTS1
|
||||
* @arg DTS_IT_TS1_ITH : interrupt flag for high of measure for DTS1
|
||||
* @arg DTS_IT_TS1_AITE : asynchronous interrupt flag for end of measure for DTS1
|
||||
* @arg DTS_IT_TS1_AITL : asynchronous interrupt flag for low of measure for DTS1
|
||||
* @arg DTS_IT_TS1_AITH : asynchronous interrupt flag for high of measure for DTS1
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DTS_DISABLE_IT(__HANDLE__,__INTERRUPT__) \
|
||||
CLEAR_BIT((__HANDLE__)->Instance->ITENR, __INTERRUPT__)
|
||||
|
||||
|
||||
/** @brief Check whether the specified DTS interrupt source is enabled or not.
|
||||
* @param __HANDLE__ DTS handle.
|
||||
* @param __INTERRUPT__ DTS interrupt source to check
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DTS_IT_TS1_ITE : interrupt flag for end of measure for DTS1
|
||||
* @arg DTS_IT_TS1_ITL : interrupt flag for low of measure for DTS1
|
||||
* @arg DTS_IT_TS1_ITH : interrupt flag for high of measure for DTS1
|
||||
* @arg DTS_IT_TS1_AITE : asynchronous interrupt flag for end of measure for DTS1
|
||||
* @arg DTS_IT_TS1_AITL : asynchronous interrupt flag for low of measure for DTS1
|
||||
* @arg DTS_IT_TS1_AITH : asynchronous interrupt flag for high of measure for DTS1
|
||||
* @retval State of interruption (SET or RESET)
|
||||
*/
|
||||
#define __HAL_DTS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
|
||||
(( ((__HANDLE__)->Instance->ITENR & (__INTERRUPT__)) == (__INTERRUPT__))? SET : RESET)
|
||||
|
||||
|
||||
/** @brief Check whether the specified DTS REFCLK is selected
|
||||
* @param __HANDLE__ DTS handle.
|
||||
* @param __REFCLK__ DTS reference clock to check
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DTS_REFCLKSEL_LSE: Low speed REF clock
|
||||
* @arg DTS_REFCLKSEL_PCLK: High speed REF clock
|
||||
* @retval State of the REF clock tested (SET or RESET)
|
||||
*/
|
||||
#define __HAL_DTS_GET_REFCLK(__HANDLE__, __REFCLK__) \
|
||||
((((__HANDLE__)->Instance->CFGR1 & (__REFCLK__)) == (__REFCLK__))? SET : RESET)
|
||||
|
||||
/** @brief Get Trigger
|
||||
* @param __HANDLE__ DTS handle.
|
||||
* @retval One of the following trigger
|
||||
* DTS_TRIGGER_HW_NONE : No HW trigger (SW trigger)
|
||||
* DTS_TRIGGER_LPTIMER1: LPTIMER1 trigger
|
||||
* DTS_TRIGGER_LPTIMER2: LPTIMER2 trigger
|
||||
* DTS_TRIGGER_LPTIMER3: LPTIMER3 trigger
|
||||
* DTS_TRIGGER_EXTI13 : EXTI13 trigger
|
||||
*/
|
||||
#define __HAL_DTS_GET_TRIGGER(__HANDLE__) ((__HANDLE__)->Instance->CFGR1 & (DTS_CFGR1_TS1_INTRIG_SEL))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions ------------------------------------------------------------------------------------------------*/
|
||||
/** @addtogroup DTS_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DTS_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions */
|
||||
HAL_StatusTypeDef HAL_DTS_Init(DTS_HandleTypeDef *hdts);
|
||||
HAL_StatusTypeDef HAL_DTS_DeInit(DTS_HandleTypeDef *hdts);
|
||||
void HAL_DTS_MspInit(DTS_HandleTypeDef *hdts);
|
||||
void HAL_DTS_MspDeInit(DTS_HandleTypeDef *hdts);
|
||||
#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1U)
|
||||
HAL_StatusTypeDef HAL_DTS_RegisterCallback(DTS_HandleTypeDef *hdts,
|
||||
HAL_DTS_CallbackIDTypeDef CallbackID,
|
||||
pDTS_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_DTS_UnRegisterCallback(DTS_HandleTypeDef *hdts,
|
||||
HAL_DTS_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup DTS_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions */
|
||||
HAL_StatusTypeDef HAL_DTS_Start(DTS_HandleTypeDef *hdts);
|
||||
HAL_StatusTypeDef HAL_DTS_Stop(DTS_HandleTypeDef *hdts);
|
||||
HAL_StatusTypeDef HAL_DTS_GetTemperature(DTS_HandleTypeDef *hdts, int32_t *Temperature);
|
||||
HAL_StatusTypeDef HAL_DTS_Start_IT(DTS_HandleTypeDef *hdts);
|
||||
HAL_StatusTypeDef HAL_DTS_Stop_IT(DTS_HandleTypeDef *hdts);
|
||||
void HAL_DTS_IRQHandler(DTS_HandleTypeDef *hdts);
|
||||
HAL_DTS_StateTypeDef HAL_DTS_GetState(const DTS_HandleTypeDef *hdts);
|
||||
|
||||
/* Callback in Interrupt mode */
|
||||
void HAL_DTS_EndCallback(DTS_HandleTypeDef *hdts);
|
||||
void HAL_DTS_LowCallback(DTS_HandleTypeDef *hdts);
|
||||
void HAL_DTS_HighCallback(DTS_HandleTypeDef *hdts);
|
||||
void HAL_DTS_AsyncEndCallback(DTS_HandleTypeDef *hdts);
|
||||
void HAL_DTS_AsyncLowCallback(DTS_HandleTypeDef *hdts);
|
||||
void HAL_DTS_AsyncHighCallback(DTS_HandleTypeDef *hdts);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -----------------------------------------------------------------------------------------------------*/
|
||||
/* Private constants -------------------------------------------------------------------------------------------------*/
|
||||
/** @defgroup DTS_Private_Constants DTS Private Constants
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup DTS_ExtiLine DTS EXTI Lines
|
||||
* @{
|
||||
*/
|
||||
#define DTS_EXTI_LINE_DTS1 (EXTI_IMR2_IM50) /*!< EXTI line 50 connected to DTS1 output */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ----------------------------------------------------------------------------------------------------*/
|
||||
/** @defgroup DTS_Private_Macros DTS Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DTS_IS_DTS_Definitions DTS Private macros to check input parameters
|
||||
* @{
|
||||
*/
|
||||
#define IS_DTS_QUICKMEAS(__SEL__) (((__SEL__) == DTS_QUICKMEAS_DISABLE) || \
|
||||
((__SEL__) == DTS_QUICKMEAS_ENABLE))
|
||||
|
||||
#define IS_DTS_REFCLK(__SEL__) (((__SEL__) == DTS_REFCLKSEL_LSE) || \
|
||||
((__SEL__) == DTS_REFCLKSEL_PCLK))
|
||||
#if defined(LPTIM3)
|
||||
#define IS_DTS_TRIGGERINPUT(__INPUT__) (((__INPUT__) == DTS_TRIGGER_HW_NONE) || \
|
||||
((__INPUT__) == DTS_TRIGGER_LPTIMER1) || \
|
||||
((__INPUT__) == DTS_TRIGGER_LPTIMER2) || \
|
||||
((__INPUT__) == DTS_TRIGGER_LPTIMER3) || \
|
||||
((__INPUT__) == DTS_TRIGGER_EXTI13))
|
||||
#else
|
||||
#define IS_DTS_TRIGGERINPUT(__INPUT__) (((__INPUT__) == DTS_TRIGGER_HW_NONE) || \
|
||||
((__INPUT__) == DTS_TRIGGER_LPTIMER1) || \
|
||||
((__INPUT__) == DTS_TRIGGER_LPTIMER2) || \
|
||||
((__INPUT__) == DTS_TRIGGER_EXTI13))
|
||||
#endif /* defined(LPTIM3) */
|
||||
|
||||
#define IS_DTS_THRESHOLD(__THRESHOLD__) ((__THRESHOLD__) <= 0xFFFFUL)
|
||||
|
||||
#define IS_DTS_DIVIDER_RATIO_NUMBER(__NUMBER__) ((__NUMBER__) <= 127UL)
|
||||
|
||||
#define IS_DTS_SAMPLINGTIME(__CYCLE__) (((__CYCLE__) == DTS_SMP_TIME_1_CYCLE) || \
|
||||
((__CYCLE__) == DTS_SMP_TIME_2_CYCLE) || \
|
||||
((__CYCLE__) == DTS_SMP_TIME_3_CYCLE) || \
|
||||
((__CYCLE__) == DTS_SMP_TIME_4_CYCLE) || \
|
||||
((__CYCLE__) == DTS_SMP_TIME_5_CYCLE) || \
|
||||
((__CYCLE__) == DTS_SMP_TIME_6_CYCLE) || \
|
||||
((__CYCLE__) == DTS_SMP_TIME_7_CYCLE) || \
|
||||
((__CYCLE__) == DTS_SMP_TIME_8_CYCLE) || \
|
||||
((__CYCLE__) == DTS_SMP_TIME_9_CYCLE) || \
|
||||
((__CYCLE__) == DTS_SMP_TIME_10_CYCLE) || \
|
||||
((__CYCLE__) == DTS_SMP_TIME_11_CYCLE) || \
|
||||
((__CYCLE__) == DTS_SMP_TIME_12_CYCLE) || \
|
||||
((__CYCLE__) == DTS_SMP_TIME_13_CYCLE) || \
|
||||
((__CYCLE__) == DTS_SMP_TIME_14_CYCLE) || \
|
||||
((__CYCLE__) == DTS_SMP_TIME_15_CYCLE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions -------------------------------------------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* DTS */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H5xx_HAL_DTS_H */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,368 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h5xx_hal_eth_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of ETH HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H5xx_HAL_ETH_EX_H
|
||||
#define STM32H5xx_HAL_ETH_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(ETH)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h5xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H5xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ETHEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup ETHEx_Exported_Types ETHEx Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief ETH RX VLAN structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
FunctionalState InnerVLANTagInStatus; /*!< Enables or disables Inner VLAN Tag in Rx Status */
|
||||
|
||||
uint32_t StripInnerVLANTag; /*!< Sets the Inner VLAN Tag Stripping on Receive
|
||||
This parameter can be a value of
|
||||
@ref ETHEx_Rx_Inner_VLAN_Tag_Stripping */
|
||||
|
||||
FunctionalState InnerVLANTag; /*!< Enables or disables Inner VLAN Tag */
|
||||
|
||||
FunctionalState DoubleVLANProcessing; /*!< Enable or Disable double VLAN processing */
|
||||
|
||||
FunctionalState VLANTagHashTableMatch; /*!< Enable or Disable VLAN Tag Hash Table Match */
|
||||
|
||||
FunctionalState VLANTagInStatus; /*!< Enable or Disable VLAN Tag in Rx status */
|
||||
|
||||
uint32_t StripVLANTag; /*!< Set the VLAN Tag Stripping on Receive
|
||||
This parameter can be a value of @ref ETHEx_Rx_VLAN_Tag_Stripping */
|
||||
|
||||
uint32_t VLANTypeCheck; /*!< Enable or Disable VLAN Type Check
|
||||
This parameter can be a value of @ref ETHEx_VLAN_Type_Check */
|
||||
|
||||
FunctionalState VLANTagInverceMatch; /*!< Enable or disable VLAN Tag Inverse Match */
|
||||
} ETH_RxVLANConfigTypeDef;
|
||||
/**
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief ETH TX VLAN structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
FunctionalState SourceTxDesc; /*!< Enable or Disable VLAN tag source from DMA tx descriptors */
|
||||
|
||||
FunctionalState SVLANType; /*!< Enable or Disable insertion of SVLAN type */
|
||||
|
||||
uint32_t VLANTagControl; /*!< Sets the VLAN tag control in tx packets
|
||||
This parameter can be a value of @ref ETHEx_VLAN_Tag_Control */
|
||||
} ETH_TxVLANConfigTypeDef;
|
||||
/**
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief ETH L3 filter structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Protocol; /*!< Sets the L3 filter protocol to IPv4 or IPv6
|
||||
This parameter can be a value of @ref ETHEx_L3_Protocol */
|
||||
|
||||
uint32_t SrcAddrFilterMatch; /*!< Sets the L3 filter source address match
|
||||
This parameter can be a value of @ref ETHEx_L3_Source_Match */
|
||||
|
||||
uint32_t DestAddrFilterMatch; /*!< Sets the L3 filter destination address match
|
||||
This parameter can be a value of @ref ETHEx_L3_Destination_Match */
|
||||
|
||||
uint32_t SrcAddrHigherBitsMatch; /*!< Sets the L3 filter source address higher bits match
|
||||
This parameter can be a value from 0 to 31 */
|
||||
|
||||
uint32_t DestAddrHigherBitsMatch; /*!< Sets the L3 filter destination address higher bits match
|
||||
This parameter can be a value from 0 to 31 */
|
||||
|
||||
uint32_t Ip4SrcAddr; /*!< Sets the L3 filter IPv4 source address if IPv4 protocol is used
|
||||
This parameter can be a value from 0x0 to 0xFFFFFFFF */
|
||||
|
||||
uint32_t Ip4DestAddr; /*!< Sets the L3 filter IPv4 destination address if IPv4 protocol is used
|
||||
This parameter can be a value from 0 to 0xFFFFFFFF */
|
||||
|
||||
uint32_t Ip6Addr[4]; /*!< Sets the L3 filter IPv6 address if IPv6 protocol is used
|
||||
This parameter must be a table of 4 words (4* 32 bits) */
|
||||
} ETH_L3FilterConfigTypeDef;
|
||||
/**
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief ETH L4 filter structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Protocol; /*!< Sets the L4 filter protocol to TCP or UDP
|
||||
This parameter can be a value of @ref ETHEx_L4_Protocol */
|
||||
|
||||
uint32_t SrcPortFilterMatch; /*!< Sets the L4 filter source port match
|
||||
This parameter can be a value of @ref ETHEx_L4_Source_Match */
|
||||
|
||||
uint32_t DestPortFilterMatch; /*!< Sets the L4 filter destination port match
|
||||
This parameter can be a value of @ref ETHEx_L4_Destination_Match */
|
||||
|
||||
uint32_t SourcePort; /*!< Sets the L4 filter source port
|
||||
This parameter must be a value from 0x0 to 0xFFFF */
|
||||
|
||||
uint32_t DestinationPort; /*!< Sets the L4 filter destination port
|
||||
This parameter must be a value from 0x0 to 0xFFFF */
|
||||
} ETH_L4FilterConfigTypeDef;
|
||||
/**
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup ETHEx_Exported_Constants ETHEx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup ETHEx_LPI_Event ETHEx LPI Event
|
||||
* @{
|
||||
*/
|
||||
#define ETH_TX_LPI_ENTRY ETH_MACLCSR_TLPIEN
|
||||
#define ETH_TX_LPI_EXIT ETH_MACLCSR_TLPIEX
|
||||
#define ETH_RX_LPI_ENTRY ETH_MACLCSR_RLPIEN
|
||||
#define ETH_RX_LPI_EXIT ETH_MACLCSR_RLPIEX
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ETHEx_L3_Filter ETHEx L3 Filter
|
||||
* @{
|
||||
*/
|
||||
#define ETH_L3_FILTER_0 0x00000000U
|
||||
#define ETH_L3_FILTER_1 0x0000000CU
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ETHEx_L4_Filter ETHEx L4 Filter
|
||||
* @{
|
||||
*/
|
||||
#define ETH_L4_FILTER_0 0x00000000U
|
||||
#define ETH_L4_FILTER_1 0x0000000CU
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ETHEx_L3_Protocol ETHEx L3 Protocol
|
||||
* @{
|
||||
*/
|
||||
#define ETH_L3_IPV6_MATCH ETH_MACL3L4CR_L3PEN
|
||||
#define ETH_L3_IPV4_MATCH 0x00000000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ETHEx_L3_Source_Match ETHEx L3 Source Match
|
||||
* @{
|
||||
*/
|
||||
#define ETH_L3_SRC_ADDR_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L3SAM
|
||||
#define ETH_L3_SRC_ADDR_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L3SAM | ETH_MACL3L4CR_L3SAIM)
|
||||
#define ETH_L3_SRC_ADDR_MATCH_DISABLE 0x00000000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ETHEx_L3_Destination_Match ETHEx L3 Destination Match
|
||||
* @{
|
||||
*/
|
||||
#define ETH_L3_DEST_ADDR_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L3DAM
|
||||
#define ETH_L3_DEST_ADDR_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L3DAM | ETH_MACL3L4CR_L3DAIM)
|
||||
#define ETH_L3_DEST_ADDR_MATCH_DISABLE 0x00000000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ETHEx_L4_Protocol ETHEx L4 Protocol
|
||||
* @{
|
||||
*/
|
||||
#define ETH_L4_UDP_MATCH ETH_MACL3L4CR_L4PEN
|
||||
#define ETH_L4_TCP_MATCH 0x00000000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ETHEx_L4_Source_Match ETHEx L4 Source Match
|
||||
* @{
|
||||
*/
|
||||
#define ETH_L4_SRC_PORT_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L4SPM
|
||||
#define ETH_L4_SRC_PORT_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L4SPM |ETH_MACL3L4CR_L4SPIM)
|
||||
#define ETH_L4_SRC_PORT_MATCH_DISABLE 0x00000000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ETHEx_L4_Destination_Match ETHEx L4 Destination Match
|
||||
* @{
|
||||
*/
|
||||
#define ETH_L4_DEST_PORT_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L4DPM
|
||||
#define ETH_L4_DEST_PORT_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM)
|
||||
#define ETH_L4_DEST_PORT_MATCH_DISABLE 0x00000000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ETHEx_Rx_Inner_VLAN_Tag_Stripping ETHEx Rx Inner VLAN Tag Stripping
|
||||
* @{
|
||||
*/
|
||||
#define ETH_INNERVLANTAGRXSTRIPPING_NONE ETH_MACVTR_EIVLS_DONOTSTRIP
|
||||
#define ETH_INNERVLANTAGRXSTRIPPING_IFPASS ETH_MACVTR_EIVLS_STRIPIFPASS
|
||||
#define ETH_INNERVLANTAGRXSTRIPPING_IFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS
|
||||
#define ETH_INNERVLANTAGRXSTRIPPING_ALWAYS ETH_MACVTR_EIVLS_ALWAYSSTRIP
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ETHEx_Rx_VLAN_Tag_Stripping ETHEx Rx VLAN Tag Stripping
|
||||
* @{
|
||||
*/
|
||||
#define ETH_VLANTAGRXSTRIPPING_NONE ETH_MACVTR_EVLS_DONOTSTRIP
|
||||
#define ETH_VLANTAGRXSTRIPPING_IFPASS ETH_MACVTR_EVLS_STRIPIFPASS
|
||||
#define ETH_VLANTAGRXSTRIPPING_IFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS
|
||||
#define ETH_VLANTAGRXSTRIPPING_ALWAYS ETH_MACVTR_EVLS_ALWAYSSTRIP
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ETHEx_VLAN_Type_Check ETHEx VLAN Type Check
|
||||
* @{
|
||||
*/
|
||||
#define ETH_VLANTYPECHECK_DISABLE ETH_MACVTR_DOVLTC
|
||||
#define ETH_VLANTYPECHECK_SVLAN (ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL)
|
||||
#define ETH_VLANTYPECHECK_CVLAN 0x00000000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ETHEx_VLAN_Tag_Control ETHEx_VLAN_Tag_Control
|
||||
* @{
|
||||
*/
|
||||
#define ETH_VLANTAGCONTROL_NONE (ETH_MACVIR_VLP | ETH_MACVIR_VLC_NOVLANTAG)
|
||||
#define ETH_VLANTAGCONTROL_DELETE (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGDELETE)
|
||||
#define ETH_VLANTAGCONTROL_INSERT (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGINSERT)
|
||||
#define ETH_VLANTAGCONTROL_REPLACE (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGREPLACE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ETHEx_Tx_VLAN_Tag ETHEx Tx VLAN Tag
|
||||
* @{
|
||||
*/
|
||||
#define ETH_INNER_TX_VLANTAG 0x00000001U
|
||||
#define ETH_OUTER_TX_VLANTAG 0x00000000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup ETHEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ETHEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* MAC ARP Offloading APIs ***************************************************/
|
||||
void HAL_ETHEx_EnableARPOffload(ETH_HandleTypeDef *heth);
|
||||
void HAL_ETHEx_DisableARPOffload(ETH_HandleTypeDef *heth);
|
||||
void HAL_ETHEx_SetARPAddressMatch(ETH_HandleTypeDef *heth, uint32_t IpAddress);
|
||||
|
||||
/* MAC L3 L4 Filtering APIs ***************************************************/
|
||||
void HAL_ETHEx_EnableL3L4Filtering(ETH_HandleTypeDef *heth);
|
||||
void HAL_ETHEx_DisableL3L4Filtering(ETH_HandleTypeDef *heth);
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
|
||||
ETH_L3FilterConfigTypeDef *pL3FilterConfig);
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
|
||||
ETH_L4FilterConfigTypeDef *pL4FilterConfig);
|
||||
HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
|
||||
ETH_L3FilterConfigTypeDef *pL3FilterConfig);
|
||||
HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
|
||||
ETH_L4FilterConfigTypeDef *pL4FilterConfig);
|
||||
|
||||
/* MAC VLAN Processing APIs ************************************************/
|
||||
void HAL_ETHEx_EnableVLANProcessing(ETH_HandleTypeDef *heth);
|
||||
void HAL_ETHEx_DisableVLANProcessing(ETH_HandleTypeDef *heth);
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig);
|
||||
HAL_StatusTypeDef HAL_ETHEx_SetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig);
|
||||
void HAL_ETHEx_SetVLANHashTable(ETH_HandleTypeDef *heth, uint32_t VLANHashTable);
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag,
|
||||
ETH_TxVLANConfigTypeDef *pVlanConfig);
|
||||
HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag,
|
||||
ETH_TxVLANConfigTypeDef *pVlanConfig);
|
||||
void HAL_ETHEx_SetTxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t VLANTag, uint32_t VLANIdentifier);
|
||||
|
||||
/* Energy Efficient Ethernet APIs *********************************************/
|
||||
void HAL_ETHEx_EnterLPIMode(ETH_HandleTypeDef *heth, FunctionalState TxAutomate,
|
||||
FunctionalState TxClockStop);
|
||||
void HAL_ETHEx_ExitLPIMode(ETH_HandleTypeDef *heth);
|
||||
uint32_t HAL_ETHEx_GetMACLPIEvent(const ETH_HandleTypeDef *heth);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* ETH */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H5xx_HAL_ETH_EX_H */
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,410 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h5xx_hal_exti.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of EXTI HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H5xx_HAL_EXTI_H
|
||||
#define STM32H5xx_HAL_EXTI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h5xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H5xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI EXTI
|
||||
* @brief EXTI HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup EXTI_Exported_Types EXTI Exported Types
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_EXTI_COMMON_CB_ID = 0x00U,
|
||||
HAL_EXTI_RISING_CB_ID = 0x01U,
|
||||
HAL_EXTI_FALLING_CB_ID = 0x02U,
|
||||
} EXTI_CallbackIDTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief EXTI Handle structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Line; /*!< Exti line number */
|
||||
void (* RisingCallback)(void); /*!< Exti rising callback */
|
||||
void (* FallingCallback)(void); /*!< Exti falling callback */
|
||||
} EXTI_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @brief EXTI Configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Line; /*!< The Exti line to be configured. This parameter
|
||||
can be a value of @ref EXTI_Line */
|
||||
uint32_t Mode; /*!< The Exit Mode to be configured for a core.
|
||||
This parameter can be a combination of @ref EXTI_Mode */
|
||||
uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter
|
||||
can be a value of @ref EXTI_Trigger */
|
||||
uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured.
|
||||
This parameter is only possible for line 0 to 15. It
|
||||
can be a value of @ref EXTI_GPIOSel */
|
||||
} EXTI_ConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Line EXTI Line
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | 0x00U)
|
||||
#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | 0x01U)
|
||||
#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | 0x02U)
|
||||
#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | 0x03U)
|
||||
#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | 0x04U)
|
||||
#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | 0x05U)
|
||||
#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | 0x06U)
|
||||
#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | 0x07U)
|
||||
#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | 0x08U)
|
||||
#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | 0x09U)
|
||||
#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | 0x0AU)
|
||||
#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | 0x0BU)
|
||||
#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | 0x0CU)
|
||||
#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | 0x0DU)
|
||||
#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | 0x0EU)
|
||||
#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | 0x0FU)
|
||||
#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | 0x10U)
|
||||
#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_REG1 | 0x11U)
|
||||
#define EXTI_LINE_18 (EXTI_DIRECT | EXTI_REG1 | 0x12U)
|
||||
#define EXTI_LINE_19 (EXTI_DIRECT | EXTI_REG1 | 0x13U)
|
||||
#define EXTI_LINE_20 (EXTI_DIRECT | EXTI_REG1 | 0x14U)
|
||||
#define EXTI_LINE_21 (EXTI_DIRECT | EXTI_REG1 | 0x15U)
|
||||
#define EXTI_LINE_22 (EXTI_DIRECT | EXTI_REG1 | 0x16U)
|
||||
#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | 0x17U)
|
||||
#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | 0x18U)
|
||||
#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | 0x19U)
|
||||
#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | 0x1AU)
|
||||
#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | 0x1BU)
|
||||
#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | 0x1CU)
|
||||
#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | 0x1DU)
|
||||
#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | 0x1EU)
|
||||
#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | 0x1FU)
|
||||
#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | 0x00U)
|
||||
#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | 0x01U)
|
||||
#define EXTI_LINE_34 (EXTI_DIRECT | EXTI_REG2 | 0x02U)
|
||||
#define EXTI_LINE_35 (EXTI_DIRECT | EXTI_REG2 | 0x03U)
|
||||
#define EXTI_LINE_36 (EXTI_DIRECT | EXTI_REG2 | 0x04U)
|
||||
#define EXTI_LINE_37 (EXTI_DIRECT | EXTI_REG2 | 0x05U)
|
||||
#define EXTI_LINE_38 (EXTI_DIRECT | EXTI_REG2 | 0x06U)
|
||||
#define EXTI_LINE_39 (EXTI_DIRECT | EXTI_REG2 | 0x07U)
|
||||
#define EXTI_LINE_40 (EXTI_DIRECT | EXTI_REG2 | 0x08U)
|
||||
#define EXTI_LINE_41 (EXTI_DIRECT | EXTI_REG2 | 0x09U)
|
||||
#define EXTI_LINE_42 (EXTI_DIRECT | EXTI_REG2 | 0x0AU)
|
||||
#define EXTI_LINE_43 (EXTI_DIRECT | EXTI_REG2 | 0x0BU)
|
||||
#define EXTI_LINE_44 (EXTI_DIRECT | EXTI_REG2 | 0x0CU)
|
||||
#define EXTI_LINE_45 (EXTI_DIRECT | EXTI_REG2 | 0x0DU)
|
||||
#if defined(ETH)
|
||||
#define EXTI_LINE_46 (EXTI_CONFIG | EXTI_REG2 | 0x0EU)
|
||||
#endif /* ETH */
|
||||
#define EXTI_LINE_47 (EXTI_DIRECT | EXTI_REG2 | 0x0FU)
|
||||
#define EXTI_LINE_48 (EXTI_DIRECT | EXTI_REG2 | 0x10U)
|
||||
#define EXTI_LINE_49 (EXTI_DIRECT | EXTI_REG2 | 0x11U)
|
||||
#define EXTI_LINE_50 (EXTI_CONFIG | EXTI_REG2 | 0x12U)
|
||||
#define EXTI_LINE_51 (EXTI_DIRECT | EXTI_REG2 | 0x13U)
|
||||
#define EXTI_LINE_52 (EXTI_DIRECT | EXTI_REG2 | 0x14U)
|
||||
#define EXTI_LINE_53 (EXTI_CONFIG | EXTI_REG2 | 0x15U)
|
||||
#define EXTI_LINE_54 (EXTI_DIRECT | EXTI_REG2 | 0x16U)
|
||||
#define EXTI_LINE_55 (EXTI_DIRECT | EXTI_REG2 | 0x17U)
|
||||
#define EXTI_LINE_56 (EXTI_DIRECT | EXTI_REG2 | 0x18U)
|
||||
#define EXTI_LINE_57 (EXTI_DIRECT | EXTI_REG2 | 0x19U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Mode EXTI Mode
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_MODE_NONE 0x00000000U
|
||||
#define EXTI_MODE_INTERRUPT 0x00000001U
|
||||
#define EXTI_MODE_EVENT 0x00000002U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Trigger EXTI Trigger
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_TRIGGER_NONE 0x00000000U
|
||||
#define EXTI_TRIGGER_RISING 0x00000001U
|
||||
#define EXTI_TRIGGER_FALLING 0x00000002U
|
||||
#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_GPIOSel EXTI GPIOSel
|
||||
* @brief
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_GPIOA 0x00000000U
|
||||
#define EXTI_GPIOB 0x00000001U
|
||||
#define EXTI_GPIOC 0x00000002U
|
||||
#define EXTI_GPIOD 0x00000003U
|
||||
#define EXTI_GPIOE 0x00000004U
|
||||
#define EXTI_GPIOF 0x00000005U
|
||||
#define EXTI_GPIOG 0x00000006U
|
||||
#define EXTI_GPIOH 0x00000007U
|
||||
#define EXTI_GPIOI 0x00000008U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Line_attributes EXTI line attributes
|
||||
* @brief EXTI line secure or non-secure and privileged or non-privileged attributes
|
||||
* @note secure and non-secure attributes are only available from secure state when the system
|
||||
* implement the security (TZEN=1)
|
||||
* @{
|
||||
*/
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
/*!< Secure line attribute */
|
||||
#define EXTI_LINE_SEC (EXTI_LINE_ATTR_SEC_MASK | 0x00000001U)
|
||||
/*!< Non-secure line attribute */
|
||||
#define EXTI_LINE_NSEC (EXTI_LINE_ATTR_SEC_MASK | 0x00000000U)
|
||||
#endif /* __ARM_FEATURE_CMSE */
|
||||
/*!< Privileged line attribute */
|
||||
#define EXTI_LINE_PRIV (EXTI_LINE_ATTR_PRIV_MASK | 0x00000002U)
|
||||
/*!< Non-privileged line attribute */
|
||||
#define EXTI_LINE_NPRIV (EXTI_LINE_ATTR_PRIV_MASK | 0x00000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup EXTI_Security_Privilege_Configuration EXTI Security Privilege Configuration
|
||||
* @brief EXTI security and privilege configurations
|
||||
* @{
|
||||
*/
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
/* Security and privilege configuration open, can be modified */
|
||||
#define EXTI_ATTRIBUTES_UNLOCKED 0x00000000U
|
||||
/* Security and privilege configuration locked, can no longer be modified */
|
||||
#define EXTI_ATTRIBUTES_LOCKED 0x00000001U
|
||||
#endif /* __ARM_FEATURE_CMSE */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants --------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Private_Constants EXTI Private Constants
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief EXTI Line property definition
|
||||
*/
|
||||
#define EXTI_PROPERTY_SHIFT 24U
|
||||
#define EXTI_DIRECT (0x01U << EXTI_PROPERTY_SHIFT)
|
||||
#define EXTI_CONFIG (0x02U << EXTI_PROPERTY_SHIFT)
|
||||
#define EXTI_GPIO ((0x04U << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
|
||||
#define EXTI_RESERVED (0x08U << EXTI_PROPERTY_SHIFT)
|
||||
#define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
|
||||
|
||||
/**
|
||||
* @brief EXTI Register and bit usage
|
||||
*/
|
||||
#define EXTI_REG_SHIFT 16U
|
||||
#define EXTI_REG1 (0x00U << EXTI_REG_SHIFT)
|
||||
#define EXTI_REG2 (0x01U << EXTI_REG_SHIFT)
|
||||
#define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2)
|
||||
#define EXTI_PIN_MASK 0x0000001FU
|
||||
|
||||
/**
|
||||
* @brief EXTI Mask for interrupt & event mode
|
||||
*/
|
||||
#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
|
||||
|
||||
/**
|
||||
* @brief EXTI Mask for trigger possibilities
|
||||
*/
|
||||
#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
|
||||
|
||||
/**
|
||||
* @brief EXTI Line number
|
||||
*/
|
||||
#define EXTI_LINE_NB 58U
|
||||
|
||||
/**
|
||||
* @brief EXTI Mask for secure & privilege attributes
|
||||
*/
|
||||
#define EXTI_LINE_ATTR_SEC_MASK 0x100U
|
||||
#define EXTI_LINE_ATTR_PRIV_MASK 0x200U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Private_Macros EXTI Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | \
|
||||
EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00U) \
|
||||
&&((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \
|
||||
(((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
|
||||
(((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
|
||||
(((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \
|
||||
(((EXTI_LINE_NB / 32U) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32U))))
|
||||
|
||||
#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00U) && \
|
||||
(((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00U))
|
||||
|
||||
#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00U)
|
||||
|
||||
#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) (((__EXTI_LINE__) == EXTI_TRIGGER_RISING) || \
|
||||
((__EXTI_LINE__) == EXTI_TRIGGER_FALLING))
|
||||
|
||||
#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00U)
|
||||
|
||||
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
|
||||
((__PORT__) == EXTI_GPIOB) || \
|
||||
((__PORT__) == EXTI_GPIOC) || \
|
||||
((__PORT__) == EXTI_GPIOD) || \
|
||||
((__PORT__) == EXTI_GPIOE) || \
|
||||
((__PORT__) == EXTI_GPIOF) || \
|
||||
((__PORT__) == EXTI_GPIOG) || \
|
||||
((__PORT__) == EXTI_GPIOH) || \
|
||||
((__PORT__) == EXTI_GPIOI))
|
||||
|
||||
#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16U)
|
||||
|
||||
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
|
||||
#define IS_EXTI_LINE_ATTRIBUTES(__ATTRIBUTES__) (((((__ATTRIBUTES__) & EXTI_LINE_SEC) == EXTI_LINE_SEC) || \
|
||||
(((__ATTRIBUTES__) & EXTI_LINE_NSEC) == EXTI_LINE_NSEC) || \
|
||||
(((__ATTRIBUTES__) & EXTI_LINE_PRIV) == EXTI_LINE_PRIV) || \
|
||||
(((__ATTRIBUTES__) & EXTI_LINE_NPRIV) == EXTI_LINE_NPRIV)) && \
|
||||
(((__ATTRIBUTES__) & ~(EXTI_LINE_SEC|EXTI_LINE_NSEC|EXTI_LINE_PRIV| \
|
||||
EXTI_LINE_NPRIV)) == 0U))
|
||||
|
||||
#else
|
||||
|
||||
#define IS_EXTI_LINE_ATTRIBUTES(__ATTRIBUTES__) (((((__ATTRIBUTES__) & EXTI_LINE_PRIV) == EXTI_LINE_PRIV) || \
|
||||
(((__ATTRIBUTES__) & EXTI_LINE_NPRIV) == EXTI_LINE_NPRIV)) && \
|
||||
(((__ATTRIBUTES__) & ~(EXTI_LINE_PRIV|EXTI_LINE_NPRIV)) == 0U))
|
||||
|
||||
#endif /* __ARM_FEATURE_CMSE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
|
||||
* @brief EXTI Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
|
||||
* @brief Configuration functions
|
||||
* @{
|
||||
*/
|
||||
/* Configuration functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
|
||||
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
|
||||
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(const EXTI_HandleTypeDef *hexti);
|
||||
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID,
|
||||
void (*pPendingCbfn)(void));
|
||||
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
|
||||
* @brief IO operation functions
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
void HAL_EXTI_IRQHandler(const EXTI_HandleTypeDef *hexti);
|
||||
uint32_t HAL_EXTI_GetPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge);
|
||||
void HAL_EXTI_ClearPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge);
|
||||
void HAL_EXTI_GenerateSWI(const EXTI_HandleTypeDef *hexti);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI_Exported_Functions_Group3 EXTI line attributes management functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* EXTI line attributes management functions **********************************/
|
||||
void HAL_EXTI_ConfigLineAttributes(uint32_t ExtiLine, uint32_t LineAttributes);
|
||||
HAL_StatusTypeDef HAL_EXTI_GetConfigLineAttributes(uint32_t ExtiLine, uint32_t *pLineAttributes);
|
||||
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
HAL_StatusTypeDef HAL_EXTI_LockConfigAttributes(void);
|
||||
HAL_StatusTypeDef HAL_EXTI_GetLockConfigAttributes(uint32_t *const pLockState);
|
||||
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H5xx_HAL_EXTI_H */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,810 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h5xx_hal_flash.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of FLASH HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H5xx_HAL_FLASH_H
|
||||
#define STM32H5xx_HAL_FLASH_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h5xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H5xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Types FLASH Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FLASH handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
HAL_LockTypeDef Lock; /*!< FLASH locking object */
|
||||
|
||||
uint32_t ErrorCode; /*!< FLASH error code */
|
||||
|
||||
uint32_t ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not
|
||||
in IT context */
|
||||
|
||||
uint32_t Address; /*!< Internal variable to save address selected for program */
|
||||
|
||||
uint32_t Bank; /*!< Internal variable to save current bank selected during erase in
|
||||
IT context */
|
||||
|
||||
uint32_t Sector; /*!< Internal variable to define the current sector which is erasing */
|
||||
|
||||
uint32_t NbSectorsToErase; /*!< Internal variable to save the remaining sectors to erase in
|
||||
IT context */
|
||||
|
||||
} FLASH_ProcessTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Flag_definition FLASH Flag definition
|
||||
* @brief Flag definition
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
|
||||
#define FLASH_FLAG_WBNE FLASH_SR_WBNE /*!< FLASH Write Buffer Not Empty flag */
|
||||
#define FLASH_FLAG_DBNE FLASH_SR_DBNE /*!< FLASH data Buffer Not Empty flag */
|
||||
#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End Of operation flag */
|
||||
#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write Protection Error flag */
|
||||
#define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< FLASH Program Sequence Error flag */
|
||||
#define FLASH_FLAG_STRBERR FLASH_SR_STRBERR /*!< FLASH Strobe Error flag */
|
||||
#define FLASH_FLAG_INCERR FLASH_SR_INCERR /*!< FLASH Inconsistency Error flag */
|
||||
#if defined (FLASH_SR_OBKERR)
|
||||
#define FLASH_FLAG_OBKERR FLASH_SR_OBKERR /*!< FLASH OBK Error flag */
|
||||
#define FLASH_FLAG_OBKWERR FLASH_SR_OBKWERR /*!< FLASH OBK Write Error flag */
|
||||
#endif /* FLASH_SR_OBKERR */
|
||||
#define FLASH_FLAG_OPTCHANGEERR FLASH_SR_OPTCHANGEERR /*!< FLASH Option Byte change Error flag */
|
||||
#define FLASH_FLAG_ECCC FLASH_ECCR_ECCC /*!< FLASH ECC Correction flag */
|
||||
#define FLASH_FLAG_ECCD FLASH_ECCR_ECCD /*!< FLASH ECC Detection flag */
|
||||
|
||||
#if defined (FLASH_SR_OBKERR)
|
||||
#define FLASH_FLAG_SR_ERRORS (FLASH_SR_WRPERR | FLASH_SR_PGSERR | \
|
||||
FLASH_SR_STRBERR | FLASH_SR_INCERR | \
|
||||
FLASH_SR_OBKERR | FLASH_SR_OBKWERR | \
|
||||
FLASH_SR_OPTCHANGEERR)
|
||||
#else
|
||||
#define FLASH_FLAG_SR_ERRORS (FLASH_SR_WRPERR | FLASH_SR_PGSERR | \
|
||||
FLASH_SR_STRBERR | FLASH_SR_INCERR | \
|
||||
FLASH_SR_OPTCHANGEERR)
|
||||
#endif /* FLASH_SR_OBKERR */
|
||||
#define FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)
|
||||
#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_SR_ERRORS | FLASH_FLAG_ECCR_ERRORS) /*!< All FLASH error flags */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Interrupt_definition FLASH Interrupts definition
|
||||
* @brief FLASH Interrupt definition
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation interrupt enable */
|
||||
#define FLASH_IT_WRPERR FLASH_CR_WRPERRIE /*!< Write Protection Error interrupt enable */
|
||||
#define FLASH_IT_PGSERR FLASH_CR_PGSERRIE /*!< Program Sequence Error interrupt enable */
|
||||
#define FLASH_IT_STRBERR FLASH_CR_STRBERRIE /*!< Strobe Error interrupt enable */
|
||||
#define FLASH_IT_INCERR FLASH_CR_INCERRIE /*!< Inconsistency Error interrupt enable */
|
||||
#if defined (FLASH_SR_OBKERR)
|
||||
#define FLASH_IT_OBKERR FLASH_CR_OBKERRIE /*!< OBK Error interrupt enable */
|
||||
#define FLASH_IT_OBKWERR FLASH_CR_OBKWERRIE /*!< OBK Write Error interrupt enable */
|
||||
#endif /* FLASH_SR_OBKERR */
|
||||
#define FLASH_IT_OPTCHANGEERR FLASH_CR_OPTCHANGEERRIE /*!< Option Byte change Error interrupt enable */
|
||||
#define FLASH_IT_ECCC FLASH_ECCR_ECCIE /*!< Single ECC Error Correction interrupt enable */
|
||||
|
||||
#if defined (FLASH_SR_OBKERR)
|
||||
#define FLASH_IT_ALL (FLASH_IT_EOP | FLASH_IT_WRPERR | \
|
||||
FLASH_IT_PGSERR | FLASH_IT_STRBERR | \
|
||||
FLASH_IT_INCERR | FLASH_IT_OBKERR | \
|
||||
FLASH_IT_OBKWERR | FLASH_IT_OPTCHANGEERR | \
|
||||
FLASH_IT_ECCC) /*!< All Flash interrupt sources */
|
||||
#else
|
||||
#define FLASH_IT_ALL (FLASH_IT_EOP | FLASH_IT_WRPERR | \
|
||||
FLASH_IT_PGSERR | FLASH_IT_STRBERR | \
|
||||
FLASH_IT_INCERR | FLASH_IT_OPTCHANGEERR | \
|
||||
FLASH_IT_ECCC) /*!< All Flash interrupt sources */
|
||||
#endif /* FLASH_SR_OBKERR */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Error_Code FLASH Error Code
|
||||
* @brief FLASH Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_FLASH_ERROR_NONE 0x00000000U /*!< No error */
|
||||
#define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR /*!< Write Protection Error */
|
||||
#define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR /*!< Program Sequence Error */
|
||||
#define HAL_FLASH_ERROR_STRB FLASH_FLAG_STRBERR /*!< Strobe Error */
|
||||
#define HAL_FLASH_ERROR_INC FLASH_FLAG_INCERR /*!< Inconsistency Error */
|
||||
#if defined (FLASH_SR_OBKERR)
|
||||
#define HAL_FLASH_ERROR_OBK FLASH_FLAG_OBKERR /*!< OBK Error */
|
||||
#define HAL_FLASH_ERROR_OBKW FLASH_FLAG_OBKWERR /*!< OBK Write Error */
|
||||
#endif /* FLASH_SR_OBKERR */
|
||||
#define HAL_FLASH_ERROR_OB_CHANGE FLASH_FLAG_OPTCHANGEERR /*!< Option Byte Change Error */
|
||||
#define HAL_FLASH_ERROR_ECCC FLASH_FLAG_ECCC /*!< ECC Single Correction Error */
|
||||
#define HAL_FLASH_ERROR_ECCD FLASH_FLAG_ECCD /*!< ECC Double Detection Error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Type_Program FLASH Program Type
|
||||
* @{
|
||||
*/
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
#define FLASH_TYPEPROGRAM_QUADWORD FLASH_CR_PG /*!< Program a quad-word
|
||||
(128-bit) at a specified secure address */
|
||||
#define FLASH_TYPEPROGRAM_QUADWORD_NS (FLASH_CR_PG | FLASH_NON_SECURE_MASK) /*!< Program a quad-word
|
||||
(128-bit) at a specified non-secure address */
|
||||
#if defined (FLASH_SR_OBKERR)
|
||||
#define FLASH_TYPEPROGRAM_QUADWORD_OBK (FLASH_CR_PG | FLASH_OBK) /*!< Program a quad-word
|
||||
(128-bit) of OBK to current sector */
|
||||
#define FLASH_TYPEPROGRAM_QUADWORD_OBK_ALT (FLASH_CR_PG | FLASH_OBK | FLASH_OBKCFGR_ALT_SECT) /*!< Program a quad-word
|
||||
(128-bit) of OBK to alternate sector */
|
||||
#endif /* FLASH_SR_OBKERR */
|
||||
#if defined (FLASH_EDATAR_EDATA_EN)
|
||||
#define FLASH_TYPEPROGRAM_HALFWORD_EDATA (FLASH_CR_PG | FLASH_EDATA) /*!< Program a flash
|
||||
high-cycle data half-word (16-bit)at a specified secure address */
|
||||
#define FLASH_TYPEPROGRAM_HALFWORD_EDATA_NS (FLASH_CR_PG | FLASH_EDATA | FLASH_NON_SECURE_MASK) /*!< Program a flash
|
||||
high-cycle data half-word (16-bit)at a specified non-secure address */
|
||||
#endif /* FLASH_EDATAR_EDATA_EN */
|
||||
#else
|
||||
#define FLASH_TYPEPROGRAM_QUADWORD FLASH_CR_PG /*!< Program a quad-word
|
||||
(128-bit) at a specified address */
|
||||
#if defined (FLASH_SR_OBKERR)
|
||||
#define FLASH_TYPEPROGRAM_QUADWORD_OBK (FLASH_CR_PG | FLASH_OBK) /*!< Program a quad-word
|
||||
(128-bit) of OBK to current sector */
|
||||
#define FLASH_TYPEPROGRAM_QUADWORD_OBK_ALT (FLASH_CR_PG | FLASH_OBK | FLASH_OBKCFGR_ALT_SECT) /*!< Program a quad-word
|
||||
(128-bit) of OBK to alternate sector */
|
||||
#endif /* FLASH_SR_OBKERR */
|
||||
#if defined (FLASH_EDATAR_EDATA_EN)
|
||||
#define FLASH_TYPEPROGRAM_HALFWORD_EDATA (FLASH_CR_PG | FLASH_EDATA) /*!< Program a flash
|
||||
high-cycle data half-word (16-bit)at a specified address */
|
||||
#endif /* FLASH_EDATAR_EDATA_EN */
|
||||
#endif /* __ARM_FEATURE_CMSE */
|
||||
#define FLASH_TYPEPROGRAM_HALFWORD_OTP (FLASH_CR_PG | FLASH_OTP | FLASH_NON_SECURE_MASK) /*!< Program an OTP
|
||||
half-word (16-bit)at a specified address */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Latency FLASH Latency
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait cycle */
|
||||
#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait cycle */
|
||||
#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait cycles */
|
||||
#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait cycles */
|
||||
#define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait cycles */
|
||||
#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five wait cycles */
|
||||
#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six wait cycles */
|
||||
#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven wait cycles */
|
||||
#define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight wait cycle */
|
||||
#define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine wait cycle */
|
||||
#define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten wait cycles */
|
||||
#define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven wait cycles */
|
||||
#define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve wait cycles */
|
||||
#define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen wait cycles */
|
||||
#define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen wait cycles */
|
||||
#define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen wait cycles */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Keys FLASH Keys
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_KEY1 0x45670123U
|
||||
#define FLASH_KEY2 0xCDEF89ABU
|
||||
#define FLASH_OPT_KEY1 0x08192A3BU
|
||||
#define FLASH_OPT_KEY2 0x4C5D6E7FU
|
||||
#if defined (FLASH_SR_OBKERR)
|
||||
#define FLASH_OBK_KEY1 0x192A083BU
|
||||
#define FLASH_OBK_KEY2 0x6E7F4C5DU
|
||||
#endif /* FLASH_SR_OBKERR */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Sectors FLASH Sectors
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_SECTOR_0 0U /*!< Sector Number 0 */
|
||||
#define FLASH_SECTOR_1 1U /*!< Sector Number 1 */
|
||||
#define FLASH_SECTOR_2 2U /*!< Sector Number 2 */
|
||||
#define FLASH_SECTOR_3 3U /*!< Sector Number 3 */
|
||||
#define FLASH_SECTOR_4 4U /*!< Sector Number 4 */
|
||||
#define FLASH_SECTOR_5 5U /*!< Sector Number 5 */
|
||||
#define FLASH_SECTOR_6 6U /*!< Sector Number 6 */
|
||||
#define FLASH_SECTOR_7 7U /*!< Sector Number 7 */
|
||||
#if (FLASH_SECTOR_NB == 128)
|
||||
#define FLASH_SECTOR_8 8U /*!< Sector Number 8 */
|
||||
#define FLASH_SECTOR_9 9U /*!< Sector Number 9 */
|
||||
#define FLASH_SECTOR_10 10U /*!< Sector Number 10 */
|
||||
#define FLASH_SECTOR_11 11U /*!< Sector Number 11 */
|
||||
#define FLASH_SECTOR_12 12U /*!< Sector Number 12 */
|
||||
#define FLASH_SECTOR_13 13U /*!< Sector Number 13 */
|
||||
#define FLASH_SECTOR_14 14U /*!< Sector Number 14 */
|
||||
#define FLASH_SECTOR_15 15U /*!< Sector Number 15 */
|
||||
#define FLASH_SECTOR_16 16U /*!< Sector Number 16 */
|
||||
#define FLASH_SECTOR_17 17U /*!< Sector Number 17 */
|
||||
#define FLASH_SECTOR_18 18U /*!< Sector Number 18 */
|
||||
#define FLASH_SECTOR_19 19U /*!< Sector Number 19 */
|
||||
#define FLASH_SECTOR_20 20U /*!< Sector Number 20 */
|
||||
#define FLASH_SECTOR_21 21U /*!< Sector Number 21 */
|
||||
#define FLASH_SECTOR_22 22U /*!< Sector Number 22 */
|
||||
#define FLASH_SECTOR_23 23U /*!< Sector Number 23 */
|
||||
#define FLASH_SECTOR_24 24U /*!< Sector Number 24 */
|
||||
#define FLASH_SECTOR_25 25U /*!< Sector Number 25 */
|
||||
#define FLASH_SECTOR_26 26U /*!< Sector Number 26 */
|
||||
#define FLASH_SECTOR_27 27U /*!< Sector Number 27 */
|
||||
#define FLASH_SECTOR_28 28U /*!< Sector Number 28 */
|
||||
#define FLASH_SECTOR_29 29U /*!< Sector Number 29 */
|
||||
#define FLASH_SECTOR_30 30U /*!< Sector Number 30 */
|
||||
#define FLASH_SECTOR_31 31U /*!< Sector Number 31 */
|
||||
#define FLASH_SECTOR_32 32U /*!< Sector Number 32 */
|
||||
#define FLASH_SECTOR_33 33U /*!< Sector Number 33 */
|
||||
#define FLASH_SECTOR_34 34U /*!< Sector Number 34 */
|
||||
#define FLASH_SECTOR_35 35U /*!< Sector Number 35 */
|
||||
#define FLASH_SECTOR_36 36U /*!< Sector Number 36 */
|
||||
#define FLASH_SECTOR_37 37U /*!< Sector Number 37 */
|
||||
#define FLASH_SECTOR_38 38U /*!< Sector Number 38 */
|
||||
#define FLASH_SECTOR_39 39U /*!< Sector Number 39 */
|
||||
#define FLASH_SECTOR_40 40U /*!< Sector Number 40 */
|
||||
#define FLASH_SECTOR_41 41U /*!< Sector Number 41 */
|
||||
#define FLASH_SECTOR_42 42U /*!< Sector Number 42 */
|
||||
#define FLASH_SECTOR_43 43U /*!< Sector Number 43 */
|
||||
#define FLASH_SECTOR_44 44U /*!< Sector Number 44 */
|
||||
#define FLASH_SECTOR_45 45U /*!< Sector Number 45 */
|
||||
#define FLASH_SECTOR_46 46U /*!< Sector Number 46 */
|
||||
#define FLASH_SECTOR_47 47U /*!< Sector Number 47 */
|
||||
#define FLASH_SECTOR_48 48U /*!< Sector Number 48 */
|
||||
#define FLASH_SECTOR_49 49U /*!< Sector Number 49 */
|
||||
#define FLASH_SECTOR_50 50U /*!< Sector Number 50 */
|
||||
#define FLASH_SECTOR_51 51U /*!< Sector Number 51 */
|
||||
#define FLASH_SECTOR_52 52U /*!< Sector Number 52 */
|
||||
#define FLASH_SECTOR_53 53U /*!< Sector Number 53 */
|
||||
#define FLASH_SECTOR_54 54U /*!< Sector Number 54 */
|
||||
#define FLASH_SECTOR_55 55U /*!< Sector Number 55 */
|
||||
#define FLASH_SECTOR_56 56U /*!< Sector Number 56 */
|
||||
#define FLASH_SECTOR_57 57U /*!< Sector Number 57 */
|
||||
#define FLASH_SECTOR_58 58U /*!< Sector Number 58 */
|
||||
#define FLASH_SECTOR_59 59U /*!< Sector Number 59 */
|
||||
#define FLASH_SECTOR_60 60U /*!< Sector Number 60 */
|
||||
#define FLASH_SECTOR_61 61U /*!< Sector Number 61 */
|
||||
#define FLASH_SECTOR_62 62U /*!< Sector Number 62 */
|
||||
#define FLASH_SECTOR_63 63U /*!< Sector Number 63 */
|
||||
#define FLASH_SECTOR_64 64U /*!< Sector Number 64 */
|
||||
#define FLASH_SECTOR_65 65U /*!< Sector Number 65 */
|
||||
#define FLASH_SECTOR_66 66U /*!< Sector Number 66 */
|
||||
#define FLASH_SECTOR_67 67U /*!< Sector Number 67 */
|
||||
#define FLASH_SECTOR_68 68U /*!< Sector Number 68 */
|
||||
#define FLASH_SECTOR_69 69U /*!< Sector Number 69 */
|
||||
#define FLASH_SECTOR_70 70U /*!< Sector Number 70 */
|
||||
#define FLASH_SECTOR_71 71U /*!< Sector Number 71 */
|
||||
#define FLASH_SECTOR_72 72U /*!< Sector Number 72 */
|
||||
#define FLASH_SECTOR_73 73U /*!< Sector Number 73 */
|
||||
#define FLASH_SECTOR_74 74U /*!< Sector Number 74 */
|
||||
#define FLASH_SECTOR_75 75U /*!< Sector Number 75 */
|
||||
#define FLASH_SECTOR_76 76U /*!< Sector Number 76 */
|
||||
#define FLASH_SECTOR_77 77U /*!< Sector Number 77 */
|
||||
#define FLASH_SECTOR_78 78U /*!< Sector Number 78 */
|
||||
#define FLASH_SECTOR_79 79U /*!< Sector Number 79 */
|
||||
#define FLASH_SECTOR_80 80U /*!< Sector Number 80 */
|
||||
#define FLASH_SECTOR_81 81U /*!< Sector Number 81 */
|
||||
#define FLASH_SECTOR_82 82U /*!< Sector Number 82 */
|
||||
#define FLASH_SECTOR_83 83U /*!< Sector Number 83 */
|
||||
#define FLASH_SECTOR_84 84U /*!< Sector Number 84 */
|
||||
#define FLASH_SECTOR_85 85U /*!< Sector Number 85 */
|
||||
#define FLASH_SECTOR_86 86U /*!< Sector Number 86 */
|
||||
#define FLASH_SECTOR_87 87U /*!< Sector Number 87 */
|
||||
#define FLASH_SECTOR_88 88U /*!< Sector Number 88 */
|
||||
#define FLASH_SECTOR_89 89U /*!< Sector Number 89 */
|
||||
#define FLASH_SECTOR_90 90U /*!< Sector Number 90 */
|
||||
#define FLASH_SECTOR_91 91U /*!< Sector Number 91 */
|
||||
#define FLASH_SECTOR_92 92U /*!< Sector Number 92 */
|
||||
#define FLASH_SECTOR_93 93U /*!< Sector Number 93 */
|
||||
#define FLASH_SECTOR_94 94U /*!< Sector Number 94 */
|
||||
#define FLASH_SECTOR_95 95U /*!< Sector Number 95 */
|
||||
#define FLASH_SECTOR_96 96U /*!< Sector Number 96 */
|
||||
#define FLASH_SECTOR_97 97U /*!< Sector Number 97 */
|
||||
#define FLASH_SECTOR_98 98U /*!< Sector Number 98 */
|
||||
#define FLASH_SECTOR_99 99U /*!< Sector Number 99 */
|
||||
#define FLASH_SECTOR_100 100U /*!< Sector Number 100 */
|
||||
#define FLASH_SECTOR_101 101U /*!< Sector Number 101 */
|
||||
#define FLASH_SECTOR_102 102U /*!< Sector Number 102 */
|
||||
#define FLASH_SECTOR_103 103U /*!< Sector Number 103 */
|
||||
#define FLASH_SECTOR_104 104U /*!< Sector Number 104 */
|
||||
#define FLASH_SECTOR_105 105U /*!< Sector Number 105 */
|
||||
#define FLASH_SECTOR_106 106U /*!< Sector Number 106 */
|
||||
#define FLASH_SECTOR_107 107U /*!< Sector Number 107 */
|
||||
#define FLASH_SECTOR_108 108U /*!< Sector Number 108 */
|
||||
#define FLASH_SECTOR_109 109U /*!< Sector Number 109 */
|
||||
#define FLASH_SECTOR_110 110U /*!< Sector Number 110 */
|
||||
#define FLASH_SECTOR_111 111U /*!< Sector Number 111 */
|
||||
#define FLASH_SECTOR_112 112U /*!< Sector Number 112 */
|
||||
#define FLASH_SECTOR_113 113U /*!< Sector Number 113 */
|
||||
#define FLASH_SECTOR_114 114U /*!< Sector Number 114 */
|
||||
#define FLASH_SECTOR_115 115U /*!< Sector Number 115 */
|
||||
#define FLASH_SECTOR_116 116U /*!< Sector Number 116 */
|
||||
#define FLASH_SECTOR_117 117U /*!< Sector Number 117 */
|
||||
#define FLASH_SECTOR_118 118U /*!< Sector Number 118 */
|
||||
#define FLASH_SECTOR_119 119U /*!< Sector Number 119 */
|
||||
#define FLASH_SECTOR_120 120U /*!< Sector Number 120 */
|
||||
#define FLASH_SECTOR_121 121U /*!< Sector Number 121 */
|
||||
#define FLASH_SECTOR_122 122U /*!< Sector Number 122 */
|
||||
#define FLASH_SECTOR_123 123U /*!< Sector Number 123 */
|
||||
#define FLASH_SECTOR_124 124U /*!< Sector Number 124 */
|
||||
#define FLASH_SECTOR_125 125U /*!< Sector Number 125 */
|
||||
#define FLASH_SECTOR_126 126U /*!< Sector Number 126 */
|
||||
#define FLASH_SECTOR_127 127U /*!< Sector Number 127 */
|
||||
#endif /* (FLASH_SECTOR_NB == 128) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros ------------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Set the FLASH Latency.
|
||||
* @param __LATENCY__: FLASH Latency
|
||||
* This parameter can be one of the following values :
|
||||
* @arg FLASH_LATENCY_0: FLASH Zero wait state
|
||||
* @arg FLASH_LATENCY_1: FLASH One wait state
|
||||
* @arg FLASH_LATENCY_2: FLASH Two wait states
|
||||
* @arg FLASH_LATENCY_3: FLASH Three wait states
|
||||
* @arg FLASH_LATENCY_4: FLASH Four wait states
|
||||
* @arg FLASH_LATENCY_5: FLASH Five wait states
|
||||
* @arg FLASH_LATENCY_6: FLASH Six wait states
|
||||
* @arg FLASH_LATENCY_7: FLASH Seven wait states
|
||||
* @arg FLASH_LATENCY_8: FLASH Eight wait states
|
||||
* @arg FLASH_LATENCY_9: FLASH Nine wait states
|
||||
* @arg FLASH_LATENCY_10: FLASH Ten wait states
|
||||
* @arg FLASH_LATENCY_11: FLASH Eleven wait states
|
||||
* @arg FLASH_LATENCY_12: FLASH Twelve wait states
|
||||
* @arg FLASH_LATENCY_13: FLASH Thirteen wait states
|
||||
* @arg FLASH_LATENCY_14: FLASH Fourteen wait states
|
||||
* @arg FLASH_LATENCY_15: FLASH Fifteen wait states
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_SET_LATENCY(__LATENCY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__))
|
||||
|
||||
/**
|
||||
* @brief Get the FLASH Latency.
|
||||
* @retval FLASH Latency
|
||||
* This return value can be one of the following values :
|
||||
* @arg FLASH_LATENCY_0: FLASH Zero wait state
|
||||
* @arg FLASH_LATENCY_1: FLASH One wait state
|
||||
* @arg FLASH_LATENCY_2: FLASH Two wait states
|
||||
* @arg FLASH_LATENCY_3: FLASH Three wait states
|
||||
* @arg FLASH_LATENCY_4: FLASH Four wait states
|
||||
* @arg FLASH_LATENCY_5: FLASH Five wait states
|
||||
* @arg FLASH_LATENCY_6: FLASH Six wait states
|
||||
* @arg FLASH_LATENCY_7: FLASH Seven wait states
|
||||
* @arg FLASH_LATENCY_8: FLASH Eight wait states
|
||||
* @arg FLASH_LATENCY_9: FLASH Nine wait states
|
||||
* @arg FLASH_LATENCY_10: FLASH Ten wait states
|
||||
* @arg FLASH_LATENCY_11: FLASH Eleven wait states
|
||||
* @arg FLASH_LATENCY_12: FLASH Twelve wait states
|
||||
* @arg FLASH_LATENCY_13: FLASH Thirteen wait states
|
||||
* @arg FLASH_LATENCY_14: FLASH Fourteen wait states
|
||||
* @arg FLASH_LATENCY_15: FLASH Fifteen wait states
|
||||
*/
|
||||
#define __HAL_FLASH_GET_LATENCY() READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)
|
||||
|
||||
/**
|
||||
* @brief Enable the specified FLASH interrupt.
|
||||
* @param __INTERRUPT__ : FLASH interrupt
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg FLASH_IT_EOP : End of FLASH Operation Interrupt
|
||||
* @arg FLASH_IT_WRPERR : Write Protection Error Interrupt
|
||||
* @arg FLASH_IT_PGSERR : Program Sequence Error Interrupt
|
||||
* @arg FLASH_IT_STRBERR : Strobe Error Interrupt
|
||||
* @arg FLASH_IT_INCERR : Inconsistency Error Interrupt
|
||||
* @arg FLASH_IT_OBKERR : OBK Error Interrupt
|
||||
* @arg FLASH_IT_OBKWERR : OBK Write Error Interrupt
|
||||
* @arg FLASH_IT_OPTCHANGEERR : Option Byte Change Error Interrupt
|
||||
* @arg FLASH_IT_ECCC : Single ECC Error Correction Interrupt
|
||||
* @retval none
|
||||
*/
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
/* Enable secure FLASH interrupts from the secure world */
|
||||
#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) \
|
||||
{ SET_BIT(FLASH->ECCCORR, FLASH_IT_ECCC); } \
|
||||
if(((__INTERRUPT__) & FLASH_IT_OPTCHANGEERR) != 0U) \
|
||||
{ SET_BIT(FLASH->NSCR, FLASH_IT_OPTCHANGEERR); } \
|
||||
if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) \
|
||||
{ SET_BIT(FLASH->SECCR, ((__INTERRUPT__) & (~(FLASH_IT_ECCC | \
|
||||
FLASH_IT_OPTCHANGEERR)))); }\
|
||||
} while(0)
|
||||
/* Enable non-secure FLASH interrupts from the secure world */
|
||||
#define __HAL_FLASH_ENABLE_IT_NS(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) \
|
||||
{ SET_BIT(FLASH->ECCCORR, FLASH_IT_ECCC); } \
|
||||
if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) \
|
||||
{ SET_BIT(FLASH->NSCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); } \
|
||||
} while(0)
|
||||
#else
|
||||
/* Enable non-secure FLASH interrupts from the non-secure world */
|
||||
#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) \
|
||||
{ SET_BIT(FLASH->ECCCORR, FLASH_IT_ECCC); } \
|
||||
if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) \
|
||||
{ SET_BIT(FLASH->NSCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); } \
|
||||
} while(0)
|
||||
#endif /* __ARM_FEATURE_CMSE */
|
||||
|
||||
/**
|
||||
* @brief Disable the specified FLASH interrupt.
|
||||
* @param __INTERRUPT__ : FLASH interrupt
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg FLASH_IT_EOP : End of FLASH Operation Interrupt
|
||||
* @arg FLASH_IT_WRPERR : Write Protection Error Interrupt
|
||||
* @arg FLASH_IT_PGSERR : Program Sequence Error Interrupt
|
||||
* @arg FLASH_IT_STRBERR : Strobe Error Interrupt
|
||||
* @arg FLASH_IT_INCERR : Inconsistency Error Interrupt
|
||||
* @arg FLASH_IT_OBKERR : OBK Error Interrupt
|
||||
* @arg FLASH_IT_OBKWERR : OBK Write Error Interrupt
|
||||
* @arg FLASH_IT_OPTCHANGEERR : Option Byte Change Error Interrupt
|
||||
* @arg FLASH_IT_ECCC : Single ECC Error Correction Interrupt
|
||||
* @retval none
|
||||
*/
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
/* Disable secure FLASH interrupts from the secure world */
|
||||
#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) \
|
||||
{ CLEAR_BIT(FLASH->ECCCORR, FLASH_IT_ECCC); } \
|
||||
if(((__INTERRUPT__) & FLASH_IT_OPTCHANGEERR) != 0U) \
|
||||
{ CLEAR_BIT(FLASH->NSCR, FLASH_IT_OPTCHANGEERR); } \
|
||||
if(((__INTERRUPT__) & (~(FLASH_IT_ECCC | FLASH_IT_OPTCHANGEERR))) \
|
||||
!= 0U){ CLEAR_BIT(FLASH->SECCR, ((__INTERRUPT__) & \
|
||||
(~(FLASH_IT_ECCC | FLASH_IT_OPTCHANGEERR)))); }\
|
||||
} while(0)
|
||||
/* Disable non-secure FLASH interrupts from the secure world */
|
||||
#define __HAL_FLASH_DISABLE_IT_NS(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT \
|
||||
(FLASH->ECCCORR, FLASH_IT_ECCC); } \
|
||||
if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) \
|
||||
{ CLEAR_BIT(FLASH->NSCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC)));\
|
||||
} \
|
||||
} while(0)
|
||||
#else
|
||||
/* Disable non-secure FLASH interrupts from the non-secure world */
|
||||
#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT \
|
||||
(FLASH->ECCCORR, FLASH_IT_ECCC); } \
|
||||
if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT \
|
||||
(FLASH->NSCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); } \
|
||||
} while(0)
|
||||
#endif /* __ARM_FEATURE_CMSE */
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified FLASH flag is set or not.
|
||||
* @param __FLAG__: specifies the FLASH flag to check.
|
||||
* This parameter can be one of the following values :
|
||||
* @arg FLASH_FLAG_BSY : FLASH Busy flag
|
||||
* @arg FLASH_FLAG_WBNE : Write Buffer Not Empty flag
|
||||
* @arg FLASH_FLAG_EOP : End Of Operation flag
|
||||
* @arg FLASH_FLAG_WRPERR : Write Protection Error flag
|
||||
* @arg FLASH_FLAG_PGSERR : Program Sequence Error flag
|
||||
* @arg FLASH_FLAG_STRBERR : Strobe Error flag
|
||||
* @arg FLASH_FLAG_INCERR : Inconsistency Error flag
|
||||
* @arg FLASH_FLAG_OBKERR : OBK Error flag
|
||||
* @arg FLASH_FLAG_OBKWERR : OBK Write Error flag
|
||||
* @arg FLASH_FLAG_OPTCHANGEERR : Option Byte Change Error flag
|
||||
* @arg FLASH_FLAG_ECCC : Single ECC Error Correction flag
|
||||
* @arg FLASH_FLAG_ECCD : Double Detection ECC Error flag
|
||||
* @retval The new state of FLASH_FLAG (SET or RESET).
|
||||
*/
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
/* Get secure FLASH flags from the secure world */
|
||||
#define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_ECCC)) != 0U) ? \
|
||||
(READ_BIT(FLASH->ECCCORR, (__FLAG__)) == (__FLAG__)) : \
|
||||
(((__FLAG__) & (FLASH_FLAG_ECCD)) != 0U) ? \
|
||||
(READ_BIT(FLASH->ECCDETR, (__FLAG__)) == (__FLAG__)) : \
|
||||
((((__FLAG__) & (FLASH_FLAG_OPTCHANGEERR)) != 0U) ? \
|
||||
(READ_BIT(FLASH->NSSR, (__FLAG__)) == (__FLAG__)) : \
|
||||
(READ_BIT(FLASH->SECSR, (__FLAG__)) == (__FLAG__))))
|
||||
/* Get non-secure FLASH flags from the secure world */
|
||||
#define __HAL_FLASH_GET_FLAG_NS(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_ECCC)) != 0U) ? \
|
||||
(READ_BIT(FLASH->ECCCORR, (__FLAG__)) == (__FLAG__)) : \
|
||||
(((__FLAG__) & (FLASH_FLAG_ECCD)) != 0U) ? \
|
||||
(READ_BIT(FLASH->ECCDETR, (__FLAG__)) == (__FLAG__)) : \
|
||||
(READ_BIT(FLASH->NSSR, (__FLAG__)) == (__FLAG__))))
|
||||
#else
|
||||
/* Get non-secure FLASH flags from the non-secure world */
|
||||
#define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_ECCC)) != 0U) ? \
|
||||
(READ_BIT(FLASH->ECCCORR, (__FLAG__)) == (__FLAG__)) : \
|
||||
(((__FLAG__) & (FLASH_FLAG_ECCD)) != 0U) ? \
|
||||
(READ_BIT(FLASH->ECCDETR, (__FLAG__)) == (__FLAG__)) : \
|
||||
(READ_BIT(FLASH->NSSR, (__FLAG__)) == (__FLAG__)))
|
||||
#endif /* __ARM_FEATURE_CMSE */
|
||||
|
||||
/**
|
||||
* @brief Clear the specified FLASH flag.
|
||||
* @param __FLAG__: specifies the FLASH flags to clear.
|
||||
* This parameter can be one of the following values :
|
||||
* @arg FLASH_FLAG_BSY : FLASH Busy flag
|
||||
* @arg FLASH_FLAG_WBNE : Write Buffer Not Empty flag
|
||||
* @arg FLASH_FLAG_EOP : End Of Operation flag
|
||||
* @arg FLASH_FLAG_WRPERR : Write Protection Error flag
|
||||
* @arg FLASH_FLAG_PGSERR : Program Sequence Error flag
|
||||
* @arg FLASH_FLAG_STRBERR : Strobe Error flag
|
||||
* @arg FLASH_FLAG_INCERR : Inconsistency Error flag
|
||||
* @arg FLASH_FLAG_OBKERR : OBK Error flag
|
||||
* @arg FLASH_FLAG_OBKWERR : OBK Write Error flag
|
||||
* @arg FLASH_FLAG_OPTCHANGEERR : Option Byte Change Error flag
|
||||
* @arg FLASH_FLAG_ECCC : Single ECC Error Correction flag
|
||||
* @arg FLASH_FLAG_ECCD : Double Detection ECC Error flag
|
||||
* @arg FLASH_FLAG_ALL_ERRORS: All errors flags
|
||||
* @retval none
|
||||
*/
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
/* Clear secure FLASH flags from the secure world */
|
||||
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCC) != 0U) { SET_BIT(FLASH->ECCCORR,\
|
||||
((__FLAG__) & FLASH_FLAG_ECCC)); } \
|
||||
if(((__FLAG__) & FLASH_FLAG_ECCD) != 0U) { SET_BIT(FLASH->ECCDETR,\
|
||||
((__FLAG__) & FLASH_FLAG_ECCD)); } \
|
||||
if(((__FLAG__) & FLASH_FLAG_OPTCHANGEERR) != 0U) { SET_BIT \
|
||||
(FLASH->NSCCR, ((__FLAG__) & (FLASH_FLAG_OPTCHANGEERR))); } \
|
||||
if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS | \
|
||||
FLASH_FLAG_OPTCHANGEERR)) != 0U) { WRITE_REG(FLASH->SECCCR, \
|
||||
((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS | \
|
||||
FLASH_FLAG_OPTCHANGEERR))); } \
|
||||
} while(0)
|
||||
/* Clear non-secure FLASH flags from the secure world */
|
||||
#define __HAL_FLASH_CLEAR_FLAG_NS(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCC) != 0U) { SET_BIT(FLASH->ECCCORR,\
|
||||
((__FLAG__) & FLASH_FLAG_ECCC)); } \
|
||||
if(((__FLAG__) & FLASH_FLAG_ECCD) != 0U) { SET_BIT(FLASH->ECCDETR,\
|
||||
((__FLAG__) & FLASH_FLAG_ECCD)); } \
|
||||
if(((__FLAG__) & (~FLASH_FLAG_ECCR_ERRORS)) != 0U) { WRITE_REG \
|
||||
(FLASH->NSCCR, ((__FLAG__) & (~FLASH_FLAG_ECCR_ERRORS))); } \
|
||||
} while(0)
|
||||
#else
|
||||
/* Clear non-secure FLASH flags from the non-secure world */
|
||||
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCC) != 0U) { SET_BIT(FLASH->ECCCORR,\
|
||||
((__FLAG__) & FLASH_FLAG_ECCC)); } \
|
||||
if(((__FLAG__) & FLASH_FLAG_ECCD) != 0U) { SET_BIT(FLASH->ECCDETR,\
|
||||
((__FLAG__) & FLASH_FLAG_ECCD)); } \
|
||||
if(((__FLAG__) & (~FLASH_FLAG_ECCR_ERRORS)) != 0U) { WRITE_REG \
|
||||
(FLASH->NSCCR, ((__FLAG__) & (~FLASH_FLAG_ECCR_ERRORS))); } \
|
||||
} while(0)
|
||||
#endif /* __ARM_FEATURE_CMSE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include FLASH HAL Extension module */
|
||||
#include "stm32h5xx_hal_flash_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup FLASH_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
/** @addtogroup FLASH_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Program operation functions */
|
||||
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress);
|
||||
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress);
|
||||
/* FLASH IRQ handler method */
|
||||
void HAL_FLASH_IRQHandler(void);
|
||||
/* Callbacks in non blocking modes */
|
||||
void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
|
||||
void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions */
|
||||
HAL_StatusTypeDef HAL_FLASH_Unlock(void);
|
||||
HAL_StatusTypeDef HAL_FLASH_Lock(void);
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
|
||||
/* Option bytes control */
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions */
|
||||
uint32_t HAL_FLASH_GetError(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_Variables FLASH Private Variables
|
||||
* @{
|
||||
*/
|
||||
extern FLASH_ProcessTypeDef pFlash;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_Constants FLASH Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_TIMEOUT_VALUE 1000U /*!< 1 s */
|
||||
|
||||
#if defined (FLASH_SR_OBKERR)
|
||||
#define FLASH_OBK 0x10000000U
|
||||
#endif /* FLASH_SR_OBKERR */
|
||||
|
||||
#define FLASH_OTP 0x20000000U
|
||||
|
||||
#if defined (FLASH_EDATAR_EDATA_EN)
|
||||
#define FLASH_EDATA 0x40000000U
|
||||
#endif /* FLASH_EDATAR_EDATA_EN */
|
||||
|
||||
#define FLASH_NON_SECURE_MASK 0x80000000U
|
||||
|
||||
#define FLASH_EDATA_SECTOR_NB 8U /*!< Maximum number of FLASH high-cycle data sectors */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_Macros FLASH Private Macros
|
||||
* @{
|
||||
*/
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
#if defined (FLASH_SR_OBKERR) && defined (FLASH_EDATAR_EDATA_EN)
|
||||
#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_QUADWORD) || \
|
||||
((VALUE) == FLASH_TYPEPROGRAM_QUADWORD_NS) || \
|
||||
((VALUE) == FLASH_TYPEPROGRAM_HALFWORD_OTP) || \
|
||||
((VALUE) == FLASH_TYPEPROGRAM_HALFWORD_EDATA) || \
|
||||
((VALUE) == FLASH_TYPEPROGRAM_HALFWORD_EDATA_NS) || \
|
||||
((VALUE) == FLASH_TYPEPROGRAM_QUADWORD_OBK) || \
|
||||
((VALUE) == FLASH_TYPEPROGRAM_QUADWORD_OBK_ALT))
|
||||
#else
|
||||
#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_QUADWORD) || \
|
||||
((VALUE) == FLASH_TYPEPROGRAM_QUADWORD_NS) || \
|
||||
((VALUE) == FLASH_TYPEPROGRAM_HALFWORD_OTP))
|
||||
#endif /* FLASH_SR_OBKERR && FLASH_EDATAR_EDATA_EN */
|
||||
#else
|
||||
#if defined (FLASH_SR_OBKERR) && defined (FLASH_EDATAR_EDATA_EN)
|
||||
#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_QUADWORD) || \
|
||||
((VALUE) == FLASH_TYPEPROGRAM_HALFWORD_OTP) || \
|
||||
((VALUE) == FLASH_TYPEPROGRAM_HALFWORD_EDATA) || \
|
||||
((VALUE) == FLASH_TYPEPROGRAM_QUADWORD_OBK) || \
|
||||
((VALUE) == FLASH_TYPEPROGRAM_QUADWORD_OBK_ALT))
|
||||
#else
|
||||
#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_QUADWORD) || \
|
||||
((VALUE) == FLASH_TYPEPROGRAM_HALFWORD_OTP))
|
||||
#endif /* FLASH_SR_OBKERR && FLASH_EDATAR_EDATA_EN */
|
||||
#endif /* __ARM_FEATURE_CMSE */
|
||||
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
#define IS_FLASH_USER_MEM_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE+FLASH_SIZE))) || \
|
||||
(((ADDRESS) >= FLASH_BASE_NS) && ((ADDRESS) < (FLASH_BASE_NS+FLASH_SIZE))))
|
||||
#if defined (FLASH_SR_OBKERR)
|
||||
#define IS_FLASH_OBK_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_OBK_BASE) && \
|
||||
((ADDRESS) < (FLASH_OBK_BASE+FLASH_OBK_SIZE))) || \
|
||||
(((ADDRESS) >= FLASH_OBK_BASE_NS) && \
|
||||
((ADDRESS) < (FLASH_OBK_BASE_NS+FLASH_OBK_SIZE))))
|
||||
#endif /* FLASH_SR_OBKERR */
|
||||
#if defined (FLASH_EDATAR_EDATA_EN)
|
||||
#define IS_FLASH_EDATA_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_EDATA_BASE_S) && \
|
||||
((ADDRESS) < (FLASH_EDATA_BASE_S+FLASH_EDATA_SIZE))) || \
|
||||
(((ADDRESS) >= FLASH_EDATA_BASE_NS) && \
|
||||
((ADDRESS) < (FLASH_EDATA_BASE_NS+FLASH_EDATA_SIZE))))
|
||||
#endif /* FLASH_EDATAR_EDATA_EN */
|
||||
#else
|
||||
#define IS_FLASH_USER_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && \
|
||||
((ADDRESS) < (FLASH_BASE+FLASH_SIZE)))
|
||||
#if defined (FLASH_SR_OBKERR)
|
||||
#define IS_FLASH_OBK_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_OBK_BASE) && \
|
||||
((ADDRESS) < (FLASH_OBK_BASE + FLASH_OBK_SIZE)))
|
||||
#endif /* FLASH_SR_OBKERR */
|
||||
#if defined (FLASH_EDATAR_EDATA_EN)
|
||||
#define IS_FLASH_EDATA_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_EDATA_BASE_NS) && \
|
||||
((ADDRESS) < (FLASH_EDATA_BASE_NS + FLASH_EDATA_SIZE)))
|
||||
#endif /* FLASH_EDATAR_EDATA_EN */
|
||||
#endif /* __ARM_FEATURE_CMSE */
|
||||
|
||||
#define IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_OTP_BASE) && \
|
||||
((ADDRESS) < (FLASH_OTP_BASE + FLASH_OTP_SIZE)))
|
||||
|
||||
#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \
|
||||
((BANK) == FLASH_BANK_2) || \
|
||||
((BANK) == FLASH_BANK_BOTH))
|
||||
|
||||
#define IS_FLASH_BANK_EXCLUSIVE(BANK) (((BANK) == FLASH_BANK_1) || \
|
||||
((BANK) == FLASH_BANK_2))
|
||||
|
||||
#define IS_FLASH_SECTOR(SECTOR) ((SECTOR) < FLASH_SECTOR_NB)
|
||||
|
||||
#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \
|
||||
((LATENCY) == FLASH_LATENCY_1) || \
|
||||
((LATENCY) == FLASH_LATENCY_2) || \
|
||||
((LATENCY) == FLASH_LATENCY_3) || \
|
||||
((LATENCY) == FLASH_LATENCY_4) || \
|
||||
((LATENCY) == FLASH_LATENCY_5) || \
|
||||
((LATENCY) == FLASH_LATENCY_6) || \
|
||||
((LATENCY) == FLASH_LATENCY_7) || \
|
||||
((LATENCY) == FLASH_LATENCY_8) || \
|
||||
((LATENCY) == FLASH_LATENCY_9) || \
|
||||
((LATENCY) == FLASH_LATENCY_10) || \
|
||||
((LATENCY) == FLASH_LATENCY_11) || \
|
||||
((LATENCY) == FLASH_LATENCY_12) || \
|
||||
((LATENCY) == FLASH_LATENCY_13) || \
|
||||
((LATENCY) == FLASH_LATENCY_14) || \
|
||||
((LATENCY) == FLASH_LATENCY_15))
|
||||
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
#define IS_FLASH_SECURE_OPERATION() ((pFlash.ProcedureOnGoing & FLASH_NON_SECURE_MASK) == 0U)
|
||||
#else
|
||||
#define IS_FLASH_SECURE_OPERATION() (1U == 0U)
|
||||
#endif /* __ARM_FEATURE_CMSE */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_Functions FLASH Private Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H5xx_HAL_FLASH_H */
|
||||
|
|
@ -0,0 +1,998 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h5xx_hal_flash_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of FLASH HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H5xx_HAL_FLASH_EX_H
|
||||
#define STM32H5xx_HAL_FLASH_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h5xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H5xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASHEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FLASH Erase structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t TypeErase; /*!< Mass erase or sector Erase.
|
||||
This parameter can be a value of @ref FLASH_Type_Erase */
|
||||
|
||||
uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled.
|
||||
This parameter can be a value of @ref FLASH_Banks
|
||||
(FLASH_BANK_BOTH should be used only for mass erase) */
|
||||
|
||||
uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled
|
||||
This parameter can be a value of @ref FLASH_Sectors */
|
||||
|
||||
uint32_t NbSectors; /*!< Number of sectors to be erased.
|
||||
This parameter can be a value between 1 and (max number of sectors in the bank -
|
||||
value of initial sector)*/
|
||||
} FLASH_EraseInitTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief FLASH Option Bytes Program structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t OptionType; /*!< Option byte to be configured.
|
||||
This parameter can be a value of @ref FLASH_Option_Type */
|
||||
|
||||
uint32_t ProductState; /*!< Set the product state.
|
||||
This parameter can be a value of @ref FLASH_OB_Product_State */
|
||||
|
||||
uint32_t USERType; /*!< Select the User Option Byte(s) to be configured (used for OPTIONBYTE_USER).
|
||||
This parameter can be a combination of @ref FLASH_OB_USER_Type */
|
||||
|
||||
uint32_t USERConfig; /*!< Value of the User Option Byte (used for OPTIONBYTE_USER).
|
||||
This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL,
|
||||
@ref FLASH_OB_USER_BORH_EN, @ref FLASH_OB_USER_IWDG_SW,
|
||||
@ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_nRST_STOP,
|
||||
@ref FLASH_OB_USER_nRST_STANDBY, @ref FLASH_OB_USER_IO_VDD_HSLV,
|
||||
@ref FLASH_OB_USER_IO_VDDIO2_HSLV, @ref FLASH_OB_USER_IWDG_STOP,
|
||||
@ref FLASH_OB_USER_IWDG_STANDBY, @ref FLASH_OB_USER_BOOT_UBE,
|
||||
@ref FLASH_OB_USER_SWAP_BANK */
|
||||
|
||||
uint32_t USERConfig2; /*!< Value of the User Option Byte (used for OPTIONBYTE_USER).
|
||||
This parameter can be a combination of @ref FLASH_OB_USER_SRAM1_3_RST,
|
||||
@ref FLASH_OB_USER_SRAM2_RST, @ref FLASH_OB_USER_BKPRAM_ECC,
|
||||
@ref FLASH_OB_USER_SRAM3_ECC, @ref FLASH_OB_USER_SRAM2_ECC,
|
||||
@ref FLASH_OB_USER_SRAM1_RST, @ref FLASH_OB_USER_SRAM1_ECC,
|
||||
@ref FLASH_OB_USER_TZEN */
|
||||
|
||||
uint32_t Banks; /*!< Select banks for WRP , HDP and secure area configuration.
|
||||
This parameter must be a value of @ref FLASH_Banks */
|
||||
|
||||
uint32_t WRPState; /*!< Write protection activation or deactivation.
|
||||
This parameter can be a value of @ref FLASH_WRP_State */
|
||||
|
||||
uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected.
|
||||
The value of this parameter depend on device used within the same series */
|
||||
|
||||
uint32_t BootConfig; /*!< Specifies if the Boot Address to be configured: secure or non-secure.
|
||||
This parameter must be a value of @ref FLASH_OB_BOOT_CONFIG enumeration */
|
||||
|
||||
uint32_t BootAddr; /*!< Boot address (used for OPTIONBYTE_BOOTADDR).
|
||||
This parameter must be a value between 0x0 and 0xFFFFFF00 */
|
||||
|
||||
uint32_t BootLock; /*!< Configuration of the boot lock (used for OPTIONBYTE_BOOT_LOCK).
|
||||
This parameter must be a value of @ref FLASH_OB_BOOT_LOCK */
|
||||
|
||||
uint32_t OTPBlockLock; /*!< Specifies the OTP block(s) to be locked.
|
||||
This parameter must be a value of @ref FLASH_OTP_Blocks */
|
||||
|
||||
uint32_t HDPStartSector; /*!< Start sector of HDP area (used for OPTIONBYTE_HDP).
|
||||
This parameter must be a value between 0 and (max number of sectors in the bank - 1) */
|
||||
|
||||
uint32_t HDPEndSector; /*!< End sector of HDP area (used for OPTIONBYTE_HDP).
|
||||
This parameter must be a value between 0 and (max number of sectors in the bank - 1) */
|
||||
|
||||
uint32_t EDATASize; /*!< Specifies the number of Flash high-cycle sectors.
|
||||
This parameter must be a value between 0 and 8 (sectors) */
|
||||
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
uint32_t WMSecStartSector; /*!< Start sector of secure area (used for OPTIONBYTE_WMSEC).
|
||||
This parameter must be a value between 0 and (max number of sectors in the bank - 1)*/
|
||||
uint32_t WMSecEndSector; /*!< End sector of secure area (used for OPTIONBYTE_WMSEC).
|
||||
This parameter must be a value between 0 and (max number of sectors in the bank - 1)*/
|
||||
#endif /* __ARM_FEATURE_CMSE */
|
||||
|
||||
} FLASH_OBProgramInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FLASHEx Block-based attributes structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Bank; /*!< Selection of the associated bank of Block-based Area.
|
||||
This parameter must be a value of @ref FLASH_Banks */
|
||||
uint32_t BBAttributesType; /*!< Block-Based Attributes type.
|
||||
This parameter must be a value of @ref FLASH_BB_Attributes
|
||||
*/
|
||||
uint32_t BBAttributes_array[FLASH_BLOCKBASED_NB_REG]; /*!< Each bit specifies the block-based attribute configuration
|
||||
of a sector:
|
||||
0 means sector non-protected, 1 means sector protected.
|
||||
Protection (secure or privilege) depends on
|
||||
BBAttributesType value */
|
||||
} FLASH_BBAttributesTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FLASHEx Operation structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t OperationType; /*!< Flash operation Type.
|
||||
This parameter must be a value of @ref FLASH_Operation_Type */
|
||||
uint32_t FlashArea; /*!< Flash operation memory area.
|
||||
This parameter must be a value of @ref FLASH_Operation_Area */
|
||||
uint32_t Address; /*!< Flash operation Address offset.
|
||||
This parameter is given by bank, and must be a value between 0x0 and 0xFFFF0 */
|
||||
} FLASH_OperationTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FLASH HDP Extension structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Banks; /*!< Selection of the associated bank of HDP Area.
|
||||
This parameter must be a value of @ref FLASH_Banks */
|
||||
uint32_t NbSectors; /*!< Number of sectors to be HDP extended.
|
||||
This parameter can be a value between 1 and max number of sectors in the bank */
|
||||
} FLASH_HDPExtensionTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Type_Erase FLASH Type Erase
|
||||
* @{
|
||||
*/
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
#define FLASH_TYPEERASE_SECTORS FLASH_CR_SER /*!< Secure flash sectors
|
||||
erase activation */
|
||||
#define FLASH_TYPEERASE_SECTORS_NS (FLASH_CR_SER | FLASH_NON_SECURE_MASK) /*!< Non-secure flash
|
||||
sectors erase activation */
|
||||
#define FLASH_TYPEERASE_MASSERASE (FLASH_CR_BER | FLASH_CR_MER) /*!< Secure flash mass erase
|
||||
activation */
|
||||
#define FLASH_TYPEERASE_MASSERASE_NS (FLASH_CR_BER | FLASH_CR_MER | FLASH_NON_SECURE_MASK) /*!< Non-secure flash mass
|
||||
erase activation */
|
||||
#if defined (FLASH_SR_OBKERR)
|
||||
#define FLASH_TYPEERASE_OBK_ALT FLASH_OBKCFGR_ALT_SECT_ERASE /*!< Flash OBK erase
|
||||
activation */
|
||||
#endif /* FLASH_SR_OBKERR */
|
||||
#else
|
||||
#define FLASH_TYPEERASE_SECTORS FLASH_CR_SER /*!< Flash sectors erase
|
||||
activation */
|
||||
#define FLASH_TYPEERASE_MASSERASE (FLASH_CR_BER | FLASH_CR_MER) /*!< Flash mass erase
|
||||
activation */
|
||||
#if defined (FLASH_SR_OBKERR)
|
||||
#define FLASH_TYPEERASE_OBK_ALT (FLASH_OBKCFGR_ALT_SECT_ERASE | FLASH_NON_SECURE_MASK) /*!< Flash OBK erase
|
||||
activation */
|
||||
#endif /* FLASH_SR_OBKERR */
|
||||
#endif /* __ARM_FEATURE_CMSE */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Option_Type FLASH Option Type
|
||||
* @{
|
||||
*/
|
||||
#define OPTIONBYTE_WRP 0x0001U /*!< WRP option byte configuration */
|
||||
#define OPTIONBYTE_PROD_STATE 0x0002U /*!< RDP option byte configuration */
|
||||
#define OPTIONBYTE_USER 0x0004U /*!< USER option byte configuration */
|
||||
#define OPTIONBYTE_BOOTADDR 0x0008U /*!< BOOT address option byte configuration */
|
||||
#define OPTIONBYTE_BOOT_LOCK 0x0010U /*!< Boot lock option byte configuration */
|
||||
#define OPTIONBYTE_OTP_LOCK 0x0020U /*!< OTP Lock option byte configuration */
|
||||
#define OPTIONBYTE_HDP 0x0040U /*!< Hide Protection area option byte configuration */
|
||||
#if defined (FLASH_EDATAR_EDATA_EN)
|
||||
#define OPTIONBYTE_EDATA 0x0080U /*!< Flash high-cycle data area option byte configuration */
|
||||
#endif /* FLASH_EDATAR_EDATA_EN */
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
#define OPTIONBYTE_WMSEC 0x0200U /*!< Watermark-based secure area option byte configuration */
|
||||
#endif /* __ARM_FEATURE_CMSE */
|
||||
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_PROD_STATE | OPTIONBYTE_USER |\
|
||||
OPTIONBYTE_BOOTADDR | OPTIONBYTE_BOOT_LOCK | OPTIONBYTE_OTP_LOCK |\
|
||||
OPTIONBYTE_HDP | OPTIONBYTE_EDATA | OPTIONBYTE_WMSEC) /*!< All option
|
||||
byte configuration */
|
||||
#else
|
||||
#if defined (FLASH_EDATAR_EDATA_EN)
|
||||
#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_PROD_STATE | OPTIONBYTE_USER |\
|
||||
OPTIONBYTE_BOOTADDR | OPTIONBYTE_BOOT_LOCK | OPTIONBYTE_OTP_LOCK |\
|
||||
OPTIONBYTE_HDP | OPTIONBYTE_EDATA) /*!< All option byte configuration */
|
||||
#else
|
||||
#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_PROD_STATE | OPTIONBYTE_USER |\
|
||||
OPTIONBYTE_BOOTADDR | OPTIONBYTE_BOOT_LOCK | OPTIONBYTE_OTP_LOCK |\
|
||||
OPTIONBYTE_HDP) /*!< All option byte configuration */
|
||||
#endif /* FLASH_EDATAR_EDATA_EN */
|
||||
#endif /* __ARM_FEATURE_CMSE */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_Type FLASH OB USER Type
|
||||
* @{
|
||||
*/
|
||||
#define OB_USER_BOR_LEV 0x00000001U /*!< BOR reset Level */
|
||||
#define OB_USER_BORH_EN 0x00000002U /*!< BOR high enable status */
|
||||
#define OB_USER_IWDG_SW 0x00000004U /*!< Independent watchdog selection */
|
||||
#define OB_USER_WWDG_SW 0x00000008U /*!< Window watchdog selection */
|
||||
#define OB_USER_NRST_STOP 0x00000010U /*!< Reset generated when entering the stop mode */
|
||||
#define OB_USER_NRST_STDBY 0x00000020U /*!< Reset generated when entering the standby mode */
|
||||
#define OB_USER_IO_VDD_HSLV 0x00000040U /*!< High speed IO at low voltage configuration bit */
|
||||
#define OB_USER_IO_VDDIO2_HSLV 0x00000080U /*!< High speed IO2 at low voltage configuration bit */
|
||||
#define OB_USER_IWDG_STOP 0x00000100U /*!< Independent watchdog counter freeze in stop mode */
|
||||
#define OB_USER_IWDG_STDBY 0x00000200U /*!< Independent watchdog counter freeze in standby mode */
|
||||
#if defined (FLASH_OPTSR_BOOT_UBE)
|
||||
#define OB_USER_BOOT_UBE 0x00000400U /*!< Unique Boot entry */
|
||||
#endif /* FLASH_OPTSR_BOOT_UBE */
|
||||
#define OB_USER_SWAP_BANK 0x00000800U /*!< Swap banks */
|
||||
|
||||
#if defined (FLASH_OPTSR2_SRAM1_3_RST)
|
||||
#define OB_USER_SRAM1_3_RST 0x00001000U /*!< SRAM1 and SRAM3 erase upon system reset */
|
||||
#endif /* FLASH_OPTSR2_SRAM1_3_RST */
|
||||
#if defined (FLASH_OPTSR2_SRAM1_RST)
|
||||
#define OB_USER_SRAM1_RST 0x00001000U /*!< SRAM1 Erase when system reset */
|
||||
#endif /* FLASH_OPTSR2_SRAM1_RST */
|
||||
#define OB_USER_SRAM2_RST 0x00002000U /*!< SRAM2 Erase when system reset */
|
||||
#define OB_USER_BKPRAM_ECC 0x00004000U /*!< Backup RAM ECC detection and correction enable */
|
||||
#define OB_USER_SRAM3_ECC 0x00008000U /*!< SRAM3 ECC detection and correction enable */
|
||||
#define OB_USER_SRAM2_ECC 0x00010000U /*!< SRAM2 ECC detection and correction enable */
|
||||
#define OB_USER_SRAM1_ECC 0x00020000U /*!< SRAM1 ECC detection and correction enable */
|
||||
#if defined (FLASH_OPTSR2_TZEN)
|
||||
#define OB_USER_TZEN 0x00080000U /*!< Global TrustZone security enable */
|
||||
#endif /* FLASH_OPTSR2_TZEN */
|
||||
|
||||
#if defined (FLASH_OPTSR2_SRAM1_3_RST) && defined (FLASH_OPTSR_BOOT_UBE)
|
||||
#define OB_USER_ALL (OB_USER_BOR_LEV | OB_USER_BORH_EN | OB_USER_IWDG_SW |\
|
||||
OB_USER_WWDG_SW | OB_USER_NRST_STOP | OB_USER_NRST_STDBY |\
|
||||
OB_USER_IO_VDD_HSLV | OB_USER_IO_VDDIO2_HSLV | OB_USER_IWDG_STOP |\
|
||||
OB_USER_IWDG_STDBY | OB_USER_BOOT_UBE | OB_USER_SWAP_BANK |\
|
||||
OB_USER_SRAM1_3_RST | OB_USER_SRAM2_RST | OB_USER_BKPRAM_ECC |\
|
||||
OB_USER_SRAM3_ECC | OB_USER_SRAM2_ECC | OB_USER_TZEN)
|
||||
#else
|
||||
#define OB_USER_ALL (OB_USER_BOR_LEV | OB_USER_BORH_EN | OB_USER_IWDG_SW |\
|
||||
OB_USER_WWDG_SW | OB_USER_NRST_STOP | OB_USER_NRST_STDBY |\
|
||||
OB_USER_IO_VDD_HSLV | OB_USER_IO_VDDIO2_HSLV | OB_USER_IWDG_STOP |\
|
||||
OB_USER_IWDG_STDBY | OB_USER_SWAP_BANK | OB_USER_SRAM1_RST |\
|
||||
OB_USER_SRAM2_RST | OB_USER_BKPRAM_ECC | OB_USER_SRAM3_ECC |\
|
||||
OB_USER_SRAM2_ECC | OB_USER_SRAM1_ECC)
|
||||
#endif /* FLASH_OPTSR2_SRAM1_3_RST && FLASH_OPTSR_BOOT_UBE */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH BOR Reset Level
|
||||
* @{
|
||||
*/
|
||||
#define OB_BOR_LEVEL_1 FLASH_OPTSR_BOR_LEV_0 /*!< Reset level 1 threshold */
|
||||
#define OB_BOR_LEVEL_2 FLASH_OPTSR_BOR_LEV_1 /*!< Reset level 2 threshold */
|
||||
#define OB_BOR_LEVEL_3 (FLASH_OPTSR_BOR_LEV_1 | FLASH_OPTSR_BOR_LEV_0) /*!< Reset level 3 threshold */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_BORH_EN FLASH BOR High Enable Status
|
||||
* @{
|
||||
*/
|
||||
#define OB_BORH_DISABLE 0x00000000U /*!< BOR high status bit disabled */
|
||||
#define OB_BORH_ENABLE FLASH_OPTSR_BORH_EN /*!< BOR high status bit enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type
|
||||
* @{
|
||||
*/
|
||||
#define OB_IWDG_HW 0x00000000U /*!< Hardware independent watchdog */
|
||||
#define OB_IWDG_SW FLASH_OPTSR_IWDG_SW /*!< Software independent watchdog */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type
|
||||
* @{
|
||||
*/
|
||||
#define OB_WWDG_HW 0x00000000U /*!< Hardware window watchdog */
|
||||
#define OB_WWDG_SW FLASH_OPTSR_WWDG_SW /*!< Software window watchdog */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes nRST_STOP
|
||||
* @{
|
||||
*/
|
||||
#define OB_STOP_RST 0x00000000U /*!< Reset generated when entering in stop mode */
|
||||
#define OB_STOP_NORST FLASH_OPTSR_NRST_STOP /*!< No reset generated when entering in stop mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes nRST_STDBY
|
||||
* @{
|
||||
*/
|
||||
#define OB_STANDBY_RST 0x00000000U /*!< Reset generated when entering in standby mode */
|
||||
#define OB_STANDBY_NORST FLASH_OPTSR_NRST_STDBY /*!< No reset generated when entering in standby mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_Product_State FLASH Product State
|
||||
* @{
|
||||
*/
|
||||
#define OB_PROD_STATE_OPEN (0xEDU << FLASH_OPTSR_PRODUCT_STATE_Pos)
|
||||
#define OB_PROD_STATE_PROVISIONING (0x17U << FLASH_OPTSR_PRODUCT_STATE_Pos)
|
||||
#define OB_PROD_STATE_IROT_PROVISIONED (0x2EU << FLASH_OPTSR_PRODUCT_STATE_Pos)
|
||||
#define OB_PROD_STATE_TZ_CLOSED (0xC6U << FLASH_OPTSR_PRODUCT_STATE_Pos)
|
||||
#define OB_PROD_STATE_CLOSED (0x72U << FLASH_OPTSR_PRODUCT_STATE_Pos)
|
||||
#define OB_PROD_STATE_LOCKED (0x5CU << FLASH_OPTSR_PRODUCT_STATE_Pos)
|
||||
#define OB_PROD_STATE_REGRESSION (0x9AU << FLASH_OPTSR_PRODUCT_STATE_Pos)
|
||||
#define OB_PROD_STATE_NS_REGRESSION (0xA3U << FLASH_OPTSR_PRODUCT_STATE_Pos)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_IO_VDD_HSLV FLASH Option Bytes VDD IO HSLV
|
||||
* @{
|
||||
*/
|
||||
#define OB_IO_VDD_HSLV_DISABLE 0x00000000U /*!< High-speed IO at low VDD voltage feature disabled */
|
||||
#define OB_IO_VDD_HSLV_ENABLE FLASH_OPTSR_IO_VDD_HSLV /*!< High-speed IO at low VDD voltage feature enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_IO_VDDIO2_HSLV FLASH Option Bytes VDDIO2 IO HSLV
|
||||
* @{
|
||||
*/
|
||||
#define OB_IO_VDDIO2_HSLV_DISABLE 0x00000000U /*!< High-speed IO at low VDDIO2 voltage feature
|
||||
disabled */
|
||||
#define OB_IO_VDDIO2_HSLV_ENABLE FLASH_OPTSR_IO_VDDIO2_HSLV /*!< High-speed IO at low VDDIO2 voltage feature
|
||||
enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_IWDG_STOP FLASH IWDG Counter Freeze in STOP
|
||||
* @{
|
||||
*/
|
||||
#define OB_IWDG_STOP_FREEZE 0x00000000U /*!< IWDG counter frozen in STOP mode */
|
||||
#define OB_IWDG_STOP_ACTIVE FLASH_OPTSR_IWDG_STOP /*!< IWDG counter active in STOP mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH IWDG Counter Freeze in STANDBY
|
||||
* @{
|
||||
*/
|
||||
#define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< IWDG counter frozen in STANDBY mode */
|
||||
#define OB_IWDG_STDBY_ACTIVE FLASH_OPTSR_IWDG_STDBY /*!< IWDG counter active in STANDBY mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_BOOT_UBE FLASH OB Boot UBE
|
||||
* @{
|
||||
*/
|
||||
#if defined (FLASH_OPTSR_BOOT_UBE)
|
||||
#define OB_UBE_OEM_IROT (0xB4U << FLASH_OPTSR_BOOT_UBE_Pos) /*!< OEM-iRoT (user flash) selected */
|
||||
#define OB_UBE_ST_IROT (0xC3U << FLASH_OPTSR_BOOT_UBE_Pos) /*!< ST-iRoT (system flash) selected */
|
||||
#endif /* FLASH_OPTSR_BOOT_UBE */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_SWAP_BANK FLASH OB SWAP BANK
|
||||
* @{
|
||||
*/
|
||||
#define OB_SWAP_BANK_DISABLE 0x00000000U /*!< Bank swap disabled */
|
||||
#define OB_SWAP_BANK_ENABLE FLASH_OPTSR_SWAP_BANK /*!< Bank swap enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_SRAM1_3_RST FLASH Option Bytes SRAM1_3 Erase On Reset
|
||||
* @{
|
||||
*/
|
||||
#if defined (FLASH_OPTSR2_SRAM1_3_RST)
|
||||
#define OB_SRAM1_3_RST_ERASE 0x00000000U /*!< SRAM1 and SRAM3 erased when a system reset occurs */
|
||||
#define OB_SRAM1_3_RST_NOT_ERASE FLASH_OPTSR2_SRAM1_3_RST /*!< SRAM1 and SRAM3 are not erased when a system reset
|
||||
occurs */
|
||||
#endif /* FLASH_OPTSR2_SRAM1_3_RST */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_SRAM1_RST FLASH Option Bytes SRAM1 Erase On Reset
|
||||
* @{
|
||||
*/
|
||||
#if defined (FLASH_OPTSR2_SRAM1_RST)
|
||||
#define OB_SRAM1_RST_ERASE 0x00000000U /*!< SRAM1 erased when a system reset occurs */
|
||||
#define OB_SRAM1_RST_NOT_ERASE FLASH_OPTSR2_SRAM1_RST /*!< SRAM1 is not erased when a system reset occurs */
|
||||
#endif /* FLASH_OPTSR2_SRAM1_RST */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup FLASH_OB_USER_SRAM2_RST FLASH Option Bytes SRAM2 Erase On Reset
|
||||
* @{
|
||||
*/
|
||||
#define OB_SRAM2_RST_ERASE 0x00000000U /*!< SRAM2 erased when a system reset occurs */
|
||||
#define OB_SRAM2_RST_NOT_ERASE FLASH_OPTSR2_SRAM2_RST /*!< SRAM2 is not erased when a system reset occurs */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_BKPRAM_ECC FLASH Option Bytes User BKPRAM ECC check
|
||||
* @{
|
||||
*/
|
||||
#define OB_BKPRAM_ECC_ENABLE 0x00000000U /*!< BKPRAM ECC check enable */
|
||||
#define OB_BKPRAM_ECC_DISABLE FLASH_OPTSR2_BKPRAM_ECC /*!< BKPRAM ECC check disable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_SRAM3_ECC FLASH Option Bytes User SRAM3 ECC check
|
||||
* @{
|
||||
*/
|
||||
#if defined (FLASH_OPTSR2_SRAM3_ECC)
|
||||
#define OB_SRAM3_ECC_ENABLE 0x00000000U /*!< SRAM3 ECC check enable */
|
||||
#define OB_SRAM3_ECC_DISABLE FLASH_OPTSR2_SRAM3_ECC /*!< SRAM3 ECC check disable */
|
||||
#endif /* FLASH_OPTSR2_SRAM3_ECC */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_SRAM2_ECC FLASH Option Bytes User SRAM2 ECC check
|
||||
* @{
|
||||
*/
|
||||
#define OB_SRAM2_ECC_ENABLE 0x00000000U /*!< SRAM2 ECC check enable */
|
||||
#define OB_SRAM2_ECC_DISABLE FLASH_OPTSR2_SRAM2_ECC /*!< SRAM2 ECC check disable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_SRAM1_ECC FLASH Option Bytes User SRAM1 ECC check
|
||||
* @{
|
||||
*/
|
||||
#if defined (FLASH_OPTSR2_SRAM1_ECC)
|
||||
#define OB_SRAM1_ECC_ENABLE 0x00000000U /*!< SRAM1 ECC check enable */
|
||||
#define OB_SRAM1_ECC_DISABLE FLASH_OPTSR2_SRAM1_ECC /*!< SRAM1 ECC check disable */
|
||||
#endif /* FLASH_OPTSR2_SRAM1_ECC */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_TZEN FLASH Option Bytes Global TrustZone
|
||||
* @{
|
||||
*/
|
||||
#if defined (FLASH_OPTSR2_TZEN)
|
||||
#define OB_TZEN_DISABLE (0xC3U << FLASH_OPTSR2_TZEN_Pos) /*!< Global TrustZone security disabled */
|
||||
#define OB_TZEN_ENABLE (0xB4U << FLASH_OPTSR2_TZEN_Pos) /*!< Global TrustZone security enabled */
|
||||
#endif /* FLASH_OPTSR2_TZEN */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Banks FLASH Banks
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_BANK_1 0x00000001U /*!< Bank 1 */
|
||||
#define FLASH_BANK_2 0x00000002U /*!< Bank 2 */
|
||||
#define FLASH_BANK_BOTH (FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_Write_Protection_Sectors FLASH Option Bytes Write Protection Sectors
|
||||
* @{
|
||||
*/
|
||||
#if (FLASH_SECTOR_NB == 128)
|
||||
#define OB_WRP_SECTOR_0TO3 0x00000001U /*!< Write protection of Sector0 to Sector3 */
|
||||
#define OB_WRP_SECTOR_4TO7 0x00000002U /*!< Write protection of Sector4 to Sector7 */
|
||||
#define OB_WRP_SECTOR_8TO11 0x00000004U /*!< Write protection of Sector8 to Sector11 */
|
||||
#define OB_WRP_SECTOR_12TO15 0x00000008U /*!< Write protection of Sector12 to Sector15 */
|
||||
#define OB_WRP_SECTOR_16TO19 0x00000010U /*!< Write protection of Sector16 to Sector19 */
|
||||
#define OB_WRP_SECTOR_20TO23 0x00000020U /*!< Write protection of Sector20 to Sector23 */
|
||||
#define OB_WRP_SECTOR_24TO27 0x00000040U /*!< Write protection of Sector24 to Sector27 */
|
||||
#define OB_WRP_SECTOR_28TO31 0x00000080U /*!< Write protection of Sector28 to Sector31 */
|
||||
#define OB_WRP_SECTOR_32TO35 0x00000100U /*!< Write protection of Sector32 to Sector35 */
|
||||
#define OB_WRP_SECTOR_36TO39 0x00000200U /*!< Write protection of Sector36 to Sector39 */
|
||||
#define OB_WRP_SECTOR_40TO43 0x00000400U /*!< Write protection of Sector40 to Sector43 */
|
||||
#define OB_WRP_SECTOR_44TO47 0x00000800U /*!< Write protection of Sector44 to Sector47 */
|
||||
#define OB_WRP_SECTOR_48TO51 0x00001000U /*!< Write protection of Sector48 to Sector51 */
|
||||
#define OB_WRP_SECTOR_52TO55 0x00002000U /*!< Write protection of Sector52 to Sector55 */
|
||||
#define OB_WRP_SECTOR_56TO59 0x00004000U /*!< Write protection of Sector56 to Sector59 */
|
||||
#define OB_WRP_SECTOR_60TO63 0x00008000U /*!< Write protection of Sector60 to Sector63 */
|
||||
#define OB_WRP_SECTOR_64TO67 0x00010000U /*!< Write protection of Sector64 to Sector67 */
|
||||
#define OB_WRP_SECTOR_68TO71 0x00020000U /*!< Write protection of Sector68 to Sector71 */
|
||||
#define OB_WRP_SECTOR_72TO75 0x00040000U /*!< Write protection of Sector72 to Sector75 */
|
||||
#define OB_WRP_SECTOR_76TO79 0x00080000U /*!< Write protection of Sector76 to Sector79 */
|
||||
#define OB_WRP_SECTOR_80TO83 0x00100000U /*!< Write protection of Sector80 to Sector83 */
|
||||
#define OB_WRP_SECTOR_84TO87 0x00200000U /*!< Write protection of Sector84 to Sector87 */
|
||||
#define OB_WRP_SECTOR_88TO91 0x00400000U /*!< Write protection of Sector88 to Sector91 */
|
||||
#define OB_WRP_SECTOR_92TO95 0x00800000U /*!< Write protection of Sector92 to Sector95 */
|
||||
#define OB_WRP_SECTOR_96TO99 0x01000000U /*!< Write protection of Sector96 to Sector99 */
|
||||
#define OB_WRP_SECTOR_100TO103 0x02000000U /*!< Write protection of Sector100 to Sector103 */
|
||||
#define OB_WRP_SECTOR_104TO107 0x04000000U /*!< Write protection of Sector104 to Sector107 */
|
||||
#define OB_WRP_SECTOR_108TO111 0x08000000U /*!< Write protection of Sector108 to Sector111 */
|
||||
#define OB_WRP_SECTOR_112TO115 0x10000000U /*!< Write protection of Sector112 to Sector115 */
|
||||
#define OB_WRP_SECTOR_116TO119 0x20000000U /*!< Write protection of Sector116 to Sector119 */
|
||||
#define OB_WRP_SECTOR_120TO123 0x40000000U /*!< Write protection of Sector120 to Sector123 */
|
||||
#define OB_WRP_SECTOR_124TO127 0x80000000U /*!< Write protection of Sector124 to Sector127 */
|
||||
#define OB_WRP_SECTOR_ALL 0xFFFFFFFFU /*!< Write protection of all Sectors */
|
||||
#else
|
||||
#define OB_WRP_SECTOR_0 0x00000001U /*!< Write protection of Sector0 */
|
||||
#define OB_WRP_SECTOR_1 0x00000002U /*!< Write protection of Sector1 */
|
||||
#define OB_WRP_SECTOR_2 0x00000004U /*!< Write protection of Sector2 */
|
||||
#define OB_WRP_SECTOR_3 0x00000008U /*!< Write protection of Sector3 */
|
||||
#define OB_WRP_SECTOR_4 0x00000010U /*!< Write protection of Sector4 */
|
||||
#define OB_WRP_SECTOR_5 0x00000020U /*!< Write protection of Sector5 */
|
||||
#define OB_WRP_SECTOR_6 0x00000040U /*!< Write protection of Sector6 */
|
||||
#define OB_WRP_SECTOR_7 0x00000080U /*!< Write protection of Sector7 */
|
||||
#define OB_WRP_SECTOR_ALL 0x000000FFU /*!< Write protection of all Sectors */
|
||||
#endif /* (FLASH_SECTOR_NB == 128) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Programming_Delay FLASH Programming Delay
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_PROGRAMMING_DELAY_0 0x00000000U /*!< programming delay set for Flash running at 70 MHz or
|
||||
below */
|
||||
#define FLASH_PROGRAMMING_DELAY_1 FLASH_ACR_WRHIGHFREQ_0 /*!< programming delay set for Flash running between 70 MHz
|
||||
and 185 MHz */
|
||||
#define FLASH_PROGRAMMING_DELAY_2 FLASH_ACR_WRHIGHFREQ_1 /*!< programming delay set for Flash running between 185 MHz
|
||||
and 225 MHz */
|
||||
#define FLASH_PROGRAMMING_DELAY_3 FLASH_ACR_WRHIGHFREQ /*!< programming delay set for Flash at startup */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OTP_Blocks FLASH OTP blocks
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_OTP_BLOCK_0 0x00000001U /*!< OTP Block0 */
|
||||
#define FLASH_OTP_BLOCK_1 0x00000002U /*!< OTP Block1 */
|
||||
#define FLASH_OTP_BLOCK_2 0x00000004U /*!< OTP Block2 */
|
||||
#define FLASH_OTP_BLOCK_3 0x00000008U /*!< OTP Block3 */
|
||||
#define FLASH_OTP_BLOCK_4 0x00000010U /*!< OTP Block4 */
|
||||
#define FLASH_OTP_BLOCK_5 0x00000020U /*!< OTP Block5 */
|
||||
#define FLASH_OTP_BLOCK_6 0x00000040U /*!< OTP Block6 */
|
||||
#define FLASH_OTP_BLOCK_7 0x00000080U /*!< OTP Block7 */
|
||||
#define FLASH_OTP_BLOCK_8 0x00000100U /*!< OTP Block8 */
|
||||
#define FLASH_OTP_BLOCK_9 0x00000200U /*!< OTP Block9 */
|
||||
#define FLASH_OTP_BLOCK_10 0x00000400U /*!< OTP Block10 */
|
||||
#define FLASH_OTP_BLOCK_11 0x00000800U /*!< OTP Block11 */
|
||||
#define FLASH_OTP_BLOCK_12 0x00001000U /*!< OTP Block12 */
|
||||
#define FLASH_OTP_BLOCK_13 0x00002000U /*!< OTP Block13 */
|
||||
#define FLASH_OTP_BLOCK_14 0x00004000U /*!< OTP Block14 */
|
||||
#define FLASH_OTP_BLOCK_15 0x00008000U /*!< OTP Block15 */
|
||||
#define FLASH_OTP_BLOCK_16 0x00010000U /*!< OTP Block16 */
|
||||
#define FLASH_OTP_BLOCK_17 0x00020000U /*!< OTP Block17 */
|
||||
#define FLASH_OTP_BLOCK_18 0x00040000U /*!< OTP Block18 */
|
||||
#define FLASH_OTP_BLOCK_19 0x00080000U /*!< OTP Block19 */
|
||||
#define FLASH_OTP_BLOCK_20 0x00100000U /*!< OTP Block20 */
|
||||
#define FLASH_OTP_BLOCK_21 0x00200000U /*!< OTP Block21 */
|
||||
#define FLASH_OTP_BLOCK_22 0x00400000U /*!< OTP Block22 */
|
||||
#define FLASH_OTP_BLOCK_23 0x00800000U /*!< OTP Block23 */
|
||||
#define FLASH_OTP_BLOCK_24 0x01000000U /*!< OTP Block24 */
|
||||
#define FLASH_OTP_BLOCK_25 0x02000000U /*!< OTP Block25 */
|
||||
#define FLASH_OTP_BLOCK_26 0x04000000U /*!< OTP Block26 */
|
||||
#define FLASH_OTP_BLOCK_27 0x08000000U /*!< OTP Block27 */
|
||||
#define FLASH_OTP_BLOCK_28 0x10000000U /*!< OTP Block28 */
|
||||
#define FLASH_OTP_BLOCK_29 0x20000000U /*!< OTP Block29 */
|
||||
#define FLASH_OTP_BLOCK_30 0x40000000U /*!< OTP Block30 */
|
||||
#define FLASH_OTP_BLOCK_31 0x80000000U /*!< OTP Block31 */
|
||||
#define FLASH_OTP_BLOCK_ALL 0xFFFFFFFFU /*!< OTP All Blocks */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_WRP_State FLASH WRP State
|
||||
* @{
|
||||
*/
|
||||
#define OB_WRPSTATE_DISABLE 0x00000000U /*!< Disable the write protection of the desired flash sectors */
|
||||
#define OB_WRPSTATE_ENABLE 0x00000001U /*!< Enable the write protection of the desired flash sectors */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_BOOT_CONFIG FLASH Option Bytes Boot configuration
|
||||
* @{
|
||||
*/
|
||||
#define OB_BOOT_NS 0x00000001U /*!< Non-secure boot address */
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
#define OB_BOOT_SEC 0x00000002U /*!< Secure boot address */
|
||||
#endif /* __ARM_FEATURE_CMSE */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_BOOT_LOCK FLASH Option Bytes Boot Lock
|
||||
* @{
|
||||
*/
|
||||
#define OB_BOOT_LOCK_DISABLE 0xC3U /*!< Boot lock disable */
|
||||
#define OB_BOOT_LOCK_ENABLE 0xB4U /*!< Boot lock enable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_BB_Attributes FLASH Block-Base Attributes
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_BB_SEC 0x01U /*!< Flash Block-Based Security Attributes */
|
||||
#define FLASH_BB_PRIV 0x02U /*!< Flash Block-Based Privilege Attributes */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_PRIV_MODE FLASH privilege mode
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_NSPRIV_GRANTED 0x00000000U /*!< access to non-secure Flash registers is granted to privileged
|
||||
or unprivileged access */
|
||||
#define FLASH_NSPRIV_DENIED FLASH_PRIVCFGR_NSPRIV /*!< access to non-secure Flash registers is denied to
|
||||
non-privilege access */
|
||||
|
||||
#define FLASH_SPRIV_GRANTED 0x00000000U /*!< access to secure Flash registers is granted to privileged or
|
||||
unprivileged access */
|
||||
#if defined (FLASH_PRIVCFGR_SPRIV)
|
||||
#define FLASH_SPRIV_DENIED FLASH_PRIVCFGR_SPRIV /*!< access to secure Flash registers is denied to non-privilege
|
||||
access */
|
||||
#endif /* FLASH_PRIVCFGR_SPRIV */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined (FLASH_SR_OBKERR)
|
||||
/** @defgroup FLASH_OBK_SWAP_Offset FLASH OBK Swap Offset
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_OBK_SWAP_OFFSET_NO_DATA 0x000U /*!< No data will be copied from current to alternate OBK */
|
||||
#define FLASH_OBK_SWAP_OFFSET_HDPL0 0x010U /*!< HDPL0 data will be copied from current to alternate OBK */
|
||||
#define FLASH_OBK_SWAP_OFFSET_HDPL1 0x090U /*!< HDPL0/1 data will be copied from current to alternate OBK */
|
||||
#define FLASH_OBK_SWAP_OFFSET_HDPL2 0x0C0U /*!< HDPL0/1/2 data will be copied from current to alternate OBK */
|
||||
#define FLASH_OBK_SWAP_OFFSET_HDPL3_S 0x180U /*!< HDPL0/1/2/3_S data will be copied from current to alternate
|
||||
OBK */
|
||||
#define FLASH_OBK_SWAP_OFFSET_ALL 0x1FFU /*!< All OBK data (511) will be copied from current to alternate
|
||||
OBK */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* FLASH_SR_OBKERR */
|
||||
|
||||
/** @defgroup FLASH_Operation_Type FLASH Operation Type
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_OPERATION_TYPE_NONE 00000000U /*!< No Flash operation */
|
||||
#define FLASH_OPERATION_TYPE_QUADWORD FLASH_OPSR_CODE_OP_0 /*!< Single write operation */
|
||||
#if defined (FLASH_SR_OBKERR)
|
||||
#define FLASH_OPERATION_TYPE_OBKALTERASE FLASH_OPSR_CODE_OP_1 /*!< OBK alternate sector erase
|
||||
operation */
|
||||
#endif /* FLASH_SR_OBKERR */
|
||||
#define FLASH_OPERATION_TYPE_SECTORERASE (FLASH_OPSR_CODE_OP_1 | FLASH_OPSR_CODE_OP_0) /*!< Sector erase operation */
|
||||
#define FLASH_OPERATION_TYPE_BANKERASE FLASH_OPSR_CODE_OP_2 /*!< Bank erase operation */
|
||||
#define FLASH_OPERATION_TYPE_MASSERASE (FLASH_OPSR_CODE_OP_2 | FLASH_OPSR_CODE_OP_0) /*!< Mass erase operation */
|
||||
#define FLASH_OPERATION_TYPE_OPTIONCHANGE (FLASH_OPSR_CODE_OP_2 | FLASH_OPSR_CODE_OP_1) /*!< Option change operation */
|
||||
#if defined (FLASH_SR_OBKERR)
|
||||
#define FLASH_OPERATION_TYPE_OBKSWAP (FLASH_OPSR_CODE_OP_2 | FLASH_OPSR_CODE_OP_1 | FLASH_OPSR_CODE_OP_0) /*!< OBK
|
||||
swap operation */
|
||||
#endif /* FLASH_SR_OBKERR */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Operation_Area FLASH Operation Area
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_OPERATION_AREA_BANK_1 00000000U /*!< Operation in Flash Bank 1 */
|
||||
#define FLASH_OPERATION_AREA_BANK_2 FLASH_OPSR_BK_OP /*!< Operation in Flash Bank 2 */
|
||||
#define FLASH_OPERATION_AREA_SYSF FLASH_OPSR_SYSF_OP /*!< Operation in System Flash memory */
|
||||
#if defined (FLASH_EDATAR_EDATA_EN)
|
||||
#define FLASH_OPERATION_AREA_DATA FLASH_OPSR_DATA_OP /*!< Operation in Flash high-cycle data area */
|
||||
#endif /* FLASH_EDATAR_EDATA_EN */
|
||||
#define FLASH_OPERATION_AREA_OTP FLASH_OPSR_OTP_OP /*!< Operation in Flash OTP area */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
/** @defgroup SEC_INVERSION_CFG FLASH security inversion configuration
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_INV_DISABLE 0x00000000U /*!< Security state of Flash is not inverted */
|
||||
#define FLASH_INV_ENABLE FLASH_CR_INV /*!< Security state of Flash is inverted */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* __ARM_FEATURE_CMSE */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported macros ------------------------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Exported_Macros FLASHEx Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the FLASH prefetch buffer.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
|
||||
|
||||
/**
|
||||
* @brief Disable the FLASH prefetch buffer.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
|
||||
|
||||
/**
|
||||
* @brief Enable the FLASH smart prefetch buffer.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FLASH_SMART_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_S_PRFTEN)
|
||||
|
||||
/**
|
||||
* @brief Disable the FLASH smart prefetch buffer.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FLASH_SMART_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_S_PRFTEN)
|
||||
|
||||
/**
|
||||
* @brief Set the FLASH Programming Delay.
|
||||
* @param __DELAY__ FLASH Programming Delay
|
||||
* This parameter can be a value of @ref FLASH_Programming_Delay
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_SET_PROGRAM_DELAY(__DELAY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_WRHIGHFREQ, (__DELAY__))
|
||||
|
||||
/**
|
||||
* @brief Get the FLASH Programming Delay.
|
||||
* @retval FLASH Programming Delay
|
||||
* This return value can be a value of @ref FLASH_Programming_Delay
|
||||
*/
|
||||
#define __HAL_FLASH_GET_PROGRAM_DELAY() READ_BIT(FLASH->ACR, FLASH_ACR_WRHIGHFREQ)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup FLASHEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASHEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Extension Erase and OB Program operation functions ******************************/
|
||||
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError);
|
||||
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
|
||||
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
|
||||
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
|
||||
#if defined (FLASH_SR_OBKERR)
|
||||
HAL_StatusTypeDef HAL_FLASHEx_OBK_Unlock(void);
|
||||
HAL_StatusTypeDef HAL_FLASHEx_OBK_Lock(void);
|
||||
HAL_StatusTypeDef HAL_FLASHEx_OBK_Swap(uint32_t SwapOffset);
|
||||
#endif /* FLASH_SR_OBKERR */
|
||||
void HAL_FLASHEx_GetOperation(FLASH_OperationTypeDef *pFlashOperation);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASHEx_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* Extension Protection configuration functions *************************************/
|
||||
HAL_StatusTypeDef HAL_FLASHEx_ConfigBBAttributes(FLASH_BBAttributesTypeDef *pBBAttributes);
|
||||
void HAL_FLASHEx_GetConfigBBAttributes(FLASH_BBAttributesTypeDef *pBBAttributes);
|
||||
void HAL_FLASHEx_ConfigPrivMode(uint32_t PrivMode);
|
||||
uint32_t HAL_FLASHEx_GetPrivMode(void);
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
HAL_StatusTypeDef HAL_FLASHEx_ConfigSecInversion(uint32_t SecInvState);
|
||||
uint32_t HAL_FLASHEx_GetSecInversion(void);
|
||||
#endif /* __ARM_FEATURE_CMSE */
|
||||
HAL_StatusTypeDef HAL_FLASHEx_ConfigHDPExtension(const FLASH_HDPExtensionTypeDef *pHDPExtension);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_TYPEPROGRAM_OB (0x00008000U | FLASH_NON_SECURE_MASK) /*!< Program Option Bytes operation type */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_IS_FLASH_Definitions FLASHEx Private macros to check input parameters
|
||||
* @{
|
||||
*/
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_SECTORS) || \
|
||||
((VALUE) == FLASH_TYPEERASE_SECTORS_NS) || \
|
||||
((VALUE) == FLASH_TYPEERASE_MASSERASE) || \
|
||||
((VALUE) == FLASH_TYPEERASE_MASSERASE_NS) || \
|
||||
((VALUE) == FLASH_TYPEERASE_OBK_ALT))
|
||||
#else
|
||||
#if defined (FLASH_SR_OBKERR)
|
||||
#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_SECTORS) || \
|
||||
((VALUE) == FLASH_TYPEERASE_MASSERASE) || \
|
||||
((VALUE) == FLASH_TYPEERASE_OBK_ALT))
|
||||
#else
|
||||
#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_SECTORS) || \
|
||||
((VALUE) == FLASH_TYPEERASE_MASSERASE))
|
||||
#endif /* FLASH_SR_OBKERR */
|
||||
#endif /* __ARM_FEATURE_CMSE */
|
||||
|
||||
#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || \
|
||||
((VALUE) == OB_WRPSTATE_ENABLE))
|
||||
|
||||
#define IS_OPTIONBYTE(VALUE) ((((VALUE) & OPTIONBYTE_ALL) != 0U) && \
|
||||
(((VALUE) & ~OPTIONBYTE_ALL) == 0U))
|
||||
|
||||
#define IS_OB_PRODUCT_STATE(STATE) (((STATE) == OB_PROD_STATE_OPEN) || \
|
||||
((STATE) == OB_PROD_STATE_PROVISIONING) || \
|
||||
((STATE) == OB_PROD_STATE_IROT_PROVISIONED) || \
|
||||
((STATE) == OB_PROD_STATE_TZ_CLOSED) || \
|
||||
((STATE) == OB_PROD_STATE_CLOSED) || \
|
||||
((STATE) == OB_PROD_STATE_LOCKED) || \
|
||||
((STATE) == OB_PROD_STATE_REGRESSION) || \
|
||||
((STATE) == OB_PROD_STATE_NS_REGRESSION))
|
||||
|
||||
#define IS_OB_USER_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL_1) || ((LEVEL) == OB_BOR_LEVEL_2) || \
|
||||
((LEVEL) == OB_BOR_LEVEL_3))
|
||||
|
||||
#define IS_OB_USER_BORH_EN(VALUE) (((VALUE) == OB_BORH_DISABLE) || ((VALUE) == OB_BORH_ENABLE))
|
||||
|
||||
#define IS_OB_USER_IWDG(VALUE) (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW))
|
||||
|
||||
#define IS_OB_USER_WWDG(VALUE) (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW))
|
||||
|
||||
#define IS_OB_USER_STOP(VALUE) (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST))
|
||||
|
||||
#define IS_OB_USER_STANDBY(VALUE) (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST))
|
||||
|
||||
#define IS_OB_USER_IO_VDD_HSLV(VALUE) (((VALUE) == OB_IO_VDD_HSLV_DISABLE) || \
|
||||
((VALUE) == OB_IO_VDD_HSLV_ENABLE))
|
||||
|
||||
#define IS_OB_USER_IO_VDDIO2_HSLV(VALUE) (((VALUE) == OB_IO_VDDIO2_HSLV_DISABLE) || \
|
||||
((VALUE) == OB_IO_VDDIO2_HSLV_ENABLE))
|
||||
|
||||
#define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_ACTIVE))
|
||||
|
||||
#define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_ACTIVE))
|
||||
|
||||
#define IS_OB_USER_BOOT_UBE(VALUE) (((VALUE) == OB_UBE_OEM_IROT) || ((VALUE) == OB_UBE_ST_IROT))
|
||||
|
||||
#define IS_OB_USER_SWAP_BANK(VALUE) (((VALUE) == OB_SWAP_BANK_DISABLE) || ((VALUE) == OB_SWAP_BANK_ENABLE))
|
||||
|
||||
#if defined (FLASH_OPTSR2_SRAM1_3_RST)
|
||||
#define IS_OB_USER_SRAM1_3_RST(VALUE) (((VALUE) == OB_SRAM1_3_RST_ERASE) || ((VALUE) == OB_SRAM1_3_RST_NOT_ERASE))
|
||||
#endif /* FLASH_OPTSR2_SRAM1_3_RST */
|
||||
|
||||
#if defined (FLASH_OPTSR2_SRAM1_RST)
|
||||
#define IS_OB_USER_SRAM1_RST(VALUE) (((VALUE) == OB_SRAM1_RST_ERASE) || ((VALUE) == OB_SRAM1_RST_NOT_ERASE))
|
||||
#endif /* FLASH_OPTSR2_SRAM1_RST */
|
||||
|
||||
#define IS_OB_USER_SRAM2_RST(VALUE) (((VALUE) == OB_SRAM2_RST_ERASE) || ((VALUE) == OB_SRAM2_RST_NOT_ERASE))
|
||||
|
||||
#define IS_OB_USER_BKPRAM_ECC(VALUE) (((VALUE) == OB_BKPRAM_ECC_ENABLE) || ((VALUE) == OB_BKPRAM_ECC_DISABLE))
|
||||
|
||||
#if defined (FLASH_OPTSR2_SRAM3_ECC)
|
||||
#define IS_OB_USER_SRAM3_ECC(VALUE) (((VALUE) == OB_SRAM3_ECC_ENABLE) || ((VALUE) == OB_SRAM3_ECC_DISABLE))
|
||||
#endif /* FLASH_OPTSR2_SRAM3_ECC */
|
||||
|
||||
#if defined (FLASH_OPTSR2_SRAM1_ECC)
|
||||
#define IS_OB_USER_SRAM1_ECC(VALUE) (((VALUE) == OB_SRAM1_ECC_ENABLE) || ((VALUE) == OB_SRAM1_ECC_DISABLE))
|
||||
#endif /* FLASH_OPTSR2_SRAM1_ECC */
|
||||
|
||||
#define IS_OB_USER_SRAM2_ECC(VALUE) (((VALUE) == OB_SRAM2_ECC_ENABLE) || ((VALUE) == OB_SRAM2_ECC_DISABLE))
|
||||
|
||||
#define IS_OB_USER_TZEN(VALUE) (((VALUE) == OB_TZEN_DISABLE) || ((VALUE) == OB_TZEN_ENABLE))
|
||||
|
||||
#define IS_OB_USER_TYPE(TYPE) ((((TYPE) & OB_USER_ALL) != 0U) && \
|
||||
(((TYPE) & ~OB_USER_ALL) == 0U))
|
||||
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
#define IS_OB_BOOT_CONFIG(CFG) (((CFG) == OB_BOOT_NS) || ((CFG) == OB_BOOT_SEC))
|
||||
#else
|
||||
#define IS_OB_BOOT_CONFIG(CFG) ((CFG) == OB_BOOT_NS)
|
||||
#endif /* __ARM_FEATURE_CMSE */
|
||||
|
||||
#define IS_OB_BOOT_LOCK(VALUE) (((VALUE) == OB_BOOT_LOCK_DISABLE) || ((VALUE) == OB_BOOT_LOCK_ENABLE))
|
||||
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
#define IS_FLASH_BB_EXCLUSIVE(CFG) (((CFG) == FLASH_BB_SEC) || ((CFG) == FLASH_BB_PRIV))
|
||||
#else
|
||||
#define IS_FLASH_BB_EXCLUSIVE(CFG) ((CFG) == FLASH_BB_PRIV)
|
||||
#endif /* __ARM_FEATURE_CMSE */
|
||||
|
||||
#define IS_FLASH_CFGPRIVMODE(CFG) (((CFG) & 0xFFFFFFFCU) == 0U)
|
||||
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
#define IS_FLASH_CFGSECINV(CFG) (((CFG) == FLASH_INV_DISABLE) || ((CFG) == FLASH_INV_ENABLE))
|
||||
#endif /* __ARM_FEATURE_CMSE */
|
||||
|
||||
#define IS_FLASH_EDATA_SIZE(SECTOR) ((SECTOR) <= FLASH_EDATA_SECTOR_NB)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
|
||||
* @{
|
||||
*/
|
||||
void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H5xx_HAL_FLASH_EX_H */
|
||||
|
|
@ -0,0 +1,727 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h5xx_hal_fmac.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header for stm32h5xx_hal_fmac.c module
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H5xx_HAL_FMAC_H
|
||||
#define STM32H5xx_HAL_FMAC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h5xx_hal_def.h"
|
||||
|
||||
#if defined(FMAC)
|
||||
/** @addtogroup STM32H5xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FMAC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup FMAC_Exported_Types FMAC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FMAC HAL State Structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_FMAC_STATE_RESET = 0x00U, /*!< FMAC not yet initialized or disabled */
|
||||
HAL_FMAC_STATE_READY = 0x20U, /*!< FMAC initialized and ready for use */
|
||||
HAL_FMAC_STATE_BUSY = 0x24U, /*!< FMAC internal process is ongoing */
|
||||
HAL_FMAC_STATE_BUSY_RD = 0x25U, /*!< FMAC reading configuration is ongoing */
|
||||
HAL_FMAC_STATE_BUSY_WR = 0x26U, /*!< FMAC writing configuration is ongoing */
|
||||
HAL_FMAC_STATE_TIMEOUT = 0xA0U, /*!< FMAC in Timeout state */
|
||||
HAL_FMAC_STATE_ERROR = 0xE0U /*!< FMAC in Error state */
|
||||
} HAL_FMAC_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FMAC Handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __FMAC_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
|
||||
{
|
||||
FMAC_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
uint32_t FilterParam; /*!< Filter configuration (operation and parameters).
|
||||
Set to 0 if no valid configuration was applied. */
|
||||
|
||||
uint8_t InputAccess; /*!< Access to the input buffer (internal memory area):
|
||||
DMA, IT, Polling, None.
|
||||
This parameter can be a value of @ref FMAC_Buffer_Access. */
|
||||
|
||||
uint8_t OutputAccess; /*!< Access to the output buffer (internal memory area):
|
||||
DMA, IT, Polling, None.
|
||||
This parameter can be a value of @ref FMAC_Buffer_Access. */
|
||||
|
||||
int16_t *pInput; /*!< Pointer to FMAC input data buffer */
|
||||
|
||||
uint16_t InputCurrentSize; /*!< Number of the input elements already written into FMAC */
|
||||
|
||||
uint16_t *pInputSize; /*!< Number of input elements to write (memory allocated to pInput).
|
||||
In case of early interruption of the filter operation,
|
||||
its value will be updated. */
|
||||
|
||||
int16_t *pOutput; /*!< Pointer to FMAC output data buffer */
|
||||
|
||||
uint16_t OutputCurrentSize; /*!< Number of the output elements already read from FMAC */
|
||||
|
||||
uint16_t *pOutputSize; /*!< Number of output elements to read (memory allocated to pOutput).
|
||||
In case of early interruption of the filter operation,
|
||||
its value will be updated. */
|
||||
|
||||
DMA_HandleTypeDef *hdmaIn; /*!< FMAC peripheral input data DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmaOut; /*!< FMAC peripheral output data DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmaPreload; /*!< FMAC peripheral preloaded data (X1, X2 and Y) DMA handle
|
||||
parameters */
|
||||
|
||||
#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
|
||||
void (* ErrorCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC error callback */
|
||||
|
||||
void (* HalfGetDataCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC get half data callback */
|
||||
|
||||
void (* GetDataCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC get data callback */
|
||||
|
||||
void (* HalfOutputDataReadyCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC half output data ready callback */
|
||||
|
||||
void (* OutputDataReadyCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC output data ready callback */
|
||||
|
||||
void (* FilterConfigCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC filter configuration callback */
|
||||
|
||||
void (* FilterPreloadCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC filter preload callback */
|
||||
|
||||
void (* MspInitCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC Msp Init callback */
|
||||
|
||||
void (* MspDeInitCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC Msp DeInit callback */
|
||||
|
||||
#endif /* (USE_HAL_FMAC_REGISTER_CALLBACKS) */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< FMAC locking object */
|
||||
|
||||
__IO HAL_FMAC_StateTypeDef State; /*!< FMAC state related to global handle management
|
||||
This parameter can be a value of @ref HAL_FMAC_StateTypeDef */
|
||||
|
||||
__IO HAL_FMAC_StateTypeDef RdState; /*!< FMAC state related to read operations (access to Y buffer)
|
||||
This parameter can be a value of @ref HAL_FMAC_StateTypeDef */
|
||||
|
||||
__IO HAL_FMAC_StateTypeDef WrState; /*!< FMAC state related to write operations (access to X1 buffer)
|
||||
This parameter can be a value of @ref HAL_FMAC_StateTypeDef */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< FMAC peripheral error code
|
||||
This parameter can be a value of @ref FMAC_Error_Code */
|
||||
|
||||
} FMAC_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief FMAC Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_FMAC_ERROR_CB_ID = 0x00U, /*!< FMAC error callback ID */
|
||||
HAL_FMAC_HALF_GET_DATA_CB_ID = 0x01U, /*!< FMAC get half data callback ID */
|
||||
HAL_FMAC_GET_DATA_CB_ID = 0x02U, /*!< FMAC get data callback ID */
|
||||
HAL_FMAC_HALF_OUTPUT_DATA_READY_CB_ID = 0x03U, /*!< FMAC half output data ready callback ID */
|
||||
HAL_FMAC_OUTPUT_DATA_READY_CB_ID = 0x04U, /*!< FMAC output data ready callback ID */
|
||||
HAL_FMAC_FILTER_CONFIG_CB_ID = 0x05U, /*!< FMAC filter configuration callback ID */
|
||||
HAL_FMAC_FILTER_PRELOAD_CB_ID = 0x06U, /*!< FMAC filter preload callback ID */
|
||||
|
||||
HAL_FMAC_MSPINIT_CB_ID = 0x07U, /*!< FMAC MspInit callback ID */
|
||||
HAL_FMAC_MSPDEINIT_CB_ID = 0x08U, /*!< FMAC MspDeInit callback ID */
|
||||
} HAL_FMAC_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL FMAC Callback pointer definition
|
||||
*/
|
||||
typedef void (*pFMAC_CallbackTypeDef)(FMAC_HandleTypeDef *hfmac); /*!< pointer to an FMAC callback function */
|
||||
|
||||
#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @brief FMAC Filter Configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t InputBaseAddress; /*!< Base address of the input buffer (X1) within the internal memory
|
||||
(0x00 to 0xFF). Ignored if InputBufferSize is set to 0
|
||||
(previous configuration kept).
|
||||
Note: the buffers can overlap or even coincide exactly. */
|
||||
|
||||
uint8_t InputBufferSize; /*!< Number of 16-bit words allocated to the input buffer
|
||||
(including the optional "headroom").
|
||||
0 if a previous configuration should be kept. */
|
||||
|
||||
uint32_t InputThreshold; /*!< Input threshold: the buffer full flag will be set if the number
|
||||
of free spaces in the buffer is lower than this threshold.
|
||||
This parameter can be a value
|
||||
of @ref FMAC_Data_Buffer_Threshold. */
|
||||
|
||||
uint8_t CoeffBaseAddress; /*!< Base address of the coefficient buffer (X2) within the internal
|
||||
memory (0x00 to 0xFF). Ignored if CoeffBufferSize is set to 0
|
||||
(previous configuration kept).
|
||||
Note: the buffers can overlap or even coincide exactly. */
|
||||
|
||||
uint8_t CoeffBufferSize; /*!< Number of 16-bit words allocated to the coefficient buffer.
|
||||
0 if a previous configuration should be kept. */
|
||||
|
||||
uint8_t OutputBaseAddress; /*!< Base address of the output buffer (Y) within the internal
|
||||
memory (0x00 to 0xFF). Ignored if OuputBufferSize is set to 0
|
||||
(previous configuration kept).
|
||||
Note: the buffers can overlap or even coincide exactly. */
|
||||
|
||||
uint8_t OutputBufferSize; /*!< Number of 16-bit words allocated to the output buffer
|
||||
(including the optional "headroom").
|
||||
0 if a previous configuration should be kept. */
|
||||
|
||||
uint32_t OutputThreshold; /*!< Output threshold: the buffer empty flag will be set if the number
|
||||
of unread values in the buffer is lower than this threshold.
|
||||
This parameter can be a value
|
||||
of @ref FMAC_Data_Buffer_Threshold. */
|
||||
|
||||
int16_t *pCoeffA; /*!< [IIR only] Initialization of the coefficient vector A.
|
||||
If not needed, it should be set to NULL. */
|
||||
|
||||
uint8_t CoeffASize; /*!< Size of the coefficient vector A. */
|
||||
|
||||
int16_t *pCoeffB; /*!< Initialization of the coefficient vector B.
|
||||
If not needed (re-use of a previously loaded buffer),
|
||||
it should be set to NULL. */
|
||||
|
||||
uint8_t CoeffBSize; /*!< Size of the coefficient vector B. */
|
||||
|
||||
uint8_t InputAccess; /*!< Access to the input buffer (internal memory area):
|
||||
DMA, IT, Polling, None.
|
||||
This parameter can be a value of @ref FMAC_Buffer_Access. */
|
||||
|
||||
uint8_t OutputAccess; /*!< Access to the output buffer (internal memory area):
|
||||
DMA, IT, Polling, None.
|
||||
This parameter can be a value of @ref FMAC_Buffer_Access. */
|
||||
|
||||
uint32_t Clip; /*!< Enable or disable the clipping feature. If the q1.15 range
|
||||
is exceeded, wrapping is done when the clipping feature is disabled
|
||||
and saturation is done when the clipping feature is enabled.
|
||||
This parameter can be a value of @ref FMAC_Clip_State. */
|
||||
|
||||
uint32_t Filter; /*!< Filter type.
|
||||
This parameter can be a value
|
||||
of @ref FMAC_Functions (filter related values). */
|
||||
|
||||
uint8_t P; /*!< Parameter P (vector length, number of filter taps, etc.). */
|
||||
|
||||
uint8_t Q; /*!< Parameter Q (vector length, etc.). Ignored if not needed. */
|
||||
|
||||
uint8_t R; /*!< Parameter R (gain, etc.). Ignored if not needed. */
|
||||
|
||||
} FMAC_FilterConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
|
||||
/** @defgroup FMAC_Exported_Constants FMAC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FMAC_Error_Code FMAC Error code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_FMAC_ERROR_NONE 0x00000000U /*!< No error */
|
||||
#define HAL_FMAC_ERROR_SAT 0x00000001U /*!< Saturation error */
|
||||
#define HAL_FMAC_ERROR_UNFL 0x00000002U /*!< Underflow error */
|
||||
#define HAL_FMAC_ERROR_OVFL 0x00000004U /*!< Overflow error */
|
||||
#define HAL_FMAC_ERROR_DMA 0x00000008U /*!< DMA error */
|
||||
#define HAL_FMAC_ERROR_RESET 0x00000010U /*!< Reset error */
|
||||
#define HAL_FMAC_ERROR_PARAM 0x00000020U /*!< Parameter error */
|
||||
#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_FMAC_ERROR_INVALID_CALLBACK 0x00000040U /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
|
||||
#define HAL_FMAC_ERROR_TIMEOUT 0x00000080U /*!< Timeout error */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMAC_Functions FMAC Functions
|
||||
* @{
|
||||
*/
|
||||
#define FMAC_FUNC_LOAD_X1 (FMAC_PARAM_FUNC_0) /*!< Load X1 buffer */
|
||||
#define FMAC_FUNC_LOAD_X2 (FMAC_PARAM_FUNC_1) /*!< Load X2 buffer */
|
||||
#define FMAC_FUNC_LOAD_Y (FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0) /*!< Load Y buffer */
|
||||
#define FMAC_FUNC_CONVO_FIR (FMAC_PARAM_FUNC_3) /*!< Convolution (FIR filter) */
|
||||
#define FMAC_FUNC_IIR_DIRECT_FORM_1 (FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0) /*!< IIR filter (direct form 1) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMAC_Data_Buffer_Threshold FMAC Data Buffer Threshold
|
||||
* @{
|
||||
* @note This parameter sets a watermark for buffer full (input) or buffer empty (output).
|
||||
*/
|
||||
#define FMAC_THRESHOLD_1 0x00000000U /*!< Input: Buffer full flag set if the number of free spaces
|
||||
in the buffer is less than 1.
|
||||
Output: Buffer empty flag set if the number
|
||||
of unread values in the buffer is less than 1. */
|
||||
#define FMAC_THRESHOLD_2 0x01000000U /*!< Input: Buffer full flag set if the number of free spaces
|
||||
in the buffer is less than 2.
|
||||
Output: Buffer empty flag set if the number
|
||||
of unread values in the buffer is less than 2. */
|
||||
#define FMAC_THRESHOLD_4 0x02000000U /*!< Input: Buffer full flag set if the number of free spaces
|
||||
in the buffer is less than 4.
|
||||
Output: Buffer empty flag set if the number
|
||||
of unread values in the buffer is less than 4. */
|
||||
#define FMAC_THRESHOLD_8 0x03000000U /*!< Input: Buffer full flag set if the number of free spaces
|
||||
in the buffer is less than 8.
|
||||
Output: Buffer empty flag set if the number
|
||||
of unread values in the buffer is less than 8. */
|
||||
#define FMAC_THRESHOLD_NO_VALUE 0xFFFFFFFFU /*!< The configured threshold value shouldn't be changed */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMAC_Buffer_Access FMAC Buffer Access
|
||||
* @{
|
||||
*/
|
||||
#define FMAC_BUFFER_ACCESS_NONE 0x00U /*!< Buffer handled by an external IP (ADC for instance) */
|
||||
#define FMAC_BUFFER_ACCESS_DMA 0x01U /*!< Buffer accessed through DMA */
|
||||
#define FMAC_BUFFER_ACCESS_POLLING 0x02U /*!< Buffer accessed through polling */
|
||||
#define FMAC_BUFFER_ACCESS_IT 0x03U /*!< Buffer accessed through interruptions */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMAC_Clip_State FMAC Clip State
|
||||
* @{
|
||||
*/
|
||||
#define FMAC_CLIP_DISABLED 0x00000000U /*!< Clipping disabled */
|
||||
#define FMAC_CLIP_ENABLED FMAC_CR_CLIPEN /*!< Clipping enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMAC_Flags FMAC status flags
|
||||
* @{
|
||||
*/
|
||||
#define FMAC_FLAG_YEMPTY FMAC_SR_YEMPTY /*!< Y Buffer Empty Flag */
|
||||
#define FMAC_FLAG_X1FULL FMAC_SR_X1FULL /*!< X1 Buffer Full Flag */
|
||||
#define FMAC_FLAG_OVFL FMAC_SR_OVFL /*!< Overflow Error Flag */
|
||||
#define FMAC_FLAG_UNFL FMAC_SR_UNFL /*!< Underflow Error Flag */
|
||||
#define FMAC_FLAG_SAT FMAC_SR_SAT /*!< Saturation Error Flag
|
||||
(this helps in debugging a filter) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMAC_Interrupts_Enable FMAC Interrupts Enable bit
|
||||
* @{
|
||||
*/
|
||||
#define FMAC_IT_RIEN FMAC_CR_RIEN /*!< Read Interrupt Enable */
|
||||
#define FMAC_IT_WIEN FMAC_CR_WIEN /*!< Write Interrupt Enable */
|
||||
#define FMAC_IT_OVFLIEN FMAC_CR_OVFLIEN /*!< Overflow Error Interrupt Enable */
|
||||
#define FMAC_IT_UNFLIEN FMAC_CR_UNFLIEN /*!< Underflow Error Interrupt Enable */
|
||||
#define FMAC_IT_SATIEN FMAC_CR_SATIEN /*!< Saturation Error Interrupt Enable
|
||||
(this helps in debugging a filter) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported variables --------------------------------------------------------*/
|
||||
/** @defgroup FMAC_Exported_variables FMAC Exported variables
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup FMAC_Exported_Macros FMAC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Reset FMAC handle state.
|
||||
* @param __HANDLE__ FMAC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_FMAC_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_FMAC_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0U)
|
||||
#else
|
||||
#define __HAL_FMAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FMAC_STATE_RESET)
|
||||
#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @brief Enable the specified FMAC interrupt
|
||||
* @param __HANDLE__ FMAC handle.
|
||||
* @param __INTERRUPT__ FMAC Interrupt.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref FMAC_IT_RIEN Read interrupt enable
|
||||
* @arg @ref FMAC_IT_WIEN Write interrupt enable
|
||||
* @arg @ref FMAC_IT_OVFLIEN Overflow error interrupt enable
|
||||
* @arg @ref FMAC_IT_UNFLIEN Underflow error interrupt enable
|
||||
* @arg @ref FMAC_IT_SATIEN Saturation error interrupt enable (this helps in debugging a filter)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FMAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
|
||||
(((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the FMAC interrupt
|
||||
* @param __HANDLE__ FMAC handle.
|
||||
* @param __INTERRUPT__ FMAC Interrupt.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref FMAC_IT_RIEN Read interrupt enable
|
||||
* @arg @ref FMAC_IT_WIEN Write interrupt enable
|
||||
* @arg @ref FMAC_IT_OVFLIEN Overflow error interrupt enable
|
||||
* @arg @ref FMAC_IT_UNFLIEN Underflow error interrupt enable
|
||||
* @arg @ref FMAC_IT_SATIEN Saturation error interrupt enable (this helps in debugging a filter)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FMAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
|
||||
(((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified FMAC interrupt occurred or not.
|
||||
* @param __HANDLE__ FMAC handle.
|
||||
* @param __INTERRUPT__ FMAC interrupt to check.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref FMAC_FLAG_YEMPTY Y Buffer Empty Flag
|
||||
* @arg @ref FMAC_FLAG_X1FULL X1 Buffer Full Flag
|
||||
* @arg @ref FMAC_FLAG_OVFL Overflow Error Flag
|
||||
* @arg @ref FMAC_FLAG_UNFL Underflow Error Flag
|
||||
* @arg @ref FMAC_FLAG_SAT Saturation Error Flag
|
||||
* @retval SET (interrupt occurred) or RESET (interrupt did not occurred)
|
||||
*/
|
||||
#define __HAL_FMAC_GET_IT(__HANDLE__, __INTERRUPT__) \
|
||||
(((__HANDLE__)->Instance->SR) &= ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Clear specified FMAC interrupt status. Dummy macro as the
|
||||
interrupt status flags are read-only.
|
||||
* @param __HANDLE__ FMAC handle.
|
||||
* @param __INTERRUPT__ FMAC interrupt to clear.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FMAC_CLEAR_IT(__HANDLE__, __INTERRUPT__) /* Dummy macro */
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified FMAC status flag is set or not.
|
||||
* @param __HANDLE__ FMAC handle.
|
||||
* @param __FLAG__ FMAC flag to check.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref FMAC_FLAG_YEMPTY Y Buffer Empty Flag
|
||||
* @arg @ref FMAC_FLAG_X1FULL X1 Buffer Full Flag
|
||||
* @arg @ref FMAC_FLAG_OVFL Overflow Error Flag
|
||||
* @arg @ref FMAC_FLAG_UNFL Underflow Error Flag
|
||||
* @arg @ref FMAC_FLAG_SAT Saturation error Flag
|
||||
* @retval SET (flag is set) or RESET (flag is reset)
|
||||
*/
|
||||
#define __HAL_FMAC_GET_FLAG(__HANDLE__, __FLAG__) \
|
||||
((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Clear specified FMAC status flag. Dummy macro as no
|
||||
flag can be cleared.
|
||||
* @param __HANDLE__ FMAC handle.
|
||||
* @param __FLAG__ FMAC flag to clear.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FMAC_CLEAR_FLAG(__HANDLE__, __FLAG__) /* Dummy macro */
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified FMAC interrupt is enabled or not.
|
||||
* @param __HANDLE__ FMAC handle.
|
||||
* @param __INTERRUPT__ FMAC interrupt to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref FMAC_IT_RIEN Read interrupt enable
|
||||
* @arg @ref FMAC_IT_WIEN Write interrupt enable
|
||||
* @arg @ref FMAC_IT_OVFLIEN Overflow error interrupt enable
|
||||
* @arg @ref FMAC_IT_UNFLIEN Underflow error interrupt enable
|
||||
* @arg @ref FMAC_IT_SATIEN Saturation error interrupt enable (this helps in debugging a filter)
|
||||
* @retval FlagStatus
|
||||
*/
|
||||
#define __HAL_FMAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
|
||||
(((__HANDLE__)->Instance->CR) & (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private defines -----------------------------------------------------------*/
|
||||
/** @addtogroup FMAC_Private_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FMAC_PARAM_P_MAX_IIR 64U /*!< Maximum value of P parameter with IIR */
|
||||
#define FMAC_PARAM_P_MAX_FIR 127U /*!< Maximum value of P parameter with FIR */
|
||||
#define FMAC_PARAM_P_MIN 2U /*!< Minimum value of P parameter */
|
||||
#define FMAC_PARAM_Q_MAX 63U /*!< Maximum value of Q parameter */
|
||||
#define FMAC_PARAM_Q_MIN 1U /*!< Minimum value of Q parameter */
|
||||
#define FMAC_PARAM_R_MAX 7U /*!< Maximum value of R parameter */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private Macros-----------------------------------------------------------*/
|
||||
/** @addtogroup FMAC_Private_Macros FMAC Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Verify the FMAC function.
|
||||
* @param __FUNCTION__ ID of the function.
|
||||
* @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
|
||||
*/
|
||||
#define IS_FMAC_FUNCTION(__FUNCTION__) (((__FUNCTION__) == FMAC_FUNC_LOAD_X1) || \
|
||||
((__FUNCTION__) == FMAC_FUNC_LOAD_X2) || \
|
||||
((__FUNCTION__) == FMAC_FUNC_LOAD_Y) || \
|
||||
((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \
|
||||
((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1))
|
||||
|
||||
/**
|
||||
* @brief Verify the FMAC load function used for input data, output data or coefficients.
|
||||
* @param __FUNCTION__ ID of the load function.
|
||||
* @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
|
||||
*/
|
||||
#define IS_FMAC_LOAD_FUNCTION(__FUNCTION__) (((__FUNCTION__) == FMAC_FUNC_LOAD_X1) || \
|
||||
((__FUNCTION__) == FMAC_FUNC_LOAD_X2) || \
|
||||
((__FUNCTION__) == FMAC_FUNC_LOAD_Y))
|
||||
|
||||
/**
|
||||
* @brief Verify the FMAC load function used with N values as input or output data.
|
||||
* @param __FUNCTION__ ID of the load function.
|
||||
* @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
|
||||
*/
|
||||
#define IS_FMAC_N_LOAD_FUNCTION(__FUNCTION__) (((__FUNCTION__) == FMAC_FUNC_LOAD_X1) || \
|
||||
((__FUNCTION__) == FMAC_FUNC_LOAD_Y))
|
||||
|
||||
/**
|
||||
* @brief Verify the FMAC load function used with N + M values as coefficients.
|
||||
* @param __FUNCTION__ ID of the load function.
|
||||
* @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
|
||||
*/
|
||||
#define IS_FMAC_N_M_LOAD_FUNCTION(__FUNCTION__) ((__FUNCTION__) == FMAC_FUNC_LOAD_X2)
|
||||
|
||||
/**
|
||||
* @brief Verify the FMAC filter function.
|
||||
* @param __FUNCTION__ ID of the filter function.
|
||||
* @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
|
||||
*/
|
||||
#define IS_FMAC_FILTER_FUNCTION(__FUNCTION__) (((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \
|
||||
((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Verify the FMAC threshold.
|
||||
* @param __THRESHOLD__ Value of the threshold.
|
||||
* @retval SET (__THRESHOLD__ is a valid value) or RESET (__THRESHOLD__ is invalid)
|
||||
*/
|
||||
#define IS_FMAC_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == FMAC_THRESHOLD_1) || \
|
||||
((__THRESHOLD__) == FMAC_THRESHOLD_2) || \
|
||||
((__THRESHOLD__) == FMAC_THRESHOLD_4) || \
|
||||
((__THRESHOLD__) == FMAC_THRESHOLD_NO_VALUE) || \
|
||||
((__THRESHOLD__) == FMAC_THRESHOLD_8))
|
||||
|
||||
/**
|
||||
* @brief Verify the FMAC filter parameter P.
|
||||
* @param __P__ Value of the filter parameter P.
|
||||
* @param __FUNCTION__ ID of the filter function.
|
||||
* @retval SET (__P__ is a valid value) or RESET (__P__ is invalid)
|
||||
*/
|
||||
#define IS_FMAC_PARAM_P(__FUNCTION__, __P__) ((((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) && \
|
||||
(((__P__) >= FMAC_PARAM_P_MIN) && \
|
||||
((__P__) <= FMAC_PARAM_P_MAX_FIR))) || \
|
||||
(((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1) && \
|
||||
(((__P__) >= FMAC_PARAM_P_MIN) && \
|
||||
((__P__) <= FMAC_PARAM_P_MAX_IIR))))
|
||||
|
||||
/**
|
||||
* @brief Verify the FMAC filter parameter Q.
|
||||
* @param __Q__ Value of the filter parameter Q.
|
||||
* @param __FUNCTION__ ID of the filter function.
|
||||
* @retval SET (__Q__ is a valid value) or RESET (__Q__ is invalid)
|
||||
*/
|
||||
#define IS_FMAC_PARAM_Q(__FUNCTION__, __Q__) ( ((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \
|
||||
(((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1) && \
|
||||
(((__Q__) >= FMAC_PARAM_Q_MIN) && ((__Q__) <= FMAC_PARAM_Q_MAX))) )
|
||||
|
||||
/**
|
||||
* @brief Verify the FMAC filter parameter R.
|
||||
* @param __R__ Value of the filter parameter.
|
||||
* @param __FUNCTION__ ID of the filter function.
|
||||
* @retval SET (__R__ is a valid value) or RESET (__R__ is invalid)
|
||||
*/
|
||||
#define IS_FMAC_PARAM_R(__FUNCTION__, __R__) ( (((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \
|
||||
((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1)) && \
|
||||
((__R__) <= FMAC_PARAM_R_MAX))
|
||||
|
||||
/**
|
||||
* @brief Verify the FMAC buffer access.
|
||||
* @param __BUFFER_ACCESS__ Type of access.
|
||||
* @retval SET (__BUFFER_ACCESS__ is a valid value) or RESET (__BUFFER_ACCESS__ is invalid)
|
||||
*/
|
||||
#define IS_FMAC_BUFFER_ACCESS(__BUFFER_ACCESS__) (((__BUFFER_ACCESS__) == FMAC_BUFFER_ACCESS_NONE) || \
|
||||
((__BUFFER_ACCESS__) == FMAC_BUFFER_ACCESS_DMA) || \
|
||||
((__BUFFER_ACCESS__) == FMAC_BUFFER_ACCESS_POLLING) || \
|
||||
((__BUFFER_ACCESS__) == FMAC_BUFFER_ACCESS_IT))
|
||||
|
||||
/**
|
||||
* @brief Verify the FMAC clip feature.
|
||||
* @param __CLIP_STATE__ Clip state.
|
||||
* @retval SET (__CLIP_STATE__ is a valid value) or RESET (__CLIP_STATE__ is invalid)
|
||||
*/
|
||||
#define IS_FMAC_CLIP_STATE(__CLIP_STATE__) (((__CLIP_STATE__) == FMAC_CLIP_DISABLED) || \
|
||||
((__CLIP_STATE__) == FMAC_CLIP_ENABLED))
|
||||
|
||||
/**
|
||||
* @brief Check whether the threshold is applicable.
|
||||
* @param __SIZE__ Size of the matching buffer.
|
||||
* @param __WM__ Watermark value.
|
||||
* @param __ACCESS__ Access to the buffer (polling, it, dma, none).
|
||||
* @retval THRESHOLD
|
||||
*/
|
||||
#define IS_FMAC_THRESHOLD_APPLICABLE(__SIZE__, __WM__, __ACCESS__) \
|
||||
(( (__SIZE__) >= (((__WM__) == FMAC_THRESHOLD_1)? 1U: \
|
||||
((__WM__) == FMAC_THRESHOLD_2)? 2U: \
|
||||
((__WM__) == FMAC_THRESHOLD_4)? 4U:8U))&& \
|
||||
((((__ACCESS__) == FMAC_BUFFER_ACCESS_DMA)&& \
|
||||
((__WM__) == FMAC_THRESHOLD_1))|| \
|
||||
((__ACCESS__ )!= FMAC_BUFFER_ACCESS_DMA)))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
/** @addtogroup FMAC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FMAC_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_FMAC_Init(FMAC_HandleTypeDef *hfmac);
|
||||
HAL_StatusTypeDef HAL_FMAC_DeInit(FMAC_HandleTypeDef *hfmac);
|
||||
void HAL_FMAC_MspInit(FMAC_HandleTypeDef *hfmac);
|
||||
void HAL_FMAC_MspDeInit(FMAC_HandleTypeDef *hfmac);
|
||||
|
||||
#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
HAL_StatusTypeDef HAL_FMAC_RegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_CallbackIDTypeDef CallbackID,
|
||||
pFMAC_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FMAC_UnRegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FMAC_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig);
|
||||
HAL_StatusTypeDef HAL_FMAC_FilterConfig_DMA(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig);
|
||||
HAL_StatusTypeDef HAL_FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
|
||||
int16_t *pOutput, uint8_t OutputSize);
|
||||
HAL_StatusTypeDef HAL_FMAC_FilterPreload_DMA(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
|
||||
int16_t *pOutput, uint8_t OutputSize);
|
||||
HAL_StatusTypeDef HAL_FMAC_FilterStart(FMAC_HandleTypeDef *hfmac, int16_t *pOutput, uint16_t *pOutputSize);
|
||||
HAL_StatusTypeDef HAL_FMAC_AppendFilterData(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint16_t *pInputSize);
|
||||
HAL_StatusTypeDef HAL_FMAC_ConfigFilterOutputBuffer(FMAC_HandleTypeDef *hfmac, int16_t *pOutput, uint16_t *pOutputSize);
|
||||
HAL_StatusTypeDef HAL_FMAC_PollFilterData(FMAC_HandleTypeDef *hfmac, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_FMAC_FilterStop(FMAC_HandleTypeDef *hfmac);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FMAC_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Callback functions *********************************************************/
|
||||
void HAL_FMAC_ErrorCallback(FMAC_HandleTypeDef *hfmac);
|
||||
void HAL_FMAC_HalfGetDataCallback(FMAC_HandleTypeDef *hfmac);
|
||||
void HAL_FMAC_GetDataCallback(FMAC_HandleTypeDef *hfmac);
|
||||
void HAL_FMAC_HalfOutputDataReadyCallback(FMAC_HandleTypeDef *hfmac);
|
||||
void HAL_FMAC_OutputDataReadyCallback(FMAC_HandleTypeDef *hfmac);
|
||||
void HAL_FMAC_FilterConfigCallback(FMAC_HandleTypeDef *hfmac);
|
||||
void HAL_FMAC_FilterPreloadCallback(FMAC_HandleTypeDef *hfmac);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FMAC_Exported_Functions_Group4
|
||||
* @{
|
||||
*/
|
||||
/* IRQ handler management *****************************************************/
|
||||
void HAL_FMAC_IRQHandler(FMAC_HandleTypeDef *hfmac);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FMAC_Exported_Functions_Group5
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions *************************************************/
|
||||
HAL_FMAC_StateTypeDef HAL_FMAC_GetState(const FMAC_HandleTypeDef *hfmac);
|
||||
uint32_t HAL_FMAC_GetError(const FMAC_HandleTypeDef *hfmac);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* FMAC */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H5xx_HAL_FMAC_H */
|
||||
|
|
@ -0,0 +1,393 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h5xx_hal_gpio.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of GPIO HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H5xx_HAL_GPIO_H
|
||||
#define STM32H5xx_HAL_GPIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h5xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H5xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO GPIO
|
||||
* @brief GPIO HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Types GPIO Exported Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief GPIO Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
|
||||
This parameter can be a value of @ref GPIO_pins */
|
||||
|
||||
uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_mode */
|
||||
|
||||
uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_pull */
|
||||
|
||||
uint32_t Speed; /*!< Specifies the speed for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_speed */
|
||||
|
||||
uint32_t Alternate; /*!< Peripheral to be connected to the selected pins
|
||||
This parameter can be a value of @ref GPIOEx_Alternate_function_selection */
|
||||
} GPIO_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief GPIO Bit SET and Bit RESET enumeration
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_PIN_RESET = 0U,
|
||||
GPIO_PIN_SET
|
||||
} GPIO_PinState;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup GPIO_pins GPIO pins
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
|
||||
#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
|
||||
#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
|
||||
#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
|
||||
#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
|
||||
#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
|
||||
#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
|
||||
#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
|
||||
#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
|
||||
#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
|
||||
#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
|
||||
#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
|
||||
#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
|
||||
#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
|
||||
#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
|
||||
#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
|
||||
#define GPIO_PIN_ALL ((uint16_t)0xFFFF) /* All pins selected */
|
||||
|
||||
#define GPIO_PIN_MASK (0x0000FFFFU) /* PIN mask for assert test */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_mode GPIO mode
|
||||
* @brief GPIO Configuration Mode
|
||||
* Elements values convention: 0xX0yz00YZ
|
||||
* - X : GPIO mode or EXTI Mode
|
||||
* - y : External IT or Event trigger detection
|
||||
* - z : IO configuration on External IT or Event
|
||||
* - Y : Output type (Push Pull or Open Drain)
|
||||
* - Z : IO Direction mode (Input, Output, (Alternate or Analog))
|
||||
* @{
|
||||
*/
|
||||
/*!< Input Floating Mode */
|
||||
#define GPIO_MODE_INPUT (0x00000000U)
|
||||
/*!< Output Push Pull Mode */
|
||||
#define GPIO_MODE_OUTPUT_PP (0x00000001U)
|
||||
/*!< Output Open Drain Mode */
|
||||
#define GPIO_MODE_OUTPUT_OD (0x00000011U)
|
||||
/*!< Alternate Function Push Pull Mode */
|
||||
#define GPIO_MODE_AF_PP (0x00000002U)
|
||||
/*!< Alternate Function Open Drain Mode */
|
||||
#define GPIO_MODE_AF_OD (0x00000012U)
|
||||
/*!< Analog Mode */
|
||||
#define GPIO_MODE_ANALOG (0x00000003U)
|
||||
/*!< External Interrupt Mode with Rising edge trigger detection */
|
||||
#define GPIO_MODE_IT_RISING (0x10110000U)
|
||||
/*!< External Interrupt Mode with Falling edge trigger detection */
|
||||
#define GPIO_MODE_IT_FALLING (0x10210000U)
|
||||
/*!< External Interrupt Mode with Rising/Falling edge trigger detection */
|
||||
#define GPIO_MODE_IT_RISING_FALLING (0x10310000U)
|
||||
/*!< External Event Mode with Rising edge trigger detection */
|
||||
#define GPIO_MODE_EVT_RISING (0x10120000U)
|
||||
/*!< External Event Mode with Falling edge trigger detection */
|
||||
#define GPIO_MODE_EVT_FALLING (0x10220000U)
|
||||
/*!< External Event Mode with Rising/Falling edge trigger detection */
|
||||
#define GPIO_MODE_EVT_RISING_FALLING (0x10320000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_speed GPIO speed
|
||||
* @brief GPIO Output Maximum frequency
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Low speed */
|
||||
#define GPIO_SPEED_FREQ_MEDIUM (0x00000001U) /*!< Medium speed */
|
||||
#define GPIO_SPEED_FREQ_HIGH (0x00000002U) /*!< High speed */
|
||||
#define GPIO_SPEED_FREQ_VERY_HIGH (0x00000003U) /*!< Very-high speed */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_pull GPIO pull
|
||||
* @brief GPIO Pull-Up or Pull-Down Activation
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_NOPULL (0x00000000U) /*!< No Pull-up or Pull-down activation */
|
||||
#define GPIO_PULLUP (0x00000001U) /*!< Pull-up activation */
|
||||
#define GPIO_PULLDOWN (0x00000002U) /*!< Pull-down activation */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
|
||||
/** @defgroup GPIO_attributes GPIO attributes
|
||||
* @brief GPIO pin secure or non-secure attributes
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_PIN_SEC (0x00000001U) /*!< Secure pin attribute */
|
||||
#define GPIO_PIN_NSEC (0x00000000U) /*!< Non-secure pin attribute */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* __ARM_FEATURE_CMSE */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified EXTI line is rising edge asserted or not.
|
||||
* @param __EXTI_LINE__: specifies the EXTI line to check.
|
||||
* This parameter can be GPIO_PIN_x where x can be(0..15)
|
||||
* @retval The new state of __EXTI_LINE__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_GET_RISING_IT(__EXTI_LINE__) (EXTI->RPR1 & (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Clear the EXTI's line rising pending bits.
|
||||
* @param __EXTI_LINE__: specifies the EXTI lines to clear.
|
||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_CLEAR_RISING_IT(__EXTI_LINE__) (EXTI->RPR1 = (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified EXTI line is falling edge asserted or not.
|
||||
* @param __EXTI_LINE__: specifies the EXTI line to check.
|
||||
* This parameter can be GPIO_PIN_x where x can be(0..15)
|
||||
* @retval The new state of __EXTI_LINE__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_GET_FALLING_IT(__EXTI_LINE__) (EXTI->FPR1 & (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Clear the EXTI's line falling pending bits.
|
||||
* @param __EXTI_LINE__: specifies the EXTI lines to clear.
|
||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_CLEAR_FALLING_IT(__EXTI_LINE__) (EXTI->FPR1 = (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified EXTI line is asserted or not.
|
||||
* @param __EXTI_LINE__: specifies the EXTI line to check.
|
||||
* This parameter can be GPIO_PIN_x where x can be(0..15)
|
||||
* @retval The new state of __EXTI_LINE__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (__HAL_GPIO_EXTI_GET_RISING_IT(__EXTI_LINE__) || \
|
||||
__HAL_GPIO_EXTI_GET_FALLING_IT(__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Clear the EXTI's line pending bits.
|
||||
* @param __EXTI_LINE__: specifies the EXTI lines to clear.
|
||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) \
|
||||
do { \
|
||||
__HAL_GPIO_EXTI_CLEAR_RISING_IT(__EXTI_LINE__); \
|
||||
__HAL_GPIO_EXTI_CLEAR_FALLING_IT(__EXTI_LINE__); \
|
||||
} while(0)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Generate a Software interrupt on selected EXTI line(s).
|
||||
* @param __EXTI_LINE__: specifies the EXTI line to set.
|
||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 = (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified EXTI line flag is set or not.
|
||||
* @param __EXTI_LINE__ specifies the EXTI line flag to check.
|
||||
* This parameter can be GPIO_PIN_x where x can be(0..15)
|
||||
* @retval The new state of __EXTI_LINE__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__)
|
||||
|
||||
/**
|
||||
* @brief Clear the EXTI line pending flags.
|
||||
* @param __EXTI_LINE__ specifies the EXTI lines flags to clear.
|
||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Private_Macros GPIO Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
|
||||
|
||||
#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
|
||||
(((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
|
||||
|
||||
#define IS_GPIO_COMMON_PIN(__RESETMASK__, __SETMASK__) \
|
||||
(((uint32_t)(__RESETMASK__) & (uint32_t)(__SETMASK__)) == 0x00u)
|
||||
|
||||
#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\
|
||||
((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\
|
||||
((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\
|
||||
((__MODE__) == GPIO_MODE_AF_PP) ||\
|
||||
((__MODE__) == GPIO_MODE_AF_OD) ||\
|
||||
((__MODE__) == GPIO_MODE_IT_RISING) ||\
|
||||
((__MODE__) == GPIO_MODE_IT_FALLING) ||\
|
||||
((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\
|
||||
((__MODE__) == GPIO_MODE_EVT_RISING) ||\
|
||||
((__MODE__) == GPIO_MODE_EVT_FALLING) ||\
|
||||
((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\
|
||||
((__MODE__) == GPIO_MODE_ANALOG))
|
||||
|
||||
#define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW) ||\
|
||||
((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) ||\
|
||||
((__SPEED__) == GPIO_SPEED_FREQ_HIGH) ||\
|
||||
((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH))
|
||||
|
||||
#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) ||\
|
||||
((__PULL__) == GPIO_PULLUP) || \
|
||||
((__PULL__) == GPIO_PULLDOWN))
|
||||
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
|
||||
#define IS_GPIO_PIN_ATTRIBUTES(__ATTRIBUTES__) (((__ATTRIBUTES__) == GPIO_PIN_SEC) ||\
|
||||
((__ATTRIBUTES__) == GPIO_PIN_NSEC))
|
||||
|
||||
#endif /* __ARM_FEATURE_CMSE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include GPIO HAL Extended module */
|
||||
#include "stm32h5xx_hal_gpio_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup GPIO_Exported_Functions GPIO Exported Functions
|
||||
* @brief GPIO Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init);
|
||||
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_Exported_Functions_Group2 IO operation functions
|
||||
* @brief IO operation functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
|
||||
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
|
||||
void HAL_GPIO_WriteMultipleStatePin(GPIO_TypeDef *GPIOx, uint16_t PinReset, uint16_t PinSet);
|
||||
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
|
||||
void HAL_GPIO_EnableHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
|
||||
void HAL_GPIO_DisableHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
|
||||
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
|
||||
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
|
||||
void HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin);
|
||||
void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
|
||||
/** @addtogroup GPIO_Exported_Functions_Group3 IO attributes management functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* IO attributes management functions *****************************************/
|
||||
void HAL_GPIO_ConfigPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32_t PinAttributes);
|
||||
HAL_StatusTypeDef HAL_GPIO_GetConfigPinAttributes(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin,
|
||||
uint32_t *pPinAttributes);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* __ARM_FEATURE_CMSE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H5xx_HAL_GPIO_H */
|
||||
|
|
@ -0,0 +1,470 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h5xx_hal_gpio_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of GPIO HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H5xx_HAL_GPIO_EX_H
|
||||
#define STM32H5xx_HAL_GPIO_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h5xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H5xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIOEx GPIOEx
|
||||
* @brief GPIO Extended HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief AF 0 selection
|
||||
*/
|
||||
#define GPIO_AF0_RTC_50HZ ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
|
||||
#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
|
||||
#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
|
||||
#define GPIO_AF0_CSLEEP ((uint8_t)0x00) /* CSLEEP Alternate Function mapping */
|
||||
#define GPIO_AF0_CSTOP ((uint8_t)0x00) /* CSTOP Alternate Function mapping */
|
||||
#define GPIO_AF0_CRS ((uint8_t)0x00) /* CRS Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 1 selection
|
||||
*/
|
||||
#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
|
||||
#if defined(TIM16)
|
||||
#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
|
||||
#endif /* TIM16 */
|
||||
#if defined(TIM17)
|
||||
#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
|
||||
#endif /* TIM17 */
|
||||
#if (defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx))
|
||||
#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */
|
||||
#endif /* defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) */
|
||||
|
||||
/**
|
||||
* @brief AF 2 selection
|
||||
*/
|
||||
#if defined(STM32H503xx)
|
||||
#define GPIO_AF2_LPTIM1 ((uint8_t)0x02) /* LPTIM1 Alternate Function mapping */
|
||||
#endif /* STM32H503xx */
|
||||
#if defined(LPTIM3)
|
||||
#define GPIO_AF2_LPTIM3 ((uint8_t)0x02) /* LPTIM3 Alternate Function mapping */
|
||||
#endif /* LPTIM3 */
|
||||
#if defined(SAI1)
|
||||
#define GPIO_AF2_SAI1 ((uint8_t)0x02) /* SAI1 Alternate Function mapping */
|
||||
#endif /* SAI1 */
|
||||
#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
|
||||
#if defined(TIM4)
|
||||
#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
|
||||
#endif /* TIM4 */
|
||||
#if defined(TIM5)
|
||||
#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
|
||||
#endif /* TIM5 */
|
||||
#if defined(TIM12)
|
||||
#define GPIO_AF2_TIM12 ((uint8_t)0x02) /* TIM12 Alternate Function mapping */
|
||||
#endif /* TIM12 */
|
||||
#if defined(TIM15)
|
||||
#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
|
||||
#endif /* TIM15 */
|
||||
/**
|
||||
* @brief AF 3 selection
|
||||
*/
|
||||
#define GPIO_AF3_I3C1 ((uint8_t)0x03) /* I3C1 Alternate Function mapping */
|
||||
#if defined(I3C2)
|
||||
#define GPIO_AF3_I3C2 ((uint8_t)0x03) /* I3C2 Alternate Function mapping */
|
||||
#endif /* I3C2 */
|
||||
#define GPIO_AF3_LPTIM2 ((uint8_t)0x03) /* LPTIM2 Alternate Function mapping */
|
||||
#if defined(LPTIM3)
|
||||
#define GPIO_AF3_LPTIM3 ((uint8_t)0x03) /* LPTIM3 Alternate Function mapping */
|
||||
#endif /* LPTIM3 */
|
||||
#define GPIO_AF3_LPUART1 ((uint8_t)0x03) /* LPUART1 Alternate Function mapping */
|
||||
#if defined(OCTOSPI1)
|
||||
#define GPIO_AF3_OCTOSPI1 ((uint8_t)0x03) /* OCTOSPI1 Alternate Function mapping */
|
||||
#endif /* OCTOSPI1 */
|
||||
#if (defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx))
|
||||
#define GPIO_AF3_TIM1 ((uint8_t)0x03) /* TIM1 Alternate Function mapping */
|
||||
#endif /* defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) */
|
||||
#if defined(TIM8)
|
||||
#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
|
||||
#endif /* TIM8 */
|
||||
|
||||
/**
|
||||
* @brief AF 4 selection
|
||||
*/
|
||||
#if defined(CEC)
|
||||
#define GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */
|
||||
#endif /* CEC */
|
||||
#if defined(DCMI)
|
||||
#define GPIO_AF4_DCMI ((uint8_t)0x04) /* DCMI Alternate Function mapping */
|
||||
#define GPIO_AF4_PSSI ((uint8_t)0x04) /* PSSI Alternate Function mapping */
|
||||
#endif /* DCMI */
|
||||
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
|
||||
#if defined(I2C3)
|
||||
#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
|
||||
#endif /* I2C3 */
|
||||
#if defined(I2C4)
|
||||
#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */
|
||||
#endif /* I2C4 */
|
||||
#define GPIO_AF4_LPTIM1 ((uint8_t)0x04) /* LPTIM1 Alternate Function mapping */
|
||||
#define GPIO_AF4_LPTIM2 ((uint8_t)0x04) /* LPTIM2 Alternate Function mapping */
|
||||
#define GPIO_AF4_SPI1 ((uint8_t)0x04) /* SPI1 Alternate Function mapping */
|
||||
#if defined(TIM15)
|
||||
#define GPIO_AF4_TIM15 ((uint8_t)0x04) /* TIM15 Alternate Function mapping */
|
||||
#endif /* TIM15 */
|
||||
#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */
|
||||
#if defined(STM32H503xx)
|
||||
#define GPIO_AF4_USART2 ((uint8_t)0x04) /* USART2 Alternate Function mapping */
|
||||
#endif /* STM32H503xx */
|
||||
|
||||
/**
|
||||
* @brief AF 5 selection
|
||||
*/
|
||||
#if defined(CEC)
|
||||
#define GPIO_AF5_CEC ((uint8_t)0x05) /* CEC Alternate Function mapping */
|
||||
#endif /* CEC */
|
||||
#if (defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx))
|
||||
#define GPIO_AF5_I3C1 ((uint8_t)0x05) /* I3C1 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3 Alternate Function mapping */
|
||||
#endif /* defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) */
|
||||
#define GPIO_AF5_LPTIM1 ((uint8_t)0x05) /* LPTIM1 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */
|
||||
#if defined(SPI4)
|
||||
#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */
|
||||
#endif /* SPI4 */
|
||||
#if defined(SPI5)
|
||||
#define GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */
|
||||
#endif /* SPI5 */
|
||||
#if defined(SPI6)
|
||||
#define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */
|
||||
#endif /* SPI6 */
|
||||
|
||||
/**
|
||||
* @brief AF 6 selection
|
||||
*/
|
||||
#if defined(I2C4)
|
||||
#define GPIO_AF6_I2C4 ((uint8_t)0x06) /* I2C4 Alternate Function mapping */
|
||||
#endif /* I2C4 */
|
||||
#if defined(OCTOSPI1)
|
||||
#define GPIO_AF6_OCTOSPI1 ((uint8_t)0x06) /* OCTOSPI1 Alternate Function mapping */
|
||||
#endif /* OCTOSPI1 */
|
||||
#if defined(SAI1)
|
||||
#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */
|
||||
#endif /* SAI1 */
|
||||
#if defined(STM32H503xx)
|
||||
#define GPIO_AF6_SPI1 ((uint8_t)0x06) /* SPI1 Alternate Function mapping */
|
||||
#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2 Alternate Function mapping */
|
||||
#endif /* STM32H503xx */
|
||||
#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */
|
||||
#if defined(SPI4)
|
||||
#define GPIO_AF6_SPI4 ((uint8_t)0x06) /* SPI4 Alternate Function mapping */
|
||||
#endif /* SPI4 */
|
||||
#if defined(UART4)
|
||||
#define GPIO_AF6_UART4 ((uint8_t)0x06) /* UART4 Alternate Function mapping */
|
||||
#endif /* UART4 */
|
||||
#if defined(UART12)
|
||||
#define GPIO_AF6_UART12 ((uint8_t)0x06) /* UART12 Alternate Function mapping */
|
||||
#endif /* UART12 */
|
||||
#if defined(USART10)
|
||||
#define GPIO_AF6_USART10 ((uint8_t)0x06) /* USART10 Alternate Function mapping */
|
||||
#endif /* USART10 */
|
||||
#if defined(UCPD1)
|
||||
#define GPIO_AF6_UCPD1 ((uint8_t)0x06) /* UCPD1 Alternate Function mapping */
|
||||
#endif /* UCPD1 */
|
||||
|
||||
/**
|
||||
* @brief AF 7 selection
|
||||
*/
|
||||
#if defined(SDMMC1)
|
||||
#define GPIO_AF7_SDMMC1 ((uint8_t)0x07) /* SDMMC1 Alternate Function mapping */
|
||||
#endif /* SDMMC1 */
|
||||
#define GPIO_AF7_SPI2 ((uint8_t)0x07) /* SPI2 Alternate Function mapping */
|
||||
#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3 Alternate Function mapping */
|
||||
#if defined(SPI6)
|
||||
#define GPIO_AF7_SPI6 ((uint8_t)0x07) /* SPI6 Alternate Function mapping */
|
||||
#endif /* SPI6 */
|
||||
#if defined(UART7)
|
||||
#define GPIO_AF7_UART7 ((uint8_t)0x07) /* UART7 Alternate Function mapping */
|
||||
#endif /* UART7 */
|
||||
#if defined(UART8)
|
||||
#define GPIO_AF7_UART8 ((uint8_t)0x07) /* UART8 Alternate Function mapping */
|
||||
#endif /* UART8 */
|
||||
#if defined(UART12)
|
||||
#define GPIO_AF7_UART12 ((uint8_t)0x07) /* UART12 Alternate Function mapping */
|
||||
#endif /* UART12 */
|
||||
#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
|
||||
#if defined(USART6)
|
||||
#define GPIO_AF7_USART6 ((uint8_t)0x07) /* USART6 Alternate Function mapping */
|
||||
#endif /* USART6 */
|
||||
#if defined(USART10)
|
||||
#define GPIO_AF7_USART10 ((uint8_t)0x07) /* USART10 Alternate Function mapping */
|
||||
#endif /* USART10 */
|
||||
#if defined(USART11)
|
||||
#define GPIO_AF7_USART11 ((uint8_t)0x07) /* USART11 Alternate Function mapping */
|
||||
#endif /* USART11 */
|
||||
|
||||
/**
|
||||
* @brief AF 8 selection
|
||||
*/
|
||||
#if defined(STM32H503xx)
|
||||
#define GPIO_AF8_I2C2 ((uint8_t)0x08) /* I2C2 Alternate Function mapping */
|
||||
#define GPIO_AF8_I3C1 ((uint8_t)0x08) /* I3C1 Alternate Function mapping */
|
||||
#define GPIO_AF8_USART1 ((uint8_t)0x08) /* USART1 Alternate Function mapping */
|
||||
#endif /* STM32H503xx */
|
||||
#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */
|
||||
#if defined(SAI2)
|
||||
#define GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */
|
||||
#endif /* SAI2 */
|
||||
#if defined(SDMMC1)
|
||||
#define GPIO_AF8_SDMMC1 ((uint8_t)0x08) /* SDMMC1 Alternate Function mapping */
|
||||
#endif /* SDMMC1 */
|
||||
#if defined(SPI6)
|
||||
#define GPIO_AF8_SPI6 ((uint8_t)0x08) /* SPI6 Alternate Function mapping */
|
||||
#endif /* SPI6 */
|
||||
#if defined(UART4)
|
||||
#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
|
||||
#endif /* UART4 */
|
||||
#if defined(UART5)
|
||||
#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
|
||||
#endif /* UART5 */
|
||||
#if defined(UART8)
|
||||
#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */
|
||||
#endif /* UART8 */
|
||||
|
||||
/**
|
||||
* @brief AF 9 selection
|
||||
*/
|
||||
#define GPIO_AF9_FDCAN1 ((uint8_t)0x09) /* FDCAN1 Alternate Function mapping */
|
||||
#if defined(FDCAN2)
|
||||
#define GPIO_AF9_FDCAN2 ((uint8_t)0x09) /* FDCAN2 Alternate Function mapping */
|
||||
#endif /* FDCAN2 */
|
||||
#if defined(FMC_BANK1)
|
||||
#define GPIO_AF9_FMC ((uint8_t)0x09) /* FMC Alternate Function mapping */
|
||||
#endif /* FMC_BANK1 */
|
||||
#if defined(OCTOSPI1)
|
||||
#define GPIO_AF9_OCTOSPI1 ((uint8_t)0x09) /* OCTOSPI1 Alternate Function mapping */
|
||||
#endif /* OCTOSPI1 */
|
||||
#if defined(SDMMC2)
|
||||
#define GPIO_AF9_SDMMC2 ((uint8_t)0x09) /* SDMMC2 Alternate Function mapping */
|
||||
#endif /* SDMMC2 */
|
||||
#if defined(TIM13)
|
||||
#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
|
||||
#endif /* TIM13 */
|
||||
#if defined(TIM14)
|
||||
#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
|
||||
#endif /* TIM14 */
|
||||
#if defined(STM32H503xx)
|
||||
#define GPIO_AF9_USART2 ((uint8_t)0x09) /* USART2 Alternate Function mapping */
|
||||
#define GPIO_AF9_USART3 ((uint8_t)0x09) /* USART3 Alternate Function mapping */
|
||||
#endif /* STM32H503xx */
|
||||
|
||||
/**
|
||||
* @brief AF 10 selection
|
||||
*/
|
||||
#define GPIO_AF10_CRS ((uint8_t)0x0A) /* CRS Alternate Function mapping */
|
||||
#if defined(STM32H503xx)
|
||||
#define GPIO_AF10_I3C1 ((uint8_t)0x0A) /* I3C1 Alternate Function mapping */
|
||||
#define GPIO_AF10_I3C2 ((uint8_t)0x0A) /* I3C2 Alternate Function mapping */
|
||||
#define GPIO_AF10_SPI3 ((uint8_t)0x0A) /* SPI3 Alternate Function mapping */
|
||||
#endif /* STM32H503xx */
|
||||
#if defined(FMC_BANK1)
|
||||
#define GPIO_AF10_FMC ((uint8_t)0x0A) /* FMC Alternate Function mapping */
|
||||
#endif /* FMC_BANK1 */
|
||||
#if defined(OCTOSPI1)
|
||||
#define GPIO_AF10_OCTOSPI1 ((uint8_t)0x0A) /* OCTOSPI1 Alternate Function mapping */
|
||||
#endif /* OCTOSPI1 */
|
||||
#if defined(SAI2)
|
||||
#define GPIO_AF10_SAI2 ((uint8_t)0x0A) /* SAI2 Alternate Function mapping */
|
||||
#endif /* SAI2 */
|
||||
#if defined(SDMMC2)
|
||||
#define GPIO_AF10_SDMMC2 ((uint8_t)0x0A) /* SDMMC2 Alternate Function mapping */
|
||||
#endif /* SDMMC2 */
|
||||
#if defined(TIM8)
|
||||
#define GPIO_AF10_TIM8 ((uint8_t)0x0A) /* TIM8 Alternate Function mapping */
|
||||
#endif /* TIM8 */
|
||||
#define GPIO_AF10_USB ((uint8_t)0x0A) /* USB Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 11 selection
|
||||
*/
|
||||
#if defined(ETH)
|
||||
#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETH Alternate Function mapping */
|
||||
#endif /* ETH */
|
||||
#if defined(FMC_BANK1)
|
||||
#define GPIO_AF11_FMC ((uint8_t)0x0B) /* FMC Alternate Function mapping */
|
||||
#endif /* FMC_BANK1 */
|
||||
#if defined(OCTOSPI1)
|
||||
#define GPIO_AF11_OCTOSPI1 ((uint8_t)0x0B) /* OCTOSPI1 Alternate Function mapping */
|
||||
#endif /* OCTOSPI1 */
|
||||
#if defined(SDMMC2)
|
||||
#define GPIO_AF11_SDMMC2 ((uint8_t)0x0B) /* SDMMC2 Alternate Function mapping */
|
||||
#endif /* SDMMC2 */
|
||||
#if defined(UART7)
|
||||
#define GPIO_AF11_UART7 ((uint8_t)0x0B) /* UART7 Alternate Function mapping */
|
||||
#endif /* UART7 */
|
||||
#if defined(UART9)
|
||||
#define GPIO_AF11_UART9 ((uint8_t)0x0B) /* UART9 Alternate Function mapping */
|
||||
#endif /* UART9 */
|
||||
#if defined(UCPD1)
|
||||
#define GPIO_AF11_UCPD1 ((uint8_t)0x0B) /* UCPD1 Alternate Function mapping */
|
||||
#endif /* UCPD1 */
|
||||
#if defined(STM32H503xx)
|
||||
#define GPIO_AF11_I2C1 ((uint8_t)0x0B) /* I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF11_I2C2 ((uint8_t)0x0B) /* I2C2 Alternate Function mapping */
|
||||
#define GPIO_AF11_SPI2 ((uint8_t)0x0B) /* SPI2 Alternate Function mapping */
|
||||
#define GPIO_AF11_USART2 ((uint8_t)0x0B) /* USART2 Alternate Function mapping */
|
||||
#endif /* STM32H503xx */
|
||||
|
||||
/**
|
||||
* @brief AF 12 selection
|
||||
*/
|
||||
#if defined(FMC_BANK1)
|
||||
#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */
|
||||
#endif /* FMC_BANK1 */
|
||||
#if defined(SDMMC1)
|
||||
#define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */
|
||||
#endif /* SDMMC1 */
|
||||
#if defined(STM32H503xx)
|
||||
#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */
|
||||
#define GPIO_AF12_SPI1 ((uint8_t)0x0C) /* SPI1 Alternate Function mapping */
|
||||
#endif /* STM32H503xx */
|
||||
|
||||
/**
|
||||
* @brief AF 13 selection
|
||||
*/
|
||||
#if defined(DCMI)
|
||||
#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
|
||||
#define GPIO_AF13_PSSI ((uint8_t)0x0D) /* PSSI Alternate Function mapping */
|
||||
#endif /* DCMI */
|
||||
#if defined(FMC_BANK1)
|
||||
#define GPIO_AF13_FMC ((uint8_t)0x0D) /* FMC Alternate Function mapping */
|
||||
#endif /* FMC_BANK1 */
|
||||
#if defined(LPTIM5)
|
||||
#define GPIO_AF13_LPTIM5 ((uint8_t)0x0D) /* LPTIM5 Alternate Function mapping */
|
||||
#endif /* LPTIM5 */
|
||||
#if defined(STM32H503xx)
|
||||
#define GPIO_AF13_USART2 ((uint8_t)0x0D) /* USART2 Alternate Function mapping */
|
||||
#define GPIO_AF13_USART3 ((uint8_t)0x0D) /* USART3 Alternate Function mapping */
|
||||
#endif /* STM32H503xx */
|
||||
|
||||
/**
|
||||
* @brief AF 14 selection
|
||||
*/
|
||||
#if defined(STM32H503xx)
|
||||
#define GPIO_AF14_LPTIM1 ((uint8_t)0x0E) /* LPTIM1 Alternate Function mapping */
|
||||
#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /* LPTIM2 Alternate Function mapping */
|
||||
#define GPIO_AF14_TIM1 ((uint8_t)0x0E) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF14_TIM3 ((uint8_t)0x0E) /* TIM3 Alternate Function mapping */
|
||||
#endif /* STM32H503xx */
|
||||
#if defined(LPTIM3)
|
||||
#define GPIO_AF14_LPTIM3 ((uint8_t)0x0E) /* LPTIM3 Alternate Function mapping */
|
||||
#endif /* LPTIM3 */
|
||||
#if defined(LPTIM4)
|
||||
#define GPIO_AF14_LPTIM4 ((uint8_t)0x0E) /* LPTIM4 Alternate Function mapping */
|
||||
#endif /* LPTIM4 */
|
||||
#if defined(LPTIM5)
|
||||
#define GPIO_AF14_LPTIM5 ((uint8_t)0x0E) /* LPTIM5 Alternate Function mapping */
|
||||
#endif /* LPTIM5 */
|
||||
#if defined(LPTIM6)
|
||||
#define GPIO_AF14_LPTIM6 ((uint8_t)0x0E) /* LPTIM6 Alternate Function mapping */
|
||||
#endif /* LPTIM6 */
|
||||
#if (defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx))
|
||||
#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */
|
||||
#endif /* defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) */
|
||||
#if defined(UART5)
|
||||
#define GPIO_AF14_UART5 ((uint8_t)0x0E) /* UART5 Alternate Function mapping */
|
||||
#endif /* UART5 */
|
||||
|
||||
/**
|
||||
* @brief AF 15 selection
|
||||
*/
|
||||
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F)
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIOEx_Get_Port_Index GPIOEx_Get Port Index
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/* GPIO_Peripheral_Memory_Mapping Peripheral Memory Mapping */
|
||||
|
||||
#if (defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) || defined(STM32H503xx))
|
||||
#define GPIO_GET_INDEX(__GPIOx__) (((uint32_t )(__GPIOx__) & (~GPIOA_BASE)) >> 10)
|
||||
#endif /* (defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) || defined(STM32H503xx)) */
|
||||
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H5xx_HAL_GPIO_EX_H */
|
||||
|
|
@ -0,0 +1,696 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h5xx_hal_gtzc.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of GTZC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H5xx_HAL_GTZC_H
|
||||
#define STM32H5xx_HAL_GTZC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h5xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H5xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GTZC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup GTZC_Exported_Types GTZC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!< Values needed for MPCBB_Attribute_ConfigTypeDef structure sizing */
|
||||
#define GTZC_MPCBB_NB_VCTR_REG_MAX (32U)
|
||||
#define GTZC_MPCBB_NB_LCK_VCTR_REG_MAX (1U)
|
||||
typedef struct
|
||||
{
|
||||
uint32_t MPCBB_SecConfig_array[GTZC_MPCBB_NB_VCTR_REG_MAX]; /*!< Each element specifies secure access mode for
|
||||
a super-block. Each bit corresponds to a block
|
||||
inside the super-block. 0 means non-secure,
|
||||
1 means secure */
|
||||
uint32_t MPCBB_PrivConfig_array[GTZC_MPCBB_NB_VCTR_REG_MAX]; /*!< Each element specifies privilege access mode for
|
||||
a super-block. Each bit corresponds to a block
|
||||
inside the super-block. 0 means non-privilege,
|
||||
1 means privilege */
|
||||
uint32_t MPCBB_LockConfig_array[GTZC_MPCBB_NB_LCK_VCTR_REG_MAX]; /*!< Each bit specifies the lock configuration of
|
||||
a super-block (32 blocks). 0 means unlocked,
|
||||
1 means locked */
|
||||
} MPCBB_Attribute_ConfigTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SecureRWIllegalMode; /*!< Secure read/write illegal access
|
||||
field. It can be a value of @ref GTZC_MPCBB_SecureRWIllegalMode */
|
||||
uint32_t InvertSecureState; /*!< Default security state field (can be inverted or not).
|
||||
It can be a value of @ref GTZC_MPCBB_InvertSecureState */
|
||||
MPCBB_Attribute_ConfigTypeDef AttributeConfig; /*!< MPCBB attribute configuration sub-structure */
|
||||
} MPCBB_ConfigTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t AreaId; /*!< Area identifier field. It can be a value of @ref
|
||||
GTZC_MPCWM_AreaId */
|
||||
uint32_t Offset; /*!< Offset of the watermark area, starting from the selected
|
||||
memory base address. It must aligned on 128KB for FMC
|
||||
and OCTOSPI memories, and on 32-byte for BKPSRAM */
|
||||
uint32_t Length; /*!< Length of the watermark area, starting from the selected
|
||||
Offset. It must aligned on 128KB for FMC and OCTOSPI
|
||||
memories, and on 32-byte for BKPSRAM */
|
||||
uint32_t Attribute; /*!< Attributes of the watermark area. It can be a value
|
||||
of @ref GTZC_MPCWM_Attribute */
|
||||
uint32_t Lock; /*!< Lock of the watermark area. It can be a value
|
||||
of @ref GTZC_MPCWM_Lock */
|
||||
uint32_t AreaStatus; /*!< Status of the watermark area. It can be set to
|
||||
ENABLE or DISABLE */
|
||||
} MPCWM_ConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup GTZC_Private_Constants GTZC Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GTZC_Private_PeriphId_composition GTZC Peripheral identifier composition
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* composition definition for Peripheral identifier parameter (PeriphId) used in
|
||||
* HAL_GTZC_TZSC_ConfigPeriphAttributes() and HAL_GTZC_TZSC_GetConfigPeriphAttributes()
|
||||
* functions and also in all HAL_GTZC_TZIC relative functions.
|
||||
* Bitmap Definition
|
||||
* bits[31:28] Field "register". Define the register index a peripheral belongs to.
|
||||
* Each bit is dedicated to a single register.
|
||||
* bit[5] Field "all peripherals". If this bit is set then the PeriphId targets
|
||||
* all peripherals within all registers.
|
||||
* bits[4:0] Field "bit position". Define the bit position within the
|
||||
* register dedicated to the peripheral, value from 0 to 31.
|
||||
*/
|
||||
#define GTZC_PERIPH_REG_SHIFT (28U)
|
||||
#define GTZC_PERIPH_REG (0xF0000000U)
|
||||
#define GTZC1_PERIPH_REG1 (0x00000000U)
|
||||
#define GTZC1_PERIPH_REG2 (0x10000000U)
|
||||
#define GTZC1_PERIPH_REG3 (0x20000000U)
|
||||
#if defined (GTZC_TZIC1)
|
||||
#define GTZC1_PERIPH_REG4 (0x30000000U)
|
||||
#endif /* defined (GTZC_TZIC1) */
|
||||
#define GTZC_PERIPH_BIT_POSITION (0x0000001FU)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GTZC_Private_Attributes_Msk GTZC Attributes Masks
|
||||
* @{
|
||||
*/
|
||||
#define GTZC_ATTR_SEC_MASK 0x100U
|
||||
#define GTZC_ATTR_PRIV_MASK 0x200U
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup GTZC_Exported_Constants GTZC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GTZC_MPCBB_SecureRWIllegalMode GTZC MPCBB SRWILADIS values
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define GTZC_MPCBB_SRWILADIS_ENABLE (0U)
|
||||
#define GTZC_MPCBB_SRWILADIS_DISABLE (GTZC_MPCBB_CR_SRWILADIS_Msk)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GTZC_MPCBB_InvertSecureState GTZC MPCBB INVSECSTATE values
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define GTZC_MPCBB_INVSECSTATE_NOT_INVERTED (0U)
|
||||
#define GTZC_MPCBB_INVSECSTATE_INVERTED (GTZC_MPCBB_CR_INVSECSTATE_Msk)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GTZC_MPCWM_AreaId GTZC MPCWM area identifier values
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define GTZC_TZSC_MPCWM_ID1 (0U)
|
||||
#define GTZC_TZSC_MPCWM_ID2 (1U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GTZC_TZSC_TZIC_PeriphId GTZC TZSC and TZIC Peripheral identifier values
|
||||
* @{
|
||||
*/
|
||||
#define GTZC_PERIPH_TIM2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM2_Pos)
|
||||
#define GTZC_PERIPH_TIM3 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM3_Pos)
|
||||
#if defined (TIM4)
|
||||
#define GTZC_PERIPH_TIM4 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM4_Pos)
|
||||
#endif /* defined (TIM4) */
|
||||
#if defined (TIM5)
|
||||
#define GTZC_PERIPH_TIM5 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM5_Pos)
|
||||
#endif /* defined (TIM5) */
|
||||
#define GTZC_PERIPH_TIM6 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM6_Pos)
|
||||
#define GTZC_PERIPH_TIM7 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM7_Pos)
|
||||
#if defined (TIM12)
|
||||
#define GTZC_PERIPH_TIM12 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM12_Pos)
|
||||
#endif /* defined (TIM12) */
|
||||
#if defined (TIM13)
|
||||
#define GTZC_PERIPH_TIM13 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM13_Pos)
|
||||
#endif /* defined (TIM13) */
|
||||
#if defined (TIM14)
|
||||
#define GTZC_PERIPH_TIM14 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM14_Pos)
|
||||
#endif /* defined (TIM14) */
|
||||
#define GTZC_PERIPH_WWDG (GTZC1_PERIPH_REG1 | GTZC_CFGR1_WWDG_Pos)
|
||||
#define GTZC_PERIPH_IWDG (GTZC1_PERIPH_REG1 | GTZC_CFGR1_IWDG_Pos)
|
||||
#define GTZC_PERIPH_SPI2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_SPI2_Pos)
|
||||
#define GTZC_PERIPH_SPI3 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_SPI3_Pos)
|
||||
#define GTZC_PERIPH_USART2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_USART2_Pos)
|
||||
#define GTZC_PERIPH_USART3 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_USART3_Pos)
|
||||
#if defined (UART4)
|
||||
#define GTZC_PERIPH_UART4 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_UART4_Pos)
|
||||
#endif /* defined (UART4) */
|
||||
#if defined (UART5)
|
||||
#define GTZC_PERIPH_UART5 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_UART5_Pos)
|
||||
#endif /* defined (UART5) */
|
||||
#define GTZC_PERIPH_I2C1 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_I2C1_Pos)
|
||||
#define GTZC_PERIPH_I2C2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_I2C2_Pos)
|
||||
#define GTZC_PERIPH_I3C1 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_I3C1_Pos)
|
||||
#define GTZC_PERIPH_CRS (GTZC1_PERIPH_REG1 | GTZC_CFGR1_CRS_Pos)
|
||||
#if defined (USART6)
|
||||
#define GTZC_PERIPH_USART6 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_USART6_Pos)
|
||||
#endif /* defined (USART6) */
|
||||
#if defined (USART10)
|
||||
#define GTZC_PERIPH_USART10 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_USART10_Pos)
|
||||
#endif /* defined (USART10) */
|
||||
#if defined (USART11)
|
||||
#define GTZC_PERIPH_USART11 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_USART11_Pos)
|
||||
#endif /* defined (USART11) */
|
||||
#if defined (CEC)
|
||||
#define GTZC_PERIPH_HDMICEC (GTZC1_PERIPH_REG1 | GTZC_CFGR1_HDMICEC_Pos)
|
||||
#endif /* defined (CEC) */
|
||||
#define GTZC_PERIPH_DAC1 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_DAC1_Pos)
|
||||
#if defined (UART7)
|
||||
#define GTZC_PERIPH_UART7 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_UART7_Pos)
|
||||
#endif /* defined (UART7) */
|
||||
#if defined (UART8)
|
||||
#define GTZC_PERIPH_UART8 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_UART8_Pos)
|
||||
#endif /* defined (UART8) */
|
||||
#if defined (UART9)
|
||||
#define GTZC_PERIPH_UART9 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_UART9_Pos)
|
||||
#endif /* defined (UART9) */
|
||||
#if defined (UART12)
|
||||
#define GTZC_PERIPH_UART12 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_UART12_Pos)
|
||||
#endif /* defined (UART12) */
|
||||
#define GTZC_PERIPH_DTS (GTZC1_PERIPH_REG1 | GTZC_CFGR1_DTS_Pos)
|
||||
#define GTZC_PERIPH_LPTIM2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_LPTIM2_Pos)
|
||||
|
||||
#define GTZC_PERIPH_FDCAN1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_FDCAN1_Pos)
|
||||
#if defined (FDCAN2)
|
||||
#define GTZC_PERIPH_FDCAN2 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_FDCAN2_Pos)
|
||||
#endif /* defined (FDCAN2) */
|
||||
#if defined (UCPD1)
|
||||
#define GTZC_PERIPH_UCPD1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_UCPD1_Pos)
|
||||
#endif /* defined (UCPD1) */
|
||||
#if defined (OPAMP1)
|
||||
#define GTZC_PERIPH_OPAMP (GTZC1_PERIPH_REG2 | GTZC_CFGR2_OPAMP_Pos)
|
||||
#endif /* defined (OPAMP1) */
|
||||
#if defined (COMP1)
|
||||
#define GTZC_PERIPH_COMP (GTZC1_PERIPH_REG2 | GTZC_CFGR2_COMP_Pos)
|
||||
#endif /* defined (COMP1) */
|
||||
#define GTZC_PERIPH_TIM1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM1_Pos)
|
||||
#define GTZC_PERIPH_SPI1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_SPI1_Pos)
|
||||
#if defined (TIM8)
|
||||
#define GTZC_PERIPH_TIM8 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM8_Pos)
|
||||
#endif /* defined (TIM8) */
|
||||
#define GTZC_PERIPH_USART1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_USART1_Pos)
|
||||
#if defined (TIM15)
|
||||
#define GTZC_PERIPH_TIM15 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM15_Pos)
|
||||
#endif /* defined (TIM15) */
|
||||
#if defined (TIM16)
|
||||
#define GTZC_PERIPH_TIM16 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM16_Pos)
|
||||
#endif /* defined (TIM16) */
|
||||
#if defined (TIM17)
|
||||
#define GTZC_PERIPH_TIM17 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM17_Pos)
|
||||
#endif /* defined (TIM17) */
|
||||
#if defined (SPI4)
|
||||
#define GTZC_PERIPH_SPI4 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_SPI4_Pos)
|
||||
#endif /* defined (SPI4) */
|
||||
#if defined (SPI6)
|
||||
#define GTZC_PERIPH_SPI6 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_SPI6_Pos)
|
||||
#endif /* defined (SPI6) */
|
||||
#if defined (SAI1)
|
||||
#define GTZC_PERIPH_SAI1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_SAI1_Pos)
|
||||
#endif /* defined (SAI1) */
|
||||
#if defined (SAI2)
|
||||
#define GTZC_PERIPH_SAI2 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_SAI2_Pos)
|
||||
#endif /* defined (SAI2) */
|
||||
#define GTZC_PERIPH_USB (GTZC1_PERIPH_REG2 | GTZC_CFGR2_USB_Pos)
|
||||
#if defined (SPI5)
|
||||
#define GTZC_PERIPH_SPI5 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_SPI5_Pos)
|
||||
#endif /* defined (SPI5) */
|
||||
#define GTZC_PERIPH_LPUART1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_LPUART1_Pos)
|
||||
#if defined (I2C3)
|
||||
#define GTZC_PERIPH_I2C3 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_I2C3_Pos)
|
||||
#endif /* defined (I2C3) */
|
||||
#if defined (I2C4)
|
||||
#define GTZC_PERIPH_I2C4 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_I2C4_Pos)
|
||||
#endif /* defined (I2C4) */
|
||||
#define GTZC_PERIPH_LPTIM1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_LPTIM1_Pos)
|
||||
#if defined (LPTIM3)
|
||||
#define GTZC_PERIPH_LPTIM3 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_LPTIM3_Pos)
|
||||
#endif /* defined (LPTIM3) */
|
||||
#if defined (LPTIM4)
|
||||
#define GTZC_PERIPH_LPTIM4 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_LPTIM4_Pos)
|
||||
#endif /* defined (LPTIM4) */
|
||||
#if defined (LPTIM5)
|
||||
#define GTZC_PERIPH_LPTIM5 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_LPTIM5_Pos)
|
||||
#endif /* defined (LPTIM5) */
|
||||
|
||||
#if defined (LPTIM6)
|
||||
#define GTZC_PERIPH_LPTIM6 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_LPTIM6_Pos)
|
||||
#endif /* defined (LPTIM6) */
|
||||
#if defined (VREFBUF)
|
||||
#define GTZC_PERIPH_VREFBUF (GTZC1_PERIPH_REG3 | GTZC_CFGR3_VREFBUF_Pos)
|
||||
#endif /* defined (VREFBUF) */
|
||||
#if defined (I3C2)
|
||||
#define GTZC_PERIPH_I3C2 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_I3C2_Pos)
|
||||
#endif /* defined (I3C2) */
|
||||
#define GTZC_PERIPH_CRC (GTZC1_PERIPH_REG3 | GTZC_CFGR3_CRC_Pos)
|
||||
#if defined (CORDIC)
|
||||
#define GTZC_PERIPH_CORDIC (GTZC1_PERIPH_REG3 | GTZC_CFGR3_CORDIC_Pos)
|
||||
#endif /* defined (CORDIC) */
|
||||
#if defined (FMAC)
|
||||
#define GTZC_PERIPH_FMAC (GTZC1_PERIPH_REG3 | GTZC_CFGR3_FMAC_Pos)
|
||||
#endif /* defined (FMAC) */
|
||||
#if defined (ETH)
|
||||
#define GTZC_PERIPH_ETHERNET (GTZC1_PERIPH_REG3 | GTZC_CFGR3_ETHERNET_Pos)
|
||||
#endif /* defined (ETH) */
|
||||
#define GTZC_PERIPH_ICACHE_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_ICACHE_REG_Pos)
|
||||
#if defined (DCACHE1)
|
||||
#define GTZC_PERIPH_DCACHE1_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_DCACHE1_REG_Pos)
|
||||
#endif /* defined (DCACHE1) */
|
||||
#define GTZC_PERIPH_ADC (GTZC1_PERIPH_REG3 | GTZC_CFGR3_ADC_Pos)
|
||||
#if defined (DCMI)
|
||||
#define GTZC_PERIPH_DCMI_PSSI (GTZC1_PERIPH_REG3 | GTZC_CFGR3_DCMI_PSSI_Pos)
|
||||
#endif /* defined (DCMI) */
|
||||
#if defined (AES)
|
||||
#define GTZC_PERIPH_AES (GTZC1_PERIPH_REG3 | GTZC_CFGR3_AES_Pos)
|
||||
#endif /* defined (AES) */
|
||||
#if defined (HASH)
|
||||
#define GTZC_PERIPH_HASH (GTZC1_PERIPH_REG3 | GTZC_CFGR3_HASH_Pos)
|
||||
#endif /* defined (HASH) */
|
||||
#define GTZC_PERIPH_RNG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_RNG_Pos)
|
||||
#if defined (PKA)
|
||||
#define GTZC_PERIPH_PKA (GTZC1_PERIPH_REG3 | GTZC_CFGR3_PKA_Pos)
|
||||
#endif /* defined (PKA) */
|
||||
#if defined (SAES)
|
||||
#define GTZC_PERIPH_SAES (GTZC1_PERIPH_REG3 | GTZC_CFGR3_SAES_Pos)
|
||||
#endif /* defined (SAES) */
|
||||
#if defined (SDMMC1)
|
||||
#define GTZC_PERIPH_SDMMC1 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_SDMMC1_Pos)
|
||||
#endif /* defined (SDMMC1) */
|
||||
#if defined (SDMMC2)
|
||||
#define GTZC_PERIPH_SDMMC2 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_SDMMC2_Pos)
|
||||
#endif /* defined (SDMMC2) */
|
||||
#if defined (FMC_Bank1_R)
|
||||
#define GTZC_PERIPH_FMC_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_FMC_REG_Pos)
|
||||
#endif /* defined (FMC_Bank1_R) */
|
||||
#if defined (OCTOSPI1)
|
||||
#define GTZC_PERIPH_OCTOSPI1 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_OCTOSPI1_Pos)
|
||||
#endif /* defined (OCTOSPI1) */
|
||||
#define GTZC_PERIPH_RAMCFG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_RAMCFG_Pos)
|
||||
|
||||
#if defined (GTZC_TZIC1)
|
||||
#define GTZC_PERIPH_GPDMA1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_GPDMA1_Pos)
|
||||
#define GTZC_PERIPH_GPDMA2 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_GPDMA2_Pos)
|
||||
#define GTZC_PERIPH_FLASH (GTZC1_PERIPH_REG4 | GTZC_CFGR4_FLASH_Pos)
|
||||
#define GTZC_PERIPH_FLASH_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_FLASH_REG_Pos)
|
||||
#define GTZC_PERIPH_OTFDEC2 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_OTFDEC2_Pos)
|
||||
#define GTZC_PERIPH_OTFDEC1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_OTFDEC1_Pos)
|
||||
#define GTZC_PERIPH_SBS (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SBS_Pos)
|
||||
#define GTZC_PERIPH_RTC (GTZC1_PERIPH_REG4 | GTZC_CFGR4_RTC_Pos)
|
||||
#define GTZC_PERIPH_TAMP (GTZC1_PERIPH_REG4 | GTZC_CFGR4_TAMP_Pos)
|
||||
#define GTZC_PERIPH_PWR (GTZC1_PERIPH_REG4 | GTZC_CFGR4_PWR_Pos)
|
||||
#define GTZC_PERIPH_RCC (GTZC1_PERIPH_REG4 | GTZC_CFGR4_RCC_Pos)
|
||||
#define GTZC_PERIPH_EXTI (GTZC1_PERIPH_REG4 | GTZC_CFGR4_EXTI_Pos)
|
||||
#define GTZC_PERIPH_TZSC (GTZC1_PERIPH_REG4 | GTZC_CFGR4_TZSC_Pos)
|
||||
#define GTZC_PERIPH_TZIC (GTZC1_PERIPH_REG4 | GTZC_CFGR4_TZIC_Pos)
|
||||
#define GTZC_PERIPH_OCTOSPI1_MEM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_OCTOSPI1_MEM_Pos)
|
||||
#define GTZC_PERIPH_FMC_MEM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_FMC_MEM_Pos)
|
||||
#define GTZC_PERIPH_BKPSRAM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_BKPSRAM_Pos)
|
||||
#define GTZC_PERIPH_SRAM1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM1_Pos)
|
||||
#define GTZC_PERIPH_MPCBB1_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB1_REG_Pos)
|
||||
#define GTZC_PERIPH_SRAM2 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM2_Pos)
|
||||
#define GTZC_PERIPH_MPCBB2_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB2_REG_Pos)
|
||||
#define GTZC_PERIPH_SRAM3 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM3_Pos)
|
||||
#define GTZC_PERIPH_MPCBB3_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB3_REG_Pos)
|
||||
#endif /* defined (GTZC_TZIC1) */
|
||||
|
||||
#define GTZC_PERIPH_ALL (0x00000020U)
|
||||
|
||||
/* Note that two maximum values are also defined here:
|
||||
* - max number of securable AHB/APB peripherals or masters
|
||||
* (used in TZSC sub-block)
|
||||
* - max number of securable and TrustZone-aware AHB/APB peripherals or masters
|
||||
* (used in TZIC sub-block)
|
||||
*/
|
||||
#define GTZC_TZSC_PERIPH_NUMBER (HAL_GTZC_GET_ARRAY_INDEX(GTZC_PERIPH_RAMCFG + 1U))
|
||||
#if defined (GTZC_TZIC1)
|
||||
#define GTZC_TZIC_PERIPH_NUMBER (HAL_GTZC_GET_ARRAY_INDEX(GTZC_PERIPH_MPCBB3_REG + 1U))
|
||||
#endif /* defined (GTZC_TZIC1) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GTZC_TZSC_PeriphAttributes GTZC TZSC peripheral attribute values
|
||||
* @note secure and non-secure attributes are only available from secure state when the system
|
||||
* implement the security (TZEN=1)
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* user-oriented definitions for attribute parameter (PeriphAttributes) used in
|
||||
* HAL_GTZC_TZSC_ConfigPeriphAttributes() and HAL_GTZC_TZSC_GetConfigPeriphAttributes()
|
||||
* functions
|
||||
*/
|
||||
#if defined (GTZC_TZIC1)
|
||||
#define GTZC_TZSC_PERIPH_SEC (GTZC_ATTR_SEC_MASK | 0x00000001U) /*!< Secure attribute */
|
||||
#define GTZC_TZSC_PERIPH_NSEC (GTZC_ATTR_SEC_MASK | 0x00000000U) /*!< Non-secure attribute */
|
||||
#endif /* (GTZC_TZIC1) */
|
||||
#define GTZC_TZSC_PERIPH_PRIV (GTZC_ATTR_PRIV_MASK | 0x00000002U) /*!< Privilege attribute */
|
||||
#define GTZC_TZSC_PERIPH_NPRIV (GTZC_ATTR_PRIV_MASK | 0x00000000U) /*!< Non-privilege attribute */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined (GTZC_TZSC_CR_LCK_Msk)
|
||||
/** @defgroup GTZC_TZSC_Lock GTZC TZSC lock values
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* user-oriented definitions for HAL_GTZC_TZSC_GetLock() returned value */
|
||||
#define GTZC_TZSC_LOCK_OFF (0U)
|
||||
#define GTZC_TZSC_LOCK_ON GTZC_TZSC_CR_LCK_Msk
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* (GTZC_TZSC_CR_LCK_Msk) */
|
||||
|
||||
/** @defgroup GTZC_MPCWM_Group GTZC MPCWM values
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* user-oriented definitions for TZSC_MPCWM */
|
||||
#define GTZC_TZSC_MPCWM_GRANULARITY_1 0x00020000U /* OCTOSPI & FMC granularity: 128 kbytes */
|
||||
#define GTZC_TZSC_MPCWM_GRANULARITY_2 0x00000020U /* BKPSRAM granularity: 32 bytes */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GTZC_MPCWM_Lock GTZC MPCWM Lock values
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* user-oriented definitions for TZSC_MPCWM */
|
||||
#define GTZC_TZSC_MPCWM_LOCK_OFF (0U)
|
||||
#define GTZC_TZSC_MPCWM_LOCK_ON GTZC_TZSC_MPCWM_CFGR_SRLOCK_Msk
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GTZC_MPCWM_Attribute GTZC MPCWM Attribute values
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* user-oriented definitions for TZSC_MPCWM */
|
||||
#define GTZC_TZSC_MPCWM_REGION_NSEC (0U)
|
||||
#define GTZC_TZSC_MPCWM_REGION_SEC (1U)
|
||||
#define GTZC_TZSC_MPCWM_REGION_NPRIV (0U)
|
||||
#define GTZC_TZSC_MPCWM_REGION_PRIV (2U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GTZC_MPCBB_Group GTZC MPCBB values
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* user-oriented definitions for MPCBB */
|
||||
#define GTZC_MPCBB_BLOCK_SIZE 0x200U /* 512 Bytes */
|
||||
#define GTZC_MPCBB_SUPERBLOCK_SIZE (GTZC_MPCBB_BLOCK_SIZE * 32U) /* 16 KBytes */
|
||||
#define GTZC_MPCBB_SUPERBLOCK_UNLOCKED (0U)
|
||||
#define GTZC_MPCBB_SUPERBLOCK_LOCKED (1U)
|
||||
|
||||
#define GTZC_MPCBB_BLOCK_NSEC (GTZC_ATTR_SEC_MASK | 0U)
|
||||
#define GTZC_MPCBB_BLOCK_SEC (GTZC_ATTR_SEC_MASK | 1U)
|
||||
#define GTZC_MPCBB_BLOCK_NPRIV (GTZC_ATTR_PRIV_MASK | 0U)
|
||||
#define GTZC_MPCBB_BLOCK_PRIV (GTZC_ATTR_PRIV_MASK | 2U)
|
||||
|
||||
/* user-oriented definitions for HAL_GTZC_MPCBB_GetLock() returned value */
|
||||
#define GTZC_MPCBB_LOCK_OFF (0U)
|
||||
#define GTZC_MPCBB_LOCK_ON (1U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GTZC_TZIC_Flag GTZC TZIC flag values
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* user-oriented definitions for HAL_GTZC_TZIC_GetFlag() flag parameter */
|
||||
#define GTZC_TZIC_NO_ILA_EVENT (0U)
|
||||
#define GTZC_TZIC_ILA_EVENT_PENDING (1U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup GTZC_Private_Macros GTZC Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* retrieve information to access register for a specific PeriphId */
|
||||
#define GTZC_GET_REG_INDEX(periph_id)\
|
||||
(((periph_id) & GTZC_PERIPH_REG) >> GTZC_PERIPH_REG_SHIFT)
|
||||
|
||||
#define GTZC_GET_PERIPH_POS(periph_id) ((periph_id) & GTZC_PERIPH_BIT_POSITION)
|
||||
|
||||
#if defined (GTZC_TZIC1)
|
||||
#define IS_GTZC_BASE_ADDRESS(mem, address)\
|
||||
( ( (uint32_t)(address) == (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) || \
|
||||
( (uint32_t)(address) == (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) )
|
||||
#else
|
||||
#define IS_GTZC_BASE_ADDRESS(mem, address)\
|
||||
( (uint32_t)(address) == (uint32_t)GTZC_BASE_ADDRESS_NS(mem) )
|
||||
#endif /* defined (GTZC_TZIC1) */
|
||||
|
||||
#define GTZC_MEM_SIZE(mem)\
|
||||
( mem ## _SIZE )
|
||||
|
||||
#if defined (GTZC_TZIC1)
|
||||
#define GTZC_BASE_ADDRESS_S(mem)\
|
||||
( mem ## _BASE_S )
|
||||
#endif /* defined (GTZC_TZIC1) */
|
||||
|
||||
#define GTZC_BASE_ADDRESS_NS(mem)\
|
||||
( mem ## _BASE_NS )
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @defgroup GTZC_Exported_Macros GTZC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* user-oriented macro to get array index of a specific PeriphId
|
||||
* in case of GTZC_PERIPH_ALL usage in the two following functions:
|
||||
* HAL_GTZC_TZSC_ConfigPeriphAttributes() and HAL_GTZC_TZSC_GetConfigPeriphAttributes()
|
||||
*/
|
||||
#define HAL_GTZC_GET_ARRAY_INDEX(periph_id)\
|
||||
( (GTZC_GET_REG_INDEX((periph_id)) * 32U) + GTZC_GET_PERIPH_POS((periph_id)) )
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup GTZC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GTZC_Exported_Functions_Group1
|
||||
* @brief TZSC Initialization and Configuration functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId,
|
||||
uint32_t PeriphAttributes);
|
||||
HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId,
|
||||
uint32_t *PeriphAttributes);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup GTZC_Exported_Functions_Group2
|
||||
* @brief MPCWM Initialization and Configuration functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddress,
|
||||
const MPCWM_ConfigTypeDef *pMPCWM_Desc);
|
||||
HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAddress,
|
||||
MPCWM_ConfigTypeDef *pMPCWM_Desc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
|
||||
/** @addtogroup GTZC_Exported_Functions_Group3
|
||||
* @brief TZSC and TZSC-MPCWM Lock functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef *TZSC_Instance);
|
||||
uint32_t HAL_GTZC_TZSC_GetLock(const GTZC_TZSC_TypeDef *TZSC_Instance);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
|
||||
/** @addtogroup GTZC_Exported_Functions_Group4
|
||||
* @brief MPCBB Initialization and Configuration functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress,
|
||||
const MPCBB_ConfigTypeDef *pMPCBB_desc);
|
||||
HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress,
|
||||
MPCBB_ConfigTypeDef *pMPCBB_desc);
|
||||
HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress,
|
||||
uint32_t NbBlocks,
|
||||
const uint32_t *pMemAttributes);
|
||||
HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress,
|
||||
uint32_t NbBlocks,
|
||||
uint32_t *pMemAttributes);
|
||||
|
||||
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress,
|
||||
uint32_t NbSuperBlocks,
|
||||
const uint32_t *pLockAttributes);
|
||||
HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress,
|
||||
uint32_t NbSuperBlocks,
|
||||
uint32_t *pLockAttributes);
|
||||
HAL_StatusTypeDef HAL_GTZC_MPCBB_Lock(uint32_t MemBaseAddress);
|
||||
HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLock(uint32_t MemBaseAddress,
|
||||
uint32_t *pLockState);
|
||||
#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
|
||||
/** @addtogroup GTZC_Exported_Functions_Group5
|
||||
* @brief TZIC functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_GTZC_TZIC_DisableIT(uint32_t PeriphId);
|
||||
HAL_StatusTypeDef HAL_GTZC_TZIC_EnableIT(uint32_t PeriphId);
|
||||
HAL_StatusTypeDef HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId, uint32_t *pFlag);
|
||||
HAL_StatusTypeDef HAL_GTZC_TZIC_ClearFlag(uint32_t PeriphId);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup GTZC_Exported_Functions_Group6
|
||||
* @brief IRQ related Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void HAL_GTZC_IRQHandler(void);
|
||||
void HAL_GTZC_TZIC_Callback(uint32_t PeriphId);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H5xx_HAL_GTZC_H */
|
||||
|
||||
|
|
@ -0,0 +1,596 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h5xx_hal_hash.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of HASH HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H5xx_HAL_HASH_H
|
||||
#define STM32H5xx_HAL_HASH_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h5xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H5xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
#if defined (HASH)
|
||||
/** @defgroup HASH HASH
|
||||
* @brief HASH HAL module driver.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup HASH_Exported_Types HASH Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HASH Configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DataType; /*!< no swap (32-bit data), half word swap (16-bit data), byte swap (8-bit data) or bit swap
|
||||
(1-bit data). This parameter can be a value of @ref HASH_Data_Type. */
|
||||
|
||||
uint32_t KeySize; /*!< The key size is used only in HMAC operation. */
|
||||
|
||||
uint8_t *pKey; /*!< The key is used only in HMAC operation. */
|
||||
|
||||
uint32_t Algorithm; /*!< HASH algorithm MD5, SHA1 or SHA2.
|
||||
This parameter can be a value of @ref HASH_Algorithm_Selection */
|
||||
|
||||
|
||||
} HASH_ConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL State structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_HASH_STATE_RESET = 0x00U, /*!< Peripheral is not initialized */
|
||||
HAL_HASH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
|
||||
HAL_HASH_STATE_BUSY = 0x02U, /*!< Processing (hashing) is ongoing */
|
||||
HAL_HASH_STATE_SUSPENDED = 0x03U /*!< Suspended state */
|
||||
} HAL_HASH_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL phase structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_HASH_PHASE_READY = 0x01U, /*!< HASH peripheral is ready to start */
|
||||
HAL_HASH_PHASE_PROCESS = 0x02U, /*!< HASH peripheral is in HASH processing phase */
|
||||
HAL_HASH_PHASE_HMAC_STEP_1 = 0x03U, /*!< HASH peripheral is in HMAC step 1 processing phase
|
||||
(step 1 consists in entering the inner hash function key)*/
|
||||
HAL_HASH_PHASE_HMAC_STEP_2 = 0x04U, /*!< HASH peripheral is in HMAC step 2 processing phase
|
||||
(step 2 consists in entering the message text) */
|
||||
HAL_HASH_PHASE_HMAC_STEP_3 = 0x05U /*!< HASH peripheral is in HMAC step 3 processing phase
|
||||
(step 3 consists in entering the outer hash function key)*/
|
||||
|
||||
} HAL_HASH_PhaseTypeDef;
|
||||
|
||||
#if (USE_HAL_HASH_SUSPEND_RESUME == 1U)
|
||||
/**
|
||||
* @brief HAL HASH mode suspend definitions
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_HASH_SUSPEND_NONE = 0x00U, /*!< HASH peripheral suspension not requested */
|
||||
HAL_HASH_SUSPEND = 0x01U /*!< HASH peripheral suspension is requested */
|
||||
} HAL_HASH_SuspendTypeDef;
|
||||
#endif /* USE_HAL_HASH_SUSPEND_RESUME */
|
||||
|
||||
|
||||
/**
|
||||
* @brief HASH Handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __HASH_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
|
||||
{
|
||||
HASH_TypeDef *Instance; /*!< HASH Register base address */
|
||||
|
||||
HASH_ConfigTypeDef Init; /*!< HASH required parameters */
|
||||
|
||||
uint8_t const *pHashInBuffPtr; /*!< Pointer to input buffer */
|
||||
|
||||
uint8_t *pHashOutBuffPtr; /*!< Pointer to output buffer (digest) */
|
||||
|
||||
__IO uint32_t HashInCount; /*!< Counter of inputted data */
|
||||
|
||||
uint32_t Size; /*!< Size of buffer to be processed in bytes */
|
||||
|
||||
uint8_t *pHashKeyBuffPtr; /*!< Pointer to key buffer (HMAC only) */
|
||||
|
||||
HAL_HASH_PhaseTypeDef Phase; /*!< HASH peripheral phase */
|
||||
|
||||
DMA_HandleTypeDef *hdmain; /*!< HASH In DMA Handle parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< HASH Error code */
|
||||
|
||||
__IO HAL_HASH_StateTypeDef State; /*!< HASH peripheral state */
|
||||
|
||||
__IO uint32_t Accumulation; /*!< HASH multi buffers accumulation flag */
|
||||
|
||||
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
|
||||
void (* InCpltCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH input completion callback */
|
||||
|
||||
void (* DgstCpltCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH digest computation complete callback */
|
||||
|
||||
void (* ErrorCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH error callback */
|
||||
|
||||
void (* MspInitCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH Msp Init callback */
|
||||
|
||||
void (* MspDeInitCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH Msp DeInit callback */
|
||||
|
||||
#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
|
||||
#if (USE_HAL_HASH_SUSPEND_RESUME == 1U)
|
||||
__IO HAL_HASH_SuspendTypeDef SuspendRequest; /*!< HASH peripheral suspension request flag */
|
||||
|
||||
HASH_ConfigTypeDef Init_saved; /*!< Saved HASH required parameters */
|
||||
|
||||
uint8_t const *pHashInBuffPtr_saved; /*!< Saved pointer to input buffer */
|
||||
|
||||
uint8_t *pHashOutBuffPtr_saved; /*!< Saved pointer to output buffer (digest) */
|
||||
|
||||
__IO uint32_t HashInCount_saved; /*!< Saved counter of inputted data */
|
||||
|
||||
uint32_t Size_saved; /*!< Saved size of buffer to be processed */
|
||||
|
||||
uint8_t *pHashKeyBuffPtr_saved; /*!< Saved pointer to key buffer (HMAC only) */
|
||||
|
||||
HAL_HASH_PhaseTypeDef Phase_saved; /*!< Saved HASH peripheral phase */
|
||||
#endif /* USE_HAL_HASH_SUSPEND_RESUME */
|
||||
|
||||
} HASH_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U)
|
||||
/**
|
||||
* @brief HAL HASH common Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_HASH_MSPINIT_CB_ID = 0x00U, /*!< HASH MspInit callback ID */
|
||||
HAL_HASH_MSPDEINIT_CB_ID = 0x01U, /*!< HASH MspDeInit callback ID */
|
||||
HAL_HASH_INPUTCPLT_CB_ID = 0x02U, /*!< HASH input completion callback ID */
|
||||
HAL_HASH_DGSTCPLT_CB_ID = 0x03U, /*!< HASH digest computation completion callback ID */
|
||||
HAL_HASH_ERROR_CB_ID = 0x04U, /*!< HASH error callback ID */
|
||||
} HAL_HASH_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL HASH Callback pointer definition
|
||||
*/
|
||||
typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef *hhash); /*!< pointer to a HASH common callback functions */
|
||||
|
||||
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup HASH_Exported_Constants HASH Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HASH_Error_Definition HASH Error Definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_HASH_ERROR_NONE 0x00000000U /*!< No error */
|
||||
#define HAL_HASH_ERROR_BUSY 0x00000001U /*!< Busy flag error */
|
||||
#define HAL_HASH_ERROR_DMA 0x00000002U /*!< DMA-based process error */
|
||||
#define HAL_HASH_ERROR_TIMEOUT 0x00000004U /*!< Timeout error */
|
||||
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U)
|
||||
#define HAL_HASH_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HASH_Algorithm_Selection HASH algorithm selection
|
||||
* @{
|
||||
*/
|
||||
#define HASH_ALGOSELECTION_SHA1 0x00000000U /*!< HASH function is SHA1 */
|
||||
#define HASH_ALGOSELECTION_SHA224 HASH_CR_ALGO_1 /*!< HASH function is SHA224 */
|
||||
#define HASH_ALGOSELECTION_SHA256 (HASH_CR_ALGO_0 | HASH_CR_ALGO_1) /*!< HASH function is SHA256 */
|
||||
#if defined (HASH_CR_ALGO_2)
|
||||
#define HASH_ALGOSELECTION_SHA384 (HASH_CR_ALGO_2 | HASH_CR_ALGO_3) /*!< HASH function is SHA384 */
|
||||
#define HASH_ALGOSELECTION_SHA512_224 (HASH_CR_ALGO_0 | HASH_CR_ALGO_2 | HASH_CR_ALGO_3)
|
||||
/*!< HASH function is SHA512_224 */
|
||||
#define HASH_ALGOSELECTION_SHA512_256 (HASH_CR_ALGO_1 | HASH_CR_ALGO_2 | HASH_CR_ALGO_3)
|
||||
/*!< HASH function is SHA512_256 */
|
||||
#define HASH_ALGOSELECTION_SHA512 HASH_CR_ALGO /*!< HASH function is SHA512 */
|
||||
#endif /* defined (HASH_CR_ALGO_2) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HASH_Mode HASH Mode
|
||||
* @{
|
||||
*/
|
||||
#define HASH_ALGOMODE_HASH 0x00000000U /*!< HASH mode */
|
||||
#define HASH_ALGOMODE_HMAC HASH_CR_MODE /*!< HMAC mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HASH_Data_Type HASH Data Type
|
||||
* @{
|
||||
*/
|
||||
#define HASH_NO_SWAP 0x00000000U /*!< 32-bit data. No swapping */
|
||||
#define HASH_HALFWORD_SWAP HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */
|
||||
#define HASH_BYTE_SWAP HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */
|
||||
#define HASH_BIT_SWAP HASH_CR_DATATYPE /*!< 1-bit data. In the word all bits are swapped */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HASH_HMAC_KEY key length only for HMAC mode
|
||||
* @{
|
||||
*/
|
||||
#define HASH_SHORTKEY 0x00000000U /*!< HMAC Key size is <= block size (64 or 128 bytes) */
|
||||
#define HASH_LONGKEY HASH_CR_LKEY /*!< HMAC Key size is > block size (64 or 128 bytes) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HASH_flags_definition HASH flags definitions
|
||||
* @{
|
||||
*/
|
||||
#define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : new block can be entered
|
||||
in the Peripheral */
|
||||
#define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */
|
||||
#define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */
|
||||
#define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy, processing a block of data */
|
||||
#define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : input buffer contains at least one word of data*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HASH_interrupts_definition HASH interrupts definitions
|
||||
* @{
|
||||
*/
|
||||
#define HASH_IT_DINI HASH_IMR_DINIE /*!< A new block can be entered into the input buffer (DIN) */
|
||||
#define HASH_IT_DCI HASH_IMR_DCIE /*!< Digest calculation complete */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup HASH_Exported_Macros HASH Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Check whether or not the specified HASH flag is set.
|
||||
* @param __HANDLE__ specifies the HASH handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.
|
||||
* @arg @ref HASH_FLAG_DCIS Digest calculation complete.
|
||||
* @arg @ref HASH_FLAG_DMAS DMA interface is enabled (DMAE=1) or a transfer is ongoing.
|
||||
* @arg @ref HASH_FLAG_BUSY The hash core is Busy : processing a block of data.
|
||||
* @arg @ref HASH_FLAG_DINNE DIN not empty : the input buffer contains at least one word of data.
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_HASH_GET_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) > 8U) ? \
|
||||
(((__HANDLE__)->Instance->CR & (__FLAG__)) == (__FLAG__)) :\
|
||||
(((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) )
|
||||
|
||||
/** @brief Clear the specified HASH flag.
|
||||
* @param __HANDLE__ specifies the HASH handle.
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.
|
||||
* @arg @ref HASH_FLAG_DCIS Digest calculation complete
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_HASH_CLEAR_FLAG(__HANDLE__, __FLAG__) CLEAR_BIT((__HANDLE__)->Instance->SR, (__FLAG__))
|
||||
|
||||
/** @brief Check whether the specified HASH interrupt source is enabled or not.
|
||||
* @param __HANDLE__ specifies the HASH handle.
|
||||
* @param __INTERRUPT__ HASH interrupt source to check
|
||||
* This parameter can be one of the following values :
|
||||
* @arg @ref HASH_IT_DINI A new block can be entered into the input buffer (DIN)
|
||||
* @arg @ref HASH_IT_DCI Digest calculation complete
|
||||
* @retval State of interruption (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_HASH_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMR\
|
||||
& (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
/** @brief Enable the specified HASH interrupt.
|
||||
* @param __HANDLE__ specifies the HASH handle.
|
||||
* @param __INTERRUPT__ specifies the HASH interrupt source to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref HASH_IT_DINI A new block can be entered into the input buffer (DIN)
|
||||
* @arg @ref HASH_IT_DCI Digest calculation complete
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_HASH_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->IMR, (__INTERRUPT__))
|
||||
|
||||
/** @brief Disable the specified HASH interrupt.
|
||||
* @param __HANDLE__ specifies the HASH handle.
|
||||
* @param __INTERRUPT__ specifies the HASH interrupt source to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref HASH_IT_DINI A new block can be entered into the input buffer (DIN)
|
||||
* @arg @ref HASH_IT_DCI Digest calculation complete
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_HASH_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->IMR, (__INTERRUPT__))
|
||||
|
||||
/** @brief Reset HASH handle state.
|
||||
* @param __HANDLE__ HASH handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) do{\
|
||||
(__HANDLE__)->State = HAL_HASH_STATE_RESET;\
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
}while(0)
|
||||
#else
|
||||
#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HASH_STATE_RESET)
|
||||
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @brief Enable the multi-buffer DMA transfer mode.
|
||||
* @note This bit is set when hashing large files when multiple DMA transfers are needed.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_HASH_SET_MDMAT() SET_BIT(HASH->CR, HASH_CR_MDMAT)
|
||||
|
||||
/**
|
||||
* @brief Disable the multi-buffer DMA transfer mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_HASH_RESET_MDMAT() CLEAR_BIT(HASH->CR, HASH_CR_MDMAT)
|
||||
|
||||
/**
|
||||
* @brief HAL HASH driver version.
|
||||
* @retval None
|
||||
*/
|
||||
#define HAL_HASH_VERSION 200 /*!< HAL HASH driver version 2.0.0*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup HASH_Exported_Functions HASH Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash);
|
||||
HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash);
|
||||
void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash);
|
||||
void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash);
|
||||
HAL_StatusTypeDef HAL_HASH_GetConfig(HASH_HandleTypeDef *hhash, HASH_ConfigTypeDef *pConf);
|
||||
HAL_StatusTypeDef HAL_HASH_SetConfig(HASH_HandleTypeDef *hhash, HASH_ConfigTypeDef *pConf);
|
||||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID,
|
||||
pHASH_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
|
||||
|
||||
HAL_StatusTypeDef HAL_HASH_ProcessSuspend(HASH_HandleTypeDef *hhash);
|
||||
void HAL_HASH_Resume(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer);
|
||||
void HAL_HASH_Suspend(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HASH_Exported_Functions_Group2 HASH processing functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_HASH_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *const pOutBuffer,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *const pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASH_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *const pOutBuffer);
|
||||
|
||||
HAL_StatusTypeDef HAL_HASH_Accumulate(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_AccumulateLast(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *const pOutBuffer,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_AccumulateLast_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *const pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HASH_Exported_Functions_Group3 HMAC processing functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASH_HMAC_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *const pOutBuffer,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_HMAC_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *const pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASH_HMAC_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *const pOutBuffer);
|
||||
|
||||
HAL_StatusTypeDef HAL_HASH_HMAC_Accumulate(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_HMAC_AccumulateLast(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *const pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_HMAC_Accumulate_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASH_HMAC_AccumulateLast_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer,
|
||||
uint32_t Size, uint8_t *const pOutBuffer);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HASH_Exported_Functions_Group4 HASH IRQ handler management
|
||||
* @{
|
||||
*/
|
||||
void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
|
||||
void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash);
|
||||
void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash);
|
||||
void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);
|
||||
HAL_HASH_StateTypeDef HAL_HASH_GetState(const HASH_HandleTypeDef *hhash);
|
||||
uint32_t HAL_HASH_GetError(const HASH_HandleTypeDef *hhash);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros --------------------------------------------------------*/
|
||||
/** @defgroup HASH_Private_Macros HASH Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Return digest length in bytes.
|
||||
* @retval Digest length
|
||||
*/
|
||||
#if defined(HASH_ALGOSELECTION_SHA512)
|
||||
#define HASH_DIGEST_LENGTH(__HANDLE__) (((READ_BIT((__HANDLE__)->Instance->CR, HASH_CR_ALGO) \
|
||||
== HASH_ALGOSELECTION_SHA1) ? 20U : \
|
||||
((READ_BIT((__HANDLE__)->Instance->CR, HASH_CR_ALGO) \
|
||||
== HASH_ALGOSELECTION_SHA224) ? 28U : \
|
||||
((READ_BIT((__HANDLE__)->Instance->CR, HASH_CR_ALGO) \
|
||||
== HASH_ALGOSELECTION_SHA256) ? 32U : \
|
||||
((READ_BIT((__HANDLE__)->Instance->CR, HASH_CR_ALGO) \
|
||||
== HASH_ALGOSELECTION_SHA384) ? 48U : \
|
||||
((READ_BIT((__HANDLE__)->Instance->CR, HASH_CR_ALGO) \
|
||||
== HASH_ALGOSELECTION_SHA512_224) ? 28U : \
|
||||
((READ_BIT((__HANDLE__)->Instance->CR, HASH_CR_ALGO) \
|
||||
== HASH_ALGOSELECTION_SHA512_256) ? 32U : \
|
||||
((READ_BIT((__HANDLE__)->Instance->CR, HASH_CR_ALGO) \
|
||||
== HASH_ALGOSELECTION_SHA512) ? 64U : 20U ) ) ))))))
|
||||
#else
|
||||
#define HASH_DIGEST_LENGTH(__HANDLE__) (((READ_BIT((__HANDLE__)->Instance->CR, HASH_CR_ALGO) \
|
||||
== HASH_ALGOSELECTION_SHA1) ? 20U : \
|
||||
((READ_BIT((__HANDLE__)->Instance->CR, HASH_CR_ALGO) \
|
||||
== HASH_ALGOSELECTION_SHA224) ? 28U : \
|
||||
((READ_BIT((__HANDLE__)->Instance->CR, HASH_CR_ALGO) \
|
||||
== HASH_ALGOSELECTION_SHA256) ? 32U :20U))))
|
||||
#endif /* HASH_ALGOSELECTION_SHA512 */
|
||||
|
||||
/**
|
||||
* @brief Ensure that HASH input data type is valid.
|
||||
* @param __DATATYPE__ HASH input data type.
|
||||
* @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid)
|
||||
*/
|
||||
#define IS_HASH_DATATYPE(__DATATYPE__) (((__DATATYPE__) == HASH_NO_SWAP)|| \
|
||||
((__DATATYPE__) == HASH_HALFWORD_SWAP)|| \
|
||||
((__DATATYPE__) == HASH_BYTE_SWAP) || \
|
||||
((__DATATYPE__) == HASH_BIT_SWAP))
|
||||
|
||||
/**
|
||||
* @brief Ensure that HASH input algorithm is valid.
|
||||
* @param __ALGORITHM__ HASH algorithm.
|
||||
* @retval SET (__ALGORITHM__ is valid) or RESET (__ALGORITHM__ is invalid)
|
||||
*/
|
||||
#if defined(HASH_ALGOSELECTION_SHA512)
|
||||
#define IS_HASH_ALGORITHM(__ALGORITHM__) (((__ALGORITHM__) == HASH_ALGOSELECTION_SHA1)|| \
|
||||
((__ALGORITHM__) == HASH_ALGOSELECTION_SHA224)|| \
|
||||
((__ALGORITHM__) == HASH_ALGOSELECTION_SHA256)|| \
|
||||
((__ALGORITHM__) == HASH_ALGOSELECTION_SHA384)|| \
|
||||
((__ALGORITHM__) == HASH_ALGOSELECTION_SHA512_224)|| \
|
||||
((__ALGORITHM__) == HASH_ALGOSELECTION_SHA512_256)|| \
|
||||
((__ALGORITHM__) == HASH_ALGOSELECTION_SHA512))
|
||||
#else
|
||||
#define IS_HASH_ALGORITHM(__ALGORITHM__) (((__ALGORITHM__) == HASH_ALGOSELECTION_SHA1)|| \
|
||||
((__ALGORITHM__) == HASH_ALGOSELECTION_SHA224)|| \
|
||||
((__ALGORITHM__) == HASH_ALGOSELECTION_SHA256))
|
||||
#endif /* HASH_ALGOSELECTION_SHA512 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup HASH_Private_Constants HASH Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private defines -----------------------------------------------------------*/
|
||||
/** @defgroup HASH_Private_Defines HASH Private Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup HASH_Private_Variables HASH Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private functions -----------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup HASH_Private_Functions HASH Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* HASH*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* STM32H5xx_HAL_HASH_H */
|
||||
|
|
@ -0,0 +1,598 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h5xx_hal_hcd.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of HCD HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H5xx_HAL_HCD_H
|
||||
#define STM32H5xx_HAL_HCD_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h5xx_ll_usb.h"
|
||||
|
||||
#if defined (USB_DRD_FS)
|
||||
/** @addtogroup STM32H5xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup HCD HCD
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup HCD_Exported_Types HCD Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HCD_Exported_Types_Group1 HCD State Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_HCD_STATE_RESET = 0x00,
|
||||
HAL_HCD_STATE_READY = 0x01,
|
||||
HAL_HCD_STATE_ERROR = 0x02,
|
||||
HAL_HCD_STATE_BUSY = 0x03,
|
||||
HAL_HCD_STATE_TIMEOUT = 0x04
|
||||
} HCD_StateTypeDef;
|
||||
|
||||
typedef USB_DRD_TypeDef HCD_TypeDef;
|
||||
typedef USB_DRD_CfgTypeDef HCD_InitTypeDef;
|
||||
typedef USB_DRD_HCTypeDef HCD_HCTypeDef;
|
||||
typedef USB_DRD_URBStateTypeDef HCD_URBStateTypeDef;
|
||||
typedef USB_DRD_HCStateTypeDef HCD_HCStateTypeDef;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
HCD_HCD_STATE_DISCONNECTED = 0x00U,
|
||||
HCD_HCD_STATE_CONNECTED = 0x01U,
|
||||
HCD_HCD_STATE_RESETED = 0x02U,
|
||||
HCD_HCD_STATE_RUN = 0x03U,
|
||||
HCD_HCD_STATE_SUSPEND = 0x04U,
|
||||
HCD_HCD_STATE_RESUME = 0x05U,
|
||||
} HCD_HostStateTypeDef;
|
||||
|
||||
/* PMA lookup Table size depending on PMA Size
|
||||
* 8Bytes each Block 32Bit in each word
|
||||
*/
|
||||
#define PMA_BLOCKS ((USB_DRD_PMA_SIZE) / (8U * 32U))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HCD_Exported_Types_Group2 HCD Handle Structure definition
|
||||
* @{
|
||||
*/
|
||||
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
|
||||
typedef struct __HCD_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
|
||||
{
|
||||
HCD_TypeDef *Instance; /*!< Register base address */
|
||||
HCD_InitTypeDef Init; /*!< HCD required parameters */
|
||||
HCD_HCTypeDef hc[16]; /*!< Host channels parameters */
|
||||
|
||||
uint32_t ep0_PmaAllocState; /*!< EP0 PMA allocation State (allocated, virtual Ch, EP0 direction) */
|
||||
uint16_t phy_chin_state[8]; /*!< Physical Channel in State (Used/Free) */
|
||||
uint16_t phy_chout_state[8]; /*!< Physical Channel out State (Used/Free)*/
|
||||
uint32_t PMALookupTable[PMA_BLOCKS]; /*PMA LookUp Table */
|
||||
HCD_HostStateTypeDef HostState; /*!< USB current state DICONNECT/CONNECT/RUN/SUSPEND/RESUME */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< HCD peripheral status */
|
||||
__IO HCD_StateTypeDef State; /*!< HCD communication state */
|
||||
__IO uint32_t ErrorCode; /*!< HCD Error code */
|
||||
void *pData; /*!< Pointer Stack Handler */
|
||||
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
|
||||
void (* SOFCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD SOF callback */
|
||||
void (* ConnectCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Connect callback */
|
||||
void (* DisconnectCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Disconnect callback */
|
||||
void (* PortEnabledCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Port Enable callback */
|
||||
void (* PortDisabledCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Port Disable callback */
|
||||
void (* HC_NotifyURBChangeCallback)(struct __HCD_HandleTypeDef *hhcd, uint8_t chnum,
|
||||
HCD_URBStateTypeDef urb_state); /*!< USB OTG HCD Host Channel Notify URB Change callback */
|
||||
|
||||
void (* MspInitCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Msp DeInit callback */
|
||||
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
|
||||
} HCD_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup HCD_Exported_Constants HCD Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HCD_Speed HCD Speed
|
||||
* @{
|
||||
*/
|
||||
#define HCD_SPEED_FULL USBH_FSLS_SPEED
|
||||
#define HCD_SPEED_LOW USBH_FSLS_SPEED
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HCD_Device_Speed HCD Device Speed
|
||||
* @{
|
||||
*/
|
||||
#define HCD_DEVICE_SPEED_HIGH 0U
|
||||
#define HCD_DEVICE_SPEED_FULL 1U
|
||||
#define HCD_DEVICE_SPEED_LOW 2U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HCD_PHY_Module HCD PHY Module
|
||||
* @{
|
||||
*/
|
||||
#define HCD_PHY_ULPI 1U
|
||||
#define HCD_PHY_EMBEDDED 2U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HCD_Error_Code_definition HCD Error Code definition
|
||||
* @brief HCD Error Code definition
|
||||
* @{
|
||||
*/
|
||||
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
|
||||
#define HAL_HCD_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup HCD_Exported_Macros HCD Exported Macros
|
||||
* @brief macros to handle interrupts and specific clock configurations
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_HCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
|
||||
#define __HAL_HCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
|
||||
|
||||
#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance)\
|
||||
& (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__))
|
||||
#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
|
||||
|
||||
#define __HAL_HCD_GET_CHNUM(__HANDLE__) (((__HANDLE__)->Instance->ISTR) & USB_ISTR_IDN)
|
||||
#define __HAL_HCD_GET_CHDIR(__HANDLE__) (((__HANDLE__)->Instance->ISTR) & USB_ISTR_DIR)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup HCD_Exported_Functions HCD Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
|
||||
HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd);
|
||||
HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
|
||||
uint8_t epnum, uint8_t dev_address,
|
||||
uint8_t speed, uint8_t ep_type, uint16_t mps);
|
||||
|
||||
HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
|
||||
|
||||
HAL_StatusTypeDef HAL_HCD_HC_Close(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
|
||||
|
||||
void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
|
||||
|
||||
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
|
||||
/** @defgroup HAL_HCD_Callback_ID_enumeration_definition HAL USB OTG HCD Callback ID enumeration definition
|
||||
* @brief HAL USB OTG HCD Callback ID enumeration definition
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_HCD_SOF_CB_ID = 0x01, /*!< USB HCD SOF callback ID */
|
||||
HAL_HCD_CONNECT_CB_ID = 0x02, /*!< USB HCD Connect callback ID */
|
||||
HAL_HCD_DISCONNECT_CB_ID = 0x03, /*!< USB HCD Disconnect callback ID */
|
||||
HAL_HCD_PORT_ENABLED_CB_ID = 0x04, /*!< USB HCD Port Enable callback ID */
|
||||
HAL_HCD_PORT_DISABLED_CB_ID = 0x05, /*!< USB HCD Port Disable callback ID */
|
||||
|
||||
HAL_HCD_MSPINIT_CB_ID = 0x06, /*!< USB HCD MspInit callback ID */
|
||||
HAL_HCD_MSPDEINIT_CB_ID = 0x07 /*!< USB HCD MspDeInit callback ID */
|
||||
|
||||
} HAL_HCD_CallbackIDTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_HCD_Callback_pointer_definition HAL USB OTG HCD Callback pointer definition
|
||||
* @brief HAL USB OTG HCD Callback pointer definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef void (*pHCD_CallbackTypeDef)(HCD_HandleTypeDef *hhcd); /*!< pointer to a common USB OTG HCD callback function */
|
||||
typedef void (*pHCD_HC_NotifyURBChangeCallbackTypeDef)(HCD_HandleTypeDef *hhcd,
|
||||
uint8_t epnum,
|
||||
HCD_URBStateTypeDef urb_state); /*!< pointer to USB OTG HCD host channel callback */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd,
|
||||
HAL_HCD_CallbackIDTypeDef CallbackID,
|
||||
pHCD_CallbackTypeDef pCallback);
|
||||
|
||||
HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd,
|
||||
HAL_HCD_CallbackIDTypeDef CallbackID);
|
||||
|
||||
HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd,
|
||||
pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback);
|
||||
|
||||
HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd);
|
||||
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* I/O operation functions ***************************************************/
|
||||
/** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
|
||||
uint8_t direction, uint8_t ep_type,
|
||||
uint8_t token, uint8_t *pbuff,
|
||||
uint16_t length, uint8_t do_ping);
|
||||
|
||||
HAL_StatusTypeDef HAL_HCD_HC_SetHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
|
||||
uint8_t addr, uint8_t PortNbr);
|
||||
|
||||
HAL_StatusTypeDef HAL_HCD_HC_ClearHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
|
||||
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd);
|
||||
|
||||
void HAL_HCD_SuspendCallback(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_ResumeCallback(HCD_HandleTypeDef *hhcd);
|
||||
|
||||
void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum,
|
||||
HCD_URBStateTypeDef urb_state);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions **********************************************/
|
||||
/** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
|
||||
HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
|
||||
HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
|
||||
|
||||
HAL_StatusTypeDef HAL_HCD_Suspend(HCD_HandleTypeDef *hhcd);
|
||||
HAL_StatusTypeDef HAL_HCD_Resume(HCD_HandleTypeDef *hhcd);
|
||||
HAL_StatusTypeDef HAL_HCD_ResumePort(HCD_HandleTypeDef *hhcd);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral State functions ************************************************/
|
||||
/** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef const *hhcd);
|
||||
HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef const *hhcd, uint8_t chnum);
|
||||
HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef const *hhcd, uint8_t chnum);
|
||||
uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef const *hhcd, uint8_t chnum);
|
||||
uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
|
||||
uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
|
||||
|
||||
|
||||
/* PMA Allocation functions **********************************************/
|
||||
/** @addtogroup PMA Allocation
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HCD_PMAlloc(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
|
||||
uint16_t ch_kind, uint16_t mps);
|
||||
|
||||
HAL_StatusTypeDef HAL_HCD_PMADeAlloc(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
|
||||
HAL_StatusTypeDef HAL_HCD_PMAReset(HCD_HandleTypeDef *hhcd);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup HCD_Private_Macros HCD Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define HCD_MIN(a, b) (((a) < (b)) ? (a) : (b))
|
||||
#define HCD_MAX(a, b) (((a) > (b)) ? (a) : (b))
|
||||
|
||||
/** @defgroup HCD_LOGICAL_CHANNEL HCD Logical Channel
|
||||
* @{
|
||||
*/
|
||||
#define HCD_LOGICAL_CH_NOT_OPENED 0xFFU
|
||||
#define HCD_FREE_CH_NOT_FOUND 0xFFU
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HCD_ENDP_Kind HCD Endpoint Kind
|
||||
* @{
|
||||
*/
|
||||
#define HCD_SNG_BUF 0U
|
||||
#define HCD_DBL_BUF 1U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Set Channel */
|
||||
#define HCD_SET_CHANNEL USB_DRD_SET_CHEP
|
||||
|
||||
/* Get Channel Register */
|
||||
#define HCD_GET_CHANNEL USB_DRD_GET_CHEP
|
||||
|
||||
|
||||
/**
|
||||
* @brief free buffer used from the application realizing it to the line
|
||||
* toggles bit SW_BUF in the double buffered endpoint register
|
||||
* @param USBx USB device.
|
||||
* @param bChNum, bDir
|
||||
* @retval None
|
||||
*/
|
||||
#define HCD_FREE_USER_BUFFER USB_DRD_FREE_USER_BUFFER
|
||||
|
||||
/**
|
||||
* @brief Set the Setup bit in the corresponding channel, when a Setup
|
||||
transaction is needed.
|
||||
* @param USBx USB device.
|
||||
* @param bChNum
|
||||
* @retval None
|
||||
*/
|
||||
#define HAC_SET_CH_TX_SETUP USB_DRD_CHEP_TX_SETUP
|
||||
|
||||
/**
|
||||
* @brief sets the status for tx transfer (bits STAT_TX[1:0]).
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bChNum Endpoint Number.
|
||||
* @param wState new state
|
||||
* @retval None
|
||||
*/
|
||||
#define HCD_SET_CH_TX_STATUS USB_DRD_SET_CHEP_TX_STATUS
|
||||
|
||||
/**
|
||||
* @brief sets the status for rx transfer (bits STAT_TX[1:0])
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bChNum Endpoint Number.
|
||||
* @param wState new state
|
||||
* @retval None
|
||||
*/
|
||||
#define HCD_SET_CH_RX_STATUS USB_DRD_SET_CHEP_RX_STATUS
|
||||
/**
|
||||
* @brief gets the status for tx/rx transfer (bits STAT_TX[1:0]
|
||||
* /STAT_RX[1:0])
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bChNum Endpoint Number.
|
||||
* @retval status
|
||||
*/
|
||||
#define HCD_GET_CH_TX_STATUS USB_DRD_GET_CHEP_TX_STATUS
|
||||
#define HCD_GET_CH_RX_STATUS USB_DRD_GET_CHEP_RX_STATUS
|
||||
/**
|
||||
* @brief Sets/clears CH_KIND bit in the Channel register.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bChNum Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define HCD_SET_CH_KIND USB_DRD_SET_CH_KIND
|
||||
#define HCD_CLEAR_CH_KIND USB_DRD_CLEAR_CH_KIND
|
||||
#define HCD_SET_BULK_CH_DBUF HCD_SET_CH_KIND
|
||||
#define HCD_CLEAR_BULK_CH_DBUF HCD_CLEAR_CH_KIND
|
||||
|
||||
/**
|
||||
* @brief Clears bit ERR_RX in the Channel register
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bChNum Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define HCD_CLEAR_RX_CH_ERR USB_DRD_CLEAR_CHEP_RX_ERR
|
||||
|
||||
/**
|
||||
* @brief Clears bit ERR_TX in the Channel register
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bChNum Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define HCD_CLEAR_TX_CH_ERR USB_DRD_CLEAR_CHEP_TX_ERR
|
||||
/**
|
||||
* @brief Clears bit CTR_RX / CTR_TX in the endpoint register.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bChNum Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define HCD_CLEAR_RX_CH_CTR USB_DRD_CLEAR_RX_CHEP_CTR
|
||||
#define HCD_CLEAR_TX_CH_CTR USB_DRD_CLEAR_TX_CHEP_CTR
|
||||
|
||||
/**
|
||||
* @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bChNum Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define HCD_RX_DTOG USB_DRD_RX_DTOG
|
||||
#define HCD_TX_DTOG USB_DRD_TX_DTOG
|
||||
/**
|
||||
* @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bChNum Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define HCD_CLEAR_RX_DTOG USB_DRD_CLEAR_RX_DTOG
|
||||
#define HCD_CLEAR_TX_DTOG USB_DRD_CLEAR_TX_DTOG
|
||||
|
||||
/**
|
||||
* @brief sets counter for the tx/rx buffer.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bChNum Endpoint Number.
|
||||
* @param wCount Counter value.
|
||||
* @retval None
|
||||
*/
|
||||
#define HCD_SET_CH_TX_CNT USB_DRD_SET_CHEP_TX_CNT
|
||||
#define HCD_SET_CH_RX_CNT USB_DRD_SET_CHEP_RX_CNT
|
||||
|
||||
/**
|
||||
* @brief gets counter of the tx buffer.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bChNum channel Number.
|
||||
* @retval Counter value
|
||||
*/
|
||||
#define HCD_GET_CH_TX_CNT USB_DRD_GET_CHEP_TX_CNT
|
||||
|
||||
/**
|
||||
* @brief gets counter of the rx buffer.
|
||||
* @param Instance USB peripheral instance register address.
|
||||
* @param bChNum channel Number.
|
||||
* @retval Counter value
|
||||
*/
|
||||
__STATIC_INLINE uint16_t HCD_GET_CH_RX_CNT(HCD_TypeDef *Instance, uint16_t bChNum)
|
||||
{
|
||||
uint32_t HostCoreSpeed;
|
||||
__IO uint32_t count = 10U;
|
||||
|
||||
/* Get Host core Speed */
|
||||
HostCoreSpeed = USB_GetHostSpeed(Instance);
|
||||
|
||||
/* Count depends on device LS */
|
||||
if (HostCoreSpeed == USB_DRD_SPEED_LS)
|
||||
{
|
||||
count = (63U * (HAL_RCC_GetHCLKFreq() / 1000000U)) / 100U;
|
||||
}
|
||||
|
||||
if (count > 15U)
|
||||
{
|
||||
count = HCD_MAX(10U, (count - 15U));
|
||||
}
|
||||
|
||||
/* WA: few cycles for RX PMA descriptor to update */
|
||||
while (count > 0U)
|
||||
{
|
||||
count--;
|
||||
}
|
||||
|
||||
return (uint16_t)USB_DRD_GET_CHEP_RX_CNT((Instance), (bChNum));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets buffer 0/1 address of a double buffer endpoint.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bChNum Endpoint Number.
|
||||
* @param bDir endpoint dir EP_DBUF_OUT = OUT
|
||||
* EP_DBUF_IN = IN
|
||||
* @param wCount: Counter value
|
||||
* @retval None
|
||||
*/
|
||||
#define HCD_SET_CH_DBUF0_CNT USB_DRD_SET_CHEP_DBUF0_CNT
|
||||
#define HCD_SET_CH_DBUF1_CNT USB_DRD_SET_CHEP_DBUF1_CNT
|
||||
#define HCD_SET_CH_DBUF_CNT USB_DRD_SET_CHEP_DBUF_CNT
|
||||
|
||||
|
||||
/**
|
||||
* @brief gets counter of the rx buffer0.
|
||||
* @param Instance USB peripheral instance register address.
|
||||
* @param bChNum channel Number.
|
||||
* @retval Counter value
|
||||
*/
|
||||
__STATIC_INLINE uint16_t HCD_GET_CH_DBUF0_CNT(const HCD_TypeDef *Instance, uint16_t bChNum)
|
||||
{
|
||||
UNUSED(Instance);
|
||||
__IO uint32_t count = 10U;
|
||||
|
||||
/* WA: few cycles for RX PMA descriptor to update */
|
||||
while (count > 0U)
|
||||
{
|
||||
count--;
|
||||
}
|
||||
|
||||
return (uint16_t)USB_DRD_GET_CHEP_DBUF0_CNT((Instance), (bChNum));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief gets counter of the rx buffer1.
|
||||
* @param Instance USB peripheral instance register address.
|
||||
* @param bChNum channel Number.
|
||||
* @retval Counter value
|
||||
*/
|
||||
__STATIC_INLINE uint16_t HCD_GET_CH_DBUF1_CNT(const HCD_TypeDef *Instance, uint16_t bChNum)
|
||||
{
|
||||
UNUSED(Instance);
|
||||
__IO uint32_t count = 10U;
|
||||
|
||||
/* WA: few cycles for RX PMA descriptor to update */
|
||||
while (count > 0U)
|
||||
{
|
||||
count--;
|
||||
}
|
||||
|
||||
return (uint16_t)USB_DRD_GET_CHEP_DBUF1_CNT((Instance), (bChNum));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private functions prototypes ----------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* defined (USB_DRD_FS) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H5xx_HAL_HCD_H */
|
||||
|
|
@ -0,0 +1,844 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h5xx_hal_i2c.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of I2C HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H5xx_HAL_I2C_H
|
||||
#define STM32H5xx_HAL_I2C_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h5xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H5xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup I2C_Exported_Types I2C Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
|
||||
* @brief I2C Configuration Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value.
|
||||
This parameter calculated by referring to I2C initialization section
|
||||
in Reference manual */
|
||||
|
||||
uint32_t OwnAddress1; /*!< Specifies the first device own address.
|
||||
This parameter can be a 7-bit or 10-bit address. */
|
||||
|
||||
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
|
||||
This parameter can be a value of @ref I2C_ADDRESSING_MODE */
|
||||
|
||||
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
|
||||
This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
|
||||
|
||||
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
|
||||
This parameter can be a 7-bit address. */
|
||||
|
||||
uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing
|
||||
mode is selected.
|
||||
This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
|
||||
|
||||
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
|
||||
This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
|
||||
|
||||
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
|
||||
This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
|
||||
|
||||
} I2C_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_state_structure_definition HAL state structure definition
|
||||
* @brief HAL State structure definition
|
||||
* @note HAL I2C State value coding follow below described bitmap :\n
|
||||
* b7-b6 Error information\n
|
||||
* 00 : No Error\n
|
||||
* 01 : Abort (Abort user request on going)\n
|
||||
* 10 : Timeout\n
|
||||
* 11 : Error\n
|
||||
* b5 Peripheral initialization status\n
|
||||
* 0 : Reset (peripheral not initialized)\n
|
||||
* 1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n
|
||||
* b4 (not used)\n
|
||||
* x : Should be set to 0\n
|
||||
* b3\n
|
||||
* 0 : Ready or Busy (No Listen mode ongoing)\n
|
||||
* 1 : Listen (peripheral in Address Listen Mode)\n
|
||||
* b2 Intrinsic process state\n
|
||||
* 0 : Ready\n
|
||||
* 1 : Busy (peripheral busy with some configuration or internal operations)\n
|
||||
* b1 Rx state\n
|
||||
* 0 : Ready (no Rx operation ongoing)\n
|
||||
* 1 : Busy (Rx operation ongoing)\n
|
||||
* b0 Tx state\n
|
||||
* 0 : Ready (no Tx operation ongoing)\n
|
||||
* 1 : Busy (Tx operation ongoing)
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
|
||||
HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
|
||||
HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
|
||||
HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
|
||||
HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
|
||||
HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */
|
||||
HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
|
||||
process is ongoing */
|
||||
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
|
||||
process is ongoing */
|
||||
HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
|
||||
HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
|
||||
HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
|
||||
|
||||
} HAL_I2C_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_mode_structure_definition HAL mode structure definition
|
||||
* @brief HAL Mode structure definition
|
||||
* @note HAL I2C Mode value coding follow below described bitmap :\n
|
||||
* b7 (not used)\n
|
||||
* x : Should be set to 0\n
|
||||
* b6\n
|
||||
* 0 : None\n
|
||||
* 1 : Memory (HAL I2C communication is in Memory Mode)\n
|
||||
* b5\n
|
||||
* 0 : None\n
|
||||
* 1 : Slave (HAL I2C communication is in Slave Mode)\n
|
||||
* b4\n
|
||||
* 0 : None\n
|
||||
* 1 : Master (HAL I2C communication is in Master Mode)\n
|
||||
* b3-b2-b1-b0 (not used)\n
|
||||
* xxxx : Should be set to 0000
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */
|
||||
HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */
|
||||
HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
|
||||
HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */
|
||||
|
||||
} HAL_I2C_ModeTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Error_Code_definition I2C Error Code definition
|
||||
* @brief I2C Error Code definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */
|
||||
#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */
|
||||
#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */
|
||||
#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */
|
||||
#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */
|
||||
#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
|
||||
#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
|
||||
#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */
|
||||
#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U) /*!< DMA Parameter Error */
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
#define HAL_I2C_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
|
||||
* @brief I2C handle Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct __I2C_HandleTypeDef
|
||||
{
|
||||
I2C_TypeDef *Instance; /*!< I2C registers base address */
|
||||
|
||||
I2C_InitTypeDef Init; /*!< I2C communication parameters */
|
||||
|
||||
uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
|
||||
|
||||
uint16_t XferSize; /*!< I2C transfer size */
|
||||
|
||||
__IO uint16_t XferCount; /*!< I2C transfer counter */
|
||||
|
||||
__IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can
|
||||
be a value of @ref I2C_XFEROPTIONS */
|
||||
|
||||
__IO uint32_t PreviousState; /*!< I2C communication Previous state */
|
||||
|
||||
HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
|
||||
/*!< I2C transfer IRQ handler function pointer */
|
||||
|
||||
#if defined(HAL_DMA_MODULE_ENABLED)
|
||||
DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
|
||||
|
||||
#endif /*HAL_DMA_MODULE_ENABLED*/
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< I2C locking object */
|
||||
|
||||
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
|
||||
|
||||
__IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< I2C Error code */
|
||||
|
||||
__IO uint32_t AddrEventCount; /*!< I2C Address Event counter */
|
||||
|
||||
__IO uint32_t Devaddress; /*!< I2C Target device address */
|
||||
|
||||
__IO uint32_t Memaddress; /*!< I2C Target memory address */
|
||||
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Master Tx Transfer completed callback */
|
||||
void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Master Rx Transfer completed callback */
|
||||
void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Slave Tx Transfer completed callback */
|
||||
void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Slave Rx Transfer completed callback */
|
||||
void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Listen Complete callback */
|
||||
void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Memory Tx Transfer completed callback */
|
||||
void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Memory Rx Transfer completed callback */
|
||||
void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Error callback */
|
||||
void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Abort callback */
|
||||
|
||||
void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
|
||||
/*!< I2C Slave Address Match callback */
|
||||
|
||||
void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Msp DeInit callback */
|
||||
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
} I2C_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL I2C Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */
|
||||
HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */
|
||||
HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */
|
||||
HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */
|
||||
HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */
|
||||
HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */
|
||||
HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */
|
||||
HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */
|
||||
HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */
|
||||
|
||||
HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */
|
||||
HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */
|
||||
|
||||
} HAL_I2C_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL I2C Callback pointer definition
|
||||
*/
|
||||
typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c);
|
||||
/*!< pointer to an I2C callback function */
|
||||
typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection,
|
||||
uint16_t AddrMatchCode);
|
||||
/*!< pointer to an I2C Address Match callback function */
|
||||
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup I2C_Exported_Constants I2C Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options
|
||||
* @{
|
||||
*/
|
||||
#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)
|
||||
#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
|
||||
#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
|
||||
#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
|
||||
#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
|
||||
#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE)
|
||||
|
||||
/* List of XferOptions in usage of :
|
||||
* 1- Restart condition in all use cases (direction change or not)
|
||||
*/
|
||||
#define I2C_OTHER_FRAME (0x000000AAU)
|
||||
#define I2C_OTHER_AND_LAST_FRAME (0x0000AA00U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_ADDRESSINGMODE_7BIT (0x00000001U)
|
||||
#define I2C_ADDRESSINGMODE_10BIT (0x00000002U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_DUALADDRESS_DISABLE (0x00000000U)
|
||||
#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
|
||||
* @{
|
||||
*/
|
||||
#define I2C_OA2_NOMASK ((uint8_t)0x00U)
|
||||
#define I2C_OA2_MASK01 ((uint8_t)0x01U)
|
||||
#define I2C_OA2_MASK02 ((uint8_t)0x02U)
|
||||
#define I2C_OA2_MASK03 ((uint8_t)0x03U)
|
||||
#define I2C_OA2_MASK04 ((uint8_t)0x04U)
|
||||
#define I2C_OA2_MASK05 ((uint8_t)0x05U)
|
||||
#define I2C_OA2_MASK06 ((uint8_t)0x06U)
|
||||
#define I2C_OA2_MASK07 ((uint8_t)0x07U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_GENERALCALL_DISABLE (0x00000000U)
|
||||
#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_NOSTRETCH_DISABLE (0x00000000U)
|
||||
#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
|
||||
* @{
|
||||
*/
|
||||
#define I2C_MEMADD_SIZE_8BIT (0x00000001U)
|
||||
#define I2C_MEMADD_SIZE_16BIT (0x00000002U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
|
||||
* @{
|
||||
*/
|
||||
#define I2C_DIRECTION_TRANSMIT (0x00000000U)
|
||||
#define I2C_DIRECTION_RECEIVE (0x00000001U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_RELOAD_MODE I2C_CR2_RELOAD
|
||||
#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
|
||||
#define I2C_SOFTEND_MODE (0x00000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_NO_STARTSTOP (0x00000000U)
|
||||
#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
|
||||
#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
|
||||
#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
|
||||
* @brief I2C Interrupt definition
|
||||
* Elements values convention: 0xXXXXXXXX
|
||||
* - XXXXXXXX : Interrupt control mask
|
||||
* @{
|
||||
*/
|
||||
#define I2C_IT_ERRI I2C_CR1_ERRIE
|
||||
#define I2C_IT_TCI I2C_CR1_TCIE
|
||||
#define I2C_IT_STOPI I2C_CR1_STOPIE
|
||||
#define I2C_IT_NACKI I2C_CR1_NACKIE
|
||||
#define I2C_IT_ADDRI I2C_CR1_ADDRIE
|
||||
#define I2C_IT_RXI I2C_CR1_RXIE
|
||||
#define I2C_IT_TXI I2C_CR1_TXIE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Flag_definition I2C Flag definition
|
||||
* @{
|
||||
*/
|
||||
#define I2C_FLAG_TXE I2C_ISR_TXE
|
||||
#define I2C_FLAG_TXIS I2C_ISR_TXIS
|
||||
#define I2C_FLAG_RXNE I2C_ISR_RXNE
|
||||
#define I2C_FLAG_ADDR I2C_ISR_ADDR
|
||||
#define I2C_FLAG_AF I2C_ISR_NACKF
|
||||
#define I2C_FLAG_STOPF I2C_ISR_STOPF
|
||||
#define I2C_FLAG_TC I2C_ISR_TC
|
||||
#define I2C_FLAG_TCR I2C_ISR_TCR
|
||||
#define I2C_FLAG_BERR I2C_ISR_BERR
|
||||
#define I2C_FLAG_ARLO I2C_ISR_ARLO
|
||||
#define I2C_FLAG_OVR I2C_ISR_OVR
|
||||
#define I2C_FLAG_PECERR I2C_ISR_PECERR
|
||||
#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
|
||||
#define I2C_FLAG_ALERT I2C_ISR_ALERT
|
||||
#define I2C_FLAG_BUSY I2C_ISR_BUSY
|
||||
#define I2C_FLAG_DIR I2C_ISR_DIR
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @defgroup I2C_Exported_Macros I2C Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset I2C handle state.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_I2C_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
|
||||
/** @brief Enable the specified I2C interrupt.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __INTERRUPT__ specifies the interrupt source to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref I2C_IT_ERRI Errors interrupt enable
|
||||
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
|
||||
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
|
||||
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
|
||||
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
|
||||
* @arg @ref I2C_IT_RXI RX interrupt enable
|
||||
* @arg @ref I2C_IT_TXI TX interrupt enable
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
|
||||
|
||||
/** @brief Disable the specified I2C interrupt.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __INTERRUPT__ specifies the interrupt source to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref I2C_IT_ERRI Errors interrupt enable
|
||||
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
|
||||
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
|
||||
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
|
||||
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
|
||||
* @arg @ref I2C_IT_RXI RX interrupt enable
|
||||
* @arg @ref I2C_IT_TXI TX interrupt enable
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
|
||||
|
||||
/** @brief Check whether the specified I2C interrupt source is enabled or not.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __INTERRUPT__ specifies the I2C interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref I2C_IT_ERRI Errors interrupt enable
|
||||
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
|
||||
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
|
||||
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
|
||||
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
|
||||
* @arg @ref I2C_IT_RXI RX interrupt enable
|
||||
* @arg @ref I2C_IT_TXI TX interrupt enable
|
||||
*
|
||||
* @retval The new state of __INTERRUPT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & \
|
||||
(__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified I2C flag is set or not.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref I2C_FLAG_TXE Transmit data register empty
|
||||
* @arg @ref I2C_FLAG_TXIS Transmit interrupt status
|
||||
* @arg @ref I2C_FLAG_RXNE Receive data register not empty
|
||||
* @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
|
||||
* @arg @ref I2C_FLAG_AF Acknowledge failure received flag
|
||||
* @arg @ref I2C_FLAG_STOPF STOP detection flag
|
||||
* @arg @ref I2C_FLAG_TC Transfer complete (master mode)
|
||||
* @arg @ref I2C_FLAG_TCR Transfer complete reload
|
||||
* @arg @ref I2C_FLAG_BERR Bus error
|
||||
* @arg @ref I2C_FLAG_ARLO Arbitration lost
|
||||
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
|
||||
* @arg @ref I2C_FLAG_PECERR PEC error in reception
|
||||
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
|
||||
* @arg @ref I2C_FLAG_ALERT SMBus alert
|
||||
* @arg @ref I2C_FLAG_BUSY Bus busy
|
||||
* @arg @ref I2C_FLAG_DIR Transfer direction (slave mode)
|
||||
*
|
||||
* @retval The new state of __FLAG__ (SET or RESET).
|
||||
*/
|
||||
#define I2C_FLAG_MASK (0x0001FFFFU)
|
||||
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \
|
||||
(__FLAG__)) == (__FLAG__)) ? SET : RESET)
|
||||
|
||||
/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref I2C_FLAG_TXE Transmit data register empty
|
||||
* @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
|
||||
* @arg @ref I2C_FLAG_AF Acknowledge failure received flag
|
||||
* @arg @ref I2C_FLAG_STOPF STOP detection flag
|
||||
* @arg @ref I2C_FLAG_BERR Bus error
|
||||
* @arg @ref I2C_FLAG_ARLO Arbitration lost
|
||||
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
|
||||
* @arg @ref I2C_FLAG_PECERR PEC error in reception
|
||||
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
|
||||
* @arg @ref I2C_FLAG_ALERT SMBus alert
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? \
|
||||
((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
|
||||
((__HANDLE__)->Instance->ICR = (__FLAG__)))
|
||||
|
||||
/** @brief Enable the specified I2C peripheral.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
|
||||
|
||||
/** @brief Disable the specified I2C peripheral.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
|
||||
|
||||
/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include I2C HAL Extended module */
|
||||
#include "stm32h5xx_hal_i2c_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup I2C_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions******************************/
|
||||
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
|
||||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
|
||||
pI2C_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
|
||||
|
||||
HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions ****************************************************/
|
||||
/******* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
|
||||
uint32_t Timeout);
|
||||
|
||||
/******* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
|
||||
|
||||
#if defined(HAL_DMA_MODULE_ENABLED)
|
||||
/******* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions);
|
||||
#endif /*HAL_DMA_MODULE_ENABLED*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
|
||||
* @{
|
||||
*/
|
||||
/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
|
||||
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
|
||||
void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State, Mode and Error functions *********************************/
|
||||
HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c);
|
||||
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c);
|
||||
uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup I2C_Private_Constants I2C Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup I2C_Private_Macro I2C Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
|
||||
((MODE) == I2C_ADDRESSINGMODE_10BIT))
|
||||
|
||||
#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
|
||||
((ADDRESS) == I2C_DUALADDRESS_ENABLE))
|
||||
|
||||
#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \
|
||||
((MASK) == I2C_OA2_MASK01) || \
|
||||
((MASK) == I2C_OA2_MASK02) || \
|
||||
((MASK) == I2C_OA2_MASK03) || \
|
||||
((MASK) == I2C_OA2_MASK04) || \
|
||||
((MASK) == I2C_OA2_MASK05) || \
|
||||
((MASK) == I2C_OA2_MASK06) || \
|
||||
((MASK) == I2C_OA2_MASK07))
|
||||
|
||||
#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
|
||||
((CALL) == I2C_GENERALCALL_ENABLE))
|
||||
|
||||
#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
|
||||
((STRETCH) == I2C_NOSTRETCH_ENABLE))
|
||||
|
||||
#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
|
||||
((SIZE) == I2C_MEMADD_SIZE_16BIT))
|
||||
|
||||
#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \
|
||||
((MODE) == I2C_AUTOEND_MODE) || \
|
||||
((MODE) == I2C_SOFTEND_MODE))
|
||||
|
||||
#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \
|
||||
((REQUEST) == I2C_GENERATE_START_READ) || \
|
||||
((REQUEST) == I2C_GENERATE_START_WRITE) || \
|
||||
((REQUEST) == I2C_NO_STARTSTOP))
|
||||
|
||||
#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
|
||||
((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
|
||||
((REQUEST) == I2C_NEXT_FRAME) || \
|
||||
((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
|
||||
((REQUEST) == I2C_LAST_FRAME) || \
|
||||
((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \
|
||||
IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
|
||||
|
||||
#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \
|
||||
((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
|
||||
|
||||
#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
|
||||
(uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \
|
||||
I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
|
||||
I2C_CR2_RD_WRN)))
|
||||
|
||||
#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) \
|
||||
>> 16U))
|
||||
#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) \
|
||||
>> 16U))
|
||||
#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
|
||||
#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
|
||||
#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
|
||||
|
||||
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
|
||||
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
|
||||
|
||||
#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \
|
||||
(uint16_t)(0xFF00U))) >> 8U)))
|
||||
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
|
||||
|
||||
#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? \
|
||||
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
|
||||
(I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
|
||||
(~I2C_CR2_RD_WRN)) : \
|
||||
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
|
||||
(I2C_CR2_ADD10) | (I2C_CR2_START) | \
|
||||
(I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)))
|
||||
|
||||
#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \
|
||||
((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
|
||||
#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private Functions ---------------------------------------------------------*/
|
||||
/** @defgroup I2C_Private_Functions I2C Private Functions
|
||||
* @{
|
||||
*/
|
||||
/* Private functions are defined in stm32h5xx_hal_i2c.c file */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* STM32H5xx_HAL_I2C_H */
|
||||
|
|
@ -0,0 +1,156 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h5xx_hal_i2c_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of I2C HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H5xx_HAL_I2C_EX_H
|
||||
#define STM32H5xx_HAL_I2C_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h5xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H5xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2CEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
|
||||
* @{
|
||||
*/
|
||||
#define I2C_ANALOGFILTER_ENABLE 0x00000000U
|
||||
#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
|
||||
* @{
|
||||
*/
|
||||
#define I2C_FASTMODEPLUS_ENABLE 0x00000000U /*!< Enable Fast Mode Plus */
|
||||
#define I2C_FASTMODEPLUS_DISABLE 0x00000001U /*!< Disable Fast Mode Plus */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ************************************************/
|
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
|
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigFastModePlus(I2C_HandleTypeDef *hi2c, uint32_t FastModePlus);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
|
||||
((FILTER) == I2C_ANALOGFILTER_DISABLE))
|
||||
|
||||
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
|
||||
|
||||
#define IS_I2C_FASTMODEPLUS(__CONFIG__) (((__CONFIG__) == (I2C_FASTMODEPLUS_ENABLE)) || \
|
||||
((__CONFIG__) == (I2C_FASTMODEPLUS_DISABLE)))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private Functions ---------------------------------------------------------*/
|
||||
/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
|
||||
* @{
|
||||
*/
|
||||
/* Private functions are defined in stm32h5xx_hal_i2c_ex.c file */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H5xx_HAL_I2C_EX_H */
|
||||
|
|
@ -0,0 +1,663 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h5xx_hal_i2s.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of I2S HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H5xx_HAL_I2S_H
|
||||
#define STM32H5xx_HAL_I2S_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h5xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H5xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2S
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup I2S_Exported_Types I2S Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief I2S Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Mode; /*!< Specifies the I2S operating mode.
|
||||
This parameter can be a value of @ref I2S_Mode */
|
||||
|
||||
uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
|
||||
This parameter can be a value of @ref I2S_Standard */
|
||||
|
||||
uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
|
||||
This parameter can be a value of @ref I2S_Data_Format */
|
||||
|
||||
uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
|
||||
This parameter can be a value of @ref I2S_MCLK_Output */
|
||||
|
||||
uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
|
||||
This parameter can be a value of @ref I2S_Audio_Frequency */
|
||||
|
||||
uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
|
||||
This parameter can be a value of @ref I2S_Clock_Polarity */
|
||||
|
||||
uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
|
||||
This parameter can be a value of @ref I2S_MSB_LSB_Transmission */
|
||||
|
||||
uint32_t WSInversion; /*!< Control the Word Select Inversion.
|
||||
This parameter can be a value of @ref I2S_WSInversion */
|
||||
|
||||
uint32_t Data24BitAlignment; /*!< Specifies the Data Padding for 24 bits data length
|
||||
This parameter can be a value of @ref I2S_Data_24Bit_Alignment */
|
||||
|
||||
uint32_t MasterKeepIOState; /*!< Control of Alternate function GPIOs state
|
||||
This parameter can be a value of @ref I2S_Master_Keep_IO_State */
|
||||
|
||||
} I2S_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2S_STATE_RESET = 0x00UL, /*!< I2S not yet initialized or disabled */
|
||||
HAL_I2S_STATE_READY = 0x01UL, /*!< I2S initialized and ready for use */
|
||||
HAL_I2S_STATE_BUSY = 0x02UL, /*!< I2S internal process is ongoing */
|
||||
HAL_I2S_STATE_BUSY_TX = 0x03UL, /*!< Data Transmission process is ongoing */
|
||||
HAL_I2S_STATE_BUSY_RX = 0x04UL, /*!< Data Reception process is ongoing */
|
||||
HAL_I2S_STATE_BUSY_TX_RX = 0x05UL, /*!< Data Transmission and Reception process is ongoing */
|
||||
HAL_I2S_STATE_TIMEOUT = 0x06UL, /*!< I2S timeout state */
|
||||
HAL_I2S_STATE_ERROR = 0x07UL /*!< I2S error state */
|
||||
} HAL_I2S_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief I2S handle Structure definition
|
||||
*/
|
||||
typedef struct __I2S_HandleTypeDef
|
||||
{
|
||||
SPI_TypeDef *Instance; /*!< I2S registers base address */
|
||||
|
||||
I2S_InitTypeDef Init; /*!< I2S communication parameters */
|
||||
|
||||
const uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */
|
||||
|
||||
__IO uint16_t TxXferSize; /*!< I2S Tx transfer size */
|
||||
|
||||
__IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */
|
||||
|
||||
uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */
|
||||
|
||||
__IO uint16_t RxXferSize; /*!< I2S Rx transfer size */
|
||||
|
||||
__IO uint16_t RxXferCount; /*!< I2S Rx transfer counter
|
||||
(This field is initialized at the
|
||||
same value as transfer size at the
|
||||
beginning of the transfer and
|
||||
decremented when a sample is received
|
||||
NbSamplesReceived = RxBufferSize-RxBufferCount) */
|
||||
|
||||
void (*RxISR)(struct __I2S_HandleTypeDef *hi2s); /*!< function pointer on Rx ISR */
|
||||
|
||||
void (*TxISR)(struct __I2S_HandleTypeDef *hi2s); /*!< function pointer on Tx ISR */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */
|
||||
|
||||
__IO HAL_LockTypeDef Lock; /*!< I2S locking object */
|
||||
|
||||
__IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< I2S Error code
|
||||
This parameter can be a value of @ref I2S_Error */
|
||||
|
||||
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
|
||||
void (* TxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Completed callback */
|
||||
void (* RxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Completed callback */
|
||||
void (* TxRxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S TxRx Completed callback */
|
||||
void (* TxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Half Completed callback */
|
||||
void (* RxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Half Completed callback */
|
||||
void (* TxRxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S TxRx Half Completed callback */
|
||||
void (* ErrorCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Error callback */
|
||||
void (* MspInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp DeInit callback */
|
||||
|
||||
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
|
||||
} I2S_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
|
||||
/**
|
||||
|
||||
* @brief HAL I2S Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2S_TX_COMPLETE_CB_ID = 0x00UL, /*!< I2S Tx Completed callback ID */
|
||||
HAL_I2S_RX_COMPLETE_CB_ID = 0x01UL, /*!< I2S Rx Completed callback ID */
|
||||
HAL_I2S_TX_RX_COMPLETE_CB_ID = 0x02UL, /*!< I2S TxRx Completed callback ID */
|
||||
HAL_I2S_TX_HALF_COMPLETE_CB_ID = 0x03UL, /*!< I2S Tx Half Completed callback ID */
|
||||
HAL_I2S_RX_HALF_COMPLETE_CB_ID = 0x04UL, /*!< I2S Rx Half Completed callback ID */
|
||||
HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID = 0x05UL, /*!< I2S TxRx Half Completed callback ID */
|
||||
HAL_I2S_ERROR_CB_ID = 0x06UL, /*!< I2S Error callback ID */
|
||||
HAL_I2S_MSPINIT_CB_ID = 0x07UL, /*!< I2S Msp Init callback ID */
|
||||
HAL_I2S_MSPDEINIT_CB_ID = 0x08UL /*!< I2S Msp DeInit callback ID */
|
||||
|
||||
} HAL_I2S_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL I2S Callback pointer definition
|
||||
*/
|
||||
typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to an I2S callback function */
|
||||
|
||||
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup I2S_Exported_Constants I2S Exported Constants
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup I2S_Error I2S Error
|
||||
* @{
|
||||
*/
|
||||
#define HAL_I2S_ERROR_NONE (0x00000000UL) /*!< No error */
|
||||
#define HAL_I2S_ERROR_TIMEOUT (0x00000001UL) /*!< Timeout error */
|
||||
#define HAL_I2S_ERROR_OVR (0x00000002UL) /*!< OVR error */
|
||||
#define HAL_I2S_ERROR_UDR (0x00000004UL) /*!< UDR error */
|
||||
#define HAL_I2S_ERROR_DMA (0x00000008UL) /*!< DMA transfer error */
|
||||
#define HAL_I2S_ERROR_PRESCALER (0x00000010UL) /*!< Prescaler Calculation error */
|
||||
#define HAL_I2S_ERROR_FRE (0x00000020UL) /*!< FRE error */
|
||||
#define HAL_I2S_ERROR_NO_OGT (0x00000040UL) /*!< No On Going Transfer error */
|
||||
#define HAL_I2S_ERROR_NOT_SUPPORTED (0x00000080UL) /*!< Requested operation not supported */
|
||||
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
|
||||
#define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000100UL) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Mode I2S Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2S_MODE_SLAVE_TX (0x00000000UL)
|
||||
#define I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)
|
||||
#define I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)
|
||||
#define I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1)
|
||||
#define I2S_MODE_SLAVE_FULLDUPLEX (SPI_I2SCFGR_I2SCFG_2)
|
||||
#define I2S_MODE_MASTER_FULLDUPLEX (SPI_I2SCFGR_I2SCFG_2 | SPI_I2SCFGR_I2SCFG_0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Standard I2S Standard
|
||||
* @{
|
||||
*/
|
||||
#define I2S_STANDARD_PHILIPS (0x00000000UL)
|
||||
#define I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)
|
||||
#define I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)
|
||||
#define I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)
|
||||
#define I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Data_Format I2S Data Format
|
||||
* @{
|
||||
*/
|
||||
#define I2S_DATAFORMAT_16B (0x00000000UL)
|
||||
#define I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)
|
||||
#define I2S_DATAFORMAT_24B (SPI_I2SCFGR_DATLEN_0)
|
||||
#define I2S_DATAFORMAT_32B (SPI_I2SCFGR_DATLEN_1)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_MCLK_Output I2S MCLK Output
|
||||
* @{
|
||||
*/
|
||||
#define I2S_MCLKOUTPUT_ENABLE (SPI_I2SCFGR_MCKOE)
|
||||
#define I2S_MCLKOUTPUT_DISABLE (0x00000000UL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Audio_Frequency I2S Audio Frequency
|
||||
* @{
|
||||
*/
|
||||
#define I2S_AUDIOFREQ_192K (192000UL)
|
||||
#define I2S_AUDIOFREQ_96K (96000UL)
|
||||
#define I2S_AUDIOFREQ_48K (48000UL)
|
||||
#define I2S_AUDIOFREQ_44K (44100UL)
|
||||
#define I2S_AUDIOFREQ_32K (32000UL)
|
||||
#define I2S_AUDIOFREQ_22K (22050UL)
|
||||
#define I2S_AUDIOFREQ_16K (16000UL)
|
||||
#define I2S_AUDIOFREQ_11K (11025UL)
|
||||
#define I2S_AUDIOFREQ_8K (8000UL)
|
||||
#define I2S_AUDIOFREQ_DEFAULT (2UL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Clock_Polarity I2S FullDuplex Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2S_CPOL_LOW (0x00000000UL)
|
||||
#define I2S_CPOL_HIGH (SPI_I2SCFGR_CKPOL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_MSB_LSB_Transmission I2S MSB LSB Transmission
|
||||
* @{
|
||||
*/
|
||||
#define I2S_FIRSTBIT_MSB (0x00000000UL)
|
||||
#define I2S_FIRSTBIT_LSB SPI_CFG2_LSBFRST
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_WSInversion I2S Word Select Inversion
|
||||
* @{
|
||||
*/
|
||||
#define I2S_WS_INVERSION_DISABLE (0x00000000UL)
|
||||
#define I2S_WS_INVERSION_ENABLE SPI_I2SCFGR_WSINV
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Data_24Bit_Alignment Data Padding 24Bit
|
||||
* @{
|
||||
*/
|
||||
#define I2S_DATA_24BIT_ALIGNMENT_RIGHT (0x00000000UL)
|
||||
#define I2S_DATA_24BIT_ALIGNMENT_LEFT SPI_I2SCFGR_DATFMT
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Master_Keep_IO_State Keep IO State
|
||||
* @{
|
||||
*/
|
||||
#define I2S_MASTER_KEEP_IO_STATE_DISABLE (0x00000000U)
|
||||
#define I2S_MASTER_KEEP_IO_STATE_ENABLE SPI_CFG2_AFCNTR
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition
|
||||
* @{
|
||||
*/
|
||||
#define I2S_IT_RXP SPI_IER_RXPIE
|
||||
#define I2S_IT_TXP SPI_IER_TXPIE
|
||||
#define I2S_IT_DXP SPI_IER_DXPIE
|
||||
#define I2S_IT_UDR SPI_IER_UDRIE
|
||||
#define I2S_IT_OVR SPI_IER_OVRIE
|
||||
#define I2S_IT_FRE SPI_IER_TIFREIE
|
||||
#define I2S_IT_ERR (SPI_IER_UDRIE | SPI_IER_OVRIE | SPI_IER_TIFREIE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Flags_Definition I2S Flags Definition
|
||||
* @{
|
||||
*/
|
||||
#define I2S_FLAG_RXP SPI_SR_RXP /* I2S status flag : Rx-Packet available flag */
|
||||
#define I2S_FLAG_TXP SPI_SR_TXP /* I2S status flag : Tx-Packet space available flag */
|
||||
#define I2S_FLAG_DXP SPI_SR_DXP /* I2S status flag : Dx-Packet space available flag */
|
||||
#define I2S_FLAG_UDR SPI_SR_UDR /* I2S Error flag : Underrun flag */
|
||||
#define I2S_FLAG_OVR SPI_SR_OVR /* I2S Error flag : Overrun flag */
|
||||
#define I2S_FLAG_FRE SPI_SR_TIFRE /* I2S Error flag : TI mode frame format error flag */
|
||||
|
||||
#define I2S_FLAG_MASK (SPI_SR_RXP | SPI_SR_TXP | SPI_SR_DXP |SPI_SR_UDR | SPI_SR_OVR | SPI_SR_TIFRE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup I2S_Exported_macros I2S Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset I2S handle state
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
|
||||
#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_I2S_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
|
||||
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
|
||||
|
||||
/** @brief Enable the specified SPI peripheral (in I2S mode).
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE))
|
||||
|
||||
/** @brief Disable the specified SPI peripheral (in I2S mode).
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE))
|
||||
|
||||
/** @brief Enable the specified I2S interrupts.
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* This parameter can be I2S where x: 1, 2 or 3 to select the I2S peripheral.
|
||||
* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_IT_RXP : Rx-Packet available interrupt
|
||||
* @arg I2S_IT_TXP : Tx-Packet space available interrupt
|
||||
* @arg I2S_IT_UDR : Underrun interrupt
|
||||
* @arg I2S_IT_OVR : Overrun interrupt
|
||||
* @arg I2S_IT_FRE : TI mode frame format error interrupt
|
||||
* @arg I2S_IT_ERR : Error interrupt enable
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
|
||||
|
||||
/** @brief Disable the specified I2S interrupts.
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* This parameter can be I2S where x: 1, 2 or 3 to select the I2S peripheral.
|
||||
* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_IT_RXP : Rx-Packet available interrupt
|
||||
* @arg I2S_IT_TXP : Tx-Packet space available interrupt
|
||||
* @arg I2S_IT_UDR : Underrun interrupt
|
||||
* @arg I2S_IT_OVR : Overrun interrupt
|
||||
* @arg I2S_IT_FRE : TI mode frame format error interrupt
|
||||
* @arg I2S_IT_ERR : Error interrupt enable
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
|
||||
|
||||
/** @brief Check if the specified I2S interrupt source is enabled or disabled.
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* This parameter can be I2S where x: 1, 2 or 3 to select the I2S peripheral.
|
||||
* @param __INTERRUPT__ specifies the I2S interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_IT_RXP : Rx-Packet available interrupt
|
||||
* @arg I2S_IT_TXP : Tx-Packet space available interrupt
|
||||
* @arg I2S_IT_DXP : Tx-Packet space available interrupt
|
||||
* @arg I2S_IT_UDR : Underrun interrupt
|
||||
* @arg I2S_IT_OVR : Overrun interrupt
|
||||
* @arg I2S_IT_FRE : TI mode frame format error interrupt
|
||||
* @arg I2S_IT_ERR : Error interrupt enable
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\
|
||||
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified I2S flag is set or not.
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* This parameter can be I2S where x: 1, 2 or 3 to select the I2S peripheral.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_FLAG_RXP : Rx-Packet available flag
|
||||
* @arg I2S_FLAG_TXP : Tx-Packet space available flag
|
||||
* @arg I2S_FLAG_UDR : Underrun flag
|
||||
* @arg I2S_FLAG_OVR : Overrun flag
|
||||
* @arg I2S_FLAG_FRE : TI mode frame format error flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clear the I2S OVR pending flag.
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC)
|
||||
|
||||
/** @brief Clear the I2S UDR pending flag.
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC)
|
||||
|
||||
/** @brief Clear the I2S FRE pending flag.
|
||||
* @param __HANDLE__: specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_CLEAR_TIFREFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup I2S_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2S_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
|
||||
HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
|
||||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
|
||||
HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
|
||||
pI2S_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2S_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* I/O operation functions ***************************************************/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, const uint16_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, const uint16_t *pTxData, uint16_t *pRxData,
|
||||
uint16_t Size, uint32_t Timeout);
|
||||
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, const uint16_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, const uint16_t *pTxData, uint16_t *pRxData,
|
||||
uint16_t Size);
|
||||
|
||||
void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
|
||||
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, const uint16_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, const uint16_t *pTxData, uint16_t *pRxData,
|
||||
uint16_t Size);
|
||||
|
||||
HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
|
||||
HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
|
||||
HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
|
||||
|
||||
/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
|
||||
void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2SEx_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2S_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control and State functions ************************************/
|
||||
HAL_I2S_StateTypeDef HAL_I2S_GetState(const I2S_HandleTypeDef *hi2s);
|
||||
uint32_t HAL_I2S_GetError(const I2S_HandleTypeDef *hi2s);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup I2S_Private_Constants I2S Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private Functions ---------------------------------------------------------*/
|
||||
/** @defgroup I2S_Private_Functions I2S Private Functions
|
||||
* @{
|
||||
*/
|
||||
/* Private functions are defined in stm32h7xx_hal_i2S.c file */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup I2S_Private_Macros I2S Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Check whether the specified SPI flag is set or not.
|
||||
* @param __SR__ copy of I2S SR register.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_FLAG_RXP : Rx-Packet available flag
|
||||
* @arg I2S_FLAG_TXP : Tx-Packet space available flag
|
||||
* @arg I2S_FLAG_UDR : Underrun flag
|
||||
* @arg I2S_FLAG_OVR : Overrun flag
|
||||
* @arg I2S_FLAG_FRE : TI mode frame format error flag
|
||||
* @retval SET or RESET.
|
||||
*/
|
||||
#define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__)\
|
||||
& ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK))\
|
||||
? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified SPI Interrupt is set or not.
|
||||
* @param __IER__ copy of I2S IER register.
|
||||
* @param __INTERRUPT__ specifies the SPI interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_IT_RXP : Rx-Packet available interrupt
|
||||
* @arg I2S_IT_TXP : Tx-Packet space available interrupt
|
||||
* @arg I2S_IT_UDR : Underrun interrupt
|
||||
* @arg I2S_IT_OVR : Overrun interrupt
|
||||
* @arg I2S_IT_FRE : TI mode frame format error interrupt
|
||||
* @arg I2S_IT_ERR : Error interrupt enable
|
||||
* @retval SET or RESET.
|
||||
*/
|
||||
#define I2S_CHECK_IT_SOURCE(__IER__, __INTERRUPT__) ((((__IER__)\
|
||||
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Checks if I2S Mode parameter is in allowed range.
|
||||
* @param __MODE__ specifies the I2S Mode.
|
||||
* This parameter can be a value of @ref I2S_Mode
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_I2S_MODE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \
|
||||
((__MODE__) == I2S_MODE_SLAVE_RX) || \
|
||||
((__MODE__) == I2S_MODE_MASTER_TX) || \
|
||||
((__MODE__) == I2S_MODE_MASTER_RX) || \
|
||||
((__MODE__) == I2S_MODE_SLAVE_FULLDUPLEX) || \
|
||||
((__MODE__) == I2S_MODE_MASTER_FULLDUPLEX))
|
||||
|
||||
#define IS_I2S_MASTER(__MODE__) (((__MODE__) == I2S_MODE_MASTER_TX) || \
|
||||
((__MODE__) == I2S_MODE_MASTER_RX) || \
|
||||
((__MODE__) == I2S_MODE_MASTER_FULLDUPLEX))
|
||||
|
||||
#define IS_I2S_SLAVE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \
|
||||
((__MODE__) == I2S_MODE_SLAVE_RX) || \
|
||||
((__MODE__) == I2S_MODE_SLAVE_FULLDUPLEX))
|
||||
|
||||
#define IS_I2S_FULLDUPLEX(__MODE__) (((__MODE__) == I2S_MODE_MASTER_FULLDUPLEX) || \
|
||||
((__MODE__) == I2S_MODE_SLAVE_FULLDUPLEX))
|
||||
|
||||
#define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS) || \
|
||||
((__STANDARD__) == I2S_STANDARD_MSB) || \
|
||||
((__STANDARD__) == I2S_STANDARD_LSB) || \
|
||||
((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \
|
||||
((__STANDARD__) == I2S_STANDARD_PCM_LONG))
|
||||
|
||||
#define IS_I2S_DATA_FORMAT(__FORMAT__) (((__FORMAT__) == I2S_DATAFORMAT_16B) || \
|
||||
((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED) || \
|
||||
((__FORMAT__) == I2S_DATAFORMAT_24B) || \
|
||||
((__FORMAT__) == I2S_DATAFORMAT_32B))
|
||||
|
||||
#define IS_I2S_MCLK_OUTPUT(__OUTPUT__) (((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE) || \
|
||||
((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE))
|
||||
|
||||
#define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K) && \
|
||||
((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \
|
||||
((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))
|
||||
|
||||
#define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) || \
|
||||
((__CPOL__) == I2S_CPOL_HIGH))
|
||||
|
||||
#define IS_I2S_FIRST_BIT(__BIT__) (((__BIT__) == I2S_FIRSTBIT_MSB) || \
|
||||
((__BIT__) == I2S_FIRSTBIT_LSB))
|
||||
|
||||
#define IS_I2S_WS_INVERSION(__WSINV__) (((__WSINV__) == I2S_WS_INVERSION_DISABLE) || \
|
||||
((__WSINV__) == I2S_WS_INVERSION_ENABLE))
|
||||
|
||||
#define IS_I2S_DATA_24BIT_ALIGNMENT(__ALIGNMENT__) (((__ALIGNMENT__) == I2S_DATA_24BIT_ALIGNMENT_RIGHT) || \
|
||||
((__ALIGNMENT__) == I2S_DATA_24BIT_ALIGNMENT_LEFT))
|
||||
|
||||
#define IS_I2S_MASTER_KEEP_IO_STATE(__AFCNTR__) (((__AFCNTR__) == I2S_MASTER_KEEP_IO_STATE_DISABLE) || \
|
||||
((__AFCNTR__) == I2S_MASTER_KEEP_IO_STATE_ENABLE))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H5xx_HAL_I2S_H */
|
||||
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h5xx_hal_i2s_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of I2S HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
===== I2S FULL DUPLEX FEATURE =====
|
||||
I2S Full Duplex APIs are available in stm32h5xx_hal_i2s.c/.h
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,300 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h5xx_hal_icache.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of ICACHE HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion ------------------------------------*/
|
||||
#ifndef STM32H5xx_HAL_ICACHE_H
|
||||
#define STM32H5xx_HAL_ICACHE_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes -----------------------------------------------------------------*/
|
||||
#include "stm32h5xx_hal_def.h"
|
||||
|
||||
#if defined(ICACHE)
|
||||
/** @addtogroup STM32H5xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ICACHE
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types -----------------------------------------------------------*/
|
||||
#if defined(ICACHE_CRRx_REN)
|
||||
/** @defgroup ICACHE_Exported_Types ICACHE Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HAL ICACHE region configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t BaseAddress; /*!< Configures the Base address of Region i to be remapped */
|
||||
|
||||
uint32_t RemapAddress; /*!< Configures the Remap address of Region i to be remapped */
|
||||
|
||||
uint32_t Size; /*!< Configures the Region size.
|
||||
This parameter can be a value of @ref ICACHE_Region_Size */
|
||||
|
||||
uint32_t TrafficRoute; /*!< Selects the traffic route.
|
||||
This parameter can be a value of @ref ICACHE_Traffic_Route */
|
||||
|
||||
uint32_t OutputBurstType; /*!< Selects the output burst type.
|
||||
This parameter can be a value of @ref ICACHE_Output_Burst_Type */
|
||||
} ICACHE_RegionConfigTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* ICACHE_CRRx_REN */
|
||||
|
||||
/* Exported constants -------------------------------------------------------*/
|
||||
/** @defgroup ICACHE_Exported_Constants ICACHE Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup ICACHE_WaysSelection Ways selection
|
||||
* @{
|
||||
*/
|
||||
#define ICACHE_1WAY 0U /*!< 1-way cache (direct mapped cache) */
|
||||
#define ICACHE_2WAYS ICACHE_CR_WAYSEL /*!< 2-ways set associative cache (default) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ICACHE_Monitor_Type Monitor type
|
||||
* @{
|
||||
*/
|
||||
#define ICACHE_MONITOR_HIT_MISS (ICACHE_CR_HITMEN | ICACHE_CR_MISSMEN) /*!< Hit & Miss monitoring */
|
||||
#define ICACHE_MONITOR_HIT ICACHE_CR_HITMEN /*!< Hit monitoring */
|
||||
#define ICACHE_MONITOR_MISS ICACHE_CR_MISSMEN /*!< Miss monitoring */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(ICACHE_CRRx_REN)
|
||||
/** @defgroup ICACHE_Region Remapped Region number
|
||||
* @{
|
||||
*/
|
||||
#define ICACHE_REGION_0 0U /*!< Region 0 */
|
||||
#define ICACHE_REGION_1 1U /*!< Region 1 */
|
||||
#define ICACHE_REGION_2 2U /*!< Region 2 */
|
||||
#define ICACHE_REGION_3 3U /*!< Region 3 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ICACHE_Region_Size Remapped Region size
|
||||
* @{
|
||||
*/
|
||||
#define ICACHE_REGIONSIZE_2MB 1U /*!< Region size 2MB */
|
||||
#define ICACHE_REGIONSIZE_4MB 2U /*!< Region size 4MB */
|
||||
#define ICACHE_REGIONSIZE_8MB 3U /*!< Region size 8MB */
|
||||
#define ICACHE_REGIONSIZE_16MB 4U /*!< Region size 16MB */
|
||||
#define ICACHE_REGIONSIZE_32MB 5U /*!< Region size 32MB */
|
||||
#define ICACHE_REGIONSIZE_64MB 6U /*!< Region size 64MB */
|
||||
#define ICACHE_REGIONSIZE_128MB 7U /*!< Region size 128MB */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ICACHE_Traffic_Route Remapped Traffic route
|
||||
* @{
|
||||
*/
|
||||
#define ICACHE_MASTER1_PORT 0U /*!< Master1 port */
|
||||
#define ICACHE_MASTER2_PORT ICACHE_CRRx_MSTSEL /*!< Master2 port */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ICACHE_Output_Burst_Type Remapped Output burst type
|
||||
* @{
|
||||
*/
|
||||
#define ICACHE_OUTPUT_BURST_WRAP 0U /*!< WRAP */
|
||||
#define ICACHE_OUTPUT_BURST_INCR ICACHE_CRRx_HBURST /*!< INCR */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* ICACHE_CRRx_REN */
|
||||
|
||||
/** @defgroup ICACHE_Interrupts Interrupts
|
||||
* @{
|
||||
*/
|
||||
#define ICACHE_IT_BUSYEND ICACHE_IER_BSYENDIE /*!< Busy end interrupt */
|
||||
#define ICACHE_IT_ERROR ICACHE_IER_ERRIE /*!< Cache error interrupt */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ICACHE_Flags Flags
|
||||
* @{
|
||||
*/
|
||||
#define ICACHE_FLAG_BUSY ICACHE_SR_BUSYF /*!< Busy flag */
|
||||
#define ICACHE_FLAG_BUSYEND ICACHE_SR_BSYENDF /*!< Busy end flag */
|
||||
#define ICACHE_FLAG_ERROR ICACHE_SR_ERRF /*!< Cache error flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros ----------------------------------------------------------*/
|
||||
/** @defgroup ICACHE_Exported_Macros ICACHE Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup ICACHE_Flags_Interrupts_Management Flags and Interrupts Management
|
||||
* @brief macros to manage the specified ICACHE flags and interrupts.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Enable ICACHE interrupts.
|
||||
* @param __INTERRUPT__ specifies the ICACHE interrupt sources to be enabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref ICACHE_IT_BUSYEND Busy end interrupt
|
||||
* @arg @ref ICACHE_IT_ERROR Cache error interrupt
|
||||
*/
|
||||
#define __HAL_ICACHE_ENABLE_IT(__INTERRUPT__) SET_BIT(ICACHE->IER, (__INTERRUPT__))
|
||||
|
||||
/** @brief Disable ICACHE interrupts.
|
||||
* @param __INTERRUPT__ specifies the ICACHE interrupt sources to be disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref ICACHE_IT_BUSYEND Busy end interrupt
|
||||
* @arg @ref ICACHE_IT_ERROR Cache error interrupt
|
||||
*/
|
||||
#define __HAL_ICACHE_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(ICACHE->IER, (__INTERRUPT__))
|
||||
|
||||
/** @brief Check whether the specified ICACHE interrupt source is enabled or not.
|
||||
* @param __INTERRUPT__ specifies the ICACHE interrupt source to check.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref ICACHE_IT_BUSYEND Busy end interrupt
|
||||
* @arg @ref ICACHE_IT_ERROR Cache error interrupt
|
||||
* @retval The state of __INTERRUPT__ (0 or 1).
|
||||
*/
|
||||
#define __HAL_ICACHE_GET_IT_SOURCE(__INTERRUPT__) \
|
||||
((READ_BIT(ICACHE->IER, (__INTERRUPT__)) == (__INTERRUPT__)) ? 1U : 0U)
|
||||
|
||||
/** @brief Check whether the selected ICACHE flag is set or not.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref ICACHE_FLAG_BUSY Busy flag
|
||||
* @arg @ref ICACHE_FLAG_BUSYEND Busy end flag
|
||||
* @arg @ref ICACHE_FLAG_ERROR Cache error flag
|
||||
* @retval The state of __FLAG__ (0 or 1).
|
||||
*/
|
||||
#define __HAL_ICACHE_GET_FLAG(__FLAG__) ((READ_BIT(ICACHE->SR, (__FLAG__)) != 0U) ? 1U : 0U)
|
||||
|
||||
/** @brief Clear the selected ICACHE flags.
|
||||
* @param __FLAG__ specifies the ICACHE flags to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref ICACHE_FLAG_BUSYEND Busy end flag
|
||||
* @arg @ref ICACHE_FLAG_ERROR Cache error flag
|
||||
*/
|
||||
#define __HAL_ICACHE_CLEAR_FLAG(__FLAG__) WRITE_REG(ICACHE->FCR, (__FLAG__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions -------------------------------------------------------*/
|
||||
/** @addtogroup ICACHE_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ICACHE_Exported_Functions_Group1
|
||||
* @brief Initialization and control functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions **********************************************/
|
||||
HAL_StatusTypeDef HAL_ICACHE_Enable(void);
|
||||
HAL_StatusTypeDef HAL_ICACHE_Disable(void);
|
||||
uint32_t HAL_ICACHE_IsEnabled(void);
|
||||
HAL_StatusTypeDef HAL_ICACHE_ConfigAssociativityMode(uint32_t AssociativityMode);
|
||||
HAL_StatusTypeDef HAL_ICACHE_DeInit(void);
|
||||
|
||||
/******* Invalidate in blocking mode (Polling) */
|
||||
HAL_StatusTypeDef HAL_ICACHE_Invalidate(void);
|
||||
/******* Invalidate in non-blocking mode (Interrupt) */
|
||||
HAL_StatusTypeDef HAL_ICACHE_Invalidate_IT(void);
|
||||
/******* Wait for Invalidate complete in blocking mode (Polling) */
|
||||
HAL_StatusTypeDef HAL_ICACHE_WaitForInvalidateComplete(void);
|
||||
|
||||
/******* Performance instruction cache monitoring functions */
|
||||
HAL_StatusTypeDef HAL_ICACHE_Monitor_Start(uint32_t MonitorType);
|
||||
HAL_StatusTypeDef HAL_ICACHE_Monitor_Stop(uint32_t MonitorType);
|
||||
HAL_StatusTypeDef HAL_ICACHE_Monitor_Reset(uint32_t MonitorType);
|
||||
uint32_t HAL_ICACHE_Monitor_GetHitValue(void);
|
||||
uint32_t HAL_ICACHE_Monitor_GetMissValue(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup ICACHE_Exported_Functions_Group2
|
||||
* @brief IRQ and callback functions
|
||||
* @{
|
||||
*/
|
||||
/******* IRQHandler and Callbacks used in non-blocking mode (Interrupt) */
|
||||
void HAL_ICACHE_IRQHandler(void);
|
||||
void HAL_ICACHE_InvalidateCompleteCallback(void);
|
||||
void HAL_ICACHE_ErrorCallback(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(ICACHE_CRRx_REN)
|
||||
/** @addtogroup ICACHE_Exported_Functions_Group3
|
||||
* @brief Memory remapped regions functions
|
||||
* @{
|
||||
*/
|
||||
/******* Memory remapped regions functions */
|
||||
HAL_StatusTypeDef HAL_ICACHE_EnableRemapRegion(uint32_t Region, const ICACHE_RegionConfigTypeDef *const pRegionConfig);
|
||||
HAL_StatusTypeDef HAL_ICACHE_DisableRemapRegion(uint32_t Region);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* ICACHE_CRRx_REN */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* ICACHE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H5xx_HAL_ICACHE_H */
|
||||
|
|
@ -0,0 +1,902 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h5xx_hal_irda.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of IRDA HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H5xx_HAL_IRDA_H
|
||||
#define STM32H5xx_HAL_IRDA_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h5xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H5xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup IRDA
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup IRDA_Exported_Types IRDA Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief IRDA Init Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t BaudRate; /*!< This member configures the IRDA communication baud rate.
|
||||
The baud rate register is computed using the following formula:
|
||||
Baud Rate Register = ((usart_ker_ckpres) / ((hirda->Init.BaudRate)))
|
||||
where usart_ker_ckpres is the IRDA input clock divided by a prescaler */
|
||||
|
||||
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
|
||||
This parameter can be a value of @ref IRDAEx_Word_Length */
|
||||
|
||||
uint32_t Parity; /*!< Specifies the parity mode.
|
||||
This parameter can be a value of @ref IRDA_Parity
|
||||
@note When parity is enabled, the computed parity is inserted
|
||||
at the MSB position of the transmitted data (9th bit when
|
||||
the word length is set to 9 data bits; 8th bit when the
|
||||
word length is set to 8 data bits). */
|
||||
|
||||
uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
|
||||
This parameter can be a value of @ref IRDA_Transfer_Mode */
|
||||
|
||||
uint8_t Prescaler; /*!< Specifies the Prescaler value for dividing the UART/USART source clock
|
||||
to achieve low-power frequency.
|
||||
@note Prescaler value 0 is forbidden */
|
||||
|
||||
uint16_t PowerMode; /*!< Specifies the IRDA power mode.
|
||||
This parameter can be a value of @ref IRDA_Low_Power */
|
||||
|
||||
uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the IRDA clock source.
|
||||
This parameter can be a value of @ref IRDA_ClockPrescaler. */
|
||||
|
||||
} IRDA_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL IRDA State definition
|
||||
* @note HAL IRDA State value is a combination of 2 different substates:
|
||||
* gState and RxState (see @ref IRDA_State_Definition).
|
||||
* - gState contains IRDA state information related to global Handle management
|
||||
* and also information related to Tx operations.
|
||||
* gState value coding follow below described bitmap :
|
||||
* b7-b6 Error information
|
||||
* 00 : No Error
|
||||
* 01 : (Not Used)
|
||||
* 10 : Timeout
|
||||
* 11 : Error
|
||||
* b5 Peripheral initialization status
|
||||
* 0 : Reset (Peripheral not initialized)
|
||||
* 1 : Init done (Peripheral initialized. HAL IRDA Init function already called)
|
||||
* b4-b3 (not used)
|
||||
* xx : Should be set to 00
|
||||
* b2 Intrinsic process state
|
||||
* 0 : Ready
|
||||
* 1 : Busy (Peripheral busy with some configuration or internal operations)
|
||||
* b1 (not used)
|
||||
* x : Should be set to 0
|
||||
* b0 Tx state
|
||||
* 0 : Ready (no Tx operation ongoing)
|
||||
* 1 : Busy (Tx operation ongoing)
|
||||
* - RxState contains information related to Rx operations.
|
||||
* RxState value coding follow below described bitmap :
|
||||
* b7-b6 (not used)
|
||||
* xx : Should be set to 00
|
||||
* b5 Peripheral initialization status
|
||||
* 0 : Reset (Peripheral not initialized)
|
||||
* 1 : Init done (Peripheral initialized)
|
||||
* b4-b2 (not used)
|
||||
* xxx : Should be set to 000
|
||||
* b1 Rx state
|
||||
* 0 : Ready (no Rx operation ongoing)
|
||||
* 1 : Busy (Rx operation ongoing)
|
||||
* b0 (not used)
|
||||
* x : Should be set to 0.
|
||||
*/
|
||||
typedef uint32_t HAL_IRDA_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief IRDA clock sources definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
IRDA_CLOCKSOURCE_PLL2Q = 0x14U, /*!< PLL2Q clock source */
|
||||
#if defined(RCC_CR_PLL3ON)
|
||||
IRDA_CLOCKSOURCE_PLL3Q = 0x18U, /*!< PLL3Q clock source */
|
||||
#endif /* RCC_CR_PLL3ON */
|
||||
IRDA_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
|
||||
IRDA_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */
|
||||
IRDA_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
|
||||
IRDA_CLOCKSOURCE_CSI = 0x08U, /*!< CSI clock source */
|
||||
IRDA_CLOCKSOURCE_LSE = 0x10U, /*!< LSE clock source */
|
||||
IRDA_CLOCKSOURCE_UNDEFINED = 0x20U /*!< Undefined clock source */
|
||||
} IRDA_ClockSourceTypeDef;
|
||||
|
||||
/**
|
||||
* @brief IRDA handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __IRDA_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
|
||||
{
|
||||
USART_TypeDef *Instance; /*!< USART registers base address */
|
||||
|
||||
IRDA_InitTypeDef Init; /*!< IRDA communication parameters */
|
||||
|
||||
const uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */
|
||||
|
||||
uint16_t TxXferSize; /*!< IRDA Tx Transfer size */
|
||||
|
||||
__IO uint16_t TxXferCount; /*!< IRDA Tx Transfer Counter */
|
||||
|
||||
uint8_t *pRxBuffPtr; /*!< Pointer to IRDA Rx transfer Buffer */
|
||||
|
||||
uint16_t RxXferSize; /*!< IRDA Rx Transfer size */
|
||||
|
||||
__IO uint16_t RxXferCount; /*!< IRDA Rx Transfer Counter */
|
||||
|
||||
uint16_t Mask; /*!< USART RX RDR register mask */
|
||||
|
||||
#if defined(HAL_DMA_MODULE_ENABLED)
|
||||
DMA_HandleTypeDef *hdmatx; /*!< IRDA Tx DMA Handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< IRDA Rx DMA Handle parameters */
|
||||
|
||||
#endif /* HAL_DMA_MODULE_ENABLED */
|
||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||
|
||||
__IO HAL_IRDA_StateTypeDef gState; /*!< IRDA state information related to global Handle management
|
||||
and also related to Tx operations.
|
||||
This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
|
||||
|
||||
__IO HAL_IRDA_StateTypeDef RxState; /*!< IRDA state information related to Rx operations.
|
||||
This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< IRDA Error code */
|
||||
|
||||
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
|
||||
void (* TxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Tx Half Complete Callback */
|
||||
|
||||
void (* TxCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Tx Complete Callback */
|
||||
|
||||
void (* RxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Rx Half Complete Callback */
|
||||
|
||||
void (* RxCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Rx Complete Callback */
|
||||
|
||||
void (* ErrorCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Error Callback */
|
||||
|
||||
void (* AbortCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Complete Callback */
|
||||
|
||||
void (* AbortTransmitCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Transmit Complete Callback */
|
||||
|
||||
void (* AbortReceiveCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Receive Complete Callback */
|
||||
|
||||
|
||||
void (* MspInitCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Msp Init callback */
|
||||
|
||||
void (* MspDeInitCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Msp DeInit callback */
|
||||
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
|
||||
|
||||
} IRDA_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL IRDA Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_IRDA_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< IRDA Tx Half Complete Callback ID */
|
||||
HAL_IRDA_TX_COMPLETE_CB_ID = 0x01U, /*!< IRDA Tx Complete Callback ID */
|
||||
HAL_IRDA_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< IRDA Rx Half Complete Callback ID */
|
||||
HAL_IRDA_RX_COMPLETE_CB_ID = 0x03U, /*!< IRDA Rx Complete Callback ID */
|
||||
HAL_IRDA_ERROR_CB_ID = 0x04U, /*!< IRDA Error Callback ID */
|
||||
HAL_IRDA_ABORT_COMPLETE_CB_ID = 0x05U, /*!< IRDA Abort Complete Callback ID */
|
||||
HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< IRDA Abort Transmit Complete Callback ID */
|
||||
HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< IRDA Abort Receive Complete Callback ID */
|
||||
|
||||
HAL_IRDA_MSPINIT_CB_ID = 0x08U, /*!< IRDA MspInit callback ID */
|
||||
HAL_IRDA_MSPDEINIT_CB_ID = 0x09U /*!< IRDA MspDeInit callback ID */
|
||||
|
||||
} HAL_IRDA_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL IRDA Callback pointer definition
|
||||
*/
|
||||
typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer to an IRDA callback function */
|
||||
|
||||
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup IRDA_Exported_Constants IRDA Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_State_Definition IRDA State Code Definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_IRDA_STATE_RESET 0x00000000U /*!< Peripheral is not initialized
|
||||
Value is allowed for gState and RxState */
|
||||
#define HAL_IRDA_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use
|
||||
Value is allowed for gState and RxState */
|
||||
#define HAL_IRDA_STATE_BUSY 0x00000024U /*!< An internal process is ongoing
|
||||
Value is allowed for gState only */
|
||||
#define HAL_IRDA_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing
|
||||
Value is allowed for gState only */
|
||||
#define HAL_IRDA_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing
|
||||
Value is allowed for RxState only */
|
||||
#define HAL_IRDA_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing
|
||||
Not to be used for neither gState nor RxState.
|
||||
Value is result of combination (Or) between
|
||||
gState and RxState values */
|
||||
#define HAL_IRDA_STATE_TIMEOUT 0x000000A0U /*!< Timeout state
|
||||
Value is allowed for gState only */
|
||||
#define HAL_IRDA_STATE_ERROR 0x000000E0U /*!< Error
|
||||
Value is allowed for gState only */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Error_Definition IRDA Error Code Definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_IRDA_ERROR_NONE (0x00000000U) /*!< No error */
|
||||
#define HAL_IRDA_ERROR_PE (0x00000001U) /*!< Parity error */
|
||||
#define HAL_IRDA_ERROR_NE (0x00000002U) /*!< Noise error */
|
||||
#define HAL_IRDA_ERROR_FE (0x00000004U) /*!< frame error */
|
||||
#define HAL_IRDA_ERROR_ORE (0x00000008U) /*!< Overrun error */
|
||||
#if defined(HAL_DMA_MODULE_ENABLED)
|
||||
#define HAL_IRDA_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
|
||||
#endif /* HAL_DMA_MODULE_ENABLED */
|
||||
#define HAL_IRDA_ERROR_BUSY (0x00000020U) /*!< Busy Error */
|
||||
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_IRDA_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Parity IRDA Parity
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_PARITY_NONE 0x00000000U /*!< No parity */
|
||||
#define IRDA_PARITY_EVEN USART_CR1_PCE /*!< Even parity */
|
||||
#define IRDA_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_MODE_RX USART_CR1_RE /*!< RX mode */
|
||||
#define IRDA_MODE_TX USART_CR1_TE /*!< TX mode */
|
||||
#define IRDA_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Low_Power IRDA Low Power
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_POWERMODE_NORMAL 0x00000000U /*!< IRDA normal power mode */
|
||||
#define IRDA_POWERMODE_LOWPOWER USART_CR3_IRLP /*!< IRDA low power mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_ClockPrescaler IRDA Clock Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */
|
||||
#define IRDA_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */
|
||||
#define IRDA_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */
|
||||
#define IRDA_PRESCALER_DIV6 0x00000003U /*!< fclk_pres = fclk/6 */
|
||||
#define IRDA_PRESCALER_DIV8 0x00000004U /*!< fclk_pres = fclk/8 */
|
||||
#define IRDA_PRESCALER_DIV10 0x00000005U /*!< fclk_pres = fclk/10 */
|
||||
#define IRDA_PRESCALER_DIV12 0x00000006U /*!< fclk_pres = fclk/12 */
|
||||
#define IRDA_PRESCALER_DIV16 0x00000007U /*!< fclk_pres = fclk/16 */
|
||||
#define IRDA_PRESCALER_DIV32 0x00000008U /*!< fclk_pres = fclk/32 */
|
||||
#define IRDA_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */
|
||||
#define IRDA_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */
|
||||
#define IRDA_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_State IRDA State
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_STATE_DISABLE 0x00000000U /*!< IRDA disabled */
|
||||
#define IRDA_STATE_ENABLE USART_CR1_UE /*!< IRDA enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Mode IRDA Mode
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_MODE_DISABLE 0x00000000U /*!< Associated UART disabled in IRDA mode */
|
||||
#define IRDA_MODE_ENABLE USART_CR3_IREN /*!< Associated UART enabled in IRDA mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_One_Bit IRDA One Bit Sampling
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< One-bit sampling disabled */
|
||||
#define IRDA_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< One-bit sampling enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_DMA_Tx IRDA DMA Tx
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_DMA_TX_DISABLE 0x00000000U /*!< IRDA DMA TX disabled */
|
||||
#define IRDA_DMA_TX_ENABLE USART_CR3_DMAT /*!< IRDA DMA TX enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_DMA_Rx IRDA DMA Rx
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_DMA_RX_DISABLE 0x00000000U /*!< IRDA DMA RX disabled */
|
||||
#define IRDA_DMA_RX_ENABLE USART_CR3_DMAR /*!< IRDA DMA RX enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Request_Parameters IRDA Request Parameters
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_AUTOBAUD_REQUEST USART_RQR_ABRRQ /*!< Auto-Baud Rate Request */
|
||||
#define IRDA_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */
|
||||
#define IRDA_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Flags IRDA Flags
|
||||
* Elements values convention: 0xXXXX
|
||||
* - 0xXXXX : Flag mask in the ISR register
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_FLAG_REACK USART_ISR_REACK /*!< IRDA receive enable acknowledge flag */
|
||||
#define IRDA_FLAG_TEACK USART_ISR_TEACK /*!< IRDA transmit enable acknowledge flag */
|
||||
#define IRDA_FLAG_BUSY USART_ISR_BUSY /*!< IRDA busy flag */
|
||||
#define IRDA_FLAG_ABRF USART_ISR_ABRF /*!< IRDA auto Baud rate flag */
|
||||
#define IRDA_FLAG_ABRE USART_ISR_ABRE /*!< IRDA auto Baud rate error */
|
||||
#define IRDA_FLAG_TXE USART_ISR_TXE_TXFNF /*!< IRDA transmit data register empty */
|
||||
#define IRDA_FLAG_TC USART_ISR_TC /*!< IRDA transmission complete */
|
||||
#define IRDA_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< IRDA read data register not empty */
|
||||
#define IRDA_FLAG_ORE USART_ISR_ORE /*!< IRDA overrun error */
|
||||
#define IRDA_FLAG_NE USART_ISR_NE /*!< IRDA noise error */
|
||||
#define IRDA_FLAG_FE USART_ISR_FE /*!< IRDA frame error */
|
||||
#define IRDA_FLAG_PE USART_ISR_PE /*!< IRDA parity error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Interrupt_definition IRDA Interrupts Definition
|
||||
* Elements values convention: 0000ZZZZ0XXYYYYYb
|
||||
* - YYYYY : Interrupt source position in the XX register (5bits)
|
||||
* - XX : Interrupt source register (2bits)
|
||||
* - 01: CR1 register
|
||||
* - 10: CR2 register
|
||||
* - 11: CR3 register
|
||||
* - ZZZZ : Flag position in the ISR register(4bits)
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_IT_PE 0x0028U /*!< IRDA Parity error interruption */
|
||||
#define IRDA_IT_TXE 0x0727U /*!< IRDA Transmit data register empty interruption */
|
||||
#define IRDA_IT_TC 0x0626U /*!< IRDA Transmission complete interruption */
|
||||
#define IRDA_IT_RXNE 0x0525U /*!< IRDA Read data register not empty interruption */
|
||||
#define IRDA_IT_IDLE 0x0424U /*!< IRDA Idle interruption */
|
||||
|
||||
/* Elements values convention: 000000000XXYYYYYb
|
||||
- YYYYY : Interrupt source position in the XX register (5bits)
|
||||
- XX : Interrupt source register (2bits)
|
||||
- 01: CR1 register
|
||||
- 10: CR2 register
|
||||
- 11: CR3 register */
|
||||
#define IRDA_IT_ERR 0x0060U /*!< IRDA Error interruption */
|
||||
|
||||
/* Elements values convention: 0000ZZZZ00000000b
|
||||
- ZZZZ : Flag position in the ISR register(4bits) */
|
||||
#define IRDA_IT_ORE 0x0300U /*!< IRDA Overrun error interruption */
|
||||
#define IRDA_IT_NE 0x0200U /*!< IRDA Noise error interruption */
|
||||
#define IRDA_IT_FE 0x0100U /*!< IRDA Frame error interruption */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_IT_CLEAR_Flags IRDA Interruption Clear Flags
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
|
||||
#define IRDA_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
|
||||
#define IRDA_CLEAR_NEF USART_ICR_NECF /*!< Noise Error detected Clear Flag */
|
||||
#define IRDA_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
|
||||
#define IRDA_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
|
||||
#define IRDA_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Interruption_Mask IRDA interruptions flags mask
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_IT_MASK 0x001FU /*!< IRDA Interruptions flags mask */
|
||||
#define IRDA_CR_MASK 0x00E0U /*!< IRDA control register mask */
|
||||
#define IRDA_CR_POS 5U /*!< IRDA control register position */
|
||||
#define IRDA_ISR_MASK 0x1F00U /*!< IRDA ISR register mask */
|
||||
#define IRDA_ISR_POS 8U /*!< IRDA ISR register position */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup IRDA_Exported_Macros IRDA Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset IRDA handle state.
|
||||
* @param __HANDLE__ IRDA handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
|
||||
#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \
|
||||
(__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0U)
|
||||
#else
|
||||
#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \
|
||||
(__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \
|
||||
} while(0U)
|
||||
#endif /*USE_HAL_IRDA_REGISTER_CALLBACKS */
|
||||
|
||||
/** @brief Flush the IRDA DR register.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) \
|
||||
do{ \
|
||||
SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
|
||||
SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
|
||||
} while(0U)
|
||||
|
||||
/** @brief Clear the specified IRDA pending flag.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref IRDA_CLEAR_PEF
|
||||
* @arg @ref IRDA_CLEAR_FEF
|
||||
* @arg @ref IRDA_CLEAR_NEF
|
||||
* @arg @ref IRDA_CLEAR_OREF
|
||||
* @arg @ref IRDA_CLEAR_TCF
|
||||
* @arg @ref IRDA_CLEAR_IDLEF
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
|
||||
|
||||
/** @brief Clear the IRDA PE pending flag.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)
|
||||
|
||||
|
||||
/** @brief Clear the IRDA FE pending flag.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)
|
||||
|
||||
/** @brief Clear the IRDA NE pending flag.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)
|
||||
|
||||
/** @brief Clear the IRDA ORE pending flag.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)
|
||||
|
||||
/** @brief Clear the IRDA IDLE pending flag.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)
|
||||
|
||||
/** @brief Check whether the specified IRDA flag is set or not.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref IRDA_FLAG_REACK Receive enable acknowledge flag
|
||||
* @arg @ref IRDA_FLAG_TEACK Transmit enable acknowledge flag
|
||||
* @arg @ref IRDA_FLAG_BUSY Busy flag
|
||||
* @arg @ref IRDA_FLAG_ABRF Auto Baud rate detection flag
|
||||
* @arg @ref IRDA_FLAG_ABRE Auto Baud rate detection error flag
|
||||
* @arg @ref IRDA_FLAG_TXE Transmit data register empty flag
|
||||
* @arg @ref IRDA_FLAG_TC Transmission Complete flag
|
||||
* @arg @ref IRDA_FLAG_RXNE Receive data register not empty flag
|
||||
* @arg @ref IRDA_FLAG_ORE OverRun Error flag
|
||||
* @arg @ref IRDA_FLAG_NE Noise Error flag
|
||||
* @arg @ref IRDA_FLAG_FE Framing Error flag
|
||||
* @arg @ref IRDA_FLAG_PE Parity Error flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
|
||||
/** @brief Enable the specified IRDA interrupt.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @param __INTERRUPT__ specifies the IRDA interrupt source to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
|
||||
* @arg @ref IRDA_IT_TC Transmission complete interrupt
|
||||
* @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
|
||||
* @arg @ref IRDA_IT_IDLE Idle line detection interrupt
|
||||
* @arg @ref IRDA_IT_PE Parity Error interrupt
|
||||
* @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \
|
||||
((__HANDLE__)->Instance->CR1 |= (1U << \
|
||||
((__INTERRUPT__) & IRDA_IT_MASK))):\
|
||||
((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \
|
||||
((__HANDLE__)->Instance->CR2 |= (1U << \
|
||||
((__INTERRUPT__) & IRDA_IT_MASK))):\
|
||||
((__HANDLE__)->Instance->CR3 |= (1U << \
|
||||
((__INTERRUPT__) & IRDA_IT_MASK))))
|
||||
|
||||
/** @brief Disable the specified IRDA interrupt.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @param __INTERRUPT__ specifies the IRDA interrupt source to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
|
||||
* @arg @ref IRDA_IT_TC Transmission complete interrupt
|
||||
* @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
|
||||
* @arg @ref IRDA_IT_IDLE Idle line detection interrupt
|
||||
* @arg @ref IRDA_IT_PE Parity Error interrupt
|
||||
* @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \
|
||||
((__HANDLE__)->Instance->CR1 &= ~ (1U << \
|
||||
((__INTERRUPT__) & IRDA_IT_MASK))): \
|
||||
((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \
|
||||
((__HANDLE__)->Instance->CR2 &= ~ (1U << \
|
||||
((__INTERRUPT__) & IRDA_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 &= ~ (1U << \
|
||||
((__INTERRUPT__) & IRDA_IT_MASK))))
|
||||
|
||||
/** @brief Check whether the specified IRDA interrupt has occurred or not.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @param __INTERRUPT__ specifies the IRDA interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
|
||||
* @arg @ref IRDA_IT_TC Transmission complete interrupt
|
||||
* @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
|
||||
* @arg @ref IRDA_IT_IDLE Idle line detection interrupt
|
||||
* @arg @ref IRDA_IT_ORE OverRun Error interrupt
|
||||
* @arg @ref IRDA_IT_NE Noise Error interrupt
|
||||
* @arg @ref IRDA_IT_FE Framing Error interrupt
|
||||
* @arg @ref IRDA_IT_PE Parity Error interrupt
|
||||
* @retval The new state of __IT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) \
|
||||
((((__HANDLE__)->Instance->ISR& (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>>IRDA_ISR_POS))) != 0U) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified IRDA interrupt source is enabled or not.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @param __INTERRUPT__ specifies the IRDA interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
|
||||
* @arg @ref IRDA_IT_TC Transmission complete interrupt
|
||||
* @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
|
||||
* @arg @ref IRDA_IT_IDLE Idle line detection interrupt
|
||||
* @arg @ref IRDA_IT_ERR Framing, overrun or noise error interrupt
|
||||
* @arg @ref IRDA_IT_PE Parity Error interrupt
|
||||
* @retval The new state of __IT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
|
||||
((((((((__INTERRUPT__) & IRDA_CR_MASK) >>IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 :(((((__INTERRUPT__) \
|
||||
& IRDA_CR_MASK) >> IRDA_CR_POS)== 0x02U)? (__HANDLE__)->Instance->CR2 :(__HANDLE__)->Instance->CR3)) \
|
||||
& (0x01U <<(((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET)
|
||||
|
||||
/** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
|
||||
* to clear the corresponding interrupt
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref IRDA_CLEAR_PEF Parity Error Clear Flag
|
||||
* @arg @ref IRDA_CLEAR_FEF Framing Error Clear Flag
|
||||
* @arg @ref IRDA_CLEAR_NEF Noise detected Clear Flag
|
||||
* @arg @ref IRDA_CLEAR_OREF OverRun Error Clear Flag
|
||||
* @arg @ref IRDA_CLEAR_TCF Transmission Complete Clear Flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
|
||||
|
||||
|
||||
/** @brief Set a specific IRDA request flag.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @param __REQ__ specifies the request flag to set
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request
|
||||
* @arg @ref IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request
|
||||
* @arg @ref IRDA_TXDATA_FLUSH_REQUEST Transmit data flush Request
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
|
||||
|
||||
/** @brief Enable the IRDA one bit sample method.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
|
||||
|
||||
/** @brief Disable the IRDA one bit sample method.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\
|
||||
&= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
|
||||
|
||||
/** @brief Enable UART/USART associated to IRDA Handle.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
|
||||
|
||||
/** @brief Disable UART/USART associated to IRDA Handle.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros --------------------------------------------------------*/
|
||||
/** @addtogroup IRDA_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Ensure that IRDA Baud rate is less or equal to maximum value.
|
||||
* @param __BAUDRATE__ specifies the IRDA Baudrate set by the user.
|
||||
* @retval True or False
|
||||
*/
|
||||
#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201U)
|
||||
|
||||
/** @brief Ensure that IRDA prescaler value is strictly larger than 0.
|
||||
* @param __PRESCALER__ specifies the IRDA prescaler value set by the user.
|
||||
* @retval True or False
|
||||
*/
|
||||
#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0U)
|
||||
|
||||
/** @brief Ensure that IRDA frame parity is valid.
|
||||
* @param __PARITY__ IRDA frame parity.
|
||||
* @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \
|
||||
((__PARITY__) == IRDA_PARITY_EVEN) || \
|
||||
((__PARITY__) == IRDA_PARITY_ODD))
|
||||
|
||||
/** @brief Ensure that IRDA communication mode is valid.
|
||||
* @param __MODE__ IRDA communication mode.
|
||||
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__)\
|
||||
& (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
|
||||
|
||||
/** @brief Ensure that IRDA power mode is valid.
|
||||
* @param __MODE__ IRDA power mode.
|
||||
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \
|
||||
((__MODE__) == IRDA_POWERMODE_NORMAL))
|
||||
|
||||
/** @brief Ensure that IRDA clock Prescaler is valid.
|
||||
* @param __CLOCKPRESCALER__ IRDA clock Prescaler value.
|
||||
* @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV1) || \
|
||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV2) || \
|
||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV4) || \
|
||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV6) || \
|
||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV8) || \
|
||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV10) || \
|
||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV12) || \
|
||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV16) || \
|
||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV32) || \
|
||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV64) || \
|
||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV128) || \
|
||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV256))
|
||||
|
||||
/** @brief Ensure that IRDA state is valid.
|
||||
* @param __STATE__ IRDA state mode.
|
||||
* @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \
|
||||
((__STATE__) == IRDA_STATE_ENABLE))
|
||||
|
||||
/** @brief Ensure that IRDA associated UART/USART mode is valid.
|
||||
* @param __MODE__ IRDA associated UART/USART mode.
|
||||
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_MODE(__MODE__) (((__MODE__) == IRDA_MODE_DISABLE) || \
|
||||
((__MODE__) == IRDA_MODE_ENABLE))
|
||||
|
||||
/** @brief Ensure that IRDA sampling rate is valid.
|
||||
* @param __ONEBIT__ IRDA sampling rate.
|
||||
* @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \
|
||||
((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE))
|
||||
|
||||
/** @brief Ensure that IRDA DMA TX mode is valid.
|
||||
* @param __DMATX__ IRDA DMA TX mode.
|
||||
* @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_DMA_TX(__DMATX__) (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \
|
||||
((__DMATX__) == IRDA_DMA_TX_ENABLE))
|
||||
|
||||
/** @brief Ensure that IRDA DMA RX mode is valid.
|
||||
* @param __DMARX__ IRDA DMA RX mode.
|
||||
* @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \
|
||||
((__DMARX__) == IRDA_DMA_RX_ENABLE))
|
||||
|
||||
/** @brief Ensure that IRDA request is valid.
|
||||
* @param __PARAM__ IRDA request.
|
||||
* @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \
|
||||
((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \
|
||||
((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include IRDA HAL Extended module */
|
||||
#include "stm32h5xx_hal_irda_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
|
||||
|
||||
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID,
|
||||
pIRDA_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
|
||||
#if defined(HAL_DMA_MODULE_ENABLED)
|
||||
HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
|
||||
#endif /* HAL_DMA_MODULE_ENABLED */
|
||||
/* Transfer Abort functions */
|
||||
HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda);
|
||||
|
||||
void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions ************************************************/
|
||||
|
||||
/** @addtogroup IRDA_Exported_Functions_Group4 Peripheral State and Error functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_IRDA_StateTypeDef HAL_IRDA_GetState(const IRDA_HandleTypeDef *hirda);
|
||||
uint32_t HAL_IRDA_GetError(const IRDA_HandleTypeDef *hirda);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H5xx_HAL_IRDA_H */
|
||||
|
||||
|
|
@ -0,0 +1,559 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h5xx_hal_irda_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of IRDA HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H5xx_HAL_IRDA_EX_H
|
||||
#define STM32H5xx_HAL_IRDA_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h5xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H5xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IRDAEx IRDAEx
|
||||
* @brief IRDA Extended HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup IRDAEx_Extended_Exported_Constants IRDAEx Extended Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IRDAEx_Word_Length IRDAEx Word Length
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long frame */
|
||||
#define IRDA_WORDLENGTH_8B 0x00000000U /*!< 8-bit long frame */
|
||||
#define IRDA_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long frame */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup IRDAEx_Private_Macros IRDAEx Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Report the IRDA clock source.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @param __CLOCKSOURCE__ output variable.
|
||||
* @retval IRDA clocking source, written in __CLOCKSOURCE__.
|
||||
*/
|
||||
#if (defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx))
|
||||
#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK2: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_CSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_PLL2Q: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_PLL3Q: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART2_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART2CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_CSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_PLL2Q: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_PLL3Q: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART3) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART3_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART3CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_CSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_PLL2Q: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_PLL3Q: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == UART4) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_UART4_SOURCE()) \
|
||||
{ \
|
||||
case RCC_UART4CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_UART4CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_UART4CLKSOURCE_CSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \
|
||||
break; \
|
||||
case RCC_UART4CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
case RCC_UART4CLKSOURCE_PLL2Q: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \
|
||||
break; \
|
||||
case RCC_UART4CLKSOURCE_PLL3Q: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == UART5) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_UART5_SOURCE()) \
|
||||
{ \
|
||||
case RCC_UART5CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_UART5CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_UART5CLKSOURCE_CSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \
|
||||
break; \
|
||||
case RCC_UART5CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
case RCC_UART5CLKSOURCE_PLL2Q: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \
|
||||
break; \
|
||||
case RCC_UART5CLKSOURCE_PLL3Q: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART6) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART6_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART6CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART6CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART6CLKSOURCE_CSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \
|
||||
break; \
|
||||
case RCC_USART6CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
case RCC_USART6CLKSOURCE_PLL2Q: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \
|
||||
break; \
|
||||
case RCC_USART6CLKSOURCE_PLL3Q: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == UART7) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_UART7_SOURCE()) \
|
||||
{ \
|
||||
case RCC_UART7CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_UART7CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_UART7CLKSOURCE_CSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \
|
||||
break; \
|
||||
case RCC_UART7CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
case RCC_UART7CLKSOURCE_PLL2Q: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \
|
||||
break; \
|
||||
case RCC_UART7CLKSOURCE_PLL3Q: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == UART8) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_UART8_SOURCE()) \
|
||||
{ \
|
||||
case RCC_UART8CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_UART8CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_UART8CLKSOURCE_CSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \
|
||||
break; \
|
||||
case RCC_UART8CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
case RCC_UART8CLKSOURCE_PLL2Q: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \
|
||||
break; \
|
||||
case RCC_UART8CLKSOURCE_PLL3Q: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == UART9) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_UART9_SOURCE()) \
|
||||
{ \
|
||||
case RCC_UART9CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_UART9CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_UART9CLKSOURCE_CSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \
|
||||
break; \
|
||||
case RCC_UART9CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
case RCC_UART9CLKSOURCE_PLL2Q: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \
|
||||
break; \
|
||||
case RCC_UART9CLKSOURCE_PLL3Q: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART10) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART10_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART10CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART10CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART10CLKSOURCE_CSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \
|
||||
break; \
|
||||
case RCC_USART10CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
case RCC_USART10CLKSOURCE_PLL2Q: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \
|
||||
break; \
|
||||
case RCC_USART10CLKSOURCE_PLL3Q: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART11) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART11_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART11CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART11CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART11CLKSOURCE_CSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \
|
||||
break; \
|
||||
case RCC_USART11CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
case RCC_USART11CLKSOURCE_PLL2Q: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \
|
||||
break; \
|
||||
case RCC_USART11CLKSOURCE_PLL3Q: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == UART12) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_UART12_SOURCE()) \
|
||||
{ \
|
||||
case RCC_UART12CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_UART12CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_UART12CLKSOURCE_CSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \
|
||||
break; \
|
||||
case RCC_UART12CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
case RCC_UART12CLKSOURCE_PLL2Q: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \
|
||||
break; \
|
||||
case RCC_UART12CLKSOURCE_PLL3Q: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0U)
|
||||
#else
|
||||
#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK2: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_CSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_PLL2Q: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART2_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART2CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_CSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_PLL2Q: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART3) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART3_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART3CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_CSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_PLL2Q: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0U)
|
||||
|
||||
#endif /* (defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) */
|
||||
|
||||
/** @brief Compute the mask to apply to retrieve the received data
|
||||
* according to the word length and to the parity bits activation.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None, the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field.
|
||||
*/
|
||||
#define IRDA_MASK_COMPUTATION(__HANDLE__) \
|
||||
do { \
|
||||
if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x01FFU ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x00FFU ; \
|
||||
} \
|
||||
} \
|
||||
else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x00FFU ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x007FU ; \
|
||||
} \
|
||||
} \
|
||||
else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x007FU ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x003FU ; \
|
||||
} \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x0000U; \
|
||||
} \
|
||||
} while(0U)
|
||||
|
||||
/** @brief Ensure that IRDA frame length is valid.
|
||||
* @param __LENGTH__ IRDA frame length.
|
||||
* @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_7B) || \
|
||||
((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
|
||||
((__LENGTH__) == IRDA_WORDLENGTH_9B))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H5xx_HAL_IRDA_EX_H */
|
||||
|
||||
|
|
@ -0,0 +1,302 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h5xx_hal_iwdg.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of IWDG HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H5xx_HAL_IWDG_H
|
||||
#define STM32H5xx_HAL_IWDG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h5xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H5xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG IWDG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Exported_Types IWDG Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief IWDG Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Prescaler; /*!< Select the prescaler of the IWDG.
|
||||
This parameter can be a value of @ref IWDG_Prescaler */
|
||||
|
||||
uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
|
||||
|
||||
uint32_t Window; /*!< Specifies the window value to be compared to the down-counter.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
|
||||
|
||||
uint32_t EWI; /*!< Specifies if IWDG Early Wakeup Interrupt is enable or not and the comparator value.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF
|
||||
value 0 means that EWI is disabled */
|
||||
} IWDG_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief IWDG Handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_IWDG_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __IWDG_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_IWDG_REGISTER_CALLBACKS */
|
||||
{
|
||||
IWDG_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
IWDG_InitTypeDef Init; /*!< IWDG required parameters */
|
||||
|
||||
#if (USE_HAL_IWDG_REGISTER_CALLBACKS == 1)
|
||||
void (* EwiCallback)(struct __IWDG_HandleTypeDef *hiwdg); /*!< IWDG Early WakeUp Interrupt callback */
|
||||
void (* MspInitCallback)(struct __IWDG_HandleTypeDef *hiwdg); /*!< IWDG Msp Init callback */
|
||||
#endif /* USE_HAL_IWDG_REGISTER_CALLBACKS */
|
||||
} IWDG_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_IWDG_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL IWDG common Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_IWDG_EWI_CB_ID = 0x00U, /*!< IWDG EWI callback ID */
|
||||
HAL_IWDG_MSPINIT_CB_ID = 0x01U, /*!< IWDG MspInit callback ID */
|
||||
} HAL_IWDG_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL IWDG Callback pointer definition
|
||||
*/
|
||||
typedef void (*pIWDG_CallbackTypeDef)(IWDG_HandleTypeDef *hppp); /*!< pointer to a IWDG common callback functions */
|
||||
#endif /* USE_HAL_IWDG_REGISTER_CALLBACKS */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Exported_Constants IWDG Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Prescaler IWDG Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define IWDG_PRESCALER_4 0x00000000u /*!< IWDG prescaler set to 4 */
|
||||
#define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */
|
||||
#define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */
|
||||
#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */
|
||||
#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */
|
||||
#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
|
||||
#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
|
||||
#define IWDG_PRESCALER_512 (IWDG_PR_PR_2 | IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 512 */
|
||||
#define IWDG_PRESCALER_1024 IWDG_PR_PR_3 /*!< IWDG prescaler set to 1024 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Window_option IWDG Window option
|
||||
* @{
|
||||
*/
|
||||
#define IWDG_WINDOW_DISABLE IWDG_WINR_WIN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_EWI_Mode IWDG Early Wakeup Interrupt Mode
|
||||
* @{
|
||||
*/
|
||||
#define IWDG_EWI_DISABLE 0x00000000u /*!< EWI Disable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Active_Status IWDG Active Status
|
||||
* @{
|
||||
*/
|
||||
#define IWDG_STATUS_DISABLE 0x00000000u
|
||||
#define IWDG_STATUS_ENABLE IWDG_SR_ONF
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Exported_Macros IWDG Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the IWDG peripheral.
|
||||
* @param __HANDLE__ IWDG handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
|
||||
|
||||
/**
|
||||
* @brief Reload IWDG counter with value defined in the reload register
|
||||
* (write access to IWDG_PR, IWDG_RLR, IWDG_WINR and EWCR registers disabled).
|
||||
* @param __HANDLE__ IWDG handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Exported_Functions IWDG Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/Start functions ********************************************/
|
||||
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
|
||||
void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg);
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_IWDG_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_IWDG_RegisterCallback(IWDG_HandleTypeDef *hiwdg, HAL_IWDG_CallbackIDTypeDef CallbackID,
|
||||
pIWDG_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_IWDG_UnRegisterCallback(IWDG_HandleTypeDef *hiwdg, HAL_IWDG_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_IWDG_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
|
||||
* @{
|
||||
*/
|
||||
/* I/O operation functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
|
||||
uint32_t HAL_IWDG_GetActiveStatus(const IWDG_HandleTypeDef *hiwdg);
|
||||
void HAL_IWDG_IRQHandler(IWDG_HandleTypeDef *hiwdg);
|
||||
void HAL_IWDG_EarlyWakeupCallback(IWDG_HandleTypeDef *hiwdg);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Private_Constants IWDG Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief IWDG Key Register BitMask
|
||||
*/
|
||||
#define IWDG_KEY_RELOAD 0x0000AAAAu /*!< IWDG Reload Counter Enable */
|
||||
#define IWDG_KEY_ENABLE 0x0000CCCCu /*!< IWDG Peripheral Enable */
|
||||
#define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u /*!< IWDG KR Write Access Enable */
|
||||
#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u /*!< IWDG KR Write Access Disable */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Private_Macros IWDG Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable write access to IWDG_PR, IWDG_RLR, IWDG_WINR and EWCR registers.
|
||||
* @param __HANDLE__ IWDG handle
|
||||
* @retval None
|
||||
*/
|
||||
#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
|
||||
|
||||
/**
|
||||
* @brief Disable write access to IWDG_PR, IWDG_RLR, IWDG_WINR and EWCR registers.
|
||||
* @param __HANDLE__ IWDG handle
|
||||
* @retval None
|
||||
*/
|
||||
#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
|
||||
|
||||
/**
|
||||
* @brief Check IWDG prescaler value.
|
||||
* @param __PRESCALER__ IWDG prescaler value
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \
|
||||
((__PRESCALER__) == IWDG_PRESCALER_8) || \
|
||||
((__PRESCALER__) == IWDG_PRESCALER_16) || \
|
||||
((__PRESCALER__) == IWDG_PRESCALER_32) || \
|
||||
((__PRESCALER__) == IWDG_PRESCALER_64) || \
|
||||
((__PRESCALER__) == IWDG_PRESCALER_128)|| \
|
||||
((__PRESCALER__) == IWDG_PRESCALER_256)|| \
|
||||
((__PRESCALER__) == IWDG_PRESCALER_512)|| \
|
||||
((__PRESCALER__) == IWDG_PRESCALER_1024))
|
||||
|
||||
/**
|
||||
* @brief Check IWDG reload value.
|
||||
* @param __RELOAD__ IWDG reload value
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
|
||||
|
||||
/**
|
||||
* @brief Check IWDG window value.
|
||||
* @param __WINDOW__ IWDG window value
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN)
|
||||
|
||||
/**
|
||||
* @brief Check IWDG ewi value.
|
||||
* @param __EWI__ IWDG ewi value
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_IWDG_EWI(__EWI__) ((__EWI__) <= IWDG_EWCR_EWIT)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H5xx_HAL_IWDG_H */
|
||||
Some files were not shown because too many files have changed in this diff Show More
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Reference in New Issue