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[bsp][phytium]适配rt-thread5.0.0 版本 (#7441) 

Co-authored-by: 朱耿宇 <zhugengyu@phytium.com.cn>
This commit is contained in:
huanghe 2023-05-11 10:25:21 +08:00 committed by GitHub
parent 23f91e83ab
commit 50a4e8c662
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
468 changed files with 35041 additions and 7087 deletions
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12
bsp/phytium/.gitignore vendored
View File

@ -1 +1,11 @@
*.dis
*.dis
*.asm
/aarch32/tools/gnu_gcc/*
/aarch32/tools/ci.py
/aarch32/tools/get_toolchain.py
/aarch32/smart-env.sh
/aarch64/tools/gnu_gcc/*
/aarch64/tools/ci.py
/aarch64/tools/get_toolchain.py
/aarch64/smart-env.sh
**/**/makefile

115
bsp/phytium/aarch32/.config
View File

@ -6,12 +6,12 @@
#
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=8
CONFIG_RT_NAME_MAX=16
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMART is not set
CONFIG_RT_USING_SMART=y
CONFIG_RT_USING_SMP=y
CONFIG_RT_CPUS_NR=4
CONFIG_RT_ALIGN_SIZE=8
CONFIG_RT_CPUS_NR=2
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
@ -22,11 +22,11 @@ CONFIG_RT_USING_HOOK=y
CONFIG_RT_HOOK_USING_FUNC_PTR=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=256
CONFIG_SYSTEM_THREAD_STACK_SIZE=256
CONFIG_IDLE_THREAD_STACK_SIZE=4096
CONFIG_SYSTEM_THREAD_STACK_SIZE=4096
CONFIG_RT_USING_TIMER_SOFT=y
CONFIG_RT_TIMER_THREAD_PRIO=4
CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
CONFIG_RT_TIMER_THREAD_STACK_SIZE=4096
#
# kservice optimization
@ -35,7 +35,7 @@ CONFIG_RT_KSERVICE_USING_STDLIB=y
# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set
# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
# CONFIG_RT_USING_TINY_FFS is not set
# CONFIG_RT_KPRINTF_USING_LONGLONG is not set
CONFIG_RT_KPRINTF_USING_LONGLONG=y
CONFIG_RT_DEBUG=y
# CONFIG_RT_DEBUG_COLOR is not set
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
@ -47,6 +47,7 @@ CONFIG_RT_DEBUG=y
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_PAGE_LEAK is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
#
@ -66,7 +67,9 @@ CONFIG_RT_PAGE_MAX_ORDER=11
CONFIG_RT_USING_MEMPOOL=y
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
# CONFIG_RT_USING_MEMHEAP is not set
CONFIG_RT_USING_MEMHEAP=y
CONFIG_RT_MEMHEAP_FAST_MODE=y
# CONFIG_RT_MEMHEAP_BEST_MODE is not set
CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
# CONFIG_RT_USING_SLAB_AS_HEAP is not set
@ -84,9 +87,9 @@ CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_DM is not set
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLEBUF_SIZE=256
CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
CONFIG_RT_VER_NUM=0x50000
CONFIG_RT_VER_NUM=0x50001
# CONFIG_RT_USING_STDC_ATOMIC is not set
CONFIG_RT_USING_CACHE=y
CONFIG_RT_USING_HW_ATOMIC=y
@ -96,6 +99,8 @@ CONFIG_RT_USING_CPU_FFS=y
CONFIG_ARCH_MM_MMU=y
CONFIG_ARCH_ARM=y
CONFIG_ARCH_ARM_MMU=y
CONFIG_KERNEL_VADDR_START=0xc0000000
# CONFIG_RT_IOREMAP_LATE is not set
CONFIG_ARCH_ARM_CORTEX_A=y
# CONFIG_RT_SMP_AUTO_BOOT is not set
# CONFIG_RT_USING_GIC_V2 is not set
@ -108,7 +113,7 @@ CONFIG_RT_USING_GIC_V3=y
#
CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
CONFIG_RT_MAIN_THREAD_STACK_SIZE=8192
CONFIG_RT_MAIN_THREAD_PRIORITY=10
# CONFIG_RT_USING_LEGACY is not set
CONFIG_RT_USING_MSH=y
@ -126,49 +131,70 @@ CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_ARG_MAX=10
#
# DFS: device virtual file system
#
CONFIG_RT_USING_DFS=y
CONFIG_DFS_USING_POSIX=y
CONFIG_DFS_USING_WORKDIR=y
# CONFIG_RT_USING_DFS_MNTTABLE is not set
CONFIG_DFS_FD_MAX=16
CONFIG_RT_USING_DFS_V1=y
# CONFIG_RT_USING_DFS_V2 is not set
CONFIG_DFS_FILESYSTEMS_MAX=4
CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
CONFIG_DFS_FD_MAX=16
# CONFIG_RT_USING_DFS_MNTTABLE is not set
# CONFIG_RT_USING_DFS_ELMFAT is not set
# CONFIG_RT_USING_DFS_DEVFS is not set
CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_CROMFS is not set
# CONFIG_RT_USING_DFS_RAMFS is not set
CONFIG_RT_USING_DFS_RAMFS=y
# CONFIG_RT_USING_DFS_TMPFS is not set
# CONFIG_RT_USING_FAL is not set
CONFIG_RT_USING_LWP=y
CONFIG_RT_LWP_MAX_NR=30
CONFIG_LWP_TASK_STACK_SIZE=16384
CONFIG_RT_CH_MSG_MAX_NR=1024
CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024
CONFIG_LWP_TID_MAX_NR=64
CONFIG_LWP_ENABLE_ASID=y
CONFIG_RT_LWP_SHM_MAX_NR=64
# CONFIG_LWP_UNIX98_PTY is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_UNAMED_PIPE_NUMBER=64
# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=4096
CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
CONFIG_RT_USING_SERIAL=y
CONFIG_RT_USING_SERIAL_V1=y
# CONFIG_RT_USING_SERIAL_V2 is not set
CONFIG_RT_SERIAL_USING_DMA=y
CONFIG_RT_SERIAL_RB_BUFSZ=64
CONFIG_RT_SERIAL_RB_BUFSZ=1024
CONFIG_RT_USING_TTY=y
# CONFIG_RT_TTY_DEBUG is not set
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
# CONFIG_RT_USING_PHY is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_PIN is not set
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_NULL is not set
# CONFIG_RT_USING_ZERO is not set
# CONFIG_RT_USING_RANDOM is not set
CONFIG_RT_USING_NULL=y
CONFIG_RT_USING_ZERO=y
CONFIG_RT_USING_RANDOM=y
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_FDT is not set
# CONFIG_RT_USING_RTC is not set
CONFIG_RT_USING_RTC=y
# CONFIG_RT_USING_ALARM is not set
# CONFIG_RT_USING_SOFT_RTC is not set
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
@ -198,19 +224,28 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
#
# POSIX (Portable Operating System Interface) layer
#
# CONFIG_RT_USING_POSIX_FS is not set
# CONFIG_RT_USING_POSIX_DELAY is not set
# CONFIG_RT_USING_POSIX_CLOCK is not set
# CONFIG_RT_USING_POSIX_TIMER is not set
CONFIG_RT_USING_POSIX_FS=y
CONFIG_RT_USING_POSIX_DEVIO=y
CONFIG_RT_USING_POSIX_STDIO=y
CONFIG_RT_USING_POSIX_POLL=y
CONFIG_RT_USING_POSIX_SELECT=y
# CONFIG_RT_USING_POSIX_SOCKET is not set
CONFIG_RT_USING_POSIX_TERMIOS=y
CONFIG_RT_USING_POSIX_AIO=y
# CONFIG_RT_USING_POSIX_MMAN is not set
CONFIG_RT_USING_POSIX_DELAY=y
CONFIG_RT_USING_POSIX_CLOCK=y
CONFIG_RT_USING_POSIX_TIMER=y
# CONFIG_RT_USING_PTHREADS is not set
# CONFIG_RT_USING_MODULE is not set
#
# Interprocess Communication (IPC)
#
# CONFIG_RT_USING_POSIX_PIPE is not set
# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
CONFIG_RT_USING_POSIX_PIPE=y
CONFIG_RT_USING_POSIX_PIPE_SIZE=512
CONFIG_RT_USING_POSIX_MESSAGE_QUEUE=y
CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE=y
#
# Socket is in the 'Network' category
@ -228,9 +263,13 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
#
# Utilities
#
# CONFIG_RT_USING_RYM is not set
CONFIG_RT_USING_RYM=y
# CONFIG_YMODEM_USING_CRC_TABLE is not set
CONFIG_YMODEM_USING_FILE_TRANSFER=y
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
CONFIG_RT_USING_UTEST=y
CONFIG_UTEST_THR_STACK_SIZE=4096
CONFIG_UTEST_THR_PRIORITY=20
# CONFIG_RT_USING_VAR_EXPORT is not set
CONFIG_RT_USING_ADT=y
# CONFIG_RT_USING_RT_LINK is not set
@ -627,7 +666,6 @@ CONFIG_RT_USING_ADT=y
# CONFIG_PKG_USING_LKDGUI is not set
# CONFIG_PKG_USING_NRF5X_SDK is not set
# CONFIG_PKG_USING_NRFX is not set
# CONFIG_PKG_USING_WM_LIBRARIES is not set
#
# Kendryte SDK
@ -685,7 +723,6 @@ CONFIG_RT_USING_ADT=y
# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
# CONFIG_PKG_USING_BL_MCU_SDK is not set
# CONFIG_PKG_USING_SOFT_SERIAL is not set
# CONFIG_PKG_USING_MB85RS16 is not set
# CONFIG_PKG_USING_RFM300 is not set
@ -1000,6 +1037,9 @@ CONFIG_RT_USING_ADT=y
CONFIG_BSP_USING_UART=y
CONFIG_RT_USING_UART1=y
# CONFIG_RT_USING_UART0 is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_CAN is not set
# CONFIG_BSP_USING_QSPI is not set
#
# Board extended module Drivers
@ -1017,8 +1057,8 @@ CONFIG_USE_AARCH64_L1_TO_AARCH32=y
#
# CONFIG_TARGET_F2000_4 is not set
# CONFIG_TARGET_D2000 is not set
CONFIG_TARGET_E2000Q=y
# CONFIG_TARGET_E2000D is not set
# CONFIG_TARGET_E2000Q is not set
CONFIG_TARGET_E2000D=y
# CONFIG_TARGET_E2000S is not set
CONFIG_TARGET_E2000=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
@ -1055,6 +1095,8 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_ADC is not set
# CONFIG_USE_PWM is not set
# CONFIG_USE_IPC is not set
# CONFIG_USE_MEDIA is not set
# CONFIG_USE_SCMI_MHU is not set
# CONFIG_LOG_VERBOS is not set
# CONFIG_LOG_DEBUG is not set
# CONFIG_LOG_INFO is not set
@ -1065,4 +1107,5 @@ CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
CONFIG_INTERRUPT_ROLE_MASTER=y
# CONFIG_INTERRUPT_ROLE_SLAVE is not set
# CONFIG_LOG_EXTRA_INFO is not set
# CONFIG_LOG_DISPALY_CORE_NUM is not set
# CONFIG_BOOTUP_DEBUG_PRINTS is not set

1152
bsp/phytium/aarch32/.configs Normal file
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File diff suppressed because it is too large Load Diff

4
bsp/phytium/aarch32/Kconfig
View File

@ -38,14 +38,14 @@ menu "Standalone Setting"
config TARGET_ARMV8_AARCH32
bool "Armv8 Aarch32"
default y
config USE_AARCH64_L1_TO_AARCH32
bool
prompt "Use Aarch64 L1 to Aarch32 code"
default y
help
Use the Aarch64 to Aarch32 mode function
source "$STANDALONE_DIR/board/Kconfig"
source "$STANDALONE_DIR/drivers/Kconfig"
source "$STANDALONE_DIR/common/Kconfig"

96
bsp/phytium/aarch32/README.md
View File

@ -1,18 +1,48 @@
# AARCH32 工作模式使用
- 当开发者需要基于 Phytium 系列芯片进行开发时，可以从以下几个步骤出发配置芯片
## 1. 准备编译环境
## 1. 如何选择芯片
- 在 aarch32 目录下创建 tools 目录，后续用于存放 RT-Thread 编译工具链
- Windows Env 环境下
```shell
menuconfig
```sh
cd ./aarch32
mkdir tools
```
- Linux 环境下
- 在 tools 目录下下载两个 python 脚本，get_toolchain.py 和 ci.py，下载完后给两个脚本添加执行权限
```shell
cd ./tools
wget https://gitee.com/rtthread/ART-Pi-smart/raw/master/tools/get_toolchain.py
wget https://gitee.com/rtthread/ART-Pi-smart/raw/master/tools/ci.py
chmod +x get_toolchain.py ci.py
```
- 然后运行 get_toolchain.py 脚本，拉取 aarch32 交叉编译链`arm-linux-musleabi_for_x86_64-pc-linux-gnu`
```shell
python3 ./get_toolchain.py arm
```
> RT-Thread 5.0 后必须使用这个带 musl-libc 的编译链，不能使用`arm-none-eabi`
- 在 aarch32 目录下下载脚本 smart-env.sh ，然后运行脚本生效环境变量
```shell
cd ./aarch32
wget https://gitee.com/rtthread/ART-Pi-smart/raw/master/smart-env.sh
source ./smart-env.sh arm
```
- 如下所示是 aarch32 编译相关的环境变量，运行 scons 前要确保环境变量设置正确
![aarch32_env](./figures/aarch32_env.png)
## 2. 如何选择芯片
- 以 E2000Q RT-Smart为例，Linux 环境下，运行 make load_e2000q_rtsmart 加载默认的 rtconfig, 然后输入下列命令，进入 menuconfig 进一步配置，
```shell
scons --menuconfig
@ -27,8 +57,7 @@ Standalone Setting > Board Configuration > Chip
![](./figures/chip_select.png)
![](./figures/phytium_cpu_select.png)
## 2. 如何选择驱动
## 3. 如何选择驱动
```shell
scons --menuconfig
@ -42,9 +71,7 @@ Hardware Drivers > On-chip Peripheral Drivers
![](./figures/select_driver.png)
## 3. 开启SDK中内部调试信息
## 4. 开启SDK中内部调试信息
```shell
scons --menuconfig
@ -55,8 +82,19 @@ Hardware Drivers > On-chip Peripheral Drivers
![](./figures/select_debug_info.png)
## 4. 如何切换至RT-Thread Smart 工作模式
## 4. 编译程序
```shell
scons --menuconfig
```
![1682477587050](figures/1682477587050.png)
开发者通过以上配置开启RT-Thread Smart 功能
## 5. 编译程序
```shell
scons -c
@ -71,18 +109,36 @@ rtthread_a32.elf
rtthread_a32.map
```
## 5. 打包导出工程源代码
## 6. 启动镜像程序
- 可以用串口通过 XMODEM 协议将 bin/elf 文件上传到开发板，然后启动，
- 首先在 Phytium 开发板上输入，上传 bin 文件
```
loadx 80080000
```
![](./figures/ymodem_upload.png)
- 加载 bin 文件完成后，输入下列命令启动
```
go 80080000
```
## 7. 打包导出工程源代码
- 指定工程名和路径，打包RT-Thread内核和Phytium BSP代码，可以导出一个工程工程
```
python ./export_project.py -n=phytium-a32 -o=D:/proj/rt-thread-e2000/phytium-a32
```
![](./figures/export_project.png)
- 进入打包工程的目录，修改工程根目录 Kconfig 中的路径 BSP_DIR 和 STANDALONE_DIR
- 进入打包工程的目录，修改工程根目录 Kconfig 中的路径 BSP_DIR 和 STANDALONE_DIR
> env 环境中的 menuconfig 不会调用 SConstruct 修改路径环境变量，因此需要手动修改路径
```
@ -99,10 +155,12 @@ config STANDALONE_DIR
- 输入 menuconfig 和 scons 完成编译
## 8. 将工程导入 RT-Studio
## 6. 将工程导入 RT-Studio
- 在 RT-Studio 使用功能`RT-Thread Bsp 到工作空间`，导入 5. 中导出的 BSP 工程
- 在 RT-Studio 使用功能 `RT-Thread Bsp 到工作空间`，导入 5. 中导出的 BSP 工程
- 设置 BSP 工程的交叉编译链后进行后续开发
![](./figures/import_project.png)
![](./figures/import_project.png)
python get_toolchain.py arm
./smart-env.bat

5
bsp/phytium/aarch32/SConstruct
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@ -53,6 +53,11 @@ if not IS_EXPORTED: # if project is not exported, libraries and board need to ma
# include board
objs.extend(SConscript(os.path.join(BSP_ROOT + '/board', 'SConscript')))
if GetDepend('RT_USING_SMART'):
# use smart link.lds
env['LINKFLAGS'] = env['LINKFLAGS'].replace('link.lds', 'link_smart.lds')
# make a building
DoBuilding(TARGET, objs)

2
bsp/phytium/aarch32/applications/main.c
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@ -70,7 +70,7 @@ void demo_core(void)
int main(void)
{
#ifdef RT_USING_SMP
demo_core();
// demo_core();
#endif
return RT_EOK;
}

63
bsp/phytium/aarch32/applications/mnt.c Normal file
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@ -0,0 +1,63 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Email: opensource_embedded@phytium.com.cn
*
* Change Logs:
* Date Author Notes
* 2023-04-27 huanghe first version
*
*/
#include <rtthread.h>
#ifdef RT_USING_DFS_RAMFS
#include <dfs_fs.h>
extern struct dfs_ramfs *dfs_ramfs_create(rt_uint8_t *pool, rt_size_t size);
int mnt_init(void)
{
rt_uint8_t *pool = RT_NULL;
rt_size_t size = 8*1024*1024;
pool = rt_malloc(size);
if (pool == RT_NULL)
return 0;
if (dfs_mount(RT_NULL, "/", "ram", 0, (const void *)dfs_ramfs_create(pool, size)) == 0)
rt_kprintf("RAM file system initializated!\n");
else
rt_kprintf("RAM file system initializate failed!\n");
return 0;
}
INIT_ENV_EXPORT(mnt_init);
#endif
#ifdef BSP_USING_SDCARD_FATFS
#include <dfs_fs.h>
#include <dfs_file.h>
#define DBG_TAG "app.filesystem"
#define DBG_LVL DBG_INFO
#include <rtdbg.h>
static int filesystem_mount(void)
{
while(rt_device_find("sd0") == RT_NULL)
{
rt_thread_mdelay(1);
}
int ret = dfs_mount("sd0", "/", "elm", 0, 0);
if (ret != 0)
{
rt_kprintf("ret: %d\n",ret);
LOG_E("sd0 mount to '/' failed!");
return ret;
}
return RT_EOK;
}
INIT_ENV_EXPORT(filesystem_mount);
#endif

1111
bsp/phytium/aarch32/configs/e2000d_rtsmart Normal file
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319
bsp/phytium/aarch32/configs/e2000d_rtsmart.h Normal file
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@ -0,0 +1,319 @@
#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* RT-Thread Project Configuration */
/* RT-Thread Kernel */
#define RT_NAME_MAX 16
#define RT_USING_SMART
#define RT_USING_SMP
#define RT_CPUS_NR 2
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 4096
#define SYSTEM_THREAD_STACK_SIZE 4096
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 4096
/* kservice optimization */
#define RT_KSERVICE_USING_STDLIB
#define RT_KPRINTF_USING_LONGLONG
#define RT_DEBUG
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* Memory Management */
#define RT_PAGE_MAX_ORDER 11
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SMALL_MEM_AS_HEAP
#define RT_USING_HEAP
/* Kernel Device Object */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 256
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50001
#define RT_USING_CACHE
#define RT_USING_HW_ATOMIC
#define RT_USING_CPU_FFS
#define ARCH_MM_MMU
#define ARCH_ARM
#define ARCH_ARM_MMU
#define KERNEL_VADDR_START 0xc0000000
#define ARCH_ARM_CORTEX_A
#define RT_USING_GIC_V3
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 8192
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
/* DFS: device virtual file system */
#define RT_USING_DFS
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FD_MAX 16
#define RT_USING_DFS_V1
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_RAMFS
#define RT_USING_LWP
#define RT_LWP_MAX_NR 30
#define LWP_TASK_STACK_SIZE 16384
#define RT_CH_MSG_MAX_NR 1024
#define LWP_CONSOLE_INPUT_BUFFER_SIZE 1024
#define LWP_TID_MAX_NR 64
#define LWP_ENABLE_ASID
#define RT_LWP_SHM_MAX_NR 64
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 4096
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 1024
#define RT_USING_TTY
#define RT_USING_NULL
#define RT_USING_ZERO
#define RT_USING_RANDOM
#define RT_USING_RTC
/* Using USB */
/* C/C++ and POSIX layer */
#define RT_LIBC_DEFAULT_TIMEZONE 8
/* POSIX (Portable Operating System Interface) layer */
#define RT_USING_POSIX_FS
#define RT_USING_POSIX_DEVIO
#define RT_USING_POSIX_STDIO
#define RT_USING_POSIX_POLL
#define RT_USING_POSIX_SELECT
#define RT_USING_POSIX_TERMIOS
#define RT_USING_POSIX_AIO
#define RT_USING_POSIX_DELAY
#define RT_USING_POSIX_CLOCK
#define RT_USING_POSIX_TIMER
/* Interprocess Communication (IPC) */
#define RT_USING_POSIX_PIPE
#define RT_USING_POSIX_PIPE_SIZE 512
#define RT_USING_POSIX_MESSAGE_QUEUE
#define RT_USING_POSIX_MESSAGE_SEMAPHORE
/* Socket is in the 'Network' category */
/* Network */
/* Utilities */
#define RT_USING_RYM
#define YMODEM_USING_FILE_TRANSFER
#define RT_USING_UTEST
#define UTEST_THR_STACK_SIZE 4096
#define UTEST_THR_PRIORITY 20
#define RT_USING_ADT
/* RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* Wiced WiFi */
/* IoT Cloud */
/* security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
/* tools packages */
/* system packages */
/* enhanced kernel services */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
/* peripheral libraries and drivers */
/* sensors drivers */
/* touch drivers */
/* Kendryte SDK */
/* AI packages */
/* Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
/* samples: kernel and components samples */
/* entertainment: terminal games and other interesting software packages */
/* Arduino libraries */
/* Projects */
/* Sensors */
/* Display */
/* Timing */
/* Data Processing */
/* Data Storage */
/* Communication */
/* Device Control */
/* Other */
/* Signal IO */
/* Uncategorized */
/* Hardware Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_UART
#define RT_USING_UART1
/* Board extended module Drivers */
#define PHYTIUM_ARCH_AARCH32
/* Standalone Setting */
#define TARGET_ARMV8_AARCH32
#define USE_AARCH64_L1_TO_AARCH32
/* Board Configuration */
#define TARGET_E2000D
#define TARGET_E2000
#define DEFAULT_DEBUG_PRINT_UART1
/* Components Configuration */
#define USE_GIC
#define ENABLE_GICV3
#define USE_SERIAL
/* Usart Configuration */
#define ENABLE_Pl011_UART
#define LOG_ERROR
#define USE_DEFAULT_INTERRUPT_CONFIG
#define INTERRUPT_ROLE_MASTER
#endif

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#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* RT-Thread Project Configuration */
/* RT-Thread Kernel */
#define RT_NAME_MAX 16
#define RT_USING_SMP
#define RT_CPUS_NR 2
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 4096
#define SYSTEM_THREAD_STACK_SIZE 4096
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 4096
/* kservice optimization */
#define RT_KSERVICE_USING_STDLIB
#define RT_KPRINTF_USING_LONGLONG
#define RT_DEBUG
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* Memory Management */
#define RT_PAGE_MAX_ORDER 11
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SMALL_MEM_AS_HEAP
#define RT_USING_HEAP
/* Kernel Device Object */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 256
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50001
#define RT_USING_CACHE
#define RT_USING_HW_ATOMIC
#define RT_USING_CPU_FFS
#define ARCH_MM_MMU
#define ARCH_ARM
#define ARCH_ARM_MMU
#define ARCH_ARM_CORTEX_A
#define RT_USING_GIC_V3
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 8192
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
/* DFS: device virtual file system */
#define RT_USING_DFS
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FD_MAX 16
#define RT_USING_DFS_V1
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_RAMFS
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 4096
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 1024
#define RT_USING_NULL
#define RT_USING_ZERO
#define RT_USING_RANDOM
#define RT_USING_RTC
/* Using USB */
/* C/C++ and POSIX layer */
#define RT_LIBC_DEFAULT_TIMEZONE 8
/* POSIX (Portable Operating System Interface) layer */
#define RT_USING_POSIX_FS
#define RT_USING_POSIX_DEVIO
#define RT_USING_POSIX_STDIO
#define RT_USING_POSIX_POLL
#define RT_USING_POSIX_SELECT
#define RT_USING_POSIX_TERMIOS
#define RT_USING_POSIX_AIO
#define RT_USING_POSIX_DELAY
#define RT_USING_POSIX_CLOCK
#define RT_USING_POSIX_TIMER
/* Interprocess Communication (IPC) */
#define RT_USING_POSIX_PIPE
#define RT_USING_POSIX_PIPE_SIZE 512
#define RT_USING_POSIX_MESSAGE_QUEUE
#define RT_USING_POSIX_MESSAGE_SEMAPHORE
/* Socket is in the 'Network' category */
/* Network */
/* Utilities */
#define RT_USING_RYM
#define YMODEM_USING_FILE_TRANSFER
#define RT_USING_UTEST
#define UTEST_THR_STACK_SIZE 4096
#define UTEST_THR_PRIORITY 20
#define RT_USING_ADT
/* RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* Wiced WiFi */
/* IoT Cloud */
/* security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
/* tools packages */
/* system packages */
/* enhanced kernel services */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
/* peripheral libraries and drivers */
/* sensors drivers */
/* touch drivers */
/* Kendryte SDK */
/* AI packages */
/* Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
/* samples: kernel and components samples */
/* entertainment: terminal games and other interesting software packages */
/* Arduino libraries */
/* Projects */
/* Sensors */
/* Display */
/* Timing */
/* Data Processing */
/* Data Storage */
/* Communication */
/* Device Control */
/* Other */
/* Signal IO */
/* Uncategorized */
/* Hardware Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_UART
#define RT_USING_UART1
/* Board extended module Drivers */
#define PHYTIUM_ARCH_AARCH32
/* Standalone Setting */
#define TARGET_ARMV8_AARCH32
#define USE_AARCH64_L1_TO_AARCH32
/* Board Configuration */
#define TARGET_E2000D
#define TARGET_E2000
#define DEFAULT_DEBUG_PRINT_UART1
/* Components Configuration */
#define USE_GIC
#define ENABLE_GICV3
#define USE_SERIAL
/* Usart Configuration */
#define ENABLE_Pl011_UART
#define LOG_ERROR
#define USE_DEFAULT_INTERRUPT_CONFIG
#define INTERRUPT_ROLE_MASTER
#endif

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#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* RT-Thread Project Configuration */
/* RT-Thread Kernel */
#define RT_NAME_MAX 16
#define RT_USING_SMART
#define RT_USING_SMP
#define RT_CPUS_NR 4
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 4096
#define SYSTEM_THREAD_STACK_SIZE 4096
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 4096
/* kservice optimization */
#define RT_KSERVICE_USING_STDLIB
#define RT_KPRINTF_USING_LONGLONG
#define RT_DEBUG
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* Memory Management */
#define RT_PAGE_MAX_ORDER 11
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SMALL_MEM_AS_HEAP
#define RT_USING_HEAP
/* Kernel Device Object */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 256
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50001
#define RT_USING_CACHE
#define RT_USING_HW_ATOMIC
#define RT_USING_CPU_FFS
#define ARCH_MM_MMU
#define ARCH_ARM
#define ARCH_ARM_MMU
#define KERNEL_VADDR_START 0xc0000000
#define ARCH_ARM_CORTEX_A
#define RT_USING_GIC_V3
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 8192
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
/* DFS: device virtual file system */
#define RT_USING_DFS
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FD_MAX 16
#define RT_USING_DFS_V1
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_RAMFS
#define RT_USING_LWP
#define RT_LWP_MAX_NR 30
#define LWP_TASK_STACK_SIZE 16384
#define RT_CH_MSG_MAX_NR 1024
#define LWP_CONSOLE_INPUT_BUFFER_SIZE 1024
#define LWP_TID_MAX_NR 64
#define LWP_ENABLE_ASID
#define RT_LWP_SHM_MAX_NR 64
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 4096
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 1024
#define RT_USING_TTY
#define RT_USING_NULL
#define RT_USING_ZERO
#define RT_USING_RANDOM
#define RT_USING_RTC
/* Using USB */
/* C/C++ and POSIX layer */
#define RT_LIBC_DEFAULT_TIMEZONE 8
/* POSIX (Portable Operating System Interface) layer */
#define RT_USING_POSIX_FS
#define RT_USING_POSIX_DEVIO
#define RT_USING_POSIX_STDIO
#define RT_USING_POSIX_POLL
#define RT_USING_POSIX_SELECT
#define RT_USING_POSIX_TERMIOS
#define RT_USING_POSIX_AIO
#define RT_USING_POSIX_DELAY
#define RT_USING_POSIX_CLOCK
#define RT_USING_POSIX_TIMER
/* Interprocess Communication (IPC) */
#define RT_USING_POSIX_PIPE
#define RT_USING_POSIX_PIPE_SIZE 512
#define RT_USING_POSIX_MESSAGE_QUEUE
#define RT_USING_POSIX_MESSAGE_SEMAPHORE
/* Socket is in the 'Network' category */
/* Network */
/* Utilities */
#define RT_USING_RYM
#define YMODEM_USING_FILE_TRANSFER
#define RT_USING_UTEST
#define UTEST_THR_STACK_SIZE 4096
#define UTEST_THR_PRIORITY 20
#define RT_USING_ADT
/* RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* Wiced WiFi */
/* IoT Cloud */
/* security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
/* tools packages */
/* system packages */
/* enhanced kernel services */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
/* peripheral libraries and drivers */
/* sensors drivers */
/* touch drivers */
/* Kendryte SDK */
/* AI packages */
/* Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
/* samples: kernel and components samples */
/* entertainment: terminal games and other interesting software packages */
/* Arduino libraries */
/* Projects */
/* Sensors */
/* Display */
/* Timing */
/* Data Processing */
/* Data Storage */
/* Communication */
/* Device Control */
/* Other */
/* Signal IO */
/* Uncategorized */
/* Hardware Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_UART
#define RT_USING_UART1
/* Board extended module Drivers */
#define PHYTIUM_ARCH_AARCH32
/* Standalone Setting */
#define TARGET_ARMV8_AARCH32
#define USE_AARCH64_L1_TO_AARCH32
/* Board Configuration */
#define TARGET_E2000Q
#define TARGET_E2000
#define DEFAULT_DEBUG_PRINT_UART1
/* Components Configuration */
#define USE_GIC
#define ENABLE_GICV3
#define USE_SERIAL
/* Usart Configuration */
#define ENABLE_Pl011_UART
#define LOG_ERROR
#define USE_DEFAULT_INTERRUPT_CONFIG
#define INTERRUPT_ROLE_MASTER
#endif

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#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* RT-Thread Project Configuration */
/* RT-Thread Kernel */
#define RT_NAME_MAX 16
#define RT_USING_SMP
#define RT_CPUS_NR 4
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 4096
#define SYSTEM_THREAD_STACK_SIZE 4096
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 4096
/* kservice optimization */
#define RT_KSERVICE_USING_STDLIB
#define RT_KPRINTF_USING_LONGLONG
#define RT_DEBUG
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* Memory Management */
#define RT_PAGE_MAX_ORDER 11
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SMALL_MEM_AS_HEAP
#define RT_USING_HEAP
/* Kernel Device Object */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 256
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50001
#define RT_USING_CACHE
#define RT_USING_HW_ATOMIC
#define RT_USING_CPU_FFS
#define ARCH_MM_MMU
#define ARCH_ARM
#define ARCH_ARM_MMU
#define ARCH_ARM_CORTEX_A
#define RT_USING_GIC_V3
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 8192
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
/* DFS: device virtual file system */
#define RT_USING_DFS
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FD_MAX 16
#define RT_USING_DFS_V1
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_RAMFS
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 4096
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 1024
#define RT_USING_NULL
#define RT_USING_ZERO
#define RT_USING_RANDOM
#define RT_USING_RTC
/* Using USB */
/* C/C++ and POSIX layer */
#define RT_LIBC_DEFAULT_TIMEZONE 8
/* POSIX (Portable Operating System Interface) layer */
#define RT_USING_POSIX_FS
#define RT_USING_POSIX_DEVIO
#define RT_USING_POSIX_STDIO
#define RT_USING_POSIX_POLL
#define RT_USING_POSIX_SELECT
#define RT_USING_POSIX_TERMIOS
#define RT_USING_POSIX_AIO
#define RT_USING_POSIX_DELAY
#define RT_USING_POSIX_CLOCK
#define RT_USING_POSIX_TIMER
/* Interprocess Communication (IPC) */
#define RT_USING_POSIX_PIPE
#define RT_USING_POSIX_PIPE_SIZE 512
#define RT_USING_POSIX_MESSAGE_QUEUE
#define RT_USING_POSIX_MESSAGE_SEMAPHORE
/* Socket is in the 'Network' category */
/* Network */
/* Utilities */
#define RT_USING_RYM
#define YMODEM_USING_FILE_TRANSFER
#define RT_USING_UTEST
#define UTEST_THR_STACK_SIZE 4096
#define UTEST_THR_PRIORITY 20
#define RT_USING_ADT
/* RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* Wiced WiFi */
/* IoT Cloud */
/* security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
/* tools packages */
/* system packages */
/* enhanced kernel services */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
/* peripheral libraries and drivers */
/* sensors drivers */
/* touch drivers */
/* Kendryte SDK */
/* AI packages */
/* Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
/* samples: kernel and components samples */
/* entertainment: terminal games and other interesting software packages */
/* Arduino libraries */
/* Projects */
/* Sensors */
/* Display */
/* Timing */
/* Data Processing */
/* Data Storage */
/* Communication */
/* Device Control */
/* Other */
/* Signal IO */
/* Uncategorized */
/* Hardware Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_UART
#define RT_USING_UART1
/* Board extended module Drivers */
#define PHYTIUM_ARCH_AARCH32
/* Standalone Setting */
#define TARGET_ARMV8_AARCH32
#define USE_AARCH64_L1_TO_AARCH32
/* Board Configuration */
#define TARGET_E2000Q
#define TARGET_E2000
#define DEFAULT_DEBUG_PRINT_UART1
/* Components Configuration */
#define USE_GIC
#define ENABLE_GICV3
#define USE_SERIAL
/* Usart Configuration */
#define ENABLE_Pl011_UART
#define LOG_ERROR
#define USE_DEFAULT_INTERRUPT_CONFIG
#define INTERRUPT_ROLE_MASTER
#endif

15
bsp/phytium/aarch32/export_project.py
View File

@ -1,3 +1,18 @@
#!/usr/bin/env python
# -*- coding: utf-8 -*-
#
# Copyright (c) 2022, RT-Thread Development Team
#
# SPDX-License-Identifier: Apache-2.0
#
# Email: opensource_embedded@phytium.com.cn
#
#
# Change Logs:
# Date Author Notes
# 2022-11-15 zhugengyu The first version
#
import os
import shutil
import argparse

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18
bsp/phytium/aarch32/link.lds
View File

@ -5,18 +5,25 @@ ENTRY(_boot)
SECTIONS
{
. = 0x80100000;
. = 0x80080000;
.text :
{
*(.boot)
. = ALIGN(64);
*(.vectors)
*(.text)
*(.text.*)
/* section information for utest */
. = ALIGN(4);
__rt_utest_tc_tab_start = .;
KEEP(*(UtestTcTab))
__rt_utest_tc_tab_end = .;
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
@ -42,6 +49,13 @@ SECTIONS
} =0
__text_end = .;
.ARM.exidx :
{
__exidx_start = .;
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
__exidx_end = .;
}
__rodata_start = .;
.rodata : { *(.rodata) *(.rodata.*) }
__rodata_end = .;

120
bsp/phytium/aarch32/link_smart.lds Normal file
View File

@ -0,0 +1,120 @@
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_boot)
SECTIONS
{
/* . = 0x80080000; */
. = 0xc0080000;
.text :
{
*(.boot)
. = ALIGN(64);
*(.vectors)
*(.text)
*(.text.*)
/* section information for utest */
. = ALIGN(4);
__rt_utest_tc_tab_start = .;
KEEP(*(UtestTcTab))
__rt_utest_tc_tab_end = .;
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
/* section information for modules */
. = ALIGN(4);
__rtmsymtab_start = .;
KEEP(*(RTMSymTab))
__rtmsymtab_end = .;
/* section information for initialization */
. = ALIGN(4);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
} =0
__text_end = .;
.ARM.exidx :
{
__exidx_start = .;
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
__exidx_end = .;
}
__rodata_start = .;
.rodata : { *(.rodata) *(.rodata.*) }
__rodata_end = .;
. = ALIGN(4);
.ctors :
{
PROVIDE(__ctors_start__ = .);
/* new GCC version uses .init_array */
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE(__ctors_end__ = .);
}
.dtors :
{
PROVIDE(__dtors_start__ = .);
KEEP(*(SORT(.dtors.*)))
KEEP(*(.dtors))
PROVIDE(__dtors_end__ = .);
}
. = ALIGN(16 * 1024);
.l1_page_table :
{
__l1_page_table_start = .;
. += 16K;
}
. = ALIGN(8);
__data_start = .;
.data :
{
*(.data)
*(.data.*)
}
__data_end = .;
. = ALIGN(8);
__bss_start = .;
.bss :
{
*(.bss)
*(.bss.*)
*(COMMON)
. = ALIGN(4);
}
. = ALIGN(4);
__bss_end = .;
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
_end = .;
}

78
bsp/phytium/aarch32/makefile Normal file
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@ -0,0 +1,78 @@
.PHONY: debug boot all clean menuconfig
CC = $(RTT_EXEC_PATH)/$(RTT_CC_PREFIX)gcc
CXX = $(RTT_EXEC_PATH)/$(RTT_CC_PREFIX)g++
CPP = $(RTT_EXEC_PATH)/$(RTT_CC_PREFIX)gcc -E -P -x c
STRIP = $(RTT_EXEC_PATH)/$(RTT_CC_PREFIX)strip --strip-unneeded
OBJCOPY = $(RTT_EXEC_PATH)/$(RTT_CC_PREFIX)objcopy
OBJDUMP = $(RTT_EXEC_PATH)/$(RTT_CC_PREFIX)objdump
LD = $(RTT_EXEC_PATH)/$(RTT_CC_PREFIX)ld
AR = $(RTT_EXEC_PATH)/$(RTT_CC_PREFIX)ar rcs
NM = $(RTT_EXEC_PATH)/$(RTT_CC_PREFIX)nm
OD = $(RTT_EXEC_PATH)/$(RTT_CC_PREFIX)objdump
include .config
ifdef CONFIG_TARGET_E2000Q
RTCONFIG := e2000q
endif
ifdef CONFIG_TARGET_E2000D
RTCONFIG := e2000d
endif
ifdef CONFIG_RT_USING_SMART
RTCONFIG := $(RTCONFIG)_rtsmart
else
RTCONFIG := $(RTCONFIG)_rtthread
endif
boot:
make all
cp rtthread_a32.elf /mnt/d/tftboot
cp rtthread_a32.bin /mnt/d/tftboot
debug:
@$(OD) -D rtthread_a32.elf > rtthread_a32.asm
@$(OD) -S rtthread_a32.elf > rtthread_a32.dis
all:
@echo "Build started..."
scons -j1024
clean:
@echo "Cleaning..."
scons -c
menuconfig:
@echo "Running menuconfig..."
scons --menuconfig
saveconfig:
@echo "Save configs to" ./configs/$(RTCONFIG)
@cp ./.config ./configs/$(RTCONFIG) -f
@cp ./rtconfig.h ./configs/$(RTCONFIG).h -f
load_e2000q_rtsmart:
@echo "Load configs from ./configs/e2000q_rtsmart"
@cp ./configs/e2000q_rtsmart ./.config -f
@cp ./configs/e2000q_rtsmart.h ./rtconfig.h -f
@scons -c
load_e2000q_rtthread:
@echo "Load configs from ./configs/e2000q_rtthread"
@cp ./configs/e2000q_rtthread ./.config -f
@cp ./configs/e2000q_rtthread.h ./rtconfig.h -f
@scons -c
load_e2000d_rtsmart:
@echo "Load configs from ./configs/e2000d_rtsmart"
@cp ./configs/e2000d_rtsmart ./.config -f
@cp ./configs/e2000d_rtsmart.h ./rtconfig.h -f
@scons -c
load_e2000d_rtthread:
@echo "Load configs from ./configs/e2000d_rtthread"
@cp ./configs/e2000d_rtthread ./.config -f
@cp ./configs/e2000d_rtthread.h ./rtconfig.h -f
scons -c

71
bsp/phytium/aarch32/rtconfig.h
View File

@ -6,10 +6,11 @@
/* RT-Thread Kernel */
#define RT_NAME_MAX 8
#define RT_NAME_MAX 16
#define RT_USING_SMART
#define RT_USING_SMP
#define RT_CPUS_NR 4
#define RT_ALIGN_SIZE 8
#define RT_CPUS_NR 2
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
@ -18,15 +19,16 @@
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 256
#define SYSTEM_THREAD_STACK_SIZE 256
#define IDLE_THREAD_STACK_SIZE 4096
#define SYSTEM_THREAD_STACK_SIZE 4096
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 512
#define RT_TIMER_THREAD_STACK_SIZE 4096
/* kservice optimization */
#define RT_KSERVICE_USING_STDLIB
#define RT_KPRINTF_USING_LONGLONG
#define RT_DEBUG
/* Inter-Thread communication */
@ -42,6 +44,8 @@
#define RT_PAGE_MAX_ORDER 11
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SMALL_MEM_AS_HEAP
#define RT_USING_HEAP
@ -49,15 +53,16 @@
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLEBUF_SIZE 256
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50000
#define RT_VER_NUM 0x50001
#define RT_USING_CACHE
#define RT_USING_HW_ATOMIC
#define RT_USING_CPU_FFS
#define ARCH_MM_MMU
#define ARCH_ARM
#define ARCH_ARM_MMU
#define KERNEL_VADDR_START 0xc0000000
#define ARCH_ARM_CORTEX_A
#define RT_USING_GIC_V3
@ -65,7 +70,7 @@
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 2048
#define RT_MAIN_THREAD_STACK_SIZE 8192
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
@ -80,22 +85,43 @@
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
/* DFS: device virtual file system */
#define RT_USING_DFS
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FD_MAX 16
#define RT_USING_DFS_V1
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define DFS_FD_MAX 16
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_RAMFS
#define RT_USING_LWP
#define RT_LWP_MAX_NR 30
#define LWP_TASK_STACK_SIZE 16384
#define RT_CH_MSG_MAX_NR 1024
#define LWP_CONSOLE_INPUT_BUFFER_SIZE 1024
#define LWP_TID_MAX_NR 64
#define LWP_ENABLE_ASID
#define RT_LWP_SHM_MAX_NR 64
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 4096
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_PIN
#define RT_SERIAL_RB_BUFSZ 1024
#define RT_USING_TTY
#define RT_USING_NULL
#define RT_USING_ZERO
#define RT_USING_RANDOM
#define RT_USING_RTC
/* Using USB */
@ -106,9 +132,23 @@
/* POSIX (Portable Operating System Interface) layer */
#define RT_USING_POSIX_FS
#define RT_USING_POSIX_DEVIO
#define RT_USING_POSIX_STDIO
#define RT_USING_POSIX_POLL
#define RT_USING_POSIX_SELECT
#define RT_USING_POSIX_TERMIOS
#define RT_USING_POSIX_AIO
#define RT_USING_POSIX_DELAY
#define RT_USING_POSIX_CLOCK
#define RT_USING_POSIX_TIMER
/* Interprocess Communication (IPC) */
#define RT_USING_POSIX_PIPE
#define RT_USING_POSIX_PIPE_SIZE 512
#define RT_USING_POSIX_MESSAGE_QUEUE
#define RT_USING_POSIX_MESSAGE_SEMAPHORE
/* Socket is in the 'Network' category */
@ -118,6 +158,11 @@
/* Utilities */
#define RT_USING_RYM
#define YMODEM_USING_FILE_TRANSFER
#define RT_USING_UTEST
#define UTEST_THR_STACK_SIZE 4096
#define UTEST_THR_PRIORITY 20
#define RT_USING_ADT
/* RT-Thread Utestcases */
@ -254,7 +299,7 @@
/* Board Configuration */
#define TARGET_E2000Q
#define TARGET_E2000D
#define TARGET_E2000
#define DEFAULT_DEBUG_PRINT_UART1

88
bsp/phytium/aarch32/rtconfig.py
View File

@ -2,67 +2,53 @@ import os
import rtconfig
# toolchains options
ARCH='arm'
CPU='cortex-a'
CROSS_TOOL='gcc'
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = r'../../..'
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
# only support GNU GCC compiler.
ARCH ='arm'
CPU ='cortex-a'
CROSS_TOOL = 'gcc'
PLATFORM = 'gcc'
EXEC_PATH = r'/usr/lib/arm-none-eabi/bin'
if os.getenv('AARCH32_CROSS_PATH'):
EXEC_PATH = os.getenv('AARCH32_CROSS_PATH')
print('EXEC_PATH = {}'.format(EXEC_PATH))
else:
print('AARCH32_CROSS_PATH not found')
EXEC_PATH = os.getenv('RTT_EXEC_PATH') or r'/usr/bin'
BUILD = 'debug'
BUILD = 'debug'
LINK_SCRIPT = 'link.lds'
LIBPATH = EXEC_PATH + r'/../lib'
if PLATFORM == 'gcc':
# toolchains
PREFIX = 'arm-none-eabi-'
CC = PREFIX + 'gcc'
CXX = PREFIX + 'g++'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
LINK = PREFIX + 'gcc'
PREFIX = os.getenv('RTT_CC_PREFIX') or 'arm-none-eabi-'
CC = PREFIX + 'gcc'
CXX = PREFIX + 'g++'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
LINK = PREFIX + 'gcc'
TARGET_EXT = 'elf'
SIZE = PREFIX + 'size'
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
STRIP = PREFIX + 'strip'
OBJCPY = PREFIX + 'objcopy'
STRIP = PREFIX + 'strip'
CFPFLAGS = ' -msoft-float'
AFPFLAGS = ' -mfloat-abi=softfp -mfpu=neon'
DEVICE = ' -march=armv8-a -ftree-vectorize -ffast-math -funwind-tables -fno-strict-aliasing'
DEVICE = ' -g -DGUEST -ffreestanding -Wextra -g -mfpu=crypto-neon-fp-armv8 -mfloat-abi=softfp -march=armv8-a -fdiagnostics-color=always'
# CFLAGS = DEVICE + ' -Wall'
CFLAGS = DEVICE
AFLAGS = ' -c'+ DEVICE + ' -fsingle-precision-constant -fno-builtin -x assembler-with-cpp -D__ASSEMBLY__'
LINK_SCRIPT = 'link.lds'
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread_a32.map,-cref,-u,system_vectors'+\
' -T %s' % LINK_SCRIPT
CPATH = ''
LPATH = LIBPATH
# generate debug info in all cases
AFLAGS += ' -gdwarf-2'
CFLAGS += ' -g -gdwarf-2'
CXXFLAGS= DEVICE + CFPFLAGS + ' -Wall -fdiagnostics-color=always'
CFLAGS = DEVICE + CFPFLAGS + ' -Wall -Wno-cpp -std=gnu99 -D_POSIX_SOURCE -fdiagnostics-color=always'
AFLAGS = DEVICE + ' -c' + AFPFLAGS + ' -x assembler-with-cpp'
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread_a32.map,-cref,-u,system_vectors -T '+ LINK_SCRIPT + ' -lsupc++ -lgcc -static'
CPATH = ''
LPATH = ''
if BUILD == 'debug':
CFLAGS += ' -O0'
CFLAGS += ' -O0 -gdwarf-2'
CXXFLAGS += ' -O0 -gdwarf-2'
AFLAGS += ' -gdwarf-2'
else:
CFLAGS += ' -O2'
CFLAGS += ' -Os'
CXXFLAGS += ' -Os'
CXXFLAGS += ' -Woverloaded-virtual -fno-rtti'
CXXFLAGS = CFLAGS
M_CFLAGS = CFLAGS + ' -mlong-calls -fPIC '
M_CXXFLAGS = CXXFLAGS + ' -mlong-calls -fPIC'
M_LFLAGS = DEVICE + CXXFLAGS + ' -Wl,--gc-sections,-z,max-page-size=0x4' +\
' -shared -fPIC -nostartfiles -nostdlib -static-libgcc'
M_POST_ACTION = STRIP + ' -R .hash $TARGET\n' + SIZE + ' $TARGET \n'
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread_a32.bin\n' +\
SIZE + ' $TARGET \n'
DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtthread_a32.asm\n'
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread_a32.bin\n' + SIZE + ' $TARGET \n'

75
bsp/phytium/aarch32/sdkconfig.h
View File

@ -1,75 +0,0 @@
/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: sdkconfig.h
* Date: 2022-10-13 15:53:46
* LastEditTime: 2022-10-13 15:53:46
* Description: This file is for
*
* Modify History:
* Ver Who Date Changes
* ----- ------ -------- --------------------------------------
*/
#ifndef SDK_CONFIG_H__
#define SDK_CONFIG_H__
#include "rtconfig.h"
/* arch */
#if defined(TARGET_ARMV8_AARCH32)
#define CONFIG_TARGET_ARMV8_AARCH32
#endif
#if defined(USE_AARCH64_L1_TO_AARCH32)
#define CONFIG_USE_AARCH64_L1_TO_AARCH32
#endif
/* board */
/* E2000 */
#if defined(TARGET_E2000)
#define CONFIG_TARGET_E2000
#endif
/* debug */
#ifdef LOG_VERBOS
#define CONFIG_LOG_VERBOS
#endif
#ifdef LOG_ERROR
#define CONFIG_LOG_ERROR
#endif
#ifdef LOG_WARN
#define CONFIG_LOG_WARN
#endif
#ifdef LOG_INFO
#define CONFIG_LOG_INFO
#endif
#ifdef LOG_DEBUG
#define CONFIG_LOG_DEBUG
#endif
#ifdef BOOTUP_DEBUG_PRINTS
#define CONFIG_BOOTUP_DEBUG_PRINTS
#endif
#endif

116
bsp/phytium/aarch64/.config
View File

@ -10,20 +10,20 @@ CONFIG_RT_NAME_MAX=16
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMART is not set
CONFIG_RT_USING_SMP=y
CONFIG_RT_CPUS_NR=4
CONFIG_RT_ALIGN_SIZE=8
CONFIG_RT_CPUS_NR=2
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=100
CONFIG_RT_TICK_PER_SECOND=1000
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
CONFIG_RT_HOOK_USING_FUNC_PTR=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=4096
CONFIG_SYSTEM_THREAD_STACK_SIZE=4096
CONFIG_IDLE_THREAD_STACK_SIZE=40960
CONFIG_SYSTEM_THREAD_STACK_SIZE=40960
CONFIG_RT_USING_TIMER_SOFT=y
CONFIG_RT_TIMER_THREAD_PRIO=4
CONFIG_RT_TIMER_THREAD_STACK_SIZE=4096
@ -47,6 +47,7 @@ CONFIG_RT_DEBUG=y
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_PAGE_LEAK is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
#
@ -66,7 +67,9 @@ CONFIG_RT_PAGE_MAX_ORDER=11
CONFIG_RT_USING_MEMPOOL=y
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
# CONFIG_RT_USING_MEMHEAP is not set
CONFIG_RT_USING_MEMHEAP=y
CONFIG_RT_MEMHEAP_FAST_MODE=y
# CONFIG_RT_MEMHEAP_BEST_MODE is not set
CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
# CONFIG_RT_USING_SLAB_AS_HEAP is not set
@ -86,12 +89,12 @@ CONFIG_RT_USING_DEVICE=y
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
CONFIG_RT_VER_NUM=0x50000
CONFIG_RT_VER_NUM=0x50001
# CONFIG_RT_USING_STDC_ATOMIC is not set
CONFIG_ARCH_CPU_64BIT=y
CONFIG_RT_USING_CACHE=y
CONFIG_RT_USING_HW_ATOMIC=y
# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE=y
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
# CONFIG_RT_USING_CPU_FFS is not set
CONFIG_ARCH_MM_MMU=y
@ -104,7 +107,7 @@ CONFIG_ARCH_ARMV8=y
#
CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=4096
CONFIG_RT_MAIN_THREAD_STACK_SIZE=8192
CONFIG_RT_MAIN_THREAD_PRIORITY=10
# CONFIG_RT_USING_LEGACY is not set
CONFIG_RT_USING_MSH=y
@ -122,18 +125,24 @@ CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_ARG_MAX=10
#
# DFS: device virtual file system
#
CONFIG_RT_USING_DFS=y
CONFIG_DFS_USING_POSIX=y
CONFIG_DFS_USING_WORKDIR=y
# CONFIG_RT_USING_DFS_MNTTABLE is not set
CONFIG_DFS_FD_MAX=16
CONFIG_RT_USING_DFS_V1=y
# CONFIG_RT_USING_DFS_V2 is not set
CONFIG_DFS_FILESYSTEMS_MAX=4
CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
CONFIG_DFS_FD_MAX=16
# CONFIG_RT_USING_DFS_MNTTABLE is not set
# CONFIG_RT_USING_DFS_ELMFAT is not set
# CONFIG_RT_USING_DFS_DEVFS is not set
CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_CROMFS is not set
# CONFIG_RT_USING_DFS_RAMFS is not set
CONFIG_RT_USING_DFS_RAMFS=y
# CONFIG_RT_USING_DFS_TMPFS is not set
# CONFIG_RT_USING_FAL is not set
@ -155,18 +164,20 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
# CONFIG_RT_USING_PHY is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_PIN is not set
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_NULL is not set
# CONFIG_RT_USING_ZERO is not set
# CONFIG_RT_USING_RANDOM is not set
CONFIG_RT_USING_NULL=y
CONFIG_RT_USING_ZERO=y
CONFIG_RT_USING_RANDOM=y
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_FDT is not set
# CONFIG_RT_USING_RTC is not set
CONFIG_RT_USING_RTC=y
# CONFIG_RT_USING_ALARM is not set
# CONFIG_RT_USING_SOFT_RTC is not set
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
@ -196,10 +207,18 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
#
# POSIX (Portable Operating System Interface) layer
#
# CONFIG_RT_USING_POSIX_FS is not set
# CONFIG_RT_USING_POSIX_DELAY is not set
# CONFIG_RT_USING_POSIX_CLOCK is not set
# CONFIG_RT_USING_POSIX_TIMER is not set
CONFIG_RT_USING_POSIX_FS=y
CONFIG_RT_USING_POSIX_DEVIO=y
CONFIG_RT_USING_POSIX_STDIO=y
# CONFIG_RT_USING_POSIX_POLL is not set
# CONFIG_RT_USING_POSIX_SELECT is not set
# CONFIG_RT_USING_POSIX_SOCKET is not set
CONFIG_RT_USING_POSIX_TERMIOS=y
# CONFIG_RT_USING_POSIX_AIO is not set
# CONFIG_RT_USING_POSIX_MMAN is not set
CONFIG_RT_USING_POSIX_DELAY=y
CONFIG_RT_USING_POSIX_CLOCK=y
CONFIG_RT_USING_POSIX_TIMER=y
# CONFIG_RT_USING_PTHREADS is not set
# CONFIG_RT_USING_MODULE is not set
@ -226,7 +245,9 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
#
# Utilities
#
# CONFIG_RT_USING_RYM is not set
CONFIG_RT_USING_RYM=y
# CONFIG_YMODEM_USING_CRC_TABLE is not set
CONFIG_YMODEM_USING_FILE_TRANSFER=y
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
# CONFIG_RT_USING_VAR_EXPORT is not set
@ -624,7 +645,6 @@ CONFIG_RT_USING_ADT=y
# CONFIG_PKG_USING_LKDGUI is not set
# CONFIG_PKG_USING_NRF5X_SDK is not set
# CONFIG_PKG_USING_NRFX is not set
# CONFIG_PKG_USING_WM_LIBRARIES is not set
#
# Kendryte SDK
@ -682,7 +702,6 @@ CONFIG_RT_USING_ADT=y
# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
# CONFIG_PKG_USING_BL_MCU_SDK is not set
# CONFIG_PKG_USING_SOFT_SERIAL is not set
# CONFIG_PKG_USING_MB85RS16 is not set
# CONFIG_PKG_USING_RFM300 is not set
@ -721,7 +740,31 @@ CONFIG_RT_USING_ADT=y
#
# samples: kernel and components samples
#
# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
CONFIG_PKG_USING_KERNEL_SAMPLES=y
CONFIG_PKG_KERNEL_SAMPLES_PATH="/packages/misc/samples/kernel_samples"
# CONFIG_PKG_USING_KERNEL_SAMPLES_V030 is not set
# CONFIG_PKG_USING_KERNEL_SAMPLES_V040 is not set
CONFIG_PKG_USING_KERNEL_SAMPLES_LATEST_VERSION=y
CONFIG_PKG_KERNEL_SAMPLES_VER="latest"
CONFIG_PKG_USING_KERNEL_SAMPLES_EN=y
# CONFIG_PKG_USING_KERNEL_SAMPLES_ZH is not set
# CONFIG_KERNEL_SAMPLES_USING_THREAD is not set
# CONFIG_KERNEL_SAMPLES_USING_SEMAPHORE is not set
# CONFIG_KERNEL_SAMPLES_USING_MUTEX is not set
# CONFIG_KERNEL_SAMPLES_USING_MAILBOX is not set
# CONFIG_KERNEL_SAMPLES_USING_EVENT is not set
# CONFIG_KERNEL_SAMPLES_USING_MESSAGEQUEUE is not set
# CONFIG_KERNEL_SAMPLES_USING_TIMER is not set
# CONFIG_KERNEL_SAMPLES_USING_HEAP is not set
# CONFIG_KERNEL_SAMPLES_USING_MEMHEAP is not set
# CONFIG_KERNEL_SAMPLES_USING_MEMPOOL is not set
# CONFIG_KERNEL_SAMPLES_USING_IDLEHOOK is not set
# CONFIG_KERNEL_SAMPLES_USING_SIGNAL is not set
# CONFIG_KERNEL_SAMPLES_USING_INTERRUPT is not set
# CONFIG_KERNEL_SAMPLES_USING_PRI_INVERSION is not set
# CONFIG_KERNEL_SAMPLES_USING_TIME_SLICE is not set
# CONFIG_KERNEL_SAMPLES_USING_SCHEDULER_HOOK is not set
# CONFIG_KERNEL_SAMPLES_USING_PRODUCER_CONSUMER is not set
# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
@ -997,6 +1040,9 @@ CONFIG_RT_USING_ADT=y
CONFIG_BSP_USING_UART=y
CONFIG_RT_USING_UART1=y
# CONFIG_RT_USING_UART0 is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_CAN is not set
# CONFIG_BSP_USING_QSPI is not set
#
# Board extended module Drivers
@ -1004,6 +1050,7 @@ CONFIG_RT_USING_UART1=y
CONFIG_BSP_USING_GIC=y
CONFIG_BSP_USING_GICV3=y
CONFIG_PHYTIUM_ARCH_AARCH64=y
CONFIG_ARM_SPI_BIND_CPU_ID=0
#
# Standalone Setting
@ -1015,8 +1062,8 @@ CONFIG_TARGET_ARMV8_AARCH64=y
#
# CONFIG_TARGET_F2000_4 is not set
# CONFIG_TARGET_D2000 is not set
CONFIG_TARGET_E2000Q=y
# CONFIG_TARGET_E2000D is not set
# CONFIG_TARGET_E2000Q is not set
CONFIG_TARGET_E2000D=y
# CONFIG_TARGET_E2000S is not set
CONFIG_TARGET_E2000=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
@ -1026,8 +1073,14 @@ CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
#
# Components Configuration
#
# CONFIG_USE_SPI is not set
# CONFIG_USE_QSPI is not set
CONFIG_USE_SPI=y
CONFIG_USE_FSPIM=y
CONFIG_USE_QSPI=y
#
# Qspi Configuration
#
CONFIG_USE_FQSPI=y
# CONFIG_USE_GIC is not set
CONFIG_USE_SERIAL=y
@ -1052,6 +1105,8 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_ADC is not set
# CONFIG_USE_PWM is not set
# CONFIG_USE_IPC is not set
# CONFIG_USE_MEDIA is not set
# CONFIG_USE_SCMI_MHU is not set
# CONFIG_LOG_VERBOS is not set
# CONFIG_LOG_DEBUG is not set
# CONFIG_LOG_INFO is not set
@ -1060,4 +1115,5 @@ CONFIG_LOG_ERROR=y
# CONFIG_LOG_NONE is not set
# CONFIG_USE_DEFAULT_INTERRUPT_CONFIG is not set
# CONFIG_LOG_EXTRA_INFO is not set
# CONFIG_LOG_DISPALY_CORE_NUM is not set
# CONFIG_BOOTUP_DEBUG_PRINTS is not set

1116
bsp/phytium/aarch64/.configs Normal file
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14
bsp/phytium/aarch64/Kconfig
View File

@ -38,7 +38,21 @@ config PHYTIUM_ARCH_AARCH64
select RT_USING_USER_MAIN
select ARCH_CPU_64BIT
select TARGET_ARMV8_AARCH64
select ARCH_ARM_BOOTWITH_FLUSH_CACHE
default y
if TARGET_E2000Q
config ARM_SPI_BIND_CPU_ID
int
default 2
endif
if TARGET_E2000D
config ARM_SPI_BIND_CPU_ID
int
default 0
endif
menu "Standalone Setting"
config TARGET_ARMV8_AARCH64

117
bsp/phytium/aarch64/README.md
View File

@ -1,31 +1,52 @@
<!--
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: README.md
* Date: 2022-10-17 15:16:12
* LastEditTime: 2022-10-17 15:16:12
* Description: This file is for
*
* Modify History:
* Ver Who Date Changes
* ----- ------ -------- --------------------------------------
-->
# AARCH64 工作模式使用
- 当开发者需要基于 Phytium 系列芯片进行开发时，可以从以下几个步骤出发配置芯片
## 1. 如何选择芯片
## 1. 准备编译环境
- 在 aarch64 目录下创建 tools 目录，后续用于存放 RT-Thread 编译工具链
```sh
cd ./aarch64
mkdir tools
```
- 在 tools 目录下下载两个 python 脚本，get_toolchain.py 和 ci.py，下载完后给两个脚本添加执行权限
```shell
cd ./tools
wget https://gitee.com/rtthread/ART-Pi-smart/raw/master/tools/get_toolchain.py
wget https://gitee.com/rtthread/ART-Pi-smart/raw/master/tools/ci.py
chmod +x get_toolchain.py ci.py
```
- 然后运行 get_toolchain.py 脚本，拉取 aarch64 交叉编译链`aarch64-linux-musleabi_for_x86_64-pc-linux-gnu`
```shell
python3 ./get_toolchain.py aarch64
```
> RT-Thread 5.0 后必须使用这个带 musl-libc 的编译链，不能使用`aarch64-none-elf`
- 在 aarch64 目录下下载脚本 smart_env.sh ，然后运行脚本生效环境变量
```shell
cd ./aarch64
wget https://gitee.com/rtthread/ART-Pi-smart/raw/master/smart-env.sh
source ./smart-env.sh aarch64
```
- 如下所示是 aarch64 编译相关的环境变量，运行 scons 前要确保环境变量设置正确
![aarch64_env](./figures/aarch64_env.png)
## NOTE
- 请使用ubuntu20.04 开发环境进行上述操作，其他开发环境没有进行测试
## 2. 如何选择芯片
- 以 E2000Q RT-Smart为例，Linux 环境下，运行 make load_e2000q_rtsmart 加载默认的 rtconfig, 然后输入下列命令，进入 menuconfig 进一步配置，
```shell
scons --menuconfig
@ -40,8 +61,7 @@ Standalone Setting > Board Configuration > Chip
![](./figures/chip_select.png)
![](./figures/phytium_cpu_select.png)
## 2. 如何选择驱动
## 3. 如何选择驱动
```shell
scons --menuconfig
@ -55,9 +75,17 @@ Hardware Drivers Config > On-chip Peripheral Drivers
![](./figures/select_driver.png)
## 4. 如何切换至RT-Thread Smart 工作模式
## 3. 开启SDK中内部调试信息
```shell
scons --menuconfig
```
![1682474861110](./figures/1682474861110.png)
开发者通过以上配置开启RT-Thread Smart 功能
## 5. 开启SDK中内部调试信息
```shell
scons --menuconfig
@ -67,9 +95,7 @@ Hardware Drivers Config > On-chip Peripheral Drivers
![](./figures/select_debug_info.png)
## 4. 编译程序
## 6. 编译程序
```shell
scons -c
@ -84,18 +110,38 @@ rtthread_a64.elf
rtthread_a64.map
```
## 5. 打包导出工程源代码
## 7. 启动镜像程序
- 可以用串口通过 XMODEM 协议将 bin/elf 文件上传到开发板，然后启动，
- 首先在 Phytium 开发板上输入，上传 bin 文件
```
loadx 80080000
```
![](./figures/ymodem_upload.png)
- 加载 bin 文件完成后，输入下列命令启动
```
go 80080000
```
> RT-Smart 模式下，64 位不能用 bootelf 启动 elf 文件
## 8. 打包导出工程源代码
- 指定工程名和路径，打包RT-Thread内核和Phytium BSP代码，可以导出一个工程工程
```
python ./export_project.py -n=phytium-a64 -o=D:/proj/rt-thread-e2000/phytium-a64
```
![](./figures/export_project.png)
- 进入打包工程的目录，修改工程根目录 Kconfig 中的路径 BSP_DIR 和 STANDALONE_DIR
- 进入打包工程的目录，修改工程根目录 Kconfig 中的路径 BSP_DIR 和 STANDALONE_DIR
> env 环境中的 menuconfig 不会调用 SConstruct 修改路径环境变量，因此需要手动修改路径
```
@ -112,10 +158,9 @@ config STANDALONE_DIR
- 输入 menuconfig 和 scons 完成编译
## 9. 将工程导入 RT-Studio
## 6. 将工程导入 RT-Studio
- 在 RT-Studio 使用功能`RT-Thread Bsp 到工作空间`，导入 5. 中导出的 BSP 工程
- 在 RT-Studio 使用功能 `RT-Thread Bsp 到工作空间`，导入 5. 中导出的 BSP 工程
- 设置 BSP 工程的交叉编译链后进行后续开发
![](./figures/import_project.png)
![](./figures/import_project.png)

4
bsp/phytium/aarch64/SConstruct
View File

@ -53,6 +53,10 @@ if not IS_EXPORTED: # if project is not exported, libraries and board need to ma
# include board
objs.extend(SConscript(os.path.join(BSP_ROOT + '/board', 'SConscript')))
if GetDepend('RT_USING_SMART'):
# use smart link.lds
env['LINKFLAGS'] = env['LINKFLAGS'].replace('link.lds', 'link_smart.lds')
# make a building
DoBuilding(TARGET, objs)

2
bsp/phytium/aarch64/applications/SConscript
View File

@ -3,7 +3,7 @@ Import('rtconfig')
from building import *
cwd = os.path.join(str(Dir('#')), 'applications')
src = Glob('*.c')
src = Glob('*.c')
CPPPATH = [cwd, str(Dir('#'))]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)

6
bsp/phytium/aarch64/applications/main.c
View File

@ -30,7 +30,7 @@ static char *core_thread_name[8] =
"core6_test",
"core7_test"
};
static rt_uint8_t core_stack[RT_CPUS_NR][1024];
static rt_uint8_t core_stack[RT_CPUS_NR][4096];
static void demo_core_thread(void *parameter)
{
@ -41,7 +41,7 @@ static void demo_core_thread(void *parameter)
level = rt_cpus_lock();
rt_kprintf("Hi, core%d \r\n", rt_hw_cpu_id());
rt_cpus_unlock(level);
rt_thread_mdelay(2000000);
rt_thread_mdelay(200000);
}
}
@ -57,7 +57,7 @@ void demo_core(void)
demo_core_thread,
RT_NULL,
&core_stack[i],
1024,
4096,
20,
32);

63
bsp/phytium/aarch64/applications/mnt.c Normal file
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@ -0,0 +1,63 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Email: opensource_embedded@phytium.com.cn
*
* Change Logs:
* Date Author Notes
* 2023-04-27 huanghe first version
*
*/
#include <rtthread.h>
#ifdef RT_USING_DFS_RAMFS
#include <dfs_fs.h>
extern struct dfs_ramfs *dfs_ramfs_create(rt_uint8_t *pool, rt_size_t size);
int mnt_init(void)
{
rt_uint8_t *pool = RT_NULL;
rt_size_t size = 8*1024*1024;
pool = rt_malloc(size);
if (pool == RT_NULL)
return 0;
if (dfs_mount(RT_NULL, "/", "ram", 0, (const void *)dfs_ramfs_create(pool, size)) == 0)
rt_kprintf("RAM file system initializated!\n");
else
rt_kprintf("RAM file system initializate failed!\n");
return 0;
}
INIT_ENV_EXPORT(mnt_init);
#endif
#ifdef BSP_USING_SDCARD_FATFS
#include <dfs_fs.h>
#include <dfs_file.h>
#define DBG_TAG "app.filesystem"
#define DBG_LVL DBG_INFO
#include <rtdbg.h>
static int filesystem_mount(void)
{
while(rt_device_find("sd0") == RT_NULL)
{
rt_thread_mdelay(1);
}
int ret = dfs_mount("sd0", "/", "elm", 0, 0);
if (ret != 0)
{
rt_kprintf("ret: %d\n",ret);
LOG_E("sd0 mount to '/' failed!");
return ret;
}
return RT_EOK;
}
INIT_ENV_EXPORT(filesystem_mount);
#endif

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bsp/phytium/aarch64/configs/e2000d_rtsmart.h Normal file
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@ -0,0 +1,316 @@
#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* RT-Thread Project Configuration */
/* RT-Thread Kernel */
#define RT_NAME_MAX 16
#define RT_USING_SMART
#define RT_USING_SMP
#define RT_CPUS_NR 2
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 40960
#define SYSTEM_THREAD_STACK_SIZE 40960
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 4096
/* kservice optimization */
#define RT_KSERVICE_USING_STDLIB
#define RT_KPRINTF_USING_LONGLONG
#define RT_DEBUG
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* Memory Management */
#define RT_PAGE_MAX_ORDER 11
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SMALL_MEM_AS_HEAP
#define RT_USING_HEAP
/* Kernel Device Object */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50001
#define ARCH_CPU_64BIT
#define RT_USING_CACHE
#define RT_USING_HW_ATOMIC
#define ARCH_ARM_BOOTWITH_FLUSH_CACHE
#define ARCH_MM_MMU
#define ARCH_ARM
#define ARCH_ARM_MMU
#define KERNEL_VADDR_START 0xffff000000000000
#define ARCH_ARMV8
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 8192
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
/* DFS: device virtual file system */
#define RT_USING_DFS
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FD_MAX 16
#define RT_USING_DFS_V1
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_RAMFS
#define RT_USING_LWP
#define RT_LWP_MAX_NR 30
#define LWP_TASK_STACK_SIZE 16384
#define RT_CH_MSG_MAX_NR 1024
#define LWP_CONSOLE_INPUT_BUFFER_SIZE 1024
#define LWP_TID_MAX_NR 64
#define RT_LWP_SHM_MAX_NR 64
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 8192
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_TTY
#define RT_USING_NULL
#define RT_USING_ZERO
#define RT_USING_RANDOM
#define RT_USING_RTC
/* Using USB */
/* C/C++ and POSIX layer */
#define RT_LIBC_DEFAULT_TIMEZONE 8
/* POSIX (Portable Operating System Interface) layer */
#define RT_USING_POSIX_FS
#define RT_USING_POSIX_DEVIO
#define RT_USING_POSIX_STDIO
#define RT_USING_POSIX_TERMIOS
#define RT_USING_POSIX_DELAY
#define RT_USING_POSIX_CLOCK
#define RT_USING_POSIX_TIMER
/* Interprocess Communication (IPC) */
/* Socket is in the 'Network' category */
/* Network */
/* Utilities */
#define RT_USING_RYM
#define YMODEM_USING_FILE_TRANSFER
#define RT_USING_ADT
/* RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* Wiced WiFi */
/* IoT Cloud */
/* security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
/* tools packages */
/* system packages */
/* enhanced kernel services */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
/* peripheral libraries and drivers */
/* sensors drivers */
/* touch drivers */
/* Kendryte SDK */
/* AI packages */
/* Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
/* samples: kernel and components samples */
#define PKG_USING_KERNEL_SAMPLES
#define PKG_USING_KERNEL_SAMPLES_LATEST_VERSION
#define PKG_USING_KERNEL_SAMPLES_EN
/* entertainment: terminal games and other interesting software packages */
/* Arduino libraries */
/* Projects */
/* Sensors */
/* Display */
/* Timing */
/* Data Processing */
/* Data Storage */
/* Communication */
/* Device Control */
/* Other */
/* Signal IO */
/* Uncategorized */
/* Hardware Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_UART
#define RT_USING_UART1
/* Board extended module Drivers */
#define BSP_USING_GIC
#define BSP_USING_GICV3
#define PHYTIUM_ARCH_AARCH64
#define ARM_SPI_BIND_CPU_ID 0
/* Standalone Setting */
#define TARGET_ARMV8_AARCH64
/* Board Configuration */
#define TARGET_E2000D
#define TARGET_E2000
#define DEFAULT_DEBUG_PRINT_UART1
/* Components Configuration */
#define USE_SPI
#define USE_FSPIM
#define USE_QSPI
/* Qspi Configuration */
#define USE_FQSPI
#define USE_SERIAL
/* Usart Configuration */
#define ENABLE_Pl011_UART
#define LOG_ERROR
#endif

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bsp/phytium/aarch64/configs/e2000d_rtthread.h Normal file
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@ -0,0 +1,306 @@
#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* RT-Thread Project Configuration */
/* RT-Thread Kernel */
#define RT_NAME_MAX 16
#define RT_USING_SMP
#define RT_CPUS_NR 2
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 40960
#define SYSTEM_THREAD_STACK_SIZE 40960
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 4096
/* kservice optimization */
#define RT_KSERVICE_USING_STDLIB
#define RT_KPRINTF_USING_LONGLONG
#define RT_DEBUG
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* Memory Management */
#define RT_PAGE_MAX_ORDER 11
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SMALL_MEM_AS_HEAP
#define RT_USING_HEAP
/* Kernel Device Object */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50001
#define ARCH_CPU_64BIT
#define RT_USING_CACHE
#define RT_USING_HW_ATOMIC
#define ARCH_ARM_BOOTWITH_FLUSH_CACHE
#define ARCH_MM_MMU
#define ARCH_ARM
#define ARCH_ARM_MMU
#define ARCH_ARMV8
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 8192
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
/* DFS: device virtual file system */
#define RT_USING_DFS
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FD_MAX 16
#define RT_USING_DFS_V1
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_RAMFS
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 8192
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_NULL
#define RT_USING_ZERO
#define RT_USING_RANDOM
#define RT_USING_RTC
/* Using USB */
/* C/C++ and POSIX layer */
#define RT_LIBC_DEFAULT_TIMEZONE 8
/* POSIX (Portable Operating System Interface) layer */
#define RT_USING_POSIX_FS
#define RT_USING_POSIX_DEVIO
#define RT_USING_POSIX_STDIO
#define RT_USING_POSIX_TERMIOS
#define RT_USING_POSIX_DELAY
#define RT_USING_POSIX_CLOCK
#define RT_USING_POSIX_TIMER
/* Interprocess Communication (IPC) */
/* Socket is in the 'Network' category */
/* Network */
/* Utilities */
#define RT_USING_RYM
#define YMODEM_USING_FILE_TRANSFER
#define RT_USING_ADT
/* RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* Wiced WiFi */
/* IoT Cloud */
/* security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
/* tools packages */
/* system packages */
/* enhanced kernel services */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
/* peripheral libraries and drivers */
/* sensors drivers */
/* touch drivers */
/* Kendryte SDK */
/* AI packages */
/* Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
/* samples: kernel and components samples */
#define PKG_USING_KERNEL_SAMPLES
#define PKG_USING_KERNEL_SAMPLES_LATEST_VERSION
#define PKG_USING_KERNEL_SAMPLES_EN
/* entertainment: terminal games and other interesting software packages */
/* Arduino libraries */
/* Projects */
/* Sensors */
/* Display */
/* Timing */
/* Data Processing */
/* Data Storage */
/* Communication */
/* Device Control */
/* Other */
/* Signal IO */
/* Uncategorized */
/* Hardware Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_UART
#define RT_USING_UART1
/* Board extended module Drivers */
#define BSP_USING_GIC
#define BSP_USING_GICV3
#define PHYTIUM_ARCH_AARCH64
#define ARM_SPI_BIND_CPU_ID 0
/* Standalone Setting */
#define TARGET_ARMV8_AARCH64
/* Board Configuration */
#define TARGET_E2000D
#define TARGET_E2000
#define DEFAULT_DEBUG_PRINT_UART1
/* Components Configuration */
#define USE_SPI
#define USE_FSPIM
#define USE_QSPI
/* Qspi Configuration */
#define USE_FQSPI
#define USE_SERIAL
/* Usart Configuration */
#define ENABLE_Pl011_UART
#define LOG_ERROR
#endif

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bsp/phytium/aarch64/configs/e2000q_rtsmart.h Normal file
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@ -0,0 +1,316 @@
#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* RT-Thread Project Configuration */
/* RT-Thread Kernel */
#define RT_NAME_MAX 16
#define RT_USING_SMART
#define RT_USING_SMP
#define RT_CPUS_NR 4
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 40960
#define SYSTEM_THREAD_STACK_SIZE 40960
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 4096
/* kservice optimization */
#define RT_KSERVICE_USING_STDLIB
#define RT_KPRINTF_USING_LONGLONG
#define RT_DEBUG
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* Memory Management */
#define RT_PAGE_MAX_ORDER 11
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SMALL_MEM_AS_HEAP
#define RT_USING_HEAP
/* Kernel Device Object */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50001
#define ARCH_CPU_64BIT
#define RT_USING_CACHE
#define RT_USING_HW_ATOMIC
#define ARCH_ARM_BOOTWITH_FLUSH_CACHE
#define ARCH_MM_MMU
#define ARCH_ARM
#define ARCH_ARM_MMU
#define KERNEL_VADDR_START 0xffff000000000000
#define ARCH_ARMV8
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 8192
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
/* DFS: device virtual file system */
#define RT_USING_DFS
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FD_MAX 16
#define RT_USING_DFS_V1
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_RAMFS
#define RT_USING_LWP
#define RT_LWP_MAX_NR 30
#define LWP_TASK_STACK_SIZE 16384
#define RT_CH_MSG_MAX_NR 1024
#define LWP_CONSOLE_INPUT_BUFFER_SIZE 1024
#define LWP_TID_MAX_NR 64
#define RT_LWP_SHM_MAX_NR 64
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 8192
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_TTY
#define RT_USING_NULL
#define RT_USING_ZERO
#define RT_USING_RANDOM
#define RT_USING_RTC
/* Using USB */
/* C/C++ and POSIX layer */
#define RT_LIBC_DEFAULT_TIMEZONE 8
/* POSIX (Portable Operating System Interface) layer */
#define RT_USING_POSIX_FS
#define RT_USING_POSIX_DEVIO
#define RT_USING_POSIX_STDIO
#define RT_USING_POSIX_TERMIOS
#define RT_USING_POSIX_DELAY
#define RT_USING_POSIX_CLOCK
#define RT_USING_POSIX_TIMER
/* Interprocess Communication (IPC) */
/* Socket is in the 'Network' category */
/* Network */
/* Utilities */
#define RT_USING_RYM
#define YMODEM_USING_FILE_TRANSFER
#define RT_USING_ADT
/* RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* Wiced WiFi */
/* IoT Cloud */
/* security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
/* tools packages */
/* system packages */
/* enhanced kernel services */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
/* peripheral libraries and drivers */
/* sensors drivers */
/* touch drivers */
/* Kendryte SDK */
/* AI packages */
/* Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
/* samples: kernel and components samples */
#define PKG_USING_KERNEL_SAMPLES
#define PKG_USING_KERNEL_SAMPLES_LATEST_VERSION
#define PKG_USING_KERNEL_SAMPLES_EN
/* entertainment: terminal games and other interesting software packages */
/* Arduino libraries */
/* Projects */
/* Sensors */
/* Display */
/* Timing */
/* Data Processing */
/* Data Storage */
/* Communication */
/* Device Control */
/* Other */
/* Signal IO */
/* Uncategorized */
/* Hardware Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_UART
#define RT_USING_UART1
/* Board extended module Drivers */
#define BSP_USING_GIC
#define BSP_USING_GICV3
#define PHYTIUM_ARCH_AARCH64
#define ARM_SPI_BIND_CPU_ID 2
/* Standalone Setting */
#define TARGET_ARMV8_AARCH64
/* Board Configuration */
#define TARGET_E2000Q
#define TARGET_E2000
#define DEFAULT_DEBUG_PRINT_UART1
/* Components Configuration */
#define USE_SPI
#define USE_FSPIM
#define USE_QSPI
/* Qspi Configuration */
#define USE_FQSPI
#define USE_SERIAL
/* Usart Configuration */
#define ENABLE_Pl011_UART
#define LOG_ERROR
#endif

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@ -0,0 +1,306 @@
#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* RT-Thread Project Configuration */
/* RT-Thread Kernel */
#define RT_NAME_MAX 16
#define RT_USING_SMP
#define RT_CPUS_NR 4
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 40960
#define SYSTEM_THREAD_STACK_SIZE 40960
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 4096
/* kservice optimization */
#define RT_KSERVICE_USING_STDLIB
#define RT_KPRINTF_USING_LONGLONG
#define RT_DEBUG
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* Memory Management */
#define RT_PAGE_MAX_ORDER 11
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SMALL_MEM_AS_HEAP
#define RT_USING_HEAP
/* Kernel Device Object */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50001
#define ARCH_CPU_64BIT
#define RT_USING_CACHE
#define RT_USING_HW_ATOMIC
#define ARCH_ARM_BOOTWITH_FLUSH_CACHE
#define ARCH_MM_MMU
#define ARCH_ARM
#define ARCH_ARM_MMU
#define ARCH_ARMV8
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 8192
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
/* DFS: device virtual file system */
#define RT_USING_DFS
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FD_MAX 16
#define RT_USING_DFS_V1
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_RAMFS
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 8192
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_NULL
#define RT_USING_ZERO
#define RT_USING_RANDOM
#define RT_USING_RTC
/* Using USB */
/* C/C++ and POSIX layer */
#define RT_LIBC_DEFAULT_TIMEZONE 8
/* POSIX (Portable Operating System Interface) layer */
#define RT_USING_POSIX_FS
#define RT_USING_POSIX_DEVIO
#define RT_USING_POSIX_STDIO
#define RT_USING_POSIX_TERMIOS
#define RT_USING_POSIX_DELAY
#define RT_USING_POSIX_CLOCK
#define RT_USING_POSIX_TIMER
/* Interprocess Communication (IPC) */
/* Socket is in the 'Network' category */
/* Network */
/* Utilities */
#define RT_USING_RYM
#define YMODEM_USING_FILE_TRANSFER
#define RT_USING_ADT
/* RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* Wiced WiFi */
/* IoT Cloud */
/* security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
/* tools packages */
/* system packages */
/* enhanced kernel services */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
/* peripheral libraries and drivers */
/* sensors drivers */
/* touch drivers */
/* Kendryte SDK */
/* AI packages */
/* Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
/* samples: kernel and components samples */
#define PKG_USING_KERNEL_SAMPLES
#define PKG_USING_KERNEL_SAMPLES_LATEST_VERSION
#define PKG_USING_KERNEL_SAMPLES_EN
/* entertainment: terminal games and other interesting software packages */
/* Arduino libraries */
/* Projects */
/* Sensors */
/* Display */
/* Timing */
/* Data Processing */
/* Data Storage */
/* Communication */
/* Device Control */
/* Other */
/* Signal IO */
/* Uncategorized */
/* Hardware Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_UART
#define RT_USING_UART1
/* Board extended module Drivers */
#define BSP_USING_GIC
#define BSP_USING_GICV3
#define PHYTIUM_ARCH_AARCH64
#define ARM_SPI_BIND_CPU_ID 2
/* Standalone Setting */
#define TARGET_ARMV8_AARCH64
/* Board Configuration */
#define TARGET_E2000Q
#define TARGET_E2000
#define DEFAULT_DEBUG_PRINT_UART1
/* Components Configuration */
#define USE_SPI
#define USE_FSPIM
#define USE_QSPI
/* Qspi Configuration */
#define USE_FQSPI
#define USE_SERIAL
/* Usart Configuration */
#define ENABLE_Pl011_UART
#define LOG_ERROR
#endif

15
bsp/phytium/aarch64/export_project.py
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@ -1,3 +1,18 @@
#!/usr/bin/env python
# -*- coding: utf-8 -*-
#
# Copyright (c) 2022, RT-Thread Development Team
#
# SPDX-License-Identifier: Apache-2.0
#
# Email: opensource_embedded@phytium.com.cn
#
#
# Change Logs:
# Date Author Notes
# 2022-11-15 zhugengyu The first version
#
import os
import shutil
import argparse

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20
bsp/phytium/aarch64/link.lds
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -11,7 +11,7 @@
SECTIONS
{
. = 0x80100000;
. = 0x80080000 ;
. = ALIGN(4096);
.text :
{
@ -28,6 +28,12 @@ SECTIONS
*(COMMON)
/* section information for utest */
. = ALIGN(8);
__rt_utest_tc_tab_start = .;
KEEP(*(UtestTcTab))
__rt_utest_tc_tab_end = .;
/* section information for finsh shell */
. = ALIGN(16);
__fsymtab_start = .;
@ -102,14 +108,6 @@ SECTIONS
PROVIDE(__bss_end = .);
}
. = ALIGN(4);
.heap :
{
PROVIDE(__heap_start = .);
. = ALIGN(8);
PROVIDE(end = .);
}
_end = .;
/* Stabs debugging sections. */
@ -147,4 +145,4 @@ SECTIONS
.debug_varnames 0 : { *(.debug_varnames) }
}
__bss_size = SIZEOF(.bss);
__bss_size = SIZEOF(.bss);

149
bsp/phytium/aarch64/link_smart.lds Normal file
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@ -0,0 +1,149 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* 2017-5-30 bernard first version
*/
/* _EL1_STACK_SIZE = DEFINED(_EL1_STACK_SIZE) ? _EL1_STACK_SIZE : 0x20000; */
SECTIONS
{
/* . = 0x80080000 ; */
. = 0xffff000000080000 ;
. = ALIGN(4096);
.text :
{
KEEP(*(.text.entrypoint)) /* The entry point */
*(.vectors)
*(.text) /* remaining code */
*(.text.*) /* remaining code */
*(.rodata) /* read-only data (constants) */
*(.rodata*)
*(.glue_7)
*(.glue_7t)
*(.gnu.linkonce.t*)
*(COMMON)
/* section information for utest */
. = ALIGN(8);
__rt_utest_tc_tab_start = .;
KEEP(*(UtestTcTab))
__rt_utest_tc_tab_end = .;
/* section information for finsh shell */
. = ALIGN(16);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(16);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(16);
/* section information for initial. */
. = ALIGN(16);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(16);
. = ALIGN(16);
_etext = .;
}
. = ALIGN(4);
.eh_frame_hdr :
{
*(.eh_frame_hdr)
*(.eh_frame_entry)
}
.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) }
. = ALIGN(16);
.data :
{
*(.data)
*(.data.*)
*(.data1)
*(.data1.*)
. = ALIGN(16);
_gp = ABSOLUTE(.); /* Base of small data */
*(.sdata)
*(.sdata.*)
}
. = ALIGN(16);
.ctors :
{
PROVIDE(__ctors_start__ = .);
/* new GCC version uses .init_array */
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE(__ctors_end__ = .);
}
. = ALIGN(4);
.dtors :
{
PROVIDE(__dtors_start__ = .);
KEEP(*(SORT(.dtors.*)))
KEEP(*(.dtors))
PROVIDE(__dtors_end__ = .);
}
. = ALIGN(16);
.bss :
{
PROVIDE(__bss_start = .);
*(.bss)
*(.bss.*)
*(.dynbss)
. = ALIGN(32);
PROVIDE(__bss_end = .);
}
_end = .;
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
* Symbols in the DWARF debugging sections are relative to the beginning
* of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}
__bss_size = SIZEOF(.bss);

79
bsp/phytium/aarch64/makefile Normal file
View File

@ -0,0 +1,79 @@
.PHONY: debug boot all clean menuconfig
CC = $(RTT_EXEC_PATH)/$(RTT_CC_PREFIX)gcc
CXX = $(RTT_EXEC_PATH)/$(RTT_CC_PREFIX)g++
CPP = $(RTT_EXEC_PATH)/$(RTT_CC_PREFIX)gcc -E -P -x c
STRIP = $(RTT_EXEC_PATH)/$(RTT_CC_PREFIX)strip --strip-unneeded
OBJCOPY = $(RTT_EXEC_PATH)/$(RTT_CC_PREFIX)objcopy
OBJDUMP = $(RTT_EXEC_PATH)/$(RTT_CC_PREFIX)objdump
LD = $(RTT_EXEC_PATH)/$(RTT_CC_PREFIX)ld
AR = $(RTT_EXEC_PATH)/$(RTT_CC_PREFIX)ar rcs
NM = $(RTT_EXEC_PATH)/$(RTT_CC_PREFIX)nm
OD = $(RTT_EXEC_PATH)/$(RTT_CC_PREFIX)objdump
RTCONFIG =
include .config
ifdef CONFIG_TARGET_E2000Q
RTCONFIG := e2000q
endif
ifdef CONFIG_TARGET_E2000D
RTCONFIG := e2000d
endif
ifdef CONFIG_RT_USING_SMART
RTCONFIG := $(RTCONFIG)_rtsmart
else
RTCONFIG := $(RTCONFIG)_rtthread
endif
boot:
make all
cp rtthread_a64.elf /mnt/d/tftboot
cp rtthread_a64.bin /mnt/d/tftboot
debug:
@$(OD) -D rtthread_a64.elf > rtthread_a64.asm
@$(OD) -S rtthread_a64.elf > rtthread_a64.dis
all:
@echo "Build started..."
scons -j1024
clean:
@echo "Cleaning..."
scons -c
menuconfig:
@echo "Running menuconfig..."
scons --menuconfig
saveconfig:
@echo "Save configs to" ./configs/$(RTCONFIG)
@cp ./.config ./configs/$(RTCONFIG) -f
@cp ./rtconfig.h ./configs/$(RTCONFIG).h -f
load_e2000q_rtsmart:
@echo "Load configs from ./configs/e2000q_rtsmart"
@cp ./configs/e2000q_rtsmart ./.config -f
@cp ./configs/e2000q_rtsmart.h ./rtconfig.h -f
@scons -c
load_e2000q_rtthread:
@echo "Load configs from ./configs/e2000q_rtthread"
@cp ./configs/e2000q_rtthread ./.config -f
@cp ./configs/e2000q_rtthread.h ./rtconfig.h -f
@scons -c
load_e2000d_rtsmart:
@echo "Load configs from ./configs/e2000d_rtsmart"
@cp ./configs/e2000d_rtsmart ./.config -f
@cp ./configs/e2000d_rtsmart.h ./rtconfig.h -f
@scons -c
load_e2000d_rtthread:
@echo "Load configs from ./configs/e2000d_rtthread"
@cp ./configs/e2000d_rtthread ./.config -f
@cp ./configs/e2000d_rtthread.h ./rtconfig.h -f
@scons -c

52
bsp/phytium/aarch64/rtconfig.h
View File

@ -8,18 +8,18 @@
#define RT_NAME_MAX 16
#define RT_USING_SMP
#define RT_CPUS_NR 4
#define RT_ALIGN_SIZE 8
#define RT_CPUS_NR 2
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 100
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 4096
#define SYSTEM_THREAD_STACK_SIZE 4096
#define IDLE_THREAD_STACK_SIZE 40960
#define SYSTEM_THREAD_STACK_SIZE 40960
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 4096
@ -43,6 +43,8 @@
#define RT_PAGE_MAX_ORDER 11
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SMALL_MEM_AS_HEAP
#define RT_USING_HEAP
@ -52,10 +54,11 @@
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50000
#define RT_VER_NUM 0x50001
#define ARCH_CPU_64BIT
#define RT_USING_CACHE
#define RT_USING_HW_ATOMIC
#define ARCH_ARM_BOOTWITH_FLUSH_CACHE
#define ARCH_MM_MMU
#define ARCH_ARM
#define ARCH_ARM_MMU
@ -65,7 +68,7 @@
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 4096
#define RT_MAIN_THREAD_STACK_SIZE 8192
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
@ -80,12 +83,18 @@
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
/* DFS: device virtual file system */
#define RT_USING_DFS
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FD_MAX 16
#define RT_USING_DFS_V1
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define DFS_FD_MAX 16
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_RAMFS
/* Device Drivers */
@ -98,7 +107,10 @@
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_PIN
#define RT_USING_NULL
#define RT_USING_ZERO
#define RT_USING_RANDOM
#define RT_USING_RTC
/* Using USB */
@ -109,6 +121,13 @@
/* POSIX (Portable Operating System Interface) layer */
#define RT_USING_POSIX_FS
#define RT_USING_POSIX_DEVIO
#define RT_USING_POSIX_STDIO
#define RT_USING_POSIX_TERMIOS
#define RT_USING_POSIX_DELAY
#define RT_USING_POSIX_CLOCK
#define RT_USING_POSIX_TIMER
/* Interprocess Communication (IPC) */
@ -121,6 +140,8 @@
/* Utilities */
#define RT_USING_RYM
#define YMODEM_USING_FILE_TRANSFER
#define RT_USING_ADT
/* RT-Thread Utestcases */
@ -201,6 +222,9 @@
/* samples: kernel and components samples */
#define PKG_USING_KERNEL_SAMPLES
#define PKG_USING_KERNEL_SAMPLES_LATEST_VERSION
#define PKG_USING_KERNEL_SAMPLES_EN
/* entertainment: terminal games and other interesting software packages */
@ -251,6 +275,7 @@
#define BSP_USING_GIC
#define BSP_USING_GICV3
#define PHYTIUM_ARCH_AARCH64
#define ARM_SPI_BIND_CPU_ID 0
/* Standalone Setting */
@ -258,12 +283,19 @@
/* Board Configuration */
#define TARGET_E2000Q
#define TARGET_E2000D
#define TARGET_E2000
#define DEFAULT_DEBUG_PRINT_UART1
/* Components Configuration */
#define USE_SPI
#define USE_FSPIM
#define USE_QSPI
/* Qspi Configuration */
#define USE_FQSPI
#define USE_SERIAL
/* Usart Configuration */

47
bsp/phytium/aarch64/rtconfig.py
View File

@ -3,26 +3,14 @@ import os
# toolchains options
ARCH ='aarch64'
CPU ='cortex-a'
CROSS_TOOL ='gcc'
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = r'../../..'
CROSS_TOOL = 'gcc'
PLATFORM = 'gcc'
EXEC_PATH = r'/opt/gcc-arm-8.3-2019.03-x86_64-aarch64-elf/bin/'
if os.getenv('AARCH64_CROSS_PATH'):
EXEC_PATH = os.getenv('AARCH64_CROSS_PATH')
print('EXEC_PATH = {}'.format(EXEC_PATH))
else:
print('AARCH64_CROSS_PATH not found')
BUILD = 'debug'
EXEC_PATH = os.getenv('RTT_EXEC_PATH') or '/usr/bin'
BUILD = 'debug'
if PLATFORM == 'gcc':
# toolchains
PREFIX = 'aarch64-none-elf-'
PREFIX = os.getenv('RTT_CC_PREFIX') or 'aarch64-none-elf-'
CC = PREFIX + 'gcc'
CXX = PREFIX + 'g++'
AS = PREFIX + 'gcc'
@ -32,21 +20,26 @@ if PLATFORM == 'gcc':
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
STRIP = PREFIX + 'strip'
CFPFLAGS = ' '
AFPFLAGS = ' '
DEVICE = ' -march=armv8-a -ftree-vectorize -ffast-math -funwind-tables -fno-strict-aliasing'
DEVICE = ' -march=armv8-a -mtune=cortex-a72'
CFLAGS = DEVICE + ' -Wall'
AFLAGS = ' -c' + ' -x assembler-with-cpp -D__ASSEMBLY__'
LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread_a64.map,-cref,-u,system_vectors -T link.lds -fdiagnostics-color=always'
CXXFLAGS= DEVICE + CFPFLAGS + ' -Wall -fdiagnostics-color=always'
CFLAGS = DEVICE + CFPFLAGS + ' -Wall -Wno-cpp -std=gnu99 -fdiagnostics-color=always'
AFLAGS = ' -c' + AFPFLAGS + ' -x assembler-with-cpp'
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread_a64.map,-cref,-u,system_vectors -T link.lds' + ' -lsupc++ -lgcc -static'
CPATH = ''
LPATH = ''
if BUILD == 'debug':
CFLAGS += ' -O0 -gdwarf-2'
AFLAGS += ' -gdwarf-2'
CFLAGS += ' -O0 -gdwarf-2'
CXXFLAGS += ' -O0 -gdwarf-2'
AFLAGS += ' -gdwarf-2'
else:
CFLAGS += ' -O2'
CFLAGS += ' -Os'
CXXFLAGS += ' -Os'
CXXFLAGS += ' -Woverloaded-virtual -fno-exceptions -fno-rtti'
CXXFLAGS = CFLAGS
DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtthread_a64.dis\n'
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread_a64.bin\n' + SIZE + ' $TARGET \n'
DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtthread_a64.asm\n'
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread_a64.bin\n' + SIZE + ' $TARGET \n'

71
bsp/phytium/aarch64/sdkconfig.h
View File

@ -1,71 +0,0 @@
/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: sdkconfig.h
* Date: 2022-10-09 15:04:36
* LastEditTime: 2022-10-09 15:04:37
* Description: This file is for
*
* Modify History:
* Ver Who Date Changes
* ----- ------ -------- --------------------------------------
*/
#ifndef SDK_CONFIG_H__
#define SDK_CONFIG_H__
#include "rtconfig.h"
/* board */
/* E2000 */
#if defined(TARGET_E2000)
#define CONFIG_TARGET_E2000
#endif
#if defined(TARGET_E2000Q)
#define CONFIG_TARGET_E2000Q
#endif
#if defined(TARGET_ARMV8_AARCH64)
#define CONFIG_TARGET_ARMV8_AARCH64
#endif
/* debug */
#ifdef LOG_VERBOS
#define CONFIG_LOG_VERBOS
#endif
#ifdef LOG_ERROR
#define CONFIG_LOG_ERROR
#endif
#ifdef LOG_WARN
#define CONFIG_LOG_WARN
#endif
#ifdef LOG_INFO
#define CONFIG_LOG_INFO
#endif
#ifdef LOG_DEBUG
#define CONFIG_LOG_DEBUG
#endif
#ifdef BOOTUP_DEBUG_PRINTS
#define CONFIG_BOOTUP_DEBUG_PRINTS
#endif
#endif

15
bsp/phytium/board/SConscript
View File

@ -2,21 +2,24 @@ from building import *
cwd = GetCurrentDir()
src = Glob('*.S')
src += Glob('*.c')
src += Glob('*.c')
if GetDepend(['TARGET_E2000']):
src += Glob(cwd + '/e2000/memory_map.c')
if GetDepend(['TARGET_E2000Q']):
src += Glob(cwd + '/e2000/q/parameters.c')
src += Glob(cwd + '/e2000/q/parameters.c')
elif GetDepend(['TARGET_E2000D']):
src += Glob(cwd + '/e2000/d/parameters.c')
src += Glob(cwd + '/e2000/d/parameters.c')
elif GetDepend(['TARGET_E2000S']):
src += Glob(cwd + '/e2000/s/parameters.c')
src += Glob(cwd + '/e2000/s/parameters.c')
if GetDepend(['TARGET_F2000_4']):
src += Glob(cwd + '/d2000/parameters.c')
src += Glob(cwd + '/ft2004/memory_map.c')
src += Glob(cwd + '/d2000/parameters.c')
if GetDepend(['TARGET_D2000']):
src += Glob(cwd + '/ft2004/parameters.c')
src += Glob(cwd + '/d2000/memory_map.c')
src += Glob(cwd + '/ft2004/parameters.c')
CPPPATH = [cwd]

405
bsp/phytium/board/board.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -9,6 +9,7 @@
* Date Author Notes
* 2022-10-26 huanghe first commit
* 2022-10-26 zhugengyu support aarch64
* 2023-04-13 zhugengyu support RT-Smart
*
*/
@ -17,6 +18,13 @@
#include <rtthread.h>
#include <mmu.h>
#include <mm_aspace.h> /* TODO: why need application space when RT_SMART off */
#include <mm_page.h>
#ifdef RT_USING_SMART
#include <page.h>
#include <lwp_arch.h>
#endif
#include <gicv3.h>
#if defined(TARGET_ARMV8_AARCH64)
@ -33,7 +41,6 @@
#include "fprintk.h"
#include "fearly_uart.h"
#include "fcpu_info.h"
#include "fpsci.h"
#define LOG_DEBUG_TAG "BOARD"
#define BSP_LOG_ERROR(format, ...) FT_DEBUG_PRINT_E(LOG_DEBUG_TAG, format, ##__VA_ARGS__)
@ -42,142 +49,36 @@
#define BSP_LOG_DEBUG(format, ...) FT_DEBUG_PRINT_D(LOG_DEBUG_TAG, format, ##__VA_ARGS__)
/* mmu config */
struct mem_desc platform_mem_desc[] =
#if defined(TARGET_E2000)
{
{
0x00U,
0x00U + 0x40000000U,
0x00U,
DEVICE_MEM
},
{
0x40000000U,
0x40000000U + 0x10000000U,
0x40000000U,
DEVICE_MEM
},
{
0x50000000U,
0x50000000U + 0x30000000U,
0x50000000U,
DEVICE_MEM
},
{
0x80000000U,
0xffffffffU,
0x80000000U,
NORMAL_MEM
},
#if defined(TARGET_ARMV8_AARCH64)
{
0x1000000000,
0x1000000000 + 0x1000000000,
0x1000000000,
DEVICE_MEM
},
{
0x2000000000,
0x2000000000 + 0x2000000000,
0x2000000000,
NORMAL_MEM
},
#endif
};
#elif defined(TARGET_F2000_4) || defined(TARGET_D2000)
{
{
0x80000000,
0xFFFFFFFF,
0x80000000,
DDR_MEM
},
{
0, //< QSPI
0x1FFFFFFF,
0,
DEVICE_MEM
},
{
0x20000000, //<! LPC
0x27FFFFFF,
0x20000000,
DEVICE_MEM
},
{
FT_DEV_BASE_ADDR, //<! Device register
FT_DEV_END_ADDR,
FT_DEV_BASE_ADDR,
DEVICE_MEM
},
{
0x30000000, //<! debug
0x39FFFFFF,
0x30000000,
DEVICE_MEM
},
{
0x3A000000, //<! Internal register space in the on-chip network
0x3AFFFFFF,
0x3A000000,
DEVICE_MEM
},
{
FT_PCI_CONFIG_BASEADDR,
FT_PCI_CONFIG_BASEADDR + FT_PCI_CONFIG_REG_LENGTH,
FT_PCI_CONFIG_BASEADDR,
DEVICE_MEM
},
{
FT_PCI_IO_CONFIG_BASEADDR,
FT_PCI_IO_CONFIG_BASEADDR + FT_PCI_IO_CONFIG_REG_LENGTH,
FT_PCI_IO_CONFIG_BASEADDR,
DEVICE_MEM
},
{
FT_PCI_MEM32_BASEADDR,
FT_PCI_MEM32_BASEADDR + FT_PCI_MEM32_REG_LENGTH,
FT_PCI_MEM32_BASEADDR,
DEVICE_MEM
}
#if defined(TARGET_ARMV8_AARCH64)
{
0x1000000000,
0x1000000000 + 0x1000000000,
0x1000000000,
DEVICE_MEM
},
{
0x2000000000,
0x2000000000 + 0x2000000000,
0x2000000000,
NORMAL_MEM
},
#endif
};
#endif
const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc) / sizeof(platform_mem_desc[0]);
#if defined(TARGET_ARMV8_AARCH64) /* AARCH64 */
/* aarch64 use kernel gtimer */
extern struct mem_desc platform_mem_desc[];
extern const rt_uint32_t platform_mem_desc_size;
void idle_wfi(void)
{
asm volatile("wfi");
}
/**
* This function will initialize board
*/
extern size_t MMUTable[];
rt_region_t init_page_region = {
PAGE_START,
PAGE_END
};
#if defined(TARGET_ARMV8_AARCH64) /* AARCH64 */
/* aarch64 use kernel gtimer */
#else /* AARCH32 */
static rt_uint32_t timerStep;
/* aarch32 implment gtimer by bsp */
static rt_uint32_t timer_step;
void rt_hw_timer_isr(int vector, void *parameter)
{
GenericTimerCompare(timerStep);
GenericTimerCompare(timer_step);
rt_tick_increase();
}
@ -185,10 +86,10 @@ int rt_hw_timer_init(void)
{
rt_hw_interrupt_install(GENERIC_TIMER_NS_IRQ_NUM, rt_hw_timer_isr, RT_NULL, "tick");
rt_hw_interrupt_umask(GENERIC_TIMER_NS_IRQ_NUM);
timerStep = GenericTimerFrequecy();
timerStep /= RT_TICK_PER_SECOND;
timer_step = GenericTimerFrequecy();
timer_step /= RT_TICK_PER_SECOND;
GenericTimerCompare(timerStep);
GenericTimerCompare(timer_step);
GenericTimerInterruptEnable();
GenericTimerStart();
return 0;
@ -196,110 +97,170 @@ int rt_hw_timer_init(void)
INIT_BOARD_EXPORT(rt_hw_timer_init);
#endif
#ifdef RT_USING_SMP
void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler);
#endif
#if defined(TARGET_ARMV8_AARCH64)
void rt_hw_board_aarch64_init(void)
{
/* AARCH64 */
#if defined(RT_USING_SMART)
/* 1. init rt_kernel_space table (aspace.start = KERNEL_VADDR_START , aspace.size = ), 2. init io map range (rt_ioremap_start \ rt_ioremap_size) 3. */
rt_hw_mmu_map_init(&rt_kernel_space, (void*)0xfffffffff0000000, 0x10000000, MMUTable, PV_OFFSET);
#else
rt_hw_mmu_map_init(&rt_kernel_space, (void*)0x80000000, 0x10000000, MMUTable, 0);
#endif
rt_page_init(init_page_region);
rt_hw_mmu_setup(&rt_kernel_space, platform_mem_desc, platform_mem_desc_size);
/* init memory pool */
#ifdef RT_USING_HEAP
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
#endif
rt_hw_interrupt_init();
rt_hw_gtimer_init();
/* compoent init */
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
/* shell init */
#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
/* set console device */
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
rt_thread_idle_sethook(idle_wfi);
#ifdef RT_USING_SMP
/* install IPI handle */
rt_hw_interrupt_set_priority(RT_SCHEDULE_IPI, 16);
rt_hw_ipi_handler_install(RT_SCHEDULE_IPI, rt_scheduler_ipi_handler);
rt_hw_interrupt_umask(RT_SCHEDULE_IPI);
#endif
}
#else
void rt_hw_board_aarch32_init(void)
{
#if defined(RT_USING_SMART)
/* set io map range is 0xf0000000 ~ 0x10000000 , Memory Protection start address is 0xf0000000 - rt_mpr_size */
rt_hw_mmu_map_init(&rt_kernel_space, (void*)0xf0000000, 0x10000000, MMUTable, PV_OFFSET);
rt_page_init(init_page_region);
/* rt_kernel_space 在start_gcc.S 中被初始化，此函数将iomap 空间放置在kernel space 上 */
rt_hw_mmu_ioremap_init(&rt_kernel_space, (void*)0xf0000000, 0x10000000);
/* */
arch_kuser_init(&rt_kernel_space, (void*)0xffff0000);
#else
/*
map kernel space memory (totally 1GB = 0x10000000), pv_offset = 0 if not RT_SMART:
0x80000000 ~ 0x80100000: kernel stack
0x80100000 ~ __bss_end: kernel code and data
*/
rt_hw_mmu_map_init(&rt_kernel_space, (void*)0x80000000, 0x10000000, MMUTable, 0);
rt_hw_mmu_ioremap_init(&rt_kernel_space, (void*)0x80000000, 0x10000000);
#endif
/* init memory pool */
#ifdef RT_USING_HEAP
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
#endif
extern int rt_hw_cpu_id(void);
u32 cpu_id, cpu_offset = 0;
GetCpuId(&cpu_id);
#if defined(FT_GIC_REDISTRUBUTIOR_OFFSET)
cpu_offset = FT_GIC_REDISTRUBUTIOR_OFFSET ;
#endif
rt_uint32_t redist_addr = 0;
#if defined(RT_USING_SMART)
redist_addr = (uint32_t)rt_ioremap(GICV3_RD_BASE_ADDR, 4 * 128*1024);
#else
redist_addr = GICV3_RD_BASE_ADDR;
#endif
arm_gic_redist_address_set(0, redist_addr + (cpu_id + cpu_offset) * GICV3_RD_OFFSET, rt_hw_cpu_id());
#if defined(TARGET_E2000Q)
#if RT_CPUS_NR == 2
arm_gic_redist_address_set(0, redist_addr + 3 * GICV3_RD_OFFSET, 1);
#elif RT_CPUS_NR == 3
arm_gic_redist_address_set(0, redist_addr + 3 * GICV3_RD_OFFSET, 1);
arm_gic_redist_address_set(0, redist_addr, 2);
#elif RT_CPUS_NR == 4
arm_gic_redist_address_set(0, redist_addr + 3 * GICV3_RD_OFFSET, 1);
arm_gic_redist_address_set(0, redist_addr, 2);
arm_gic_redist_address_set(0, redist_addr + GICV3_RD_OFFSET, 3);
#endif
#else
#if RT_CPUS_NR == 2
arm_gic_redist_address_set(0, redist_addr + (1 + cpu_offset) * GICV3_RD_OFFSET, 1);
#elif RT_CPUS_NR == 3
arm_gic_redist_address_set(0, redist_addr + (1 + cpu_offset) * GICV3_RD_OFFSET, 1);
arm_gic_redist_address_set(0, redist_addr + (2 + cpu_offset) * GICV3_RD_OFFSET, 2);
#elif RT_CPUS_NR == 4
arm_gic_redist_address_set(0, redist_addr + (1 + cpu_offset) * GICV3_RD_OFFSET, 1);
arm_gic_redist_address_set(0, redist_addr + (2 + cpu_offset) * GICV3_RD_OFFSET, 2);
arm_gic_redist_address_set(0, redist_addr + (3 + cpu_offset) * GICV3_RD_OFFSET, 3);
#endif
#endif
rt_hw_interrupt_init();
/* compoent init */
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
/* shell init */
#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
/* set console device */
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
rt_thread_idle_sethook(idle_wfi);
#ifdef RT_USING_SMP
/* install IPI handle */
rt_hw_interrupt_set_priority(RT_SCHEDULE_IPI, 16);
rt_hw_ipi_handler_install(RT_SCHEDULE_IPI, rt_scheduler_ipi_handler);
rt_hw_interrupt_umask(RT_SCHEDULE_IPI);
#endif
}
#endif
/**
* This function will initialize hardware board
*/
void rt_hw_board_init(void)
{
/* mmu init */
#if defined(TARGET_ARMV8_AARCH64)
rt_hw_init_mmu_table(platform_mem_desc, platform_mem_desc_size);
rt_hw_mmu_init();
#endif
/* interrupt init */
#if defined(TARGET_ARMV8_AARCH64)
f_printk("aarch64 interrupt init \r\n");
rt_hw_board_aarch64_init();
#else
f_printk("aarch32 interrupt init \r\n");
extern int rt_hw_cpu_id(void);
u32 cpu_id, cpu_offset = 0;
GetCpuId(&cpu_id);
f_printk("cpu_id is %d \r\n", cpu_id);
#if defined(FT_GIC_REDISTRUBUTIOR_OFFSET)
cpu_offset = FT_GIC_REDISTRUBUTIOR_OFFSET ;
#endif
f_printk("cpu_offset is %d \r\n", cpu_offset);
arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + (cpu_id + cpu_offset) * GICV3_RD_OFFSET, rt_hw_cpu_id());
#if defined(TARGET_E2000Q)
#if RT_CPUS_NR == 2
f_printk("arm_gic_redist_address_set is 2 \r\n");
arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + 3 * GICV3_RD_OFFSET, 1);
#elif RT_CPUS_NR == 3
arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + 3 * GICV3_RD_OFFSET, 1);
arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS, 2);
#elif RT_CPUS_NR == 4
arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + 3 * GICV3_RD_OFFSET, 1);
arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS, 2);
arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + GICV3_RD_OFFSET, 3);
#endif
#else
#if RT_CPUS_NR == 2
f_printk("arm_gic_redist_address_set is 2 \r\n");
arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + (1 + cpu_offset) * GICV3_RD_OFFSET, 1);
#elif RT_CPUS_NR == 3
arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + (1 + cpu_offset) * GICV3_RD_OFFSET, 1);
arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + (2 + cpu_offset) * GICV3_RD_OFFSET, 2);
#elif RT_CPUS_NR == 4
arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + (1 + cpu_offset) * GICV3_RD_OFFSET, 1);
arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + (2 + cpu_offset) * GICV3_RD_OFFSET, 2);
arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + (3 + cpu_offset) * GICV3_RD_OFFSET, 3);
#endif
#endif
#endif
rt_hw_interrupt_init();
/* gtimer init */
#if defined(TARGET_ARMV8_AARCH64)
rt_hw_gtimer_init();
#endif
/* compoent init */
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
/* shell init */
#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
/* set console device */
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
/* init memory pool */
#ifdef RT_USING_HEAP
rt_system_heap_init(HEAP_BEGIN, HEAP_END);
#endif
#ifdef RT_USING_SMP
/* install IPI handle */
rt_hw_interrupt_set_priority(RT_SCHEDULE_IPI, 16);
rt_hw_ipi_handler_install(RT_SCHEDULE_IPI, rt_scheduler_ipi_handler);
rt_hw_interrupt_umask(RT_SCHEDULE_IPI);
rt_hw_board_aarch32_init();
#endif
}
static void ft_reset(void)
{
PsciCpuReset();
}
MSH_CMD_EXPORT_ALIAS(ft_reset, ft_reset, ft_reset);
/*@}*/

19
bsp/phytium/board/board.h
View File

@ -8,6 +8,7 @@
* Change Logs:
* Date Author Notes
* 2022-10-26 huanghe first commit
* 2022-04-13 zhugengyu support RT-Smart
*
*/
@ -17,6 +18,11 @@
#include "fparameters.h"
#include "phytium_cpu.h"
#include "mmu.h"
#ifdef RT_USING_SMART
#include "ioremap.h"
#endif
#if defined(__CC_ARM)
extern int Image$$RW_IRAM1$$ZI$$Limit;
#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
@ -25,7 +31,18 @@
#define HEAP_BEGIN ((void *)&__bss_end)
#endif
#define HEAP_END (void *)(0x80000000 + 1024 * 1024 * 1024)
#ifdef RT_USING_SMART
#define HEAP_END (rt_size_t)((rt_size_t)KERNEL_VADDR_START + 64 * 1024 * 1024)
#define PAGE_START HEAP_END + 1 * 1024 * 1024
#define PAGE_END (rt_size_t)((rt_size_t)KERNEL_VADDR_START + 128 * 1024 * 1024)
#else
#define HEAP_END (rt_size_t)(HEAP_BEGIN + 64*1024*1024)
#define KERNEL_VADDR_START (rt_size_t)0x80000000
#define DDR_END_ADDRESS (KERNEL_VADDR_START + 1024*1024*1024 - 1 )
#define PAGE_POOL_SIZE (8ul << 20)
#define PAGE_START (rt_size_t)(HEAP_END)
#define PAGE_END (PAGE_START +PAGE_POOL_SIZE)
#endif
void rt_hw_board_init(void);

119
bsp/phytium/board/d2000/memory_map.c Normal file
View File

@ -0,0 +1,119 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Email: opensource_embedded@phytium.com.cn
*
* Change Logs:
* Date Author Notes
* 2023-04-27 huanghe first version
*
*/
#include "rtconfig.h"
#include <board.h>
#include <mmu.h>
/* mmu config */
#ifdef RT_USING_SMART
#if defined(TARGET_ARMV8_AARCH64)
struct mem_desc platform_mem_desc[] =
{
{ KERNEL_VADDR_START,
KERNEL_VADDR_START + 0x0fffffff,
(rt_size_t)ARCH_MAP_FAILED,
NORMAL_MEM
}
};
#else
struct mem_desc platform_mem_desc[] =
{
{ KERNEL_VADDR_START,
KERNEL_VADDR_START + 0x10000000,
(rt_size_t)ARCH_MAP_FAILED,
NORMAL_MEM
}
};
#endif
const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc) / sizeof(platform_mem_desc[0]);
#else
/* mmu config */
struct mem_desc platform_mem_desc[] =
{
{
0x80000000,
0xFFFFFFFF,
0x80000000,
DDR_MEM
},
{
0, //< QSPI
0x1FFFFFFF,
0,
DEVICE_MEM
},
{
0x20000000, //<! LPC
0x27FFFFFF,
0x20000000,
DEVICE_MEM
},
{
FT_DEV_BASE_ADDR, //<! Device register
FT_DEV_END_ADDR,
FT_DEV_BASE_ADDR,
DEVICE_MEM
},
{
0x30000000, //<! debug
0x39FFFFFF,
0x30000000,
DEVICE_MEM
},
{
0x3A000000, //<! Internal register space in the on-chip network
0x3AFFFFFF,
0x3A000000,
DEVICE_MEM
},
{
FT_PCI_CONFIG_BASEADDR,
FT_PCI_CONFIG_BASEADDR + FT_PCI_CONFIG_REG_LENGTH,
FT_PCI_CONFIG_BASEADDR,
DEVICE_MEM
},
{
FT_PCI_IO_CONFIG_BASEADDR,
FT_PCI_IO_CONFIG_BASEADDR + FT_PCI_IO_CONFIG_REG_LENGTH,
FT_PCI_IO_CONFIG_BASEADDR,
DEVICE_MEM
},
{
FT_PCI_MEM32_BASEADDR,
FT_PCI_MEM32_BASEADDR + FT_PCI_MEM32_REG_LENGTH,
FT_PCI_MEM32_BASEADDR,
DEVICE_MEM
}
#if defined(TARGET_ARMV8_AARCH64)
{
0x1000000000,
0x1000000000 + 0x1000000000,
0x1000000000,
DEVICE_MEM
},
{
0x2000000000,
0x2000000000 + 0x2000000000,
0x2000000000,
NORMAL_MEM
},
#endif
};
const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc) / sizeof(platform_mem_desc[0]);
#endif

4
bsp/phytium/board/d2000/parameters.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -112,4 +112,4 @@ u32 GetCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list)
}
return 1;
}
}

99
bsp/phytium/board/e2000/memory_map.c Normal file
View File

@ -0,0 +1,99 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Email: opensource_embedded@phytium.com.cn
*
* Change Logs:
* Date Author Notes
* 2023-04-27 huanghe first version
*
*/
#include "rtconfig.h"
#include <board.h>
#include <mmu.h>
/* mmu config */
#ifdef RT_USING_SMART
#if defined(TARGET_ARMV8_AARCH64)
struct mem_desc platform_mem_desc[] =
{
{ KERNEL_VADDR_START,
KERNEL_VADDR_START + 0x0fffffff,
(rt_size_t)ARCH_MAP_FAILED,
NORMAL_MEM
}
};
#else
struct mem_desc platform_mem_desc[] =
{
{ KERNEL_VADDR_START,
KERNEL_VADDR_START + 0x10000000,
(rt_size_t)ARCH_MAP_FAILED,
NORMAL_MEM
}
};
#endif
#else
#if defined(TARGET_ARMV8_AARCH64)
struct mem_desc platform_mem_desc[] = {
{KERNEL_VADDR_START, DDR_END_ADDRESS , KERNEL_VADDR_START, NORMAL_MEM},
{
0x28000000U,
0x32B36FFFU,
0x28000000U,
DEVICE_MEM
},
};
#else
struct mem_desc platform_mem_desc[] =
{
{
0x00U,
0x00U + 0x40000000U,
0x00U,
DEVICE_MEM
},
{
0x40000000U,
0x40000000U + 0x10000000U,
0x40000000U,
DEVICE_MEM
},
{
0x50000000U,
0x50000000U + 0x30000000U,
0x50000000U,
DEVICE_MEM
},
{
0x80000000U,
0xffffffffU,
0x80000000U,
NORMAL_MEM
},
#if defined(TARGET_ARMV8_AARCH64)
{
0x1000000000,
0x1000000000 + 0x1000000000,
0x1000000000,
DEVICE_MEM
},
{
0x2000000000,
0x2000000000 + 0x2000000000,
0x2000000000,
NORMAL_MEM
},
#endif
};
#endif
#endif
const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc) / sizeof(platform_mem_desc[0]);

4
bsp/phytium/board/e2000/q/parameters.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -72,4 +72,4 @@ u32 GetCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list)
}
return 1;
}
}

91
bsp/phytium/board/ft2004/memory_map.c Normal file
View File

@ -0,0 +1,91 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Email: opensource_embedded@phytium.com.cn
*
* Change Logs:
* Date Author Notes
* 2023-04-27 huanghe first version
*
*/
#include "rtconfig.h"
#include <board.h>
#include <mmu.h>
/* mmu config */
struct mem_desc platform_mem_desc[] =
{
{
0x80000000,
0xFFFFFFFF,
0x80000000,
DDR_MEM
},
{
0, //< QSPI
0x1FFFFFFF,
0,
DEVICE_MEM
},
{
0x20000000, //<! LPC
0x27FFFFFF,
0x20000000,
DEVICE_MEM
},
{
FT_DEV_BASE_ADDR, //<! Device register
FT_DEV_END_ADDR,
FT_DEV_BASE_ADDR,
DEVICE_MEM
},
{
0x30000000, //<! debug
0x39FFFFFF,
0x30000000,
DEVICE_MEM
},
{
0x3A000000, //<! Internal register space in the on-chip network
0x3AFFFFFF,
0x3A000000,
DEVICE_MEM
},
{
FT_PCI_CONFIG_BASEADDR,
FT_PCI_CONFIG_BASEADDR + FT_PCI_CONFIG_REG_LENGTH,
FT_PCI_CONFIG_BASEADDR,
DEVICE_MEM
},
{
FT_PCI_IO_CONFIG_BASEADDR,
FT_PCI_IO_CONFIG_BASEADDR + FT_PCI_IO_CONFIG_REG_LENGTH,
FT_PCI_IO_CONFIG_BASEADDR,
DEVICE_MEM
},
{
FT_PCI_MEM32_BASEADDR,
FT_PCI_MEM32_BASEADDR + FT_PCI_MEM32_REG_LENGTH,
FT_PCI_MEM32_BASEADDR,
DEVICE_MEM
}
#if defined(TARGET_ARMV8_AARCH64)
{
0x1000000000,
0x1000000000 + 0x1000000000,
0x1000000000,
DEVICE_MEM
},
{
0x2000000000,
0x2000000000 + 0x2000000000,
0x2000000000,
NORMAL_MEM
},
#endif
};
const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc) / sizeof(platform_mem_desc[0]);

4
bsp/phytium/board/ft2004/parameters.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -68,4 +68,4 @@ u32 GetCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list)
}
return 1;
}
}

89
bsp/phytium/board/phytium_cpu.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,6 +20,72 @@
#include "phytium_cpu.h"
#if defined(TARGET_ARMV8_AARCH64)
/**
@name: phytium_cpu_id_mapping
@msg: Map Phytium CPU ID
@brief: Map the input CPU ID to a new CPU ID based on the type and quantity of CPUs on the target board.
@param {int} cpu_id Input CPU ID
@return {int} Mapped CPU ID
*/
int phytium_cpu_id_mapping(int cpu_id)
{
#if defined(TARGET_E2000Q)
#if RT_CPUS_NR <= 2
switch (cpu_id)
{
case 0:
return 2;
case 1:
return 3;
case 2:
return 0;
case 3:
return 1;
default:
RT_ASSERT(0);
return 0;
break;
}
#else
return (int)cpu_id;
#endif
#else
return (int)cpu_id;
#endif
}
int phytium_cpu_id(void)
{
FError ret;
u32 cpu_id;
ret = GetCpuId(&cpu_id);
if (ret != ERR_SUCCESS)
{
RT_ASSERT(0);
}
return phytium_cpu_id_mapping(cpu_id);
}
int rt_hw_cpu_id(void)
{
FError ret;
u32 cpu_id;
ret = GetCpuId(&cpu_id);
if (ret != ERR_SUCCESS)
{
RT_ASSERT(0);
}
return phytium_cpu_id_mapping(cpu_id);
}
#else
int phytium_cpu_id_mapping(int cpu_id)
{
#if defined(TARGET_E2000Q)
@ -43,23 +109,6 @@ int phytium_cpu_id_mapping(int cpu_id)
#endif
}
#if defined(TARGET_ARMV8_AARCH64)
int phytium_cpu_id(void)
{
FError ret;
u32 cpu_id;
ret = GetCpuId(&cpu_id);
if (ret != ERR_SUCCESS)
{
RT_ASSERT(0);
}
return phytium_cpu_id_mapping(cpu_id);
};
#else
int rt_hw_cpu_id(void)
{
FError ret;
@ -72,7 +121,7 @@ int rt_hw_cpu_id(void)
}
return phytium_cpu_id_mapping(cpu_id);
};
}
@ -110,4 +159,4 @@ MSH_CMD_EXPORT(send_core_isg, send_core_isg);
#endif
#endif
#endif

27
bsp/phytium/board/phytium_cpu.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -19,7 +19,16 @@
#include "fparameters.h"
#define ARM_GIC_MAX_NR 1
#if defined(TARGET_FT2000_4) || defined(TARGET_D2000)
#define MAX_HANDLERS 160
#endif
#if defined(TARGET_E2000)
#define MAX_HANDLERS 270
#define ARM_GIC_CPU_NUM 4
#endif
#define GIC_IRQ_START 0
#define GIC_ACK_INTID_MASK 0x000003ff
@ -28,7 +37,7 @@ rt_uint64_t get_main_cpu_affval(void);
rt_inline rt_uint32_t platform_get_gic_dist_base(void)
{
return GICV3_DISTRIBUTOR_BASEADDRESS;
return GICV3_DISTRIBUTOR_BASE_ADDR;
}
#if defined(TARGET_ARMV8_AARCH64)
@ -38,6 +47,7 @@ rt_inline rt_uint32_t platform_get_gic_redist_base(void)
{
extern int phytium_cpu_id(void);
#if RT_CPUS_NR <= 2
s32 cpu_offset = 0;
#if defined(FT_GIC_REDISTRUBUTIOR_OFFSET)
cpu_offset = FT_GIC_REDISTRUBUTIOR_OFFSET ;
@ -59,10 +69,15 @@ rt_inline rt_uint32_t platform_get_gic_redist_base(void)
default:
break;
}
#endif
rt_kprintf("offset is %x\n", cpu_offset);
return (GICV3_RD_BASEADDRESS + (cpu_offset) * GICV3_RD_OFFSET);
rt_kprintf("cpu_id is %d \r\n",cpu_id);
#endif
rt_kprintf("offset is %d\n", cpu_offset);
return (GICV3_RD_BASE_ADDR + (cpu_offset) * GICV3_RD_OFFSET);
#else
return (GICV3_RD_BASE_ADDR);
#endif
}
rt_inline rt_uint32_t platform_get_gic_cpu_base(void)
@ -77,4 +92,4 @@ int phytium_cpu_id_mapping(int cpu_id);
#endif // !
#endif // !

218
bsp/phytium/board/phytium_cpu_id.S Normal file
View File

@ -0,0 +1,218 @@
#include "fparameters.h"
#include "sdkconfig.h"
#ifndef __aarch64__
.globl cpu_id_mapping
cpu_id_mapping:
#if defined(CONFIG_TARGET_E2000Q)
cmp r0, #0 // compare cpu_id with 0
beq map_cpu_id_0
cmp r0, #1 // compare cpu_id with 1
beq map_cpu_id_1
cmp r0, #2 // compare cpu_id with 2
beq map_cpu_id_2
cmp r0, #3 // compare cpu_id with 3
beq map_cpu_id_3
mov pc, lr // no mapping needed
#endif
mov pc, lr // no mapping needed
// Mapping for E2000Q
map_cpu_id_0:
mov r0, #2
mov pc, lr
map_cpu_id_1:
mov r0, #3
mov pc, lr
map_cpu_id_2:
mov r0, #0
mov pc, lr
map_cpu_id_3:
mov r0, #1
mov pc, lr
.globl rt_asm_cpu_id
rt_asm_cpu_id:
// read MPIDR
mov r9, lr
mrc p15, 0, r0, c0, c0, 5
ubfx r0, r0, #0, #12
ldr r1,= CORE0_AFF
cmp r0, r1
beq core0
#if defined(CORE1_AFF)
ldr r1,= CORE1_AFF
cmp r0, r1
beq core1
#endif
#if defined(CORE2_AFF)
ldr r1,= CORE2_AFF
cmp r0, r1
beq core2
#endif
#if defined(CORE3_AFF)
ldr r1,= CORE3_AFF
cmp r0, r1
beq core3
#endif
b default
core0:
mov r0, #0
b return
core1:
mov r0, #1
b return
core2:
mov r0, #2
b return
core3:
mov r0, #3
b return
core4:
mov r0, #4
b return
core5:
mov r0, #5
b return
core6:
mov r0, #6
b return
core8:
mov r0, #8
b return
default:
and r0, r0, #15
return:
bl cpu_id_mapping
mov pc, r9
#else
.globl cpu_id_mapping
cpu_id_mapping:
#if defined(CONFIG_TARGET_E2000Q)
cmp x0, #0 // compare cpu_id with 0
beq map_cpu_id_0
cmp x0, #1 // compare cpu_id with 1
beq map_cpu_id_1
cmp x0, #2 // compare cpu_id with 2
beq map_cpu_id_2
cmp x0, #3 // compare cpu_id with 3
beq map_cpu_id_3
RET // no mapping needed
#endif
RET // no mapping needed
// Mapping for E2000Q
map_cpu_id_0:
mov x0, #2
RET
map_cpu_id_1:
mov x0, #3
RET
map_cpu_id_2:
mov x0, #0
RET
map_cpu_id_3:
mov x0, #1
RET
.globl rt_hw_cpu_id_set
rt_hw_cpu_id_set:
mov x9, lr
mrs x0,MPIDR_EL1
and x1, x0, #15
msr tpidr_el1, x1
ubfx x0, x0, #0, #12
ldr x1,= CORE0_AFF
cmp x0, x1
beq core0
#if defined(CORE1_AFF)
ldr x1,= CORE1_AFF
cmp x0, x1
beq core1
#endif
#if defined(CORE2_AFF)
ldr x1,= CORE2_AFF
cmp x0, x1
beq core2
#endif
#if defined(CORE3_AFF)
ldr x1,= CORE3_AFF
cmp x0, x1
beq core3
#endif
b default
core0:
mov x0, #0
b return
core1:
mov x0, #1
b return
core2:
mov x0, #2
b return
core3:
mov x0, #3
b return
core4:
mov x0, #4
b return
core5:
mov x0, #5
b return
core6:
mov x0, #6
b return
core8:
mov x0, #8
b return
default:
and x0, x0, #15
return:
//bl cpu_id_mapping
mov lr, x9
RET
#endif

63
bsp/phytium/board/secondary_cpu.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -22,6 +22,7 @@
#include "cpuport.h"
#include "gtimer.h"
#include "mmu.h"
#include "cp15.h"
#endif
#ifdef RT_USING_SMP
@ -29,6 +30,9 @@
#if defined(TARGET_ARMV8_AARCH64)
#include "psci.h"
extern void _secondary_cpu_entry(void);
#else
extern void rt_secondary_cpu_entry(void);
#endif
#include "fpsci.h"
@ -39,10 +43,10 @@ rt_uint64_t rt_cpu_mpidr_early[] =
[0] = 0x80000200,
[1] = 0x80000201,
#elif defined(TARGET_E2000Q)
[0] = 0x80000200,
[1] = 0x80000201,
[2] = 0x80000000,
[3] = 0x80000100,
[0] = 0x80000000,
[1] = 0x80000100,
[2] = 0x80000200,
[3] = 0x80000201,
#elif defined(TARGET_F2000_4) || defined(TARGET_D2000)
[0] = 0x80000000,
[1] = 0x80000001,
@ -59,53 +63,66 @@ rt_uint64_t rt_cpu_mpidr_early[] =
};
extern int rt_hw_timer_init(void);
extern void secondary_cpu_start(void);
#include "fcache.h"
void rt_hw_secondary_cpu_up(void)
{
rt_uint32_t i;
rt_uint32_t cpu_mask = 0;
int cpu_id;
cpu_id = rt_hw_cpu_id();
rt_kprintf("rt_hw_secondary_cpu_up is processing \r\n");
for (i = 1; i < RT_CPUS_NR; i++)
for (i = 0; i < RT_CPUS_NR;i++)
{
if(i == cpu_id)
{
continue;
}
cpu_mask = 1 << phytium_cpu_id_mapping(i);
/* code */
PsciCpuOn(cpu_mask, (uintptr)secondary_cpu_start);
#if defined(TARGET_ARMV8_AARCH64)
/* code */
char *entry = (char *)_secondary_cpu_entry;
entry += PV_OFFSET;
PsciCpuOn(cpu_mask, (uintptr)entry);
__DSB();
#else
/* code */
PsciCpuOn(cpu_mask, (uintptr)rt_secondary_cpu_entry);
__asm__ volatile("dsb" ::: "memory");
#endif
}
}
void secondary_cpu_c_start(void)
void rt_hw_secondary_cpu_bsp_start(void)
{
/* mmu init */
#if defined(TARGET_ARMV8_AARCH64)
rt_hw_mmu_init();
#endif
/* spin lock init */
rt_hw_spin_lock(&_cpus_lock);
/* mmu init */
#if defined(TARGET_ARMV8_AARCH64)
extern unsigned long MMUTable[];
rt_hw_mmu_ktbl_set((unsigned long)MMUTable);
#endif
/* vector init */
rt_hw_vector_init();
/* interrupt init */
#if defined(TARGET_ARMV8_AARCH64)
arm_gic_cpu_init(0, platform_get_gic_cpu_base());
arm_gic_redist_init(0, platform_get_gic_redist_base());
arm_gic_cpu_init(0, 0);
arm_gic_redist_init(0, 0);
rt_kprintf("arm_gic_redist_init is over rt_hw_cpu_id() is %d \r\n", rt_hw_cpu_id());
#else
arm_gic_cpu_init(0);
arm_gic_redist_init(0);
#endif
/* vector init */
rt_hw_vector_init();
/* gtimer init */
#if defined(TARGET_ARMV8_AARCH64)
rt_hw_gtimer_local_enable();
rt_hw_gtimer_init();
#else
rt_hw_timer_init();
#endif

6
bsp/phytium/libraries/.ignore_format.yml Normal file
View File

@ -0,0 +1,6 @@
# files format check exclude path, please follow the instructions below to modify;
# If you need to exclude an entire folder, add the folder path in dir_path;
# If you need to exclude a file, add the path to the file in file_path.
dir_path:
- standalone

65
bsp/phytium/libraries/SConscript
View File

@ -8,66 +8,83 @@ STANDALONE_DIR = cwd + '/standalone'
# common source
src = Glob(STANDALONE_DIR+'/common/*.c')
path = [STANDALONE_DIR + '/common']
# arch
path += [STANDALONE_DIR + '/arch/common']
# port
src += Glob(STANDALONE_DIR+'/port/*.c')
path += [STANDALONE_DIR + '/port'] + [STANDALONE_DIR + '/port/arch']
if GetDepend(['TARGET_ARMV8_AARCH32']):
src += Glob(STANDALONE_DIR+'/arch/armv8/aarch32/*.c') + Glob(STANDALONE_DIR+'/arch/armv8/aarch32/gcc/*.S')
path += [STANDALONE_DIR + '/arch/armv8/aarch32']
src += Glob(STANDALONE_DIR+'/port/arch/armv8/aarch32/*.c') + Glob(STANDALONE_DIR+'/port/arch/armv8/aarch32/*.S')
path += [STANDALONE_DIR + '/port/arch/armv8/aarch32']
elif GetDepend(['TARGET_ARMV8_AARCH64']):
src += Glob(STANDALONE_DIR+'/arch/armv8/aarch64/*.c') + Glob(STANDALONE_DIR+'/arch/armv8/aarch64/gcc/*.S')
path += [STANDALONE_DIR + '/arch/armv8/aarch64']
src += Glob(STANDALONE_DIR+'/port/arch/armv8/aarch64/*.c') + Glob(STANDALONE_DIR+'/port/arch/armv8/aarch64/*.S')
path += [STANDALONE_DIR + '/port/arch/armv8/aarch64']
# board
src += Glob(STANDALONE_DIR+'/board/common/*.c') + Glob(STANDALONE_DIR+'/board/common/*.S')
path += [STANDALONE_DIR + '/board/common']
path += [STANDALONE_DIR + '/board/common']
if GetDepend(['TARGET_F2000_4']):
src += Glob(STANDALONE_DIR+'/board/ft2004/*.c')
path += [STANDALONE_DIR + '/board/ft2004']
path += [STANDALONE_DIR + '/board/ft2004']
if GetDepend(['TARGET_E2000']):
src += Glob(STANDALONE_DIR+'/board/e2000/*.c')
path += [STANDALONE_DIR + '/board/e2000']
path += [STANDALONE_DIR + '/board/e2000']
if GetDepend(['TARGET_E2000Q']):
src += Glob(STANDALONE_DIR+'/board/e2000/q/*.c')
path += [STANDALONE_DIR + '/board/e2000/q']
path += [STANDALONE_DIR + '/board/e2000/q']
if GetDepend(['TARGET_E2000D']):
src += Glob(STANDALONE_DIR+'/board/e2000/d/*.c')
path += [STANDALONE_DIR + '/board/e2000/d']
path += [STANDALONE_DIR + '/board/e2000/d']
if GetDepend(['ARGET_E2000S']):
src += Glob(STANDALONE_DIR+'/board/e2000/s/*.c')
path += [STANDALONE_DIR + '/board/e2000/s']
path += [STANDALONE_DIR + '/board/e2000/s']
if GetDepend(['TARGET_D2000']):
src += Glob(STANDALONE_DIR+'/board/d2000/*.c')
path += [STANDALONE_DIR + '/board/d2000']
path += [STANDALONE_DIR + '/board/d2000']
# driver
## spim
if GetDepend(['BSP_USING_SPI']):
src += Glob(STANDALONE_DIR+'/drivers/spi/fspim/*.c')
path += [STANDALONE_DIR + '/drivers/spi/fspim']
## serial
if GetDepend(['ENABLE_Pl011_UART']):
if GetDepend(['BSP_USING_UART']):
src += Glob(STANDALONE_DIR+'/drivers/serial/fpl011/*.c')
path += [STANDALONE_DIR + '/drivers/serial/fpl011']
path += [STANDALONE_DIR + '/drivers/serial/fpl011']
## gicv3
if GetDepend(['ENABLE_GICV3']):
src += Glob(STANDALONE_DIR+'/drivers/gic/fgic/*.c') + Glob(STANDALONE_DIR+'/drivers/gic/fgic/*.S')
path += [STANDALONE_DIR + '/drivers/gic/fgic']
## can
if GetDepend(['BSP_USING_CAN']):
src += Glob(STANDALONE_DIR+'/drivers/can/fcan/*.c') + Glob(STANDALONE_DIR+'/drivers/can/fcan/*.S')
path += [STANDALONE_DIR + '/drivers/can/fcan/']
## qspi
if GetDepend(['BSP_USING_QSPI']):
src += Glob(STANDALONE_DIR+'/drivers/qspi/fqspi/*.c') + Glob(STANDALONE_DIR+'/drivers/qspi/fqspi/*.S')
path += [STANDALONE_DIR + '/drivers/qspi/fqspi/']
# phytium ports rt-thread drivers
PORT_DRV_DIR = cwd + '/drivers'
src += Glob(PORT_DRV_DIR + '/*.S')
src += Glob(PORT_DRV_DIR + '/*.c')
src += Glob(PORT_DRV_DIR + '/*.c')
# phytium ports rt-thread examples
PORT_DRV_DIR = cwd + '/examples'
src += Glob(PORT_DRV_DIR + '/*.c')
# sdkcomfig.h
path += [cwd]
# add group
ASFLAGS = ''
group = DefineGroup('FT_DRIVER', src, depend=[
''], CPPPATH=path, ASFLAGS = ASFLAGS)

37
bsp/phytium/libraries/drivers/Kconfig
View File

@ -5,20 +5,53 @@ menu "On-chip Peripheral Drivers"
bool "Enable UART"
default y
select USE_SERIAL # sdk serial component
select ENABLE_Pl011_UART # select sdk pl011 driver
select RT_USING_SERIAL
if BSP_USING_UART
config RT_USING_UART1
bool "Enable UART1"
default y
config RT_USING_UART0
bool "Enable UART0"
default n
endif
menuconfig BSP_USING_SPI
bool "Enable Spi"
default y
select USE_SPI # sdk spi component
select RT_USING_SPI
if BSP_USING_SPI
config RT_USING_SPIM0
bool "Enable spim0"
default n
config RT_USING_SPIM1
bool "Enable spim1"
default n
config RT_USING_SPIM2
bool "Enable spim2"
default y
config RT_USING_SPIM3
bool "Enable spim3"
default n
endif
menuconfig BSP_USING_CAN
bool "Enable CAN"
default y
select RT_USING_CAN
select RT_CAN_USING_HDR
select RT_CAN_USING_CANFD
menuconfig BSP_USING_QSPI
bool "Enable QSPI"
default y
select RT_USING_QSPI
select RT_USING_SPI
endmenu

594
bsp/phytium/libraries/drivers/drv_can.c Normal file
View File

@ -0,0 +1,594 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Email: opensource_embedded@phytium.com.cn
*
* Change Logs:
* Date Author Notes
* 2023-03-20 zhangyan first version
*
*/
#include "drv_can.h"
#include "sdkconfig.h"
#ifdef RT_USING_CAN
#include "fdebug.h"
#include "fpinctrl.h"
#define FCAN_TEST_DEBUG_TAG "FCAN_TEST"
#define FCAN_TEST_DEBUG(format, ...) FT_DEBUG_PRINT_D(FCAN_TEST_DEBUG_TAG, format, ##__VA_ARGS__)
#define FCAN_TEST_INFO(format, ...) FT_DEBUG_PRINT_I(FCAN_TEST_DEBUG_TAG, format, ##__VA_ARGS__)
#define FCAN_TEST_WARN(format, ...) FT_DEBUG_PRINT_W(FCAN_TEST_DEBUG_TAG, format, ##__VA_ARGS__)
#define FCAN_TEST_ERROR(format, ...) FT_DEBUG_PRINT_E(FCAN_TEST_DEBUG_TAG, format, ##__VA_ARGS__)
struct phytium_can
{
const char *name;
FCanCtrl can_handle;
FCanIdMaskConfig filter;
struct rt_can_device device; /* inherit from can device */
};
static struct phytium_can drv_can[FCAN_NUM] =
{
{
.name = "CAN0",
.can_handle.config.instance_id = 0,
},
{
.name = "CAN1",
.can_handle.config.instance_id = 1,
},
#if defined(CONFIG_TARGET_F2000_4) || defined(CONFIG_TARGET_D2000)
{
.name = "CAN2",
.can_handle.config.instance_id = 2,
},
#endif
};
static void CanRxIrqCallback(void *args)
{
FCanCtrl *instance_p = (FCanCtrl *)args;
rt_hw_can_isr(&drv_can[instance_p->config.instance_id].device, RT_CAN_EVENT_RX_IND);
FCAN_TEST_DEBUG("CAN%d irq recv frame callback.", instance_p->config.instance_id);
}
static void CanErrorCallback(void *args)
{
FCanCtrl *instance_p = (FCanCtrl *)args;
uintptr base_addr = instance_p->config.base_address;
FCAN_TEST_DEBUG("CAN %d is under error.", instance_p->config.instance_id);
FCAN_TEST_DEBUG("error_status is %x.", FCAN_READ_REG32(base_addr, FCAN_INTR_OFFSET));
FCAN_TEST_DEBUG("rxerr_cnt is %x.", FCAN_ERR_CNT_RFN_GET(FCAN_READ_REG32(base_addr, FCAN_ERR_CNT_OFFSET)));
FCAN_TEST_DEBUG("txerr_cnt is %x.", FCAN_ERR_CNT_TFN_GET(FCAN_READ_REG32(base_addr, FCAN_ERR_CNT_OFFSET)));
}
static void CanTxIrqCallback(void *args)
{
FCanCtrl *instance_p = (FCanCtrl *)args;
rt_hw_can_isr(&drv_can[instance_p->config.instance_id].device, RT_CAN_EVENT_TX_DONE);
FCAN_TEST_DEBUG("CAN%d irq send frame callback.", instance_p->config.instance_id);
}
static rt_err_t _can_config(struct rt_can_device *can, struct can_configure *cfg)
{
RT_ASSERT(can);
RT_ASSERT(cfg);
struct phytium_can *drv_can;
drv_can = (struct phytium_can *)can->parent.user_data;
RT_ASSERT(drv_can);
FError status = FT_SUCCESS;
rt_kprintf("CAN%d begin to config.\n", drv_can->can_handle.config.instance_id);
#if defined(CONFIG_TARGET_F2000_4) || defined(CONFIG_TARGET_D2000)
if(drv_can->can_handle.config.instance_id == FCAN_INSTANCE_0)
{
FPinSetFunc(FIOCTRL_TJTAG_TDI_PAD, FPIN_FUNC1); /* can0-tx: func 1 */
FPinSetFunc(FIOCTRL_SWDITMS_SWJ_PAD, FPIN_FUNC1); /* can0-rx: func 1 */
}
else if(drv_can->can_handle.config.instance_id == FCAN_INSTANCE_1)
{
FPinSetFunc(FIOCTRL_NTRST_SWJ_PAD, FPIN_FUNC1); /* can1-tx: func 1 */
FPinSetFunc(FIOCTRL_SWDO_SWJ_PAD, FPIN_FUNC1); /* can1-rx: func 1 */
}
else
{
FCAN_TEST_ERROR("CAN id is under error.");
return RT_ERROR;
}
#elif defined(CONFIG_TARGET_E2000)
FIOPadSetCanMux(drv_can->can_handle.config.instance_id);
#endif
/*CAN config init*/
status = FCanCfgInitialize(&(drv_can->can_handle), FCanLookupConfig(drv_can->can_handle.config.instance_id));
if (status != FT_SUCCESS)
{
FCAN_TEST_DEBUG("CAN %d initialize error, status = %#x.", drv_can->can_handle.config.instance_id, status);
return RT_ERROR;
}
/*Set the baudrate*/
FCanBaudrateConfig arb_segment_config;
FCanBaudrateConfig data_segment_config;
memset(&arb_segment_config, 0, sizeof(arb_segment_config));
memset(&data_segment_config, 0, sizeof(data_segment_config));
#if defined(RT_CAN_USING_CANFD)
arb_segment_config.auto_calc = TRUE;
arb_segment_config.baudrate = CAN1MBaud; /*CANFD arb baud defaults to 1M ,allowed to be modified*/
arb_segment_config.segment = FCAN_ARB_SEGMENT;
status = FCanBaudrateSet(&(drv_can->can_handle), &arb_segment_config);
if (status != RT_EOK)
{
FCAN_TEST_DEBUG("CAN%d set arb segment baudrate failed.", drv_can->can_handle.config.instance_id);
return RT_ERROR;
}
data_segment_config.auto_calc = TRUE;
data_segment_config.baudrate = cfg->baud_rate_fd;
data_segment_config.segment = FCAN_DATA_SEGMENT;
status = FCanBaudrateSet(&(drv_can->can_handle), &data_segment_config);
if (status != RT_EOK)
{
FCAN_TEST_DEBUG("CAN%d set data segment baudrate failed.", drv_can->can_handle.config.instance_id);
return RT_ERROR;
}
#else
arb_segment_config.auto_calc = TRUE;
arb_segment_config.baudrate = cfg->baud_rate;
arb_segment_config.segment = FCAN_ARB_SEGMENT;
status = FCanBaudrateSet(&(drv_can->can_handle), &arb_segment_config);
if (status != FT_SUCCESS)
{
FCAN_TEST_DEBUG("CAN%d set arb segment baudrate failed.", drv_can->can_handle.config.instance_id);
return RT_ERROR;
}
data_segment_config.auto_calc = TRUE;
data_segment_config.baudrate = cfg->baud_rate;
data_segment_config.segment = FCAN_DATA_SEGMENT;
status = FCanBaudrateSet(&(drv_can->can_handle), &data_segment_config);
if (status != FT_SUCCESS)
{
FCAN_TEST_DEBUG("CAN%d set data segment baudrate failed.", drv_can->can_handle.config.instance_id);
return RT_ERROR;
}
#endif
/*CAN filter function init*/
for (int i = 0; i < FCAN_ACC_ID_REG_NUM; i++)
{
drv_can->filter.filter_index = i;
drv_can->filter.id = 0;
drv_can->filter.mask = FCAN_ACC_IDN_MASK;
status |= FCanIdMaskFilterSet(&(drv_can->can_handle), &(drv_can->filter));
}
if (status != FT_SUCCESS)
{
FCAN_TEST_ERROR("CAN%d set mask filter failed.", drv_can->can_handle.config.instance_id);
return RT_ERROR;
}
/* Identifier mask enable */
FCanIdMaskFilterEnable(&(drv_can->can_handle));
/* Transmit mode init , the default setting is normal mode */
FCanSetMode(&(drv_can->can_handle), FCAN_PROBE_NORMAL_MODE);
/* enable can transfer */
FCanEnable(&(drv_can->can_handle), RT_TRUE);
return RT_EOK;
}
static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg)
{
RT_ASSERT(can);
rt_uint32_t argval;
struct phytium_can *drv_can;
drv_can = (struct phytium_can *)can->parent.user_data;
RT_ASSERT(drv_can != RT_NULL);
rt_uint32_t cpu_id;
FCanIntrEventConfig intr_event;
FError status = FT_SUCCESS;
#ifdef RT_CAN_USING_HDR
struct rt_can_filter_config *filter_cfg;
#endif
switch (cmd)
{
case RT_DEVICE_CTRL_SET_INT:
GetCpuId(&cpu_id);
rt_hw_interrupt_set_target_cpus(drv_can->can_handle.config.irq_num, cpu_id);
argval = (rt_uint32_t) arg;
/*Open different interrupts*/
if (argval == RT_DEVICE_CAN_INT_ERR)
{
intr_event.type = FCAN_INTR_EVENT_ERROR;
intr_event.handler = CanErrorCallback;
intr_event.param = (void *)(&(drv_can->can_handle));
FCanRegisterInterruptHandler(&(drv_can->can_handle), &intr_event);
FCanInterruptEnable(&(drv_can->can_handle), intr_event.type);
}
if (argval == RT_DEVICE_FLAG_INT_TX)
{
intr_event.type = FCAN_INTR_EVENT_SEND;
intr_event.handler = CanTxIrqCallback;
intr_event.param = (void *)(&(drv_can->can_handle));
FCanRegisterInterruptHandler(&(drv_can->can_handle), &intr_event);
FCanInterruptEnable(&(drv_can->can_handle), intr_event.type);
}
if (argval == RT_DEVICE_FLAG_INT_RX)
{
intr_event.type = FCAN_INTR_EVENT_RECV;
intr_event.handler = CanRxIrqCallback;
intr_event.param = (void *)(&(drv_can->can_handle));
FCanRegisterInterruptHandler(&(drv_can->can_handle), &intr_event);
FCanInterruptEnable(&(drv_can->can_handle), intr_event.type);
}
rt_hw_interrupt_set_priority(drv_can->can_handle.config.irq_num, 16);
rt_hw_interrupt_install(drv_can->can_handle.config.irq_num, FCanIntrHandler, &(drv_can->can_handle), drv_can->name);
rt_hw_interrupt_umask(drv_can->can_handle.config.irq_num);
break;
case RT_CAN_CMD_SET_MODE:
argval = (rt_uint32_t) arg;
FCanEnable(&(drv_can->can_handle), RT_FALSE);
if (argval == RT_CAN_MODE_LISTEN)
{
FCanSetMode(&(drv_can->can_handle), FCAN_PROBE_MONITOR_MODE);
drv_can->device.config.mode = RT_CAN_MODE_LISTEN;
}
else if (argval == RT_CAN_MODE_NORMAL)
{
FCanSetMode(&(drv_can->can_handle), FCAN_PROBE_NORMAL_MODE);
drv_can->device.config.mode = RT_CAN_MODE_NORMAL;
}
FCanEnable(&(drv_can->can_handle), RT_TRUE);
break;
case RT_CAN_CMD_SET_BAUD:
argval = (rt_uint32_t) arg;
if (argval != CAN1MBaud &&
argval != CAN800kBaud &&
argval != CAN500kBaud &&
argval != CAN250kBaud &&
argval != CAN125kBaud &&
argval != CAN100kBaud &&
argval != CAN50kBaud &&
argval != CAN20kBaud &&
argval != CAN10kBaud)
{
return RT_ERROR;
}
if (argval != drv_can->device.config.baud_rate)
{
FCanBaudrateConfig arb_segment_config;
FCanBaudrateConfig data_segment_config;
memset(&arb_segment_config, 0, sizeof(arb_segment_config));
memset(&data_segment_config, 0, sizeof(data_segment_config));
drv_can->device.config.baud_rate = argval;
FCanEnable(&(drv_can->can_handle), RT_FALSE);
arb_segment_config.auto_calc = TRUE;
arb_segment_config.baudrate = drv_can->device.config.baud_rate;
arb_segment_config.segment = FCAN_ARB_SEGMENT;
status = FCanBaudrateSet(&(drv_can->can_handle), &arb_segment_config);
if (status != FT_SUCCESS)
{
FCAN_TEST_DEBUG("CAN%d set arb segment baudrate failed.", drv_can->can_handle.config.instance_id);
return RT_ERROR;
}
data_segment_config.auto_calc = TRUE;
data_segment_config.baudrate = drv_can->device.config.baud_rate;
data_segment_config.segment = FCAN_DATA_SEGMENT;
status = FCanBaudrateSet(&(drv_can->can_handle), &data_segment_config);
if (status != FT_SUCCESS)
{
FCAN_TEST_DEBUG("CAN%d set data segment baudrate failed.", drv_can->can_handle.config.instance_id);
return RT_ERROR;
}
FCanEnable(&(drv_can->can_handle), RT_TRUE);
}
break;
case RT_CAN_CMD_SET_BAUD_FD:
#if defined RT_CAN_USING_CANFD
argval = (rt_uint32_t) arg;
if (argval != drv_can->device.config.baud_rate_fd)
{
FCanBaudrateConfig arb_segment_config;
FCanBaudrateConfig data_segment_config;
memset(&arb_segment_config, 0, sizeof(arb_segment_config));
memset(&data_segment_config, 0, sizeof(data_segment_config));
drv_can->device.config.baud_rate = argval;
FCanEnable(&(drv_can->can_handle), RT_FALSE);
arb_segment_config.auto_calc = TRUE;
arb_segment_config.baudrate = CAN1MBaud;
arb_segment_config.segment = FCAN_ARB_SEGMENT;
status = FCanBaudrateSet(&(drv_can->can_handle), &arb_segment_config);
if (status != FT_SUCCESS)
{
FCAN_TEST_DEBUG("CAN%d set arb segment baudrate failed.", drv_can->can_handle.config.instance_id);
return RT_ERROR;
}
data_segment_config.auto_calc = TRUE;
data_segment_config.baudrate = drv_can->device.config.baud_rate_fd;
data_segment_config.segment = FCAN_DATA_SEGMENT;
status = FCanBaudrateSet(&(drv_can->can_handle), &data_segment_config);
if (status != FT_SUCCESS)
{
FCAN_TEST_DEBUG("CAN%d set data segment baudrate failed.", drv_can->can_handle.config.instance_id);
return RT_ERROR;
}
FCanEnable(&(drv_can->can_handle), RT_TRUE);
}
#endif
break;
case RT_CAN_CMD_SET_FILTER:
#ifdef RT_CAN_USING_HDR
filter_cfg = (struct rt_can_filter_config *)arg;
FCanEnable(&(drv_can->can_handle), RT_FALSE);
for (int i = 0; i < filter_cfg->count; i++)
{
drv_can->filter.filter_index = i;
drv_can->filter.mask = filter_cfg->items[i].mask;
drv_can->filter.id = filter_cfg->items[i].id;
drv_can->filter.type = FCAN_STANDARD_FRAME;
status = FCanIdMaskFilterSet(&(drv_can->can_handle), &(drv_can->filter));
if (status != FT_SUCCESS)
{
FCAN_TEST_ERROR("CAN%d set mask filter failed.", drv_can->can_handle.config.instance_id);
return RT_ERROR;
}
}
FCanEnable(&(drv_can->can_handle), RT_TRUE);
#endif
break;
}
return RT_EOK;
}
static int _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t box_num)
{
RT_ASSERT(can);
RT_ASSERT(buf);
struct phytium_can *drv_can;
drv_can = (struct phytium_can *)can->parent.user_data;
RT_ASSERT(drv_can);
struct rt_can_msg *pmsg = (struct rt_can_msg *)buf;
FCanFrame can_frame = {0};
/* Check the parameters */
RT_ASSERT(pmsg->len <= 8U);
if (RT_CAN_STDID == pmsg->ide)
{
can_frame.canid = pmsg->id;
}
else
{
can_frame.canid = pmsg->id;
can_frame.canid |= CAN_EFF_FLAG;
}
if (RT_CAN_DTR == pmsg->rtr)
{
}
else
{
can_frame.canid |= CAN_RTR_FLAG;
}
can_frame.candlc = pmsg->len ;
memcpy(can_frame.data, pmsg->data, 8);
return (FCanSend(&drv_can->can_handle, &can_frame) == RT_EOK) ? RT_EOK : -RT_ERROR;
}
static int _can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t fifo)
{
RT_ASSERT(can);
RT_ASSERT(buf);
struct phytium_can *drv_can;
drv_can = (struct phytium_can *)can->parent.user_data;
RT_ASSERT(drv_can);
struct rt_can_msg *pmsg = (struct rt_can_msg *)buf;
FCanFrame recv_frame;
FError status = FT_SUCCESS;
status = FCanRecv(&(drv_can->can_handle), &recv_frame);
if (status != FT_SUCCESS)
{
FCAN_TEST_DEBUG("CAN%d recv data failed.", drv_can->can_handle.config.instance_id);
return RT_ERROR;
}
if (CAN_EFF_FLAG & recv_frame.canid)
{
pmsg->ide = RT_CAN_EXTID;
pmsg->id = (recv_frame.canid & ~(RT_CAN_EXTID));
}
else
{
pmsg->ide = RT_CAN_STDID;
pmsg->id = recv_frame.canid;
}
if (CAN_RTR_FLAG & recv_frame.canid)
{
pmsg->id &= ~CAN_RTR_FLAG;
pmsg->rtr = RT_CAN_RTR;
}
else
{
pmsg->rtr = RT_CAN_DTR;
}
/* get len */
pmsg->len = recv_frame.candlc;
for (int i = 0; i < pmsg->len; i++)
{
pmsg->data[i] = recv_frame.data[i];
}
/* get hdr */
pmsg->hdr = 0;
return RT_EOK;
}
static const struct rt_can_ops _can_ops =
{
_can_config,
_can_control,
_can_sendmsg,
_can_recvmsg,
};
int rt_hw_can_init(void)
{
rt_err_t ret = RT_EOK;
for (int i = 0; i < (u32)FCAN_NUM; i++)
{
drv_can[i].device.config.ticks = 20000;
drv_can[i].device.config.baud_rate = 800000;
#ifdef RT_CAN_USING_CANFD
drv_can[i].device.config.baud_rate_fd = 800000;
#endif
drv_can[i].device.config.mode = RT_CAN_MODE_NORMAL;
drv_can[i].device.config.sndboxnumber = 1;
drv_can[i].device.config.msgboxsz = 1;
#ifdef RT_CAN_USING_HDR
drv_can[i].device.config.maxhdr = 1;
#endif
ret = rt_hw_can_register(&drv_can[i].device,
drv_can[i].name,
&_can_ops,
&drv_can[i]);
RT_ASSERT(ret == RT_EOK);
}
return (int)ret;
}
INIT_BOARD_EXPORT(rt_hw_can_init);
/*can test example*/
static rt_device_t can_dev; /* CAN device handle */
static struct rt_semaphore rx_sem;
static rt_err_t can_rx_call(rt_device_t dev, rt_size_t size)
{
/* The CAN generates an interrupt after receiving data, calls this callback function, and then sends the received semaphore */
rt_sem_release(&rx_sem);
return RT_EOK;
}
static void can_rx_thread(void *parameter)
{
int i;
rt_err_t res = RT_EOK;
struct rt_can_msg rxmsg = {0};
rt_device_set_rx_indicate(can_dev, can_rx_call);
while (1)
{
/* The hdr value is - 1, which means reading data directly from the uselist */
rxmsg.hdr = -1;
/* Blocking waiting to receive semaphore */
res = rt_sem_take(&rx_sem, RT_WAITING_FOREVER);
RT_ASSERT(res == RT_EOK);
/* Read a frame of data from CAN */
rt_device_read(can_dev, 0, &rxmsg, sizeof(rxmsg));
/* Print data ID and conten */
rt_kprintf("ID:%x\n", rxmsg.id);
rt_kprintf("DATA: ");
for (i = 0; i < 8; i++)
{
rt_kprintf("%2x ", rxmsg.data[i]);
}
rt_kprintf("\n");
}
}
int can_sample(int argc, char *argv[])
{
struct rt_can_msg msg = {0};
rt_err_t res = RT_EOK;;
rt_size_t size;
rt_thread_t thread;
char can_name[RT_NAME_MAX];
if (argc == 2)
{
rt_strncpy(can_name, argv[1], RT_NAME_MAX);
}
else
{
rt_strncpy(can_name, "CAN0", RT_NAME_MAX);
}
/* Find CAN device */
can_dev = rt_device_find(can_name);
if (!can_dev)
{
rt_kprintf("Find %s failed.\n", can_name);
return RT_ERROR;
}
/* Initialize CAN receive signal quantity */
res = rt_sem_init(&rx_sem, "rx_sem", 0, RT_IPC_FLAG_FIFO);
RT_ASSERT(res == RT_EOK);
/* Open the CAN device in the way of interrupt reception and transmission */
res = rt_device_open(can_dev, RT_DEVICE_FLAG_INT_TX | RT_DEVICE_FLAG_INT_RX);
rt_device_control(can_dev,RT_CAN_CMD_SET_BAUD, CAN1MBaud);
RT_ASSERT(res == RT_EOK);
#ifdef RT_CAN_USING_HDR
struct rt_can_filter_item items[4] =
{
RT_CAN_FILTER_ITEM_INIT(0x3, 0, 0, 0, 0, RT_NULL, RT_NULL),
RT_CAN_FILTER_ITEM_INIT(0x3, 0, 0, 0, 0, RT_NULL, RT_NULL),
RT_CAN_FILTER_ITEM_INIT(0x3, 0, 0, 0, 0, RT_NULL, RT_NULL),
RT_CAN_FILTER_ITEM_INIT(0x3, 0, 0, 0, 0, RT_NULL, RT_NULL)
};
struct rt_can_filter_config cfg = {4, 1, items}; /* There are 4 filter tables in total */
/* Set the hardware filter table. After setting, only frames with id=0x03 can be received*/
res = rt_device_control(can_dev, RT_CAN_CMD_SET_FILTER, &cfg);
RT_ASSERT(res == RT_EOK);
#endif
/* Create data receiving thread */
thread = rt_thread_create("can_rx", can_rx_thread, RT_NULL, 1024, 25, 10);
if (thread != RT_NULL)
{
res = rt_thread_startup(thread);
RT_ASSERT(res == RT_EOK);
}
else
{
rt_kprintf("Create can_rx thread failed.\n");
}
msg.id = 0x78; /* ID = 0x78 */
msg.ide = RT_CAN_STDID; /* Standard format */
msg.rtr = RT_CAN_RTR; /* Data frame */
msg.len = 8; /* Data length is 8 */
/* Send CAN data */
for (int i = 0; i < 10; i++)
{
/* 8-byte data to be sent */
msg.data[0] = 0x00+i;
msg.data[1] = 0x11+i;
msg.data[2] = 0x22+i;
msg.data[3] = 0x33+i;
msg.data[4] = 0x44+i;
msg.data[5] = 0x55+i;
msg.data[6] = 0x66+i;
msg.data[7] = 0x77+i;
rt_device_write(can_dev, 0, &msg, sizeof(msg));
}
return res;
}
/* Enter can_sample command for testing */
MSH_CMD_EXPORT(can_sample, can device sample);
#endif

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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Email: opensource_embedded@phytium.com.cn
*
* Change Logs:
* Date Author Notes
* 2023-03-20 zhangyan first version
*
*/
#ifndef __DRV_CAN_H__
#define __DRV_CAN_H__
#include <rtdevice.h>
#ifdef RT_USING_CAN
#include "fcan.h"
#ifdef __cplusplus
extern "C"
{
#endif
int rt_hw_can_init(void);
#ifdef __cplusplus
}
#endif
#endif
#endif /* __DRV_CAN_H__ */

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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Email: opensource_embedded@phytium.com.cn
*
* Change Logs:
* Date Author Notes
* 2023-03-20 zhangyan first version
*
*/
#include "drv_qspi.h"
#include "sdkconfig.h"
#ifdef RT_USING_QSPI
#include <rtthread.h>
#include "rtdevice.h"
#include "fqspi_flash.h"
#include "fdebug.h"
#include "fpinctrl.h"
#define FQSPI_DEBUG_TAG "FQSPI"
#define FQSPI_ERROR(format, ...) FT_DEBUG_PRINT_E(FQSPI_DEBUG_TAG, format, ##__VA_ARGS__)
#define FQSPI_WARN(format, ...) FT_DEBUG_PRINT_W(FQSPI_DEBUG_TAG, format, ##__VA_ARGS__)
#define FQSPI_INFO(format, ...) FT_DEBUG_PRINT_I(FQSPI_DEBUG_TAG, format, ##__VA_ARGS__)
#define FQSPI_DEBUG(format, ...) FT_DEBUG_PRINT_D(FQSPI_DEBUG_TAG, format, ##__VA_ARGS__)
#define DAT_LENGTH 128
struct phytium_qspi_bus
{
char *name;
rt_uint32_t init; /* 0 is init already */
FQspiCtrl fqspi;
struct rt_spi_bus qspi_bus;
};
static struct phytium_qspi_bus phytium_qspi; /* phytium qspi bus handle */
static struct rt_qspi_device *qspi_device; /* phytium device bus handle */
static char qspi_bus_name[RT_NAME_MAX] = "QSPIBUS";
static char qspi_dev_name[RT_NAME_MAX] = "QSPIDEV";
rt_err_t FQspiInit(FQspiCtrl *fqspi)
{
u32 qspi_id = FQSPI0_ID;
FError ret = FT_SUCCESS;
#if defined(CONFIG_TARGET_E2000)
FIOPadSetQspiMux(qspi_id, FQSPI_CS_0);
FIOPadSetQspiMux(qspi_id, FQSPI_CS_1);
#endif
FQspiDeInitialize(fqspi);
FQspiConfig pconfig = *FQspiLookupConfig(qspi_id);
/* Norflash init, include reset and read flash_size */
ret = FQspiCfgInitialize(fqspi, &pconfig);
if (FT_SUCCESS != ret)
{
FQSPI_DEBUG("Qspi init failed.\n");
return RT_ERROR;
}
else
{
FQSPI_DEBUG("Qspi init successfully.\n");
}
/* Detect connected flash infomation */
ret = FQspiFlashDetect(fqspi);
if (FT_SUCCESS != ret)
{
FQSPI_DEBUG("Qspi flash detect failed.\n");
return RT_ERROR;
}
else
{
FQSPI_DEBUG("Qspi flash detect successfully.\n");
}
return RT_EOK;
}
static rt_err_t phytium_qspi_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration)
{
RT_ASSERT(device != RT_NULL);
RT_ASSERT(configuration != RT_NULL);
struct phytium_qspi_bus *qspi_bus;
qspi_bus = (struct phytium_qspi_bus *) device->bus->parent.user_data;
rt_err_t ret = RT_EOK;
ret = FQspiInit(&(qspi_bus->fqspi));
if (RT_EOK != ret)
{
qspi_bus->init = RT_FALSE;
FQSPI_DEBUG("Qspi init failed!!!\n");
return RT_ERROR;
}
qspi_bus->init = RT_EOK;
return RT_EOK;
}
static rt_uint32_t phytium_qspi_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
{
RT_ASSERT(device != RT_NULL);
RT_ASSERT(message != RT_NULL);
struct phytium_qspi_bus *qspi_bus;
struct rt_qspi_message *qspi_message = (struct rt_qspi_message *)message;
rt_uint32_t cmd = qspi_message->instruction.content;
rt_uint32_t flash_addr = qspi_message->address.content;
rt_uint8_t *rcvb = message->recv_buf;
rt_uint8_t *sndb = message->send_buf;
FError ret = FT_SUCCESS;
qspi_bus = (struct phytium_qspi_bus *) device->bus->parent.user_data;
/*Distinguish the write mode according to different commands*/
if (cmd == FQSPI_FLASH_CMD_PP||cmd == FQSPI_FLASH_CMD_QPP||cmd ==FQSPI_FLASH_CMD_4PP||cmd ==FQSPI_FLASH_CMD_4QPP )
{
char *strs = (char *)message->send_buf;
rt_uint8_t len = strlen(strs) + 1;
rt_uint8_t *wr_buf = NULL;
wr_buf = (rt_uint8_t *)rt_malloc(DAT_LENGTH * sizeof(rt_uint8_t));
rt_memcpy(wr_buf, strs, len);
message->length = len;
ret = FQspiFlashErase(&(qspi_bus->fqspi), FQSPI_FLASH_CMD_SE, flash_addr);
if (FT_SUCCESS != ret)
{
FQSPI_DEBUG("Failed to erase mem, test result 0x%x.\r\n", ret);
return RT_ERROR;
}
/* write norflash data */
ret = FQspiFlashWriteData(&(qspi_bus->fqspi), cmd, flash_addr, wr_buf, len);
if (FT_SUCCESS != ret)
{
FQSPI_DEBUG("Failed to write mem, test result 0x%x.\r\n", ret);
return RT_ERROR;
}
else
{
rt_kprintf("Write successfully!!!\r\n");
}
rt_free(wr_buf);
return RT_EOK;
}
/*Distinguish the read mode according to different commands*/
if (cmd == FQSPI_FLASH_CMD_READ||cmd == FQSPI_FLASH_CMD_4READ||cmd == FQSPI_FLASH_CMD_FAST_READ||cmd == FQSPI_FLASH_CMD_4FAST_READ||
cmd == FQSPI_FLASH_CMD_DUAL_READ||cmd == FQSPI_FLASH_CMD_QIOR||cmd == FQSPI_FLASH_CMD_4QIOR)
{
rt_uint8_t *rd_buf = NULL;
rd_buf = (rt_uint8_t *)rt_malloc(DAT_LENGTH * sizeof(rt_uint8_t));
ret |= FQspiFlashReadDataConfig(&(qspi_bus->fqspi), cmd);
if (FT_SUCCESS != ret)
{
FQSPI_DEBUG("Failed to config read, test result 0x%x.\r\n", ret);
return RT_ERROR;
}
/* read norflash data */
size_t read_len = FQspiFlashReadData(&(qspi_bus->fqspi), flash_addr, rd_buf, DAT_LENGTH);
message->length = read_len;
if (read_len != DAT_LENGTH)
{
FQSPI_DEBUG("Failed to read mem, read len = %d.\r\n", read_len);
return RT_ERROR;
}
else
{
rt_kprintf("Read successfully!!!\r\n");
message->recv_buf = rd_buf;
rt_free(rd_buf);
}
FtDumpHexByte(message->recv_buf, DAT_LENGTH);
return RT_EOK;
}
if (rcvb)
{
if (cmd == FQSPI_FLASH_CMD_RDID||cmd == FQSPI_FLASH_CMD_RDSR1||cmd == FQSPI_FLASH_CMD_RDSR2 ||cmd == FQSPI_FLASH_CMD_RDSR3)
{
ret |= FQspiFlashSpecialInstruction(&(qspi_bus->fqspi), cmd, rcvb, sizeof(rcvb));
if (FT_SUCCESS != ret)
{
FQSPI_DEBUG("Failed to read flash information.\n");
return RT_ERROR;
}
}
return RT_EOK;
}
if (sndb)
{
ret |= FQspiFlashEnableWrite(&(qspi_bus->fqspi));
if (FT_SUCCESS != ret)
{
FQSPI_DEBUG("Failed to enable flash reg write.\n");
return RT_ERROR;
}
ret |= FQspiFlashWriteReg(&(qspi_bus->fqspi), cmd, sndb, 1);
if (FT_SUCCESS != ret)
{
FQSPI_DEBUG("Failed to write flash reg.\n");
return RT_ERROR;
}
return RT_EOK;
}
}
static struct rt_spi_ops phytium_qspi_ops =
{
.configure = phytium_qspi_configure,
.xfer = phytium_qspi_xfer,
};
rt_err_t phytium_qspi_bus_attach_device(const char *bus_name, const char *device_name)
{
struct rt_qspi_device *qspi_device;
rt_err_t result = RT_EOK;
RT_ASSERT(bus_name != RT_NULL);
RT_ASSERT(device_name != RT_NULL);
qspi_device = (struct rt_qspi_device *)rt_malloc(sizeof(struct rt_qspi_device));
if (qspi_device == RT_NULL)
{
FQSPI_DEBUG("Qspi bus attach device failed.");
result = RT_ENOMEM;
goto __exit;
}
result = rt_spi_bus_attach_device(&(qspi_device->parent), device_name, bus_name, RT_NULL);
__exit:
if (result != RT_EOK)
{
if (qspi_device)
{
rt_free(qspi_device);
}
return result;
}
}
int rt_hw_qspi_init(void)
{
int i = 0;
int result = RT_EOK;
phytium_qspi.qspi_bus.parent.user_data = &phytium_qspi;
if(rt_qspi_bus_register(&phytium_qspi.qspi_bus, qspi_bus_name , &phytium_qspi_ops) == RT_EOK)
{
rt_kprintf("Qspi bus register successfully!!!\n");
}
else
{
FQSPI_DEBUG("Qspi bus register Failed!!!\n");
result = -RT_ERROR;
}
return result;
}
INIT_BOARD_EXPORT(rt_hw_qspi_init);
/*example*/
struct rt_spi_message write_message;
struct rt_spi_message read_message;
rt_err_t qspi_init()
{
rt_err_t res = RT_EOK;
res = phytium_qspi_bus_attach_device(qspi_bus_name, qspi_dev_name);
RT_ASSERT(res == RT_EOK);
qspi_device = (struct rt_qspi_device *)rt_device_find(qspi_dev_name);
return res;
}
/*read cmd example message improvement*/
void ReadCmd(struct rt_spi_message *spi_message)
{
struct rt_qspi_message *message = (struct rt_qspi_message*) spi_message;
message->address.content = 0x360000 ;/*Flash address*/
message->instruction.content = 0x03 ;/*read cmd*/
rt_qspi_transfer_message(qspi_device, message);
}
/*write cmd example message improvement*/
void WriteCmd(struct rt_spi_message *spi_message)
{
struct rt_qspi_message *message = (struct rt_qspi_message*) spi_message;
message->address.content = 0x360000 ;/*Flash address*/
message->instruction.content = 0x02 ;/*write cmd*/
rt_qspi_transfer_message(qspi_device, message);
}
/*write cmd example message improvement*/
void qspi_thread(void *parameter)
{
rt_err_t res;
qspi_init();
/*Read and write flash chip fixed area repeatedly*/
write_message.send_buf = "111111111111111111111111";
WriteCmd(&write_message);
ReadCmd(&read_message);
write_message.send_buf = "222222222222222222222222";
WriteCmd(&write_message);
ReadCmd(&read_message);
write_message.send_buf = "333333333333333333333333";
WriteCmd(&write_message);
ReadCmd(&read_message);
rt_uint8_t recv;
rt_uint8_t cmd = 0x9F;/*read the flash status reg2*/
res = rt_qspi_send_then_recv(qspi_device, &cmd, sizeof(cmd), &recv, sizeof(recv));
RT_ASSERT(res!=RT_EOK);
rt_kprintf("The status reg = %x \n" ,recv);
return 0;
}
rt_err_t qspi_sample(int argc, char *argv[])
{
rt_thread_t thread;
rt_err_t res;
thread = rt_thread_create("qspi_thread", qspi_thread, RT_NULL, 1024, 25, 10);
res = rt_thread_startup(thread);
RT_ASSERT(res==RT_EOK);
return res;
}
/* Enter qspi_sample command for testing */
MSH_CMD_EXPORT(qspi_sample, qspi sample);
#endif

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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Email: opensource_embedded@phytium.com.cn
*
* Change Logs:
* Date Author Notes
* 2023-03-20 zhangyan first version
*
*/
#ifndef __DRT_QSPI_H__
#define __DRT_QSPI_H__
#include <rtthread.h>
#ifdef RT_USING_QSPI
#define PHYTIUM_QSPI_NAME "qspi"
#ifdef __cplusplus
extern "C"
{
#endif
rt_err_t phytium_qspi_bus_attach_device(const char *bus_name, const char *device_name);
#ifdef __cplusplus
}
#endif
#endif
#endif // !DRT_QSPI_H

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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Email: opensource_embedded@phytium.com.cn
*
* Change Logs:
* Date Author Notes
* 2022-11-10 liqiaozhong first commit
* 2023-03-08 liqiaozhong support 4 spis and qspi working together
*
*/
#include <rtthread.h>
#include <rtdevice.h>
#include "interrupt.h"
#include <string.h>
#include "fdebug.h"
#if defined(TARGET_E2000)
#include "fparameters.h"
#endif
#include "fcpu_info.h"
#include "fkernel.h"
#include "ftypes.h"
#include "fsleep.h"
#ifdef RT_USING_SPI
#include <dfs_file.h>
#include "fspim.h"
#include "fspim_hw.h" /* include low-level header file for internal probe */
#include "drv_spi.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/************************** Variable Definitions *****************************/
#ifdef RT_USING_SPIM0
static struct drv_spi _RTSpim0;
#endif
#ifdef RT_USING_SPIM1
static struct drv_spi _RTSpim1;
#endif
#ifdef RT_USING_SPIM2
static struct drv_spi _RTSpim2;
#endif
#ifdef RT_USING_SPIM3
static struct drv_spi _RTSpim3;
#endif
static struct rt_spi_device *spi_device = RT_NULL;
static struct rt_event rx_done_event;
/***************** Macros (Inline Functions) Definitions *********************/
#define FSPIM_DEBUG_TAG "SPIM"
#define FSPIM_ERROR(format, ...) FT_DEBUG_PRINT_E(FSPIM_DEBUG_TAG, format, ##__VA_ARGS__)
#define FSPIM_WARN(format, ...) FT_DEBUG_PRINT_W(FSPIM_DEBUG_TAG, format, ##__VA_ARGS__)
#define FSPIM_INFO(format, ...) FT_DEBUG_PRINT_I(FSPIM_DEBUG_TAG, format, ##__VA_ARGS__)
#define FSPIM_DEBUG(format, ...) FT_DEBUG_PRINT_D(FSPIM_DEBUG_TAG, format, ##__VA_ARGS__)
#define EVENT_RX_DONE (1 << 1)
/*******************************Api Functions*********************************/
static rt_err_t spim_configure(struct rt_spi_device* device, struct rt_spi_configuration* configuration);
static rt_uint32_t spim_xfer(struct rt_spi_device* device, struct rt_spi_message* message);
static FError FSpimSetupInterrupt(FSpim *instance_p)
{
FASSERT(instance_p);
FSpimConfig *config_p = &instance_p->config;
uintptr base_addr = config_p->base_addr;
u32 cpu_id = 0;
GetCpuId(&cpu_id);
FSPIM_DEBUG("cpu_id is %d, irq_num is %d\n", cpu_id, config_p->irq_num);
config_p->irq_prority = 0xd0;
rt_hw_interrupt_set_target_cpus(config_p->irq_num, cpu_id);
rt_hw_interrupt_set_priority(config_p->irq_num, config_p->irq_prority);
/* register intr callback */
rt_hw_interrupt_install(config_p->irq_num,
FSpimInterruptHandler,
instance_p,
NULL);
/* enable tx fifo overflow / rx overflow / rx full */
FSpimMaskIrq(base_addr, FSPIM_IMR_ALL_BITS);
/* enable irq */
rt_hw_interrupt_umask(config_p->irq_num);
return FSPIM_SUCCESS;
}
static void rt_ft_send_event_done(void *instance_p, void *param)
{
FASSERT(instance_p);
rt_event_send(&rx_done_event, EVENT_RX_DONE);
return;
}
static const struct rt_spi_ops spim_ops =
{
.configure = spim_configure,
.xfer = spim_xfer
};
static rt_err_t spim_configure(struct rt_spi_device *device,
struct rt_spi_configuration *configuration)
{
FError ret = FSPIM_SUCCESS;
RT_ASSERT(device != RT_NULL);
RT_ASSERT(configuration != RT_NULL);
struct drv_spi *user_data_cfg = device->parent.user_data;
FSpimConfig input_cfg = *FSpimLookupConfig(user_data_cfg->spi_id);
FSpimConfig *set_input_cfg = &input_cfg;
/* set fspim device according to configuration */
if (configuration->mode & RT_SPI_CPOL)
{
set_input_cfg->cpol = FSPIM_CPOL_HIGH;
}
else
{
set_input_cfg->cpol = FSPIM_CPOL_LOW;
}
if (configuration->mode & RT_SPI_CPHA)
{
set_input_cfg->cpha = FSPIM_CPHA_2_EDGE;
}
else
{
set_input_cfg->cpha = FSPIM_CPHA_1_EDGE;
}
if (configuration->data_width == 8)
{
set_input_cfg->n_bytes = FSPIM_1_BYTE;
}
else if (configuration->data_width == 16)
{
set_input_cfg->n_bytes = FSPIM_2_BYTE;
}
/* send spi_cfg to RT-Thread sys */
ret = FSpimCfgInitialize(&user_data_cfg->spim_instance, &input_cfg);
if (FSPIM_SUCCESS != ret)
return RT_ERROR;
/* irq setting */
ret = FSpimSetupInterrupt(&user_data_cfg->spim_instance);
if (FSPIM_SUCCESS != ret)
return RT_ERROR;
FSpimRegisterIntrruptHandler(&user_data_cfg->spim_instance, FSPIM_INTR_EVT_RX_DONE, rt_ft_send_event_done, NULL);
return ret;
}
static rt_uint32_t spim_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
{
RT_ASSERT(device != RT_NULL);
RT_ASSERT(device->parent.user_data != RT_NULL);
RT_ASSERT(message != RT_NULL);
rt_size_t message_length;
rt_uint8_t *recv_buf;
const rt_uint8_t *send_buf;
/* recv spi_cfg from RT-Thread sys */
struct drv_spi *user_data_xfer = device->parent.user_data;
FSpim *xfer_spim_instance = &user_data_xfer->spim_instance;
FError tx_rx_result = FSPIM_SUCCESS;
message_length = message->length;
recv_buf = message->recv_buf;
send_buf = message->send_buf;
if (message->cs_take)
{
FSpimSetChipSelection(xfer_spim_instance, TRUE);
}
if (message_length > 0)
{
if (send_buf == RT_NULL && recv_buf != RT_NULL)
{
/* receive message */
tx_rx_result = FSpimTransferByInterrupt(xfer_spim_instance, RT_NULL, recv_buf, message_length);
}
else if (send_buf != RT_NULL && recv_buf == RT_NULL)
{
/* send message */
tx_rx_result = FSpimTransferByInterrupt(xfer_spim_instance, send_buf, RT_NULL, message_length);
}
else if (send_buf != RT_NULL && recv_buf != RT_NULL)
{
/* not supported yet */
rt_kprintf("Do not support the situation that send_buf and recv_buf both not equal to 0.");
}
}
if (FSPIM_SUCCESS != tx_rx_result)
{
rt_kprintf("FSpimTransferByInterrupt() fail!!!");
message_length = 0;
}
if (rt_event_recv(&rx_done_event, (EVENT_RX_DONE),
(RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR),
RT_WAITING_FOREVER, RT_NULL) != RT_EOK)
{
rt_kprintf("Wait rx timeout!!!\n");
message_length = 0;
}
if (message->cs_release)
{
FSpimSetChipSelection(xfer_spim_instance, FALSE);
}
return message_length;
}
int ft_spi_init(void)
{
rt_err_t result;
static struct rt_spi_bus spim_bus;
/* event creat */
if (RT_EOK != rt_event_init(&rx_done_event, "rx_done_event", RT_IPC_FLAG_FIFO))
{
rt_kprintf("Create event failed.\n");
return RT_ERROR;
}
/* spi bus init */
result = rt_spi_bus_register(&spim_bus, "spi0", &spim_ops);
RT_ASSERT((struct rt_spi_device *)rt_device_find("spi0"));
rt_kprintf("Spi bus spi0 init\n");
/* spi device init and attach to bus */
#ifdef RT_USING_SPIM0
_RTSpim0.spi_id = FSPI0_ID;
result = rt_spi_bus_attach_device(&_RTSpim0.device, "spi00", "spi0", &_RTSpim0);
spi_device = (struct rt_spi_device *)rt_device_find("spi00");
if (RT_NULL == spi_device)
{
rt_kprintf("Spi init failed -> can't find spi00 device!\n");
return RT_ERROR;
}
rt_kprintf("Spi master device spi00 init.\n");
#endif
#ifdef RT_USING_SPIM1
_RTSpim1.spi_id = FSPI1_ID;
result = rt_spi_bus_attach_device(&_RTSpim1.device, "spi01", "spi0", &_RTSpim1);
spi_device = (struct rt_spi_device *)rt_device_find("spi01");
if (RT_NULL == spi_device)
{
rt_kprintf("Spi init failed -> can't find spi01 device!\n");
return RT_ERROR;
}
rt_kprintf("Spi master device spi01 init.\n");
#endif
#ifdef RT_USING_SPIM2
_RTSpim2.spi_id = FSPI2_ID;
result = rt_spi_bus_attach_device(&_RTSpim2.device, "spi02", "spi0", &_RTSpim2);
spi_device = (struct rt_spi_device *)rt_device_find("spi02");
if (RT_NULL == spi_device)
{
rt_kprintf("Spi init failed -> can't find spi02 device!\n");
return RT_ERROR;
}
rt_kprintf("Spi master device spi02 init.\n");
#endif
#ifdef RT_USING_SPIM3
_RTSpim3.spi_id = FSPI3_ID;
result = rt_spi_bus_attach_device(&_RTSpim3.device, "spi03", "spi0", &_RTSpim3);
spi_device = (struct rt_spi_device *)rt_device_find("spi03");
if (RT_NULL == spi_device)
{
rt_kprintf("Spi init failed -> can't find spi03 device!\n");
return RT_ERROR;
}
rt_kprintf("Spi master device spi03 init.\n");
#endif
return result;
}
INIT_DEVICE_EXPORT(ft_spi_init);
/* spi test example */
static void fspim_test_sample(int argc, char *argv[])
{
rt_uint8_t send_to_flash_id = 0x9f; /* Flash cmd */
rt_uint8_t recv_from_falsh_id1[5] = {0};
rt_uint8_t recv_from_falsh_id2[5] = {0};
/* find the spi device to get the device handle */
spi_device = (struct rt_spi_device *)rt_device_find("spi02");
if (!spi_device)
{
rt_kprintf("fspim_test_sample run failed! can't find spi02 device!\n");
}
else
{
static struct rt_spi_message msg1, msg2;
msg1.send_buf = &send_to_flash_id;
msg1.recv_buf = RT_NULL;
msg1.length = 1;
msg1.cs_take = 1;
msg1.cs_release = 0;
msg1.next = &msg2;
msg2.send_buf = RT_NULL;
msg2.recv_buf = recv_from_falsh_id2;
msg2.length = 5;
msg2.cs_take = 0;
msg2.cs_release = 1;
msg2.next = RT_NULL;
/* send the command to read the ID using rt_spi_send_then_recv() */
rt_spi_send_then_recv(spi_device, &send_to_flash_id, 1, recv_from_falsh_id1, 5);
rt_kprintf("use rt_spi_send_then_recv() read flash ID is:0x%x 0x%x 0x%x 0x%x 0x%x\n", recv_from_falsh_id1[0], recv_from_falsh_id1[1], recv_from_falsh_id1[2], recv_from_falsh_id1[3], recv_from_falsh_id1[4]);
/* send the command to read the ID using rt_spi_transfer_message() */
rt_spi_transfer_message(spi_device, &msg1);
rt_kprintf("use rt_spi_transfer_message() read flash ID is:0x%x 0x%x 0x%x 0x%x 0x%x\n", recv_from_falsh_id2[0], recv_from_falsh_id2[1], recv_from_falsh_id2[2], recv_from_falsh_id2[3], recv_from_falsh_id2[4]);
}
}
MSH_CMD_EXPORT(fspim_test_sample, "fspim test sample");
#endif

28
bsp/phytium/libraries/drivers/drv_spi.h Normal file
View File

@ -0,0 +1,28 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Email: opensource_embedded@phytium.com.cn
*
* Change Logs:
* Date Author Notes
* 2022-11-10 liqiaozhong first commit
* 2023-03-08 liqiaozhong support 4 spis and qspi working together
*/
#ifndef __DRV_SPI_H__
#define __DRV_SPI_H__
#include <rtthread.h>
struct drv_spi
{
u32 spi_id;
FSpim spim_instance;
struct rt_spi_device device;
};
#endif

46
bsp/phytium/libraries/drivers/drv_usart.c
View File

@ -8,10 +8,13 @@
* Change Logs:
* Date Author Notes
* 2022-10-26 huanghe first commit
*
* 2023-04-27 huanghe support RT-Smart
*/
#include "board.h"
#include <mmu.h>
#include "drv_usart.h"
#include "interrupt.h"
#include "fpl011.h"
@ -42,6 +45,10 @@ static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_co
uart_hw = uart->handle;
config = *(const FPl011Config *)FPl011LookupConfig(uart->config.uart_instance);
#ifdef RT_USING_SMART
config.base_address = (uintptr)rt_ioremap((void*)config.base_address, 0x1000);
#endif
RT_ASSERT(FPl011CfgInitialize(uart_hw, &config) == FT_SUCCESS);
FPl011SetHandler(uart_hw, Ft_Os_Uart_Callback, serial);
@ -129,13 +136,13 @@ static int uart_putc(struct rt_serial_device *serial, char c)
return 1;
}
u8 FPl011RecvByteNoBlocking(u32 addr)
u32 FPl011RecvByteNoBlocking(uintptr addr)
{
u32 recieved_byte;
while (FUART_ISRECEIVEDATA(addr))
while (FUART_RECEIVEDATAEMPTY(addr))
{
return 0xff;
return 0xffff;
}
recieved_byte = FUART_READREG32(addr, FPL011DR_OFFSET);
return recieved_byte;
@ -152,14 +159,13 @@ static int uart_getc(struct rt_serial_device *serial)
uart_ptr = uart->handle;
ch = FPl011RecvByteNoBlocking(uart_ptr->config.base_address);
if (ch == 0xff)
if (ch == 0xffff)
{
ch = -1;
rt_kprintf("") ;
}
else
{
//
ch &= 0xff;
}
return ch;
@ -176,6 +182,7 @@ static const struct rt_uart_ops _uart_ops =
#define RT_USING_UART0
#define RT_USING_UART1
#define RT_USING_UART2
#ifdef RT_USING_UART0
@ -188,6 +195,11 @@ static const struct rt_uart_ops _uart_ops =
static struct drv_usart _RtUart1;
#endif
#ifdef RT_USING_UART2
static FPl011 Ft_Uart2;
static struct drv_usart _RtUart2;
#endif
int rt_hw_uart_init(void)
{
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
@ -196,7 +208,6 @@ int rt_hw_uart_init(void)
config.bufsz = RT_SERIAL_RB_BUFSZ;
_RtUart0.serial.ops = &_uart_ops;
_RtUart0.serial.config = config;
// Ft_Uart0.config.instance_id = FUART0_ID;
_RtUart0.handle = &Ft_Uart0;
_RtUart0.config.uart_instance = FUART0_ID;
@ -213,7 +224,6 @@ int rt_hw_uart_init(void)
config.bufsz = RT_SERIAL_RB_BUFSZ;
_RtUart1.serial.ops = &_uart_ops;
_RtUart1.serial.config = config;
// Ft_Uart1.config.instance_id = FUART1_ID;
_RtUart1.handle = &Ft_Uart1;
_RtUart1.config.uart_instance = FUART1_ID;
@ -226,6 +236,24 @@ int rt_hw_uart_init(void)
&_RtUart1);
#endif
#ifdef RT_USING_UART2
config.bufsz = RT_SERIAL_RB_BUFSZ;
_RtUart2.serial.ops = &_uart_ops;
_RtUart2.serial.config = config;
_RtUart2.handle = &Ft_Uart2;
_RtUart2.config.uart_instance = FUART2_ID;
_RtUart2.config.isr_priority = 0xd0;
_RtUart2.config.isr_event_mask = (RTOS_UART_ISR_OEIM_MASK | RTOS_UART_ISR_BEIM_MASK | RTOS_UART_ISR_PEIM_MASK | RTOS_UART_ISR_FEIM_MASK | RTOS_UART_ISR_RTIM_MASK | RTOS_UART_ISR_RXIM_MASK);
_RtUart2.config.uart_baudrate = 115200;
rt_hw_serial_register(&_RtUart2.serial, "uart2",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
&_RtUart2);
#endif
return 0;
}
INIT_BOARD_EXPORT(rt_hw_uart_init);

2
bsp/phytium/libraries/drivers/drv_usart.h
View File

@ -8,7 +8,7 @@
* Change Logs:
* Date Author Notes
* 2022-10-26 huanghe first commit
*
* 2023-04-27 huanghe support RT-Smart
*/
#ifndef __DRV_USART_H__

22
bsp/phytium/libraries/drivers/drv_xmac.c Normal file
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@ -0,0 +1,22 @@
/*
* @Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* @FilePath: drv_xmac.c
* @Date: 2023-04-19 15:19:29
* @LastEditTime: 2023-04-19 15:19:29
* @Description: This file is for
*
* @Modify History:
* Ver Who Date Changes
* ----- ------ -------- --------------------------------------
*/

22
bsp/phytium/libraries/drivers/drv_xmac.h Normal file
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@ -0,0 +1,22 @@
/*
* @Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* @FilePath: drv_xmac.h
* @Date: 2023-04-19 15:19:39
* @LastEditTime: 2023-04-19 15:19:40
* @Description: This file is for
*
* @Modify History:
* Ver Who Date Changes
* ----- ------ -------- --------------------------------------
*/

79
bsp/phytium/libraries/examples/spi_sfud_sample.c Normal file
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@ -0,0 +1,79 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Email: opensource_embedded@phytium.com.cn
*
* Change Logs:
* Date Author Notes
* 2022-11-20 liqiaozhong first commit
* 2022-03-08 liqiaozhong add format function and mount table
*/
#include <rtthread.h>
#include <string.h>
#if defined (RT_USING_SFUD) && defined(RT_USING_DFS)
#include <dfs_fs.h>
#include <dfs_file.h>
#include <unistd.h>
#include <stdio.h>
#include <sys/stat.h>
#include <sys/statfs.h>
#include "spi_flash.h"
#include "spi_flash_sfud.h"
#include "fdebug.h"
#include "fparameters_comm.h"
#include "fspim.h"
/************************** Variable Definitions *****************************/
sfud_flash_t spim_flash = RT_NULL;
const struct dfs_mount_tbl mount_table[] =
{
{ "flash2", "/", "elm", 0, RT_NULL },
{0},
};
/***************** Macros (Inline Fungoctions) Definitions *********************/
#define FSPIM_DEBUG_TAG "SPIM"
#define FSPIM_ERROR(format, ...) FT_DEBUG_PRINT_E(FSPIM_DEBUG_TAG, format, ##__VA_ARGS__)
#define FSPIM_WARN(format, ...) FT_DEBUG_PRINT_W(FSPIM_DEBUG_TAG, format, ##__VA_ARGS__)
#define FSPIM_INFO(format, ...) FT_DEBUG_PRINT_I(FSPIM_DEBUG_TAG, format, ##__VA_ARGS__)
#define FSPIM_DEBUG(format, ...) FT_DEBUG_PRINT_D(FSPIM_DEBUG_TAG, format, ##__VA_ARGS__)
/*******************************Api Functions*********************************/
static int spi_flash_sfud_init(void)
{
if (RT_NULL == rt_sfud_flash_probe("flash2", "spi02"))
{
rt_kprintf("rt_sfud_flash_probe failed\n");
return RT_ERROR;
}
spim_flash = rt_sfud_flash_find_by_dev_name("flash2");
if (RT_NULL == spim_flash)
{
rt_kprintf("Flash init failed -> can't find flash2 device!\n");
return RT_ERROR;
}
rt_kprintf("Spi flash device flash2 init\n");
rt_kprintf("Flash device: flash2 info\nmf_id: 0x%x\ntype_id: 0x%x\ncapacity_id: 0x%x\nerase granularity: %lu\n",
spim_flash->chip.mf_id,
spim_flash->chip.type_id,
spim_flash->chip.capacity_id,
spim_flash->chip.erase_gran);
return RT_EOK;
}
INIT_DEVICE_EXPORT(spi_flash_sfud_init);
/* format the flash with elm environment */
static int flash_format_operation(void)
{
int result = RT_EOK;
result = dfs_mkfs("elm", "flash2");
return result;
}
INIT_ENV_EXPORT(flash_format_operation);
#endif /* RT_USING_SFUD || RT_USING_DFS */

85
bsp/phytium/libraries/standalone/README.md
View File

@ -1,17 +1,23 @@
# Phytium-Standalone-SDK
**v0.3.1** [ReleaseNote](./doc/ChangeLog.md)
**v1.0.0** [ReleaseNote](./doc/ChangeLog.md)
## 1. 项目概要
### 1.1 基本介绍
### 1.1 仓库介绍
本项目代码仓库整体共分为两个分支：
master 分支：开发分支，用于保存最新的协作开发代码以及bug修复后的代码。其只要求保障新功能基本正确并且能够满足基本的使用需求，并没有经过系统性和复杂条件下的测试。
release 分支：发布分支，包含核心启动代码、芯片外设驱动、用户使用例程和构建的脚本工具。用于保存经过系统性测试的代码并对外发布版本，默认下载此分支的代码。
### 1.2 基本介绍
本项目发布了 Phytium 系列 CPU 的 嵌入式软件开发工具包，包括板级支持包、第三方开源中间件、交叉编译构建工具、及其 Baremetal 参考例程，在支持多平台裸机应用开发的基础上，能够为多种RTOS提供外设驱动和配置构建工具。
![LetterShell](./doc/fig/letter_shell.png)
### 1.2 系统架构
### 1.3 系统架构
本项目的整体设计如下所示，自下而上可以分为平台层、组件层、框架层和应用层。
@ -26,7 +32,7 @@
- 应用层（Application）提供了应用开发模板和例程，帮助开发者迅速熟悉SDK的使用，进行不同类型的应用程序开发
### 1.3. 源代码结构
### 1.4 源代码结构
```
.
@ -105,9 +111,8 @@ FT-2000/4 是一款面向桌面应用的高性能通用 4 核处理器。每 2
- 集成 34 Lane PCIE3.0 接口：2 个 X16（每个可拆分成 2 个 X8），2 个 X1
- 集成 2 个 GMAC，RGMII 接口，支持 10/100/1000 自适应
- 集成 1 个 SD 卡控制器，兼容 SD 2.0 规范
- 集成 1 个 HDAudio，支持音频输出，可同时支持最多 4 个 Codec
- 集成 SM2、SM3、SM4 模块
- 集成 4 个 UART，1 个 LPC，32 个 GPIO，4 个 I2C，1 个 QSPI，2 个通 用 SPI，2 个 WDT，16 个外部中断（和 GPIO 共用 IO）
- 集成 加密计算单元
- 集成 4 个 UART，32 个 GPIO，4 个 I2C，1 个 QSPI，2 个通 用 SPI，2 个 WDT，16 个外部中断（和 GPIO 共用 IO）
- 集成温度传感器
### 3.2 D2000
@ -123,39 +128,55 @@ D2000 是一款面向桌面应用的高性能通用 8 核处理器。每 2 个
- 集成 1 个 SD 卡控制器，兼容 SD 2.0 规范
- 集成 1 个 HDAudio，支持音频输出，可同时支持最多 4 个 Codec
- 集成 SM2、SM3、SM4、SM9 模块
- 集成 4 个 UART，1 个 LPC，32 个 GPIO，4 个 I2C，1 个 QSPI，2 个通用 SPI，2 个 WDT，16 个外部中断（和 GPIO 共用 IO）
- 集成 4 个 UART，32 个 GPIO，4 个 I2C，1 个 QSPI，2 个通用 SPI，2 个 WDT，16 个外部中断（和 GPIO 共用 IO）
- 集成 2 个温度传感器
### 3.3 E2000Q
### 3.3 E2000D
- E2000D 1个cluster有2个cpu，共两核。主要技术特征如下：
- E2000Q 集成2个FTC664核和2个FTC310核。主要技术特征如下：
- 兼容ARM v8 64 位指令系统，兼容32 位指令
- 集成 1 路 16 通道 General DMA 和 1 路 8 通道 Device DMA
- 支持单精度、双精度浮点运算指令
- L1有32KB，L2有256KB
- 集成1个DDR4 通道，可对DDR 存储数据进行实时加密
- 集成4 Lane PCIE3.0 接口（4X1）
- 集成网络接口4x1000M SGMII，1路支持RGMII/RMII，支持1路TSN
- 集成2个USB2.0(OTG)接口
- 集成1个HDAudio，支持音频输出;2路DP显示接口
- 两个 FTC664 核各包含 1MB 私有 L2 Cache,由两个 FTC310 核组成的Cluster 内含 256KB 共享的 L2 Cache
- 集成1个DDR4 通道
- 集成6Lane PCIE3.0 接口（X4+2*X1 、X2+4*X2、6*X1）
- 集成4个1000M以太网控制器，支持2路SGMII接口和2路SGMII/RGMII接口
- 集成3路USB2.0(OTG)和2路USB3.0(兼容 2.0)
- 集成2路SATA3.0模块
- 集成常用低速接口：WDT，DMAC，QSPI，PWM，Nand，SD/SDIO/eMMC ，SPI_M，UART，I2C，MIO，CAN， LPC_M_S，GPIO，LBC，Timer
- 2路 DisplayPort1.4 接口
- 集成常用低速接口：WDT、QSPI、PWM、Nand、SD/SDIO/eMMC 、SPI_M、UART、I2C、I2S、MIO、CAN-FD、GPIO、LocalBus、Timer
### 3.4 E2000S
### 3.4 E2000D
- E2000S 1个cluster有1个cpu，单核结构。主要技术特征如下：
- E2000D 集成 2 个 FTC310 核。主要技术特征如下：
- 兼容ARM v8 64 位指令系统，兼容32 位指令
- 集成 1 路 16 通道 General DMA 和 1 路 8 通道 Device DMA
- 支持单精度、双精度浮点运算指令
- L1有32KB，L2有256KB
- 集成1个DDR4 通道，可对DDR 存储数据进行实时加密
- L2 Cache 有256KB
- 集成1个DDR4 通道
- 集成4 Lane PCIE3.0 接口（4X1）
- 集成4个1000M以太网控制器，支持 2 路 SGMII 接口和 2 路 SGMII/RGMII 接口
- 集成3路USB2.0(OTG)和2路USB3.0(兼容 2.0)
- 集成2路SATA3.0模块
- 2路 DisplayPort1.4 接口
- 集成常用低速接口：WDT，QSPI，PWM，Nand，SD/SDIO/eMMC ，SPI_M，UART，I2C，MIO，CAN-FD，GPIO，LocalBus，Timer
### 3.5 E2000S
- E2000S 集成 1 个 FTC310 核，单核结构。主要技术特征如下：
- 兼容ARM v8 64 位指令系统，兼容32 位指令
- 集成 1 路 16 通道 General DMA 和 1 路 8 通道 Device DMA
- 支持单精度、双精度浮点运算指令
- L2 Cache 有256KB
- 集成1个DDR4 通道
- 集成2 Lane PCIE3.0 接口（2X1）
- 集成网络接口2x1000M SGMII/RGMII/RMII，支持2路NCSI
- 集成2个USB2.0(OTG)接口
- 集成1个HDAudio，支持音频输出;2路DP显示接口
- 集成JPEG Encoder模块
- 集成常用低速接口：WDT，DMAC，PWM，QSPI，SD/SDIO/eMMC，SPI_M，UART，I2C，MIO，I3C，PMBUS， LPC_M_S，GPIO，oneWire，Timer
- 集成3个1000M以太网控制器，支持1路SGMII接口和2路RGMII/RMII接口
- 集成1路USB2.0(Device)和2路USB2.0(OTG)
- 2路 DisplayPort1.4 接口
- 集成常用低速接口：WDT、DMAC、PWM、QSPI、SD/SDIO/eMMC、SPI Master、UART、I2C、MIO、I3C、PMBUS、GPIO、SGPIO、One-Wire、Timer、One-Wire
## 4 外设驱动支持情况
@ -200,6 +221,7 @@ D2000 是一款面向桌面应用的高性能通用 8 核处理器。每 2 个
| OpenAMP | FT2000/4<br>D2000<br>E2000 | | openamp |
| LittleFS-2.4.2 | | FT2000/4<br>E2000<br>D2000 | littlefs-2.4.2 |
| SPIFFS-0.3.7 | FT2000/4<br>D2000<br>E2000 | | spiffs-0.3.7 |
| freemodbus-v1.6 | E2000 | | protocols/fmodbus_test |
---
@ -241,6 +263,8 @@ D2000 是一款面向桌面应用的高性能通用 8 核处理器。每 2 个
#### 5.1.17 [FSDIO](./doc/reference/driver/fsdio.md)
#### 5.1.18 [FMEDIA](doc/reference/driver/fmedia.md)
### 5.2 MEMORY
#### 5.2.1 [FMEMORY_POOL](./doc/reference/sdk/fmemory_pool.md)
@ -266,6 +290,13 @@ wangxiaodong1030@phytium.com.cn
liushengming1118@phytium.com.cn
wangzongqiang1322@phytium.com.cn
liqiaozhong1404@phytium.com.cn
liuzhihong1235@phytium.com.cn
zhangyan1491@phytium.com.cn
---

416
bsp/phytium/libraries/standalone/arch/armv8/aarch32/faarch32.h
View File

@ -1,416 +0,0 @@
/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: faarch32.h
* Date: 2022-02-10 14:53:41
* LastEditTime: 2022-02-17 17:28:37
* Description:  This files is for
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
* 1.0 Huanghe 2021/7/3 init
* 1.1 Wangxiaodong 2021/9/24 modify sys_icc_bpr_set and sys_icc_bpr_get
*/
#ifndef BSP_AARCH32_ASM_H
#define BSP_AARCH32_ASM_H
#ifdef __cplusplus
extern "C"
{
#endif
#include "ftypes.h"
#define __ASM __asm
#define __STATIC_INLINE static inline
#define __STRINGIFY(x) #x
/* C语言实现MCR指令 */
#define __MCR(coproc, opcode_1, src, CRn, CRm, opcode_2) \
__ASM volatile("MCR " __STRINGIFY(p##coproc) ", " __STRINGIFY(opcode_1) ", " \
"%0, " __STRINGIFY(c##CRn) ", " __STRINGIFY(c##CRm) ", " __STRINGIFY(opcode_2) \
: \
: "r"(src) \
: "memory");
/* C语言实现MRC指令 */
#define __MRC(coproc, opcode_1, CRn, CRm, opcode_2) \
( \
{ \
u32 __dst; \
__ASM volatile("MRC " __STRINGIFY(p##coproc) ", " __STRINGIFY(opcode_1) ", " \
"%0, " __STRINGIFY(c##CRn) ", " __STRINGIFY(c##CRm) ", " __STRINGIFY(opcode_2) \
: "=r"(__dst)::"memory"); \
__dst; \
})
/* C语言实现MRRC指令 */
#define __MRRC(coproc, opcode_1, dst_1, dst_2, CRm) ( \
{ \
__asm__ __volatile__( \
"MRRC " __STRINGIFY(p##coproc) ", " __STRINGIFY(opcode_1) ", " \
"%0,%1," __STRINGIFY(c##CRm) \
: "=r"(dst_1), "=r"(dst_2)); \
})
/**
* @name: aarch32_cntp_ctl_get
* @msg: Read the register that holds the timer value for the EL1 physical timer.
* @return {__STATIC_INLINEu32}: TimerValue, bits [31:0] The TimerValue view of the EL1 physical timer.
*/
__attribute__((always_inline)) __STATIC_INLINE u32 aarch32_cntp_ctl_get(void)
{
/* MRC p15(coproc) 0(opcode1) CR14(n) CR2(m) 1(opcode2) */
return __MRC(15, 0, 14, 2, 1);
}
/**
* @name: aarch32_cntp_tlb_get
* @msg:
* @return {*}
* @param {__STATIC_INLINE u32} aarch32_cntp_ctl_get
*/
__attribute__((always_inline)) __STATIC_INLINE u32 aarch32_cntp_tlb_get(void)
{
return __MRC(15, 0, 0, 2, 0);
}
/**
* @name: aarch32_cntp_ctl_set
* @msg: Read the register that holds the timer value for the EL1 physical timer.
* @return {__STATIC_INLINEu32}: TimerValue, bits [31:0] The TimerValue view of the EL1 physical timer.
*/
__attribute__((always_inline)) __STATIC_INLINE void aarch32_cntp_ctl_set(u32 regVal)
{
/* MRC p15(coproc) regVal 0(opcode1) CR14(n) CR2(m) 1(opcode2) */
__MCR(15, 0, regVal, 14, 2, 1);
}
/**
* @name: arm_aarch32_cntfrq_get
* @msg: This register is provided so that software can discover the frequency of the system counter.
* @return {__STATIC_INLINEu32}: frequency of the system counter
*/
__attribute__((always_inline)) __STATIC_INLINE u32 aarch32_cntfrq_get(void)
{
return __MRC(15, 0, 14, 0, 0);
}
/**
* @name: aarch32_cntpct_get
* @msg: get the 64-bit physical count value
* @return {*}
* @param {__STATIC_INLINE u64} aarch32_cntpct_get
*/
__attribute__((always_inline)) __STATIC_INLINE u64 aarch32_cntpct_get()
{
u64 cnt = 0;
u32 cnt_low = 0, cnt_high = 0;
__MRRC(15, 0, cnt_low, cnt_high, 14);
cnt = (u64)cnt_high << 32 | cnt_low;
return cnt;
}
/**
* @name: aarch32_cntp_tval_set
* @msg: write the register that control register for the EL1 physical timer.
* @in param {u32}: TimerValue, bits [31:0] The TimerValue view of the EL1 physical timer.
*/
__attribute__((always_inline)) __STATIC_INLINE void aarch32_cntp_tval_set(u32 RegValue)
{
__MCR(15, 0, RegValue, 14, 2, 0);
}
/**
* @name: aarch32_sctrl_get
* @msg: read the register that control system
*/
__attribute__((always_inline)) __STATIC_INLINE u32 aarch32_sctrl_get()
{
return __MRC(15, 0, 1, 0, 0);
}
/**
* @name: aarch32_sctrl_set
* @msg: read the register that control system
*/
#define AARCH32_SCTRL_CACHE_BIT (1 << 2) /* 1: enable, 0: disable */
__attribute__((always_inline)) __STATIC_INLINE void aarch32_sctrl_set(u32 RegVal)
{
__MCR(15, 0, RegVal, 1, 0, 0);
}
/**********************************************/
__attribute__((always_inline)) __STATIC_INLINE u32 __get_VBAR(void)
{
return __MRC(15, 0, 12, 0, 0);
}
__attribute__((always_inline)) __STATIC_INLINE void __set_VBAR(u32 vbar)
{
__MCR(15, 0, vbar, 12, 0, 0);
}
__attribute__((always_inline)) __STATIC_INLINE void sys_icc_igrpen0_set(u32 value)
{
__MCR(15, 0, value, 12, 12, 6);
}
__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_igrpen0_get(void)
{
return __MRC(15, 0, 12, 12, 6);
}
__attribute__((always_inline)) __STATIC_INLINE void sys_icc_igrpen1_set(u32 value)
{
__MCR(15, 0, value, 12, 12, 7);
}
__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_igrpen1_get(void)
{
return __MRC(15, 0, 12, 12, 7);
}
__attribute__((always_inline)) __STATIC_INLINE void sys_icc_ctlr_set(u32 value)
{
__MCR(15, 0, value, 12, 12, 4);
}
__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_ctlr_get(void)
{
return __MRC(15, 0, 12, 12, 4);
}
__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_hppir0_get(void)
{
return __MRC(15, 0, 12, 8, 2);
}
__attribute__((always_inline)) __STATIC_INLINE void sys_icc_bpr_set(u32 value)
{
__MCR(15, 0, value, 12, 12, 3);
}
__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_bpr_get(void)
{
return __MRC(15, 0, 12, 12, 3);
}
__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_hppir1_get(void)
{
return __MRC(15, 0, 12, 12, 2);
}
__attribute__((always_inline)) __STATIC_INLINE void sys_icc_eoir0_set(u32 value)
{
__MCR(15, 0, value, 12, 8, 1);
}
__attribute__((always_inline)) __STATIC_INLINE void sys_icc_eoir1_set(u32 value)
{
__MCR(15, 0, value, 12, 12, 1);
}
__attribute__((always_inline)) __STATIC_INLINE void sys_icc_pmr_set(u32 value)
{
__MCR(15, 0, value, 4, 6, 0);
}
__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_pmr_get(void)
{
return __MRC(15, 0, 4, 6, 0);
}
__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_iar1_get(void)
{
return __MRC(15, 0, 12, 12, 0);
}
__attribute__((always_inline)) __STATIC_INLINE void sys_icc_sre_set(u32 value)
{
__MCR(15, 0, value, 12, 12, 5);
}
__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_sre_get(void)
{
return __MRC(15, 0, 12, 12, 5);
}
__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_rpr_get(void)
{
return __MRC(15, 0, 12, 11, 3);
}
/* Generic Timer registers */
/**
* @name: arm_aarch32_cntfrq_get
* @msg: This register is provided so that software can discover the frequency of the system counter.
* @return {__STATIC_INLINEu32}: frequency of the system counter
*/
__attribute__((always_inline)) __STATIC_INLINE u32 arm_aarch32_cntfrq_get(void)
{
return __MRC(15, 0, 14, 0, 0);
}
/* arm_aarch32_cnttimer_set */
__attribute__((always_inline)) __STATIC_INLINE void arm_aarch32_cnttimer_set(u32 RegValue)
{
__MCR(15, 0, RegValue, 14, 2, 2);
}
/**
* @name: arm_aarch32_cnthv_tval_get
* @msg: Provides AArch32 access to the timer value for the EL2 virtual timer.
* @return {__STATIC_INLINEu32}: EL2 virtual timer Cnt.
*/
__attribute__((always_inline)) __STATIC_INLINE u32 arm_aarch32_cnthv_tval_get(void)
{
return __MRC(15, 0, 14, 3, 0);
}
/**
* @name: arm_aarch32_cnthv_ctl_set
* @msg: Provides AArch32 access to the control register for the EL2 virtual timer.
* @in param {u32}: RegValue;ENABLE: bit [0] 0 Timer disabled,1 Timer enabled.
* IMASK,bit [1]: 0 Timer interrupt is not masked by the IMASK bit. 1 Timer interrupt is masked by the IMASK bit.
* ISTATUS, bit [2]: 0 Timer condition is not met. 1 Timer condition is met. rea-only
*/
__attribute__((always_inline)) __STATIC_INLINE void arm_aarch32_cnthv_ctl_set(u32 RegValue)
{
__MCR(15, 0, RegValue, 14, 3, 1);
}
/**
* @name: arm_aarch32_cnthv_ctl_get
* @msg: Provides AArch32 access to the control register for the EL2 virtual timer.
* @return {__STATIC_INLINEu32}: RegValue;ENABLE: bit [0] 0 Timer disabled,1 Timer enabled.
* IMASK,bit [1]: 0 Timer interrupt is not masked by the IMASK bit. 1 Timer interrupt is masked by the IMASK bit.
* ISTATUS, bit [2]: 0 Timer condition is not met. 1 Timer condition is met. read-only
*/
__attribute__((always_inline)) __STATIC_INLINE u32 arm_aarch32_cnthv_ctl_get(void)
{
return __MRC(15, 0, 14, 3, 1);
}
/**
* @name: arm_aarch32_cnthv_tval_set
* @msg: Provides AArch32 access to the timer value for the EL2 virtual timer.
* @in param {u32}: TimerValue, bits [31:0] The TimerValue view of the EL2 virtual timer.
*/
__attribute__((always_inline)) __STATIC_INLINE void arm_aarch32_cnthv_tval_set(u32 RegValue)
{
__MCR(15, 0, RegValue, 14, 3, 0);
}
/**
* @name: arm_aarch32_cntvct_get
* @msg: Read the register that holds the 64-bit virtual count value. The virtual count value is equal to the physical count value visible in CNTPCT minus the virtual offset visible in CNTVOFF.
* @return {__STATIC_INLINEu64}Bits [63:0] Virtual count value.
*/
__attribute__((always_inline)) __STATIC_INLINE u64 arm_aarch32_cntvct_get(void)
{
/* "r0" --- low,
"r1" --- hi
*/
u32 low;
u32 hi;
__asm__ volatile(
".word 0xec510f1e \n" /* mrrc p15, 1, r0, r1, c14 */
"mov %0, r0 \n"
"mov %1, r1 \n"
: "=&r"(low), "=&r"(hi));
return (((u64)hi) << 32) | low;
}
/* physical */
/**
* @name: arm_aarch32_cntp_tval_get
* @msg: Read the register that holds the timer value for the EL1 physical timer.
* @return {__STATIC_INLINEu32}: TimerValue, bits [31:0] The TimerValue view of the EL1 physical timer.
*/
__attribute__((always_inline)) __STATIC_INLINE u32 arm_aarch32_cntp_tval_get(void)
{
return __MRC(15, 0, 14, 2, 0);
}
/**
* @name: arm_aarch32_cntp_tval_set
* @msg: write the register that control register for the EL1 physical timer.
* @in param {u32}: TimerValue, bits [31:0] The TimerValue view of the EL1 physical timer.
*/
__attribute__((always_inline)) __STATIC_INLINE void arm_aarch32_cntp_tval_set(u32 RegValue)
{
__MCR(15, 0, RegValue, 14, 2, 0);
}
/**
* @name: arm_aarch32_cntp_ctl_set
* @msg: write the register that control register for the EL1 physical timer.
* @in param {u32}: ENABLE, bit[0] Enables the timer ; IMASK, bit [1] Timer interrupt mask bit; ISTATUS, bit [2] The status of the timer.
*/
__attribute__((always_inline)) __STATIC_INLINE void arm_aarch32_cntp_ctl_set(u32 RegValue)
{
__MCR(15, 0, RegValue, 14, 2, 1);
}
/**
* @name: arm_aarch32_cntp_ctl_get
* @msg: Read the register that control register for the EL1 physical timer.
* @return {__STATIC_INLINEu32}: ENABLE, bit[0] Enables the timer ; IMASK, bit [1] Timer interrupt mask bit; ISTATUS, bit [2] The status of the timer.
*/
__attribute__((always_inline)) __STATIC_INLINE u32 arm_aarch32_cntp_ctl_get(void)
{
return __MRC(15, 0, 14, 2, 1);
}
/**
* @name: arm_aarch32_cntpct_get
* @msg: Read the register that holds the 64-bit physical count value.
* @return {__STATIC_INLINEu64} CompareValue, bits [63:0] Physical count value.
*/
__attribute__((always_inline)) __STATIC_INLINE u64 arm_aarch32_cntpct_get(void)
{
/* "r0" --- low,
"r1" --- hi
*/
u32 low;
u32 hi;
__asm__ volatile(
".word 0xec510f0e \n" /* mrrc p15, 0, r0, r1, c14 */
"mov %0, r0 \n"
"mov %1, r1 \n"
: "=&r"(low), "=&r"(hi));
return (((u64)hi) << 32) | low;
}
#define INTERRUPT_DISABLE() \
__asm volatile("CPSID i" :: \
: "memory"); \
__asm volatile("DSB"); \
__asm volatile("ISB");
#define INTERRUPT_ENABLE() \
__asm volatile("CPSIE i" :: \
: "memory"); \
__asm volatile("DSB"); \
__asm volatile("ISB");
#ifdef __cplusplus
}
#endif
#endif // !

154
bsp/phytium/libraries/standalone/arch/armv8/aarch32/fgeneric_timer.c
View File

@ -1,154 +0,0 @@
/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: generic_timer.c
* Date: 2022-02-10 14:53:41
* LastEditTime: 2022-02-17 17:30:07
* Description:  This files is for
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
*/
#include "fparameters.h"
#include "fgeneric_timer.h"
#include "faarch32.h"
#include "sdkconfig.h"
#ifndef SDK_CONFIG_H__
#warning "Please include sdkconfig.h"
#endif
#ifdef CONFIG_USE_SYS_TICK
#include "fassert.h"
#include "finterrupt.h"
static volatile u32 genericTick;
static GenericTimerTickHandler usr_tick_handler = NULL;
#endif
#define AARCH32_CNTP_CTL_ENABLE_MASK (1ul << 0)
#define AARCH32_CNTP_CTL_INTERRUPT_MASK (1ul << 1)
void GenericTimerStart(void)
{
u32 ctrl = aarch32_cntp_ctl_get();
if (!(ctrl & AARCH32_CNTP_CTL_ENABLE_MASK))
{
ctrl |= AARCH32_CNTP_CTL_ENABLE_MASK;
aarch32_cntp_ctl_set(ctrl);
}
}
void GenericTimerStop(void)
{
u32 ctrl = aarch32_cntp_ctl_get();
if ((ctrl & AARCH32_CNTP_CTL_ENABLE_MASK))
{
ctrl &= ~AARCH32_CNTP_CTL_ENABLE_MASK;
aarch32_cntp_ctl_set(ctrl);
}
}
void GenericTimerInterruptEnable(void)
{
u32 ctrl = aarch32_cntp_ctl_get();
if (ctrl & AARCH32_CNTP_CTL_INTERRUPT_MASK)
{
ctrl &= ~AARCH32_CNTP_CTL_INTERRUPT_MASK;
aarch32_cntp_ctl_set(ctrl);
}
}
void GenericTimerInterruptDisable(void)
{
u64 ctrl = aarch32_cntp_ctl_get();
if (!(ctrl & AARCH32_CNTP_CTL_INTERRUPT_MASK))
{
ctrl |= AARCH32_CNTP_CTL_INTERRUPT_MASK;
aarch32_cntp_ctl_set(ctrl);
}
}
u32 GenericTimerFrequecy(void)
{
u32 rate = aarch32_cntfrq_get();
return (rate != 0) ? rate : 1000000;
}
u64 GenericTimerRead(void)
{
return aarch32_cntpct_get();
}
void GenericTimerCompare(u32 interval)
{
aarch32_cntp_tval_set(interval);
}
#ifdef CONFIG_USE_SYS_TICK
static void GenericTimerClearTickIntr(u32 tickRateHz)
{
GenericTimerCompare(GenericTimerFrequecy() / tickRateHz);
}
static void GenericTimerTickIntrHandler(s32 vector, void *param)
{
u32 tickRateHz = (u32)param;
(void)vector;
genericTick++; /* tick */
GenericTimerClearTickIntr(tickRateHz); /* clear tick intrrupt */
if (usr_tick_handler) /* execute user handler */
usr_tick_handler();
}
#endif
void GenericTimerSetupSystick(u32 tickRateHz, GenericTimerTickHandler tickHandler, u32 intrPrority)
{
#ifdef CONFIG_USE_SYS_TICK
u32 cntFrq;
/* disable timer and get system frequency */
GenericTimerStop();
cntFrq = GenericTimerFrequecy();
/* set tick rate */
GenericTimerCompare(cntFrq / tickRateHz);
GenericTimerInterruptEnable();
/* set generic timer intrrupt */
InterruptSetPriority(GENERIC_TIMER_NS_IRQ_NUM, intrPrority);
/* install tick handler */
usr_tick_handler = tickHandler;
InterruptInstall(GENERIC_TIMER_NS_IRQ_NUM, GenericTimerTickIntrHandler,
(void *)tickRateHz, "GenericTimerTick");
/* enable intrrupt */
InterruptUmask(GENERIC_TIMER_NS_IRQ_NUM);
GenericTimerStart();
#endif
}
u32 GenericGetTick(void)
{
#ifdef CONFIG_USE_SYS_TICK
return genericTick;
#else
return 0xffU;
#endif
}

11
bsp/phytium/libraries/standalone/board/Kconfig
View File

@ -11,19 +11,22 @@ menu "Board Configuration"
config TARGET_D2000
bool "D2000"
config TARGET_E2000Q
bool "E2000Q"
select TARGET_E2000
config TARGET_E2000D
bool "E2000D"
select TARGET_E2000
config TARGET_E2000S
bool "E2000S"
select TARGET_E2000
# config TARGET_TARDIGRADE
# bool "TARDIGRADE"
endchoice # BUILD_TARGET_CHIP_TYPE
# an invisible config to define common code of E2000 Q/D/S
@ -43,7 +46,7 @@ menu "Board Configuration"
config DEFAULT_DEBUG_PRINT_UART2
bool "Use uart2"
endchoice # DEBUG_PRINT_UART
endmenu

2
bsp/phytium/libraries/standalone/board/common/fcpu_asm.S
View File

@ -14,7 +14,7 @@
* FilePath: _cpu_asm.S
* Date: 2022-02-10 14:53:42
* LastEditTime: 2022-02-17 17:57:55
* Description:  This files is for
* Description:  This file is for
*
* Modify History:
* Ver   Who        Date         Changes

216
bsp/phytium/libraries/standalone/board/common/fcpu_info.c
View File

@ -34,48 +34,48 @@ FError GetCpuId(u32 *cpu_id_p)
switch (affinity & 0xfff)
{
#ifdef CORE0_AFF
case CORE0_AFF:
*cpu_id_p = 0 ;
break;
case CORE0_AFF:
*cpu_id_p = 0 ;
break;
#endif
#ifdef CORE1_AFF
case CORE1_AFF:
*cpu_id_p = 1 ;
break;
case CORE1_AFF:
*cpu_id_p = 1 ;
break;
#endif
#ifdef CORE2_AFF
case CORE2_AFF:
*cpu_id_p = 2;
break;
case CORE2_AFF:
*cpu_id_p = 2;
break;
#endif
#ifdef CORE3_AFF
case CORE3_AFF:
*cpu_id_p = 3 ;
break;
case CORE3_AFF:
*cpu_id_p = 3 ;
break;
#endif
#ifdef CORE4_AFF
case CORE4_AFF:
*cpu_id_p = 4 ;
break;
case CORE4_AFF:
*cpu_id_p = 4 ;
break;
#endif
#ifdef CORE5_AFF
case CORE5_AFF:
*cpu_id_p = 5 ;
break;
case CORE5_AFF:
*cpu_id_p = 5 ;
break;
#endif
#ifdef CORE6_AFF
case CORE6_AFF:
*cpu_id_p = 6 ;
break;
case CORE6_AFF:
*cpu_id_p = 6 ;
break;
#endif
#ifdef CORE7_AFF
case CORE7_AFF:
*cpu_id_p = 7 ;
break;
case CORE7_AFF:
*cpu_id_p = 7 ;
break;
#endif
default:
ret = ERR_GENERAL ;
break;
default:
ret = ERR_GENERAL ;
break;
}
return ret;
}
@ -95,48 +95,48 @@ FError GetCpuAffinityByMask(u32 cpu_id_mask, u64 *affinity_level_p)
switch (cpu_id_mask)
{
#ifdef CORE0_AFF
case (1<<0):
*affinity_level_p = CORE0_AFF;
break ;
case (1<<0):
*affinity_level_p = CORE0_AFF;
break ;
#endif
#ifdef CORE1_AFF
case (1<<1):
*affinity_level_p = CORE1_AFF;
break ;
case (1<<1):
*affinity_level_p = CORE1_AFF;
break ;
#endif
#ifdef CORE2_AFF
case (1<<2):
*affinity_level_p = CORE2_AFF;
break ;
case (1<<2):
*affinity_level_p = CORE2_AFF;
break ;
#endif
#ifdef CORE3_AFF
case (1<<3):
*affinity_level_p = CORE3_AFF;
break ;
case (1<<3):
*affinity_level_p = CORE3_AFF;
break ;
#endif
#ifdef CORE4_AFF
case (1<<4):
*affinity_level_p = CORE4_AFF;
break ;
case (1<<4):
*affinity_level_p = CORE4_AFF;
break ;
#endif
#ifdef CORE5_AFF
case (1<<5):
*affinity_level_p = CORE5_AFF;
break ;
case (1<<5):
*affinity_level_p = CORE5_AFF;
break ;
#endif
#ifdef CORE6_AFF
case (1<<6):
*affinity_level_p = CORE6_AFF;
break ;
case (1<<6):
*affinity_level_p = CORE6_AFF;
break ;
#endif
#ifdef CORE7_AFF
case (1<<7):
*affinity_level_p = CORE7_AFF;
break ;
case (1<<7):
*affinity_level_p = CORE7_AFF;
break ;
#endif
default:
ret = ERR_GENERAL;
break;
default:
ret = ERR_GENERAL;
break;
}
return ret;
}
@ -157,48 +157,48 @@ FError GetCpuAffinity(u32 cpu_id, u64 *affinity_level_p)
switch (cpu_id)
{
#ifdef CORE0_AFF
case (0):
*affinity_level_p = CORE0_AFF;
break ;
case (0):
*affinity_level_p = CORE0_AFF;
break ;
#endif
#ifdef CORE1_AFF
case (1):
*affinity_level_p = CORE1_AFF;
break ;
case (1):
*affinity_level_p = CORE1_AFF;
break ;
#endif
#ifdef CORE2_AFF
case (2):
*affinity_level_p = CORE2_AFF;
break ;
case (2):
*affinity_level_p = CORE2_AFF;
break ;
#endif
#ifdef CORE3_AFF
case (3):
*affinity_level_p = CORE3_AFF;
break ;
case (3):
*affinity_level_p = CORE3_AFF;
break ;
#endif
#ifdef CORE4_AFF
case (4):
*affinity_level_p = CORE4_AFF;
break ;
case (4):
*affinity_level_p = CORE4_AFF;
break ;
#endif
#ifdef CORE5_AFF
case (5):
*affinity_level_p = CORE5_AFF;
break ;
case (5):
*affinity_level_p = CORE5_AFF;
break ;
#endif
#ifdef CORE6_AFF
case (6):
*affinity_level_p = CORE6_AFF;
break ;
case (6):
*affinity_level_p = CORE6_AFF;
break ;
#endif
#ifdef CORE7_AFF
case (7):
*affinity_level_p = CORE7_AFF;
break ;
case (7):
*affinity_level_p = CORE7_AFF;
break ;
#endif
default:
ret = ERR_GENERAL;
break;
default:
ret = ERR_GENERAL;
break;
}
return ret;
}
@ -217,48 +217,48 @@ FError UseAffinityGetCpuId(u64 affinity_level, u32 *cpu_id_p)
switch (affinity_level)
{
#ifdef CORE0_AFF
case CORE0_AFF:
*cpu_id_p = 0;
break ;
case CORE0_AFF:
*cpu_id_p = 0;
break ;
#endif
#ifdef CORE1_AFF
case CORE1_AFF:
*cpu_id_p = 1;
break ;
case CORE1_AFF:
*cpu_id_p = 1;
break ;
#endif
#ifdef CORE2_AFF
case CORE2_AFF:
*cpu_id_p = 2;
break ;
case CORE2_AFF:
*cpu_id_p = 2;
break ;
#endif
#ifdef CORE3_AFF
case CORE3_AFF:
*cpu_id_p = 3;
break ;
case CORE3_AFF:
*cpu_id_p = 3;
break ;
#endif
#ifdef CORE4_AFF
case CORE4_AFF:
*cpu_id_p = 4;
break ;
case CORE4_AFF:
*cpu_id_p = 4;
break ;
#endif
#ifdef CORE5_AFF
case CORE5_AFF:
*cpu_id_p = 5;
break ;
case CORE5_AFF:
*cpu_id_p = 5;
break ;
#endif
#ifdef CORE6_AFF
case CORE6_AFF:
*cpu_id_p = 6;
break ;
case CORE6_AFF:
*cpu_id_p = 6;
break ;
#endif
#ifdef CORE7_AFF
case CORE7_AFF:
*cpu_id_p = 7;
break ;
case CORE7_AFF:
*cpu_id_p = 7;
break ;
#endif
default:
ret = ERR_GENERAL;
break;
default:
ret = ERR_GENERAL;
break;
}
return ret;
}

2
bsp/phytium/libraries/standalone/board/e2000/fearly_uart.c → bsp/phytium/libraries/standalone/board/common/fearly_uart.c
View File

@ -14,7 +14,7 @@
* FilePath: early_uart.c
* Date: 2022-02-11 13:33:28
* LastEditTime: 2022-02-17 17:59:26
* Description:  This files is for
* Description:  This file is for
*
* Modify History:
* Ver   Who        Date         Changes

6
bsp/phytium/libraries/standalone/board/e2000/fearly_uart.h → bsp/phytium/libraries/standalone/board/common/fearly_uart.h
View File

@ -14,15 +14,15 @@
* FilePath: fearly_uart.h
* Date: 2022-02-11 13:33:28
* LastEditTime: 2022-02-17 18:00:16
* Description:  This files is for
* Description:  This file is for
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
* 1.0 rtos 2022/6/25 init commit
*/
#ifndef BOARD_E2000_EARLY_UART_H
#define BOARD_E2000_EARLY_UART_H
#ifndef BOARD_COMMON_EARLY_UART_H
#define BOARD_COMMON_EARLY_UART_H
#ifdef __cplusplus
extern "C"

406
bsp/phytium/libraries/standalone/board/d2000/fioctrl.c Normal file
View File

@ -0,0 +1,406 @@
/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: fioctrl.c
* Date: 2022-02-10 14:53:42
* LastEditTime: 2022-02-18 08:25:29
* Description:  This files is for io-ctrl function implementation (io-mux/io-config/io-delay)
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
* 1.0 zhugengyu 2022/2/22 init commit
*/
/***************************** Include Files *********************************/
#include "fparameters.h"
#include "fio.h"
#include "fkernel.h"
#include "fassert.h"
#include "fdebug.h"
#include "fioctrl.h"
#include "fpinctrl.h"
/************************** Constant Definitions *****************************/
/* Bit[0] : 输入延迟功能使能 */
#define FIOCTRL_DELAY_EN(delay_beg) BIT(delay_beg)
#define FIOCTRL_INPUT_DELAY_OFF 0
/* Bit[3:1] : 输入延迟精调档位选择 */
#define FIOCTRL_DELICATE_DELAY_MASK(delay_beg) GENMASK((delay_beg + 3), (delay_beg + 1))
#define FIOCTRL_DELICATE_DELAY_GET(reg_val, delay_beg) GET_REG32_BITS((reg_val), (delay_beg + 3), (delay_beg + 1))
#define FIOCTRL_DELICATE_DELAY_SET(val, delay_beg) SET_REG32_BITS((val), (delay_beg + 3), (delay_beg + 1))
/* Bit[6:4] : 输入延迟粗调档位选择 */
#define FIOCTRL_ROUGH_DELAY_MASK(delay_beg) GENMASK((delay_beg + 6), (delay_beg + 4))
#define FIOCTRL_ROUGH_DELAY_GET(reg_val, delay_beg) GET_REG32_BITS((reg_val), (delay_beg + 6), (delay_beg + 4))
#define FIOCTRL_ROUGH_DELAY_SET(val, delay_beg) SET_REG32_BITS((val), (delay_beg + 6), (delay_beg + 4))
/* Bit[7] : 保留 */
/* Bit[8] : 输出延迟功能使能 */
/* Bit[11:9] : 输出延迟精调档位选择 */
/* Bit [14:12] : 输出延迟粗调档位选择 */
/* Bit [15] : 保留 */
#define FIOCTRL_FUNC_BEG_OFF(reg_bit) ((reg_bit) + 0)
#define FIOCTRL_FUNC_END_OFF(reg_bit) ((reg_bit) + 1) /* bit[1:0] 复用功能占2个位 */
#define FIOCTRL_PULL_BEG_OFF(reg_bit) ((reg_bit) + 2)
#define FIOCTRL_PULL_END_OFF(reg_bit) ((reg_bit) + 3) /* bit[3:2] 上下拉功能占2个位 */
#define FIOCTRL_DELAY_IN_BEG_OFF(reg_bit) ((reg_bit) + 0)
#define FIOCTRL_DELAY_IN_END_OFF(reg_bit) ((reg_bit) + 7) /* bit[8:1] 输入延时占7个位 */
#define FIOCTRL_DELAY_OUT_BEG_OFF(reg_bit) ((reg_bit) + 8)
#define FIOCTRL_DELAY_OUT_END_OFF(reg_bit) ((reg_bit) + 15) /* bit[15:9] 输出延时占7个位 */
/* 芯片引脚控制寄存器的起止位置 */
#define FIOCTRL_REG_OFFSET_MIN 0x200
#define FIOCTRL_REG_OFFSET_MAX 0x22c
/* 芯片引脚延时寄存器的起止位置 */
#define FIOCTRL_DELAY_REG_OFFSET_MIN 0x400
#define FIOCTRL_DELAY_REG_OFFSET_MAX 0x404
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
#define FIOCTRL_DEBUG_TAG "FIOCTRL"
#define FIOCTRL_ERROR(format, ...) FT_DEBUG_PRINT_E(FIOCTRL_DEBUG_TAG, format, ##__VA_ARGS__)
#define FIOCTRL_WARN(format, ...) FT_DEBUG_PRINT_W(FIOCTRL_DEBUG_TAG, format, ##__VA_ARGS__)
#define FIOCTRL_INFO(format, ...) FT_DEBUG_PRINT_I(FIOCTRL_DEBUG_TAG, format, ##__VA_ARGS__)
#define FIOCTRL_DEBUG(format, ...) FT_DEBUG_PRINT_D(FIOCTRL_DEBUG_TAG, format, ##__VA_ARGS__)
#define FIOCTRL_ASSERT_REG_OFF(pin) FASSERT_MSG(((pin.reg_off >= FIOCTRL_REG_OFFSET_MIN) && (pin.reg_off <= FIOCTRL_REG_OFFSET_MAX)), "invalid pin register off @%d", (pin.reg_off))
#define FIOCTRL_ASSERT_FUNC(func) FASSERT_MSG((func < FPIN_NUM_OF_FUNC), "invalid func as %d", (func))
#define FIOCTRL_ASSERT_PULL(pull) FASSERT_MSG((pull < FPIN_NUM_OF_PULL), "invalid pull as %d", (pull))
#define FIOCTRL_ASSERT_DELAY_REG_OFF(pin) FASSERT_MSG(((pin.reg_off >= FIOCTRL_DELAY_REG_OFFSET_MIN) && (pin.reg_off <= FIOCTRL_DELAY_REG_OFFSET_MAX)), "invalid delay pin register off @%d", (pin.reg_off))
#define FIOCTRL_ASSERT_DELAY(delay) FASSERT_MSG(((delay) < FPIN_NUM_OF_DELAY), "invalid delay as %d", (delay));
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/*****************************************************************************/
/**
* @name: FPinGetFunc
* @msg: 获取IO引脚当前的复用功能
* @return {FPinFunc} 当前的复用功能
* @param {FPinIndex} pin IO引脚索引
* @note 参考编程手册，使用 FIOCTRL_INDEX 宏定义index的值
*/
FPinFunc FPinGetFunc(const FPinIndex pin)
{
FIOCTRL_ASSERT_REG_OFF(pin);
u32 func_beg = FIOCTRL_FUNC_BEG_OFF(pin.reg_bit);
u32 func_end = FIOCTRL_FUNC_END_OFF(pin.reg_bit);
u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
u32 func = GET_REG32_BITS(reg_val, func_end, func_beg);
FIOCTRL_ASSERT_FUNC(func);
return (FPinFunc)GET_REG32_BITS(reg_val, func_end, func_beg);
}
/**
* @name: FPinSetFunc
* @msg: 设置IO引脚复用功能
* @return {*}
* @param {FPinIndex} pin IO引脚索引
* @param {FPinFunc} func IO复用功能
* @note 参考编程手册，使用 FIOCTRL_INDEX 宏定义index的值
*/
void FPinSetFunc(const FPinIndex pin, FPinFunc func)
{
FIOCTRL_ASSERT_REG_OFF(pin);
FIOCTRL_ASSERT_FUNC(func);
u32 func_beg = FIOCTRL_FUNC_BEG_OFF(pin.reg_bit);
u32 func_end = FIOCTRL_FUNC_END_OFF(pin.reg_bit);
u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
reg_val &= ~GENMASK(func_end, func_beg);
reg_val |= SET_REG32_BITS(func, func_end, func_beg);
FtOut32(FIOCTRL_REG_BASE_ADDR + pin.reg_off, reg_val);
return;
}
/**
* @name: FPinGetPull
* @msg: 获取IO引脚当前的上下拉设置
* @return {*}
* @param {FPinIndex} pin IO引脚索引
* @note 参考编程手册，使用 FIOCTRL_INDEX 宏定义index的值
*/
FPinPull FPinGetPull(const FPinIndex pin)
{
FIOCTRL_ASSERT_REG_OFF(pin);
u32 pull_beg = FIOCTRL_PULL_BEG_OFF(pin.reg_bit);
u32 pull_end = FIOCTRL_PULL_END_OFF(pin.reg_bit);
u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
u32 pull = GET_REG32_BITS(reg_val, pull_end, pull_beg);
FIOCTRL_ASSERT_PULL(pull);
return (FPinPull)pull;
}
/**
* @name: FPinSetPull
* @msg: 设置IO引脚当前的上下拉
* @return {*}
* @param {FPinIndex} pin IO引脚索引
* @param {FPinPull} pull 上下拉设置
*/
void FPinSetPull(const FPinIndex pin, FPinPull pull)
{
FIOCTRL_ASSERT_REG_OFF(pin);
FIOCTRL_ASSERT_PULL(pull);
u32 pull_beg = FIOCTRL_PULL_BEG_OFF(pin.reg_bit);
u32 pull_end = FIOCTRL_PULL_END_OFF(pin.reg_bit);
u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
reg_val &= ~GENMASK(pull_end, pull_beg);
reg_val |= SET_REG32_BITS(pull, pull_end, pull_beg);
FtOut32(FIOCTRL_REG_BASE_ADDR + pin.reg_off, reg_val);
return;
}
/**
* @name: FPinGetConfig
* @msg: 获取IO引脚的复用、上下拉和驱动能力设置
* @return {*}
* @param {FPinIndex} pin IO引脚索引
* @param {FPinFunc} *func IO复用功能
* @param {FPinPull} *pull pull 上下拉设置
*/
void FPinGetConfig(const FPinIndex pin, FPinFunc *func, FPinPull *pull)
{
FIOCTRL_ASSERT_REG_OFF(pin);
u32 func_beg = FIOCTRL_FUNC_BEG_OFF(pin.reg_bit);
u32 func_end = FIOCTRL_FUNC_END_OFF(pin.reg_bit);
u32 pull_beg = FIOCTRL_PULL_BEG_OFF(pin.reg_bit);
u32 pull_end = FIOCTRL_PULL_END_OFF(pin.reg_bit);
u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
if (func)
{
*func = GET_REG32_BITS(reg_val, func_end, func_beg);
}
if (pull)
{
*pull = GET_REG32_BITS(reg_val, pull_end, pull_beg);
}
return;
}
/**
* @name: FPinSetConfig
* @msg: 设置IO引脚的复用、上下拉和驱动能力
* @return {*}
* @param {FPinIndex} pin IO引脚索引
* @param {FPinFunc} func IO复用功能
* @param {FPinPull} pull pull 上下拉设置
*/
void FPinSetConfig(const FPinIndex pin, FPinFunc func, FPinPull pull)
{
FIOCTRL_ASSERT_REG_OFF(pin);
u32 func_beg = FIOCTRL_FUNC_BEG_OFF(pin.reg_bit);
u32 func_end = FIOCTRL_FUNC_END_OFF(pin.reg_bit);
u32 pull_beg = FIOCTRL_PULL_BEG_OFF(pin.reg_bit);
u32 pull_end = FIOCTRL_PULL_END_OFF(pin.reg_bit);
u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
reg_val &= ~GENMASK(func_end, func_beg);
reg_val |= SET_REG32_BITS(func, func_end, func_beg);
reg_val &= ~GENMASK(pull_end, pull_beg);
reg_val |= SET_REG32_BITS(pull, pull_end, pull_beg);
FtOut32(FIOCTRL_REG_BASE_ADDR + pin.reg_off, reg_val);
return;
}
/**
* @name: FPinGetDelay
* @msg: 获取IO引脚当前的延时设置
* @return {FPinDelay} 当前的延时设置
* @param {FPinIndex} pin IO引脚延时设置索引
* @param {FPinDelayDir} dir 输入/输出延时
* @param {FPinDelayType} type 精调/粗调延时
*/
FPinDelay FPinGetDelay(const FPinIndex pin, FPinDelayDir dir, FPinDelayType type)
{
FIOCTRL_ASSERT_DELAY_REG_OFF(pin);
u8 delay = 0;
const u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
u32 delay_beg = 0, delay_end = 0;
if (FPIN_OUTPUT_DELAY == dir)
{
delay_beg = FIOCTRL_DELAY_OUT_BEG_OFF(pin.reg_off);
}
else if (FPIN_INPUT_DELAY == dir)
{
delay_beg = FIOCTRL_DELAY_IN_BEG_OFF(pin.reg_off);
}
else
{
FASSERT(0);
}
if (FPIN_DELAY_FINE_TUNING == type)
{
delay = FIOCTRL_DELICATE_DELAY_GET(reg_val, delay_beg);
}
else if (FPIN_DELAY_COARSE_TUNING == type)
{
delay = FIOCTRL_ROUGH_DELAY_GET(reg_val, delay_beg);
}
else
{
FASSERT(0);
}
FIOCTRL_ASSERT_DELAY(delay);
return (FPinDelay)delay;
}
/**
* @name: FPinGetDelayEn
* @msg: 获取IO引脚当前的延时使能标志位
* @return {*}
* @param {FPinIndex} pin IO引脚延时设置索引
* @param {FPinDelayDir} dir 输入/输出延时
*/
boolean FPinGetDelayEn(const FPinIndex pin, FPinDelayDir dir)
{
FIOCTRL_ASSERT_DELAY_REG_OFF(pin);
boolean enabled = FALSE;
const u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
u32 delay_beg = 0, delay_end = 0;
if (FPIN_OUTPUT_DELAY == dir)
{
delay_beg = FIOCTRL_DELAY_OUT_BEG_OFF(pin.reg_off);
}
else if (FPIN_INPUT_DELAY == dir)
{
delay_beg = FIOCTRL_DELAY_IN_BEG_OFF(pin.reg_off);
}
else
{
FASSERT(0);
}
if (FIOCTRL_DELAY_EN(delay_beg) & reg_val)
{
enabled = TRUE;
}
return enabled;
}
/**
* @name: FPinSetDelay
* @msg: 设置IO引脚延时
* @return {*}
* @param {FPinIndex} pin IO引脚延时设置索引
* @param {FPinDelayDir} dir 输入/输出延时
* @param {FPinDelayType} type 精调/粗调延时
* @param {FPinDelay} delay 延时档位设置 0 ~ 8 档可用
*/
void FPinSetDelay(const FPinIndex pin, FPinDelayDir dir, FPinDelayType type, FPinDelay delay)
{
FIOCTRL_ASSERT_DELAY_REG_OFF(pin);
FIOCTRL_ASSERT_DELAY(delay);
u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
u32 delay_beg = 0, delay_end = 0;
if (FPIN_OUTPUT_DELAY == dir)
{
delay_beg = FIOCTRL_DELAY_OUT_BEG_OFF(pin.reg_off);
}
else if (FPIN_INPUT_DELAY == dir)
{
delay_beg = FIOCTRL_DELAY_IN_BEG_OFF(pin.reg_off);
}
else
{
FASSERT(0);
}
if (FPIN_DELAY_FINE_TUNING == type)
{
reg_val &= ~FIOCTRL_DELICATE_DELAY_MASK(delay_beg);
delay = FIOCTRL_DELICATE_DELAY_GET(reg_val, delay_beg);
}
else if (FPIN_DELAY_COARSE_TUNING == type)
{
reg_val &= ~FIOCTRL_ROUGH_DELAY_MASK(delay_beg);
delay = FIOCTRL_ROUGH_DELAY_GET(reg_val, delay_beg);
}
else
{
FASSERT(0);
}
FtOut32(FIOCTRL_REG_BASE_ADDR + pin.reg_off, reg_val);
return;
}
/**
* @name: FPinSetDelayEn
* @msg: 使能/去使能IO引脚延时
* @return {*}
* @param {FPinIndex} pin IO引脚延时设置索引
* @param {FPinDelayDir} dir 输入/输出延时
* @param {boolean} enable TRUE: 使能, FALSE: 去使能
*/
void FPinSetDelayEn(const FPinIndex pin, FPinDelayDir dir, boolean enable)
{
FIOCTRL_ASSERT_DELAY_REG_OFF(pin);
u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
u32 delay_beg = 0, delay_end = 0;
if (FPIN_OUTPUT_DELAY == dir)
{
delay_beg = FIOCTRL_DELAY_OUT_BEG_OFF(pin.reg_off);
}
else if (FPIN_INPUT_DELAY == dir)
{
delay_beg = FIOCTRL_DELAY_IN_BEG_OFF(pin.reg_off);
}
else
{
FASSERT(0);
}
reg_val &= ~FIOCTRL_DELAY_EN(delay_beg);
if (enable)
{
reg_val |= FIOCTRL_DELAY_EN(delay_beg);
}
FtOut32(FIOCTRL_REG_BASE_ADDR + pin.reg_off, reg_val);
return;
}

83
bsp/phytium/libraries/standalone/board/d2000/fioctrl.h Normal file
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@ -0,0 +1,83 @@
/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: fioctrl.h
* Date: 2022-02-10 14:53:42
* LastEditTime: 2022-02-18 08:25:35
* Description:  This files is for io-ctrl function definition (io-mux/io-config/io-delay)
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
* 1.0 zhugengyu 2022/2/22 init commit
*/
#ifndef BOARD_D2000_FIOCTRL_H
#define BOARD_D2000_FIOCTRL_H
#ifdef __cplusplus
extern "C"
{
#endif
/***************************** Include Files *********************************/
#include "ftypes.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
#define FIOCTRL_INDEX(offset, func_beg) \
{ \
/* reg_off */ (offset), \
/* reg_bit */ (func_beg) \
}
/************************** Variable Definitions *****************************/
#define FIOCTRL_CRU_CLK_OBV_PAD (FPinIndex)FIOCTRL_INDEX(0x200, 24)
#define FIOCTRL_SPI0_CSN0_PAD (FPinIndex)FIOCTRL_INDEX(0x208, 16)
#define FIOCTRL_SPI0_SCK_PAD (FPinIndex)FIOCTRL_INDEX(0x208, 12)
#define FIOCTRL_SPI0_SO_PAD (FPinIndex)FIOCTRL_INDEX(0x208, 8)
#define FIOCTRL_SPI0_SI_PAD (FPinIndex)FIOCTRL_INDEX(0x208, 4)
#define FIOCTRL_TJTAG_TDI_PAD (FPinIndex)FIOCTRL_INDEX(0x204, 24) /* can0-tx: func 1 */
#define FIOCTRL_SWDITMS_SWJ_PAD (FPinIndex)FIOCTRL_INDEX(0x204, 12) /* can0-rx: func 1 */
#define FIOCTRL_NTRST_SWJ_PAD (FPinIndex)FIOCTRL_INDEX(0x204, 20) /* can1-tx: func 1 */
#define FIOCTRL_SWDO_SWJ_PAD (FPinIndex)FIOCTRL_INDEX(0x204, 8) /* can1-rx: func 1 */
#define FIOCTRL_I2C0_SCL_PAD (FPinIndex)FIOCTRL_INDEX(0x208, 24) /* i2c0-scl: func 0 */
#define FIOCTRL_I2C0_SDA_PAD (FPinIndex)FIOCTRL_INDEX(0x208, 20) /* i2c0-sda: func 0 */
#define FIOCTRL_ALL_PLL_LOCK_PAD (FPinIndex)FIOCTRL_INDEX(0x200, 28) /* i2c1-scl: func 2 */
#define FIOCTRL_CRU_CLK_OBV_PAD (FPinIndex)FIOCTRL_INDEX(0x200, 24) /* i2c1-sda: func 2 */
#define FIOCTRL_SWDO_SWJ_PAD (FPinIndex)FIOCTRL_INDEX(0x204, 8) /* i2c2-scl: func 2 */
#define FIOCTRL_TDO_SWJ_IN_PAD (FPinIndex)FIOCTRL_INDEX(0x204, 4) /* i2c2-sda: func 2 */
#define FIOCTRL_HDT_MB_DONE_STATE_PAD (FPinIndex)FIOCTRL_INDEX(0x204, 0) /* i2c3-scl: func 2 */
#define FIOCTRL_HDT_MB_FAIL_STATE_PAD (FPinIndex)FIOCTRL_INDEX(0x208, 28) /* i2c3-sda: func 2 */
#define FIOCTRL_UART_2_RXD_PAD (FPinIndex)FIOCTRL_INDEX(0x210, 0) /* spi1_csn0: func 1 */
#define FIOCTRL_UART_2_TXD_PAD (FPinIndex)FIOCTRL_INDEX(0x214, 28) /* spi1_sck: func 1 */
#define FIOCTRL_UART_3_RXD_PAD (FPinIndex)FIOCTRL_INDEX(0x214, 24) /* spi1_so: func 1 */
#define FIOCTRL_UART_3_TXD_PAD (FPinIndex)FIOCTRL_INDEX(0x214, 20) /* spi1_si: func 1 */
#define FIOCTRL_QSPI_CSN2_PAD (FPinIndex)FIOCTRL_INDEX(0x214, 8) /* spi1_csn1: func 1 */
#define FIOCTRL_QSPI_CSN3_PAD (FPinIndex)FIOCTRL_INDEX(0x214, 4) /* spi1_csn2: func 1 */
#ifdef __cplusplus
}
#endif
#endif

347
bsp/phytium/libraries/standalone/board/d2000/fparameters.h Normal file
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@ -0,0 +1,347 @@
/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: fparameters.h
* Date: 2022-02-10 14:53:42
* LastEditTime: 2022-02-17 17:58:51
* Description:  This file is for
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
*/
#ifndef BSP_BOARD_D2000_PARAMETERS_H
#define BSP_BOARD_D2000_PARAMETERS_H
#ifdef __cplusplus
extern "C"
{
#endif
#if !defined(__ASSEMBLER__)
#include "ftypes.h"
#endif
#define CORE0_AFF 0x0
#define CORE1_AFF 0x1
#define CORE2_AFF 0x100
#define CORE3_AFF 0x101
#define CORE4_AFF 0x200
#define CORE5_AFF 0x201
#define CORE6_AFF 0x300
#define CORE7_AFF 0x301
/* cache */
#define CACHE_LINE_ADDR_MASK 0x3F
#define CACHE_LINE 64U
/* Device register address */
#define FDEV_BASE_ADDR 0x28000000
#define FDEV_END_ADDR 0x2FFFFFFF
/* Generic Timer */
#define GENERIC_TIMER_NS_IRQ_NUM 30
/* PCI */
#define FPCIE_NUM 1
#define FPCIE0_ID 0
#define FPCIE0_MISC_IRQ_NUM 59
#define FPCIE_CFG_MAX_NUM_OF_BUS 256
#define FPCIE_CFG_MAX_NUM_OF_DEV 32
#define FPCIE_CFG_MAX_NUM_OF_FUN 8
#define FPCI_CONFIG_BASE_ADDR 0x40000000
#define FPCI_CONFIG_REG_LENGTH 0x10000000
#define FPCI_IO_CONFIG_BASE_ADDR 0x50000000
#define FPCI_IO_CONFIG_REG_LENGTH 0x08000000
#define FPCI_MEM32_BASE_ADDR 0x58000000
#define FPCI_MEM32_REG_LENGTH 0x27ffffff
#define FPCI_MEM64_BASE_ADDR 0x1000000000
#define FPCI_MEM64_REG_LENGTH 0x1000000000
#define FPCI_EU0_C0_CONTROL_BASE_ADDR 0x29900000
#define FPCI_EU0_C1_CONTROL_BASE_ADDR 0x29910000
#define FPCI_EU0_C2_CONTROL_BASE_ADDR 0x29920000
#define FPCI_EU1_C0_CONTROL_BASE_ADDR 0x29930000
#define FPCI_EU1_C1_CONTROL_BASE_ADDR 0x29940000
#define FPCI_EU1_C2_CONTROL_BASE_ADDR 0x29950000
#define FPCI_EU0_CONFIG_BASE_ADDR 0x29900000
#define FPCI_EU1_CONFIG_BASE_ADDR 0x299A0000
#define FPCI_INTA_IRQ_NUM 60
#define FPCI_INTB_IRQ_NUM 61
#define FPCI_INTC_IRQ_NUM 62
#define FPCI_INTD_IRQ_NUM 63
#define FPCI_NEED_SKIP 0
#define FPCI_INTX_EOI
#define FPCI_INTX_PEU0_STAT 0x29100000
#define FPCI_INTX_PEU1_STAT 0x29101000
#define FPCI_INTX_EU0_C0_CONTROL 0x29000184
#define FPCI_INTX_EU0_C1_CONTROL 0x29010184
#define FPCI_INTX_EU0_C2_CONTROL 0x29020184
#define FPCI_INTX_EU1_C0_CONTROL 0x29030184
#define FPCI_INTX_EU1_C1_CONTROL 0x29040184
#define FPCI_INTX_EU1_C2_CONTROL 0x29050184
#define FPCI_INTX_CONTROL_NUM 6 /* Total number of controllers */
#define FPCI_INTX_SATA_NUM 2 /* Total number of controllers */
/* platform ahci host */
#define PLAT_AHCI_HOST_MAX_COUNT 5
#define AHCI_BASE_0 0
#define AHCI_BASE_1 0
#define AHCI_BASE_2 0
#define AHCI_BASE_3 0
#define AHCI_BASE_4 0
#define AHCI_IRQ_0 0
#define AHCI_IRQ_1 0
#define AHCI_IRQ_2 0
#define AHCI_IRQ_3 0
#define AHCI_IRQ_4 0
/* UART */
#if !defined(__ASSEMBLER__)
enum
{
FUART0_ID = 0,
FUART1_ID,
FUART2_ID,
FUART3_ID,
FUART_NUM
};
#endif
#define FUART0_IRQ_NUM 38
#define FUART0_BASE_ADDR 0x28000000
#define FUART0_CLK_FREQ_HZ 48000000
#define FUART1_IRQ_NUM 39
#define FUART1_BASE_ADDR 0x28001000
#define FUART1_CLK_FREQ_HZ 48000000
#define FUART2_IRQ_NUM 40
#define FUART2_BASE_ADDR 0x28002000
#define FUART2_CLK_FREQ_HZ 48000000
#define FUART3_IRQ_NUM 41
#define FUART3_BASE_ADDR 0x28003000
#define FUART3_CLK_FREQ_HZ 48000000
#define FT_STDOUT_BASE_ADDR FUART1_BASE_ADDR
#define FT_STDIN_BASE_ADDR FUART1_BASE_ADDR
/* QSPI */
#if !defined(__ASSEMBLER__)
enum
{
FQSPI0_ID = 0,
FQSPI_NUM
};
/* FQSPI cs 0_3, chip number */
enum
{
FQSPI_CS_0 = 0,
FQSPI_CS_1 = 1,
FQSPI_CS_2 = 2,
FQSPI_CS_3 = 3,
FQSPI_CS_NUM
};
#endif
#define FQSPI_BASE_ADDR 0x28014000
#define FQSPI_MEM_START_ADDR 0x0
#define FQSPI_MEM_END_ADDR 0x1FFFFFFF
/* GIC v3 */
#define ARM_GIC_NR_IRQS 1024
#define ARM_GIC_IRQ_START 0
#define FGIC_NUM 1
#define GICV3_BASE_ADDR 0x29a00000U
#define GICV3_DISTRIBUTOR_BASE_ADDR (GICV3_BASE_ADDR + 0)
#define GICV3_RD_BASE_ADDR (GICV3_BASE_ADDR + 0x100000U)
#define GICV3_RD_OFFSET (2U << 16)
#define FT_GICV3_VECTORTABLE_NUM GIC_INT_MAX_NUM
/*
* The maximum priority value that can be used in the GIC.
*/
#define GICV3_MAX_INTR_PRIO_VAL 240U
#define GICV3_INTR_PRIO_MASK 0x000000f0U
#define ARM_GIC_IPI_COUNT 16 /* MPCore IPI count */
#define SGI_INT_MAX 16
#define SPI_START_INT_NUM 32 /* SPI start at ID32 */
#define PPI_START_INT_NUM 16 /* PPI start at ID16 */
#define GIC_INT_MAX_NUM 1020 /* GIC max interrupts count */
/* GPIO */
#define FGPIO0_BASE_ADDR (0x28004000)
#define FGPIO1_BASE_ADDR (0x28005000)
#define FGPIO0_ID 0
#define FGPIO1_ID 1
#define FGPIO_NUM 2
#define FGPIO0_IRQ_NUM (42) /* gpio0 irq number */
#define FGPIO1_IRQ_NUM (43) /* gpio1 irq number */
/* IOMUX */
#define FIOCTRL_REG_BASE_ADDR 0x28180000
/* SPI */
#define FSPI0_BASE_ADDR 0x2800c000
#define FSPI1_BASE_ADDR 0x28013000
#define FSPI0_ID 0
#define FSPI1_ID 1
#define FSPI_CLK_FREQ_HZ 48000000
#define FSPI_NUM 2
#define FSPI0_IRQ_NUM 50
#define FSPI1_IRQ_NUM 51
/* I2C */
#if !defined(__ASSEMBLER__)
enum
{
FI2C0_ID = 0,
FI2C1_ID = 1,
FI2C2_ID,
FI2C3_ID,
FI2C_NUM
};
#endif
#define FI2C0_BASE_ADDR 0x28006000
#define FI2C1_BASE_ADDR 0x28007000
#define FI2C2_BASE_ADDR 0x28008000
#define FI2C3_BASE_ADDR 0x28009000
#define FI2C0_IRQ_NUM 44
#define FI2C1_IRQ_NUM 45
#define FI2C2_IRQ_NUM 46
#define FI2C3_IRQ_NUM 47
#define FI2C_CLK_FREQ_HZ 48000000 /* 48MHz */
/* WDT */
#if !defined(__ASSEMBLER__)
enum
{
FWDT0_ID = 0,
FWDT1_ID = 1,
FWDT_NUM
};
#endif
#define FWDT0_REFRESH_BASE_ADDR 0x2800a000
#define FWDT1_REFRESH_BASE_ADDR 0x28016000
#define FWDT_CONTROL_BASE_ADDR(x) ((x)+0x1000)
#define FWDT0_IRQ_NUM 48
#define FWDT1_IRQ_NUM 49
#define FWDT_CLK_FREQ_HZ 48000000 /* 48MHz */
/* SDCI */
#if !defined(__ASSEMBLER__)
enum
{
FSDMMC0_ID = 0,
FSDMMC_NUM
};
#endif
#define FSDMMC0_BASE_ADDR 0x28207C00
#define FSDMMC0_DMA_IRQ_NUM 52
#define FSDMMC0_CMD_IRQ_NUM 53
#define FSDMMC0_ERR_IRQ_NUM 54
#define FSDMMC_CLK_FREQ_HZ 600000000 /* 600 MHz */
/* GMAC */
#define FGMAC_PUB_REG_BASE_ADDR 0x2820B000 /* 公共寄存器基地址 */
#if !defined(__ASSEMBLER__)
enum
{
FGMAC0_ID = 0,
FGMAC1_ID,
FGMAC_NUM
};
#endif
#define FGMAC0_BASE_ADDR 0x2820C000
#define FGMAC1_BASE_ADDR 0x28210000
#define FGMAC0_IRQ_NUM 81
#define FGMAC1_IRQ_NUM 82
#define FGMAC_DMA_MIN_ALIGN 128
#define FGMAC_MAX_PACKET_SIZE 1600
/* rtc base address */
#define RTC_CONTROL_BASE 0x2800D000
#define FT_CPUS_NR CORE_NUM
/* can */
#define FCAN_CLK_FREQ_HZ 600000000
#define FCAN_REG_LENGTH 0x1000
#define FCAN0_BASE_ADDR 0x28207000
#define FCAN1_BASE_ADDR 0x28207400
#define FCAN2_BASE_ADDR 0x28207800
#define FCAN0_IRQ_NUM 119
#define FCAN1_IRQ_NUM 123
#define FCAN2_IRQNUM 124
#if !defined(__ASSEMBLER__)
enum
{
FCAN0_ID = 0,
FCAN1_ID = 1,
FCAN2_ID = 2,
FCAN_NUM
};
#endif
#ifdef __cplusplus
}
#endif
#endif // !

673
bsp/phytium/libraries/standalone/board/e2000/d/fiopad_config.c
View File

@ -14,7 +14,7 @@
* FilePath: fiopad_config.c
* Date: 2022-02-10 14:53:42
* LastEditTime: 2022-02-18 08:25:29
* Description:  This files is for io-pad function definition
* Description:  This file is for io-pad function definition
*
* Modify History:
* Ver   Who        Date         Changes
@ -70,33 +70,59 @@ void FIOPadSetSpimMux(u32 spim_id)
*/
void FIOPadSetGpioMux(u32 gpio_id, u32 pin_id)
{
if (FGPIO_ID_3 == gpio_id)
if (FGPIO3_ID == gpio_id)
{
switch (pin_id)
{
case 3: /* gpio 3-a-3 */
FPinSetFunc(FIOPAD_A29, FPIN_FUNC6);
break;
case 4: /* gpio 3-a-4 */
FPinSetFunc(FIOPAD_C29, FPIN_FUNC6);
break;
case 5: /* gpio 3-a-5 */
FPinSetFunc(FIOPAD_C27, FPIN_FUNC6);
break;
case 6: /* gpio 3-a-6 */
FPinSetFunc(FIOPAD_A27, FPIN_FUNC6);
break;
case 7: /* gpio 3-a-7 */ /*cannot use this pin*/
FPinSetFunc(FIOPAD_AJ49, FPIN_FUNC6);
break;
case 8: /* gpio 3-a-8 */
FPinSetFunc(FIOPAD_AL45, FPIN_FUNC6);
break;
case 9: /* gpio 3-a-9 */
FPinSetFunc(FIOPAD_AL43, FPIN_FUNC6);
break;
default:
break;
case 3: /* gpio 3-a-3 */
FPinSetFunc(FIOPAD_A29, FPIN_FUNC6);
break;
case 4: /* gpio 3-a-4 */
FPinSetFunc(FIOPAD_C29, FPIN_FUNC6);
break;
case 5: /* gpio 3-a-5 */
FPinSetFunc(FIOPAD_C27, FPIN_FUNC6);
break;
case 6: /* gpio 3-a-6 */
FPinSetFunc(FIOPAD_A27, FPIN_FUNC6);
break;
case 7: /* gpio 3-a-7 */ /*cannot use this pin*/
FPinSetFunc(FIOPAD_AJ49, FPIN_FUNC6);
break;
case 8: /* gpio 3-a-8 */
FPinSetFunc(FIOPAD_AL45, FPIN_FUNC6);
break;
case 9: /* gpio 3-a-9 */
FPinSetFunc(FIOPAD_AL43, FPIN_FUNC6);
break;
default:
break;
}
}
else if (FGPIO4_ID == gpio_id)
{
switch (pin_id)
{
case 5: /* gpio 4-a-5 */
FPinSetFunc(FIOPAD_W47, FPIN_FUNC6);
break;
case 9: /* gpio 4-a-9 */
FPinSetFunc(FIOPAD_U49, FPIN_FUNC6);
break;
case 10: /* gpio 4-a-10 */
FPinSetFunc(FIOPAD_AE45, FPIN_FUNC6);
break;
case 11: /* gpio 4-a-11 */
FPinSetFunc(FIOPAD_AC45, FPIN_FUNC6);
break;
case 12: /* gpio 4-a-12 */
FPinSetFunc(FIOPAD_AE43, FPIN_FUNC6);
break;
case 13: /* gpio 4-a-13 */
FPinSetFunc(FIOPAD_AA43, FPIN_FUNC6);
break;
default:
break;
}
}
}
@ -109,15 +135,15 @@ void FIOPadSetGpioMux(u32 gpio_id, u32 pin_id)
*/
void FIOPadSetCanMux(u32 can_id)
{
if (can_id == FCAN_INSTANCE_0)
if (can_id == FCAN0_ID)
{
/* mio0 */
/* can0 */
FPinSetFunc(FIOPAD_A37, FPIN_FUNC0); /* can0-tx: func 0 */
FPinSetFunc(FIOPAD_A39, FPIN_FUNC0); /* can0-rx: func 0 */
}
else if (can_id == FCAN_INSTANCE_1)
else if (can_id == FCAN1_ID)
{
/* mio1 */
/* can1 */
FPinSetFunc(FIOPAD_A41, FPIN_FUNC0); /* can1-tx: func 0 */
FPinSetFunc(FIOPAD_C41, FPIN_FUNC0); /* can1-rx: func 0 */
}
@ -137,7 +163,7 @@ void FIOPadSetCanMux(u32 can_id)
void FIOPadSetQspiMux(u32 qspi_id, u32 cs_id)
{
if (qspi_id == FQSPI_INSTANCE_0)
if (qspi_id == FQSPI0_ID)
{
/* add sck, io0-io3 iopad multiplex */
}
@ -174,102 +200,102 @@ void FIOPadSetQspiMux(u32 qspi_id, u32 cs_id)
*/
void FIOPadSetPwmMux(u32 pwm_id, u32 pwm_channel)
{
FASSERT(pwm_id < FPWM_INSTANCE_NUM);
FASSERT(pwm_id < FPWM_NUM);
FASSERT(pwm_channel < FPWM_CHANNEL_NUM);
switch (pwm_id)
{
case FPWM_INSTANCE_0:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_AL55, FPIN_FUNC1); /* PWM0_OUT: func 1 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_AJ53, FPIN_FUNC1); /* PWM1_OUT: func 1 */
}
break;
case FPWM0_ID:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_AL55, FPIN_FUNC1); /* PWM0_OUT: func 1 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_AJ53, FPIN_FUNC1); /* PWM1_OUT: func 1 */
}
break;
case FPWM_INSTANCE_1:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_AG53, FPIN_FUNC1); /* PWM2_OUT: func 1 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_AC55, FPIN_FUNC1); /* PWM3_OUT: func 1 */
}
break;
case FPWM1_ID:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_AG53, FPIN_FUNC1); /* PWM2_OUT: func 1 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_AC55, FPIN_FUNC1); /* PWM3_OUT: func 1 */
}
break;
case FPWM_INSTANCE_2:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_BA51, FPIN_FUNC1); /* PWM4_OUT: func 1 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_C35, FPIN_FUNC2); /* PWM5_OUT: func 2 */
}
break;
case FPWM2_ID:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_BA51, FPIN_FUNC1); /* PWM4_OUT: func 1 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_C35, FPIN_FUNC2); /* PWM5_OUT: func 2 */
}
break;
case FPWM_INSTANCE_3:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_A33, FPIN_FUNC2); /* PWM6_OUT: func 2 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_A39, FPIN_FUNC2); /* PWM7_OUT: func 2 */
}
break;
case FPWM3_ID:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_A33, FPIN_FUNC2); /* PWM6_OUT: func 2 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_A39, FPIN_FUNC2); /* PWM7_OUT: func 2 */
}
break;
case FPWM_INSTANCE_4:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_C41, FPIN_FUNC2); /* PWM8_OUT: func 2 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_A45, FPIN_FUNC2); /* PWM9_OUT: func 2 */
}
break;
case FPWM4_ID:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_C41, FPIN_FUNC2); /* PWM8_OUT: func 2 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_A45, FPIN_FUNC2); /* PWM9_OUT: func 2 */
}
break;
case FPWM_INSTANCE_5:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_A47, FPIN_FUNC2); /* PWM10_OUT: func 2 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_C29, FPIN_FUNC2); /* PWM11_OUT: func 2 */
}
break;
case FPWM5_ID:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_A47, FPIN_FUNC2); /* PWM10_OUT: func 2 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_C29, FPIN_FUNC2); /* PWM11_OUT: func 2 */
}
break;
case FPWM_INSTANCE_6:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_A27, FPIN_FUNC2); /* PWM12_OUT: func 2 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_J35, FPIN_FUNC3); /* PWM13_OUT: func 3 */
}
break;
case FPWM6_ID:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_A27, FPIN_FUNC2); /* PWM12_OUT: func 2 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_J35, FPIN_FUNC3); /* PWM13_OUT: func 3 */
}
break;
case FPWM_INSTANCE_7:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_E39, FPIN_FUNC3); /* PWM14_OUT: func 3 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_C39, FPIN_FUNC3); /* PWM15_OUT: func 3 */
}
break;
case FPWM7_ID:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_E39, FPIN_FUNC3); /* PWM14_OUT: func 3 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_C39, FPIN_FUNC3); /* PWM15_OUT: func 3 */
}
break;
default:
FIOPAD_ERROR("pwm id is error.\r\n");
break;
default:
FIOPAD_ERROR("pwm id is error.\r\n");
break;
}
}
@ -284,70 +310,37 @@ void FIOPadSetPwmMux(u32 pwm_id, u32 pwm_channel)
void FIOPadSetAdcMux(u32 adc_id, u32 adc_channel)
{
if (adc_id == FADC_INSTANCE_0)
if (adc_id == FADC0_ID)
{
switch (adc_channel)
{
case FADC_CHANNEL_0:
FPinSetFunc(FIOPAD_R47, FPIN_FUNC7); /* adc0-0: func 7 */
break;
case FADC_CHANNEL_1:
FPinSetFunc(FIOPAD_R45, FPIN_FUNC7); /* adc0-1: func 7 */
break;
case FADC_CHANNEL_2:
FPinSetFunc(FIOPAD_N47, FPIN_FUNC7); /* adc0-2: func 7 */
break;
case FADC_CHANNEL_3:
FPinSetFunc(FIOPAD_N51, FPIN_FUNC7); /* adc0-3: func 7 */
break;
case FADC_CHANNEL_4:
FPinSetFunc(FIOPAD_L51, FPIN_FUNC7); /* adc0-4: func 7 */
break;
case FADC_CHANNEL_5:
FPinSetFunc(FIOPAD_J51, FPIN_FUNC7); /* adc0-5: func 7 */
break;
case FADC_CHANNEL_6:
FPinSetFunc(FIOPAD_J41, FPIN_FUNC7); /* adc0-6: func 7 */
break;
case FADC_CHANNEL_7:
FPinSetFunc(FIOPAD_E43, FPIN_FUNC7); /* adc0-7: func 7 */
break;
default:
FIOPAD_ERROR("adc %d channel %d is error.\r\n", adc_id, adc_channel);
break;
}
}
else if (adc_id == FADC_INSTANCE_1)
{
switch (adc_channel)
{
case FADC_CHANNEL_0:
FPinSetFunc(FIOPAD_G43, FPIN_FUNC7); /* adc1-0: func 7 */
break;
case FADC_CHANNEL_1:
FPinSetFunc(FIOPAD_J43, FPIN_FUNC7); /* adc1-1: func 7 */
break;
case FADC_CHANNEL_2:
FPinSetFunc(FIOPAD_J45, FPIN_FUNC7); /* adc1-2: func 7 */
break;
case FADC_CHANNEL_3:
FPinSetFunc(FIOPAD_N45, FPIN_FUNC7); /* adc1-3: func 7 */
break;
case FADC_CHANNEL_4:
FPinSetFunc(FIOPAD_L47, FPIN_FUNC7); /* adc1-4: func 7 */
break;
case FADC_CHANNEL_5:
FPinSetFunc(FIOPAD_L45, FPIN_FUNC7); /* adc1-5: func 7 */
break;
case FADC_CHANNEL_6:
FPinSetFunc(FIOPAD_N49, FPIN_FUNC7); /* adc1-6: func 7 */
break;
case FADC_CHANNEL_7:
FPinSetFunc(FIOPAD_J49, FPIN_FUNC7); /* adc1-7: func 7 */
break;
default:
FIOPAD_ERROR("adc %d channel %d is error.\r\n", adc_id, adc_channel);
break;
case FADC_CHANNEL_0:
FPinSetFunc(FIOPAD_R47, FPIN_FUNC7); /* adc0-0: func 7 */
break;
case FADC_CHANNEL_1:
FPinSetFunc(FIOPAD_R45, FPIN_FUNC7); /* adc0-1: func 7 */
break;
case FADC_CHANNEL_2:
FPinSetFunc(FIOPAD_N47, FPIN_FUNC7); /* adc0-2: func 7 */
break;
case FADC_CHANNEL_3:
FPinSetFunc(FIOPAD_N51, FPIN_FUNC7); /* adc0-3: func 7 */
break;
case FADC_CHANNEL_4:
FPinSetFunc(FIOPAD_L51, FPIN_FUNC7); /* adc0-4: func 7 */
break;
case FADC_CHANNEL_5:
FPinSetFunc(FIOPAD_J51, FPIN_FUNC7); /* adc0-5: func 7 */
break;
case FADC_CHANNEL_6:
FPinSetFunc(FIOPAD_J41, FPIN_FUNC7); /* adc0-6: func 7 */
break;
case FADC_CHANNEL_7:
FPinSetFunc(FIOPAD_E43, FPIN_FUNC7); /* adc0-7: func 7 */
break;
default:
FIOPAD_ERROR("adc %d channel %d is error.\r\n", adc_id, adc_channel);
break;
}
}
else
@ -366,104 +359,104 @@ void FIOPadSetMioMux(u32 mio_id)
{
switch (mio_id)
{
case MIO_INSTANCE_0:
{
FPinSetFunc(FIOPAD_A37, FPIN_FUNC5); /* scl */
FPinSetFunc(FIOPAD_A39, FPIN_FUNC5); /* sda */
}
break;
case MIO_INSTANCE_1:
{
FPinSetFunc(FIOPAD_A41, FPIN_FUNC5); /* scl */
FPinSetFunc(FIOPAD_C41, FPIN_FUNC5); /* sda */
}
break;
case MIO_INSTANCE_2:
{
FPinSetFunc(FIOPAD_A43, FPIN_FUNC5); /* scl */
FPinSetFunc(FIOPAD_A45, FPIN_FUNC5); /* sda */
}
break;
case MIO_INSTANCE_3:
{
FPinSetFunc(FIOPAD_BA51, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_BA49, FPIN_FUNC4); /* sda */
}
break;
case MIO_INSTANCE_4:
{
FPinSetFunc(FIOPAD_R55, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_U55, FPIN_FUNC4); /* sda */
}
break;
case MIO_INSTANCE_5:
{
FPinSetFunc(FIOPAD_W45, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_U53, FPIN_FUNC4); /* sda */
}
break;
case MIO_INSTANCE_6:
{
FPinSetFunc(FIOPAD_AA53, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_AA55, FPIN_FUNC4); /* sda */
}
break;
case MIO_INSTANCE_7:
{
FPinSetFunc(FIOPAD_A35, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_C35, FPIN_FUNC4); /* sda */
}
break;
case MIO_INSTANCE_8:
{
FPinSetFunc(FIOPAD_AA45, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_W45, FPIN_FUNC4); /* sda */
}
break;
case MIO_INSTANCE_9:
{
FPinSetFunc(FIOPAD_AA47, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_U45, FPIN_FUNC4); /* sda */
}
break;
case MIO_INSTANCE_10:
{
FPinSetFunc(FIOPAD_C45, FPIN_FUNC5); /* scl */
FPinSetFunc(FIOPAD_A47, FPIN_FUNC5); /* sda */
}
break;
case MIO_INSTANCE_11:
{
FPinSetFunc(FIOPAD_N23, FPIN_FUNC3); /* scl */
FPinSetFunc(FIOPAD_L25, FPIN_FUNC3); /* sda */
}
break;
case MIO_INSTANCE_12:
{
FPinSetFunc(FIOPAD_E37, FPIN_FUNC3); /* scl */
FPinSetFunc(FIOPAD_L41, FPIN_FUNC3); /* sda */
}
break;
case MIO_INSTANCE_13:
{
FPinSetFunc(FIOPAD_J45, FPIN_FUNC6); /* scl */
FPinSetFunc(FIOPAD_N45, FPIN_FUNC6); /* sda */
}
break;
case MIO_INSTANCE_14:
{
FPinSetFunc(FIOPAD_L47, FPIN_FUNC6); /* scl */
FPinSetFunc(FIOPAD_L45, FPIN_FUNC6); /* sda */
}
break;
case MIO_INSTANCE_15:
{
FPinSetFunc(FIOPAD_N49, FPIN_FUNC6); /* scl */
FPinSetFunc(FIOPAD_J49, FPIN_FUNC6); /* sda */
}
break;
default:
case FMIO0_ID:
{
FPinSetFunc(FIOPAD_A37, FPIN_FUNC5); /* scl */
FPinSetFunc(FIOPAD_A39, FPIN_FUNC5); /* sda */
}
break;
case FMIO1_ID:
{
FPinSetFunc(FIOPAD_A41, FPIN_FUNC5); /* scl */
FPinSetFunc(FIOPAD_C41, FPIN_FUNC5); /* sda */
}
break;
case FMIO2_ID:
{
FPinSetFunc(FIOPAD_A43, FPIN_FUNC5); /* scl */
FPinSetFunc(FIOPAD_A45, FPIN_FUNC5); /* sda */
}
break;
case FMIO3_ID:
{
FPinSetFunc(FIOPAD_BA51, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_BA49, FPIN_FUNC4); /* sda */
}
break;
case FMIO4_ID:
{
FPinSetFunc(FIOPAD_R55, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_U55, FPIN_FUNC4); /* sda */
}
break;
case FMIO5_ID:
{
FPinSetFunc(FIOPAD_W45, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_U53, FPIN_FUNC4); /* sda */
}
break;
case FMIO6_ID:
{
FPinSetFunc(FIOPAD_AA53, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_AA55, FPIN_FUNC4); /* sda */
}
break;
case FMIO7_ID:
{
FPinSetFunc(FIOPAD_A35, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_C35, FPIN_FUNC4); /* sda */
}
break;
case FMIO8_ID:
{
FPinSetFunc(FIOPAD_AA45, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_W45, FPIN_FUNC4); /* sda */
}
break;
case FMIO9_ID:
{
FPinSetFunc(FIOPAD_AA47, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_U45, FPIN_FUNC4); /* sda */
}
break;
case FMIO10_ID:
{
FPinSetFunc(FIOPAD_C45, FPIN_FUNC5); /* scl */
FPinSetFunc(FIOPAD_A47, FPIN_FUNC5); /* sda */
}
break;
case FMIO11_ID:
{
FPinSetFunc(FIOPAD_N23, FPIN_FUNC3); /* scl */
FPinSetFunc(FIOPAD_L25, FPIN_FUNC3); /* sda */
}
break;
case FMIO12_ID:
{
FPinSetFunc(FIOPAD_E37, FPIN_FUNC3); /* scl */
FPinSetFunc(FIOPAD_L41, FPIN_FUNC3); /* sda */
}
break;
case FMIO13_ID:
{
FPinSetFunc(FIOPAD_J45, FPIN_FUNC6); /* scl */
FPinSetFunc(FIOPAD_N45, FPIN_FUNC6); /* sda */
}
break;
case FMIO14_ID:
{
FPinSetFunc(FIOPAD_L47, FPIN_FUNC6); /* scl */
FPinSetFunc(FIOPAD_L45, FPIN_FUNC6); /* sda */
}
break;
case FMIO15_ID:
{
FPinSetFunc(FIOPAD_N49, FPIN_FUNC6); /* scl */
FPinSetFunc(FIOPAD_J49, FPIN_FUNC6); /* sda */
}
break;
default:
break;
}
}
@ -477,56 +470,56 @@ void FIOPadSetTachoMux(u32 pwm_in_id)
{
switch (pwm_in_id)
{
case TACHO_INSTANCE_0:
FPinSetFunc(FIOPAD_AN53, FPIN_FUNC1);
break;
case TACHO_INSTANCE_1:
FPinSetFunc(FIOPAD_AJ55, FPIN_FUNC1);
break;
case TACHO_INSTANCE_2:
FPinSetFunc(FIOPAD_AG55, FPIN_FUNC1);
break;
case TACHO_INSTANCE_3:
FPinSetFunc(FIOPAD_AE55, FPIN_FUNC1);
break;
case TACHO_INSTANCE_4:
FPinSetFunc(FIOPAD_AC53, FPIN_FUNC1);
break;
case TACHO_INSTANCE_5:
FPinSetFunc(FIOPAD_BA49, FPIN_FUNC1);
break;
case TACHO_INSTANCE_6:
FPinSetFunc(FIOPAD_C33, FPIN_FUNC2);
break;
case TACHO_INSTANCE_7:
FPinSetFunc(FIOPAD_A37, FPIN_FUNC2);
break;
case TACHO_INSTANCE_8:
FPinSetFunc(FIOPAD_A41, FPIN_FUNC2);
break;
case TACHO_INSTANCE_9:
FPinSetFunc(FIOPAD_A43, FPIN_FUNC2);
break;
case TACHO_INSTANCE_10:
FPinSetFunc(FIOPAD_C45, FPIN_FUNC2);
break;
case TACHO_INSTANCE_11:
FPinSetFunc(FIOPAD_A29, FPIN_FUNC2);
break;
case TACHO_INSTANCE_12:
FPinSetFunc(FIOPAD_C27, FPIN_FUNC2);
break;
case TACHO_INSTANCE_13:
FPinSetFunc(FIOPAD_AA45, FPIN_FUNC2);
break;
case TACHO_INSTANCE_14:
FPinSetFunc(FIOPAD_AA47, FPIN_FUNC2);
break;
case TACHO_INSTANCE_15:
FPinSetFunc(FIOPAD_G55, FPIN_FUNC2);
break;
default:
break;
case FTACHO0_ID:
FPinSetFunc(FIOPAD_AN53, FPIN_FUNC1);
break;
case FTACHO1_ID:
FPinSetFunc(FIOPAD_AJ55, FPIN_FUNC1);
break;
case FTACHO2_ID:
FPinSetFunc(FIOPAD_AG55, FPIN_FUNC1);
break;
case FTACHO3_ID:
FPinSetFunc(FIOPAD_AE55, FPIN_FUNC1);
break;
case FTACHO4_ID:
FPinSetFunc(FIOPAD_AC53, FPIN_FUNC1);
break;
case FTACHO5_ID:
FPinSetFunc(FIOPAD_BA49, FPIN_FUNC1);
break;
case FTACHO6_ID:
FPinSetFunc(FIOPAD_C33, FPIN_FUNC2);
break;
case FTACHO7_ID:
FPinSetFunc(FIOPAD_A37, FPIN_FUNC2);
break;
case FTACHO8_ID:
FPinSetFunc(FIOPAD_A41, FPIN_FUNC2);
break;
case FTACHO9_ID:
FPinSetFunc(FIOPAD_A43, FPIN_FUNC2);
break;
case FTACHO10_ID:
FPinSetFunc(FIOPAD_C45, FPIN_FUNC2);
break;
case FTACHO11_ID:
FPinSetFunc(FIOPAD_A29, FPIN_FUNC2);
break;
case FTACHO12_ID:
FPinSetFunc(FIOPAD_C27, FPIN_FUNC2);
break;
case FTACHO13_ID:
FPinSetFunc(FIOPAD_AA45, FPIN_FUNC2);
break;
case FTACHO14_ID:
FPinSetFunc(FIOPAD_AA47, FPIN_FUNC2);
break;
case FTACHO15_ID:
FPinSetFunc(FIOPAD_G55, FPIN_FUNC2);
break;
default:
break;
}
}
@ -540,23 +533,23 @@ void FIOPadSetUartMux(u32 uart_id)
{
switch (uart_id)
{
case FUART0_ID:
FPinSetFunc(FIOPAD_J33, FPIN_FUNC4);
FPinSetFunc(FIOPAD_J35, FPIN_FUNC4);
break;
case FUART1_ID:
FPinSetFunc(FIOPAD_AW47, FPIN_FUNC0);
FPinSetFunc(FIOPAD_AU47, FPIN_FUNC0);
break;
case FUART2_ID:
FPinSetFunc(FIOPAD_A43, FPIN_FUNC0);
FPinSetFunc(FIOPAD_A45, FPIN_FUNC0);
break;
case FUART3_ID:
FPinSetFunc(FIOPAD_L33, FPIN_FUNC2);
FPinSetFunc(FIOPAD_N31, FPIN_FUNC2);
break;
default:
break;
case FUART0_ID:
FPinSetFunc(FIOPAD_J33, FPIN_FUNC4);
FPinSetFunc(FIOPAD_J35, FPIN_FUNC4);
break;
case FUART1_ID:
FPinSetFunc(FIOPAD_AW47, FPIN_FUNC0);
FPinSetFunc(FIOPAD_AU47, FPIN_FUNC0);
break;
case FUART2_ID:
FPinSetFunc(FIOPAD_A43, FPIN_FUNC0);
FPinSetFunc(FIOPAD_A45, FPIN_FUNC0);
break;
case FUART3_ID:
FPinSetFunc(FIOPAD_L33, FPIN_FUNC2);
FPinSetFunc(FIOPAD_N31, FPIN_FUNC2);
break;
default:
break;
}
}

2
bsp/phytium/libraries/standalone/board/e2000/d/fparameters.h
View File

@ -14,7 +14,7 @@
* FilePath: fparameters.h
* Date: 2022-02-11 13:33:28
* LastEditTime: 2022-02-17 18:00:50
* Description:  This files is for
* Description:  This file is for
*
* Modify History:
* Ver   Who        Date         Changes

20
bsp/phytium/libraries/standalone/board/e2000/fiopad_comm.c
View File

@ -14,7 +14,7 @@
* FilePath: fiopad_comm.c
* Date: 2022-02-10 14:53:42
* LastEditTime: 2022-02-18 08:25:29
* Description:  This files is for io-pad function definition
* Description:  This file is for io-pad function definition
*
* Modify History:
* Ver   Who        Date         Changes
@ -202,7 +202,7 @@ void FPinGetConfig(const FPinIndex pin, FPinFunc *func, FPinPull *pull, FPinDriv
if (drive)
{
*pull = FIOPAD_X_REG0_DRIVE_GET(reg_val);
*drive = FIOPAD_X_REG0_DRIVE_GET(reg_val);
}
return;
@ -331,16 +331,24 @@ boolean FPinGetDelayEn(const FPinIndex pin, FPinDelayDir dir)
if (FPIN_OUTPUT_DELAY == dir)
{
if (FIOPAD_X_REG1_OUT_DELAY_EN & reg_val)
{
enabled = TRUE;
}
else
{
enabled = FALSE;
}
}
else if (FPIN_INPUT_DELAY == dir)
{
if (FIOPAD_X_REG1_IN_DELAY_EN & reg_val)
{
enabled = TRUE;
}
else
{
enabled = FALSE;
}
}
else
{
@ -424,16 +432,24 @@ void FPinSetDelayEn(const FPinIndex pin, FPinDelayDir dir, boolean enable)
if (FPIN_OUTPUT_DELAY == dir)
{
if (enable)
{
reg_val |= FIOPAD_X_REG1_OUT_DELAY_EN;
}
else
{
reg_val &= ~FIOPAD_X_REG1_OUT_DELAY_EN;
}
}
else if (FPIN_INPUT_DELAY == dir)
{
if (enable)
{
reg_val |= FIOPAD_X_REG1_IN_DELAY_EN;
}
else
{
reg_val &= ~FIOPAD_X_REG1_IN_DELAY_EN;
}
}
else
{

4
bsp/phytium/libraries/standalone/board/e2000/fiopad_comm.h
View File

@ -17,10 +17,10 @@ extern "C"
/***************** Macros (Inline Functions) Definitions *********************/
#define FIOPAD_INDEX(offset) \
{ \
{ \
/* reg_off */ (offset), \
/* reg_bit */ (0) \
}
}
/*****************************************************************************/
/* register offset of iopad function / pull / driver strength */

571
bsp/phytium/libraries/standalone/board/e2000/fparameters_comm.h
View File

@ -14,7 +14,7 @@
* FilePath: fparameters_comm.h
* Date: 2022-02-10 14:53:42
* LastEditTime: 2022-02-17 18:01:11
* Description:  This files is for
* Description:  This file is for
*
* Modify History:
* Ver   Who        Date         Changes
@ -44,55 +44,55 @@ extern "C"
#define FT_DEV_END_ADDR 0x2FFFFFFFU
/* PCI */
#define FT_PCIE_NUM 1
#define FT_PCIE0_ID 0
#define FT_PCIE0_MISC_IRQ_NUM 40
#define FPCIE_NUM 1
#define FPCIE0_ID 0
#define FPCIE0_MISC_IRQ_NUM 40
#define FT_PCIE_CFG_MAX_NUM_OF_BUS 256
#define FT_PCIE_CFG_MAX_NUM_OF_DEV 32
#define FT_PCIE_CFG_MAX_NUM_OF_FUN 8
#define FPCIE_CFG_MAX_NUM_OF_BUS 256
#define FPCIE_CFG_MAX_NUM_OF_DEV 32
#define FPCIE_CFG_MAX_NUM_OF_FUN 8
#define FT_PCI_CONFIG_BASEADDR 0x40000000U
#define FT_PCI_CONFIG_REG_LENGTH 0x10000000U
#define FPCI_CONFIG_BASE_ADDR 0x40000000U
#define FPCI_CONFIG_REG_LENGTH 0x10000000U
#define FT_PCI_IO_CONFIG_BASEADDR 0x50000000U
#define FT_PCI_IO_CONFIG_REG_LENGTH 0x08000000U
#define FPCI_IO_CONFIG_BASE_ADDR 0x50000000U
#define FPCI_IO_CONFIG_REG_LENGTH 0x08000000U
#define FT_PCI_MEM32_BASEADDR 0x58000000U
#define FT_PCI_MEM32_REG_LENGTH 0x27FFFFFFU
#define FPCI_MEM32_BASE_ADDR 0x58000000U
#define FPCI_MEM32_REG_LENGTH 0x27FFFFFFU
#define FT_PCI_MEM64_BASEADDR 0x1000000000U
#define FT_PCI_MEM64_REG_LENGTH 0x1000000000U
#define FPCI_MEM64_BASE_ADDR 0x1000000000U
#define FPCI_MEM64_REG_LENGTH 0x1000000000U
#define FT_PCI_EU0_C0_CONTROL_BASEADDR 0x29000000U
#define FT_PCI_EU0_C1_CONTROL_BASEADDR 0x29010000U
#define FT_PCI_EU0_C2_CONTROL_BASEADDR 0x29020000U
#define FT_PCI_EU1_C0_CONTROL_BASEADDR 0x29030000U
#define FT_PCI_EU1_C1_CONTROL_BASEADDR 0x29040000U
#define FT_PCI_EU1_C2_CONTROL_BASEADDR 0x29050000U
#define FPCI_EU0_C0_CONTROL_BASE_ADDR 0x29000000U
#define FPCI_EU0_C1_CONTROL_BASE_ADDR 0x29010000U
#define FPCI_EU0_C2_CONTROL_BASE_ADDR 0x29020000U
#define FPCI_EU1_C0_CONTROL_BASE_ADDR 0x29030000U
#define FPCI_EU1_C1_CONTROL_BASE_ADDR 0x29040000U
#define FPCI_EU1_C2_CONTROL_BASE_ADDR 0x29050000U
#define FT_PCI_EU0_CONFIG_BASEADDR 0x29100000U
#define FT_PCI_EU1_CONFIG_BASEADDR 0x29101000U
#define FPCI_EU0_CONFIG_BASE_ADDR 0x29100000U
#define FPCI_EU1_CONFIG_BASE_ADDR 0x29101000U
#define FT_PCI_INTA_IRQ_NUM 36
#define FT_PCI_INTB_IRQ_NUM 37
#define FT_PCI_INTC_IRQ_NUM 38
#define FT_PCI_INTD_IRQ_NUM 39
#define FPCI_INTA_IRQ_NUM 36
#define FPCI_INTB_IRQ_NUM 37
#define FPCI_INTC_IRQ_NUM 38
#define FPCI_INTD_IRQ_NUM 39
#define FT_PCI_NEED_SKIP 0
#define FPCI_NEED_SKIP 0
#define FT_PCI_INTX_PEU0_STAT 0x29100000U
#define FT_PCI_INTX_PEU1_STAT 0x29101000U
#define FPCI_INTX_PEU0_STAT 0x29100000U
#define FPCI_INTX_PEU1_STAT 0x29101000U
#define FT_PCI_INTX_EU0_C0_CONTROL 0x29000184U
#define FT_PCI_INTX_EU0_C1_CONTROL 0x29010184U
#define FT_PCI_INTX_EU0_C2_CONTROL 0x29020184U
#define FT_PCI_INTX_EU1_C0_CONTROL 0x29030184U
#define FT_PCI_INTX_EU1_C1_CONTROL 0x29040184U
#define FT_PCI_INTX_EU1_C2_CONTROL 0x29050184U
#define FPCI_INTX_EU0_C0_CONTROL 0x29000184U
#define FPCI_INTX_EU0_C1_CONTROL 0x29010184U
#define FPCI_INTX_EU0_C2_CONTROL 0x29020184U
#define FPCI_INTX_EU1_C0_CONTROL 0x29030184U
#define FPCI_INTX_EU1_C1_CONTROL 0x29040184U
#define FPCI_INTX_EU1_C2_CONTROL 0x29050184U
#define FT_PCI_INTX_CONTROL_NUM 6 /* Total number of controllers */
#define FT_PCI_INTX_SATA_NUM 2 /* Total number of controllers */
#define FPCI_INTX_CONTROL_NUM 6 /* Total number of controllers */
#define FPCI_INTX_SATA_NUM 2 /* Total number of controllers */
/* platform ahci host */
@ -110,22 +110,37 @@ extern "C"
#define AHCI_IRQ_4 0
/* sata controller */
#define FSATA0_BASEADDR 0x31A40000U
#define FSATA1_BASEADDR 0x32014000U
#define FSATA0_BASE_ADDR 0x31A40000U
#define FSATA1_BASE_ADDR 0x32014000U
#define FSATA0_IRQNUM 74
#define FSATA1_IRQNUM 75
#define FSATA0_IRQ_NUM 74
#define FSATA1_IRQ_NUM 75
#if !defined(__ASSEMBLER__)
typedef enum
enum
{
FSATA_INSTANCE_0 = 0,
FSATA_INSTANCE_1 = 1,
FSATA0_ID = 0,
FSATA1_ID = 1,
FSATA_INSTANCE_NUM
} FSataInstance;
FSATA_NUM
};
#endif
/* SCMI and MHU */
#define FSCMI_MHU_BASE_ADDR 0x32a00000
#define FSCMI_MHU_IRQ_NUM (22U + 32U)
#define FSCMI_SHR_MEM_ADDR 0x32a11400
#define FSCMI_MEM_TX_OFSET 0x1400
#define FSCMI_MEM_RX_OFSET 0x1000
#define FSCMI_SHR_MEM_SIZE 0x400
#define FSCMI_MSG_SIZE 128
#define FSCMI_MAX_STR_SIZE 16
#define FSCMI_MAX_NUM_SENSOR 16
#define FSCMI_MAX_PROTOCOLS_IMP 16
#define FSCMI_MAX_PERF_DOMAINS 3
#define FSCMI_MAX_OPPS 4
/* Generic Timer */
#define GENERIC_TIMER_CLK_FREQ_MHZ 48U
#define GENERIC_TIMER_NS_IRQ_NUM 30U
@ -169,7 +184,7 @@ typedef enum
#define GICV3_MAX_INTR_PRIO_VAL 240U
#define GICV3_INTR_PRIO_MASK 0x000000f0U
#define ARM_GIC_NR_IRQS 160U
#define ARM_GIC_NR_IRQS 270U
#define ARM_GIC_IRQ_START 0U
#define FGIC_NUM 1U
@ -179,28 +194,35 @@ typedef enum
#define PPI_START_INT_NUM 16U /* PPI start at ID16 */
#define GIC_INT_MAX_NUM 1020U /* GIC max interrupts count */
#define GICV3_BASEADDRESS 0x30800000U
#define GICV3_DISTRIBUTOR_BASEADDRESS (GICV3_BASEADDRESS + 0)
#define GICV3_RD_BASEADDRESS (GICV3_BASEADDRESS + 0x80000U)
#define GICV3_BASE_ADDR 0x30800000U
#define GICV3_DISTRIBUTOR_BASE_ADDR (GICV3_BASE_ADDR + 0)
#define GICV3_RD_BASE_ADDR (GICV3_BASE_ADDR + 0x80000U)
#define GICV3_RD_OFFSET (2U << 16)
#define FT_GICV3_VECTORTABLE_NUM GIC_INT_MAX_NUM
/* GPIO */
#define FGPIO_ID_0 0U
#define FGPIO_ID_1 1U
#define FGPIO_ID_2 2U
#define FGPIO_WITH_PIN_IRQ 2U /* max id of gpio assign irq for each pin */
#define FGPIO_ID_3 3U
#define FGPIO_ID_4 4U
#define FGPIO_ID_5 5U
#define FGPIO_NUM 6U
#if !defined(__ASSEMBLER__)
enum
{
FGPIO0_ID = 0,
FGPIO1_ID = 1,
FGPIO2_ID,
FGPIO3_ID,
FGPIO4_ID,
FGPIO5_ID,
#define FGPIO_0_BASE_ADDR 0x28034000U
#define FGPIO_1_BASE_ADDR 0x28035000U
#define FGPIO_2_BASE_ADDR 0x28036000U
#define FGPIO_3_BASE_ADDR 0x28037000U
#define FGPIO_4_BASE_ADDR 0x28038000U
#define FGPIO_5_BASE_ADDR 0x28039000U
FGPIO_NUM
};
#endif
#define FGPIO_WITH_PIN_IRQ 2U /* max id of gpio assign irq for each pin */
#define FGPIO0_BASE_ADDR 0x28034000U
#define FGPIO1_BASE_ADDR 0x28035000U
#define FGPIO2_BASE_ADDR 0x28036000U
#define FGPIO3_BASE_ADDR 0x28037000U
#define FGPIO4_BASE_ADDR 0x28038000U
#define FGPIO5_BASE_ADDR 0x28039000U
#define FGPIO_CTRL_PIN_NUM 16U
@ -214,8 +236,8 @@ typedef enum
#define FGPIO_PIN_IRQ_TOTAL 51U
/* SPI */
#define FSPI0_BASE 0x2803A000U
#define FSPI1_BASE 0x2803B000U
#define FSPI0_BASE_ADDR 0x2803A000U
#define FSPI1_BASE_ADDR 0x2803B000U
#define FSPI2_BASE 0x2803C000U
#define FSPI3_BASE 0x2803D000U
#define FSPI0_ID 0U
@ -228,90 +250,88 @@ typedef enum
#define FSPI2_IRQ_NUM 193U
#define FSPI3_IRQ_NUM 194U
#define FSPI_FREQ 50000000U
#define FSPI_DEVICE_NUM 4U
#define FSPI_CLK_FREQ_HZ 50000000U
#define FSPI_NUM 4U
/* XMAC */
#define FT_XMAC_NUM 4U
#define FXMAC_NUM 4U
#define FT_XMAC0_ID 0U
#define FT_XMAC1_ID 1U
#define FT_XMAC2_ID 2U
#define FT_XMAC3_ID 3U
#define FXMAC0_ID 0U
#define FXMAC1_ID 1U
#define FXMAC2_ID 2U
#define FXMAC3_ID 3U
#define FT_XMAC0_BASEADDRESS 0x3200C000U
#define FT_XMAC1_BASEADDRESS 0x3200E000U
#define FT_XMAC2_BASEADDRESS 0x32010000U
#define FT_XMAC3_BASEADDRESS 0x32012000U
#define FXMAC0_BASE_ADDR 0x3200C000U
#define FXMAC1_BASE_ADDR 0x3200E000U
#define FXMAC2_BASE_ADDR 0x32010000U
#define FXMAC3_BASE_ADDR 0x32012000U
#define FT_XMAC0_MODE_SEL_BASEADDRESS 0x3200DC00U
#define FT_XMAC0_LOOPBACK_SEL_BASEADDRESS 0x3200DC04U
#define FT_XMAC1_MODE_SEL_BASEADDRESS 0x3200FC00U
#define FT_XMAC1_LOOPBACK_SEL_BASEADDRESS 0x3200FC04U
#define FT_XMAC2_MODE_SEL_BASEADDRESS 0x32011C00U
#define FT_XMAC2_LOOPBACK_SEL_BASEADDRESS 0x32011C04U
#define FT_XMAC3_MODE_SEL_BASEADDRESS 0x32013C00U
#define FT_XMAC3_LOOPBACK_SEL_BASEADDRESS 0x32013C04U
#define FXMAC0_MODE_SEL_BASE_ADDR 0x3200DC00U
#define FXMAC0_LOOPBACK_SEL_BASE_ADDR 0x3200DC04U
#define FXMAC1_MODE_SEL_BASE_ADDR 0x3200FC00U
#define FXMAC1_LOOPBACK_SEL_BASE_ADDR 0x3200FC04U
#define FXMAC2_MODE_SEL_BASE_ADDR 0x32011C00U
#define FXMAC2_LOOPBACK_SEL_BASE_ADDR 0x32011C04U
#define FXMAC3_MODE_SEL_BASE_ADDR 0x32013C00U
#define FXMAC3_LOOPBACK_SEL_BASE_ADDR 0x32013C04U
#define FT_XMAC0_PCLK 50000000U
#define FT_XMAC1_PCLK 50000000U
#define FT_XMAC2_PCLK 50000000U
#define FT_XMAC3_PCLK 50000000U
#define FT_XMAC0_HOTPLUG_IRQ_NUM (53U + 30U)
#define FT_XMAC1_HOTPLUG_IRQ_NUM (54U + 30U)
#define FT_XMAC2_HOTPLUG_IRQ_NUM (55U + 30U)
#define FT_XMAC3_HOTPLUG_IRQ_NUM (56U + 30U)
#define FXMAC0_PCLK 50000000U
#define FXMAC1_PCLK 50000000U
#define FXMAC2_PCLK 50000000U
#define FXMAC3_PCLK 50000000U
#define FXMAC0_HOTPLUG_IRQ_NUM (53U + 30U)
#define FXMAC1_HOTPLUG_IRQ_NUM (54U + 30U)
#define FXMAC2_HOTPLUG_IRQ_NUM (55U + 30U)
#define FXMAC3_HOTPLUG_IRQ_NUM (56U + 30U)
#define FT_XMAC_QUEUE_MAX_NUM 16U
#define FXMAC_QUEUE_MAX_NUM 16U
#define FT_XMAC0_QUEUE0_IRQ_NUM (57U + 30U)
#define FT_XMAC0_QUEUE1_IRQ_NUM (58U + 30U)
#define FT_XMAC0_QUEUE2_IRQ_NUM (59U + 30U)
#define FT_XMAC0_QUEUE3_IRQ_NUM (60U + 30U)
#define FT_XMAC0_QUEUE4_IRQ_NUM (30U + 30U)
#define FT_XMAC0_QUEUE5_IRQ_NUM (31U + 30U)
#define FT_XMAC0_QUEUE6_IRQ_NUM (32U + 30U)
#define FT_XMAC0_QUEUE7_IRQ_NUM (33U + 30U)
#define FXMAC0_QUEUE0_IRQ_NUM (57U + 30U)
#define FXMAC0_QUEUE1_IRQ_NUM (58U + 30U)
#define FXMAC0_QUEUE2_IRQ_NUM (59U + 30U)
#define FXMAC0_QUEUE3_IRQ_NUM (60U + 30U)
#define FXMAC0_QUEUE4_IRQ_NUM (30U + 30U)
#define FXMAC0_QUEUE5_IRQ_NUM (31U + 30U)
#define FXMAC0_QUEUE6_IRQ_NUM (32U + 30U)
#define FXMAC0_QUEUE7_IRQ_NUM (33U + 30U)
#define FT_XMAC1_QUEUE0_IRQ_NUM (61U + 30U)
#define FT_XMAC1_QUEUE1_IRQ_NUM (62U + 30U)
#define FT_XMAC1_QUEUE2_IRQ_NUM (63U + 30U)
#define FT_XMAC1_QUEUE3_IRQ_NUM (64U + 30U)
#define FXMAC1_QUEUE0_IRQ_NUM (61U + 30U)
#define FXMAC1_QUEUE1_IRQ_NUM (62U + 30U)
#define FXMAC1_QUEUE2_IRQ_NUM (63U + 30U)
#define FXMAC1_QUEUE3_IRQ_NUM (64U + 30U)
#define FT_XMAC2_QUEUE0_IRQ_NUM (66U + 30U)
#define FT_XMAC2_QUEUE1_IRQ_NUM (67U + 30U)
#define FT_XMAC2_QUEUE2_IRQ_NUM (68U + 30U)
#define FT_XMAC2_QUEUE3_IRQ_NUM (69U + 30U)
#define FXMAC2_QUEUE0_IRQ_NUM (66U + 30U)
#define FXMAC2_QUEUE1_IRQ_NUM (67U + 30U)
#define FXMAC2_QUEUE2_IRQ_NUM (68U + 30U)
#define FXMAC2_QUEUE3_IRQ_NUM (69U + 30U)
#define FT_XMAC3_QUEUE0_IRQ_NUM (70U + 30U)
#define FT_XMAC3_QUEUE1_IRQ_NUM (71U + 30U)
#define FT_XMAC3_QUEUE2_IRQ_NUM (72U + 30U)
#define FT_XMAC3_QUEUE3_IRQ_NUM (73U + 30U)
#define FXMAC3_QUEUE0_IRQ_NUM (70U + 30U)
#define FXMAC3_QUEUE1_IRQ_NUM (71U + 30U)
#define FXMAC3_QUEUE2_IRQ_NUM (72U + 30U)
#define FXMAC3_QUEUE3_IRQ_NUM (73U + 30U)
#define FT_XMAC_PHY_MAX_NUM 32U
#define FXMAC_PHY_MAX_NUM 32U
/* QSPI */
#define FQSPI_BASEADDR 0x028008000U
#if !defined(__ASSEMBLER__)
typedef enum
enum
{
FQSPI_INSTANCE_0 = 0,
FQSPI0_ID = 0,
FQSPI_INSTANCE_NUM
} FQspiInstance;
FQSPI_NUM
};
#define FQSPI_BASE_ADDR 0x028008000U
/* FQSPI cs 0_3, chip number */
typedef enum
enum
{
FQSPI_CS_0 = 0,
FQSPI_CS_1 = 1,
FQSPI_CS_2 = 2,
FQSPI_CS_3 = 3,
FQSPI_CS_NUM
} FQspiChipCS;
};
#endif
@ -321,113 +341,112 @@ typedef enum
#define FQSPI_MEM_END_ADDR_64 0x17FFFFFFFU /* 2GB */
/* TIMER and TACHO */
#define TIMER_NUM 38U
#define TACHO_NUM 16U
#define TIMER_CLK_FREQ_HZ 50000000U /* 50MHz */
#define TIMER_TICK_PERIOD_NS 20U /* 20ns */
#define TIMER_TACHO_IRQ_ID(n) (226U + (n))
#define TIMER_TACHO_BASE_ADDR(n) (0x28054000U + 0x1000U * (n))
#define FTIMER_NUM 38U
#define FTIMER_CLK_FREQ_HZ 50000000U /* 50MHz */
#define FTIMER_TICK_PERIOD_NS 20U /* 20ns */
#define FTIMER_TACHO_IRQ_NUM(n) (226U + (n))
#define FTIMER_TACHO_BASE_ADDR(n) (0x28054000U + 0x1000U * (n))
#if !defined(__ASSEMBLER__)
typedef enum
enum
{
TACHO_INSTANCE_0 = 0,
TACHO_INSTANCE_1 = 1,
TACHO_INSTANCE_2 = 2,
TACHO_INSTANCE_3 = 3,
TACHO_INSTANCE_4 = 4,
TACHO_INSTANCE_5 = 5,
TACHO_INSTANCE_6 = 6,
TACHO_INSTANCE_7 = 7,
TACHO_INSTANCE_8 = 8,
TACHO_INSTANCE_9 = 9,
TACHO_INSTANCE_10 = 10,
TACHO_INSTANCE_11 = 11,
TACHO_INSTANCE_12 = 12,
TACHO_INSTANCE_13 = 13,
TACHO_INSTANCE_14 = 14,
TACHO_INSTANCE_15 = 15,
FTACHO0_ID = 0,
FTACHO1_ID = 1,
FTACHO2_ID,
FTACHO3_ID,
FTACHO4_ID,
FTACHO5_ID,
FTACHO6_ID,
FTACHO7_ID,
FTACHO8_ID,
FTACHO9_ID,
FTACHO10_ID,
FTACHO11_ID,
FTACHO12_ID,
FTACHO13_ID,
FTACHO14_ID,
FTACHO15_ID,
TACHO_INSTANCE_NUM
} TachoInstance;
FTACHO_NUM
} ;
#endif
/* GDMA */
#define FGDMA0_ID 0U
#define FGDMA0_BASE_ADDR 0x32B34000U
#define FGDMA0_IRQ_NUM 266U
#define FGDMA0_CHANNEL0_IRQ_NUM 266U
#define FGDMA_NUM_OF_CHAN 16
#define FGDMA_INSTANCE_NUM 1U
#define FGDMA0_CAPACITY (1U<<0)
/* CANFD */
#define FCAN_REF_CLOCK 200000000U
#define FCAN_CLK_FREQ_HZ 200000000U
#define FCAN0_BASEADDR 0x2800A000U
#define FCAN1_BASEADDR 0x2800B000U
#define FCAN0_BASE_ADDR 0x2800A000U
#define FCAN1_BASE_ADDR 0x2800B000U
#define FCAN0_IRQNUM 113U
#define FCAN1_IRQNUM 114U
#define FCAN0_IRQ_NUM 113U
#define FCAN1_IRQ_NUM 114U
#if !defined(__ASSEMBLER__)
typedef enum
enum
{
FCAN_INSTANCE_0 = 0,
FCAN_INSTANCE_1 = 1,
FCAN0_ID = 0,
FCAN1_ID = 1,
FCAN_INSTANCE_NUM
} FCanInstance;
FCAN_NUM
};
#endif
/* WDT */
#if !defined(__ASSEMBLER__)
typedef enum
enum
{
FWDT_INSTANCE_0 = 0,
FWDT_INSTANCE_1,
FWDT0_ID = 0,
FWDT1_ID,
FWDT_INSTANCE_NUM
} FWdtInstance;
FWDT_NUM
};
#endif
#define FWDT0_REFRESH_BASE 0x28040000U
#define FWDT0_CONTROL_BASE 0x28041000U
#define FWDT1_REFRESH_BASE 0x28042000U
#define FWDT1_CONTROL_BASE 0x28043000U
#define FWDT0_REFRESH_BASE_ADDR 0x28040000U
#define FWDT1_REFRESH_BASE_ADDR 0x28042000U
#define FWDT0_INTR_IRQ 196U
#define FWDT1_INTR_IRQ 197U
#define FWDT_CONTROL_BASE_ADDR(x) ((x)+0x1000)
#define FWDT_CLK 48000000U /* 48MHz */
#define FWDT0_IRQ_NUM 196U
#define FWDT1_IRQ_NUM 197U
#define FWDT_CLK_FREQ_HZ 48000000U /* 48MHz */
/*MIO*/
#define FMIO_NUM 16
#define FMIO_BASE_ADDR(n) (0x28014000 + 0x2000 * (n))
#define FMIO_CONF_ADDR(n) FMIO_BASE_ADDR(n)+0x1000
#define FMIO_IRQ_NUM(n) (124+n)
#define MIO_REF_CLK_HZ 50000000 /* 50MHz */
#define FMIO_CLK_FREQ_HZ 50000000 /* 50MHz */
#if !defined(__ASSEMBLER__)
typedef enum
enum
{
MIO_INSTANCE_0 = 0,
MIO_INSTANCE_1,
MIO_INSTANCE_2,
MIO_INSTANCE_3,
MIO_INSTANCE_4,
MIO_INSTANCE_5,
MIO_INSTANCE_6,
MIO_INSTANCE_7,
MIO_INSTANCE_8,
MIO_INSTANCE_9,
MIO_INSTANCE_10,
MIO_INSTANCE_11,
MIO_INSTANCE_12,
MIO_INSTANCE_13,
MIO_INSTANCE_14,
MIO_INSTANCE_15,
FMIO0_ID = 0,
FMIO1_ID = 1,
FMIO2_ID,
FMIO3_ID,
FMIO4_ID,
FMIO5_ID,
FMIO6_ID,
FMIO7_ID,
FMIO8_ID,
FMIO9_ID,
FMIO10_ID,
FMIO11_ID,
FMIO12_ID,
FMIO13_ID,
FMIO14_ID,
FMIO15_ID,
MIO_INSTANCE_NUM
} MioInstance;
FMIO_NUM
};
#endif
#if !defined(__ASSEMBLER__)
@ -435,49 +454,49 @@ typedef enum
* I2C1 -> PMBUS1
* I2C2 -> SMBUS0
*/
typedef enum
enum
{
I2C_INSTANCE_0 = 0,
I2C_INSTANCE_1,
I2C_INSTANCE_2,
FI2C0_ID = 0,
FI2C1_ID,
FI2C2_ID,
I2C_INSTANCE_NUM
} I2cInstance;
FI2C_NUM
};
#endif
#define I2C_0_BASEADDR 0x28011000
#define I2C_1_BASEADDR 0x28012000
#define I2C_2_BASEADDR 0x28013000
#define FI2C0_BASE_ADDR 0x28011000
#define FI2C1_BASE_ADDR 0x28012000
#define FI2C2_BASE_ADDR 0x28013000
#define I2C_0_INTR_IRQ 121
#define I2C_1_INTR_IRQ 122
#define I2C_2_INTR_IRQ 123
#define FI2C0_IRQ_NUM 121
#define FI2C1_IRQ_NUM 122
#define FI2C2_IRQ_NUM 123
#define I2C_REF_CLK_HZ 50000000 /* 50MHz */
#define FI2C_CLK_FREQ_HZ 50000000 /* 50MHz */
/* SDIO */
#if !defined(__ASSEMBLER__)
enum
{
FSDIO_HOST_INSTANCE_0 = 0,
FSDIO_HOST_INSTANCE_1,
FSDIO0_ID = 0,
FSDIO1_ID = 1,
FSDIO_HOST_INSTANCE_NUM
FSDIO_NUM
};
#endif
#define FSDIO_HOST_0_BASE_ADDR 0x28000000U
#define FSDIO_HOST_1_BASE_ADDR 0x28001000U
#define FSDIO0_BASE_ADDR 0x28000000U
#define FSDIO1_BASE_ADDR 0x28001000U
#define FSDIO_HOST_0_IRQ_NUM 104U
#define FSDIO_HOST_1_IRQ_NUM 105U
#define FSDIO0_IRQ_NUM 104U
#define FSDIO1_IRQ_NUM 105U
#define FSDIO_CLK_RATE_HZ (1200000000UL) /* 1.2GHz */
#define FSDIO_CLK_FREQ_HZ (1200000000UL) /* 1.2GHz */
/* NAND */
#define FNAND_NUM 1U
#define FNAND_INSTANCE0 0U
#define FNAND_BASEADDRESS 0x28002000U
#define FNAND_BASE_ADDR 0x28002000U
#define FNAND_IRQ_NUM (106U)
#define FNAND_CONNECT_MAX_NUM 1U
@ -519,13 +538,12 @@ enum
/* ADC */
#if !defined(__ASSEMBLER__)
typedef enum
enum
{
FADC_INSTANCE_0 = 0,
FADC_INSTANCE_1,
FADC0_ID = 0,
FADC_INSTANCE_NUM
} FAdcInstance;
FADC_NUM
};
typedef enum
{
@ -543,27 +561,25 @@ typedef enum
#endif
#define FADC0_CONTROL_BASE 0x2807B000U
#define FADC1_CONTROL_BASE 0x2807C000U
#define FADC0_BASE_ADDR 0x2807B000U
#define FADC0_INTR_IRQ 264U
#define FADC1_INTR_IRQ 265U
#define FADC0_IRQ_NUM 264U
/* PWM */
#if !defined(__ASSEMBLER__)
typedef enum
enum
{
FPWM_INSTANCE_0 = 0,
FPWM_INSTANCE_1,
FPWM_INSTANCE_2,
FPWM_INSTANCE_3,
FPWM_INSTANCE_4,
FPWM_INSTANCE_5,
FPWM_INSTANCE_6,
FPWM_INSTANCE_7,
FPWM0_ID = 0,
FPWM1_ID = 1,
FPWM2_ID,
FPWM3_ID,
FPWM4_ID,
FPWM5_ID,
FPWM6_ID,
FPWM7_ID,
FPWM_INSTANCE_NUM
} FPwmInstance;
FPWM_NUM
};
typedef enum
{
@ -574,26 +590,26 @@ typedef enum
} FPwmChannel;
#endif
#define FPWM_CONTROL_BASE 0x2804A000U
#define FPWM_BASE_ADDR 0x2804A000U
#define FPWM_CLK 50000000U /* 50MHz */
#define FPWM_CLK_FREQ_HZ 50000000U /* 50MHz */
#define FPWM0_INTR_IRQ 205U
#define FPWM1_INTR_IRQ 206U
#define FPWM2_INTR_IRQ 207U
#define FPWM3_INTR_IRQ 208U
#define FPWM4_INTR_IRQ 209U
#define FPWM5_INTR_IRQ 210U
#define FPWM6_INTR_IRQ 211U
#define FPWM7_INTR_IRQ 212U
#define FPWM8_INTR_IRQ 213U
#define FPWM9_INTR_IRQ 214U
#define FPWM10_INTR_IRQ 215U
#define FPWM11_INTR_IRQ 216U
#define FPWM12_INTR_IRQ 217U
#define FPWM13_INTR_IRQ 218U
#define FPWM14_INTR_IRQ 219U
#define FPWM15_INTR_IRQ 220U
#define FPWM0_IRQ_NUM 205U
#define FPWM1_IRQ_NUM 206U
#define FPWM2_IRQ_NUM 207U
#define FPWM3_IRQ_NUM 208U
#define FPWM4_IRQ_NUM 209U
#define FPWM5_IRQ_NUM 210U
#define FPWM6_IRQ_NUM 211U
#define FPWM7_IRQ_NUM 212U
#define FPWM8_IRQ_NUM 213U
#define FPWM9_IRQ_NUM 214U
#define FPWM10_IRQ_NUM 215U
#define FPWM11_IRQ_NUM 216U
#define FPWM12_IRQ_NUM 217U
#define FPWM13_IRQ_NUM 218U
#define FPWM14_IRQ_NUM 219U
#define FPWM15_IRQ_NUM 220U
/* Semaphore */
#define FSEMA0_ID 0U
@ -606,14 +622,41 @@ typedef enum
#define FLSD_CK_STOP_CONFIG0_HADDR 0x10U
/* USB3 */
#define FUSB3_ID_0 0U
#define FUSB3_ID_1 1U
#define FUSB3_NUM 2U
#define FUSB3_XHCI_OFFSET 0x8000U
#define FUSB3_0_BASE_ADDR 0x31A00000U
#define FUSB3_1_BASE_ADDR 0x31A20000U
#define FUSB3_0_IRQ_NUM 48U
#define FUSB3_1_IRQ_NUM 49U
#define FUSB3_ID_0 0U
#define FUSB3_ID_1 1U
#define FUSB3_NUM 2U
#define FUSB3_XHCI_OFFSET 0x8000U
#define FUSB3_0_BASE_ADDR 0x31A00000U
#define FUSB3_1_BASE_ADDR 0x31A20000U
#define FUSB3_0_IRQ_NUM 48U
#define FUSB3_1_IRQ_NUM 49U
/* DcDp */
#if !defined(__ASSEMBLER__)
typedef enum
{
FDCDP_ID0 = 0,
FDCDP_ID1,
FDCDP_INSTANCE_NUM
} FDcDpNum;
#endif
#define FDC_CTRL_BASE_OFFSET 0x32000000U
#define FDC0_CHANNEL_BASE_OFFSET 0x32001000U
#define FDC1_CHANNEL_BASE_OFFSET (FDC0_CHANNEL_BASE_OFFSET + 0x1000U)
#define FDP0_CHANNEL_BASE_OFFSET 0x32004000U
#define FDP1_CHANNEL_BASE_OFFSET (FDP0_CHANNEL_BASE_OFFSET + 0x1000U)
#define FDP0_PHY_BASE_OFFSET 0x32300000U
#define FDP1_PHY_BASE_OFFSET (FDP0_PHY_BASE_OFFSET + 0x100000U)
#define FDCDP_IRQ_NUM 76
/*****************************************************************************/
#ifdef __cplusplus

702
bsp/phytium/libraries/standalone/board/e2000/q/fiopad_config.c
View File

@ -14,7 +14,7 @@
* FilePath: fiopad_config.c
* Date: 2022-02-10 14:53:42
* LastEditTime: 2022-02-18 08:25:29
* Description:  This files is for io-pad function definition
* Description:  This file is for io-pad function definition
*
* Modify History:
* Ver   Who        Date         Changes
@ -93,6 +93,17 @@ void FIOPadSetSpimMux(u32 spim_id)
}
}
static void FIOPadDumpGpioPin(FPinIndex pin, u32 gpio_id, u32 pin_id)
{
FPinFunc func = FPIN_FUNC0;
FPinPull pull = FPIN_PULL_NONE;
FPinDrive drive = FPIN_DRV0;
FPinGetConfig(pin, &func, &pull, &drive);
FIOPAD_DEBUG("GPIO-%d-%d: func: %d, pull: %d, drive: %d",
gpio_id, pin_id, func, pull, drive);
}
/**
* @name: FIOPadSetGpioMux
* @msg: set iopad mux for gpio
@ -102,59 +113,71 @@ void FIOPadSetSpimMux(u32 spim_id)
*/
void FIOPadSetGpioMux(u32 gpio_id, u32 pin_id)
{
if (FGPIO_ID_2 == gpio_id)
if (FGPIO2_ID == gpio_id)
{
switch (pin_id)
{
case 11: /* gpio 2-a-11 */
FPinSetFunc(FIOPAD_N49, FPIN_FUNC0);
break;
case 12: /* gpio 2-a-12 */
FPinSetFunc(FIOPAD_L51, FPIN_FUNC0);
break;
case 13: /* gpio 2-a-13 */
FPinSetFunc(FIOPAD_L49, FPIN_FUNC0);
break;
case 14: /* gpio 2-a-14 */
FPinSetFunc(FIOPAD_N53, FPIN_FUNC0);
break;
case 15: /* gpio 2-a-15 */
FPinSetFunc(FIOPAD_J53, FPIN_FUNC0);
break;
case 11: /* gpio 2-a-11 */
FPinSetFunc(FIOPAD_N49, FPIN_FUNC0);
break;
case 12: /* gpio 2-a-12 */
FPinSetFunc(FIOPAD_L51, FPIN_FUNC0);
break;
case 13: /* gpio 2-a-13 */
FPinSetFunc(FIOPAD_L49, FPIN_FUNC0);
break;
case 14: /* gpio 2-a-14 */
FPinSetFunc(FIOPAD_N53, FPIN_FUNC0);
break;
case 15: /* gpio 2-a-15 */
FPinSetFunc(FIOPAD_J53, FPIN_FUNC0);
break;
}
}
else if (FGPIO_ID_3 == gpio_id)
else if (FGPIO3_ID == gpio_id)
{
switch (pin_id)
{
case 3: /* gpio 3-a-3 */
FPinSetFunc(FIOPAD_A33, FPIN_FUNC6);
break;
case 4: /* gpio 3-a-4 */
FPinSetFunc(FIOPAD_C33, FPIN_FUNC6);
break;
case 5: /* gpio 3-a-5 */
FPinSetFunc(FIOPAD_C31, FPIN_FUNC6);
break;
case 6: /* gpio 3-a-6 */
FPinSetFunc(FIOPAD_A31, FPIN_FUNC6);
break;
default:
break;
case 3: /* gpio 3-a-3 */
FPinSetFunc(FIOPAD_A33, FPIN_FUNC6);
break;
case 4: /* gpio 3-a-4 */
FPinSetFunc(FIOPAD_C33, FPIN_FUNC6);
break;
case 5: /* gpio 3-a-5 */
FPinSetFunc(FIOPAD_C31, FPIN_FUNC6);
break;
case 6: /* gpio 3-a-6 */
FPinSetFunc(FIOPAD_A31, FPIN_FUNC6);
break;
default:
break;
}
}
else if (FGPIO_ID_4 == gpio_id)
else if (FGPIO4_ID == gpio_id)
{
switch (pin_id)
{
case 5: /* gpio 4-a-5 */
FPinSetFunc(FIOPAD_W51, FPIN_FUNC6);
break;
case 9: /* gpio 4-a-9 */
FPinSetFunc(FIOPAD_U53, FPIN_FUNC6);
break;
default:
break;
case 5: /* gpio 4-a-5 */
FPinSetFunc(FIOPAD_W51, FPIN_FUNC6);
break;
case 9: /* gpio 4-a-9 */
FPinSetFunc(FIOPAD_U53, FPIN_FUNC6);
break;
case 10: /* gpio 4-a-10 */
FPinSetFunc(FIOPAD_AE49, FPIN_FUNC6);
break;
case 11: /* gpio 4-a-11 */
FPinSetFunc(FIOPAD_AC49, FPIN_FUNC6);
break;
case 12: /* gpio 4-a-12 */
FPinSetFunc(FIOPAD_AE47, FPIN_FUNC6);
break;
case 13: /* gpio 4-a-13 */
FPinSetFunc(FIOPAD_AA47, FPIN_FUNC6);
break;
default:
break;
}
}
}
@ -168,15 +191,15 @@ void FIOPadSetGpioMux(u32 gpio_id, u32 pin_id)
*/
void FIOPadSetCanMux(u32 can_id)
{
if (can_id == FCAN_INSTANCE_0)
if (can_id == FCAN0_ID)
{
/* mio0 */
/* can0 */
FPinSetFunc(FIOPAD_A41, FPIN_FUNC0); /* can0-tx: func 0 */
FPinSetFunc(FIOPAD_A43, FPIN_FUNC0); /* can0-rx: func 0 */
}
else if (can_id == FCAN_INSTANCE_1)
else if (can_id == FCAN1_ID)
{
/* mio1 */
/* can1 */
FPinSetFunc(FIOPAD_A45, FPIN_FUNC0); /* can1-tx: func 0 */
FPinSetFunc(FIOPAD_C45, FPIN_FUNC0); /* can1-rx: func 0 */
}
@ -196,7 +219,7 @@ void FIOPadSetCanMux(u32 can_id)
void FIOPadSetQspiMux(u32 qspi_id, u32 cs_id)
{
if (qspi_id == FQSPI_INSTANCE_0)
if (qspi_id == FQSPI0_ID)
{
/* add sck, io0-io3 iopad multiplex */
}
@ -232,102 +255,102 @@ void FIOPadSetQspiMux(u32 qspi_id, u32 cs_id)
*/
void FIOPadSetPwmMux(u32 pwm_id, u32 pwm_channel)
{
FASSERT(pwm_id < FPWM_INSTANCE_NUM);
FASSERT(pwm_id < FPWM_NUM);
FASSERT(pwm_channel < FPWM_CHANNEL_NUM);
switch (pwm_id)
{
case FPWM_INSTANCE_0:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_AL59, FPIN_FUNC1); /* PWM0_OUT: func 1 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_AJ57, FPIN_FUNC1); /* PWM1_OUT: func 1 */
}
break;
case FPWM0_ID:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_AL59, FPIN_FUNC1); /* PWM0_OUT: func 1 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_AJ57, FPIN_FUNC1); /* PWM1_OUT: func 1 */
}
break;
case FPWM_INSTANCE_1:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_AG57, FPIN_FUNC1); /* PWM2_OUT: func 1 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_AC59, FPIN_FUNC1); /* PWM3_OUT: func 1 */
}
break;
case FPWM1_ID:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_AG57, FPIN_FUNC1); /* PWM2_OUT: func 1 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_AC59, FPIN_FUNC1); /* PWM3_OUT: func 1 */
}
break;
case FPWM_INSTANCE_2:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_BA55, FPIN_FUNC1); /* PWM4_OUT: func 1 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_C39, FPIN_FUNC2); /* PWM5_OUT: func 2 */
}
break;
case FPWM2_ID:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_BA55, FPIN_FUNC1); /* PWM4_OUT: func 1 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_C39, FPIN_FUNC2); /* PWM5_OUT: func 2 */
}
break;
case FPWM_INSTANCE_3:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_A37, FPIN_FUNC2); /* PWM6_OUT: func 2 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_A43, FPIN_FUNC2); /* PWM7_OUT: func 2 */
}
break;
case FPWM3_ID:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_A37, FPIN_FUNC2); /* PWM6_OUT: func 2 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_A43, FPIN_FUNC2); /* PWM7_OUT: func 2 */
}
break;
case FPWM_INSTANCE_4:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_C45, FPIN_FUNC2); /* PWM8_OUT: func 2 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_A49, FPIN_FUNC2); /* PWM9_OUT: func 2 */
}
break;
case FPWM4_ID:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_C45, FPIN_FUNC2); /* PWM8_OUT: func 2 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_A49, FPIN_FUNC2); /* PWM9_OUT: func 2 */
}
break;
case FPWM_INSTANCE_5:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_A51, FPIN_FUNC2); /* PWM10_OUT: func 2 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_C33, FPIN_FUNC2); /* PWM11_OUT: func 2 */
}
break;
case FPWM5_ID:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_A51, FPIN_FUNC2); /* PWM10_OUT: func 2 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_C33, FPIN_FUNC2); /* PWM11_OUT: func 2 */
}
break;
case FPWM_INSTANCE_6:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_A31, FPIN_FUNC2); /* PWM12_OUT: func 2 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_J39, FPIN_FUNC3); /* PWM13_OUT: func 3 */
}
break;
case FPWM6_ID:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_A31, FPIN_FUNC2); /* PWM12_OUT: func 2 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_J39, FPIN_FUNC3); /* PWM13_OUT: func 3 */
}
break;
case FPWM_INSTANCE_7:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_E43, FPIN_FUNC3); /* PWM14_OUT: func 3 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_C43, FPIN_FUNC3); /* PWM15_OUT: func 3 */
}
break;
case FPWM7_ID:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_E43, FPIN_FUNC3); /* PWM14_OUT: func 3 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_C43, FPIN_FUNC3); /* PWM15_OUT: func 3 */
}
break;
default:
FIOPAD_ERROR("pwm id is error.\r\n");
break;
default:
FIOPAD_ERROR("pwm id is error.\r\n");
break;
}
}
@ -341,70 +364,37 @@ void FIOPadSetPwmMux(u32 pwm_id, u32 pwm_channel)
*/
void FIOPadSetAdcMux(u32 adc_id, u32 adc_channel)
{
if (adc_id == FADC_INSTANCE_0)
if (adc_id == FADC0_ID)
{
switch (adc_channel)
{
case FADC_CHANNEL_0:
FPinSetFunc(FIOPAD_R51, FPIN_FUNC7); /* adc0-0: func 7 */
break;
case FADC_CHANNEL_1:
FPinSetFunc(FIOPAD_R49, FPIN_FUNC7); /* adc0-1: func 7 */
break;
case FADC_CHANNEL_2:
FPinSetFunc(FIOPAD_N51, FPIN_FUNC7); /* adc0-2: func 7 */
break;
case FADC_CHANNEL_3:
FPinSetFunc(FIOPAD_N55, FPIN_FUNC7); /* adc0-3: func 7 */
break;
case FADC_CHANNEL_4:
FPinSetFunc(FIOPAD_L55, FPIN_FUNC7); /* adc0-4: func 7 */
break;
case FADC_CHANNEL_5:
FPinSetFunc(FIOPAD_J55, FPIN_FUNC7); /* adc0-5: func 7 */
break;
case FADC_CHANNEL_6:
FPinSetFunc(FIOPAD_J45, FPIN_FUNC7); /* adc0-6: func 7 */
break;
case FADC_CHANNEL_7:
FPinSetFunc(FIOPAD_E47, FPIN_FUNC7); /* adc0-7: func 7 */
break;
default:
FIOPAD_ERROR("adc %d channel %d is error.\r\n", adc_id, adc_channel);
break;
}
}
else if (adc_id == FADC_INSTANCE_1)
{
switch (adc_channel)
{
case FADC_CHANNEL_0:
FPinSetFunc(FIOPAD_G47, FPIN_FUNC7); /* adc1-0: func 7 */
break;
case FADC_CHANNEL_1:
FPinSetFunc(FIOPAD_J47, FPIN_FUNC7); /* adc1-1: func 7 */
break;
case FADC_CHANNEL_2:
FPinSetFunc(FIOPAD_J49, FPIN_FUNC7); /* adc1-2: func 7 */
break;
case FADC_CHANNEL_3:
FPinSetFunc(FIOPAD_N49, FPIN_FUNC7); /* adc1-3: func 7 */
break;
case FADC_CHANNEL_4:
FPinSetFunc(FIOPAD_L51, FPIN_FUNC7); /* adc1-4: func 7 */
break;
case FADC_CHANNEL_5:
FPinSetFunc(FIOPAD_L49, FPIN_FUNC7); /* adc1-5: func 7 */
break;
case FADC_CHANNEL_6:
FPinSetFunc(FIOPAD_N53, FPIN_FUNC7); /* adc1-6: func 7 */
break;
case FADC_CHANNEL_7:
FPinSetFunc(FIOPAD_J53, FPIN_FUNC7); /* adc1-7: func 7 */
break;
default:
FIOPAD_ERROR("adc %d channel %d is error.\r\n", adc_id, adc_channel);
break;
case FADC_CHANNEL_0:
FPinSetFunc(FIOPAD_R51, FPIN_FUNC7); /* adc0-0: func 7 */
break;
case FADC_CHANNEL_1:
FPinSetFunc(FIOPAD_R49, FPIN_FUNC7); /* adc0-1: func 7 */
break;
case FADC_CHANNEL_2:
FPinSetFunc(FIOPAD_N51, FPIN_FUNC7); /* adc0-2: func 7 */
break;
case FADC_CHANNEL_3:
FPinSetFunc(FIOPAD_N55, FPIN_FUNC7); /* adc0-3: func 7 */
break;
case FADC_CHANNEL_4:
FPinSetFunc(FIOPAD_L55, FPIN_FUNC7); /* adc0-4: func 7 */
break;
case FADC_CHANNEL_5:
FPinSetFunc(FIOPAD_J55, FPIN_FUNC7); /* adc0-5: func 7 */
break;
case FADC_CHANNEL_6:
FPinSetFunc(FIOPAD_J45, FPIN_FUNC7); /* adc0-6: func 7 */
break;
case FADC_CHANNEL_7:
FPinSetFunc(FIOPAD_E47, FPIN_FUNC7); /* adc0-7: func 7 */
break;
default:
FIOPAD_ERROR("adc %d channel %d is error.\r\n", adc_id, adc_channel);
break;
}
}
else
@ -423,104 +413,104 @@ void FIOPadSetMioMux(u32 mio_id)
{
switch (mio_id)
{
case MIO_INSTANCE_0:
{
FPinSetFunc(FIOPAD_A41, FPIN_FUNC5); /* scl */
FPinSetFunc(FIOPAD_A43, FPIN_FUNC5); /* sda */
}
break;
case MIO_INSTANCE_1:
{
FPinSetFunc(FIOPAD_A45, FPIN_FUNC5); /* scl */
FPinSetFunc(FIOPAD_C45, FPIN_FUNC5); /* sda */
}
break;
case MIO_INSTANCE_2:
{
FPinSetFunc(FIOPAD_A47, FPIN_FUNC5); /* scl */
FPinSetFunc(FIOPAD_A49, FPIN_FUNC5); /* sda */
}
break;
case MIO_INSTANCE_3:
{
FPinSetFunc(FIOPAD_BA55, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_BA53, FPIN_FUNC4); /* sda */
}
break;
case MIO_INSTANCE_4:
{
FPinSetFunc(FIOPAD_R59, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_U59, FPIN_FUNC4); /* sda */
}
break;
case MIO_INSTANCE_5:
{
FPinSetFunc(FIOPAD_W49, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_U57, FPIN_FUNC4); /* sda */
}
break;
case MIO_INSTANCE_6:
{
FPinSetFunc(FIOPAD_AA57, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_AA59, FPIN_FUNC4); /* sda */
}
break;
case MIO_INSTANCE_7:
{
FPinSetFunc(FIOPAD_A39, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_C39, FPIN_FUNC4); /* sda */
}
break;
case MIO_INSTANCE_8:
{
FPinSetFunc(FIOPAD_AA49, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_W49, FPIN_FUNC4); /* sda */
}
break;
case MIO_INSTANCE_9:
{
FPinSetFunc(FIOPAD_AA51, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_U49, FPIN_FUNC4); /* sda */
}
break;
case MIO_INSTANCE_10:
{
FPinSetFunc(FIOPAD_C49, FPIN_FUNC5); /* scl */
FPinSetFunc(FIOPAD_A51, FPIN_FUNC5); /* sda */
}
break;
case MIO_INSTANCE_11:
{
FPinSetFunc(FIOPAD_N27, FPIN_FUNC3); /* scl */
FPinSetFunc(FIOPAD_L29, FPIN_FUNC3); /* sda */
}
break;
case MIO_INSTANCE_12:
{
FPinSetFunc(FIOPAD_E41, FPIN_FUNC3); /* scl */
FPinSetFunc(FIOPAD_L45, FPIN_FUNC3); /* sda */
}
break;
case MIO_INSTANCE_13:
{
FPinSetFunc(FIOPAD_J49, FPIN_FUNC6); /* scl */
FPinSetFunc(FIOPAD_N49, FPIN_FUNC6); /* sda */
}
break;
case MIO_INSTANCE_14:
{
FPinSetFunc(FIOPAD_L51, FPIN_FUNC6); /* scl */
FPinSetFunc(FIOPAD_L49, FPIN_FUNC6); /* sda */
}
break;
case MIO_INSTANCE_15:
{
FPinSetFunc(FIOPAD_N53, FPIN_FUNC6); /* scl */
FPinSetFunc(FIOPAD_J53, FPIN_FUNC6); /* sda */
}
break;
default:
case FMIO0_ID:
{
FPinSetFunc(FIOPAD_A41, FPIN_FUNC5); /* scl */
FPinSetFunc(FIOPAD_A43, FPIN_FUNC5); /* sda */
}
break;
case FMIO1_ID:
{
FPinSetFunc(FIOPAD_A45, FPIN_FUNC5); /* scl */
FPinSetFunc(FIOPAD_C45, FPIN_FUNC5); /* sda */
}
break;
case FMIO2_ID:
{
FPinSetFunc(FIOPAD_A47, FPIN_FUNC5); /* scl */
FPinSetFunc(FIOPAD_A49, FPIN_FUNC5); /* sda */
}
break;
case FMIO3_ID:
{
FPinSetFunc(FIOPAD_BA55, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_BA53, FPIN_FUNC4); /* sda */
}
break;
case FMIO4_ID:
{
FPinSetFunc(FIOPAD_R59, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_U59, FPIN_FUNC4); /* sda */
}
break;
case FMIO5_ID:
{
FPinSetFunc(FIOPAD_W49, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_U57, FPIN_FUNC4); /* sda */
}
break;
case FMIO6_ID:
{
FPinSetFunc(FIOPAD_AA57, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_AA59, FPIN_FUNC4); /* sda */
}
break;
case FMIO7_ID:
{
FPinSetFunc(FIOPAD_A39, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_C39, FPIN_FUNC4); /* sda */
}
break;
case FMIO8_ID:
{
FPinSetFunc(FIOPAD_AA49, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_W49, FPIN_FUNC4); /* sda */
}
break;
case FMIO9_ID:
{
FPinSetFunc(FIOPAD_AA51, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_U49, FPIN_FUNC4); /* sda */
}
break;
case FMIO10_ID:
{
FPinSetFunc(FIOPAD_C49, FPIN_FUNC5); /* scl */
FPinSetFunc(FIOPAD_A51, FPIN_FUNC5); /* sda */
}
break;
case FMIO11_ID:
{
FPinSetFunc(FIOPAD_N27, FPIN_FUNC3); /* scl */
FPinSetFunc(FIOPAD_L29, FPIN_FUNC3); /* sda */
}
break;
case FMIO12_ID:
{
FPinSetFunc(FIOPAD_E41, FPIN_FUNC3); /* scl */
FPinSetFunc(FIOPAD_L45, FPIN_FUNC3); /* sda */
}
break;
case FMIO13_ID:
{
FPinSetFunc(FIOPAD_J49, FPIN_FUNC6); /* scl */
FPinSetFunc(FIOPAD_N49, FPIN_FUNC6); /* sda */
}
break;
case FMIO14_ID:
{
FPinSetFunc(FIOPAD_L51, FPIN_FUNC6); /* scl */
FPinSetFunc(FIOPAD_L49, FPIN_FUNC6); /* sda */
}
break;
case FMIO15_ID:
{
FPinSetFunc(FIOPAD_N53, FPIN_FUNC6); /* scl */
FPinSetFunc(FIOPAD_J53, FPIN_FUNC6); /* sda */
}
break;
default:
break;
}
}
@ -534,56 +524,56 @@ void FIOPadSetTachoMux(u32 pwm_in_id)
{
switch (pwm_in_id)
{
case TACHO_INSTANCE_0:
FPinSetFunc(FIOPAD_AN57, FPIN_FUNC1);
break;
case TACHO_INSTANCE_1:
FPinSetFunc(FIOPAD_AJ59, FPIN_FUNC1);
break;
case TACHO_INSTANCE_2:
FPinSetFunc(FIOPAD_AG59, FPIN_FUNC1);
break;
case TACHO_INSTANCE_3:
FPinSetFunc(FIOPAD_AE59, FPIN_FUNC1);
break;
case TACHO_INSTANCE_4:
FPinSetFunc(FIOPAD_AC57, FPIN_FUNC1);
break;
case TACHO_INSTANCE_5:
FPinSetFunc(FIOPAD_BA53, FPIN_FUNC1);
break;
case TACHO_INSTANCE_6:
FPinSetFunc(FIOPAD_C37, FPIN_FUNC2);
break;
case TACHO_INSTANCE_7:
FPinSetFunc(FIOPAD_A41, FPIN_FUNC2);
break;
case TACHO_INSTANCE_8:
FPinSetFunc(FIOPAD_A45, FPIN_FUNC2);
break;
case TACHO_INSTANCE_9:
FPinSetFunc(FIOPAD_A47, FPIN_FUNC2);
break;
case TACHO_INSTANCE_10:
FPinSetFunc(FIOPAD_C49, FPIN_FUNC2);
break;
case TACHO_INSTANCE_11:
FPinSetFunc(FIOPAD_A33, FPIN_FUNC2);
break;
case TACHO_INSTANCE_12:
FPinSetFunc(FIOPAD_C31, FPIN_FUNC2);
break;
case TACHO_INSTANCE_13:
FPinSetFunc(FIOPAD_AA49, FPIN_FUNC2);
break;
case TACHO_INSTANCE_14:
FPinSetFunc(FIOPAD_AA51, FPIN_FUNC2);
break;
case TACHO_INSTANCE_15:
FPinSetFunc(FIOPAD_G59, FPIN_FUNC2);
break;
default:
break;
case FTACHO0_ID:
FPinSetFunc(FIOPAD_AN57, FPIN_FUNC1);
break;
case FTACHO1_ID:
FPinSetFunc(FIOPAD_AJ59, FPIN_FUNC1);
break;
case FTACHO2_ID:
FPinSetFunc(FIOPAD_AG59, FPIN_FUNC1);
break;
case FTACHO3_ID:
FPinSetFunc(FIOPAD_AE59, FPIN_FUNC1);
break;
case FTACHO4_ID:
FPinSetFunc(FIOPAD_AC57, FPIN_FUNC1);
break;
case FTACHO5_ID:
FPinSetFunc(FIOPAD_BA53, FPIN_FUNC1);
break;
case FTACHO6_ID:
FPinSetFunc(FIOPAD_C37, FPIN_FUNC2);
break;
case FTACHO7_ID:
FPinSetFunc(FIOPAD_A41, FPIN_FUNC2);
break;
case FTACHO8_ID:
FPinSetFunc(FIOPAD_A45, FPIN_FUNC2);
break;
case FTACHO9_ID:
FPinSetFunc(FIOPAD_A47, FPIN_FUNC2);
break;
case FTACHO10_ID:
FPinSetFunc(FIOPAD_C49, FPIN_FUNC2);
break;
case FTACHO11_ID:
FPinSetFunc(FIOPAD_A33, FPIN_FUNC2);
break;
case FTACHO12_ID:
FPinSetFunc(FIOPAD_C31, FPIN_FUNC2);
break;
case FTACHO13_ID:
FPinSetFunc(FIOPAD_AA49, FPIN_FUNC2);
break;
case FTACHO14_ID:
FPinSetFunc(FIOPAD_AA51, FPIN_FUNC2);
break;
case FTACHO15_ID:
FPinSetFunc(FIOPAD_G59, FPIN_FUNC2);
break;
default:
break;
}
}
@ -597,23 +587,23 @@ void FIOPadSetUartMux(u32 uart_id)
{
switch (uart_id)
{
case FUART0_ID:
FPinSetFunc(FIOPAD_J37, FPIN_FUNC4);
FPinSetFunc(FIOPAD_J39, FPIN_FUNC4);
break;
case FUART1_ID:
FPinSetFunc(FIOPAD_AW51, FPIN_FUNC0);
FPinSetFunc(FIOPAD_AU51, FPIN_FUNC0);
break;
case FUART2_ID:
FPinSetFunc(FIOPAD_A47, FPIN_FUNC0);
FPinSetFunc(FIOPAD_A49, FPIN_FUNC0);
break;
case FUART3_ID:
FPinSetFunc(FIOPAD_L37, FPIN_FUNC2);
FPinSetFunc(FIOPAD_N35, FPIN_FUNC2);
break;
default:
break;
case FUART0_ID:
FPinSetFunc(FIOPAD_J37, FPIN_FUNC4);
FPinSetFunc(FIOPAD_J39, FPIN_FUNC4);
break;
case FUART1_ID:
FPinSetFunc(FIOPAD_AW51, FPIN_FUNC0);
FPinSetFunc(FIOPAD_AU51, FPIN_FUNC0);
break;
case FUART2_ID:
FPinSetFunc(FIOPAD_A47, FPIN_FUNC0);
FPinSetFunc(FIOPAD_A49, FPIN_FUNC0);
break;
case FUART3_ID:
FPinSetFunc(FIOPAD_L37, FPIN_FUNC2);
FPinSetFunc(FIOPAD_N35, FPIN_FUNC2);
break;
default:
break;
}
}

2
bsp/phytium/libraries/standalone/board/e2000/q/fparameters.h
View File

@ -14,7 +14,7 @@
* FilePath: fparameters.h
* Date: 2022-02-11 13:33:28
* LastEditTime: 2022-02-17 18:00:50
* Description:  This files is for
* Description:  This file is for
*
* Modify History:
* Ver   Who        Date         Changes

388
bsp/phytium/libraries/standalone/board/e2000/s/fiopad_config.c
View File

@ -14,7 +14,7 @@
* FilePath: fiopad_config.c
* Date: 2022-02-10 14:53:42
* LastEditTime: 2022-02-18 08:25:29
* Description:  This files is for io-pad function definition
* Description:  This file is for io-pad function definition
*
* Modify History:
* Ver   Who        Date         Changes
@ -63,24 +63,50 @@ void FIOPadSetSpimMux(u32 spim_id)
*/
void FIOPadSetGpioMux(u32 gpio_id, u32 pin_id)
{
if (FGPIO_ID_3 == gpio_id)
if (FGPIO3_ID == gpio_id)
{
switch (pin_id)
{
case 3: /* gpio 3-a-3 */
FPinSetFunc(FIOPAD_A29, FPIN_FUNC6);
break;
case 4: /* gpio 3-a-4 */
FPinSetFunc(FIOPAD_C29, FPIN_FUNC6);
break;
case 5: /* gpio 3-a-5 */
FPinSetFunc(FIOPAD_C27, FPIN_FUNC6);
break;
case 6: /* gpio 3-a-6 */
FPinSetFunc(FIOPAD_A27, FPIN_FUNC6);
break;
default:
break;
case 3: /* gpio 3-a-3 */
FPinSetFunc(FIOPAD_A29, FPIN_FUNC6);
break;
case 4: /* gpio 3-a-4 */
FPinSetFunc(FIOPAD_C29, FPIN_FUNC6);
break;
case 5: /* gpio 3-a-5 */
FPinSetFunc(FIOPAD_C27, FPIN_FUNC6);
break;
case 6: /* gpio 3-a-6 */
FPinSetFunc(FIOPAD_A27, FPIN_FUNC6);
break;
default:
break;
}
}
else if (FGPIO4_ID == gpio_id)
{
switch (pin_id)
{
case 5: /* gpio 4-a-5 */
FPinSetFunc(FIOPAD_W47, FPIN_FUNC6);
break;
case 9: /* gpio 4-a-9 */
FPinSetFunc(FIOPAD_U49, FPIN_FUNC6);
break;
case 10: /* gpio 4-a-10 */
FPinSetFunc(FIOPAD_AE45, FPIN_FUNC6);
break;
case 11: /* gpio 4-a-11 */
FPinSetFunc(FIOPAD_AC45, FPIN_FUNC6);
break;
case 12: /* gpio 4-a-12 */
FPinSetFunc(FIOPAD_AE43, FPIN_FUNC6);
break;
case 13: /* gpio 4-a-13 */
FPinSetFunc(FIOPAD_AA43, FPIN_FUNC6);
break;
default:
break;
}
}
}
@ -95,104 +121,104 @@ void FIOPadSetMioMux(u32 mio_id)
{
switch (mio_id)
{
case MIO_INSTANCE_0:
{
FPinSetFunc(FIOPAD_A37, FPIN_FUNC5); /* scl */
FPinSetFunc(FIOPAD_A39, FPIN_FUNC5); /* sda */
}
break;
case MIO_INSTANCE_1:
{
FPinSetFunc(FIOPAD_A41, FPIN_FUNC5); /* scl */
FPinSetFunc(FIOPAD_C41, FPIN_FUNC5); /* sda */
}
break;
case MIO_INSTANCE_2:
{
FPinSetFunc(FIOPAD_A43, FPIN_FUNC5); /* scl */
FPinSetFunc(FIOPAD_A45, FPIN_FUNC5); /* sda */
}
break;
case MIO_INSTANCE_3:
{
FPinSetFunc(FIOPAD_BA51, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_BA49, FPIN_FUNC4); /* sda */
}
break;
case MIO_INSTANCE_4:
{
FPinSetFunc(FIOPAD_R55, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_U55, FPIN_FUNC4); /* sda */
}
break;
case MIO_INSTANCE_5:
{
FPinSetFunc(FIOPAD_W45, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_U53, FPIN_FUNC4); /* sda */
}
break;
case MIO_INSTANCE_6:
{
FPinSetFunc(FIOPAD_AA53, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_AA55, FPIN_FUNC4); /* sda */
}
break;
case MIO_INSTANCE_7:
{
FPinSetFunc(FIOPAD_A35, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_C35, FPIN_FUNC4); /* sda */
}
break;
case MIO_INSTANCE_8:
{
FPinSetFunc(FIOPAD_AA45, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_W45, FPIN_FUNC4); /* sda */
}
break;
case MIO_INSTANCE_9:
{
FPinSetFunc(FIOPAD_AA47, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_U45, FPIN_FUNC4); /* sda */
}
break;
case MIO_INSTANCE_10:
{
FPinSetFunc(FIOPAD_C45, FPIN_FUNC5); /* scl */
FPinSetFunc(FIOPAD_A47, FPIN_FUNC5); /* sda */
}
break;
case MIO_INSTANCE_11:
{
FPinSetFunc(FIOPAD_N23, FPIN_FUNC3); /* scl */
FPinSetFunc(FIOPAD_L25, FPIN_FUNC3); /* sda */
}
break;
case MIO_INSTANCE_12:
{
FPinSetFunc(FIOPAD_E37, FPIN_FUNC3); /* scl */
FPinSetFunc(FIOPAD_L41, FPIN_FUNC3); /* sda */
}
break;
case MIO_INSTANCE_13:
{
FPinSetFunc(FIOPAD_J45, FPIN_FUNC6); /* scl */
FPinSetFunc(FIOPAD_N45, FPIN_FUNC6); /* sda */
}
break;
case MIO_INSTANCE_14:
{
FPinSetFunc(FIOPAD_L47, FPIN_FUNC6); /* scl */
FPinSetFunc(FIOPAD_L45, FPIN_FUNC6); /* sda */
}
break;
case MIO_INSTANCE_15:
{
FPinSetFunc(FIOPAD_N49, FPIN_FUNC6); /* scl */
FPinSetFunc(FIOPAD_J49, FPIN_FUNC6); /* sda */
}
break;
default:
case FMIO0_ID:
{
FPinSetFunc(FIOPAD_A37, FPIN_FUNC5); /* scl */
FPinSetFunc(FIOPAD_A39, FPIN_FUNC5); /* sda */
}
break;
case FMIO1_ID:
{
FPinSetFunc(FIOPAD_A41, FPIN_FUNC5); /* scl */
FPinSetFunc(FIOPAD_C41, FPIN_FUNC5); /* sda */
}
break;
case FMIO2_ID:
{
FPinSetFunc(FIOPAD_A43, FPIN_FUNC5); /* scl */
FPinSetFunc(FIOPAD_A45, FPIN_FUNC5); /* sda */
}
break;
case FMIO3_ID:
{
FPinSetFunc(FIOPAD_BA51, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_BA49, FPIN_FUNC4); /* sda */
}
break;
case FMIO4_ID:
{
FPinSetFunc(FIOPAD_R55, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_U55, FPIN_FUNC4); /* sda */
}
break;
case FMIO5_ID:
{
FPinSetFunc(FIOPAD_W45, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_U53, FPIN_FUNC4); /* sda */
}
break;
case FMIO6_ID:
{
FPinSetFunc(FIOPAD_AA53, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_AA55, FPIN_FUNC4); /* sda */
}
break;
case FMIO7_ID:
{
FPinSetFunc(FIOPAD_A35, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_C35, FPIN_FUNC4); /* sda */
}
break;
case FMIO8_ID:
{
FPinSetFunc(FIOPAD_AA45, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_W45, FPIN_FUNC4); /* sda */
}
break;
case FMIO9_ID:
{
FPinSetFunc(FIOPAD_AA47, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_U45, FPIN_FUNC4); /* sda */
}
break;
case FMIO10_ID:
{
FPinSetFunc(FIOPAD_C45, FPIN_FUNC5); /* scl */
FPinSetFunc(FIOPAD_A47, FPIN_FUNC5); /* sda */
}
break;
case FMIO11_ID:
{
FPinSetFunc(FIOPAD_N23, FPIN_FUNC3); /* scl */
FPinSetFunc(FIOPAD_L25, FPIN_FUNC3); /* sda */
}
break;
case FMIO12_ID:
{
FPinSetFunc(FIOPAD_E37, FPIN_FUNC3); /* scl */
FPinSetFunc(FIOPAD_L41, FPIN_FUNC3); /* sda */
}
break;
case FMIO13_ID:
{
FPinSetFunc(FIOPAD_J45, FPIN_FUNC6); /* scl */
FPinSetFunc(FIOPAD_N45, FPIN_FUNC6); /* sda */
}
break;
case FMIO14_ID:
{
FPinSetFunc(FIOPAD_L47, FPIN_FUNC6); /* scl */
FPinSetFunc(FIOPAD_L45, FPIN_FUNC6); /* sda */
}
break;
case FMIO15_ID:
{
FPinSetFunc(FIOPAD_N49, FPIN_FUNC6); /* scl */
FPinSetFunc(FIOPAD_J49, FPIN_FUNC6); /* sda */
}
break;
default:
break;
}
}
@ -206,56 +232,56 @@ void FIOPadSetTachoMux(u32 pwm_in_id)
{
switch (pwm_in_id)
{
case TACHO_INSTANCE_0:
FPinSetFunc(FIOPAD_AN53, FPIN_FUNC1);
break;
case TACHO_INSTANCE_1:
FPinSetFunc(FIOPAD_AJ55, FPIN_FUNC1);
break;
case TACHO_INSTANCE_2:
FPinSetFunc(FIOPAD_AG55, FPIN_FUNC1);
break;
case TACHO_INSTANCE_3:
FPinSetFunc(FIOPAD_AE55, FPIN_FUNC1);
break;
case TACHO_INSTANCE_4:
FPinSetFunc(FIOPAD_AC53, FPIN_FUNC1);
break;
case TACHO_INSTANCE_5:
FPinSetFunc(FIOPAD_BA49, FPIN_FUNC1);
break;
case TACHO_INSTANCE_6:
FPinSetFunc(FIOPAD_C33, FPIN_FUNC2);
break;
case TACHO_INSTANCE_7:
FPinSetFunc(FIOPAD_A37, FPIN_FUNC2);
break;
case TACHO_INSTANCE_8:
FPinSetFunc(FIOPAD_A41, FPIN_FUNC2);
break;
case TACHO_INSTANCE_9:
FPinSetFunc(FIOPAD_A43, FPIN_FUNC2);
break;
case TACHO_INSTANCE_10:
FPinSetFunc(FIOPAD_C45, FPIN_FUNC2);
break;
case TACHO_INSTANCE_11:
FPinSetFunc(FIOPAD_A29, FPIN_FUNC2);
break;
case TACHO_INSTANCE_12:
FPinSetFunc(FIOPAD_C27, FPIN_FUNC2);
break;
case TACHO_INSTANCE_13:
FPinSetFunc(FIOPAD_AA45, FPIN_FUNC2);
break;
case TACHO_INSTANCE_14:
FPinSetFunc(FIOPAD_AA47, FPIN_FUNC2);
break;
case TACHO_INSTANCE_15:
FPinSetFunc(FIOPAD_G55, FPIN_FUNC2);
break;
default:
break;
case FTACHO0_ID:
FPinSetFunc(FIOPAD_AN53, FPIN_FUNC1);
break;
case FTACHO1_ID:
FPinSetFunc(FIOPAD_AJ55, FPIN_FUNC1);
break;
case FTACHO2_ID:
FPinSetFunc(FIOPAD_AG55, FPIN_FUNC1);
break;
case FTACHO3_ID:
FPinSetFunc(FIOPAD_AE55, FPIN_FUNC1);
break;
case FTACHO4_ID:
FPinSetFunc(FIOPAD_AC53, FPIN_FUNC1);
break;
case FTACHO5_ID:
FPinSetFunc(FIOPAD_BA49, FPIN_FUNC1);
break;
case FTACHO6_ID:
FPinSetFunc(FIOPAD_C33, FPIN_FUNC2);
break;
case FTACHO7_ID:
FPinSetFunc(FIOPAD_A37, FPIN_FUNC2);
break;
case FTACHO8_ID:
FPinSetFunc(FIOPAD_A41, FPIN_FUNC2);
break;
case FTACHO9_ID:
FPinSetFunc(FIOPAD_A43, FPIN_FUNC2);
break;
case FTACHO10_ID:
FPinSetFunc(FIOPAD_C45, FPIN_FUNC2);
break;
case FTACHO11_ID:
FPinSetFunc(FIOPAD_A29, FPIN_FUNC2);
break;
case FTACHO12_ID:
FPinSetFunc(FIOPAD_C27, FPIN_FUNC2);
break;
case FTACHO13_ID:
FPinSetFunc(FIOPAD_AA45, FPIN_FUNC2);
break;
case FTACHO14_ID:
FPinSetFunc(FIOPAD_AA47, FPIN_FUNC2);
break;
case FTACHO15_ID:
FPinSetFunc(FIOPAD_G55, FPIN_FUNC2);
break;
default:
break;
}
}
@ -269,23 +295,23 @@ void FIOPadSetUartMux(u32 uart_id)
{
switch (uart_id)
{
case FUART0_ID:
FPinSetFunc(FIOPAD_J33, FPIN_FUNC4);
FPinSetFunc(FIOPAD_J35, FPIN_FUNC4);
break;
case FUART1_ID:
FPinSetFunc(FIOPAD_AW47, FPIN_FUNC0);
FPinSetFunc(FIOPAD_AU47, FPIN_FUNC0);
break;
case FUART2_ID:
FPinSetFunc(FIOPAD_A43, FPIN_FUNC0);
FPinSetFunc(FIOPAD_A45, FPIN_FUNC0);
break;
case FUART3_ID:
FPinSetFunc(FIOPAD_L33, FPIN_FUNC2);
FPinSetFunc(FIOPAD_N31, FPIN_FUNC2);
break;
default:
break;
case FUART0_ID:
FPinSetFunc(FIOPAD_J33, FPIN_FUNC4);
FPinSetFunc(FIOPAD_J35, FPIN_FUNC4);
break;
case FUART1_ID:
FPinSetFunc(FIOPAD_AW47, FPIN_FUNC0);
FPinSetFunc(FIOPAD_AU47, FPIN_FUNC0);
break;
case FUART2_ID:
FPinSetFunc(FIOPAD_A43, FPIN_FUNC0);
FPinSetFunc(FIOPAD_A45, FPIN_FUNC0);
break;
case FUART3_ID:
FPinSetFunc(FIOPAD_L33, FPIN_FUNC2);
FPinSetFunc(FIOPAD_N31, FPIN_FUNC2);
break;
default:
break;
}
}

2
bsp/phytium/libraries/standalone/board/e2000/s/fparameters.h
View File

@ -14,7 +14,7 @@
* FilePath: fparameters.h
* Date: 2022-02-11 13:33:28
* LastEditTime: 2022-02-17 18:00:50
* Description:  This files is for
* Description:  This file is for
*
* Modify History:
* Ver   Who        Date         Changes

348
bsp/phytium/libraries/standalone/board/ft2004/fioctrl.c Normal file
View File

@ -0,0 +1,348 @@
/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: fioctrl.c
* Date: 2022-02-10 14:53:42
* LastEditTime: 2022-02-18 08:25:29
* Description:  This files is for io-ctrl function implementation (io-mux/io-config/io-delay)
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
* 1.0 zhugengyu 2022/2/22 init commit
*/
/***************************** Include Files *********************************/
#include "fparameters.h"
#include "fio.h"
#include "fkernel.h"
#include "fassert.h"
#include "fdebug.h"
#include "fioctrl.h"
#include "fpinctrl.h"
/************************** Constant Definitions *****************************/
/* Bit[0] : 输入延迟功能使能 */
#define FIOCTRL_DELAY_EN(delay_beg) BIT(delay_beg)
#define FIOCTRL_INPUT_DELAY_OFF 0
/* Bit[3:1] : 输入延迟精调档位选择 */
#define FIOCTRL_DELICATE_DELAY_MASK(delay_beg) GENMASK((delay_beg + 3), (delay_beg + 1))
#define FIOCTRL_DELICATE_DELAY_GET(reg_val, delay_beg) GET_REG32_BITS((reg_val), (delay_beg + 3), (delay_beg + 1))
#define FIOCTRL_DELICATE_DELAY_SET(val, delay_beg) SET_REG32_BITS((val), (delay_beg + 3), (delay_beg + 1))
/* Bit[6:4] : 输入延迟粗调档位选择 */
#define FIOCTRL_ROUGH_DELAY_MASK(delay_beg) GENMASK((delay_beg + 6), (delay_beg + 4))
#define FIOCTRL_ROUGH_DELAY_GET(reg_val, delay_beg) GET_REG32_BITS((reg_val), (delay_beg + 6), (delay_beg + 4))
#define FIOCTRL_ROUGH_DELAY_SET(val, delay_beg) SET_REG32_BITS((val), (delay_beg + 6), (delay_beg + 4))
/* Bit[7] : 保留 */
/* Bit[8] : 输出延迟功能使能 */
/* Bit[11:9] : 输出延迟精调档位选择 */
/* Bit [14:12] : 输出延迟粗调档位选择 */
/* Bit [15] : 保留 */
#define FIOCTRL_FUNC_BEG_OFF(reg_bit) ((reg_bit) + 0)
#define FIOCTRL_FUNC_END_OFF(reg_bit) ((reg_bit) + 1) /* bit[1:0] 复用功能占2个位 */
#define FIOCTRL_PULL_BEG_OFF(reg_bit) ((reg_bit) + 2)
#define FIOCTRL_PULL_END_OFF(reg_bit) ((reg_bit) + 3) /* bit[3:2] 上下拉功能占2个位 */
#define FIOCTRL_DELAY_IN_BEG_OFF(reg_bit) ((reg_bit) + 0)
#define FIOCTRL_DELAY_IN_END_OFF(reg_bit) ((reg_bit) + 7) /* bit[8:1] 输入延时占7个位 */
#define FIOCTRL_DELAY_OUT_BEG_OFF(reg_bit) ((reg_bit) + 8)
#define FIOCTRL_DELAY_OUT_END_OFF(reg_bit) ((reg_bit) + 15) /* bit[15:9] 输出延时占7个位 */
/* 芯片引脚控制寄存器的起止位置 */
#define FIOCTRL_REG_OFFSET_MIN 0x200
#define FIOCTRL_REG_OFFSET_MAX 0x22c
/* 芯片引脚延时寄存器的起止位置 */
#define FIOCTRL_DELAY_REG_OFFSET_MIN 0x400
#define FIOCTRL_DELAY_REG_OFFSET_MAX 0x404
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
#define FIOCTRL_DEBUG_TAG "FIOCTRL"
#define FIOCTRL_ERROR(format, ...) FT_DEBUG_PRINT_E(FIOCTRL_DEBUG_TAG, format, ##__VA_ARGS__)
#define FIOCTRL_WARN(format, ...) FT_DEBUG_PRINT_W(FIOCTRL_DEBUG_TAG, format, ##__VA_ARGS__)
#define FIOCTRL_INFO(format, ...) FT_DEBUG_PRINT_I(FIOCTRL_DEBUG_TAG, format, ##__VA_ARGS__)
#define FIOCTRL_DEBUG(format, ...) FT_DEBUG_PRINT_D(FIOCTRL_DEBUG_TAG, format, ##__VA_ARGS__)
#define FIOCTRL_ASSERT_REG_OFF(pin) FASSERT_MSG(((pin.reg_off >= FIOCTRL_REG_OFFSET_MIN) && (pin.reg_off <= FIOCTRL_REG_OFFSET_MAX)), "invalid pin register off @%d", (pin.reg_off))
#define FIOCTRL_ASSERT_FUNC(func) FASSERT_MSG((func < FPIN_NUM_OF_FUNC), "invalid func as %d", (func))
#define FIOCTRL_ASSERT_PULL(pull) FASSERT_MSG((pull < FPIN_NUM_OF_PULL), "invalid pull as %d", (pull))
#define FIOCTRL_ASSERT_DELAY_REG_OFF(pin) FASSERT_MSG(((pin.reg_off >= FIOCTRL_DELAY_REG_OFFSET_MIN) && (pin.reg_off <= FIOCTRL_DELAY_REG_OFFSET_MAX)), "invalid delay pin register off @%d", (pin.reg_off))
#define FIOCTRL_ASSERT_DELAY(delay) FASSERT_MSG(((delay) < FPIN_NUM_OF_DELAY), "invalid delay as %d", (delay));
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/*****************************************************************************/
/**
* @name: FPinGetFunc
* @msg: 获取IO引脚当前的复用功能
* @return {FPinFunc} 当前的复用功能
* @param {FPinIndex} pin IO引脚索引
* @note 参考编程手册，使用 FIOCTRL_INDEX 宏定义index的值
*/
FPinFunc FPinGetFunc(const FPinIndex pin)
{
FIOCTRL_ASSERT_REG_OFF(pin);
u32 func_beg = FIOCTRL_FUNC_BEG_OFF(pin.reg_bit);
u32 func_end = FIOCTRL_FUNC_END_OFF(pin.reg_bit);
u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
u32 func = GET_REG32_BITS(reg_val, func_end, func_beg);
FIOCTRL_ASSERT_FUNC(func);
return (FPinFunc)GET_REG32_BITS(reg_val, func_end, func_beg);
}
/**
* @name: FPinSetFunc
* @msg: 设置IO引脚复用功能
* @return {*}
* @param {FPinIndex} pin IO引脚索引
* @param {FPinFunc} func IO复用功能
* @note 参考编程手册，使用 FIOCTRL_INDEX 宏定义index的值
*/
void FPinSetFunc(const FPinIndex pin, FPinFunc func)
{
FIOCTRL_ASSERT_REG_OFF(pin);
FIOCTRL_ASSERT_FUNC(func);
u32 func_beg = FIOCTRL_FUNC_BEG_OFF(pin.reg_bit);
u32 func_end = FIOCTRL_FUNC_END_OFF(pin.reg_bit);
u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
reg_val &= ~GENMASK(func_end, func_beg);
reg_val |= SET_REG32_BITS(func, func_end, func_beg);
FtOut32(FIOCTRL_REG_BASE_ADDR + pin.reg_off, reg_val);
return;
}
/**
* @name: FPinGetPull
* @msg: 获取IO引脚当前的上下拉设置
* @return {*}
* @param {FPinIndex} pin IO引脚索引
* @note 参考编程手册，使用 FIOCTRL_INDEX 宏定义index的值
*/
FPinPull FPinGetPull(const FPinIndex pin)
{
FIOCTRL_ASSERT_REG_OFF(pin);
u32 pull_beg = FIOCTRL_PULL_BEG_OFF(pin.reg_bit);
u32 pull_end = FIOCTRL_PULL_END_OFF(pin.reg_bit);
u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
u32 pull = GET_REG32_BITS(reg_val, pull_end, pull_beg);
FIOCTRL_ASSERT_PULL(pull);
return (FPinPull)pull;
}
/**
* @name: FPinSetPull
* @msg: 设置IO引脚当前的上下拉
* @return {*}
* @param {FPinIndex} pin IO引脚索引
* @param {FPinPull} pull 上下拉设置
*/
void FPinSetPull(const FPinIndex pin, FPinPull pull)
{
FIOCTRL_ASSERT_REG_OFF(pin);
FIOCTRL_ASSERT_PULL(pull);
u32 pull_beg = FIOCTRL_PULL_BEG_OFF(pin.reg_bit);
u32 pull_end = FIOCTRL_PULL_END_OFF(pin.reg_bit);
u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
reg_val &= ~GENMASK(pull_end, pull_beg);
reg_val |= SET_REG32_BITS(pull, pull_end, pull_beg);
FtOut32(FIOCTRL_REG_BASE_ADDR + pin.reg_off, reg_val);
return;
}
/**
* @name: FPinGetDelay
* @msg: 获取IO引脚当前的延时设置
* @return {FPinDelay} 当前的延时设置
* @param {FPinIndex} pin IO引脚延时设置索引
* @param {FPinDelayDir} dir 输入/输出延时
* @param {FPinDelayType} type 精调/粗调延时
*/
FPinDelay FPinGetDelay(const FPinIndex pin, FPinDelayDir dir, FPinDelayType type)
{
FIOCTRL_ASSERT_DELAY_REG_OFF(pin);
u8 delay = 0;
const u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
u32 delay_beg = 0, delay_end = 0;
if (FPIN_OUTPUT_DELAY == dir)
{
delay_beg = FIOCTRL_DELAY_OUT_BEG_OFF(pin.reg_off);
}
else if (FPIN_INPUT_DELAY == dir)
{
delay_beg = FIOCTRL_DELAY_IN_BEG_OFF(pin.reg_off);
}
else
{
FASSERT(0);
}
if (FPIN_DELAY_FINE_TUNING == type)
{
delay = FIOCTRL_DELICATE_DELAY_GET(reg_val, delay_beg); /* bit[3:1] delicate delay tune */
}
else if (FPIN_DELAY_COARSE_TUNING == type)
{
delay = FIOCTRL_ROUGH_DELAY_GET(reg_val, delay_beg); /* bit[6:4] rough delay adjust */
}
else
{
FASSERT(0);
}
FIOCTRL_ASSERT_DELAY(delay);
return (FPinDelay)delay;
}
/**
* @name: FPinGetDelayEn
* @msg: 获取IO引脚当前的延时使能标志位
* @return {*}
* @param {FPinIndex} pin IO引脚延时设置索引
* @param {FPinDelayDir} dir 输入/输出延时
*/
boolean FPinGetDelayEn(const FPinIndex pin, FPinDelayDir dir)
{
FIOCTRL_ASSERT_DELAY_REG_OFF(pin);
boolean enabled = FALSE;
const u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
u32 delay_beg = 0, delay_end = 0;
if (FPIN_OUTPUT_DELAY == dir)
{
delay_beg = FIOCTRL_DELAY_OUT_BEG_OFF(pin.reg_off);
}
else if (FPIN_INPUT_DELAY == dir)
{
delay_beg = FIOCTRL_DELAY_IN_BEG_OFF(pin.reg_off);
}
else
{
FASSERT(0);
}
if (FIOCTRL_DELAY_EN(delay_beg) & reg_val)
{
enabled = TRUE;
}
return enabled;
}
/**
* @name: FPinSetDelay
* @msg: 设置IO引脚延时
* @return {*}
* @param {FPinIndex} pin IO引脚延时设置索引
* @param {FPinDelayDir} dir 输入/输出延时
* @param {FPinDelayType} type 精调/粗调延时
* @param {FPinDelay} delay 延时档位设置 0 ~ 8 档可用
*/
void FPinSetDelay(const FPinIndex pin, FPinDelayDir dir, FPinDelayType type, FPinDelay delay)
{
FIOCTRL_ASSERT_DELAY_REG_OFF(pin);
FIOCTRL_ASSERT_DELAY(delay);
u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
u32 delay_beg = 0, delay_end = 0;
if (FPIN_OUTPUT_DELAY == dir)
{
delay_beg = FIOCTRL_DELAY_OUT_BEG_OFF(pin.reg_off);
}
else if (FPIN_INPUT_DELAY == dir)
{
delay_beg = FIOCTRL_DELAY_IN_BEG_OFF(pin.reg_off);
}
else
{
FASSERT(0);
}
if (FPIN_DELAY_FINE_TUNING == type)
{
reg_val &= ~FIOCTRL_DELICATE_DELAY_MASK(delay_beg);
delay = FIOCTRL_DELICATE_DELAY_GET(reg_val, delay_beg);
}
else if (FPIN_DELAY_COARSE_TUNING == type)
{
reg_val &= ~FIOCTRL_ROUGH_DELAY_MASK(delay_beg);
delay = FIOCTRL_ROUGH_DELAY_GET(reg_val, delay_beg);
}
else
{
FASSERT(0);
}
FtOut32(FIOCTRL_REG_BASE_ADDR + pin.reg_off, reg_val);
return;
}
/**
* @name: FPinSetDelayEn
* @msg: 使能/去使能IO引脚延时
* @return {*}
* @param {FPinIndex} pin IO引脚延时设置索引
* @param {FPinDelayDir} dir 输入/输出延时
* @param {boolean} enable TRUE: 使能, FALSE: 去使能
*/
void FPinSetDelayEn(const FPinIndex pin, FPinDelayDir dir, boolean enable)
{
FIOCTRL_ASSERT_DELAY_REG_OFF(pin);
u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
u32 delay_beg = 0, delay_end = 0;
if (FPIN_OUTPUT_DELAY == dir)
{
delay_beg = FIOCTRL_DELAY_OUT_BEG_OFF(pin.reg_off);
}
else if (FPIN_INPUT_DELAY == dir)
{
delay_beg = FIOCTRL_DELAY_IN_BEG_OFF(pin.reg_off);
}
else
{
FASSERT(0);
}
reg_val &= ~FIOCTRL_DELAY_EN(delay_beg);
if (enable)
{
reg_val |= FIOCTRL_DELAY_EN(delay_beg);
}
FtOut32(FIOCTRL_REG_BASE_ADDR + pin.reg_off, reg_val);
return;
}

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bsp/phytium/libraries/standalone/board/ft2004/fioctrl.h Normal file
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@ -0,0 +1,81 @@
/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: fioctrl.h
* Date: 2022-02-10 14:53:42
* LastEditTime: 2022-02-18 08:25:35
* Description:  This files is for io-ctrl function definition (io-mux/io-config/io-delay)
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
* 1.0 zhugengyu 2022/2/22 init commit
*/
#ifndef BOARD_D2000_FIOCTRL_H
#define BOARD_D2000_FIOCTRL_H
#ifdef __cplusplus
extern "C"
{
#endif
/***************************** Include Files *********************************/
#include "ftypes.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
#define FIOCTRL_INDEX(offset, func_beg) \
{ \
/* reg_off */ (offset), \
/* reg_bit */ (func_beg) \
}
/************************** Variable Definitions *****************************/
#define FIOCTRL_CRU_CLK_OBV_PAD (FPinIndex)FIOCTRL_INDEX(0x200, 24)
#define FIOCTRL_SPI0_CSN0_PAD (FPinIndex)FIOCTRL_INDEX(0x208, 16)
#define FIOCTRL_SPI0_SCK_PAD (FPinIndex)FIOCTRL_INDEX(0x208, 12)
#define FIOCTRL_SPI0_SO_PAD (FPinIndex)FIOCTRL_INDEX(0x208, 8)
#define FIOCTRL_SPI0_SI_PAD (FPinIndex)FIOCTRL_INDEX(0x208, 4)
#define FIOCTRL_TJTAG_TDI_PAD (FPinIndex)FIOCTRL_INDEX(0x204, 24) /* can0-tx: func 1 */
#define FIOCTRL_SWDITMS_SWJ_PAD (FPinIndex)FIOCTRL_INDEX(0x204, 12) /* can0-rx: func 1 */
#define FIOCTRL_NTRST_SWJ_PAD (FPinIndex)FIOCTRL_INDEX(0x204, 20) /* can1-tx: func 1 */
#define FIOCTRL_SWDO_SWJ_PAD (FPinIndex)FIOCTRL_INDEX(0x204, 8) /* can1-rx: func 1 */
#define FIOCTRL_I2C0_SCL_PAD (FPinIndex)FIOCTRL_INDEX(0x208, 24) /* i2c0-scl: func 0 */
#define FIOCTRL_I2C0_SDA_PAD (FPinIndex)FIOCTRL_INDEX(0x208, 20) /* i2c0-sda: func 0 */
#define FIOCTRL_ALL_PLL_LOCK_PAD (FPinIndex)FIOCTRL_INDEX(0x200, 28) /* i2c1-scl: func 2 */
#define FIOCTRL_CRU_CLK_OBV_PAD (FPinIndex)FIOCTRL_INDEX(0x200, 24) /* i2c1-sda: func 2 */
#define FIOCTRL_SWDO_SWJ_PAD (FPinIndex)FIOCTRL_INDEX(0x204, 8) /* i2c2-scl: func 2 */
#define FIOCTRL_TDO_SWJ_IN_PAD (FPinIndex)FIOCTRL_INDEX(0x204, 4) /* i2c2-sda: func 2 */
#define FIOCTRL_HDT_MB_DONE_STATE_PAD (FPinIndex)FIOCTRL_INDEX(0x204, 0) /* i2c3-scl: func 2 */
#define FIOCTRL_HDT_MB_FAIL_STATE_PAD (FPinIndex)FIOCTRL_INDEX(0x208, 28) /* i2c3-sda: func 2 */
#define FIOCTRL_UART_2_RXD_PAD (FPinIndex)FIOCTRL_INDEX(0x210, 0) /* spi1_csn0: func 1 */
#define FIOCTRL_UART_2_TXD_PAD (FPinIndex)FIOCTRL_INDEX(0x214, 28) /* spi1_sck: func 1 */
#define FIOCTRL_UART_3_RXD_PAD (FPinIndex)FIOCTRL_INDEX(0x214, 24) /* spi1_so: func 1 */
#define FIOCTRL_UART_3_TXD_PAD (FPinIndex)FIOCTRL_INDEX(0x214, 20) /* spi1_si: func 1 */
#define FIOCTRL_QSPI_CSN2_PAD (FPinIndex)FIOCTRL_INDEX(0x214, 8) /* spi1_csn1: func 1 */
#define FIOCTRL_QSPI_CSN3_PAD (FPinIndex)FIOCTRL_INDEX(0x214, 4) /* spi1_csn2: func 1 */
#ifdef __cplusplus
}
#endif
#endif

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