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[bsp][Infineon] add a new bsp for XMC7100D-F144K4160AA

This commit is contained in:
hydevcode 2025-04-21 22:24:15 +08:00 committed by Rbb666
parent ae83165609
commit 5804973a49
86 changed files with 68461 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
.github/ALL_BSP_COMPILE.json vendored
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@ -338,6 +338,7 @@
"Infineon/psoc6-cy8cproto-062S3-4343W",
"Infineon/psoc6-evaluationkit-062S2",
"Infineon/xmc7200-kit_xmc7200_evk",
"Infineon/xmc7100d-f144k4160aa",
"fujitsu/mb9x/mb9bf500r",
"fujitsu/mb9x/mb9bf506r",
"fujitsu/mb9x/mb9bf618s",

2
bsp/Infineon/libraries/HAL_Drivers/SConscript
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@ -23,7 +23,7 @@ if GetDepend(['RT_USING_I2C', 'RT_USING_I2C_BITOPS']):
src += ['drv_soft_i2c.c']
if GetDepend(['RT_USING_I2C']):
if GetDepend('BSP_USING_HW_I2C3') or GetDepend('BSP_USING_HW_I2C4') or GetDepend('BSP_USING_HW_I2C6'):
if GetDepend('BSP_USING_HW_I2C1') or GetDepend('BSP_USING_HW_I2C3') or GetDepend('BSP_USING_HW_I2C4') or GetDepend('BSP_USING_HW_I2C6'):
src += ['drv_i2c.c']
if GetDepend(['BSP_USING_SDIO1']):

19
bsp/Infineon/libraries/HAL_Drivers/drv_i2c.c
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@ -6,14 +6,24 @@
* Change Logs:
* Date Author Notes
* 2022-07-08 Rbb666 first implementation.
* 2025-04-21 Hydevcode adapt xmc7100d
*/
#include "board.h"
#if defined(RT_USING_I2C)
#if defined(BSP_USING_HW_I2C2) || defined(BSP_USING_HW_I2C3) || defined(BSP_USING_HW_I2C4)|| defined(BSP_USING_HW_I2C6)
#if defined(BSP_USING_HW_I2C1) || defined(BSP_USING_HW_I2C2) || defined(BSP_USING_HW_I2C3) || defined(BSP_USING_HW_I2C4)|| defined(BSP_USING_HW_I2C6)
#include <rtdevice.h>
#ifndef I2C1_CONFIG
#define I2C1_CONFIG \
{ \
.name = "i2c1", \
.scl_pin = BSP_I2C1_SCL_PIN, \
.sda_pin = BSP_I2C1_SDA_PIN, \
}
#endif /* I2C1_CONFIG */
#ifndef I2C2_CONFIG
#define I2C2_CONFIG \
{ \
@ -53,6 +63,9 @@
enum
{
#ifdef BSP_USING_HW_I2C1
I2C1_INDEX,
#endif
#ifdef BSP_USING_HW_I2C2
I2C2_INDEX,
#endif
@ -84,6 +97,10 @@ struct ifx_i2c
static struct ifx_i2c_config i2c_config[] =
{
#ifdef BSP_USING_HW_I2C1
I2C1_CONFIG,
#endif
#ifdef BSP_USING_HW_I2C2
I2C2_CONFIG,
#endif

4
bsp/Infineon/libraries/HAL_Drivers/drv_uart.c
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@ -6,6 +6,7 @@
* Change Logs:
* Date Author Notes
* 2022-06-29 Rbb666 first version
* 2025-04-21 hydevcode modify xmc7100d uart
*/
#include <rtthread.h>
@ -228,9 +229,10 @@ static rt_err_t ifx_control(struct rt_serial_device *serial, int cmd, void *arg)
/* Enable the interrupt */
#if defined(SOC_SERIES_IFX_XMC)
NVIC_DisableIRQ(UART_NvicMuxN_IRQn);
NVIC_EnableIRQ(UART_NvicMuxN_IRQn);
#else
NVIC_EnableIRQ(uart->config->intrSrc);
NVIC_EnableIRQ(uart->config->UART_SCB_IRQ_cfg->intrSrc);
#endif
break;
}

6
bsp/Infineon/libraries/HAL_Drivers/drv_uart.h
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@ -21,16 +21,10 @@
struct ifx_uart_config
{
cyhal_uart_t *uart_obj;
const char *name;
rt_uint32_t tx_pin;
rt_uint32_t rx_pin;
CySCB_Type *usart_x;
#if defined(SOC_SERIES_IFX_XMC)
rt_uint32_t intrSrc;
#else
IRQn_Type intrSrc;
#endif
cy_israddress userIsr;
cy_stc_sysint_t *UART_SCB_IRQ_cfg;
};

52
bsp/Infineon/libraries/HAL_Drivers/uart_config.h
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@ -6,6 +6,7 @@
* Change Logs:
* Date Author Notes
* 2022-07-08 Rbb666 first version
* 2025-04-21 Hydevcode adapt xmc7100d
*/
#ifndef __UART_CONFIG_H__
@ -45,7 +46,11 @@ extern "C"
/* UART0 device driver structure */
cy_stc_sysint_t UART0_SCB_IRQ_cfg =
{
#if defined(SOC_SERIES_IFX_XMC)
.intrSrc = ((UART_NvicMuxN_IRQn << 16) | (cy_en_intr_t)scb_0_interrupt_IRQn),
#else
.intrSrc = (IRQn_Type)scb_0_interrupt_IRQn,
#endif
.intrPriority = (7u),
};
#endif
@ -53,7 +58,11 @@ extern "C"
/* UART1 device driver structure */
cy_stc_sysint_t UART1_SCB_IRQ_cfg =
{
#if defined(SOC_SERIES_IFX_XMC)
.intrSrc = ((UART_NvicMuxN_IRQn << 16) | (cy_en_intr_t)scb_1_interrupt_IRQn),
#else
.intrSrc = (IRQn_Type)scb_1_interrupt_IRQn,
#endif
.intrPriority = (7u),
};
#endif
@ -61,7 +70,11 @@ extern "C"
/* UART2 device driver structure */
cy_stc_sysint_t UART2_SCB_IRQ_cfg =
{
#if defined(SOC_SERIES_IFX_XMC)
.intrSrc = ((UART_NvicMuxN_IRQn << 16) | (cy_en_intr_t)scb_2_interrupt_IRQn),
#else
.intrSrc = (IRQn_Type)scb_2_interrupt_IRQn,
#endif
.intrPriority = (7u),
};
#endif
@ -81,7 +94,11 @@ extern "C"
/* UART4 device driver structure */
cy_stc_sysint_t UART4_SCB_IRQ_cfg =
{
#if defined(SOC_SERIES_IFX_XMC)
.intrSrc = ((UART_NvicMuxN_IRQn << 16) |(cy_en_intr_t)scb_4_interrupt_IRQn),
#else
.intrSrc = (IRQn_Type)scb_4_interrupt_IRQn,
#endif
.intrPriority = (7u),
};
#endif
@ -89,7 +106,11 @@ extern "C"
/* UART5 device driver structure */
cy_stc_sysint_t UART5_SCB_IRQ_cfg =
{
#if defined(SOC_SERIES_IFX_XMC)
.intrSrc = ((UART_NvicMuxN_IRQn << 16) |(cy_en_intr_t)scb_5_interrupt_IRQn),
#else
.intrSrc = (IRQn_Type)scb_5_interrupt_IRQn,
#endif
.intrPriority = (7u),
};
#endif
@ -97,7 +118,11 @@ extern "C"
/* UART6 device driver structure */
cy_stc_sysint_t UART6_SCB_IRQ_cfg =
{
#if defined(SOC_SERIES_IFX_XMC)
.intrSrc = ((UART_NvicMuxN_IRQn << 16) |(cy_en_intr_t)scb_6_interrupt_IRQn),
#else
.intrSrc = (IRQn_Type)scb_6_interrupt_IRQn,
#endif
.intrPriority = (7u),
};
#endif
@ -110,7 +135,6 @@ extern "C"
.tx_pin = P0_3, \
.rx_pin = P0_2, \
.usart_x = SCB0, \
.intrSrc = scb_0_interrupt_IRQn, \
.userIsr = uart_isr_callback(uart0), \
.UART_SCB_IRQ_cfg = &UART0_SCB_IRQ_cfg, \
}
@ -126,7 +150,6 @@ extern "C"
.tx_pin = P10_1, \
.rx_pin = P10_0, \
.usart_x = SCB1, \
.intrSrc = scb_1_interrupt_IRQn, \
.userIsr = uart_isr_callback(uart1), \
.UART_SCB_IRQ_cfg = &UART1_SCB_IRQ_cfg, \
}
@ -136,14 +159,13 @@ extern "C"
#if defined(BSP_USING_UART2)
#ifndef UART2_CONFIG
#if defined(SOC_CY8C6244LQI_S4D92)
#if defined(SOC_XMC7100D_F144K4160AA)
#define UART2_CONFIG \
{ \
.name = "uart2", \
.tx_pin = P3_1, \
.rx_pin = P3_0, \
.tx_pin = P19_1, \
.rx_pin = P19_0, \
.usart_x = SCB2, \
.intrSrc = scb_2_interrupt_IRQn, \
.userIsr = uart_isr_callback(uart2), \
.UART_SCB_IRQ_cfg = &UART2_SCB_IRQ_cfg, \
}
@ -154,7 +176,6 @@ extern "C"
.tx_pin = P9_1, \
.rx_pin = P9_0, \
.usart_x = SCB2, \
.intrSrc = scb_2_interrupt_IRQn, \
.userIsr = uart_isr_callback(uart2), \
.UART_SCB_IRQ_cfg = &UART2_SCB_IRQ_cfg, \
}
@ -172,7 +193,6 @@ extern "C"
.tx_pin = P13_1, \
.rx_pin = P13_0, \
.usart_x = SCB3, \
.intrSrc = scb_3_interrupt_IRQn, \
.userIsr = uart_isr_callback(uart3), \
.UART_SCB_IRQ_cfg = &UART3_SCB_IRQ_cfg, \
}
@ -183,7 +203,6 @@ extern "C"
.tx_pin = P6_1, \
.rx_pin = P6_0, \
.usart_x = SCB3, \
.intrSrc = scb_3_interrupt_IRQn, \
.userIsr = uart_isr_callback(uart3), \
.UART_SCB_IRQ_cfg = &UART3_SCB_IRQ_cfg, \
}
@ -194,16 +213,27 @@ extern "C"
#if defined(BSP_USING_UART4)
#ifndef UART4_CONFIG
#if defined(SOC_XMC7100D_F144K4160AA)
#define UART4_CONFIG \
{ \
.name = "uart4", \
.tx_pin = P10_1, \
.rx_pin = P10_0, \
.usart_x = SCB4, \
.userIsr = uart_isr_callback(uart4), \
.UART_SCB_IRQ_cfg = &UART4_SCB_IRQ_cfg, \
}
#else
#define UART4_CONFIG \
{ \
.name = "uart4", \
.tx_pin = P7_1, \
.rx_pin = P7_0, \
.usart_x = SCB4, \
.intrSrc = scb_4_interrupt_IRQn, \
.userIsr = uart_isr_callback(uart4), \
.UART_SCB_IRQ_cfg = &UART4_SCB_IRQ_cfg, \
}
#endif
void uart4_isr_callback(void);
#endif /* UART4_CONFIG */
#endif /* BSP_USING_UART4 */
@ -216,7 +246,6 @@ extern "C"
.tx_pin = P5_1, \
.rx_pin = P5_0, \
.usart_x = SCB5, \
.intrSrc = scb_5_interrupt_IRQn, \
.userIsr = uart_isr_callback(uart5), \
.UART_SCB_IRQ_cfg = &UART5_SCB_IRQ_cfg, \
}
@ -232,7 +261,6 @@ extern "C"
.tx_pin = P6_5, \
.rx_pin = P6_4, \
.usart_x = SCB6, \
.intrSrc = scb_6_interrupt_IRQn, \
.userIsr = uart_isr_callback(uart6), \
.UART_SCB_IRQ_cfg = &UART6_SCB_IRQ_cfg, \
}

9
bsp/Infineon/xmc7100d-f144k4160aa/.ci/attachconfig/ci.attachconfig.yml Normal file
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@ -0,0 +1,9 @@
scons.args: &scons
scons_arg:
- '--strict'
# ------ Drivers CI ------
Drivers.I2C:
<<: *scons
kconfig:
- CONFIG_BSP_USING_I2C=y
- CONFIG_BSP_USING_HW_I2C1=y

1390
bsp/Infineon/xmc7100d-f144k4160aa/.config Normal file
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File diff suppressed because it is too large Load Diff

42
bsp/Infineon/xmc7100d-f144k4160aa/.gitignore vendored Normal file
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@ -0,0 +1,42 @@
*.pyc
*.map
*.dblite
*.elf
*.bin
*.hex
*.axf
*.exe
*.pdb
*.idb
*.ilk
*.old
build
Debug
documentation/html
packages/
*~
*.o
*.obj
*.out
*.bak
*.dep
*.lib
*.i
*.d
.DS_Stor*
.config 3
.config 4
.config 5
Midea-X1
*.uimg
GPATH
GRTAGS
GTAGS
.vscode
JLinkLog.txt
JLinkSettings.ini
DebugConfig/
RTE/
settings/
*.uvguix*
cconfig.h

12
bsp/Infineon/xmc7100d-f144k4160aa/Kconfig Normal file
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@ -0,0 +1,12 @@
mainmenu "RT-Thread Configuration"
BSP_DIR := .
RTT_DIR := ../../..
PKGS_DIR := packages
source "$(RTT_DIR)/Kconfig"
osource "$PKGS_DIR/Kconfig"
rsource "../libraries/Kconfig"
rsource "board/Kconfig"

132
bsp/Infineon/xmc7100d-f144k4160aa/README.md Normal file
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@ -0,0 +1,132 @@
# Infineon XMC7100D-F144K4160AA 说明
## 简介
本文档为 `RT-Thread` 为 ` XMC7100D-F144K4160AA`开发板提供的 BSP (板级支持包) 说明。
主要内容如下：
- 开发板资源介绍
- BSP 快速上手
- 进阶使用方法
通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 `RT-Thread` 驱动更多板载资源。
## 外设支持
本 BSP 目前对外设的支持情况如下：
| **片上外设** | **支持情况** | **备注** |
| :----------: | :----------: | :------: |
| USB 转串口 | 支持 | UART4 |
| GPIO | 支持 | — |
| UART | 支持 | UART2,UART4 |
| I2C | 支持 | I2C1 |
## 快速上手
本 BSP 是以 `GCC` 和 `Jlink` 为开发环境（编译器：GCC），接下来介绍如何将系统运行起来。
### 使用 Vscode 开发
#### 硬件连接
将开发板的swd接口与jlink相连,注意jlink版本建议V8.18以上
#### 编译下载
1、下载软件包：在ENV环境下输入`pkgs --update`命令，将所需要的HAL库软件包下载下来，文件会存放在`Packages`目录下。
2、编译工程：在ENV环境下输入`SCons -j4`或者 `SCons -j16` 命令，j后面的数字取决于cpu线程数，然后ENV会自动编译生成可烧写elf文件
3、下载此工程：
Vscode下载拓展Cortex-Debug，然后在.vscode下新建launch.json文件,并添加以下内容
```
{
"version": "0.2.0",
"configurations": [
{
"name": "Launch XMC7100D CM7 (JLink)",
"type": "cortex-debug",
"request": "launch",
"cwd": "${workspaceFolder}",
"executable": "${workspaceRoot}/rt-thread.elf",
"servertype": "jlink",
"device": "XMC7100-4160_CM7_0_tm",
"interface": "swd",
"serialNumber": "",
"preLaunchCommands": [
// Program via the hex file to get complete coverage
"exec-file rt-thread.hex"
],
"overrideRestartCommands": [
"starti"
],
// svdFile is optional, it can be very large.
"svdFile": "${workspaceRoot}/libs/cat1c4m.svd",
"breakAfterReset": true,
"runToEntryPoint": "main", // Specifies application entry point name where program will halt
"showDevDebugOutput": "none",
"presentation": {
"hidden": false,
"group": "CM7"
},
"serverpath": "C:/Program Files/SEGGER/JLink_V820/JLinkGDBServerCL.exe"
},
// When using 'attach', make sure your program is running on the board and that your
// executable matches the image in the chip exactly, or else strange things can happen
// with breakpoints, variables, etc.
{
"name": "Attach XMC7100D CM7 (JLink)",
"type": "cortex-debug",
"request": "attach",
"cwd": "${workspaceFolder}",
"executable": "${workspaceRoot}/rt-thread.elf",
"servertype": "jlink",
"device": "XMC7100-4160_CM7_0_tm",
"interface": "swd",
"serialNumber": "",
"overrideRestartCommands": [
"starti"
],
// svdFile is optional, it can be very large.
"svdFile": "${workspaceRoot}/libs/cat1c4m.svd",
"breakAfterReset": true,
"runToEntryPoint": "main", // Specifies application entry point name for restart/reset
"showDevDebugOutput": "none",
"presentation": {
"hidden": false,
"group": "CM7"
},
"serverpath": "C:/Program Files/SEGGER/JLink_V820/JLinkGDBServerCL.exe"
}
]
}
```
随后点击运行按钮即可自动下载程序到开发板
## 运行结果
下载程序成功之后，点击全速运行。然后打开终端工具串口助手，选择波特率为 115200。复位设备后，LED 将会闪烁，而且在终端上可以看到 `RT-Thread` 的输出信息：
注：推荐使用串口调试助手如：`MobaXterm`
```c
\ | /
- RT - Thread Operating System
/ | \ 5.2.1 build Apr 21 2025 20:49:36
2006 - 2024 Copyright by RT-Thread team
msh >
```
## 联系人
维护人:
- [LZerro](https://github.com/LZerro)
- [Hydevcode](https://github.com/hydevcode)

15
bsp/Infineon/xmc7100d-f144k4160aa/SConscript Normal file
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@ -0,0 +1,15 @@
# for module compiling
import os
Import('RTT_ROOT')
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')

59
bsp/Infineon/xmc7100d-f144k4160aa/SConstruct Normal file
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@ -0,0 +1,59 @@
import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
try:
from building import *
except:
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
print(RTT_ROOT)
exit(-1)
TARGET = 'rt-thread.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
if rtconfig.PLATFORM in ['iccarm']:
env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
env.Replace(ARFLAGS = [''])
env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map')
Export('RTT_ROOT')
Export('rtconfig')
SDK_ROOT = os.path.abspath('./')
libraries_path_prefix = SDK_ROOT
if os.path.exists(SDK_ROOT + '/packages'):
libraries_path_prefix = SDK_ROOT + '/packages'
else:
print("Error: Packages for HAL_Driver does not exist, pull it in ENV using `pkg --update`.")
SDK_LIB = libraries_path_prefix
Export('SDK_LIB')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
IFX_library = 'Packages'
rtconfig.BSP_LIBRARY_TYPE = IFX_library
# include drivers
objs.extend(SConscript(os.path.join('../libraries', 'HAL_Drivers', 'SConscript')))
# make a building
DoBuilding(TARGET, objs)

16
bsp/Infineon/xmc7100d-f144k4160aa/applications/SConscript Normal file
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@ -0,0 +1,16 @@
import rtconfig
from building import *
import os
cwd = GetCurrentDir()
path = [cwd]
src = Glob('*.c')
group = DefineGroup('Applications', src, depend = [''], CPPPATH = path)
list = os.listdir(cwd)
for item in list:
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
group = group + SConscript(os.path.join(item, 'SConscript'))
Return('group')

28
bsp/Infineon/xmc7100d-f144k4160aa/applications/main.c Normal file
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@ -0,0 +1,28 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-04-15 Hydevcode first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include "drv_gpio.h"
#define LED_PIN GET_PIN(10, 3)
int main(void)
{
rt_kprintf("\nHello RT-Thread!\n");
rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT);
while (1)
{
rt_pin_write(LED_PIN, PIN_HIGH);
rt_thread_mdelay(1000);
rt_pin_write(LED_PIN, PIN_LOW);
rt_thread_mdelay(1000);
}
}

65
bsp/Infineon/xmc7100d-f144k4160aa/board/Kconfig Normal file
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@ -0,0 +1,65 @@
menu "Hardware Drivers Config"
config SOC_XMC7100D_F144K4160AA
bool
select SOC_SERIES_IFX_XMC
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
default y
menu "Onboard Peripheral Drivers"
config BSP_USING_USB_TO_USART
bool "Enable USB TO USART (uart4)"
select BSP_USING_GPIO
select BSP_USING_UART
select BSP_USING_UART4
default y
endmenu
menu "On-chip Peripheral Drivers"
config BSP_USING_GPIO
bool "Enable GPIO"
select RT_USING_PIN
default y
menuconfig BSP_USING_UART
bool "Enable UART"
default y
select RT_USING_SERIAL
if BSP_USING_UART
config BSP_USING_UART2
bool "Enable UART2"
default n
config BSP_USING_UART4
bool "Enable UART4"
default y
config UART_CPU_IRQ_Number
int "UART connect CPU Interrupt Number (0-7)"
range 0 7
default 3
endif
menuconfig BSP_USING_I2C
bool "Enable HW I2C"
default n
select RT_USING_I2C
if BSP_USING_I2C
menuconfig BSP_USING_HW_I2C1
bool "Enable BSP_USING_HW_I2C1"
default n
if BSP_USING_HW_I2C1
config BSP_I2C1_SCL_PIN
int "BSP_I2C1_SCL_PIN number(18,2)"
range 0 999
default 146
config BSP_I2C1_SDA_PIN
int "BSP_I2C1_SDA_PIN number(18,1)"
range 0 999
default 145
endif
endif
endmenu
endmenu

61
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import os
import rtconfig
from building import *
Import('SDK_LIB')
objs = []
cwd = GetCurrentDir()
# add general drivers
src = Split('''
board.c
''')
path = [cwd]
path += [cwd + '/ports']
startup_path_prefix = SDK_LIB
Tool_path = None
index = 'Infineon_mtb-pdl-cat1-latest'
for filename in os.listdir(startup_path_prefix):
if index in filename:
Tool_path = os.path.join(startup_path_prefix, filename)
if rtconfig.PLATFORM in ['gcc']:
src += [Tool_path +
'/drivers/source/TOOLCHAIN_GCC_ARM/cy_syslib_ext.S']
elif rtconfig.PLATFORM in ['armclang']:
src += [Tool_path +
'/drivers/source/TOOLCHAIN_ARM/cy_syslib_ext.s']
# CPPDEFINES = []
CPPDEFINES = ['XMC7100D_F144K4160',
'COMPONENT_APP_KIT_XMC71_EVK_LITE_V2',
'COMPONENT_CAT1',
'COMPONENT_CAT1C',
'COMPONENT_CAT1C4M',
'COMPONENT_CM7',
'COMPONENT_CM7_0',
'COMPONENT_Debug'
'COMPONENT_GCC_ARM',
'COMPONENT_MW_CAT1CM0P',
'COMPONENT_MW_CMSIS',
'COMPONENT_MW_CORE_LIB',
'COMPONENT_MW_CORE_MAKE',
'COMPONENT_MW_MTB_HAL_CAT1',
'COMPONENT_MW_MTB_PDL_CAT1',
'COMPONENT_MW_RECIPE_MAKE_CAT1C',
'COMPONENT_MW_RETARGET_IO',
'COMPONENT_SOFTFP',
'COMPONENT_XMC7x_CM0P_SLEEP',
'CORE_NAME_CM7_0=1',
'CY_APPNAME_mtb_example_hal_hello_world',
'CY_SUPPORTS_DEVICE_VALIDATION',
'CY_TARGET_BOARD=APP_KIT_XMC71_EVK_LITE_V2',
'CY_USING_HAL',
'DEBUG',
'TARGET_APP_KIT_XMC71_EVK_LITE_V2']
group = DefineGroup('Drivers', src, depend=[''], CPPPATH=path, CPPDEFINES=CPPDEFINES)
Return('group')

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bsp/Infineon/xmc7100d-f144k4160aa/board/board.c Normal file
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-06-29 Rbb666 first version
*/
#include "board.h"
void cy_bsp_all_init(void)
{
cy_rslt_t result;
/* Initialize the device and board peripherals */
result = cybsp_init();
/* Board init failed. Stop program execution */
if (result != CY_RSLT_SUCCESS)
{
CY_ASSERT(0);
}
}

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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-06-29 Rbb666 first version
* 2022-07-26 Rbb666 Add Flash Config
* 2022-04-21 Hydevcode modify Flash Config
*/
#ifndef __BOARD_H__
#define __BOARD_H__
#include <rtthread.h>
#include "drv_common.h"
#include "drv_gpio.h"
#include "cy_result.h"
#include "cybsp_types.h"
#include "cyhal.h"
#include "cybsp.h"
#ifdef BSP_USING_USBD
#include "cy_usb_dev.h"
#include "cy_usb_dev_hid.h"
#include "cycfg_usbdev.h"
#endif
/*SRAM CONFIG*/
#define IFX_SRAM_SIZE (768)
#define IFX_SRAM_END (0x28000000 + IFX_SRAM_SIZE * 1024)
#ifdef __ARMCC_VERSION
extern int Image$$RW_IRAM1$$ZI$$Limit;
#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
#define HEAP_END IFX_SRAM_END
#elif __ICCARM__
#pragma section="HEAP"
#define HEAP_BEGIN (__segment_end("HEAP"))
#else
extern unsigned int __end__;
extern unsigned int __HeapLimit;
#define HEAP_BEGIN (void*)&__end__
#define HEAP_END (void*)&__HeapLimit
#endif
void cy_bsp_all_init(void);
#endif

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/***************************************************************************//**
* /file xmc7100_x4160_cm7.ld
* /version 1.0.0
*
* Linker file for the GNU C compiler.
*
* The main purpose of the linker script is to describe how the sections in the
* input files should be mapped into the output file, and to control the memory
* layout of the output file.
*
* /note The entry point location is fixed and starts at 0x10000000. The valid
* application image should be placed there.
*
* /note The linker files included with the PDL template projects must be generic
* and handle all common use cases. Your project may not use every section
* defined in the linker files. In that case you may see warnings during the
* build process. In your project, you can simply comment out or remove the
* relevant code in the linker file.
*
********************************************************************************
* /copyright
* Copyright 2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
GROUP(-lgcc -lc -lnosys )
SEARCH_DIR(.)
GROUP(libgcc.a libc.a libm.a libnosys.a)
ENTRY(Reset_Handler)
/* The size of the stack section at the end of CM7 SRAM */
STACK_SIZE = 0x1000;
RAMVECTORS_ALIGNMENT = 128;
sram_start_reserve = 0;
sram_total_size = 0x000C0000; /* 768K: SRAM0 + SRAM1 */
sram_private_for_srom = 0x00000800; /* Private SRAM for SROM (e.g. API processing) */
sram_used_by_boot = 0x0; /* Used during boot by Cypress firmware (content will be overwritten on reset, so it should not be used for loadable sections in case of RAM build configurations) */
cm0plus_sram_reserve = 0x00004000; /* 16K : cm0 sram size */
cm7_0_sram_reserve = 0x000BC000; /* 752K : cm7_0 sram size */
code_flash_total_size = 0x00410000; /* 4160K: total flash size */
cm0plus_code_flash_reserve = 0x00080000; /* 512K : cm0 flash size */
cm7_0_code_flash_reserve = 0x00390000; /* 3648K: cm7_0 flash size */
code_flash_base_address = 0x10000000;
sram_base_address = 0x28000000;
/* SRAM reservations */
_base_SRAM_CM7_0 = sram_base_address + cm0plus_sram_reserve;
_size_SRAM_CM7_0 = cm7_0_sram_reserve;
/* Code flash reservations */
_base_CODE_FLASH_CM0P = code_flash_base_address;
_size_CODE_FLASH_CM0P = cm0plus_code_flash_reserve;
_base_CODE_FLASH_CM7_0 = code_flash_base_address + cm0plus_code_flash_reserve;
_size_CODE_FLASH_CM7_0 = cm7_0_code_flash_reserve;
/* Fixed Addresses */
_base_WORK_FLASH = 0x14000000;
_size_WORK_FLASH = 0x00040000; /* 256K Work flash */
_base_CM7_0_ITCM = 0x00000000;
_size_CM7_0_ITCM = 0x00004000;
_base_CM7_0_DTCM = 0x20000000;
_size_CM7_0_DTCM = 0x00004000;
/* For the non-dual cm7 device, _CORE_CM7_0_ should be defined and _CORE_CM7_1_ should not be defined */
_base_SRAM = _base_SRAM_CM7_0;
_size_SRAM = _size_SRAM_CM7_0;
_base_CODE_FLASH = _base_CODE_FLASH_CM7_0;
_size_CODE_FLASH = _size_CODE_FLASH_CM7_0;
_base_SFLASH_USER_DATA = 0x17000800;
_size_SFLASH_USER_DATA = 0x00000800;
_base_SFLASH_NAR = 0x17001A00;
_size_SFLASH_NAR = 0x00000200;
_base_SFLASH_PUB_KEY = 0x17006400;
_size_SFLASH_PUB_KEY = 0x00000C00;
_base_SFLASH_APP_PROT = 0x17007600;
_size_SFLASH_APP_PROT = 0x00000200;
_base_SFLASH_TOC2 = 0x17007C00;
_size_SFLASH_TOC2 = 0x00000200;
_base_XIP = 0x60000000;
_size_XIP = 0x08000000;
_base_EFUSE = 0x90700000;
_size_EFUSE = 0x00100000;
_base_ITCM = _base_CM7_0_ITCM;
_size_ITCM = _size_CM7_0_ITCM;
_base_DTCM = _base_CM7_0_DTCM;
_size_DTCM = _size_CM7_0_DTCM;
/* Force symbol to be entered in the output file as an undefined symbol. Doing
* this may, for example, trigger linking of additional modules from standard
* libraries. You may list several symbols for each EXTERN, and you may use
* EXTERN multiple times. This command has the same effect as the -u command-line
* option.
*/
EXTERN(Reset_Handler)
/* The MEMORY section below describes the location and size of blocks of memory in the target.
* Use this section to specify the memory regions available for allocation.
*/
MEMORY
{
/* The ram and flash regions control RAM and flash memory allocation for the CM7_0/CM7_1 core. */
ram (rxw) : ORIGIN = _base_SRAM, LENGTH = _size_SRAM /* SRAM */
flash_cm0p (rx) : ORIGIN = _base_CODE_FLASH_CM0P, LENGTH = _size_CODE_FLASH_CM0P /* CODE flash CM0+ */
flash (rx) : ORIGIN = _base_CODE_FLASH, LENGTH = _size_CODE_FLASH /* CODE flash CM7_0/1 */
/* This is a 256K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
* You can assign sections to this memory region for only one of the cores.
*/
em_eeprom (rw) : ORIGIN = _base_WORK_FLASH, LENGTH = _size_WORK_FLASH /* WORK flash */
/* The following regions define device specific memory regions and must not be changed. */
sflash_user_data (rx) : ORIGIN = _base_SFLASH_USER_DATA, LENGTH = _size_SFLASH_USER_DATA /* Supervisory flash: User data */
sflash_nar (rx) : ORIGIN = _base_SFLASH_NAR, LENGTH = _size_SFLASH_NAR /* Supervisory flash: Normal Access Restrictions (NAR) */
sflash_public_key (rx) : ORIGIN = _base_SFLASH_PUB_KEY, LENGTH = _size_SFLASH_PUB_KEY /* Supervisory flash: Public Key */
sflash_app_prot (rx) : ORIGIN = _base_SFLASH_APP_PROT, LENGTH = _size_SFLASH_APP_PROT
sflash_toc_2 (rx) : ORIGIN = _base_SFLASH_TOC2, LENGTH = _size_SFLASH_TOC2 /* Supervisory flash: Table of Content # 2 */
xip (rx) : ORIGIN = _base_XIP, LENGTH = _size_XIP /* XIP: 128 MB */
efuse (rx) : ORIGIN = _base_EFUSE, LENGTH = _size_EFUSE /* 1MB */
itcm (rx) : ORIGIN = _base_ITCM, LENGTH = _size_ITCM /* ITCM */
dtcm (rx) : ORIGIN = _base_DTCM, LENGTH = _base_DTCM /* DTCM */
}
/* Library configurations */
GROUP(libgcc.a libc.a libm.a libnosys.a)
SECTIONS
{
/* Cortex-M0+ application flash image area. Comment this section if you don't want to include CM0+ image */
.cy_cm0p_image ORIGIN(flash_cm0p):
{
. = ALIGN(4);
__cy_m0p_code_start = . ;
KEEP(*(.cy_m0p_image))
__cy_m0p_code_end = . ;
} > flash_cm0p
/* Check if .cy_m0p_image size exceeds cm0plus_code_flash_reserve */
ASSERT(__cy_m0p_code_end < ORIGIN(flash), "CM0+ flash image overflows with CM7, increase CM7 base address ")
/* Cortex-M7 application flash area */
.text ORIGIN(flash) :
{
/* Cortex-M7 flash vector table */
. = ALIGN(4);
__Vectors = . ;
KEEP(*(.vectors))
. = ALIGN(4);
__Vectors_End = .;
__Vectors_Size = __Vectors_End - __Vectors;
__end__ = .;
. = ALIGN(4);
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
/* Read-only code (constants). */
*(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
KEEP(*(.eh_frame*))
} > flash
.rtt_const_tables :
{
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
/* section information for utest */
. = ALIGN(4);
__rt_utest_tc_tab_start = .;
KEEP(*(UtestTcTab))
__rt_utest_tc_tab_end = .;
/* section information for initial. */
. = ALIGN(4);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(4);
PROVIDE(__ctors_start__ = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
PROVIDE(__ctors_end__ = .);
} > flash
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > flash
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > flash
__exidx_end = .;
.copy.table :
{
. = ALIGN(4);
__copy_table_start__ = .;
/* Copy data section to RAM */
LONG (__etext) /* From */
LONG (__data_start__) /* To */
LONG ((__data_end__ - __data_start__)/4) /* Size */
/* Copy code to ITCM */
LONG (__zero_table_end__) /* From */
LONG (__itcm_start__) /* To */
LONG ((__itcm_end__ - __itcm_start__)/4) /* Size */
/* Copy data to DTCM */
LONG (__itcm_flash_end__) /* From */
LONG (__dtcm_start__) /* To */
LONG ((__dtcm_end__ - __dtcm_start__)/4) /* Size */
__copy_table_end__ = .;
} > flash
.zero.table :
{
. = ALIGN(4);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG ((__bss_end__ - __bss_start__)/4)
__zero_table_end__ = .;
} > flash
/* itcm */
.cy_itcm ORIGIN(itcm):
{
__itcm_start__ = .;
KEEP(*(.cy_itcm))
__itcm_end__ = .;
} > itcm AT>flash
__itcm_flash_end__ = __zero_table_end__ + (__itcm_end__ - __itcm_start__);
/* dtcm */
.cy_dtcm ORIGIN(dtcm):
{
__dtcm_start__ = .;
KEEP(*(.cy_dtcm))
__dtcm_end__ = .;
} > dtcm AT>flash
__etext = __itcm_flash_end__ + (__dtcm_end__ - __dtcm_start__) ;
.ramVectors (NOLOAD) :
{
. = ALIGN(RAMVECTORS_ALIGNMENT);
__ram_vectors_start__ = .;
KEEP(*(.ram_vectors))
__ram_vectors_end__ = .;
} > ram
.data __ram_vectors_end__ :
{
. = ALIGN(4);
__data_start__ = .;
*(vtable)
KEEP(*(.data.cybsp_sysclk_pm_callback.1))
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
KEEP(*(.cy_ramfunc*))
. = ALIGN(32);
KEEP(*(cy_sharedmem*))
. = ALIGN(4);
__data_end__ = .;
} > ram AT>flash
/* Place variables in the section that should not be initialized during the
* device startup.
*/
.noinit (NOLOAD) : ALIGN(8)
{
KEEP(*(.noinit))
} > ram
/* The uninitialized global or static variables are placed in this section.
*
* The NOLOAD attribute tells linker that .bss section does not consume
* any space in the image. The NOLOAD attribute changes the .bss type to
* NOBITS, and that makes linker to A) not allocate section in memory, and
* A) put information to clear the section with all zeros during application
* loading.
*
* Without the NOLOAD attribute, the .bss section might get PROGBITS type.
* This makes linker to A) allocate zeroed section in memory, and B) copy
* this section to RAM during application loading.
*/
.bss (NOLOAD):
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > ram
.heap (NOLOAD):
{
__HeapBase = .;
__end__ = .;
end = __end__;
KEEP(*(.heap*))
. = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
__HeapLimit = .;
} > ram
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (NOLOAD):
{
KEEP(*(.stack*))
} > ram
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(ram) + LENGTH(ram);
__StackLimit = __StackTop - STACK_SIZE;
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
/* Emulated EEPROM Flash area */
.cy_em_eeprom :
{
KEEP(*(.cy_em_eeprom))
} > em_eeprom
/* Supervisory Flash: User data */
.cy_sflash_user_data :
{
KEEP(*(.cy_sflash_user_data))
} > sflash_user_data
/* Supervisory Flash: Normal Access Restrictions (NAR) */
.cy_sflash_nar :
{
KEEP(*(.cy_sflash_nar))
} > sflash_nar
/* Supervisory Flash: Public Key */
.cy_sflash_public_key :
{
KEEP(*(.cy_sflash_public_key))
} > sflash_public_key
/* Supervisory Flash: Table of Content # 2 */
.cy_toc_part2 :
{
KEEP(*(.cy_toc_part2))
} > sflash_toc_2
/* Places the code in the Execute in Place (XIP) section. See the smif driver
* documentation for details.
*/
cy_xip :
{
__cy_xip_start = .;
KEEP(*(.cy_xip))
__cy_xip_end = .;
} > xip
/* eFuse */
.cy_efuse :
{
KEEP(*(.cy_efuse))
} > efuse
}
/*============================================================
* Symbols for use by application
*============================================================
*/
__ecc_init_sram_start_address = ORIGIN(ram);
__ecc_init_sram_end_address = ORIGIN(ram) + LENGTH(ram);
/* EOF */

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#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m7
; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor.
;*******************************************************************************
;* \file xmc7100_x4160_cm7.sct
;* \version 1.0
;*
;* Linker file for the ARMCC.
;*
;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory
;* layout of the output file.
;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there.
;*
;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker
;* file.
;*
;*******************************************************************************
;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0
;*
;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at
;*
;* http://www.apache.org/licenses/LICENSE-2.0
;*
;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and
;* limitations under the License.
;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM0+ core.
; You can change the memory allocation by editing the RAM and Flash defines.
; Your changes must be aligned with the corresponding defines for the CM7 core in 'xxx_cm7.sct',
; where 'xx' is the device group; for example, 'xmc7200d_x8384_cm7.sct'.
; RAM
#define SRAM_TOTAL_SIZE 0x000C0000 /* 768K: SRAM0 + SRAM1 */
; FLASH
#define CODE_FLASH_TOTAL_SIZE 0x00410000 /* 4160K: TOTAL FLASH SIZE */
#define SRAM_START_RESERVE 0
#define SRAM_PRIVATE_FOR_SROM 0x800 /* 2K Private SRAM for SROM (e.g. API processing). Reserved at the beginning */
#define STACK_SIZE 0x1000
#define RAMVECTORS_ALIGNMENT 128
; RAM
#define SRAM_BASE_ADDRESS 0x28000000 /* SRAM START */
#define CM0PLUS_SRAM_RESERVE 0x00004000 /* 16K : cm0 sram size */
#define CM7_0_SRAM_RESERVE 0x000BC000 /* 752K: cm7_0 sram size */
; FLASH
#define CODE_FLASH_BASE_ADDRESS 0x10000000 /* FLASH START */
#define CM0PLUS_CODE_FLASH_RESERVE 0x00080000 /* 512K : cm0 flash size */
#define CM7_0_CODE_FLASH_RESERVE 0x00390000 /* 3648K: cm7_0 flash size */
; SRAM reservations
#define BASE_SRAM_CM0P SRAM_BASE_ADDRESS + SRAM_START_RESERVE + SRAM_PRIVATE_FOR_SROM
#define SIZE_SRAM_CM0P CM0PLUS_SRAM_RESERVE - SRAM_START_RESERVE - SRAM_PRIVATE_FOR_SROM
#define BASE_SRAM_CM7_0 SRAM_BASE_ADDRESS + CM0PLUS_SRAM_RESERVE
#define SIZE_SRAM_CM7_0 CM7_0_SRAM_RESERVE
; Code flash reservations
#define BASE_CODE_FLASH_CM0P CODE_FLASH_BASE_ADDRESS
#define SIZE_CODE_FLASH_CM0P CM0PLUS_CODE_FLASH_RESERVE
#define BASE_CODE_FLASH_CM7_0 CODE_FLASH_BASE_ADDRESS + CM0PLUS_CODE_FLASH_RESERVE
#define SIZE_CODE_FLASH_CM7_0 CM7_0_CODE_FLASH_RESERVE
#define BASE_SRAM BASE_SRAM_CM7_0
#define SIZE_SRAM SIZE_SRAM_CM7_0
#define BASE_CODE_FLASH BASE_CODE_FLASH_CM7_0
#define SIZE_CODE_FLASH SIZE_CODE_FLASH_CM7_0
; Cortex-M0+ application flash image area
LR_IROM BASE_CODE_FLASH_CM0P SIZE_CODE_FLASH_CM0P
{
.cy_m0p_image +0
{
* (.cy_m0p_image)
}
}
; Cortex-M7 application flash area
LR_IROM1 BASE_CODE_FLASH SIZE_CODE_FLASH
{
ER_FLASH_VECTORS +0
{
* (RESET, +FIRST)
}
ER_FLASH_CODE +0 FIXED
{
* (InRoot$$Sections)
* (+RO)
}
ER_RAM_VECTORS BASE_SRAM UNINIT
{
* (.bss.noinit.RESET_RAM, +FIRST)
}
RW_RAM_DATA +0
{
* (+RW, +ZI)
}
RW_RAM_SHARED_DATA +0 ALIGN 32
{
* (.cy_sharedmem)
}
; Place variables in the section that should not be initialized during the
; device startup.
RW_IRAM1 +0 UNINIT
{
* (.noinit)
* (.bss.noinit)
}
; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY BASE_SRAM+SIZE_SRAM-STACK_SIZE-AlignExpr(ImageLimit(RW_IRAM1), 8)
{
}
; Stack region growing down
ARM_LIB_STACK (BASE_SRAM+SIZE_SRAM) EMPTY -STACK_SIZE
{
}
}

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Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
src = []
group = []
CPPPATH = []
if rtconfig.PLATFORM in ['iccarm']:
print("\nThe current project does not support IAR build\n")
Return('group')
elif rtconfig.PLATFORM in ['gcc', 'armclang']:
src += Glob(cwd + '/TARGET_APP_KIT_XMC71_EVK_LITE_V2/*.c')
src += Glob(cwd + '/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/*.c')
CPPPATH = [ cwd + '/TARGET_APP_KIT_XMC71_EVK_LITE_V2',
cwd + '/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource']
if rtconfig.PLATFORM in ['gcc']:
src += [cwd + '/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM7/system_cm7.c']
src += [cwd + '/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM7/startup_cm7.c']
elif rtconfig.PLATFORM in ['armclang']:
src += [cwd + '/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM7/system_cm7.c']
src += [cwd + '/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM7/startup_cm7.c']
group = DefineGroup('libs', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

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docs

115
bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM0P/TOOLCHAIN_ARM/linker.sct Normal file
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#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor.
;*******************************************************************************
;* \file xmc7100_x4160_cm0plus.sct
;* \version 1.0
;*
;* Linker file for the ARMCC.
;*
;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory
;* layout of the output file.
;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there.
;*
;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker
;* file.
;*
;*******************************************************************************
;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0
;*
;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at
;*
;* http://www.apache.org/licenses/LICENSE-2.0
;*
;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and
;* limitations under the License.
;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM0+ core.
; You can change the memory allocation by editing the RAM and Flash defines.
; Your changes must be aligned with the corresponding defines for the CM7 core in 'xxx_cm7.sct',
; where 'xx' is the device group; for example, 'xmc7200d_x8384_cm7.sct'.
#define SRAM_START_RESERVE 0
#define SRAM_PRIVATE_FOR_SROM 0x800 /* 2K Private SRAM for SROM (e.g. API processing). Reserved at the beginning */
#define STACK_SIZE 0x1000
#define RAMVECTORS_ALIGNMENT 128
; SRAM reservations
#define SRAM_BASE_ADDRESS 0x28000000 /* SRAM START */
#define CM0PLUS_SRAM_RESERVE 0x00004000 /* 16K : cm0 sram size */
#define BASE_SRAM_CM0P SRAM_BASE_ADDRESS + SRAM_START_RESERVE + SRAM_PRIVATE_FOR_SROM
#define SIZE_SRAM_CM0P CM0PLUS_SRAM_RESERVE - SRAM_START_RESERVE - SRAM_PRIVATE_FOR_SROM
#define SRAM_CM0P_START BASE_SRAM_CM0P
#define SRAM_CM0P_SIZE SIZE_SRAM_CM0P
; Code flash reservations
#define CODE_FLASH_BASE_ADDRESS 0x10000000 /* FLASH START */
#define CM0PLUS_CODE_FLASH_RESERVE 0x00080000 /* 512K: cm0 flash size */
#define BASE_CODE_FLASH_CM0P CODE_FLASH_BASE_ADDRESS
#define SIZE_CODE_FLASH_CM0P CM0PLUS_CODE_FLASH_RESERVE
#define CODE_FLASH_CM0P_START BASE_CODE_FLASH_CM0P
#define CODE_FLASH_CM0P_SIZE SIZE_CODE_FLASH_CM0P
; Cortex-M0+ application flash area
LR_IROM1 CODE_FLASH_CM0P_START CODE_FLASH_CM0P_SIZE
{
ER_FLASH_VECTORS +0
{
* (RESET, +FIRST)
}
ER_FLASH_CODE +0 FIXED
{
* (InRoot$$Sections)
* (+RO)
}
ER_RAM_VECTORS SRAM_CM0P_START UNINIT
{
* (RESET_RAM, +FIRST)
}
RW_RAM_DATA +0
{
* (+RW, +ZI)
}
; Place variables in the section that should not be initialized during the
; device startup.
RW_IRAM1 +0 UNINIT
{
* (.noinit)
* (.bss.noinit)
}
; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY SRAM_CM0P_START+SRAM_CM0P_SIZE-STACK_SIZE-AlignExpr(ImageLimit(RW_IRAM1), 8)
{
}
; Stack region growing down
ARM_LIB_STACK (SRAM_CM0P_START+SRAM_CM0P_SIZE) EMPTY -STACK_SIZE
{
}
}

115
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#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor.
;*******************************************************************************
;* \file xmc7100d_x4160_cm0plus.sct
;* \version 1.0
;*
;* Linker file for the ARMCC.
;*
;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory
;* layout of the output file.
;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there.
;*
;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker
;* file.
;*
;*******************************************************************************
;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0
;*
;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at
;*
;* http://www.apache.org/licenses/LICENSE-2.0
;*
;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and
;* limitations under the License.
;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM0+ core.
; You can change the memory allocation by editing the RAM and Flash defines.
; Your changes must be aligned with the corresponding defines for the CM7 core in 'xxx_cm7.sct',
; where 'xx' is the device group; for example, 'xmc7200d_x8384_cm7.sct'.
#define SRAM_START_RESERVE 0
#define SRAM_PRIVATE_FOR_SROM 0x800 /* 2K Private SRAM for SROM (e.g. API processing). Reserved at the beginning */
#define STACK_SIZE 0x1000
#define RAMVECTORS_ALIGNMENT 128
; SRAM reservations
#define SRAM_BASE_ADDRESS 0x28000000 /* SRAM START */
#define CM0PLUS_SRAM_RESERVE 0x00004000 /* 16K : cm0 sram size */
#define BASE_SRAM_CM0P SRAM_BASE_ADDRESS + SRAM_START_RESERVE + SRAM_PRIVATE_FOR_SROM
#define SIZE_SRAM_CM0P CM0PLUS_SRAM_RESERVE - SRAM_START_RESERVE - SRAM_PRIVATE_FOR_SROM
#define SRAM_CM0P_START BASE_SRAM_CM0P
#define SRAM_CM0P_SIZE SIZE_SRAM_CM0P
; Code flash reservations
#define CODE_FLASH_BASE_ADDRESS 0x10000000 /* FLASH START */
#define CM0PLUS_CODE_FLASH_RESERVE 0x00080000 /* 512K: cm0 flash size */
#define BASE_CODE_FLASH_CM0P CODE_FLASH_BASE_ADDRESS
#define SIZE_CODE_FLASH_CM0P CM0PLUS_CODE_FLASH_RESERVE
#define CODE_FLASH_CM0P_START BASE_CODE_FLASH_CM0P
#define CODE_FLASH_CM0P_SIZE SIZE_CODE_FLASH_CM0P
; Cortex-M0+ application flash area
LR_IROM1 CODE_FLASH_CM0P_START CODE_FLASH_CM0P_SIZE
{
ER_FLASH_VECTORS +0
{
* (RESET, +FIRST)
}
ER_FLASH_CODE +0 FIXED
{
* (InRoot$$Sections)
* (+RO)
}
ER_RAM_VECTORS SRAM_CM0P_START UNINIT
{
* (RESET_RAM, +FIRST)
}
RW_RAM_DATA +0
{
* (+RW, +ZI)
}
; Place variables in the section that should not be initialized during the
; device startup.
RW_IRAM1 +0 UNINIT
{
* (.noinit)
* (.bss.noinit)
}
; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY SRAM_CM0P_START+SRAM_CM0P_SIZE-STACK_SIZE-AlignExpr(ImageLimit(RW_IRAM1), 8)
{
}
; Stack region growing down
ARM_LIB_STACK (SRAM_CM0P_START+SRAM_CM0P_SIZE) EMPTY -STACK_SIZE
{
}
}

213
bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_cm0plus.s Normal file
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;/**************************************************************************//**
; * @file startup_cm0plus.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM0plus Device
; * @version V1.0.1
; * @date 23. July 2019
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
CPUSS_RAM0_CTL0 EQU 0x40201300
CPUSS_RAM1_CTL0 EQU 0x40201380
CPUSS_RAM2_CTL0 EQU 0x402013a0
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Base|
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Length|
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Base| + |Image$$ARM_LIB_STACK$$ZI$$Length| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Default_Intr_Handler ; CPU User Interrupt #0
DCD Default_Intr_Handler ; CPU User Interrupt #1
DCD CM0P_CpuIntr2_Handler ; CPU User Interrupt #2
DCD CM0P_CpuIntr3_Handler ; CPU User Interrupt #3
DCD CM0P_CpuIntr4_Handler ; CPU User Interrupt #4
DCD CM0P_CpuIntr5_Handler ; CPU User Interrupt #5
DCD CM0P_CpuIntr6_Handler ; CPU User Interrupt #6
DCD CM0P_CpuIntr7_Handler ; CPU User Interrupt #7
DCD Default_Intr_Handler ; Internal SW Interrupt #0
DCD Default_Intr_Handler ; Internal SW Interrupt #1
DCD Default_Intr_Handler ; Internal SW Interrupt #2
DCD Default_Intr_Handler ; Internal SW Interrupt #3
DCD Default_Intr_Handler ; Internal SW Interrupt #4
DCD Default_Intr_Handler ; Internal SW Interrupt #5
DCD Default_Intr_Handler ; Internal SW Interrupt #6
DCD Default_Intr_Handler ; Internal SW Interrupt #7
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
EXPORT __ramVectors
AREA RESET_RAM, READWRITE, NOINIT
__ramVectors SPACE __Vectors_Size
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT CyMain
; Disable global interrupts
CPSID I
; CM0+ bus width is 32-bit, but SRAM is built with 64-bit based ECC on Traveo II parts with CM7 core
; Set CPUSS->RAMx_CTL0.ECC_CHECK_DIS bits to avoid causing unintentional ECC faults during startup while SRAM ECC has not been initialized yet
; Generic code can be used, even if RAMx_CTL0 (x > 0) registers are not implemented in a device
; or if no ECC_CHECK_DIS bits are available in the registers in case of m4cpuss with 32-bit ECC SRAM
MOVS r0, #1
LSLS r0, r0, #19
LDR r1, =CPUSS_RAM0_CTL0
LDR r2, [r1]
ORRS r2, r0
STR r2, [r1]
LDR r1, =CPUSS_RAM1_CTL0
LDR r2, [r1]
ORRS r2, r0
STR r2, [r1]
LDR r1, =CPUSS_RAM2_CTL0
LDR r2, [r1]
ORRS r2, r0
STR r2, [r1]
; Initialize ECC of startup stack (needed for local variables in C startup code) by processing 8 bytes per loop iteration,
; because the ECC initialization feature uses this generic granularity that will cover any memory (SRAM/TCM) in any TVII device
; Prerequisite: Stack Pointer (SP) has not been modified (from the vector table init value) by above code (otherwise code must be adapted)
LDR r3, =|Image$$ARM_LIB_STACK$$ZI$$Base|
LDR r1, =|Image$$ARM_LIB_STACK$$ZI$$Length|
ADD r1, r1, r3 ; r1 = stack top
MOV r0, r1
LDR r3, =0x100
SUBS r0, r0, r3 ; r0 = stack offset
MOVS r2, #0 ; clear value
MOVS r3, #0 ; clear value
loopstackclean
STM r0!, {r2, r3}
CMP r0, r1
BNE loopstackclean
LDR R0, =SystemInit
BLX R0
LDR R0, =CyMain
BX R0
ENDP
Default_Handler PROC
EXPORT Default_Handler [WEAK]
EXPORT CM0P_CpuIntr2_Handler [WEAK]
EXPORT CM0P_CpuIntr3_Handler [WEAK]
EXPORT CM0P_CpuIntr4_Handler [WEAK]
EXPORT CM0P_CpuIntr5_Handler [WEAK]
EXPORT CM0P_CpuIntr6_Handler [WEAK]
EXPORT CM0P_CpuIntr7_Handler [WEAK]
CM0P_CpuIntr2_Handler
CM0P_CpuIntr3_Handler
CM0P_CpuIntr4_Handler
CM0P_CpuIntr5_Handler
CM0P_CpuIntr6_Handler
CM0P_CpuIntr7_Handler
B .
ENDP
Cy_SysLib_FaultHandler PROC
EXPORT Cy_SysLib_FaultHandler [WEAK]
B .
ENDP
; The default macro is not used for HardFault_Handler
; because this results in a poor debug illusion.
HardFault_Handler PROC
EXPORT HardFault_Handler [WEAK]
movs r0, #4
mov r1, LR
tst r0, r1
beq L_MSP
mrs r0, PSP
bl L_API_call
L_MSP
mrs r0, MSP
L_API_call
bl Cy_SysLib_FaultHandler
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Default_Intr_Handler
ALIGN
END

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/***************************************************************************//**
* \file xmc7100_x4160_cm0plus.ld
* \version 1.0.0
*
* Linker file for the GNU C compiler.
*
* The main purpose of the linker script is to describe how the sections in the
* input files should be mapped into the output file, and to control the memory
* layout of the output file.
*
* \note The entry point location is fixed and starts at 0x10000000. The valid
* application image should be placed there.
*
* \note The linker files included with the PDL template projects must be generic
* and handle all common use cases. Your project may not use every section
* defined in the linker files. In that case you may see warnings during the
* build process. In your project, you can simply comment out or remove the
* relevant code in the linker file.
*
********************************************************************************
* \copyright
* Copyright 2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
GROUP(-lgcc -lc -lnosys )
SEARCH_DIR(.)
GROUP(libgcc.a libc.a libm.a libnosys.a)
ENTRY(Reset_Handler)
/* The size of the stack section at the end of CM7 SRAM */
STACK_SIZE = 0x1000;
RAMVECTORS_ALIGNMENT = 128;
sram_start_reserve = 0;
sram_private_for_srom = 0x00000800; /* Private SRAM for SROM (e.g. API processing). Reserved at the beginning */
cm0plus_sram_reserve = 0x00004000; /* 16K : cm0 sram size */
cm0plus_code_flash_reserve = 0x00080000; /* 512K: cm0 flash size */
sram_base_address = 0x28000000;
code_flash_base_address = 0x10000000;
_base_SRAM_CM0P = sram_base_address + sram_start_reserve + sram_private_for_srom;
_size_SRAM_CM0P = cm0plus_sram_reserve - sram_start_reserve - sram_private_for_srom;
_base_CODE_FLASH_CM0P = code_flash_base_address;
_size_CODE_FLASH_CM0P = cm0plus_code_flash_reserve;
/* Fixed Addesses */
_base_WORK_FLASH = 0x14000000;
_size_WORK_FLASH = 0x00040000; /* 256K Work flash */
_base_SFLASH_USER_DATA = 0x17000800;
_size_SFLASH_USER_DATA = 0x00000800;
_base_SFLASH_NAR = 0x17001A00;
_size_SFLASH_NAR = 0x00000200;
_base_SFLASH_PUB_KEY = 0x17006400;
_size_SFLASH_PUB_KEY = 0x00000C00;
_base_SFLASH_APP_PROT = 0x17007600;
_size_SFLASH_APP_PROT = 0x00000200;
_base_SFLASH_TOC2 = 0x17007C00;
_size_SFLASH_TOC2 = 0x00000200;
_base_XIP = 0x60000000;
_size_XIP = 0x08000000;
_base_EFUSE = 0x90700000;
_size_EFUSE = 0x00100000;
/* Force symbol to be entered in the output file as an undefined symbol. Doing
* this may, for example, trigger linking of additional modules from standard
* libraries. You may list several symbols for each EXTERN, and you may use
* EXTERN multiple times. This command has the same effect as the -u command-line
* option.
*/
EXTERN(Reset_Handler)
/* The MEMORY section below describes the location and size of blocks of memory in the target.
* Use this section to specify the memory regions available for allocation.
*/
MEMORY
{
/* The ram and flash regions control RAM and flash memory allocation for the CM33 core.
*/
cm0_ram (rxw) : ORIGIN = _base_SRAM_CM0P, LENGTH = _size_SRAM_CM0P
cm0_flash (rx) : ORIGIN = _base_CODE_FLASH_CM0P, LENGTH = _size_CODE_FLASH_CM0P
/* This is a 256K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
* You can assign sections to this memory region for only one of the cores.
*/
em_eeprom (rw) : ORIGIN = _base_WORK_FLASH, LENGTH = _size_WORK_FLASH /* WORK flash */
/* The following regions define device specific memory regions and must not be changed. */
sflash_user_data (rx) : ORIGIN = _base_SFLASH_USER_DATA, LENGTH = _size_SFLASH_USER_DATA /* Supervisory flash: User data */
sflash_nar (rx) : ORIGIN = _base_SFLASH_NAR, LENGTH = _size_SFLASH_NAR /* Supervisory flash: Normal Access Restrictions (NAR) */
sflash_public_key (rx) : ORIGIN = _base_SFLASH_PUB_KEY, LENGTH = _size_SFLASH_PUB_KEY /* Supervisory flash: Public Key */
sflash_app_prot (rx) : ORIGIN = _base_SFLASH_APP_PROT, LENGTH = _size_SFLASH_APP_PROT
sflash_toc_2 (rx) : ORIGIN = _base_SFLASH_TOC2, LENGTH = _size_SFLASH_TOC2 /* Supervisory flash: Table of Content # 2 */
xip (rx) : ORIGIN = _base_XIP, LENGTH = _size_XIP /* XIP: 128 MB */
efuse (rx) : ORIGIN = _base_EFUSE, LENGTH = _size_EFUSE /* 1MB */
}
/* Library configurations */
GROUP(libgcc.a libc.a libm.a libnosys.a)
SECTIONS
{
/* Cortex-M4 application flash area */
.text ORIGIN(cm0_flash) :
{
/* Cortex-M4 flash vector table */
. = ALIGN(4);
__Vectors = . ;
KEEP(*(.vectors))
. = ALIGN(4);
__Vectors_End = .;
__Vectors_Size = __Vectors_End - __Vectors;
__end__ = .;
. = ALIGN(4);
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
/* Read-only code (constants). */
*(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
KEEP(*(.eh_frame*))
} > cm0_flash
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > cm0_flash
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > cm0_flash
__exidx_end = .;
/* To copy multiple ROM to RAM sections,
* uncomment .copy.table section and,
* define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm4.S */
.copy.table :
{
. = ALIGN(4);
__copy_table_start__ = .;
/* Copy data section to RAM */
LONG (__etext) /* From */
LONG (__data_start__) /* To */
LONG ((__data_end__ - __data_start__)/4) /* Size */
__copy_table_end__ = .;
} > cm0_flash
/* To clear multiple BSS sections,
* uncomment .zero.table section and,
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm4.S */
.zero.table :
{
. = ALIGN(4);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG ((__bss_end__ - __bss_start__)/4)
__zero_table_end__ = .;
} > cm0_flash
__etext = . ;
.ramVectors (NOLOAD) :
{
. = ALIGN(RAMVECTORS_ALIGNMENT);
__ram_vectors_start__ = .;
KEEP(*(.ram_vectors))
__ram_vectors_end__ = .;
} > cm0_ram
.data __ram_vectors_end__ :
{
. = ALIGN(4);
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
KEEP(*(.cy_ramfunc*))
. = ALIGN(4);
__data_end__ = .;
} > cm0_ram AT>cm0_flash
/* Place variables in the section that should not be initialized during the
* device startup.
*/
.noinit (NOLOAD) : ALIGN(8)
{
KEEP(*(.noinit))
} > cm0_ram
/* The uninitialized global or static variables are placed in this section.
*
* The NOLOAD attribute tells linker that .bss section does not consume
* any space in the image. The NOLOAD attribute changes the .bss type to
* NOBITS, and that makes linker to A) not allocate section in memory, and
* A) put information to clear the section with all zeros during application
* loading.
*
* Without the NOLOAD attribute, the .bss section might get PROGBITS type.
* This makes linker to A) allocate zeroed section in memory, and B) copy
* this section to RAM during application loading.
*/
.bss (NOLOAD):
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > cm0_ram
.heap (NOLOAD):
{
__HeapBase = .;
__end__ = .;
end = __end__;
KEEP(*(.heap*))
. = ORIGIN(cm0_ram) + LENGTH(cm0_ram) - STACK_SIZE;
__HeapLimit = .;
} > cm0_ram
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (NOLOAD):
{
KEEP(*(.stack*))
} > cm0_ram
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(cm0_ram) + LENGTH(cm0_ram);
__StackLimit = __StackTop - STACK_SIZE;
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
/* Emulated EEPROM Flash area */
.cy_em_eeprom :
{
KEEP(*(.cy_em_eeprom))
} > em_eeprom
/* Supervisory Flash: User data */
.cy_sflash_user_data :
{
KEEP(*(.cy_sflash_user_data))
} > sflash_user_data
/* Supervisory Flash: Normal Access Restrictions (NAR) */
.cy_sflash_nar :
{
KEEP(*(.cy_sflash_nar))
} > sflash_nar
/* Supervisory Flash: Public Key */
.cy_sflash_public_key :
{
KEEP(*(.cy_sflash_public_key))
} > sflash_public_key
/* Supervisory Flash: Table of Content # 2 */
.cy_toc_part2 :
{
KEEP(*(.cy_toc_part2))
} > sflash_toc_2
/* Places the code in the Execute in Place (XIP) section. See the smif driver
* documentation for details.
*/
cy_xip :
{
__cy_xip_start = .;
KEEP(*(.cy_xip))
__cy_xip_end = .;
} > xip
/* eFuse */
.cy_efuse :
{
KEEP(*(.cy_efuse))
} > efuse
}
/* EOF */

367
bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/linker_d.ld Normal file
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/***************************************************************************//**
* \file xmc7100d_x4160_cm0plus.ld
* \version 1.0.0
*
* Linker file for the GNU C compiler.
*
* The main purpose of the linker script is to describe how the sections in the
* input files should be mapped into the output file, and to control the memory
* layout of the output file.
*
* \note The entry point location is fixed and starts at 0x10000000. The valid
* application image should be placed there.
*
* \note The linker files included with the PDL template projects must be generic
* and handle all common use cases. Your project may not use every section
* defined in the linker files. In that case you may see warnings during the
* build process. In your project, you can simply comment out or remove the
* relevant code in the linker file.
*
********************************************************************************
* \copyright
* Copyright 2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
GROUP(-lgcc -lc -lnosys )
SEARCH_DIR(.)
GROUP(libgcc.a libc.a libm.a libnosys.a)
ENTRY(Reset_Handler)
/* The size of the stack section at the end of CM7_1 SRAM */
STACK_SIZE = 0x1000;
RAMVECTORS_ALIGNMENT = 128;
sram_start_reserve = 0;
sram_private_for_srom = 0x00000800; /* Private SRAM for SROM (e.g. API processing). Reserved at the beginning */
cm0plus_sram_reserve = 0x00004000; /* 16K : cm0 sram size */
cm0plus_code_flash_reserve = 0x00080000; /* 512K: cm0 flash size */
sram_base_address = 0x28000000;
code_flash_base_address = 0x10000000;
_base_SRAM_CM0P = sram_base_address + sram_start_reserve + sram_private_for_srom;
_size_SRAM_CM0P = cm0plus_sram_reserve - sram_start_reserve - sram_private_for_srom;
_base_CODE_FLASH_CM0P = code_flash_base_address;
_size_CODE_FLASH_CM0P = cm0plus_code_flash_reserve;
/* Fixed Addesses */
_base_WORK_FLASH = 0x14000000;
_size_WORK_FLASH = 0x00040000; /* 256K Work flash */
_base_SFLASH_USER_DATA = 0x17000800;
_size_SFLASH_USER_DATA = 0x00000800;
_base_SFLASH_NAR = 0x17001A00;
_size_SFLASH_NAR = 0x00000200;
_base_SFLASH_PUB_KEY = 0x17006400;
_size_SFLASH_PUB_KEY = 0x00000C00;
_base_SFLASH_APP_PROT = 0x17007600;
_size_SFLASH_APP_PROT = 0x00000200;
_base_SFLASH_TOC2 = 0x17007C00;
_size_SFLASH_TOC2 = 0x00000200;
_base_XIP = 0x60000000;
_size_XIP = 0x08000000;
_base_EFUSE = 0x90700000;
_size_EFUSE = 0x00100000;
/* Force symbol to be entered in the output file as an undefined symbol. Doing
* this may, for example, trigger linking of additional modules from standard
* libraries. You may list several symbols for each EXTERN, and you may use
* EXTERN multiple times. This command has the same effect as the -u command-line
* option.
*/
EXTERN(Reset_Handler)
/* The MEMORY section below describes the location and size of blocks of memory in the target.
* Use this section to specify the memory regions available for allocation.
*/
MEMORY
{
/* The ram and flash regions control RAM and flash memory allocation for the CM33 core.
*/
cm0_ram (rxw) : ORIGIN = _base_SRAM_CM0P, LENGTH = _size_SRAM_CM0P
cm0_flash (rx) : ORIGIN = _base_CODE_FLASH_CM0P, LENGTH = _size_CODE_FLASH_CM0P
/* This is a 256K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
* You can assign sections to this memory region for only one of the cores.
*/
em_eeprom (rw) : ORIGIN = _base_WORK_FLASH, LENGTH = _size_WORK_FLASH /* WORK flash */
/* The following regions define device specific memory regions and must not be changed. */
sflash_user_data (rx) : ORIGIN = _base_SFLASH_USER_DATA, LENGTH = _size_SFLASH_USER_DATA /* Supervisory flash: User data */
sflash_nar (rx) : ORIGIN = _base_SFLASH_NAR, LENGTH = _size_SFLASH_NAR /* Supervisory flash: Normal Access Restrictions (NAR) */
sflash_public_key (rx) : ORIGIN = _base_SFLASH_PUB_KEY, LENGTH = _size_SFLASH_PUB_KEY /* Supervisory flash: Public Key */
sflash_app_prot (rx) : ORIGIN = _base_SFLASH_APP_PROT, LENGTH = _size_SFLASH_APP_PROT
sflash_toc_2 (rx) : ORIGIN = _base_SFLASH_TOC2, LENGTH = _size_SFLASH_TOC2 /* Supervisory flash: Table of Content # 2 */
xip (rx) : ORIGIN = _base_XIP, LENGTH = _size_XIP /* XIP: 128 MB */
efuse (rx) : ORIGIN = _base_EFUSE, LENGTH = _size_EFUSE /* 1MB */
}
/* Library configurations */
GROUP(libgcc.a libc.a libm.a libnosys.a)
SECTIONS
{
/* Cortex-M4 application flash area */
.text ORIGIN(cm0_flash) :
{
/* Cortex-M4 flash vector table */
. = ALIGN(4);
__Vectors = . ;
KEEP(*(.vectors))
. = ALIGN(4);
__Vectors_End = .;
__Vectors_Size = __Vectors_End - __Vectors;
__end__ = .;
. = ALIGN(4);
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
/* Read-only code (constants). */
*(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
KEEP(*(.eh_frame*))
} > cm0_flash
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > cm0_flash
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > cm0_flash
__exidx_end = .;
/* To copy multiple ROM to RAM sections,
* uncomment .copy.table section and,
* define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm4.S */
.copy.table :
{
. = ALIGN(4);
__copy_table_start__ = .;
/* Copy data section to RAM */
LONG (__etext) /* From */
LONG (__data_start__) /* To */
LONG ((__data_end__ - __data_start__)/4) /* Size */
__copy_table_end__ = .;
} > cm0_flash
/* To clear multiple BSS sections,
* uncomment .zero.table section and,
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm4.S */
.zero.table :
{
. = ALIGN(4);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG ((__bss_end__ - __bss_start__)/4)
__zero_table_end__ = .;
} > cm0_flash
__etext = . ;
.ramVectors (NOLOAD) :
{
. = ALIGN(RAMVECTORS_ALIGNMENT);
__ram_vectors_start__ = .;
KEEP(*(.ram_vectors))
__ram_vectors_end__ = .;
} > cm0_ram
.data __ram_vectors_end__ :
{
. = ALIGN(4);
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
KEEP(*(.cy_ramfunc*))
. = ALIGN(4);
__data_end__ = .;
} > cm0_ram AT>cm0_flash
/* Place variables in the section that should not be initialized during the
* device startup.
*/
.noinit (NOLOAD) : ALIGN(8)
{
KEEP(*(.noinit))
} > cm0_ram
/* The uninitialized global or static variables are placed in this section.
*
* The NOLOAD attribute tells linker that .bss section does not consume
* any space in the image. The NOLOAD attribute changes the .bss type to
* NOBITS, and that makes linker to A) not allocate section in memory, and
* A) put information to clear the section with all zeros during application
* loading.
*
* Without the NOLOAD attribute, the .bss section might get PROGBITS type.
* This makes linker to A) allocate zeroed section in memory, and B) copy
* this section to RAM during application loading.
*/
.bss (NOLOAD):
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > cm0_ram
.heap (NOLOAD):
{
__HeapBase = .;
__end__ = .;
end = __end__;
KEEP(*(.heap*))
. = ORIGIN(cm0_ram) + LENGTH(cm0_ram) - STACK_SIZE;
__HeapLimit = .;
} > cm0_ram
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (NOLOAD):
{
KEEP(*(.stack*))
} > cm0_ram
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(cm0_ram) + LENGTH(cm0_ram);
__StackLimit = __StackTop - STACK_SIZE;
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
/* Emulated EEPROM Flash area */
.cy_em_eeprom :
{
KEEP(*(.cy_em_eeprom))
} > em_eeprom
/* Supervisory Flash: User data */
.cy_sflash_user_data :
{
KEEP(*(.cy_sflash_user_data))
} > sflash_user_data
/* Supervisory Flash: Normal Access Restrictions (NAR) */
.cy_sflash_nar :
{
KEEP(*(.cy_sflash_nar))
} > sflash_nar
/* Supervisory Flash: Public Key */
.cy_sflash_public_key :
{
KEEP(*(.cy_sflash_public_key))
} > sflash_public_key
/* Supervisory Flash: Table of Content # 2 */
.cy_toc_part2 :
{
KEEP(*(.cy_toc_part2))
} > sflash_toc_2
/* Places the code in the Execute in Place (XIP) section. See the smif driver
* documentation for details.
*/
cy_xip :
{
__cy_xip_start = .;
KEEP(*(.cy_xip))
__cy_xip_end = .;
} > xip
/* eFuse */
.cy_efuse :
{
KEEP(*(.cy_efuse))
} > efuse
}
/* EOF */

200
bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_cm0plus.S Normal file
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@ -0,0 +1,200 @@
/**************************************************************************//**
* @file startup_cm0plus.S
* @brief CMSIS-Core(M) Device Startup File for Cortex-M0plus Device
* @version V2.2.0
* @date 26. May 2021
******************************************************************************/
/*
* Copyright (c) 2009-2021 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#define CPUSS_RAM0_CTL0 0x40201300
#define CPUSS_RAM1_CTL0 0x40201380
#define CPUSS_RAM2_CTL0 0x402013a0
.syntax unified
.arch armv6-m
.section .vectors
.align 2
.globl __Vectors
.globl __Vectors_End
.globl __Vectors_Size
.global CM0P_CpuIntr2_Handler
.global CM0P_CpuIntr3_Handler
.global CM0P_CpuIntr4_Handler
.global CM0P_CpuIntr5_Handler
.global CM0P_CpuIntr6_Handler
.global CM0P_CpuIntr7_Handler
__Vectors:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* -14 NMI Handler */
.long HardFault_Handler /* -13 Hard Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* -5 SVCall Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long PendSV_Handler /* -2 PendSV Handler */
.long SysTick_Handler /* -1 SysTick Handler */
/* Interrupts */
.long Default_Intr_Handler /* CPU User Interrupt #0 */
.long Default_Intr_Handler /* CPU User Interrupt #1 */
.long CM0P_CpuIntr2_Handler /* CPU User Interrupt #2 */
.long CM0P_CpuIntr3_Handler /* CPU User Interrupt #3 */
.long CM0P_CpuIntr4_Handler /* CPU User Interrupt #4 */
.long CM0P_CpuIntr5_Handler /* CPU User Interrupt #5 */
.long CM0P_CpuIntr6_Handler /* CPU User Interrupt #6 */
.long CM0P_CpuIntr7_Handler /* CPU User Interrupt #7 */
.long Default_Intr_Handler /* Internal SW Interrupt #0 */
.long Default_Intr_Handler /* Internal SW Interrupt #1 */
.long Default_Intr_Handler /* Internal SW Interrupt #2 */
.long Default_Intr_Handler /* Internal SW Interrupt #3 */
.long Default_Intr_Handler /* Internal SW Interrupt #4 */
.long Default_Intr_Handler /* Internal SW Interrupt #5 */
.long Default_Intr_Handler /* Internal SW Interrupt #6 */
.long Default_Intr_Handler /* Internal SW Interrupt #7 */
__Vectors_End:
.equ __Vectors_Size, __Vectors_End - __Vectors
.size __Vectors, . - __Vectors
.section .ram_vectors
.align 2
.globl __ramVectors
__ramVectors:
.space __Vectors_Size
.size __ramVectors, . - __ramVectors
.thumb
.section .text
.align 2
.thumb_func
.type Reset_Handler, %function
.globl Reset_Handler
.extern __cmsis_start
.fnstart
Reset_Handler:
/* CM0+ bus width is 32-bit, but SRAM is built with 64-bit based ECC on Traveo II parts with CM7 core
* Set CPUSS->RAMx_CTL0.ECC_CHECK_DIS bits to avoid causing unintentional ECC faults during startup while SRAM ECC has not been initialized yet
* Generic code can be used, even if RAMx_CTL0 (x > 0) registers are not implemented in a device
* or if no ECC_CHECK_DIS bits are available in the registers in case of m4cpuss with 32-bit ECC SRAM
*/
movs r0, #1
lsls r0, r0, #19
ldr r1, =CPUSS_RAM0_CTL0
ldr r2, [r1]
orrs r2, r0
str r2, [r1]
ldr r1, =CPUSS_RAM1_CTL0
ldr r2, [r1]
orrs r2, r0
str r2, [r1]
ldr r1, =CPUSS_RAM2_CTL0
ldr r2, [r1]
orrs r2, r0
str r2, [r1]
/* Initialize ECC of startup stack (needed for local variables in C startup code) by processing 8 bytes per loop iteration,
* because the ECC initialization feature uses this generic granularity that will cover any memory (SRAM/TCM) in any TVII device
* Prerequisite: Stack Pointer (SP) has not been modified (from the vector table init value) by above code (otherwise code must be adapted)
*/
ldr r0, =__StackTop-0x100
ldr r1, =__StackTop
movs r2, #0
movs r3, #0
loopstackclean:
stmia r0!, {r2, r3}
cmp r0, r1
bcc.n loopstackclean
bl SystemInit
bl CyMain
.fnend
.size Reset_Handler, . - Reset_Handler
.thumb_func
.type Default_Handler, %function
.weak Default_Handler
Default_Handler:
b .
.size Default_Handler, . - Default_Handler
.weak Cy_SysLib_FaultHandler
.type Cy_SysLib_FaultHandler, %function
Cy_SysLib_FaultHandler:
b .
.size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler
.type Fault_Handler, %function
Fault_Handler:
/* Storing LR content for Creator call stack trace */
push {LR}
movs r0, #4
mov r1, LR
tst r0, r1
beq .L_MSP
mrs r0, PSP
b .L_API_call
.L_MSP:
mrs r0, MSP
/* Compensation of stack pointer address due to pushing 4 bytes of LR */
adds r0, r0, #4
.L_API_call:
bl Cy_SysLib_FaultHandler
b .
.size Fault_Handler, . - Fault_Handler
.macro Def_Fault_Handler fault_handler_name
.weak \fault_handler_name
.set \fault_handler_name, Fault_Handler
.endm
/* Macro to define default exception/interrupt handlers.
* Default handler are weak symbols with an endless loop.
* They can be overwritten by real handlers.
*/
.macro Def_Irq_Handler Handler_Name
.weak \Handler_Name
.set \Handler_Name, Default_Handler
.endm
/* Default exception/interrupt handlers */
Def_Irq_Handler NMI_Handler
Def_Fault_Handler HardFault_Handler
Def_Irq_Handler SVC_Handler
Def_Irq_Handler PendSV_Handler
Def_Irq_Handler SysTick_Handler
Def_Irq_Handler Default_Intr_Handler
.end
/* [] END OF FILE */

147
bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM0P/TOOLCHAIN_IAR/linker.icf Normal file
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/*******************************************************************************
* \file xmc7100_x4160_cm0plus.icf
* \version 1.0.0
*
* Linker file for the IAR compiler.
*
* The main purpose of the linker script is to describe how the sections in the
* input files should be mapped into the output file, and to control the memory
* layout of the output file.
*
* \note The entry point is fixed and starts at 0x10000000. The valid application
* image should be placed there.
*
* \note The linker files included with the PDL template projects must be generic
* and handle all common use cases. Your project may not use every section
* defined in the linker files. In that case you may see warnings during the
* build process. In your project, you can simply comment out or remove the
* relevant code in the linker file.
*
********************************************************************************
* \copyright
* Copyright 2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
define symbol RAMVECTORS_ALIGNMENT = 128;
define symbol sram_start_reserve = 0;
define symbol sram_private_for_srom = 0x00000800; /* Private SRAM for SROM (e.g. API processing). Reserved at the beginning */
define symbol cm0plus_sram_reserve = 0x00004000; /* 16K : cm0 sram size */
define symbol cm0plus_code_flash_reserve = 0x00080000; /* 512K: cm0 flash size */
define symbol sram_base_address = 0x28000000;
define symbol code_flash_base_address = 0x10000000;
define symbol ecc_init_width = 8; /* Most restrictive native ECC width of all "normal" memories (SRAM, DTCM, ITCM) in any Traveo II derivate is used to keep the code generic */
define symbol cm0plus_heap_reserve = 0x00001000;
define symbol cm0plus_stack_reserve = 0x00001000;
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/* The symbols below define the location and size of blocks of memory in the target.
* Use these symbols to specify the memory regions available for allocation.
*/
/* The following symbols control RAM and flash memory allocation for the CM0+ core.
* You can change the memory allocation by editing RAM and Flash values.
* Using this memory region for other purposes will lead to unexpected behavior.
* Your changes must be aligned with the corresponding symbols for CM7 core in 'xx_cm7.icf',
* where 'xx' is the device group; for example, 'xmc7200d_x8384_cm7.icf'.
* any changes here must also be aligned in file 'xmc7xxx_partition.h'.
* after which cm0p core aplication must be build and flashed again.
*/
/* RAM */
define symbol __ICFEDIT_region_RAM_start__ = 0x28000800; // sram_base_address + sram_start_reserve + sram_private_for_srom;
define symbol __ICFEDIT_region_RAM_end__ = 0x28003FFF; // cm0plus_sram_reserve - 1
/* Flash */
define symbol __ICFEDIT_region_ROM_start__ = 0x10000000; // code_flash_base_address
define symbol __ICFEDIT_region_ROM_end__ = 0x1007FFFF; // cm0plus_code_flash_reserve - 1
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x00001000; //cm0plus_stack_reserve
/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
define symbol __ICFEDIT_size_heap__ = 0x00001000; //cm0plus_heap_reserve
/**** End of ICF editor section. ###ICF###*/
define symbol heap_reserve = __ICFEDIT_size_heap__;
define symbol stack_reserve = (__ICFEDIT_size_cstack__ + (ecc_init_width - 1)) & (~((ecc_init_width - 1))); /* Ensure that stack size is an integer multiple of ECC init width (round up) */
define symbol _base_SRAM_CM0P = __ICFEDIT_region_RAM_start__;
define symbol _size_SRAM_CM0P = __ICFEDIT_region_RAM_end__ - __ICFEDIT_region_RAM_start__ + 1;
define symbol _base_CODE_FLASH_CM0P = __ICFEDIT_region_ROM_start__;
define symbol _size_CODE_FLASH_CM0P = __ICFEDIT_region_ROM_end__ - __ICFEDIT_region_ROM_start__ + 1;
/*============================================================
* Memory definitions
*============================================================
*/
define memory mem with size = 4G;
define region SRAM = mem:[from _base_SRAM_CM0P size _size_SRAM_CM0P ];
define region CODE_FLASH = mem:[from _base_CODE_FLASH_CM0P size _size_CODE_FLASH_CM0P ];
/*============================================================
* Block definitions
*============================================================
*/
define block CSTACK with alignment = 8, size = stack_reserve { };
define block HEAP with expanding size, alignment = 8, minimum size = heap_reserve { };
define block HEAP_STACK { block HEAP, last block CSTACK };
/*============================================================
* Initialization
*============================================================
*/
initialize by copy { readwrite };
do not initialize { section .noinit, section .intvec_ram };
/*============================================================
* Placement
*============================================================
*/
/* Link location specific assignment of 'readonly' type sections to either SRAM or CODE_FLASH */
/* Note: .intvec must be the first section in ROM in order for __cm7_vector_base_linker_symbol to be correctly calculated! */
place at start of CODE_FLASH { section .intvec };
place in CODE_FLASH { readonly };
place in SRAM { readwrite };
place at end of SRAM { block HEAP_STACK };
keep { section .intvec };
/*============================================================
* Symbols for use by application
*============================================================
*/
/* The start of CM7_0/1 vector table is required by CM0+ application to correctly
* set CPUSS->CM7_0/1_VECTOR_TABLE_BASE register before releasing CM7_0 or CM7_1 from reset
*/
define exported symbol __ecc_init_sram_start_address = start(SRAM);
define exported symbol __ecc_init_sram_end_address = end(SRAM);
/* EOF */

148
bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM0P/TOOLCHAIN_IAR/linker_d.icf Normal file
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/*******************************************************************************
* \file xmc7100d_x4160_cm0plus.icf
* \version 1.0.0
*
* Linker file for the IAR compiler.
*
* The main purpose of the linker script is to describe how the sections in the
* input files should be mapped into the output file, and to control the memory
* layout of the output file.
*
* \note The entry point is fixed and starts at 0x10000000. The valid application
* image should be placed there.
*
* \note The linker files included with the PDL template projects must be generic
* and handle all common use cases. Your project may not use every section
* defined in the linker files. In that case you may see warnings during the
* build process. In your project, you can simply comment out or remove the
* relevant code in the linker file.
*
********************************************************************************
* \copyright
* Copyright 2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
define symbol RAMVECTORS_ALIGNMENT = 128;
define symbol sram_start_reserve = 0;
define symbol sram_private_for_srom = 0x00000800; /* Private SRAM for SROM (e.g. API processing). Reserved at the beginning */
define symbol cm0plus_sram_reserve = 0x00004000; /* 16K : cm0 sram size */
define symbol cm0plus_code_flash_reserve = 0x00080000; /* 512K: cm0 flash size */
define symbol sram_base_address = 0x28000000;
define symbol code_flash_base_address = 0x10000000;
define symbol ecc_init_width = 8; /* Most restrictive native ECC width of all "normal" memories (SRAM, DTCM, ITCM) in any Traveo II derivate is used to keep the code generic */
define symbol cm0plus_heap_reserve = 0x00001000;
define symbol cm0plus_stack_reserve = 0x00001000;
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/* The symbols below define the location and size of blocks of memory in the target.
* Use these symbols to specify the memory regions available for allocation.
*/
/* The following symbols control RAM and flash memory allocation for the CM0+ core.
* You can change the memory allocation by editing RAM and Flash values.
* Using this memory region for other purposes will lead to unexpected behavior.
* Your changes must be aligned with the corresponding symbols for CM7 core in 'xx_cm7.icf',
* where 'xx' is the device group; for example, 'xmc7100d_x4160_cm7.icf'.
* any changes here must also be aligned in file 'xmc7xxx_partition.h'.
* after which cm0p core aplication must be build and flashed again.
*/
/* RAM */
define symbol __ICFEDIT_region_RAM_start__ = 0x28000800; // sram_base_address + sram_start_reserve + sram_private_for_srom;
define symbol __ICFEDIT_region_RAM_end__ = 0x28003FFF; // cm0plus_sram_reserve - 1
/* Flash */
define symbol __ICFEDIT_region_ROM_start__ = 0x10000000; // code_flash_base_address
define symbol __ICFEDIT_region_ROM_end__ = 0x1007FFFF; // cm0plus_code_flash_reserve - 1
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x00001000; //cm0plus_stack_reserve
/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
define symbol __ICFEDIT_size_heap__ = 0x00001000; //cm0plus_heap_reserve
/**** End of ICF editor section. ###ICF###*/
define symbol heap_reserve = __ICFEDIT_size_heap__;
define symbol stack_reserve = (__ICFEDIT_size_cstack__ + (ecc_init_width - 1)) & (~((ecc_init_width - 1))); /* Ensure that stack size is an integer multiple of ECC init width (round up) */
define symbol _base_SRAM_CM0P = __ICFEDIT_region_RAM_start__;
define symbol _size_SRAM_CM0P = __ICFEDIT_region_RAM_end__ - __ICFEDIT_region_RAM_start__ + 1;
define symbol _base_CODE_FLASH_CM0P = __ICFEDIT_region_ROM_start__;
define symbol _size_CODE_FLASH_CM0P = __ICFEDIT_region_ROM_end__ - __ICFEDIT_region_ROM_start__ + 1;
/*============================================================
* Memory definitions
*============================================================
*/
define memory mem with size = 4G;
define region SRAM = mem:[from _base_SRAM_CM0P size _size_SRAM_CM0P ];
define region CODE_FLASH = mem:[from _base_CODE_FLASH_CM0P size _size_CODE_FLASH_CM0P ];
/*============================================================
* Block definitions
*============================================================
*/
define block CSTACK with alignment = 8, size = stack_reserve { };
define block HEAP with expanding size, alignment = 8, minimum size = heap_reserve { };
define block HEAP_STACK { block HEAP, last block CSTACK };
/*============================================================
* Initialization
*============================================================
*/
initialize by copy { readwrite };
do not initialize { section .noinit, section .intvec_ram };
/*============================================================
* Placement
*============================================================
*/
/* Link location specific assignment of 'readonly' type sections to either SRAM or CODE_FLASH */
/* Note: .intvec must be the first section in ROM in order for __cm7_vector_base_linker_symbol to be correctly calculated! */
place at start of CODE_FLASH { section .intvec };
place in CODE_FLASH { readonly };
place in SRAM { readwrite };
place at end of SRAM { block HEAP_STACK };
keep { section .intvec };
/*============================================================
* Symbols for use by application
*============================================================
*/
/* The start of CM7_0/1 vector table is required by CM0+ application to correctly
* set CPUSS->CM7_0/1_VECTOR_TABLE_BASE register before releasing CM7_0 or CM7_1 from reset
*/
define exported symbol __ecc_init_sram_start_address = start(SRAM);
define exported symbol __ecc_init_sram_end_address = end(SRAM);
/* EOF */

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bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_cm0plus.s Normal file
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;/**************************************************************************//**
; * @file startup_cm0plus.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM0plus Device
; * @version V1.0.0
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;************************************************************************
;* Local definitions
;************************************************************************
; Set a sufficient startup stack size for correct operation of C startup code (startup.c)
STARTUP_STACK_SIZE_DOUBLE_WORDS EQU 32
VTOR EQU 0xe000ed08
CPUSS_RAM0_CTL0 EQU 0x40201300
CPUSS_RAM1_CTL0 EQU 0x40201380
CPUSS_RAM2_CTL0 EQU 0x402013a0
;************************************************************************
;* Import symbols
;************************************************************************
EXTERN CM0P_CpuIntr2_Handler
EXTERN CM0P_CpuIntr3_Handler
EXTERN CM0P_CpuIntr4_Handler
EXTERN CM0P_CpuIntr5_Handler
EXTERN CM0P_CpuIntr6_Handler
EXTERN CM0P_CpuIntr7_Handler
EXTERN __iar_program_start
EXTERN __iar_data_init3
EXTERN __iar_dynamic_initialization
EXTERN SystemInit
EXTERN CyMain
;************************************************************************
;* Export symbols
;************************************************************************
PUBLIC __vector_table
PUBLIC __vector_table_0x1c
PUBLIC __Vectors
PUBLIC __Vectors_End
PUBLIC __Vectors_Size
PUBLIC __ramVectors
PUBLIC Cy_u32StartupStackStartAddress
PUBLIC Cy_u32StartupStackEndAddress
;************************************************************************
;* Vector Table and RAM Vector Table
;************************************************************************
SECTION CSTACK:DATA:NOROOT(3)
; align to 256 byte, because CM0_VECTOR_TABLE_BASE register only supports address bits [31:8] (Note: for VTOR a 128-byte alignment would be ok)
SECTION .intvec:CODE:ROOT(8)
DATA
__vector_table:
DCD sfe(CSTACK)
DCD Reset_Handler
DCD NMI_Handler
DCD HardFault_Handler
DCD 0
DCD 0
DCD 0
__vector_table_0x1c:
DCD 0
DCD 0
DCD 0
DCD 0
DCD SVC_Handler
DCD 0
DCD 0
DCD PendSV_Handler
DCD SysTick_Handler
; External interrupts PowerMode Description
DCD DefaultInt_Handler ; DeepSleep CPU User Interrupt #0 ; updated in RAM vector table with corresponding SROM vector table entry (after ROM-to-RAM copy)
DCD DefaultInt_Handler ; DeepSleep CPU User Interrupt #1 ; updated in RAM vector table with corresponding SROM vector table entry (after ROM-to-RAM copy)
DCD CM0P_CpuIntr2_Handler ; DeepSleep CPU User Interrupt #2
DCD CM0P_CpuIntr3_Handler ; DeepSleep CPU User Interrupt #3
DCD CM0P_CpuIntr4_Handler ; DeepSleep CPU User Interrupt #4
DCD CM0P_CpuIntr5_Handler ; DeepSleep CPU User Interrupt #5
DCD CM0P_CpuIntr6_Handler ; DeepSleep CPU User Interrupt #6
DCD CM0P_CpuIntr7_Handler ; DeepSleep CPU User Interrupt #7
; These IRQs can only be triggered by SW via NVIC regs
DCD CpuUserInt8_Handler ; Active CPU User Interrupt #8
DCD CpuUserInt9_Handler ; Active CPU User Interrupt #9
DCD CpuUserInt10_Handler ; Active CPU User Interrupt #10
DCD CpuUserInt11_Handler ; Active CPU User Interrupt #11
DCD CpuUserInt12_Handler ; Active CPU User Interrupt #12
DCD CpuUserInt13_Handler ; Active CPU User Interrupt #13
DCD CpuUserInt14_Handler ; Active CPU User Interrupt #14
DCD CpuUserInt15_Handler ; Active CPU User Interrupt #15
__Vectors_End:
__Vectors EQU __vector_table
__Vectors_Size EQU __Vectors_End - __Vectors
; use same alignment like vector table in ROM above (even though VTOR minimum requirement would be 128 bytes if not used in combination with CM0_VECTOR_TABLE_BASE register)
SECTION .intvec_ram:DATA:ROOT(8)
__ramVectors:
DS8 __Vectors_Size
;************************************************************************
;* Start-up Code
;************************************************************************
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler:
; Disable global interrupts
CPSID I
; Update Vector Table Offset Register with address of user ROM table
; (will be updated later to user RAM table address in C startup code)
LDR r0, =__vector_table
LDR r1, =VTOR
STR r0, [r1]
DSB
; CM0+ bus width is 32-bit, but SRAM is built with 64-bit based ECC on Traveo II parts with CM7 core
; Set CPUSS->RAMx_CTL0.ECC_CHECK_DIS bits to avoid causing unintentional ECC faults during startup while SRAM ECC has not been initialized yet
; Generic code can be used, even if RAMx_CTL0 (x > 0) registers are not implemented in a device
; or if no ECC_CHECK_DIS bits are available in the registers in case of m4cpuss with 32-bit ECC SRAM
MOVS r0, #1
LSLS r0, r0, #19
LDR r1, =CPUSS_RAM0_CTL0
LDR r2, [r1]
ORRS r2, r0
STR r2, [r1]
LDR r1, =CPUSS_RAM1_CTL0
LDR r2, [r1]
ORRS r2, r0
STR r2, [r1]
LDR r1, =CPUSS_RAM2_CTL0
LDR r2, [r1]
ORRS r2, r0
STR r2, [r1]
; Initialize ECC of startup stack (needed for local variables in C startup code) by processing 8 bytes per loop iteration,
; because the ECC initialization feature uses this generic granularity that will cover any memory (SRAM/TCM) in any TVII device
; Prerequisite: Stack Pointer (SP) has not been modified (from the vector table init value) by above code (otherwise code must be adapted)
MOVS r0, #0 ; clear value
MOVS r1, #0 ; clear value
LDR r2, Cy_u32StartupStackStartAddress
startup_stack_ecc_init_loop:
STM r2!, {r0, r1}
CMP r2, sp
BNE startup_stack_ecc_init_loop
; Call C startup code (no ANSI C context established yet!)
LDR r0, =SystemInit
BLX r0
LDR r0, =CyMain
BLX r0
; Note: Control flow does not necessarily return here.
; On some tool-chains (e.g. IAR) control flow will never return from
; the system library.
Cy_Main_Exited:
B Cy_Main_Exited
;************************************************************************
;* Literal pool
;************************************************************************
ALIGNROM 2
LTORG
DATA
ALIGNROM 2
STARTUP_STACK_SIZE_BYTES EQU (STARTUP_STACK_SIZE_DOUBLE_WORDS * 8) ; Multiplication does not work in below data definition directive, so an additional define is created
Cy_u32StartupStackStartAddress:
DCD (sfe(CSTACK) - STARTUP_STACK_SIZE_BYTES)
Cy_u32StartupStackEndAddress:
DCD (sfe(CSTACK) - 1)
;************************************************************************
;* Default and weak implementation of interrupt handlers
;************************************************************************
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
NMI_Handler:
B NMI_Handler
;-----------------------------------------
PUBWEAK Cy_SysLib_FaultHandler
SECTION .text:CODE:REORDER:NOROOT(2)
Cy_SysLib_FaultHandler:
B Cy_SysLib_FaultHandler
;-----------------------------------------
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
HardFault_Handler:
IMPORT Cy_SysLib_FaultHandler
MOVS r0, #4
MOV r1, lr
TST r0, r1
BEQ L_MSP
MRS r0, PSP
B L_API_call
L_MSP
MRS r0, MSP
L_API_call
; Storing LR content for Creator call stack trace
PUSH {lr}
LDR r1, =Cy_SysLib_FaultHandler
BLX r1
;-----------------------------------------
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
SVC_Handler:
B SVC_Handler
;-----------------------------------------
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
PendSV_Handler:
B PendSV_Handler
;-----------------------------------------
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
SysTick_Handler:
B SysTick_Handler
;-----------------------------------------
PUBWEAK DefaultInt_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
DefaultInt_Handler:
B DefaultInt_Handler
;-----------------------------------------
; External interrupts
; Traveo II CPU User Interrupts 0-7 handlers are defined in the project interrupt mapping file
; Traveo II CPU User Interrupts 8-15 can only be used as SW interrupts and need to be defined by user (weak implementation provided below)
PUBWEAK CpuUserInt8_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
CpuUserInt8_Handler:
B CpuUserInt8_Handler
;-----------------------------------------
PUBWEAK CpuUserInt9_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
CpuUserInt9_Handler:
B CpuUserInt9_Handler
;-----------------------------------------
PUBWEAK CpuUserInt10_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
CpuUserInt10_Handler:
B CpuUserInt10_Handler
;-----------------------------------------
PUBWEAK CpuUserInt11_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
CpuUserInt11_Handler:
B CpuUserInt11_Handler
;-----------------------------------------
PUBWEAK CpuUserInt12_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
CpuUserInt12_Handler:
B CpuUserInt12_Handler
;-----------------------------------------
PUBWEAK CpuUserInt13_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
CpuUserInt13_Handler:
B CpuUserInt13_Handler
;-----------------------------------------
PUBWEAK CpuUserInt14_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
CpuUserInt14_Handler:
B CpuUserInt14_Handler
;-----------------------------------------
PUBWEAK CpuUserInt15_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
CpuUserInt15_Handler:
B CpuUserInt15_Handler
;-----------------------------------------
;************************************************************************
;* File end
;************************************************************************
END

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bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM0P/system_cm0plus.c Normal file
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/***************************************************************************//**
* \file system_cm0plus.c
* \version 1.1
*
* The device system-source file.
*
********************************************************************************
* \copyright
* Copyright 2021-2024 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/*******************************************************************************
* Function Name: SystemInit
****************************************************************************//**
*
* Initializes the system:
* - Unlocks and disables WDT.
* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator.
* - Calls \ref SystemCoreClockUpdate().
*
*******************************************************************************/
#include <stdbool.h>
#include "cy_device.h"
#include "cy_device_headers.h"
#include "cy_syslib.h"
#include "cy_sysclk.h"
#include "cy_wdt.h"
#include "cmsis_compiler.h"
#define CY_SYS_CM7_PWR_CTL_KEY_OPEN (0x05FAUL)
#define CY_SYS_CM7_PWR_CTL_KEY_CLOSE (0xFA05UL)
void Cy_DefaultUserHandler(void);
static void CopyVectorTable(void);
static void InitMemoryEccClearArea(uint32_t u32StartAddr, uint32_t u32EndAddr);
static void InitMemoryEcc(void);
static void EnableEcc(void);
static void PrepareSystemCallInfrastructure(void);
#define DEFAULT_HANDLER_NAME Cy_DefaultUserHandler
CY_NOINIT cy_israddress Cy_SystemIrqUserTable[CPUSS_SYSTEM_INT_NR] ;
CY_NOINIT cy_israddress * Cy_SysInt_SystemIrqUserTableRamPointer ;
extern uint32_t Cy_u32StartupStackStartAddress;
extern uint32_t Cy_u32StartupStackEndAddress;
extern void * __Vectors;
extern void * __Vectors_Size;
extern cy_israddress __ramVectors[];
/*******************************************************************************
* SystemCoreClockUpdate()
*******************************************************************************/
/** Default HFClk frequency in Hz */
#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (8000000UL)
/** Default PeriClk frequency in Hz */
#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (8000000UL)
/** Default system core frequency in Hz */
#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (100000000UL)
/** Holds the CLK_SLOW(Cortex-M0+) or CLK_FAST0(Cortex-M7_0) or CLK_FAST(Cortex-M7_1) system core clock */
CY_NOINIT uint32_t SystemCoreClock ;
/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */
CY_NOINIT uint32_t cy_Hfclk0FreqHz ;
/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */
CY_NOINIT uint32_t cy_PeriClkFreqHz ;
/** Holds the AHB frequency. Updated by \ref SystemCoreClockUpdate(). */
CY_NOINIT uint32_t cy_AhbFreqHz ;
/*******************************************************************************
* SystemCoreClockUpdate (void)
*******************************************************************************/
/* Do not use these definitions directly in your application */
#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u)
#define CY_DELAY_1K_THRESHOLD (1000u)
#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u)
#define CY_DELAY_1M_THRESHOLD (1000000u)
#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u)
CY_NOINIT uint32_t cy_delayFreqHz ;
CY_NOINIT uint32_t cy_delayFreqKhz ;
CY_NOINIT uint32_t cy_delayFreqMhz ;
/*****************************************************************************
* Global variable definitions (declared in header file with 'extern')
*****************************************************************************/
// CAUTION: Static or global initialized and non-const variables will not have their init value yet!
#define SRAM_BEGIN_ADDR (BASE_SRAM_CM0P)
#define SRAM_END_ADDR (CY_SRAM_BASE + CY_SRAM_SIZE)
#define STARTUP_STACK_OFFSEST (0x100) /* 32 2-words are cleaned by startup */
#define ECC_INIT_WIDTH_BYTES 8
#define SROM_VECTOR_TABLE_BASE_ADDRESS 0x00000000
#define VECTOR_TABLE_OFFSET_IRQ0 0x40
#define VECTOR_TABLE_OFFSET_IRQ1 0x44
#if defined(__ARMCC_VERSION)
extern unsigned int Image$$ARM_LIB_STACK$$ZI$$Limit; /* for (default) One Region model */
extern void __main(void);
#elif defined (__GNUC__)
extern unsigned int __StackTop;
#elif defined (__ICCARM__)
extern unsigned int CSTACK$$Limit; /* for (default) One Region model */
#endif
/******************************************************************************/
/** Define an abstract type for the chosen ECC initialization granularity */
typedef uint64_t ecc_init_width_t;
/* Provide empty __WEAK implementation for the low-level initialization
routine required by the RTOS-enabled applications.
clib-support library provides FreeRTOS-specific implementation:
https://github.com/Infineon/clib-support */
void cy_toolchain_init(void);
__WEAK void cy_toolchain_init(void)
{
}
#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
/* GCC: newlib crt0 _start executes software_init_hook.
The cy_toolchain_init hook provided by clib-support library must execute
after static data initialization and before static constructors. */
void software_init_hook();
void software_init_hook()
{
cy_toolchain_init();
}
#elif defined(__ICCARM__)
/* Initialize data section */
void __iar_data_init3(void);
/* Call the constructors of all global objects */
void __iar_dynamic_initialization(void);
/* Define strong version to return zero for __iar_program_start
to skip data sections initialization (__iar_data_init3). */
int __low_level_init(void);
int __low_level_init(void)
{
return 0;
}
#else
/**/
#endif /* defined(__GNUC__) && !defined(__ARMCC_VERSION) */
void CyMain(void)
{
#if defined(__ICCARM__)
/* Initialize data section */
__iar_data_init3();
/* Initialization hook for RTOS environment */
cy_toolchain_init();
/* Call the constructors of all global objects */
__iar_dynamic_initialization();
#endif
__PROGRAM_START();
}
void SystemInit(void)
{
/* startup Init */
InitMemoryEcc();
EnableEcc();
CopyVectorTable();
PrepareSystemCallInfrastructure();
/* startup Init done */
Cy_PDL_Init(CY_DEVICE_CFG);
Cy_WDT_Unlock();
Cy_WDT_Disable();
Cy_SystemInit();
SystemCoreClockUpdate();
SystemIrqInit();
}
/*******************************************************************************
* Function Name: EnableEcc
****************************************************************************//**
*
* The function is called during device startup.
*
*******************************************************************************/
static void EnableEcc(void)
{
/* Enable ECC checking in SRAM controllers again (had been switched off by assembly startup code) */
CPUSS->RAM0_CTL0 &= ~(0x80000); /* set bit 19 to 0 */
#if (CPUSS_RAMC1_PRESENT == 1u)
CPUSS->RAM1_CTL0 &= ~(0x80000); /* set bit 19 to 0 */
#endif
#if (CPUSS_RAMC2_PRESENT == 1u)
CPUSS->RAM2_CTL0 &= ~(0x80000); /* set bit 19 to 0 */
#endif
}
/*******************************************************************************
* Function Name: InitMemoryEcc
****************************************************************************//**
*
* The function is called during device startup.
*
*******************************************************************************/
static void InitMemoryEcc(void)
{
uint32_t *sp = (uint32_t*)&__INITIAL_SP;
uint32_t u32StckLow = (uint32_t)sp - STARTUP_STACK_OFFSEST;
uint32_t u32StackHigh = (uint32_t)sp;
InitMemoryEccClearArea(SRAM_BEGIN_ADDR, u32StckLow);
InitMemoryEccClearArea(u32StackHigh, SRAM_END_ADDR);
}
/**
*****************************************************************************
** Clears an area by writing '0' using a pointer of type #ecc_init_width_t
**
** \param u32StartAddr Start address of area to be cleared,
** must be aligned to #ECC_INIT_WIDTH_BYTES
** \param u32EndAddr Last address within area to be cleared, (u32EndAddr+1)
** must be aligned to #ECC_INIT_WIDTH_BYTES
**
** \return none
*****************************************************************************/
static void InitMemoryEccClearArea(uint32_t u32StartAddr, uint32_t u32EndAddr)
{
volatile ecc_init_width_t * pRam = (volatile ecc_init_width_t *) u32StartAddr;
ecc_init_width_t Zero = 0;
for(; (uint32_t)pRam < u32EndAddr; pRam++)
{
// Note: Even if ecc_init_width_t is uint64_t, this will be compiled as two 32-bit accesses
// in case of CM0+, because there is no STRD instruction specified in ARMv6-M Thumb
*pRam = Zero;
}
}
/**
*****************************************************************************
** Copies the vector table from ROM to RAM and updates the VTOR (CMx vector
** table base register) accordingly
**
** \return none
*****************************************************************************/
static void CopyVectorTable(void)
{
const uint8_t numVectors = (uint8_t)((uint32_t)&__Vectors_Size / 4);
uint32_t * const ramTable = (uint32_t *)__ramVectors;
uint32_t * const romTable = (uint32_t *)(&__Vectors);
// Copy the vector table from ROM into RAM
for(uint8_t index = 0; index < numVectors; index++)
{
ramTable[index] = romTable[index];
}
// Update the ARM System Control Block vector table base address.
SCB->VTOR = (uint32_t)ramTable;
}
/**
*****************************************************************************
** Prepares necessary settings to get SROM system calls working
**
** \return none
*****************************************************************************/
static void PrepareSystemCallInfrastructure(void)
{
const uint8_t u8Irq0Index = (uint8_t) (VECTOR_TABLE_OFFSET_IRQ0 / 4);
const uint8_t u8Irq1Index = (uint8_t) (VECTOR_TABLE_OFFSET_IRQ1 / 4);
volatile uint32_t * const ramTable = (uint32_t *)__ramVectors;
volatile uint32_t * const sromTable = (uint32_t *)SROM_VECTOR_TABLE_BASE_ADDRESS;
// Use IRQ0 and IRQ1 handlers from SROM vector table
ramTable[u8Irq0Index] = sromTable[u8Irq0Index];
ramTable[u8Irq1Index] = sromTable[u8Irq1Index];
NVIC_SetPriority(NvicMux0_IRQn, 1);
NVIC_SetPriority(NvicMux1_IRQn, 0);
NVIC_EnableIRQ(NvicMux0_IRQn);
NVIC_EnableIRQ(NvicMux1_IRQn);
// Only item left is clearing of PRIMASK:
// This should be done by the application at a later point in time (e.g. in main())
}
/*******************************************************************************
* Function Name: SystemIrqInit
****************************************************************************//**
*
* The function is called during device startup.
*
*******************************************************************************/
void SystemIrqInit(void)
{
for (int i=0; i<(int)CPUSS_SYSTEM_INT_NR; i++)
{
Cy_SystemIrqUserTable[i] = DEFAULT_HANDLER_NAME;
}
Cy_SysInt_SystemIrqUserTableRamPointer = Cy_SystemIrqUserTable;
}
/*******************************************************************************
* Function Name: Cy_SystemInit
****************************************************************************//**
*
* The function is called during device startup.
*
*******************************************************************************/
__WEAK void Cy_SystemInit(void)
{
/* Empty weak function. The actual implementation to be in the app
* generated strong function.
*/
}
/*******************************************************************************
* Function Name: SystemCoreClockUpdate
****************************************************************************//**
*
* Gets core clock frequency and updates \ref SystemCoreClock.
*
* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref
* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles().
*
*******************************************************************************/
void SystemCoreClockUpdate (void)
{
/* Get frequency for the high-frequency clock*/
cy_Hfclk0FreqHz = Cy_SysClk_ClkHfGetFrequency(CY_SYSCLK_CLK_CORE_HF_PATH_NUM);
/* The CM0P core's clock source is the slow clock. */
SystemCoreClock = Cy_SysClk_ClkSlowGetFrequency();
/* Get Peripheral clock Frequency*/
cy_PeriClkFreqHz = Cy_SysClk_ClkHfGetFrequency(CY_SYSCLK_CLK_PERI_HF_PATH_NUM);
/* Sets clock frequency for Delay API */
cy_delayFreqHz = SystemCoreClock;
cy_delayFreqMhz = (uint32_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD);
cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD;
/* Get the frequency of AHB source, CLK HF0 is the source for AHB*/
cy_AhbFreqHz = Cy_SysClk_ClkHfGetFrequency(0UL);
}
uint32_t Cy_SysGetCM7Status(uint8_t core)
{
uint32_t regValue = 0u;
CY_ASSERT(core < CORE_MAX);
if(core == CORE_CM7_0)
{
/* Get current power mode */
regValue = _FLD2VAL(CPUSS_CM7_0_PWR_CTL_PWR_MODE, CPUSS->CM7_0_PWR_CTL);
}
else if(core == CORE_CM7_1)
{
/* Get current power mode */
regValue = _FLD2VAL(CPUSS_CM7_1_PWR_CTL_PWR_MODE, CPUSS->CM7_1_PWR_CTL);
}
else
{
/* */
}
return (regValue);
}
void Cy_SysEnableCM7(uint8_t core, uint32_t vectorTableOffset)
{
uint32_t cmStatus;
uint32_t interruptState;
uint32_t regValue;
CY_ASSERT(core < CORE_MAX);
interruptState = Cy_SaveIRQ();
cmStatus = Cy_SysGetCM7Status(core);
if(cmStatus == CY_SYS_CM7_STATUS_ENABLED)
{
// Set core into reset first, so that new settings can get effective
// This branch is e.g. entered if a debugger is connected that would power-up the CM7,
// but let it run in ROM boot or pause its execution by keeping CPU_WAIT bit set.
Cy_SysResetCM7(core);
}
// CLK_HF1, by default is disabled for use by CM7_0/1, hence enable
SRSS->CLK_ROOT_SELECT[1] |= SRSS_CLK_ROOT_SELECT_ENABLE_Msk;
if(core == CORE_CM7_0)
{
/* Adjust the vector address */
CPUSS->CM7_0_VECTOR_TABLE_BASE = vectorTableOffset;
/* Enable the Power Control Key */
regValue = CPUSS->CM7_0_PWR_CTL & ~(CPUSS_CM7_0_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM7_0_PWR_CTL_PWR_MODE_Msk);
regValue |= _VAL2FLD(CPUSS_CM7_0_PWR_CTL_VECTKEYSTAT, CY_SYS_CM7_PWR_CTL_KEY_OPEN);
regValue |= CY_SYS_CM7_STATUS_ENABLED;
CPUSS->CM7_0_PWR_CTL = regValue;
while((CPUSS->CM7_0_STATUS & CPUSS_CM7_0_STATUS_PWR_DONE_Msk) == 0UL)
{
/* Wait for the power mode to take effect */
}
CPUSS->CM7_0_CTL &= ~(0x1 << CPUSS_CM7_0_CTL_CPU_WAIT_Pos);
}
else if(core == CORE_CM7_1)
{
/* Adjust the vector address */
CPUSS->CM7_1_VECTOR_TABLE_BASE = vectorTableOffset;
/* Enable the Power Control Key */
regValue = CPUSS->CM7_1_PWR_CTL & ~(CPUSS_CM7_1_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM7_1_PWR_CTL_PWR_MODE_Msk);
regValue |= _VAL2FLD(CPUSS_CM7_1_PWR_CTL_VECTKEYSTAT, CY_SYS_CM7_PWR_CTL_KEY_OPEN);
regValue |= CY_SYS_CM7_STATUS_ENABLED;
CPUSS->CM7_1_PWR_CTL = regValue;
while((CPUSS->CM7_1_STATUS & CPUSS_CM7_1_STATUS_PWR_DONE_Msk) == 0UL)
{
/* Wait for the power mode to take effect */
}
CPUSS->CM7_1_CTL &= ~(0x1 << CPUSS_CM7_1_CTL_CPU_WAIT_Pos);
}
Cy_RestoreIRQ(interruptState);
}
void Cy_SysDisableCM7(uint8_t core)
{
uint32_t regValue;
CY_ASSERT(core < CORE_MAX);
if(core == CORE_CM7_0)
{
regValue = CPUSS->CM7_0_PWR_CTL & ~(CPUSS_CM7_0_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM7_0_PWR_CTL_PWR_MODE_Msk);
regValue |= _VAL2FLD(CPUSS_CM7_0_PWR_CTL_VECTKEYSTAT, CY_SYS_CM7_PWR_CTL_KEY_OPEN);
regValue |= CY_SYS_CM7_STATUS_DISABLED;
CPUSS->CM7_0_PWR_CTL = regValue;
while((CPUSS->CM7_0_STATUS & CPUSS_CM7_0_STATUS_PWR_DONE_Msk) == 0UL)
{
/* Wait for the power mode to take effect */
}
}
else if(core == CORE_CM7_1)
{
regValue = CPUSS->CM7_1_PWR_CTL & ~(CPUSS_CM7_1_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM7_1_PWR_CTL_PWR_MODE_Msk);
regValue |= _VAL2FLD(CPUSS_CM7_1_PWR_CTL_VECTKEYSTAT, CY_SYS_CM7_PWR_CTL_KEY_OPEN);
regValue |= CY_SYS_CM7_STATUS_DISABLED;
CPUSS->CM7_1_PWR_CTL = regValue;
while((CPUSS->CM7_1_STATUS & CPUSS_CM7_0_STATUS_PWR_DONE_Msk) == 0UL)
{
/* Wait for the power mode to take effect */
}
}
}
void Cy_SysRetainCM7(uint8_t core)
{
uint32_t cmStatus;
uint32_t interruptState;
uint32_t regValue;
interruptState = Cy_SaveIRQ();
cmStatus = Cy_SysGetCM7Status(core);
if(cmStatus == CY_SYS_CM7_STATUS_ENABLED)
{
if(core == CORE_CM7_0)
{
regValue = CPUSS->CM7_0_PWR_CTL & ~(CPUSS_CM7_0_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM7_0_PWR_CTL_PWR_MODE_Msk);
regValue |= _VAL2FLD(CPUSS_CM7_0_PWR_CTL_VECTKEYSTAT, CY_SYS_CM7_PWR_CTL_KEY_OPEN);
regValue |= CY_SYS_CM7_STATUS_RETAINED;
CPUSS->CM7_0_PWR_CTL = regValue;
}
else if(core == CORE_CM7_1)
{
regValue = CPUSS->CM7_1_PWR_CTL & ~(CPUSS_CM7_1_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM7_1_PWR_CTL_PWR_MODE_Msk);
regValue |= _VAL2FLD(CPUSS_CM7_1_PWR_CTL_VECTKEYSTAT, CY_SYS_CM7_PWR_CTL_KEY_OPEN);
regValue |= CY_SYS_CM7_STATUS_RETAINED;
CPUSS->CM7_1_PWR_CTL = regValue;
}
}
Cy_RestoreIRQ(interruptState);
}
void Cy_SysResetCM7(uint8_t core)
{
uint32_t regValue;
CY_ASSERT(core < CORE_MAX);
if(core == CORE_CM7_0)
{
regValue = CPUSS->CM7_0_PWR_CTL & ~(CPUSS_CM7_0_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM7_0_PWR_CTL_PWR_MODE_Msk);
regValue |= _VAL2FLD(CPUSS_CM7_0_PWR_CTL_VECTKEYSTAT, CY_SYS_CM7_PWR_CTL_KEY_OPEN);
regValue |= CY_SYS_CM7_STATUS_RESET;
CPUSS->CM7_0_PWR_CTL = regValue;
while((CPUSS->CM7_0_STATUS & CPUSS_CM7_0_STATUS_PWR_DONE_Msk) == 0UL)
{
/* Wait for the power mode to take effect */
}
}
else if(core == CORE_CM7_1)
{
regValue = CPUSS->CM7_1_PWR_CTL & ~(CPUSS_CM7_1_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM7_1_PWR_CTL_PWR_MODE_Msk);
regValue |= _VAL2FLD(CPUSS_CM7_1_PWR_CTL_VECTKEYSTAT, CY_SYS_CM7_PWR_CTL_KEY_OPEN);
regValue |= CY_SYS_CM7_STATUS_RESET;
CPUSS->CM7_1_PWR_CTL = regValue;
while((CPUSS->CM7_1_STATUS & CPUSS_CM7_1_STATUS_PWR_DONE_Msk) == 0UL)
{
/* Wait for the power mode to take effect */
}
}
}
/*******************************************************************************
* Function Name: Cy_DefaultUserHandler
****************************************************************************//**
*
* The Handler is called when the CPU attempts to call IRQ that has not been mapped to user functions.
*
*******************************************************************************/
void Cy_DefaultUserHandler(void)
{
// This IRQ occurred because CPU attempted to call IRQ that has not been mapped to user function
while(1);
}
/*******************************************************************************
* Function Name: CM0P_CpuIntr_HandlerInline
****************************************************************************//**
*
* The Inline handler for CPU interrupt.
* The system interrupt mapped to CPU interrupt will be fetched and executed
*
*******************************************************************************/
__STATIC_FORCEINLINE void CM0P_CpuIntr_HandlerInline(uint8_t intrNum)
{
uint32_t system_int_idx;
cy_israddress handler;
if (_FLD2VAL(CPUSS_CM0_INT0_STATUS_SYSTEM_INT_VALID, CPUSS_CM0_INT_STATUS_BASE[intrNum]))
{
system_int_idx = _FLD2VAL(CPUSS_CM0_INT0_STATUS_SYSTEM_INT_IDX, CPUSS_CM0_INT_STATUS_BASE[intrNum]);
handler = Cy_SystemIrqUserTable[system_int_idx];
if(handler != NULL)
handler(); // jump to system interrupt handler
}
else
{
// Triggered by software or because of software cleared a peripheral interrupt flag but did not clear the pending flag at NVIC
}
NVIC_ClearPendingIRQ((IRQn_Type)intrNum);
}
/*******************************************************************************
* Function Name: CpuIntr2_Handler
****************************************************************************//**
*
* The Handler is called when the CPU interrupt2 occurs.
*
*******************************************************************************/
void CM0P_CpuIntr2_Handler(void)
{
CM0P_CpuIntr_HandlerInline(2);
}
/*******************************************************************************
* Function Name: CpuIntr3_Handler
****************************************************************************//**
*
* The Handler is called when the CPU interrupt3 occurs.
*
*******************************************************************************/
void CM0P_CpuIntr3_Handler(void)
{
CM0P_CpuIntr_HandlerInline(3);
}
/*******************************************************************************
* Function Name: CpuIntr4_Handler
****************************************************************************//**
*
* The Handler is called when the CPU interrupt4 occurs.
*
*******************************************************************************/
void CM0P_CpuIntr4_Handler(void)
{
CM0P_CpuIntr_HandlerInline(4);
}
/*******************************************************************************
* Function Name: CpuIntr5_Handler
****************************************************************************//**
*
* The Handler is called when the CPU interrupt5 occurs.
*
*******************************************************************************/
void CM0P_CpuIntr5_Handler(void)
{
CM0P_CpuIntr_HandlerInline(5);
}
/*******************************************************************************
* Function Name: CpuIntr6_Handler
****************************************************************************//**
*
* The Handler is called when the CPU interrupt6 occurs.
*
*******************************************************************************/
void CM0P_CpuIntr6_Handler(void)
{
CM0P_CpuIntr_HandlerInline(6);
}
/*******************************************************************************
* Function Name: CpuIntr7_Handler
****************************************************************************//**
*
* The Handler is called when the CPU interrupt7 occurs.
*
*******************************************************************************/
void CM0P_CpuIntr7_Handler(void)
{
CM0P_CpuIntr_HandlerInline(7);
}

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bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM7/TOOLCHAIN_ARM/linker.sct Normal file
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#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m7
; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor.
;*******************************************************************************
;* \file xmc7100_x4160_cm7.sct
;* \version 1.0
;*
;* Linker file for the ARMCC.
;*
;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory
;* layout of the output file.
;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there.
;*
;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker
;* file.
;*
;*******************************************************************************
;* \copyright
;* Copyright 2016-2021 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0
;*
;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at
;*
;* http://www.apache.org/licenses/LICENSE-2.0
;*
;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and
;* limitations under the License.
;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM0+ core.
; You can change the memory allocation by editing the RAM and Flash defines.
; Your changes must be aligned with the corresponding defines for the CM7 core in 'xxx_cm7.sct',
; where 'xx' is the device group; for example, 'xmc7200d_x8384_cm7.sct'.
; RAM
#define SRAM_TOTAL_SIZE 0x000C0000 /* 768K: SRAM0 + SRAM1 */
; FLASH
#define CODE_FLASH_TOTAL_SIZE 0x00410000 /* 4160K: TOTAL FLASH SIZE */
#define SRAM_START_RESERVE 0
#define SRAM_PRIVATE_FOR_SROM 0x800 /* 2K Private SRAM for SROM (e.g. API processing). Reserved at the beginning */
#define STACK_SIZE 0x1000
#define RAMVECTORS_ALIGNMENT 128
; RAM
#define SRAM_BASE_ADDRESS 0x28000000 /* SRAM START */
#define CM0PLUS_SRAM_RESERVE 0x00004000 /* 16K : cm0 sram size */
#define CM7_0_SRAM_RESERVE 0x000BC000 /* 752K: cm7_0 sram size */
; FLASH
#define CODE_FLASH_BASE_ADDRESS 0x10000000 /* FLASH START */
#define CM0PLUS_CODE_FLASH_RESERVE 0x00080000 /* 512K : cm0 flash size */
#define CM7_0_CODE_FLASH_RESERVE 0x00390000 /* 3648K: cm7_0 flash size */
; SRAM reservations
#define BASE_SRAM_CM0P SRAM_BASE_ADDRESS + SRAM_START_RESERVE + SRAM_PRIVATE_FOR_SROM
#define SIZE_SRAM_CM0P CM0PLUS_SRAM_RESERVE - SRAM_START_RESERVE - SRAM_PRIVATE_FOR_SROM
#define BASE_SRAM_CM7_0 SRAM_BASE_ADDRESS + CM0PLUS_SRAM_RESERVE
#define SIZE_SRAM_CM7_0 CM7_0_SRAM_RESERVE
; Code flash reservations
#define BASE_CODE_FLASH_CM0P CODE_FLASH_BASE_ADDRESS
#define SIZE_CODE_FLASH_CM0P CM0PLUS_CODE_FLASH_RESERVE
#define BASE_CODE_FLASH_CM7_0 CODE_FLASH_BASE_ADDRESS + CM0PLUS_CODE_FLASH_RESERVE
#define SIZE_CODE_FLASH_CM7_0 CM7_0_CODE_FLASH_RESERVE
#define BASE_SRAM BASE_SRAM_CM7_0
#define SIZE_SRAM SIZE_SRAM_CM7_0
#define BASE_CODE_FLASH BASE_CODE_FLASH_CM7_0
#define SIZE_CODE_FLASH SIZE_CODE_FLASH_CM7_0
#ifdef _CORE_CM7_0_
; Cortex-M0+ application flash image area
LR_IROM BASE_CODE_FLASH_CM0P SIZE_CODE_FLASH_CM0P
{
.cy_m0p_image +0
{
* (.cy_m0p_image)
}
}
#endif
; Cortex-M7 application flash area
LR_IROM1 BASE_CODE_FLASH SIZE_CODE_FLASH
{
ER_FLASH_VECTORS +0
{
* (RESET, +FIRST)
}
ER_FLASH_CODE +0 FIXED
{
* (InRoot$$Sections)
* (+RO)
}
ER_RAM_VECTORS BASE_SRAM UNINIT
{
* (.bss.noinit.RESET_RAM, +FIRST)
}
RW_RAM_DATA +0
{
* (+RW, +ZI)
}
RW_RAM_SHARED_DATA +0 ALIGN 32
{
* (.cy_sharedmem)
}
; Place variables in the section that should not be initialized during the
; device startup.
RW_IRAM1 +0 UNINIT
{
* (.noinit)
* (.bss.noinit)
}
; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY BASE_SRAM+SIZE_SRAM-STACK_SIZE-AlignExpr(ImageLimit(RW_IRAM1), 8)
{
}
; Stack region growing down
ARM_LIB_STACK (BASE_SRAM+SIZE_SRAM) EMPTY -STACK_SIZE
{
}
}

439
bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM7/TOOLCHAIN_GCC_ARM/linker.ld Normal file
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/***************************************************************************//**
* \file xmc7100_x4160_cm7.ld
* \version 1.0.0
*
* Linker file for the GNU C compiler.
*
* The main purpose of the linker script is to describe how the sections in the
* input files should be mapped into the output file, and to control the memory
* layout of the output file.
*
* \note The entry point location is fixed and starts at 0x10000000. The valid
* application image should be placed there.
*
* \note The linker files included with the PDL template projects must be generic
* and handle all common use cases. Your project may not use every section
* defined in the linker files. In that case you may see warnings during the
* build process. In your project, you can simply comment out or remove the
* relevant code in the linker file.
*
********************************************************************************
* \copyright
* Copyright 2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
GROUP(-lgcc -lc -lnosys )
SEARCH_DIR(.)
GROUP(libgcc.a libc.a libm.a libnosys.a)
ENTRY(Reset_Handler)
/* The size of the stack section at the end of CM7 SRAM */
STACK_SIZE = 0x1000;
RAMVECTORS_ALIGNMENT = 128;
sram_start_reserve = 0;
sram_total_size = 0x000C0000; /* 768K: SRAM0 + SRAM1 */
sram_private_for_srom = 0x00000800; /* Private SRAM for SROM (e.g. API processing) */
sram_used_by_boot = 0x0; /* Used during boot by Cypress firmware (content will be overwritten on reset, so it should not be used for loadable sections in case of RAM build configurations) */
cm0plus_sram_reserve = 0x00004000; /* 16K : cm0 sram size */
cm7_0_sram_reserve = 0x000BC000; /* 752K : cm7_0 sram size */
code_flash_total_size = 0x00410000; /* 4160K: total flash size */
cm0plus_code_flash_reserve = 0x00080000; /* 512K : cm0 flash size */
cm7_0_code_flash_reserve = 0x00390000; /* 3648K: cm7_0 flash size */
code_flash_base_address = 0x10000000;
sram_base_address = 0x28000000;
/* SRAM reservations */
_base_SRAM_CM7_0 = sram_base_address + cm0plus_sram_reserve;
_size_SRAM_CM7_0 = cm7_0_sram_reserve;
/* Code flash reservations */
_base_CODE_FLASH_CM0P = code_flash_base_address;
_size_CODE_FLASH_CM0P = cm0plus_code_flash_reserve;
_base_CODE_FLASH_CM7_0 = code_flash_base_address + cm0plus_code_flash_reserve;
_size_CODE_FLASH_CM7_0 = cm7_0_code_flash_reserve;
/* Fixed Addresses */
_base_WORK_FLASH = 0x14000000;
_size_WORK_FLASH = 0x00040000; /* 256K Work flash */
_base_CM7_0_ITCM = 0x00000000;
_size_CM7_0_ITCM = 0x00004000;
_base_CM7_0_DTCM = 0x20000000;
_size_CM7_0_DTCM = 0x00004000;
/* For the non-dual cm7 device, _CORE_CM7_0_ should be defined and _CORE_CM7_1_ should not be defined */
_base_SRAM = _base_SRAM_CM7_0;
_size_SRAM = _size_SRAM_CM7_0;
_base_CODE_FLASH = _base_CODE_FLASH_CM7_0;
_size_CODE_FLASH = _size_CODE_FLASH_CM7_0;
_base_SFLASH_USER_DATA = 0x17000800;
_size_SFLASH_USER_DATA = 0x00000800;
_base_SFLASH_NAR = 0x17001A00;
_size_SFLASH_NAR = 0x00000200;
_base_SFLASH_PUB_KEY = 0x17006400;
_size_SFLASH_PUB_KEY = 0x00000C00;
_base_SFLASH_APP_PROT = 0x17007600;
_size_SFLASH_APP_PROT = 0x00000200;
_base_SFLASH_TOC2 = 0x17007C00;
_size_SFLASH_TOC2 = 0x00000200;
_base_XIP = 0x60000000;
_size_XIP = 0x08000000;
_base_EFUSE = 0x90700000;
_size_EFUSE = 0x00100000;
_base_ITCM = _base_CM7_0_ITCM;
_size_ITCM = _size_CM7_0_ITCM;
_base_DTCM = _base_CM7_0_DTCM;
_size_DTCM = _size_CM7_0_DTCM;
/* Force symbol to be entered in the output file as an undefined symbol. Doing
* this may, for example, trigger linking of additional modules from standard
* libraries. You may list several symbols for each EXTERN, and you may use
* EXTERN multiple times. This command has the same effect as the -u command-line
* option.
*/
EXTERN(Reset_Handler)
/* The MEMORY section below describes the location and size of blocks of memory in the target.
* Use this section to specify the memory regions available for allocation.
*/
MEMORY
{
/* The ram and flash regions control RAM and flash memory allocation for the CM7_0/CM7_1 core. */
ram (rxw) : ORIGIN = _base_SRAM, LENGTH = _size_SRAM /* SRAM */
flash_cm0p (rx) : ORIGIN = _base_CODE_FLASH_CM0P, LENGTH = _size_CODE_FLASH_CM0P /* CODE flash CM0+ */
flash (rx) : ORIGIN = _base_CODE_FLASH, LENGTH = _size_CODE_FLASH /* CODE flash CM7_0/1 */
/* This is a 256K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
* You can assign sections to this memory region for only one of the cores.
*/
em_eeprom (rw) : ORIGIN = _base_WORK_FLASH, LENGTH = _size_WORK_FLASH /* WORK flash */
/* The following regions define device specific memory regions and must not be changed. */
sflash_user_data (rx) : ORIGIN = _base_SFLASH_USER_DATA, LENGTH = _size_SFLASH_USER_DATA /* Supervisory flash: User data */
sflash_nar (rx) : ORIGIN = _base_SFLASH_NAR, LENGTH = _size_SFLASH_NAR /* Supervisory flash: Normal Access Restrictions (NAR) */
sflash_public_key (rx) : ORIGIN = _base_SFLASH_PUB_KEY, LENGTH = _size_SFLASH_PUB_KEY /* Supervisory flash: Public Key */
sflash_app_prot (rx) : ORIGIN = _base_SFLASH_APP_PROT, LENGTH = _size_SFLASH_APP_PROT
sflash_toc_2 (rx) : ORIGIN = _base_SFLASH_TOC2, LENGTH = _size_SFLASH_TOC2 /* Supervisory flash: Table of Content # 2 */
xip (rx) : ORIGIN = _base_XIP, LENGTH = _size_XIP /* XIP: 128 MB */
efuse (rx) : ORIGIN = _base_EFUSE, LENGTH = _size_EFUSE /* 1MB */
itcm (rx) : ORIGIN = _base_ITCM, LENGTH = _size_ITCM /* ITCM */
dtcm (rx) : ORIGIN = _base_DTCM, LENGTH = _base_DTCM /* DTCM */
}
/* Library configurations */
GROUP(libgcc.a libc.a libm.a libnosys.a)
SECTIONS
{
/* Cortex-M0+ application flash image area. Comment this section if you don't want to include CM0+ image */
.cy_cm0p_image ORIGIN(flash_cm0p):
{
. = ALIGN(4);
__cy_m0p_code_start = . ;
KEEP(*(.cy_m0p_image))
__cy_m0p_code_end = . ;
} > flash_cm0p
/* Check if .cy_m0p_image size exceeds cm0plus_code_flash_reserve */
ASSERT(__cy_m0p_code_end < ORIGIN(flash), "CM0+ flash image overflows with CM7, increase CM7 base address ")
/* Cortex-M7 application flash area */
.text ORIGIN(flash) :
{
/* Cortex-M7 flash vector table */
. = ALIGN(4);
__Vectors = . ;
KEEP(*(.vectors))
. = ALIGN(4);
__Vectors_End = .;
__Vectors_Size = __Vectors_End - __Vectors;
__end__ = .;
. = ALIGN(4);
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
/* Read-only code (constants). */
*(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
KEEP(*(.eh_frame*))
} > flash
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > flash
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > flash
__exidx_end = .;
.copy.table :
{
. = ALIGN(4);
__copy_table_start__ = .;
/* Copy data section to RAM */
LONG (__etext) /* From */
LONG (__data_start__) /* To */
LONG ((__data_end__ - __data_start__)/4) /* Size */
/* Copy code to ITCM */
LONG (__zero_table_end__) /* From */
LONG (__itcm_start__) /* To */
LONG ((__itcm_end__ - __itcm_start__)/4) /* Size */
/* Copy data to DTCM */
LONG (__itcm_flash_end__) /* From */
LONG (__dtcm_start__) /* To */
LONG ((__dtcm_end__ - __dtcm_start__)/4) /* Size */
__copy_table_end__ = .;
} > flash
.zero.table :
{
. = ALIGN(4);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG ((__bss_end__ - __bss_start__)/4)
__zero_table_end__ = .;
} > flash
/* itcm */
.cy_itcm ORIGIN(itcm):
{
__itcm_start__ = .;
KEEP(*(.cy_itcm))
__itcm_end__ = .;
} > itcm AT>flash
__itcm_flash_end__ = __zero_table_end__ + (__itcm_end__ - __itcm_start__);
/* dtcm */
.cy_dtcm ORIGIN(dtcm):
{
__dtcm_start__ = .;
KEEP(*(.cy_dtcm))
__dtcm_end__ = .;
} > dtcm AT>flash
__etext = __itcm_flash_end__ + (__dtcm_end__ - __dtcm_start__) ;
.ramVectors (NOLOAD) :
{
. = ALIGN(RAMVECTORS_ALIGNMENT);
__ram_vectors_start__ = .;
KEEP(*(.ram_vectors))
__ram_vectors_end__ = .;
} > ram
.data __ram_vectors_end__ :
{
. = ALIGN(4);
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
KEEP(*(.cy_ramfunc*))
. = ALIGN(32);
KEEP(*(cy_sharedmem*))
. = ALIGN(4);
__data_end__ = .;
} > ram AT>flash
/* Place variables in the section that should not be initialized during the
* device startup.
*/
.noinit (NOLOAD) : ALIGN(8)
{
KEEP(*(.noinit))
} > ram
/* The uninitialized global or static variables are placed in this section.
*
* The NOLOAD attribute tells linker that .bss section does not consume
* any space in the image. The NOLOAD attribute changes the .bss type to
* NOBITS, and that makes linker to A) not allocate section in memory, and
* A) put information to clear the section with all zeros during application
* loading.
*
* Without the NOLOAD attribute, the .bss section might get PROGBITS type.
* This makes linker to A) allocate zeroed section in memory, and B) copy
* this section to RAM during application loading.
*/
.bss (NOLOAD):
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > ram
.heap (NOLOAD):
{
__HeapBase = .;
__end__ = .;
end = __end__;
KEEP(*(.heap*))
. = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
__HeapLimit = .;
} > ram
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (NOLOAD):
{
KEEP(*(.stack*))
} > ram
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(ram) + LENGTH(ram);
__StackLimit = __StackTop - STACK_SIZE;
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
/* Emulated EEPROM Flash area */
.cy_em_eeprom :
{
KEEP(*(.cy_em_eeprom))
} > em_eeprom
/* Supervisory Flash: User data */
.cy_sflash_user_data :
{
KEEP(*(.cy_sflash_user_data))
} > sflash_user_data
/* Supervisory Flash: Normal Access Restrictions (NAR) */
.cy_sflash_nar :
{
KEEP(*(.cy_sflash_nar))
} > sflash_nar
/* Supervisory Flash: Public Key */
.cy_sflash_public_key :
{
KEEP(*(.cy_sflash_public_key))
} > sflash_public_key
/* Supervisory Flash: Table of Content # 2 */
.cy_toc_part2 :
{
KEEP(*(.cy_toc_part2))
} > sflash_toc_2
/* Places the code in the Execute in Place (XIP) section. See the smif driver
* documentation for details.
*/
cy_xip :
{
__cy_xip_start = .;
KEEP(*(.cy_xip))
__cy_xip_end = .;
} > xip
/* eFuse */
.cy_efuse :
{
KEEP(*(.cy_efuse))
} > efuse
}
/*============================================================
* Symbols for use by application
*============================================================
*/
__ecc_init_sram_start_address = ORIGIN(ram);
__ecc_init_sram_end_address = ORIGIN(ram) + LENGTH(ram);
/* EOF */

187
bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM7/TOOLCHAIN_IAR/linker.icf Normal file
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/*******************************************************************************
* \file xmc7100_x4160_cm7.icf
* \version 1.0.0
*
* Linker file for the IAR compiler.
*
* The main purpose of the linker script is to describe how the sections in the
* input files should be mapped into the output file, and to control the memory
* layout of the output file.
*
* \note The entry point is fixed and starts at 0x10000000. The valid application
* image should be placed there.
*
* \note The linker files included with the PDL template projects must be generic
* and handle all common use cases. Your project may not use every section
* defined in the linker files. In that case you may see warnings during the
* build process. In your project, you can simply comment out or remove the
* relevant code in the linker file.
*
********************************************************************************
* \copyright
* Copyright 2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
define symbol sram_start_reserve = 0;
define symbol sram_total_size = 0x000C0000; /* 768K: SRAM0 + SRAM1 */
define symbol sram_private_for_srom = 0x00000800; /* Private SRAM for SROM (e.g. API processing) */
define symbol sram_used_by_boot = 0x0; /* Used during boot by Cypress firmware (content will be overwritten on reset, so it should not be used for loadable sections in case of RAM build configurations) */
define symbol cm0plus_sram_reserve = 0x00004000; /* 16K : cm0 sram size */
define symbol cm7_0_sram_reserve = 0x000BC000; /* 752K : cm7_0 sram size */
define symbol code_flash_total_size = 0x00410000; /* 4160K: total flash size */
define symbol cm0plus_code_flash_reserve = 0x00080000; /* 512K : cm0 flash size */
define symbol cm7_0_code_flash_reserve = 0x00390000; /* 3648K: cm7_0 flash size */
define symbol code_flash_base_address = 0x10000000;
define symbol sram_base_address = 0x28000000;
define symbol ecc_init_width = 8; /* Most restrictive native ECC width of all "normal" memories (SRAM, DTCM, ITCM) in any Traveo II derivate is used to keep the code generic */
define symbol cm7_heap_reserve = 0x00001000;
define symbol cm7_stack_reserve = 0x00001000;
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/* The symbols below define the location and size of blocks of memory in the target.
* Use these symbols to specify the memory regions available for allocation.
*/
/* The following symbols control RAM and flash memory allocation for the CM7 cores.
* You can change the memory allocation by editing RAM and Flash values.
* Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf',
* where 'xx' is the device group; for example, 'xmc7100d_x4160_cm0plus.icf'.
* any changes here must also be aligned in file 'xmc7xxx_partition.h'.
* after which cm0p core aplication must be build and flashed again.
*/
/* RAM */
define symbol __ICFEDIT_region_IRAM1_start__ = 0x28004000; //_base_SRAM_CM7_0 = sram_base_address + cm0plus_sram_reserve;
define symbol __ICFEDIT_region_IRAM1_end__ = 0x280BFFFF; //_size_SRAM_CM7_0 = cm7_0_sram_reserve;
define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
define symbol __ICFEDIT_region_IRAM2_end__ = 0x0;
/* Flash */
define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000; //_base_CODE_FLASH_CM7_0 = code_flash_base_address + cm0plus_code_flash_reserve
define symbol __ICFEDIT_region_IROM1_end__ = 0x1040FFFF; //_size_CODE_FLASH_CM7_0 = cm7_0_code_flash_reserve
define symbol __ICFEDIT_region_IROM2_start__ = 0x0;
define symbol __ICFEDIT_region_IROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
define symbol __ICFEDIT_region_EROM1_end__ = 0x0;
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x00001000; //cm7_stack_reserve
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
define symbol __ICFEDIT_size_heap__ = 0x00001000; //cm7_heap_reserve
/**** End of ICF editor section. ###ICF###*/
define symbol heap_reserve = __ICFEDIT_size_heap__;
define symbol stack_reserve = (__ICFEDIT_size_cstack__ + (ecc_init_width - 1)) & (~((ecc_init_width - 1))); /* Ensure that stack size is an integer multiple of ECC init width (round up) */
/* SRAM reservations */
define symbol _base_SRAM_CM7_0 = __ICFEDIT_region_IRAM1_start__;
define symbol _size_SRAM_CM7_0 = __ICFEDIT_region_IRAM1_end__ - __ICFEDIT_region_IRAM1_start__ + 1;
/* Code flash reservations */
define symbol _base_CODE_FLASH_CM0P = code_flash_base_address;
define symbol _size_CODE_FLASH_CM0P = cm0plus_code_flash_reserve;
define symbol _base_CODE_FLASH_CM7_0 = __ICFEDIT_region_IROM1_start__;
define symbol _size_CODE_FLASH_CM7_0 = __ICFEDIT_region_IROM1_end__ - __ICFEDIT_region_IROM1_start__ + 1;
define symbol _base_SRAM = _base_SRAM_CM7_0;
define symbol _size_SRAM = _size_SRAM_CM7_0;
define symbol _base_CODE_FLASH = _base_CODE_FLASH_CM7_0;
define symbol _size_CODE_FLASH = _size_CODE_FLASH_CM7_0;
/*============================================================
* Memory definitions
*============================================================
*/
define memory mem with size = 4G;
define region SRAM = mem:[from _base_SRAM size _size_SRAM ];
define region CODE_FLASH = mem:[from _base_CODE_FLASH size _size_CODE_FLASH ];
/*============================================================
* Block definitions
*============================================================
*/
define block CSTACK with alignment = 8, size = stack_reserve { };
define block HEAP with expanding size, alignment = 8, minimum size = heap_reserve { };
define block HEAP_STACK { block HEAP, last block CSTACK };
define block CM0P_RO with size = (_size_CODE_FLASH_CM0P) { readonly section .cy_m0p_image };
define block CY_SHAREDMEM with alignment = 32 { section .cy_sharedmem };
/*============================================================
* Initialization
*============================================================
*/
initialize by copy { readwrite };
do not initialize { section .noinit, section .intvec_ram };
/*============================================================
* Placement
*============================================================
*/
/* Flash - Cortex-M0+ application image */
place at address (_base_CODE_FLASH_CM0P) { block CM0P_RO };
/* Link location specific assignment of 'readonly' type sections to either SRAM or CODE_FLASH */
/* Note: .intvec must be the first section in ROM in order for __cm7_vector_base_linker_symbol to be correctly calculated! */
place at start of CODE_FLASH { section .intvec };
place in CODE_FLASH { readonly };
place in SRAM { readwrite };
place in SRAM { block CY_SHAREDMEM };
place at end of SRAM { block HEAP_STACK };
keep { section .intvec };
keep { section .cy_m0p_image };
/* Following definitions ensure that SRAM will not be touched at all by startup ECC initialization when code is linked to SRAM,
* use debugger script to initialize the SRAM before downloading the application or adjust below symbols to not include
* the area of SRAM where "ROM type" sections are linked to
*/
define exported symbol __ecc_init_sram_start_address = start(SRAM);
define exported symbol __ecc_init_sram_end_address = end(SRAM);
/* EOF */

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/***************************************************************************//**
* \file startup_cm7.c
* \version 1.0
*
* The device system-source file.
*
********************************************************************************
* \copyright
* Copyright 2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include "cy_syslib.h"
#include "cmsis_compiler.h"
#include "startup_cat1c.h"
#include "core_cm7.h"
#include "system_cat1c.h"
#if defined(__cplusplus)
extern "C" {
#endif
extern void CM7_CpuIntr_Handler(uint8_t intrNum);
void Reset_Handler(void);
/* Internal Reference */
void Default_Handler(void);
void Default_NMIException_Handler(void);
void Default_Fault_Handler(void);
void SysLib_FaultHandler(uint32_t const *faultStackAddr);
__WEAK void cy_toolchain_init(void);
void FpuEnable(void);
#if defined(__ARMCC_VERSION)
extern unsigned int Image$$ARM_LIB_STACK$$ZI$$Limit;
interrupt_type extern void __main(void);
cy_israddress __ramVectors[VECTORTABLE_SIZE] __attribute__( ( section(".bss.noinit.RESET_RAM"))) __attribute__((aligned(VECTORTABLE_ALIGN)));
#elif defined (__GNUC__)
extern unsigned int __StackTop;
extern uint32_t __StackLimit;
cy_israddress __ramVectors[VECTORTABLE_SIZE] __attribute__( ( section(".ram_vectors"))) __attribute__((aligned(VECTORTABLE_ALIGN)));
#elif defined (__ICCARM__)
extern unsigned int CSTACK$$Limit;
interrupt_type extern void __cmain();
cy_israddress __ramVectors[VECTORTABLE_SIZE] __attribute__( ( section(".intvec_ram"))) __attribute__((aligned(VECTORTABLE_ALIGN)));
#else
#error "An unsupported toolchain"
#endif /* (__ARMCC_VERSION) */
/* SCB->CPACR */
#define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u)
/*******************************************************************************
* Function Name: FpuEnable
****************************************************************************//**
*
* Enables the FPU if it is used. The function is called from the startup file.
*
*******************************************************************************/
void FpuEnable(void)
{
#if defined (__FPU_USED) && (__FPU_USED == 1U)
uint32_t interruptState;
interruptState = Cy_SaveIRQ();
SCB->CPACR |= SCB_CPACR_CP10_CP11_ENABLE;
__DSB();
__ISB();
Cy_RestoreIRQ(interruptState);
#endif /* (__FPU_USED) && (__FPU_USED == 1U) */
}
void SysLib_FaultHandler(uint32_t const *faultStackAddr)
{
Cy_SysLib_FaultHandler(faultStackAddr);
}
/* Exception Vector Table & Handlers */
/*----------------------------------------------------------------*/
void Default_NMIException_Handler(void)
{
__asm volatile(
"bkpt #10\n"
"B .\n"
);
}
void Default_Fault_Handler(void)
{
__asm (
"MRS R0, CONTROL\n"
"TST R0, #2\n"
"ITE EQ\n"
"MRSEQ R0, MSP\n"
"MRSNE R0, PSP\n"
"B SysLib_FaultHandler\n"
);
}
/*----------------------------------------------------------------------------
Default Handler for Exceptions / Interrupts
*----------------------------------------------------------------------------*/
void Default_Handler(void)
{
while(1);
}
/*******************************************************************************
* Function Name: Default_CM7_CpuIntr0_Handler
****************************************************************************//**
*
* The Handler is called when the CPU interrupt0 occurs.
*
*******************************************************************************/
CY_SECTION_ITCM_BEGIN
void Default_CpuIntr0_Handler(void)
{
CM7_CpuIntr_Handler(0);
}
CY_SECTION_ITCM_END
/*******************************************************************************
* Function Name: Default_CM7_CpuIntr1_Handler
****************************************************************************//**
*
* The Handler is called when the CPU interrupt1 occurs.
*
*******************************************************************************/
CY_SECTION_ITCM_BEGIN
void Default_CpuIntr1_Handler(void)
{
CM7_CpuIntr_Handler(1);
}
CY_SECTION_ITCM_END
/*******************************************************************************
* Function Name: Default_CM7_CpuIntr2_Handler
****************************************************************************//**
*
* The Handler is called when the CPU interrupt2 occurs.
*
*******************************************************************************/
CY_SECTION_ITCM_BEGIN
void Default_CpuIntr2_Handler(void)
{
CM7_CpuIntr_Handler(2);
}
CY_SECTION_ITCM_END
/*******************************************************************************
* Function Name: Default_CM7_CpuIntr3_Handler
****************************************************************************//**
*
* The Handler is called when the CPU interrupt3 occurs.
*
*******************************************************************************/
CY_SECTION_ITCM_BEGIN
void Default_CpuIntr3_Handler(void)
{
CM7_CpuIntr_Handler(3);
}
CY_SECTION_ITCM_END
/*******************************************************************************
* Function Name: Default_CM7_CpuIntr4_Handler
****************************************************************************//**
*
* The Handler is called when the CPU interrupt4 occurs.
*
*******************************************************************************/
CY_SECTION_ITCM_BEGIN
void Default_CpuIntr4_Handler(void)
{
CM7_CpuIntr_Handler(4);
}
CY_SECTION_ITCM_END
/*******************************************************************************
* Function Name: Default_CM7_CpuIntr5_Handler
****************************************************************************//**
*
* The Handler is called when the CPU interrupt5 occurs.
*
*******************************************************************************/
CY_SECTION_ITCM_BEGIN
void Default_CpuIntr5_Handler(void)
{
CM7_CpuIntr_Handler(5);
}
CY_SECTION_ITCM_END
/*******************************************************************************
* Function Name: Default_CM7_CpuIntr6_Handler
****************************************************************************//**
*
* The Handler is called when the CPU interrupt6 occurs.
*
*******************************************************************************/
CY_SECTION_ITCM_BEGIN
void Default_CpuIntr6_Handler(void)
{
CM7_CpuIntr_Handler(6);
}
CY_SECTION_ITCM_END
/*******************************************************************************
* Function Name: Default_CM7_CpuIntr7_Handler
****************************************************************************//**
*
* The Handler is called when the CPU interrupt7 occurs.
*
*******************************************************************************/
CY_SECTION_ITCM_BEGIN
void Default_CpuIntr7_Handler(void)
{
CM7_CpuIntr_Handler(7);
}
CY_SECTION_ITCM_END
void NMIException_Handler (void) __attribute__ ((weak, alias("Default_NMIException_Handler")));
void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Fault_Handler")));
void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Fault_Handler")));
void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Fault_Handler")));
void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Fault_Handler")));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void CM7_CpuIntr0_Handler (void) __attribute__ ((weak, alias("Default_CpuIntr0_Handler")));
void CM7_CpuIntr1_Handler (void) __attribute__ ((weak, alias("Default_CpuIntr1_Handler")));
void CM7_CpuIntr2_Handler (void) __attribute__ ((weak, alias("Default_CpuIntr2_Handler")));
void CM7_CpuIntr3_Handler (void) __attribute__ ((weak, alias("Default_CpuIntr3_Handler")));
void CM7_CpuIntr4_Handler (void) __attribute__ ((weak, alias("Default_CpuIntr4_Handler")));
void CM7_CpuIntr5_Handler (void) __attribute__ ((weak, alias("Default_CpuIntr5_Handler")));
void CM7_CpuIntr6_Handler (void) __attribute__ ((weak, alias("Default_CpuIntr6_Handler")));
void CM7_CpuIntr7_Handler (void) __attribute__ ((weak, alias("Default_CpuIntr7_Handler")));
extern const cy_israddress __Vectors[VECTORTABLE_SIZE];
#if defined (__GNUC__)
_Pragma("GCC diagnostic push")
_Pragma("GCC diagnostic ignored \"-Wpedantic\"")
#endif /* __GNUC__ */
const cy_israddress __Vectors[VECTORTABLE_SIZE] __VECTOR_TABLE_ATTRIBUTE = {
(cy_israddress)&__INITIAL_SP,
(cy_israddress)Reset_Handler, /* initial PC/Reset */
(cy_israddress)NMIException_Handler, /* NMI */
(cy_israddress)HardFault_Handler, /* Hard Fault*/
(cy_israddress)MemManage_Handler, /* Memory Manage Fault */
(cy_israddress)BusFault_Handler, /* Bus Fault */
(cy_israddress)UsageFault_Handler, /* Usage Fault */
0, /* RESERVED */
0, /* RESERVED */
0, /* RESERVED */
0, /* RESERVED */
(cy_israddress)SVC_Handler, /* SVC */
(cy_israddress)DebugMon_Handler, /* debug */
0, /* RESERVED */
(cy_israddress)PendSV_Handler, /* Pend SV */
(cy_israddress)SysTick_Handler, /* systick */
/* External interrupts */
(cy_israddress)CM7_CpuIntr0_Handler,
(cy_israddress)CM7_CpuIntr1_Handler,
(cy_israddress)CM7_CpuIntr2_Handler,
(cy_israddress)CM7_CpuIntr3_Handler,
(cy_israddress)CM7_CpuIntr4_Handler,
(cy_israddress)CM7_CpuIntr5_Handler,
(cy_israddress)CM7_CpuIntr6_Handler,
(cy_israddress)CM7_CpuIntr7_Handler,
/* Internal interrupts */
(cy_israddress)Default_Handler,
(cy_israddress)Default_Handler,
(cy_israddress)Default_Handler,
(cy_israddress)Default_Handler,
(cy_israddress)Default_Handler,
(cy_israddress)Default_Handler,
(cy_israddress)Default_Handler,
(cy_israddress)Default_Handler
};
#if defined (__GNUC__)
_Pragma("GCC diagnostic pop")
#endif /* __GNUC__ */
/* Provide empty __WEAK implementation for the low-level initialization
routine required by the RTOS-enabled applications.
clib-support library provides FreeRTOS-specific implementation:
https://github.com/Infineon/clib-support */
void cy_toolchain_init(void);
__WEAK void cy_toolchain_init(void)
{
}
#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
/* GCC: newlib crt0 _start executes software_init_hook.
The cy_toolchain_init hook provided by clib-support library must execute
after static data initialization and before static constructors. */
void software_init_hook();
void software_init_hook()
{
cy_toolchain_init();
}
#elif defined(__ICCARM__)
/* Initialize data section */
void __iar_data_init3(void);
/* Call the constructors of all global objects */
void __iar_dynamic_initialization(void);
/* Define strong version to return zero for __iar_program_start
to skip data sections initialization (__iar_data_init3). */
int __low_level_init(void);
int __low_level_init(void)
{
return 0;
}
#else
/**/
#endif /* defined(__GNUC__) && !defined(__ARMCC_VERSION) */
// Reset Handler
void Reset_Handler(void)
{
/* disable global interrupt */
__disable_irq();
/* Allow write access to Vector Table Offset Register and ITCM/DTCM configuration register
* (CPUSS_CM7_X_CTL.PPB_LOCK[3] and CPUSS_CM7_X_CTL.PPB_LOCK[1:0]) */
#ifdef CORE_NAME_CM7_1
CPUSS->CM7_1_CTL &= ~(0xB);
#elif CORE_NAME_CM7_0
CPUSS->CM7_0_CTL &= ~(0xB);
#else
#error "Not valid"
#endif
__DSB();
__ISB();
/* Enable ITCM and DTCM */
SCB->ITCMCR = SCB->ITCMCR | 0x7; /* Set ITCMCR.EN, .RMW and .RETEN fields */
SCB->DTCMCR = SCB->DTCMCR | 0x7; /* Set DTCMCR.EN, .RMW and .RETEN fields */
#ifdef CORE_NAME_CM7_0
CPUSS_CM7_0_CTL |= (0x1 << CPUSS_CM7_0_CTL_INIT_TCM_EN_Pos);
CPUSS_CM7_0_CTL |= (0x2 << CPUSS_CM7_0_CTL_INIT_TCM_EN_Pos);
CPUSS_CM7_0_CTL |= (0x1 << CPUSS_CM7_0_CTL_INIT_RMW_EN_Pos);
CPUSS_CM7_0_CTL |= (0x2 << CPUSS_CM7_0_CTL_INIT_RMW_EN_Pos);
#elif CORE_NAME_CM7_1
CPUSS_CM7_1_CTL |= (0x1 << CPUSS_CM7_1_CTL_INIT_TCM_EN_Pos);
CPUSS_CM7_1_CTL |= (0x2 << CPUSS_CM7_1_CTL_INIT_TCM_EN_Pos);
CPUSS_CM7_1_CTL |= (0x1 << CPUSS_CM7_1_CTL_INIT_RMW_EN_Pos);
CPUSS_CM7_1_CTL |= (0x2 << CPUSS_CM7_1_CTL_INIT_RMW_EN_Pos);
#else
/**/
#endif
// ITCMCR EN/RMW/RETEN enabled to access ITCM
__UNALIGNED_UINT32_WRITE(((void const *)0xE000EF90), 0x2F);
// DTCMCR EN/RMW/RETEN enabled to access DTCM
__UNALIGNED_UINT32_WRITE(((void const *)0xE000EF94), 0x2F);
/* Enable FPU if present */
FpuEnable();
/* copy vector table */
for (uint32_t count = 0; count < VECTORTABLE_SIZE; count++)
{
__ramVectors[count] =__Vectors[count];
}
SCB->VTOR = (uint32_t)__ramVectors;
__DSB();
__ISB();
#ifdef ENABLE_CM7_INSTRUCTION_CACHE
SCB_EnableICache();
#endif /* ENABLE_CM7_INSTRUCTION_CACHE */
#ifdef ENABLE_CM7_DATA_CACHE
SCB_EnableDCache();
#else
// Ensure that the undefined valid bits in the cache RAM are set to invalid if cache is disabled, because the application
// may call further cache maintenance functions (e.g. SCB_CleanInvalidateDCache) independent of the "cache enabled" state.
SCB_InvalidateDCache();
#endif /* ENABLE_CM7_DATA_CACHE */
SystemInit();
#if defined(__ICCARM__)
/* Initialize data section */
__iar_data_init3();
/* Initialization hook for RTOS environment */
cy_toolchain_init();
/* Call the constructors of all global objects */
__iar_dynamic_initialization();
#endif
/* c-runtime */
__PROGRAM_START();
}
#if defined(__cplusplus)
}
#endif
/* [] END OF FILE */

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/***************************************************************************//**
* \file system_cm7.c
* \version 1.2
*
* The device system-source file.
*
********************************************************************************
* \copyright
* Copyright 2021-2024 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include <stdbool.h>
#include "cy_device.h"
#include "cy_device_headers.h"
#include "cy_syslib.h"
#include "cy_sysclk.h"
#include "cy_wdt.h"
void Cy_DefaultUserHandler(void);
#define DEFAULT_HANDLER_NAME Cy_DefaultUserHandler
CY_NOINIT cy_israddress Cy_SystemIrqUserTable[CPUSS_SYSTEM_INT_NR] ;
CY_NOINIT cy_israddress * Cy_SysInt_SystemIrqUserTableRamPointer ;
/*******************************************************************************
* SystemCoreClockUpdate()
*******************************************************************************/
/** Default HFClk frequency in Hz */
#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (8000000UL)
/** Default PeriClk frequency in Hz */
#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (8000000UL)
/** Default system core frequency in Hz */
#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL)
/** Holds the CLK_SLOW(Cortex-M0+) or CLK_FAST0(Cortex-M7_0) or CLK_FAST(Cortex-M7_1) system core clock */
CY_NOINIT uint32_t SystemCoreClock ;
/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). Note that the HfClk0 does not source any CPU core directly. */
CY_NOINIT uint32_t cy_Hfclk0FreqHz ;
/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */
CY_NOINIT uint32_t cy_PeriClkFreqHz ;
/** Holds the AHB frequency. Updated by \ref SystemCoreClockUpdate(). */
CY_NOINIT uint32_t cy_AhbFreqHz ;
/*******************************************************************************
* SystemCoreClockUpdate (void)
*******************************************************************************/
/* Do not use these definitions directly in your application */
#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u)
#define CY_DELAY_1K_THRESHOLD (1000u)
#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u)
#define CY_DELAY_1M_THRESHOLD (1000000u)
#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u)
CY_NOINIT uint32_t cy_delayFreqHz ;
CY_NOINIT uint32_t cy_delayFreqKhz ;
CY_NOINIT uint32_t cy_delayFreqMhz ;
/*******************************************************************************
* Function Name: SystemInit
****************************************************************************//**
* \cond
* Initializes the system:
* - Unlocks and disables WDT.
* - Calls the Cy_SystemInit() function.
* - Calls \ref SystemCoreClockUpdate().
* \endcond
*******************************************************************************/
void SystemInit(void)
{
/* if CM0+ is not enabled then unlock and disable WDT */
#ifdef __CM0P_PRESENT
#if (__CM0P_PRESENT == 0)
/* Release reset for all groups IP except group 0 */
(void)Cy_SysClk_PeriGroupSetSlaveCtl(1, CY_SYSCLK_PERI_GROUP_SL_CTL, 0xFFFFU); /* Suppress a compiler warning about unused return value */
(void)Cy_SysClk_PeriGroupSetSlaveCtl(2, CY_SYSCLK_PERI_GROUP_SL_CTL, 0xFFFFU); /* Suppress a compiler warning about unused return value */
(void)Cy_SysClk_PeriGroupSetSlaveCtl(3, CY_SYSCLK_PERI_GROUP_SL_CTL, 0xFFFFU); /* Suppress a compiler warning about unused return value */
(void)Cy_SysClk_PeriGroupSetSlaveCtl(4, CY_SYSCLK_PERI_GROUP_SL_CTL, 0xFFFFU); /* Suppress a compiler warning about unused return value */
(void)Cy_SysClk_PeriGroupSetSlaveCtl(5, CY_SYSCLK_PERI_GROUP_SL_CTL, 0xFFFFU); /* Suppress a compiler warning about unused return value */
(void)Cy_SysClk_PeriGroupSetSlaveCtl(6, CY_SYSCLK_PERI_GROUP_SL_CTL, 0xFFFFU); /* Suppress a compiler warning about unused return value */
(void)Cy_SysClk_PeriGroupSetSlaveCtl(8, CY_SYSCLK_PERI_GROUP_SL_CTL, 0xFFFFU); /* Suppress a compiler warning about unused return value */
(void)Cy_SysClk_PeriGroupSetSlaveCtl(9, CY_SYSCLK_PERI_GROUP_SL_CTL, 0xFFFFU); /* Suppress a compiler warning about unused return value */
/* Unlock and disable WDT */
Cy_WDT_Unlock();
Cy_WDT_Disable();
#endif /* (__CM0P_PRESENT == 0) */
#endif /* __CM0P_PRESENT */
Cy_SystemInit();
SystemCoreClockUpdate();
SystemIrqInit();
}
/*******************************************************************************
* Function Name: SystemIrqInit
****************************************************************************//**
*
* The function is called during device startup.
*
*******************************************************************************/
void SystemIrqInit(void)
{
for (int i=0; i<(int)CPUSS_SYSTEM_INT_NR; i++)
{
Cy_SystemIrqUserTable[i] = DEFAULT_HANDLER_NAME;
}
Cy_SysInt_SystemIrqUserTableRamPointer = Cy_SystemIrqUserTable;
}
/*******************************************************************************
* Function Name: Cy_SystemInit
****************************************************************************//**
*
* The function is called during device startup.
*
*******************************************************************************/
__WEAK void Cy_SystemInit(void)
{
/* Empty weak function. The actual implementation to be in the user application
* as strong function.
*/
}
/*******************************************************************************
* Function Name: SystemCoreClockUpdate
****************************************************************************//**
*
* Gets core clock frequency and updates \ref SystemCoreClock, \ref
* cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz.
*
* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref
* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles().
*
*******************************************************************************/
void SystemCoreClockUpdate (void)
{
/* Get frequency for the fast clock source of the core we are currently building for. */
#if defined (CORE_NAME_CM7_0) && (CORE_NAME_CM7_0 == 1)
SystemCoreClock = Cy_SysClk_ClkFastSrcGetFrequency(0);
#else
SystemCoreClock = Cy_SysClk_ClkFastSrcGetFrequency(1);
#endif
/* This is part of the clock tree for the CM0+; do not use for CM7 clock calculations. */
cy_Hfclk0FreqHz = Cy_SysClk_ClkHfGetFrequency(CY_SYSCLK_CLK_CORE_HF_PATH_NUM);
/* Get frequency for the high-frequency clock # 2 , which is used for PERI PCLK. */
cy_PeriClkFreqHz = Cy_SysClk_ClkHfGetFrequency(CY_SYSCLK_CLK_PERI_HF_PATH_NUM);
/* Sets clock frequency for Delay API */
cy_delayFreqHz = SystemCoreClock;
cy_delayFreqMhz = (uint32_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD);
cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD;
/* Get the frequency of AHB source, CLK HF0 is the source for AHB*/
cy_AhbFreqHz = Cy_SysClk_ClkHfGetFrequency(0UL);
}
/*******************************************************************************
* Function Name: Cy_DefaultUserHandler
****************************************************************************//**
*
*The Handler is called when the CPU attempts to call IRQ that has not been mapped to user functions.
*
*
*******************************************************************************/
void Cy_DefaultUserHandler(void)
{
// This IRQ occurred because CPU attempted to call IRQ that has not been mapped to user function
while(1);
}
/*******************************************************************************
* Function Name: CM7_CpuIntr_Handler
****************************************************************************//**
*
* The Inline handler for CPU interrupt.
* The system interrupt mapped to CPU interrupt will be fetched and executed
*
*******************************************************************************/
CY_SECTION_ITCM_BEGIN
void CM7_CpuIntr_Handler(uint8_t intrNum)
{
uint32_t system_int_idx;
cy_israddress handler;
#ifdef CORE_NAME_CM7_0
if((_FLD2VAL(CPUSS_CM7_0_INT_STATUS_SYSTEM_INT_VALID, CPUSS_CM7_0_INT_STATUS[intrNum])))
{
system_int_idx = _FLD2VAL(CPUSS_CM7_0_INT_STATUS_SYSTEM_INT_IDX, CPUSS_CM7_0_INT_STATUS[intrNum]);
handler = Cy_SystemIrqUserTable[system_int_idx];
handler(); // jump to system interrupt handler
}
#endif
#ifdef CORE_NAME_CM7_1
if((_FLD2VAL(CPUSS_CM7_1_INT_STATUS_SYSTEM_INT_VALID, CPUSS_CM7_1_INT_STATUS[intrNum])))
{
system_int_idx = _FLD2VAL(CPUSS_CM7_1_INT_STATUS_SYSTEM_INT_IDX, CPUSS_CM7_1_INT_STATUS[intrNum]);
handler = Cy_SystemIrqUserTable[system_int_idx];
handler(); // jump to system interrupt handler
}
#endif
NVIC_ClearPendingIRQ((IRQn_Type)intrNum);
}
CY_SECTION_ITCM_END

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CYPRESS (AN INFINEON COMPANY) END USER LICENSE AGREEMENT
PLEASE READ THIS END USER LICENSE AGREEMENT ("Agreement") CAREFULLY BEFORE
DOWNLOADING, INSTALLING, COPYING, OR USING THIS SOFTWARE AND ACCOMPANYING
DOCUMENTATION. BY DOWNLOADING, INSTALLING, COPYING OR USING THE SOFTWARE,
YOU ARE AGREEING TO BE BOUND BY THIS AGREEMENT. IF YOU DO NOT AGREE TO ALL
OF THE TERMS OF THIS AGREEMENT, PROMPTLY RETURN AND DO NOT USE THE SOFTWARE.
IF YOU HAVE PURCHASED THIS LICENSE TO THE SOFTWARE, YOUR RIGHT TO RETURN THE
SOFTWARE EXPIRES 30 DAYS AFTER YOUR PURCHASE AND APPLIES ONLY TO THE ORIGINAL
PURCHASER.
1. Definitions.
"Software" means this software and any accompanying documentation,
including any upgrades, updates, bug fixes or modified versions provided
to you by Cypress.
"Source Code" means software in human-readable form.
"Binary Code" means the software in binary code form such as object code or
an executable.
"Development Tools" means software that is intended to be installed on a
personal computer and used to create programming code for Firmware,
Drivers, or Host Applications. Examples of Development Tools are
Cypress's PSoC Creator software, Cypress's AIROC SDKs, and Cypress's
ModusToolbox software.
"Firmware" means software that executes on a Cypress hardware product.
"Driver" means software that enables the use of a Cypress hardware product
on a particular host operating system such as GNU/Linux, Windows, MacOS,
Android, and iOS.
"Host Application" means software that executes on a device other than a
Cypress hardware product in order to program, control, or communicate
with a Cypress hardware product.
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# KIT_XMC71_EVK_LITE_V2 BSP
## Overview
The KIT_XMC71_EVK_LITE_V2, a 100-pin evaluation board is based on the XMC7100 family of devices. XMC7100 MCU is designed for industrial applications. The evaluation board carries a XMC7100D microcontroller,and headers compatible with Arduino for interfacing Arduino shields. In addition, the board features an on-board programmer/debugger (KitProg3), a 512-Mbit QSPI NOR flash, CAN FD transceiver, Ethernet PHY transceiver with RJ45 connector interface, a Shield2Go connector interface and MikroBUS connector interface, two user LEDs, one potentiometer, and two push buttons. The board supports operating voltages from 3.3 V to 5.0 V for XMC7100D device.
**Note:**
KIT_XMC71_EVK_LITE_V2 is the board support package for the XMC7100 Lite Evaluation board with XMC7100D-F100K4160 MCU. Replace the XMC7100D-F176K4160 (default device) on the XMC7100 Lite Evaluation board with XMC7100D-F100K4160 to use this BSP.
To use code from the BSP, simply include a reference to `cybsp.h`.
## Features
### Kit Features:
* XMC7100D-F100K4160 8MB Flash 100-pin TEQFP device
* Programming interface (Arm® Standard JTAG, Cortex® Debug + ETM with Arm® ETM Mictor)
* Reset control with manual reset switch and voltage supervision
* CAN FD interface
* Ethernet interface
* One 512-Mbit external Quad SPI NOR Flash that provides a fast, expandable memory for data and code
* KitProg3 on-board SWD programmer/debugger, USB-UART and USB-I2C bridge functionality
* A Shield2Go connector interface and a MikroBUS connector interface
* Selectable input supply voltages of 3.3 V and 5.0 V for the XMC7100D device
* Two user LEDs, two user buttons, and a reset button for the XMC7100D device
* A potentiometer which can be used to simulate analog sensor output
* A mode button and a mode LED for KitProg3
### Kit Contents:
* XMC7100 evaluation board
* USB Type-A to Micro-B cable
* Quick start guide (printed on the kit package)
## BSP Configuration
The BSP has a few hooks that allow its behavior to be configured. Some of these items are enabled by default while others must be explicitly enabled. Items enabled by default are specified in the KIT_XMC71_EVK_LITE_V2.mk file. The items that are enabled can be changed by creating a custom BSP or by editing the application makefile.
Components:
* Device specific category reference (e.g.: CAT1) - This component, enabled by default, pulls in any device specific code for this board.
Defines:
* CYBSP_WIFI_CAPABLE - This define, disabled by default, causes the BSP to initialize the interface to an onboard wireless chip if it has one.
* CY_USING_HAL - This define, enabled by default, specifies that the HAL is intended to be used by the application. This will cause the BSP to include the applicable header file and to initialize the system level drivers.
* CYBSP_CUSTOM_SYSCLK_PM_CALLBACK - This define, disabled by default, causes the BSP to skip registering its default SysClk Power Management callback, if any, and instead to invoke the application-defined function `cybsp_register_custom_sysclk_pm_callback` to register an application-specific callback.
### Clock Configuration
| Clock | Source | Output Frequency |
|----------|-----------|------------------|
| FLL | ECO | 100.0 MHz |
| PLL | ECO | 200.0 MHz |
| CLK_HF0 | CLK_PATH0 | 100 MHz |
| CLK_HF1 | CLK_PATH1 | 250 MHz |
| CLK_HF2 | CLK_PATH4 | 100 MHz |
| CLK_HF3 | CLK_PATH4 | 100 MHz |
| CLK_HF4 | CLK_PATH4 | 50 MHz |
| CLK_HF5 | CLK_PATH2 | 125 MHz |
| CLK_HF6 | CLK_PATH4 | 200 MHz |
| CLK_HF7 | CLK_PATH5 | 0 MHz |
### Power Configuration
* System Idle Power Mode: Deep Sleep
* VDDA Voltage: 3300 mV
* VDDD Voltage: 3300 mV
See the [BSP Setttings][settings] for additional board specific configuration settings.
## API Reference Manual
The KIT_XMC71_EVK_LITE_V2 Board Support Package provides a set of APIs to configure, initialize and use the board resources.
See the [BSP API Reference Manual][api] for the complete list of the provided interfaces.
## More information
* [KIT_XMC71_EVK_LITE_V2 BSP API Reference Manual][api]
* [KIT_XMC71_EVK_LITE_V2 Documentation](https://www.infineon.com/KIT_XMC71_EVK_LITE_V1)
* [Cypress Semiconductor, an Infineon Technologies Company](http://www.cypress.com)
* [Infineon GitHub](https://github.com/infineon)
* [ModusToolbox™](https://www.cypress.com/products/modustoolbox-software-environment)
[api]: https://infineon.github.io/TARGET_KIT_XMC71_EVK_LITE_V2/html/modules.html
[settings]: https://infineon.github.io/TARGET_KIT_XMC71_EVK_LITE_V2/html/md_bsp_settings.html
---
© Cypress Semiconductor Corporation (an Infineon company) or an affiliate of Cypress Semiconductor Corporation, 2019-2024.

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# KIT_XMC71_EVK_LITE_V2 BSP Release Notes
The KIT_XMC71_EVK_LITE_V2, a 100-pin evaluation board is based on the XMC7100 family of devices. XMC7100 MCU is designed for industrial applications. The evaluation board carries a XMC7100D microcontroller,and headers compatible with Arduino for interfacing Arduino shields. In addition, the board features an on-board programmer/debugger (KitProg3), a 512-Mbit QSPI NOR flash, CAN FD transceiver, Ethernet PHY transceiver with RJ45 connector interface, a Shield2Go connector interface and MikroBUS connector interface, two user LEDs, one potentiometer, and two push buttons. The board supports operating voltages from 3.3 V to 5.0 V for XMC7100D device.
**Note:**
KIT_XMC71_EVK_LITE_V2 is the board support package for the XMC7100 Lite Evaluation board with XMC7100D-F100K4160 MCU. Replace the XMC7100D-F176K4160 (default device) on the XMC7100 Lite Evaluation board with XMC7100D-F100K4160 to use this BSP.
NOTE: BSPs are versioned by family. This means that version 1.2.0 of any BSP in a family (eg: XMC™ ) will have the same software maturity level. However, not all updates are necessarily applicable for each BSP in the family so not all version numbers will exist for each board. Additionally, new BSPs may not start at version 1.0.0. In the event of adding a common feature across all BSPs, the libraries are assigned the same version number. For example if BSP_A is at v1.3.0 and BSP_B is at v1.2.0, the event will trigger a version update to v1.4.0 for both BSP_A and BSP_B. This allows the common feature to be tracked in a consistent way.
### What's Included?
The KIT_XMC71_EVK_LITE_V2 library includes the following:
* BSP specific makefile to configure the build process for the board
* cybsp.c/h files to initialize the board and any system peripherals
* cybsp_types.h file describing basic board setup
* Linker script & startup code for GCC and ARM toolchains
* Configurator design files (and generated code) to setup board specific peripherals
* .lib file references for all dependent libraries
* API documentation
### What Changed?
#### v2.3.0
* Updated linker scripts and startup code to align with mtb-pdl-cat1 v3.14.0
* Added bt-fw-mur-cyw43439 as a dependency for KIT_XMC72_EVK_MUR_43439M2
#### v2.2.0
* Added the BSP for KIT_T2G_C-2D-6M_LITE
#### v2.1.0
* Updated the KIT_XMC72_EVK, KIT_XMC72_EVK_MUR_43439M2, KIT_XMC71_EVK_LITE_V1 and KIT_XMC71_EVK_LITE_V2 BSPs to use ECO as main clock source
#### v2.0.2
* Updated the BSP description for KIT_XMC71_EVK_LITE_V1 and KIT_XMC71_EVK_LITE_V2 BSPs
#### v2.0.1
* Updated the description in README file for KIT_XMC72_EVK and KIT_XMC72_EVK_MUR_43439M2 BSPs
#### v2.0.0
* Fixed issue where CM0P prebuilt image would enable both CM7 cores on devices which contain
two CM7 cores, even for single core applications.
* Updated default clock divider selections to better align with frequency limitations documented
in the datasheet.
##### Known issues:
Issue: Wifi companion radio connection may fail when the board is programmed using `make program`
Workaround: Program the board using an IDE launch config.
#### v1.2.1
* Updated the description in README file for KIT_XMC72_EVK and KIT_XMC72_EVK_MUR_43439M2 BSPs
#### v1.2.0
* Updated linker scripts and startup code to align with mtb-pdl-cat1 v3.4.0
* Added functionality to enable BSP Assistant chip flow
* Added capabilities to match BSPS created by BSP Assistant chip flow
#### v1.1.0
* Add macro `CYBSP_USER_BTN_DRIVE` indicating the drive mode that should be used for user buttons
#### v1.0.0
Note: This revision is only compatible with ModusToolbox Tools 3.0 and newer.
* Initial production release
### Supported Software and Tools
This version of the KIT_XMC71_EVK_LITE_V2 BSP was validated for compatibility with the following Software and Tools:
| Software and Tools | Version |
| :--- | :----: |
| ModusToolbox™ Software Environment | 3.2.0 |
| GCC Compiler | 11.3.1 |
| IAR Compiler | 9.50.2 |
| ARM Compiler | 6.22 |
Minimum required ModusToolbox™ Software Environment: v3.0.0
### More information
* [KIT_XMC71_EVK_LITE_V2 BSP API Reference Manual][api]
* [KIT_XMC71_EVK_LITE_V2 Documentation](https://www.infineon.com/KIT_XMC71_EVK_LITE_V1)
* [Cypress Semiconductor, an Infineon Technologies Company](http://www.cypress.com)
* [Infineon GitHub](https://github.com/infineon)
* [ModusToolbox™](https://www.cypress.com/products/modustoolbox-software-environment)
[api]: https://infineon.github.io/TARGET_KIT_XMC71_EVK_LITE_V2/html/modules.html
---
© Cypress Semiconductor Corporation (an Infineon company) or an affiliate of Cypress Semiconductor Corporation, 2019-2024.

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<version>1.0.0.103</version>

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cycfg_clocks.c
cycfg_clocks.h
cycfg_notices.h
cycfg_peripherals.h
cycfg_pins.c
cycfg_pins.h
cycfg_routing.c
cycfg_routing.h
cycfg_system.c
cycfg_system.h

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bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/CAT1C_SMIF.FLM Normal file
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/*******************************************************************************
* File Name: cycfg.c
*
* Description:
* Simple wrapper containing all generated files and function to initialize
* all generated code.
* This file was automatically generated and should not be modified.
* Configurator Backend 3.50.0
* device-db 4.22.0.7873
* mtb-pdl-cat1 3.15.0.40227
*
*******************************************************************************
* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
******************************************************************************/
#include "cycfg.h"
/* This function is provided for compatibility with older 2.X style projects. */
void init_cycfg_all(void)
{
cycfg_config_init();
cycfg_config_reservations();
}
void cycfg_config_init(void)
{
init_cycfg_system();
init_cycfg_clocks();
init_cycfg_routing();
init_cycfg_pins();
}
void cycfg_config_reservations(void)
{
reserve_cycfg_system();
reserve_cycfg_clocks();
reserve_cycfg_pins();
}

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/*******************************************************************************
* File Name: cycfg.h
*
* Description:
* Simple wrapper containing all generated files and function to initialize
* all generated code.
* This file was automatically generated and should not be modified.
* Configurator Backend 3.50.0
* device-db 4.22.0.7873
* mtb-pdl-cat1 3.15.0.40227
*
*******************************************************************************
* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
******************************************************************************/
#if !defined(CYCFG_H)
#define CYCFG_H
#include "cycfg_notices.h"
#include "cycfg_system.h"
#include "cycfg_clocks.h"
#include "cycfg_routing.h"
#include "cycfg_peripherals.h"
#include "cycfg_pins.h"
#if defined(__cplusplus)
extern "C" {
#endif /* defined(__cplusplus) */
void init_cycfg_all(void);
void cycfg_config_init(void);
void cycfg_config_reservations(void);
#if defined(__cplusplus)
}
#endif /* defined(__cplusplus) */
#endif /* CYCFG_H */

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/*******************************************************************************
* File Name: cycfg.timestamp
*
* Description:
* Sentinel file for determining if generated source is up to date.
* This file was automatically generated and should not be modified.
* Configurator Backend 3.50.0
* device-db 4.22.0.7873
* mtb-pdl-cat1 3.15.0.40227
*
*******************************************************************************
* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
******************************************************************************/

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/*******************************************************************************
* File Name: cycfg_clocks.c
*
* Description:
* Clock configuration
* This file was automatically generated and should not be modified.
* Configurator Backend 3.50.0
* device-db 4.22.0.7873
* mtb-pdl-cat1 3.15.0.40227
*
*******************************************************************************
* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
******************************************************************************/
#include "cycfg_clocks.h"
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_TRACE_CLK_DIV2_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = CYBSP_TRACE_CLK_DIV2_HW,
.channel_num = CYBSP_TRACE_CLK_DIV2_NUM,
};
const cyhal_resource_inst_t peri_0_group_1_div_8_0_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = peri_0_group_1_div_8_0_HW,
.channel_num = peri_0_group_1_div_8_0_NUM,
};
const cyhal_resource_inst_t peri_0_group_1_div_8_1_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = peri_0_group_1_div_8_1_HW,
.channel_num = peri_0_group_1_div_8_1_NUM,
};
const cyhal_resource_inst_t peri_0_group_1_div_8_2_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = peri_0_group_1_div_8_2_HW,
.channel_num = peri_0_group_1_div_8_2_NUM,
};
const cyhal_resource_inst_t peri_0_group_1_div_8_3_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = peri_0_group_1_div_8_3_HW,
.channel_num = peri_0_group_1_div_8_3_NUM,
};
const cyhal_resource_inst_t peri_0_group_1_div_8_4_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = peri_0_group_1_div_8_4_HW,
.channel_num = peri_0_group_1_div_8_4_NUM,
};
const cyhal_resource_inst_t peri_0_group_1_div_8_5_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = peri_0_group_1_div_8_5_HW,
.channel_num = peri_0_group_1_div_8_5_NUM,
};
const cyhal_resource_inst_t peri_0_group_1_div_8_6_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = peri_0_group_1_div_8_6_HW,
.channel_num = peri_0_group_1_div_8_6_NUM,
};
const cyhal_resource_inst_t peri_0_group_1_div_8_7_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = peri_0_group_1_div_8_7_HW,
.channel_num = peri_0_group_1_div_8_7_NUM,
};
#endif /* defined (CY_USING_HAL) */
void init_cycfg_clocks(void)
{
Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)CYBSP_TRACE_CLK_DIV2_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 2U);
Cy_SysClk_PeriPclkSetDivider((en_clk_dst_t)CYBSP_TRACE_CLK_DIV2_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 2U, 0U);
Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)CYBSP_TRACE_CLK_DIV2_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 2U);
Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_0_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 0U);
Cy_SysClk_PeriPclkSetDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_0_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 0U, 108U);
Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_0_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 0U);
Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_1_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 1U);
Cy_SysClk_PeriPclkSetDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_1_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 1U, 0U);
Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_1_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 1U);
Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_2_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 2U);
Cy_SysClk_PeriPclkSetDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_2_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 2U, 0U);
Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_2_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 2U);
Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_3_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 3U);
Cy_SysClk_PeriPclkSetDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_3_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 3U, 0U);
Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_3_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 3U);
Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_4_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 4U);
Cy_SysClk_PeriPclkSetDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_4_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 4U, 0U);
Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_4_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 4U);
Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_5_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 5U);
Cy_SysClk_PeriPclkSetDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_5_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 5U, 0U);
Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_5_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 5U);
Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_6_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 6U);
Cy_SysClk_PeriPclkSetDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_6_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 6U, 0U);
Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_6_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 6U);
Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_7_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 7U);
Cy_SysClk_PeriPclkSetDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_7_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 7U, 108U);
Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_7_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 7U);
}
void reserve_cycfg_clocks(void)
{
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_TRACE_CLK_DIV2_obj);
cyhal_hwmgr_reserve(&peri_0_group_1_div_8_0_obj);
cyhal_hwmgr_reserve(&peri_0_group_1_div_8_1_obj);
cyhal_hwmgr_reserve(&peri_0_group_1_div_8_2_obj);
cyhal_hwmgr_reserve(&peri_0_group_1_div_8_3_obj);
cyhal_hwmgr_reserve(&peri_0_group_1_div_8_4_obj);
cyhal_hwmgr_reserve(&peri_0_group_1_div_8_5_obj);
cyhal_hwmgr_reserve(&peri_0_group_1_div_8_6_obj);
cyhal_hwmgr_reserve(&peri_0_group_1_div_8_7_obj);
#endif /* defined (CY_USING_HAL) */
}

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/*******************************************************************************
* File Name: cycfg_clocks.h
*
* Description:
* Clock configuration
* This file was automatically generated and should not be modified.
* Configurator Backend 3.50.0
* device-db 4.22.0.7873
* mtb-pdl-cat1 3.15.0.40227
*
*******************************************************************************
* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
******************************************************************************/
#if !defined(CYCFG_CLOCKS_H)
#define CYCFG_CLOCKS_H
#include "cycfg_notices.h"
#include "cy_sysclk.h"
#if defined (CY_USING_HAL)
#include "cyhal_hwmgr.h"
#endif /* defined (CY_USING_HAL) */
#if defined(__cplusplus)
extern "C" {
#endif /* defined(__cplusplus) */
#define CYBSP_TRACE_CLK_DIV2_ENABLED 1U
#if defined (CY_USING_HAL) || defined (CY_USING_HAL_LITE)
#define CYBSP_TRACE_CLK_DIV2_HW CYHAL_CLOCK_BLOCK_PERIPHERAL0_8BIT
#endif /* defined (CY_USING_HAL) || defined (CY_USING_HAL_LITE) */
#if !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE)
#define CYBSP_TRACE_CLK_DIV2_HW CY_SYSCLK_DIV_8_BIT
#endif /* !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE) */
#define CYBSP_TRACE_CLK_DIV2_NUM 2U
#define CYBSP_TRACE_CLK_DIV2_GRP_NUM ((0U << PERI_PCLK_GR_NUM_Pos) | (0U << PERI_PCLK_INST_NUM_Pos))
#if !defined (CYBSP_TRACE_CLK_DIV2_GRP_NUM)
#define CYBSP_TRACE_CLK_DIV2_GRP_NUM CYBSP_TRACE_CLK_DIV2_GRP_NUM
#endif /* !defined (CYBSP_TRACE_CLK_DIV2_GRP_NUM) */
#define peri_0_group_1_div_8_0_ENABLED 1U
#if defined (CY_USING_HAL) || defined (CY_USING_HAL_LITE)
#define peri_0_group_1_div_8_0_HW CYHAL_CLOCK_BLOCK_PERIPHERAL1_8BIT
#endif /* defined (CY_USING_HAL) || defined (CY_USING_HAL_LITE) */
#if !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE)
#define peri_0_group_1_div_8_0_HW CY_SYSCLK_DIV_8_BIT
#endif /* !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE) */
#define peri_0_group_1_div_8_0_NUM 0U
#define PERI_0_GROUP_1_DIV_8_0_GRP_NUM ((1U << PERI_PCLK_GR_NUM_Pos) | (0U << PERI_PCLK_INST_NUM_Pos))
#if !defined (peri_0_group_1_div_8_0_GRP_NUM)
#define peri_0_group_1_div_8_0_GRP_NUM PERI_0_GROUP_1_DIV_8_0_GRP_NUM
#endif /* !defined (peri_0_group_1_div_8_0_GRP_NUM) */
#define peri_0_group_1_div_8_1_ENABLED 1U
#if defined (CY_USING_HAL) || defined (CY_USING_HAL_LITE)
#define peri_0_group_1_div_8_1_HW CYHAL_CLOCK_BLOCK_PERIPHERAL1_8BIT
#endif /* defined (CY_USING_HAL) || defined (CY_USING_HAL_LITE) */
#if !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE)
#define peri_0_group_1_div_8_1_HW CY_SYSCLK_DIV_8_BIT
#endif /* !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE) */
#define peri_0_group_1_div_8_1_NUM 1U
#define PERI_0_GROUP_1_DIV_8_1_GRP_NUM ((1U << PERI_PCLK_GR_NUM_Pos) | (0U << PERI_PCLK_INST_NUM_Pos))
#if !defined (peri_0_group_1_div_8_1_GRP_NUM)
#define peri_0_group_1_div_8_1_GRP_NUM PERI_0_GROUP_1_DIV_8_1_GRP_NUM
#endif /* !defined (peri_0_group_1_div_8_1_GRP_NUM) */
#define peri_0_group_1_div_8_2_ENABLED 1U
#if defined (CY_USING_HAL) || defined (CY_USING_HAL_LITE)
#define peri_0_group_1_div_8_2_HW CYHAL_CLOCK_BLOCK_PERIPHERAL1_8BIT
#endif /* defined (CY_USING_HAL) || defined (CY_USING_HAL_LITE) */
#if !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE)
#define peri_0_group_1_div_8_2_HW CY_SYSCLK_DIV_8_BIT
#endif /* !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE) */
#define peri_0_group_1_div_8_2_NUM 2U
#define PERI_0_GROUP_1_DIV_8_2_GRP_NUM ((1U << PERI_PCLK_GR_NUM_Pos) | (0U << PERI_PCLK_INST_NUM_Pos))
#if !defined (peri_0_group_1_div_8_2_GRP_NUM)
#define peri_0_group_1_div_8_2_GRP_NUM PERI_0_GROUP_1_DIV_8_2_GRP_NUM
#endif /* !defined (peri_0_group_1_div_8_2_GRP_NUM) */
#define peri_0_group_1_div_8_3_ENABLED 1U
#if defined (CY_USING_HAL) || defined (CY_USING_HAL_LITE)
#define peri_0_group_1_div_8_3_HW CYHAL_CLOCK_BLOCK_PERIPHERAL1_8BIT
#endif /* defined (CY_USING_HAL) || defined (CY_USING_HAL_LITE) */
#if !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE)
#define peri_0_group_1_div_8_3_HW CY_SYSCLK_DIV_8_BIT
#endif /* !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE) */
#define peri_0_group_1_div_8_3_NUM 3U
#define PERI_0_GROUP_1_DIV_8_3_GRP_NUM ((1U << PERI_PCLK_GR_NUM_Pos) | (0U << PERI_PCLK_INST_NUM_Pos))
#if !defined (peri_0_group_1_div_8_3_GRP_NUM)
#define peri_0_group_1_div_8_3_GRP_NUM PERI_0_GROUP_1_DIV_8_3_GRP_NUM
#endif /* !defined (peri_0_group_1_div_8_3_GRP_NUM) */
#define peri_0_group_1_div_8_4_ENABLED 1U
#if defined (CY_USING_HAL) || defined (CY_USING_HAL_LITE)
#define peri_0_group_1_div_8_4_HW CYHAL_CLOCK_BLOCK_PERIPHERAL1_8BIT
#endif /* defined (CY_USING_HAL) || defined (CY_USING_HAL_LITE) */
#if !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE)
#define peri_0_group_1_div_8_4_HW CY_SYSCLK_DIV_8_BIT
#endif /* !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE) */
#define peri_0_group_1_div_8_4_NUM 4U
#define PERI_0_GROUP_1_DIV_8_4_GRP_NUM ((1U << PERI_PCLK_GR_NUM_Pos) | (0U << PERI_PCLK_INST_NUM_Pos))
#if !defined (peri_0_group_1_div_8_4_GRP_NUM)
#define peri_0_group_1_div_8_4_GRP_NUM PERI_0_GROUP_1_DIV_8_4_GRP_NUM
#endif /* !defined (peri_0_group_1_div_8_4_GRP_NUM) */
#define peri_0_group_1_div_8_5_ENABLED 1U
#if defined (CY_USING_HAL) || defined (CY_USING_HAL_LITE)
#define peri_0_group_1_div_8_5_HW CYHAL_CLOCK_BLOCK_PERIPHERAL1_8BIT
#endif /* defined (CY_USING_HAL) || defined (CY_USING_HAL_LITE) */
#if !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE)
#define peri_0_group_1_div_8_5_HW CY_SYSCLK_DIV_8_BIT
#endif /* !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE) */
#define peri_0_group_1_div_8_5_NUM 5U
#define PERI_0_GROUP_1_DIV_8_5_GRP_NUM ((1U << PERI_PCLK_GR_NUM_Pos) | (0U << PERI_PCLK_INST_NUM_Pos))
#if !defined (peri_0_group_1_div_8_5_GRP_NUM)
#define peri_0_group_1_div_8_5_GRP_NUM PERI_0_GROUP_1_DIV_8_5_GRP_NUM
#endif /* !defined (peri_0_group_1_div_8_5_GRP_NUM) */
#define peri_0_group_1_div_8_6_ENABLED 1U
#if defined (CY_USING_HAL) || defined (CY_USING_HAL_LITE)
#define peri_0_group_1_div_8_6_HW CYHAL_CLOCK_BLOCK_PERIPHERAL1_8BIT
#endif /* defined (CY_USING_HAL) || defined (CY_USING_HAL_LITE) */
#if !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE)
#define peri_0_group_1_div_8_6_HW CY_SYSCLK_DIV_8_BIT
#endif /* !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE) */
#define peri_0_group_1_div_8_6_NUM 6U
#define PERI_0_GROUP_1_DIV_8_6_GRP_NUM ((1U << PERI_PCLK_GR_NUM_Pos) | (0U << PERI_PCLK_INST_NUM_Pos))
#if !defined (peri_0_group_1_div_8_6_GRP_NUM)
#define peri_0_group_1_div_8_6_GRP_NUM PERI_0_GROUP_1_DIV_8_6_GRP_NUM
#endif /* !defined (peri_0_group_1_div_8_6_GRP_NUM) */
#define peri_0_group_1_div_8_7_ENABLED 1U
#if defined (CY_USING_HAL) || defined (CY_USING_HAL_LITE)
#define peri_0_group_1_div_8_7_HW CYHAL_CLOCK_BLOCK_PERIPHERAL1_8BIT
#endif /* defined (CY_USING_HAL) || defined (CY_USING_HAL_LITE) */
#if !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE)
#define peri_0_group_1_div_8_7_HW CY_SYSCLK_DIV_8_BIT
#endif /* !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE) */
#define peri_0_group_1_div_8_7_NUM 7U
#define PERI_0_GROUP_1_DIV_8_7_GRP_NUM ((1U << PERI_PCLK_GR_NUM_Pos) | (0U << PERI_PCLK_INST_NUM_Pos))
#if !defined (peri_0_group_1_div_8_7_GRP_NUM)
#define peri_0_group_1_div_8_7_GRP_NUM PERI_0_GROUP_1_DIV_8_7_GRP_NUM
#endif /* !defined (peri_0_group_1_div_8_7_GRP_NUM) */
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_TRACE_CLK_DIV2_obj;
extern const cyhal_resource_inst_t peri_0_group_1_div_8_0_obj;
extern const cyhal_resource_inst_t peri_0_group_1_div_8_1_obj;
extern const cyhal_resource_inst_t peri_0_group_1_div_8_2_obj;
extern const cyhal_resource_inst_t peri_0_group_1_div_8_3_obj;
extern const cyhal_resource_inst_t peri_0_group_1_div_8_4_obj;
extern const cyhal_resource_inst_t peri_0_group_1_div_8_5_obj;
extern const cyhal_resource_inst_t peri_0_group_1_div_8_6_obj;
extern const cyhal_resource_inst_t peri_0_group_1_div_8_7_obj;
#endif /* defined (CY_USING_HAL) */
void init_cycfg_clocks(void);
void reserve_cycfg_clocks(void);
#if defined(__cplusplus)
}
#endif /* defined(__cplusplus) */
#endif /* CYCFG_CLOCKS_H */

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/*******************************************************************************
* File Name: cycfg_notices.h
*
* Description:
* Contains warnings and errors that occurred while generating code for the
* design.
* This file was automatically generated and should not be modified.
* Configurator Backend 3.50.0
* device-db 4.22.0.7873
* mtb-pdl-cat1 3.15.0.40227
*
*******************************************************************************
* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
******************************************************************************/
#if !defined(CYCFG_NOTICES_H)
#define CYCFG_NOTICES_H
#if defined(__cplusplus)
extern "C" {
#endif /* defined(__cplusplus) */
#if defined(CY_SUPPORTS_DEVICE_VALIDATION)
#if !defined(XMC7100D_F144K4160)
#error "Unexpected MPN; expected DEVICE:=XMC7100D-F144K4160. There may be an inconsistency between the *.modus file and the makefile target configuration device sets."
#endif /* !defined(XMC7100D_F144K4160) */
#endif /* defined(CY_SUPPORTS_DEVICE_VALIDATION) */
#if defined(CY_SUPPORTS_COMPLETE_DEVICE_VALIDATION)
#if !defined(XMC7100D_F144K4160)
#error "Unexpected MPN; expected DEVICE:=XMC7100D-F144K4160. There may be an inconsistency between the *.modus file and the makefile target configuration device sets."
#endif /* !defined(XMC7100D_F144K4160) */
#endif /* defined(CY_SUPPORTS_COMPLETE_DEVICE_VALIDATION) */
#if defined(__cplusplus)
}
#endif /* defined(__cplusplus) */
#endif /* CYCFG_NOTICES_H */

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bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg_peripherals.h Normal file
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/*******************************************************************************
* File Name: cycfg_peripherals.h
*
* Description:
* Peripheral Hardware Block configuration
* This file was automatically generated and should not be modified.
* Configurator Backend 3.50.0
* device-db 4.22.0.7873
* mtb-pdl-cat1 3.15.0.40227
*
*******************************************************************************
* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
******************************************************************************/
#if !defined(CYCFG_PERIPHERALS_H)
#define CYCFG_PERIPHERALS_H
#include "cycfg_notices.h"
#if defined(__cplusplus)
extern "C" {
#endif /* defined(__cplusplus) */
#if defined(__cplusplus)
}
#endif /* defined(__cplusplus) */
#endif /* CYCFG_PERIPHERALS_H */

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/*******************************************************************************
* File Name: cycfg_pins.c
*
* Description:
* Pin configuration
* This file was automatically generated and should not be modified.
* Configurator Backend 3.50.0
* device-db 4.22.0.7873
* mtb-pdl-cat1 3.15.0.40227
*
*******************************************************************************
* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
******************************************************************************/
#include "cycfg_pins.h"
const cy_stc_smartio_config_t ioss_0_port_14_smartio_0_config =
{
.clkSrc = CY_SMARTIO_CLK_ASYNC,
.bypassMask = CY_SMARTIO_CHANNEL0|CY_SMARTIO_CHANNEL1|0u|0u|CY_SMARTIO_CHANNEL4|CY_SMARTIO_CHANNEL5|0u|0u,
.ioSyncEn = 0u|0u|0u|0u|0u|0u|0u|0u,
.chipSyncEn = 0u|0u|0u|0u|0u|0u|0u|0u,
.lutCfg0 = NULL,
.lutCfg1 = NULL,
.lutCfg2 = NULL,
.lutCfg3 = NULL,
.lutCfg4 = NULL,
.lutCfg5 = NULL,
.lutCfg6 = NULL,
.lutCfg7 = NULL,
.duCfg = NULL,
.hldOvr = false,
};
const cy_stc_gpio_pin_config_t M2B_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_HIGHZ,
.hsiom = M2B_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
const cyhal_resource_inst_t M2B_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = M2B_PORT_NUM,
.channel_num = M2B_PIN,
};
#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
const cy_stc_gpio_pin_config_t M2A_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_HIGHZ,
.hsiom = M2A_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
const cyhal_resource_inst_t M2A_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = M2A_PORT_NUM,
.channel_num = M2A_PIN,
};
#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
const cy_stc_gpio_pin_config_t CYBSP_ECO_IN_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
.hsiom = CYBSP_ECO_IN_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
const cyhal_resource_inst_t CYBSP_ECO_IN_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_ECO_IN_PORT_NUM,
.channel_num = CYBSP_ECO_IN_PIN,
};
#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
const cy_stc_gpio_pin_config_t CYBSP_ECO_OUT_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
.hsiom = CYBSP_ECO_OUT_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
const cyhal_resource_inst_t CYBSP_ECO_OUT_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_ECO_OUT_PORT_NUM,
.channel_num = CYBSP_ECO_OUT_PIN,
};
#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = CYBSP_SWO_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
const cyhal_resource_inst_t CYBSP_SWO_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SWO_PORT_NUM,
.channel_num = CYBSP_SWO_PIN,
};
#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_PULLDOWN,
.hsiom = CYBSP_SWDCK_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
const cyhal_resource_inst_t CYBSP_SWDCK_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SWDCK_PORT_NUM,
.channel_num = CYBSP_SWDCK_PIN,
};
#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_PULLUP,
.hsiom = CYBSP_SWDIO_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
const cyhal_resource_inst_t CYBSP_SWDIO_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SWDIO_PORT_NUM,
.channel_num = CYBSP_SWDIO_PIN,
};
#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
void init_cycfg_pins(void)
{
Cy_GPIO_Pin_Init(M2B_PORT, M2B_PIN, &M2B_config);
Cy_GPIO_Pin_Init(M2A_PORT, M2A_PIN, &M2A_config);
Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config);
Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config);
Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config);
}
void reserve_cycfg_pins(void)
{
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&M2B_obj);
cyhal_hwmgr_reserve(&M2A_obj);
cyhal_hwmgr_reserve(&CYBSP_ECO_IN_obj);
cyhal_hwmgr_reserve(&CYBSP_ECO_OUT_obj);
cyhal_hwmgr_reserve(&CYBSP_SWO_obj);
cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj);
cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj);
#endif /* defined (CY_USING_HAL) */
}

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/*******************************************************************************
* File Name: cycfg_pins.h
*
* Description:
* Pin configuration
* This file was automatically generated and should not be modified.
* Configurator Backend 3.50.0
* device-db 4.22.0.7873
* mtb-pdl-cat1 3.15.0.40227
*
*******************************************************************************
* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
******************************************************************************/
#if !defined(CYCFG_PINS_H)
#define CYCFG_PINS_H
#include "cycfg_notices.h"
#include "cy_smartio.h"
#include "cy_gpio.h"
#include "cycfg_routing.h"
#if defined (CY_USING_HAL)
#include "cyhal_hwmgr.h"
#endif /* defined (CY_USING_HAL) */
#if defined (CY_USING_HAL_LITE)
#include "cyhal_hw_types.h"
#endif /* defined (CY_USING_HAL_LITE) */
#if defined(__cplusplus)
extern "C" {
#endif /* defined(__cplusplus) */
#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
#define CYBSP_D2 (P0_0)
#define CYBSP_S2G1_INT CYBSP_D2
#define CYBSP_S2G2_INT CYBSP_D2
#define CYBSP_D3 (P0_1)
#define CYBSP_I2C_SCL (P0_2)
#define CYBSP_S2G1_I2C_SCL CYBSP_I2C_SCL
#define CYBSP_MIKROBUS_I2C_SCL CYBSP_I2C_SCL
#define CYBSP_S2G2_I2C_SCL CYBSP_I2C_SCL
#define CYBSP_I2C_SDA (P0_3)
#define CYBSP_S2G1_I2C_SDA CYBSP_I2C_SDA
#define CYBSP_MIKROBUS_I2C_SDA CYBSP_I2C_SDA
#define CYBSP_S2G2_I2C_SDA CYBSP_I2C_SDA
#define CYBSP_DEBUG_UART_RX (P10_0)
#define CYBSP_DEBUG_UART_TX (P10_1)
#define CYBSP_A1 (P11_0)
#define CYBSP_S2G1_GPIO1 CYBSP_A1
#define CYBSP_S2G2_GPIO1 CYBSP_A1
#define CYBSP_A2 (P11_1)
#define CYBSP_MIKROBUS_INT CYBSP_A2
#define CYBSP_A3 (P11_2)
#define CYBSP_MIKROBUS_UART_RX (P12_0)
#define CYBSP_MIKROBUS_UART_TX (P12_1)
#define CYBSP_D9 (P12_2)
#define CYBSP_D8 (P12_3)
#define CYBSP_SPI_MISO (P13_0)
#define CYBSP_S2G1_SPI_MISO CYBSP_SPI_MISO
#define CYBSP_MIKROBUS_SPI_MISO CYBSP_SPI_MISO
#define CYBSP_S2G2_SPI_MISO CYBSP_SPI_MISO
#define CYBSP_SPI_MOSI (P13_1)
#define CYBSP_S2G1_SPI_MOSI CYBSP_SPI_MOSI
#define CYBSP_MIKROBUS_SPI_MOSI CYBSP_SPI_MOSI
#define CYBSP_S2G2_SPI_MOSI CYBSP_SPI_MOSI
#define CYBSP_SPI_CLK (P13_2)
#define CYBSP_S2G1_SPI_SCK CYBSP_SPI_CLK
#define CYBSP_MIKROBUS_SPI_SCK CYBSP_SPI_CLK
#define CYBSP_S2G2_SPI_SCK CYBSP_SPI_CLK
#define CYBSP_SPI_CS (P13_3)
#define CYBSP_MIKROBUS_SPI_CS (P13_4)
#define CYBSP_S2G2_SPI_CS (P13_5)
#define CYBSP_S2G1_SPI_CS (P13_6)
#define CYBSP_A4 (P13_7)
#define CYBSP_S2G1_UART_RX (P14_0)
#define CYBSP_S2G2_UART_RX CYBSP_S2G1_UART_RX
#define CYBSP_S2G1_UART_TX (P14_1)
#define CYBSP_S2G2_UART_TX CYBSP_S2G1_UART_TX
#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
#define ioss_0_port_14_smartio_0_ENABLED 1U
#define ioss_0_port_14_smartio_0_HW SMARTIO_PRT14
#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
#define CYBSP_ETH_REF_CLK (P18_0)
#define CYBSP_ETH_TX_CTL (P18_1)
#define CYBSP_MIKROBUS_AN (P18_2)
#define CYBSP_ETH_TXD_0 (P18_4)
#define CYBSP_ETH_TXD_1 (P18_5)
#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
#define M2B_ENABLED 1U
#define M2B_PORT GPIO_PRT18
#define M2B_PORT_NUM 18U
#define M2B_PIN 6U
#define M2B_NUM 6U
#define M2B_DRIVEMODE CY_GPIO_DM_HIGHZ
#define M2B_INIT_DRIVESTATE 1
#ifndef ioss_0_port_18_pin_6_HSIOM
#define ioss_0_port_18_pin_6_HSIOM HSIOM_SEL_GPIO
#endif
#define M2B_HSIOM ioss_0_port_18_pin_6_HSIOM
#define M2B_IRQ ioss_interrupts_gpio_dpslp_18_IRQn
#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
#define M2B_HAL_PORT_PIN P18_6
#define M2B P18_6
#define M2B_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#define M2B_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define M2B_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE
#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
#define M2A_ENABLED 1U
#define M2A_PORT GPIO_PRT18
#define M2A_PORT_NUM 18U
#define M2A_PIN 7U
#define M2A_NUM 7U
#define M2A_DRIVEMODE CY_GPIO_DM_HIGHZ
#define M2A_INIT_DRIVESTATE 1
#ifndef ioss_0_port_18_pin_7_HSIOM
#define ioss_0_port_18_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
#define M2A_HSIOM ioss_0_port_18_pin_7_HSIOM
#define M2A_IRQ ioss_interrupts_gpio_dpslp_18_IRQn
#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
#define M2A_HAL_PORT_PIN P18_7
#define M2A P18_7
#define M2A_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#define M2A_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define M2A_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE
#define UART_RX (P19_0)
#define UART_TX (P19_1)
#define CYBSP_MIKROBUS_PWM (P19_3)
#define CYBSP_WCO_IN (P21_0)
#define CYBSP_WCO_OUT (P21_1)
#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
#define CYBSP_ECO_IN_ENABLED 1U
#define CYBSP_ECO_IN_PORT GPIO_PRT21
#define CYBSP_ECO_IN_PORT_NUM 21U
#define CYBSP_ECO_IN_PIN 2U
#define CYBSP_ECO_IN_NUM 2U
#define CYBSP_ECO_IN_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_ECO_IN_INIT_DRIVESTATE 1
#ifndef ioss_0_port_21_pin_2_HSIOM
#define ioss_0_port_21_pin_2_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_ECO_IN_HSIOM ioss_0_port_21_pin_2_HSIOM
#define CYBSP_ECO_IN_IRQ ioss_interrupts_gpio_dpslp_21_IRQn
#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
#define CYBSP_ECO_IN_HAL_PORT_PIN P21_2
#define CYBSP_ECO_IN P21_2
#define CYBSP_ECO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#define CYBSP_ECO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_ECO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
#define CYBSP_ECO_OUT_ENABLED 1U
#define CYBSP_ECO_OUT_PORT GPIO_PRT21
#define CYBSP_ECO_OUT_PORT_NUM 21U
#define CYBSP_ECO_OUT_PIN 3U
#define CYBSP_ECO_OUT_NUM 3U
#define CYBSP_ECO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_ECO_OUT_INIT_DRIVESTATE 1
#ifndef ioss_0_port_21_pin_3_HSIOM
#define ioss_0_port_21_pin_3_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_ECO_OUT_HSIOM ioss_0_port_21_pin_3_HSIOM
#define CYBSP_ECO_OUT_IRQ ioss_interrupts_gpio_dpslp_21_IRQn
#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
#define CYBSP_ECO_OUT_HAL_PORT_PIN P21_3
#define CYBSP_ECO_OUT P21_3
#define CYBSP_ECO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#define CYBSP_ECO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_ECO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#define CYBSP_ETH_RX_CTL (P21_5)
#define CYBSP_S2G1_PWM (P23_3)
#define CYBSP_S2G2_PWM CYBSP_S2G1_PWM
#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
#define CYBSP_SWO_ENABLED 1U
#define CYBSP_SWO_PORT GPIO_PRT23
#define CYBSP_SWO_PORT_NUM 23U
#define CYBSP_SWO_PIN 4U
#define CYBSP_SWO_NUM 4U
#define CYBSP_SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_SWO_INIT_DRIVESTATE 1
#ifndef ioss_0_port_23_pin_4_HSIOM
#define ioss_0_port_23_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_SWO_HSIOM ioss_0_port_23_pin_4_HSIOM
#define CYBSP_SWO_IRQ ioss_interrupts_gpio_dpslp_23_IRQn
#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
#define CYBSP_SWO_HAL_PORT_PIN P23_4
#define CYBSP_SWO P23_4
#define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
#define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
#define CYBSP_SWDCK_ENABLED 1U
#define CYBSP_SWDCK_PORT GPIO_PRT23
#define CYBSP_SWDCK_PORT_NUM 23U
#define CYBSP_SWDCK_PIN 5U
#define CYBSP_SWDCK_NUM 5U
#define CYBSP_SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN
#define CYBSP_SWDCK_INIT_DRIVESTATE 1
#ifndef ioss_0_port_23_pin_5_HSIOM
#define ioss_0_port_23_pin_5_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_SWDCK_HSIOM ioss_0_port_23_pin_5_HSIOM
#define CYBSP_SWDCK_IRQ ioss_interrupts_gpio_dpslp_23_IRQn
#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
#define CYBSP_SWDCK_HAL_PORT_PIN P23_5
#define CYBSP_SWDCK P23_5
#define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN
#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
#define CYBSP_SWDIO_ENABLED 1U
#define CYBSP_SWDIO_PORT GPIO_PRT23
#define CYBSP_SWDIO_PORT_NUM 23U
#define CYBSP_SWDIO_PIN 6U
#define CYBSP_SWDIO_NUM 6U
#define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP
#define CYBSP_SWDIO_INIT_DRIVESTATE 1
#ifndef ioss_0_port_23_pin_6_HSIOM
#define ioss_0_port_23_pin_6_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_SWDIO_HSIOM ioss_0_port_23_pin_6_HSIOM
#define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_dpslp_23_IRQn
#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
#define CYBSP_SWDIO_HAL_PORT_PIN P23_6
#define CYBSP_SWDIO P23_6
#define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP
#define CYBSP_ETH_RX_ERR (P2_2)
#define CYBSP_ETH_MDIO (P3_0)
#define CYBSP_ETH_MDC (P3_1)
#define CYBSP_USER_LED2 (P5_1)
#define LED2 CYBSP_USER_LED2
#define CYBSP_CANFD_STB (P5_2)
#define CYBSP_USER_BTN1 (P5_3)
#define CYBSP_USER_BTN CYBSP_USER_BTN1
#define CYBSP_POT (P6_0)
#define CYBSP_D4 (P6_1)
#define CYBSP_QSPI_SCK (P6_3)
#define CYBSP_FLASH_RST (P6_4)
#define CYBSP_QSPI_SS (P7_0)
#define CYBSP_QSPI_D0 (P7_1)
#define CYBSP_QSPI_D1 (P7_2)
#define CYBSP_QSPI_D2 (P7_3)
#define CYBSP_QSPI_D3 (P7_4)
#define CYBSP_USER_BUZZER (P7_5)
#define CYBSP_CAN_TX (P8_0)
#define CYBSP_CAN_RX (P8_1)
#define M1B (P8_2)
#define M1A (P8_3)
#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
extern const cy_stc_smartio_config_t ioss_0_port_14_smartio_0_config;
extern const cy_stc_gpio_pin_config_t M2B_config;
#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
extern const cyhal_resource_inst_t M2B_obj;
#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
extern const cy_stc_gpio_pin_config_t M2A_config;
#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
extern const cyhal_resource_inst_t M2A_obj;
#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
extern const cy_stc_gpio_pin_config_t CYBSP_ECO_IN_config;
#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
extern const cyhal_resource_inst_t CYBSP_ECO_IN_obj;
#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
extern const cy_stc_gpio_pin_config_t CYBSP_ECO_OUT_config;
#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
extern const cyhal_resource_inst_t CYBSP_ECO_OUT_obj;
#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config;
#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
extern const cyhal_resource_inst_t CYBSP_SWO_obj;
#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
extern const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config;
#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
extern const cyhal_resource_inst_t CYBSP_SWDCK_obj;
#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config;
#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
extern const cyhal_resource_inst_t CYBSP_SWDIO_obj;
#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
void init_cycfg_pins(void);
void reserve_cycfg_pins(void);
#if defined(__cplusplus)
}
#endif /* defined(__cplusplus) */
#endif /* CYCFG_PINS_H */

484
bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg_qspi_memslot.c Normal file
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/*******************************************************************************
* File Name: cycfg_qspi_memslot.c
*
* Description:
* Provides definitions of the SMIF-driver memory configuration.
* This file was automatically generated and should not be modified.
* QSPI Configurator 4.50.0.2481
*
*******************************************************************************
* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
******************************************************************************/
#include "cycfg_qspi_memslot.h"
cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_1_readCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0xECU,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_QUAD,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0x01U,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_QUAD,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 8U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_QUAD,
#if (CY_IP_MXSMIF_VERSION >= 2)
/* The Data rate of data */
.dataRate = CY_SMIF_SDR,
/* This specifies the presence of the dummy field */
.dummyCyclesPresence = CY_SMIF_PRESENT_1BYTE,
/* This specifies the presence of the mode field */
.modePresence = CY_SMIF_PRESENT_1BYTE,
/* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */
.modeH = 0x00,
/* The Data rate of mode */
.modeRate = CY_SMIF_SDR,
/* The Data rate of address */
.addrRate = CY_SMIF_SDR,
/* This specifies the width of the command field */
.cmdPresence = CY_SMIF_PRESENT_1BYTE,
/* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
.commandH = 0x00,
/* The Data rate of command */
.cmdRate = CY_SMIF_SDR,
#endif /* CY_IP_MXSMIF_VERSION */
};
cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_1_writeEnCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x06U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE,
#if (CY_IP_MXSMIF_VERSION >= 2)
/* The Data rate of data */
.dataRate = CY_SMIF_SDR,
/* This specifies the presence of the dummy field */
.dummyCyclesPresence = CY_SMIF_NOT_PRESENT,
/* This specifies the presence of the mode field */
.modePresence = CY_SMIF_NOT_PRESENT,
/* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */
.modeH = 0x00,
/* The Data rate of mode */
.modeRate = CY_SMIF_SDR,
/* The Data rate of address */
.addrRate = CY_SMIF_SDR,
/* This specifies the width of the command field */
.cmdPresence = CY_SMIF_PRESENT_1BYTE,
/* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
.commandH = 0x00,
/* The Data rate of command */
.cmdRate = CY_SMIF_SDR,
#endif /* CY_IP_MXSMIF_VERSION */
};
cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_1_writeDisCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x04U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE,
#if (CY_IP_MXSMIF_VERSION >= 2)
/* The Data rate of data */
.dataRate = CY_SMIF_SDR,
/* This specifies the presence of the dummy field */
.dummyCyclesPresence = CY_SMIF_NOT_PRESENT,
/* This specifies the presence of the mode field */
.modePresence = CY_SMIF_NOT_PRESENT,
/* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */
.modeH = 0x00,
/* The Data rate of mode */
.modeRate = CY_SMIF_SDR,
/* The Data rate of address */
.addrRate = CY_SMIF_SDR,
/* This specifies the width of the command field */
.cmdPresence = CY_SMIF_PRESENT_1BYTE,
/* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
.commandH = 0x00,
/* The Data rate of command */
.cmdRate = CY_SMIF_SDR,
#endif /* CY_IP_MXSMIF_VERSION */
};
cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_1_eraseCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0xDCU,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE,
#if (CY_IP_MXSMIF_VERSION >= 2)
/* The Data rate of data */
.dataRate = CY_SMIF_SDR,
/* This specifies the presence of the dummy field */
.dummyCyclesPresence = CY_SMIF_NOT_PRESENT,
/* This specifies the presence of the mode field */
.modePresence = CY_SMIF_NOT_PRESENT,
/* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */
.modeH = 0x00,
/* The Data rate of mode */
.modeRate = CY_SMIF_SDR,
/* The Data rate of address */
.addrRate = CY_SMIF_SDR,
/* This specifies the width of the command field */
.cmdPresence = CY_SMIF_PRESENT_1BYTE,
/* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
.commandH = 0x00,
/* The Data rate of command */
.cmdRate = CY_SMIF_SDR,
#endif /* CY_IP_MXSMIF_VERSION */
};
cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_1_chipEraseCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x60U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE,
#if (CY_IP_MXSMIF_VERSION >= 2)
/* The Data rate of data */
.dataRate = CY_SMIF_SDR,
/* This specifies the presence of the dummy field */
.dummyCyclesPresence = CY_SMIF_NOT_PRESENT,
/* This specifies the presence of the mode field */
.modePresence = CY_SMIF_NOT_PRESENT,
/* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */
.modeH = 0x00,
/* The Data rate of mode */
.modeRate = CY_SMIF_SDR,
/* The Data rate of address */
.addrRate = CY_SMIF_SDR,
/* This specifies the width of the command field */
.cmdPresence = CY_SMIF_PRESENT_1BYTE,
/* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
.commandH = 0x00,
/* The Data rate of command */
.cmdRate = CY_SMIF_SDR,
#endif /* CY_IP_MXSMIF_VERSION */
};
cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_1_programCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x12U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE,
#if (CY_IP_MXSMIF_VERSION >= 2)
/* The Data rate of data */
.dataRate = CY_SMIF_SDR,
/* This specifies the presence of the dummy field */
.dummyCyclesPresence = CY_SMIF_NOT_PRESENT,
/* This specifies the presence of the mode field */
.modePresence = CY_SMIF_NOT_PRESENT,
/* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */
.modeH = 0x00,
/* The Data rate of mode */
.modeRate = CY_SMIF_SDR,
/* The Data rate of address */
.addrRate = CY_SMIF_SDR,
/* This specifies the width of the command field */
.cmdPresence = CY_SMIF_PRESENT_1BYTE,
/* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
.commandH = 0x00,
/* The Data rate of command */
.cmdRate = CY_SMIF_SDR,
#endif /* CY_IP_MXSMIF_VERSION */
};
cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_1_readStsRegQeCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x35U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE,
#if (CY_IP_MXSMIF_VERSION >= 2)
/* The Data rate of data */
.dataRate = CY_SMIF_SDR,
/* This specifies the presence of the dummy field */
.dummyCyclesPresence = CY_SMIF_NOT_PRESENT,
/* This specifies the presence of the mode field */
.modePresence = CY_SMIF_NOT_PRESENT,
/* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */
.modeH = 0x00,
/* The Data rate of mode */
.modeRate = CY_SMIF_SDR,
/* The Data rate of address */
.addrRate = CY_SMIF_SDR,
/* This specifies the width of the command field */
.cmdPresence = CY_SMIF_PRESENT_1BYTE,
/* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
.commandH = 0x00,
/* The Data rate of command */
.cmdRate = CY_SMIF_SDR,
#endif /* CY_IP_MXSMIF_VERSION */
};
cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_1_readStsRegWipCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x05U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE,
#if (CY_IP_MXSMIF_VERSION >= 2)
/* The Data rate of data */
.dataRate = CY_SMIF_SDR,
/* This specifies the presence of the dummy field */
.dummyCyclesPresence = CY_SMIF_NOT_PRESENT,
/* This specifies the presence of the mode field */
.modePresence = CY_SMIF_NOT_PRESENT,
/* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */
.modeH = 0x00,
/* The Data rate of mode */
.modeRate = CY_SMIF_SDR,
/* The Data rate of address */
.addrRate = CY_SMIF_SDR,
/* This specifies the width of the command field */
.cmdPresence = CY_SMIF_PRESENT_1BYTE,
/* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
.commandH = 0x00,
/* The Data rate of command */
.cmdRate = CY_SMIF_SDR,
#endif /* CY_IP_MXSMIF_VERSION */
};
cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_1_writeStsRegQeCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x01U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE,
#if (CY_IP_MXSMIF_VERSION >= 2)
/* The Data rate of data */
.dataRate = CY_SMIF_SDR,
/* This specifies the presence of the dummy field */
.dummyCyclesPresence = CY_SMIF_NOT_PRESENT,
/* This specifies the presence of the mode field */
.modePresence = CY_SMIF_NOT_PRESENT,
/* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */
.modeH = 0x00,
/* The Data rate of mode */
.modeRate = CY_SMIF_SDR,
/* The Data rate of address */
.addrRate = CY_SMIF_SDR,
/* This specifies the width of the command field */
.cmdPresence = CY_SMIF_PRESENT_1BYTE,
/* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
.commandH = 0x00,
/* The Data rate of command */
.cmdRate = CY_SMIF_SDR,
#endif /* CY_IP_MXSMIF_VERSION */
};
cy_stc_smif_mem_device_cfg_t deviceCfg_S25HL512T_SlaveSlot_1 =
{
/* Specifies the number of address bytes used by the memory slave device. */
.numOfAddrBytes = 0x04U,
/* The size of the memory. */
.memSize = 0x04000000U,
/* Specifies the Read command. */
.readCmd = &S25HL512T_SlaveSlot_1_readCmd,
/* Specifies the Write Enable command. */
.writeEnCmd = &S25HL512T_SlaveSlot_1_writeEnCmd,
/* Specifies the Write Disable command. */
.writeDisCmd = &S25HL512T_SlaveSlot_1_writeDisCmd,
/* Specifies the Erase command. */
.eraseCmd = &S25HL512T_SlaveSlot_1_eraseCmd,
/* Specifies the sector size of each erase. */
.eraseSize = 0x0040000U,
/* Specifies the Chip Erase command. */
.chipEraseCmd = &S25HL512T_SlaveSlot_1_chipEraseCmd,
/* Specifies the Program command. */
.programCmd = &S25HL512T_SlaveSlot_1_programCmd,
/* Specifies the page size for programming. */
.programSize = 0x0000100U,
/* Specifies the command to read the QE-containing status register. */
.readStsRegQeCmd = &S25HL512T_SlaveSlot_1_readStsRegQeCmd,
/* Specifies the command to read the WIP-containing status register. */
.readStsRegWipCmd = &S25HL512T_SlaveSlot_1_readStsRegWipCmd,
/* Specifies the command to write into the QE-containing status register. */
.writeStsRegQeCmd = &S25HL512T_SlaveSlot_1_writeStsRegQeCmd,
/* The mask for the status register. */
.stsRegBusyMask = 0x01U,
/* The mask for the status register. */
.stsRegQuadEnableMask = 0x02U,
/* The max time for the erase type-1 cycle-time in ms. */
.eraseTime = 5869U,
/* The max time for the chip-erase cycle-time in ms. */
.chipEraseTime = 696000U,
/* The max time for the page-program cycle-time in us. */
.programTime = 2175U,
#if (CY_SMIF_DRV_VERSION_MAJOR > 1) || (CY_SMIF_DRV_VERSION_MINOR >= 50)
/* Points to NULL or to structure with info about sectors for hybrid memory. */
.hybridRegionCount = 0U,
.hybridRegionInfo = 0,
#endif
/* Specifies the command to read variable latency cycles configuration register */
.readLatencyCmd = 0,
/* Specifies the command to write variable latency cycles configuration register */
.writeLatencyCmd = 0,
/* Specifies the address for variable latency cycle address */
.latencyCyclesRegAddr = 0x00U,
/* Specifies variable latency cycles Mask */
.latencyCyclesMask = 0x00U,
#if (CY_IP_MXSMIF_VERSION >= 2)
/* Specifies data for memory with hybrid sectors */
.octalDDREnableSeq = 0,
/* Specifies the command to read the OE-containing status register. */
.readStsRegOeCmd = 0,
/* Specifies the command to write the OE-containing status register. */
.writeStsRegOeCmd = 0,
/* QE mask for the status registers */
.stsRegOctalEnableMask = 0x00U,
/* Octal enable register address */
.octalEnableRegAddr = 0x00U,
/* Frequency of operation used in Octal mode */
.freq_of_operation = CY_SMIF_100MHZ_OPERATION,
#endif
};
cy_stc_smif_mem_config_t S25HL512T_SlaveSlot_1 =
{
/* Determines the slot number where the memory device is placed. */
.slaveSelect = CY_SMIF_SLAVE_SELECT_1,
/* Flags. */
#if (CY_IP_MXSMIF_VERSION >= 2)
.flags = CY_SMIF_FLAG_SMIF_REV_3 | CY_SMIF_FLAG_MEMORY_MAPPED | CY_SMIF_FLAG_WR_EN,
#else
.flags = CY_SMIF_FLAG_MEMORY_MAPPED | CY_SMIF_FLAG_WR_EN,
#endif /* CY_IP_MXSMIF_VERSION */
/* The data-line selection options for a slave device. */
.dataSelect = CY_SMIF_DATA_SEL0,
/* The base address the memory slave is mapped to in the PSoC memory map.
Valid when the memory-mapped mode is enabled. */
.baseAddress = 0x60000000U,
/* The size allocated in the PSoC memory map, for the memory slave device.
The size is allocated from the base address. Valid when the memory mapped mode is enabled. */
.memMappedSize = 0x10000U,
/* If this memory device is one of the devices in the dual quad SPI configuration.
Valid when the memory mapped mode is enabled. */
.dualQuadSlots = 0,
/* The configuration of the device. */
.deviceCfg = &deviceCfg_S25HL512T_SlaveSlot_1,
#if (CY_IP_MXSMIF_VERSION >= 2)
/** Continous transfer merge timeout.
* After this period the memory device is deselected. A later transfer, even from a
* continuous address, starts with the overhead phases (command, address, mode, dummy cycles).
* This configuration parameter is available for CAT1B devices. */
.mergeTimeout = CY_SMIF_MERGE_TIMEOUT_1_CYCLE,
#endif /* CY_IP_MXSMIF_VERSION */
};
cy_stc_smif_mem_config_t* smifMemConfigs[CY_SMIF_DEVICE_NUM] = {
&S25HL512T_SlaveSlot_1,
};
cy_stc_smif_block_config_t smifBlockConfig =
{
/* The number of SMIF memories defined. */
.memCount = CY_SMIF_DEVICE_NUM,
/* The pointer to the array of memory config structures of size memCount. */
.memConfig = (cy_stc_smif_mem_config_t**)smifMemConfigs,
/* The version of the SMIF driver. */
.majorVersion = CY_SMIF_DRV_VERSION_MAJOR,
/* The version of the SMIF driver. */
.minorVersion = CY_SMIF_DRV_VERSION_MINOR,
};

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bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg_qspi_memslot.h Normal file
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/*******************************************************************************
* File Name: cycfg_qspi_memslot.h
*
* Description:
* Provides declarations of the SMIF-driver memory configuration.
* This file was automatically generated and should not be modified.
* QSPI Configurator 4.50.0.2481
*
*******************************************************************************
* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
******************************************************************************/
#ifndef CYCFG_QSPI_MEMSLOT_H
#define CYCFG_QSPI_MEMSLOT_H
#include "cy_smif_memslot.h"
#define CY_SMIF_CFG_TOOL_VERSION (450)
/* Supported QSPI Driver version */
#define CY_SMIF_DRV_VERSION_REQUIRED (100)
#if !defined(CY_SMIF_DRV_VERSION)
#define CY_SMIF_DRV_VERSION (100)
#endif
/* Check the used Driver version */
#if (CY_SMIF_DRV_VERSION_REQUIRED > CY_SMIF_DRV_VERSION)
#error The QSPI Configurator requires a newer version of the PDL. Update the PDL in your project.
#endif
typedef cy_stc_smif_mem_config_t cy_serial_flash_mem_config_t;
typedef cy_stc_smif_block_config_t cy_serial_flash_block_config_t;
#define CY_SMIF_DEVICE_NUM 1
extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_1_readCmd;
extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_1_writeEnCmd;
extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_1_writeDisCmd;
extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_1_eraseCmd;
extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_1_chipEraseCmd;
extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_1_programCmd;
extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_1_readStsRegQeCmd;
extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_1_readStsRegWipCmd;
extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_1_writeStsRegQeCmd;
extern cy_stc_smif_mem_device_cfg_t deviceCfg_S25HL512T_SlaveSlot_1;
extern cy_stc_smif_mem_config_t S25HL512T_SlaveSlot_1;
extern cy_stc_smif_mem_config_t* smifMemConfigs[CY_SMIF_DEVICE_NUM];
extern cy_stc_smif_block_config_t smifBlockConfig;
#endif /*CYCFG_QSPI_MEMSLOT_H*/

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bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg_qspi_memslot.timestamp Normal file
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/*******************************************************************************
* File Name: cycfg_qspi_memslot.timestamp
*
* Description:
* Sentinel file for determining if generated source is up to date.
* This file was automatically generated and should not be modified.
* QSPI Configurator 4.50.0.2481
*
*******************************************************************************
* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
******************************************************************************/

50
bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/cycfg_routing.h Normal file
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/*******************************************************************************
* File Name: cycfg_routing.h
*
* Description:
* Establishes all necessary connections between hardware elements.
* This file was automatically generated and should not be modified.
* Configurator Backend 3.50.0
* device-db 4.22.0.7873
* mtb-pdl-cat1 3.15.0.40227
*
*******************************************************************************
* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
******************************************************************************/
#if !defined(CYCFG_ROUTING_H)
#define CYCFG_ROUTING_H
#include "cycfg_notices.h"
#if defined(__cplusplus)
extern "C" {
#endif /* defined(__cplusplus) */
#define ioss_0_port_21_pin_2_ANALOG P21_2_SRSS_ECO_IN
#define ioss_0_port_21_pin_3_ANALOG P21_3_SRSS_ECO_OUT
#define ioss_0_port_23_pin_4_HSIOM P23_4_CPUSS_SWJ_SWO_TDO
#define ioss_0_port_23_pin_5_HSIOM P23_5_CPUSS_SWJ_SWCLK_TCLK
#define ioss_0_port_23_pin_6_HSIOM P23_6_CPUSS_SWJ_SWDIO_TMS
static inline void init_cycfg_routing(void) {}
#if defined(__cplusplus)
}
#endif /* defined(__cplusplus) */
#endif /* CYCFG_ROUTING_H */

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/*******************************************************************************
* File Name: cycfg_system.c
*
* Description:
* System configuration
* This file was automatically generated and should not be modified.
* Configurator Backend 3.50.0
* device-db 4.22.0.7873
* mtb-pdl-cat1 3.15.0.40227
*
*******************************************************************************
* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
******************************************************************************/
#include "cycfg_system.h"
#define CY_CFG_SYSCLK_ECO_ERROR 1
#define CY_CFG_SYSCLK_ALTHF_ERROR 2
#define CY_CFG_SYSCLK_PLL_ERROR 3
#define CY_CFG_SYSCLK_FLL_ERROR 4
#define CY_CFG_SYSCLK_WCO_ERROR 5
#if (CY_CPU_CORTEX_M7)
#define CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED 1
#define CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE CY_SYSTICK_CLOCK_SOURCE_CLK_IMO
#define CY_CFG_SYSCLK_CLKALTSYSTICK_INTERVAL 1000
#define CY_CFG_SYSCLK_CLKALTSYSTICK_FREQUENCY 8000000
#define CY_CFG_SYSCLK_CLKALTSYSTICK_TICKS ((1000)/1000000.0)*8000000
#endif /* (CY_CPU_CORTEX_M7) */
#define CY_CFG_SYSCLK_CLKBAK_ENABLED 1
#define CY_CFG_SYSCLK_CLKBAK_SOURCE CY_SYSCLK_BAK_IN_CLKLF
#define CY_CFG_SYSCLK_ECO_ENABLED 1
#define CY_CFG_SYSCLK_ECO_FREQ 20000000UL
#define CY_CFG_SYSCLK_ECO_GPIO_IN_PRT GPIO_PRT21
#define CY_CFG_SYSCLK_ECO_GPIO_IN_PIN 2
#define CY_CFG_SYSCLK_ECO_GPIO_OUT_PRT GPIO_PRT21
#define CY_CFG_SYSCLK_ECO_GPIO_OUT_PIN 3
#define CY_CFG_SYSCLK_ECO_CLOAD 8UL
#define CY_CFG_SYSCLK_ECO_ESR 50UL
#define CY_CFG_SYSCLK_ECO_DRIVE_LEVEL 100UL
#define CY_CFG_SYSCLK_CLKFAST_0_ENABLED 1
#define CY_CFG_SYSCLK_CLKFAST_0_INT_DIVIDER 0
#define CY_CFG_SYSCLK_CLKFAST_0_FRAC_DIVIDER 0
#define CY_CFG_SYSCLK_CLKFAST_1_ENABLED 1
#define CY_CFG_SYSCLK_CLKFAST_1_INT_DIVIDER 0
#define CY_CFG_SYSCLK_CLKFAST_1_FRAC_DIVIDER 0
#define CY_CFG_SYSCLK_FLL_ENABLED 1
#define CY_CFG_SYSCLK_FLL_MULT 500U
#define CY_CFG_SYSCLK_FLL_REFDIV 50U
#define CY_CFG_SYSCLK_FLL_CCO_RANGE CY_SYSCLK_FLL_CCO_RANGE4
#define CY_CFG_SYSCLK_FLL_ENABLE_OUTDIV true
#define CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE 2U
#define CY_CFG_SYSCLK_FLL_IGAIN 9U
#define CY_CFG_SYSCLK_FLL_PGAIN 5U
#define CY_CFG_SYSCLK_FLL_SETTLING_COUNT 20U
#define CY_CFG_SYSCLK_FLL_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT
#define CY_CFG_SYSCLK_FLL_CCO_FREQ 355U
#define CY_CFG_SYSCLK_FLL_OUT_FREQ 100000000
#define CY_CFG_SYSCLK_CLKHF0_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF0_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE
#define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 100UL
#define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
#define CY_CFG_SYSCLK_CLKHF1_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF1_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE
#define CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ 250UL
#define CY_CFG_SYSCLK_CLKHF1_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH1
#define CY_CFG_SYSCLK_CLKHF2_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF2_DIVIDER CY_SYSCLK_CLKHF_DIVIDE_BY_2
#define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 100UL
#define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH4
#define CY_CFG_SYSCLK_CLKHF3_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF3_DIVIDER CY_SYSCLK_CLKHF_DIVIDE_BY_2
#define CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ 100UL
#define CY_CFG_SYSCLK_CLKHF3_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH4
#define CY_CFG_SYSCLK_CLKHF4_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF4_DIVIDER CY_SYSCLK_CLKHF_DIVIDE_BY_4
#define CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ 50UL
#define CY_CFG_SYSCLK_CLKHF4_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH4
#define CY_CFG_SYSCLK_CLKHF5_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF5_DIVIDER CY_SYSCLK_CLKHF_DIVIDE_BY_2
#define CY_CFG_SYSCLK_CLKHF5_FREQ_MHZ 125UL
#define CY_CFG_SYSCLK_CLKHF5_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH2
#define CY_CFG_SYSCLK_CLKHF6_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF6_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE
#define CY_CFG_SYSCLK_CLKHF6_FREQ_MHZ 200UL
#define CY_CFG_SYSCLK_CLKHF6_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH4
#define CY_CFG_SYSCLK_CLKHF7_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF7_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE
#define CY_CFG_SYSCLK_CLKHF7_FREQ_MHZ 0UL
#define CY_CFG_SYSCLK_CLKHF7_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH5
#define CY_CFG_SYSCLK_ILO0_ENABLED 1
#define CY_CFG_SYSCLK_ILO0_HIBERNATE true
#define CY_CFG_SYSCLK_ILO1_ENABLED 1
#define CY_CFG_SYSCLK_ILO1_HIBERNATE true
#define CY_CFG_SYSCLK_IMO_ENABLED 1
#define CY_CFG_SYSCLK_CLKLF_ENABLED 1
#define CY_CFG_SYSCLK_CLKMEM_ENABLED 1
#define CY_CFG_SYSCLK_CLKMEM_DIVIDER 0
#define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1
#define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_ECO
#define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1
#define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_ECO
#define CY_CFG_SYSCLK_CLKPATH2_ENABLED 1
#define CY_CFG_SYSCLK_CLKPATH2_SOURCE CY_SYSCLK_CLKPATH_IN_ECO
#define CY_CFG_SYSCLK_CLKPATH3_ENABLED 1
#define CY_CFG_SYSCLK_CLKPATH3_SOURCE CY_SYSCLK_CLKPATH_IN_ECO
#define CY_CFG_SYSCLK_CLKPATH4_ENABLED 1
#define CY_CFG_SYSCLK_CLKPATH4_SOURCE CY_SYSCLK_CLKPATH_IN_ECO
#define CY_CFG_SYSCLK_CLKPATH5_ENABLED 1
#define CY_CFG_SYSCLK_CLKPATH5_SOURCE CY_SYSCLK_CLKPATH_IN_ILO0
#define CY_CFG_SYSCLK_CLKPATH6_ENABLED 1
#define CY_CFG_SYSCLK_CLKPATH6_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
#define CY_CFG_SYSCLK_PLL0_ENABLED 1
#define CY_CFG_SYSCLK_PLL0_FEEDBACK_DIV 25
#define CY_CFG_SYSCLK_PLL0_REFERENCE_DIV 1
#define CY_CFG_SYSCLK_PLL0_OUTPUT_DIV 2
#define CY_CFG_SYSCLK_PLL0_FRAC_DIV 0
#define CY_CFG_SYSCLK_PLL0_FRAC_DITHER_EN false
#define CY_CFG_SYSCLK_PLL0_FRAC_EN false
#define CY_CFG_SYSCLK_PLL0_LF_MODE false
#define CY_CFG_SYSCLK_PLL0_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_AUTO
#define CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ 250000000
#define CY_CFG_SYSCLK_PLL1_ENABLED 1
#define CY_CFG_SYSCLK_PLL1_FEEDBACK_DIV 25
#define CY_CFG_SYSCLK_PLL1_REFERENCE_DIV 1
#define CY_CFG_SYSCLK_PLL1_OUTPUT_DIV 2
#define CY_CFG_SYSCLK_PLL1_FRAC_DIV 0
#define CY_CFG_SYSCLK_PLL1_FRAC_DITHER_EN false
#define CY_CFG_SYSCLK_PLL1_FRAC_EN false
#define CY_CFG_SYSCLK_PLL1_LF_MODE false
#define CY_CFG_SYSCLK_PLL1_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_AUTO
#define CY_CFG_SYSCLK_PLL1_OUTPUT_FREQ 250000000
#define CY_CFG_SYSCLK_PLL2_ENABLED 1
#define CY_CFG_SYSCLK_PLL2_FEEDBACK_DIV 48
#define CY_CFG_SYSCLK_PLL2_REFERENCE_DIV 3
#define CY_CFG_SYSCLK_PLL2_OUTPUT_DIV 2
#define CY_CFG_SYSCLK_PLL2_LF_MODE false
#define CY_CFG_SYSCLK_PLL2_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_AUTO
#define CY_CFG_SYSCLK_PLL2_OUTPUT_FREQ 160000000
#define CY_CFG_SYSCLK_PLL3_ENABLED 1
#define CY_CFG_SYSCLK_PLL3_FEEDBACK_DIV 60
#define CY_CFG_SYSCLK_PLL3_REFERENCE_DIV 3
#define CY_CFG_SYSCLK_PLL3_OUTPUT_DIV 2
#define CY_CFG_SYSCLK_PLL3_LF_MODE false
#define CY_CFG_SYSCLK_PLL3_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_AUTO
#define CY_CFG_SYSCLK_PLL3_OUTPUT_FREQ 200000000
#define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1
#define CY_CFG_SYSCLK_CLKSLOW_DIVIDER 0
#define CY_CFG_PWR_ENABLED 1
#define CY_CFG_PWR_INIT 1
#define CY_CFG_PWR_VBACKUP_USING_VDDD 1
#define CY_CFG_PWR_REGULATOR_MODE_MIN 0
#define CY_CFG_PWR_USING_ULP 0
#if (!defined(CY_DEVICE_SECURE))
static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
{
.fllMult = 500U,
.refDiv = 50U,
.ccoRange = CY_SYSCLK_FLL_CCO_RANGE4,
.enableOutputDiv = true,
.lockTolerance = 2U,
.igain = 9U,
.pgain = 5U,
.settlingCount = 20U,
.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT,
.cco_Freq = 355U,
};
#endif /* (!defined(CY_DEVICE_SECURE)) */
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 0U,
.channel_num = 0U,
};
const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 1U,
.channel_num = 0U,
};
const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 2U,
.channel_num = 0U,
};
const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 3U,
.channel_num = 0U,
};
const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 4U,
.channel_num = 0U,
};
const cyhal_resource_inst_t srss_0_clock_0_pathmux_5_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 5U,
.channel_num = 0U,
};
const cyhal_resource_inst_t srss_0_clock_0_pathmux_6_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 6U,
.channel_num = 0U,
};
#endif /* defined (CY_USING_HAL) */
typedef enum
{
CY_SYSCLK_SSCG_DEPTH_MINUS_0_5 = 0x029u, /**< - 0.5 [%] (down spread) */
CY_SYSCLK_SSCG_DEPTH_MINUS_1_0 = 0x052u, /**< - 1.0 [%] (down spread) */
CY_SYSCLK_SSCG_DEPTH_MINUS_2_0 = 0x0A4u, /**< - 2.0 [%] (down spread) */
CY_SYSCLK_SSCG_DEPTH_MINUS_3_0 = 0x0F6u, /**< - 3.0 [%] (down spread) */
} cy_en_pll_400M_ssgc_depth_t;
typedef enum
{
CY_SYSCLK_SSCG_RATE_DIV_4096 = 0u, /**< Modulation rate = fPFD/4096 */
CY_SYSCLK_SSCG_RATE_DIV_2048 = 1u, /**< Modulation rate = fPFD/2048 */
CY_SYSCLK_SSCG_RATE_DIV_1024 = 2u, /**< Modulation rate = fPFD/1024 */
CY_SYSCLK_SSCG_RATE_DIV_512 = 3u, /**< Modulation rate = fPFD/512 */
CY_SYSCLK_SSCG_RATE_DIV_256 = 4u, /**< Modulation rate = fPFD/256 */
} cy_en_pll_400M_ssgc_rate_t;
static const cy_stc_pll_manual_config_t srss_0_clock_0_pll400m_0_pllConfig =
{
.feedbackDiv = 25,
.referenceDiv = 1,
.outputDiv = 2,
.lfMode = false,
.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
.fracDiv = 0,
.fracDitherEn = false,
.fracEn = false,
.sscgEn = false,
.sscgRate = CY_SYSCLK_SSCG_RATE_DIV_4096,
.sscgDepth = CY_SYSCLK_SSCG_DEPTH_MINUS_0_5,
};
static const cy_stc_pll_manual_config_t srss_0_clock_0_pll400m_1_pllConfig =
{
.feedbackDiv = 25,
.referenceDiv = 1,
.outputDiv = 2,
.lfMode = false,
.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
.fracDiv = 0,
.fracDitherEn = false,
.fracEn = false,
.sscgEn = false,
.sscgRate = CY_SYSCLK_SSCG_RATE_DIV_4096,
.sscgDepth = CY_SYSCLK_SSCG_DEPTH_MINUS_0_5,
};
#if (!defined(CY_DEVICE_SECURE))
static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig =
{
.feedbackDiv = 48,
.referenceDiv = 3,
.outputDiv = 2,
.lfMode = false,
.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
};
static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_1_pllConfig =
{
.feedbackDiv = 60,
.referenceDiv = 3,
.outputDiv = 2,
.lfMode = false,
.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
};
#endif /* (!defined(CY_DEVICE_SECURE)) */
__WEAK void cycfg_ClockStartupError(uint32_t error);
#if !defined (CY_CFG_SYSCLK_ILO0_ENABLED)
__STATIC_INLINE void Cy_SysClk_Ilo0DeInit(void);
#endif /* !defined (CY_CFG_SYSCLK_ILO0_ENABLED) */
#if !defined (CY_CFG_SYSCLK_ILO1_ENABLED)
__STATIC_INLINE void Cy_SysClk_Ilo1DeInit(void);
#endif /* !defined (CY_CFG_SYSCLK_ILO1_ENABLED) */
#if ((!defined(CY_DEVICE_SECURE)))
__STATIC_INLINE void Cy_SysClk_FllDeInit(void);
#endif /* ((!defined(CY_DEVICE_SECURE))) */
#if (CY_CPU_CORTEX_M7)
__STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit(void);
#endif /* (CY_CPU_CORTEX_M7) */
#if (!defined(CY_DEVICE_SECURE))
__STATIC_INLINE void Cy_SysClk_ClkBakInit(void);
__STATIC_INLINE void Cy_SysClk_EcoInit(void);
#endif /* (!defined(CY_DEVICE_SECURE)) */
__STATIC_INLINE void Cy_SysClk_ClkFast_0_Init(void);
__STATIC_INLINE void Cy_SysClk_ClkFast_1_Init(void);
#if (!defined(CY_DEVICE_SECURE))
__STATIC_INLINE void Cy_SysClk_FllInit(void);
#endif /* (!defined(CY_DEVICE_SECURE)) */
__STATIC_INLINE void Cy_SysClk_ClkHf0Init(void);
__STATIC_INLINE void Cy_SysClk_ClkHf1Init(void);
__STATIC_INLINE void Cy_SysClk_ClkHf2Init(void);
__STATIC_INLINE void Cy_SysClk_ClkHf3Init(void);
__STATIC_INLINE void Cy_SysClk_ClkHf4Init(void);
__STATIC_INLINE void Cy_SysClk_ClkHf5Init(void);
__STATIC_INLINE void Cy_SysClk_ClkHf6Init(void);
__STATIC_INLINE void Cy_SysClk_ClkHf7Init(void);
#if (!defined(CY_DEVICE_SECURE))
__STATIC_INLINE void Cy_SysClk_Ilo0Init(void);
__STATIC_INLINE void Cy_SysClk_Ilo1Init(void);
#endif /* (!defined(CY_DEVICE_SECURE)) */
__STATIC_INLINE void Cy_SysClk_ClkLfInit(void);
__STATIC_INLINE void Cy_SysClk_ClkMemInit(void);
#if (!defined(CY_DEVICE_SECURE))
__STATIC_INLINE void Cy_SysClk_ClkPath0Init(void);
__STATIC_INLINE void Cy_SysClk_ClkPath1Init(void);
__STATIC_INLINE void Cy_SysClk_ClkPath2Init(void);
__STATIC_INLINE void Cy_SysClk_ClkPath3Init(void);
__STATIC_INLINE void Cy_SysClk_ClkPath4Init(void);
__STATIC_INLINE void Cy_SysClk_ClkPath5Init(void);
__STATIC_INLINE void Cy_SysClk_ClkPath6Init(void);
__STATIC_INLINE void Cy_SysClk_ClkPeriInit(void);
#endif /* (!defined(CY_DEVICE_SECURE)) */
__STATIC_INLINE void Cy_SysClk_Pll0Init(void);
__STATIC_INLINE void Cy_SysClk_Pll1Init(void);
__STATIC_INLINE void Cy_SysClk_Pll2Init(void);
__STATIC_INLINE void Cy_SysClk_Pll3Init(void);
#if (!defined(CY_DEVICE_SECURE))
__STATIC_INLINE void Cy_SysClk_ClkSlowInit(void);
#endif /* (!defined(CY_DEVICE_SECURE)) */
__STATIC_INLINE void init_cycfg_power(void);
__WEAK void cycfg_ClockStartupError(uint32_t error)
{
(void)error; /* Suppress the compiler warning */
while(1);
}
#if !defined (CY_CFG_SYSCLK_ILO0_ENABLED)
__STATIC_INLINE void Cy_SysClk_Ilo0DeInit(void)
{
if(Cy_SysPm_IsBgRefCtrl())
{
Cy_SysPm_BgRefCtrl(false);
Cy_WDT_Unlock();
Cy_SysClk_IloSrcDisable(0);
Cy_SysClk_IloSrcHibernateOn(0, false);
Cy_WDT_Lock();
Cy_SysPm_BgRefCtrl(true);
}
else
{
Cy_WDT_Unlock();
Cy_SysClk_IloSrcDisable(0);
Cy_SysClk_IloSrcHibernateOn(0, false);
Cy_WDT_Lock();
}
}
#endif /* !defined (CY_CFG_SYSCLK_ILO0_ENABLED) */
#if !defined (CY_CFG_SYSCLK_ILO1_ENABLED)
__STATIC_INLINE void Cy_SysClk_Ilo1DeInit(void)
{
Cy_SysClk_IloSrcDisable(1);
Cy_SysClk_IloSrcHibernateOn(1, false);
}
#endif /* !defined (CY_CFG_SYSCLK_ILO1_ENABLED) */
#if ((!defined(CY_DEVICE_SECURE)))
__STATIC_INLINE void Cy_SysClk_FllDeInit(void)
{
Cy_SysClk_FllDisable();
}
#endif /* ((!defined(CY_DEVICE_SECURE))) */
#if (CY_CPU_CORTEX_M7)
__STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit(void)
{
Cy_SysTick_Init(CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE, CY_CFG_SYSCLK_CLKALTSYSTICK_TICKS);
}
#endif /* (CY_CPU_CORTEX_M7) */
#if (!defined(CY_DEVICE_SECURE))
__STATIC_INLINE void Cy_SysClk_ClkBakInit(void)
{
Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_CLKLF);
}
__STATIC_INLINE void Cy_SysClk_EcoInit(void)
{
(void)Cy_GPIO_Pin_FastInit(GPIO_PRT21, 2, CY_GPIO_DM_ANALOG, 0UL, HSIOM_SEL_GPIO);
(void)Cy_GPIO_Pin_FastInit(GPIO_PRT21, 3, CY_GPIO_DM_ANALOG, 0UL, HSIOM_SEL_GPIO);
if (CY_SYSCLK_BAD_PARAM == Cy_SysClk_EcoConfigure(CY_CFG_SYSCLK_ECO_FREQ, 15UL, 50UL, 100UL))
{
cycfg_ClockStartupError(CY_CFG_SYSCLK_ECO_ERROR);
}
if (CY_SYSCLK_TIMEOUT == Cy_SysClk_EcoEnable(3000UL))
{
cycfg_ClockStartupError(CY_CFG_SYSCLK_ECO_ERROR);
}
}
#endif /* (!defined(CY_DEVICE_SECURE)) */
__STATIC_INLINE void Cy_SysClk_ClkFast_0_Init(void)
{
Cy_SysClk_ClkFastSrcSetDivider(0, CY_CFG_SYSCLK_CLKFAST_0_INT_DIVIDER, CY_CFG_SYSCLK_CLKFAST_0_FRAC_DIVIDER);
}
__STATIC_INLINE void Cy_SysClk_ClkFast_1_Init(void)
{
Cy_SysClk_ClkFastSrcSetDivider(1, CY_CFG_SYSCLK_CLKFAST_1_INT_DIVIDER, CY_CFG_SYSCLK_CLKFAST_1_FRAC_DIVIDER);
}
#if (!defined(CY_DEVICE_SECURE))
__STATIC_INLINE void Cy_SysClk_FllInit(void)
{
if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllManualConfigure(&srss_0_clock_0_fll_0_fllConfig))
{
cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR);
}
if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(200000UL))
{
cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR);
}
}
#endif /* (!defined(CY_DEVICE_SECURE)) */
__STATIC_INLINE void Cy_SysClk_ClkHf0Init(void)
{
Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH);
Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
Cy_SysClk_ClkHfDirectSel(CY_CFG_SYSCLK_CLKHF0, false);
}
__STATIC_INLINE void Cy_SysClk_ClkHf1Init(void)
{
Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF1, CY_CFG_SYSCLK_CLKHF1_CLKPATH);
Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF1, CY_SYSCLK_CLKHF_NO_DIVIDE);
Cy_SysClk_ClkHfDirectSel(CY_CFG_SYSCLK_CLKHF1, false);
Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF1);
}
__STATIC_INLINE void Cy_SysClk_ClkHf2Init(void)
{
Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF2, CY_CFG_SYSCLK_CLKHF2_CLKPATH);
Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF2, CY_SYSCLK_CLKHF_DIVIDE_BY_2);
Cy_SysClk_ClkHfDirectSel(CY_CFG_SYSCLK_CLKHF2, false);
Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF2);
}
__STATIC_INLINE void Cy_SysClk_ClkHf3Init(void)
{
Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF3, CY_CFG_SYSCLK_CLKHF3_CLKPATH);
Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF3, CY_SYSCLK_CLKHF_DIVIDE_BY_2);
Cy_SysClk_ClkHfDirectSel(CY_CFG_SYSCLK_CLKHF3, false);
Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF3);
}
__STATIC_INLINE void Cy_SysClk_ClkHf4Init(void)
{
Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF4, CY_CFG_SYSCLK_CLKHF4_CLKPATH);
Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF4, CY_SYSCLK_CLKHF_DIVIDE_BY_4);
Cy_SysClk_ClkHfDirectSel(CY_CFG_SYSCLK_CLKHF4, false);
Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF4);
}
__STATIC_INLINE void Cy_SysClk_ClkHf5Init(void)
{
Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF5, CY_CFG_SYSCLK_CLKHF5_CLKPATH);
Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF5, CY_SYSCLK_CLKHF_DIVIDE_BY_2);
Cy_SysClk_ClkHfDirectSel(CY_CFG_SYSCLK_CLKHF5, false);
Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF5);
}
__STATIC_INLINE void Cy_SysClk_ClkHf6Init(void)
{
Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF6, CY_CFG_SYSCLK_CLKHF6_CLKPATH);
Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF6, CY_SYSCLK_CLKHF_NO_DIVIDE);
Cy_SysClk_ClkHfDirectSel(CY_CFG_SYSCLK_CLKHF6, false);
Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF6);
}
__STATIC_INLINE void Cy_SysClk_ClkHf7Init(void)
{
Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF7, CY_CFG_SYSCLK_CLKHF7_CLKPATH);
Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF7, CY_SYSCLK_CLKHF_NO_DIVIDE);
Cy_SysClk_ClkHfDirectSel(CY_CFG_SYSCLK_CLKHF7, false);
Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF7);
}
#if (!defined(CY_DEVICE_SECURE))
__STATIC_INLINE void Cy_SysClk_Ilo0Init(void)
{
/* The WDT is unlocked in the default startup code */
Cy_SysClk_IloSrcEnable(0);
Cy_SysClk_IloSrcHibernateOn(0, true);
}
__STATIC_INLINE void Cy_SysClk_Ilo1Init(void)
{
/* The WDT is unlocked in the default startup code */
Cy_SysClk_IloSrcEnable(1);
Cy_SysClk_IloSrcHibernateOn(1, true);
}
#endif /* (!defined(CY_DEVICE_SECURE)) */
__STATIC_INLINE void Cy_SysClk_ClkLfInit(void)
{
/* The WDT is unlocked in the default startup code */
Cy_SysClk_ClkLfSetSource(CY_CFG_SYSCLK_CLKLF_SOURCE);
}
__STATIC_INLINE void Cy_SysClk_ClkMemInit(void)
{
Cy_SysClk_ClkMemSetDivider(0U);
}
#if (!defined(CY_DEVICE_SECURE))
__STATIC_INLINE void Cy_SysClk_ClkPath0Init(void)
{
Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE);
}
__STATIC_INLINE void Cy_SysClk_ClkPath1Init(void)
{
Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE);
}
__STATIC_INLINE void Cy_SysClk_ClkPath2Init(void)
{
Cy_SysClk_ClkPathSetSource(2U, CY_CFG_SYSCLK_CLKPATH2_SOURCE);
}
__STATIC_INLINE void Cy_SysClk_ClkPath3Init(void)
{
Cy_SysClk_ClkPathSetSource(3U, CY_CFG_SYSCLK_CLKPATH3_SOURCE);
}
__STATIC_INLINE void Cy_SysClk_ClkPath4Init(void)
{
Cy_SysClk_ClkPathSetSource(4U, CY_CFG_SYSCLK_CLKPATH4_SOURCE);
}
__STATIC_INLINE void Cy_SysClk_ClkPath5Init(void)
{
Cy_SysClk_ClkPathSetSource(5U, CY_CFG_SYSCLK_CLKPATH5_SOURCE);
}
__STATIC_INLINE void Cy_SysClk_ClkPath6Init(void)
{
Cy_SysClk_ClkPathSetSource(6U, CY_CFG_SYSCLK_CLKPATH6_SOURCE);
}
__STATIC_INLINE void Cy_SysClk_ClkPeriInit(void)
{
Cy_SysClk_ClkPeriSetDivider(0U);
}
#endif /* (!defined(CY_DEVICE_SECURE)) */
__STATIC_INLINE void Cy_SysClk_Pll0Init(void)
{
Cy_SysClk_PllDisable(SRSS_PLL_400M_0_PATH_NUM);
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(SRSS_PLL_400M_0_PATH_NUM, &srss_0_clock_0_pll400m_0_pllConfig))
{
cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
}
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(SRSS_PLL_400M_0_PATH_NUM, 10000u))
{
cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
}
}
__STATIC_INLINE void Cy_SysClk_Pll1Init(void)
{
Cy_SysClk_PllDisable(SRSS_PLL_400M_1_PATH_NUM);
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(SRSS_PLL_400M_1_PATH_NUM, &srss_0_clock_0_pll400m_1_pllConfig))
{
cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
}
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(SRSS_PLL_400M_1_PATH_NUM, 10000u))
{
cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
}
}
__STATIC_INLINE void Cy_SysClk_Pll2Init(void)
{
Cy_SysClk_PllDisable(SRSS_PLL_200M_0_PATH_NUM);
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(SRSS_PLL_200M_0_PATH_NUM, &srss_0_clock_0_pll_0_pllConfig))
{
cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
}
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(SRSS_PLL_200M_0_PATH_NUM, 10000u))
{
cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
}
}
__STATIC_INLINE void Cy_SysClk_Pll3Init(void)
{
Cy_SysClk_PllDisable(SRSS_PLL_200M_1_PATH_NUM);
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(SRSS_PLL_200M_1_PATH_NUM, &srss_0_clock_0_pll_1_pllConfig))
{
cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
}
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(SRSS_PLL_200M_1_PATH_NUM, 10000u))
{
cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
}
}
#if (!defined(CY_DEVICE_SECURE))
__STATIC_INLINE void Cy_SysClk_ClkSlowInit(void)
{
Cy_SysClk_ClkSlowSetDivider(0U);
}
#endif /* (!defined(CY_DEVICE_SECURE)) */
__STATIC_INLINE void init_cycfg_power(void)
{
/* **Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD** */
#if (CY_CFG_PWR_VBACKUP_USING_VDDD)
#ifdef CY_CFG_SYSCLK_ILO_ENABLED
if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */)
{
Cy_SysLib_ResetBackupDomain();
Cy_SysClk_IloDisable();
Cy_SysClk_IloInit();
}
#endif /* CY_CFG_SYSCLK_ILO_ENABLED */
#endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */
/* **REGHC Configuration** */
#if (CY_CFG_PWR_REGHC_ENABLED)
Cy_SysPm_ReghcConfigure(CY_CFG_PWR_REGHC_MODE, CY_CFG_PWR_REGHC_TRANS_VADJ_VOLT);
#endif /* CY_CFG_PWR_REGHC_ENABLED */
/* **System Active Low Power Profile(LPACTIVE/LPSLEEP) Configuration** */
#if (CY_CFG_PWR_SYS_LP_PROFILE_MODE)
Cy_SysPm_SystemLpActiveEnter();
#endif /* CY_CFG_PWR_SYS_ACTIVE_MODE */
/* **System Regulators Low Current Configuration** */
#if CY_CFG_PWR_REGULATOR_MODE_MIN
Cy_SysPm_SystemSetMinRegulatorCurrent();
#else
Cy_SysPm_SystemSetNormalRegulatorCurrent();
#endif /* CY_CFG_PWR_REGULATOR_MODE_MIN */
}
void init_cycfg_system(void)
{
Cy_SysClk_PeriPclkAssignDivider(PCLK_CPUSS_CLOCK_TRACE_IN, CY_SYSCLK_DIV_8_BIT, 2U);
/* Set worst case memory wait states (! ultra low power, 180 MHz), will update at the end */
Cy_SysLib_SetWaitStates(false, 180UL);
#ifdef CY_CFG_PWR_ENABLED
#ifdef CY_CFG_PWR_INIT
init_cycfg_power();
#else
#warning Power system will not be configured. Update power personality to v1.20 or later.
#endif /* CY_CFG_PWR_INIT */
#endif /* CY_CFG_PWR_ENABLED */
/* Disable FLL */
Cy_SysClk_FllDeInit();
/* Enable all source clocks */
#ifdef CY_CFG_SYSCLK_ILO0_ENABLED
Cy_SysClk_Ilo0Init();
#else
Cy_SysClk_Ilo0DeInit();
#endif
#ifdef CY_CFG_SYSCLK_ILO1_ENABLED
Cy_SysClk_Ilo1Init();
#else
Cy_SysClk_Ilo1DeInit();
#endif
#ifdef CY_CFG_SYSCLK_PILO_ENABLED
Cy_SysClk_PiloInit();
#endif
#ifdef CY_CFG_SYSCLK_WCO_ENABLED
Cy_SysClk_WcoInit();
#endif
#ifdef CY_CFG_SYSCLK_ECO_ENABLED
Cy_SysClk_EcoInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKLF_ENABLED
Cy_SysClk_ClkLfInit();
#endif
#ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED
Cy_SysClk_ExtClkInit();
#endif
#ifdef CY_CFG_SYSCLK_ALTHF_ENABLED
Cy_SysClk_AltHfInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED
Cy_SysClk_ClkPeriInit();
#endif
/* Configure Path Clocks */
#ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
Cy_SysClk_ClkPath1Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED
Cy_SysClk_ClkPath2Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED
Cy_SysClk_ClkPath3Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED
Cy_SysClk_ClkPath4Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED
Cy_SysClk_ClkPath5Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED
Cy_SysClk_ClkPath6Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED
Cy_SysClk_ClkPath7Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED
Cy_SysClk_ClkPath8Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED
Cy_SysClk_ClkPath9Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED
Cy_SysClk_ClkPath10Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED
Cy_SysClk_ClkPath11Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED
Cy_SysClk_ClkPath12Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED
Cy_SysClk_ClkPath13Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED
Cy_SysClk_ClkPath14Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED
Cy_SysClk_ClkPath15Init();
#endif
/* Configure and enable PLLs */
#ifdef CY_CFG_SYSCLK_PLL0_ENABLED
Cy_SysClk_Pll0Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL1_ENABLED
Cy_SysClk_Pll1Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL2_ENABLED
Cy_SysClk_Pll2Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL3_ENABLED
Cy_SysClk_Pll3Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL4_ENABLED
Cy_SysClk_Pll4Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL5_ENABLED
Cy_SysClk_Pll5Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL6_ENABLED
Cy_SysClk_Pll6Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL7_ENABLED
Cy_SysClk_Pll7Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL8_ENABLED
Cy_SysClk_Pll8Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL9_ENABLED
Cy_SysClk_Pll9Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL10_ENABLED
Cy_SysClk_Pll10Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL11_ENABLED
Cy_SysClk_Pll11Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL12_ENABLED
Cy_SysClk_Pll12Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL13_ENABLED
Cy_SysClk_Pll13Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL14_ENABLED
Cy_SysClk_Pll14Init();
#endif
/* Configure HF clocks */
#ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED
Cy_SysClk_ClkHf1Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED
Cy_SysClk_ClkHf2Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED
Cy_SysClk_ClkHf3Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED
Cy_SysClk_ClkHf4Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED
Cy_SysClk_ClkHf5Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED
Cy_SysClk_ClkHf6Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED
Cy_SysClk_ClkHf7Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED
Cy_SysClk_ClkHf8Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED
Cy_SysClk_ClkHf9Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED
Cy_SysClk_ClkHf10Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED
Cy_SysClk_ClkHf11Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED
Cy_SysClk_ClkHf12Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED
Cy_SysClk_ClkHf13Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED
Cy_SysClk_ClkHf14Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED
Cy_SysClk_ClkHf15Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED
Cy_SysClk_ClkAltSysTickInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED
Cy_SysClk_ClkPumpInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED
Cy_SysClk_ClkBakInit();
#endif
/* Configure default enabled clocks */
#ifdef CY_CFG_SYSCLK_ILO_ENABLED
Cy_SysClk_IloInit();
#endif
#ifndef CY_CFG_SYSCLK_IMO_ENABLED
#error the IMO must be enabled for proper chip operation
#endif
#ifdef CY_CFG_SYSCLK_MFO_ENABLED
Cy_SysClk_MfoInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKMF_ENABLED
Cy_SysClk_ClkMfInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKPWR_ENABLED
Cy_SysClk_ClkPwrInit();
#endif
/* Set accurate flash wait states */
#if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF1_ENABLED))
Cy_SysLib_SetWaitStates(false, CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ);
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED
Cy_SysClk_ClkPath0Init();
#endif
/* Configure and enable FLL */
#ifdef CY_CFG_SYSCLK_FLL_ENABLED
Cy_SysClk_FllInit();
#endif
Cy_SysClk_ClkHf0Init();
#ifdef CY_CFG_SYSCLK_CLKFAST_0_ENABLED
Cy_SysClk_ClkFast_0_Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKFAST_1_ENABLED
Cy_SysClk_ClkFast_1_Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED
Cy_SysClk_ClkSlowInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKMEM_ENABLED
Cy_SysClk_ClkMemInit();
#endif
#if defined(CY_CFG_SYSCLK_ECO_PRESCALER_ENABLED)
Cy_SysClk_EcoPrescalerInit();
#endif /* defined(CY_CFG_SYSCLK_ECO_PRESCALER_ENABLED) */
#ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED
Cy_SysClk_ClkAltSysTickInit();
#endif
/* Update System Core Clock values for correct Cy_SysLib_Delay functioning */
SystemCoreClockUpdate();
/* Configure HF clocks CSV */
#ifdef CY_CFG_SYSCLK_CLKHF0_CSV_ENABLED
Cy_SysClk_ClkHf0CsvInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF1_CSV_ENABLED
Cy_SysClk_ClkHf1CsvInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF2_CSV_ENABLED
Cy_SysClk_ClkHf2CsvInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF3_CSV_ENABLED
Cy_SysClk_ClkHf3CsvInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF4_CSV_ENABLED
Cy_SysClk_ClkHf4CsvInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF5_CSV_ENABLED
Cy_SysClk_ClkHf5CsvInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF6_CSV_ENABLED
Cy_SysClk_ClkHf6CsvInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF7_CSV_ENABLED
Cy_SysClk_ClkHf7CsvInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF8_CSV_ENABLED
Cy_SysClk_ClkHf8CsvInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF9_CSV_ENABLED
Cy_SysClk_ClkHf9CsvInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF10CSV_ENABLED
Cy_SysClk_ClkHf10CsvInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF11_CSV_ENABLED
Cy_SysClk_ClkHf11CsvInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF12_CSV_ENABLED
Cy_SysClk_ClkHf12CsvInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF13_CSV_ENABLED
Cy_SysClk_ClkHf13CsvInit();
#endif
/* Configure LF clocks CSV */
#ifdef CY_CFG_SYSCLK_CLKLF_CSV_ENABLED
Cy_SysClk_ClkLfCsvInit();
#endif
#if defined (CY_USING_HAL)
if(CY_RSLT_SUCCESS != (cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj)))
{
CY_HALT();
}
if(CY_RSLT_SUCCESS != (cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj)))
{
CY_HALT();
}
if(CY_RSLT_SUCCESS != (cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj)))
{
CY_HALT();
}
if(CY_RSLT_SUCCESS != (cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj)))
{
CY_HALT();
}
if(CY_RSLT_SUCCESS != (cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj)))
{
CY_HALT();
}
if(CY_RSLT_SUCCESS != (cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_5_obj)))
{
CY_HALT();
}
if(CY_RSLT_SUCCESS != (cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_6_obj)))
{
CY_HALT();
}
#endif /* defined (CY_USING_HAL) */
}
void reserve_cycfg_system(void)
{
Cy_SysClk_EcoSetFrequency(CY_CFG_SYSCLK_ECO_FREQ);
SystemCoreClockUpdate();
}

138
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/*******************************************************************************
* File Name: cycfg_system.h
*
* Description:
* System configuration
* This file was automatically generated and should not be modified.
* Configurator Backend 3.50.0
* device-db 4.22.0.7873
* mtb-pdl-cat1 3.15.0.40227
*
*******************************************************************************
* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
******************************************************************************/
#if !defined(CYCFG_SYSTEM_H)
#define CYCFG_SYSTEM_H
#include "cycfg_notices.h"
#include "cy_sysclk.h"
#include "cy_wdt.h"
#include "cy_systick.h"
#include "cy_gpio.h"
#include "cy_syspm.h"
#if defined (CY_USING_HAL)
#include "cyhal_hwmgr.h"
#endif /* defined (CY_USING_HAL) */
#if defined(__cplusplus)
extern "C" {
#endif /* defined(__cplusplus) */
#define cpuss_0_dap_0_ENABLED 1U
#define srss_0_clock_0_ENABLED 1U
#define srss_0_clock_0_altsystickclk_0_ENABLED 1U
#define srss_0_clock_0_bakclk_0_ENABLED 1U
#define srss_0_clock_0_eco_0_ENABLED 1U
#define srss_0_clock_0_fastclk_0_ENABLED 1U
#define srss_0_clock_0_fastclk_1_ENABLED 1U
#define srss_0_clock_0_fll_0_ENABLED 1U
#define srss_0_clock_0_hfclk_0_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF0 0UL
#define CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM 0UL
#define srss_0_clock_0_hfclk_1_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF1 1UL
#define CY_CFG_SYSCLK_CLKHF1_CLKPATH_NUM 1UL
#define srss_0_clock_0_hfclk_2_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF2 2UL
#define CY_CFG_SYSCLK_CLKHF2_CLKPATH_NUM 4UL
#define srss_0_clock_0_hfclk_3_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF3 3UL
#define CY_CFG_SYSCLK_CLKHF3_CLKPATH_NUM 4UL
#define srss_0_clock_0_hfclk_4_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF4 4UL
#define CY_CFG_SYSCLK_CLKHF4_CLKPATH_NUM 4UL
#define srss_0_clock_0_hfclk_5_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF5 5UL
#define CY_CFG_SYSCLK_CLKHF5_CLKPATH_NUM 2UL
#define srss_0_clock_0_hfclk_6_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF6 6UL
#define CY_CFG_SYSCLK_CLKHF6_CLKPATH_NUM 4UL
#define srss_0_clock_0_hfclk_7_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF7 7UL
#define CY_CFG_SYSCLK_CLKHF7_CLKPATH_NUM 5UL
#define srss_0_clock_0_ilo_0_ENABLED 1U
#define srss_0_clock_0_ilo_1_ENABLED 1U
#define srss_0_clock_0_imo_0_ENABLED 1U
#define srss_0_clock_0_lfclk_0_ENABLED 1U
#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768
#define CY_CFG_SYSCLK_CLKLF_SOURCE CY_SYSCLK_CLKLF_IN_ILO
#define srss_0_clock_0_memclk_0_ENABLED 1U
#define srss_0_clock_0_pathmux_0_ENABLED 1U
#define srss_0_clock_0_pathmux_1_ENABLED 1U
#define srss_0_clock_0_pathmux_2_ENABLED 1U
#define srss_0_clock_0_pathmux_3_ENABLED 1U
#define srss_0_clock_0_pathmux_4_ENABLED 1U
#define srss_0_clock_0_pathmux_5_ENABLED 1U
#define srss_0_clock_0_pathmux_6_ENABLED 1U
#define srss_0_clock_0_periclk_0_ENABLED 1U
#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1
#define CY_CFG_SYSCLK_CLKPERI_DIVIDER 0
#define srss_0_clock_0_pll400m_0_ENABLED 1U
#define srss_0_clock_0_pll400m_1_ENABLED 1U
#define srss_0_clock_0_pll_0_ENABLED 1U
#define srss_0_clock_0_pll_1_ENABLED 1U
#define srss_0_clock_0_slowclk_0_ENABLED 1U
#define srss_0_clock_0_timerclk_0_ENABLED 1U
#define srss_0_power_0_ENABLED 1U
#define CY_CFG_PWR_MODE_LP 0x01UL
#define CY_CFG_PWR_MODE_ULP 0x02UL
#define CY_CFG_PWR_MODE_ACTIVE 0x04UL
#define CY_CFG_PWR_MODE_SLEEP 0x08UL
#define CY_CFG_PWR_MODE_DEEPSLEEP 0x10UL
#define CY_CFG_PWR_MODE_DEEPSLEEP_RAM 0x11UL
#define CY_CFG_PWR_MODE_DEEPSLEEP_OFF 0x12UL
#define CY_CFG_PWR_SYS_IDLE_MODE CY_CFG_PWR_MODE_DEEPSLEEP
#define CY_CFG_PWR_DEEPSLEEP_LATENCY 0UL
#define CY_CFG_PWR_SYS_LP_PROFILE_MODE 0
#define CY_CFG_PWR_VDDA_MV 3300
#define CY_CFG_PWR_VDDD_MV 3300
#define CY_CFG_PWR_VDDIO0_MV 3300
#define CY_CFG_PWR_VDDIO1_MV 3300
#define CY_CFG_PWR_REGHC_ENABLED false
#define CY_CFG_PWR_REGHC_MODE 255
#define CY_CFG_PWR_REGHC_TRANS_VADJ_VOLT 0
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj;
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj;
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj;
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj;
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj;
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_5_obj;
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_6_obj;
#endif /* defined (CY_USING_HAL) */
void init_cycfg_system(void);
void reserve_cycfg_system(void);
#if defined(__cplusplus)
}
#endif /* defined(__cplusplus) */
#endif /* CYCFG_SYSTEM_H */

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bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/GeneratedSource/qspi_config.cfg Normal file
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################################################################################
# File Name: qspi_config.cfg
#
# Description:
# This file contains a SMIF Bank layout for use with OpenOCD.
# This file was automatically generated and should not be modified.
# QSPI Configurator: 4.50.0.2481
#
################################################################################
# Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
# an affiliate of Cypress Semiconductor Corporation.
# SPDX-License-Identifier: Apache-2.0
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
################################################################################
set SMIF_BANKS {
1 {addr 0x60000000 size 0x10000 psize 0x0000100 esize 0x0040000}
}

70
bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/config/design.cyqspi Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!--This file should not be modified. It was automatically generated by QSPI Configurator 4.10.0.1343-->
<Configuration app="QSPI" formatVersion="2" lastSavedWith="QSPI Configurator" lastSavedWithVersion="4.10.0" toolsPackage="ModusToolbox 3.1.0" xmlns="http://cypress.com/xsd/cyconfigurationfile_v1">
<DevicePath>cat1c.xml</DevicePath>
<FlashloaderDir>FlashLoaders</FlashloaderDir>
<FlashloaderProgramChunkSize>4096</FlashloaderProgramChunkSize>
<FlashloaderEraseChunkSize>262144</FlashloaderEraseChunkSize>
<SlotConfigs>
<SlotConfig>
<SlaveSlot>0</SlaveSlot>
<MemoryId>Not used</MemoryId>
<MemoryMapped>true</MemoryMapped>
<DualQuad>None</DualQuad>
<StartAddress>0x60000000</StartAddress>
<Size>0x800000</Size>
<EndAddress>0x607FFFFF</EndAddress>
<WriteEnable>true</WriteEnable>
<Encrypt>false</Encrypt>
<DataSelect>QUAD_SPI_DATA_0_3</DataSelect>
<MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
<ConfigDataInFlash>false</ConfigDataInFlash>
<MergeTimeout>CY_SMIF_MERGE_TIMEOUT_DISABLED</MergeTimeout>
</SlotConfig>
<SlotConfig>
<SlaveSlot>1</SlaveSlot>
<MemoryId>S25HL512T (Uniform)</MemoryId>
<MemoryMapped>true</MemoryMapped>
<DualQuad>None</DualQuad>
<StartAddress>0x60000000</StartAddress>
<Size>0x10000</Size>
<EndAddress>0x6000FFFF</EndAddress>
<WriteEnable>true</WriteEnable>
<Encrypt>false</Encrypt>
<DataSelect>QUAD_SPI_DATA_0_3</DataSelect>
<MemoryConfigsPath>S25HL512T (Uniform)</MemoryConfigsPath>
<ConfigDataInFlash>false</ConfigDataInFlash>
<MergeTimeout>CY_SMIF_MERGE_TIMEOUT_DISABLED</MergeTimeout>
</SlotConfig>
<SlotConfig>
<SlaveSlot>2</SlaveSlot>
<MemoryId>Not used</MemoryId>
<MemoryMapped>false</MemoryMapped>
<DualQuad>None</DualQuad>
<StartAddress>0x60000000</StartAddress>
<Size>0x10000</Size>
<EndAddress>0x6000FFFF</EndAddress>
<WriteEnable>false</WriteEnable>
<Encrypt>false</Encrypt>
<DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
<MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
<ConfigDataInFlash>false</ConfigDataInFlash>
<MergeTimeout>CY_SMIF_MERGE_TIMEOUT_DISABLED</MergeTimeout>
</SlotConfig>
<SlotConfig>
<SlaveSlot>3</SlaveSlot>
<MemoryId>Not used</MemoryId>
<MemoryMapped>false</MemoryMapped>
<DualQuad>None</DualQuad>
<StartAddress>0x60000000</StartAddress>
<Size>0x10000</Size>
<EndAddress>0x6000FFFF</EndAddress>
<WriteEnable>false</WriteEnable>
<Encrypt>false</Encrypt>
<DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
<MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
<ConfigDataInFlash>false</ConfigDataInFlash>
<MergeTimeout>CY_SMIF_MERGE_TIMEOUT_DISABLED</MergeTimeout>
</SlotConfig>
</SlotConfigs>
</Configuration>

930
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<?xml version="1.0" encoding="UTF-8"?>
<Configuration app="BACKEND" formatVersion="14" lastSavedWith="Configurator Backend" lastSavedWithVersion="3.50.0" toolsPackage="ModusToolbox 3.5.0" xmlns="http://cypress.com/xsd/cydesignfile_v5">
<Devices>
<Device mpn="XMC7100D-F144K4160">
<BlockConfig>
<Block location="ioss[0].port[0].pin[0]">
<Aliases>
<Alias value="CYBSP_D2"/>
<Alias value="CYBSP_S2G1_INT"/>
<Alias value="CYBSP_S2G2_INT"/>
</Aliases>
</Block>
<Block location="ioss[0].port[0].pin[1]">
<Aliases>
<Alias value="CYBSP_D3"/>
</Aliases>
</Block>
<Block location="ioss[0].port[0].pin[2]">
<Aliases>
<Alias value="CYBSP_I2C_SCL"/>
<Alias value="CYBSP_S2G1_I2C_SCL"/>
<Alias value="CYBSP_MIKROBUS_I2C_SCL"/>
<Alias value="CYBSP_S2G2_I2C_SCL"/>
</Aliases>
</Block>
<Block location="ioss[0].port[0].pin[3]">
<Aliases>
<Alias value="CYBSP_I2C_SDA"/>
<Alias value="CYBSP_S2G1_I2C_SDA"/>
<Alias value="CYBSP_MIKROBUS_I2C_SDA"/>
<Alias value="CYBSP_S2G2_I2C_SDA"/>
</Aliases>
</Block>
<Block location="ioss[0].port[2].pin[2]">
<Aliases>
<Alias value="CYBSP_ETH_RX_ERR"/>
</Aliases>
</Block>
<Block location="ioss[0].port[3].pin[0]">
<Aliases>
<Alias value="CYBSP_ETH_MDIO"/>
</Aliases>
</Block>
<Block location="ioss[0].port[3].pin[1]">
<Aliases>
<Alias value="CYBSP_ETH_MDC"/>
</Aliases>
</Block>
<Block location="ioss[0].port[5].pin[1]">
<Aliases>
<Alias value="CYBSP_USER_LED2"/>
<Alias value="LED2"/>
</Aliases>
</Block>
<Block location="ioss[0].port[5].pin[2]">
<Aliases>
<Alias value="CYBSP_CANFD_STB"/>
</Aliases>
</Block>
<Block location="ioss[0].port[5].pin[3]">
<Aliases>
<Alias value="CYBSP_USER_BTN1"/>
<Alias value="CYBSP_USER_BTN"/>
</Aliases>
</Block>
<Block location="ioss[0].port[6].pin[0]">
<Aliases>
<Alias value="CYBSP_POT"/>
</Aliases>
</Block>
<Block location="ioss[0].port[6].pin[1]">
<Aliases>
<Alias value="CYBSP_D4"/>
</Aliases>
</Block>
<Block location="ioss[0].port[6].pin[3]">
<Aliases>
<Alias value="CYBSP_QSPI_SCK"/>
</Aliases>
</Block>
<Block location="ioss[0].port[6].pin[4]">
<Aliases>
<Alias value="CYBSP_FLASH_RST"/>
</Aliases>
</Block>
<Block location="ioss[0].port[7].pin[0]">
<Aliases>
<Alias value="CYBSP_QSPI_SS"/>
</Aliases>
</Block>
<Block location="ioss[0].port[7].pin[1]">
<Aliases>
<Alias value="CYBSP_QSPI_D0"/>
</Aliases>
</Block>
<Block location="ioss[0].port[7].pin[2]">
<Aliases>
<Alias value="CYBSP_QSPI_D1"/>
</Aliases>
</Block>
<Block location="ioss[0].port[7].pin[3]">
<Aliases>
<Alias value="CYBSP_QSPI_D2"/>
</Aliases>
</Block>
<Block location="ioss[0].port[7].pin[4]">
<Aliases>
<Alias value="CYBSP_QSPI_D3"/>
</Aliases>
</Block>
<Block location="ioss[0].port[7].pin[5]">
<Aliases>
<Alias value="CYBSP_USER_BUZZER"/>
</Aliases>
</Block>
<Block location="ioss[0].port[8].pin[0]">
<Aliases>
<Alias value="CYBSP_CAN_TX"/>
</Aliases>
</Block>
<Block location="ioss[0].port[8].pin[1]">
<Aliases>
<Alias value="CYBSP_CAN_RX"/>
</Aliases>
</Block>
<Block location="ioss[0].port[8].pin[2]">
<Aliases>
<Alias value="M1B"/>
</Aliases>
</Block>
<Block location="ioss[0].port[8].pin[3]">
<Aliases>
<Alias value="M1A"/>
</Aliases>
</Block>
<Block location="ioss[0].port[10].pin[0]">
<Aliases>
<Alias value="CYBSP_DEBUG_UART_RX"/>
</Aliases>
</Block>
<Block location="ioss[0].port[10].pin[1]">
<Aliases>
<Alias value="CYBSP_DEBUG_UART_TX"/>
</Aliases>
</Block>
<Block location="ioss[0].port[11].pin[0]">
<Aliases>
<Alias value="CYBSP_A1"/>
<Alias value="CYBSP_S2G1_GPIO1"/>
<Alias value="CYBSP_S2G2_GPIO1"/>
</Aliases>
</Block>
<Block location="ioss[0].port[11].pin[1]">
<Aliases>
<Alias value="CYBSP_A2"/>
<Alias value="CYBSP_MIKROBUS_INT"/>
</Aliases>
</Block>
<Block location="ioss[0].port[11].pin[2]">
<Aliases>
<Alias value="CYBSP_A3"/>
</Aliases>
</Block>
<Block location="ioss[0].port[12].pin[0]">
<Aliases>
<Alias value="CYBSP_MIKROBUS_UART_RX"/>
</Aliases>
</Block>
<Block location="ioss[0].port[12].pin[1]">
<Aliases>
<Alias value="CYBSP_MIKROBUS_UART_TX"/>
</Aliases>
</Block>
<Block location="ioss[0].port[12].pin[2]">
<Aliases>
<Alias value="CYBSP_D9"/>
</Aliases>
</Block>
<Block location="ioss[0].port[12].pin[3]">
<Aliases>
<Alias value="CYBSP_D8"/>
</Aliases>
</Block>
<Block location="ioss[0].port[13].pin[0]">
<Aliases>
<Alias value="CYBSP_SPI_MISO"/>
<Alias value="CYBSP_S2G1_SPI_MISO"/>
<Alias value="CYBSP_MIKROBUS_SPI_MISO"/>
<Alias value="CYBSP_S2G2_SPI_MISO"/>
</Aliases>
</Block>
<Block location="ioss[0].port[13].pin[1]">
<Aliases>
<Alias value="CYBSP_SPI_MOSI"/>
<Alias value="CYBSP_S2G1_SPI_MOSI"/>
<Alias value="CYBSP_MIKROBUS_SPI_MOSI"/>
<Alias value="CYBSP_S2G2_SPI_MOSI"/>
</Aliases>
</Block>
<Block location="ioss[0].port[13].pin[2]">
<Aliases>
<Alias value="CYBSP_SPI_CLK"/>
<Alias value="CYBSP_S2G1_SPI_SCK"/>
<Alias value="CYBSP_MIKROBUS_SPI_SCK"/>
<Alias value="CYBSP_S2G2_SPI_SCK"/>
</Aliases>
</Block>
<Block location="ioss[0].port[13].pin[3]">
<Aliases>
<Alias value="CYBSP_SPI_CS"/>
</Aliases>
</Block>
<Block location="ioss[0].port[13].pin[4]">
<Aliases>
<Alias value="CYBSP_MIKROBUS_SPI_CS"/>
</Aliases>
</Block>
<Block location="ioss[0].port[13].pin[5]">
<Aliases>
<Alias value="CYBSP_S2G2_SPI_CS"/>
</Aliases>
</Block>
<Block location="ioss[0].port[13].pin[6]">
<Aliases>
<Alias value="CYBSP_S2G1_SPI_CS"/>
</Aliases>
</Block>
<Block location="ioss[0].port[13].pin[7]">
<Aliases>
<Alias value="CYBSP_A4"/>
</Aliases>
</Block>
<Block location="ioss[0].port[14].pin[0]">
<Aliases>
<Alias value="CYBSP_S2G1_UART_RX"/>
<Alias value="CYBSP_S2G2_UART_RX"/>
</Aliases>
</Block>
<Block location="ioss[0].port[14].pin[1]">
<Aliases>
<Alias value="CYBSP_S2G1_UART_TX"/>
<Alias value="CYBSP_S2G2_UART_TX"/>
</Aliases>
</Block>
<Block location="ioss[0].port[18].pin[0]">
<Aliases>
<Alias value="CYBSP_ETH_REF_CLK"/>
</Aliases>
</Block>
<Block location="ioss[0].port[18].pin[1]">
<Aliases>
<Alias value="CYBSP_ETH_TX_CTL"/>
</Aliases>
</Block>
<Block location="ioss[0].port[18].pin[2]">
<Aliases>
<Alias value="CYBSP_MIKROBUS_AN"/>
</Aliases>
</Block>
<Block location="ioss[0].port[18].pin[4]">
<Aliases>
<Alias value="CYBSP_ETH_TXD_0"/>
</Aliases>
</Block>
<Block location="ioss[0].port[18].pin[5]">
<Aliases>
<Alias value="CYBSP_ETH_TXD_1"/>
</Aliases>
</Block>
<Block location="ioss[0].port[19].pin[0]">
<Aliases>
<Alias value="UART_RX"/>
</Aliases>
</Block>
<Block location="ioss[0].port[19].pin[1]">
<Aliases>
<Alias value="UART_TX"/>
</Aliases>
</Block>
<Block location="ioss[0].port[19].pin[3]">
<Aliases>
<Alias value="CYBSP_MIKROBUS_PWM"/>
</Aliases>
</Block>
<Block location="ioss[0].port[21].pin[0]">
<Aliases>
<Alias value="CYBSP_WCO_IN"/>
</Aliases>
</Block>
<Block location="ioss[0].port[21].pin[1]">
<Aliases>
<Alias value="CYBSP_WCO_OUT"/>
</Aliases>
</Block>
<Block location="ioss[0].port[21].pin[5]">
<Aliases>
<Alias value="CYBSP_ETH_RX_CTL"/>
</Aliases>
</Block>
<Block location="ioss[0].port[23].pin[3]">
<Aliases>
<Alias value="CYBSP_S2G1_PWM"/>
<Alias value="CYBSP_S2G2_PWM"/>
</Aliases>
</Block>
<Block location="peri[0].group[0].div_8[0]">
<Aliases>
<Alias value="CYBSP_TRACE_CLK_DIV0"/>
</Aliases>
</Block>
<Block location="peri[0].group[0].div_8[1]">
<Aliases>
<Alias value="CYBSP_TRACE_CLK_DIV1"/>
</Aliases>
</Block>
<Personality template="dap" version="2.0">
<Block location="cpuss[0].dap[0]" locked="true"/>
<Parameters>
<Param id="dbgMode" value="SWD"/>
<Param id="traceModeParallel" value="0"/>
<Param id="traceModeSerial" value="true"/>
</Parameters>
</Personality>
<Personality template="smartio" version="4.0">
<Block location="ioss[0].port[14].smartio[0]" locked="true"/>
<Parameters>
<Param id="chipMode0" value="CY_SMARTIO_BYPASS"/>
<Param id="chipMode1" value="CY_SMARTIO_BYPASS"/>
<Param id="chipMode2" value="CY_SMARTIO_NONE"/>
<Param id="chipMode3" value="CY_SMARTIO_NONE"/>
<Param id="chipMode4" value="CY_SMARTIO_BYPASS"/>
<Param id="chipMode5" value="CY_SMARTIO_BYPASS"/>
<Param id="chipMode6" value="CY_SMARTIO_NONE"/>
<Param id="chipMode7" value="CY_SMARTIO_NONE"/>
<Param id="clkSrc" value="CY_SMARTIO_CLK_ASYNC"/>
<Param id="duData0" value="CY_SMARTIO_DUDATA_ZERO"/>
<Param id="duData1" value="CY_SMARTIO_DUDATA_ZERO"/>
<Param id="duDataReg" value="0"/>
<Param id="duEn" value="false"/>
<Param id="duOpcode" value="CY_SMARTIO_DUOPC_INCR"/>
<Param id="duSize" value="CY_SMARTIO_DUSIZE_8"/>
<Param id="duTr0" value="CY_SMARTIO_DUTR_ZERO"/>
<Param id="duTr1" value="CY_SMARTIO_DUTR_ZERO"/>
<Param id="duTr2" value="CY_SMARTIO_DUTR_ZERO"/>
<Param id="hldOvr" value="false"/>
<Param id="inFlash" value="true"/>
<Param id="ioMode0" value="CY_SMARTIO_BYPASS"/>
<Param id="ioMode1" value="CY_SMARTIO_BYPASS"/>
<Param id="ioMode4" value="CY_SMARTIO_BYPASS"/>
<Param id="ioMode5" value="CY_SMARTIO_BYPASS"/>
<Param id="lut0Map" value="0"/>
<Param id="lut0Notes" value=""/>
<Param id="lut0Opcode" value="CY_SMARTIO_LUTOPC_COMB"/>
<Param id="lut0Tr0" value="CY_SMARTIO_LUTTR_INVALID"/>
<Param id="lut0Tr1" value="CY_SMARTIO_LUTTR_INVALID"/>
<Param id="lut0Tr2" value="CY_SMARTIO_LUTTR_INVALID"/>
<Param id="lut1Map" value="0"/>
<Param id="lut1Notes" value=""/>
<Param id="lut1Opcode" value="CY_SMARTIO_LUTOPC_COMB"/>
<Param id="lut1Tr0" value="CY_SMARTIO_LUTTR_INVALID"/>
<Param id="lut1Tr1" value="CY_SMARTIO_LUTTR_INVALID"/>
<Param id="lut1Tr2" value="CY_SMARTIO_LUTTR_INVALID"/>
<Param id="lut2Map" value="0"/>
<Param id="lut2Notes" value=""/>
<Param id="lut2Opcode" value="CY_SMARTIO_LUTOPC_COMB"/>
<Param id="lut2Tr0" value="CY_SMARTIO_LUTTR_INVALID"/>
<Param id="lut2Tr1" value="CY_SMARTIO_LUTTR_INVALID"/>
<Param id="lut2Tr2" value="CY_SMARTIO_LUTTR_INVALID"/>
<Param id="lut3Map" value="0"/>
<Param id="lut3Notes" value=""/>
<Param id="lut3Opcode" value="CY_SMARTIO_LUTOPC_COMB"/>
<Param id="lut3Tr0" value="CY_SMARTIO_LUTTR_INVALID"/>
<Param id="lut3Tr1" value="CY_SMARTIO_LUTTR_INVALID"/>
<Param id="lut3Tr2" value="CY_SMARTIO_LUTTR_INVALID"/>
<Param id="lut4Map" value="0"/>
<Param id="lut4Notes" value=""/>
<Param id="lut4Opcode" value="CY_SMARTIO_LUTOPC_COMB"/>
<Param id="lut4Tr0" value="CY_SMARTIO_LUTTR_INVALID"/>
<Param id="lut4Tr1" value="CY_SMARTIO_LUTTR_INVALID"/>
<Param id="lut4Tr2" value="CY_SMARTIO_LUTTR_INVALID"/>
<Param id="lut5Map" value="0"/>
<Param id="lut5Notes" value=""/>
<Param id="lut5Opcode" value="CY_SMARTIO_LUTOPC_COMB"/>
<Param id="lut5Tr0" value="CY_SMARTIO_LUTTR_INVALID"/>
<Param id="lut5Tr1" value="CY_SMARTIO_LUTTR_INVALID"/>
<Param id="lut5Tr2" value="CY_SMARTIO_LUTTR_INVALID"/>
<Param id="lut6Map" value="0"/>
<Param id="lut6Notes" value=""/>
<Param id="lut6Opcode" value="CY_SMARTIO_LUTOPC_COMB"/>
<Param id="lut6Tr0" value="CY_SMARTIO_LUTTR_INVALID"/>
<Param id="lut6Tr1" value="CY_SMARTIO_LUTTR_INVALID"/>
<Param id="lut6Tr2" value="CY_SMARTIO_LUTTR_INVALID"/>
<Param id="lut7Map" value="0"/>
<Param id="lut7Notes" value=""/>
<Param id="lut7Opcode" value="CY_SMARTIO_LUTOPC_COMB"/>
<Param id="lut7Tr0" value="CY_SMARTIO_LUTTR_INVALID"/>
<Param id="lut7Tr1" value="CY_SMARTIO_LUTTR_INVALID"/>
<Param id="lut7Tr2" value="CY_SMARTIO_LUTTR_INVALID"/>
<Param id="lutEn0" value="false"/>
<Param id="lutEn1" value="false"/>
<Param id="lutEn2" value="false"/>
<Param id="lutEn3" value="false"/>
<Param id="lutEn4" value="false"/>
<Param id="lutEn5" value="false"/>
<Param id="lutEn6" value="false"/>
<Param id="lutEn7" value="false"/>
</Parameters>
</Personality>
<Personality template="pin" version="3.0">
<Block location="ioss[0].port[18].pin[6]" locked="true">
<Aliases>
<Alias value="M2B"/>
</Aliases>
</Block>
<Parameters>
<Param id="DriveModes" value="CY_GPIO_DM_HIGHZ"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="driveStrengthTrim" value="CY_GPIO_DRIVE_STRENGTH_DEFAULT"/>
<Param id="inFlash" value="true"/>
<Param id="initialState" value="1"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="nonSec" value="1"/>
<Param id="pullUpRes" value="CY_GPIO_PULLUP_RES_DISABLE"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
</Parameters>
</Personality>
<Personality template="pin" version="3.0">
<Block location="ioss[0].port[18].pin[7]" locked="true">
<Aliases>
<Alias value="M2A"/>
</Aliases>
</Block>
<Parameters>
<Param id="DriveModes" value="CY_GPIO_DM_HIGHZ"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="driveStrengthTrim" value="CY_GPIO_DRIVE_STRENGTH_DEFAULT"/>
<Param id="inFlash" value="true"/>
<Param id="initialState" value="1"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="nonSec" value="1"/>
<Param id="pullUpRes" value="CY_GPIO_PULLUP_RES_DISABLE"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
</Parameters>
</Personality>
<Personality template="pin" version="3.0">
<Block location="ioss[0].port[21].pin[2]" locked="true">
<Aliases>
<Alias value="CYBSP_ECO_IN"/>
</Aliases>
</Block>
<Parameters>
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="driveStrengthTrim" value="CY_GPIO_DRIVE_STRENGTH_DEFAULT"/>
<Param id="inFlash" value="true"/>
<Param id="initialState" value="1"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="nonSec" value="1"/>
<Param id="pullUpRes" value="CY_GPIO_PULLUP_RES_DISABLE"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
</Parameters>
</Personality>
<Personality template="pin" version="3.0">
<Block location="ioss[0].port[21].pin[3]" locked="true">
<Aliases>
<Alias value="CYBSP_ECO_OUT"/>
</Aliases>
</Block>
<Parameters>
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="driveStrengthTrim" value="CY_GPIO_DRIVE_STRENGTH_DEFAULT"/>
<Param id="inFlash" value="true"/>
<Param id="initialState" value="1"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="nonSec" value="1"/>
<Param id="pullUpRes" value="CY_GPIO_PULLUP_RES_DISABLE"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
</Parameters>
</Personality>
<Personality template="pin" version="3.0">
<Block location="ioss[0].port[23].pin[4]" locked="true">
<Aliases>
<Alias value="CYBSP_SWO"/>
</Aliases>
</Block>
<Parameters>
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="driveStrengthTrim" value="CY_GPIO_DRIVE_STRENGTH_DEFAULT"/>
<Param id="inFlash" value="true"/>
<Param id="initialState" value="1"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="nonSec" value="1"/>
<Param id="pullUpRes" value="CY_GPIO_PULLUP_RES_DISABLE"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
</Parameters>
</Personality>
<Personality template="pin" version="3.0">
<Block location="ioss[0].port[23].pin[5]" locked="true">
<Aliases>
<Alias value="CYBSP_SWDCK"/>
</Aliases>
</Block>
<Parameters>
<Param id="DriveModes" value="CY_GPIO_DM_PULLDOWN"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="driveStrengthTrim" value="CY_GPIO_DRIVE_STRENGTH_DEFAULT"/>
<Param id="inFlash" value="true"/>
<Param id="initialState" value="1"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="nonSec" value="1"/>
<Param id="pullUpRes" value="CY_GPIO_PULLUP_RES_DISABLE"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
</Parameters>
</Personality>
<Personality template="pin" version="3.0">
<Block location="ioss[0].port[23].pin[6]" locked="true">
<Aliases>
<Alias value="CYBSP_SWDIO"/>
</Aliases>
</Block>
<Parameters>
<Param id="DriveModes" value="CY_GPIO_DM_PULLUP"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="driveStrengthTrim" value="CY_GPIO_DRIVE_STRENGTH_DEFAULT"/>
<Param id="inFlash" value="true"/>
<Param id="initialState" value="1"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="nonSec" value="1"/>
<Param id="pullUpRes" value="CY_GPIO_PULLUP_RES_DISABLE"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
</Parameters>
</Personality>
<Personality template="pclk_v2" version="1.0">
<Block location="peri[0].group[0].div_8[2]" locked="true">
<Aliases>
<Alias value="CYBSP_TRACE_CLK_DIV2"/>
</Aliases>
</Block>
<Parameters>
<Param id="fracDivider" value="0"/>
<Param id="intDivider" value="1"/>
<Param id="startOnReset" value="true"/>
</Parameters>
</Personality>
<Personality template="pclk_v2" version="1.0">
<Block location="peri[0].group[1].div_8[0]" locked="true"/>
<Parameters>
<Param id="fracDivider" value="0"/>
<Param id="intDivider" value="109"/>
<Param id="startOnReset" value="true"/>
</Parameters>
</Personality>
<Personality template="pclk_v2" version="1.0">
<Block location="peri[0].group[1].div_8[1]" locked="true"/>
<Parameters>
<Param id="fracDivider" value="0"/>
<Param id="intDivider" value="1"/>
<Param id="startOnReset" value="true"/>
</Parameters>
</Personality>
<Personality template="pclk_v2" version="1.0">
<Block location="peri[0].group[1].div_8[2]" locked="true"/>
<Parameters>
<Param id="fracDivider" value="0"/>
<Param id="intDivider" value="1"/>
<Param id="startOnReset" value="true"/>
</Parameters>
</Personality>
<Personality template="pclk_v2" version="1.0">
<Block location="peri[0].group[1].div_8[3]" locked="true"/>
<Parameters>
<Param id="fracDivider" value="0"/>
<Param id="intDivider" value="1"/>
<Param id="startOnReset" value="true"/>
</Parameters>
</Personality>
<Personality template="pclk_v2" version="1.0">
<Block location="peri[0].group[1].div_8[4]" locked="true"/>
<Parameters>
<Param id="fracDivider" value="0"/>
<Param id="intDivider" value="1"/>
<Param id="startOnReset" value="true"/>
</Parameters>
</Personality>
<Personality template="pclk_v2" version="1.0">
<Block location="peri[0].group[1].div_8[5]" locked="true"/>
<Parameters>
<Param id="fracDivider" value="0"/>
<Param id="intDivider" value="1"/>
<Param id="startOnReset" value="true"/>
</Parameters>
</Personality>
<Personality template="pclk_v2" version="1.0">
<Block location="peri[0].group[1].div_8[6]" locked="true"/>
<Parameters>
<Param id="fracDivider" value="0"/>
<Param id="intDivider" value="1"/>
<Param id="startOnReset" value="true"/>
</Parameters>
</Personality>
<Personality template="pclk_v2" version="1.0">
<Block location="peri[0].group[1].div_8[7]" locked="true"/>
<Parameters>
<Param id="fracDivider" value="0"/>
<Param id="intDivider" value="109"/>
<Param id="startOnReset" value="true"/>
</Parameters>
</Personality>
<Personality template="sysclocks" version="3.0">
<Block location="srss[0].clock[0]" locked="true"/>
</Personality>
<Personality template="altsystick" version="3.0">
<Block location="srss[0].clock[0].altsystickclk[0]" locked="true"/>
<Parameters>
<Param id="interval" value="1000"/>
<Param id="sourceClock" value="imo"/>
</Parameters>
</Personality>
<Personality template="bakclk" version="3.0">
<Block location="srss[0].clock[0].bakclk[0]" locked="true"/>
<Parameters>
<Param id="sourceClock" value="lfclk"/>
</Parameters>
</Personality>
<Personality template="eco" version="3.0">
<Block location="srss[0].clock[0].eco[0]" locked="true"/>
<Parameters>
<Param id="accuracyPpm" value="10"/>
<Param id="c0" value="7"/>
<Param id="cLoad" value="8"/>
<Param id="driveLevel" value="100"/>
<Param id="ecoFrequency" value="20.0000"/>
<Param id="esr" value="50"/>
</Parameters>
</Personality>
<Personality template="fastclk" version="2.0">
<Block location="srss[0].clock[0].fastclk[0]" locked="true"/>
<Parameters>
<Param id="divider" value="1"/>
<Param id="fracDivider" value="0"/>
<Param id="intDivider" value="1"/>
</Parameters>
</Personality>
<Personality template="fastclk" version="2.0">
<Block location="srss[0].clock[0].fastclk[1]" locked="true"/>
<Parameters>
<Param id="divider" value="1"/>
<Param id="fracDivider" value="0"/>
<Param id="intDivider" value="1"/>
</Parameters>
</Personality>
<Personality template="fll" version="4.0">
<Block location="srss[0].clock[0].fll[0]" locked="true"/>
<Parameters>
<Param id="configuration" value="auto"/>
<Param id="desiredFrequency" value="100.000"/>
<Param id="enableOutputDivider" value="false"/>
</Parameters>
</Personality>
<Personality template="hfclk" version="3.0">
<Block location="srss[0].clock[0].hfclk[0]" locked="true"/>
<Parameters>
<Param id="ClkHfCsv" value="false"/>
<Param id="accuracyCsv" value="99"/>
<Param id="actionCsv" value="FAULT"/>
<Param id="divider" value="1"/>
<Param id="sourceClockCsv" value="IMO"/>
<Param id="sourceClockNumber" value="0"/>
</Parameters>
</Personality>
<Personality template="hfclk" version="3.0">
<Block location="srss[0].clock[0].hfclk[1]" locked="true"/>
<Parameters>
<Param id="ClkHfCsv" value="false"/>
<Param id="accuracyCsv" value="99"/>
<Param id="actionCsv" value="FAULT"/>
<Param id="divider" value="1"/>
<Param id="sourceClockCsv" value="IMO"/>
<Param id="sourceClockNumber" value="1"/>
</Parameters>
</Personality>
<Personality template="hfclk" version="3.0">
<Block location="srss[0].clock[0].hfclk[2]" locked="true"/>
<Parameters>
<Param id="ClkHfCsv" value="false"/>
<Param id="accuracyCsv" value="99"/>
<Param id="actionCsv" value="FAULT"/>
<Param id="divider" value="2"/>
<Param id="sourceClockCsv" value="IMO"/>
<Param id="sourceClockNumber" value="4"/>
</Parameters>
</Personality>
<Personality template="hfclk" version="3.0">
<Block location="srss[0].clock[0].hfclk[3]" locked="true"/>
<Parameters>
<Param id="ClkHfCsv" value="false"/>
<Param id="accuracyCsv" value="99"/>
<Param id="actionCsv" value="FAULT"/>
<Param id="divider" value="2"/>
<Param id="sourceClockCsv" value="IMO"/>
<Param id="sourceClockNumber" value="4"/>
</Parameters>
</Personality>
<Personality template="hfclk" version="3.0">
<Block location="srss[0].clock[0].hfclk[4]" locked="true"/>
<Parameters>
<Param id="ClkHfCsv" value="false"/>
<Param id="accuracyCsv" value="99"/>
<Param id="actionCsv" value="FAULT"/>
<Param id="divider" value="4"/>
<Param id="sourceClockCsv" value="IMO"/>
<Param id="sourceClockNumber" value="4"/>
</Parameters>
</Personality>
<Personality template="hfclk" version="3.0">
<Block location="srss[0].clock[0].hfclk[5]" locked="true"/>
<Parameters>
<Param id="ClkHfCsv" value="false"/>
<Param id="accuracyCsv" value="99"/>
<Param id="actionCsv" value="FAULT"/>
<Param id="divider" value="2"/>
<Param id="sourceClockCsv" value="IMO"/>
<Param id="sourceClockNumber" value="2"/>
</Parameters>
</Personality>
<Personality template="hfclk" version="3.0">
<Block location="srss[0].clock[0].hfclk[6]" locked="true"/>
<Parameters>
<Param id="ClkHfCsv" value="false"/>
<Param id="accuracyCsv" value="99"/>
<Param id="actionCsv" value="FAULT"/>
<Param id="divider" value="1"/>
<Param id="sourceClockCsv" value="IMO"/>
<Param id="sourceClockNumber" value="4"/>
</Parameters>
</Personality>
<Personality template="hfclk" version="3.0">
<Block location="srss[0].clock[0].hfclk[7]" locked="true"/>
<Parameters>
<Param id="ClkHfCsv" value="false"/>
<Param id="accuracyCsv" value="99"/>
<Param id="actionCsv" value="FAULT"/>
<Param id="divider" value="1"/>
<Param id="sourceClockCsv" value="IMO"/>
<Param id="sourceClockNumber" value="5"/>
</Parameters>
</Personality>
<Personality template="ilo" version="3.0">
<Block location="srss[0].clock[0].ilo[0]" locked="true"/>
<Parameters>
<Param id="hibernate" value="true"/>
</Parameters>
</Personality>
<Personality template="ilo" version="3.0">
<Block location="srss[0].clock[0].ilo[1]" locked="true"/>
<Parameters>
<Param id="hibernate" value="true"/>
</Parameters>
</Personality>
<Personality template="imo" version="3.0">
<Block location="srss[0].clock[0].imo[0]" locked="true"/>
<Parameters>
<Param id="trim" value="1"/>
</Parameters>
</Personality>
<Personality template="lfclk" version="3.0">
<Block location="srss[0].clock[0].lfclk[0]" locked="true"/>
<Parameters>
<Param id="ClkLfCsv" value="false"/>
<Param id="accuracyCsv" value="99"/>
<Param id="sourceClock" value="ilo0"/>
<Param id="sourceClockCsv" value="IMO"/>
</Parameters>
</Personality>
<Personality template="mxs40memclk" version="1.0">
<Block location="srss[0].clock[0].memclk[0]" locked="true"/>
<Parameters>
<Param id="divider" value="1"/>
</Parameters>
</Personality>
<Personality template="pathmux" version="3.0">
<Block location="srss[0].clock[0].pathmux[0]" locked="true"/>
<Parameters>
<Param id="sourceClock" value="eco"/>
</Parameters>
</Personality>
<Personality template="pathmux" version="3.0">
<Block location="srss[0].clock[0].pathmux[1]" locked="true"/>
<Parameters>
<Param id="sourceClock" value="eco"/>
</Parameters>
</Personality>
<Personality template="pathmux" version="3.0">
<Block location="srss[0].clock[0].pathmux[2]" locked="true"/>
<Parameters>
<Param id="sourceClock" value="eco"/>
</Parameters>
</Personality>
<Personality template="pathmux" version="3.0">
<Block location="srss[0].clock[0].pathmux[3]" locked="true"/>
<Parameters>
<Param id="sourceClock" value="eco"/>
</Parameters>
</Personality>
<Personality template="pathmux" version="3.0">
<Block location="srss[0].clock[0].pathmux[4]" locked="true"/>
<Parameters>
<Param id="sourceClock" value="eco"/>
</Parameters>
</Personality>
<Personality template="pathmux" version="3.0">
<Block location="srss[0].clock[0].pathmux[5]" locked="true"/>
<Parameters>
<Param id="sourceClock" value="ilo0"/>
</Parameters>
</Personality>
<Personality template="pathmux" version="3.0">
<Block location="srss[0].clock[0].pathmux[6]" locked="true"/>
<Parameters>
<Param id="sourceClock" value="imo"/>
</Parameters>
</Personality>
<Personality template="periclk" version="2.0">
<Block location="srss[0].clock[0].periclk[0]" locked="true"/>
<Parameters>
<Param id="divider" value="1"/>
</Parameters>
</Personality>
<Personality template="mxs40pll400" version="1.0">
<Block location="srss[0].clock[0].pll400m[0]" locked="true"/>
<Parameters>
<Param id="configuration" value="auto"/>
<Param id="desiredFrequency" value="250.000"/>
</Parameters>
</Personality>
<Personality template="mxs40pll400" version="1.0">
<Block location="srss[0].clock[0].pll400m[1]" locked="true"/>
<Parameters>
<Param id="configuration" value="auto"/>
<Param id="desiredFrequency" value="250.000"/>
</Parameters>
</Personality>
<Personality template="pll" version="3.0">
<Block location="srss[0].clock[0].pll[0]" locked="true"/>
<Parameters>
<Param id="configuration" value="auto"/>
<Param id="desiredFrequency" value="160.000"/>
<Param id="lowFrequencyMode" value="false"/>
<Param id="optimization" value="MinPower"/>
</Parameters>
</Personality>
<Personality template="pll" version="3.0">
<Block location="srss[0].clock[0].pll[1]" locked="true"/>
<Parameters>
<Param id="configuration" value="auto"/>
<Param id="desiredFrequency" value="200.000"/>
<Param id="lowFrequencyMode" value="false"/>
<Param id="optimization" value="MinPower"/>
</Parameters>
</Personality>
<Personality template="slowclk" version="2.0">
<Block location="srss[0].clock[0].slowclk[0]" locked="true"/>
<Parameters>
<Param id="divider" value="1"/>
</Parameters>
</Personality>
<Personality template="timerclk" version="3.0">
<Block location="srss[0].clock[0].timerclk[0]" locked="true"/>
</Personality>
<Personality template="power_v3" version="1.0">
<Block location="srss[0].power[0]" locked="true"/>
<Parameters>
<Param id="deepsleepLatency" value="0"/>
<Param id="enableLowPowerProfileMode" value="false"/>
<Param id="idlePwrMode" value="CY_CFG_PWR_MODE_DEEPSLEEP"/>
<Param id="minCurrRegulator" value="CY_SYSPM_LDO_MODE_NORMAL"/>
<Param id="transistorEnable" value="false"/>
<Param id="vadjMv" value="1100"/>
<Param id="vddaMv" value="3300"/>
<Param id="vdddMv" value="3300"/>
<Param id="vddio0Mv" value="3300"/>
<Param id="vddio1Mv" value="3300"/>
</Parameters>
</Personality>
</BlockConfig>
<Netlist>
<Net>
<Port name="cpuss[0].dap[0].clock_trace_in[0]"/>
<Port name="peri[0].group[0].div_8[2].clk[0]"/>
</Net>
<Net>
<Port name="cpuss[0].dap[0].swj_swclk_tclk[0]"/>
<Port name="ioss[0].port[23].pin[5].digital_in[0]"/>
</Net>
<Net>
<Port name="cpuss[0].dap[0].swj_swdio_tms[0]"/>
<Port name="ioss[0].port[23].pin[6].digital_inout[0]"/>
</Net>
<Net>
<Port name="cpuss[0].dap[0].swj_swo_tdo[0]"/>
<Port name="ioss[0].port[23].pin[4].digital_out[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[21].pin[2].analog[0]"/>
<Port name="srss[0].clock[0].eco[0].eco_in[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[21].pin[3].analog[0]"/>
<Port name="srss[0].clock[0].eco[0].eco_out[0]"/>
</Net>
</Netlist>
</Device>
</Devices>
</Configuration>

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/***************************************************************************//**
* \file cybsp.c
*
* Description:
* Provides initialization code for starting up the hardware contained on the
* Infineon board.
*
********************************************************************************
* \copyright
* Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include <stdlib.h>
#include "cy_syspm.h"
#include "cy_sysclk.h"
#include "cybsp.h"
#if defined(CY_USING_HAL)
#include "cyhal_hwmgr.h"
#include "cyhal_syspm.h"
#endif
#if defined(COMPONENT_MW_CAT1CM0P)
#include "mtb_cat1cm0p.h"
#endif
#if defined(__cplusplus)
extern "C" {
#endif
// The sysclk deep sleep callback is recommended to be the last callback that is executed before
// entry into deep sleep mode and the first one upon exit the deep sleep mode.
// Doing so minimizes the time spent on low power mode entry and exit.
#ifndef CYBSP_SYSCLK_PM_CALLBACK_ORDER
#define CYBSP_SYSCLK_PM_CALLBACK_ORDER (255u)
#endif
#if !defined(CYBSP_CUSTOM_SYSCLK_PM_CALLBACK)
//--------------------------------------------------------------------------------------------------
// cybsp_register_sysclk_pm_callback
//
// Registers a power management callback that prepares the clock system for entering deep sleep mode
// and restore the clocks upon wakeup from deep sleep.
// NOTE: This is called automatically as part of \ref cybsp_init
//--------------------------------------------------------------------------------------------------
static cy_rslt_t cybsp_register_sysclk_pm_callback(void)
{
cy_rslt_t result = CY_RSLT_SUCCESS;
static cy_stc_syspm_callback_params_t cybsp_sysclk_pm_callback_param = { NULL, NULL };
static cy_stc_syspm_callback_t cybsp_sysclk_pm_callback =
{
.callback = &Cy_SysClk_DeepSleepCallback,
.type = CY_SYSPM_DEEPSLEEP,
.callbackParams = &cybsp_sysclk_pm_callback_param,
.order = CYBSP_SYSCLK_PM_CALLBACK_ORDER
};
if (!Cy_SysPm_RegisterCallback(&cybsp_sysclk_pm_callback))
{
result = CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK;
}
return result;
}
#endif // if !defined(CYBSP_CUSTOM_SYSCLK_PM_CALLBACK)
//--------------------------------------------------------------------------------------------------
// cybsp_init
//--------------------------------------------------------------------------------------------------
cy_rslt_t cybsp_init(void)
{
// Setup hardware manager to track resource usage then initialize all system (clock/power) board
// configuration
#if defined(CY_USING_HAL)
cy_rslt_t result = cyhal_hwmgr_init();
if (CY_RSLT_SUCCESS == result)
{
result = cyhal_syspm_init();
}
#ifdef CY_CFG_PWR_VDDA_MV
if (CY_RSLT_SUCCESS == result)
{
cyhal_syspm_set_supply_voltage(CYHAL_VOLTAGE_SUPPLY_VDDA, CY_CFG_PWR_VDDA_MV);
}
#endif
#else // if defined(CY_USING_HAL)
cy_rslt_t result = CY_RSLT_SUCCESS;
#endif // if defined(CY_USING_HAL)
// By default, the peripheral configuration will be done on the first core running user code.
// This is the CM0+ if it is available and not running a pre-built image, and the CM7 otherwise.
// This is done to ensure configuration is available for all cores that might need to use it.
// In the case of a dual core project, this can be changed below to perform initialization on
// the CM7 if necessary.
#if defined(CORE_NAME_CM0P_0) || !(__CM0P_PRESENT) || (defined(CORE_NAME_CM7_0) && \
defined(CY_USING_PREBUILT_CM0P_IMAGE))
cycfg_config_init();
#endif
cycfg_config_reservations();
if (CY_RSLT_SUCCESS == result)
{
#if defined(CYBSP_CUSTOM_SYSCLK_PM_CALLBACK)
result = cybsp_register_custom_sysclk_pm_callback();
#else
result = cybsp_register_sysclk_pm_callback();
#endif
}
// CYHAL_HWMGR_RSLT_ERR_INUSE error code could be returned if any needed for BSP resource was
// reserved by user previously. Please review the Device Configurator (design.modus) and the BSP
// reservation list (cyreservedresources.list) to make sure no resources are reserved by both.
return result;
}
#if defined(__cplusplus)
}
#endif

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/***********************************************************************************************//**
* \file cybsp.h
*
* \brief
* Basic API for setting up boards containing a Cypress MCU.
*
***************************************************************************************************
* \copyright
* Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
**************************************************************************************************/
#pragma once
#include "cy_result.h"
#include "cybsp_types.h"
#include "cybsp_hw_config.h"
#if defined(COMPONENT_WICED_BLE) || defined(COMPONENT_WICED_DUALMODE)
#include "cybsp_bt_config.h"
#endif
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \addtogroup group_bsp_errors Error Codes
* \{
* Error codes specific to the board.
*/
/** Failed to configure sysclk power management callback */
#define CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK \
(CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 0))
/** \} group_bsp_errors */
/**
* \addtogroup group_bsp_functions Functions
* \{
* All functions exposed by the board.
*/
/**
* \brief Initialize all hardware on the board
* \returns CY_RSLT_SUCCESS if the board is successfully initialized, if there is
* a problem initializing any hardware it returns an error code specific
* to the hardware module that had a problem.
*/
cy_rslt_t cybsp_init(void);
#if defined(CYBSP_CUSTOM_SYSCLK_PM_CALLBACK)
//--------------------------------------------------------------------------------------------------
// cybsp_register_custom_sysclk_pm_callback
//
// Registers a power management callback that prepares the clock system for entering deep sleep mode
// and restore the clocks upon wakeup from deep sleep. The application should implement this
// function and define `CYBSP_CUSTOM_SYSCLK_PM_CALLBACK` if it needs to replace the default SysClk
// DeepSleep callback behavior with application specific logic.
// NOTE: This is called automatically as part of \ref cybsp_init
//--------------------------------------------------------------------------------------------------
cy_rslt_t cybsp_register_custom_sysclk_pm_callback(void);
#endif // defined(CYBSP_CUSTOM_SYSCLK_PM_CALLBACK)
/** \} group_bsp_functions */
#ifdef __cplusplus
}
#endif // __cplusplus

847
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/***********************************************************************************************//**
* \copyright
* Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
**************************************************************************************************/
#pragma once
#if defined(CY_USING_HAL)
#include "cyhal_pin_package.h"
#endif
/* CAT4 and CAT5 do not have configurators so the BSP defines pins in a non-generated header */
#if defined(COMPONENT_CAT4)
#include "cybsp_pins.h"
#else
#include "cycfg.h"
#endif
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \addtogroup group_bsp_pins Pin Mappings
* \{
* Macro definitions for common peripheral pins on the board.
*/
#if defined(CYBSP_USER_LED)
/**
* \addtogroup group_bsp_pins_led LED Pins
* \{
* Pins connected to user LEDs on the board.
*/
#ifdef CYBSP_LED_RGB_RED
/** RGB LED - Red \def CYBSP_LED_RGB_RED
*/
#endif
#ifdef CYBSP_LED_RGB_GREEN
/** RGB LED - Green \def CYBSP_LED_RGB_GREEN
*/
#endif
#ifdef CYBSP_LED_RGB_BLUE
/** RGB LED - Blue \def CYBSP_LED_RGB_BLUE
*/
#endif
#ifdef CYBSP_USER_LED
/** User LED \def CYBSP_USER_LED
*/
#endif
#ifdef CYBSP_USER_LED1
/** User LED1 \def CYBSP_USER_LED1
*/
#endif
#ifdef CYBSP_USER_LED2
/** User LED2 \def CYBSP_USER_LED2
*/
#endif
#ifdef CYBSP_USER_LED3
/** User LED3 \def CYBSP_USER_LED3
*/
#endif
#ifdef CYBSP_USER_LED4
/** User LED 4 \def CYBSP_USER_LED4
*/
#endif
#ifdef CYBSP_USER_LED5
/** User LED 5 \def CYBSP_USER_LED5
*/
#endif
#ifdef CYBSP_USER_LED6
/** User LED 6 \def CYBSP_USER_LED6
*/
#endif
#ifdef CYBSP_USER_LED7
/** User LED 7 \def CYBSP_USER_LED7
*/
#endif
#ifdef CYBSP_USER_LED8
/** User LED 8 \def CYBSP_USER_LED8
*/
#endif
#ifdef CYBSP_USER_LED9
/** User LED 9 \def CYBSP_USER_LED9
*/
#endif
#ifdef CYBSP_USER_LED10
/** User LED 10 \def CYBSP_USER_LED10
*/
#endif
#ifdef CYBSP_LED1
/** LED 1 \def CYBSP_LED1
*/
#endif
#ifdef CYBSP_LED2
/** LED 2 \def CYBSP_LED2
*/
#endif
#ifdef CYBSP_LED3
/** LED 3 \def CYBSP_LED3
*/
#endif
#ifdef CYBSP_LED3_RGB_RED
/** LED 3: RGB LED - Red \def CYBSP_LED3_RGB_RED
*/
#endif
#ifdef CYBSP_LED3_RGB_GREEN
/** LED 3: RGB LED - Green \def CYBSP_LED3_RGB_GREEN
*/
#endif
#ifdef CYBSP_LED3_RGB_BLUE
/** LED 3: RGB LED - Blue \def CYBSP_LED3_RGB_BLUE
*/
#endif
#ifdef CYBSP_LED4
/** LED 4 \def CYBSP_LED4
*/
#endif
#ifdef CYBSP_LED5
/** LED 5 \def CYBSP_LED5
*/
#endif
#ifdef CYBSP_LED6
/** LED 6 \def CYBSP_LED6
*/
#endif
#ifdef CYBSP_LED7
/** LED 7 \def CYBSP_LED7
*/
#endif
#ifdef CYBSP_LED8
/** LED 8 \def CYBSP_LED8
*/
#endif
#ifdef CYBSP_LED9
/** LED 9 \def CYBSP_LED9
*/
#endif
#ifdef CYBSP_LED10
/** LED 10 \def CYBSP_LED10
*/
#endif
#ifdef CYBSP_LED11
/** LED 11 \def CYBSP_LED11
*/
#endif
#ifdef CYBSP_LED12
/** LED 12 \def CYBSP_LED12
*/
#endif
#ifdef CYBSP_LED13
/** LED 13 \def CYBSP_LED13
*/
#endif
#ifdef CYBSP_LED_SLD0
/** Slider LED 0 \def CYBSP_LED_SLD0
*/
#endif
#ifdef CYBSP_LED_SLD1
/** Slider LED 1 \def CYBSP_LED_SLD1
*/
#endif
#ifdef CYBSP_LED_SLD2
/** Slider LED 2 \def CYBSP_LED_SLD2
*/
#endif
#ifdef CYBSP_LED_SLD3
/** Slider LED 3 \def CYBSP_LED_SLD3
*/
#endif
#ifdef CYBSP_LED_SLD4
/** Slider LED 4 \def CYBSP_LED_SLD4
*/
#endif
#ifdef CYBSP_LED_SLD5
/** LED 10; Slider LED 5 \def CYBSP_LED_SLD5
*/
#endif
#ifdef CYBSP_LED_BTN0
/** Button LED 0 \def CYBSP_LED_BTN0
*/
#endif
#ifdef CYBSP_LED_BTN1
/** Button LED 1 \def CYBSP_LED_BTN1
*/
#endif
#ifdef CYBSP_LED_BTN2
/** Button LED 2 \def CYBSP_LED_BTN2
*/
#endif
/** \} group_bsp_pins_led */
#endif // defined(CYBSP_USER_LED)
#if defined(CYBSP_USER_BTN)
/**
* \addtogroup group_bsp_pins_btn Button Pins
* \{
* Pins connected to user buttons on the board.
*/
#ifdef CYBSP_SW1
/** Switch 1 \def CYBSP_SW1
*/
#endif
#ifdef CYBSP_SW2
/** Switch 2 \def CYBSP_SW2
*/
#endif
#ifdef CYBSP_SW3
/** Switch 3 \def CYBSP_SW3
*/
#endif
#ifdef CYBSP_SW4
/** Switch 4 \def CYBSP_SW4
*/
#endif
#ifdef CYBSP_USER_BTN
/** User Button 1 \def CYBSP_USER_BTN
*/
#endif
#ifdef CYBSP_USER_BTN1
/** User Button 1 \def CYBSP_USER_BTN1
*/
#endif
#ifdef CYBSP_USER_BTN2
/** User Button 2 \def CYBSP_USER_BTN2
*/
#endif
#ifdef CYBSP_POTENTIOMETER_INPUT
/** Potentiometer input \def CYBSP_POTENTIOMETER_INPUT
*/
#endif
/** \} group_bsp_pins_btn */
#endif // defined(CYBSP_USER_BTN)
#if defined(CYBSP_DEBUG_UART_RX) || defined(CYBSP_SWDIO)
/**
* \addtogroup group_bsp_pins_comm Communication Pins
* \{
* Pins associated with connections on the board for communication interfaces (UART/I2C/SPI/...)
*/
#ifdef CYBSP_DEBUG_UART_RX
/** Pin: UART RX \def CYBSP_DEBUG_UART_RX
*/
#endif
#ifdef CYBSP_DEBUG_UART_TX
/** Pin: UART TX \def CYBSP_DEBUG_UART_TX
*/
#endif
#ifdef CYBSP_I2C_SCL
/** Pin: I2C SCL \def CYBSP_I2C_SCL
*/
#endif
#ifdef CYBSP_I2C_SDA
/** Pin: I2C SDA \def CYBSP_I2C_SDA
*/
#endif
#ifdef CYBSP_SWDIO
/** Pin: SWDIO \def CYBSP_SWDIO
*/
#endif
#ifdef CYBSP_SWDCK
/** Pin: SWDCK \def CYBSP_SWDCK
*/
#endif
#ifdef CYBSP_SPI_MOSI
/** Pin: SPI MOSI \def CYBSP_SPI_MOSI
*/
#endif
#ifdef CYBSP_SPI_MISO
/** Pin: SPI MISO \def CYBSP_SPI_MISO
*/
#endif
#ifdef CYBSP_SPI_CLK
/** Pin: SPI CLK \def CYBSP_SPI_CLK
*/
#endif
#ifdef CYBSP_SPI_CS
/** Pin: SPI CS \def CYBSP_SPI_CS
*/
#endif
#ifdef CYBSP_SWO
/** Pin: SWO \def CYBSP_SWO
*/
#endif
#ifdef CYBSP_QSPI_SS
/** Pin: QUAD SPI SS \def CYBSP_QSPI_SS
*/
#endif
#ifdef CYBSP_QSPI_D3
/** Pin: QUAD SPI D3 \def CYBSP_QSPI_D3
*/
#endif
#ifdef CYBSP_QSPI_D2
/** Pin: QUAD SPI D2 \def CYBSP_QSPI_D2
*/
#endif
#ifdef CYBSP_QSPI_D1
/** Pin: QUAD SPI D1 \def CYBSP_QSPI_D1
*/
#endif
#ifdef CYBSP_QSPI_D0
/** Pin: QUAD SPI D0 \def CYBSP_QSPI_D0
*/
#endif
#ifdef CYBSP_QSPI_SCK
/** Pin: QUAD SPI SCK \def CYBSP_QSPI_SCK
*/
#endif
#ifdef CYBSP_WIFI_SDIO_D0
/** Pin: WIFI SDIO D0 \def CYBSP_WIFI_SDIO_D0
*/
#endif
#ifdef CYBSP_WIFI_SDIO_D1
/** Pin: WIFI SDIO D1 \def CYBSP_WIFI_SDIO_D1
*/
#endif
#ifdef CYBSP_WIFI_SDIO_D2
/** Pin: WIFI SDIO D2 \def CYBSP_WIFI_SDIO_D2
*/
#endif
#ifdef CYBSP_WIFI_SDIO_D3
/** Pin: WIFI SDIO D3 \def CYBSP_WIFI_SDIO_D3
*/
#endif
#ifdef CYBSP_WIFI_SDIO_CMD
/** Pin: WIFI SDIO CMD \def CYBSP_WIFI_SDIO_CMD
*/
#endif
#ifdef CYBSP_WIFI_SDIO_CLK
/** Pin: WIFI SDIO CLK \def CYBSP_WIFI_SDIO_CLK
*/
#endif
#ifdef CYBSP_WIFI_WL_REG_ON
/** Pin: WIFI ON \def CYBSP_WIFI_WL_REG_ON
*/
#endif
#ifdef CYBSP_WIFI_HOST_WAKE
/** Pin: WIFI Host Wakeup \def CYBSP_WIFI_HOST_WAKE
*/
#ifndef CYBSP_WIFI_HOST_WAKE_GPIO_DM
/** WiFi host-wake GPIO drive mode */
#define CYBSP_WIFI_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_ANALOG)
#endif
#ifndef CYBSP_WIFI_HOST_WAKE_IRQ_EVENT
/** WiFi host-wake IRQ event */
#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT (CYHAL_GPIO_IRQ_RISE)
#endif
#endif // ifdef CYBSP_WIFI_HOST_WAKE
#ifdef CYBSP_BT_UART_RX
/** Pin: BT UART RX \def CYBSP_BT_UART_RX
*/
#endif
#ifdef CYBSP_BT_UART_TX
/** Pin: BT UART TX \def CYBSP_BT_UART_TX
*/
#endif
#ifdef CYBSP_BT_UART_RTS
/** Pin: BT UART RTS \def CYBSP_BT_UART_RTS
*/
#endif
#ifdef CYBSP_BT_UART_CTS
/** Pin: BT UART CTS \def CYBSP_BT_UART_CTS
*/
#endif
#ifdef CYBSP_BT_POWER
/** Pin: BT Power \def CYBSP_BT_POWER
*/
#endif
#ifdef CYBSP_BT_HOST_WAKE
/** Pin: BT Host Wakeup \def CYBSP_BT_HOST_WAKE
*/
/** BT host-wake GPIO drive mode */
#define CYBSP_BT_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_NONE)
/** BT host wake IRQ event */
#define CYBSP_BT_HOST_WAKE_IRQ_EVENT (CYHAL_GPIO_IRQ_FALL)
#endif
#ifdef CYBSP_BT_DEVICE_WAKE
/** Pin: BT Device Wakeup \def CYBSP_BT_DEVICE_WAKE
*/
/** BT device wakeup GPIO drive mode */
#define CYBSP_BT_DEVICE_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_STRONG)
/** BT device wakeup polarity */
#define CYBSP_BT_DEVICE_WAKE_POLARITY (0u)
#endif
#ifdef CYBSP_PDM_CLK
/** Pin: PDM PCM CLK \def CYBSP_PDM_CLK
*/
#endif
#ifdef CYBSP_PDM_DATA
/** Pin PDM PCM DATA \def CYBSP_PDM_DATA
*/
#endif
#ifdef CYBSP_I2S_MCLK
/** Pin: I2S MCLK \def CYBSP_I2S_MCLK
*/
#endif
#ifdef CYBSP_I2S_TX_SCK
/** Pin: I2S TX SCK \def CYBSP_I2S_TX_SCK
*/
#endif
#ifdef CYBSP_I2S_TX_WS
/** Pin: I2S TX WS \def CYBSP_I2S_TX_WS
*/
#endif
#ifdef CYBSP_I2S_TX_DATA
/** Pin: I2S TX DATA \def CYBSP_I2S_TX_DATA
*/
#endif
#ifdef CYBSP_I2S_RX_SCK
/** Pin: I2S RX SCK \def CYBSP_I2S_RX_SCK
*/
#endif
#ifdef CYBSP_I2S_RX_WS
/** Pin: I2S RX WS \def CYBSP_I2S_RX_WS
*/
#endif
#ifdef CYBSP_I2S_RX_DATA
/** Pin: I2S RX DATA \def CYBSP_I2S_RX_DATA
*/
#endif
#ifdef CYBSP_DEBUG_UART_RTS
/** Pin: UART RX \def CYBSP_DEBUG_UART_RTS
*/
#endif
#ifdef CYBSP_DEBUG_UART_CTS
/** Pin: UART TX \def CYBSP_DEBUG_UART_CTS
*/
#endif
#ifdef CYBSP_UART_RX
/** Pin: UART RX \def CYBSP_UART_RX
*/
#endif
#ifdef CYBSP_UART_TX
/** Pin: UART TX \def CYBSP_UART_TX
*/
#endif
#ifdef CYBSP_TDO_SWO
/** Pin: \def CYBSP_TDO_SWO
*/
#endif
#ifdef CYBSP_TMS_SWDIO
/** Pin: \def CYBSP_TMS_SWDIO
*/
#endif
#ifdef CYBSP_SWCLK
/** Pin: \def CYBSP_SWCLK
*/
#endif
/** \} group_bsp_pins_comm */
#endif // defined(CYBSP_DEBUG_UART_RX) || defined(CYBSP_SWDIO)
#if defined(CYBSP_A0)
/**
* \addtogroup group_bsp_pins_arduino Arduino Header Pins
* \{
* Pins mapped to the Arduino header on the board.
*/
#ifdef CYBSP_A0
/** Arduino A0 \def CYBSP_A0
*/
#endif
#ifdef CYBSP_A1
/** Arduino A1 \def CYBSP_A1
*/
#endif
#ifdef CYBSP_A2
/** Arduino A2 \def CYBSP_A2
*/
#endif
#ifdef CYBSP_A3
/** Arduino A3 \def CYBSP_A3
*/
#endif
#ifdef CYBSP_A4
/** Arduino A4 \def CYBSP_A4
*/
#endif
#ifdef CYBSP_A5
/** Arduino A5 \def CYBSP_A5
*/
#endif
#ifdef CYBSP_D0
/** Arduino D0 \def CYBSP_D0
*/
#endif
#ifdef CYBSP_D1
/** Arduino D1 \def CYBSP_D1
*/
#endif
#ifdef CYBSP_D2
/** Arduino D2 \def CYBSP_D2
*/
#endif
#ifdef CYBSP_D3
/** Arduino D3 \def CYBSP_D3
*/
#endif
#ifdef CYBSP_D4
/** Arduino D4 \def CYBSP_D4
*/
#endif
#ifdef CYBSP_D5
/** Arduino D5 \def CYBSP_D5
*/
#endif
#ifdef CYBSP_D6
/** Arduino D6 \def CYBSP_D6
*/
#endif
#ifdef CYBSP_D7
/** Arduino D7 \def CYBSP_D7
*/
#endif
#ifdef CYBSP_D8
/** Arduino D8 \def CYBSP_D8
*/
#endif
#ifdef CYBSP_D9
/** Arduino D9 \def CYBSP_D9
*/
#endif
#ifdef CYBSP_D10
/** Arduino D10 \def CYBSP_D10
*/
#endif
#ifdef CYBSP_D11
/** Arduino D11 \def CYBSP_D11
*/
#endif
#ifdef CYBSP_D12
/** Arduino D12 \def CYBSP_D12
*/
#endif
#ifdef CYBSP_D13
/** Arduino D13 \def CYBSP_D13
*/
#endif
#ifdef CYBSP_D14
/** Arduino D14 \def CYBSP_D14
*/
#endif
#ifdef CYBSP_D15
/** Arduino D15 \def CYBSP_D15
*/
#endif
/** \} group_bsp_pins_arduino */
#endif // defined(CYBSP_A0)
#if defined(CYBSP_J2_1)
/**
* \addtogroup group_bsp_pins_j2 J2 Header Pins
* \{
* Pins mapped to the J2 header on the board.
*/
#ifdef CYBSP_J2_1
/** Infineon J2 Header pin 1 \def CYBSP_J2_1
*/
#endif
#ifdef CYBSP_J2_2
/** Infineon J2 Header pin 2 \def CYBSP_J2_2
*/
#endif
#ifdef CYBSP_J2_3
/** Infineon J2 Header pin 3 \def CYBSP_J2_3
*/
#endif
#ifdef CYBSP_J2_4
/** Infineon J2 Header pin 4 \def CYBSP_J2_4
*/
#endif
#ifdef CYBSP_J2_5
/** Infineon J2 Header pin 5 \def CYBSP_J2_5
*/
#endif
#ifdef CYBSP_J2_7
/** Infineon J2 Header pin 7 \def CYBSP_J2_7
*/
#endif
#ifdef CYBSP_J2_8
/** Infineon J2 Header pin 8 \def CYBSP_J2_8
*/
#endif
#ifdef CYBSP_J2_9
/** Infineon J2 Header pin 9 \def CYBSP_J2_9
*/
#endif
#ifdef CYBSP_J2_10
/** Infineon J2 Header pin 10 \def CYBSP_J2_10
*/
#endif
#ifdef CYBSP_J2_11
/** Infineon J2 Header pin 11 \def CYBSP_J2_11
*/
#endif
#ifdef CYBSP_J2_12
/** Infineon J2 Header pin 12 \def CYBSP_J2_12
*/
#endif
#ifdef CYBSP_J2_13
/** Infineon J2 Header pin 13 \def CYBSP_J2_13
*/
#endif
#ifdef CYBSP_J2_15
/** Infineon J2 Header pin 15 \def CYBSP_J2_15
*/
#endif
#ifdef CYBSP_J2_16
/** Infineon J2 Header pin 16 \def CYBSP_J2_16
*/
#endif
#ifdef CYBSP_J2_16
/** Infineon J2 Header pin 16 \def CYBSP_J2_16
*/
#endif
#ifdef CYBSP_J2_6
/** Infineon J2 Header pin 6 \def CYBSP_J2_6
*/
#endif
#ifdef CYBSP_J2_17
/** Infineon J2 Header pin 17 \def CYBSP_J2_17
*/
#endif
#ifdef CYBSP_J2_18
/** Infineon J2 Header pin 18 \def CYBSP_J2_18
*/
#endif
#ifdef CYBSP_J2_19
/** Infineon J2 Header pin 19 \def CYBSP_J2_19
*/
#endif
#ifdef CYBSP_J2_20
/** Infineon J2 Header pin 20 \def CYBSP_J2_20
*/
#endif
#ifdef CYBSP_J2_14
/** Infineon J2 Header pin 14 \def CYBSP_J2_14
*/
#endif
/** \} group_bsp_pins_j2 */
#endif // defined(CYBSP_J2_1)
#if defined(CYBSP_J6_1)
/**
* \addtogroup group_bsp_pins_j6 J6 Header Pins
* \{
* Pins mapped to the J6 header on the board.
*/
#ifdef CYBSP_J6_1
/** Infineon J6 Header pin 1 \def CYBSP_J6_1
*/
#endif
#ifdef CYBSP_J6_2
/** Infineon J6 Header pin 2 \def CYBSP_J6_2
*/
#endif
#ifdef CYBSP_J6_3
/** Infineon J6 Header pin 3 \def CYBSP_J6_3
*/
#endif
#ifdef CYBSP_J6_4
/** Infineon J6 Header pin 4 \def CYBSP_J6_4
*/
#endif
#ifdef CYBSP_J6_5
/** Infineon J6 Header pin 5 \def CYBSP_J6_5
*/
#endif
#ifdef CYBSP_J6_6
/** Infineon J6 Header pin 6 \def CYBSP_J6_6
*/
#endif
#ifdef CYBSP_J6_7
/** Infineon J6 Header pin 7 \def CYBSP_J6_7
*/
#endif
#ifdef CYBSP_J6_8
/** Infineon J6 Header pin 8 \def CYBSP_J6_8
*/
#endif
#ifdef CYBSP_J6_9
/** Infineon J6 Header pin 9 \def CYBSP_J6_9
*/
#endif
#ifdef CYBSP_J6_10
/** Infineon J6 Header pin 10 \def CYBSP_J6_10
*/
#endif
#ifdef CYBSP_J6_11
/** Infineon J6 Header pin 11 \def CYBSP_J6_11
*/
#endif
#ifdef CYBSP_J6_12
/** Infineon J6 Header pin 12 \def CYBSP_J6_12
*/
#endif
#ifdef CYBSP_J6_13
/** Infineon J6 Header pin 13 \def CYBSP_J6_13
*/
#endif
#ifdef CYBSP_J6_14
/** Infineon J6 Header pin 14 \def CYBSP_J6_14
*/
#endif
#ifdef CYBSP_J6_15
/** Infineon J6 Header pin 15 \def CYBSP_J6_15
*/
#endif
#ifdef CYBSP_J6_16
/** Infineon J6 Header pin 16 \def CYBSP_J6_16
*/
#endif
/** \} group_bsp_pins_j6 */
#endif // defined(CYBSP_J6_1)
#if defined(CYBSP_CMOD) || defined(CYBSP_CINA) || defined(CYBSP_CINTA)
/**
* \addtogroup group_bsp_pins_capsense Capsense
* \{
* Pins connected to CAPSENSE™ sensors on the board.
*/
#ifdef CYBSP_CSD_TX
/** Pin: CapSesnse TX \def CYBSP_CSD_TX
*/
#endif
#ifdef CYBSP_CINA
/** Pin: CapSesnse CINA \def CYBSP_CINA
*/
#endif
#ifdef CYBSP_CINTA
/** Pin: CapSesnse CINTA \def CYBSP_CINTA
*/
#endif
#ifdef CYBSP_CINB
/** Pin: CapSesnse CINB \def CYBSP_CINB
*/
#endif
#ifdef CYBSP_CINTB
/** Pin: CapSesnse CINTB \def CYBSP_CINTB
*/
#endif
#ifdef CYBSP_CMOD
/** Pin: CapSesnse CMOD \def CYBSP_CMOD
*/
#endif
#ifdef CYBSP_CSD_BTN0
/** Pin: CapSesnse Button 0 \def CYBSP_CSD_BTN0
*/
#endif
#ifdef CYBSP_CSD_BTN1
/** Pin: CapSesnse Button 1 \def CYBSP_CSD_BTN1
*/
#endif
#ifdef CYBSP_CSD_SLD0
/** Pin: CapSesnse Slider 0 \def CYBSP_CSD_SLD0
*/
#endif
#ifdef CYBSP_CSD_SLD1
/** Pin: CapSesnse Slider 1 \def CYBSP_CSD_SLD1
*/
#endif
#ifdef CYBSP_CSD_SLD2
/** Pin: CapSesnse Slider 2 \def CYBSP_CSD_SLD2
*/
#endif
#ifdef CYBSP_CSD_SLD3
/** Pin: CapSesnse Slider 3 \def CYBSP_CSD_SLD3
*/
#endif
#ifdef CYBSP_CSD_SLD4
/** Pin: CapSesnse Slider 4 \def CYBSP_CSD_SLD4
*/
#endif
#ifdef CYBSP_CSD_SLD5
/** Pin: CapSesnse Slider 5 \def CYBSP_CSD_SLD5
*/
#endif
#ifdef CYBSP_CSX_BTN_TX
/** Pin: CapSesnse Button TX \def CYBSP_CSX_BTN_TX
*/
#endif
#ifdef CYBSP_CSX_BTN0
/** Pin: CapSesnse Button 0 \def CYBSP_CSX_BTN0
*/
#endif
#ifdef CYBSP_CSX_BTN1
/** Pin: CapSesnse Button 1 \def CYBSP_CSX_BTN1
*/
#endif
#ifdef CYBSP_CSX_BTN2
/** Pin: CapSesnse Button 2 \def CYBSP_CSX_BTN2
*/
#endif
/** \} group_bsp_pins_capsense */
#endif // defined(CYBSP_CMOD) || defined(CYBSP_CINA) || defined(CYBSP_CINTA)
#if defined(CYBSP_WCO_IN)
/**
* \addtogroup group_bsp_pins_wco WCO
* \{
* Pins connected to the WCO on the board.
*/
#ifdef CYBSP_WCO_IN
/** Pin: WCO input \def CYBSP_WCO_IN
*/
#endif
#ifdef CYBSP_WCO_OUT
/** Pin: WCO output \def CYBSP_WCO_OUT
*/
#endif
/** \} group_bsp_pins_wco */
#endif // defined(CYBSP_WCO_IN)
/** \} group_bsp_pins */
#if defined(__cplusplus)
}
#endif

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/***********************************************************************************************//**
* \file cybsp_hw_config.h
*
* \brief
* Basic API for handling defaults for hardware so code examples behave the same across different
* devices.
*
***************************************************************************************************
* \copyright
* Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
**************************************************************************************************/
#pragma once
#include "cy_result.h"
#include "cybsp_types.h"
#include "cycfg_pins.h"
#if defined(__cplusplus)
extern "C" {
#endif
#ifndef CYBSP_USER_BTN_DRIVE
#define CYBSP_USER_BTN_DRIVE (CYHAL_GPIO_DRIVE_PULLUP)
#endif
#ifndef CYBSP_DEBUG_UART_CTS
#define CYBSP_DEBUG_UART_CTS (NC)
#endif
#ifndef CYBSP_DEBUG_UART_RTS
#define CYBSP_DEBUG_UART_RTS (NC)
#endif
#if defined(__cplusplus)
}
#endif

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/***********************************************************************************************//**
* \copyright
* Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
**************************************************************************************************/
#pragma once
#include "cybsp_doc.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \cond INTERNAL
*/
/* WIFI interface types */
#define CYBSP_SDIO_INTERFACE (0)
#define CYBSP_SPI_INTERFACE (1)
#define CYBSP_M2M_INTERFACE (2)
/* Map from the new components to the old interface names for
* compatibility with code that still depends on those defines */
#if defined(COMPONENT_WIFI_INTERFACE_SDIO)
#define CYBSP_WIFI_INTERFACE_TYPE (CYBSP_SDIO_INTERFACE)
#elif defined(COMPONENT_WIFI_INTERFACE_SPI)
#define CYBSP_WIFI_INTERFACE_TYPE (CYBSP_SPI_INTERFACE)
#elif defined(COMPONENT_WIFI_INTERFACE_M2M)
#define CYBSP_WIFI_INTERFACE_TYPE (CYBSP_M2M_INTERFACE)
#endif
/** \endcond */
/**
* \addtogroup group_bsp_pin_state Pin States
* \{
* Macros to abstract out whether the LEDs & Buttons are wired high or active low.
*/
/** Pin state for the LED on. */
#ifndef CYBSP_LED_STATE_ON
#define CYBSP_LED_STATE_ON (0U)
#endif
/** Pin state for the LED off. */
#ifndef CYBSP_LED_STATE_OFF
#define CYBSP_LED_STATE_OFF (1U)
#endif
/** Pin state for when a button is pressed. */
#ifndef CYBSP_BTN_PRESSED
#define CYBSP_BTN_PRESSED (0U)
#endif
/** Pin state for when a button is released. */
#ifndef CYBSP_BTN_OFF
#define CYBSP_BTN_OFF (1U)
#endif
/** \} group_bsp_pin_state */
#if defined(__cplusplus)
}
#endif

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https://github.com/Infineon/cat1cm0p#release-v1.8.0#$$ASSET_REPO$$/cat1cm0p/release-v1.8.0

1
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https://github.com/cypresssemiconductorco/core-lib#release-v1.4.3#$$ASSET_REPO$$/core-lib/release-v1.4.3

1
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https://github.com/cypresssemiconductorco/core-make#release-v3.4.1#$$ASSET_REPO$$/core-make/release-v3.4.1

1
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https://github.com/cypresssemiconductorco/mtb-hal-cat1#release-v2.6.2#$$ASSET_REPO$$/mtb-hal-cat1/release-v2.6.2

1
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https://github.com/cypresssemiconductorco/mtb-pdl-cat1#release-v3.15.0#$$ASSET_REPO$$/mtb-pdl-cat1/release-v3.15.0

1
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https://github.com/Infineon/recipe-make-cat1c#release-v1.4.1#$$ASSET_REPO$$/recipe-make-cat1c/release-v1.4.1

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{
"core": {
"version": "2.3.0.44500"
},
"opt": {
"props": {
"capabilities": [
"adc",
"arduino",
"bsp_gen5",
"can",
"cat1",
"cat1c",
"dma",
"ethernet",
"flash_4160k",
"hal",
"i2c",
"i2s",
"kit_xmc71_evk_lite_v2",
"led",
"low_power",
"lptimer",
"mcu_gp",
"memory",
"memory_qspi",
"multi_core",
"nor_flash",
"qspi",
"rtc",
"sdhc",
"sdio",
"smart_io",
"spi",
"sram_768k",
"std_crypto",
"switch",
"uart",
"xmc7000"
],
"dependencies": {
"cat1cm0p": "release-v1.8.0",
"core-lib": "release-v1.4.3",
"core-make": "release-v3.4.1",
"mtb-hal-cat1": "release-v2.6.2",
"mtb-pdl-cat1": "release-v3.15.0",
"recipe-make-cat1c": "release-v1.4.1"
},
"docs_dir": "docs",
"flow_version": "2.0",
"min_tools": "3.0.0",
"template": {
"id": "mtb-template-cat1",
"version": "release-v1.6.0"
}
}
}
}

9
bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/startup_cat1c.h Normal file
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#ifndef __STARTUP_CAT1C_H__
#define __STARTUP_CAT1C_H__
#define FIXED_EXP_NR (15u)
#define VECTORTABLE_SIZE (16u + FIXED_EXP_NR + 1u) /* +1 is for Stack pointer */
#define VECTORTABLE_ALIGN (128) /* alignment for 85 entries (32x4=128) is 2^7=128 bytes */
#endif /* __STARTUP_CAT1C_H__ */

582
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/***************************************************************************//**
* \file system_cat1c.h
* \version 1.0
*
* \brief Device system header file.
*
********************************************************************************
* \copyright
* Copyright 2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#ifndef _SYSTEM_FACELIFT_H_
#define _SYSTEM_FACELIFT_H_
/**
* \addtogroup group_system_config_cm7
* \{
* Provides device startup, system configuration, and linker script files.
* The system startup provides the followings features:
* - \ref group_system_config_device_memory_definition_cm7
* - \ref group_system_config_device_initialization_cm7
* - \ref group_system_config_heap_stack_config_cm7
* - \ref group_system_config_default_handlers_cm7
* - \ref group_system_config_device_vector_table_cm7
* - \ref group_system_config_cm7_functions
*
* \section group_system_config_configuration_cm7 Configuration Considerations
*
* \subsection group_system_config_device_memory_definition_cm7 Device Memory Definition
* Allocation of different types of memory such as the flash, RAM etc., for the CPU is defined by the linker scripts.
*
* \note - The linker files provided with the PDL are generic and handle all common
* use cases. Your project may not use every section defined in the linker files.
* In that case you may see warnings during the build process. To eliminate build
* warnings in your project, you can simply comment out or remove the relevant
* code in the linker file.
*
* \note - There is a common linker script for both CM7_0 and CM7_1 core.
* By default it links for CM7_0 core. But if the application is built for CM7_1, then a linker option _CORE_cm7_1 is provided in build system.
* For example, below piece of code is implemented in the build system.
* \code
* ifeq ($(TOOLCHAIN),IAR)
* LDFLAGS += --config_def _CORE_cm7_1_=1
* else ifeq ($(TOOLCHAIN),GCC_ARM)
* LDFLAGS += -Wl,'--defsym=_CORE_cm7_1_=1'
* endif
* \endcode
*
* <b>ARM GCC</b>\n
* The flash and RAM sections for the CPU are defined in the linker files:
* 'xx_yy_zz.ld', where 'xx_ yy' is the device group, and 'zz' is the target CPU;
* for example, 'xmc7200d_x8384_cm7.ld', 'xmc7100d_x4160_cm7.ld', 'xmc7200d_x8384_cm0plus.ld' and 'xmc7100d_x4160_cm0plus.ld'.
* \note If the start of the Cortex-M7_0 or Cortex-M7_1 application image is changed, the value
* of the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR should also be changed. The
* \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR macro should be used as the parameter for the
* Cy_SysEnableCM7() function call.
* By default,
* - the COMPONENT_XMC7x_CM0P_SLEEP prebuilt image is used for the CM0p core of the XMC dual-core MCU device (CM0+, CM7_0).
* - the COMPONENT_XMC7xDUAL_CM0P_SLEEP prebuilt image is used for the CM0p core of the XMC dual CM7-core MCU device (CM0+, CM7_0 and CM7_1).
*
* Change the flash and RAM sizes by editing the macro values in the
* linker files for both CPUs:
* - 'xx_yy_cm0plus.ld', where 'xx_yy' is the device group:
* \code
* cm0_ram (rxw) : ORIGIN = _base_SRAM_CM0P, LENGTH = _size_SRAM_CM0P
* cm0_flash (rx) : ORIGIN = _base_CODE_FLASH_CM0P,LENGTH = _size_CODE_FLASH_CM0P
* \endcode
* - 'xx_yy_cm7.ld', where 'xx_yy' is the device group:
* \code
* ram (rxw) : ORIGIN = _base_SRAM, LENGTH = _size_SRAM
* flash_cm0p (rx) : ORIGIN = _base_CODE_FLASH_CM0P, LENGTH = _size_CODE_FLASH_CM0P
* flash (rx) : ORIGIN = _base_CODE_FLASH, LENGTH = _size_CODE_FLASH
* \endcode
*
* Change the value of the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR
* macro to the ROM ORIGIN's value (0x10000000) + FLASH_CM0P_SIZE
* value (0x80000, the size of a flash image of the Cortex-M0+ application should be the
* same value as the flash LENGTH in 'xx_yy_cm0plus.ld') in the 'xx_yy_cm7.ld' file,
* where 'xx_yy' is the device group.
*
* - Do this by editing the the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR value
* in the 'system_xx.h', where 'xx' is the device family:\n
* \code
* #define CY_CORTEX_M7_0_APPL_ADDR BASE_CODE_FLASH_CM7_0
* #define CY_CORTEX_M7_1_APPL_ADDR BASE_CODE_FLASH_CM7_1
* \endcode
* 'BASE_CODE_FLASH_CM7_0' and ''BASE_CODE_FLASH_CM7_1' macros are defined in the xmc7xxx_partition.h
*
* <b>ARM Compiler</b>\n
* The flash and RAM sections for the CPU are defined in the linker files:
* 'xx_yy_zz.sct', where 'xx_ yy' is the device group, and 'zz' is the target CPU;
* for example 'xmc7200d_x8384_cm7.sct', 'xmc7100d_x4160_cm7.sct', 'xmc7200d_x8384_cm0plus.sct' and 'xmc7100d_x4160_cm0plus.sct'.
*
* \note If the start of the Cortex-M7_0 or Cortex-M7_1 application image is changed, the value
* of the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR should also be changed. The
* \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR macro should be used as the parameter for the
* Cy_SysEnableCM7() function call.
* By default,
* - the COMPONENT_XMC7x_CM0P_SLEEP prebuilt image is used for the CM0p core of the XMC dual-core MCU device (CM0+, CM7_0).
* - the COMPONENT_XMC7xDUAL_CM0P_SLEEP prebuilt image is used for the CM0p core of the XMC dual CM7-core MCU device (CM0+, CM7_0 and CM7_1).
*
* \note The linker files provided with the PDL are generic and handle all common
* use cases. Your project may not use every section defined in the linker files.
* In that case you may see the warnings during the build process:
* L6314W (no section matches pattern) and/or L6329W
* (pattern only matches removed unused sections). In your project, you can
* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
* the linker. You can also comment out or remove the relevant code in the linker
* file.
*
* Change the flash and RAM sizes by editing the macros value in the
* linker files for both CPUs:
* - 'xx_yy_cm0plus.sct', where 'xx_yy' is the device group:
* \code
* #define SRAM_BASE_ADDRESS 0x28000000
* #define CM0PLUS_SRAM_RESERVE 0x00020000
* #define CODE_FLASH_BASE_ADDRESS 0x10000000
* #define CM0PLUS_CODE_FLASH_RESERVE 0x00080000
* \endcode
* - 'xx_yy_cm7.sct', where 'xx_yy' is the device group:
* \code
* #define SRAM_BASE_ADDRESS 0x28000000 //SRAM START
* #define CM7_0_SRAM_RESERVE 0x00060000 //cm7_0 sram size
* #define BASE_SRAM_CM7_0 SRAM_BASE_ADDRESS + CM0PLUS_SRAM_RESERVE
* #define SIZE_SRAM_CM7_0 CM7_0_SRAM_RESERVE
* //In case of dual CM7-core MCU device device
* #define SIZE_SRAM_CM7_1 SRAM_TOTAL_SIZE - CM0PLUS_SRAM_RESERVE - CM7_0_SRAM_RESERVE
* #define BASE_SRAM_CM7_1 SRAM_BASE_ADDRESS + CM0PLUS_SRAM_RESERVE + CM7_0_SRAM_RESERVE
*
* #define CODE_FLASH_BASE_ADDRESS 0x10000000 //FLASH START
* #define CM7_0_CODE_FLASH_RESERVE 0x00200000 //cm7_0 flash size
* #define BASE_CODE_FLASH_CM7_0 CODE_FLASH_BASE_ADDRESS + CM0PLUS_CODE_FLASH_RESERVE
* #define SIZE_CODE_FLASH_CM7_0 CM7_0_CODE_FLASH_RESERVE
* //In case of dual CM7-core MCU device device
* #define BASE_CODE_FLASH_CM7_1 CODE_FLASH_BASE_ADDRESS + CM0PLUS_CODE_FLASH_RESERVE + CM7_0_CODE_FLASH_RESERVE
* #define SIZE_CODE_FLASH_CM7_1 CODE_FLASH_TOTAL_SIZE - CM0PLUS_CODE_FLASH_RESERVE - CM7_0_CODE_FLASH_RESERVE
* \endcode
*
* Change the value of the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR
* macro to the ROM ORIGIN's value (0x10000000) + FLASH_CM0P_SIZE
* value (0x80000, the size of a flash image of the Cortex-M0+ application should be the
* same value as the flash LENGTH in 'xx_yy_cm0plus.sct') in the 'xx_yy_cm7.sct' file,
* where 'xx_yy' is the device group.
*
* - Do this by editing the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR value
* in the 'system_xx.h', where 'xx' is the device family:\n
* \code
* #define CY_CORTEX_M7_0_APPL_ADDR BASE_CODE_FLASH_CM7_0
* #define CY_CORTEX_M7_1_APPL_ADDR BASE_CODE_FLASH_CM7_1
* \endcode
* 'BASE_CODE_FLASH_CM7_0' and ''BASE_CODE_FLASH_CM7_1' macros are defined in the xmc7xxx_partition.h
* <b>IAR</b>\n
* The flash and RAM sections for the CPU are defined in the linker files:
* 'xx_yy_zz.icf', where 'xx_ yy' is the device group, and 'zz' is the target CPU; for example,
* 'xmc7200d_x8384_cm7.icf','xmc7100d_x4160_cm7.icf','xmc7200d_x8384_cm0plus.icf' and 'xmc7100d_x4160_cm0plus.icf'.
* \note If the start of the Cortex-M7_0 or Cortex-M7_1 application image is changed, the value
* of the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR should also be changed. The
* \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR macro should be used as the parameter for the
* Cy_SysEnableCM7() function call.
* By default,
* - the COMPONENT_XMC7x_CM0P_SLEEP prebuilt image is used for the CM0p core of the XMC dual-core MCU device (CM0+, CM7_0).
* - the COMPONENT_XMC7xDUAL_CM0P_SLEEP prebuilt image is used for the CM0p core of the XMC dual CM7-core MCU device (CM0+, CM7_0 and CM7_1).
*
* Change the flash and RAM sizes by editing the macros value in the
* linker files for both CPUs:
* - 'xx_yy_cm0plus.icf', where 'xx_yy' is the device group:
* \code
* define symbol sram_base_address = 0x28000000;
* define symbol cm0plus_sram_reserve = 0x00020000; //cm0 sram size
* define symbol code_flash_base_address = 0x10000000;
* define symbol cm0plus_code_flash_reserve = 0x00080000; //cm0 flash size
* \endcode
* - 'xx_yy_cm7.icf', where 'xx_yy' is the device group:
* \code
* define symbol sram_base_address = 0x28000000;
* define symbol cm7_0_sram_reserve = 0x00060000;
* define symbol _base_SRAM_CM7_0 = sram_base_address + cm0plus_sram_reserve;
* define symbol _size_SRAM_CM7_0 = cm7_0_sram_reserve;
* //In case of dual CM7-core MCU device device
* define symbol _base_SRAM_CM7_1 = sram_base_address + cm0plus_sram_reserve + cm7_0_sram_reserve;
* define symbol _size_SRAM_CM7_1 = sram_total_size - cm0plus_sram_reserve - cm7_0_sram_reserve;
*
* define symbol code_flash_base_address = 0x10000000;
* define symbol cm7_0_code_flash_reserve = 0x00200000;
* define symbol _base_CODE_FLASH_CM7_0 = code_flash_base_address + cm0plus_code_flash_reserve;
* define symbol _size_CODE_FLASH_CM7_0 = cm7_0_code_flash_reserve;
* //In case of dual CM7-core MCU device device
* define symbol _base_CODE_FLASH_CM7_1 = code_flash_base_address + cm0plus_code_flash_reserve + cm7_0_code_flash_reserve;
* define symbol _size_CODE_FLASH_CM7_1 = code_flash_total_size - cm0plus_code_flash_reserve - cm7_0_code_flash_reserve;
* \endcode
*
* Change the value of the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR
* macro to the ROM ORIGIN's value (0x10000000) + FLASH_CM0P_SIZE
* value (0x80000, the size of a flash image of the Cortex-M0+ application should be the
* same value as the flash LENGTH in 'xx_yy_cm0plus.icf') in the 'xx_yy_cm7.icf' file,
* where 'xx_yy' is the device group.
*
* - Do this by editing the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR value
* in the 'system_xx.h', where 'xx' is the device family:\n
* \code
* #define CY_CORTEX_M7_0_APPL_ADDR BASE_CODE_FLASH_CM7_0
* #define CY_CORTEX_M7_1_APPL_ADDR BASE_CODE_FLASH_CM7_1
* \endcode
* 'BASE_CODE_FLASH_CM7_0' and ''BASE_CODE_FLASH_CM7_1' macros are defined in the xmc7xxx_partition.h
*
* \subsection group_system_config_device_initialization_cm7 Device Initialization
* After a power-on-reset (POR), the CM0+ starts boot-ROM directly from ROM and boot-ROM starts CM0+ startup.
* The CM0+ startup starts CM0+ user application. The CM0+ user application enables CM7 cores and starts CM7 startup.
* The startup code is the piece of code which is executed after every system reset.
* It initializes the system components like, memory, FPU, interrupts, clock, etc. and calls application's main() function.
* The startup code is always build as part of user application. There are two different startup codes for CM0+ and CM7 core.
*
* The CM0+ startup code implements the following functions to run the CM0+ application:
*
* 1. In the Reset Handler, it disables global interrupts
* 3. Disables the SRAM ECC checking: CM0+ bus width is 32-bit, but SRAM is built with 64-bit based ECC on Facelift parts with CM7 core,
* sets CPUSS->RAMx_CTL0.ECC_CHECK_DIS bits to avoid causing unintentional ECC faults during startup while SRAM ECC has not been initialized yet.
* 4. Calls SystemInit() function
* - Initializes and enables the SRAM memory for ECC
* - Copies the vector table from ROM to RAM and updates the VTOR (Vector Table Offset Register)
* - Sets the CM0+ IRQ0 and IRQ1 handlers from SROM vector table, sets the CM0+ IRQ0 and IRQ1priority,
* then enables these interrupts: the SROM APIs are executed by CM0+ core in interrupt context using IRQ0 and IRQ1.
* So, proper interrupt handler addresses and priorities need to be configured for IRQ0 and IRQ1
* - Unlocks and disable WDT (Watchdog timer)
* - Calls the SystemCoreClockUpdate()
* 5. Executes main() application
*
* The CM7 startup code implement the following functions to run the CM7 user application:
*
* 1. In the Reset handler, it disables global interrupts
* 2. Allows write access to Vector Table Offset Register and ITCM/DTCM configuration register
* 3. Enables CM7 core ITCM and DTCM
* 4. Enables the FPU if it is used
* 5. Copies the vector table from ROM to RAM and updates the VTOR (Vector Table Offset Register)
* 6. Enables the CM7 core instruction and data cache
* 7. Calls SystemInit() function
* - Unlocks and disable WDT (Watchdog timer)
* - Calls the SystemCoreClockUpdate()
* 6. Executes CM7 main() application
*
* \subsection group_system_config_heap_stack_config_cm7 Heap and Stack Configuration
* By default, the stack size is set to 0x00001000 and the Heap size is allocated
* dynamically to the whole available free memory up to stack memory.
* The Stack grows from higher to lower address. The Stack top or start is assigned to end of SRAM address.
* The Heap grows opposite of Stack. It grows from lower to higher address.
* The Heap top starts from end of used data section till Stack end.
*
* \subsubsection group_system_config_heap_stack_config_gcc_cm7 ARM GCC
* <b>Editing source code files</b>\n
* The stack size is defined in the linker script files: 'xx_yy_zz.ld',
* 'xx_yy_zz.ld', where 'xx_ yy' is the device group, and 'zz' is the target CPU; for example,
* 'xmc7200d_x8384_cm7.ld', 'xmc7100d_x4160_cm7.ld', 'xmc7200d_x8384_cm0plus.ld' and 'xmc7100d_x4160_cm0plus.ld'.
* Change the stack size by modifying the following line:\n
* \code STACK_SIZE = 0x1000; \endcode
*
* \note Correct operation of malloc and related functions depends on the working
* implementation of the 'sbrk' function. Newlib-nano (default C runtime library
* used by the GNU Arm Embedded toolchain) provides weak 'sbrk' implementation that
* doesn't check for heap and stack collisions during excessive memory allocations.
* To ensure the heap always remains within the range defined by __HeapBase and
* __HeapLimit linker symbols, provide a strong override for the 'sbrk' function:
* \snippet startup/snippet/main.c snippet_sbrk
* For FreeRTOS-enabled multi-threaded applications, it is sufficient to include
* clib-support library that provides newlib-compatible implementations of
* 'sbrk', '__malloc_lock' and '__malloc_unlock':
* <br>
* https://github.com/Infineon/clib-support.
*
* \subsubsection group_system_config_heap_stack_config_mdk_cm7 ARM Compiler
* <b>Editing source code files</b>\n
* The stack size is defined in the linker script files: 'xx_yy_zz.sct',
* 'xx_yy_zz.sct', where 'xx_ yy' is the device group, and 'zz' is the target CPU; for example,
* 'xmc7200d_x8384_cm7.sct', 'xmc7100d_x4160_cm7.sct', 'xmc7200d_x8384_cm0plus.sct' and 'xmc7100d_x4160_cm0plus.sct'.
* Change the stack size by modifying the following line:\n
* \code #define STACK_SIZE 0x1000 \endcode
*
* \subsubsection group_system_config_heap_stack_config_iar_cm7 IAR
* <b>Editing source code files</b>\n
* The heap and stack sizes are defined in the linker script files: 'xx_yy_zz.icf',
* where 'xx_ yy' is the device group, and 'zz' is the target CPU; for example,
* 'xmc7200d_x8384_cm7.icf','xmc7100d_x4160_cm7.icf','xmc7200d_x8384_cm0plus.icf' and 'xmc7100d_x4160_cm0plus.icf'.
* Change the heap and stack sizes by modifying the following lines:\n
* \code define symbol cm7_stack_reserve = 0x00001000; \endcode
*
* \subsection group_system_config_default_handlers_cm7 Default Interrupt Handlers Definition
* The default interrupt handler functions are defined as weak functions to a dummy
* handler in the startup file. The naming convention for the interrupt handler names
* is \<interrupt_name\>_IRQHandler. A default interrupt handler can be overwritten in
* user code by defining the handler function using the same name. For example:
* \code
* void scb_0_interrupt_IRQHandler(void)
*{
* ...
*}
* \endcode
*
* \subsection group_system_config_device_vector_table_cm7 Vectors Table Copy from Flash to RAM
* This process uses memory sections defined in the linker script. The startup
* code actually defines the contents of the vector table and performs the copy.
*
* \subsubsection group_system_config_device_vector_table_gcc_cm7 ARM GCC
* The linker script file is 'xx_yy_zz.ld', where 'xx_ yy' is the device group, and 'zz' is the target CPU;
* for example, 'xmc7200d_x8384_cm7.ld', 'xmc7100d_x4160_cm7.ld', 'xmc7200d_x8384_cm0plus.ld' and 'xmc7100d_x4160_cm0plus.ld'.
* It defines sections and locations in memory.\n
* Copy interrupt vectors from flash to RAM: \n
* From: \code LONG (__Vectors) \endcode
* To: \code LONG (__ram_vectors_start__) \endcode
* Size: \code LONG (__Vectors_End - __Vectors) \endcode
* The vector table address (and the vector table itself) are defined in the
* startup files (e.g. startup_cm0plus.S and startup_cm7.c).
* The code in these files copies the vector table from Flash to RAM.
*
* \subsubsection group_system_config_device_vector_table_mdk_cm7 ARM Compiler
* The linker script file is 'xx_yy_zz.sct', where 'xx_ yy' is the device group, and 'zz' is the target CPU;
* for example 'xmc7200d_x8384_cm7.sct', 'xmc7100d_x4160_cm7.sct', 'xmc7200d_x8384_cm0plus.sct' and
* 'xmc7100d_x4160_cm0plus.sct'. The linker script specifies that the vector table
* (RESET_RAM) shall be first in the RAM section.\n
* RESET_RAM represents the vector table. It is defined in the startup
* files (e.g. startup_cm0plus.S and startup_cm7.c).
* The code in these files copies the vector table from Flash to RAM.
*
* \subsubsection group_system_config_device_vector_table_iar_cm7 IAR
* The linker script file is 'xx_yy_zz.icf', where 'xx_ yy' is the device group, and 'zz' is the target CPU;
* for example, 'xmc7200d_x8384_cm7.icf','xmc7100d_x4160_cm7.icf','xmc7200d_x8384_cm0plus.icf' and '
* 'xmc7100d_x4160_cm0plus.icf'.\n
* The vector table address (and the vector table itself) are defined in the
* startup files (e.g. startup_cm0plus.S and startup_cm7.c).
* The code in these files copies the vector table from Flash to RAM.
*
* \section group_system_config_changelog_cm7 Changelog
* <table class="doxtable">
* <tr>
* <th>Version</th>
* <th>Changes</th>
* <th>Reason for Change</th>
* </tr>
* <tr>
* <td>1.0</td>
* <td>Initial version</td>
* <td></td>
* </tr>
* </table>
*
* \defgroup group_system_config_macro_cm7 Macros
* \{
* \defgroup group_system_config_system_macro_cm7 System Macros
* \}
* \defgroup group_system_config_functions_cm7 Functions
* \{
* \defgroup group_system_config_cm7_functions Cortex-M7 Control
* \}
* \}
*/
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************
* Include files
*******************************************************************************/
#include <stdint.h>
#if defined (CY_DEVICE_TVIIC2D6M)
#include "tviic_partition.h"
#else
#include "xmc7xxx_partition.h"
#endif
/*******************************************************************************
* Global preprocessor symbols/macros ('define')
*******************************************************************************/
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined (__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)))
#define CY_SYSTEM_CPU_CM0P 1UL
#else
#define CY_SYSTEM_CPU_CM0P 0UL
#endif
/*******************************************************************************
*
* START OF USER SETTINGS HERE
* ===========================
*
* All lines with '<<<' can be set by user.
*
*******************************************************************************/
/**
* \addtogroup group_system_config_system_macro_cm7
* \{
*/
/*******************************************************************************
*
* END OF USER SETTINGS HERE
* =========================
*
*******************************************************************************/
/** Start address of the Cortex-M7_0 application */
#ifndef CY_CORTEX_M7_0_APPL_ADDR
#define CY_CORTEX_M7_0_APPL_ADDR BASE_CODE_FLASH_CM7_0
#endif
/** Start address of the Cortex-M7_1 application */
#ifndef CY_CORTEX_M7_1_APPL_ADDR
#define CY_CORTEX_M7_1_APPL_ADDR BASE_CODE_FLASH_CM7_1
#endif
/** The Cortex-M7 core is enabled: power on, clock on, no isolate, no reset and no retain. */
#define CY_SYS_CM7_STATUS_ENABLED (3U)
/** The Cortex-M7 core is disabled: power off, clock off, isolate, reset and no retain. */
#define CY_SYS_CM7_STATUS_DISABLED (0U)
/** The Cortex-M7 core is retained. power off, clock off, isolate, no reset and retain. */
#define CY_SYS_CM7_STATUS_RETAINED (2U)
/** The Cortex-M7 core is in the Reset mode: clock off, no isolated, no retain and reset. */
#define CY_SYS_CM7_STATUS_RESET (1U)
/** \} group_system_config_system_macro_cm7 */
/** \cond */
/** Cortex-M7 core 0 */
#define CORE_CM7_0 (0U)
/** Cortex-M7 core 1 */
#define CORE_CM7_1 (1U)
/** Error Selection */
#define CORE_MAX (2U)
/** Define start of the function placed to the ITCM area by the linker */
#ifndef CY_SECTION_ITCM_BEGIN
#define CY_SECTION_ITCM_BEGIN CY_SECTION(".cy_itcm")
#endif
/** Define end of the function placed to the ITCM area by the linker */
#ifndef CY_SECTION_ITCM_END
#define CY_SECTION_ITCM_END
#endif
extern uint32_t cy_delayFreqHz;
extern uint32_t cy_delayFreqKhz;
extern uint32_t cy_delayFreqMhz;
extern uint32_t SystemCoreClock;
extern uint32_t cy_Hfclk0FreqHz;
extern uint32_t cy_PeriClkFreqHz;
extern uint32_t cy_AhbFreqHz;
extern void SystemInit(void);
extern void SystemIrqInit(void);
extern void SystemCoreClockUpdate(void);
/** \endcond */
/**
* \addtogroup group_system_config_cm7_functions
* \{
*/
/*******************************************************************************
* Function Name: Cy_SysGetCM7Status
****************************************************************************//**
*
* Gets the Cortex-M7 core power mode.
*
* \param core Core type (CM7_0 or CM7_1).
*
* \return \ref group_system_config_system_macro_cm7 \n
* If 0: CY_SYS_CM7_STATUS_DISABLED \n
* 1: CY_SYS_CM7_STATUS_RESET \n
* 2: CY_SYS_CM7_STATUS_RETAINED \n
* 3: CY_SYS_CM7_STATUS_ENABLED \n
*
******************************************************************************/
extern uint32_t Cy_SysGetCM7Status(uint8_t core);
/*******************************************************************************
* Function Name: Cy_SysEnableCM7
****************************************************************************//**
*
* Enables the Cortex-M7 core. The CPU is enabled once if it was in the disabled
* or retained mode.
*
* \param core Core type (CM7_0 or CM7_1).
*
* \param vectorTableOffset The offset of the vector table base address from
* memory address 0x00000000. The offset should be multiple to 1024 bytes.
*
*******************************************************************************/
extern void Cy_SysEnableCM7(uint8_t core, uint32_t vectorTableOffset);
/*******************************************************************************
* Function Name: Cy_SysDisableCM7
****************************************************************************//**
*
* Disables the Cortex-M7 core.
*
* \param core Core type (CM7_0 or CM7_1).
*
* \warning Do not call the function while the Cortex-M7 is executing because
* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
* unexpected behavior in the system including a deadlock. Call the function
* while the Cortex-M7 core is in the Sleep or Deep Sleep low-power mode. Use
* the \ref group_syspm Power Management (syspm) API to put the CPU into the
* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU.
*
*******************************************************************************/
extern void Cy_SysDisableCM7(uint8_t core);
/*******************************************************************************
* Function Name: Cy_SysRetainCM7
****************************************************************************//**
*
* Retains the Cortex-M7 core.
*
* \param core Core type (CM7_0 or CM7_1).
*
* \warning Do not call the function while the Cortex-M7 is executing because
* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
* unexpected behavior in the system including a deadlock. Call the function
* while the Cortex-M7 core is in the Sleep or Deep Sleep low-power mode. Use
* the \ref group_syspm Power Management (syspm) API to put the CPU into the
* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU.
*
*******************************************************************************/
extern void Cy_SysRetainCM7(uint8_t core);
/*******************************************************************************
* Function Name: Cy_SysResetCM7
****************************************************************************//**
*
* Resets the Cortex-M7 core.
*
* \param core Core type (CM7_0 or CM7_1).
*
* \warning Do not call the function while the Cortex-M7 is executing because
* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
* unexpected behavior in the system including a deadlock. Call the function
* while the Cortex-M7 core is in the Sleep or Deep Sleep low-power mode. Use
* the \ref group_syspm Power Management (syspm) API to put the CPU into the
* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU.
*
*******************************************************************************/
extern void Cy_SysResetCM7(uint8_t core);
/** \} group_system_config_cm7_functions */
/** \cond */
extern void Default_Handler (void);
extern void Cy_SystemInit(void);
extern void Cy_SystemInitFpuEnable(void);
extern void CyMain(void);
#define Cy_SaveIRQ Cy_SysLib_EnterCriticalSection
#define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection
/** \endcond */
#ifdef __cplusplus
}
#endif
#endif /* _SYSTEM_FACELIFT_H_ */
/* [] END OF FILE */

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#if !defined(LAYOUT_CAT1C_H)
#define LAYOUT_CAT1C_H
#define STACK_SIZE 0x1000
#define RAMVECTORS_ALIGNMENT 128
#define SRAM_START_RESERVE 0
#define SRAM_PRIVATE_FOR_SROM 0x800 /* 2K Private SRAM for SROM (e.g. API processing). Reserved at the beginning */
/* RAM */
#define SRAM_BASE_ADDRESS CY_SRAM_BASE /* SRAM START */
#define TOTAL_RAM CY_SRAM_SIZE
#define CM0PLUS_SRAM_RESERVE 0x00004000 /* 16K cm0plus */
/* FLASH */
#define CODE_FLASH_BASE_ADDRESS CY_FLASH_LG_SBM_BASE /* FLASH START */
#define TOTAL_FLASH (CY_FLASH_LG_SBM_SIZE + CY_FLASH_SM_SBM_SIZE)
#define CM0PLUS_CODE_FLASH_RESERVE 0x00080000 /* 512K CM0P FLASH SIZE */
/* CM7_1 RAM and FLASH */
#if defined (__CM7_1_PRESENT)
#define CM7_1_SRAM_RESERVE 0x00010000 /* (SRAM0/64KB) -> cm7_1 */
#else
#define CM7_1_SRAM_RESERVE 0x00000000UL
#endif
#if (TOTAL_FLASH == 0x830000) /** 8M device */
#define CM7_0_CODE_FLASH_RESERVE 0x00200000
#elif (TOTAL_FLASH == 0x410000) /** 4M device */
#define CM7_0_CODE_FLASH_RESERVE 0x00200000
#elif (TOTAL_FLASH == 0x210000) /** 2M device */
#define CM7_0_CODE_FLASH_RESERVE 0x00100000
#elif (TOTAL_FLASH == 0x110000) /** 1M device */
#define CM7_0_CODE_FLASH_RESERVE 0x00090000
#else
#error "Invalid device"
#endif
/* SRAM reservations */
#define BASE_SRAM_CM0P (SRAM_BASE_ADDRESS + SRAM_START_RESERVE + SRAM_PRIVATE_FOR_SROM)
#define SIZE_SRAM_CM0P (CM0PLUS_SRAM_RESERVE - SRAM_START_RESERVE - SRAM_PRIVATE_FOR_SROM)
#define BASE_SRAM_CM7_0 (SRAM_BASE_ADDRESS + CM0PLUS_SRAM_RESERVE)
#define SIZE_SRAM_CM7_0 TOTAL_RAM - CM0PLUS_SRAM_RESERVE - CM7_1_SRAM_RESERVE
#define BASE_SRAM_CM7_1 SRAM_BASE_ADDRESS + CM0PLUS_SRAM_RESERVE + SIZE_SRAM_CM7_0
/* Code flash reservations */
#define BASE_CODE_FLASH_CM0P CODE_FLASH_BASE_ADDRESS
#define SIZE_CODE_FLASH_CM0P CM0PLUS_CODE_FLASH_RESERVE
#define BASE_CODE_FLASH_CM7_0 CODE_FLASH_BASE_ADDRESS + CM0PLUS_CODE_FLASH_RESERVE
#define SIZE_CODE_FLASH_CM7_0 CM7_0_CODE_FLASH_RESERVE
#define BASE_CODE_FLASH_CM7_1 CODE_FLASH_BASE_ADDRESS + CM0PLUS_CODE_FLASH_RESERVE + CM7_0_CODE_FLASH_RESERVE
#endif /* LAYOUT_CAT1C_H */
/* [] END OF FILE */

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#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* RT-Thread Kernel */
/* klibc options */
/* rt_vsnprintf options */
/* end of rt_vsnprintf options */
/* rt_vsscanf options */
/* end of rt_vsscanf options */
/* rt_memset options */
/* end of rt_memset options */
/* rt_memcpy options */
/* end of rt_memcpy options */
/* rt_memmove options */
/* end of rt_memmove options */
/* rt_memcmp options */
/* end of rt_memcmp options */
/* rt_strstr options */
/* end of rt_strstr options */
/* rt_strcasecmp options */
/* end of rt_strcasecmp options */
/* rt_strncpy options */
/* end of rt_strncpy options */
/* rt_strcpy options */
/* end of rt_strcpy options */
/* rt_strncmp options */
/* end of rt_strncmp options */
/* rt_strcmp options */
/* end of rt_strcmp options */
/* rt_strlen options */
/* end of rt_strlen options */
/* rt_strnlen options */
/* end of rt_strnlen options */
/* end of klibc options */
#define RT_NAME_MAX 8
#define RT_CPUS_NR 1
#define RT_ALIGN_SIZE 8
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_HOOKLIST
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 256
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 512
/* kservice options */
/* end of kservice options */
#define RT_USING_DEBUG
#define RT_DEBUGING_ASSERT
#define RT_DEBUGING_COLOR
#define RT_DEBUGING_CONTEXT
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* end of Inter-Thread communication */
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_USING_SMALL_MEM_AS_HEAP
#define RT_USING_HEAP
/* end of Memory Management */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart4"
#define RT_VER_NUM 0x50201
#define RT_BACKTRACE_LEVEL_MAX_NR 32
/* end of RT-Thread Kernel */
#define RT_USING_CACHE
#define RT_USING_HW_ATOMIC
#define RT_USING_CPU_FFS
#define ARCH_ARM
#define ARCH_ARM_CORTEX_M
#define ARCH_ARM_CORTEX_M7
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 2048
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
#define FINSH_USING_OPTION_COMPLETION
/* DFS: device virtual file system */
/* end of DFS: device virtual file system */
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_PIN
/* end of Device Drivers */
/* C/C++ and POSIX layer */
/* ISO-ANSI C layer */
/* Timezone and Daylight Saving Time */
#define RT_LIBC_USING_LIGHT_TZ_DST
#define RT_LIBC_TZ_DEFAULT_HOUR 8
#define RT_LIBC_TZ_DEFAULT_MIN 0
#define RT_LIBC_TZ_DEFAULT_SEC 0
/* end of Timezone and Daylight Saving Time */
/* end of ISO-ANSI C layer */
/* POSIX (Portable Operating System Interface) layer */
/* Interprocess Communication (IPC) */
/* Socket is in the 'Network' category */
/* end of Interprocess Communication (IPC) */
/* end of POSIX (Portable Operating System Interface) layer */
/* end of C/C++ and POSIX layer */
/* Network */
/* end of Network */
/* Memory protection */
/* end of Memory protection */
/* Utilities */
/* end of Utilities */
/* Using USB legacy version */
/* end of Using USB legacy version */
/* end of RT-Thread Components */
/* RT-Thread Utestcases */
/* end of RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* end of Marvell WiFi */
/* Wiced WiFi */
/* end of Wiced WiFi */
/* CYW43012 WiFi */
/* end of CYW43012 WiFi */
/* BL808 WiFi */
/* end of BL808 WiFi */
/* CYW43439 WiFi */
/* end of CYW43439 WiFi */
/* end of Wi-Fi */
/* IoT Cloud */
/* end of IoT Cloud */
/* end of IoT - internet of things */
/* security packages */
/* end of security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* end of XML: Extensible Markup Language */
/* end of language packages */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
/* end of LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
/* end of u8g2: a monochrome graphic library */
/* end of multimedia packages */
/* tools packages */
/* end of tools packages */
/* system packages */
/* enhanced kernel services */
/* end of enhanced kernel services */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* end of acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
/* end of Micrium: Micrium software products porting for RT-Thread */
/* end of system packages */
/* peripheral libraries and drivers */
/* HAL & SDK Drivers */
/* STM32 HAL & SDK Drivers */
/* end of STM32 HAL & SDK Drivers */
/* Infineon HAL Packages */
#define PKG_USING_INFINEON_CAT1CM0P
#define PKG_USING_INFINEON_CAT1CM0P_LATEST_VERSION
#define PKG_USING_INFINEON_CMSIS
#define PKG_USING_INFINEON_CMSIS_LATEST_VERSION
#define PKG_USING_INFINEON_CORE_LIB
#define PKG_USING_INFINEON_CORE_LIB_LATEST_VERSION
#define PKG_USING_INFINEON_MTB_HAL_CAT1
#define PKG_USING_INFINEON_MTB_HAL_CAT1_LATEST_VERSION
#define PKG_USING_INFINEON_MTB_PDL_CAT1
#define PKG_USING_INFINEON_MTB_PDL_CAT1_LATEST_VERSION
#define PKG_USING_INFINEON_RETARGET_IO
#define PKG_USING_INFINEON_RETARGET_IO_LATEST_VERSION
/* end of Infineon HAL Packages */
/* Kendryte SDK */
/* end of Kendryte SDK */
/* WCH HAL & SDK Drivers */
/* end of WCH HAL & SDK Drivers */
/* AT32 HAL & SDK Drivers */
/* end of AT32 HAL & SDK Drivers */
/* end of HAL & SDK Drivers */
/* sensors drivers */
/* end of sensors drivers */
/* touch drivers */
/* end of touch drivers */
/* end of peripheral libraries and drivers */
/* AI packages */
/* end of AI packages */
/* Signal Processing and Control Algorithm Packages */
/* end of Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
/* end of project laboratory */
/* samples: kernel and components samples */
/* end of samples: kernel and components samples */
/* entertainment: terminal games and other interesting software packages */
/* end of entertainment: terminal games and other interesting software packages */
/* end of miscellaneous packages */
/* Arduino libraries */
/* Projects and Demos */
/* end of Projects and Demos */
/* Sensors */
/* end of Sensors */
/* Display */
/* end of Display */
/* Timing */
/* end of Timing */
/* Data Processing */
/* end of Data Processing */
/* Data Storage */
/* Communication */
/* end of Communication */
/* Device Control */
/* end of Device Control */
/* Other */
/* end of Other */
/* Signal IO */
/* end of Signal IO */
/* Uncategorized */
/* end of Arduino libraries */
/* end of RT-Thread online packages */
#define SOC_FAMILY_IFX
#define SOC_SERIES_IFX_XMC
/* Hardware Drivers Config */
#define SOC_XMC7100D_F144K4160AA
/* Onboard Peripheral Drivers */
#define BSP_USING_USB_TO_USART
/* end of Onboard Peripheral Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_GPIO
#define BSP_USING_UART
#define BSP_USING_UART2
#define BSP_USING_UART4
#define UART_CPU_IRQ_Number 3
/* end of On-chip Peripheral Drivers */
/* end of Hardware Drivers Config */
#endif

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import os
# toolchains options
ARCH='arm'
CPU='cortex-m7'
CROSS_TOOL='armclang'
# bsp lib config
BSP_LIBRARY_TYPE = None
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
# cross_tool provides the cross compiler
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = r'C:\Users\XXYYZZ'
elif CROSS_TOOL == 'keil':
PLATFORM = 'armclang'
EXEC_PATH = r'C:/Keil_v5'
elif CROSS_TOOL == 'iar':
PLATFORM = 'iccarm'
EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3'
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
BUILD = 'debug'
if PLATFORM == 'gcc':
# toolchains
PREFIX = 'arm-none-eabi-'
CC = PREFIX + 'gcc'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
CXX = PREFIX + 'g++'
LINK = PREFIX + 'gcc'
TARGET_EXT = 'elf'
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
DEVICE = ' -mcpu=cortex-m7 -mthumb -mfpu=fpv5-d16 -mfloat-abi=softfp -ffunction-sections -fdata-sections -nostdlib -ffunction-sections -fno-strict-aliasing'
CFLAGS = DEVICE + ' -Dgcc'
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb --specs=nano.specs -ffat-lto-objects'
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.ld'
CPATH = ''
LPATH = ''
if BUILD == 'debug':
CFLAGS += ' -Og -gdwarf-2 -g'
AFLAGS += ' -gdwarf-2'
else:
CFLAGS += ' -O2'
CXXFLAGS = CFLAGS
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n '+OBJCPY+' -O ihex rt-thread.elf rt-thread.hex\n'
elif PLATFORM == 'armcc':
# toolchains
CC = 'armcc'
CXX = 'armcc'
AS = 'armasm'
AR = 'armar'
LINK = 'armlink'
TARGET_EXT = 'axf'
DEVICE = ' --cpu Cortex-M7.fp '
CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
AFLAGS = DEVICE + ' --apcs=interwork '
LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict'
CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib'
CFLAGS += ' -D__MICROLIB '
AFLAGS += ' --pd "__MICROLIB SETA 1" '
LFLAGS += ' --library_type=microlib '
EXEC_PATH += '/ARM/ARMCC/bin/'
if BUILD == 'debug':
CFLAGS += ' -g -O0'
AFLAGS += ' -g'
else:
CFLAGS += ' -O2'
CXXFLAGS = CFLAGS
CFLAGS += ' -std=c99'
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
elif PLATFORM == 'armclang':
# toolchains
CC = 'armclang'
CXX = 'armclang'
AS = 'armasm'
AR = 'armar'
LINK = 'armlink'
TARGET_EXT = 'axf'
DEVICE = ' --cpu Cortex-M7.fp '
CFLAGS = ' --target=arm-arm-none-eabi -mcpu=cortex-m7 '
CFLAGS += ' -mcpu=cortex-m7 -mfpu=fpv4-d16 '
CFLAGS += ' -mfloat-abi=softfp -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -nostdlib'
CFLAGS += ' -gdwarf-3 -ffunction-sections '
AFLAGS = DEVICE + ' --apcs=interwork '
LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers '
LFLAGS += ' --list rt-thread.map '
LFLAGS += r' --strict --scatter "board\linker_scripts\link.sct" '
CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include'
LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib'
EXEC_PATH += '/ARM/ARMCLANG/bin/'
if BUILD == 'debug':
CFLAGS += ' -g -O1' # armclang recommend
AFLAGS += ' -g'
else:
CFLAGS += ' -O2'
CXXFLAGS = CFLAGS
CFLAGS += ' -std=c99'
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
def dist_handle(BSP_ROOT, dist_dir):
import sys
cwd_path = os.getcwd()
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
from sdk_dist import dist_do_building
dist_do_building(BSP_ROOT, dist_dir)

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>Target 1</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\Listings\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>6</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>1</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>4</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon>Segger\JL2CM3.dll</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
<Name>UL2CM3(-S0 -C0 -P0 ) -FN5 -FCFFF0 -FD28001000 -FF0CAT1C_SFLASH_TOC2 -FF1CAT1C_SFLASH_PKEY -FF2CAT1C_SFLASH_USER -FF3CAT1C_WFLASH_256 -FF4CAT1C_4160 -FL0200 -FL1C00 -FL2800 -FL340000 -FL4410000 -FS017007C00 -FS117006400 -FS217000800 -FS314000000 -FS410000000 -FP0($$Device:XMC7100D-F144K4160$Flash\CAT1C_SFLASH_TOC2.FLM) -FP1($$Device:XMC7100D-F144K4160$Flash\CAT1C_SFLASH_PKEY.FLM) -FP2($$Device:XMC7100D-F144K4160$Flash\CAT1C_SFLASH_USER.FLM) -FP3($$Device:XMC7100D-F144K4160$Flash\CAT1C_WFLASH_256.FLM) -FP4($$Device:XMC7100D-F144K4160$Flash\CAT1C_4160.FLM)</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>1</periodic>
<aLwin>0</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>0</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>0</bLintAuto>
<bAutoGenD>0</bAutoGenD>
<LntExFlags>0</LntExFlags>
<pMisraName></pMisraName>
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
<Group>
<GroupName>Source Group 1</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
</Group>
</ProjectOpt>

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
<SchemaVersion>2.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>Target 1</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>6090000::V6.9::.\ARMCLANG</pCCUsed>
<uAC6>1</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>XMC7100D-F144K4160:Cortex-M7-0</Device>
<Vendor>Infineon</Vendor>
<PackID>Infineon.CAT1C_DFP.1.0.0</PackID>
<PackURL>https://github.com/Infineon/cmsis-packs/raw/master/CAT1C_DFP/</PackURL>
<Cpu>IRAM(0x28000000,0xC0000) IROM(0x10000000,0x410000) CPUTYPE("Cortex-M7") FPU3(SFPU) CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD28001000 -FCFFF0 -FN5 -FF0CAT1C_SFLASH_TOC2 -FS017007C00 -FL0200 -FF1CAT1C_SFLASH_PKEY -FS117006400 -FL1C00 -FF2CAT1C_SFLASH_USER -FS217000800 -FL2800 -FF3CAT1C_WFLASH_256 -FS314000000 -FL340000 -FF4CAT1C_4160 -FS410000000 -FL4410000 -FP0($$Device:XMC7100D-F144K4160$Flash\CAT1C_SFLASH_TOC2.FLM) -FP1($$Device:XMC7100D-F144K4160$Flash\CAT1C_SFLASH_PKEY.FLM) -FP2($$Device:XMC7100D-F144K4160$Flash\CAT1C_SFLASH_USER.FLM) -FP3($$Device:XMC7100D-F144K4160$Flash\CAT1C_WFLASH_256.FLM) -FP4($$Device:XMC7100D-F144K4160$Flash\CAT1C_4160.FLM))</FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile></RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>$$Device:XMC7100D-F144K4160$SVD\cat1c4m.svd</SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath></RegisterFilePath>
<DBRegisterFilePath></DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\Objects\</OutputDirectory>
<OutputName>rtthread</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>1</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>0</BrowseInformation>
<ListingPath>.\Listings\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
<nStopU2X>0</nStopU2X>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopB1X>0</nStopB1X>
<nStopB2X>0</nStopB2X>
</BeforeMake>
<AfterMake>
<RunUserProg1>1</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopA1X>0</nStopA1X>
<nStopA2X>0</nStopA2X>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<DllOption>
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments> -REMAP -MPU</SimDllArguments>
<SimDlgDll>DCM.DLL</SimDlgDll>
<SimDlgDllArguments>-pCM7</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments> -MPU</TargetDllArguments>
<TargetDlgDll>TCM.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM7</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
<Capability>0</Capability>
<DriverSelection>-1</DriverSelection>
</Flash1>
<bUseTDR>1</bUseTDR>
<Flash2>BIN\UL2CM3.DLL</Flash2>
<Flash3></Flash3>
<Flash4></Flash4>
<pFcarmOut></pFcarmOut>
<pFcarmGrp></pFcarmGrp>
<pFcArmRoot></pFcArmRoot>
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>1</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
<AdsLven>1</AdsLven>
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M7"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>1</hadIROM>
<hadIRAM>1</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>2</RvdsVP>
<hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
<useUlib>0</useUlib>
<EndSel>0</EndSel>
<uLtcg>0</uLtcg>
<nSecure>0</nSecure>
<RoSelD>3</RoSelD>
<RwSelD>3</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>0</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>1</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>1</Im1Chk>
<Im2Chk>0</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x28000000</StartAddress>
<Size>0xc0000</Size>
</IRAM>
<IROM>
<Type>1</Type>
<StartAddress>0x10000000</StartAddress>
<Size>0x410000</Size>
</IROM>
<XRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x10000000</StartAddress>
<Size>0x410000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x28000000</StartAddress>
<Size>0xc0000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>1</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>3</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>1</uC99>
<uGnu>1</uGnu>
<useXO>0</useXO>
<v6Lang>3</v6Lang>
<v6LangP>1</v6LangP>
<vShortEn>1</vShortEn>
<vShortWch>1</vShortWch>
<v6Lto>0</v6Lto>
<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<uClangAs>0</uClangAs>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>0</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>1</RepFail>
<useFile>0</useFile>
<TextAddressRange>0x10000000</TextAddressRange>
<DataAddressRange>0x08000000</DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile>.\board\linker_scripts\link.sct</ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>Source Group 1</GroupName>
</Group>
</Groups>
</Target>
</Targets>
<RTE>
<apis/>
<components/>
<files/>
</RTE>
</Project>