mirror of https://github.com/RT-Thread/rt-thread
bsp/stm32：Separate STM32H7RS HAL drivers (#10217)
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@ -77,6 +77,12 @@ config SOC_SERIES_STM32H7
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select SOC_FAMILY_STM32
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select PKG_USING_STM32H7_HAL_DRIVER
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config SOC_SERIES_STM32H7RS
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bool
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select ARCH_ARM_CORTEX_M7
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select SOC_FAMILY_STM32
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select PKG_USING_STM32H7RS_HAL_DRIVER
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config SOC_SERIES_STM32U5
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bool
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select ARCH_ARM_CORTEX_M33
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@ -1,234 +0,0 @@
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/**
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******************************************************************************
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* @file stm32h7rsxx.h
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* @author MCD Application Team
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* @brief CMSIS STM32H7RSxx Device Peripheral Access Layer Header File.
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*
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* The file is the unique include file that the application programmer
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* is using in the C source code, usually in main.c. This file contains:
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* - Configuration section that allows to select:
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* - The STM32H7RSxx device used in the target application
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* - To use or not the peripherals drivers in application code(i.e.
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* code will be based on direct access to peripherals registers
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* rather than drivers API), this option is controlled by
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* "#define USE_HAL_DRIVER"
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*
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2022 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup stm32h7rsxx
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* @{
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*/
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#ifndef STM32H7RSxx_H
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#define STM32H7RSxx_H
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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/** @addtogroup Library_configuration_section
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* @{
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*/
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/**
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* @brief STM32 Family
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*/
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#if !defined (STM32H7RS)
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#define STM32H7RS
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#endif /* STM32H7RS */
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/* Uncomment the line below according to the target STM32H7RS device used in your
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application
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*/
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#if !defined (STM32H7R7xx) && !defined (STM32H7R3xx) && !defined (STM32H7S3xx) && !defined (STM32H7S7xx)
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/* #define STM32H7R3xx */ /*!< STM32H7R3xx Devices */
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/* #define STM32H7R7xx */ /*!< STM32H7R7xx Devices */
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/* #define STM32H7S3xx */ /*!< STM32H7S3xx Devices */
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/* #define STM32H7S7xx */ /*!< STM32H7S7xx Devices */
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#endif
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/* Tip: To avoid modifying this file each time you need to switch between these
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devices, you can define the device in your toolchain compiler preprocessor.
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*/
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#if !defined (USE_HAL_DRIVER)
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/**
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* @brief Comment the line below if you will not use the peripherals drivers.
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In this case, these drivers will not be included and the application code will
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be based on direct access to peripherals registers
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*/
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/*#define USE_HAL_DRIVER */
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#endif /* USE_HAL_DRIVER */
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/**
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* @brief CMSIS Device version number
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*/
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#define __STM32H7RS_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */
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#define __STM32H7RS_CMSIS_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */
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#define __STM32H7RS_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
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#define __STM32H7RS_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
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#define __STM32H7RS_CMSIS_VERSION ((__STM32H7RS_CMSIS_VERSION_MAIN << 24U)\
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|(__STM32H7RS_CMSIS_VERSION_SUB1 << 16U)\
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|(__STM32H7RS_CMSIS_VERSION_SUB2 << 8U )\
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|(__STM32H7RS_CMSIS_VERSION_RC))
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/**
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* @}
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*/
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/** @addtogroup Device_Included
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* @{
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*/
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#if defined(STM32H7R3xx)
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#include "stm32h7r3xx.h"
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#elif defined(STM32H7R7xx)
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#include "stm32h7r7xx.h"
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#elif defined(STM32H7S3xx)
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#include "stm32h7s3xx.h"
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#elif defined(STM32H7S7xx)
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#include "stm32h7s7xx.h"
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#else
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#error "Please select first the target STM32H7RSxx device used in your application (in stm32h7rsxx.h file)"
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#endif
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/**
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* @}
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*/
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/** @addtogroup Exported_types
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* @{
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*/
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typedef enum
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{
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RESET = 0,
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SET = !RESET
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} FlagStatus, ITStatus;
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typedef enum
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{
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DISABLE = 0,
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ENABLE = !DISABLE
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} FunctionalState;
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#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
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typedef enum
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{
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SUCCESS = 0,
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ERROR = !SUCCESS
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} ErrorStatus;
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/**
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* @}
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*/
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/** @addtogroup Exported_macros
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* @{
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*/
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#define SET_BIT(REG, BIT) ((REG) |= (BIT))
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#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
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#define READ_BIT(REG, BIT) ((REG) & (BIT))
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#define CLEAR_REG(REG) ((REG) = (0x0))
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#define WRITE_REG(REG, VAL) ((REG) = (VAL))
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#define READ_REG(REG) ((REG))
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#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
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#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
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/* Use of CMSIS compiler intrinsics for register exclusive access */
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/* Atomic 32-bit register access macro to set one or several bits */
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#define ATOMIC_SET_BIT(REG, BIT) \
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do { \
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uint32_t val; \
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do { \
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val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \
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} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
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} while(0)
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/* Atomic 32-bit register access macro to clear one or several bits */
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#define ATOMIC_CLEAR_BIT(REG, BIT) \
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do { \
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uint32_t val; \
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do { \
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val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \
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} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
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} while(0)
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/* Atomic 32-bit register access macro to clear and set one or several bits */
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#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
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do { \
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uint32_t val; \
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do { \
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val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
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} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
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} while(0)
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/* Atomic 16-bit register access macro to set one or several bits */
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#define ATOMIC_SETH_BIT(REG, BIT) \
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do { \
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uint16_t val; \
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do { \
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val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \
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} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
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} while(0)
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/* Atomic 16-bit register access macro to clear one or several bits */
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#define ATOMIC_CLEARH_BIT(REG, BIT) \
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do { \
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uint16_t val; \
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do { \
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val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \
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} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
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} while(0)
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/* Atomic 16-bit register access macro to clear and set one or several bits */
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#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \
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do { \
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uint16_t val; \
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do { \
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val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
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} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
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} while(0)
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/**
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* @}
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*/
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#if defined (USE_HAL_DRIVER)
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#include "stm32h7rsxx_hal.h"
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#endif /* USE_HAL_DRIVER */
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* STM32H7RSxx_H */
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/**
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* @}
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*/
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/**
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* @}
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*/
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
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@ -1,95 +0,0 @@
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/**
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******************************************************************************
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* @file system_stm32h7rsxx.h
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* @author MCD Application Team
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* @brief CMSIS Cortex-M7 Device System Source File for STM32H7RSxx devices.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2022 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup STM32H7RSxx_system
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* @{
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*/
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#ifndef SYSTEM_STM32H7RSXX_H
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#define SYSTEM_STM32H7RSXX_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @addtogroup STM32H7RSxx_System_Includes
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* @{
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*/
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#include <stdint.h>
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/**
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* @}
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*/
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/** @addtogroup STM32H7RSxx_System_Exported_Variables
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* @{
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*/
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/* The SystemCoreClock variable is updated in three ways:
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1) by calling CMSIS function SystemCoreClockUpdate()
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2) by calling HAL API function HAL_RCC_GetSysClockFreq()
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3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
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Note: If you use this function to configure the system clock; then there
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is no need to call the 2 first functions listed above, since SystemCoreClock
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variable is updated automatically.
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*/
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extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
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/**
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* @}
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*/
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/** @addtogroup STM32H7RSxx_System_Exported_Functions
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* @{
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*/
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/**
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\brief Setup the microcontroller system.
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Initialize the System and update the SystemCoreClock variable.
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*/
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extern void SystemInit (void);
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/**
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\brief Update SystemCoreClock variable.
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Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
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*/
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extern void SystemCoreClockUpdate (void);
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* SYSTEM_STM32H7RSXX_H */
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/**
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* @}
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*/
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/**
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* @}
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*/
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@ -1,126 +0,0 @@
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<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" lang="en" xml:lang="en">
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<head>
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<meta charset="utf-8" />
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<meta name="generator" content="pandoc" />
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<meta name="viewport" content="width=device-width, initial-scale=1.0, user-scalable=yes" />
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<title>Release Notes for STM32H7RSxx CMSIS</title>
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<style type="text/css">
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code{white-space: pre-wrap;}
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span.smallcaps{font-variant: small-caps;}
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span.underline{text-decoration: underline;}
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div.column{display: inline-block; vertical-align: top; width: 50%;}
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</style>
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<link rel="stylesheet" href="_htmresc/mini-st_2020.css" />
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<!--[if lt IE 9]>
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<script src="//cdnjs.cloudflare.com/ajax/libs/html5shiv/3.7.3/html5shiv-printshiv.min.js"></script>
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<![endif]-->
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<link rel="icon" type="image/x-icon" href="_htmresc/favicon.png" />
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</head>
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<body>
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<div class="row">
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<div class="col-sm-12 col-lg-4">
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<center>
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<h1 id="release-notes-for">Release Notes for</h1>
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<h1 id="stm32h7rsxx-cmsis"><mark>STM32H7RSxx CMSIS</mark></h1>
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<p>Copyright © 2024 STMicroelectronics<br />
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</p>
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<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo_2020.png" alt="ST logo" /></a>
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</center>
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<h1 id="purpose">Purpose</h1>
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<p>This driver provides the CMSIS device for the stm32H7RSxx products. This covers</p>
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<ul>
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<li>STM32H7S7xx devices</li>
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<li>STM32H7S3xx devices</li>
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<li>STM32H7R7xx devices</li>
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<li>STM32H7R3xx devices</li>
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</ul>
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<p>This driver is composed of the description of the registers under “Include” directory.</p>
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<p>Various template files are provided to easily build an application. They can be adapted to fit applications requirements.</p>
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<ul>
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<li>Templates/system_stm32h7rsxx.c contains the initialization code referred as SystemInit.</li>
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<li>Startup files are provided as example for EWARM©, MDK-ARM©, STM32CubeIDE©.</li>
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<li>Linker files are provided as example for EWARM©, MDK-ARM©, STM32CubeIDE©.</li>
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</ul>
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</div>
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<div class="col-sm-12 col-lg-8">
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<h1 id="update-history">Update History</h1>
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<div class="collapse">
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<input type="checkbox" id="collapse-section1" checked aria-hidden="true"> <label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 / 28-February-2024</strong></label>
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<div>
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<h2 id="first-release">First release</h2>
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<h3 id="first-official-release-of-stm32h7rsxx-firmware-package-supporting-stm32h7rsxx-devices">First official Release of <strong>STM32H7RSxx</strong> Firmware package supporting <strong>STM32H7RSxx</strong> devices</h3>
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<h2 id="contents">Contents</h2>
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<ul>
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<li>Support of STM32H7Rx/Sx devices</li>
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</ul>
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<p><br />
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</p>
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<p>Notes: linker file mapping vs HW boards</p>
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<table>
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<thead>
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<tr class="header">
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<th style="text-align: left;">Board</th>
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<th>Internal Flash (boot)</th>
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<th style="text-align: left;">External memories (Appli)</th>
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</tr>
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</thead>
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<tbody>
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<tr class="odd">
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||||
<td style="text-align: left;">STM32H7S78-DK</td>
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<td>stm32h7s7xx_flash.*</td>
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<td style="text-align: left;">stm32h7rsxx_RAMxspi1_ROMxspi2.*</td>
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</tr>
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<tr class="even">
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<td style="text-align: left;">NUCLEO-H7S3L8</td>
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<td>stm32h7s3xx_flash.*</td>
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<td style="text-align: left;">stm32h7rsxx_ROMxspi2.*</td>
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||||
</tr>
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||||
</tbody>
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||||
</table>
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<p><br />
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</p>
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<h2 id="development-toolchains-and-compilers">Development Toolchains and Compilers</h2>
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<ul>
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<li>IAR Embedded Workbench for ARM (EWARM) toolchain V9.20.1</li>
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<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.38a</li>
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<li>STM32CubeIDE V1.15.0 (GCC12)</li>
|
||||
</ul>
|
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<p><br />
|
||||
</p>
|
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<h2 id="supported-devices-and-boards">Supported Devices and boards</h2>
|
||||
<ul>
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<li>STM32H7R3xx/STM32H7R7xx/STM32H7S3xx/STM32H7S7xx devices</li>
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</ul>
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<p><br />
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</p>
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<h2 id="known-limitations">Known Limitations</h2>
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||||
<ul>
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<li>None</li>
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</ul>
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<h2 id="dependencies">Dependencies</h2>
|
||||
<ul>
|
||||
<li>None</li>
|
||||
</ul>
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<h2 id="notes">Notes</h2>
|
||||
<ul>
|
||||
<li>None</li>
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||||
</ul>
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||||
</div>
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||||
</div>
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||||
</div>
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||||
</div>
|
||||
<footer class="sticky">
|
||||
<div class="columns">
|
||||
<div class="column" style="width:95%;">
|
||||
<p>For complete documentation on STM32H7Rx/Sx,</p>
|
||||
<p>visit: <span style="font-color: blue;"><a href="https://www.st.com/content/st_com/en/products/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32h7-series/stm32h7r3-7s3.html">stm32h7-series/stm32h7r3-7s3</a></span></p>
|
||||
<p>visit: <span style="font-color: blue;"><a href="https://www.st.com/content/st_com/en/products/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32h7-series/stm32h7r7-7s7.html">stm32h7-series/stm32h7r7-7s7</a></span></p>
|
||||
<p><em>This release note uses up to date web standards and, for this reason, should not be opened with Internet Explorer but preferably with popular browsers such as Google Chrome, Mozilla Firefox, Opera or Microsoft Edge.</em></p>
|
||||
</div><div class="column" style="width:5%;">
|
||||
<p><abbr title="Based on template cx566953 version 2.0">Info</abbr></p>
|
||||
</div>
|
||||
</div>
|
||||
</footer>
|
||||
</body>
|
||||
</html>
|
||||
|
|
@ -1,34 +0,0 @@
|
|||
; *************************************************************
|
||||
; *** Scatter-Loading Description File generated by uVision ***
|
||||
; *************************************************************
|
||||
|
||||
LOAD_FLASH 0x08000000 0x08010000 { ; load region size_region
|
||||
ER_ROM 0x08000000 0x08010000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
.ANY (+XO)
|
||||
}
|
||||
|
||||
ER_ITCM 0x00000000 0x00010000 { ;
|
||||
}
|
||||
|
||||
RW_DTCM 0x20000000 0x00010000 { ; RW data
|
||||
*(STACK)
|
||||
*(HEAP)
|
||||
}
|
||||
|
||||
RW_SRAMAHB 0x30000000 0x8000 {
|
||||
}
|
||||
|
||||
RW_BKPSRAM 0x38800000 0x1000 {
|
||||
}
|
||||
|
||||
RW_RAM 0x24000000 0x00072000-0x400 {
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
|
||||
RW_NONCACHEABLEBUFFER 0x24072000-0x400 0x400 {
|
||||
*(noncacheable_buffer)
|
||||
}
|
||||
}
|
||||
|
|
@ -1,34 +0,0 @@
|
|||
; *************************************************************
|
||||
; *** Scatter-Loading Description File generated by uVision ***
|
||||
; *************************************************************
|
||||
|
||||
LOAD_FLASH 0x24050000 0x00022000 { ; load region size_region
|
||||
ER_ROM 0x24050000 0x00022000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
.ANY (+XO)
|
||||
}
|
||||
|
||||
ER_ITCM 0x00000000 0x00010000 { ;
|
||||
}
|
||||
|
||||
RW_DTCM 0x20000000 0x00010000 { ; RW data
|
||||
*(STACK)
|
||||
*(HEAP)
|
||||
}
|
||||
|
||||
RW_SRAMAHB 0x30000000 0x8000 {
|
||||
}
|
||||
|
||||
RW_BKPSRAM 0x38800000 0x1000 {
|
||||
}
|
||||
|
||||
RW_RAM 0x24000000 0x00050000-0x400 {
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
|
||||
RW_NONCACHEABLEBUFFER 0x24050000-0x400 0x400 {
|
||||
*(noncacheable_buffer)
|
||||
}
|
||||
}
|
||||
|
|
@ -1,34 +0,0 @@
|
|||
; *************************************************************
|
||||
; *** Scatter-Loading Description File generated by uVision ***
|
||||
; *************************************************************
|
||||
|
||||
LOAD_FLASH 0x08000000 0x08010000 { ; load region size_region
|
||||
ER_ROM 0x08000000 0x08010000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
.ANY (+XO)
|
||||
}
|
||||
|
||||
ER_ITCM 0x00000000 0x00010000 { ;
|
||||
}
|
||||
|
||||
RW_DTCM 0x20000000 0x00010000 { ; RW data
|
||||
*(STACK)
|
||||
*(HEAP)
|
||||
}
|
||||
|
||||
RW_SRAMAHB 0x30000000 0x8000 {
|
||||
}
|
||||
|
||||
RW_BKPSRAM 0x38800000 0x1000 {
|
||||
}
|
||||
|
||||
RW_RAM 0x24000000 0x00072000-0x400 {
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
|
||||
RW_NONCACHEABLEBUFFER 0x24072000-0x400 0x400 {
|
||||
*(noncacheable_buffer)
|
||||
}
|
||||
}
|
||||
|
|
@ -1,34 +0,0 @@
|
|||
; *************************************************************
|
||||
; *** Scatter-Loading Description File generated by uVision ***
|
||||
; *************************************************************
|
||||
|
||||
LOAD_FLASH 0x24050000 0x00022000 { ; load region size_region
|
||||
ER_ROM 0x24050000 0x00022000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
.ANY (+XO)
|
||||
}
|
||||
|
||||
ER_ITCM 0x00000000 0x00010000 { ;
|
||||
}
|
||||
|
||||
RW_DTCM 0x20000000 0x00010000 { ; RW data
|
||||
*(STACK)
|
||||
*(HEAP)
|
||||
}
|
||||
|
||||
RW_SRAMAHB 0x30000000 0x8000 {
|
||||
}
|
||||
|
||||
RW_BKPSRAM 0x38800000 0x1000 {
|
||||
}
|
||||
|
||||
RW_RAM 0x24000000 0x00050000-0x400 {
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
|
||||
RW_NONCACHEABLEBUFFER 0x24050000-0x400 0x400 {
|
||||
*(noncacheable_buffer)
|
||||
}
|
||||
}
|
||||
|
|
@ -1,37 +0,0 @@
|
|||
; *************************************************************
|
||||
; *** Scatter-Loading Description File generated by uVision ***
|
||||
; *************************************************************
|
||||
|
||||
LOAD_FLASH 0x70000000 0x08000000 { ; load region size_region
|
||||
ER_ROM 0x70000000 0x08000000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
.ANY (+XO)
|
||||
}
|
||||
|
||||
ER_ITCM 0x00000000 0x00010000 { ;
|
||||
}
|
||||
|
||||
RW_DTCM 0x20000000 0x00010000 { ; RW data
|
||||
*(STACK)
|
||||
*(HEAP)
|
||||
}
|
||||
|
||||
RW_SRAMAHB 0x30000000 0x8000 {
|
||||
}
|
||||
|
||||
RW_BKPSRAM 0x38800000 0x1000 {
|
||||
}
|
||||
|
||||
RW_EXTRAM 0x90000000 0x2000000 {
|
||||
}
|
||||
|
||||
RW_RAM 0x24000000 0x00072000-0x400 {
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
|
||||
RW_NONCACHEABLEBUFFER 0x24072000-0x400 0x400 {
|
||||
*(noncacheable_buffer)
|
||||
}
|
||||
}
|
||||
|
|
@ -1,34 +0,0 @@
|
|||
; *************************************************************
|
||||
; *** Scatter-Loading Description File generated by uVision ***
|
||||
; *************************************************************
|
||||
|
||||
LOAD_FLASH 0x90000000 0x08000000 { ; load region size_region
|
||||
ER_ROM 0x90000000 0x08000000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
.ANY (+XO)
|
||||
}
|
||||
|
||||
ER_ITCM 0x00000000 0x00010000 { ;
|
||||
}
|
||||
|
||||
RW_DTCM 0x20000000 0x00010000 { ; RW data
|
||||
*(STACK)
|
||||
*(HEAP)
|
||||
}
|
||||
|
||||
RW_SRAMAHB 0x30000000 0x8000 {
|
||||
}
|
||||
|
||||
RW_BKPSRAM 0x38800000 0x1000 {
|
||||
}
|
||||
|
||||
RW_RAM 0x24000000 0x00072000-0x400 {
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
|
||||
RW_NONCACHEABLEBUFFER 0x24072000-0x400 0x400 {
|
||||
*(noncacheable_buffer)
|
||||
}
|
||||
}
|
||||
|
|
@ -1,37 +0,0 @@
|
|||
; *************************************************************
|
||||
; *** Scatter-Loading Description File generated by uVision ***
|
||||
; *************************************************************
|
||||
|
||||
LOAD_FLASH 0x90000000 0x08000000 { ; load region size_region
|
||||
ER_ROM 0x90000000 0x08000000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
.ANY (+XO)
|
||||
}
|
||||
|
||||
ER_ITCM 0x00000000 0x00010000 { ;
|
||||
}
|
||||
|
||||
RW_DTCM 0x20000000 0x00010000 { ; RW data
|
||||
*(STACK)
|
||||
*(HEAP)
|
||||
}
|
||||
|
||||
RW_SRAMAHB 0x30000000 0x8000 {
|
||||
}
|
||||
|
||||
RW_BKPSRAM 0x38800000 0x1000 {
|
||||
}
|
||||
|
||||
RW_EXTRAM 0x70000000 0x2000000 {
|
||||
}
|
||||
|
||||
RW_RAM 0x24000000 0x00072000-0x400 {
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
|
||||
RW_NONCACHEABLEBUFFER 0x24072000-0x400 0x400 {
|
||||
*(noncacheable_buffer)
|
||||
}
|
||||
}
|
||||
|
|
@ -1,34 +0,0 @@
|
|||
; *************************************************************
|
||||
; *** Scatter-Loading Description File generated by uVision ***
|
||||
; *************************************************************
|
||||
|
||||
LOAD_FLASH 0x70000000 0x08000000 { ; load region size_region
|
||||
ER_ROM 0x70000000 0x08000000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
.ANY (+XO)
|
||||
}
|
||||
|
||||
ER_ITCM 0x00000000 0x00010000 { ;
|
||||
}
|
||||
|
||||
RW_DTCM 0x20000000 0x00010000 { ; RW data
|
||||
*(STACK)
|
||||
*(HEAP)
|
||||
}
|
||||
|
||||
RW_SRAMAHB 0x30000000 0x8000 {
|
||||
}
|
||||
|
||||
RW_BKPSRAM 0x38800000 0x1000 {
|
||||
}
|
||||
|
||||
RW_RAM 0x24000000 0x00072000-0x400 {
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
|
||||
RW_NONCACHEABLEBUFFER 0x24072000-0x400 0x400 {
|
||||
*(noncacheable_buffer)
|
||||
}
|
||||
}
|
||||
|
|
@ -1,23 +0,0 @@
|
|||
; *************************************************************
|
||||
; MDK-ARM ExtFlashLoader Linker Control File (scatter-loading)
|
||||
; *************************************************************
|
||||
PRG 0 PI ; Programming Functions
|
||||
{
|
||||
PrgCode +0 ; Code
|
||||
{
|
||||
* (+RO)
|
||||
}
|
||||
PrgData +0 ; Data
|
||||
{
|
||||
* (+ZI,+RW)
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
DSCR +0x1000
|
||||
{
|
||||
DevDscr +0
|
||||
{
|
||||
FlashDev.o
|
||||
}
|
||||
}
|
||||
|
|
@ -1,26 +0,0 @@
|
|||
; *************************************************************
|
||||
; STM32CubeProgrammer ExtFlashLoader Linker Control File (scatter-loading)
|
||||
; *************************************************************
|
||||
|
||||
;0x20000004 is the address where the flashloader is loaded
|
||||
FLASH_LOADER 0x20000004 PI ; FlashLoader Functions
|
||||
{
|
||||
PrgCode +0 ; Code
|
||||
{
|
||||
* (+RO)
|
||||
}
|
||||
; 0x0401FFFC+0x20000004=0x24020000 where data and bss is loaded
|
||||
PrgData +0x0401FFFC ; Data
|
||||
{
|
||||
* (+RW,+ZI)
|
||||
}
|
||||
}
|
||||
|
||||
;reserved for device information
|
||||
DEVICE_INFO 0 ; Device Info
|
||||
{
|
||||
DevInfo 0 ; Info structure
|
||||
{
|
||||
stm32_device_info.o
|
||||
}
|
||||
}
|
||||
|
|
@ -1,34 +0,0 @@
|
|||
; *************************************************************
|
||||
; *** Scatter-Loading Description File generated by uVision ***
|
||||
; *************************************************************
|
||||
|
||||
LOAD_FLASH 0x08000000 0x08010000 { ; load region size_region
|
||||
ER_ROM 0x08000000 0x08010000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
.ANY (+XO)
|
||||
}
|
||||
|
||||
ER_ITCM 0x00000000 0x00010000 { ;
|
||||
}
|
||||
|
||||
RW_DTCM 0x20000000 0x00010000 { ; RW data
|
||||
*(STACK)
|
||||
*(HEAP)
|
||||
}
|
||||
|
||||
RW_SRAMAHB 0x30000000 0x8000 {
|
||||
}
|
||||
|
||||
RW_BKPSRAM 0x38800000 0x1000 {
|
||||
}
|
||||
|
||||
RW_RAM 0x24000000 0x00072000-0x400 {
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
|
||||
RW_NONCACHEABLEBUFFER 0x24072000-0x400 0x400 {
|
||||
*(noncacheable_buffer)
|
||||
}
|
||||
}
|
||||
|
|
@ -1,34 +0,0 @@
|
|||
; *************************************************************
|
||||
; *** Scatter-Loading Description File generated by uVision ***
|
||||
; *************************************************************
|
||||
|
||||
LOAD_FLASH 0x24050000 0x00022000 { ; load region size_region
|
||||
ER_ROM 0x24050000 0x00022000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
.ANY (+XO)
|
||||
}
|
||||
|
||||
ER_ITCM 0x00000000 0x00010000 { ;
|
||||
}
|
||||
|
||||
RW_DTCM 0x20000000 0x00010000 { ; RW data
|
||||
*(STACK)
|
||||
*(HEAP)
|
||||
}
|
||||
|
||||
RW_SRAMAHB 0x30000000 0x8000 {
|
||||
}
|
||||
|
||||
RW_BKPSRAM 0x38800000 0x1000 {
|
||||
}
|
||||
|
||||
RW_RAM 0x24000000 0x00050000-0x400 {
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
|
||||
RW_NONCACHEABLEBUFFER 0x24050000-0x400 0x400 {
|
||||
*(noncacheable_buffer)
|
||||
}
|
||||
}
|
||||
|
|
@ -1,34 +0,0 @@
|
|||
; *************************************************************
|
||||
; *** Scatter-Loading Description File generated by uVision ***
|
||||
; *************************************************************
|
||||
|
||||
LOAD_FLASH 0x08000000 0x08010000 { ; load region size_region
|
||||
ER_ROM 0x08000000 0x08010000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
.ANY (+XO)
|
||||
}
|
||||
|
||||
ER_ITCM 0x00000000 0x00010000 { ;
|
||||
}
|
||||
|
||||
RW_DTCM 0x20000000 0x00010000 { ; RW data
|
||||
*(STACK)
|
||||
*(HEAP)
|
||||
}
|
||||
|
||||
RW_SRAMAHB 0x30000000 0x8000 {
|
||||
}
|
||||
|
||||
RW_BKPSRAM 0x38800000 0x1000 {
|
||||
}
|
||||
|
||||
RW_RAM 0x24000000 0x00072000-0x400 {
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
|
||||
RW_NONCACHEABLEBUFFER 0x24072000-0x400 0x400 {
|
||||
*(noncacheable_buffer)
|
||||
}
|
||||
}
|
||||
|
|
@ -1,34 +0,0 @@
|
|||
; *************************************************************
|
||||
; *** Scatter-Loading Description File generated by uVision ***
|
||||
; *************************************************************
|
||||
|
||||
LOAD_FLASH 0x24050000 0x00022000 { ; load region size_region
|
||||
ER_ROM 0x24050000 0x00022000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
.ANY (+XO)
|
||||
}
|
||||
|
||||
ER_ITCM 0x00000000 0x00010000 { ;
|
||||
}
|
||||
|
||||
RW_DTCM 0x20000000 0x00010000 { ; RW data
|
||||
*(STACK)
|
||||
*(HEAP)
|
||||
}
|
||||
|
||||
RW_SRAMAHB 0x30000000 0x8000 {
|
||||
}
|
||||
|
||||
RW_BKPSRAM 0x38800000 0x1000 {
|
||||
}
|
||||
|
||||
RW_RAM 0x24000000 0x00050000-0x400 {
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
|
||||
RW_NONCACHEABLEBUFFER 0x24050000-0x400 0x400 {
|
||||
*(noncacheable_buffer)
|
||||
}
|
||||
}
|
||||
|
|
@ -1,613 +0,0 @@
|
|||
;*******************************************************************************
|
||||
;* File Name : startup_stm32h7r3xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : STM32H7R3xx devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M7 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;*******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* Copyright (c) 2023 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;*******************************************************************************
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
; External Interrupts
|
||||
DCD PVD_PVM_IRQHandler ; PVD/PVM through EXTI Line detection
|
||||
DCD 0 ; Reserved
|
||||
DCD DTS_IRQHandler ; Digital Temperature Sensor
|
||||
DCD IWDG_IRQHandler ; Internal Watchdog
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD RCC_IRQHandler ; RCC global interrupts through EXTI Line detection
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD FLASH_IRQHandler ; FLASH interrupts
|
||||
DCD RAMECC_IRQHandler ; RAMECC interrupts
|
||||
DCD FPU_IRQHandler ; FPU
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD TAMP_IRQHandler ; Tamper and TimeStamp interrupts through EXTI Line detection
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD EXTI0_IRQHandler ; EXTI Line0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line4
|
||||
DCD EXTI5_IRQHandler ; EXTI Line5
|
||||
DCD EXTI6_IRQHandler ; EXTI Line6
|
||||
DCD EXTI7_IRQHandler ; EXTI Line7
|
||||
DCD EXTI8_IRQHandler ; EXTI Line8
|
||||
DCD EXTI9_IRQHandler ; EXTI Line9
|
||||
DCD EXTI10_IRQHandler ; EXTI Line10
|
||||
DCD EXTI11_IRQHandler ; EXTI Line11
|
||||
DCD EXTI12_IRQHandler ; EXTI Line12
|
||||
DCD EXTI13_IRQHandler ; EXTI Line13
|
||||
DCD EXTI14_IRQHandler ; EXTI Line14
|
||||
DCD EXTI15_IRQHandler ; EXTI Line15
|
||||
DCD RTC_IRQHandler ; RTC wakeup and alarm interrupts through EXTI Line detection
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PKA_IRQHandler ; PKA
|
||||
DCD HASH_IRQHandler ; HASH
|
||||
DCD RNG_IRQHandler ; RNG
|
||||
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
|
||||
DCD GPDMA1_Channel0_IRQHandler ; GPDMA1 Channel 0
|
||||
DCD GPDMA1_Channel1_IRQHandler ; GPDMA1 Channel 1
|
||||
DCD GPDMA1_Channel2_IRQHandler ; GPDMA1 Channel 2
|
||||
DCD GPDMA1_Channel3_IRQHandler ; GPDMA1 Channel 3
|
||||
DCD GPDMA1_Channel4_IRQHandler ; GPDMA1 Channel 4
|
||||
DCD GPDMA1_Channel5_IRQHandler ; GPDMA1 Channel 5
|
||||
DCD GPDMA1_Channel6_IRQHandler ; GPDMA1 Channel 6
|
||||
DCD GPDMA1_Channel7_IRQHandler ; GPDMA1 Channel 7
|
||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break
|
||||
DCD TIM1_UP_IRQHandler ; TIM1 Update
|
||||
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD TIM5_IRQHandler ; TIM5
|
||||
DCD TIM6_IRQHandler ; TIM6
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD TIM9_IRQHandler ; TIM9
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD SPI4_IRQHandler ; SPI4
|
||||
DCD SPI5_IRQHandler ; SPI5
|
||||
DCD SPI6_IRQHandler ; SPI6
|
||||
DCD HPDMA1_Channel0_IRQHandler ; HPDMA1 Channel 0
|
||||
DCD HPDMA1_Channel1_IRQHandler ; HPDMA1 Channel 1
|
||||
DCD HPDMA1_Channel2_IRQHandler ; HPDMA1 Channel 2
|
||||
DCD HPDMA1_Channel3_IRQHandler ; HPDMA1 Channel 3
|
||||
DCD HPDMA1_Channel4_IRQHandler ; HPDMA1 Channel 4
|
||||
DCD HPDMA1_Channel5_IRQHandler ; HPDMA1 Channel 5
|
||||
DCD HPDMA1_Channel6_IRQHandler ; HPDMA1 Channel 6
|
||||
DCD HPDMA1_Channel7_IRQHandler ; HPDMA1 Channel 7
|
||||
DCD SAI1_A_IRQHandler ; Serial Audio Interface 1 block A
|
||||
DCD SAI1_B_IRQHandler ; Serial Audio Interface 1 block B
|
||||
DCD SAI2_A_IRQHandler ; Serial Audio Interface 2 block A
|
||||
DCD SAI2_B_IRQHandler ; Serial Audio Interface 2 block B
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD I2C3_EV_IRQHandler ; I2C3 Event
|
||||
DCD I2C3_ER_IRQHandler ; I2C3 Error
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD UART4_IRQHandler ; UART4
|
||||
DCD UART5_IRQHandler ; UART5
|
||||
DCD UART7_IRQHandler ; UART7
|
||||
DCD UART8_IRQHandler ; UART8
|
||||
DCD I3C1_EV_IRQHandler ; I3C1 Event
|
||||
DCD I3C1_ER_IRQHandler ; I3C1 Error
|
||||
DCD OTG_HS_IRQHandler ; USB OTG HS
|
||||
DCD ETH_IRQHandler ; Ethernet
|
||||
DCD CORDIC_IRQHandler ; CORDIC
|
||||
DCD GFXTIM_IRQHandler ; GFXTIM
|
||||
DCD DCMIPP_IRQHandler ; DCMIPP
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD DMA2D_IRQHandler ; DMA2D
|
||||
DCD JPEG_IRQHandler ; JPEG
|
||||
DCD GFXMMU_IRQHandler ; GFXMMU
|
||||
DCD I3C1_WKUP_IRQHandler ; I3C1 wakeup
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD XSPI1_IRQHandler ; XSPI1
|
||||
DCD XSPI2_IRQHandler ; XSPI2
|
||||
DCD FMC_IRQHandler ; FMC
|
||||
DCD SDMMC1_IRQHandler ; SDMMC1
|
||||
DCD SDMMC2_IRQHandler ; SDMMC2
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD OTG_FS_IRQHandler ; USB OTG FS
|
||||
DCD TIM12_IRQHandler ; TIM12
|
||||
DCD TIM13_IRQHandler ; TIM13
|
||||
DCD TIM14_IRQHandler ; TIM14
|
||||
DCD TIM15_IRQHandler ; TIM15
|
||||
DCD TIM16_IRQHandler ; TIM16
|
||||
DCD TIM17_IRQHandler ; TIM17
|
||||
DCD LPTIM1_IRQHandler ; LP TIM1
|
||||
DCD LPTIM2_IRQHandler ; LP TIM2
|
||||
DCD LPTIM3_IRQHandler ; LP TIM3
|
||||
DCD LPTIM4_IRQHandler ; LP TIM4
|
||||
DCD LPTIM5_IRQHandler ; LP TIM5
|
||||
DCD SPDIF_RX_IRQHandler ; SPDIF_RX
|
||||
DCD MDIOS_IRQHandler ; MDIOS
|
||||
DCD ADF1_FLT0_IRQHandler ; ADF1 Filter 0
|
||||
DCD CRS_IRQHandler ; CRS
|
||||
DCD UCPD1_IRQHandler ; UCPD1
|
||||
DCD CEC_IRQHandler ; HDMI_CEC
|
||||
DCD PSSI_IRQHandler ; PSSI
|
||||
DCD LPUART1_IRQHandler ; LP UART1
|
||||
DCD WAKEUP_PIN_IRQHandler ; Wake-up pins interrupt
|
||||
DCD GPDMA1_Channel8_IRQHandler ; GPDMA1 Channel 8
|
||||
DCD GPDMA1_Channel9_IRQHandler ; GPDMA1 Channel 9
|
||||
DCD GPDMA1_Channel10_IRQHandler ; GPDMA1 Channel 10
|
||||
DCD GPDMA1_Channel11_IRQHandler ; GPDMA1 Channel 11
|
||||
DCD GPDMA1_Channel12_IRQHandler ; GPDMA1 Channel 12
|
||||
DCD GPDMA1_Channel13_IRQHandler ; GPDMA1 Channel 13
|
||||
DCD GPDMA1_Channel14_IRQHandler ; GPDMA1 Channel 14
|
||||
DCD GPDMA1_Channel15_IRQHandler ; GPDMA1 Channel 15
|
||||
DCD HPDMA1_Channel8_IRQHandler ; HPDMA1 Channel 8
|
||||
DCD HPDMA1_Channel9_IRQHandler ; HPDMA1 Channel 9
|
||||
DCD HPDMA1_Channel10_IRQHandler ; HPDMA1 Channel 10
|
||||
DCD HPDMA1_Channel11_IRQHandler ; HPDMA1 Channel 11
|
||||
DCD HPDMA1_Channel12_IRQHandler ; HPDMA1 Channel 12
|
||||
DCD HPDMA1_Channel13_IRQHandler ; HPDMA1 Channel 13
|
||||
DCD HPDMA1_Channel14_IRQHandler ; HPDMA1 Channel 14
|
||||
DCD HPDMA1_Channel15_IRQHandler ; HPDMA1 Channel 15
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 Interrupt 0
|
||||
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 Interrupt 1
|
||||
DCD FDCAN2_IT0_IRQHandler ; FDCAN2 Interrupt 0
|
||||
DCD FDCAN2_IT1_IRQHandler ; FDCAN2 Interrupt 1
|
||||
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler\
|
||||
PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler\
|
||||
PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler\
|
||||
PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler\
|
||||
PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT PVD_PVM_IRQHandler [WEAK]
|
||||
EXPORT DTS_IRQHandler [WEAK]
|
||||
EXPORT IWDG_IRQHandler [WEAK]
|
||||
EXPORT WWDG_IRQHandler [WEAK]
|
||||
EXPORT RCC_IRQHandler [WEAK]
|
||||
EXPORT FLASH_IRQHandler [WEAK]
|
||||
EXPORT RAMECC_IRQHandler [WEAK]
|
||||
EXPORT FPU_IRQHandler [WEAK]
|
||||
EXPORT TAMP_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT EXTI5_IRQHandler [WEAK]
|
||||
EXPORT EXTI6_IRQHandler [WEAK]
|
||||
EXPORT EXTI7_IRQHandler [WEAK]
|
||||
EXPORT EXTI8_IRQHandler [WEAK]
|
||||
EXPORT EXTI9_IRQHandler [WEAK]
|
||||
EXPORT EXTI10_IRQHandler [WEAK]
|
||||
EXPORT EXTI11_IRQHandler [WEAK]
|
||||
EXPORT EXTI12_IRQHandler [WEAK]
|
||||
EXPORT EXTI13_IRQHandler [WEAK]
|
||||
EXPORT EXTI14_IRQHandler [WEAK]
|
||||
EXPORT EXTI15_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT PKA_IRQHandler [WEAK]
|
||||
EXPORT HASH_IRQHandler [WEAK]
|
||||
EXPORT RNG_IRQHandler [WEAK]
|
||||
EXPORT ADC1_2_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel0_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel1_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel2_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel3_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel4_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel5_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel6_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel7_IRQHandler [WEAK]
|
||||
EXPORT TIM1_BRK_IRQHandler [WEAK]
|
||||
EXPORT TIM1_UP_IRQHandler [WEAK]
|
||||
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
|
||||
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT TIM3_IRQHandler [WEAK]
|
||||
EXPORT TIM4_IRQHandler [WEAK]
|
||||
EXPORT TIM5_IRQHandler [WEAK]
|
||||
EXPORT TIM6_IRQHandler [WEAK]
|
||||
EXPORT TIM7_IRQHandler [WEAK]
|
||||
EXPORT TIM9_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT SPI3_IRQHandler [WEAK]
|
||||
EXPORT SPI4_IRQHandler [WEAK]
|
||||
EXPORT SPI5_IRQHandler [WEAK]
|
||||
EXPORT SPI6_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel0_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel1_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel2_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel3_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel4_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel5_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel6_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel7_IRQHandler [WEAK]
|
||||
EXPORT SAI1_A_IRQHandler [WEAK]
|
||||
EXPORT SAI1_B_IRQHandler [WEAK]
|
||||
EXPORT SAI2_A_IRQHandler [WEAK]
|
||||
EXPORT SAI2_B_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C3_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C3_ER_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT USART2_IRQHandler [WEAK]
|
||||
EXPORT USART3_IRQHandler [WEAK]
|
||||
EXPORT UART4_IRQHandler [WEAK]
|
||||
EXPORT UART5_IRQHandler [WEAK]
|
||||
EXPORT UART7_IRQHandler [WEAK]
|
||||
EXPORT UART8_IRQHandler [WEAK]
|
||||
EXPORT I3C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I3C1_ER_IRQHandler [WEAK]
|
||||
EXPORT OTG_HS_IRQHandler [WEAK]
|
||||
EXPORT ETH_IRQHandler [WEAK]
|
||||
EXPORT CORDIC_IRQHandler [WEAK]
|
||||
EXPORT GFXTIM_IRQHandler [WEAK]
|
||||
EXPORT DCMIPP_IRQHandler [WEAK]
|
||||
EXPORT DMA2D_IRQHandler [WEAK]
|
||||
EXPORT JPEG_IRQHandler [WEAK]
|
||||
EXPORT GFXMMU_IRQHandler [WEAK]
|
||||
EXPORT I3C1_WKUP_IRQHandler [WEAK]
|
||||
EXPORT XSPI1_IRQHandler [WEAK]
|
||||
EXPORT XSPI2_IRQHandler [WEAK]
|
||||
EXPORT FMC_IRQHandler [WEAK]
|
||||
EXPORT SDMMC1_IRQHandler [WEAK]
|
||||
EXPORT SDMMC2_IRQHandler [WEAK]
|
||||
EXPORT OTG_FS_IRQHandler [WEAK]
|
||||
EXPORT TIM12_IRQHandler [WEAK]
|
||||
EXPORT TIM13_IRQHandler [WEAK]
|
||||
EXPORT TIM14_IRQHandler [WEAK]
|
||||
EXPORT TIM15_IRQHandler [WEAK]
|
||||
EXPORT TIM16_IRQHandler [WEAK]
|
||||
EXPORT TIM17_IRQHandler [WEAK]
|
||||
EXPORT LPTIM1_IRQHandler [WEAK]
|
||||
EXPORT LPTIM2_IRQHandler [WEAK]
|
||||
EXPORT LPTIM3_IRQHandler [WEAK]
|
||||
EXPORT LPTIM4_IRQHandler [WEAK]
|
||||
EXPORT LPTIM5_IRQHandler [WEAK]
|
||||
EXPORT SPDIF_RX_IRQHandler [WEAK]
|
||||
EXPORT MDIOS_IRQHandler [WEAK]
|
||||
EXPORT ADF1_FLT0_IRQHandler [WEAK]
|
||||
EXPORT CRS_IRQHandler [WEAK]
|
||||
EXPORT UCPD1_IRQHandler [WEAK]
|
||||
EXPORT CEC_IRQHandler [WEAK]
|
||||
EXPORT PSSI_IRQHandler [WEAK]
|
||||
EXPORT LPUART1_IRQHandler [WEAK]
|
||||
EXPORT WAKEUP_PIN_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel8_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel9_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel10_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel11_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel12_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel13_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel14_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel15_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel8_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel9_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel10_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel11_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel12_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel13_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel14_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel15_IRQHandler [WEAK]
|
||||
EXPORT FDCAN1_IT0_IRQHandler [WEAK]
|
||||
EXPORT FDCAN1_IT1_IRQHandler [WEAK]
|
||||
EXPORT FDCAN2_IT0_IRQHandler [WEAK]
|
||||
EXPORT FDCAN2_IT1_IRQHandler [WEAK]
|
||||
|
||||
PVD_PVM_IRQHandler
|
||||
DTS_IRQHandler
|
||||
IWDG_IRQHandler
|
||||
WWDG_IRQHandler
|
||||
RCC_IRQHandler
|
||||
FLASH_IRQHandler
|
||||
RAMECC_IRQHandler
|
||||
FPU_IRQHandler
|
||||
TAMP_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
EXTI5_IRQHandler
|
||||
EXTI6_IRQHandler
|
||||
EXTI7_IRQHandler
|
||||
EXTI8_IRQHandler
|
||||
EXTI9_IRQHandler
|
||||
EXTI10_IRQHandler
|
||||
EXTI11_IRQHandler
|
||||
EXTI12_IRQHandler
|
||||
EXTI13_IRQHandler
|
||||
EXTI14_IRQHandler
|
||||
EXTI15_IRQHandler
|
||||
RTC_IRQHandler
|
||||
PKA_IRQHandler
|
||||
HASH_IRQHandler
|
||||
RNG_IRQHandler
|
||||
ADC1_2_IRQHandler
|
||||
GPDMA1_Channel0_IRQHandler
|
||||
GPDMA1_Channel1_IRQHandler
|
||||
GPDMA1_Channel2_IRQHandler
|
||||
GPDMA1_Channel3_IRQHandler
|
||||
GPDMA1_Channel4_IRQHandler
|
||||
GPDMA1_Channel5_IRQHandler
|
||||
GPDMA1_Channel6_IRQHandler
|
||||
GPDMA1_Channel7_IRQHandler
|
||||
TIM1_BRK_IRQHandler
|
||||
TIM1_UP_IRQHandler
|
||||
TIM1_TRG_COM_IRQHandler
|
||||
TIM1_CC_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
TIM3_IRQHandler
|
||||
TIM4_IRQHandler
|
||||
TIM5_IRQHandler
|
||||
TIM6_IRQHandler
|
||||
TIM7_IRQHandler
|
||||
TIM9_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
SPI3_IRQHandler
|
||||
SPI4_IRQHandler
|
||||
SPI5_IRQHandler
|
||||
SPI6_IRQHandler
|
||||
HPDMA1_Channel0_IRQHandler
|
||||
HPDMA1_Channel1_IRQHandler
|
||||
HPDMA1_Channel2_IRQHandler
|
||||
HPDMA1_Channel3_IRQHandler
|
||||
HPDMA1_Channel4_IRQHandler
|
||||
HPDMA1_Channel5_IRQHandler
|
||||
HPDMA1_Channel6_IRQHandler
|
||||
HPDMA1_Channel7_IRQHandler
|
||||
SAI1_A_IRQHandler
|
||||
SAI1_B_IRQHandler
|
||||
SAI2_A_IRQHandler
|
||||
SAI2_B_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
I2C2_EV_IRQHandler
|
||||
I2C2_ER_IRQHandler
|
||||
I2C3_EV_IRQHandler
|
||||
I2C3_ER_IRQHandler
|
||||
USART1_IRQHandler
|
||||
USART2_IRQHandler
|
||||
USART3_IRQHandler
|
||||
UART4_IRQHandler
|
||||
UART5_IRQHandler
|
||||
UART7_IRQHandler
|
||||
UART8_IRQHandler
|
||||
I3C1_EV_IRQHandler
|
||||
I3C1_ER_IRQHandler
|
||||
OTG_HS_IRQHandler
|
||||
ETH_IRQHandler
|
||||
CORDIC_IRQHandler
|
||||
GFXTIM_IRQHandler
|
||||
DCMIPP_IRQHandler
|
||||
DMA2D_IRQHandler
|
||||
JPEG_IRQHandler
|
||||
GFXMMU_IRQHandler
|
||||
I3C1_WKUP_IRQHandler
|
||||
XSPI1_IRQHandler
|
||||
XSPI2_IRQHandler
|
||||
FMC_IRQHandler
|
||||
SDMMC1_IRQHandler
|
||||
SDMMC2_IRQHandler
|
||||
OTG_FS_IRQHandler
|
||||
TIM12_IRQHandler
|
||||
TIM13_IRQHandler
|
||||
TIM14_IRQHandler
|
||||
TIM15_IRQHandler
|
||||
TIM16_IRQHandler
|
||||
TIM17_IRQHandler
|
||||
LPTIM1_IRQHandler
|
||||
LPTIM2_IRQHandler
|
||||
LPTIM3_IRQHandler
|
||||
LPTIM4_IRQHandler
|
||||
LPTIM5_IRQHandler
|
||||
SPDIF_RX_IRQHandler
|
||||
MDIOS_IRQHandler
|
||||
ADF1_FLT0_IRQHandler
|
||||
CRS_IRQHandler
|
||||
UCPD1_IRQHandler
|
||||
CEC_IRQHandler
|
||||
PSSI_IRQHandler
|
||||
LPUART1_IRQHandler
|
||||
WAKEUP_PIN_IRQHandler
|
||||
GPDMA1_Channel8_IRQHandler
|
||||
GPDMA1_Channel9_IRQHandler
|
||||
GPDMA1_Channel10_IRQHandler
|
||||
GPDMA1_Channel11_IRQHandler
|
||||
GPDMA1_Channel12_IRQHandler
|
||||
GPDMA1_Channel13_IRQHandler
|
||||
GPDMA1_Channel14_IRQHandler
|
||||
GPDMA1_Channel15_IRQHandler
|
||||
HPDMA1_Channel8_IRQHandler
|
||||
HPDMA1_Channel9_IRQHandler
|
||||
HPDMA1_Channel10_IRQHandler
|
||||
HPDMA1_Channel11_IRQHandler
|
||||
HPDMA1_Channel12_IRQHandler
|
||||
HPDMA1_Channel13_IRQHandler
|
||||
HPDMA1_Channel14_IRQHandler
|
||||
HPDMA1_Channel15_IRQHandler
|
||||
FDCAN1_IT0_IRQHandler
|
||||
FDCAN1_IT1_IRQHandler
|
||||
FDCAN2_IT0_IRQHandler
|
||||
FDCAN2_IT1_IRQHandler
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
|
|
@ -1,623 +0,0 @@
|
|||
;*******************************************************************************
|
||||
;* File Name : startup_stm32h7r7xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : STM32H7R7xx devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M7 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;*******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* Copyright (c) 2023 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;*******************************************************************************
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
; External Interrupts
|
||||
DCD PVD_PVM_IRQHandler ; PVD/PVM through EXTI Line detection
|
||||
DCD 0 ; Reserved
|
||||
DCD DTS_IRQHandler ; Digital Temperature Sensor
|
||||
DCD IWDG_IRQHandler ; Internal Watchdog
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD RCC_IRQHandler ; RCC global interrupts through EXTI Line detection
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD FLASH_IRQHandler ; FLASH interrupts
|
||||
DCD RAMECC_IRQHandler ; RAMECC interrupts
|
||||
DCD FPU_IRQHandler ; FPU
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD TAMP_IRQHandler ; Tamper and TimeStamp interrupts through EXTI Line detection
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD EXTI0_IRQHandler ; EXTI Line0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line4
|
||||
DCD EXTI5_IRQHandler ; EXTI Line5
|
||||
DCD EXTI6_IRQHandler ; EXTI Line6
|
||||
DCD EXTI7_IRQHandler ; EXTI Line7
|
||||
DCD EXTI8_IRQHandler ; EXTI Line8
|
||||
DCD EXTI9_IRQHandler ; EXTI Line9
|
||||
DCD EXTI10_IRQHandler ; EXTI Line10
|
||||
DCD EXTI11_IRQHandler ; EXTI Line11
|
||||
DCD EXTI12_IRQHandler ; EXTI Line12
|
||||
DCD EXTI13_IRQHandler ; EXTI Line13
|
||||
DCD EXTI14_IRQHandler ; EXTI Line14
|
||||
DCD EXTI15_IRQHandler ; EXTI Line15
|
||||
DCD RTC_IRQHandler ; RTC wakeup and alarm interrupts through EXTI Line detection
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PKA_IRQHandler ; PKA
|
||||
DCD HASH_IRQHandler ; HASH
|
||||
DCD RNG_IRQHandler ; RNG
|
||||
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
|
||||
DCD GPDMA1_Channel0_IRQHandler ; GPDMA1 Channel 0
|
||||
DCD GPDMA1_Channel1_IRQHandler ; GPDMA1 Channel 1
|
||||
DCD GPDMA1_Channel2_IRQHandler ; GPDMA1 Channel 2
|
||||
DCD GPDMA1_Channel3_IRQHandler ; GPDMA1 Channel 3
|
||||
DCD GPDMA1_Channel4_IRQHandler ; GPDMA1 Channel 4
|
||||
DCD GPDMA1_Channel5_IRQHandler ; GPDMA1 Channel 5
|
||||
DCD GPDMA1_Channel6_IRQHandler ; GPDMA1 Channel 6
|
||||
DCD GPDMA1_Channel7_IRQHandler ; GPDMA1 Channel 7
|
||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break
|
||||
DCD TIM1_UP_IRQHandler ; TIM1 Update
|
||||
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD TIM5_IRQHandler ; TIM5
|
||||
DCD TIM6_IRQHandler ; TIM6
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD TIM9_IRQHandler ; TIM9
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD SPI4_IRQHandler ; SPI4
|
||||
DCD SPI5_IRQHandler ; SPI5
|
||||
DCD SPI6_IRQHandler ; SPI6
|
||||
DCD HPDMA1_Channel0_IRQHandler ; HPDMA1 Channel 0
|
||||
DCD HPDMA1_Channel1_IRQHandler ; HPDMA1 Channel 1
|
||||
DCD HPDMA1_Channel2_IRQHandler ; HPDMA1 Channel 2
|
||||
DCD HPDMA1_Channel3_IRQHandler ; HPDMA1 Channel 3
|
||||
DCD HPDMA1_Channel4_IRQHandler ; HPDMA1 Channel 4
|
||||
DCD HPDMA1_Channel5_IRQHandler ; HPDMA1 Channel 5
|
||||
DCD HPDMA1_Channel6_IRQHandler ; HPDMA1 Channel 6
|
||||
DCD HPDMA1_Channel7_IRQHandler ; HPDMA1 Channel 7
|
||||
DCD SAI1_A_IRQHandler ; Serial Audio Interface 1 block A
|
||||
DCD SAI1_B_IRQHandler ; Serial Audio Interface 1 block B
|
||||
DCD SAI2_A_IRQHandler ; Serial Audio Interface 2 block A
|
||||
DCD SAI2_B_IRQHandler ; Serial Audio Interface 2 block B
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD I2C3_EV_IRQHandler ; I2C3 Event
|
||||
DCD I2C3_ER_IRQHandler ; I2C3 Error
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD UART4_IRQHandler ; UART4
|
||||
DCD UART5_IRQHandler ; UART5
|
||||
DCD UART7_IRQHandler ; UART7
|
||||
DCD UART8_IRQHandler ; UART8
|
||||
DCD I3C1_EV_IRQHandler ; I3C1 Event
|
||||
DCD I3C1_ER_IRQHandler ; I3C1 Error
|
||||
DCD OTG_HS_IRQHandler ; USB OTG HS
|
||||
DCD ETH_IRQHandler ; Ethernet
|
||||
DCD CORDIC_IRQHandler ; CORDIC
|
||||
DCD GFXTIM_IRQHandler ; GFXTIM
|
||||
DCD DCMIPP_IRQHandler ; DCMIPP
|
||||
DCD LTDC_IRQHandler ; LTDC
|
||||
DCD LTDC_ER_IRQHandler ; LTDC error
|
||||
DCD DMA2D_IRQHandler ; DMA2D
|
||||
DCD JPEG_IRQHandler ; JPEG
|
||||
DCD GFXMMU_IRQHandler ; GFXMMU
|
||||
DCD I3C1_WKUP_IRQHandler ; I3C1 wakeup
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD XSPI1_IRQHandler ; XSPI1
|
||||
DCD XSPI2_IRQHandler ; XSPI2
|
||||
DCD FMC_IRQHandler ; FMC
|
||||
DCD SDMMC1_IRQHandler ; SDMMC1
|
||||
DCD SDMMC2_IRQHandler ; SDMMC2
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD OTG_FS_IRQHandler ; USB OTG FS
|
||||
DCD TIM12_IRQHandler ; TIM12
|
||||
DCD TIM13_IRQHandler ; TIM13
|
||||
DCD TIM14_IRQHandler ; TIM14
|
||||
DCD TIM15_IRQHandler ; TIM15
|
||||
DCD TIM16_IRQHandler ; TIM16
|
||||
DCD TIM17_IRQHandler ; TIM17
|
||||
DCD LPTIM1_IRQHandler ; LP TIM1
|
||||
DCD LPTIM2_IRQHandler ; LP TIM2
|
||||
DCD LPTIM3_IRQHandler ; LP TIM3
|
||||
DCD LPTIM4_IRQHandler ; LP TIM4
|
||||
DCD LPTIM5_IRQHandler ; LP TIM5
|
||||
DCD SPDIF_RX_IRQHandler ; SPDIF_RX
|
||||
DCD MDIOS_IRQHandler ; MDIOS
|
||||
DCD ADF1_FLT0_IRQHandler ; ADF1 Filter 0
|
||||
DCD CRS_IRQHandler ; CRS
|
||||
DCD UCPD1_IRQHandler ; UCPD1
|
||||
DCD CEC_IRQHandler ; HDMI_CEC
|
||||
DCD PSSI_IRQHandler ; PSSI
|
||||
DCD LPUART1_IRQHandler ; LP UART1
|
||||
DCD WAKEUP_PIN_IRQHandler ; Wake-up pins interrupt
|
||||
DCD GPDMA1_Channel8_IRQHandler ; GPDMA1 Channel 8
|
||||
DCD GPDMA1_Channel9_IRQHandler ; GPDMA1 Channel 9
|
||||
DCD GPDMA1_Channel10_IRQHandler ; GPDMA1 Channel 10
|
||||
DCD GPDMA1_Channel11_IRQHandler ; GPDMA1 Channel 11
|
||||
DCD GPDMA1_Channel12_IRQHandler ; GPDMA1 Channel 12
|
||||
DCD GPDMA1_Channel13_IRQHandler ; GPDMA1 Channel 13
|
||||
DCD GPDMA1_Channel14_IRQHandler ; GPDMA1 Channel 14
|
||||
DCD GPDMA1_Channel15_IRQHandler ; GPDMA1 Channel 15
|
||||
DCD HPDMA1_Channel8_IRQHandler ; HPDMA1 Channel 8
|
||||
DCD HPDMA1_Channel9_IRQHandler ; HPDMA1 Channel 9
|
||||
DCD HPDMA1_Channel10_IRQHandler ; HPDMA1 Channel 10
|
||||
DCD HPDMA1_Channel11_IRQHandler ; HPDMA1 Channel 11
|
||||
DCD HPDMA1_Channel12_IRQHandler ; HPDMA1 Channel 12
|
||||
DCD HPDMA1_Channel13_IRQHandler ; HPDMA1 Channel 13
|
||||
DCD HPDMA1_Channel14_IRQHandler ; HPDMA1 Channel 14
|
||||
DCD HPDMA1_Channel15_IRQHandler ; HPDMA1 Channel 15
|
||||
DCD GPU2D_IRQHandler ; GPU2D
|
||||
DCD GPU2D_ER_IRQHandler ; GPU2D error
|
||||
DCD ICACHE_IRQHandler ; ICACHE
|
||||
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 Interrupt 0
|
||||
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 Interrupt 1
|
||||
DCD FDCAN2_IT0_IRQHandler ; FDCAN2 Interrupt 0
|
||||
DCD FDCAN2_IT1_IRQHandler ; FDCAN2 Interrupt 1
|
||||
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler\
|
||||
PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler\
|
||||
PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler\
|
||||
PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler\
|
||||
PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT PVD_PVM_IRQHandler [WEAK]
|
||||
EXPORT DTS_IRQHandler [WEAK]
|
||||
EXPORT IWDG_IRQHandler [WEAK]
|
||||
EXPORT WWDG_IRQHandler [WEAK]
|
||||
EXPORT RCC_IRQHandler [WEAK]
|
||||
EXPORT FLASH_IRQHandler [WEAK]
|
||||
EXPORT RAMECC_IRQHandler [WEAK]
|
||||
EXPORT FPU_IRQHandler [WEAK]
|
||||
EXPORT TAMP_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT EXTI5_IRQHandler [WEAK]
|
||||
EXPORT EXTI6_IRQHandler [WEAK]
|
||||
EXPORT EXTI7_IRQHandler [WEAK]
|
||||
EXPORT EXTI8_IRQHandler [WEAK]
|
||||
EXPORT EXTI9_IRQHandler [WEAK]
|
||||
EXPORT EXTI10_IRQHandler [WEAK]
|
||||
EXPORT EXTI11_IRQHandler [WEAK]
|
||||
EXPORT EXTI12_IRQHandler [WEAK]
|
||||
EXPORT EXTI13_IRQHandler [WEAK]
|
||||
EXPORT EXTI14_IRQHandler [WEAK]
|
||||
EXPORT EXTI15_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT PKA_IRQHandler [WEAK]
|
||||
EXPORT HASH_IRQHandler [WEAK]
|
||||
EXPORT RNG_IRQHandler [WEAK]
|
||||
EXPORT ADC1_2_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel0_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel1_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel2_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel3_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel4_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel5_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel6_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel7_IRQHandler [WEAK]
|
||||
EXPORT TIM1_BRK_IRQHandler [WEAK]
|
||||
EXPORT TIM1_UP_IRQHandler [WEAK]
|
||||
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
|
||||
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT TIM3_IRQHandler [WEAK]
|
||||
EXPORT TIM4_IRQHandler [WEAK]
|
||||
EXPORT TIM5_IRQHandler [WEAK]
|
||||
EXPORT TIM6_IRQHandler [WEAK]
|
||||
EXPORT TIM7_IRQHandler [WEAK]
|
||||
EXPORT TIM9_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT SPI3_IRQHandler [WEAK]
|
||||
EXPORT SPI4_IRQHandler [WEAK]
|
||||
EXPORT SPI5_IRQHandler [WEAK]
|
||||
EXPORT SPI6_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel0_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel1_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel2_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel3_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel4_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel5_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel6_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel7_IRQHandler [WEAK]
|
||||
EXPORT SAI1_A_IRQHandler [WEAK]
|
||||
EXPORT SAI1_B_IRQHandler [WEAK]
|
||||
EXPORT SAI2_A_IRQHandler [WEAK]
|
||||
EXPORT SAI2_B_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C3_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C3_ER_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT USART2_IRQHandler [WEAK]
|
||||
EXPORT USART3_IRQHandler [WEAK]
|
||||
EXPORT UART4_IRQHandler [WEAK]
|
||||
EXPORT UART5_IRQHandler [WEAK]
|
||||
EXPORT UART7_IRQHandler [WEAK]
|
||||
EXPORT UART8_IRQHandler [WEAK]
|
||||
EXPORT I3C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I3C1_ER_IRQHandler [WEAK]
|
||||
EXPORT OTG_HS_IRQHandler [WEAK]
|
||||
EXPORT ETH_IRQHandler [WEAK]
|
||||
EXPORT CORDIC_IRQHandler [WEAK]
|
||||
EXPORT GFXTIM_IRQHandler [WEAK]
|
||||
EXPORT DCMIPP_IRQHandler [WEAK]
|
||||
EXPORT LTDC_IRQHandler [WEAK]
|
||||
EXPORT LTDC_ER_IRQHandler [WEAK]
|
||||
EXPORT DMA2D_IRQHandler [WEAK]
|
||||
EXPORT JPEG_IRQHandler [WEAK]
|
||||
EXPORT GFXMMU_IRQHandler [WEAK]
|
||||
EXPORT I3C1_WKUP_IRQHandler [WEAK]
|
||||
EXPORT XSPI1_IRQHandler [WEAK]
|
||||
EXPORT XSPI2_IRQHandler [WEAK]
|
||||
EXPORT FMC_IRQHandler [WEAK]
|
||||
EXPORT SDMMC1_IRQHandler [WEAK]
|
||||
EXPORT SDMMC2_IRQHandler [WEAK]
|
||||
EXPORT OTG_FS_IRQHandler [WEAK]
|
||||
EXPORT TIM12_IRQHandler [WEAK]
|
||||
EXPORT TIM13_IRQHandler [WEAK]
|
||||
EXPORT TIM14_IRQHandler [WEAK]
|
||||
EXPORT TIM15_IRQHandler [WEAK]
|
||||
EXPORT TIM16_IRQHandler [WEAK]
|
||||
EXPORT TIM17_IRQHandler [WEAK]
|
||||
EXPORT LPTIM1_IRQHandler [WEAK]
|
||||
EXPORT LPTIM2_IRQHandler [WEAK]
|
||||
EXPORT LPTIM3_IRQHandler [WEAK]
|
||||
EXPORT LPTIM4_IRQHandler [WEAK]
|
||||
EXPORT LPTIM5_IRQHandler [WEAK]
|
||||
EXPORT SPDIF_RX_IRQHandler [WEAK]
|
||||
EXPORT MDIOS_IRQHandler [WEAK]
|
||||
EXPORT ADF1_FLT0_IRQHandler [WEAK]
|
||||
EXPORT CRS_IRQHandler [WEAK]
|
||||
EXPORT UCPD1_IRQHandler [WEAK]
|
||||
EXPORT CEC_IRQHandler [WEAK]
|
||||
EXPORT PSSI_IRQHandler [WEAK]
|
||||
EXPORT LPUART1_IRQHandler [WEAK]
|
||||
EXPORT WAKEUP_PIN_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel8_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel9_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel10_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel11_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel12_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel13_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel14_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel15_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel8_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel9_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel10_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel11_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel12_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel13_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel14_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel15_IRQHandler [WEAK]
|
||||
EXPORT GPU2D_IRQHandler [WEAK]
|
||||
EXPORT GPU2D_ER_IRQHandler [WEAK]
|
||||
EXPORT ICACHE_IRQHandler [WEAK]
|
||||
EXPORT FDCAN1_IT0_IRQHandler [WEAK]
|
||||
EXPORT FDCAN1_IT1_IRQHandler [WEAK]
|
||||
EXPORT FDCAN2_IT0_IRQHandler [WEAK]
|
||||
EXPORT FDCAN2_IT1_IRQHandler [WEAK]
|
||||
|
||||
PVD_PVM_IRQHandler
|
||||
DTS_IRQHandler
|
||||
IWDG_IRQHandler
|
||||
WWDG_IRQHandler
|
||||
RCC_IRQHandler
|
||||
FLASH_IRQHandler
|
||||
RAMECC_IRQHandler
|
||||
FPU_IRQHandler
|
||||
TAMP_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
EXTI5_IRQHandler
|
||||
EXTI6_IRQHandler
|
||||
EXTI7_IRQHandler
|
||||
EXTI8_IRQHandler
|
||||
EXTI9_IRQHandler
|
||||
EXTI10_IRQHandler
|
||||
EXTI11_IRQHandler
|
||||
EXTI12_IRQHandler
|
||||
EXTI13_IRQHandler
|
||||
EXTI14_IRQHandler
|
||||
EXTI15_IRQHandler
|
||||
RTC_IRQHandler
|
||||
PKA_IRQHandler
|
||||
HASH_IRQHandler
|
||||
RNG_IRQHandler
|
||||
ADC1_2_IRQHandler
|
||||
GPDMA1_Channel0_IRQHandler
|
||||
GPDMA1_Channel1_IRQHandler
|
||||
GPDMA1_Channel2_IRQHandler
|
||||
GPDMA1_Channel3_IRQHandler
|
||||
GPDMA1_Channel4_IRQHandler
|
||||
GPDMA1_Channel5_IRQHandler
|
||||
GPDMA1_Channel6_IRQHandler
|
||||
GPDMA1_Channel7_IRQHandler
|
||||
TIM1_BRK_IRQHandler
|
||||
TIM1_UP_IRQHandler
|
||||
TIM1_TRG_COM_IRQHandler
|
||||
TIM1_CC_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
TIM3_IRQHandler
|
||||
TIM4_IRQHandler
|
||||
TIM5_IRQHandler
|
||||
TIM6_IRQHandler
|
||||
TIM7_IRQHandler
|
||||
TIM9_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
SPI3_IRQHandler
|
||||
SPI4_IRQHandler
|
||||
SPI5_IRQHandler
|
||||
SPI6_IRQHandler
|
||||
HPDMA1_Channel0_IRQHandler
|
||||
HPDMA1_Channel1_IRQHandler
|
||||
HPDMA1_Channel2_IRQHandler
|
||||
HPDMA1_Channel3_IRQHandler
|
||||
HPDMA1_Channel4_IRQHandler
|
||||
HPDMA1_Channel5_IRQHandler
|
||||
HPDMA1_Channel6_IRQHandler
|
||||
HPDMA1_Channel7_IRQHandler
|
||||
SAI1_A_IRQHandler
|
||||
SAI1_B_IRQHandler
|
||||
SAI2_A_IRQHandler
|
||||
SAI2_B_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
I2C2_EV_IRQHandler
|
||||
I2C2_ER_IRQHandler
|
||||
I2C3_EV_IRQHandler
|
||||
I2C3_ER_IRQHandler
|
||||
USART1_IRQHandler
|
||||
USART2_IRQHandler
|
||||
USART3_IRQHandler
|
||||
UART4_IRQHandler
|
||||
UART5_IRQHandler
|
||||
UART7_IRQHandler
|
||||
UART8_IRQHandler
|
||||
I3C1_EV_IRQHandler
|
||||
I3C1_ER_IRQHandler
|
||||
OTG_HS_IRQHandler
|
||||
ETH_IRQHandler
|
||||
CORDIC_IRQHandler
|
||||
GFXTIM_IRQHandler
|
||||
DCMIPP_IRQHandler
|
||||
LTDC_IRQHandler
|
||||
LTDC_ER_IRQHandler
|
||||
DMA2D_IRQHandler
|
||||
JPEG_IRQHandler
|
||||
GFXMMU_IRQHandler
|
||||
I3C1_WKUP_IRQHandler
|
||||
XSPI1_IRQHandler
|
||||
XSPI2_IRQHandler
|
||||
FMC_IRQHandler
|
||||
SDMMC1_IRQHandler
|
||||
SDMMC2_IRQHandler
|
||||
OTG_FS_IRQHandler
|
||||
TIM12_IRQHandler
|
||||
TIM13_IRQHandler
|
||||
TIM14_IRQHandler
|
||||
TIM15_IRQHandler
|
||||
TIM16_IRQHandler
|
||||
TIM17_IRQHandler
|
||||
LPTIM1_IRQHandler
|
||||
LPTIM2_IRQHandler
|
||||
LPTIM3_IRQHandler
|
||||
LPTIM4_IRQHandler
|
||||
LPTIM5_IRQHandler
|
||||
SPDIF_RX_IRQHandler
|
||||
MDIOS_IRQHandler
|
||||
ADF1_FLT0_IRQHandler
|
||||
CRS_IRQHandler
|
||||
UCPD1_IRQHandler
|
||||
CEC_IRQHandler
|
||||
PSSI_IRQHandler
|
||||
LPUART1_IRQHandler
|
||||
WAKEUP_PIN_IRQHandler
|
||||
GPDMA1_Channel8_IRQHandler
|
||||
GPDMA1_Channel9_IRQHandler
|
||||
GPDMA1_Channel10_IRQHandler
|
||||
GPDMA1_Channel11_IRQHandler
|
||||
GPDMA1_Channel12_IRQHandler
|
||||
GPDMA1_Channel13_IRQHandler
|
||||
GPDMA1_Channel14_IRQHandler
|
||||
GPDMA1_Channel15_IRQHandler
|
||||
HPDMA1_Channel8_IRQHandler
|
||||
HPDMA1_Channel9_IRQHandler
|
||||
HPDMA1_Channel10_IRQHandler
|
||||
HPDMA1_Channel11_IRQHandler
|
||||
HPDMA1_Channel12_IRQHandler
|
||||
HPDMA1_Channel13_IRQHandler
|
||||
HPDMA1_Channel14_IRQHandler
|
||||
HPDMA1_Channel15_IRQHandler
|
||||
GPU2D_IRQHandler
|
||||
GPU2D_ER_IRQHandler
|
||||
ICACHE_IRQHandler
|
||||
FDCAN1_IT0_IRQHandler
|
||||
FDCAN1_IT1_IRQHandler
|
||||
FDCAN2_IT0_IRQHandler
|
||||
FDCAN2_IT1_IRQHandler
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
|
|
@ -1,623 +0,0 @@
|
|||
;*******************************************************************************
|
||||
;* File Name : startup_stm32h7s3xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : STM32H7S3xx Crypto devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M7 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;*******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* Copyright (c) 2023 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;*******************************************************************************
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
; External Interrupts
|
||||
DCD PVD_PVM_IRQHandler ; PVD/PVM through EXTI Line detection
|
||||
DCD 0 ; Reserved
|
||||
DCD DTS_IRQHandler ; Digital Temperature Sensor
|
||||
DCD IWDG_IRQHandler ; Internal Watchdog
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD RCC_IRQHandler ; RCC global interrupts through EXTI Line detection
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD FLASH_IRQHandler ; FLASH interrupts
|
||||
DCD RAMECC_IRQHandler ; RAMECC interrupts
|
||||
DCD FPU_IRQHandler ; FPU
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD TAMP_IRQHandler ; Tamper and TimeStamp interrupts through EXTI Line detection
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD EXTI0_IRQHandler ; EXTI Line0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line4
|
||||
DCD EXTI5_IRQHandler ; EXTI Line5
|
||||
DCD EXTI6_IRQHandler ; EXTI Line6
|
||||
DCD EXTI7_IRQHandler ; EXTI Line7
|
||||
DCD EXTI8_IRQHandler ; EXTI Line8
|
||||
DCD EXTI9_IRQHandler ; EXTI Line9
|
||||
DCD EXTI10_IRQHandler ; EXTI Line10
|
||||
DCD EXTI11_IRQHandler ; EXTI Line11
|
||||
DCD EXTI12_IRQHandler ; EXTI Line12
|
||||
DCD EXTI13_IRQHandler ; EXTI Line13
|
||||
DCD EXTI14_IRQHandler ; EXTI Line14
|
||||
DCD EXTI15_IRQHandler ; EXTI Line15
|
||||
DCD RTC_IRQHandler ; RTC wakeup and alarm interrupts through EXTI Line detection
|
||||
DCD SAES_IRQHandler ; SAES
|
||||
DCD CRYP_IRQHandler ; CRYP
|
||||
DCD PKA_IRQHandler ; PKA
|
||||
DCD HASH_IRQHandler ; HASH
|
||||
DCD RNG_IRQHandler ; RNG
|
||||
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
|
||||
DCD GPDMA1_Channel0_IRQHandler ; GPDMA1 Channel 0
|
||||
DCD GPDMA1_Channel1_IRQHandler ; GPDMA1 Channel 1
|
||||
DCD GPDMA1_Channel2_IRQHandler ; GPDMA1 Channel 2
|
||||
DCD GPDMA1_Channel3_IRQHandler ; GPDMA1 Channel 3
|
||||
DCD GPDMA1_Channel4_IRQHandler ; GPDMA1 Channel 4
|
||||
DCD GPDMA1_Channel5_IRQHandler ; GPDMA1 Channel 5
|
||||
DCD GPDMA1_Channel6_IRQHandler ; GPDMA1 Channel 6
|
||||
DCD GPDMA1_Channel7_IRQHandler ; GPDMA1 Channel 7
|
||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break
|
||||
DCD TIM1_UP_IRQHandler ; TIM1 Update
|
||||
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD TIM5_IRQHandler ; TIM5
|
||||
DCD TIM6_IRQHandler ; TIM6
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD TIM9_IRQHandler ; TIM9
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD SPI4_IRQHandler ; SPI4
|
||||
DCD SPI5_IRQHandler ; SPI5
|
||||
DCD SPI6_IRQHandler ; SPI6
|
||||
DCD HPDMA1_Channel0_IRQHandler ; HPDMA1 Channel 0
|
||||
DCD HPDMA1_Channel1_IRQHandler ; HPDMA1 Channel 1
|
||||
DCD HPDMA1_Channel2_IRQHandler ; HPDMA1 Channel 2
|
||||
DCD HPDMA1_Channel3_IRQHandler ; HPDMA1 Channel 3
|
||||
DCD HPDMA1_Channel4_IRQHandler ; HPDMA1 Channel 4
|
||||
DCD HPDMA1_Channel5_IRQHandler ; HPDMA1 Channel 5
|
||||
DCD HPDMA1_Channel6_IRQHandler ; HPDMA1 Channel 6
|
||||
DCD HPDMA1_Channel7_IRQHandler ; HPDMA1 Channel 7
|
||||
DCD SAI1_A_IRQHandler ; Serial Audio Interface 1 block A
|
||||
DCD SAI1_B_IRQHandler ; Serial Audio Interface 1 block B
|
||||
DCD SAI2_A_IRQHandler ; Serial Audio Interface 2 block A
|
||||
DCD SAI2_B_IRQHandler ; Serial Audio Interface 2 block B
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD I2C3_EV_IRQHandler ; I2C3 Event
|
||||
DCD I2C3_ER_IRQHandler ; I2C3 Error
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD UART4_IRQHandler ; UART4
|
||||
DCD UART5_IRQHandler ; UART5
|
||||
DCD UART7_IRQHandler ; UART7
|
||||
DCD UART8_IRQHandler ; UART8
|
||||
DCD I3C1_EV_IRQHandler ; I3C1 Event
|
||||
DCD I3C1_ER_IRQHandler ; I3C1 Error
|
||||
DCD OTG_HS_IRQHandler ; USB OTG HS
|
||||
DCD ETH_IRQHandler ; Ethernet
|
||||
DCD CORDIC_IRQHandler ; CORDIC
|
||||
DCD GFXTIM_IRQHandler ; GFXTIM
|
||||
DCD DCMIPP_IRQHandler ; DCMIPP
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD DMA2D_IRQHandler ; DMA2D
|
||||
DCD JPEG_IRQHandler ; JPEG
|
||||
DCD GFXMMU_IRQHandler ; GFXMMU
|
||||
DCD I3C1_WKUP_IRQHandler ; I3C1 wakeup
|
||||
DCD MCE1_IRQHandler ; MCE1
|
||||
DCD MCE2_IRQHandler ; MCE2
|
||||
DCD MCE3_IRQHandler ; MCE3
|
||||
DCD XSPI1_IRQHandler ; XSPI1
|
||||
DCD XSPI2_IRQHandler ; XSPI2
|
||||
DCD FMC_IRQHandler ; FMC
|
||||
DCD SDMMC1_IRQHandler ; SDMMC1
|
||||
DCD SDMMC2_IRQHandler ; SDMMC2
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD OTG_FS_IRQHandler ; USB OTG FS
|
||||
DCD TIM12_IRQHandler ; TIM12
|
||||
DCD TIM13_IRQHandler ; TIM13
|
||||
DCD TIM14_IRQHandler ; TIM14
|
||||
DCD TIM15_IRQHandler ; TIM15
|
||||
DCD TIM16_IRQHandler ; TIM16
|
||||
DCD TIM17_IRQHandler ; TIM17
|
||||
DCD LPTIM1_IRQHandler ; LP TIM1
|
||||
DCD LPTIM2_IRQHandler ; LP TIM2
|
||||
DCD LPTIM3_IRQHandler ; LP TIM3
|
||||
DCD LPTIM4_IRQHandler ; LP TIM4
|
||||
DCD LPTIM5_IRQHandler ; LP TIM5
|
||||
DCD SPDIF_RX_IRQHandler ; SPDIF_RX
|
||||
DCD MDIOS_IRQHandler ; MDIOS
|
||||
DCD ADF1_FLT0_IRQHandler ; ADF1 Filter 0
|
||||
DCD CRS_IRQHandler ; CRS
|
||||
DCD UCPD1_IRQHandler ; UCPD1
|
||||
DCD CEC_IRQHandler ; HDMI_CEC
|
||||
DCD PSSI_IRQHandler ; PSSI
|
||||
DCD LPUART1_IRQHandler ; LP UART1
|
||||
DCD WAKEUP_PIN_IRQHandler ; Wake-up pins interrupt
|
||||
DCD GPDMA1_Channel8_IRQHandler ; GPDMA1 Channel 8
|
||||
DCD GPDMA1_Channel9_IRQHandler ; GPDMA1 Channel 9
|
||||
DCD GPDMA1_Channel10_IRQHandler ; GPDMA1 Channel 10
|
||||
DCD GPDMA1_Channel11_IRQHandler ; GPDMA1 Channel 11
|
||||
DCD GPDMA1_Channel12_IRQHandler ; GPDMA1 Channel 12
|
||||
DCD GPDMA1_Channel13_IRQHandler ; GPDMA1 Channel 13
|
||||
DCD GPDMA1_Channel14_IRQHandler ; GPDMA1 Channel 14
|
||||
DCD GPDMA1_Channel15_IRQHandler ; GPDMA1 Channel 15
|
||||
DCD HPDMA1_Channel8_IRQHandler ; HPDMA1 Channel 8
|
||||
DCD HPDMA1_Channel9_IRQHandler ; HPDMA1 Channel 9
|
||||
DCD HPDMA1_Channel10_IRQHandler ; HPDMA1 Channel 10
|
||||
DCD HPDMA1_Channel11_IRQHandler ; HPDMA1 Channel 11
|
||||
DCD HPDMA1_Channel12_IRQHandler ; HPDMA1 Channel 12
|
||||
DCD HPDMA1_Channel13_IRQHandler ; HPDMA1 Channel 13
|
||||
DCD HPDMA1_Channel14_IRQHandler ; HPDMA1 Channel 14
|
||||
DCD HPDMA1_Channel15_IRQHandler ; HPDMA1 Channel 15
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 Interrupt 0
|
||||
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 Interrupt 1
|
||||
DCD FDCAN2_IT0_IRQHandler ; FDCAN2 Interrupt 0
|
||||
DCD FDCAN2_IT1_IRQHandler ; FDCAN2 Interrupt 1
|
||||
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler\
|
||||
PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler\
|
||||
PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler\
|
||||
PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler\
|
||||
PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT PVD_PVM_IRQHandler [WEAK]
|
||||
EXPORT DTS_IRQHandler [WEAK]
|
||||
EXPORT IWDG_IRQHandler [WEAK]
|
||||
EXPORT WWDG_IRQHandler [WEAK]
|
||||
EXPORT RCC_IRQHandler [WEAK]
|
||||
EXPORT FLASH_IRQHandler [WEAK]
|
||||
EXPORT RAMECC_IRQHandler [WEAK]
|
||||
EXPORT FPU_IRQHandler [WEAK]
|
||||
EXPORT TAMP_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT EXTI5_IRQHandler [WEAK]
|
||||
EXPORT EXTI6_IRQHandler [WEAK]
|
||||
EXPORT EXTI7_IRQHandler [WEAK]
|
||||
EXPORT EXTI8_IRQHandler [WEAK]
|
||||
EXPORT EXTI9_IRQHandler [WEAK]
|
||||
EXPORT EXTI10_IRQHandler [WEAK]
|
||||
EXPORT EXTI11_IRQHandler [WEAK]
|
||||
EXPORT EXTI12_IRQHandler [WEAK]
|
||||
EXPORT EXTI13_IRQHandler [WEAK]
|
||||
EXPORT EXTI14_IRQHandler [WEAK]
|
||||
EXPORT EXTI15_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT SAES_IRQHandler [WEAK]
|
||||
EXPORT CRYP_IRQHandler [WEAK]
|
||||
EXPORT PKA_IRQHandler [WEAK]
|
||||
EXPORT HASH_IRQHandler [WEAK]
|
||||
EXPORT RNG_IRQHandler [WEAK]
|
||||
EXPORT ADC1_2_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel0_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel1_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel2_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel3_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel4_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel5_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel6_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel7_IRQHandler [WEAK]
|
||||
EXPORT TIM1_BRK_IRQHandler [WEAK]
|
||||
EXPORT TIM1_UP_IRQHandler [WEAK]
|
||||
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
|
||||
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT TIM3_IRQHandler [WEAK]
|
||||
EXPORT TIM4_IRQHandler [WEAK]
|
||||
EXPORT TIM5_IRQHandler [WEAK]
|
||||
EXPORT TIM6_IRQHandler [WEAK]
|
||||
EXPORT TIM7_IRQHandler [WEAK]
|
||||
EXPORT TIM9_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT SPI3_IRQHandler [WEAK]
|
||||
EXPORT SPI4_IRQHandler [WEAK]
|
||||
EXPORT SPI5_IRQHandler [WEAK]
|
||||
EXPORT SPI6_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel0_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel1_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel2_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel3_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel4_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel5_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel6_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel7_IRQHandler [WEAK]
|
||||
EXPORT SAI1_A_IRQHandler [WEAK]
|
||||
EXPORT SAI1_B_IRQHandler [WEAK]
|
||||
EXPORT SAI2_A_IRQHandler [WEAK]
|
||||
EXPORT SAI2_B_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C3_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C3_ER_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT USART2_IRQHandler [WEAK]
|
||||
EXPORT USART3_IRQHandler [WEAK]
|
||||
EXPORT UART4_IRQHandler [WEAK]
|
||||
EXPORT UART5_IRQHandler [WEAK]
|
||||
EXPORT UART7_IRQHandler [WEAK]
|
||||
EXPORT UART8_IRQHandler [WEAK]
|
||||
EXPORT I3C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I3C1_ER_IRQHandler [WEAK]
|
||||
EXPORT OTG_HS_IRQHandler [WEAK]
|
||||
EXPORT ETH_IRQHandler [WEAK]
|
||||
EXPORT CORDIC_IRQHandler [WEAK]
|
||||
EXPORT GFXTIM_IRQHandler [WEAK]
|
||||
EXPORT DCMIPP_IRQHandler [WEAK]
|
||||
EXPORT DMA2D_IRQHandler [WEAK]
|
||||
EXPORT JPEG_IRQHandler [WEAK]
|
||||
EXPORT GFXMMU_IRQHandler [WEAK]
|
||||
EXPORT I3C1_WKUP_IRQHandler [WEAK]
|
||||
EXPORT MCE1_IRQHandler [WEAK]
|
||||
EXPORT MCE2_IRQHandler [WEAK]
|
||||
EXPORT MCE3_IRQHandler [WEAK]
|
||||
EXPORT XSPI1_IRQHandler [WEAK]
|
||||
EXPORT XSPI2_IRQHandler [WEAK]
|
||||
EXPORT FMC_IRQHandler [WEAK]
|
||||
EXPORT SDMMC1_IRQHandler [WEAK]
|
||||
EXPORT SDMMC2_IRQHandler [WEAK]
|
||||
EXPORT OTG_FS_IRQHandler [WEAK]
|
||||
EXPORT TIM12_IRQHandler [WEAK]
|
||||
EXPORT TIM13_IRQHandler [WEAK]
|
||||
EXPORT TIM14_IRQHandler [WEAK]
|
||||
EXPORT TIM15_IRQHandler [WEAK]
|
||||
EXPORT TIM16_IRQHandler [WEAK]
|
||||
EXPORT TIM17_IRQHandler [WEAK]
|
||||
EXPORT LPTIM1_IRQHandler [WEAK]
|
||||
EXPORT LPTIM2_IRQHandler [WEAK]
|
||||
EXPORT LPTIM3_IRQHandler [WEAK]
|
||||
EXPORT LPTIM4_IRQHandler [WEAK]
|
||||
EXPORT LPTIM5_IRQHandler [WEAK]
|
||||
EXPORT SPDIF_RX_IRQHandler [WEAK]
|
||||
EXPORT MDIOS_IRQHandler [WEAK]
|
||||
EXPORT ADF1_FLT0_IRQHandler [WEAK]
|
||||
EXPORT CRS_IRQHandler [WEAK]
|
||||
EXPORT UCPD1_IRQHandler [WEAK]
|
||||
EXPORT CEC_IRQHandler [WEAK]
|
||||
EXPORT PSSI_IRQHandler [WEAK]
|
||||
EXPORT LPUART1_IRQHandler [WEAK]
|
||||
EXPORT WAKEUP_PIN_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel8_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel9_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel10_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel11_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel12_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel13_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel14_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel15_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel8_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel9_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel10_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel11_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel12_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel13_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel14_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel15_IRQHandler [WEAK]
|
||||
EXPORT FDCAN1_IT0_IRQHandler [WEAK]
|
||||
EXPORT FDCAN1_IT1_IRQHandler [WEAK]
|
||||
EXPORT FDCAN2_IT0_IRQHandler [WEAK]
|
||||
EXPORT FDCAN2_IT1_IRQHandler [WEAK]
|
||||
|
||||
PVD_PVM_IRQHandler
|
||||
DTS_IRQHandler
|
||||
IWDG_IRQHandler
|
||||
WWDG_IRQHandler
|
||||
RCC_IRQHandler
|
||||
FLASH_IRQHandler
|
||||
RAMECC_IRQHandler
|
||||
FPU_IRQHandler
|
||||
TAMP_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
EXTI5_IRQHandler
|
||||
EXTI6_IRQHandler
|
||||
EXTI7_IRQHandler
|
||||
EXTI8_IRQHandler
|
||||
EXTI9_IRQHandler
|
||||
EXTI10_IRQHandler
|
||||
EXTI11_IRQHandler
|
||||
EXTI12_IRQHandler
|
||||
EXTI13_IRQHandler
|
||||
EXTI14_IRQHandler
|
||||
EXTI15_IRQHandler
|
||||
RTC_IRQHandler
|
||||
SAES_IRQHandler
|
||||
CRYP_IRQHandler
|
||||
PKA_IRQHandler
|
||||
HASH_IRQHandler
|
||||
RNG_IRQHandler
|
||||
ADC1_2_IRQHandler
|
||||
GPDMA1_Channel0_IRQHandler
|
||||
GPDMA1_Channel1_IRQHandler
|
||||
GPDMA1_Channel2_IRQHandler
|
||||
GPDMA1_Channel3_IRQHandler
|
||||
GPDMA1_Channel4_IRQHandler
|
||||
GPDMA1_Channel5_IRQHandler
|
||||
GPDMA1_Channel6_IRQHandler
|
||||
GPDMA1_Channel7_IRQHandler
|
||||
TIM1_BRK_IRQHandler
|
||||
TIM1_UP_IRQHandler
|
||||
TIM1_TRG_COM_IRQHandler
|
||||
TIM1_CC_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
TIM3_IRQHandler
|
||||
TIM4_IRQHandler
|
||||
TIM5_IRQHandler
|
||||
TIM6_IRQHandler
|
||||
TIM7_IRQHandler
|
||||
TIM9_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
SPI3_IRQHandler
|
||||
SPI4_IRQHandler
|
||||
SPI5_IRQHandler
|
||||
SPI6_IRQHandler
|
||||
HPDMA1_Channel0_IRQHandler
|
||||
HPDMA1_Channel1_IRQHandler
|
||||
HPDMA1_Channel2_IRQHandler
|
||||
HPDMA1_Channel3_IRQHandler
|
||||
HPDMA1_Channel4_IRQHandler
|
||||
HPDMA1_Channel5_IRQHandler
|
||||
HPDMA1_Channel6_IRQHandler
|
||||
HPDMA1_Channel7_IRQHandler
|
||||
SAI1_A_IRQHandler
|
||||
SAI1_B_IRQHandler
|
||||
SAI2_A_IRQHandler
|
||||
SAI2_B_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
I2C2_EV_IRQHandler
|
||||
I2C2_ER_IRQHandler
|
||||
I2C3_EV_IRQHandler
|
||||
I2C3_ER_IRQHandler
|
||||
USART1_IRQHandler
|
||||
USART2_IRQHandler
|
||||
USART3_IRQHandler
|
||||
UART4_IRQHandler
|
||||
UART5_IRQHandler
|
||||
UART7_IRQHandler
|
||||
UART8_IRQHandler
|
||||
I3C1_EV_IRQHandler
|
||||
I3C1_ER_IRQHandler
|
||||
OTG_HS_IRQHandler
|
||||
ETH_IRQHandler
|
||||
CORDIC_IRQHandler
|
||||
GFXTIM_IRQHandler
|
||||
DCMIPP_IRQHandler
|
||||
DMA2D_IRQHandler
|
||||
JPEG_IRQHandler
|
||||
GFXMMU_IRQHandler
|
||||
I3C1_WKUP_IRQHandler
|
||||
MCE1_IRQHandler
|
||||
MCE2_IRQHandler
|
||||
MCE3_IRQHandler
|
||||
XSPI1_IRQHandler
|
||||
XSPI2_IRQHandler
|
||||
FMC_IRQHandler
|
||||
SDMMC1_IRQHandler
|
||||
SDMMC2_IRQHandler
|
||||
OTG_FS_IRQHandler
|
||||
TIM12_IRQHandler
|
||||
TIM13_IRQHandler
|
||||
TIM14_IRQHandler
|
||||
TIM15_IRQHandler
|
||||
TIM16_IRQHandler
|
||||
TIM17_IRQHandler
|
||||
LPTIM1_IRQHandler
|
||||
LPTIM2_IRQHandler
|
||||
LPTIM3_IRQHandler
|
||||
LPTIM4_IRQHandler
|
||||
LPTIM5_IRQHandler
|
||||
SPDIF_RX_IRQHandler
|
||||
MDIOS_IRQHandler
|
||||
ADF1_FLT0_IRQHandler
|
||||
CRS_IRQHandler
|
||||
UCPD1_IRQHandler
|
||||
CEC_IRQHandler
|
||||
PSSI_IRQHandler
|
||||
LPUART1_IRQHandler
|
||||
WAKEUP_PIN_IRQHandler
|
||||
GPDMA1_Channel8_IRQHandler
|
||||
GPDMA1_Channel9_IRQHandler
|
||||
GPDMA1_Channel10_IRQHandler
|
||||
GPDMA1_Channel11_IRQHandler
|
||||
GPDMA1_Channel12_IRQHandler
|
||||
GPDMA1_Channel13_IRQHandler
|
||||
GPDMA1_Channel14_IRQHandler
|
||||
GPDMA1_Channel15_IRQHandler
|
||||
HPDMA1_Channel8_IRQHandler
|
||||
HPDMA1_Channel9_IRQHandler
|
||||
HPDMA1_Channel10_IRQHandler
|
||||
HPDMA1_Channel11_IRQHandler
|
||||
HPDMA1_Channel12_IRQHandler
|
||||
HPDMA1_Channel13_IRQHandler
|
||||
HPDMA1_Channel14_IRQHandler
|
||||
HPDMA1_Channel15_IRQHandler
|
||||
FDCAN1_IT0_IRQHandler
|
||||
FDCAN1_IT1_IRQHandler
|
||||
FDCAN2_IT0_IRQHandler
|
||||
FDCAN2_IT1_IRQHandler
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
|
|
@ -1,633 +0,0 @@
|
|||
;*******************************************************************************
|
||||
;* File Name : startup_stm32h7s7xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : STM32H7S7xx Crypto devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M7 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;*******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* Copyright (c) 2023 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;*******************************************************************************
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
; External Interrupts
|
||||
DCD PVD_PVM_IRQHandler ; PVD/PVM through EXTI Line detection
|
||||
DCD 0 ; Reserved
|
||||
DCD DTS_IRQHandler ; Digital Temperature Sensor
|
||||
DCD IWDG_IRQHandler ; Internal Watchdog
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD RCC_IRQHandler ; RCC global interrupts through EXTI Line detection
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD FLASH_IRQHandler ; FLASH interrupts
|
||||
DCD RAMECC_IRQHandler ; RAMECC interrupts
|
||||
DCD FPU_IRQHandler ; FPU
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD TAMP_IRQHandler ; Tamper and TimeStamp interrupts through EXTI Line detection
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD EXTI0_IRQHandler ; EXTI Line0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line4
|
||||
DCD EXTI5_IRQHandler ; EXTI Line5
|
||||
DCD EXTI6_IRQHandler ; EXTI Line6
|
||||
DCD EXTI7_IRQHandler ; EXTI Line7
|
||||
DCD EXTI8_IRQHandler ; EXTI Line8
|
||||
DCD EXTI9_IRQHandler ; EXTI Line9
|
||||
DCD EXTI10_IRQHandler ; EXTI Line10
|
||||
DCD EXTI11_IRQHandler ; EXTI Line11
|
||||
DCD EXTI12_IRQHandler ; EXTI Line12
|
||||
DCD EXTI13_IRQHandler ; EXTI Line13
|
||||
DCD EXTI14_IRQHandler ; EXTI Line14
|
||||
DCD EXTI15_IRQHandler ; EXTI Line15
|
||||
DCD RTC_IRQHandler ; RTC wakeup and alarm interrupts through EXTI Line detection
|
||||
DCD SAES_IRQHandler ; SAES
|
||||
DCD CRYP_IRQHandler ; CRYP
|
||||
DCD PKA_IRQHandler ; PKA
|
||||
DCD HASH_IRQHandler ; HASH
|
||||
DCD RNG_IRQHandler ; RNG
|
||||
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
|
||||
DCD GPDMA1_Channel0_IRQHandler ; GPDMA1 Channel 0
|
||||
DCD GPDMA1_Channel1_IRQHandler ; GPDMA1 Channel 1
|
||||
DCD GPDMA1_Channel2_IRQHandler ; GPDMA1 Channel 2
|
||||
DCD GPDMA1_Channel3_IRQHandler ; GPDMA1 Channel 3
|
||||
DCD GPDMA1_Channel4_IRQHandler ; GPDMA1 Channel 4
|
||||
DCD GPDMA1_Channel5_IRQHandler ; GPDMA1 Channel 5
|
||||
DCD GPDMA1_Channel6_IRQHandler ; GPDMA1 Channel 6
|
||||
DCD GPDMA1_Channel7_IRQHandler ; GPDMA1 Channel 7
|
||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break
|
||||
DCD TIM1_UP_IRQHandler ; TIM1 Update
|
||||
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD TIM5_IRQHandler ; TIM5
|
||||
DCD TIM6_IRQHandler ; TIM6
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD TIM9_IRQHandler ; TIM9
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD SPI4_IRQHandler ; SPI4
|
||||
DCD SPI5_IRQHandler ; SPI5
|
||||
DCD SPI6_IRQHandler ; SPI6
|
||||
DCD HPDMA1_Channel0_IRQHandler ; HPDMA1 Channel 0
|
||||
DCD HPDMA1_Channel1_IRQHandler ; HPDMA1 Channel 1
|
||||
DCD HPDMA1_Channel2_IRQHandler ; HPDMA1 Channel 2
|
||||
DCD HPDMA1_Channel3_IRQHandler ; HPDMA1 Channel 3
|
||||
DCD HPDMA1_Channel4_IRQHandler ; HPDMA1 Channel 4
|
||||
DCD HPDMA1_Channel5_IRQHandler ; HPDMA1 Channel 5
|
||||
DCD HPDMA1_Channel6_IRQHandler ; HPDMA1 Channel 6
|
||||
DCD HPDMA1_Channel7_IRQHandler ; HPDMA1 Channel 7
|
||||
DCD SAI1_A_IRQHandler ; Serial Audio Interface 1 block A
|
||||
DCD SAI1_B_IRQHandler ; Serial Audio Interface 1 block B
|
||||
DCD SAI2_A_IRQHandler ; Serial Audio Interface 2 block A
|
||||
DCD SAI2_B_IRQHandler ; Serial Audio Interface 2 block B
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD I2C3_EV_IRQHandler ; I2C3 Event
|
||||
DCD I2C3_ER_IRQHandler ; I2C3 Error
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD UART4_IRQHandler ; UART4
|
||||
DCD UART5_IRQHandler ; UART5
|
||||
DCD UART7_IRQHandler ; UART7
|
||||
DCD UART8_IRQHandler ; UART8
|
||||
DCD I3C1_EV_IRQHandler ; I3C1 Event
|
||||
DCD I3C1_ER_IRQHandler ; I3C1 Error
|
||||
DCD OTG_HS_IRQHandler ; USB OTG HS
|
||||
DCD ETH_IRQHandler ; Ethernet
|
||||
DCD CORDIC_IRQHandler ; CORDIC
|
||||
DCD GFXTIM_IRQHandler ; GFXTIM
|
||||
DCD DCMIPP_IRQHandler ; DCMIPP
|
||||
DCD LTDC_IRQHandler ; LTDC
|
||||
DCD LTDC_ER_IRQHandler ; LTDC error
|
||||
DCD DMA2D_IRQHandler ; DMA2D
|
||||
DCD JPEG_IRQHandler ; JPEG
|
||||
DCD GFXMMU_IRQHandler ; GFXMMU
|
||||
DCD I3C1_WKUP_IRQHandler ; I3C1 wakeup
|
||||
DCD MCE1_IRQHandler ; MCE1
|
||||
DCD MCE2_IRQHandler ; MCE2
|
||||
DCD MCE3_IRQHandler ; MCE3
|
||||
DCD XSPI1_IRQHandler ; XSPI1
|
||||
DCD XSPI2_IRQHandler ; XSPI2
|
||||
DCD FMC_IRQHandler ; FMC
|
||||
DCD SDMMC1_IRQHandler ; SDMMC1
|
||||
DCD SDMMC2_IRQHandler ; SDMMC2
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD OTG_FS_IRQHandler ; USB OTG FS
|
||||
DCD TIM12_IRQHandler ; TIM12
|
||||
DCD TIM13_IRQHandler ; TIM13
|
||||
DCD TIM14_IRQHandler ; TIM14
|
||||
DCD TIM15_IRQHandler ; TIM15
|
||||
DCD TIM16_IRQHandler ; TIM16
|
||||
DCD TIM17_IRQHandler ; TIM17
|
||||
DCD LPTIM1_IRQHandler ; LP TIM1
|
||||
DCD LPTIM2_IRQHandler ; LP TIM2
|
||||
DCD LPTIM3_IRQHandler ; LP TIM3
|
||||
DCD LPTIM4_IRQHandler ; LP TIM4
|
||||
DCD LPTIM5_IRQHandler ; LP TIM5
|
||||
DCD SPDIF_RX_IRQHandler ; SPDIF_RX
|
||||
DCD MDIOS_IRQHandler ; MDIOS
|
||||
DCD ADF1_FLT0_IRQHandler ; ADF1 Filter 0
|
||||
DCD CRS_IRQHandler ; CRS
|
||||
DCD UCPD1_IRQHandler ; UCPD1
|
||||
DCD CEC_IRQHandler ; HDMI_CEC
|
||||
DCD PSSI_IRQHandler ; PSSI
|
||||
DCD LPUART1_IRQHandler ; LP UART1
|
||||
DCD WAKEUP_PIN_IRQHandler ; Wake-up pins interrupt
|
||||
DCD GPDMA1_Channel8_IRQHandler ; GPDMA1 Channel 8
|
||||
DCD GPDMA1_Channel9_IRQHandler ; GPDMA1 Channel 9
|
||||
DCD GPDMA1_Channel10_IRQHandler ; GPDMA1 Channel 10
|
||||
DCD GPDMA1_Channel11_IRQHandler ; GPDMA1 Channel 11
|
||||
DCD GPDMA1_Channel12_IRQHandler ; GPDMA1 Channel 12
|
||||
DCD GPDMA1_Channel13_IRQHandler ; GPDMA1 Channel 13
|
||||
DCD GPDMA1_Channel14_IRQHandler ; GPDMA1 Channel 14
|
||||
DCD GPDMA1_Channel15_IRQHandler ; GPDMA1 Channel 15
|
||||
DCD HPDMA1_Channel8_IRQHandler ; HPDMA1 Channel 8
|
||||
DCD HPDMA1_Channel9_IRQHandler ; HPDMA1 Channel 9
|
||||
DCD HPDMA1_Channel10_IRQHandler ; HPDMA1 Channel 10
|
||||
DCD HPDMA1_Channel11_IRQHandler ; HPDMA1 Channel 11
|
||||
DCD HPDMA1_Channel12_IRQHandler ; HPDMA1 Channel 12
|
||||
DCD HPDMA1_Channel13_IRQHandler ; HPDMA1 Channel 13
|
||||
DCD HPDMA1_Channel14_IRQHandler ; HPDMA1 Channel 14
|
||||
DCD HPDMA1_Channel15_IRQHandler ; HPDMA1 Channel 15
|
||||
DCD GPU2D_IRQHandler ; GPU2D
|
||||
DCD GPU2D_ER_IRQHandler ; GPU2D error
|
||||
DCD ICACHE_IRQHandler ; ICACHE
|
||||
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 Interrupt 0
|
||||
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 Interrupt 1
|
||||
DCD FDCAN2_IT0_IRQHandler ; FDCAN2 Interrupt 0
|
||||
DCD FDCAN2_IT1_IRQHandler ; FDCAN2 Interrupt 1
|
||||
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler\
|
||||
PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler\
|
||||
PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler\
|
||||
PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler\
|
||||
PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT PVD_PVM_IRQHandler [WEAK]
|
||||
EXPORT DTS_IRQHandler [WEAK]
|
||||
EXPORT IWDG_IRQHandler [WEAK]
|
||||
EXPORT WWDG_IRQHandler [WEAK]
|
||||
EXPORT RCC_IRQHandler [WEAK]
|
||||
EXPORT FLASH_IRQHandler [WEAK]
|
||||
EXPORT RAMECC_IRQHandler [WEAK]
|
||||
EXPORT FPU_IRQHandler [WEAK]
|
||||
EXPORT TAMP_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT EXTI5_IRQHandler [WEAK]
|
||||
EXPORT EXTI6_IRQHandler [WEAK]
|
||||
EXPORT EXTI7_IRQHandler [WEAK]
|
||||
EXPORT EXTI8_IRQHandler [WEAK]
|
||||
EXPORT EXTI9_IRQHandler [WEAK]
|
||||
EXPORT EXTI10_IRQHandler [WEAK]
|
||||
EXPORT EXTI11_IRQHandler [WEAK]
|
||||
EXPORT EXTI12_IRQHandler [WEAK]
|
||||
EXPORT EXTI13_IRQHandler [WEAK]
|
||||
EXPORT EXTI14_IRQHandler [WEAK]
|
||||
EXPORT EXTI15_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT SAES_IRQHandler [WEAK]
|
||||
EXPORT CRYP_IRQHandler [WEAK]
|
||||
EXPORT PKA_IRQHandler [WEAK]
|
||||
EXPORT HASH_IRQHandler [WEAK]
|
||||
EXPORT RNG_IRQHandler [WEAK]
|
||||
EXPORT ADC1_2_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel0_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel1_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel2_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel3_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel4_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel5_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel6_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel7_IRQHandler [WEAK]
|
||||
EXPORT TIM1_BRK_IRQHandler [WEAK]
|
||||
EXPORT TIM1_UP_IRQHandler [WEAK]
|
||||
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
|
||||
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT TIM3_IRQHandler [WEAK]
|
||||
EXPORT TIM4_IRQHandler [WEAK]
|
||||
EXPORT TIM5_IRQHandler [WEAK]
|
||||
EXPORT TIM6_IRQHandler [WEAK]
|
||||
EXPORT TIM7_IRQHandler [WEAK]
|
||||
EXPORT TIM9_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT SPI3_IRQHandler [WEAK]
|
||||
EXPORT SPI4_IRQHandler [WEAK]
|
||||
EXPORT SPI5_IRQHandler [WEAK]
|
||||
EXPORT SPI6_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel0_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel1_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel2_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel3_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel4_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel5_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel6_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel7_IRQHandler [WEAK]
|
||||
EXPORT SAI1_A_IRQHandler [WEAK]
|
||||
EXPORT SAI1_B_IRQHandler [WEAK]
|
||||
EXPORT SAI2_A_IRQHandler [WEAK]
|
||||
EXPORT SAI2_B_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C3_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C3_ER_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT USART2_IRQHandler [WEAK]
|
||||
EXPORT USART3_IRQHandler [WEAK]
|
||||
EXPORT UART4_IRQHandler [WEAK]
|
||||
EXPORT UART5_IRQHandler [WEAK]
|
||||
EXPORT UART7_IRQHandler [WEAK]
|
||||
EXPORT UART8_IRQHandler [WEAK]
|
||||
EXPORT I3C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I3C1_ER_IRQHandler [WEAK]
|
||||
EXPORT OTG_HS_IRQHandler [WEAK]
|
||||
EXPORT ETH_IRQHandler [WEAK]
|
||||
EXPORT CORDIC_IRQHandler [WEAK]
|
||||
EXPORT GFXTIM_IRQHandler [WEAK]
|
||||
EXPORT DCMIPP_IRQHandler [WEAK]
|
||||
EXPORT LTDC_IRQHandler [WEAK]
|
||||
EXPORT LTDC_ER_IRQHandler [WEAK]
|
||||
EXPORT DMA2D_IRQHandler [WEAK]
|
||||
EXPORT JPEG_IRQHandler [WEAK]
|
||||
EXPORT GFXMMU_IRQHandler [WEAK]
|
||||
EXPORT I3C1_WKUP_IRQHandler [WEAK]
|
||||
EXPORT MCE1_IRQHandler [WEAK]
|
||||
EXPORT MCE2_IRQHandler [WEAK]
|
||||
EXPORT MCE3_IRQHandler [WEAK]
|
||||
EXPORT XSPI1_IRQHandler [WEAK]
|
||||
EXPORT XSPI2_IRQHandler [WEAK]
|
||||
EXPORT FMC_IRQHandler [WEAK]
|
||||
EXPORT SDMMC1_IRQHandler [WEAK]
|
||||
EXPORT SDMMC2_IRQHandler [WEAK]
|
||||
EXPORT OTG_FS_IRQHandler [WEAK]
|
||||
EXPORT TIM12_IRQHandler [WEAK]
|
||||
EXPORT TIM13_IRQHandler [WEAK]
|
||||
EXPORT TIM14_IRQHandler [WEAK]
|
||||
EXPORT TIM15_IRQHandler [WEAK]
|
||||
EXPORT TIM16_IRQHandler [WEAK]
|
||||
EXPORT TIM17_IRQHandler [WEAK]
|
||||
EXPORT LPTIM1_IRQHandler [WEAK]
|
||||
EXPORT LPTIM2_IRQHandler [WEAK]
|
||||
EXPORT LPTIM3_IRQHandler [WEAK]
|
||||
EXPORT LPTIM4_IRQHandler [WEAK]
|
||||
EXPORT LPTIM5_IRQHandler [WEAK]
|
||||
EXPORT SPDIF_RX_IRQHandler [WEAK]
|
||||
EXPORT MDIOS_IRQHandler [WEAK]
|
||||
EXPORT ADF1_FLT0_IRQHandler [WEAK]
|
||||
EXPORT CRS_IRQHandler [WEAK]
|
||||
EXPORT UCPD1_IRQHandler [WEAK]
|
||||
EXPORT CEC_IRQHandler [WEAK]
|
||||
EXPORT PSSI_IRQHandler [WEAK]
|
||||
EXPORT LPUART1_IRQHandler [WEAK]
|
||||
EXPORT WAKEUP_PIN_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel8_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel9_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel10_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel11_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel12_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel13_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel14_IRQHandler [WEAK]
|
||||
EXPORT GPDMA1_Channel15_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel8_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel9_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel10_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel11_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel12_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel13_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel14_IRQHandler [WEAK]
|
||||
EXPORT HPDMA1_Channel15_IRQHandler [WEAK]
|
||||
EXPORT GPU2D_IRQHandler [WEAK]
|
||||
EXPORT GPU2D_ER_IRQHandler [WEAK]
|
||||
EXPORT ICACHE_IRQHandler [WEAK]
|
||||
EXPORT FDCAN1_IT0_IRQHandler [WEAK]
|
||||
EXPORT FDCAN1_IT1_IRQHandler [WEAK]
|
||||
EXPORT FDCAN2_IT0_IRQHandler [WEAK]
|
||||
EXPORT FDCAN2_IT1_IRQHandler [WEAK]
|
||||
|
||||
PVD_PVM_IRQHandler
|
||||
DTS_IRQHandler
|
||||
IWDG_IRQHandler
|
||||
WWDG_IRQHandler
|
||||
RCC_IRQHandler
|
||||
FLASH_IRQHandler
|
||||
RAMECC_IRQHandler
|
||||
FPU_IRQHandler
|
||||
TAMP_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
EXTI5_IRQHandler
|
||||
EXTI6_IRQHandler
|
||||
EXTI7_IRQHandler
|
||||
EXTI8_IRQHandler
|
||||
EXTI9_IRQHandler
|
||||
EXTI10_IRQHandler
|
||||
EXTI11_IRQHandler
|
||||
EXTI12_IRQHandler
|
||||
EXTI13_IRQHandler
|
||||
EXTI14_IRQHandler
|
||||
EXTI15_IRQHandler
|
||||
RTC_IRQHandler
|
||||
SAES_IRQHandler
|
||||
CRYP_IRQHandler
|
||||
PKA_IRQHandler
|
||||
HASH_IRQHandler
|
||||
RNG_IRQHandler
|
||||
ADC1_2_IRQHandler
|
||||
GPDMA1_Channel0_IRQHandler
|
||||
GPDMA1_Channel1_IRQHandler
|
||||
GPDMA1_Channel2_IRQHandler
|
||||
GPDMA1_Channel3_IRQHandler
|
||||
GPDMA1_Channel4_IRQHandler
|
||||
GPDMA1_Channel5_IRQHandler
|
||||
GPDMA1_Channel6_IRQHandler
|
||||
GPDMA1_Channel7_IRQHandler
|
||||
TIM1_BRK_IRQHandler
|
||||
TIM1_UP_IRQHandler
|
||||
TIM1_TRG_COM_IRQHandler
|
||||
TIM1_CC_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
TIM3_IRQHandler
|
||||
TIM4_IRQHandler
|
||||
TIM5_IRQHandler
|
||||
TIM6_IRQHandler
|
||||
TIM7_IRQHandler
|
||||
TIM9_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
SPI3_IRQHandler
|
||||
SPI4_IRQHandler
|
||||
SPI5_IRQHandler
|
||||
SPI6_IRQHandler
|
||||
HPDMA1_Channel0_IRQHandler
|
||||
HPDMA1_Channel1_IRQHandler
|
||||
HPDMA1_Channel2_IRQHandler
|
||||
HPDMA1_Channel3_IRQHandler
|
||||
HPDMA1_Channel4_IRQHandler
|
||||
HPDMA1_Channel5_IRQHandler
|
||||
HPDMA1_Channel6_IRQHandler
|
||||
HPDMA1_Channel7_IRQHandler
|
||||
SAI1_A_IRQHandler
|
||||
SAI1_B_IRQHandler
|
||||
SAI2_A_IRQHandler
|
||||
SAI2_B_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
I2C2_EV_IRQHandler
|
||||
I2C2_ER_IRQHandler
|
||||
I2C3_EV_IRQHandler
|
||||
I2C3_ER_IRQHandler
|
||||
USART1_IRQHandler
|
||||
USART2_IRQHandler
|
||||
USART3_IRQHandler
|
||||
UART4_IRQHandler
|
||||
UART5_IRQHandler
|
||||
UART7_IRQHandler
|
||||
UART8_IRQHandler
|
||||
I3C1_EV_IRQHandler
|
||||
I3C1_ER_IRQHandler
|
||||
OTG_HS_IRQHandler
|
||||
ETH_IRQHandler
|
||||
CORDIC_IRQHandler
|
||||
GFXTIM_IRQHandler
|
||||
DCMIPP_IRQHandler
|
||||
LTDC_IRQHandler
|
||||
LTDC_ER_IRQHandler
|
||||
DMA2D_IRQHandler
|
||||
JPEG_IRQHandler
|
||||
GFXMMU_IRQHandler
|
||||
I3C1_WKUP_IRQHandler
|
||||
MCE1_IRQHandler
|
||||
MCE2_IRQHandler
|
||||
MCE3_IRQHandler
|
||||
XSPI1_IRQHandler
|
||||
XSPI2_IRQHandler
|
||||
FMC_IRQHandler
|
||||
SDMMC1_IRQHandler
|
||||
SDMMC2_IRQHandler
|
||||
OTG_FS_IRQHandler
|
||||
TIM12_IRQHandler
|
||||
TIM13_IRQHandler
|
||||
TIM14_IRQHandler
|
||||
TIM15_IRQHandler
|
||||
TIM16_IRQHandler
|
||||
TIM17_IRQHandler
|
||||
LPTIM1_IRQHandler
|
||||
LPTIM2_IRQHandler
|
||||
LPTIM3_IRQHandler
|
||||
LPTIM4_IRQHandler
|
||||
LPTIM5_IRQHandler
|
||||
SPDIF_RX_IRQHandler
|
||||
MDIOS_IRQHandler
|
||||
ADF1_FLT0_IRQHandler
|
||||
CRS_IRQHandler
|
||||
UCPD1_IRQHandler
|
||||
CEC_IRQHandler
|
||||
PSSI_IRQHandler
|
||||
LPUART1_IRQHandler
|
||||
WAKEUP_PIN_IRQHandler
|
||||
GPDMA1_Channel8_IRQHandler
|
||||
GPDMA1_Channel9_IRQHandler
|
||||
GPDMA1_Channel10_IRQHandler
|
||||
GPDMA1_Channel11_IRQHandler
|
||||
GPDMA1_Channel12_IRQHandler
|
||||
GPDMA1_Channel13_IRQHandler
|
||||
GPDMA1_Channel14_IRQHandler
|
||||
GPDMA1_Channel15_IRQHandler
|
||||
HPDMA1_Channel8_IRQHandler
|
||||
HPDMA1_Channel9_IRQHandler
|
||||
HPDMA1_Channel10_IRQHandler
|
||||
HPDMA1_Channel11_IRQHandler
|
||||
HPDMA1_Channel12_IRQHandler
|
||||
HPDMA1_Channel13_IRQHandler
|
||||
HPDMA1_Channel14_IRQHandler
|
||||
HPDMA1_Channel15_IRQHandler
|
||||
GPU2D_IRQHandler
|
||||
GPU2D_ER_IRQHandler
|
||||
ICACHE_IRQHandler
|
||||
FDCAN1_IT0_IRQHandler
|
||||
FDCAN1_IT1_IRQHandler
|
||||
FDCAN2_IT0_IRQHandler
|
||||
FDCAN2_IT1_IRQHandler
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
|
|
@ -1,209 +0,0 @@
|
|||
/*
|
||||
******************************************************************************
|
||||
**
|
||||
** @file : LinkerScript.ld
|
||||
**
|
||||
** @author : Auto-generated by STM32CubeIDE
|
||||
**
|
||||
** @brief : Linker script for STM32H7R3xx Device from STM32H7RS series
|
||||
** 64Kbytes FLASH
|
||||
** 456Kbytes RAM
|
||||
**
|
||||
** Set heap size, stack size and stack location according
|
||||
** to application requirements.
|
||||
**
|
||||
** Set memory bank area and size if external memory is used
|
||||
**
|
||||
** Target : STMicroelectronics STM32
|
||||
**
|
||||
** Distribution: The file is distributed as is, without any warranty
|
||||
** of any kind.
|
||||
**
|
||||
******************************************************************************
|
||||
** @attention
|
||||
**
|
||||
** Copyright (c) 2023 STMicroelectronics.
|
||||
** All rights reserved.
|
||||
**
|
||||
** This software is licensed under terms that can be found in the LICENSE file
|
||||
** in the root directory of this software component.
|
||||
** If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
**
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = ORIGIN(DTCM) + LENGTH(DTCM); /* end of "DTCM" Ram type memory */
|
||||
|
||||
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||
|
||||
__FLASH_BEGIN = 0x08000000;
|
||||
__FLASH_SIZE = 0x00010000;
|
||||
|
||||
|
||||
__RAM_BEGIN = 0x24000000;
|
||||
__RAM_SIZE = 0x71C00;
|
||||
__RAM_NONCACHEABLEBUFFER_SIZE = 0x400;
|
||||
|
||||
/* Memories definition */
|
||||
MEMORY
|
||||
{
|
||||
RAM (xrw) : ORIGIN = __RAM_BEGIN, LENGTH = __RAM_SIZE
|
||||
RAM_NONCACHEABLEBUFFER (xrw) : ORIGIN = __RAM_BEGIN + __RAM_SIZE, LENGTH = __RAM_NONCACHEABLEBUFFER_SIZE
|
||||
|
||||
ITCM (xrw) : ORIGIN = 0x00000000, LENGTH = 0x00010000
|
||||
DTCM (rw) : ORIGIN = 0x20000000, LENGTH = 0x00010000
|
||||
SRAMAHB (rw) : ORIGIN = 0x30000000, LENGTH = 0x00008000
|
||||
BKPSRAM (rw) : ORIGIN = 0x38800000, LENGTH = 0x00001000
|
||||
|
||||
FLASH (xrw) : ORIGIN = __FLASH_BEGIN, LENGTH = __FLASH_SIZE
|
||||
}
|
||||
|
||||
/* Sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code into "FLASH" Rom type memory */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* The program code and other data into "FLASH" Rom type memory */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >FLASH
|
||||
|
||||
/* Constant data into "FLASH" Rom type memory */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* Used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections into "RAM" Ram type memory */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
*(.RamFunc) /* .RamFunc sections */
|
||||
*(.RamFunc*) /* .RamFunc* sections */
|
||||
|
||||
. = ALIGN(4);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
|
||||
} >RAM AT> FLASH
|
||||
|
||||
/* Uninitialized data section into "RAM" Ram type memory */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss section */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
|
||||
|
||||
RW_NONCACHEABLE :
|
||||
{
|
||||
__NONCACHEABLEBUFFER_BEGIN = .;/* create symbol for start of section */
|
||||
KEEP(*(noncacheable_buffer))
|
||||
__NONCACHEABLEBUFFER_END = .; /* create symbol for start of section */
|
||||
} > RAM_NONCACHEABLEBUFFER
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough "DTCM" Ram type memory left */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(8);
|
||||
} >DTCM
|
||||
|
||||
/* Remove information from the compiler libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
|
|
@ -1,206 +0,0 @@
|
|||
/*
|
||||
******************************************************************************
|
||||
**
|
||||
** @file : LinkerScript.ld (debug in RAM dedicated)
|
||||
**
|
||||
** @author : Auto-generated by STM32CubeIDE
|
||||
**
|
||||
** @brief : Linker script for STM32H7R3xx Device from STM32H7RS series
|
||||
**
|
||||
** Set heap size, stack size and stack location according
|
||||
** to application requirements.
|
||||
**
|
||||
** Set memory bank area and size if external memory is used
|
||||
**
|
||||
** Target : STMicroelectronics STM32
|
||||
**
|
||||
** Distribution: The file is distributed as is, without any warranty
|
||||
** of any kind.
|
||||
**
|
||||
******************************************************************************
|
||||
** @attention
|
||||
**
|
||||
** Copyright (c) 2023 STMicroelectronics.
|
||||
** All rights reserved.
|
||||
**
|
||||
** This software is licensed under terms that can be found in the LICENSE file
|
||||
** in the root directory of this software component.
|
||||
** If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
**
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
__FLASH_BEGIN = 0x24050000;
|
||||
__FLASH_SIZE = 0x00022000;
|
||||
|
||||
__RAM_BEGIN = 0x24000000;
|
||||
__RAM_SIZE = 0x50000;
|
||||
__RAM_NONCACHEABLEBUFFER_SIZE = 0x400;
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = ORIGIN(DTCM) + LENGTH(DTCM); /* end of "DTCM" Ram type memory */
|
||||
|
||||
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||
|
||||
/* Memories definition */
|
||||
MEMORY
|
||||
{
|
||||
RAM(xrw) : ORIGIN = __RAM_BEGIN, LENGTH = __RAM_SIZE
|
||||
RAM_NONCACHEABLEBUFFER (xrw) : ORIGIN = __RAM_BEGIN + __RAM_SIZE, LENGTH = __RAM_NONCACHEABLEBUFFER_SIZE
|
||||
|
||||
ITCM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K
|
||||
DTCM (rw) : ORIGIN = 0x20000000, LENGTH = 64K
|
||||
SRAMAHB(rw) : ORIGIN = 0x30000000, LENGTH = 32
|
||||
BKPSRAM(rw) : ORIGIN = 0x38800000, LENGTH = 4K
|
||||
|
||||
FLASH(xrw) : ORIGIN = __FLASH_BEGIN,LENGTH = __FLASH_SIZE
|
||||
}
|
||||
|
||||
/* Sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code into "FLASH" Ram type memory */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* The program code and other data into "FLASH" Ram type memory */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >FLASH
|
||||
|
||||
/* Constant data into "FLASH" Ram type memory */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* Used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections into "RAM" Ram type memory */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
*(.RamFunc) /* .RamFunc sections */
|
||||
*(.RamFunc*) /* .RamFunc* sections */
|
||||
|
||||
. = ALIGN(4);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
|
||||
} >RAM AT> FLASH
|
||||
|
||||
/* Uninitialized data section into "RAM" Ram type memory */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss section */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
|
||||
|
||||
RW_NONCACHEABLE :
|
||||
{
|
||||
__NONCACHEABLEBUFFER_BEGIN = .;/* create symbol for start of section */
|
||||
KEEP(*(noncacheable_buffer))
|
||||
__NONCACHEABLEBUFFER_END = .; /* create symbol for start of section */
|
||||
} >RAM_NONCACHEABLEBUFFER
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(8);
|
||||
} >DTCM
|
||||
|
||||
/* Remove information from the compiler libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
|
|
@ -1,209 +0,0 @@
|
|||
/*
|
||||
******************************************************************************
|
||||
**
|
||||
** @file : LinkerScript.ld
|
||||
**
|
||||
** @author : Auto-generated by STM32CubeIDE
|
||||
**
|
||||
** @brief : Linker script for STM32H7R7xx Device from STM32H7RS series
|
||||
** 64Kbytes FLASH
|
||||
** 456Kbytes RAM
|
||||
**
|
||||
** Set heap size, stack size and stack location according
|
||||
** to application requirements.
|
||||
**
|
||||
** Set memory bank area and size if external memory is used
|
||||
**
|
||||
** Target : STMicroelectronics STM32
|
||||
**
|
||||
** Distribution: The file is distributed as is, without any warranty
|
||||
** of any kind.
|
||||
**
|
||||
******************************************************************************
|
||||
** @attention
|
||||
**
|
||||
** Copyright (c) 2023 STMicroelectronics.
|
||||
** All rights reserved.
|
||||
**
|
||||
** This software is licensed under terms that can be found in the LICENSE file
|
||||
** in the root directory of this software component.
|
||||
** If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
**
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = ORIGIN(DTCM) + LENGTH(DTCM); /* end of "DTCM" Ram type memory */
|
||||
|
||||
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||
|
||||
__FLASH_BEGIN = 0x08000000;
|
||||
__FLASH_SIZE = 0x00010000;
|
||||
|
||||
|
||||
__RAM_BEGIN = 0x24000000;
|
||||
__RAM_SIZE = 0x71C00;
|
||||
__RAM_NONCACHEABLEBUFFER_SIZE = 0x400;
|
||||
|
||||
/* Memories definition */
|
||||
MEMORY
|
||||
{
|
||||
RAM (xrw) : ORIGIN = __RAM_BEGIN, LENGTH = __RAM_SIZE
|
||||
RAM_NONCACHEABLEBUFFER (xrw) : ORIGIN = __RAM_BEGIN + __RAM_SIZE, LENGTH = __RAM_NONCACHEABLEBUFFER_SIZE
|
||||
|
||||
ITCM (xrw) : ORIGIN = 0x00000000, LENGTH = 0x00010000
|
||||
DTCM (rw) : ORIGIN = 0x20000000, LENGTH = 0x00010000
|
||||
SRAMAHB (rw) : ORIGIN = 0x30000000, LENGTH = 0x00008000
|
||||
BKPSRAM (rw) : ORIGIN = 0x38800000, LENGTH = 0x00001000
|
||||
|
||||
FLASH (xrw) : ORIGIN = __FLASH_BEGIN, LENGTH = __FLASH_SIZE
|
||||
}
|
||||
|
||||
/* Sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code into "FLASH" Rom type memory */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* The program code and other data into "FLASH" Rom type memory */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >FLASH
|
||||
|
||||
/* Constant data into "FLASH" Rom type memory */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* Used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections into "RAM" Ram type memory */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
*(.RamFunc) /* .RamFunc sections */
|
||||
*(.RamFunc*) /* .RamFunc* sections */
|
||||
|
||||
. = ALIGN(4);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
|
||||
} >RAM AT> FLASH
|
||||
|
||||
/* Uninitialized data section into "RAM" Ram type memory */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss section */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
|
||||
|
||||
RW_NONCACHEABLE :
|
||||
{
|
||||
__NONCACHEABLEBUFFER_BEGIN = .;/* create symbol for start of section */
|
||||
KEEP(*(noncacheable_buffer))
|
||||
__NONCACHEABLEBUFFER_END = .; /* create symbol for start of section */
|
||||
} > RAM_NONCACHEABLEBUFFER
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough "DTCM" Ram type memory left */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(8);
|
||||
} >DTCM
|
||||
|
||||
/* Remove information from the compiler libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
|
|
@ -1,206 +0,0 @@
|
|||
/*
|
||||
******************************************************************************
|
||||
**
|
||||
** @file : LinkerScript.ld (debug in RAM dedicated)
|
||||
**
|
||||
** @author : Auto-generated by STM32CubeIDE
|
||||
**
|
||||
** @brief : Linker script for STM32H7R7xx Device from STM32H7RS series
|
||||
**
|
||||
** Set heap size, stack size and stack location according
|
||||
** to application requirements.
|
||||
**
|
||||
** Set memory bank area and size if external memory is used
|
||||
**
|
||||
** Target : STMicroelectronics STM32
|
||||
**
|
||||
** Distribution: The file is distributed as is, without any warranty
|
||||
** of any kind.
|
||||
**
|
||||
******************************************************************************
|
||||
** @attention
|
||||
**
|
||||
** Copyright (c) 2023 STMicroelectronics.
|
||||
** All rights reserved.
|
||||
**
|
||||
** This software is licensed under terms that can be found in the LICENSE file
|
||||
** in the root directory of this software component.
|
||||
** If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
**
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
__FLASH_BEGIN = 0x24050000;
|
||||
__FLASH_SIZE = 0x00022000;
|
||||
|
||||
__RAM_BEGIN = 0x24000000;
|
||||
__RAM_SIZE = 0x50000;
|
||||
__RAM_NONCACHEABLEBUFFER_SIZE = 0x400;
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = ORIGIN(DTCM) + LENGTH(DTCM); /* end of "DTCM" Ram type memory */
|
||||
|
||||
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||
|
||||
/* Memories definition */
|
||||
MEMORY
|
||||
{
|
||||
RAM(xrw) : ORIGIN = __RAM_BEGIN, LENGTH = __RAM_SIZE
|
||||
RAM_NONCACHEABLEBUFFER (xrw) : ORIGIN = __RAM_BEGIN + __RAM_SIZE, LENGTH = __RAM_NONCACHEABLEBUFFER_SIZE
|
||||
|
||||
ITCM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K
|
||||
DTCM (rw) : ORIGIN = 0x20000000, LENGTH = 64K
|
||||
SRAMAHB(rw) : ORIGIN = 0x30000000, LENGTH = 32
|
||||
BKPSRAM(rw) : ORIGIN = 0x38800000, LENGTH = 4K
|
||||
|
||||
FLASH(xrw) : ORIGIN = __FLASH_BEGIN,LENGTH = __FLASH_SIZE
|
||||
}
|
||||
|
||||
/* Sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code into "FLASH" Ram type memory */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* The program code and other data into "FLASH" Ram type memory */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >FLASH
|
||||
|
||||
/* Constant data into "FLASH" Ram type memory */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* Used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections into "RAM" Ram type memory */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
*(.RamFunc) /* .RamFunc sections */
|
||||
*(.RamFunc*) /* .RamFunc* sections */
|
||||
|
||||
. = ALIGN(4);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
|
||||
} >RAM AT> FLASH
|
||||
|
||||
/* Uninitialized data section into "RAM" Ram type memory */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss section */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
|
||||
|
||||
RW_NONCACHEABLE :
|
||||
{
|
||||
__NONCACHEABLEBUFFER_BEGIN = .;/* create symbol for start of section */
|
||||
KEEP(*(noncacheable_buffer))
|
||||
__NONCACHEABLEBUFFER_END = .; /* create symbol for start of section */
|
||||
} >RAM_NONCACHEABLEBUFFER
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(8);
|
||||
} >DTCM
|
||||
|
||||
/* Remove information from the compiler libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
|
|
@ -1,210 +0,0 @@
|
|||
/*
|
||||
******************************************************************************
|
||||
**
|
||||
** @file : LinkerScript.ld
|
||||
**
|
||||
** @author : STM32CubeIDE
|
||||
**
|
||||
** Abstract : Linker script for STM32H7Rxx8 Device
|
||||
** 64Kbytes FLASH
|
||||
** 456Kbytes RAM
|
||||
**
|
||||
** Set heap size, stack size and stack location according
|
||||
** to application requirements.
|
||||
**
|
||||
** Set memory bank area and size if external memory is used
|
||||
**
|
||||
** Target : STMicroelectronics STM32
|
||||
**
|
||||
** Distribution: The file is distributed as is, without any warranty
|
||||
** of any kind.
|
||||
**
|
||||
******************************************************************************
|
||||
** @attention
|
||||
**
|
||||
** Copyright (c) 2023 STMicroelectronics.
|
||||
** All rights reserved.
|
||||
**
|
||||
** This software is licensed under terms that can be found in the LICENSE file
|
||||
** in the root directory of this software component.
|
||||
** If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
**
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = ORIGIN(DTCM) + LENGTH(DTCM); /* end of "DTCM" Ram type memory */
|
||||
|
||||
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||
|
||||
__FLASH_BEGIN = 0x70000000;
|
||||
__FLASH_SIZE = 0x08000000;
|
||||
__EXTRAM_BEGIN = 0x90000000;
|
||||
__EXTRAM_SIZE = 0x02000000;
|
||||
|
||||
|
||||
__RAM = 0x24000000;
|
||||
__RAM_SIZE = 0x72000;
|
||||
__RAM_NONCACHEABLEBUFFER_SIZE = 0x400;
|
||||
|
||||
/* Memories definition */
|
||||
MEMORY
|
||||
{
|
||||
RAM (xrw) : ORIGIN = __RAM, LENGTH = __RAM_SIZE -__RAM_NONCACHEABLEBUFFER_SIZE
|
||||
RAM_NONCACHEABLEBUFFER (xrw) : ORIGIN = __RAM + __RAM_SIZE - __RAM_NONCACHEABLEBUFFER_SIZE, LENGTH = __RAM_NONCACHEABLEBUFFER_SIZE
|
||||
ITCM (rw) : ORIGIN = 0x00000000, LENGTH = 0x00010000
|
||||
DTCM (xrw) : ORIGIN = 0x20000000, LENGTH = 0x00010000
|
||||
SRAMAHB (rw) : ORIGIN = 0x30000000, LENGTH = 0x00008000
|
||||
BKPSRAM (rw) : ORIGIN = 0x38800000, LENGTH = 0x00001000
|
||||
FLASH (xrw) : ORIGIN = __FLASH_BEGIN, LENGTH = __FLASH_SIZE
|
||||
EXTRAM (rw) : ORIGIN = __EXTRAM_BEGIN,LENGTH = __EXTRAM_SIZE
|
||||
}
|
||||
|
||||
/* Sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code into "FLASH" Rom type memory */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* The program code and other data into "FLASH" Rom type memory */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >FLASH
|
||||
|
||||
/* Constant data into "FLASH" Rom type memory */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM.extab (READONLY) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM (READONLY) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.preinit_array (READONLY) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.init_array (READONLY) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.fini_array (READONLY) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* Used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections into "RAM" Ram type memory */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
*(.RamFunc) /* .RamFunc sections */
|
||||
*(.RamFunc*) /* .RamFunc* sections */
|
||||
|
||||
. = ALIGN(4);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
|
||||
} >RAM AT> FLASH
|
||||
|
||||
/* Uninitialized data section into "RAM" Ram type memory */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss section */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
|
||||
|
||||
RW_NONCACHEABLE :
|
||||
{
|
||||
__NONCACHEABLEBUFFER_BEGIN = .;/* create symbol for start of section */
|
||||
KEEP(*(noncacheable_buffer))
|
||||
__NONCACHEABLEBUFFER_END = .; /* create symbol for start of section */
|
||||
} > RAM_NONCACHEABLEBUFFER
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(8);
|
||||
} >DTCM
|
||||
|
||||
/* Remove information from the compiler libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
|
|
@ -1,206 +0,0 @@
|
|||
/*
|
||||
******************************************************************************
|
||||
**
|
||||
** @file : LinkerScript.ld
|
||||
**
|
||||
** @author : STM32CubeIDE
|
||||
**
|
||||
** Abstract : Linker script for STM32H7Rxx8 Device
|
||||
** 64Kbytes FLASH
|
||||
** 456Kbytes RAM
|
||||
**
|
||||
** Set heap size, stack size and stack location according
|
||||
** to application requirements.
|
||||
**
|
||||
** Set memory bank area and size if external memory is used
|
||||
**
|
||||
** Target : STMicroelectronics STM32
|
||||
**
|
||||
** Distribution: The file is distributed as is, without any warranty
|
||||
** of any kind.
|
||||
**
|
||||
******************************************************************************
|
||||
** @attention
|
||||
**
|
||||
** Copyright (c) 2023 STMicroelectronics.
|
||||
** All rights reserved.
|
||||
**
|
||||
** This software is licensed under terms that can be found in the LICENSE file
|
||||
** in the root directory of this software component.
|
||||
** If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
**
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = ORIGIN(DTCM) + LENGTH(DTCM); /* end of "DTCM" Ram type memory */
|
||||
|
||||
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||
|
||||
__FLASH_BEGIN = 0x90000000;
|
||||
__FLASH_SIZE = 0x08000000;
|
||||
|
||||
__RAM = 0x24000000;
|
||||
__RAM_SIZE = 0x72000;
|
||||
__RAM_NONCACHEABLEBUFFER_SIZE = 0x400;
|
||||
|
||||
/* Memories definition */
|
||||
MEMORY
|
||||
{
|
||||
RAM (xrw) : ORIGIN = __RAM, LENGTH = __RAM_SIZE -__RAM_NONCACHEABLEBUFFER_SIZE
|
||||
RAM_NONCACHEABLEBUFFER (xrw) : ORIGIN = __RAM + __RAM_SIZE - __RAM_NONCACHEABLEBUFFER_SIZE, LENGTH = __RAM_NONCACHEABLEBUFFER_SIZE
|
||||
ITCM (rw) : ORIGIN = 0x00000000, LENGTH = 0x00010000
|
||||
DTCM (xrw) : ORIGIN = 0x20000000, LENGTH = 0x00010000
|
||||
SRAMAHB (rw) : ORIGIN = 0x30000000, LENGTH = 0x00008000
|
||||
BKPSRAM (rw) : ORIGIN = 0x38800000, LENGTH = 0x00001000
|
||||
FLASH (xrw) : ORIGIN = __FLASH_BEGIN, LENGTH = __FLASH_SIZE
|
||||
}
|
||||
|
||||
/* Sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code into "FLASH" Rom type memory */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* The program code and other data into "FLASH" Rom type memory */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >FLASH
|
||||
|
||||
/* Constant data into "FLASH" Rom type memory */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM.extab (READONLY) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM (READONLY) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.preinit_array (READONLY) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.init_array (READONLY) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.fini_array (READONLY) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* Used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections into "RAM" Ram type memory */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
*(.RamFunc) /* .RamFunc sections */
|
||||
*(.RamFunc*) /* .RamFunc* sections */
|
||||
|
||||
. = ALIGN(4);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
|
||||
} >RAM AT> FLASH
|
||||
|
||||
/* Uninitialized data section into "RAM" Ram type memory */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss section */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
|
||||
|
||||
RW_NONCACHEABLE :
|
||||
{
|
||||
__NONCACHEABLEBUFFER_BEGIN = .;/* create symbol for start of section */
|
||||
KEEP(*(noncacheable_buffer))
|
||||
__NONCACHEABLEBUFFER_END = .; /* create symbol for start of section */
|
||||
} > RAM_NONCACHEABLEBUFFER
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(8);
|
||||
} >DTCM
|
||||
|
||||
/* Remove information from the compiler libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
|
|
@ -1,210 +0,0 @@
|
|||
/*
|
||||
******************************************************************************
|
||||
**
|
||||
** @file : LinkerScript.ld
|
||||
**
|
||||
** @author : STM32CubeIDE
|
||||
**
|
||||
** Abstract : Linker script for STM32H7Rxx8 Device
|
||||
** 64Kbytes FLASH
|
||||
** 456Kbytes RAM
|
||||
**
|
||||
** Set heap size, stack size and stack location according
|
||||
** to application requirements.
|
||||
**
|
||||
** Set memory bank area and size if external memory is used
|
||||
**
|
||||
** Target : STMicroelectronics STM32
|
||||
**
|
||||
** Distribution: The file is distributed as is, without any warranty
|
||||
** of any kind.
|
||||
**
|
||||
******************************************************************************
|
||||
** @attention
|
||||
**
|
||||
** Copyright (c) 2023 STMicroelectronics.
|
||||
** All rights reserved.
|
||||
**
|
||||
** This software is licensed under terms that can be found in the LICENSE file
|
||||
** in the root directory of this software component.
|
||||
** If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
**
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = ORIGIN(DTCM) + LENGTH(DTCM); /* end of "DTCM" Ram type memory */
|
||||
|
||||
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||
|
||||
__FLASH_BEGIN = 0x90000000;
|
||||
__FLASH_SIZE = 0x08000000;
|
||||
__EXTRAM_BEGIN = 0x70000000;
|
||||
__EXTRAM_SIZE = 0x02000000;
|
||||
|
||||
|
||||
__RAM = 0x24000000;
|
||||
__RAM_SIZE = 0x72000;
|
||||
__RAM_NONCACHEABLEBUFFER_SIZE = 0x400;
|
||||
|
||||
/* Memories definition */
|
||||
MEMORY
|
||||
{
|
||||
RAM (xrw) : ORIGIN = __RAM, LENGTH = __RAM_SIZE -__RAM_NONCACHEABLEBUFFER_SIZE
|
||||
RAM_NONCACHEABLEBUFFER (xrw) : ORIGIN = __RAM + __RAM_SIZE - __RAM_NONCACHEABLEBUFFER_SIZE, LENGTH = __RAM_NONCACHEABLEBUFFER_SIZE
|
||||
ITCM (rw) : ORIGIN = 0x00000000, LENGTH = 0x00010000
|
||||
DTCM (xrw) : ORIGIN = 0x20000000, LENGTH = 0x00010000
|
||||
SRAMAHB (rw) : ORIGIN = 0x30000000, LENGTH = 0x00008000
|
||||
BKPSRAM (rw) : ORIGIN = 0x38800000, LENGTH = 0x00001000
|
||||
FLASH (xrw) : ORIGIN = __FLASH_BEGIN, LENGTH = __FLASH_SIZE
|
||||
EXTRAM (rw) : ORIGIN = __EXTRAM_BEGIN,LENGTH = __EXTRAM_SIZE
|
||||
}
|
||||
|
||||
/* Sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code into "FLASH" Rom type memory */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* The program code and other data into "FLASH" Rom type memory */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >FLASH
|
||||
|
||||
/* Constant data into "FLASH" Rom type memory */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM.extab (READONLY) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM (READONLY) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.preinit_array (READONLY) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.init_array (READONLY) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.fini_array (READONLY) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* Used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections into "RAM" Ram type memory */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
*(.RamFunc) /* .RamFunc sections */
|
||||
*(.RamFunc*) /* .RamFunc* sections */
|
||||
|
||||
. = ALIGN(4);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
|
||||
} >RAM AT> FLASH
|
||||
|
||||
/* Uninitialized data section into "RAM" Ram type memory */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss section */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
|
||||
|
||||
RW_NONCACHEABLE :
|
||||
{
|
||||
__NONCACHEABLEBUFFER_BEGIN = .;/* create symbol for start of section */
|
||||
KEEP(*(noncacheable_buffer))
|
||||
__NONCACHEABLEBUFFER_END = .; /* create symbol for start of section */
|
||||
} > RAM_NONCACHEABLEBUFFER
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(8);
|
||||
} >DTCM
|
||||
|
||||
/* Remove information from the compiler libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
|
|
@ -1,206 +0,0 @@
|
|||
/*
|
||||
******************************************************************************
|
||||
**
|
||||
** @file : LinkerScript.ld
|
||||
**
|
||||
** @author : STM32CubeIDE
|
||||
**
|
||||
** Abstract : Linker script for STM32H7Rxx8 Device
|
||||
** 64Kbytes FLASH
|
||||
** 456Kbytes RAM
|
||||
**
|
||||
** Set heap size, stack size and stack location according
|
||||
** to application requirements.
|
||||
**
|
||||
** Set memory bank area and size if external memory is used
|
||||
**
|
||||
** Target : STMicroelectronics STM32
|
||||
**
|
||||
** Distribution: The file is distributed as is, without any warranty
|
||||
** of any kind.
|
||||
**
|
||||
******************************************************************************
|
||||
** @attention
|
||||
**
|
||||
** Copyright (c) 2023 STMicroelectronics.
|
||||
** All rights reserved.
|
||||
**
|
||||
** This software is licensed under terms that can be found in the LICENSE file
|
||||
** in the root directory of this software component.
|
||||
** If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
**
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = ORIGIN(DTCM) + LENGTH(DTCM); /* end of "DTCM" Ram type memory */
|
||||
|
||||
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||
|
||||
__FLASH_BEGIN = 0x70000000;
|
||||
__FLASH_SIZE = 0x08000000;
|
||||
|
||||
__RAM = 0x24000000;
|
||||
__RAM_SIZE = 0x72000;
|
||||
__RAM_NONCACHEABLEBUFFER_SIZE = 0x400;
|
||||
|
||||
/* Memories definition */
|
||||
MEMORY
|
||||
{
|
||||
RAM (xrw) : ORIGIN = __RAM, LENGTH = __RAM_SIZE -__RAM_NONCACHEABLEBUFFER_SIZE
|
||||
RAM_NONCACHEABLEBUFFER (xrw) : ORIGIN = __RAM + __RAM_SIZE - __RAM_NONCACHEABLEBUFFER_SIZE, LENGTH = __RAM_NONCACHEABLEBUFFER_SIZE
|
||||
ITCM (rw) : ORIGIN = 0x00000000, LENGTH = 0x00010000
|
||||
DTCM (xrw) : ORIGIN = 0x20000000, LENGTH = 0x00010000
|
||||
SRAMAHB (rw) : ORIGIN = 0x30000000, LENGTH = 0x00008000
|
||||
BKPSRAM (rw) : ORIGIN = 0x38800000, LENGTH = 0x00001000
|
||||
FLASH (xrw) : ORIGIN = __FLASH_BEGIN, LENGTH = __FLASH_SIZE
|
||||
}
|
||||
|
||||
/* Sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code into "FLASH" Rom type memory */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* The program code and other data into "FLASH" Rom type memory */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >FLASH
|
||||
|
||||
/* Constant data into "FLASH" Rom type memory */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM.extab (READONLY) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM (READONLY) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.preinit_array (READONLY) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.init_array (READONLY) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.fini_array (READONLY) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* Used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections into "RAM" Ram type memory */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
*(.RamFunc) /* .RamFunc sections */
|
||||
*(.RamFunc*) /* .RamFunc* sections */
|
||||
|
||||
. = ALIGN(4);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
|
||||
} >RAM AT> FLASH
|
||||
|
||||
/* Uninitialized data section into "RAM" Ram type memory */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss section */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
|
||||
|
||||
RW_NONCACHEABLE :
|
||||
{
|
||||
__NONCACHEABLEBUFFER_BEGIN = .;/* create symbol for start of section */
|
||||
KEEP(*(noncacheable_buffer))
|
||||
__NONCACHEABLEBUFFER_END = .; /* create symbol for start of section */
|
||||
} > RAM_NONCACHEABLEBUFFER
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(8);
|
||||
} >DTCM
|
||||
|
||||
/* Remove information from the compiler libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
|
|
@ -1,159 +0,0 @@
|
|||
/*
|
||||
*****************************************************************************
|
||||
** File : linker.ld
|
||||
**
|
||||
** Set heap size, stack size and stack location according
|
||||
** to application requirements.
|
||||
**
|
||||
** Set memory bank area and size if external memory is used.
|
||||
**
|
||||
** Target : STMicroelectronics STM32
|
||||
**
|
||||
*****************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Generate 2 segment for Loader code and device info */
|
||||
PHDRS {Loader PT_LOAD FLAGS(5) ; SgInfo PT_LOAD ; }
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = ORIGIN(RAM_D1) + LENGTH(RAM_D1)-1; /* end of RAM */
|
||||
/* Generate a link error if heap and stack don't fit into RAM */
|
||||
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||
|
||||
/* Specify the memory areas */
|
||||
MEMORY
|
||||
{
|
||||
RAM_D1 (xrw) : ORIGIN = 0x20000004, LENGTH = 64K-4
|
||||
RAM_D2 (xrw) : ORIGIN = 0x24020000, LENGTH = 128K
|
||||
}
|
||||
|
||||
/* Define output sections */
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
|
||||
/* The startup code goes first into FLASH */
|
||||
.isr_vector :
|
||||
{
|
||||
. = . + 0x1FC;
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} >RAM_D1 :Loader
|
||||
|
||||
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >RAM_D1
|
||||
.ARM : {
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} >RAM_D1 :Loader
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >RAM_D1 :Loader
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >RAM_D1 :Loader
|
||||
|
||||
.fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >RAM_D1 :Loader
|
||||
|
||||
/* used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
|
||||
. = ALIGN(4);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
|
||||
} >RAM_D1 :Loader
|
||||
|
||||
|
||||
/* Uninitialized data section */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss section */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM_D2 :Loader
|
||||
|
||||
/* The program code and other data goes into FLASH */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >RAM_D1 :Loader
|
||||
|
||||
.stm32_device_info :
|
||||
{
|
||||
KEEP(*stm32_device_info.o ( .rodata* ))
|
||||
|
||||
} :SgInfo
|
||||
|
||||
|
||||
|
||||
/* Constant data goes into FLASH */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(4);
|
||||
} >RAM_D1 :Loader
|
||||
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(4);
|
||||
} >RAM_D1 :Loader
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
|
||||
|
|
@ -1,209 +0,0 @@
|
|||
/*
|
||||
******************************************************************************
|
||||
**
|
||||
** @file : LinkerScript.ld
|
||||
**
|
||||
** @author : Auto-generated by STM32CubeIDE
|
||||
**
|
||||
** @brief : Linker script for STM32H7S3xx Device from STM32H7RS series
|
||||
** 64Kbytes FLASH
|
||||
** 456Kbytes RAM
|
||||
**
|
||||
** Set heap size, stack size and stack location according
|
||||
** to application requirements.
|
||||
**
|
||||
** Set memory bank area and size if external memory is used
|
||||
**
|
||||
** Target : STMicroelectronics STM32
|
||||
**
|
||||
** Distribution: The file is distributed as is, without any warranty
|
||||
** of any kind.
|
||||
**
|
||||
******************************************************************************
|
||||
** @attention
|
||||
**
|
||||
** Copyright (c) 2023 STMicroelectronics.
|
||||
** All rights reserved.
|
||||
**
|
||||
** This software is licensed under terms that can be found in the LICENSE file
|
||||
** in the root directory of this software component.
|
||||
** If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
**
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = ORIGIN(DTCM) + LENGTH(DTCM); /* end of "DTCM" Ram type memory */
|
||||
|
||||
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||
|
||||
__FLASH_BEGIN = 0x08000000;
|
||||
__FLASH_SIZE = 0x00010000;
|
||||
|
||||
|
||||
__RAM_BEGIN = 0x24000000;
|
||||
__RAM_SIZE = 0x71C00;
|
||||
__RAM_NONCACHEABLEBUFFER_SIZE = 0x400;
|
||||
|
||||
/* Memories definition */
|
||||
MEMORY
|
||||
{
|
||||
RAM (xrw) : ORIGIN = __RAM_BEGIN, LENGTH = __RAM_SIZE
|
||||
RAM_NONCACHEABLEBUFFER (xrw) : ORIGIN = __RAM_BEGIN + __RAM_SIZE, LENGTH = __RAM_NONCACHEABLEBUFFER_SIZE
|
||||
|
||||
ITCM (xrw) : ORIGIN = 0x00000000, LENGTH = 0x00010000
|
||||
DTCM (rw) : ORIGIN = 0x20000000, LENGTH = 0x00010000
|
||||
SRAMAHB (rw) : ORIGIN = 0x30000000, LENGTH = 0x00008000
|
||||
BKPSRAM (rw) : ORIGIN = 0x38800000, LENGTH = 0x00001000
|
||||
|
||||
FLASH (xrw) : ORIGIN = __FLASH_BEGIN, LENGTH = __FLASH_SIZE
|
||||
}
|
||||
|
||||
/* Sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code into "FLASH" Rom type memory */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* The program code and other data into "FLASH" Rom type memory */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >FLASH
|
||||
|
||||
/* Constant data into "FLASH" Rom type memory */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* Used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections into "RAM" Ram type memory */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
*(.RamFunc) /* .RamFunc sections */
|
||||
*(.RamFunc*) /* .RamFunc* sections */
|
||||
|
||||
. = ALIGN(4);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
|
||||
} >RAM AT> FLASH
|
||||
|
||||
/* Uninitialized data section into "RAM" Ram type memory */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss section */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
|
||||
|
||||
RW_NONCACHEABLE :
|
||||
{
|
||||
__NONCACHEABLEBUFFER_BEGIN = .;/* create symbol for start of section */
|
||||
KEEP(*(noncacheable_buffer))
|
||||
__NONCACHEABLEBUFFER_END = .; /* create symbol for start of section */
|
||||
} > RAM_NONCACHEABLEBUFFER
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough "DTCM" Ram type memory left */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(8);
|
||||
} >DTCM
|
||||
|
||||
/* Remove information from the compiler libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
|
|
@ -1,206 +0,0 @@
|
|||
/*
|
||||
******************************************************************************
|
||||
**
|
||||
** @file : LinkerScript.ld (debug in RAM dedicated)
|
||||
**
|
||||
** @author : Auto-generated by STM32CubeIDE
|
||||
**
|
||||
** @brief : Linker script for STM32H7S3xx Device from STM32H7RS series
|
||||
**
|
||||
** Set heap size, stack size and stack location according
|
||||
** to application requirements.
|
||||
**
|
||||
** Set memory bank area and size if external memory is used
|
||||
**
|
||||
** Target : STMicroelectronics STM32
|
||||
**
|
||||
** Distribution: The file is distributed as is, without any warranty
|
||||
** of any kind.
|
||||
**
|
||||
******************************************************************************
|
||||
** @attention
|
||||
**
|
||||
** Copyright (c) 2023 STMicroelectronics.
|
||||
** All rights reserved.
|
||||
**
|
||||
** This software is licensed under terms that can be found in the LICENSE file
|
||||
** in the root directory of this software component.
|
||||
** If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
**
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
__FLASH_BEGIN = 0x24050000;
|
||||
__FLASH_SIZE = 0x00022000;
|
||||
|
||||
__RAM_BEGIN = 0x24000000;
|
||||
__RAM_SIZE = 0x50000;
|
||||
__RAM_NONCACHEABLEBUFFER_SIZE = 0x400;
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = ORIGIN(DTCM) + LENGTH(DTCM); /* end of "DTCM" Ram type memory */
|
||||
|
||||
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||
|
||||
/* Memories definition */
|
||||
MEMORY
|
||||
{
|
||||
RAM(xrw) : ORIGIN = __RAM_BEGIN, LENGTH = __RAM_SIZE
|
||||
RAM_NONCACHEABLEBUFFER (xrw) : ORIGIN = __RAM_BEGIN + __RAM_SIZE, LENGTH = __RAM_NONCACHEABLEBUFFER_SIZE
|
||||
|
||||
ITCM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K
|
||||
DTCM (rw) : ORIGIN = 0x20000000, LENGTH = 64K
|
||||
SRAMAHB(rw) : ORIGIN = 0x30000000, LENGTH = 32
|
||||
BKPSRAM(rw) : ORIGIN = 0x38800000, LENGTH = 4K
|
||||
|
||||
FLASH(xrw) : ORIGIN = __FLASH_BEGIN,LENGTH = __FLASH_SIZE
|
||||
}
|
||||
|
||||
/* Sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code into "FLASH" Ram type memory */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* The program code and other data into "FLASH" Ram type memory */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >FLASH
|
||||
|
||||
/* Constant data into "FLASH" Ram type memory */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* Used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections into "RAM" Ram type memory */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
*(.RamFunc) /* .RamFunc sections */
|
||||
*(.RamFunc*) /* .RamFunc* sections */
|
||||
|
||||
. = ALIGN(4);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
|
||||
} >RAM AT> FLASH
|
||||
|
||||
/* Uninitialized data section into "RAM" Ram type memory */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss section */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
|
||||
|
||||
RW_NONCACHEABLE :
|
||||
{
|
||||
__NONCACHEABLEBUFFER_BEGIN = .;/* create symbol for start of section */
|
||||
KEEP(*(noncacheable_buffer))
|
||||
__NONCACHEABLEBUFFER_END = .; /* create symbol for start of section */
|
||||
} >RAM_NONCACHEABLEBUFFER
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(8);
|
||||
} >DTCM
|
||||
|
||||
/* Remove information from the compiler libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
|
|
@ -1,209 +0,0 @@
|
|||
/*
|
||||
******************************************************************************
|
||||
**
|
||||
** @file : LinkerScript.ld
|
||||
**
|
||||
** @author : Auto-generated by STM32CubeIDE
|
||||
**
|
||||
** @brief : Linker script for STM32H7S7xx Device from STM32H7RS series
|
||||
** 64Kbytes FLASH
|
||||
** 456Kbytes RAM
|
||||
**
|
||||
** Set heap size, stack size and stack location according
|
||||
** to application requirements.
|
||||
**
|
||||
** Set memory bank area and size if external memory is used
|
||||
**
|
||||
** Target : STMicroelectronics STM32
|
||||
**
|
||||
** Distribution: The file is distributed as is, without any warranty
|
||||
** of any kind.
|
||||
**
|
||||
******************************************************************************
|
||||
** @attention
|
||||
**
|
||||
** Copyright (c) 2023 STMicroelectronics.
|
||||
** All rights reserved.
|
||||
**
|
||||
** This software is licensed under terms that can be found in the LICENSE file
|
||||
** in the root directory of this software component.
|
||||
** If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
**
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = ORIGIN(DTCM) + LENGTH(DTCM); /* end of "DTCM" Ram type memory */
|
||||
|
||||
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||
|
||||
__FLASH_BEGIN = 0x08000000;
|
||||
__FLASH_SIZE = 0x00010000;
|
||||
|
||||
|
||||
__RAM_BEGIN = 0x24000000;
|
||||
__RAM_SIZE = 0x71C00;
|
||||
__RAM_NONCACHEABLEBUFFER_SIZE = 0x400;
|
||||
|
||||
/* Memories definition */
|
||||
MEMORY
|
||||
{
|
||||
RAM (xrw) : ORIGIN = __RAM_BEGIN, LENGTH = __RAM_SIZE
|
||||
RAM_NONCACHEABLEBUFFER (xrw) : ORIGIN = __RAM_BEGIN + __RAM_SIZE, LENGTH = __RAM_NONCACHEABLEBUFFER_SIZE
|
||||
|
||||
ITCM (xrw) : ORIGIN = 0x00000000, LENGTH = 0x00010000
|
||||
DTCM (rw) : ORIGIN = 0x20000000, LENGTH = 0x00010000
|
||||
SRAMAHB (rw) : ORIGIN = 0x30000000, LENGTH = 0x00008000
|
||||
BKPSRAM (rw) : ORIGIN = 0x38800000, LENGTH = 0x00001000
|
||||
|
||||
FLASH (xrw) : ORIGIN = __FLASH_BEGIN, LENGTH = __FLASH_SIZE
|
||||
}
|
||||
|
||||
/* Sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code into "FLASH" Rom type memory */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* The program code and other data into "FLASH" Rom type memory */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >FLASH
|
||||
|
||||
/* Constant data into "FLASH" Rom type memory */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* Used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections into "RAM" Ram type memory */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
*(.RamFunc) /* .RamFunc sections */
|
||||
*(.RamFunc*) /* .RamFunc* sections */
|
||||
|
||||
. = ALIGN(4);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
|
||||
} >RAM AT> FLASH
|
||||
|
||||
/* Uninitialized data section into "RAM" Ram type memory */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss section */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
|
||||
|
||||
RW_NONCACHEABLE :
|
||||
{
|
||||
__NONCACHEABLEBUFFER_BEGIN = .;/* create symbol for start of section */
|
||||
KEEP(*(noncacheable_buffer))
|
||||
__NONCACHEABLEBUFFER_END = .; /* create symbol for start of section */
|
||||
} > RAM_NONCACHEABLEBUFFER
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough "DTCM" Ram type memory left */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(8);
|
||||
} >DTCM
|
||||
|
||||
/* Remove information from the compiler libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
|
|
@ -1,206 +0,0 @@
|
|||
/*
|
||||
******************************************************************************
|
||||
**
|
||||
** @file : LinkerScript.ld (debug in RAM dedicated)
|
||||
**
|
||||
** @author : Auto-generated by STM32CubeIDE
|
||||
**
|
||||
** @brief : Linker script for STM32H7S7xx Device from STM32H7RS series
|
||||
**
|
||||
** Set heap size, stack size and stack location according
|
||||
** to application requirements.
|
||||
**
|
||||
** Set memory bank area and size if external memory is used
|
||||
**
|
||||
** Target : STMicroelectronics STM32
|
||||
**
|
||||
** Distribution: The file is distributed as is, without any warranty
|
||||
** of any kind.
|
||||
**
|
||||
******************************************************************************
|
||||
** @attention
|
||||
**
|
||||
** Copyright (c) 2023 STMicroelectronics.
|
||||
** All rights reserved.
|
||||
**
|
||||
** This software is licensed under terms that can be found in the LICENSE file
|
||||
** in the root directory of this software component.
|
||||
** If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
**
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
__FLASH_BEGIN = 0x24050000;
|
||||
__FLASH_SIZE = 0x00022000;
|
||||
|
||||
__RAM_BEGIN = 0x24000000;
|
||||
__RAM_SIZE = 0x50000;
|
||||
__RAM_NONCACHEABLEBUFFER_SIZE = 0x400;
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = ORIGIN(DTCM) + LENGTH(DTCM); /* end of "DTCM" Ram type memory */
|
||||
|
||||
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||
|
||||
/* Memories definition */
|
||||
MEMORY
|
||||
{
|
||||
RAM(xrw) : ORIGIN = __RAM_BEGIN, LENGTH = __RAM_SIZE
|
||||
RAM_NONCACHEABLEBUFFER (xrw) : ORIGIN = __RAM_BEGIN + __RAM_SIZE, LENGTH = __RAM_NONCACHEABLEBUFFER_SIZE
|
||||
|
||||
ITCM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K
|
||||
DTCM (rw) : ORIGIN = 0x20000000, LENGTH = 64K
|
||||
SRAMAHB(rw) : ORIGIN = 0x30000000, LENGTH = 32
|
||||
BKPSRAM(rw) : ORIGIN = 0x38800000, LENGTH = 4K
|
||||
|
||||
FLASH(xrw) : ORIGIN = __FLASH_BEGIN,LENGTH = __FLASH_SIZE
|
||||
}
|
||||
|
||||
/* Sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code into "FLASH" Ram type memory */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* The program code and other data into "FLASH" Ram type memory */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >FLASH
|
||||
|
||||
/* Constant data into "FLASH" Ram type memory */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* Used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections into "RAM" Ram type memory */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
*(.RamFunc) /* .RamFunc sections */
|
||||
*(.RamFunc*) /* .RamFunc* sections */
|
||||
|
||||
. = ALIGN(4);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
|
||||
} >RAM AT> FLASH
|
||||
|
||||
/* Uninitialized data section into "RAM" Ram type memory */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss section */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
|
||||
|
||||
RW_NONCACHEABLE :
|
||||
{
|
||||
__NONCACHEABLEBUFFER_BEGIN = .;/* create symbol for start of section */
|
||||
KEEP(*(noncacheable_buffer))
|
||||
__NONCACHEABLEBUFFER_END = .; /* create symbol for start of section */
|
||||
} >RAM_NONCACHEABLEBUFFER
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(8);
|
||||
} >DTCM
|
||||
|
||||
/* Remove information from the compiler libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
|
|
@ -1,750 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file startup_stm32h7s7xx.s
|
||||
* @author MCD Application Team
|
||||
* @brief STM32H7R3xx Devices vector table for GCC toolchain.
|
||||
* This module performs:
|
||||
* - Set the initial SP
|
||||
* - Set the initial PC == Reset_Handler,
|
||||
* - Set the vector table entries with the exceptions ISR address
|
||||
* - Branches to main in the C library (which eventually
|
||||
* calls main()).
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m7
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global g_pfnVectors
|
||||
.global Default_Handler
|
||||
|
||||
/* start address for the initialization values of the .data section.
|
||||
defined in linker script */
|
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */
|
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */
|
||||
.word _edata
|
||||
/* start address for the .bss section. defined in linker script */
|
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */
|
||||
.word _ebss
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor first
|
||||
* starts execution following a reset event. Only the absolutely
|
||||
* necessary set is performed, after which the application
|
||||
* supplied main() routine is called.
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
ldr r0, =_estack
|
||||
mov sp, r0 /* set stack pointer */
|
||||
/* Call the clock system initialization function.*/
|
||||
bl SystemInit
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
ldr r0, =_sdata
|
||||
ldr r1, =_edata
|
||||
ldr r2, =_sidata
|
||||
movs r3, #0
|
||||
b LoopCopyDataInit
|
||||
|
||||
CopyDataInit:
|
||||
ldr r4, [r2, r3]
|
||||
str r4, [r0, r3]
|
||||
adds r3, r3, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
adds r4, r0, r3
|
||||
cmp r4, r1
|
||||
bcc CopyDataInit
|
||||
|
||||
/* Zero fill the bss segment. */
|
||||
ldr r2, =_sbss
|
||||
ldr r4, =_ebss
|
||||
movs r3, #0
|
||||
b LoopFillZerobss
|
||||
|
||||
FillZerobss:
|
||||
str r3, [r2]
|
||||
adds r2, r2, #4
|
||||
|
||||
LoopFillZerobss:
|
||||
cmp r2, r4
|
||||
bcc FillZerobss
|
||||
|
||||
/* Call static constructors */
|
||||
bl __libc_init_array
|
||||
/* Call the application's entry point.*/
|
||||
bl main
|
||||
|
||||
LoopForever:
|
||||
b LoopForever
|
||||
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||
* the system state for examination by a debugger.
|
||||
*
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* The STM32H7R3xx vector table. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*
|
||||
******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
g_pfnVectors:
|
||||
.word _estack
|
||||
.word Reset_Handler
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word MemManage_Handler
|
||||
.word BusFault_Handler
|
||||
.word UsageFault_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word SVC_Handler
|
||||
.word DebugMon_Handler
|
||||
.word 0
|
||||
.word PendSV_Handler
|
||||
.word SysTick_Handler
|
||||
/* External Interrupts */
|
||||
.word PVD_PVM_IRQHandler /* PVD/PVM through EXTI Line detection */
|
||||
.word 0 /* Reserved */
|
||||
.word DTS_IRQHandler /* Digital Temperature Sensor */
|
||||
.word IWDG_IRQHandler /* Internal Watchdog */
|
||||
.word WWDG_IRQHandler /* Window Watchdog */
|
||||
.word RCC_IRQHandler /* RCC global interrupts through EXTI Line detection */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word FLASH_IRQHandler /* FLASH interrupts */
|
||||
.word RAMECC_IRQHandler /* RAMECC interruptsflags */
|
||||
.word FPU_IRQHandler /* FPU */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word TAMP_IRQHandler /* Tamper and TimeStamp interrupts */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word EXTI0_IRQHandler /* EXTI Line0 */
|
||||
.word EXTI1_IRQHandler /* EXTI Line1 */
|
||||
.word EXTI2_IRQHandler /* EXTI Line2 */
|
||||
.word EXTI3_IRQHandler /* EXTI Line3 */
|
||||
.word EXTI4_IRQHandler /* EXTI Line4 */
|
||||
.word EXTI5_IRQHandler /* EXTI Line5 */
|
||||
.word EXTI6_IRQHandler /* EXTI Line6 */
|
||||
.word EXTI7_IRQHandler /* EXTI Line7 */
|
||||
.word EXTI8_IRQHandler /* EXTI Line8 */
|
||||
.word EXTI9_IRQHandler /* EXTI Line9 */
|
||||
.word EXTI10_IRQHandler /* EXTI Line10 */
|
||||
.word EXTI11_IRQHandler /* EXTI Line11 */
|
||||
.word EXTI12_IRQHandler /* EXTI Line12 */
|
||||
.word EXTI13_IRQHandler /* EXTI Line13 */
|
||||
.word EXTI14_IRQHandler /* EXTI Line14 */
|
||||
.word EXTI15_IRQHandler /* EXTI Line15 */
|
||||
.word RTC_IRQHandler /* RTC wakeup and alarm interrupts */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word PKA_IRQHandler /* PKA */
|
||||
.word HASH_IRQHandler /* HASH */
|
||||
.word RNG_IRQHandler /* RNG */
|
||||
.word ADC1_2_IRQHandler /* ADC1 & ADC2 */
|
||||
.word GPDMA1_Channel0_IRQHandler /* GPDMA1 Channel 0 */
|
||||
.word GPDMA1_Channel1_IRQHandler /* GPDMA1 Channel 1 */
|
||||
.word GPDMA1_Channel2_IRQHandler /* GPDMA1 Channel 2 */
|
||||
.word GPDMA1_Channel3_IRQHandler /* GPDMA1 Channel 3 */
|
||||
.word GPDMA1_Channel4_IRQHandler /* GPDMA1 Channel 4 */
|
||||
.word GPDMA1_Channel5_IRQHandler /* GPDMA1 Channel 5 */
|
||||
.word GPDMA1_Channel6_IRQHandler /* GPDMA1 Channel 6 */
|
||||
.word GPDMA1_Channel7_IRQHandler /* GPDMA1 Channel 7 */
|
||||
.word TIM1_BRK_IRQHandler /* TIM1 Break */
|
||||
.word TIM1_UP_IRQHandler /* TIM1 Update */
|
||||
.word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */
|
||||
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
|
||||
.word TIM2_IRQHandler /* TIM2 */
|
||||
.word TIM3_IRQHandler /* TIM3 */
|
||||
.word TIM4_IRQHandler /* TIM4 */
|
||||
.word TIM5_IRQHandler /* TIM5 */
|
||||
.word TIM6_IRQHandler /* TIM6 */
|
||||
.word TIM7_IRQHandler /* TIM7 */
|
||||
.word TIM9_IRQHandler /* TIM9 */
|
||||
.word SPI1_IRQHandler /* SPI1 */
|
||||
.word SPI2_IRQHandler /* SPI2 */
|
||||
.word SPI3_IRQHandler /* SPI3 */
|
||||
.word SPI4_IRQHandler /* SPI4 */
|
||||
.word SPI5_IRQHandler /* SPI5 */
|
||||
.word SPI6_IRQHandler /* SPI6 */
|
||||
.word HPDMA1_Channel0_IRQHandler /* HPDMA1 Channel 0 */
|
||||
.word HPDMA1_Channel1_IRQHandler /* HPDMA1 Channel 1 */
|
||||
.word HPDMA1_Channel2_IRQHandler /* HPDMA1 Channel 2 */
|
||||
.word HPDMA1_Channel3_IRQHandler /* HPDMA1 Channel 3 */
|
||||
.word HPDMA1_Channel4_IRQHandler /* HPDMA1 Channel 4 */
|
||||
.word HPDMA1_Channel5_IRQHandler /* HPDMA1 Channel 5 */
|
||||
.word HPDMA1_Channel6_IRQHandler /* HPDMA1 Channel 6 */
|
||||
.word HPDMA1_Channel7_IRQHandler /* HPDMA1 Channel 7 */
|
||||
.word SAI1_A_IRQHandler /* Serial Audio Interface 1 block A */
|
||||
.word SAI1_B_IRQHandler /* Serial Audio Interface 1 block B */
|
||||
.word SAI2_A_IRQHandler /* Serial Audio Interface 2 block A */
|
||||
.word SAI2_B_IRQHandler /* Serial Audio Interface 2 block B */
|
||||
.word I2C1_EV_IRQHandler /* I2C1 Event */
|
||||
.word I2C1_ER_IRQHandler /* I2C1 Error */
|
||||
.word I2C2_EV_IRQHandler /* I2C2 Event */
|
||||
.word I2C2_ER_IRQHandler /* I2C2 Error */
|
||||
.word I2C3_EV_IRQHandler /* I2C3 Event */
|
||||
.word I2C3_ER_IRQHandler /* I2C3 Error */
|
||||
.word USART1_IRQHandler /* USART1 */
|
||||
.word USART2_IRQHandler /* USART2 */
|
||||
.word USART3_IRQHandler /* USART3 */
|
||||
.word UART4_IRQHandler /* UART4 */
|
||||
.word UART5_IRQHandler /* UART5 */
|
||||
.word UART7_IRQHandler /* UART7 */
|
||||
.word UART8_IRQHandler /* UART8 */
|
||||
.word I3C1_EV_IRQHandler /* I3C1 Event */
|
||||
.word I3C1_ER_IRQHandler /* I3C1 Error */
|
||||
.word OTG_HS_IRQHandler /* USB OTG HS */
|
||||
.word ETH_IRQHandler /* Ethernet */
|
||||
.word CORDIC_IRQHandler /* CORDIC */
|
||||
.word GFXTIM_IRQHandler /* GFXTIM */
|
||||
.word DCMIPP_IRQHandler /* DCMIPP */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word DMA2D_IRQHandler /* DMA2D */
|
||||
.word JPEG_IRQHandler /* JPEG */
|
||||
.word GFXMMU_IRQHandler /* GFXMMU */
|
||||
.word I3C1_WKUP_IRQHandler /* I3C1 wakeup */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word XSPI1_IRQHandler /* XSPI1 */
|
||||
.word XSPI2_IRQHandler /* XSPI2 */
|
||||
.word FMC_IRQHandler /* FMC */
|
||||
.word SDMMC1_IRQHandler /* SDMMC1 */
|
||||
.word SDMMC2_IRQHandler /* SDMMC2 */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word OTG_FS_IRQHandler /* USB OTG FS */
|
||||
.word TIM12_IRQHandler /* TIM12 */
|
||||
.word TIM13_IRQHandler /* TIM13 */
|
||||
.word TIM14_IRQHandler /* TIM14 */
|
||||
.word TIM15_IRQHandler /* TIM15 */
|
||||
.word TIM16_IRQHandler /* TIM16 */
|
||||
.word TIM17_IRQHandler /* TIM17 */
|
||||
.word LPTIM1_IRQHandler /* LP TIM1 */
|
||||
.word LPTIM2_IRQHandler /* LP TIM2 */
|
||||
.word LPTIM3_IRQHandler /* LP TIM3 */
|
||||
.word LPTIM4_IRQHandler /* LP TIM4 */
|
||||
.word LPTIM5_IRQHandler /* LP TIM5 */
|
||||
.word SPDIF_RX_IRQHandler /* SPDIF_RX */
|
||||
.word MDIOS_IRQHandler /* MDIOS */
|
||||
.word ADF1_FLT0_IRQHandler /* ADF1 Filter 0 */
|
||||
.word CRS_IRQHandler /* CRS */
|
||||
.word UCPD1_IRQHandler /* UCPD1 */
|
||||
.word CEC_IRQHandler /* HDMI_CEC */
|
||||
.word PSSI_IRQHandler /* PSSI */
|
||||
.word LPUART1_IRQHandler /* LP UART1 */
|
||||
.word WAKEUP_PIN_IRQHandler /* Wake-up pins interrupt */
|
||||
.word GPDMA1_Channel8_IRQHandler /* GPDMA1 Channel 8 */
|
||||
.word GPDMA1_Channel9_IRQHandler /* GPDMA1 Channel 9 */
|
||||
.word GPDMA1_Channel10_IRQHandler /* GPDMA1 Channel 10 */
|
||||
.word GPDMA1_Channel11_IRQHandler /* GPDMA1 Channel 11 */
|
||||
.word GPDMA1_Channel12_IRQHandler /* GPDMA1 Channel 12 */
|
||||
.word GPDMA1_Channel13_IRQHandler /* GPDMA1 Channel 13 */
|
||||
.word GPDMA1_Channel14_IRQHandler /* GPDMA1 Channel 14 */
|
||||
.word GPDMA1_Channel15_IRQHandler /* GPDMA1 Channel 15 */
|
||||
.word HPDMA1_Channel8_IRQHandler /* HPDMA1 Channel 8 */
|
||||
.word HPDMA1_Channel9_IRQHandler /* HPDMA1 Channel 9 */
|
||||
.word HPDMA1_Channel10_IRQHandler /* HPDMA1 Channel 10 */
|
||||
.word HPDMA1_Channel11_IRQHandler /* HPDMA1 Channel 11 */
|
||||
.word HPDMA1_Channel12_IRQHandler /* HPDMA1 Channel 12 */
|
||||
.word HPDMA1_Channel13_IRQHandler /* HPDMA1 Channel 13 */
|
||||
.word HPDMA1_Channel14_IRQHandler /* HPDMA1 Channel 14 */
|
||||
.word HPDMA1_Channel15_IRQHandler /* HPDMA1 Channel 15 */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word FDCAN1_IT0_IRQHandler /* FDCAN1 Interrupt 0 */
|
||||
.word FDCAN1_IT1_IRQHandler /* FDCAN1 Interrupt 1 */
|
||||
.word FDCAN2_IT0_IRQHandler /* FDCAN2 Interrupt 0 */
|
||||
.word FDCAN2_IT1_IRQHandler /* FDCAN2 Interrupt 1 */
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak PVD_PVM_IRQHandler
|
||||
.thumb_set PVD_PVM_IRQHandler,Default_Handler
|
||||
|
||||
.weak DTS_IRQHandler
|
||||
.thumb_set DTS_IRQHandler,Default_Handler
|
||||
|
||||
.weak IWDG_IRQHandler
|
||||
.thumb_set IWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak WWDG_IRQHandler
|
||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_IRQHandler
|
||||
.thumb_set RCC_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak RAMECC_IRQHandler
|
||||
.thumb_set RAMECC_IRQHandler,Default_Handler
|
||||
|
||||
.weak FPU_IRQHandler
|
||||
.thumb_set FPU_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMP_IRQHandler
|
||||
.thumb_set TAMP_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI5_IRQHandler
|
||||
.thumb_set EXTI5_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI6_IRQHandler
|
||||
.thumb_set EXTI6_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI7_IRQHandler
|
||||
.thumb_set EXTI7_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI8_IRQHandler
|
||||
.thumb_set EXTI8_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI9_IRQHandler
|
||||
.thumb_set EXTI9_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI10_IRQHandler
|
||||
.thumb_set EXTI10_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI11_IRQHandler
|
||||
.thumb_set EXTI11_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI12_IRQHandler
|
||||
.thumb_set EXTI12_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI13_IRQHandler
|
||||
.thumb_set EXTI13_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI14_IRQHandler
|
||||
.thumb_set EXTI14_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI15_IRQHandler
|
||||
.thumb_set EXTI15_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_IRQHandler
|
||||
.thumb_set RTC_IRQHandler,Default_Handler
|
||||
|
||||
.weak PKA_IRQHandler
|
||||
.thumb_set PKA_IRQHandler,Default_Handler
|
||||
|
||||
.weak HASH_IRQHandler
|
||||
.thumb_set HASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak RNG_IRQHandler
|
||||
.thumb_set RNG_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC1_2_IRQHandler
|
||||
.thumb_set ADC1_2_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel0_IRQHandler
|
||||
.thumb_set GPDMA1_Channel0_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel1_IRQHandler
|
||||
.thumb_set GPDMA1_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel2_IRQHandler
|
||||
.thumb_set GPDMA1_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel3_IRQHandler
|
||||
.thumb_set GPDMA1_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel4_IRQHandler
|
||||
.thumb_set GPDMA1_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel5_IRQHandler
|
||||
.thumb_set GPDMA1_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel6_IRQHandler
|
||||
.thumb_set GPDMA1_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel7_IRQHandler
|
||||
.thumb_set GPDMA1_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_BRK_IRQHandler
|
||||
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_UP_IRQHandler
|
||||
.thumb_set TIM1_UP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_TRG_COM_IRQHandler
|
||||
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_CC_IRQHandler
|
||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM2_IRQHandler
|
||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM3_IRQHandler
|
||||
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM4_IRQHandler
|
||||
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM5_IRQHandler
|
||||
.thumb_set TIM5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM6_IRQHandler
|
||||
.thumb_set TIM6_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM7_IRQHandler
|
||||
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM9_IRQHandler
|
||||
.thumb_set TIM9_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI3_IRQHandler
|
||||
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI4_IRQHandler
|
||||
.thumb_set SPI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI5_IRQHandler
|
||||
.thumb_set SPI5_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI6_IRQHandler
|
||||
.thumb_set SPI6_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel0_IRQHandler
|
||||
.thumb_set HPDMA1_Channel0_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel1_IRQHandler
|
||||
.thumb_set HPDMA1_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel2_IRQHandler
|
||||
.thumb_set HPDMA1_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel3_IRQHandler
|
||||
.thumb_set HPDMA1_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel4_IRQHandler
|
||||
.thumb_set HPDMA1_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel5_IRQHandler
|
||||
.thumb_set HPDMA1_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel6_IRQHandler
|
||||
.thumb_set HPDMA1_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel7_IRQHandler
|
||||
.thumb_set HPDMA1_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI1_A_IRQHandler
|
||||
.thumb_set SAI1_A_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI1_B_IRQHandler
|
||||
.thumb_set SAI1_B_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI2_A_IRQHandler
|
||||
.thumb_set SAI2_A_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI2_B_IRQHandler
|
||||
.thumb_set SAI2_B_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_EV_IRQHandler
|
||||
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_ER_IRQHandler
|
||||
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_EV_IRQHandler
|
||||
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_ER_IRQHandler
|
||||
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART2_IRQHandler
|
||||
.thumb_set USART2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART3_IRQHandler
|
||||
.thumb_set USART3_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART4_IRQHandler
|
||||
.thumb_set UART4_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART5_IRQHandler
|
||||
.thumb_set UART5_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART7_IRQHandler
|
||||
.thumb_set UART7_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART8_IRQHandler
|
||||
.thumb_set UART8_IRQHandler,Default_Handler
|
||||
|
||||
.weak I3C1_EV_IRQHandler
|
||||
.thumb_set I3C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I3C1_ER_IRQHandler
|
||||
.thumb_set I3C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_IRQHandler
|
||||
.thumb_set OTG_HS_IRQHandler,Default_Handler
|
||||
|
||||
.weak ETH_IRQHandler
|
||||
.thumb_set ETH_IRQHandler,Default_Handler
|
||||
|
||||
.weak CORDIC_IRQHandler
|
||||
.thumb_set CORDIC_IRQHandler,Default_Handler
|
||||
|
||||
.weak GFXTIM_IRQHandler
|
||||
.thumb_set GFXTIM_IRQHandler,Default_Handler
|
||||
|
||||
.weak DCMIPP_IRQHandler
|
||||
.thumb_set DCMIPP_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2D_IRQHandler
|
||||
.thumb_set DMA2D_IRQHandler,Default_Handler
|
||||
|
||||
.weak JPEG_IRQHandler
|
||||
.thumb_set JPEG_IRQHandler,Default_Handler
|
||||
|
||||
.weak GFXMMU_IRQHandler
|
||||
.thumb_set GFXMMU_IRQHandler,Default_Handler
|
||||
|
||||
.weak I3C1_WKUP_IRQHandler
|
||||
.thumb_set I3C1_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak XSPI1_IRQHandler
|
||||
.thumb_set XSPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak XSPI2_IRQHandler
|
||||
.thumb_set XSPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak FMC_IRQHandler
|
||||
.thumb_set FMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDMMC1_IRQHandler
|
||||
.thumb_set SDMMC1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDMMC2_IRQHandler
|
||||
.thumb_set SDMMC2_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_FS_IRQHandler
|
||||
.thumb_set OTG_FS_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM12_IRQHandler
|
||||
.thumb_set TIM12_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM13_IRQHandler
|
||||
.thumb_set TIM13_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM14_IRQHandler
|
||||
.thumb_set TIM14_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM15_IRQHandler
|
||||
.thumb_set TIM15_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM16_IRQHandler
|
||||
.thumb_set TIM16_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM17_IRQHandler
|
||||
.thumb_set TIM17_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM1_IRQHandler
|
||||
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM2_IRQHandler
|
||||
.thumb_set LPTIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM3_IRQHandler
|
||||
.thumb_set LPTIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM4_IRQHandler
|
||||
.thumb_set LPTIM4_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM5_IRQHandler
|
||||
.thumb_set LPTIM5_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPDIF_RX_IRQHandler
|
||||
.thumb_set SPDIF_RX_IRQHandler,Default_Handler
|
||||
|
||||
.weak MDIOS_IRQHandler
|
||||
.thumb_set MDIOS_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADF1_FLT0_IRQHandler
|
||||
.thumb_set ADF1_FLT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak CRS_IRQHandler
|
||||
.thumb_set CRS_IRQHandler,Default_Handler
|
||||
|
||||
.weak UCPD1_IRQHandler
|
||||
.thumb_set UCPD1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CEC_IRQHandler
|
||||
.thumb_set CEC_IRQHandler,Default_Handler
|
||||
|
||||
.weak PSSI_IRQHandler
|
||||
.thumb_set PSSI_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPUART1_IRQHandler
|
||||
.thumb_set LPUART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak WAKEUP_PIN_IRQHandler
|
||||
.thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel8_IRQHandler
|
||||
.thumb_set GPDMA1_Channel8_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel9_IRQHandler
|
||||
.thumb_set GPDMA1_Channel9_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel10_IRQHandler
|
||||
.thumb_set GPDMA1_Channel10_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel11_IRQHandler
|
||||
.thumb_set GPDMA1_Channel11_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel12_IRQHandler
|
||||
.thumb_set GPDMA1_Channel12_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel13_IRQHandler
|
||||
.thumb_set GPDMA1_Channel13_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel14_IRQHandler
|
||||
.thumb_set GPDMA1_Channel14_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel15_IRQHandler
|
||||
.thumb_set GPDMA1_Channel15_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel8_IRQHandler
|
||||
.thumb_set HPDMA1_Channel8_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel9_IRQHandler
|
||||
.thumb_set HPDMA1_Channel9_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel10_IRQHandler
|
||||
.thumb_set HPDMA1_Channel10_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel11_IRQHandler
|
||||
.thumb_set HPDMA1_Channel11_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel12_IRQHandler
|
||||
.thumb_set HPDMA1_Channel12_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel13_IRQHandler
|
||||
.thumb_set HPDMA1_Channel13_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel14_IRQHandler
|
||||
.thumb_set HPDMA1_Channel14_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel15_IRQHandler
|
||||
.thumb_set HPDMA1_Channel15_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN1_IT0_IRQHandler
|
||||
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN1_IT1_IRQHandler
|
||||
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN2_IT0_IRQHandler
|
||||
.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN2_IT1_IRQHandler
|
||||
.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SystemInit
|
||||
|
|
@ -1,765 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file startup_stm32h7s7xx.s
|
||||
* @author MCD Application Team
|
||||
* @brief STM32H7R7xx Devices vector table for GCC toolchain.
|
||||
* This module performs:
|
||||
* - Set the initial SP
|
||||
* - Set the initial PC == Reset_Handler,
|
||||
* - Set the vector table entries with the exceptions ISR address
|
||||
* - Branches to main in the C library (which eventually
|
||||
* calls main()).
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m7
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global g_pfnVectors
|
||||
.global Default_Handler
|
||||
|
||||
/* start address for the initialization values of the .data section.
|
||||
defined in linker script */
|
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */
|
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */
|
||||
.word _edata
|
||||
/* start address for the .bss section. defined in linker script */
|
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */
|
||||
.word _ebss
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor first
|
||||
* starts execution following a reset event. Only the absolutely
|
||||
* necessary set is performed, after which the application
|
||||
* supplied main() routine is called.
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
ldr r0, =_estack
|
||||
mov sp, r0 /* set stack pointer */
|
||||
/* Call the clock system initialization function.*/
|
||||
bl SystemInit
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
ldr r0, =_sdata
|
||||
ldr r1, =_edata
|
||||
ldr r2, =_sidata
|
||||
movs r3, #0
|
||||
b LoopCopyDataInit
|
||||
|
||||
CopyDataInit:
|
||||
ldr r4, [r2, r3]
|
||||
str r4, [r0, r3]
|
||||
adds r3, r3, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
adds r4, r0, r3
|
||||
cmp r4, r1
|
||||
bcc CopyDataInit
|
||||
|
||||
/* Zero fill the bss segment. */
|
||||
ldr r2, =_sbss
|
||||
ldr r4, =_ebss
|
||||
movs r3, #0
|
||||
b LoopFillZerobss
|
||||
|
||||
FillZerobss:
|
||||
str r3, [r2]
|
||||
adds r2, r2, #4
|
||||
|
||||
LoopFillZerobss:
|
||||
cmp r2, r4
|
||||
bcc FillZerobss
|
||||
|
||||
/* Call static constructors */
|
||||
bl __libc_init_array
|
||||
/* Call the application's entry point.*/
|
||||
bl main
|
||||
|
||||
LoopForever:
|
||||
b LoopForever
|
||||
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||
* the system state for examination by a debugger.
|
||||
*
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* The STM32H7R7xx vector table. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*
|
||||
******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
g_pfnVectors:
|
||||
.word _estack
|
||||
.word Reset_Handler
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word MemManage_Handler
|
||||
.word BusFault_Handler
|
||||
.word UsageFault_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word SVC_Handler
|
||||
.word DebugMon_Handler
|
||||
.word 0
|
||||
.word PendSV_Handler
|
||||
.word SysTick_Handler
|
||||
/* External Interrupts */
|
||||
.word PVD_PVM_IRQHandler /* PVD/PVM through EXTI Line detection */
|
||||
.word 0 /* Reserved */
|
||||
.word DTS_IRQHandler /* Digital Temperature Sensor */
|
||||
.word IWDG_IRQHandler /* Internal Watchdog */
|
||||
.word WWDG_IRQHandler /* Window Watchdog */
|
||||
.word RCC_IRQHandler /* RCC global interrupts through EXTI Line detection */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word FLASH_IRQHandler /* FLASH interrupts */
|
||||
.word RAMECC_IRQHandler /* RAMECC interrupts */
|
||||
.word FPU_IRQHandler /* FPU */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word TAMP_IRQHandler /* Tamper and TimeStamp interrupts */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word EXTI0_IRQHandler /* EXTI Line0 */
|
||||
.word EXTI1_IRQHandler /* EXTI Line1 */
|
||||
.word EXTI2_IRQHandler /* EXTI Line2 */
|
||||
.word EXTI3_IRQHandler /* EXTI Line3 */
|
||||
.word EXTI4_IRQHandler /* EXTI Line4 */
|
||||
.word EXTI5_IRQHandler /* EXTI Line5 */
|
||||
.word EXTI6_IRQHandler /* EXTI Line6 */
|
||||
.word EXTI7_IRQHandler /* EXTI Line7 */
|
||||
.word EXTI8_IRQHandler /* EXTI Line8 */
|
||||
.word EXTI9_IRQHandler /* EXTI Line9 */
|
||||
.word EXTI10_IRQHandler /* EXTI Line10 */
|
||||
.word EXTI11_IRQHandler /* EXTI Line11 */
|
||||
.word EXTI12_IRQHandler /* EXTI Line12 */
|
||||
.word EXTI13_IRQHandler /* EXTI Line13 */
|
||||
.word EXTI14_IRQHandler /* EXTI Line14 */
|
||||
.word EXTI15_IRQHandler /* EXTI Line15 */
|
||||
.word RTC_IRQHandler /* RTC wakeup and alarm interrupts */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word PKA_IRQHandler /* PKA */
|
||||
.word HASH_IRQHandler /* HASH */
|
||||
.word RNG_IRQHandler /* RNG */
|
||||
.word ADC1_2_IRQHandler /* ADC1 & ADC2 */
|
||||
.word GPDMA1_Channel0_IRQHandler /* GPDMA1 Channel 0 */
|
||||
.word GPDMA1_Channel1_IRQHandler /* GPDMA1 Channel 1 */
|
||||
.word GPDMA1_Channel2_IRQHandler /* GPDMA1 Channel 2 */
|
||||
.word GPDMA1_Channel3_IRQHandler /* GPDMA1 Channel 3 */
|
||||
.word GPDMA1_Channel4_IRQHandler /* GPDMA1 Channel 4 */
|
||||
.word GPDMA1_Channel5_IRQHandler /* GPDMA1 Channel 5 */
|
||||
.word GPDMA1_Channel6_IRQHandler /* GPDMA1 Channel 6 */
|
||||
.word GPDMA1_Channel7_IRQHandler /* GPDMA1 Channel 7 */
|
||||
.word TIM1_BRK_IRQHandler /* TIM1 Break */
|
||||
.word TIM1_UP_IRQHandler /* TIM1 Update */
|
||||
.word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */
|
||||
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
|
||||
.word TIM2_IRQHandler /* TIM2 */
|
||||
.word TIM3_IRQHandler /* TIM3 */
|
||||
.word TIM4_IRQHandler /* TIM4 */
|
||||
.word TIM5_IRQHandler /* TIM5 */
|
||||
.word TIM6_IRQHandler /* TIM6 */
|
||||
.word TIM7_IRQHandler /* TIM7 */
|
||||
.word TIM9_IRQHandler /* TIM9 */
|
||||
.word SPI1_IRQHandler /* SPI1 */
|
||||
.word SPI2_IRQHandler /* SPI2 */
|
||||
.word SPI3_IRQHandler /* SPI3 */
|
||||
.word SPI4_IRQHandler /* SPI4 */
|
||||
.word SPI5_IRQHandler /* SPI5 */
|
||||
.word SPI6_IRQHandler /* SPI6 */
|
||||
.word HPDMA1_Channel0_IRQHandler /* HPDMA1 Channel 0 */
|
||||
.word HPDMA1_Channel1_IRQHandler /* HPDMA1 Channel 1 */
|
||||
.word HPDMA1_Channel2_IRQHandler /* HPDMA1 Channel 2 */
|
||||
.word HPDMA1_Channel3_IRQHandler /* HPDMA1 Channel 3 */
|
||||
.word HPDMA1_Channel4_IRQHandler /* HPDMA1 Channel 4 */
|
||||
.word HPDMA1_Channel5_IRQHandler /* HPDMA1 Channel 5 */
|
||||
.word HPDMA1_Channel6_IRQHandler /* HPDMA1 Channel 6 */
|
||||
.word HPDMA1_Channel7_IRQHandler /* HPDMA1 Channel 7 */
|
||||
.word SAI1_A_IRQHandler /* Serial Audio Interface 1 block A */
|
||||
.word SAI1_B_IRQHandler /* Serial Audio Interface 1 block B */
|
||||
.word SAI2_A_IRQHandler /* Serial Audio Interface 2 block A */
|
||||
.word SAI2_B_IRQHandler /* Serial Audio Interface 2 block B */
|
||||
.word I2C1_EV_IRQHandler /* I2C1 Event */
|
||||
.word I2C1_ER_IRQHandler /* I2C1 Error */
|
||||
.word I2C2_EV_IRQHandler /* I2C2 Event */
|
||||
.word I2C2_ER_IRQHandler /* I2C2 Error */
|
||||
.word I2C3_EV_IRQHandler /* I2C3 Event */
|
||||
.word I2C3_ER_IRQHandler /* I2C3 Error */
|
||||
.word USART1_IRQHandler /* USART1 */
|
||||
.word USART2_IRQHandler /* USART2 */
|
||||
.word USART3_IRQHandler /* USART3 */
|
||||
.word UART4_IRQHandler /* UART4 */
|
||||
.word UART5_IRQHandler /* UART5 */
|
||||
.word UART7_IRQHandler /* UART7 */
|
||||
.word UART8_IRQHandler /* UART8 */
|
||||
.word I3C1_EV_IRQHandler /* I3C1 Event */
|
||||
.word I3C1_ER_IRQHandler /* I3C1 Error */
|
||||
.word OTG_HS_IRQHandler /* USB OTG HS */
|
||||
.word ETH_IRQHandler /* Ethernet */
|
||||
.word CORDIC_IRQHandler /* CORDIC */
|
||||
.word GFXTIM_IRQHandler /* GFXTIM */
|
||||
.word DCMIPP_IRQHandler /* DCMIPP */
|
||||
.word LTDC_IRQHandler /* LTDC */
|
||||
.word LTDC_ER_IRQHandler /* LTDC error */
|
||||
.word DMA2D_IRQHandler /* DMA2D */
|
||||
.word JPEG_IRQHandler /* JPEG */
|
||||
.word GFXMMU_IRQHandler /* GFXMMU */
|
||||
.word I3C1_WKUP_IRQHandler /* I3C1 wakeup */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word XSPI1_IRQHandler /* XSPI1 */
|
||||
.word XSPI2_IRQHandler /* XSPI2 */
|
||||
.word FMC_IRQHandler /* FMC */
|
||||
.word SDMMC1_IRQHandler /* SDMMC1 */
|
||||
.word SDMMC2_IRQHandler /* SDMMC2 */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word OTG_FS_IRQHandler /* USB OTG FS */
|
||||
.word TIM12_IRQHandler /* TIM12 */
|
||||
.word TIM13_IRQHandler /* TIM13 */
|
||||
.word TIM14_IRQHandler /* TIM14 */
|
||||
.word TIM15_IRQHandler /* TIM15 */
|
||||
.word TIM16_IRQHandler /* TIM16 */
|
||||
.word TIM17_IRQHandler /* TIM17 */
|
||||
.word LPTIM1_IRQHandler /* LP TIM1 */
|
||||
.word LPTIM2_IRQHandler /* LP TIM2 */
|
||||
.word LPTIM3_IRQHandler /* LP TIM3 */
|
||||
.word LPTIM4_IRQHandler /* LP TIM4 */
|
||||
.word LPTIM5_IRQHandler /* LP TIM5 */
|
||||
.word SPDIF_RX_IRQHandler /* SPDIF_RX */
|
||||
.word MDIOS_IRQHandler /* MDIOS */
|
||||
.word ADF1_FLT0_IRQHandler /* ADF1 Filter 0 */
|
||||
.word CRS_IRQHandler /* CRS */
|
||||
.word UCPD1_IRQHandler /* UCPD1 */
|
||||
.word CEC_IRQHandler /* HDMI_CEC */
|
||||
.word PSSI_IRQHandler /* PSSI */
|
||||
.word LPUART1_IRQHandler /* LP UART1 */
|
||||
.word WAKEUP_PIN_IRQHandler /* Wake-up pins interrupt */
|
||||
.word GPDMA1_Channel8_IRQHandler /* GPDMA1 Channel 8 */
|
||||
.word GPDMA1_Channel9_IRQHandler /* GPDMA1 Channel 9 */
|
||||
.word GPDMA1_Channel10_IRQHandler /* GPDMA1 Channel 10 */
|
||||
.word GPDMA1_Channel11_IRQHandler /* GPDMA1 Channel 11 */
|
||||
.word GPDMA1_Channel12_IRQHandler /* GPDMA1 Channel 12 */
|
||||
.word GPDMA1_Channel13_IRQHandler /* GPDMA1 Channel 13 */
|
||||
.word GPDMA1_Channel14_IRQHandler /* GPDMA1 Channel 14 */
|
||||
.word GPDMA1_Channel15_IRQHandler /* GPDMA1 Channel 15 */
|
||||
.word HPDMA1_Channel8_IRQHandler /* HPDMA1 Channel 8 */
|
||||
.word HPDMA1_Channel9_IRQHandler /* HPDMA1 Channel 9 */
|
||||
.word HPDMA1_Channel10_IRQHandler /* HPDMA1 Channel 10 */
|
||||
.word HPDMA1_Channel11_IRQHandler /* HPDMA1 Channel 11 */
|
||||
.word HPDMA1_Channel12_IRQHandler /* HPDMA1 Channel 12 */
|
||||
.word HPDMA1_Channel13_IRQHandler /* HPDMA1 Channel 13 */
|
||||
.word HPDMA1_Channel14_IRQHandler /* HPDMA1 Channel 14 */
|
||||
.word HPDMA1_Channel15_IRQHandler /* HPDMA1 Channel 15 */
|
||||
.word GPU2D_IRQHandler /* GPU2D */
|
||||
.word GPU2D_ER_IRQHandler /* GPU2D error */
|
||||
.word ICACHE_IRQHandler /* ICACHE */
|
||||
.word FDCAN1_IT0_IRQHandler /* FDCAN1 Interrupt 0 */
|
||||
.word FDCAN1_IT1_IRQHandler /* FDCAN1 Interrupt 1 */
|
||||
.word FDCAN2_IT0_IRQHandler /* FDCAN2 Interrupt 0 */
|
||||
.word FDCAN2_IT1_IRQHandler /* FDCAN2 Interrupt 1 */
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak PVD_PVM_IRQHandler
|
||||
.thumb_set PVD_PVM_IRQHandler,Default_Handler
|
||||
|
||||
.weak DTS_IRQHandler
|
||||
.thumb_set DTS_IRQHandler,Default_Handler
|
||||
|
||||
.weak IWDG_IRQHandler
|
||||
.thumb_set IWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak WWDG_IRQHandler
|
||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_IRQHandler
|
||||
.thumb_set RCC_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak RAMECC_IRQHandler
|
||||
.thumb_set RAMECC_IRQHandler,Default_Handler
|
||||
|
||||
.weak FPU_IRQHandler
|
||||
.thumb_set FPU_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMP_IRQHandler
|
||||
.thumb_set TAMP_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI5_IRQHandler
|
||||
.thumb_set EXTI5_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI6_IRQHandler
|
||||
.thumb_set EXTI6_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI7_IRQHandler
|
||||
.thumb_set EXTI7_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI8_IRQHandler
|
||||
.thumb_set EXTI8_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI9_IRQHandler
|
||||
.thumb_set EXTI9_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI10_IRQHandler
|
||||
.thumb_set EXTI10_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI11_IRQHandler
|
||||
.thumb_set EXTI11_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI12_IRQHandler
|
||||
.thumb_set EXTI12_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI13_IRQHandler
|
||||
.thumb_set EXTI13_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI14_IRQHandler
|
||||
.thumb_set EXTI14_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI15_IRQHandler
|
||||
.thumb_set EXTI15_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_IRQHandler
|
||||
.thumb_set RTC_IRQHandler,Default_Handler
|
||||
|
||||
.weak PKA_IRQHandler
|
||||
.thumb_set PKA_IRQHandler,Default_Handler
|
||||
|
||||
.weak HASH_IRQHandler
|
||||
.thumb_set HASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak RNG_IRQHandler
|
||||
.thumb_set RNG_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC1_2_IRQHandler
|
||||
.thumb_set ADC1_2_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel0_IRQHandler
|
||||
.thumb_set GPDMA1_Channel0_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel1_IRQHandler
|
||||
.thumb_set GPDMA1_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel2_IRQHandler
|
||||
.thumb_set GPDMA1_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel3_IRQHandler
|
||||
.thumb_set GPDMA1_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel4_IRQHandler
|
||||
.thumb_set GPDMA1_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel5_IRQHandler
|
||||
.thumb_set GPDMA1_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel6_IRQHandler
|
||||
.thumb_set GPDMA1_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel7_IRQHandler
|
||||
.thumb_set GPDMA1_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_BRK_IRQHandler
|
||||
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_UP_IRQHandler
|
||||
.thumb_set TIM1_UP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_TRG_COM_IRQHandler
|
||||
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_CC_IRQHandler
|
||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM2_IRQHandler
|
||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM3_IRQHandler
|
||||
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM4_IRQHandler
|
||||
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM5_IRQHandler
|
||||
.thumb_set TIM5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM6_IRQHandler
|
||||
.thumb_set TIM6_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM7_IRQHandler
|
||||
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM9_IRQHandler
|
||||
.thumb_set TIM9_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI3_IRQHandler
|
||||
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI4_IRQHandler
|
||||
.thumb_set SPI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI5_IRQHandler
|
||||
.thumb_set SPI5_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI6_IRQHandler
|
||||
.thumb_set SPI6_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel0_IRQHandler
|
||||
.thumb_set HPDMA1_Channel0_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel1_IRQHandler
|
||||
.thumb_set HPDMA1_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel2_IRQHandler
|
||||
.thumb_set HPDMA1_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel3_IRQHandler
|
||||
.thumb_set HPDMA1_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel4_IRQHandler
|
||||
.thumb_set HPDMA1_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel5_IRQHandler
|
||||
.thumb_set HPDMA1_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel6_IRQHandler
|
||||
.thumb_set HPDMA1_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel7_IRQHandler
|
||||
.thumb_set HPDMA1_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI1_A_IRQHandler
|
||||
.thumb_set SAI1_A_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI1_B_IRQHandler
|
||||
.thumb_set SAI1_B_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI2_A_IRQHandler
|
||||
.thumb_set SAI2_A_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI2_B_IRQHandler
|
||||
.thumb_set SAI2_B_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_EV_IRQHandler
|
||||
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_ER_IRQHandler
|
||||
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_EV_IRQHandler
|
||||
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_ER_IRQHandler
|
||||
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART2_IRQHandler
|
||||
.thumb_set USART2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART3_IRQHandler
|
||||
.thumb_set USART3_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART4_IRQHandler
|
||||
.thumb_set UART4_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART5_IRQHandler
|
||||
.thumb_set UART5_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART7_IRQHandler
|
||||
.thumb_set UART7_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART8_IRQHandler
|
||||
.thumb_set UART8_IRQHandler,Default_Handler
|
||||
|
||||
.weak I3C1_EV_IRQHandler
|
||||
.thumb_set I3C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I3C1_ER_IRQHandler
|
||||
.thumb_set I3C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_IRQHandler
|
||||
.thumb_set OTG_HS_IRQHandler,Default_Handler
|
||||
|
||||
.weak ETH_IRQHandler
|
||||
.thumb_set ETH_IRQHandler,Default_Handler
|
||||
|
||||
.weak CORDIC_IRQHandler
|
||||
.thumb_set CORDIC_IRQHandler,Default_Handler
|
||||
|
||||
.weak GFXTIM_IRQHandler
|
||||
.thumb_set GFXTIM_IRQHandler,Default_Handler
|
||||
|
||||
.weak DCMIPP_IRQHandler
|
||||
.thumb_set DCMIPP_IRQHandler,Default_Handler
|
||||
|
||||
.weak LTDC_IRQHandler
|
||||
.thumb_set LTDC_IRQHandler,Default_Handler
|
||||
|
||||
.weak LTDC_ER_IRQHandler
|
||||
.thumb_set LTDC_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2D_IRQHandler
|
||||
.thumb_set DMA2D_IRQHandler,Default_Handler
|
||||
|
||||
.weak JPEG_IRQHandler
|
||||
.thumb_set JPEG_IRQHandler,Default_Handler
|
||||
|
||||
.weak GFXMMU_IRQHandler
|
||||
.thumb_set GFXMMU_IRQHandler,Default_Handler
|
||||
|
||||
.weak I3C1_WKUP_IRQHandler
|
||||
.thumb_set I3C1_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak XSPI1_IRQHandler
|
||||
.thumb_set XSPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak XSPI2_IRQHandler
|
||||
.thumb_set XSPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak FMC_IRQHandler
|
||||
.thumb_set FMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDMMC1_IRQHandler
|
||||
.thumb_set SDMMC1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDMMC2_IRQHandler
|
||||
.thumb_set SDMMC2_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_FS_IRQHandler
|
||||
.thumb_set OTG_FS_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM12_IRQHandler
|
||||
.thumb_set TIM12_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM13_IRQHandler
|
||||
.thumb_set TIM13_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM14_IRQHandler
|
||||
.thumb_set TIM14_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM15_IRQHandler
|
||||
.thumb_set TIM15_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM16_IRQHandler
|
||||
.thumb_set TIM16_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM17_IRQHandler
|
||||
.thumb_set TIM17_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM1_IRQHandler
|
||||
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM2_IRQHandler
|
||||
.thumb_set LPTIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM3_IRQHandler
|
||||
.thumb_set LPTIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM4_IRQHandler
|
||||
.thumb_set LPTIM4_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM5_IRQHandler
|
||||
.thumb_set LPTIM5_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPDIF_RX_IRQHandler
|
||||
.thumb_set SPDIF_RX_IRQHandler,Default_Handler
|
||||
|
||||
.weak MDIOS_IRQHandler
|
||||
.thumb_set MDIOS_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADF1_FLT0_IRQHandler
|
||||
.thumb_set ADF1_FLT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak CRS_IRQHandler
|
||||
.thumb_set CRS_IRQHandler,Default_Handler
|
||||
|
||||
.weak UCPD1_IRQHandler
|
||||
.thumb_set UCPD1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CEC_IRQHandler
|
||||
.thumb_set CEC_IRQHandler,Default_Handler
|
||||
|
||||
.weak PSSI_IRQHandler
|
||||
.thumb_set PSSI_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPUART1_IRQHandler
|
||||
.thumb_set LPUART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak WAKEUP_PIN_IRQHandler
|
||||
.thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel8_IRQHandler
|
||||
.thumb_set GPDMA1_Channel8_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel9_IRQHandler
|
||||
.thumb_set GPDMA1_Channel9_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel10_IRQHandler
|
||||
.thumb_set GPDMA1_Channel10_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel11_IRQHandler
|
||||
.thumb_set GPDMA1_Channel11_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel12_IRQHandler
|
||||
.thumb_set GPDMA1_Channel12_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel13_IRQHandler
|
||||
.thumb_set GPDMA1_Channel13_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel14_IRQHandler
|
||||
.thumb_set GPDMA1_Channel14_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel15_IRQHandler
|
||||
.thumb_set GPDMA1_Channel15_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel8_IRQHandler
|
||||
.thumb_set HPDMA1_Channel8_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel9_IRQHandler
|
||||
.thumb_set HPDMA1_Channel9_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel10_IRQHandler
|
||||
.thumb_set HPDMA1_Channel10_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel11_IRQHandler
|
||||
.thumb_set HPDMA1_Channel11_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel12_IRQHandler
|
||||
.thumb_set HPDMA1_Channel12_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel13_IRQHandler
|
||||
.thumb_set HPDMA1_Channel13_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel14_IRQHandler
|
||||
.thumb_set HPDMA1_Channel14_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel15_IRQHandler
|
||||
.thumb_set HPDMA1_Channel15_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPU2D_IRQHandler
|
||||
.thumb_set GPU2D_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPU2D_ER_IRQHandler
|
||||
.thumb_set GPU2D_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak ICACHE_IRQHandler
|
||||
.thumb_set ICACHE_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN1_IT0_IRQHandler
|
||||
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN1_IT1_IRQHandler
|
||||
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN2_IT0_IRQHandler
|
||||
.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN2_IT1_IRQHandler
|
||||
.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SystemInit
|
||||
|
|
@ -1,765 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file startup_stm32h7s3xx.s
|
||||
* @author MCD Application Team
|
||||
* @brief STM32H7S3xx Devices vector table for GCC toolchain.
|
||||
* This module performs:
|
||||
* - Set the initial SP
|
||||
* - Set the initial PC == Reset_Handler,
|
||||
* - Set the vector table entries with the exceptions ISR address
|
||||
* - Branches to main in the C library (which eventually
|
||||
* calls main()).
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m7
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global g_pfnVectors
|
||||
.global Default_Handler
|
||||
|
||||
/* start address for the initialization values of the .data section.
|
||||
defined in linker script */
|
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */
|
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */
|
||||
.word _edata
|
||||
/* start address for the .bss section. defined in linker script */
|
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */
|
||||
.word _ebss
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor first
|
||||
* starts execution following a reset event. Only the absolutely
|
||||
* necessary set is performed, after which the application
|
||||
* supplied main() routine is called.
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
ldr r0, =_estack
|
||||
mov sp, r0 /* set stack pointer */
|
||||
/* Call the clock system initialization function.*/
|
||||
bl SystemInit
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
ldr r0, =_sdata
|
||||
ldr r1, =_edata
|
||||
ldr r2, =_sidata
|
||||
movs r3, #0
|
||||
b LoopCopyDataInit
|
||||
|
||||
CopyDataInit:
|
||||
ldr r4, [r2, r3]
|
||||
str r4, [r0, r3]
|
||||
adds r3, r3, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
adds r4, r0, r3
|
||||
cmp r4, r1
|
||||
bcc CopyDataInit
|
||||
|
||||
/* Zero fill the bss segment. */
|
||||
ldr r2, =_sbss
|
||||
ldr r4, =_ebss
|
||||
movs r3, #0
|
||||
b LoopFillZerobss
|
||||
|
||||
FillZerobss:
|
||||
str r3, [r2]
|
||||
adds r2, r2, #4
|
||||
|
||||
LoopFillZerobss:
|
||||
cmp r2, r4
|
||||
bcc FillZerobss
|
||||
|
||||
/* Call static constructors */
|
||||
bl __libc_init_array
|
||||
/* Call the application's entry point.*/
|
||||
bl main
|
||||
|
||||
LoopForever:
|
||||
b LoopForever
|
||||
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||
* the system state for examination by a debugger.
|
||||
*
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* The STM32H7S3xx vector table. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*
|
||||
******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
g_pfnVectors:
|
||||
.word _estack
|
||||
.word Reset_Handler
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word MemManage_Handler
|
||||
.word BusFault_Handler
|
||||
.word UsageFault_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word SVC_Handler
|
||||
.word DebugMon_Handler
|
||||
.word 0
|
||||
.word PendSV_Handler
|
||||
.word SysTick_Handler
|
||||
/* External Interrupts */
|
||||
.word PVD_PVM_IRQHandler /* PVD/PVM through EXTI Line detection */
|
||||
.word 0 /* Reserved */
|
||||
.word DTS_IRQHandler /* Digital Temperature Sensor */
|
||||
.word IWDG_IRQHandler /* Internal Watchdog */
|
||||
.word WWDG_IRQHandler /* Window Watchdog */
|
||||
.word RCC_IRQHandler /* RCC global interrupts through EXTI Line detection */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word FLASH_IRQHandler /* FLASH interrupts */
|
||||
.word RAMECC_IRQHandler /* RAMECC interrupts */
|
||||
.word FPU_IRQHandler /* FPU */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word TAMP_IRQHandler /* Tamper and TimeStamp interrupts */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word EXTI0_IRQHandler /* EXTI Line0 */
|
||||
.word EXTI1_IRQHandler /* EXTI Line1 */
|
||||
.word EXTI2_IRQHandler /* EXTI Line2 */
|
||||
.word EXTI3_IRQHandler /* EXTI Line3 */
|
||||
.word EXTI4_IRQHandler /* EXTI Line4 */
|
||||
.word EXTI5_IRQHandler /* EXTI Line5 */
|
||||
.word EXTI6_IRQHandler /* EXTI Line6 */
|
||||
.word EXTI7_IRQHandler /* EXTI Line7 */
|
||||
.word EXTI8_IRQHandler /* EXTI Line8 */
|
||||
.word EXTI9_IRQHandler /* EXTI Line9 */
|
||||
.word EXTI10_IRQHandler /* EXTI Line10 */
|
||||
.word EXTI11_IRQHandler /* EXTI Line11 */
|
||||
.word EXTI12_IRQHandler /* EXTI Line12 */
|
||||
.word EXTI13_IRQHandler /* EXTI Line13 */
|
||||
.word EXTI14_IRQHandler /* EXTI Line14 */
|
||||
.word EXTI15_IRQHandler /* EXTI Line15 */
|
||||
.word RTC_IRQHandler /* RTC wakeup and alarm interrupts */
|
||||
.word SAES_IRQHandler /* SAES */
|
||||
.word CRYP_IRQHandler /* CRYP */
|
||||
.word PKA_IRQHandler /* PKA */
|
||||
.word HASH_IRQHandler /* HASH */
|
||||
.word RNG_IRQHandler /* RNG */
|
||||
.word ADC1_2_IRQHandler /* ADC1 & ADC2 */
|
||||
.word GPDMA1_Channel0_IRQHandler /* GPDMA1 Channel 0 */
|
||||
.word GPDMA1_Channel1_IRQHandler /* GPDMA1 Channel 1 */
|
||||
.word GPDMA1_Channel2_IRQHandler /* GPDMA1 Channel 2 */
|
||||
.word GPDMA1_Channel3_IRQHandler /* GPDMA1 Channel 3 */
|
||||
.word GPDMA1_Channel4_IRQHandler /* GPDMA1 Channel 4 */
|
||||
.word GPDMA1_Channel5_IRQHandler /* GPDMA1 Channel 5 */
|
||||
.word GPDMA1_Channel6_IRQHandler /* GPDMA1 Channel 6 */
|
||||
.word GPDMA1_Channel7_IRQHandler /* GPDMA1 Channel 7 */
|
||||
.word TIM1_BRK_IRQHandler /* TIM1 Break */
|
||||
.word TIM1_UP_IRQHandler /* TIM1 Update */
|
||||
.word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */
|
||||
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
|
||||
.word TIM2_IRQHandler /* TIM2 */
|
||||
.word TIM3_IRQHandler /* TIM3 */
|
||||
.word TIM4_IRQHandler /* TIM4 */
|
||||
.word TIM5_IRQHandler /* TIM5 */
|
||||
.word TIM6_IRQHandler /* TIM6 */
|
||||
.word TIM7_IRQHandler /* TIM7 */
|
||||
.word TIM9_IRQHandler /* TIM9 */
|
||||
.word SPI1_IRQHandler /* SPI1 */
|
||||
.word SPI2_IRQHandler /* SPI2 */
|
||||
.word SPI3_IRQHandler /* SPI3 */
|
||||
.word SPI4_IRQHandler /* SPI4 */
|
||||
.word SPI5_IRQHandler /* SPI5 */
|
||||
.word SPI6_IRQHandler /* SPI6 */
|
||||
.word HPDMA1_Channel0_IRQHandler /* HPDMA1 Channel 0 */
|
||||
.word HPDMA1_Channel1_IRQHandler /* HPDMA1 Channel 1 */
|
||||
.word HPDMA1_Channel2_IRQHandler /* HPDMA1 Channel 2 */
|
||||
.word HPDMA1_Channel3_IRQHandler /* HPDMA1 Channel 3 */
|
||||
.word HPDMA1_Channel4_IRQHandler /* HPDMA1 Channel 4 */
|
||||
.word HPDMA1_Channel5_IRQHandler /* HPDMA1 Channel 5 */
|
||||
.word HPDMA1_Channel6_IRQHandler /* HPDMA1 Channel 6 */
|
||||
.word HPDMA1_Channel7_IRQHandler /* HPDMA1 Channel 7 */
|
||||
.word SAI1_A_IRQHandler /* Serial Audio Interface 1 block A */
|
||||
.word SAI1_B_IRQHandler /* Serial Audio Interface 1 block B */
|
||||
.word SAI2_A_IRQHandler /* Serial Audio Interface 2 block A */
|
||||
.word SAI2_B_IRQHandler /* Serial Audio Interface 2 block B */
|
||||
.word I2C1_EV_IRQHandler /* I2C1 Event */
|
||||
.word I2C1_ER_IRQHandler /* I2C1 Error */
|
||||
.word I2C2_EV_IRQHandler /* I2C2 Event */
|
||||
.word I2C2_ER_IRQHandler /* I2C2 Error */
|
||||
.word I2C3_EV_IRQHandler /* I2C3 Event */
|
||||
.word I2C3_ER_IRQHandler /* I2C3 Error */
|
||||
.word USART1_IRQHandler /* USART1 */
|
||||
.word USART2_IRQHandler /* USART2 */
|
||||
.word USART3_IRQHandler /* USART3 */
|
||||
.word UART4_IRQHandler /* UART4 */
|
||||
.word UART5_IRQHandler /* UART5 */
|
||||
.word UART7_IRQHandler /* UART7 */
|
||||
.word UART8_IRQHandler /* UART8 */
|
||||
.word I3C1_EV_IRQHandler /* I3C1 Event */
|
||||
.word I3C1_ER_IRQHandler /* I3C1 Error */
|
||||
.word OTG_HS_IRQHandler /* USB OTG HS */
|
||||
.word ETH_IRQHandler /* Ethernet */
|
||||
.word CORDIC_IRQHandler /* CORDIC */
|
||||
.word GFXTIM_IRQHandler /* GFXTIM */
|
||||
.word DCMIPP_IRQHandler /* DCMIPP */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word DMA2D_IRQHandler /* DMA2D */
|
||||
.word JPEG_IRQHandler /* JPEG */
|
||||
.word GFXMMU_IRQHandler /* GFXMMU */
|
||||
.word I3C1_WKUP_IRQHandler /* I3C1 wakeup */
|
||||
.word MCE1_IRQHandler /* MCE1 */
|
||||
.word MCE2_IRQHandler /* MCE2 */
|
||||
.word MCE3_IRQHandler /* MCE3 */
|
||||
.word XSPI1_IRQHandler /* XSPI1 */
|
||||
.word XSPI2_IRQHandler /* XSPI2 */
|
||||
.word FMC_IRQHandler /* FMC */
|
||||
.word SDMMC1_IRQHandler /* SDMMC1 */
|
||||
.word SDMMC2_IRQHandler /* SDMMC2 */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word OTG_FS_IRQHandler /* USB OTG FS */
|
||||
.word TIM12_IRQHandler /* TIM12 */
|
||||
.word TIM13_IRQHandler /* TIM13 */
|
||||
.word TIM14_IRQHandler /* TIM14 */
|
||||
.word TIM15_IRQHandler /* TIM15 */
|
||||
.word TIM16_IRQHandler /* TIM16 */
|
||||
.word TIM17_IRQHandler /* TIM17 */
|
||||
.word LPTIM1_IRQHandler /* LP TIM1 */
|
||||
.word LPTIM2_IRQHandler /* LP TIM2 */
|
||||
.word LPTIM3_IRQHandler /* LP TIM3 */
|
||||
.word LPTIM4_IRQHandler /* LP TIM4 */
|
||||
.word LPTIM5_IRQHandler /* LP TIM5 */
|
||||
.word SPDIF_RX_IRQHandler /* SPDIF_RX */
|
||||
.word MDIOS_IRQHandler /* MDIOS */
|
||||
.word ADF1_FLT0_IRQHandler /* ADF1 Filter 0 */
|
||||
.word CRS_IRQHandler /* CRS */
|
||||
.word UCPD1_IRQHandler /* UCPD1 */
|
||||
.word CEC_IRQHandler /* HDMI_CEC */
|
||||
.word PSSI_IRQHandler /* PSSI */
|
||||
.word LPUART1_IRQHandler /* LP UART1 */
|
||||
.word WAKEUP_PIN_IRQHandler /* Wake-up pins interrupt */
|
||||
.word GPDMA1_Channel8_IRQHandler /* GPDMA1 Channel 8 */
|
||||
.word GPDMA1_Channel9_IRQHandler /* GPDMA1 Channel 9 */
|
||||
.word GPDMA1_Channel10_IRQHandler /* GPDMA1 Channel 10 */
|
||||
.word GPDMA1_Channel11_IRQHandler /* GPDMA1 Channel 11 */
|
||||
.word GPDMA1_Channel12_IRQHandler /* GPDMA1 Channel 12 */
|
||||
.word GPDMA1_Channel13_IRQHandler /* GPDMA1 Channel 13 */
|
||||
.word GPDMA1_Channel14_IRQHandler /* GPDMA1 Channel 14 */
|
||||
.word GPDMA1_Channel15_IRQHandler /* GPDMA1 Channel 15 */
|
||||
.word HPDMA1_Channel8_IRQHandler /* HPDMA1 Channel 8 */
|
||||
.word HPDMA1_Channel9_IRQHandler /* HPDMA1 Channel 9 */
|
||||
.word HPDMA1_Channel10_IRQHandler /* HPDMA1 Channel 10 */
|
||||
.word HPDMA1_Channel11_IRQHandler /* HPDMA1 Channel 11 */
|
||||
.word HPDMA1_Channel12_IRQHandler /* HPDMA1 Channel 12 */
|
||||
.word HPDMA1_Channel13_IRQHandler /* HPDMA1 Channel 13 */
|
||||
.word HPDMA1_Channel14_IRQHandler /* HPDMA1 Channel 14 */
|
||||
.word HPDMA1_Channel15_IRQHandler /* HPDMA1 Channel 15 */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word FDCAN1_IT0_IRQHandler /* FDCAN1 Interrupt 0 */
|
||||
.word FDCAN1_IT1_IRQHandler /* FDCAN1 Interrupt 1 */
|
||||
.word FDCAN2_IT0_IRQHandler /* FDCAN2 Interrupt 0 */
|
||||
.word FDCAN2_IT1_IRQHandler /* FDCAN2 Interrupt 1 */
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak PVD_PVM_IRQHandler
|
||||
.thumb_set PVD_PVM_IRQHandler,Default_Handler
|
||||
|
||||
.weak DTS_IRQHandler
|
||||
.thumb_set DTS_IRQHandler,Default_Handler
|
||||
|
||||
.weak IWDG_IRQHandler
|
||||
.thumb_set IWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak WWDG_IRQHandler
|
||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_IRQHandler
|
||||
.thumb_set RCC_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak RAMECC_IRQHandler
|
||||
.thumb_set RAMECC_IRQHandler,Default_Handler
|
||||
|
||||
.weak FPU_IRQHandler
|
||||
.thumb_set FPU_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMP_IRQHandler
|
||||
.thumb_set TAMP_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI5_IRQHandler
|
||||
.thumb_set EXTI5_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI6_IRQHandler
|
||||
.thumb_set EXTI6_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI7_IRQHandler
|
||||
.thumb_set EXTI7_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI8_IRQHandler
|
||||
.thumb_set EXTI8_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI9_IRQHandler
|
||||
.thumb_set EXTI9_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI10_IRQHandler
|
||||
.thumb_set EXTI10_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI11_IRQHandler
|
||||
.thumb_set EXTI11_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI12_IRQHandler
|
||||
.thumb_set EXTI12_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI13_IRQHandler
|
||||
.thumb_set EXTI13_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI14_IRQHandler
|
||||
.thumb_set EXTI14_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI15_IRQHandler
|
||||
.thumb_set EXTI15_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_IRQHandler
|
||||
.thumb_set RTC_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAES_IRQHandler
|
||||
.thumb_set SAES_IRQHandler,Default_Handler
|
||||
|
||||
.weak CRYP_IRQHandler
|
||||
.thumb_set CRYP_IRQHandler,Default_Handler
|
||||
|
||||
.weak PKA_IRQHandler
|
||||
.thumb_set PKA_IRQHandler,Default_Handler
|
||||
|
||||
.weak HASH_IRQHandler
|
||||
.thumb_set HASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak RNG_IRQHandler
|
||||
.thumb_set RNG_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC1_2_IRQHandler
|
||||
.thumb_set ADC1_2_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel0_IRQHandler
|
||||
.thumb_set GPDMA1_Channel0_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel1_IRQHandler
|
||||
.thumb_set GPDMA1_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel2_IRQHandler
|
||||
.thumb_set GPDMA1_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel3_IRQHandler
|
||||
.thumb_set GPDMA1_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel4_IRQHandler
|
||||
.thumb_set GPDMA1_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel5_IRQHandler
|
||||
.thumb_set GPDMA1_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel6_IRQHandler
|
||||
.thumb_set GPDMA1_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel7_IRQHandler
|
||||
.thumb_set GPDMA1_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_BRK_IRQHandler
|
||||
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_UP_IRQHandler
|
||||
.thumb_set TIM1_UP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_TRG_COM_IRQHandler
|
||||
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_CC_IRQHandler
|
||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM2_IRQHandler
|
||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM3_IRQHandler
|
||||
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM4_IRQHandler
|
||||
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM5_IRQHandler
|
||||
.thumb_set TIM5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM6_IRQHandler
|
||||
.thumb_set TIM6_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM7_IRQHandler
|
||||
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM9_IRQHandler
|
||||
.thumb_set TIM9_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI3_IRQHandler
|
||||
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI4_IRQHandler
|
||||
.thumb_set SPI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI5_IRQHandler
|
||||
.thumb_set SPI5_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI6_IRQHandler
|
||||
.thumb_set SPI6_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel0_IRQHandler
|
||||
.thumb_set HPDMA1_Channel0_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel1_IRQHandler
|
||||
.thumb_set HPDMA1_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel2_IRQHandler
|
||||
.thumb_set HPDMA1_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel3_IRQHandler
|
||||
.thumb_set HPDMA1_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel4_IRQHandler
|
||||
.thumb_set HPDMA1_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel5_IRQHandler
|
||||
.thumb_set HPDMA1_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel6_IRQHandler
|
||||
.thumb_set HPDMA1_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel7_IRQHandler
|
||||
.thumb_set HPDMA1_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI1_A_IRQHandler
|
||||
.thumb_set SAI1_A_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI1_B_IRQHandler
|
||||
.thumb_set SAI1_B_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI2_A_IRQHandler
|
||||
.thumb_set SAI2_A_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI2_B_IRQHandler
|
||||
.thumb_set SAI2_B_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_EV_IRQHandler
|
||||
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_ER_IRQHandler
|
||||
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_EV_IRQHandler
|
||||
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_ER_IRQHandler
|
||||
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART2_IRQHandler
|
||||
.thumb_set USART2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART3_IRQHandler
|
||||
.thumb_set USART3_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART4_IRQHandler
|
||||
.thumb_set UART4_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART5_IRQHandler
|
||||
.thumb_set UART5_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART7_IRQHandler
|
||||
.thumb_set UART7_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART8_IRQHandler
|
||||
.thumb_set UART8_IRQHandler,Default_Handler
|
||||
|
||||
.weak I3C1_EV_IRQHandler
|
||||
.thumb_set I3C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I3C1_ER_IRQHandler
|
||||
.thumb_set I3C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_IRQHandler
|
||||
.thumb_set OTG_HS_IRQHandler,Default_Handler
|
||||
|
||||
.weak ETH_IRQHandler
|
||||
.thumb_set ETH_IRQHandler,Default_Handler
|
||||
|
||||
.weak CORDIC_IRQHandler
|
||||
.thumb_set CORDIC_IRQHandler,Default_Handler
|
||||
|
||||
.weak GFXTIM_IRQHandler
|
||||
.thumb_set GFXTIM_IRQHandler,Default_Handler
|
||||
|
||||
.weak DCMIPP_IRQHandler
|
||||
.thumb_set DCMIPP_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2D_IRQHandler
|
||||
.thumb_set DMA2D_IRQHandler,Default_Handler
|
||||
|
||||
.weak JPEG_IRQHandler
|
||||
.thumb_set JPEG_IRQHandler,Default_Handler
|
||||
|
||||
.weak GFXMMU_IRQHandler
|
||||
.thumb_set GFXMMU_IRQHandler,Default_Handler
|
||||
|
||||
.weak I3C1_WKUP_IRQHandler
|
||||
.thumb_set I3C1_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak MCE1_IRQHandler
|
||||
.thumb_set MCE1_IRQHandler,Default_Handler
|
||||
|
||||
.weak MCE2_IRQHandler
|
||||
.thumb_set MCE2_IRQHandler,Default_Handler
|
||||
|
||||
.weak MCE3_IRQHandler
|
||||
.thumb_set MCE3_IRQHandler,Default_Handler
|
||||
|
||||
.weak XSPI1_IRQHandler
|
||||
.thumb_set XSPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak XSPI2_IRQHandler
|
||||
.thumb_set XSPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak FMC_IRQHandler
|
||||
.thumb_set FMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDMMC1_IRQHandler
|
||||
.thumb_set SDMMC1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDMMC2_IRQHandler
|
||||
.thumb_set SDMMC2_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_FS_IRQHandler
|
||||
.thumb_set OTG_FS_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM12_IRQHandler
|
||||
.thumb_set TIM12_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM13_IRQHandler
|
||||
.thumb_set TIM13_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM14_IRQHandler
|
||||
.thumb_set TIM14_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM15_IRQHandler
|
||||
.thumb_set TIM15_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM16_IRQHandler
|
||||
.thumb_set TIM16_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM17_IRQHandler
|
||||
.thumb_set TIM17_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM1_IRQHandler
|
||||
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM2_IRQHandler
|
||||
.thumb_set LPTIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM3_IRQHandler
|
||||
.thumb_set LPTIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM4_IRQHandler
|
||||
.thumb_set LPTIM4_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM5_IRQHandler
|
||||
.thumb_set LPTIM5_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPDIF_RX_IRQHandler
|
||||
.thumb_set SPDIF_RX_IRQHandler,Default_Handler
|
||||
|
||||
.weak MDIOS_IRQHandler
|
||||
.thumb_set MDIOS_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADF1_FLT0_IRQHandler
|
||||
.thumb_set ADF1_FLT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak CRS_IRQHandler
|
||||
.thumb_set CRS_IRQHandler,Default_Handler
|
||||
|
||||
.weak UCPD1_IRQHandler
|
||||
.thumb_set UCPD1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CEC_IRQHandler
|
||||
.thumb_set CEC_IRQHandler,Default_Handler
|
||||
|
||||
.weak PSSI_IRQHandler
|
||||
.thumb_set PSSI_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPUART1_IRQHandler
|
||||
.thumb_set LPUART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak WAKEUP_PIN_IRQHandler
|
||||
.thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel8_IRQHandler
|
||||
.thumb_set GPDMA1_Channel8_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel9_IRQHandler
|
||||
.thumb_set GPDMA1_Channel9_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel10_IRQHandler
|
||||
.thumb_set GPDMA1_Channel10_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel11_IRQHandler
|
||||
.thumb_set GPDMA1_Channel11_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel12_IRQHandler
|
||||
.thumb_set GPDMA1_Channel12_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel13_IRQHandler
|
||||
.thumb_set GPDMA1_Channel13_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel14_IRQHandler
|
||||
.thumb_set GPDMA1_Channel14_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel15_IRQHandler
|
||||
.thumb_set GPDMA1_Channel15_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel8_IRQHandler
|
||||
.thumb_set HPDMA1_Channel8_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel9_IRQHandler
|
||||
.thumb_set HPDMA1_Channel9_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel10_IRQHandler
|
||||
.thumb_set HPDMA1_Channel10_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel11_IRQHandler
|
||||
.thumb_set HPDMA1_Channel11_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel12_IRQHandler
|
||||
.thumb_set HPDMA1_Channel12_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel13_IRQHandler
|
||||
.thumb_set HPDMA1_Channel13_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel14_IRQHandler
|
||||
.thumb_set HPDMA1_Channel14_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel15_IRQHandler
|
||||
.thumb_set HPDMA1_Channel15_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN1_IT0_IRQHandler
|
||||
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN1_IT1_IRQHandler
|
||||
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN2_IT0_IRQHandler
|
||||
.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN2_IT1_IRQHandler
|
||||
.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SystemInit
|
||||
|
|
@ -1,780 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file startup_stm32h7s7xx.s
|
||||
* @author MCD Application Team
|
||||
* @brief STM32H7S7xx Devices vector table for GCC toolchain.
|
||||
* This module performs:
|
||||
* - Set the initial SP
|
||||
* - Set the initial PC == Reset_Handler,
|
||||
* - Set the vector table entries with the exceptions ISR address
|
||||
* - Branches to main in the C library (which eventually
|
||||
* calls main()).
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m7
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global g_pfnVectors
|
||||
.global Default_Handler
|
||||
|
||||
/* start address for the initialization values of the .data section.
|
||||
defined in linker script */
|
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */
|
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */
|
||||
.word _edata
|
||||
/* start address for the .bss section. defined in linker script */
|
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */
|
||||
.word _ebss
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor first
|
||||
* starts execution following a reset event. Only the absolutely
|
||||
* necessary set is performed, after which the application
|
||||
* supplied main() routine is called.
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
ldr r0, =_estack
|
||||
mov sp, r0 /* set stack pointer */
|
||||
/* Call the clock system initialization function.*/
|
||||
bl SystemInit
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
ldr r0, =_sdata
|
||||
ldr r1, =_edata
|
||||
ldr r2, =_sidata
|
||||
movs r3, #0
|
||||
b LoopCopyDataInit
|
||||
|
||||
CopyDataInit:
|
||||
ldr r4, [r2, r3]
|
||||
str r4, [r0, r3]
|
||||
adds r3, r3, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
adds r4, r0, r3
|
||||
cmp r4, r1
|
||||
bcc CopyDataInit
|
||||
|
||||
/* Zero fill the bss segment. */
|
||||
ldr r2, =_sbss
|
||||
ldr r4, =_ebss
|
||||
movs r3, #0
|
||||
b LoopFillZerobss
|
||||
|
||||
FillZerobss:
|
||||
str r3, [r2]
|
||||
adds r2, r2, #4
|
||||
|
||||
LoopFillZerobss:
|
||||
cmp r2, r4
|
||||
bcc FillZerobss
|
||||
|
||||
/* Call static constructors */
|
||||
bl __libc_init_array
|
||||
/* Call the application's entry point.*/
|
||||
bl main
|
||||
|
||||
LoopForever:
|
||||
b LoopForever
|
||||
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||
* the system state for examination by a debugger.
|
||||
*
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* The STM32H7S7xx vector table. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*
|
||||
******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
g_pfnVectors:
|
||||
.word _estack
|
||||
.word Reset_Handler
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word MemManage_Handler
|
||||
.word BusFault_Handler
|
||||
.word UsageFault_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word SVC_Handler
|
||||
.word DebugMon_Handler
|
||||
.word 0
|
||||
.word PendSV_Handler
|
||||
.word SysTick_Handler
|
||||
/* External Interrupts */
|
||||
.word PVD_PVM_IRQHandler /* PVD/PVM through EXTI Line detection */
|
||||
.word 0 /* Reserved */
|
||||
.word DTS_IRQHandler /* Digital Temperature Sensor */
|
||||
.word IWDG_IRQHandler /* Internal Watchdog */
|
||||
.word WWDG_IRQHandler /* Window Watchdog */
|
||||
.word RCC_IRQHandler /* RCC global interrupts through EXTI Line detection */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word FLASH_IRQHandler /* FLASH interrupts */
|
||||
.word RAMECC_IRQHandler /* RAMECC interrupts */
|
||||
.word FPU_IRQHandler /* FPU */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word TAMP_IRQHandler /* Tamper and TimeStamp interrupts */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word EXTI0_IRQHandler /* EXTI Line0 */
|
||||
.word EXTI1_IRQHandler /* EXTI Line1 */
|
||||
.word EXTI2_IRQHandler /* EXTI Line2 */
|
||||
.word EXTI3_IRQHandler /* EXTI Line3 */
|
||||
.word EXTI4_IRQHandler /* EXTI Line4 */
|
||||
.word EXTI5_IRQHandler /* EXTI Line5 */
|
||||
.word EXTI6_IRQHandler /* EXTI Line6 */
|
||||
.word EXTI7_IRQHandler /* EXTI Line7 */
|
||||
.word EXTI8_IRQHandler /* EXTI Line8 */
|
||||
.word EXTI9_IRQHandler /* EXTI Line9 */
|
||||
.word EXTI10_IRQHandler /* EXTI Line10 */
|
||||
.word EXTI11_IRQHandler /* EXTI Line11 */
|
||||
.word EXTI12_IRQHandler /* EXTI Line12 */
|
||||
.word EXTI13_IRQHandler /* EXTI Line13 */
|
||||
.word EXTI14_IRQHandler /* EXTI Line14 */
|
||||
.word EXTI15_IRQHandler /* EXTI Line15 */
|
||||
.word RTC_IRQHandler /* RTC wakeup and alarm interrupts */
|
||||
.word SAES_IRQHandler /* SAES */
|
||||
.word CRYP_IRQHandler /* CRYP */
|
||||
.word PKA_IRQHandler /* PKA */
|
||||
.word HASH_IRQHandler /* HASH */
|
||||
.word RNG_IRQHandler /* RNG */
|
||||
.word ADC1_2_IRQHandler /* ADC1 & ADC2 */
|
||||
.word GPDMA1_Channel0_IRQHandler /* GPDMA1 Channel 0 */
|
||||
.word GPDMA1_Channel1_IRQHandler /* GPDMA1 Channel 1 */
|
||||
.word GPDMA1_Channel2_IRQHandler /* GPDMA1 Channel 2 */
|
||||
.word GPDMA1_Channel3_IRQHandler /* GPDMA1 Channel 3 */
|
||||
.word GPDMA1_Channel4_IRQHandler /* GPDMA1 Channel 4 */
|
||||
.word GPDMA1_Channel5_IRQHandler /* GPDMA1 Channel 5 */
|
||||
.word GPDMA1_Channel6_IRQHandler /* GPDMA1 Channel 6 */
|
||||
.word GPDMA1_Channel7_IRQHandler /* GPDMA1 Channel 7 */
|
||||
.word TIM1_BRK_IRQHandler /* TIM1 Break */
|
||||
.word TIM1_UP_IRQHandler /* TIM1 Update */
|
||||
.word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */
|
||||
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
|
||||
.word TIM2_IRQHandler /* TIM2 */
|
||||
.word TIM3_IRQHandler /* TIM3 */
|
||||
.word TIM4_IRQHandler /* TIM4 */
|
||||
.word TIM5_IRQHandler /* TIM5 */
|
||||
.word TIM6_IRQHandler /* TIM6 */
|
||||
.word TIM7_IRQHandler /* TIM7 */
|
||||
.word TIM9_IRQHandler /* TIM9 */
|
||||
.word SPI1_IRQHandler /* SPI1 */
|
||||
.word SPI2_IRQHandler /* SPI2 */
|
||||
.word SPI3_IRQHandler /* SPI3 */
|
||||
.word SPI4_IRQHandler /* SPI4 */
|
||||
.word SPI5_IRQHandler /* SPI5 */
|
||||
.word SPI6_IRQHandler /* SPI6 */
|
||||
.word HPDMA1_Channel0_IRQHandler /* HPDMA1 Channel 0 */
|
||||
.word HPDMA1_Channel1_IRQHandler /* HPDMA1 Channel 1 */
|
||||
.word HPDMA1_Channel2_IRQHandler /* HPDMA1 Channel 2 */
|
||||
.word HPDMA1_Channel3_IRQHandler /* HPDMA1 Channel 3 */
|
||||
.word HPDMA1_Channel4_IRQHandler /* HPDMA1 Channel 4 */
|
||||
.word HPDMA1_Channel5_IRQHandler /* HPDMA1 Channel 5 */
|
||||
.word HPDMA1_Channel6_IRQHandler /* HPDMA1 Channel 6 */
|
||||
.word HPDMA1_Channel7_IRQHandler /* HPDMA1 Channel 7 */
|
||||
.word SAI1_A_IRQHandler /* Serial Audio Interface 1 block A */
|
||||
.word SAI1_B_IRQHandler /* Serial Audio Interface 1 block B */
|
||||
.word SAI2_A_IRQHandler /* Serial Audio Interface 2 block A */
|
||||
.word SAI2_B_IRQHandler /* Serial Audio Interface 2 block B */
|
||||
.word I2C1_EV_IRQHandler /* I2C1 Event */
|
||||
.word I2C1_ER_IRQHandler /* I2C1 Error */
|
||||
.word I2C2_EV_IRQHandler /* I2C2 Event */
|
||||
.word I2C2_ER_IRQHandler /* I2C2 Error */
|
||||
.word I2C3_EV_IRQHandler /* I2C3 Event */
|
||||
.word I2C3_ER_IRQHandler /* I2C3 Error */
|
||||
.word USART1_IRQHandler /* USART1 */
|
||||
.word USART2_IRQHandler /* USART2 */
|
||||
.word USART3_IRQHandler /* USART3 */
|
||||
.word UART4_IRQHandler /* UART4 */
|
||||
.word UART5_IRQHandler /* UART5 */
|
||||
.word UART7_IRQHandler /* UART7 */
|
||||
.word UART8_IRQHandler /* UART8 */
|
||||
.word I3C1_EV_IRQHandler /* I3C1 Event */
|
||||
.word I3C1_ER_IRQHandler /* I3C1 Error */
|
||||
.word OTG_HS_IRQHandler /* USB OTG HS */
|
||||
.word ETH_IRQHandler /* Ethernet */
|
||||
.word CORDIC_IRQHandler /* CORDIC */
|
||||
.word GFXTIM_IRQHandler /* GFXTIM */
|
||||
.word DCMIPP_IRQHandler /* DCMIPP */
|
||||
.word LTDC_IRQHandler /* LTDC */
|
||||
.word LTDC_ER_IRQHandler /* LTDC error */
|
||||
.word DMA2D_IRQHandler /* DMA2D */
|
||||
.word JPEG_IRQHandler /* JPEG */
|
||||
.word GFXMMU_IRQHandler /* GFXMMU */
|
||||
.word I3C1_WKUP_IRQHandler /* I3C1 wakeup */
|
||||
.word MCE1_IRQHandler /* MCE1 */
|
||||
.word MCE2_IRQHandler /* MCE2 */
|
||||
.word MCE3_IRQHandler /* MCE3 */
|
||||
.word XSPI1_IRQHandler /* XSPI1 */
|
||||
.word XSPI2_IRQHandler /* XSPI2 */
|
||||
.word FMC_IRQHandler /* FMC */
|
||||
.word SDMMC1_IRQHandler /* SDMMC1 */
|
||||
.word SDMMC2_IRQHandler /* SDMMC2 */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word OTG_FS_IRQHandler /* USB OTG FS */
|
||||
.word TIM12_IRQHandler /* TIM12 */
|
||||
.word TIM13_IRQHandler /* TIM13 */
|
||||
.word TIM14_IRQHandler /* TIM14 */
|
||||
.word TIM15_IRQHandler /* TIM15 */
|
||||
.word TIM16_IRQHandler /* TIM16 */
|
||||
.word TIM17_IRQHandler /* TIM17 */
|
||||
.word LPTIM1_IRQHandler /* LP TIM1 */
|
||||
.word LPTIM2_IRQHandler /* LP TIM2 */
|
||||
.word LPTIM3_IRQHandler /* LP TIM3 */
|
||||
.word LPTIM4_IRQHandler /* LP TIM4 */
|
||||
.word LPTIM5_IRQHandler /* LP TIM5 */
|
||||
.word SPDIF_RX_IRQHandler /* SPDIF_RX */
|
||||
.word MDIOS_IRQHandler /* MDIOS */
|
||||
.word ADF1_FLT0_IRQHandler /* ADF1 Filter 0 */
|
||||
.word CRS_IRQHandler /* CRS */
|
||||
.word UCPD1_IRQHandler /* UCPD1 */
|
||||
.word CEC_IRQHandler /* HDMI_CEC */
|
||||
.word PSSI_IRQHandler /* PSSI */
|
||||
.word LPUART1_IRQHandler /* LP UART1 */
|
||||
.word WAKEUP_PIN_IRQHandler /* Wake-up pins interrupt */
|
||||
.word GPDMA1_Channel8_IRQHandler /* GPDMA1 Channel 8 */
|
||||
.word GPDMA1_Channel9_IRQHandler /* GPDMA1 Channel 9 */
|
||||
.word GPDMA1_Channel10_IRQHandler /* GPDMA1 Channel 10 */
|
||||
.word GPDMA1_Channel11_IRQHandler /* GPDMA1 Channel 11 */
|
||||
.word GPDMA1_Channel12_IRQHandler /* GPDMA1 Channel 12 */
|
||||
.word GPDMA1_Channel13_IRQHandler /* GPDMA1 Channel 13 */
|
||||
.word GPDMA1_Channel14_IRQHandler /* GPDMA1 Channel 14 */
|
||||
.word GPDMA1_Channel15_IRQHandler /* GPDMA1 Channel 15 */
|
||||
.word HPDMA1_Channel8_IRQHandler /* HPDMA1 Channel 8 */
|
||||
.word HPDMA1_Channel9_IRQHandler /* HPDMA1 Channel 9 */
|
||||
.word HPDMA1_Channel10_IRQHandler /* HPDMA1 Channel 10 */
|
||||
.word HPDMA1_Channel11_IRQHandler /* HPDMA1 Channel 11 */
|
||||
.word HPDMA1_Channel12_IRQHandler /* HPDMA1 Channel 12 */
|
||||
.word HPDMA1_Channel13_IRQHandler /* HPDMA1 Channel 13 */
|
||||
.word HPDMA1_Channel14_IRQHandler /* HPDMA1 Channel 14 */
|
||||
.word HPDMA1_Channel15_IRQHandler /* HPDMA1 Channel 15 */
|
||||
.word GPU2D_IRQHandler /* GPU2D */
|
||||
.word GPU2D_ER_IRQHandler /* GPU2D error */
|
||||
.word ICACHE_IRQHandler /* ICACHE */
|
||||
.word FDCAN1_IT0_IRQHandler /* FDCAN1 Interrupt 0 */
|
||||
.word FDCAN1_IT1_IRQHandler /* FDCAN1 Interrupt 1 */
|
||||
.word FDCAN2_IT0_IRQHandler /* FDCAN2 Interrupt 0 */
|
||||
.word FDCAN2_IT1_IRQHandler /* FDCAN2 Interrupt 1 */
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak PVD_PVM_IRQHandler
|
||||
.thumb_set PVD_PVM_IRQHandler,Default_Handler
|
||||
|
||||
.weak DTS_IRQHandler
|
||||
.thumb_set DTS_IRQHandler,Default_Handler
|
||||
|
||||
.weak IWDG_IRQHandler
|
||||
.thumb_set IWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak WWDG_IRQHandler
|
||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_IRQHandler
|
||||
.thumb_set RCC_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak RAMECC_IRQHandler
|
||||
.thumb_set RAMECC_IRQHandler,Default_Handler
|
||||
|
||||
.weak FPU_IRQHandler
|
||||
.thumb_set FPU_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMP_IRQHandler
|
||||
.thumb_set TAMP_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI5_IRQHandler
|
||||
.thumb_set EXTI5_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI6_IRQHandler
|
||||
.thumb_set EXTI6_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI7_IRQHandler
|
||||
.thumb_set EXTI7_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI8_IRQHandler
|
||||
.thumb_set EXTI8_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI9_IRQHandler
|
||||
.thumb_set EXTI9_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI10_IRQHandler
|
||||
.thumb_set EXTI10_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI11_IRQHandler
|
||||
.thumb_set EXTI11_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI12_IRQHandler
|
||||
.thumb_set EXTI12_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI13_IRQHandler
|
||||
.thumb_set EXTI13_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI14_IRQHandler
|
||||
.thumb_set EXTI14_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI15_IRQHandler
|
||||
.thumb_set EXTI15_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_IRQHandler
|
||||
.thumb_set RTC_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAES_IRQHandler
|
||||
.thumb_set SAES_IRQHandler,Default_Handler
|
||||
|
||||
.weak CRYP_IRQHandler
|
||||
.thumb_set CRYP_IRQHandler,Default_Handler
|
||||
|
||||
.weak PKA_IRQHandler
|
||||
.thumb_set PKA_IRQHandler,Default_Handler
|
||||
|
||||
.weak HASH_IRQHandler
|
||||
.thumb_set HASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak RNG_IRQHandler
|
||||
.thumb_set RNG_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC1_2_IRQHandler
|
||||
.thumb_set ADC1_2_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel0_IRQHandler
|
||||
.thumb_set GPDMA1_Channel0_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel1_IRQHandler
|
||||
.thumb_set GPDMA1_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel2_IRQHandler
|
||||
.thumb_set GPDMA1_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel3_IRQHandler
|
||||
.thumb_set GPDMA1_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel4_IRQHandler
|
||||
.thumb_set GPDMA1_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel5_IRQHandler
|
||||
.thumb_set GPDMA1_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel6_IRQHandler
|
||||
.thumb_set GPDMA1_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel7_IRQHandler
|
||||
.thumb_set GPDMA1_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_BRK_IRQHandler
|
||||
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_UP_IRQHandler
|
||||
.thumb_set TIM1_UP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_TRG_COM_IRQHandler
|
||||
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_CC_IRQHandler
|
||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM2_IRQHandler
|
||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM3_IRQHandler
|
||||
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM4_IRQHandler
|
||||
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM5_IRQHandler
|
||||
.thumb_set TIM5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM6_IRQHandler
|
||||
.thumb_set TIM6_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM7_IRQHandler
|
||||
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM9_IRQHandler
|
||||
.thumb_set TIM9_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI3_IRQHandler
|
||||
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI4_IRQHandler
|
||||
.thumb_set SPI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI5_IRQHandler
|
||||
.thumb_set SPI5_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI6_IRQHandler
|
||||
.thumb_set SPI6_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel0_IRQHandler
|
||||
.thumb_set HPDMA1_Channel0_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel1_IRQHandler
|
||||
.thumb_set HPDMA1_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel2_IRQHandler
|
||||
.thumb_set HPDMA1_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel3_IRQHandler
|
||||
.thumb_set HPDMA1_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel4_IRQHandler
|
||||
.thumb_set HPDMA1_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel5_IRQHandler
|
||||
.thumb_set HPDMA1_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel6_IRQHandler
|
||||
.thumb_set HPDMA1_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel7_IRQHandler
|
||||
.thumb_set HPDMA1_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI1_A_IRQHandler
|
||||
.thumb_set SAI1_A_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI1_B_IRQHandler
|
||||
.thumb_set SAI1_B_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI2_A_IRQHandler
|
||||
.thumb_set SAI2_A_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI2_B_IRQHandler
|
||||
.thumb_set SAI2_B_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_EV_IRQHandler
|
||||
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_ER_IRQHandler
|
||||
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_EV_IRQHandler
|
||||
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_ER_IRQHandler
|
||||
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART2_IRQHandler
|
||||
.thumb_set USART2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART3_IRQHandler
|
||||
.thumb_set USART3_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART4_IRQHandler
|
||||
.thumb_set UART4_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART5_IRQHandler
|
||||
.thumb_set UART5_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART7_IRQHandler
|
||||
.thumb_set UART7_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART8_IRQHandler
|
||||
.thumb_set UART8_IRQHandler,Default_Handler
|
||||
|
||||
.weak I3C1_EV_IRQHandler
|
||||
.thumb_set I3C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I3C1_ER_IRQHandler
|
||||
.thumb_set I3C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_IRQHandler
|
||||
.thumb_set OTG_HS_IRQHandler,Default_Handler
|
||||
|
||||
.weak ETH_IRQHandler
|
||||
.thumb_set ETH_IRQHandler,Default_Handler
|
||||
|
||||
.weak CORDIC_IRQHandler
|
||||
.thumb_set CORDIC_IRQHandler,Default_Handler
|
||||
|
||||
.weak GFXTIM_IRQHandler
|
||||
.thumb_set GFXTIM_IRQHandler,Default_Handler
|
||||
|
||||
.weak DCMIPP_IRQHandler
|
||||
.thumb_set DCMIPP_IRQHandler,Default_Handler
|
||||
|
||||
.weak LTDC_IRQHandler
|
||||
.thumb_set LTDC_IRQHandler,Default_Handler
|
||||
|
||||
.weak LTDC_ER_IRQHandler
|
||||
.thumb_set LTDC_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2D_IRQHandler
|
||||
.thumb_set DMA2D_IRQHandler,Default_Handler
|
||||
|
||||
.weak JPEG_IRQHandler
|
||||
.thumb_set JPEG_IRQHandler,Default_Handler
|
||||
|
||||
.weak GFXMMU_IRQHandler
|
||||
.thumb_set GFXMMU_IRQHandler,Default_Handler
|
||||
|
||||
.weak I3C1_WKUP_IRQHandler
|
||||
.thumb_set I3C1_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak MCE1_IRQHandler
|
||||
.thumb_set MCE1_IRQHandler,Default_Handler
|
||||
|
||||
.weak MCE2_IRQHandler
|
||||
.thumb_set MCE2_IRQHandler,Default_Handler
|
||||
|
||||
.weak MCE3_IRQHandler
|
||||
.thumb_set MCE3_IRQHandler,Default_Handler
|
||||
|
||||
.weak XSPI1_IRQHandler
|
||||
.thumb_set XSPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak XSPI2_IRQHandler
|
||||
.thumb_set XSPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak FMC_IRQHandler
|
||||
.thumb_set FMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDMMC1_IRQHandler
|
||||
.thumb_set SDMMC1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDMMC2_IRQHandler
|
||||
.thumb_set SDMMC2_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_FS_IRQHandler
|
||||
.thumb_set OTG_FS_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM12_IRQHandler
|
||||
.thumb_set TIM12_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM13_IRQHandler
|
||||
.thumb_set TIM13_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM14_IRQHandler
|
||||
.thumb_set TIM14_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM15_IRQHandler
|
||||
.thumb_set TIM15_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM16_IRQHandler
|
||||
.thumb_set TIM16_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM17_IRQHandler
|
||||
.thumb_set TIM17_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM1_IRQHandler
|
||||
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM2_IRQHandler
|
||||
.thumb_set LPTIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM3_IRQHandler
|
||||
.thumb_set LPTIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM4_IRQHandler
|
||||
.thumb_set LPTIM4_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM5_IRQHandler
|
||||
.thumb_set LPTIM5_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPDIF_RX_IRQHandler
|
||||
.thumb_set SPDIF_RX_IRQHandler,Default_Handler
|
||||
|
||||
.weak MDIOS_IRQHandler
|
||||
.thumb_set MDIOS_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADF1_FLT0_IRQHandler
|
||||
.thumb_set ADF1_FLT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak CRS_IRQHandler
|
||||
.thumb_set CRS_IRQHandler,Default_Handler
|
||||
|
||||
.weak UCPD1_IRQHandler
|
||||
.thumb_set UCPD1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CEC_IRQHandler
|
||||
.thumb_set CEC_IRQHandler,Default_Handler
|
||||
|
||||
.weak PSSI_IRQHandler
|
||||
.thumb_set PSSI_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPUART1_IRQHandler
|
||||
.thumb_set LPUART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak WAKEUP_PIN_IRQHandler
|
||||
.thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel8_IRQHandler
|
||||
.thumb_set GPDMA1_Channel8_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel9_IRQHandler
|
||||
.thumb_set GPDMA1_Channel9_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel10_IRQHandler
|
||||
.thumb_set GPDMA1_Channel10_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel11_IRQHandler
|
||||
.thumb_set GPDMA1_Channel11_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel12_IRQHandler
|
||||
.thumb_set GPDMA1_Channel12_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel13_IRQHandler
|
||||
.thumb_set GPDMA1_Channel13_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel14_IRQHandler
|
||||
.thumb_set GPDMA1_Channel14_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel15_IRQHandler
|
||||
.thumb_set GPDMA1_Channel15_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel8_IRQHandler
|
||||
.thumb_set HPDMA1_Channel8_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel9_IRQHandler
|
||||
.thumb_set HPDMA1_Channel9_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel10_IRQHandler
|
||||
.thumb_set HPDMA1_Channel10_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel11_IRQHandler
|
||||
.thumb_set HPDMA1_Channel11_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel12_IRQHandler
|
||||
.thumb_set HPDMA1_Channel12_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel13_IRQHandler
|
||||
.thumb_set HPDMA1_Channel13_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel14_IRQHandler
|
||||
.thumb_set HPDMA1_Channel14_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel15_IRQHandler
|
||||
.thumb_set HPDMA1_Channel15_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPU2D_IRQHandler
|
||||
.thumb_set GPU2D_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPU2D_ER_IRQHandler
|
||||
.thumb_set GPU2D_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak ICACHE_IRQHandler
|
||||
.thumb_set ICACHE_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN1_IT0_IRQHandler
|
||||
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN1_IT1_IRQHandler
|
||||
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN2_IT0_IRQHandler
|
||||
.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN2_IT1_IRQHandler
|
||||
.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SystemInit
|
||||
|
|
@ -1,55 +0,0 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol NONCACHEABLEBUFFER_size = 0x400;
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0800FFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x24071FFF - NONCACHEABLEBUFFER_size;
|
||||
define symbol NONCACHEABLEBUFFER_start = __ICFEDIT_region_RAM_end__ + 1;
|
||||
define symbol NONCACHEABLEBUFFER_end = __ICFEDIT_region_RAM_end__ + NONCACHEABLEBUFFER_size;
|
||||
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define symbol __region_ITCM_start__ = 0x00000000;
|
||||
define symbol __region_ITCM_end__ = 0x0000FFFF;
|
||||
define symbol __region_DTCM_start__ = 0x20000000;
|
||||
define symbol __region_DTCM_end__ = 0x2000FFFF;
|
||||
define symbol __region_SRAMAHB_start__ = 0x30000000;
|
||||
define symbol __region_SRAMAHB_end__ = 0x30007FFF;
|
||||
define symbol __region_BKPSRAM_start__ = 0x38800000;
|
||||
define symbol __region_BKPSRAM_end__ = 0x38800FFF;
|
||||
|
||||
export symbol NONCACHEABLEBUFFER_start;
|
||||
export symbol NONCACHEABLEBUFFER_size;
|
||||
|
||||
export symbol __ICFEDIT_region_ROM_start__;
|
||||
export symbol __ICFEDIT_region_ROM_end__;
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region NONCACHEABLE_region = mem:[from NONCACHEABLEBUFFER_start to NONCACHEABLEBUFFER_end];
|
||||
define region ITCM_region = mem:[from __region_ITCM_start__ to __region_ITCM_end__];
|
||||
define region DTCM_region = mem:[from __region_DTCM_start__ to __region_DTCM_end__];
|
||||
define region SRAMAHB_region = mem:[from __region_SRAMAHB_start__ to __region_SRAMAHB_end__];
|
||||
define region BKPSRAM_region = mem:[from __region_BKPSRAM_start__ to __region_BKPSRAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite };
|
||||
place in NONCACHEABLE_region { section noncacheable_buffer };
|
||||
place in DTCM_region { block CSTACK, block HEAP };
|
||||
|
|
@ -1,55 +0,0 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x24050000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol NONCACHEABLEBUFFER_size = 0x400;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2404FFFF - NONCACHEABLEBUFFER_size;
|
||||
define symbol NONCACHEABLEBUFFER_start = __ICFEDIT_region_RAM_end__ + 1;
|
||||
define symbol NONCACHEABLEBUFFER_end = __ICFEDIT_region_RAM_end__ + NONCACHEABLEBUFFER_size;
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x24050000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x24071FFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define symbol __region_ITCM_start__ = 0x00000000;
|
||||
define symbol __region_ITCM_end__ = 0x0000FFFF;
|
||||
define symbol __region_DTCM_start__ = 0x20000000;
|
||||
define symbol __region_DTCM_end__ = 0x2000FFFF;
|
||||
define symbol __region_SRAMAHB_start__ = 0x30000000;
|
||||
define symbol __region_SRAMAHB_end__ = 0x30007FFF;
|
||||
define symbol __region_BKPSRAM_start__ = 0x38800000;
|
||||
define symbol __region_BKPSRAM_end__ = 0x38800FFF;
|
||||
|
||||
export symbol NONCACHEABLEBUFFER_start;
|
||||
export symbol NONCACHEABLEBUFFER_size;
|
||||
|
||||
export symbol __ICFEDIT_region_ROM_start__;
|
||||
export symbol __ICFEDIT_region_ROM_end__;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region NONCACHEABLE_region = mem:[from NONCACHEABLEBUFFER_start to NONCACHEABLEBUFFER_end];
|
||||
define region ITCM_region = mem:[from __region_ITCM_start__ to __region_ITCM_end__];
|
||||
define region DTCM_region = mem:[from __region_DTCM_start__ to __region_DTCM_end__];
|
||||
define region SRAMAHB_region = mem:[from __region_SRAMAHB_start__ to __region_SRAMAHB_end__];
|
||||
define region BKPSRAM_region = mem:[from __region_BKPSRAM_start__ to __region_BKPSRAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec};
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite };
|
||||
place in NONCACHEABLE_region { section noncacheable_buffer };
|
||||
place in DTCM_region { block CSTACK, block HEAP };
|
||||
|
|
@ -1,55 +0,0 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol NONCACHEABLEBUFFER_size = 0x400;
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0800FFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x24071FFF - NONCACHEABLEBUFFER_size;
|
||||
define symbol NONCACHEABLEBUFFER_start = __ICFEDIT_region_RAM_end__ + 1;
|
||||
define symbol NONCACHEABLEBUFFER_end = __ICFEDIT_region_RAM_end__ + NONCACHEABLEBUFFER_size;
|
||||
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define symbol __region_ITCM_start__ = 0x00000000;
|
||||
define symbol __region_ITCM_end__ = 0x0000FFFF;
|
||||
define symbol __region_DTCM_start__ = 0x20000000;
|
||||
define symbol __region_DTCM_end__ = 0x2000FFFF;
|
||||
define symbol __region_SRAMAHB_start__ = 0x30000000;
|
||||
define symbol __region_SRAMAHB_end__ = 0x30007FFF;
|
||||
define symbol __region_BKPSRAM_start__ = 0x38800000;
|
||||
define symbol __region_BKPSRAM_end__ = 0x38800FFF;
|
||||
|
||||
export symbol NONCACHEABLEBUFFER_start;
|
||||
export symbol NONCACHEABLEBUFFER_size;
|
||||
|
||||
export symbol __ICFEDIT_region_ROM_start__;
|
||||
export symbol __ICFEDIT_region_ROM_end__;
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region NONCACHEABLE_region = mem:[from NONCACHEABLEBUFFER_start to NONCACHEABLEBUFFER_end];
|
||||
define region ITCM_region = mem:[from __region_ITCM_start__ to __region_ITCM_end__];
|
||||
define region DTCM_region = mem:[from __region_DTCM_start__ to __region_DTCM_end__];
|
||||
define region SRAMAHB_region = mem:[from __region_SRAMAHB_start__ to __region_SRAMAHB_end__];
|
||||
define region BKPSRAM_region = mem:[from __region_BKPSRAM_start__ to __region_BKPSRAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite };
|
||||
place in NONCACHEABLE_region { section noncacheable_buffer };
|
||||
place in DTCM_region { block CSTACK, block HEAP };
|
||||
|
|
@ -1,55 +0,0 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x24050000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol NONCACHEABLEBUFFER_size = 0x400;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2404FFFF - NONCACHEABLEBUFFER_size;
|
||||
define symbol NONCACHEABLEBUFFER_start = __ICFEDIT_region_RAM_end__ + 1;
|
||||
define symbol NONCACHEABLEBUFFER_end = __ICFEDIT_region_RAM_end__ + NONCACHEABLEBUFFER_size;
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x24050000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x24071FFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define symbol __region_ITCM_start__ = 0x00000000;
|
||||
define symbol __region_ITCM_end__ = 0x0000FFFF;
|
||||
define symbol __region_DTCM_start__ = 0x20000000;
|
||||
define symbol __region_DTCM_end__ = 0x2000FFFF;
|
||||
define symbol __region_SRAMAHB_start__ = 0x30000000;
|
||||
define symbol __region_SRAMAHB_end__ = 0x30007FFF;
|
||||
define symbol __region_BKPSRAM_start__ = 0x38800000;
|
||||
define symbol __region_BKPSRAM_end__ = 0x38800FFF;
|
||||
|
||||
export symbol NONCACHEABLEBUFFER_start;
|
||||
export symbol NONCACHEABLEBUFFER_size;
|
||||
|
||||
export symbol __ICFEDIT_region_ROM_start__;
|
||||
export symbol __ICFEDIT_region_ROM_end__;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region NONCACHEABLE_region = mem:[from NONCACHEABLEBUFFER_start to NONCACHEABLEBUFFER_end];
|
||||
define region ITCM_region = mem:[from __region_ITCM_start__ to __region_ITCM_end__];
|
||||
define region DTCM_region = mem:[from __region_DTCM_start__ to __region_DTCM_end__];
|
||||
define region SRAMAHB_region = mem:[from __region_SRAMAHB_start__ to __region_SRAMAHB_end__];
|
||||
define region BKPSRAM_region = mem:[from __region_BKPSRAM_start__ to __region_BKPSRAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec};
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite };
|
||||
place in NONCACHEABLE_region { section noncacheable_buffer };
|
||||
place in DTCM_region { block CSTACK, block HEAP };
|
||||
|
|
@ -1,61 +0,0 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x70000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x70000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x77FFFFFF;
|
||||
define symbol NONCACHEABLEBUFFER_size = 0x400;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x24071FFF - NONCACHEABLEBUFFER_size;
|
||||
define symbol NONCACHEABLEBUFFER_start = __ICFEDIT_region_RAM_end__ + 1;
|
||||
define symbol NONCACHEABLEBUFFER_end = __ICFEDIT_region_RAM_end__ + NONCACHEABLEBUFFER_size;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define symbol __region_ITCM_start__ = 0x00000000;
|
||||
define symbol __region_ITCM_end__ = 0x0000FFFF;
|
||||
define symbol __region_DTCM_start__ = 0x20000000;
|
||||
define symbol __region_DTCM_end__ = 0x2000FFFF;
|
||||
define symbol __region_SRAMAHB_start__ = 0x30000000;
|
||||
define symbol __region_SRAMAHB_end__ = 0x30007FFF;
|
||||
define symbol __region_BKPSRAM_start__ = 0x38800000;
|
||||
define symbol __region_BKPSRAM_end__ = 0x38800FFF;
|
||||
define symbol __region_EXTRAM_start__ = 0x90000000;
|
||||
define symbol __region_EXTRAM_end__ = 0x91FFFFFF;
|
||||
|
||||
export symbol NONCACHEABLEBUFFER_start;
|
||||
export symbol NONCACHEABLEBUFFER_size;
|
||||
|
||||
export symbol __ICFEDIT_region_ROM_start__;
|
||||
export symbol __ICFEDIT_region_ROM_end__;
|
||||
|
||||
export symbol __region_EXTRAM_start__;
|
||||
export symbol __region_EXTRAM_end__;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region EXTRAM_region = mem:[from __region_EXTRAM_start__ to __region_EXTRAM_end__];
|
||||
define region NONCACHEABLE_region = mem:[from NONCACHEABLEBUFFER_start to NONCACHEABLEBUFFER_end];
|
||||
define region ITCM_region = mem:[from __region_ITCM_start__ to __region_ITCM_end__];
|
||||
define region DTCM_region = mem:[from __region_DTCM_start__ to __region_DTCM_end__];
|
||||
define region SRAMAHB_region = mem:[from __region_SRAMAHB_start__ to __region_SRAMAHB_end__];
|
||||
define region BKPSRAM_region = mem:[from __region_BKPSRAM_start__ to __region_BKPSRAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite };
|
||||
place in NONCACHEABLE_region { section noncacheable_buffer };
|
||||
place in DTCM_region { block CSTACK, block HEAP };
|
||||
|
|
@ -1,55 +0,0 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x90000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x90000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x97FFFFFF;
|
||||
define symbol NONCACHEABLEBUFFER_size = 0x400;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x24071FFF - NONCACHEABLEBUFFER_size;
|
||||
define symbol NONCACHEABLEBUFFER_start = __ICFEDIT_region_RAM_end__ + 1;
|
||||
define symbol NONCACHEABLEBUFFER_end = __ICFEDIT_region_RAM_end__ + NONCACHEABLEBUFFER_size;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define symbol __region_ITCM_start__ = 0x00000000;
|
||||
define symbol __region_ITCM_end__ = 0x0000FFFF;
|
||||
define symbol __region_DTCM_start__ = 0x20000000;
|
||||
define symbol __region_DTCM_end__ = 0x2000FFFF;
|
||||
define symbol __region_SRAMAHB_start__ = 0x30000000;
|
||||
define symbol __region_SRAMAHB_end__ = 0x30007FFF;
|
||||
define symbol __region_BKPSRAM_start__ = 0x38800000;
|
||||
define symbol __region_BKPSRAM_end__ = 0x38800FFF;
|
||||
|
||||
export symbol NONCACHEABLEBUFFER_start;
|
||||
export symbol NONCACHEABLEBUFFER_size;
|
||||
|
||||
export symbol __ICFEDIT_region_ROM_start__;
|
||||
export symbol __ICFEDIT_region_ROM_end__;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region NONCACHEABLE_region = mem:[from NONCACHEABLEBUFFER_start to NONCACHEABLEBUFFER_end];
|
||||
define region ITCM_region = mem:[from __region_ITCM_start__ to __region_ITCM_end__];
|
||||
define region DTCM_region = mem:[from __region_DTCM_start__ to __region_DTCM_end__];
|
||||
define region SRAMAHB_region = mem:[from __region_SRAMAHB_start__ to __region_SRAMAHB_end__];
|
||||
define region BKPSRAM_region = mem:[from __region_BKPSRAM_start__ to __region_BKPSRAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite };
|
||||
place in NONCACHEABLE_region { section noncacheable_buffer };
|
||||
place in DTCM_region { block CSTACK, block HEAP };
|
||||
|
|
@ -1,62 +0,0 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x90000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x90000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x97FFFFFF;
|
||||
define symbol NONCACHEABLEBUFFER_size = 0x400;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x24071FFF - NONCACHEABLEBUFFER_size;
|
||||
define symbol NONCACHEABLEBUFFER_start = __ICFEDIT_region_RAM_end__ + 1;
|
||||
define symbol NONCACHEABLEBUFFER_end = __ICFEDIT_region_RAM_end__ + NONCACHEABLEBUFFER_size;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define symbol __region_ITCM_start__ = 0x00000000;
|
||||
define symbol __region_ITCM_end__ = 0x0000FFFF;
|
||||
define symbol __region_DTCM_start__ = 0x20000000;
|
||||
define symbol __region_DTCM_end__ = 0x2000FFFF;
|
||||
define symbol __region_SRAMAHB_start__ = 0x30000000;
|
||||
define symbol __region_SRAMAHB_end__ = 0x30007FFF;
|
||||
define symbol __region_BKPSRAM_start__ = 0x38800000;
|
||||
define symbol __region_BKPSRAM_end__ = 0x38800FFF;
|
||||
define symbol __region_EXTRAM_start__ = 0x70000000;
|
||||
define symbol __region_EXTRAM_end__ = 0x71FFFFFF;
|
||||
|
||||
export symbol NONCACHEABLEBUFFER_start;
|
||||
export symbol NONCACHEABLEBUFFER_size;
|
||||
|
||||
export symbol __ICFEDIT_region_ROM_start__;
|
||||
export symbol __ICFEDIT_region_ROM_end__;
|
||||
|
||||
export symbol __region_EXTRAM_start__;
|
||||
export symbol __region_EXTRAM_end__;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region EXTRAM_region = mem:[from __region_EXTRAM_start__ to __region_EXTRAM_end__];
|
||||
define region NONCACHEABLE_region = mem:[from NONCACHEABLEBUFFER_start to NONCACHEABLEBUFFER_end];
|
||||
define region ITCM_region = mem:[from __region_ITCM_start__ to __region_ITCM_end__];
|
||||
define region DTCM_region = mem:[from __region_DTCM_start__ to __region_DTCM_end__];
|
||||
define region SRAMAHB_region = mem:[from __region_SRAMAHB_start__ to __region_SRAMAHB_end__];
|
||||
define region BKPSRAM_region = mem:[from __region_BKPSRAM_start__ to __region_BKPSRAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite };
|
||||
place in NONCACHEABLE_region { section noncacheable_buffer };
|
||||
place in DTCM_region { block CSTACK, block HEAP };
|
||||
|
|
@ -1,56 +0,0 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x70000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x70000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x77FFFFFF;
|
||||
define symbol NONCACHEABLEBUFFER_size = 0x400;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x24071FFF - NONCACHEABLEBUFFER_size;
|
||||
define symbol NONCACHEABLEBUFFER_start = __ICFEDIT_region_RAM_end__ + 1;
|
||||
define symbol NONCACHEABLEBUFFER_end = __ICFEDIT_region_RAM_end__ + NONCACHEABLEBUFFER_size;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define symbol __region_ITCM_start__ = 0x00000000;
|
||||
define symbol __region_ITCM_end__ = 0x0000FFFF;
|
||||
define symbol __region_DTCM_start__ = 0x20000000;
|
||||
define symbol __region_DTCM_end__ = 0x2000FFFF;
|
||||
define symbol __region_SRAMAHB_start__ = 0x30000000;
|
||||
define symbol __region_SRAMAHB_end__ = 0x30007FFF;
|
||||
define symbol __region_BKPSRAM_start__ = 0x38800000;
|
||||
define symbol __region_BKPSRAM_end__ = 0x38800FFF;
|
||||
|
||||
export symbol NONCACHEABLEBUFFER_start;
|
||||
export symbol NONCACHEABLEBUFFER_size;
|
||||
|
||||
export symbol __ICFEDIT_region_ROM_start__;
|
||||
export symbol __ICFEDIT_region_ROM_end__;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region NONCACHEABLE_region = mem:[from NONCACHEABLEBUFFER_start to NONCACHEABLEBUFFER_end];
|
||||
define region ITCM_region = mem:[from __region_ITCM_start__ to __region_ITCM_end__];
|
||||
define region DTCM_region = mem:[from __region_DTCM_start__ to __region_DTCM_end__];
|
||||
define region SRAMAHB_region = mem:[from __region_SRAMAHB_start__ to __region_SRAMAHB_end__];
|
||||
define region BKPSRAM_region = mem:[from __region_BKPSRAM_start__ to __region_BKPSRAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite };
|
||||
place in NONCACHEABLE_region { section noncacheable_buffer };
|
||||
place in DTCM_region { block CSTACK, block HEAP };
|
||||
|
|
@ -1,34 +0,0 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_1.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
|
||||
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_IRAM1_start__ = 0x00000040;
|
||||
define symbol __ICFEDIT_region_IRAM1_end__ = 0x0000EFFF;
|
||||
define symbol __ICFEDIT_region_IRAM2_start__ = 0x0000F000;
|
||||
define symbol __ICFEDIT_region_IRAM2_end__ = 0x0000FFFF;
|
||||
define symbol __ICFEDIT_region_DTCM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_DTCM_end__ = 0x2000FFFF;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x8; /* not used defined the min size */
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region IRAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
|
||||
define region IRAM_region_2 = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
|
||||
define region DTCM_region = mem:[from __ICFEDIT_region_DTCM_start__ to __ICFEDIT_region_DTCM_end__];
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
do not initialize { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { section .intvec };
|
||||
place at start of IRAM_region { readonly };
|
||||
place in IRAM_region { block RamTop with fixed order { readwrite, block CSTACK, block HEAP }};
|
||||
place in IRAM_region_2 { zi};
|
||||
place at start of DTCM_region { section RAMBUFFER_END };
|
||||
place at end of DTCM_region { section RAMBUFFER_START };
|
||||
|
|
@ -1,22 +0,0 @@
|
|||
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20010000;
|
||||
|
||||
define symbol __ICFEDIT_region_RAM2_start__ = 0x24020000;
|
||||
define symbol __ICFEDIT_region_RAM2_end__ = 0x24040000;
|
||||
|
||||
export symbol __ICFEDIT_region_RAM_end__;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region RAM2_region = mem:[from __ICFEDIT_region_RAM2_start__ to __ICFEDIT_region_RAM2_end__];
|
||||
define region Info_region = mem:[from 0 to 0x3000];
|
||||
|
||||
define block RAM_BLOCK with fixed order {readonly code, readonly data, readwrite };
|
||||
define block StorageInfo_BLOCK with fixed order { readonly data object stm32_device_Info.o};
|
||||
|
||||
place in RAM_region { block RAM_BLOCK};
|
||||
place in RAM2_region { zi };
|
||||
place in Info_region { block StorageInfo_BLOCK };
|
||||
|
||||
do not initialize { section .info, readwrite };
|
||||
|
|
@ -1,55 +0,0 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x24050000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol NONCACHEABLEBUFFER_size = 0x400;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2404FFFF - NONCACHEABLEBUFFER_size;
|
||||
define symbol NONCACHEABLEBUFFER_start = __ICFEDIT_region_RAM_end__ + 1;
|
||||
define symbol NONCACHEABLEBUFFER_end = __ICFEDIT_region_RAM_end__ + NONCACHEABLEBUFFER_size;
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x24050000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x24071FFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define symbol __region_ITCM_start__ = 0x00000000;
|
||||
define symbol __region_ITCM_end__ = 0x0000FFFF;
|
||||
define symbol __region_DTCM_start__ = 0x20000000;
|
||||
define symbol __region_DTCM_end__ = 0x2000FFFF;
|
||||
define symbol __region_SRAMAHB_start__ = 0x30000000;
|
||||
define symbol __region_SRAMAHB_end__ = 0x30007FFF;
|
||||
define symbol __region_BKPSRAM_start__ = 0x38800000;
|
||||
define symbol __region_BKPSRAM_end__ = 0x38800FFF;
|
||||
|
||||
export symbol NONCACHEABLEBUFFER_start;
|
||||
export symbol NONCACHEABLEBUFFER_size;
|
||||
|
||||
export symbol __ICFEDIT_region_ROM_start__;
|
||||
export symbol __ICFEDIT_region_ROM_end__;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region NONCACHEABLE_region = mem:[from NONCACHEABLEBUFFER_start to NONCACHEABLEBUFFER_end];
|
||||
define region ITCM_region = mem:[from __region_ITCM_start__ to __region_ITCM_end__];
|
||||
define region DTCM_region = mem:[from __region_DTCM_start__ to __region_DTCM_end__];
|
||||
define region SRAMAHB_region = mem:[from __region_SRAMAHB_start__ to __region_SRAMAHB_end__];
|
||||
define region BKPSRAM_region = mem:[from __region_BKPSRAM_start__ to __region_BKPSRAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec};
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite };
|
||||
place in NONCACHEABLE_region { section noncacheable_buffer };
|
||||
place in DTCM_region { block CSTACK, block HEAP };
|
||||
|
|
@ -1,55 +0,0 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol NONCACHEABLEBUFFER_size = 0x400;
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0800FFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x24071FFF - NONCACHEABLEBUFFER_size;
|
||||
define symbol NONCACHEABLEBUFFER_start = __ICFEDIT_region_RAM_end__ + 1;
|
||||
define symbol NONCACHEABLEBUFFER_end = __ICFEDIT_region_RAM_end__ + NONCACHEABLEBUFFER_size;
|
||||
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define symbol __region_ITCM_start__ = 0x00000000;
|
||||
define symbol __region_ITCM_end__ = 0x0000FFFF;
|
||||
define symbol __region_DTCM_start__ = 0x20000000;
|
||||
define symbol __region_DTCM_end__ = 0x2000FFFF;
|
||||
define symbol __region_SRAMAHB_start__ = 0x30000000;
|
||||
define symbol __region_SRAMAHB_end__ = 0x30007FFF;
|
||||
define symbol __region_BKPSRAM_start__ = 0x38800000;
|
||||
define symbol __region_BKPSRAM_end__ = 0x38800FFF;
|
||||
|
||||
export symbol NONCACHEABLEBUFFER_start;
|
||||
export symbol NONCACHEABLEBUFFER_size;
|
||||
|
||||
export symbol __ICFEDIT_region_ROM_start__;
|
||||
export symbol __ICFEDIT_region_ROM_end__;
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region NONCACHEABLE_region = mem:[from NONCACHEABLEBUFFER_start to NONCACHEABLEBUFFER_end];
|
||||
define region ITCM_region = mem:[from __region_ITCM_start__ to __region_ITCM_end__];
|
||||
define region DTCM_region = mem:[from __region_DTCM_start__ to __region_DTCM_end__];
|
||||
define region SRAMAHB_region = mem:[from __region_SRAMAHB_start__ to __region_SRAMAHB_end__];
|
||||
define region BKPSRAM_region = mem:[from __region_BKPSRAM_start__ to __region_BKPSRAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite };
|
||||
place in NONCACHEABLE_region { section noncacheable_buffer };
|
||||
place in DTCM_region { block CSTACK, block HEAP };
|
||||
|
|
@ -1,55 +0,0 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x24050000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol NONCACHEABLEBUFFER_size = 0x400;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2404FFFF - NONCACHEABLEBUFFER_size;
|
||||
define symbol NONCACHEABLEBUFFER_start = __ICFEDIT_region_RAM_end__ + 1;
|
||||
define symbol NONCACHEABLEBUFFER_end = __ICFEDIT_region_RAM_end__ + NONCACHEABLEBUFFER_size;
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x24050000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x24071FFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define symbol __region_ITCM_start__ = 0x00000000;
|
||||
define symbol __region_ITCM_end__ = 0x0000FFFF;
|
||||
define symbol __region_DTCM_start__ = 0x20000000;
|
||||
define symbol __region_DTCM_end__ = 0x2000FFFF;
|
||||
define symbol __region_SRAMAHB_start__ = 0x30000000;
|
||||
define symbol __region_SRAMAHB_end__ = 0x30007FFF;
|
||||
define symbol __region_BKPSRAM_start__ = 0x38800000;
|
||||
define symbol __region_BKPSRAM_end__ = 0x38800FFF;
|
||||
|
||||
export symbol NONCACHEABLEBUFFER_start;
|
||||
export symbol NONCACHEABLEBUFFER_size;
|
||||
|
||||
export symbol __ICFEDIT_region_ROM_start__;
|
||||
export symbol __ICFEDIT_region_ROM_end__;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region NONCACHEABLE_region = mem:[from NONCACHEABLEBUFFER_start to NONCACHEABLEBUFFER_end];
|
||||
define region ITCM_region = mem:[from __region_ITCM_start__ to __region_ITCM_end__];
|
||||
define region DTCM_region = mem:[from __region_DTCM_start__ to __region_DTCM_end__];
|
||||
define region SRAMAHB_region = mem:[from __region_SRAMAHB_start__ to __region_SRAMAHB_end__];
|
||||
define region BKPSRAM_region = mem:[from __region_BKPSRAM_start__ to __region_BKPSRAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec};
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite };
|
||||
place in NONCACHEABLE_region { section noncacheable_buffer };
|
||||
place in DTCM_region { block CSTACK, block HEAP };
|
||||
|
|
@ -1,55 +0,0 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol NONCACHEABLEBUFFER_size = 0x400;
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0800FFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x24071FFF - NONCACHEABLEBUFFER_size;
|
||||
define symbol NONCACHEABLEBUFFER_start = __ICFEDIT_region_RAM_end__ + 1;
|
||||
define symbol NONCACHEABLEBUFFER_end = __ICFEDIT_region_RAM_end__ + NONCACHEABLEBUFFER_size;
|
||||
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define symbol __region_ITCM_start__ = 0x00000000;
|
||||
define symbol __region_ITCM_end__ = 0x0000FFFF;
|
||||
define symbol __region_DTCM_start__ = 0x20000000;
|
||||
define symbol __region_DTCM_end__ = 0x2000FFFF;
|
||||
define symbol __region_SRAMAHB_start__ = 0x30000000;
|
||||
define symbol __region_SRAMAHB_end__ = 0x30007FFF;
|
||||
define symbol __region_BKPSRAM_start__ = 0x38800000;
|
||||
define symbol __region_BKPSRAM_end__ = 0x38800FFF;
|
||||
|
||||
export symbol NONCACHEABLEBUFFER_start;
|
||||
export symbol NONCACHEABLEBUFFER_size;
|
||||
|
||||
export symbol __ICFEDIT_region_ROM_start__;
|
||||
export symbol __ICFEDIT_region_ROM_end__;
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region NONCACHEABLE_region = mem:[from NONCACHEABLEBUFFER_start to NONCACHEABLEBUFFER_end];
|
||||
define region ITCM_region = mem:[from __region_ITCM_start__ to __region_ITCM_end__];
|
||||
define region DTCM_region = mem:[from __region_DTCM_start__ to __region_DTCM_end__];
|
||||
define region SRAMAHB_region = mem:[from __region_SRAMAHB_start__ to __region_SRAMAHB_end__];
|
||||
define region BKPSRAM_region = mem:[from __region_BKPSRAM_start__ to __region_BKPSRAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite };
|
||||
place in NONCACHEABLE_region { section noncacheable_buffer };
|
||||
place in DTCM_region { block CSTACK, block HEAP };
|
||||
|
|
@ -1,55 +0,0 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x24050000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol NONCACHEABLEBUFFER_size = 0x400;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2404FFFF - NONCACHEABLEBUFFER_size;
|
||||
define symbol NONCACHEABLEBUFFER_start = __ICFEDIT_region_RAM_end__ + 1;
|
||||
define symbol NONCACHEABLEBUFFER_end = __ICFEDIT_region_RAM_end__ + NONCACHEABLEBUFFER_size;
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x24050000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x24071FFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define symbol __region_ITCM_start__ = 0x00000000;
|
||||
define symbol __region_ITCM_end__ = 0x0000FFFF;
|
||||
define symbol __region_DTCM_start__ = 0x20000000;
|
||||
define symbol __region_DTCM_end__ = 0x2000FFFF;
|
||||
define symbol __region_SRAMAHB_start__ = 0x30000000;
|
||||
define symbol __region_SRAMAHB_end__ = 0x30007FFF;
|
||||
define symbol __region_BKPSRAM_start__ = 0x38800000;
|
||||
define symbol __region_BKPSRAM_end__ = 0x38800FFF;
|
||||
|
||||
export symbol NONCACHEABLEBUFFER_start;
|
||||
export symbol NONCACHEABLEBUFFER_size;
|
||||
|
||||
export symbol __ICFEDIT_region_ROM_start__;
|
||||
export symbol __ICFEDIT_region_ROM_end__;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region NONCACHEABLE_region = mem:[from NONCACHEABLEBUFFER_start to NONCACHEABLEBUFFER_end];
|
||||
define region ITCM_region = mem:[from __region_ITCM_start__ to __region_ITCM_end__];
|
||||
define region DTCM_region = mem:[from __region_DTCM_start__ to __region_DTCM_end__];
|
||||
define region SRAMAHB_region = mem:[from __region_SRAMAHB_start__ to __region_SRAMAHB_end__];
|
||||
define region BKPSRAM_region = mem:[from __region_BKPSRAM_start__ to __region_BKPSRAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec};
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite };
|
||||
place in NONCACHEABLE_region { section noncacheable_buffer };
|
||||
place in DTCM_region { block CSTACK, block HEAP };
|
||||
|
|
@ -1,981 +0,0 @@
|
|||
;********************************************************************************
|
||||
;* File Name : startup_stm32h7r3xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : STM32H7R3xx Devices vector
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == _iar_program_start,
|
||||
;* - Set the vector table entries with the exceptions ISR
|
||||
;* address.
|
||||
;* - Branches to main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M7 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* Copyright (c) 2022 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;*******************************************************************************
|
||||
;
|
||||
;
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
;
|
||||
; Cortex-M version
|
||||
;
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
PUBLIC __Vectors
|
||||
PUBLIC __Vectors_End
|
||||
PUBLIC __Vectors_Size
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD PVD_PVM_IRQHandler ; PVD/PVM through EXTI Line detection
|
||||
DCD 0 ; Reserved
|
||||
DCD DTS_IRQHandler ; Digital Temperature Sensor
|
||||
DCD IWDG_IRQHandler ; Internal Watchdog
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD RCC_IRQHandler ; RCC global interrupts through EXTI Line detection
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD FLASH_IRQHandler ; FLASH interrupts
|
||||
DCD RAMECC_IRQHandler ; RAMECC interrupts
|
||||
DCD FPU_IRQHandler ; FPU
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD TAMP_IRQHandler ; Tamper and TimeStamp interrupts through EXTI Line detection
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD EXTI0_IRQHandler ; EXTI Line0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line4
|
||||
DCD EXTI5_IRQHandler ; EXTI Line5
|
||||
DCD EXTI6_IRQHandler ; EXTI Line6
|
||||
DCD EXTI7_IRQHandler ; EXTI Line7
|
||||
DCD EXTI8_IRQHandler ; EXTI Line8
|
||||
DCD EXTI9_IRQHandler ; EXTI Line9
|
||||
DCD EXTI10_IRQHandler ; EXTI Line10
|
||||
DCD EXTI11_IRQHandler ; EXTI Line11
|
||||
DCD EXTI12_IRQHandler ; EXTI Line12
|
||||
DCD EXTI13_IRQHandler ; EXTI Line13
|
||||
DCD EXTI14_IRQHandler ; EXTI Line14
|
||||
DCD EXTI15_IRQHandler ; EXTI Line15
|
||||
DCD RTC_IRQHandler ; RTC wakeup and alarm interrupts through EXTI Line detection
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PKA_IRQHandler ; PKA
|
||||
DCD HASH_IRQHandler ; HASH
|
||||
DCD RNG_IRQHandler ; RNG
|
||||
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
|
||||
DCD GPDMA1_Channel0_IRQHandler ; GPDMA1 Channel 0
|
||||
DCD GPDMA1_Channel1_IRQHandler ; GPDMA1 Channel 1
|
||||
DCD GPDMA1_Channel2_IRQHandler ; GPDMA1 Channel 2
|
||||
DCD GPDMA1_Channel3_IRQHandler ; GPDMA1 Channel 3
|
||||
DCD GPDMA1_Channel4_IRQHandler ; GPDMA1 Channel 4
|
||||
DCD GPDMA1_Channel5_IRQHandler ; GPDMA1 Channel 5
|
||||
DCD GPDMA1_Channel6_IRQHandler ; GPDMA1 Channel 6
|
||||
DCD GPDMA1_Channel7_IRQHandler ; GPDMA1 Channel 7
|
||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break
|
||||
DCD TIM1_UP_IRQHandler ; TIM1 Update
|
||||
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD TIM5_IRQHandler ; TIM5
|
||||
DCD TIM6_IRQHandler ; TIM6
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD TIM9_IRQHandler ; TIM9
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD SPI4_IRQHandler ; SPI4
|
||||
DCD SPI5_IRQHandler ; SPI5
|
||||
DCD SPI6_IRQHandler ; SPI6
|
||||
DCD HPDMA1_Channel0_IRQHandler ; HPDMA1 Channel 0
|
||||
DCD HPDMA1_Channel1_IRQHandler ; HPDMA1 Channel 1
|
||||
DCD HPDMA1_Channel2_IRQHandler ; HPDMA1 Channel 2
|
||||
DCD HPDMA1_Channel3_IRQHandler ; HPDMA1 Channel 3
|
||||
DCD HPDMA1_Channel4_IRQHandler ; HPDMA1 Channel 4
|
||||
DCD HPDMA1_Channel5_IRQHandler ; HPDMA1 Channel 5
|
||||
DCD HPDMA1_Channel6_IRQHandler ; HPDMA1 Channel 6
|
||||
DCD HPDMA1_Channel7_IRQHandler ; HPDMA1 Channel 7
|
||||
DCD SAI1_A_IRQHandler ; Serial Audio Interface 1 block A
|
||||
DCD SAI1_B_IRQHandler ; Serial Audio Interface 1 block B
|
||||
DCD SAI2_A_IRQHandler ; Serial Audio Interface 2 block A
|
||||
DCD SAI2_B_IRQHandler ; Serial Audio Interface 2 block B
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD I2C3_EV_IRQHandler ; I2C3 Event
|
||||
DCD I2C3_ER_IRQHandler ; I2C3 Error
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD UART4_IRQHandler ; UART4
|
||||
DCD UART5_IRQHandler ; UART5
|
||||
DCD UART7_IRQHandler ; UART7
|
||||
DCD UART8_IRQHandler ; UART8
|
||||
DCD I3C1_EV_IRQHandler ; I3C1 Event
|
||||
DCD I3C1_ER_IRQHandler ; I3C1 Error
|
||||
DCD OTG_HS_IRQHandler ; USB OTG HS
|
||||
DCD ETH_IRQHandler ; Ethernet
|
||||
DCD CORDIC_IRQHandler ; CORDIC
|
||||
DCD GFXTIM_IRQHandler ; GFXTIM
|
||||
DCD DCMIPP_IRQHandler ; DCMIPP
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD DMA2D_IRQHandler ; DMA2D
|
||||
DCD JPEG_IRQHandler ; JPEG
|
||||
DCD GFXMMU_IRQHandler ; GFXMMU
|
||||
DCD I3C1_WKUP_IRQHandler ; I3C1 wakeup
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD XSPI1_IRQHandler ; XSPI1
|
||||
DCD XSPI2_IRQHandler ; XSPI2
|
||||
DCD FMC_IRQHandler ; FMC
|
||||
DCD SDMMC1_IRQHandler ; SDMMC1
|
||||
DCD SDMMC2_IRQHandler ; SDMMC2
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD OTG_FS_IRQHandler ; USB OTG FS
|
||||
DCD TIM12_IRQHandler ; TIM12
|
||||
DCD TIM13_IRQHandler ; TIM13
|
||||
DCD TIM14_IRQHandler ; TIM14
|
||||
DCD TIM15_IRQHandler ; TIM15
|
||||
DCD TIM16_IRQHandler ; TIM16
|
||||
DCD TIM17_IRQHandler ; TIM17
|
||||
DCD LPTIM1_IRQHandler ; LP TIM1
|
||||
DCD LPTIM2_IRQHandler ; LP TIM2
|
||||
DCD LPTIM3_IRQHandler ; LP TIM3
|
||||
DCD LPTIM4_IRQHandler ; LP TIM4
|
||||
DCD LPTIM5_IRQHandler ; LP TIM5
|
||||
DCD SPDIF_RX_IRQHandler ; SPDIF_RX
|
||||
DCD MDIOS_IRQHandler ; MDIOS
|
||||
DCD ADF1_FLT0_IRQHandler ; ADF1 Filter 0
|
||||
DCD CRS_IRQHandler ; CRS
|
||||
DCD UCPD1_IRQHandler ; UCPD1
|
||||
DCD CEC_IRQHandler ; HDMI_CEC
|
||||
DCD PSSI_IRQHandler ; PSSI
|
||||
DCD LPUART1_IRQHandler ; LP UART1
|
||||
DCD WAKEUP_PIN_IRQHandler ; Wake-up pins interrupt
|
||||
DCD GPDMA1_Channel8_IRQHandler ; GPDMA1 Channel 8
|
||||
DCD GPDMA1_Channel9_IRQHandler ; GPDMA1 Channel 9
|
||||
DCD GPDMA1_Channel10_IRQHandler ; GPDMA1 Channel 10
|
||||
DCD GPDMA1_Channel11_IRQHandler ; GPDMA1 Channel 11
|
||||
DCD GPDMA1_Channel12_IRQHandler ; GPDMA1 Channel 12
|
||||
DCD GPDMA1_Channel13_IRQHandler ; GPDMA1 Channel 13
|
||||
DCD GPDMA1_Channel14_IRQHandler ; GPDMA1 Channel 14
|
||||
DCD GPDMA1_Channel15_IRQHandler ; GPDMA1 Channel 15
|
||||
DCD HPDMA1_Channel8_IRQHandler ; HPDMA1 Channel 8
|
||||
DCD HPDMA1_Channel9_IRQHandler ; HPDMA1 Channel 9
|
||||
DCD HPDMA1_Channel10_IRQHandler ; HPDMA1 Channel 10
|
||||
DCD HPDMA1_Channel11_IRQHandler ; HPDMA1 Channel 11
|
||||
DCD HPDMA1_Channel12_IRQHandler ; HPDMA1 Channel 12
|
||||
DCD HPDMA1_Channel13_IRQHandler ; HPDMA1 Channel 13
|
||||
DCD HPDMA1_Channel14_IRQHandler ; HPDMA1 Channel 14
|
||||
DCD HPDMA1_Channel15_IRQHandler ; HPDMA1 Channel 15
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 Interrupt 0
|
||||
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 Interrupt 1
|
||||
DCD FDCAN2_IT0_IRQHandler ; FDCAN2 Interrupt 0
|
||||
DCD FDCAN2_IT1_IRQHandler ; FDCAN2 Interrupt 1
|
||||
__Vectors_End
|
||||
|
||||
__Vectors EQU __vector_table
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||
Reset_Handler
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
NMI_Handler
|
||||
B NMI_Handler
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HardFault_Handler
|
||||
B HardFault_Handler
|
||||
|
||||
PUBWEAK MemManage_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
MemManage_Handler
|
||||
B MemManage_Handler
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
BusFault_Handler
|
||||
B BusFault_Handler
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UsageFault_Handler
|
||||
B UsageFault_Handler
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SVC_Handler
|
||||
B SVC_Handler
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DebugMon_Handler
|
||||
B DebugMon_Handler
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PendSV_Handler
|
||||
B PendSV_Handler
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SysTick_Handler
|
||||
B SysTick_Handler
|
||||
|
||||
PUBWEAK PVD_PVM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PVD_PVM_IRQHandler
|
||||
B PVD_PVM_IRQHandler
|
||||
|
||||
PUBWEAK DTS_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DTS_IRQHandler
|
||||
B DTS_IRQHandler
|
||||
|
||||
PUBWEAK IWDG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IWDG_IRQHandler
|
||||
B IWDG_IRQHandler
|
||||
|
||||
PUBWEAK WWDG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
WWDG_IRQHandler
|
||||
B WWDG_IRQHandler
|
||||
|
||||
PUBWEAK RCC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RCC_IRQHandler
|
||||
B RCC_IRQHandler
|
||||
|
||||
PUBWEAK FLASH_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FLASH_IRQHandler
|
||||
B FLASH_IRQHandler
|
||||
|
||||
PUBWEAK RAMECC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RAMECC_IRQHandler
|
||||
B RAMECC_IRQHandler
|
||||
|
||||
PUBWEAK FPU_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FPU_IRQHandler
|
||||
B FPU_IRQHandler
|
||||
|
||||
PUBWEAK TAMP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TAMP_IRQHandler
|
||||
B TAMP_IRQHandler
|
||||
|
||||
PUBWEAK EXTI0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI0_IRQHandler
|
||||
B EXTI0_IRQHandler
|
||||
|
||||
PUBWEAK EXTI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI1_IRQHandler
|
||||
B EXTI1_IRQHandler
|
||||
|
||||
PUBWEAK EXTI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI2_IRQHandler
|
||||
B EXTI2_IRQHandler
|
||||
|
||||
PUBWEAK EXTI3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI3_IRQHandler
|
||||
B EXTI3_IRQHandler
|
||||
|
||||
PUBWEAK EXTI4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI4_IRQHandler
|
||||
B EXTI4_IRQHandler
|
||||
|
||||
PUBWEAK EXTI5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI5_IRQHandler
|
||||
B EXTI5_IRQHandler
|
||||
|
||||
PUBWEAK EXTI6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI6_IRQHandler
|
||||
B EXTI6_IRQHandler
|
||||
|
||||
PUBWEAK EXTI7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI7_IRQHandler
|
||||
B EXTI7_IRQHandler
|
||||
|
||||
PUBWEAK EXTI8_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI8_IRQHandler
|
||||
B EXTI8_IRQHandler
|
||||
|
||||
PUBWEAK EXTI9_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI9_IRQHandler
|
||||
B EXTI9_IRQHandler
|
||||
|
||||
PUBWEAK EXTI10_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI10_IRQHandler
|
||||
B EXTI10_IRQHandler
|
||||
|
||||
PUBWEAK EXTI11_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI11_IRQHandler
|
||||
B EXTI11_IRQHandler
|
||||
|
||||
PUBWEAK EXTI12_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI12_IRQHandler
|
||||
B EXTI12_IRQHandler
|
||||
|
||||
PUBWEAK EXTI13_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI13_IRQHandler
|
||||
B EXTI13_IRQHandler
|
||||
|
||||
PUBWEAK EXTI14_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI14_IRQHandler
|
||||
B EXTI14_IRQHandler
|
||||
|
||||
PUBWEAK EXTI15_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI15_IRQHandler
|
||||
B EXTI15_IRQHandler
|
||||
|
||||
PUBWEAK RTC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_IRQHandler
|
||||
B RTC_IRQHandler
|
||||
|
||||
PUBWEAK PKA_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PKA_IRQHandler
|
||||
B PKA_IRQHandler
|
||||
|
||||
PUBWEAK HASH_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HASH_IRQHandler
|
||||
B HASH_IRQHandler
|
||||
|
||||
PUBWEAK RNG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RNG_IRQHandler
|
||||
B RNG_IRQHandler
|
||||
|
||||
PUBWEAK ADC1_2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ADC1_2_IRQHandler
|
||||
B ADC1_2_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA1_Channel0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA1_Channel0_IRQHandler
|
||||
B GPDMA1_Channel0_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA1_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA1_Channel1_IRQHandler
|
||||
B GPDMA1_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA1_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA1_Channel2_IRQHandler
|
||||
B GPDMA1_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA1_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA1_Channel3_IRQHandler
|
||||
B GPDMA1_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA1_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA1_Channel4_IRQHandler
|
||||
B GPDMA1_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA1_Channel5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA1_Channel5_IRQHandler
|
||||
B GPDMA1_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA1_Channel6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA1_Channel6_IRQHandler
|
||||
B GPDMA1_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA1_Channel7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA1_Channel7_IRQHandler
|
||||
B GPDMA1_Channel7_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_BRK_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_BRK_IRQHandler
|
||||
B TIM1_BRK_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_UP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_UP_IRQHandler
|
||||
B TIM1_UP_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_TRG_COM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_TRG_COM_IRQHandler
|
||||
B TIM1_TRG_COM_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_CC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_CC_IRQHandler
|
||||
B TIM1_CC_IRQHandler
|
||||
|
||||
PUBWEAK TIM2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM2_IRQHandler
|
||||
B TIM2_IRQHandler
|
||||
|
||||
PUBWEAK TIM3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM3_IRQHandler
|
||||
B TIM3_IRQHandler
|
||||
|
||||
PUBWEAK TIM4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM4_IRQHandler
|
||||
B TIM4_IRQHandler
|
||||
|
||||
PUBWEAK TIM5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM5_IRQHandler
|
||||
B TIM5_IRQHandler
|
||||
|
||||
PUBWEAK TIM6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM6_IRQHandler
|
||||
B TIM6_IRQHandler
|
||||
|
||||
PUBWEAK TIM7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM7_IRQHandler
|
||||
B TIM7_IRQHandler
|
||||
|
||||
PUBWEAK TIM9_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM9_IRQHandler
|
||||
B TIM9_IRQHandler
|
||||
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI1_IRQHandler
|
||||
B SPI1_IRQHandler
|
||||
|
||||
PUBWEAK SPI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI2_IRQHandler
|
||||
B SPI2_IRQHandler
|
||||
|
||||
PUBWEAK SPI3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI3_IRQHandler
|
||||
B SPI3_IRQHandler
|
||||
|
||||
PUBWEAK SPI4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI4_IRQHandler
|
||||
B SPI4_IRQHandler
|
||||
|
||||
PUBWEAK SPI5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI5_IRQHandler
|
||||
B SPI5_IRQHandler
|
||||
|
||||
PUBWEAK SPI6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI6_IRQHandler
|
||||
B SPI6_IRQHandler
|
||||
|
||||
PUBWEAK HPDMA1_Channel0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HPDMA1_Channel0_IRQHandler
|
||||
B HPDMA1_Channel0_IRQHandler
|
||||
|
||||
PUBWEAK HPDMA1_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HPDMA1_Channel1_IRQHandler
|
||||
B HPDMA1_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK HPDMA1_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HPDMA1_Channel2_IRQHandler
|
||||
B HPDMA1_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK HPDMA1_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HPDMA1_Channel3_IRQHandler
|
||||
B HPDMA1_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK HPDMA1_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HPDMA1_Channel4_IRQHandler
|
||||
B HPDMA1_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK HPDMA1_Channel5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HPDMA1_Channel5_IRQHandler
|
||||
B HPDMA1_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK HPDMA1_Channel6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HPDMA1_Channel6_IRQHandler
|
||||
B HPDMA1_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK HPDMA1_Channel7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HPDMA1_Channel7_IRQHandler
|
||||
B HPDMA1_Channel7_IRQHandler
|
||||
|
||||
PUBWEAK SAI1_A_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SAI1_A_IRQHandler
|
||||
B SAI1_A_IRQHandler
|
||||
|
||||
PUBWEAK SAI1_B_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SAI1_B_IRQHandler
|
||||
B SAI1_A_IRQHandler
|
||||
|
||||
PUBWEAK SAI2_A_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SAI2_A_IRQHandler
|
||||
B SAI2_A_IRQHandler
|
||||
|
||||
PUBWEAK SAI2_B_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SAI2_B_IRQHandler
|
||||
B SAI2_B_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_EV_IRQHandler
|
||||
B I2C1_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_ER_IRQHandler
|
||||
B I2C1_ER_IRQHandler
|
||||
|
||||
PUBWEAK I2C2_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C2_EV_IRQHandler
|
||||
B I2C2_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C2_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C2_ER_IRQHandler
|
||||
B I2C2_ER_IRQHandler
|
||||
|
||||
PUBWEAK I2C3_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C3_EV_IRQHandler
|
||||
B I2C3_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C3_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C3_ER_IRQHandler
|
||||
B I2C3_ER_IRQHandler
|
||||
|
||||
PUBWEAK USART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART1_IRQHandler
|
||||
B USART1_IRQHandler
|
||||
|
||||
PUBWEAK USART2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART2_IRQHandler
|
||||
B USART2_IRQHandler
|
||||
|
||||
PUBWEAK USART3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART3_IRQHandler
|
||||
B USART3_IRQHandler
|
||||
|
||||
PUBWEAK UART4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART4_IRQHandler
|
||||
B UART4_IRQHandler
|
||||
|
||||
PUBWEAK UART5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART5_IRQHandler
|
||||
B UART5_IRQHandler
|
||||
|
||||
PUBWEAK UART7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART7_IRQHandler
|
||||
B UART7_IRQHandler
|
||||
|
||||
PUBWEAK UART8_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART8_IRQHandler
|
||||
B UART8_IRQHandler
|
||||
|
||||
PUBWEAK I3C1_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I3C1_EV_IRQHandler
|
||||
B I3C1_EV_IRQHandler
|
||||
|
||||
PUBWEAK I3C1_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I3C1_ER_IRQHandler
|
||||
B I3C1_ER_IRQHandler
|
||||
|
||||
PUBWEAK OTG_HS_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
OTG_HS_IRQHandler
|
||||
B OTG_HS_IRQHandler
|
||||
|
||||
PUBWEAK ETH_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ETH_IRQHandler
|
||||
B ETH_IRQHandler
|
||||
|
||||
PUBWEAK CORDIC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CORDIC_IRQHandler
|
||||
B CORDIC_IRQHandler
|
||||
|
||||
PUBWEAK GFXTIM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GFXTIM_IRQHandler
|
||||
B GFXTIM_IRQHandler
|
||||
|
||||
PUBWEAK DCMIPP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DCMIPP_IRQHandler
|
||||
B DCMIPP_IRQHandler
|
||||
|
||||
PUBWEAK DMA2D_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2D_IRQHandler
|
||||
B DMA2D_IRQHandler
|
||||
|
||||
PUBWEAK JPEG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
JPEG_IRQHandler
|
||||
B JPEG_IRQHandler
|
||||
|
||||
PUBWEAK GFXMMU_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GFXMMU_IRQHandler
|
||||
B GFXMMU_IRQHandler
|
||||
|
||||
PUBWEAK I3C1_WKUP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I3C1_WKUP_IRQHandler
|
||||
B I3C1_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK XSPI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
XSPI1_IRQHandler
|
||||
B XSPI1_IRQHandler
|
||||
|
||||
PUBWEAK XSPI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
XSPI2_IRQHandler
|
||||
B XSPI2_IRQHandler
|
||||
|
||||
PUBWEAK FMC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FMC_IRQHandler
|
||||
B FMC_IRQHandler
|
||||
|
||||
PUBWEAK SDMMC1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SDMMC1_IRQHandler
|
||||
B SDMMC1_IRQHandler
|
||||
|
||||
PUBWEAK SDMMC2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SDMMC2_IRQHandler
|
||||
B SDMMC2_IRQHandler
|
||||
|
||||
PUBWEAK OTG_FS_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
OTG_FS_IRQHandler
|
||||
B OTG_FS_IRQHandler
|
||||
|
||||
PUBWEAK TIM12_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM12_IRQHandler
|
||||
B TIM12_IRQHandler
|
||||
|
||||
PUBWEAK TIM13_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM13_IRQHandler
|
||||
B TIM13_IRQHandler
|
||||
|
||||
PUBWEAK TIM14_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM14_IRQHandler
|
||||
B TIM14_IRQHandler
|
||||
|
||||
PUBWEAK TIM15_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM15_IRQHandler
|
||||
B TIM15_IRQHandler
|
||||
|
||||
PUBWEAK TIM16_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM16_IRQHandler
|
||||
B TIM16_IRQHandler
|
||||
|
||||
PUBWEAK TIM17_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM17_IRQHandler
|
||||
B TIM17_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM1_IRQHandler
|
||||
B LPTIM1_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM2_IRQHandler
|
||||
B LPTIM2_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM3_IRQHandler
|
||||
B LPTIM3_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM4_IRQHandler
|
||||
B LPTIM4_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM5_IRQHandler
|
||||
B LPTIM5_IRQHandler
|
||||
|
||||
PUBWEAK SPDIF_RX_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPDIF_RX_IRQHandler
|
||||
B SPDIF_RX_IRQHandler
|
||||
|
||||
PUBWEAK MDIOS_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
MDIOS_IRQHandler
|
||||
B MDIOS_IRQHandler
|
||||
|
||||
PUBWEAK ADF1_FLT0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ADF1_FLT0_IRQHandler
|
||||
B ADF1_FLT0_IRQHandler
|
||||
|
||||
PUBWEAK CRS_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CRS_IRQHandler
|
||||
B CRS_IRQHandler
|
||||
|
||||
PUBWEAK UCPD1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UCPD1_IRQHandler
|
||||
B UCPD1_IRQHandler
|
||||
|
||||
PUBWEAK CEC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CEC_IRQHandler
|
||||
B CEC_IRQHandler
|
||||
|
||||
PUBWEAK PSSI_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PSSI_IRQHandler
|
||||
B PSSI_IRQHandler
|
||||
|
||||
PUBWEAK LPUART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPUART1_IRQHandler
|
||||
B LPUART1_IRQHandler
|
||||
|
||||
PUBWEAK WAKEUP_PIN_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
WAKEUP_PIN_IRQHandler
|
||||
B WAKEUP_PIN_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA1_Channel8_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA1_Channel8_IRQHandler
|
||||
B GPDMA1_Channel8_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA1_Channel9_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA1_Channel9_IRQHandler
|
||||
B GPDMA1_Channel9_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA1_Channel10_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA1_Channel10_IRQHandler
|
||||
B GPDMA1_Channel10_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA1_Channel11_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA1_Channel11_IRQHandler
|
||||
B GPDMA1_Channel11_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA1_Channel12_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA1_Channel12_IRQHandler
|
||||
B GPDMA1_Channel12_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA1_Channel13_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA1_Channel13_IRQHandler
|
||||
B GPDMA1_Channel13_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA1_Channel14_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA1_Channel14_IRQHandler
|
||||
B GPDMA1_Channel14_IRQHandler
|
||||
|
||||
PUBWEAK GPDMA1_Channel15_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
GPDMA1_Channel15_IRQHandler
|
||||
B GPDMA1_Channel15_IRQHandler
|
||||
|
||||
PUBWEAK HPDMA1_Channel8_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HPDMA1_Channel8_IRQHandler
|
||||
B HPDMA1_Channel8_IRQHandler
|
||||
|
||||
PUBWEAK HPDMA1_Channel9_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HPDMA1_Channel9_IRQHandler
|
||||
B HPDMA1_Channel9_IRQHandler
|
||||
|
||||
PUBWEAK HPDMA1_Channel10_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HPDMA1_Channel10_IRQHandler
|
||||
B HPDMA1_Channel10_IRQHandler
|
||||
|
||||
PUBWEAK HPDMA1_Channel11_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HPDMA1_Channel11_IRQHandler
|
||||
B HPDMA1_Channel11_IRQHandler
|
||||
|
||||
PUBWEAK HPDMA1_Channel12_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HPDMA1_Channel12_IRQHandler
|
||||
B HPDMA1_Channel12_IRQHandler
|
||||
|
||||
PUBWEAK HPDMA1_Channel13_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HPDMA1_Channel13_IRQHandler
|
||||
B HPDMA1_Channel13_IRQHandler
|
||||
|
||||
PUBWEAK HPDMA1_Channel14_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HPDMA1_Channel14_IRQHandler
|
||||
B HPDMA1_Channel14_IRQHandler
|
||||
|
||||
PUBWEAK HPDMA1_Channel15_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HPDMA1_Channel15_IRQHandler
|
||||
B HPDMA1_Channel15_IRQHandler
|
||||
|
||||
PUBWEAK FDCAN1_IT0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FDCAN1_IT0_IRQHandler
|
||||
B FDCAN1_IT0_IRQHandler
|
||||
|
||||
PUBWEAK FDCAN1_IT1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FDCAN1_IT1_IRQHandler
|
||||
B FDCAN1_IT1_IRQHandler
|
||||
|
||||
PUBWEAK FDCAN2_IT0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FDCAN2_IT0_IRQHandler
|
||||
B FDCAN2_IT0_IRQHandler
|
||||
|
||||
PUBWEAK FDCAN2_IT1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FDCAN2_IT1_IRQHandler
|
||||
B FDCAN2_IT1_IRQHandler
|
||||
|
||||
END
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,285 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32h7rsxx.c
|
||||
* @author MCD Application Team
|
||||
* @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*
|
||||
* This file provides two functions and one global variable to be called from
|
||||
* user application:
|
||||
* - SystemInit(): This function is called at startup just after reset and
|
||||
* before branch to main program. This call is made inside
|
||||
* the "startup_stm32h7rsxx.s" file.
|
||||
*
|
||||
* - SystemCoreClock variable: Contains the core clock (sys_cpu_ck), it can
|
||||
* be used by the user application to setup the
|
||||
* SysTick timer or configure other parameters.
|
||||
*
|
||||
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
|
||||
* be called whenever the core clock is changed
|
||||
* during program execution.
|
||||
*
|
||||
* After each device reset the HSI (64 MHz) is used as system clock source.
|
||||
* Then SystemInit() function is called, in "startup_stm32h7rsxx.s" file, to
|
||||
* optionally configure the system clock before to branch to main program.
|
||||
*
|
||||
*=============================================================================
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H7RSxx_System
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H7RSxx_System_Private_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "stm32h7rsxx.h"
|
||||
#include <math.h>
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H7RSxx_System_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H7RSxx_System_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
#if !defined (HSE_VALUE)
|
||||
#define HSE_VALUE 24000000UL /*!< Value of the High-Speed External oscillator in Hz */
|
||||
#endif /* HSE_VALUE */
|
||||
|
||||
#if !defined (HSI_VALUE)
|
||||
#define HSI_VALUE 64000000UL /*!< Value of the High-Speed Internal oscillator in Hz */
|
||||
#endif /* HSI_VALUE */
|
||||
|
||||
#if !defined (CSI_VALUE)
|
||||
#define CSI_VALUE 4000000UL /*!< Value of the Low-power Internal oscillator in Hz */
|
||||
#endif /* CSI_VALUE */
|
||||
|
||||
/*!< The VTOR location information is based on information from the linker with a dependency
|
||||
on the IDE, the cortex register is updated using the INTVECT_START.
|
||||
*/
|
||||
#if defined(__ICCARM__)
|
||||
extern uint32_t __vector_table;
|
||||
#define INTVECT_START ((uint32_t)& __vector_table)
|
||||
#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
|
||||
extern void * __Vectors;
|
||||
#define INTVECT_START ((uint32_t) & __Vectors)
|
||||
#elif defined(__GNUC__)
|
||||
extern void * g_pfnVectors;
|
||||
#define INTVECT_START ((uint32_t)& g_pfnVectors)
|
||||
#endif /* __ICCARM__*/
|
||||
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H7RSxx_System_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H7RSxx_System_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
/* The SystemCoreClock variable is updated in two ways:
|
||||
1) by calling CMSIS function SystemCoreClockUpdate()
|
||||
2) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
|
||||
Note: If you use this function to configure the system clock; then there
|
||||
is no need to call the first function listed above, since SystemCoreClock
|
||||
variable is updated automatically.
|
||||
*/
|
||||
uint32_t SystemCoreClock = HSI_VALUE;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H7RSxx_System_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H7RSxx_System_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system.
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* Configure the Vector Table location -------------------------------------*/
|
||||
SCB->VTOR = INTVECT_START;
|
||||
|
||||
/* FPU settings ------------------------------------------------------------*/
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock variable according to RCC registers values.
|
||||
* The SystemCoreClock variable contains the core clock (sys_cpu_ck), it can
|
||||
* be used by the user application to setup the SysTick timer or configure
|
||||
* other parameters.
|
||||
*
|
||||
* @note Each time the core clock changes, this function must be called
|
||||
* to update SystemCoreClock variable value. Otherwise, any configuration
|
||||
* based on this variable will be incorrect.
|
||||
*
|
||||
* @note - The system frequency computed by this function is not the real
|
||||
* frequency in the chip. It is calculated based on the predefined
|
||||
* constant and the selected clock source:
|
||||
*
|
||||
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
|
||||
*
|
||||
* - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(**)
|
||||
*
|
||||
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
|
||||
*
|
||||
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSI_VALUE(*)
|
||||
* or CSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
|
||||
*
|
||||
* (*) HSI_VALUE is a constant defined in stm32h7rsxx_hal.h file (default value
|
||||
* 64 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (**) CSI_VALUE is a constant defined in stm32h7rsxx_hal.h file (default value
|
||||
* 4 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (***) HSE_VALUE is a constant defined in stm32h7rsxx_hal.h file (default value
|
||||
* 24 MHz), user has to ensure that HSE_VALUE is same as the real
|
||||
* frequency of the crystal used. Otherwise, this function may
|
||||
* have wrong result.
|
||||
*
|
||||
* - The result of this function could be not correct when using fractional
|
||||
* value for HSE crystal.
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
uint32_t sysclk, hsivalue, pllsource, pllm, pllp, core_presc;
|
||||
float_t pllfracn, pllvco;
|
||||
|
||||
/* Get SYSCLK source -------------------------------------------------------*/
|
||||
switch (RCC->CFGR & RCC_CFGR_SWS)
|
||||
{
|
||||
case 0x00: /* HSI used as system clock source (default after reset) */
|
||||
sysclk = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> RCC_CR_HSIDIV_Pos));
|
||||
break;
|
||||
|
||||
case 0x08: /* CSI used as system clock source */
|
||||
sysclk = CSI_VALUE;
|
||||
break;
|
||||
|
||||
case 0x10: /* HSE used as system clock source */
|
||||
sysclk = HSE_VALUE;
|
||||
break;
|
||||
|
||||
case 0x18: /* PLL1 used as system clock source */
|
||||
/* PLL1_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
|
||||
SYSCLK = PLL1_VCO / PLL1R
|
||||
*/
|
||||
pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
|
||||
pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) ;
|
||||
if ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) != 0U)
|
||||
{
|
||||
pllfracn = (float_t)(uint32_t)(((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN)>> RCC_PLL1FRACR_FRACN_Pos));
|
||||
}
|
||||
else
|
||||
{
|
||||
pllfracn = (float_t)0U;
|
||||
}
|
||||
|
||||
if (pllm != 0U)
|
||||
{
|
||||
switch (pllsource)
|
||||
{
|
||||
case 0x02: /* HSE used as PLL1 clock source */
|
||||
pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVN) + (pllfracn/(float_t)0x2000) +(float_t)1 );
|
||||
break;
|
||||
|
||||
case 0x01: /* CSI used as PLL1 clock source */
|
||||
pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVN) + (pllfracn/(float_t)0x2000) +(float_t)1 );
|
||||
break;
|
||||
|
||||
case 0x00: /* HSI used as PLL1 clock source */
|
||||
default:
|
||||
hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> RCC_CR_HSIDIV_Pos));
|
||||
pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVN) + (pllfracn/(float_t)0x2000) +(float_t)1 );
|
||||
break;
|
||||
}
|
||||
pllp = (((RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVP) >> RCC_PLL1DIVR1_DIVP_Pos) + 1U ) ;
|
||||
sysclk = (uint32_t)(float_t)(pllvco/(float_t)pllp);
|
||||
}
|
||||
else
|
||||
{
|
||||
sysclk = 0U;
|
||||
}
|
||||
break;
|
||||
|
||||
default: /* Unexpected, default to HSI used as system clock source (default after reset) */
|
||||
sysclk = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> RCC_CR_HSIDIV_Pos));
|
||||
break;
|
||||
}
|
||||
|
||||
/* system clock frequency : CM7 CPU frequency */
|
||||
core_presc = (RCC->CDCFGR & RCC_CDCFGR_CPRE);
|
||||
if (core_presc >= 8U)
|
||||
{
|
||||
SystemCoreClock = (sysclk >> (core_presc - RCC_CDCFGR_CPRE_3 + 1U));
|
||||
}
|
||||
else
|
||||
{
|
||||
SystemCoreClock = sysclk;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -1,47 +0,0 @@
|
|||
import rtconfig
|
||||
from building import *
|
||||
|
||||
# get current directory
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
# The set of source files associated with this SConscript file.
|
||||
|
||||
src = Split('''
|
||||
CMSIS/Device/ST/STM32H7RSxx/Source/Templates/system_stm32h7rsxx.c
|
||||
STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal.c
|
||||
STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_cec.c
|
||||
STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_cortex.c
|
||||
STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_crc.c
|
||||
STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_crc_ex.c
|
||||
STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_cryp.c
|
||||
STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_cryp_ex.c
|
||||
STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_dma.c
|
||||
STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_dma_ex.c
|
||||
STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_pwr.c
|
||||
STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_pwr_ex.c
|
||||
STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_rcc.c
|
||||
STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_rcc_ex.c
|
||||
STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_rng.c
|
||||
STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_sram.c
|
||||
STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_gpio.c
|
||||
STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_adc.c
|
||||
STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_adc_ex.c
|
||||
STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_xspi.c
|
||||
STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_flash.c
|
||||
STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_flash_ex.c
|
||||
''')
|
||||
|
||||
if GetDepend(['RT_USING_SERIAL']) or GetDepend(['RT_USING_NANO', 'RT_USING_CONSOLE']):
|
||||
src += ['STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_uart.c']
|
||||
src += ['STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_usart.c']
|
||||
src += ['STM32H7RSxx_HAL_Driver/Src/stm32h7rsxx_hal_uart_ex.c']
|
||||
|
||||
|
||||
path = [cwd + '/STM32H7RSxx_HAL_Driver/Inc',
|
||||
cwd + '/CMSIS/Device/ST/STM32H7RSxx/Include']
|
||||
|
||||
CPPDEFINES = ['USE_HAL_DRIVER']
|
||||
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
|
||||
|
||||
Return('group')
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,53 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32_assert.h
|
||||
* @author MCD Application Team
|
||||
* @brief STM32 assert template file.
|
||||
* This file should be copied to the application folder and renamed
|
||||
* to stm32_assert.h.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32_ASSERT_H
|
||||
#define STM32_ASSERT_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
#ifdef USE_FULL_ASSERT
|
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check.
|
||||
* @param expr If expr is false, it calls assert_failed function
|
||||
* which reports the name of the source file and the source
|
||||
* line number of the call that failed.
|
||||
* If expr is true, it returns no value.
|
||||
* @retval None
|
||||
*/
|
||||
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void assert_failed(uint8_t *file, uint32_t line);
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32_ASSERT_H */
|
||||
|
|
@ -1,767 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7rsxx_hal.h
|
||||
* @author MCD Application Team
|
||||
* @brief This file contains all the functions prototypes for the HAL
|
||||
* module driver.
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7RSxx_HAL_H
|
||||
#define STM32H7RSxx_HAL_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7rsxx_hal_conf.h"
|
||||
|
||||
/** @addtogroup STM32H7RSxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup HAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup HAL_TICK_FREQ Tick Frequency
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief HAL Tick frequency
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_TICK_FREQ_10HZ = 100U,
|
||||
HAL_TICK_FREQ_100HZ = 10U,
|
||||
HAL_TICK_FREQ_1KHZ = 1U,
|
||||
HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
|
||||
} HAL_TickFreqTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup REV_ID device revision ID
|
||||
* @{
|
||||
*/
|
||||
#define REV_ID_A 0x1003U /*!< STM32H7Rx/Sx rev.A */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_Exported_Constants HAL Exported Constants
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief STM32H7RSxx HAL Driver version number
|
||||
*/
|
||||
#define STM32H7RSXX_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
|
||||
#define STM32H7RSXX_HAL_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */
|
||||
#define STM32H7RSXX_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
|
||||
#define STM32H7RSXX_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
|
||||
#define STM32H7RSXX_HAL_VERSION ((STM32H7RSXX_HAL_VERSION_MAIN << 24U)\
|
||||
|(STM32H7RSXX_HAL_VERSION_SUB1 << 16U)\
|
||||
|(STM32H7RSXX_HAL_VERSION_SUB2 << 8U )\
|
||||
|(STM32H7RSXX_HAL_VERSION_RC))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SBS_Exported_Constants SBS Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SBS_HDPL_Value HDPL Value
|
||||
* @{
|
||||
*/
|
||||
#define SBS_HDPL_VALUE_0 0x000000B4U /*!< Hide protection level 0 */
|
||||
#define SBS_HDPL_VALUE_1 0x00000051U /*!< Hide protection level 1 */
|
||||
#define SBS_HDPL_VALUE_2 0x0000008AU /*!< Hide protection level 2 */
|
||||
#define SBS_HDPL_VALUE_3 0x0000006FU /*!< Hide protection level 3 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SBS_Timer_Break_Inputs Timer Break Inputs
|
||||
* @{
|
||||
*/
|
||||
#define SBS_TIMER_BREAK_LOCK_PVD SBS_BKLOCKR_PVD_BL /*!< PVD break lock */
|
||||
#define SBS_TIMER_BREAK_LOCK_FLASH SBS_BKLOCKR_FLASHECC_BL /*!< FLASH ECC error break lock */
|
||||
#define SBS_TIMER_BREAK_LOCK_CORE SBS_BKLOCKR_CM7LCKUP_BL /*!< Cortex-M7 lockup break lock */
|
||||
#define SBS_TIMER_BREAK_LOCK_BKPRAM SBS_BKLOCKR_BKRAMECC_BL /*!< Backup RAM ECC error break lock */
|
||||
#define SBS_TIMER_BREAK_LOCK_DTCM SBS_BKLOCKR_DTCMECC_BL /*!< DTCM ECC error break lock */
|
||||
#define SBS_TIMER_BREAK_LOCK_ITCM SBS_BKLOCKR_ITCMECC_BL /*!< ITCM ECC error break lock */
|
||||
#define SBS_TIMER_BREAK_LOCK_AXISRAM3 SBS_BKLOCKR_ARAM3ECC_BL /*!< AXISRAM3 ECC error break lock */
|
||||
#define SBS_TIMER_BREAK_LOCK_AXISRAM1 SBS_BKLOCKR_ARAM1ECC_BL /*!< AXISRAM1 ECC error break lock */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SBS_FPU_Interrupts FPU Interrupts
|
||||
* @{
|
||||
*/
|
||||
#define SBS_IT_FPU_IOC SBS_FPUIMR_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt */
|
||||
#define SBS_IT_FPU_DZC SBS_FPUIMR_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */
|
||||
#define SBS_IT_FPU_UFC SBS_FPUIMR_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */
|
||||
#define SBS_IT_FPU_OFC SBS_FPUIMR_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */
|
||||
#define SBS_IT_FPU_IDC SBS_FPUIMR_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */
|
||||
#define SBS_IT_FPU_IXC SBS_FPUIMR_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SBS_Compensation_Cell_Selection Compensation Cell Selection
|
||||
* @{
|
||||
*/
|
||||
#define SBS_IO_ANALOG_CELL SBS_CCCSR_COMP_EN /*!< Compensation cell for the I/O analog switches */
|
||||
#define SBS_IO_XSPI1_CELL SBS_CCCSR_XSPI1_COMP_EN /*!< Compensation cell for the I/O of the XSPI1 */
|
||||
#define SBS_IO_XSPI2_CELL SBS_CCCSR_XSPI2_COMP_EN /*!< Compensation cell for the I/O of the XSPI2 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SBS_Compensation_Cell_Ready_Selection Compensation Cell Ready Selection
|
||||
* @{
|
||||
*/
|
||||
#define SBS_IO_ANALOG_CELL_READY SBS_CCCSR_COMP_RDY /*!< Ready flag of compensation cell for the I/O analog switches */
|
||||
#define SBS_IO_XSPI1_CELL_READY SBS_CCCSR_XSPI1_COMP_RDY /*!< Ready flag of compensation cell for the I/O of the XSPI1 */
|
||||
#define SBS_IO_XSPI2_CELL_READY SBS_CCCSR_XSPI2_COMP_RDY /*!< Ready flag of compensation cell for the I/O of the XSPI2 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SBS_IO_Compensation_Code_Config IO Compensation Code config
|
||||
* @{
|
||||
*/
|
||||
#define SBS_IO_CELL_CODE 0UL /*!< Code from the cell */
|
||||
#define SBS_IO_REGISTER_CODE 1UL /*!< Code from the values in the cell code register */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SBS_IO_HSLV_Selection IO High Speed at Low Voltage Selection
|
||||
* @{
|
||||
*/
|
||||
#define SBS_IO_ANALOG_HSLV SBS_CCCSR_IOHSLV /*!< High speed at low voltage for the I/O analog switches */
|
||||
#define SBS_IO_XSPI1_HSLV SBS_CCCSR_XSPI1_IOHSLV /*!< High speed at low voltage for the I/O of the XSPI1 */
|
||||
#define SBS_IO_XSPI2_HSLV SBS_CCCSR_XSPI2_IOHSLV /*!< High speed at low voltage for the I/O of the XSPI2 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SBS_Ethernet_PHY_Config Ethernet PHY config
|
||||
* @{
|
||||
*/
|
||||
#define SBS_ETHERNET_PHY_GMII_OR_MII 0U /*!< GMII or MII */
|
||||
#define SBS_ETHERNET_PHY_RMII SBS_PMCR_ETH_PHYSEL_2 /*!< RMII */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SBS_ECC_AXISRAM_WS_Config ECC AXISRAMs Wait State when ECC=0 config
|
||||
* @{
|
||||
*/
|
||||
#define SBS_AXISRAM_WS_0 0U /*!< 0 Wait state */
|
||||
#define SBS_AXISRAM_WS_1 SBS_PMCR_AXISRAM_WS /*!< 1 Wait state */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SBS_EXTI_Port EXTI Port configuration
|
||||
* @{
|
||||
*/
|
||||
#define SBS_EXTI_PIN_PORTA 0x00UL /*!< Port A pin input of EXTI event detection */
|
||||
#define SBS_EXTI_PIN_PORTB 0x01UL /*!< Port B pin input of EXTI event detection */
|
||||
#define SBS_EXTI_PIN_PORTC 0x02UL /*!< Port C pin input of EXTI event detection */
|
||||
#define SBS_EXTI_PIN_PORTD 0x03UL /*!< Port D pin input of EXTI event detection */
|
||||
#define SBS_EXTI_PIN_PORTE 0x04UL /*!< Port E pin input of EXTI event detection */
|
||||
#define SBS_EXTI_PIN_PORTF 0x05UL /*!< Port F pin input of EXTI event detection */
|
||||
#define SBS_EXTI_PIN_PORTG 0x06UL /*!< Port G pin input of EXTI event detection */
|
||||
#define SBS_EXTI_PIN_PORTH 0x07UL /*!< Port H pin input of EXTI event detection */
|
||||
#define SBS_EXTI_PIN_PORTM 0x0CUL /*!< Port M pin input of EXTI event detection */
|
||||
#define SBS_EXTI_PIN_PORTN 0x0DUL /*!< Port N pin input of EXTI event detection */
|
||||
#define SBS_EXTI_PIN_PORTO 0x0EUL /*!< Port O pin input of EXTI event detection */
|
||||
#define SBS_EXTI_PIN_PORTP 0x0FUL /*!< Port P pin input of EXTI event detection */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup AXIM_Exported_Constants AXIM Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup AXIM_ASIB_READ_ISSUING_CAP AXIM ASIBs Read Issuing Capability
|
||||
* @{
|
||||
*/
|
||||
#define AXIM_ASIB_READ_ISS_NORMAL 0U /*!< Normal issuing capability */
|
||||
#define AXIM_ASIB_READ_ISS_FORCE_TO_1 AXIM_ASIB_FNMOD_READ_ISS /*!< Force issuing capability to 1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup AXIM_ASIB_WRITE_ISSUING_CAP AXIM ASIBs Write Issuing Capability
|
||||
* @{
|
||||
*/
|
||||
#define AXIM_ASIB_WRITE_ISS_NORMAL 0U /*!< Normal issuing capability */
|
||||
#define AXIM_ASIB_WRITE_ISS_FORCE_TO_1 AXIM_ASIB_FNMOD_WRITE_ISS /*!< Force issuing capability to 1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup AXIM_AMIB_READ_ISSUING_CAP AXIM AMIBs Read Issuing Capability
|
||||
* @{
|
||||
*/
|
||||
#define AXIM_AMIB_READ_ISS_NORMAL 0U /*!< Normal issuing capability */
|
||||
#define AXIM_AMIB_READ_ISS_FORCE_TO_1 AXIM_AMIB_FNMOD_READ_ISS /*!< Force issuing capability to 1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup AXIM_AMIB_WRITE_ISSUING_CAP AXIM AMIBs Write Issuing Capability
|
||||
* @{
|
||||
*/
|
||||
#define AXIM_AMIB_WRITE_ISS_NORMAL 0U /*!< Normal issuing capability */
|
||||
#define AXIM_AMIB_WRITE_ISS_FORCE_TO_1 AXIM_AMIB_FNMOD_WRITE_ISS /*!< Force issuing capability to 1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup AXIM_AMIB_READ_ISSUING_BM_CAP AXIM AMIBs Read Issuing Bus Matrix Capability
|
||||
* @{
|
||||
*/
|
||||
#define AXIM_AMIB_READ_ISS_BM_NORMAL 0U /*!< Normal issuing capability */
|
||||
#define AXIM_AMIB_READ_ISS_BM_FORCE_TO_1 AXIM_AMIB_FNMOD_READ_ISS /*!< Force issuing capability to 1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup AXIM_AMIB_WRITE_ISSUING_BM_CAP AXIM AMIBs Write Issuing Bus Matrix Capability
|
||||
* @{
|
||||
*/
|
||||
#define AXIM_AMIB_WRITE_ISS_BM_NORMAL 0U /*!< Normal issuing capability */
|
||||
#define AXIM_AMIB_WRITE_ISS_BM_FORCE_TO_1 AXIM_AMIB_FNMOD_WRITE_ISS /*!< Force issuing capability to 1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Freeze/Unfreeze Peripherals in Debug mode
|
||||
*/
|
||||
#define __HAL_DBGMCU_FREEZE_GPDMA0() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_0)
|
||||
#define __HAL_DBGMCU_UNFREEZE_GPDMA0() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_0)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_GPDMA1() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_1)
|
||||
#define __HAL_DBGMCU_UNFREEZE_GPDMA1() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_1)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_GPDMA2() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_2)
|
||||
#define __HAL_DBGMCU_UNFREEZE_GPDMA2() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_2)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_GPDMA3() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_3)
|
||||
#define __HAL_DBGMCU_UNFREEZE_GPDMA3() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_3)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_GPDMA4() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_4)
|
||||
#define __HAL_DBGMCU_UNFREEZE_GPDMA4() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_4)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_GPDMA5() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_5)
|
||||
#define __HAL_DBGMCU_UNFREEZE_GPDMA5() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_5)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_GPDMA6() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_6)
|
||||
#define __HAL_DBGMCU_UNFREEZE_GPDMA6() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_6)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_GPDMA7() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_7)
|
||||
#define __HAL_DBGMCU_UNFREEZE_GPDMA7() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_7)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_GPDMA8() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_8)
|
||||
#define __HAL_DBGMCU_UNFREEZE_GPDMA8() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_8)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_GPDMA9() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_9)
|
||||
#define __HAL_DBGMCU_UNFREEZE_GPDMA9() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_9)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_GPDMA10() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_10)
|
||||
#define __HAL_DBGMCU_UNFREEZE_GPDMA10() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_10)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_GPDMA11() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_11)
|
||||
#define __HAL_DBGMCU_UNFREEZE_GPDMA11() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_11)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_GPDMA12() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_12)
|
||||
#define __HAL_DBGMCU_UNFREEZE_GPDMA12() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_12)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_GPDMA13() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_13)
|
||||
#define __HAL_DBGMCU_UNFREEZE_GPDMA13() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_13)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_GPDMA14() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_14)
|
||||
#define __HAL_DBGMCU_UNFREEZE_GPDMA14() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_14)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_GPDMA15() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_15)
|
||||
#define __HAL_DBGMCU_UNFREEZE_GPDMA15() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_15)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_HPDMA0() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_0)
|
||||
#define __HAL_DBGMCU_UNFREEZE_HPDMA0() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_0)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_HPDMA1() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_1)
|
||||
#define __HAL_DBGMCU_UNFREEZE_HPDMA1() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_1)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_HPDMA2() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_2)
|
||||
#define __HAL_DBGMCU_UNFREEZE_HPDMA2() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_2)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_HPDMA3() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_3)
|
||||
#define __HAL_DBGMCU_UNFREEZE_HPDMA3() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_3)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_HPDMA4() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_4)
|
||||
#define __HAL_DBGMCU_UNFREEZE_HPDMA4() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_4)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_HPDMA5() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_5)
|
||||
#define __HAL_DBGMCU_UNFREEZE_HPDMA5() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_5)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_HPDMA6() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_6)
|
||||
#define __HAL_DBGMCU_UNFREEZE_HPDMA6() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_6)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_HPDMA7() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_7)
|
||||
#define __HAL_DBGMCU_UNFREEZE_HPDMA7() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_7)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_HPDMA8() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_8)
|
||||
#define __HAL_DBGMCU_UNFREEZE_HPDMA8() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_8)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_HPDMA9() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_9)
|
||||
#define __HAL_DBGMCU_UNFREEZE_HPDMA9() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_9)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_HPDMA10() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_10)
|
||||
#define __HAL_DBGMCU_UNFREEZE_HPDMA10() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_10)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_HPDMA11() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_11)
|
||||
#define __HAL_DBGMCU_UNFREEZE_HPDMA11() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_11)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_HPDMA12() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_12)
|
||||
#define __HAL_DBGMCU_UNFREEZE_HPDMA12() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_12)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_HPDMA13() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_13)
|
||||
#define __HAL_DBGMCU_UNFREEZE_HPDMA13() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_13)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_HPDMA14() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_14)
|
||||
#define __HAL_DBGMCU_UNFREEZE_HPDMA14() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_14)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_HPDMA15() SET_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_15)
|
||||
#define __HAL_DBGMCU_UNFREEZE_HPDMA15() CLEAR_BIT(DBGMCU->AHB5FZR, DBGMCU_AHB5FZR_HPDMA_15)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_I2C1() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_I2C1)
|
||||
#define __HAL_DBGMCU_UNFREEZE_I2C1() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_I2C1)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_I2C2() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_I2C2)
|
||||
#define __HAL_DBGMCU_UNFREEZE_I2C2() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_I2C2)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_I2C3() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_I2C3)
|
||||
#define __HAL_DBGMCU_UNFREEZE_I2C3() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_I2C3)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM2)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM2)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM3)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM3)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM4)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM4)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM5)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM5)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM6)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM6)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM7)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM7)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_TIM9() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_TIM9)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_TIM9)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM12)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM12)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM13)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM13)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM14)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_TIM14)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_TIM1)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_TIM1)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_TIM15)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_TIM15)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_TIM16)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_TIM16)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_TIM17)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_TIM17)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_LPTIM1)
|
||||
#define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_LPTIM1)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB4FZR, DBGMCU_APB4FZR_LPTIM2)
|
||||
#define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB4FZR, DBGMCU_APB4FZR_LPTIM2)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_LPTIM3() SET_BIT(DBGMCU->APB4FZR, DBGMCU_APB4FZR_LPTIM3)
|
||||
#define __HAL_DBGMCU_UNFREEZE_LPTIM3() CLEAR_BIT(DBGMCU->APB4FZR, DBGMCU_APB4FZR_LPTIM3)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_LPTIM4() SET_BIT(DBGMCU->APB4FZR, DBGMCU_APB4FZR_LPTIM4)
|
||||
#define __HAL_DBGMCU_UNFREEZE_LPTIM4() CLEAR_BIT(DBGMCU->APB4FZR, DBGMCU_APB4FZR_LPTIM4)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_LPTIM5() SET_BIT(DBGMCU->APB4FZR, DBGMCU_APB4FZR_LPTIM5)
|
||||
#define __HAL_DBGMCU_UNFREEZE_LPTIM5() CLEAR_BIT(DBGMCU->APB4FZR, DBGMCU_APB4FZR_LPTIM5)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB4FZR, DBGMCU_APB4FZR_IWDG)
|
||||
#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB4FZR, DBGMCU_APB4FZR_IWDG)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_PWM1() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_PWM1)
|
||||
#define __HAL_DBGMCU_UNFREEZE_PWM1() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_PWM1)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB4FZR, DBGMCU_APB4FZR_RTC)
|
||||
#define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB4FZR, DBGMCU_APB4FZR_RTC)
|
||||
|
||||
#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_WWDG)
|
||||
#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR, DBGMCU_APB1FZR_WWDG)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SBS_Exported_Macros SBS Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Floating Point Unit interrupt enable/disable macros
|
||||
* @param __INTERRUPT__ This parameter can be a value of @ref SBS_FPU_Interrupts
|
||||
*/
|
||||
#define __HAL_SBS_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do { \
|
||||
assert_param(IS_SBS_FPU_INTERRUPT((__INTERRUPT__))); \
|
||||
SET_BIT(SBS->FPUIMR, (__INTERRUPT__)); \
|
||||
} while(0)
|
||||
|
||||
#define __HAL_SBS_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do { \
|
||||
assert_param(IS_SBS_FPU_INTERRUPT((__INTERRUPT__))); \
|
||||
CLEAR_BIT(SBS->FPUIMR, (__INTERRUPT__)); \
|
||||
} while(0)
|
||||
|
||||
/** @brief Check SBS Memories Erase Status Flags.
|
||||
* @retval The state of memory erase.
|
||||
*/
|
||||
#define __HAL_SBS_GET_MEMORIES_ERASE_STATUS() ((SBS->MESR) & (SBS_MESR_MEF))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup VREFBUF_VoltageScale VREFBUF Voltage Scale
|
||||
* @{
|
||||
*/
|
||||
#define VREFBUF_VOLTAGE_SCALE0 VREFBUF_CSR_VRS_OUT1 /*!< Voltage reference scale 0 (VREF_OUT1) */
|
||||
#define VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_OUT2 /*!< Voltage reference scale 1 (VREF_OUT2) */
|
||||
#define VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_OUT3 /*!< Voltage reference scale 2 (VREF_OUT3) */
|
||||
#define VREFBUF_VOLTAGE_SCALE3 VREFBUF_CSR_VRS_OUT4 /*!< Voltage reference scale 3 (VREF_OUT4) */
|
||||
|
||||
|
||||
#define IS_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == VREFBUF_VOLTAGE_SCALE0) || \
|
||||
((__SCALE__) == VREFBUF_VOLTAGE_SCALE1) || \
|
||||
((__SCALE__) == VREFBUF_VOLTAGE_SCALE2) || \
|
||||
((__SCALE__) == VREFBUF_VOLTAGE_SCALE3))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup VREFBUF_HighImpedance VREFBUF High Impedance
|
||||
* @{
|
||||
*/
|
||||
#define VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to Voltage reference buffer output */
|
||||
#define VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */
|
||||
|
||||
#define IS_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
|
||||
((__VALUE__) == VREFBUF_HIGH_IMPEDANCE_ENABLE))
|
||||
|
||||
#define IS_VREFBUF_TRIMMING(__VALUE__) ((__VALUE__) <= VREFBUF_CCR_TRIM)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SBS_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_SBS_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SBS_IT_FPU_IOC) == SBS_IT_FPU_IOC) || \
|
||||
(((__INTERRUPT__) & SBS_IT_FPU_DZC) == SBS_IT_FPU_DZC) || \
|
||||
(((__INTERRUPT__) & SBS_IT_FPU_UFC) == SBS_IT_FPU_UFC) || \
|
||||
(((__INTERRUPT__) & SBS_IT_FPU_OFC) == SBS_IT_FPU_OFC) || \
|
||||
(((__INTERRUPT__) & SBS_IT_FPU_IDC) == SBS_IT_FPU_IDC) || \
|
||||
(((__INTERRUPT__) & SBS_IT_FPU_IXC) == SBS_IT_FPU_IXC))
|
||||
|
||||
#define IS_SBS_HDPL(__LEVEL__) (((__LEVEL__) == SBS_HDPL_VALUE_0) || \
|
||||
((__LEVEL__) == SBS_HDPL_VALUE_1) || \
|
||||
((__LEVEL__) == SBS_HDPL_VALUE_2) || \
|
||||
((__LEVEL__) == SBS_HDPL_VALUE_3))
|
||||
|
||||
#define IS_SBS_COMPENSATION_CELL(__CELL__) (((__CELL__) == SBS_IO_ANALOG_CELL) || \
|
||||
((__CELL__) == SBS_IO_XSPI1_CELL) || \
|
||||
((__CELL__) == SBS_IO_XSPI2_CELL))
|
||||
|
||||
#define IS_SBS_COMPENSATION_CELL_READY(__CELL__) (((__CELL__) == SBS_IO_ANALOG_CELL_READY) || \
|
||||
((__CELL__) == SBS_IO_XSPI1_CELL_READY) || \
|
||||
((__CELL__) == SBS_IO_XSPI2_CELL_READY))
|
||||
|
||||
#define IS_SBS_IOHSLV(__HSLV__) (((__HSLV__) == SBS_IO_ANALOG_HSLV) || \
|
||||
((__HSLV__) == SBS_IO_XSPI1_HSLV) || \
|
||||
((__HSLV__) == SBS_IO_XSPI2_HSLV))
|
||||
|
||||
#define IS_SBS_EXTI_INPUT(__INPUT__) ((__INPUT__) < 16U)
|
||||
|
||||
#define IS_SBS_EXTI_PIN(__PIN__) (((__PIN__) == SBS_EXTI_PIN_PORTA) || \
|
||||
((__PIN__) == SBS_EXTI_PIN_PORTB) || \
|
||||
((__PIN__) == SBS_EXTI_PIN_PORTC) || \
|
||||
((__PIN__) == SBS_EXTI_PIN_PORTD) || \
|
||||
((__PIN__) == SBS_EXTI_PIN_PORTE) || \
|
||||
((__PIN__) == SBS_EXTI_PIN_PORTF) || \
|
||||
((__PIN__) == SBS_EXTI_PIN_PORTG) || \
|
||||
((__PIN__) == SBS_EXTI_PIN_PORTH) || \
|
||||
((__PIN__) == SBS_EXTI_PIN_PORTM) || \
|
||||
((__PIN__) == SBS_EXTI_PIN_PORTN) || \
|
||||
((__PIN__) == SBS_EXTI_PIN_PORTO) || \
|
||||
((__PIN__) == SBS_EXTI_PIN_PORTP))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup AXIM_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_AXIM_ASIB_READ_ISS(__ISS__) (((__ISS__) == AXIM_ASIB_READ_ISS_NORMAL) || \
|
||||
((__ISS__) == AXIM_ASIB_READ_ISS_FORCE_TO_1))
|
||||
|
||||
#define IS_AXIM_ASIB_WRITE_ISS(__ISS__) (((__ISS__) == AXIM_ASIB_WRITE_ISS_NORMAL) || \
|
||||
((__ISS__) == AXIM_ASIB_WRITE_ISS_FORCE_TO_1))
|
||||
|
||||
#define IS_AXIM_QOS(__QOS__) ((__QOS__) <= AXIM_ASIB_READQOS_AR_QOS)
|
||||
|
||||
#define IS_AXIM_AMIB_READ_ISS(__ISS__) (((__ISS__) == AXIM_AMIB_READ_ISS_NORMAL) || \
|
||||
((__ISS__) == AXIM_AMIB_READ_ISS_FORCE_TO_1))
|
||||
|
||||
#define IS_AXIM_AMIB_WRITE_ISS(__ISS__) (((__ISS__) == AXIM_AMIB_WRITE_ISS_NORMAL) || \
|
||||
((__ISS__) == AXIM_AMIB_WRITE_ISS_FORCE_TO_1))
|
||||
|
||||
#define IS_AXIM_AMIB_READ_ISS_BM(__ISS__) (((__ISS__) == AXIM_AMIB_READ_ISS_NORMAL) || \
|
||||
((__ISS__) == AXIM_AMIB_READ_ISS_FORCE_TO_1))
|
||||
|
||||
#define IS_AXIM_AMIB_WRITE_ISS_BM(__ISS__) (((__ISS__) == AXIM_AMIB_WRITE_ISS_BM_NORMAL) || \
|
||||
((__ISS__) == AXIM_AMIB_WRITE_ISS_BM_FORCE_TO_1))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported variables --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup HAL_Exported_Variables
|
||||
* @{
|
||||
*/
|
||||
extern __IO uint32_t uwTick;
|
||||
extern uint32_t uwTickPrio;
|
||||
extern HAL_TickFreqTypeDef uwTickFreq;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup HAL_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup HAL_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_Init(void);
|
||||
HAL_StatusTypeDef HAL_DeInit(void);
|
||||
void HAL_MspInit(void);
|
||||
void HAL_MspDeInit(void);
|
||||
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HAL_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions **********************************************/
|
||||
void HAL_IncTick(void);
|
||||
void HAL_Delay(uint32_t Delay);
|
||||
uint32_t HAL_GetTick(void);
|
||||
uint32_t HAL_GetTickPrio(void);
|
||||
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
|
||||
HAL_TickFreqTypeDef HAL_GetTickFreq(void);
|
||||
void HAL_SuspendTick(void);
|
||||
void HAL_ResumeTick(void);
|
||||
uint32_t HAL_GetHalVersion(void);
|
||||
uint32_t HAL_GetREVID(void);
|
||||
uint32_t HAL_GetDEVID(void);
|
||||
uint32_t HAL_GetUIDw0(void);
|
||||
uint32_t HAL_GetUIDw1(void);
|
||||
uint32_t HAL_GetUIDw2(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HAL_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* DBGMCU Peripheral Control functions ***************************************/
|
||||
void HAL_DBGMCU_EnableDBGSleepMode(void);
|
||||
void HAL_DBGMCU_DisableDBGSleepMode(void);
|
||||
void HAL_DBGMCU_EnableDBGStopMode(void);
|
||||
void HAL_DBGMCU_DisableDBGStopMode(void);
|
||||
void HAL_DBGMCU_EnableDBGStandbyMode(void);
|
||||
void HAL_DBGMCU_DisableDBGStandbyMode(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HAL_Exported_Functions_Group4
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* SBS Control functions *****************************************************/
|
||||
uint32_t HAL_SBS_GetBootAddress(void);
|
||||
|
||||
void HAL_SBS_IncrementHDPLValue(void);
|
||||
uint32_t HAL_SBS_GetHDPLValue(void);
|
||||
|
||||
void HAL_SBS_OpenAccessPort(void);
|
||||
void HAL_SBS_OpenDebug(void);
|
||||
HAL_StatusTypeDef HAL_SBS_ConfigDebugLevel(uint32_t Level);
|
||||
uint32_t HAL_SBS_GetDebugLevel(void);
|
||||
void HAL_SBS_UnlockDebugConfig(void);
|
||||
void HAL_SBS_LockDebugConfig(void);
|
||||
|
||||
void HAL_SBS_ConfigRSSCommand(uint32_t Cmd);
|
||||
uint32_t HAL_SBS_GetRSSCommand(void);
|
||||
|
||||
void HAL_SBS_EnableIOAnalogBooster(void);
|
||||
void HAL_SBS_DisableIOAnalogBooster(void);
|
||||
void HAL_SBS_EnableIOAnalogSwitchVdd(void);
|
||||
void HAL_SBS_DisableIOAnalogSwitchVdd(void);
|
||||
void HAL_SBS_ConfigEthernetPHY(uint32_t Config);
|
||||
void HAL_SBS_ConfigAXISRAMWaitState(uint32_t Config);
|
||||
|
||||
void HAL_SBS_EnableCompensationCell(uint32_t Selection);
|
||||
void HAL_SBS_DisableCompensationCell(uint32_t Selection);
|
||||
uint32_t HAL_SBS_GetCompensationCellReadyStatus(uint32_t Selection);
|
||||
void HAL_SBS_ConfigCompensationCell(uint32_t Selection, uint32_t Code, uint32_t NmosValue,
|
||||
uint32_t PmosValue);
|
||||
HAL_StatusTypeDef HAL_SBS_GetCompensationCell(uint32_t Selection, uint32_t *pCode, uint32_t *pNmosValue,
|
||||
uint32_t *pPmosValue);
|
||||
|
||||
void HAL_SBS_EnableIOSpeedOptimize(uint32_t Selection);
|
||||
void HAL_SBS_DisableIOSpeedOptimize(uint32_t Selection);
|
||||
|
||||
void HAL_SBS_ConfigTimerBreakInput(uint32_t Input);
|
||||
uint32_t HAL_SBS_GetTimerBreakInputConfig(void);
|
||||
|
||||
void HAL_SBS_EXTIConfig(uint32_t Exti, uint32_t Port);
|
||||
uint32_t HAL_SBS_GetEXTIConfig(uint32_t Exti);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HAL_Exported_Functions_Group5
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* VREFBUF Control functions *************************************************/
|
||||
void HAL_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
|
||||
void HAL_VREFBUF_HighImpedanceConfig(uint32_t Mode);
|
||||
void HAL_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
|
||||
HAL_StatusTypeDef HAL_VREFBUF_Enable(void);
|
||||
void HAL_VREFBUF_Disable(void);
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HAL_Exported_Functions_Group6
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* AXIM Configuration functions *************************************************/
|
||||
void HAL_AXIM_ASIB_EnablePacking(AXIM_ASIB_TypeDef *AsibInstance);
|
||||
void HAL_AXIM_ASIB_DisablePacking(AXIM_ASIB_TypeDef *AsibInstance);
|
||||
void HAL_AXIM_ASIB_IssuingConfig(AXIM_ASIB_TypeDef *AsibInstance, uint32_t ReadIssuing,
|
||||
uint32_t WriteIssuing);
|
||||
void HAL_AXIM_ASIB_ReadQoSConfig(AXIM_ASIB_TypeDef *AsibInstance, uint32_t QosPriority);
|
||||
void HAL_AXIM_ASIB_WriteQoSConfig(AXIM_ASIB_TypeDef *AsibInstance, uint32_t QosPriority);
|
||||
|
||||
|
||||
void HAL_AXIM_AMIB_EnablePacking(AXIM_AMIB_TypeDef *AmibInstance);
|
||||
void HAL_AXIM_AMIB_DisablePacking(AXIM_AMIB_TypeDef *AmibInstance);
|
||||
void HAL_AXIM_AMIB_IssuingConfig(AXIM_AMIB_TypeDef *AmibInstance, uint32_t ReadIssuing,
|
||||
uint32_t WriteIssuing);
|
||||
void HAL_AXIM_AMIB_IssuingConfigBusMatrix(AXIM_AMIB_TypeDef *AmibInstance, uint32_t ReadIssuing,
|
||||
uint32_t WriteIssuing);
|
||||
void HAL_AXIM_AMIB_EnableLongBurst(AXIM_AMIB_TypeDef *AmibInstance);
|
||||
void HAL_AXIM_AMIB_DisableLongBurst(AXIM_AMIB_TypeDef *AmibInstance);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7RSxx_HAL_H */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,804 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7rsxx_hal_cec.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CEC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7RSxx_HAL_CEC_H
|
||||
#define STM32H7RSxx_HAL_CEC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7rsxx_hal_def.h"
|
||||
|
||||
#if defined (CEC)
|
||||
|
||||
/** @addtogroup STM32H7RSxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CEC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup CEC_Exported_Types CEC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief CEC Init Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SignalFreeTime; /*!< Set SFT field, specifies the Signal Free Time.
|
||||
It can be one of CEC_Signal_Free_Time
|
||||
and belongs to the set {0,...,7} where
|
||||
0x0 is the default configuration
|
||||
else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */
|
||||
|
||||
uint32_t Tolerance; /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms,
|
||||
it can be a value of CEC_Tolerance :
|
||||
it is either CEC_STANDARD_TOLERANCE or CEC_EXTENDED_TOLERANCE */
|
||||
|
||||
uint32_t BRERxStop; /*!< Set BRESTP bit CEC_BRERxStop : specifies whether or not a Bit Rising
|
||||
Error stops the reception.
|
||||
CEC_NO_RX_STOP_ON_BRE: reception is not stopped.
|
||||
CEC_RX_STOP_ON_BRE: reception is stopped. */
|
||||
|
||||
uint32_t BREErrorBitGen; /*!< Set BREGEN bit CEC_BREErrorBitGen : specifies whether or not an
|
||||
Error-Bit is generated on the
|
||||
CEC line upon Bit Rising Error detection.
|
||||
CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation.
|
||||
CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */
|
||||
|
||||
uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit CEC_LBPEErrorBitGen : specifies whether or not an
|
||||
Error-Bit is generated on the
|
||||
CEC line upon Long Bit Period Error detection.
|
||||
CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation.
|
||||
CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */
|
||||
|
||||
uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit CEC_BroadCastMsgErrorBitGen : allows to avoid an
|
||||
Error-Bit generation on the CEC line
|
||||
upon an error detected on a broadcast message.
|
||||
|
||||
It supersedes BREGEN and LBPEGEN bits for a broadcast message error
|
||||
handling. It can take two values:
|
||||
|
||||
1) CEC_BROADCASTERROR_ERRORBIT_GENERATION.
|
||||
a) BRE detection: error-bit generation on the CEC line if
|
||||
BRESTP=CEC_RX_STOP_ON_BRE and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.
|
||||
b) LBPE detection: error-bit generation on the CEC line
|
||||
if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.
|
||||
|
||||
2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION.
|
||||
no error-bit generation in case neither a) nor b) are satisfied.
|
||||
Additionally, there is no error-bit generation in case of Short Bit
|
||||
Period Error detection in a broadcast message while LSTN bit is set. */
|
||||
|
||||
uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit CEC_SFT_Option : specifies when SFT timer starts.
|
||||
CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software.
|
||||
CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end
|
||||
of message transmission/reception. */
|
||||
|
||||
uint32_t ListenMode; /*!< Set LSTN bit CEC_Listening_Mode : specifies device listening mode.
|
||||
It can take two values:
|
||||
|
||||
CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed
|
||||
to its own address (OAR). Messages addressed to different destination
|
||||
are ignored.
|
||||
Broadcast messages are always received.
|
||||
|
||||
CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its
|
||||
own address (OAR) with positive acknowledge. Messages addressed to
|
||||
different destination are received, but without interfering with the
|
||||
CEC bus: no acknowledge sent. */
|
||||
|
||||
uint16_t OwnAddress; /*!< Own addresses configuration
|
||||
This parameter can be a value of CEC_OWN_ADDRESS */
|
||||
|
||||
uint8_t *RxBuffer; /*!< CEC Rx buffer pointer */
|
||||
|
||||
|
||||
} CEC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL CEC State definition
|
||||
* @note HAL CEC State value is a combination of 2 different substates: gState and RxState
|
||||
(see CEC_State_Definition).
|
||||
* - gState contains CEC state information related to global Handle management
|
||||
* and also information related to Tx operations.
|
||||
* gState value coding follow below described bitmap :
|
||||
* b7 (not used)
|
||||
* x : Should be set to 0
|
||||
* b6 Error information
|
||||
* 0 : No Error
|
||||
* 1 : Error
|
||||
* b5 CEC peripheral initialization status
|
||||
* 0 : Reset (peripheral not initialized)
|
||||
* 1 : Init done (peripheral initialized. HAL CEC Init function already called)
|
||||
* b4-b3 (not used)
|
||||
* xx : Should be set to 00
|
||||
* b2 Intrinsic process state
|
||||
* 0 : Ready
|
||||
* 1 : Busy (peripheral busy with some configuration or internal operations)
|
||||
* b1 (not used)
|
||||
* x : Should be set to 0
|
||||
* b0 Tx state
|
||||
* 0 : Ready (no Tx operation ongoing)
|
||||
* 1 : Busy (Tx operation ongoing)
|
||||
* - RxState contains information related to Rx operations.
|
||||
* RxState value coding follow below described bitmap :
|
||||
* b7-b6 (not used)
|
||||
* xx : Should be set to 00
|
||||
* b5 CEC peripheral initialization status
|
||||
* 0 : Reset (peripheral not initialized)
|
||||
* 1 : Init done (peripheral initialized)
|
||||
* b4-b2 (not used)
|
||||
* xxx : Should be set to 000
|
||||
* b1 Rx state
|
||||
* 0 : Ready (no Rx operation ongoing)
|
||||
* 1 : Busy (Rx operation ongoing)
|
||||
* b0 (not used)
|
||||
* x : Should be set to 0.
|
||||
*/
|
||||
typedef uint32_t HAL_CEC_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CEC handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __CEC_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
|
||||
{
|
||||
CEC_TypeDef *Instance; /*!< CEC registers base address */
|
||||
|
||||
CEC_InitTypeDef Init; /*!< CEC communication parameters */
|
||||
|
||||
const uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */
|
||||
|
||||
uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */
|
||||
|
||||
uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||
|
||||
HAL_CEC_StateTypeDef gState; /*!< CEC state information related to global Handle management
|
||||
and also related to Tx operations.
|
||||
This parameter can be a value of HAL_CEC_StateTypeDef */
|
||||
|
||||
HAL_CEC_StateTypeDef RxState; /*!< CEC state information related to Rx operations.
|
||||
This parameter can be a value of HAL_CEC_StateTypeDef */
|
||||
|
||||
uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register
|
||||
in case error is reported */
|
||||
|
||||
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
|
||||
void (* TxCpltCallback)(struct __CEC_HandleTypeDef
|
||||
*hcec); /*!< CEC Tx Transfer completed callback */
|
||||
void (* RxCpltCallback)(struct __CEC_HandleTypeDef *hcec,
|
||||
uint32_t RxFrameSize); /*!< CEC Rx Transfer completed callback */
|
||||
void (* ErrorCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC error callback */
|
||||
|
||||
void (* MspInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp DeInit callback */
|
||||
|
||||
#endif /* (USE_HAL_CEC_REGISTER_CALLBACKS) */
|
||||
} CEC_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL CEC Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CEC_TX_CPLT_CB_ID = 0x00U, /*!< CEC Tx Transfer completed callback ID */
|
||||
HAL_CEC_RX_CPLT_CB_ID = 0x01U, /*!< CEC Rx Transfer completed callback ID */
|
||||
HAL_CEC_ERROR_CB_ID = 0x02U, /*!< CEC error callback ID */
|
||||
HAL_CEC_MSPINIT_CB_ID = 0x03U, /*!< CEC Msp Init callback ID */
|
||||
HAL_CEC_MSPDEINIT_CB_ID = 0x04U /*!< CEC Msp DeInit callback ID */
|
||||
} HAL_CEC_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL CEC Callback pointer definition
|
||||
*/
|
||||
typedef void (*pCEC_CallbackTypeDef)(CEC_HandleTypeDef *hcec); /*!< pointer to an CEC callback function */
|
||||
typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec,
|
||||
uint32_t RxFrameSize); /*!< pointer to an Rx Transfer completed
|
||||
callback function */
|
||||
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CEC_Exported_Constants CEC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup CEC_State_Definition CEC State Code Definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_CEC_STATE_RESET ((uint32_t)0x00000000) /*!< Peripheral is not yet Initialized
|
||||
Value is allowed for gState and RxState */
|
||||
#define HAL_CEC_STATE_READY ((uint32_t)0x00000020) /*!< Peripheral Initialized and ready for use
|
||||
Value is allowed for gState and RxState */
|
||||
#define HAL_CEC_STATE_BUSY ((uint32_t)0x00000024) /*!< an internal process is ongoing
|
||||
Value is allowed for gState only */
|
||||
#define HAL_CEC_STATE_BUSY_RX ((uint32_t)0x00000022) /*!< Data Reception process is ongoing
|
||||
Value is allowed for RxState only */
|
||||
#define HAL_CEC_STATE_BUSY_TX ((uint32_t)0x00000021) /*!< Data Transmission process is ongoing
|
||||
Value is allowed for gState only */
|
||||
#define HAL_CEC_STATE_BUSY_RX_TX ((uint32_t)0x00000023) /*!< an internal process is ongoing
|
||||
Value is allowed for gState only */
|
||||
#define HAL_CEC_STATE_ERROR ((uint32_t)0x00000050) /*!< Error Value is allowed for gState only */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup CEC_Error_Code CEC Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_CEC_ERROR_NONE (uint32_t) 0x0000U /*!< no error */
|
||||
#define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR /*!< CEC Rx-Overrun */
|
||||
#define HAL_CEC_ERROR_BRE CEC_ISR_BRE /*!< CEC Rx Bit Rising Error */
|
||||
#define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE /*!< CEC Rx Short Bit period Error */
|
||||
#define HAL_CEC_ERROR_LBPE CEC_ISR_LBPE /*!< CEC Rx Long Bit period Error */
|
||||
#define HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE /*!< CEC Rx Missing Acknowledge */
|
||||
#define HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST /*!< CEC Arbitration Lost */
|
||||
#define HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR /*!< CEC Tx-Buffer Underrun */
|
||||
#define HAL_CEC_ERROR_TXERR CEC_ISR_TXERR /*!< CEC Tx-Error */
|
||||
#define HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE /*!< CEC Tx Missing Acknowledge */
|
||||
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_CEC_ERROR_INVALID_CALLBACK ((uint32_t)0x00002000U) /*!< Invalid Callback Error */
|
||||
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Signal_Free_Time CEC Signal Free Time setting parameter
|
||||
* @{
|
||||
*/
|
||||
#define CEC_DEFAULT_SFT ((uint32_t)0x00000000U)
|
||||
#define CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001U)
|
||||
#define CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002U)
|
||||
#define CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003U)
|
||||
#define CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004U)
|
||||
#define CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005U)
|
||||
#define CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006U)
|
||||
#define CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Tolerance CEC Receiver Tolerance
|
||||
* @{
|
||||
*/
|
||||
#define CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000U)
|
||||
#define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_BRERxStop CEC Reception Stop on Error
|
||||
* @{
|
||||
*/
|
||||
#define CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000U)
|
||||
#define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_BREErrorBitGen CEC Error Bit Generation if Bit Rise Error reported
|
||||
* @{
|
||||
*/
|
||||
#define CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)
|
||||
#define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_LBPEErrorBitGen CEC Error Bit Generation if Long Bit Period Error reported
|
||||
* @{
|
||||
*/
|
||||
#define CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)
|
||||
#define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_BroadCastMsgErrorBitGen CEC Error Bit Generation on Broadcast message
|
||||
* @{
|
||||
*/
|
||||
#define CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000U)
|
||||
#define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_SFT_Option CEC Signal Free Time start option
|
||||
* @{
|
||||
*/
|
||||
#define CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000U)
|
||||
#define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Listening_Mode CEC Listening mode option
|
||||
* @{
|
||||
*/
|
||||
#define CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000U)
|
||||
#define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_OAR_Position CEC Device Own Address position in CEC CFGR register
|
||||
* @{
|
||||
*/
|
||||
#define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Initiator_Position CEC Initiator logical address position in message header
|
||||
* @{
|
||||
*/
|
||||
#define CEC_INITIATOR_LSB_POS ((uint32_t) 4U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_OWN_ADDRESS CEC Own Address
|
||||
* @{
|
||||
*/
|
||||
#define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */
|
||||
#define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0 */
|
||||
#define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1 */
|
||||
#define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2 */
|
||||
#define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3 */
|
||||
#define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4 */
|
||||
#define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5 */
|
||||
#define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6 */
|
||||
#define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7 */
|
||||
#define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9 */
|
||||
#define CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) /* Logical Address 10 */
|
||||
#define CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) /* Logical Address 11 */
|
||||
#define CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) /* Logical Address 12 */
|
||||
#define CEC_OWN_ADDRESS_12 ((uint16_t) 0x1000U) /* Logical Address 13 */
|
||||
#define CEC_OWN_ADDRESS_13 ((uint16_t) 0x2000U) /* Logical Address 14 */
|
||||
#define CEC_OWN_ADDRESS_14 ((uint16_t) 0x4000U) /* Logical Address 15 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Interrupts_Definitions CEC Interrupts definition
|
||||
* @{
|
||||
*/
|
||||
#define CEC_IT_TXACKE CEC_IER_TXACKEIE
|
||||
#define CEC_IT_TXERR CEC_IER_TXERRIE
|
||||
#define CEC_IT_TXUDR CEC_IER_TXUDRIE
|
||||
#define CEC_IT_TXEND CEC_IER_TXENDIE
|
||||
#define CEC_IT_TXBR CEC_IER_TXBRIE
|
||||
#define CEC_IT_ARBLST CEC_IER_ARBLSTIE
|
||||
#define CEC_IT_RXACKE CEC_IER_RXACKEIE
|
||||
#define CEC_IT_LBPE CEC_IER_LBPEIE
|
||||
#define CEC_IT_SBPE CEC_IER_SBPEIE
|
||||
#define CEC_IT_BRE CEC_IER_BREIE
|
||||
#define CEC_IT_RXOVR CEC_IER_RXOVRIE
|
||||
#define CEC_IT_RXEND CEC_IER_RXENDIE
|
||||
#define CEC_IT_RXBR CEC_IER_RXBRIE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Flags_Definitions CEC Flags definition
|
||||
* @{
|
||||
*/
|
||||
#define CEC_FLAG_TXACKE CEC_ISR_TXACKE
|
||||
#define CEC_FLAG_TXERR CEC_ISR_TXERR
|
||||
#define CEC_FLAG_TXUDR CEC_ISR_TXUDR
|
||||
#define CEC_FLAG_TXEND CEC_ISR_TXEND
|
||||
#define CEC_FLAG_TXBR CEC_ISR_TXBR
|
||||
#define CEC_FLAG_ARBLST CEC_ISR_ARBLST
|
||||
#define CEC_FLAG_RXACKE CEC_ISR_RXACKE
|
||||
#define CEC_FLAG_LBPE CEC_ISR_LBPE
|
||||
#define CEC_FLAG_SBPE CEC_ISR_SBPE
|
||||
#define CEC_FLAG_BRE CEC_ISR_BRE
|
||||
#define CEC_FLAG_RXOVR CEC_ISR_RXOVR
|
||||
#define CEC_FLAG_RXEND CEC_ISR_RXEND
|
||||
#define CEC_FLAG_RXBR CEC_ISR_RXBR
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags
|
||||
* @{
|
||||
*/
|
||||
#define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
|
||||
CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag
|
||||
* @{
|
||||
*/
|
||||
#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag
|
||||
* @{
|
||||
*/
|
||||
#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup CEC_Exported_Macros CEC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset CEC handle gstate & RxState
|
||||
* @param __HANDLE__ CEC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->gState = HAL_CEC_STATE_RESET; \
|
||||
(__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->gState = HAL_CEC_STATE_RESET; \
|
||||
(__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \
|
||||
} while(0)
|
||||
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
|
||||
/** @brief Checks whether or not the specified CEC interrupt flag is set.
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
|
||||
* @arg CEC_FLAG_TXERR: Tx Error.
|
||||
* @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
|
||||
* @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
|
||||
* @arg CEC_FLAG_TXBR: Tx-Byte Request.
|
||||
* @arg CEC_FLAG_ARBLST: Arbitration Lost
|
||||
* @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
|
||||
* @arg CEC_FLAG_LBPE: Rx Long period Error
|
||||
* @arg CEC_FLAG_SBPE: Rx Short period Error
|
||||
* @arg CEC_FLAG_BRE: Rx Bit Rising Error
|
||||
* @arg CEC_FLAG_RXOVR: Rx Overrun.
|
||||
* @arg CEC_FLAG_RXEND: End Of Reception.
|
||||
* @arg CEC_FLAG_RXBR: Rx-Byte Received.
|
||||
* @retval ITStatus
|
||||
*/
|
||||
#define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
|
||||
|
||||
/** @brief Clears the interrupt or status flag when raised (write at 1)
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @param __FLAG__ specifies the interrupt/status flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
|
||||
* @arg CEC_FLAG_TXERR: Tx Error.
|
||||
* @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
|
||||
* @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
|
||||
* @arg CEC_FLAG_TXBR: Tx-Byte Request.
|
||||
* @arg CEC_FLAG_ARBLST: Arbitration Lost
|
||||
* @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
|
||||
* @arg CEC_FLAG_LBPE: Rx Long period Error
|
||||
* @arg CEC_FLAG_SBPE: Rx Short period Error
|
||||
* @arg CEC_FLAG_BRE: Rx Bit Rising Error
|
||||
* @arg CEC_FLAG_RXOVR: Rx Overrun.
|
||||
* @arg CEC_FLAG_RXEND: End Of Reception.
|
||||
* @arg CEC_FLAG_RXBR: Rx-Byte Received.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__))
|
||||
|
||||
/** @brief Enables the specified CEC interrupt.
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @param __INTERRUPT__ specifies the CEC interrupt to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
|
||||
* @arg CEC_IT_TXERR: Tx Error IT Enable
|
||||
* @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
|
||||
* @arg CEC_IT_TXEND: End of transmission IT Enable
|
||||
* @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
|
||||
* @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
|
||||
* @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
|
||||
* @arg CEC_IT_LBPE: Rx Long period Error IT Enable
|
||||
* @arg CEC_IT_SBPE: Rx Short period Error IT Enable
|
||||
* @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
|
||||
* @arg CEC_IT_RXOVR: Rx Overrun IT Enable
|
||||
* @arg CEC_IT_RXEND: End Of Reception IT Enable
|
||||
* @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
|
||||
|
||||
/** @brief Disables the specified CEC interrupt.
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @param __INTERRUPT__ specifies the CEC interrupt to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
|
||||
* @arg CEC_IT_TXERR: Tx Error IT Enable
|
||||
* @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
|
||||
* @arg CEC_IT_TXEND: End of transmission IT Enable
|
||||
* @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
|
||||
* @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
|
||||
* @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
|
||||
* @arg CEC_IT_LBPE: Rx Long period Error IT Enable
|
||||
* @arg CEC_IT_SBPE: Rx Short period Error IT Enable
|
||||
* @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
|
||||
* @arg CEC_IT_RXOVR: Rx Overrun IT Enable
|
||||
* @arg CEC_IT_RXEND: End Of Reception IT Enable
|
||||
* @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
|
||||
|
||||
/** @brief Checks whether or not the specified CEC interrupt is enabled.
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @param __INTERRUPT__ specifies the CEC interrupt to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
|
||||
* @arg CEC_IT_TXERR: Tx Error IT Enable
|
||||
* @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
|
||||
* @arg CEC_IT_TXEND: End of transmission IT Enable
|
||||
* @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
|
||||
* @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
|
||||
* @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
|
||||
* @arg CEC_IT_LBPE: Rx Long period Error IT Enable
|
||||
* @arg CEC_IT_SBPE: Rx Short period Error IT Enable
|
||||
* @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
|
||||
* @arg CEC_IT_RXOVR: Rx Overrun IT Enable
|
||||
* @arg CEC_IT_RXEND: End Of Reception IT Enable
|
||||
* @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
|
||||
* @retval FlagStatus
|
||||
*/
|
||||
#define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
|
||||
|
||||
/** @brief Enables the CEC device
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN)
|
||||
|
||||
/** @brief Disables the CEC device
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN)
|
||||
|
||||
/** @brief Set Transmission Start flag
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM)
|
||||
|
||||
/** @brief Set Transmission End flag
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @retval none
|
||||
* If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.
|
||||
*/
|
||||
#define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM)
|
||||
|
||||
/** @brief Get Transmission Start flag
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @retval FlagStatus
|
||||
*/
|
||||
#define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
|
||||
|
||||
/** @brief Get Transmission End flag
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @retval FlagStatus
|
||||
*/
|
||||
#define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
|
||||
|
||||
/** @brief Clear OAR register
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
|
||||
|
||||
/** @brief Set OAR register (without resetting previously set address in case of multi-address mode)
|
||||
* To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @param __ADDRESS__ Own Address value (CEC logical address is identified by bit position)
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, \
|
||||
(__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup CEC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CEC_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
|
||||
HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
|
||||
HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress);
|
||||
void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
|
||||
void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
|
||||
|
||||
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID,
|
||||
pCEC_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_CEC_UnRegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID);
|
||||
|
||||
HAL_StatusTypeDef HAL_CEC_RegisterRxCpltCallback(CEC_HandleTypeDef *hcec, pCEC_RxCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec);
|
||||
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CEC_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* I/O operation functions ***************************************************/
|
||||
HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress,
|
||||
const uint8_t *pData, uint32_t Size);
|
||||
uint32_t HAL_CEC_GetLastReceivedFrameSize(const CEC_HandleTypeDef *hcec);
|
||||
void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer);
|
||||
void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
|
||||
void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
|
||||
void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize);
|
||||
void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CEC_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions ************************************************/
|
||||
HAL_CEC_StateTypeDef HAL_CEC_GetState(const CEC_HandleTypeDef *hcec);
|
||||
uint32_t HAL_CEC_GetError(const CEC_HandleTypeDef *hcec);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/** @defgroup CEC_Private_Types CEC Private Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup CEC_Private_Variables CEC Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup CEC_Private_Constants CEC Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup CEC_Private_Macros CEC Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT)
|
||||
|
||||
#define IS_CEC_TOLERANCE(__RXTOL__) (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \
|
||||
((__RXTOL__) == CEC_EXTENDED_TOLERANCE))
|
||||
|
||||
#define IS_CEC_BRERXSTOP(__BRERXSTOP__) (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \
|
||||
((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE))
|
||||
|
||||
#define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \
|
||||
((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION))
|
||||
|
||||
#define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \
|
||||
((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION))
|
||||
|
||||
#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) \
|
||||
(((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
|
||||
((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))
|
||||
|
||||
#define IS_CEC_SFTOP(__SFTOP__) (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \
|
||||
((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END))
|
||||
|
||||
#define IS_CEC_LISTENING_MODE(__MODE__) (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \
|
||||
((__MODE__) == CEC_FULL_LISTENING_MODE))
|
||||
|
||||
/** @brief Check CEC message size.
|
||||
* The message size is the payload size: without counting the header,
|
||||
* it varies from 0 byte (ping operation, one header only, no payload) to
|
||||
* 15 bytes (1 opcode and up to 14 operands following the header).
|
||||
* @param __SIZE__ CEC message size.
|
||||
* @retval Test result (TRUE or FALSE).
|
||||
*/
|
||||
#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U)
|
||||
|
||||
/** @brief Check CEC device Own Address Register (OAR) setting.
|
||||
* OAR address is written in a 15-bit field within CEC_CFGR register.
|
||||
* @param __ADDRESS__ CEC own address.
|
||||
* @retval Test result (TRUE or FALSE).
|
||||
*/
|
||||
#define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFFU)
|
||||
|
||||
/** @brief Check CEC initiator or destination logical address setting.
|
||||
* Initiator and destination addresses are coded over 4 bits.
|
||||
* @param __ADDRESS__ CEC initiator or logical address.
|
||||
* @retval Test result (TRUE or FALSE).
|
||||
*/
|
||||
#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xFU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup CEC_Private_Functions CEC Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* CEC */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7RSxxHAL_CEC_H */
|
||||
|
|
@ -1,507 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7rsxx_hal_conf.h
|
||||
* @author MCD Application Team
|
||||
* @brief HAL configuration template file.
|
||||
* This file should be copied to the application folder and renamed
|
||||
* to stm32h7rsxx_hal_conf.h.
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7RSxx_HAL_CONF_H
|
||||
#define STM32H7RSxx_HAL_CONF_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/* ########################## Module Selection ############################## */
|
||||
/**
|
||||
* @brief This is the list of modules to be used in the HAL driver
|
||||
*/
|
||||
#define HAL_MODULE_ENABLED
|
||||
#define HAL_ADC_MODULE_ENABLED
|
||||
#define HAL_CEC_MODULE_ENABLED
|
||||
#define HAL_CORDIC_MODULE_ENABLED
|
||||
#define HAL_CORTEX_MODULE_ENABLED
|
||||
#define HAL_CRC_MODULE_ENABLED
|
||||
#define HAL_CRYP_MODULE_ENABLED
|
||||
#define HAL_DCMIPP_MODULE_ENABLED
|
||||
#define HAL_DMA_MODULE_ENABLED
|
||||
#define HAL_DMA2D_MODULE_ENABLED
|
||||
#define HAL_DTS_MODULE_ENABLED
|
||||
#define HAL_ETH_MODULE_ENABLED
|
||||
#define HAL_EXTI_MODULE_ENABLED
|
||||
#define HAL_FDCAN_MODULE_ENABLED
|
||||
#define HAL_FLASH_MODULE_ENABLED
|
||||
#define HAL_GFXMMU_MODULE_ENABLED
|
||||
#define HAL_GFXTIM_MODULE_ENABLED
|
||||
#define HAL_GPIO_MODULE_ENABLED
|
||||
#define HAL_GPU2D_MODULE_ENABLED
|
||||
#define HAL_HASH_MODULE_ENABLED
|
||||
#define HAL_HCD_MODULE_ENABLED
|
||||
#define HAL_I2C_MODULE_ENABLED
|
||||
#define HAL_I2S_MODULE_ENABLED
|
||||
#define HAL_I3C_MODULE_ENABLED
|
||||
#define HAL_ICACHE_MODULE_ENABLED
|
||||
#define HAL_IRDA_MODULE_ENABLED
|
||||
#define HAL_IWDG_MODULE_ENABLED
|
||||
#define HAL_JPEG_MODULE_ENABLED
|
||||
#define HAL_LPTIM_MODULE_ENABLED
|
||||
#define HAL_LTDC_MODULE_ENABLED
|
||||
#define HAL_MCE_MODULE_ENABLED
|
||||
#define HAL_MDF_MODULE_ENABLED
|
||||
#define HAL_MMC_MODULE_ENABLED
|
||||
#define HAL_NAND_MODULE_ENABLED
|
||||
#define HAL_NOR_MODULE_ENABLED
|
||||
#define HAL_PCD_MODULE_ENABLED
|
||||
#define HAL_PKA_MODULE_ENABLED
|
||||
#define HAL_PSSI_MODULE_ENABLED
|
||||
#define HAL_PWR_MODULE_ENABLED
|
||||
#define HAL_RAMECC_MODULE_ENABLED
|
||||
#define HAL_RCC_MODULE_ENABLED
|
||||
#define HAL_RNG_MODULE_ENABLED
|
||||
#define HAL_RTC_MODULE_ENABLED
|
||||
#define HAL_SAI_MODULE_ENABLED
|
||||
#define HAL_SD_MODULE_ENABLED
|
||||
#define HAL_SDRAM_MODULE_ENABLED
|
||||
#define HAL_SMARTCARD_MODULE_ENABLED
|
||||
#define HAL_SMBUS_MODULE_ENABLED
|
||||
#define HAL_SPDIFRX_MODULE_ENABLED
|
||||
#define HAL_SPI_MODULE_ENABLED
|
||||
#define HAL_SRAM_MODULE_ENABLED
|
||||
#define HAL_TIM_MODULE_ENABLED
|
||||
#define HAL_UART_MODULE_ENABLED
|
||||
#define HAL_USART_MODULE_ENABLED
|
||||
#define HAL_WWDG_MODULE_ENABLED
|
||||
#define HAL_XSPI_MODULE_ENABLED
|
||||
|
||||
/* ########################## Oscillator Values adaptation ####################*/
|
||||
/**
|
||||
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSE is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
#if !defined (HSE_VALUE)
|
||||
#define HSE_VALUE 24000000UL /*!< Value of the External oscillator in Hz */
|
||||
#endif /* HSE_VALUE */
|
||||
|
||||
#if !defined (HSE_STARTUP_TIMEOUT)
|
||||
#define HSE_STARTUP_TIMEOUT 100UL /*!< Time out for HSE start up (in ms) */
|
||||
#endif /* HSE_STARTUP_TIMEOUT */
|
||||
|
||||
/**
|
||||
* @brief Internal High Speed oscillator (HSI) value.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSI is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
#if !defined (HSI_VALUE)
|
||||
#define HSI_VALUE 64000000UL /*!< Value of the Internal oscillator in Hz */
|
||||
#endif /* HSI_VALUE */
|
||||
|
||||
/**
|
||||
* @brief Internal Low-power oscillator (CSI) default value.
|
||||
* This value is the default CSI range value after Reset.
|
||||
*/
|
||||
#if !defined (CSI_VALUE)
|
||||
#define CSI_VALUE 4000000UL /*!< Value of the Internal oscillator in Hz */
|
||||
#endif /* CSI_VALUE */
|
||||
|
||||
/**
|
||||
* @brief Internal High Speed oscillator (HSI48) value for USB OTG FS and RNG.
|
||||
* This internal oscillator is mainly dedicated to provide a high precision clock to
|
||||
* the USB peripheral by means of a special Clock Recovery System (CRS) circuitry.
|
||||
* When the CRS is not used, the HSI48 RC oscillator runs on it default frequency
|
||||
* which is subject to manufacturing process variations.
|
||||
*/
|
||||
#if !defined (HSI48_VALUE)
|
||||
#define HSI48_VALUE 48000000UL /*!< Value of the Internal High Speed oscillator for USB OTG FS/RNG in Hz.
|
||||
The real value my vary depending on manufacturing process variations. */
|
||||
#endif /* HSI48_VALUE */
|
||||
|
||||
/**
|
||||
* @brief Internal Low Speed oscillator (LSI) value.
|
||||
*/
|
||||
#if !defined (LSI_VALUE)
|
||||
#define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz.
|
||||
Value of the Internal Low Speed oscillator in Hz.
|
||||
The real value may vary depending on the variations
|
||||
in voltage and temperature. */
|
||||
#endif /* LSI_VALUE */
|
||||
|
||||
/**
|
||||
* @brief External Low Speed oscillator (LSE) value.
|
||||
*/
|
||||
#if !defined (LSE_VALUE)
|
||||
#define LSE_VALUE 32768UL /*!< Value of the External oscillator in Hz */
|
||||
#endif /* LSE_VALUE */
|
||||
|
||||
#if !defined (LSE_STARTUP_TIMEOUT)
|
||||
#define LSE_STARTUP_TIMEOUT 5000UL /*!< Time out for LSE start up (in ms) */
|
||||
#endif /* LSE_STARTUP_TIMEOUT */
|
||||
|
||||
/**
|
||||
* @brief External clock source for digital audio interfaces: SPI/I2S, SAI and ADF
|
||||
* This value is used by the RCC HAL module to provide the digital audio interfaces
|
||||
* frequency. This clock source is inserted directly through I2S_CKIN pad.
|
||||
*/
|
||||
#if !defined (EXTERNAL_CLOCK_VALUE)
|
||||
#define EXTERNAL_CLOCK_VALUE 48000UL /*!< Value of the external clock source in Hz */
|
||||
#endif /* EXTERNAL_CLOCK_VALUE */
|
||||
|
||||
/* Tip: To avoid modifying this file each time you need to use different HSE,
|
||||
=== you can define the HSE value in your toolchain compiler preprocessor. */
|
||||
|
||||
/* ########################### System Configuration ######################### */
|
||||
/**
|
||||
* @brief This is the HAL system configuration section
|
||||
*/
|
||||
#define VDD_VALUE 3300UL /*!< Value of VDD in mv */
|
||||
#define TICK_INT_PRIORITY ((1UL<<__NVIC_PRIO_BITS) - 1UL) /*!< tick interrupt priority (lowest by default) */
|
||||
#define USE_RTOS 0U
|
||||
|
||||
/* ########################## Assert Selection ############################## */
|
||||
/**
|
||||
* @brief Uncomment the line below to expanse the "assert_param" macro in the
|
||||
* HAL drivers code
|
||||
*/
|
||||
/* #define USE_FULL_ASSERT 1U */
|
||||
|
||||
/* ################## Register callback feature configuration ############### */
|
||||
/**
|
||||
* @brief Set below the peripheral configuration to "1U" to add the support
|
||||
* of HAL callback registration/unregistration feature for the HAL
|
||||
* driver(s). This allows user application to provide specific callback
|
||||
* functions thanks to HAL_PPP_RegisterCallback() rather than overwriting
|
||||
* the default weak callback functions (see each stm32h7rsxx_hal_ppp.h file
|
||||
* for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef
|
||||
* for each PPP peripheral).
|
||||
*/
|
||||
#define USE_HAL_ADC_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_CEC_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_DCMIPP_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_HASH_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_I2C_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_I2S_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_JPEG_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_MDF_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_MMC_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_NAND_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_NOR_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_PCD_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_PKA_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_PSSI_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_RNG_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_RTC_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_SAI_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_SD_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_SPI_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_TIM_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_UART_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_USART_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_XSPI_REGISTER_CALLBACKS 0U
|
||||
|
||||
/* ################## SPI peripheral configuration ########################## */
|
||||
|
||||
/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
|
||||
* Activated: CRC code is present inside driver
|
||||
* Deactivated: CRC code cleaned from driver
|
||||
*/
|
||||
|
||||
#define USE_SPI_CRC 1U
|
||||
|
||||
/* ################## CRYP peripheral configuration ########################## */
|
||||
|
||||
/**
|
||||
* @brief For code optimization purpose, uncomment and set to "1U" the USE_HAL_CRYP_ONLY or USE_HAL_SAES_ONLY,
|
||||
* to use only one peripheral. Both defines cannot be set to "1U" at the same time.
|
||||
*/
|
||||
|
||||
|
||||
/* #define USE_HAL_CRYP_ONLY 1U */
|
||||
/* #define USE_HAL_SAES_ONLY 0U */
|
||||
|
||||
#define USE_HAL_CRYP_SUSPEND_RESUME 0U
|
||||
|
||||
/* ################## HASH peripheral configuration ########################## */
|
||||
|
||||
#define USE_HAL_HASH_SUSPEND_RESUME 0U
|
||||
|
||||
/* ################## SDMMC peripheral configuration ######################### */
|
||||
|
||||
#define USE_SD_TRANSCEIVER 0U
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Include module's header file
|
||||
*/
|
||||
|
||||
#ifdef HAL_RCC_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_rcc.h"
|
||||
#endif /* HAL_RCC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_GPIO_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_gpio.h"
|
||||
#endif /* HAL_GPIO_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DMA_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_dma.h"
|
||||
#endif /* HAL_DMA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CORTEX_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_cortex.h"
|
||||
#endif /* HAL_CORTEX_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_ADC_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_adc.h"
|
||||
#endif /* HAL_ADC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CEC_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_cec.h"
|
||||
#endif /* HAL_CEC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CORDIC_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_cordic.h"
|
||||
#endif /* HAL_CORDIC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CRC_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_crc.h"
|
||||
#endif /* HAL_CRC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CRYP_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_cryp.h"
|
||||
#endif /* HAL_CRYP_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DCMIPP_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_dcmipp.h"
|
||||
#endif /* HAL_DCMIPP_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DMA2D_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_dma2d.h"
|
||||
#endif /* HAL_DMA2D_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DTS_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_dts.h"
|
||||
#endif /* HAL_DTS_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_ETH_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_eth.h"
|
||||
#endif /* HAL_ETH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_EXTI_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_exti.h"
|
||||
#endif /* HAL_EXTI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_FDCAN_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_fdcan.h"
|
||||
#endif /* HAL_FDCAN_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_FLASH_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_flash.h"
|
||||
#endif /* HAL_FLASH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_GFXMMU_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_gfxmmu.h"
|
||||
#endif /* HAL_GFXMMU_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_GFXTIM_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_gfxtim.h"
|
||||
#endif /* HAL_GFXTIM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_GPU2D_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_gpu2d.h"
|
||||
#endif /* HAL_GPU2D_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_HASH_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_hash.h"
|
||||
#endif /* HAL_HASH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_HCD_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_hcd.h"
|
||||
#endif /* HAL_HCD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I2C_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_i2c.h"
|
||||
#endif /* HAL_I2C_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I2S_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_i2s.h"
|
||||
#endif /* HAL_I2S_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I3C_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_i3c.h"
|
||||
#endif /* HAL_I3C_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_ICACHE_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_icache.h"
|
||||
#endif /* HAL_ICACHE_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IRDA_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_irda.h"
|
||||
#endif /* HAL_IRDA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IWDG_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_iwdg.h"
|
||||
#endif /* HAL_IWDG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_JPEG_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_jpeg.h"
|
||||
#endif /* HAL_JPEG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_LTDC_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_ltdc.h"
|
||||
#endif /* HAL_LTDC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_LPTIM_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_lptim.h"
|
||||
#endif /* HAL_LPTIM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_MCE_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_mce.h"
|
||||
#endif /* HAL_MCE_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_MDF_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_mdf.h"
|
||||
#endif /* HAL_MDF_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_MMC_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_mmc.h"
|
||||
#endif /* HAL_MMC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_NAND_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_nand.h"
|
||||
#endif /* HAL_NAND_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_NOR_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_nor.h"
|
||||
#endif /* HAL_NOR_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PCD_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_pcd.h"
|
||||
#endif /* HAL_PCD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PKA_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_pka.h"
|
||||
#endif /* HAL_PKA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PSSI_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_pssi.h"
|
||||
#endif /* HAL_PSSI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PWR_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_pwr.h"
|
||||
#endif /* HAL_PWR_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RAMECC_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_ramecc.h"
|
||||
#endif /* HAL_RAMECC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RNG_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_rng.h"
|
||||
#endif /* HAL_RNG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RTC_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_rtc.h"
|
||||
#endif /* HAL_RTC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SAI_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_sai.h"
|
||||
#endif /* HAL_SAI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SD_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_sd.h"
|
||||
#endif /* HAL_SD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SDRAM_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_sdram.h"
|
||||
#endif /* HAL_SDRAM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SMARTCARD_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_smartcard.h"
|
||||
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SMBUS_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_smbus.h"
|
||||
#endif /* HAL_SMBUS_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SPDIFRX_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_spdifrx.h"
|
||||
#endif /* HAL_SPDIFRX_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SPI_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_spi.h"
|
||||
#endif /* HAL_SPI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SRAM_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_sram.h"
|
||||
#endif /* HAL_SRAM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_TIM_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_tim.h"
|
||||
#endif /* HAL_TIM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_UART_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_uart.h"
|
||||
#endif /* HAL_UART_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_USART_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_usart.h"
|
||||
#endif /* HAL_USART_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_WWDG_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_wwdg.h"
|
||||
#endif /* HAL_WWDG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_XSPI_MODULE_ENABLED
|
||||
#include "stm32h7rsxx_hal_xspi.h"
|
||||
#endif /* HAL_XSPI_MODULE_ENABLED */
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#ifdef USE_FULL_ASSERT
|
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check.
|
||||
* @param expr If expr is false, it calls assert_failed function
|
||||
* which reports the name of the source file and the source
|
||||
* line number of the call that failed.
|
||||
* If expr is true, it returns no value.
|
||||
* @retval None
|
||||
*/
|
||||
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void assert_failed(uint8_t *file, uint32_t line);
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7RSxx_HAL_CONF_H */
|
||||
|
|
@ -1,609 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7rsxx_hal_cordic.h
|
||||
* @author MCD Application Team
|
||||
* @brief This file contains all the functions prototypes for the CORDIC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7RSxx_HAL_CORDIC_H
|
||||
#define STM32H7RSxx_HAL_CORDIC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7rsxx_hal_def.h"
|
||||
|
||||
#if defined(CORDIC)
|
||||
/** @addtogroup STM32H7RSxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CORDIC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup CORDIC_Exported_Types CORDIC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief CORDIC HAL State Structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CORDIC_STATE_RESET = 0x00U, /*!< CORDIC not yet initialized or disabled */
|
||||
HAL_CORDIC_STATE_READY = 0x01U, /*!< CORDIC initialized and ready for use */
|
||||
HAL_CORDIC_STATE_BUSY = 0x02U, /*!< CORDIC internal process is ongoing */
|
||||
HAL_CORDIC_STATE_ERROR = 0x03U /*!< CORDIC error state */
|
||||
} HAL_CORDIC_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CORDIC Handle Structure definition
|
||||
*/
|
||||
#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
|
||||
typedef struct __CORDIC_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
|
||||
{
|
||||
CORDIC_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
const int32_t *pInBuff; /*!< Pointer to CORDIC input data buffer */
|
||||
|
||||
int32_t *pOutBuff; /*!< Pointer to CORDIC output data buffer */
|
||||
|
||||
uint32_t NbCalcToOrder; /*!< Remaining number of calculation to order */
|
||||
|
||||
uint32_t NbCalcToGet; /*!< Remaining number of calculation result to get */
|
||||
|
||||
uint32_t DMADirection; /*!< Direction of CORDIC DMA transfers */
|
||||
|
||||
DMA_HandleTypeDef *hdmaIn; /*!< CORDIC peripheral input data DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmaOut; /*!< CORDIC peripheral output data DMA handle parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< CORDIC locking object */
|
||||
|
||||
__IO HAL_CORDIC_StateTypeDef State; /*!< CORDIC state */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< CORDIC peripheral error code
|
||||
This parameter can be a value of @ref CORDIC_Error_Code */
|
||||
|
||||
#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
|
||||
void (* ErrorCallback)(struct __CORDIC_HandleTypeDef *hcordic); /*!< CORDIC error callback */
|
||||
void (* CalculateCpltCallback)(struct __CORDIC_HandleTypeDef *hcordic); /*!< CORDIC calculate complete callback */
|
||||
|
||||
void (* MspInitCallback)(struct __CORDIC_HandleTypeDef *hcordic); /*!< CORDIC Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __CORDIC_HandleTypeDef *hcordic); /*!< CORDIC Msp DeInit callback */
|
||||
|
||||
#endif /* (USE_HAL_CORDIC_REGISTER_CALLBACKS) */
|
||||
|
||||
} CORDIC_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CORDIC Config Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Function; /*!< Function
|
||||
This parameter can be a value of @ref CORDIC_Function */
|
||||
|
||||
uint32_t Scale; /*!< Scaling factor
|
||||
This parameter can be a value of @ref CORDIC_Scale */
|
||||
|
||||
uint32_t InSize; /*!< Width of input data
|
||||
This parameter can be a value of @ref CORDIC_In_Size */
|
||||
|
||||
uint32_t OutSize; /*!< Width of output data
|
||||
This parameter can be a value of @ref CORDIC_Out_Size */
|
||||
|
||||
uint32_t NbWrite; /*!< Number of 32-bit write expected for one calculation
|
||||
This parameter can be a value of @ref CORDIC_Nb_Write */
|
||||
|
||||
uint32_t NbRead; /*!< Number of 32-bit read expected after one calculation
|
||||
This parameter can be a value of @ref CORDIC_Nb_Read */
|
||||
|
||||
uint32_t Precision; /*!< Number of cycles for calculation
|
||||
This parameter can be a value of @ref CORDIC_Precision_In_Cycles_Number */
|
||||
|
||||
} CORDIC_ConfigTypeDef;
|
||||
|
||||
#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
|
||||
/**
|
||||
* @brief HAL CORDIC Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CORDIC_ERROR_CB_ID = 0x00U, /*!< CORDIC error callback ID */
|
||||
HAL_CORDIC_CALCULATE_CPLT_CB_ID = 0x01U, /*!< CORDIC calculate complete callback ID */
|
||||
|
||||
HAL_CORDIC_MSPINIT_CB_ID = 0x02U, /*!< CORDIC MspInit callback ID */
|
||||
HAL_CORDIC_MSPDEINIT_CB_ID = 0x03U, /*!< CORDIC MspDeInit callback ID */
|
||||
|
||||
} HAL_CORDIC_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL CORDIC Callback pointer definition
|
||||
*/
|
||||
typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< pointer to a CORDIC callback function */
|
||||
|
||||
#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CORDIC_Exported_Constants CORDIC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CORDIC_Error_Code CORDIC Error code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_CORDIC_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
|
||||
#define HAL_CORDIC_ERROR_PARAM ((uint32_t)0x00000001U) /*!< Wrong parameter error */
|
||||
#define HAL_CORDIC_ERROR_NOT_READY ((uint32_t)0x00000002U) /*!< Peripheral not ready */
|
||||
#define HAL_CORDIC_ERROR_TIMEOUT ((uint32_t)0x00000004U) /*!< Timeout error */
|
||||
#define HAL_CORDIC_ERROR_DMA ((uint32_t)0x00000008U) /*!< DMA error */
|
||||
#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
|
||||
#define HAL_CORDIC_ERROR_INVALID_CALLBACK ((uint32_t)0x00000010U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORDIC_Function CORDIC Function
|
||||
* @{
|
||||
*/
|
||||
#define CORDIC_FUNCTION_COSINE (0x00000000U) /*!< Cosine */
|
||||
#define CORDIC_FUNCTION_SINE ((uint32_t)(CORDIC_CSR_FUNC_0)) /*!< Sine */
|
||||
#define CORDIC_FUNCTION_PHASE ((uint32_t)(CORDIC_CSR_FUNC_1)) /*!< Phase */
|
||||
#define CORDIC_FUNCTION_MODULUS ((uint32_t)(CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0)) /*!< Modulus */
|
||||
#define CORDIC_FUNCTION_ARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2)) /*!< Arctangent */
|
||||
#define CORDIC_FUNCTION_HCOSINE ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_0)) /*!< Hyperbolic Cosine */
|
||||
#define CORDIC_FUNCTION_HSINE ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1)) /*!< Hyperbolic Sine */
|
||||
#define CORDIC_FUNCTION_HARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0))/*!< Hyperbolic Arctangent */
|
||||
#define CORDIC_FUNCTION_NATURALLOG ((uint32_t)(CORDIC_CSR_FUNC_3)) /*!< Natural Logarithm */
|
||||
#define CORDIC_FUNCTION_SQUAREROOT ((uint32_t)(CORDIC_CSR_FUNC_3 | CORDIC_CSR_FUNC_0)) /*!< Square Root */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORDIC_Precision_In_Cycles_Number CORDIC Precision in Cycles Number
|
||||
* @{
|
||||
*/
|
||||
/* Note: 1 cycle corresponds to 4 algorithm iterations */
|
||||
#define CORDIC_PRECISION_1CYCLE ((uint32_t)(CORDIC_CSR_PRECISION_0))
|
||||
#define CORDIC_PRECISION_2CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_1))
|
||||
#define CORDIC_PRECISION_3CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
|
||||
#define CORDIC_PRECISION_4CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2))
|
||||
#define CORDIC_PRECISION_5CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0))
|
||||
#define CORDIC_PRECISION_6CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1))
|
||||
#define CORDIC_PRECISION_7CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2\
|
||||
| CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
|
||||
#define CORDIC_PRECISION_8CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3))
|
||||
#define CORDIC_PRECISION_9CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_0))
|
||||
#define CORDIC_PRECISION_10CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_1))
|
||||
#define CORDIC_PRECISION_11CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
|
||||
| CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
|
||||
#define CORDIC_PRECISION_12CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2))
|
||||
#define CORDIC_PRECISION_13CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
|
||||
| CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0))
|
||||
#define CORDIC_PRECISION_14CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
|
||||
| CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1))
|
||||
#define CORDIC_PRECISION_15CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
|
||||
| CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1\
|
||||
|CORDIC_CSR_PRECISION_0))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORDIC_Scale CORDIC Scaling factor
|
||||
* @{
|
||||
*/
|
||||
/* Scale factor value 'n' implies that the input data have been multiplied
|
||||
by a factor 2exp(-n), and/or the output data need to be multiplied by 2exp(n). */
|
||||
#define CORDIC_SCALE_0 (0x00000000U)
|
||||
#define CORDIC_SCALE_1 ((uint32_t)(CORDIC_CSR_SCALE_0))
|
||||
#define CORDIC_SCALE_2 ((uint32_t)(CORDIC_CSR_SCALE_1))
|
||||
#define CORDIC_SCALE_3 ((uint32_t)(CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0))
|
||||
#define CORDIC_SCALE_4 ((uint32_t)(CORDIC_CSR_SCALE_2))
|
||||
#define CORDIC_SCALE_5 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_0))
|
||||
#define CORDIC_SCALE_6 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1))
|
||||
#define CORDIC_SCALE_7 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORDIC_Interrupts_Enable CORDIC Interrupts Enable bit
|
||||
* @{
|
||||
*/
|
||||
#define CORDIC_IT_IEN CORDIC_CSR_IEN /*!< Result ready interrupt enable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORDIC_DMAR DMA Read Request Enable bit
|
||||
* @{
|
||||
*/
|
||||
#define CORDIC_DMA_REN CORDIC_CSR_DMAREN /*!< DMA Read requests enable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORDIC_DMAW DMA Write Request Enable bit
|
||||
* @{
|
||||
*/
|
||||
#define CORDIC_DMA_WEN CORDIC_CSR_DMAWEN /*!< DMA Write channel enable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORDIC_Nb_Write CORDIC Number of 32-bit write required for one calculation
|
||||
* @{
|
||||
*/
|
||||
#define CORDIC_NBWRITE_1 (0x00000000U) /*!< One 32-bits write containing either only one
|
||||
32-bit data input (Q1.31 format), or two 16-bit
|
||||
data input (Q1.15 format) packed in one 32 bits
|
||||
Data */
|
||||
#define CORDIC_NBWRITE_2 CORDIC_CSR_NARGS /*!< Two 32-bit write containing two 32-bits data input
|
||||
(Q1.31 format) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORDIC_Nb_Read CORDIC Number of 32-bit read required after one calculation
|
||||
* @{
|
||||
*/
|
||||
#define CORDIC_NBREAD_1 (0x00000000U) /*!< One 32-bits read containing either only one
|
||||
32-bit data output (Q1.31 format), or two 16-bit
|
||||
data output (Q1.15 format) packed in one 32 bits
|
||||
Data */
|
||||
#define CORDIC_NBREAD_2 CORDIC_CSR_NRES /*!< Two 32-bit Data containing two 32-bits data output
|
||||
(Q1.31 format) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORDIC_In_Size CORDIC input data size
|
||||
* @{
|
||||
*/
|
||||
#define CORDIC_INSIZE_32BITS (0x00000000U) /*!< 32 bits input data size (Q1.31 format) */
|
||||
#define CORDIC_INSIZE_16BITS CORDIC_CSR_ARGSIZE /*!< 16 bits input data size (Q1.15 format) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORDIC_Out_Size CORDIC Results Size
|
||||
* @{
|
||||
*/
|
||||
#define CORDIC_OUTSIZE_32BITS (0x00000000U) /*!< 32 bits output data size (Q1.31 format) */
|
||||
#define CORDIC_OUTSIZE_16BITS CORDIC_CSR_RESSIZE /*!< 16 bits output data size (Q1.15 format) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORDIC_Flags CORDIC status flags
|
||||
* @{
|
||||
*/
|
||||
#define CORDIC_FLAG_RRDY CORDIC_CSR_RRDY /*!< Result Ready Flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORDIC_DMA_Direction CORDIC DMA direction
|
||||
* @{
|
||||
*/
|
||||
#define CORDIC_DMA_DIR_NONE ((uint32_t)0x00000000U) /*!< DMA direction : none */
|
||||
#define CORDIC_DMA_DIR_IN ((uint32_t)0x00000001U) /*!< DMA direction : Input of CORDIC */
|
||||
#define CORDIC_DMA_DIR_OUT ((uint32_t)0x00000002U) /*!< DMA direction : Output of CORDIC */
|
||||
#define CORDIC_DMA_DIR_IN_OUT ((uint32_t)0x00000003U) /*!< DMA direction : Input and Output of CORDIC */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup CORDIC_Exported_Macros CORDIC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset CORDIC handle state.
|
||||
* @param __HANDLE__ CORDIC handle
|
||||
* @retval None
|
||||
*/
|
||||
#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
|
||||
#define __HAL_CORDIC_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_CORDIC_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_CORDIC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CORDIC_STATE_RESET)
|
||||
#endif /*USE_HAL_CORDIC_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @brief Enable the CORDIC interrupt when result is ready
|
||||
* @param __HANDLE__ CORDIC handle.
|
||||
* @param __INTERRUPT__ CORDIC Interrupt.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref CORDIC_IT_IEN Enable Interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CORDIC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
|
||||
(((__HANDLE__)->Instance->CSR) |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the CORDIC interrupt
|
||||
* @param __HANDLE__ CORDIC handle.
|
||||
* @param __INTERRUPT__ CORDIC Interrupt.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref CORDIC_IT_IEN Enable Interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CORDIC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
|
||||
(((__HANDLE__)->Instance->CSR) &= ~(__INTERRUPT__))
|
||||
|
||||
/** @brief Check whether the specified CORDIC interrupt occurred or not.
|
||||
Dummy macro as no interrupt status flag.
|
||||
* @param __HANDLE__ CORDIC handle.
|
||||
* @param __INTERRUPT__ CORDIC interrupt to check
|
||||
* @retval SET (interrupt occurred) or RESET (interrupt did not occurred)
|
||||
*/
|
||||
#define __HAL_CORDIC_GET_IT(__HANDLE__, __INTERRUPT__) /* Dummy macro */
|
||||
|
||||
/** @brief Clear specified CORDIC interrupt status. Dummy macro as no
|
||||
interrupt status flag.
|
||||
* @param __HANDLE__ CORDIC handle.
|
||||
* @param __INTERRUPT__ CORDIC interrupt to clear
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CORDIC_CLEAR_IT(__HANDLE__, __INTERRUPT__) /* Dummy macro */
|
||||
|
||||
/** @brief Check whether the specified CORDIC status flag is set or not.
|
||||
* @param __HANDLE__ CORDIC handle.
|
||||
* @param __FLAG__ CORDIC flag to check
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref CORDIC_FLAG_RRDY Result Ready Flag
|
||||
* @retval SET (flag is set) or RESET (flag is reset)
|
||||
*/
|
||||
#define __HAL_CORDIC_GET_FLAG(__HANDLE__, __FLAG__) \
|
||||
((((__HANDLE__)->Instance->CSR) & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clear specified CORDIC status flag. Dummy macro as no
|
||||
flag can be cleared.
|
||||
* @param __HANDLE__ CORDIC handle.
|
||||
* @param __FLAG__ CORDIC flag to clear
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref CORDIC_FLAG_RRDY Result Ready Flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CORDIC_CLEAR_FLAG(__HANDLE__, __FLAG__) /* Dummy macro */
|
||||
|
||||
/** @brief Check whether the specified CORDIC interrupt is enabled or not.
|
||||
* @param __HANDLE__ CORDIC handle.
|
||||
* @param __INTERRUPT__ CORDIC interrupt to check
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref CORDIC_IT_IEN Enable Interrupt
|
||||
* @retval FlagStatus
|
||||
*/
|
||||
#define __HAL_CORDIC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
|
||||
(((__HANDLE__)->Instance->CSR) & (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros --------------------------------------------------------*/
|
||||
/** @defgroup CORDIC_Private_Macros CORDIC Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Verify the CORDIC function.
|
||||
* @param __FUNCTION__ Name of the function.
|
||||
* @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
|
||||
*/
|
||||
#define IS_CORDIC_FUNCTION(__FUNCTION__) (((__FUNCTION__) == CORDIC_FUNCTION_COSINE) || \
|
||||
((__FUNCTION__) == CORDIC_FUNCTION_SINE) || \
|
||||
((__FUNCTION__) == CORDIC_FUNCTION_PHASE) || \
|
||||
((__FUNCTION__) == CORDIC_FUNCTION_MODULUS) || \
|
||||
((__FUNCTION__) == CORDIC_FUNCTION_ARCTANGENT) || \
|
||||
((__FUNCTION__) == CORDIC_FUNCTION_HCOSINE) || \
|
||||
((__FUNCTION__) == CORDIC_FUNCTION_HSINE) || \
|
||||
((__FUNCTION__) == CORDIC_FUNCTION_HARCTANGENT) || \
|
||||
((__FUNCTION__) == CORDIC_FUNCTION_NATURALLOG) || \
|
||||
((__FUNCTION__) == CORDIC_FUNCTION_SQUAREROOT))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Verify the CORDIC precision.
|
||||
* @param __PRECISION__ CORDIC Precision in Cycles Number.
|
||||
* @retval SET (__PRECISION__ is a valid value) or RESET (__PRECISION__ is invalid)
|
||||
*/
|
||||
#define IS_CORDIC_PRECISION(__PRECISION__) (((__PRECISION__) == CORDIC_PRECISION_1CYCLE) || \
|
||||
((__PRECISION__) == CORDIC_PRECISION_2CYCLES) || \
|
||||
((__PRECISION__) == CORDIC_PRECISION_3CYCLES) || \
|
||||
((__PRECISION__) == CORDIC_PRECISION_4CYCLES) || \
|
||||
((__PRECISION__) == CORDIC_PRECISION_5CYCLES) || \
|
||||
((__PRECISION__) == CORDIC_PRECISION_6CYCLES) || \
|
||||
((__PRECISION__) == CORDIC_PRECISION_7CYCLES) || \
|
||||
((__PRECISION__) == CORDIC_PRECISION_8CYCLES) || \
|
||||
((__PRECISION__) == CORDIC_PRECISION_9CYCLES) || \
|
||||
((__PRECISION__) == CORDIC_PRECISION_10CYCLES) || \
|
||||
((__PRECISION__) == CORDIC_PRECISION_11CYCLES) || \
|
||||
((__PRECISION__) == CORDIC_PRECISION_12CYCLES) || \
|
||||
((__PRECISION__) == CORDIC_PRECISION_13CYCLES) || \
|
||||
((__PRECISION__) == CORDIC_PRECISION_14CYCLES) || \
|
||||
((__PRECISION__) == CORDIC_PRECISION_15CYCLES))
|
||||
|
||||
/**
|
||||
* @brief Verify the CORDIC scaling factor.
|
||||
* @param __SCALE__ Number of cycles for calculation, 1 cycle corresponding to 4 algorithm iterations.
|
||||
* @retval SET (__SCALE__ is a valid value) or RESET (__SCALE__ is invalid)
|
||||
*/
|
||||
#define IS_CORDIC_SCALE(__SCALE__) (((__SCALE__) == CORDIC_SCALE_0) || \
|
||||
((__SCALE__) == CORDIC_SCALE_1) || \
|
||||
((__SCALE__) == CORDIC_SCALE_2) || \
|
||||
((__SCALE__) == CORDIC_SCALE_3) || \
|
||||
((__SCALE__) == CORDIC_SCALE_4) || \
|
||||
((__SCALE__) == CORDIC_SCALE_5) || \
|
||||
((__SCALE__) == CORDIC_SCALE_6) || \
|
||||
((__SCALE__) == CORDIC_SCALE_7))
|
||||
|
||||
/**
|
||||
* @brief Verify the CORDIC number of 32-bits write expected for one calculation.
|
||||
* @param __NBWRITE__ Number of 32-bits write expected for one calculation.
|
||||
* @retval SET (__NBWRITE__ is a valid value) or RESET (__NBWRITE__ is invalid)
|
||||
*/
|
||||
#define IS_CORDIC_NBWRITE(__NBWRITE__) (((__NBWRITE__) == CORDIC_NBWRITE_1) || \
|
||||
((__NBWRITE__) == CORDIC_NBWRITE_2))
|
||||
|
||||
/**
|
||||
* @brief Verify the CORDIC number of 32-bits read expected after one calculation.
|
||||
* @param __NBREAD__ Number of 32-bits read expected after one calculation.
|
||||
* @retval SET (__NBREAD__ is a valid value) or RESET (__NBREAD__ is invalid)
|
||||
*/
|
||||
#define IS_CORDIC_NBREAD(__NBREAD__) (((__NBREAD__) == CORDIC_NBREAD_1) || \
|
||||
((__NBREAD__) == CORDIC_NBREAD_2))
|
||||
|
||||
/**
|
||||
* @brief Verify the CORDIC input data size for one calculation.
|
||||
* @param __INSIZE__ input data size for one calculation.
|
||||
* @retval SET (__INSIZE__ is a valid value) or RESET (__INSIZE__ is invalid)
|
||||
*/
|
||||
#define IS_CORDIC_INSIZE(__INSIZE__) (((__INSIZE__) == CORDIC_INSIZE_32BITS) || \
|
||||
((__INSIZE__) == CORDIC_INSIZE_16BITS))
|
||||
|
||||
/**
|
||||
* @brief Verify the CORDIC output data size for one calculation.
|
||||
* @param __OUTSIZE__ output data size for one calculation.
|
||||
* @retval SET (__OUTSIZE__ is a valid value) or RESET (__OUTSIZE__ is invalid)
|
||||
*/
|
||||
#define IS_CORDIC_OUTSIZE(__OUTSIZE__) (((__OUTSIZE__) == CORDIC_OUTSIZE_32BITS) || \
|
||||
((__OUTSIZE__) == CORDIC_OUTSIZE_16BITS))
|
||||
|
||||
/**
|
||||
* @brief Verify the CORDIC DMA transfer Direction.
|
||||
* @param __DMADIR__ DMA transfer direction.
|
||||
* @retval SET (__DMADIR__ is a valid value) or RESET (__DMADIR__ is invalid)
|
||||
*/
|
||||
#define IS_CORDIC_DMA_DIRECTION(__DMADIR__) (((__DMADIR__) == CORDIC_DMA_DIR_IN) || \
|
||||
((__DMADIR__) == CORDIC_DMA_DIR_OUT) || \
|
||||
((__DMADIR__) == CORDIC_DMA_DIR_IN_OUT))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CORDIC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/** @addtogroup CORDIC_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions ******************************/
|
||||
HAL_StatusTypeDef HAL_CORDIC_Init(CORDIC_HandleTypeDef *hcordic);
|
||||
HAL_StatusTypeDef HAL_CORDIC_DeInit(CORDIC_HandleTypeDef *hcordic);
|
||||
void HAL_CORDIC_MspInit(CORDIC_HandleTypeDef *hcordic);
|
||||
void HAL_CORDIC_MspDeInit(CORDIC_HandleTypeDef *hcordic);
|
||||
|
||||
#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
HAL_StatusTypeDef HAL_CORDIC_RegisterCallback(CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID,
|
||||
pCORDIC_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_CORDIC_UnRegisterCallback(CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CORDIC_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_CORDIC_Configure(CORDIC_HandleTypeDef *hcordic, const CORDIC_ConfigTypeDef *sConfig);
|
||||
HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff,
|
||||
uint32_t NbCalc, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff,
|
||||
uint32_t NbCalc, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff,
|
||||
uint32_t NbCalc);
|
||||
HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff,
|
||||
uint32_t NbCalc, uint32_t DMADirection);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CORDIC_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Callback functions *********************************************************/
|
||||
void HAL_CORDIC_ErrorCallback(CORDIC_HandleTypeDef *hcordic);
|
||||
void HAL_CORDIC_CalculateCpltCallback(CORDIC_HandleTypeDef *hcordic);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CORDIC_Exported_Functions_Group4
|
||||
* @{
|
||||
*/
|
||||
/* IRQ handler management *****************************************************/
|
||||
void HAL_CORDIC_IRQHandler(CORDIC_HandleTypeDef *hcordic);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CORDIC_Exported_Functions_Group5
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions *************************************************/
|
||||
HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(const CORDIC_HandleTypeDef *hcordic);
|
||||
uint32_t HAL_CORDIC_GetError(const CORDIC_HandleTypeDef *hcordic);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* CORDIC */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7RSxx_HAL_CORDIC_H */
|
||||
|
|
@ -1,409 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7rsxx_hal_cortex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CORTEX HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7RSxx_HAL_CORTEX_H
|
||||
#define STM32H7RSxx_HAL_CORTEX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7rsxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H7RSxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX CORTEX
|
||||
* @brief CORTEX HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup CORTEX_Exported_Types CORTEX Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
|
||||
* @brief MPU Region initialization structure
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t Enable; /*!< Specifies the status of the region.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
|
||||
uint8_t Number; /*!< Specifies the number of the region to protect.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Number */
|
||||
uint32_t BaseAddress; /*!< Specifies the base address of the region to protect.
|
||||
*/
|
||||
uint8_t Size; /*!< Specifies the size of the region to protect.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Size */
|
||||
uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
|
||||
uint8_t TypeExtField; /*!< Specifies the TEX field level.
|
||||
This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
|
||||
uint8_t AccessPermission; /*!< Specifies the region access permission type.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
|
||||
uint8_t DisableExec; /*!< Specifies the instruction access status.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
|
||||
uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
|
||||
uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
|
||||
uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
|
||||
} MPU_Region_InitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
|
||||
* @{
|
||||
*/
|
||||
#define NVIC_PRIORITYGROUP_0 7U /*!< 0 bit for pre-emption priority,
|
||||
4 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_1 6U /*!< 1 bit for pre-emption priority,
|
||||
3 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_2 5U /*!< 2 bits for pre-emption priority,
|
||||
2 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_3 4U /*!< 3 bits for pre-emption priority,
|
||||
1 bit for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_4 3U /*!< 4 bits for pre-emption priority,
|
||||
0 bit for subpriority */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
|
||||
* @{
|
||||
*/
|
||||
#define SYSTICK_CLKSOURCE_HCLK_DIV8 0U
|
||||
#define SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control
|
||||
* @{
|
||||
*/
|
||||
#define MPU_HFNMI_PRIVDEF_NONE 0U
|
||||
#define MPU_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk
|
||||
#define MPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk
|
||||
#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
|
||||
* @{
|
||||
*/
|
||||
#define MPU_REGION_ENABLE 1U
|
||||
#define MPU_REGION_DISABLE 0U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
|
||||
* @{
|
||||
*/
|
||||
#define MPU_INSTRUCTION_ACCESS_ENABLE 0U
|
||||
#define MPU_INSTRUCTION_ACCESS_DISABLE 1U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
|
||||
* @{
|
||||
*/
|
||||
#define MPU_ACCESS_NOT_SHAREABLE 0U
|
||||
#define MPU_ACCESS_SHAREABLE 1U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
|
||||
* @{
|
||||
*/
|
||||
#define MPU_ACCESS_CACHEABLE 1U
|
||||
#define MPU_ACCESS_NOT_CACHEABLE 0U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
|
||||
* @{
|
||||
*/
|
||||
#define MPU_ACCESS_BUFFERABLE 1U
|
||||
#define MPU_ACCESS_NOT_BUFFERABLE 0U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels
|
||||
* @{
|
||||
*/
|
||||
#define MPU_TEX_LEVEL0 0U
|
||||
#define MPU_TEX_LEVEL1 1U
|
||||
#define MPU_TEX_LEVEL2 2U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
|
||||
* @{
|
||||
*/
|
||||
#define MPU_REGION_SIZE_32B 0x04U
|
||||
#define MPU_REGION_SIZE_64B 0x05U
|
||||
#define MPU_REGION_SIZE_128B 0x06U
|
||||
#define MPU_REGION_SIZE_256B 0x07U
|
||||
#define MPU_REGION_SIZE_512B 0x08U
|
||||
#define MPU_REGION_SIZE_1KB 0x09U
|
||||
#define MPU_REGION_SIZE_2KB 0x0AU
|
||||
#define MPU_REGION_SIZE_4KB 0x0BU
|
||||
#define MPU_REGION_SIZE_8KB 0x0CU
|
||||
#define MPU_REGION_SIZE_16KB 0x0DU
|
||||
#define MPU_REGION_SIZE_32KB 0x0EU
|
||||
#define MPU_REGION_SIZE_64KB 0x0FU
|
||||
#define MPU_REGION_SIZE_128KB 0x10U
|
||||
#define MPU_REGION_SIZE_256KB 0x11U
|
||||
#define MPU_REGION_SIZE_512KB 0x12U
|
||||
#define MPU_REGION_SIZE_1MB 0x13U
|
||||
#define MPU_REGION_SIZE_2MB 0x14U
|
||||
#define MPU_REGION_SIZE_4MB 0x15U
|
||||
#define MPU_REGION_SIZE_8MB 0x16U
|
||||
#define MPU_REGION_SIZE_16MB 0x17U
|
||||
#define MPU_REGION_SIZE_32MB 0x18U
|
||||
#define MPU_REGION_SIZE_64MB 0x19U
|
||||
#define MPU_REGION_SIZE_128MB 0x1AU
|
||||
#define MPU_REGION_SIZE_256MB 0x1BU
|
||||
#define MPU_REGION_SIZE_512MB 0x1CU
|
||||
#define MPU_REGION_SIZE_1GB 0x1DU
|
||||
#define MPU_REGION_SIZE_2GB 0x1EU
|
||||
#define MPU_REGION_SIZE_4GB 0x1FU
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
|
||||
* @{
|
||||
*/
|
||||
#define MPU_REGION_NO_ACCESS 0U
|
||||
#define MPU_REGION_PRIV_RW 1U
|
||||
#define MPU_REGION_PRIV_RW_URO 2U
|
||||
#define MPU_REGION_FULL_ACCESS 3U
|
||||
#define MPU_REGION_PRIV_RO 5U
|
||||
#define MPU_REGION_PRIV_RO_URO 6U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
|
||||
* @{
|
||||
*/
|
||||
#define MPU_REGION_NUMBER0 0U
|
||||
#define MPU_REGION_NUMBER1 1U
|
||||
#define MPU_REGION_NUMBER2 2U
|
||||
#define MPU_REGION_NUMBER3 3U
|
||||
#define MPU_REGION_NUMBER4 4U
|
||||
#define MPU_REGION_NUMBER5 5U
|
||||
#define MPU_REGION_NUMBER6 6U
|
||||
#define MPU_REGION_NUMBER7 7U
|
||||
#define MPU_REGION_NUMBER8 8U
|
||||
#define MPU_REGION_NUMBER9 9U
|
||||
#define MPU_REGION_NUMBER10 10U
|
||||
#define MPU_REGION_NUMBER11 11U
|
||||
#define MPU_REGION_NUMBER12 12U
|
||||
#define MPU_REGION_NUMBER13 13U
|
||||
#define MPU_REGION_NUMBER14 14U
|
||||
#define MPU_REGION_NUMBER15 15U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions
|
||||
* @brief Initialization and Configuration functions
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and Configuration functions *****************************/
|
||||
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
|
||||
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
|
||||
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_SystemReset(void);
|
||||
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @brief Cortex control functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
uint32_t HAL_NVIC_GetPriorityGrouping(void);
|
||||
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority);
|
||||
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
|
||||
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
|
||||
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
|
||||
void HAL_SYSTICK_IRQHandler(void);
|
||||
void HAL_SYSTICK_Callback(void);
|
||||
void HAL_MPU_Enable(uint32_t MPU_Control);
|
||||
void HAL_MPU_Disable(void);
|
||||
void HAL_MPU_EnableRegion(uint32_t RegionNumber);
|
||||
void HAL_MPU_DisableRegion(uint32_t RegionNumber);
|
||||
void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *pMPU_RegionInit);
|
||||
void HAL_CORTEX_ClearEvent(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_NVIC_PRIORITY_GROUP(__GROUP__) (((__GROUP__) == NVIC_PRIORITYGROUP_0) || \
|
||||
((__GROUP__) == NVIC_PRIORITYGROUP_1) || \
|
||||
((__GROUP__) == NVIC_PRIORITYGROUP_2) || \
|
||||
((__GROUP__) == NVIC_PRIORITYGROUP_3) || \
|
||||
((__GROUP__) == NVIC_PRIORITYGROUP_4))
|
||||
|
||||
#define IS_NVIC_PREEMPTION_PRIORITY(__PRIO__, __PRIOGRP__) (((__PRIO__) < (1uL << __NVIC_PRIO_BITS)) && \
|
||||
((__PRIO__) < (0x1uL << (0x07u - __PRIOGRP__))))
|
||||
|
||||
#define IS_NVIC_SUB_PRIORITY(__PRIO__, __PRIOGRP__) \
|
||||
((__PRIOGRP__ < (0x07u - __NVIC_PRIO_BITS)) ?\
|
||||
((__PRIO__) < (1u)): \
|
||||
((__PRIO__) < (0x1uL << (__PRIOGRP__ - (0x07u - __NVIC_PRIO_BITS)))))
|
||||
|
||||
#define IS_NVIC_DEVICE_IRQ(__IRQ__) ((__IRQ__) > SysTick_IRQn)
|
||||
|
||||
#define IS_NVIC_PRIO_INTERRUPT(__IT__) (((__IT__) > HardFault_IRQn) && ((__IT__) != DebugMonitor_IRQn))
|
||||
|
||||
#define IS_SYSTICK_CLK_SOURCE(__SOURCE__) (((__SOURCE__) == SYSTICK_CLKSOURCE_HCLK) || \
|
||||
((__SOURCE__) == SYSTICK_CLKSOURCE_HCLK_DIV8))
|
||||
|
||||
#define IS_MPU_REGION_ENABLE(__STATE__) (((__STATE__) == MPU_REGION_ENABLE) || \
|
||||
((__STATE__) == MPU_REGION_DISABLE))
|
||||
|
||||
#define IS_MPU_INSTRUCTION_ACCESS(__STATE__) (((__STATE__) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
|
||||
((__STATE__) == MPU_INSTRUCTION_ACCESS_DISABLE))
|
||||
|
||||
#define IS_MPU_ACCESS_SHAREABLE(__STATE__) (((__STATE__) == MPU_ACCESS_SHAREABLE) || \
|
||||
((__STATE__) == MPU_ACCESS_NOT_SHAREABLE))
|
||||
|
||||
#define IS_MPU_ACCESS_CACHEABLE(__STATE__) (((__STATE__) == MPU_ACCESS_CACHEABLE) || \
|
||||
((__STATE__) == MPU_ACCESS_NOT_CACHEABLE))
|
||||
|
||||
#define IS_MPU_ACCESS_BUFFERABLE(__STATE__) (((__STATE__) == MPU_ACCESS_BUFFERABLE) || \
|
||||
((__STATE__) == MPU_ACCESS_NOT_BUFFERABLE))
|
||||
|
||||
#define IS_MPU_TEX_LEVEL(__TYPE__) (((__TYPE__) == MPU_TEX_LEVEL0) || \
|
||||
((__TYPE__) == MPU_TEX_LEVEL1) || \
|
||||
((__TYPE__) == MPU_TEX_LEVEL2))
|
||||
|
||||
#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(__TYPE__) (((__TYPE__) == MPU_REGION_NO_ACCESS) || \
|
||||
((__TYPE__) == MPU_REGION_PRIV_RW) || \
|
||||
((__TYPE__) == MPU_REGION_PRIV_RW_URO) || \
|
||||
((__TYPE__) == MPU_REGION_FULL_ACCESS) || \
|
||||
((__TYPE__) == MPU_REGION_PRIV_RO) || \
|
||||
((__TYPE__) == MPU_REGION_PRIV_RO_URO))
|
||||
|
||||
#define IS_MPU_REGION_NUMBER(__NUMBER__) ((__NUMBER__) <= MPU_REGION_NUMBER15)
|
||||
|
||||
#define IS_MPU_REGION_SIZE(__SIZE__) (((__SIZE__) == MPU_REGION_SIZE_32B) || \
|
||||
((__SIZE__) == MPU_REGION_SIZE_64B) || \
|
||||
((__SIZE__) == MPU_REGION_SIZE_128B) || \
|
||||
((__SIZE__) == MPU_REGION_SIZE_256B) || \
|
||||
((__SIZE__) == MPU_REGION_SIZE_512B) || \
|
||||
((__SIZE__) == MPU_REGION_SIZE_1KB) || \
|
||||
((__SIZE__) == MPU_REGION_SIZE_2KB) || \
|
||||
((__SIZE__) == MPU_REGION_SIZE_4KB) || \
|
||||
((__SIZE__) == MPU_REGION_SIZE_8KB) || \
|
||||
((__SIZE__) == MPU_REGION_SIZE_16KB) || \
|
||||
((__SIZE__) == MPU_REGION_SIZE_32KB) || \
|
||||
((__SIZE__) == MPU_REGION_SIZE_64KB) || \
|
||||
((__SIZE__) == MPU_REGION_SIZE_128KB) || \
|
||||
((__SIZE__) == MPU_REGION_SIZE_256KB) || \
|
||||
((__SIZE__) == MPU_REGION_SIZE_512KB) || \
|
||||
((__SIZE__) == MPU_REGION_SIZE_1MB) || \
|
||||
((__SIZE__) == MPU_REGION_SIZE_2MB) || \
|
||||
((__SIZE__) == MPU_REGION_SIZE_4MB) || \
|
||||
((__SIZE__) == MPU_REGION_SIZE_8MB) || \
|
||||
((__SIZE__) == MPU_REGION_SIZE_16MB) || \
|
||||
((__SIZE__) == MPU_REGION_SIZE_32MB) || \
|
||||
((__SIZE__) == MPU_REGION_SIZE_64MB) || \
|
||||
((__SIZE__) == MPU_REGION_SIZE_128MB) || \
|
||||
((__SIZE__) == MPU_REGION_SIZE_256MB) || \
|
||||
((__SIZE__) == MPU_REGION_SIZE_512MB) || \
|
||||
((__SIZE__) == MPU_REGION_SIZE_1GB) || \
|
||||
((__SIZE__) == MPU_REGION_SIZE_2GB) || \
|
||||
((__SIZE__) == MPU_REGION_SIZE_4GB))
|
||||
|
||||
#define IS_MPU_SUB_REGION_DISABLE(__SUBREGION__) ((__SUBREGION__) < (uint16_t)0x00FFU)
|
||||
|
||||
#define IS_MPU_ADDRESS_MULTIPLE_SIZE(__ADDRESS__, __SIZE__) (((__ADDRESS__) & ((1<<(__SIZE__+1U))- 1U)) == 0U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7RSxx_HAL_CORTEX_H */
|
||||
|
|
@ -1,342 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7rsxx_hal_crc.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CRC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7RSxx_HAL_CRC_H
|
||||
#define STM32H7RSxx_HAL_CRC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7rsxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H7RSxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup CRC_Exported_Types CRC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief CRC HAL State Structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CRC_STATE_RESET = 0x00U, /*!< CRC not yet initialized or disabled */
|
||||
HAL_CRC_STATE_READY = 0x01U, /*!< CRC initialized and ready for use */
|
||||
HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */
|
||||
HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */
|
||||
HAL_CRC_STATE_ERROR = 0x04U /*!< CRC error state */
|
||||
} HAL_CRC_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CRC Init Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.
|
||||
If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default
|
||||
X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 +
|
||||
X^4 + X^2+ X +1.
|
||||
In that case, there is no need to set GeneratingPolynomial field.
|
||||
If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and
|
||||
CRCLength fields must be set. */
|
||||
|
||||
uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used.
|
||||
If set to DEFAULT_INIT_VALUE_ENABLE, resort to default
|
||||
0xFFFFFFFF value. In that case, there is no need to set InitValue field. If
|
||||
otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */
|
||||
|
||||
uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree
|
||||
respectively equal to 7, 8, 16 or 32. This field is written in normal,
|
||||
representation e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1
|
||||
is written 0x65. No need to specify it if DefaultPolynomialUse is set to
|
||||
DEFAULT_POLYNOMIAL_ENABLE. */
|
||||
|
||||
uint32_t CRCLength; /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length.
|
||||
Value can be either one of
|
||||
@arg @ref CRC_POLYLENGTH_32B (32-bit CRC),
|
||||
@arg @ref CRC_POLYLENGTH_16B (16-bit CRC),
|
||||
@arg @ref CRC_POLYLENGTH_8B (8-bit CRC),
|
||||
@arg @ref CRC_POLYLENGTH_7B (7-bit CRC). */
|
||||
|
||||
uint32_t InitValue; /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse
|
||||
is set to DEFAULT_INIT_VALUE_ENABLE. */
|
||||
|
||||
uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode.
|
||||
Can be either one of the following values
|
||||
@arg @ref CRC_INPUTDATA_INVERSION_NONE no input data inversion
|
||||
@arg @ref CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D
|
||||
becomes 0x58D43CB2
|
||||
@arg @ref CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion,
|
||||
0x1A2B3C4D becomes 0xD458B23C
|
||||
@arg @ref CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D
|
||||
becomes 0xB23CD458 */
|
||||
|
||||
uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
|
||||
Can be either
|
||||
@arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion,
|
||||
@arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted
|
||||
into 0x22CC4488 */
|
||||
} CRC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CRC Handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
CRC_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
CRC_InitTypeDef Init; /*!< CRC configuration parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< CRC Locking object */
|
||||
|
||||
__IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */
|
||||
|
||||
uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format.
|
||||
Can be either
|
||||
@arg @ref CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes
|
||||
(8-bit data)
|
||||
@arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of
|
||||
half-words (16-bit data)
|
||||
@arg @ref CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words
|
||||
(32-bit data)
|
||||
|
||||
Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization
|
||||
error must occur if InputBufferFormat is not one of the three values listed
|
||||
above */
|
||||
} CRC_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CRC_Exported_Constants CRC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Default_Polynomial_Value Default CRC generating polynomial
|
||||
* @{
|
||||
*/
|
||||
#define DEFAULT_CRC32_POLY 0x04C11DB7U /*!< X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Default_InitValue Default CRC computation initialization value
|
||||
* @{
|
||||
*/
|
||||
#define DEFAULT_CRC_INITVALUE 0xFFFFFFFFU /*!< Initial CRC default value */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used
|
||||
* @{
|
||||
*/
|
||||
#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U) /*!< Enable default generating polynomial 0x04C11DB7 */
|
||||
#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U) /*!< Disable default generating polynomial 0x04C11DB7 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Default_InitValue_Use Indicates whether or not default init value is used
|
||||
* @{
|
||||
*/
|
||||
#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U) /*!< Enable initial CRC default value */
|
||||
#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U) /*!< Disable initial CRC default value */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the peripheral
|
||||
* @{
|
||||
*/
|
||||
#define CRC_POLYLENGTH_32B 0x00000000U /*!< Resort to a 32-bit long generating polynomial */
|
||||
#define CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0 /*!< Resort to a 16-bit long generating polynomial */
|
||||
#define CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1 /*!< Resort to a 8-bit long generating polynomial */
|
||||
#define CRC_POLYLENGTH_7B CRC_CR_POLYSIZE /*!< Resort to a 7-bit long generating polynomial */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions
|
||||
* @{
|
||||
*/
|
||||
#define HAL_CRC_LENGTH_32B 32U /*!< 32-bit long CRC */
|
||||
#define HAL_CRC_LENGTH_16B 16U /*!< 16-bit long CRC */
|
||||
#define HAL_CRC_LENGTH_8B 8U /*!< 8-bit long CRC */
|
||||
#define HAL_CRC_LENGTH_7B 7U /*!< 7-bit long CRC */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Input_Buffer_Format Input Buffer Format
|
||||
* @{
|
||||
*/
|
||||
/* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but
|
||||
* an error is triggered in HAL_CRC_Init() if InputDataFormat field is set
|
||||
* to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for
|
||||
* the CRC APIs to provide a correct result */
|
||||
#define CRC_INPUTDATA_FORMAT_UNDEFINED 0x00000000U /*!< Undefined input data format */
|
||||
#define CRC_INPUTDATA_FORMAT_BYTES 0x00000001U /*!< Input data in byte format */
|
||||
#define CRC_INPUTDATA_FORMAT_HALFWORDS 0x00000002U /*!< Input data in half-word format */
|
||||
#define CRC_INPUTDATA_FORMAT_WORDS 0x00000003U /*!< Input data in word format */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup CRC_Exported_Macros CRC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset CRC handle state.
|
||||
* @param __HANDLE__ CRC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @brief Reset CRC Data Register.
|
||||
* @param __HANDLE__ CRC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
|
||||
|
||||
/**
|
||||
* @brief Set CRC INIT non-default value
|
||||
* @param __HANDLE__ CRC handle
|
||||
* @param __INIT__ 32-bit initial value
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
|
||||
|
||||
/**
|
||||
* @brief Store data in the Independent Data (ID) register.
|
||||
* @param __HANDLE__ CRC handle
|
||||
* @param __VALUE__ Value to be stored in the ID register
|
||||
* @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
|
||||
|
||||
/**
|
||||
* @brief Return the data stored in the Independent Data (ID) register.
|
||||
* @param __HANDLE__ CRC handle
|
||||
* @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits
|
||||
* @retval Value of the ID register
|
||||
*/
|
||||
#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private macros --------------------------------------------------------*/
|
||||
/** @defgroup CRC_Private_Macros CRC Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
|
||||
((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))
|
||||
|
||||
#define IS_DEFAULT_INIT_VALUE(VALUE) (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
|
||||
((VALUE) == DEFAULT_INIT_VALUE_DISABLE))
|
||||
|
||||
#define IS_CRC_POL_LENGTH(LENGTH) (((LENGTH) == CRC_POLYLENGTH_32B) || \
|
||||
((LENGTH) == CRC_POLYLENGTH_16B) || \
|
||||
((LENGTH) == CRC_POLYLENGTH_8B) || \
|
||||
((LENGTH) == CRC_POLYLENGTH_7B))
|
||||
|
||||
#define IS_CRC_INPUTDATA_FORMAT(FORMAT) (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES) || \
|
||||
((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
|
||||
((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include CRC HAL Extended module */
|
||||
#include "stm32h7rsxx_hal_crc_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup CRC_Exported_Functions CRC Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
|
||||
HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc);
|
||||
void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
|
||||
void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
|
||||
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7RSxx_HAL_CRC_H */
|
||||
|
|
@ -1,150 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7rsxx_hal_crc_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CRC HAL extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7RSxx_HAL_CRC_EX_H
|
||||
#define STM32H7RSxx_HAL_CRC_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7rsxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H7RSxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRCEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CRCEx_Exported_Constants CRC Extended Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRCEx_Input_Data_Inversion Input Data Inversion Modes
|
||||
* @{
|
||||
*/
|
||||
#define CRC_INPUTDATA_INVERSION_NONE 0x00000000U /*!< No input data inversion */
|
||||
#define CRC_INPUTDATA_INVERSION_BYTE CRC_CR_REV_IN_0 /*!< Byte-wise input data inversion */
|
||||
#define CRC_INPUTDATA_INVERSION_HALFWORD CRC_CR_REV_IN_1 /*!< HalfWord-wise input data inversion */
|
||||
#define CRC_INPUTDATA_INVERSION_WORD CRC_CR_REV_IN /*!< Word-wise input data inversion */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes
|
||||
* @{
|
||||
*/
|
||||
#define CRC_OUTPUTDATA_INVERSION_DISABLE 0x00000000U /*!< No output data inversion */
|
||||
#define CRC_OUTPUTDATA_INVERSION_ENABLE CRC_CR_REV_OUT /*!< Bit-wise output data inversion */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup CRCEx_Exported_Macros CRC Extended Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set CRC output reversal
|
||||
* @param __HANDLE__ CRC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
|
||||
|
||||
/**
|
||||
* @brief Unset CRC output reversal
|
||||
* @param __HANDLE__ CRC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
|
||||
|
||||
/**
|
||||
* @brief Set CRC non-default polynomial
|
||||
* @param __HANDLE__ CRC handle
|
||||
* @param __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros --------------------------------------------------------*/
|
||||
/** @defgroup CRCEx_Private_Macros CRC Extended Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_CRC_INPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_INPUTDATA_INVERSION_NONE) || \
|
||||
((MODE) == CRC_INPUTDATA_INVERSION_BYTE) || \
|
||||
((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
|
||||
((MODE) == CRC_INPUTDATA_INVERSION_WORD))
|
||||
|
||||
#define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
|
||||
((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup CRCEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRCEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
|
||||
HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);
|
||||
HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7RSxx_HAL_CRC_EX_H */
|
||||
|
|
@ -1,944 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7rsxx_hal_cryp.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CRYP HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7RSxx_HAL_CRYP_H
|
||||
#define STM32H7RSxx_HAL_CRYP_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(USE_HAL_SAES_ONLY) && (USE_HAL_SAES_ONLY == 1U)
|
||||
#if !defined(USE_HAL_CRYP_ONLY)
|
||||
#define USE_HAL_CRYP_ONLY 0U
|
||||
#elif (USE_HAL_CRYP_ONLY == 1U)
|
||||
#error ' USE_HAL_CRYP_ONLY and USE_HAL_SAES_ONLY cannot be set both to 1U '
|
||||
#endif /* defined (USE_HAL_CRYP_ONLY) */
|
||||
#endif /* defined (USE_HAL_SAES_ONLY) */
|
||||
|
||||
#if defined(USE_HAL_CRYP_ONLY) && (USE_HAL_CRYP_ONLY == 1U)
|
||||
#if !defined(USE_HAL_SAES_ONLY)
|
||||
#define USE_HAL_SAES_ONLY 0U
|
||||
#elif (USE_HAL_SAES_ONLY == 1U)
|
||||
#error ' USE_HAL_CRYP_ONLY and USE_HAL_SAES_ONLY cannot be set both to 1U '
|
||||
#endif /* defined (USE_HAL_SAES_ONLY) */
|
||||
#endif /* defined (USE_HAL_CRYP_ONLY) */
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7rsxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H7RSxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
#if defined (CRYP)
|
||||
/** @addtogroup CRYP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Exported_Types CRYP Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief CRYP Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
|
||||
This parameter can be a value of @ref CRYP_Data_Type */
|
||||
uint32_t KeySize; /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1.
|
||||
This parameter can be a value of @ref CRYP_Key_Size */
|
||||
uint32_t *pKey; /*!< The key used for encryption/decryption */
|
||||
uint32_t *pInitVect; /*!< The initialization vector used also as initialization
|
||||
counter in CTR mode */
|
||||
uint32_t Algorithm; /*!< AES Algorithm ECB/CBC/CTR/GCM or CCM
|
||||
This parameter can be a value of @ref CRYP_CR_ALGOMODE */
|
||||
uint32_t *Header; /*!< used only in AES GCM and CCM Algorithm for authentication,
|
||||
GCM : also known as Additional Authentication Data
|
||||
CCM : named B1 composed of the associated data length and Associated Data. */
|
||||
uint32_t HeaderSize; /*!< The size of header buffer in word */
|
||||
uint32_t *B0; /*!< B0 is first authentication block used only in AES CCM mode */
|
||||
uint32_t DataWidthUnit; /*!< Data With Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/
|
||||
uint32_t HeaderWidthUnit; /*!< Header Width Unit, this parameter can be value
|
||||
of @ref CRYP_Header_Width_Unit */
|
||||
uint32_t KeyIVConfigSkip; /*!< CRYP peripheral Key and IV configuration skip,
|
||||
to configure Key and Initialization
|
||||
Vector only once and to skip configuration for consecutive processing.
|
||||
This parameter can be a value of @ref CRYP_Configuration_Skip */
|
||||
uint32_t KeyMode; /*!< Key mode selection, this parameter can be a value of @ref CRYP_Key_Mode */
|
||||
uint32_t KeySelect; /*!< Only for SAES : Key selection, this parameter can be a value
|
||||
of @ref CRYP_Key_Select */
|
||||
|
||||
} CRYP_ConfigTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief CRYP State Structure definition
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
HAL_CRYP_STATE_RESET = 0x00U, /*!< CRYP not yet initialized or disabled */
|
||||
HAL_CRYP_STATE_READY = 0x01U, /*!< CRYP initialized and ready for use */
|
||||
HAL_CRYP_STATE_BUSY = 0x02U, /*!< CRYP BUSY, internal processing is ongoing */
|
||||
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
|
||||
HAL_CRYP_STATE_SUSPENDED = 0x03U, /*!< CRYP suspended */
|
||||
#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
|
||||
} HAL_CRYP_STATETypeDef;
|
||||
|
||||
|
||||
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
|
||||
/**
|
||||
* @brief HAL CRYP mode suspend definitions
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
HAL_CRYP_SUSPEND_NONE = 0x00U, /*!< CRYP processing suspension not requested */
|
||||
HAL_CRYP_SUSPEND = 0x01U /*!< CRYP processing suspension requested */
|
||||
} HAL_SuspendTypeDef;
|
||||
#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
|
||||
|
||||
/**
|
||||
* @brief CRYP handle Structure definition
|
||||
*/
|
||||
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
|
||||
typedef struct __CRYP_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
|
||||
{
|
||||
void *Instance; /*!< CRYP or SAES registers base address */
|
||||
|
||||
CRYP_ConfigTypeDef Init; /*!< CRYP required parameters */
|
||||
|
||||
uint32_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...)
|
||||
buffer */
|
||||
|
||||
uint32_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...)
|
||||
buffer */
|
||||
|
||||
__IO uint16_t CrypHeaderCount; /*!< Counter of header data */
|
||||
|
||||
__IO uint16_t CrypInCount; /*!< Counter of input data */
|
||||
|
||||
__IO uint16_t CrypOutCount; /*!< Counter of output data */
|
||||
|
||||
uint16_t Size; /*!< length of input data in word or in byte,
|
||||
according to DataWidthUnit */
|
||||
|
||||
uint32_t Phase; /*!< CRYP peripheral phase */
|
||||
|
||||
DMA_HandleTypeDef *hdmain; /*!< CRYP In DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmaout; /*!< CRYP Out DMA handle parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< CRYP locking object */
|
||||
|
||||
__IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< CRYP peripheral error code */
|
||||
|
||||
uint32_t Version; /*!< CRYP1 IP version*/
|
||||
|
||||
uint32_t KeyIVConfig; /*!< CRYP peripheral Key and IV configuration flag, used when
|
||||
configuration can be skipped */
|
||||
|
||||
uint32_t SizesSum; /*!< Sum of successive payloads lengths (in bytes), stored
|
||||
for a single signature computation after several
|
||||
messages processing */
|
||||
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
|
||||
void (*InCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Input FIFO transfer completed callback */
|
||||
void (*OutCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Output FIFO transfer completed callback */
|
||||
void (*ErrorCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Error callback */
|
||||
|
||||
void (* MspInitCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Msp DeInit callback */
|
||||
|
||||
#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
|
||||
|
||||
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
|
||||
|
||||
__IO HAL_SuspendTypeDef SuspendRequest; /*!< CRYP peripheral suspension request flag */
|
||||
|
||||
CRYP_ConfigTypeDef Init_saved; /*!< copy of CRYP required parameters when processing
|
||||
is suspended */
|
||||
|
||||
uint32_t *pCrypInBuffPtr_saved; /*!< copy of CRYP input pointer when processing
|
||||
is suspended */
|
||||
|
||||
uint32_t *pCrypOutBuffPtr_saved; /*!< copy of CRYP output pointer when processing
|
||||
is suspended */
|
||||
|
||||
uint32_t CrypInCount_saved; /*!< copy of CRYP input data counter when processing
|
||||
is suspended */
|
||||
|
||||
uint32_t CrypOutCount_saved; /*!< copy of CRYP output data counter when processing
|
||||
is suspended */
|
||||
|
||||
uint32_t Phase_saved; /*!< copy of CRYP authentication phase when processing
|
||||
is suspended */
|
||||
|
||||
__IO HAL_CRYP_STATETypeDef State_saved; /*!< copy of CRYP peripheral state when processing
|
||||
is suspended */
|
||||
|
||||
uint32_t IV_saved[4]; /*!< copy of Initialisation Vector registers */
|
||||
|
||||
uint32_t SUSPxR_saved[16]; /*!< copy of suspension registers */
|
||||
|
||||
uint32_t CR_saved; /*!< copy of CRYP control register when processing
|
||||
is suspended*/
|
||||
|
||||
uint32_t Key_saved[8]; /*!< copy of key registers */
|
||||
|
||||
uint16_t Size_saved; /*!< copy of input buffer size */
|
||||
|
||||
uint16_t CrypHeaderCount_saved; /*!< copy of CRYP header data counter when processing
|
||||
is suspended */
|
||||
|
||||
uint32_t SizesSum_saved; /*!< copy of SizesSum when processing is suspended */
|
||||
|
||||
uint32_t ResumingFlag; /*!< resumption flag to bypass steps already carried out */
|
||||
|
||||
uint32_t SuspendedProcessing; /*< Report whether interruption or DMA-mode processing
|
||||
was suspended */
|
||||
#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
|
||||
|
||||
} CRYP_HandleTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
|
||||
/** @defgroup HAL_CRYP_Callback_ID_enumeration_definition HAL CRYP Callback ID enumeration definition
|
||||
* @brief HAL CRYP Callback ID enumeration definition
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CRYP_INPUT_COMPLETE_CB_ID = 0x01U, /*!< CRYP Input FIFO transfer completed callback ID */
|
||||
HAL_CRYP_OUTPUT_COMPLETE_CB_ID = 0x02U, /*!< CRYP Output FIFO transfer completed callback ID */
|
||||
HAL_CRYP_ERROR_CB_ID = 0x03U, /*!< CRYP Error callback ID */
|
||||
HAL_CRYP_MSPINIT_CB_ID = 0x04U, /*!< CRYP MspInit callback ID */
|
||||
HAL_CRYP_MSPDEINIT_CB_ID = 0x05U /*!< CRYP MspDeInit callback ID */
|
||||
|
||||
} HAL_CRYP_CallbackIDTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_CRYP_Callback_pointer_definition HAL CRYP Callback pointer definition
|
||||
* @brief HAL CRYP Callback pointer definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< pointer to a common CRYP callback function */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Exported_Constants CRYP Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Error_Definition CRYP Error Definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_CRYP_ERROR_NONE 0x00000000U /*!< No error */
|
||||
#define HAL_CRYP_ERROR_WRITE 0x00000001U /*!< Write error */
|
||||
#define HAL_CRYP_ERROR_READ 0x00000002U /*!< Read error */
|
||||
#define HAL_CRYP_ERROR_DMA 0x00000004U /*!< DMA error */
|
||||
#define HAL_CRYP_ERROR_BUSY 0x00000008U /*!< Busy flag error */
|
||||
#define HAL_CRYP_ERROR_TIMEOUT 0x00000010U /*!< Timeout error */
|
||||
#define HAL_CRYP_ERROR_NOT_SUPPORTED 0x00000020U /*!< Not supported mode */
|
||||
#define HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE 0x00000040U /*!< Sequence are not respected only for GCM or CCM */
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
|
||||
#define HAL_CRYP_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
|
||||
#define HAL_CRYP_ERROR_KEY 0x00000100U /*!< Key error */
|
||||
#define HAL_CRYP_ERROR_RNG 0x00000200U /*!< RNG error */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CRYP_Data_Width_Unit CRYP Data Width Unit
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_DATAWIDTHUNIT_WORD 0x00000000U /*!< By default, size unit is word */
|
||||
#define CRYP_DATAWIDTHUNIT_BYTE 0x00000001U /*!< By default, size unit is byte */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Header_Width_Unit CRYP Header Width Unit
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_HEADERWIDTHUNIT_WORD 0x00000000U /*!< By default, size unit is word */
|
||||
#define CRYP_HEADERWIDTHUNIT_BYTE 0x00000001U /*!< By default, size unit is byte */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
|
||||
/** @defgroup SAES_CR_CHMOD SAES CHMOD Selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SAES_CR_CHMOD_AES_ECB ((uint32_t)0x00000000)
|
||||
#define SAES_CR_CHMOD_AES_CBC (SAES_CR_CHMOD_0)
|
||||
#define SAES_CR_CHMOD_AES_CTR (SAES_CR_CHMOD_1)
|
||||
#define SAES_CR_CHMOD_AES_GCM (SAES_CR_CHMOD_0 | SAES_CR_CHMOD_1)
|
||||
#define SAES_CR_CHMOD_AES_CCM (SAES_CR_CHMOD_2)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* USE_HAL_SAES_ONLY */
|
||||
|
||||
/** @defgroup CRYP_CR_ALGOMODE CRYP Algorithm Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_AES_ECB (CRYP_CR_ALGOMODE_2)
|
||||
#define CRYP_AES_CBC (CRYP_CR_ALGOMODE_0 | CRYP_CR_ALGOMODE_2)
|
||||
#define CRYP_AES_CTR (CRYP_CR_ALGOMODE_1 | CRYP_CR_ALGOMODE_2)
|
||||
#define CRYP_AES_KEY (CRYP_CR_ALGOMODE_0 | CRYP_CR_ALGOMODE_1 | CRYP_CR_ALGOMODE_2)
|
||||
#define CRYP_AES_GCM (CRYP_CR_ALGOMODE_3)
|
||||
#define CRYP_AES_CCM (CRYP_CR_ALGOMODE_0 | CRYP_CR_ALGOMODE_3)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Key_Size CRYP Key Size
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_KEYSIZE_128B 0x00000000U
|
||||
#define CRYP_KEYSIZE_192B CRYP_CR_KEYSIZE_0
|
||||
#define CRYP_KEYSIZE_256B CRYP_CR_KEYSIZE_1
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Data_Type CRYP Data Type
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_DATATYPE_32B 0x00000000U
|
||||
#define CRYP_DATATYPE_16B CRYP_CR_DATATYPE_0
|
||||
#define CRYP_DATATYPE_8B CRYP_CR_DATATYPE_1
|
||||
#define CRYP_DATATYPE_1B CRYP_CR_DATATYPE
|
||||
|
||||
#define CRYP_NO_SWAP CRYP_DATATYPE_32B /*!< 32-bit data type (no swapping) */
|
||||
#define CRYP_HALFWORD_SWAP CRYP_DATATYPE_16B /*!< 16-bit data type (half-word swapping) */
|
||||
#define CRYP_BYTE_SWAP CRYP_DATATYPE_8B /*!< 8-bit data type (byte swapping) */
|
||||
#define CRYP_BIT_SWAP CRYP_DATATYPE_1B /*!< 1-bit data type (bit swapping) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Interrupt CRYP and SAES peripherals interrupts
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_IT_INI CRYP_IMSCR_INIM /*!< CRYP peripheral input FIFO Interrupt */
|
||||
#define CRYP_IT_OUTI CRYP_IMSCR_OUTIM /*!< CRYP peripheral output FIFO Interrupt */
|
||||
|
||||
#define CRYP_IT_CCFIE SAES_IER_CCFIE /*!< SAES peripheral computation Complete interrupt enable */
|
||||
#define CRYP_IT_RWEIE SAES_IER_RWEIE /*!< SAES peripheral read or write Error interrupt enable */
|
||||
#define CRYP_IT_KEIE SAES_IER_KEIE /*!< SAES peripheral key error interrupt enable */
|
||||
#define CRYP_IT_RNGEIE SAES_IER_RNGEIE /*!< SAES peripheral RNG error interrupt enable */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Flags CRYP & SAES Flags
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Flags in the SR register */
|
||||
#define CRYP_FLAG_IFEM CRYP_SR_IFEM /*!< CRYP peripheral Input FIFO is empty */
|
||||
#define CRYP_FLAG_IFNF CRYP_SR_IFNF /*!< CRYP peripheral Input FIFO is not Full */
|
||||
#define CRYP_FLAG_OFNE CRYP_SR_OFNE /*!< CRYP peripheral Output FIFO is not empty */
|
||||
#define CRYP_FLAG_OFFU CRYP_SR_OFFU /*!< CRYP peripheral Output FIFO is Full */
|
||||
#define CRYP_FLAG_KERF CRYP_SR_KERF /*!< CRYP peripheral Key error flag */
|
||||
/* Flags in the RISR register */
|
||||
#define CRYP_FLAG_OUTRIS 0x01000002U /*!< Output FIFO service raw interrupt status */
|
||||
#define CRYP_FLAG_INRIS 0x01000001U /*!< Input FIFO service raw interrupt status*/
|
||||
|
||||
#define CRYP_FLAG_BUSY CRYP_SR_BUSY /*!< The CRYP peripheral is currently processing a block of data
|
||||
or a key preparation (for AES decryption). */
|
||||
|
||||
|
||||
#define CRYP_FLAG_KEYVALID CRYP_SR_KEYVALID /*!< CRYP or SAES peripheral Key valid flag */
|
||||
|
||||
#define SAES_FLAG_BUSY SAES_SR_BUSY /*!< The SAES peripheral is currently processing a block of data
|
||||
or a key preparation (for AES decryption). */
|
||||
|
||||
#define CRYP_FLAG_WRERR (SAES_SR_WRERR | 0x80000000U) /*!< SAES peripheral Write Error flag */
|
||||
#define CRYP_FLAG_RDERR (SAES_SR_RDERR | 0x80000000U) /*!< SAES peripheral Read error flag */
|
||||
#define CRYP_FLAG_CCF SAES_SR_CCF /*!< SAES peripheral Computation completed flag
|
||||
as AES_ISR_CCF */
|
||||
#define CRYP_FLAG_KEIF SAES_ISR_KEIF /*!< SAES peripheral Key error interrupt flag */
|
||||
#define CRYP_FLAG_RWEIF SAES_ISR_RWEIF /*!< SAES peripheral Read or Write error Interrupt flag */
|
||||
#define CRYP_FLAG_RNGEIF SAES_ISR_RNGEIF /*!< SAES peripheral RNG error Interrupt flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_CLEAR_Flags SAES peripheral Clear Flags
|
||||
* @{
|
||||
*/
|
||||
#define CRYP_CLEAR_CCF SAES_ICR_CCF /*!< SAES peripheral clear Computation Complete Flag */
|
||||
#define CRYP_CLEAR_RWEIF SAES_ICR_RWEIF /*!< SAES peripheral clear Error Flag : RWEIF in SAES_ISR and
|
||||
both RDERR and WRERR flags in SAES_SR */
|
||||
#define CRYP_CLEAR_KEIF SAES_ICR_KEIF /*!< SAES peripheral clear Key Error Flag: KEIF in SAES_ISR */
|
||||
#define CRYP_CLEAR_RNGEIF SAES_ICR_RNGEIF /*!< SAES peripheral clear RNG error Flag */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CRYP_Configuration_Skip CRYP Key and IV Configuration Skip Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_KEYIVCONFIG_ALWAYS 0x00000000U /*!< Peripheral Key and IV configuration
|
||||
to do systematically */
|
||||
#define CRYP_KEYIVCONFIG_ONCE 0x00000001U /*!< Peripheral Key and IV configuration
|
||||
to do only once */
|
||||
#define CRYP_KEYNOCONFIG 0x00000002U /*!< Peripheral Key configuration to not do */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Key_Mode CRYP or SAES Key Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_KEYMODE_NORMAL 0x00000000U /*!< Normal key usage, Key registers are freely usable */
|
||||
#define CRYP_KEYMODE_WRAPPED SAES_CR_KMOD_0 /*!< Only for SAES, Wrapped key: to encrypt
|
||||
or decrypt AES keys */
|
||||
#define CRYP_KEYMODE_SHARED SAES_CR_KMOD_1 /*!< Key shared by SAES peripheral */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Key_Select SAES Key Select
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_KEYSEL_NORMAL 0x00000000U /*!< Normal key, key registers SAES_KEYx or CRYP_KEYx */
|
||||
#define CRYP_KEYSEL_HW SAES_CR_KEYSEL_0 /*!< Only for SAES, Hardware key : derived hardware
|
||||
unique key (DHUK 256-bit) */
|
||||
#define CRYP_KEYSEL_SW SAES_CR_KEYSEL_1 /*!< Only for SAES, Software key : boot hardware
|
||||
key BHK (256-bit) */
|
||||
#define CRYP_KEYSEL_HSW SAES_CR_KEYSEL_2 /*!< Only for SAES, DHUK XOR BHK Hardware unique
|
||||
key XOR software key */
|
||||
#define CRYP_KEYSEL_AHK (SAES_CR_KEYSEL_1|SAES_CR_KEYSEL_0) /*!< Only for SAES, Software key :
|
||||
application hardware key AHK (128- or 256-bit) */
|
||||
#define CRYP_KEYSEL_DUK_AHK (SAES_CR_KEYSEL_2|SAES_CR_KEYSEL_0) /*!< Only for SAES, DHUK XOR AHK */
|
||||
#define CRYP_KEYSEL_TEST_KEY (SAES_CR_KEYSEL_2|SAES_CR_KEYSEL_1|SAES_CR_KEYSEL_0) /*!< Test mode key (256-bit
|
||||
hardware constant key 0xA5A5...A5A5) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Key_Shared SAES Key Shared with Peripheral
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_KEYSHARED_CRYP 0x00000000U /*!< Only for SAES, key is shared with CRYP peripheral */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Mode SAES processing mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_MODE_ENCRYPT 0x00000000U /*!< SAES peripheral encryption mode */
|
||||
#define CRYP_MODE_KEY_DERIVATION SAES_CR_MODE_0 /*!< SAES peripheral key derivation */
|
||||
#define CRYP_MODE_DECRYPT SAES_CR_MODE_1 /*!< SAES peripheral decryption mode */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* USE_HAL_SAES_ONLY */
|
||||
|
||||
/** @defgroup CRYP_Mode SAES processing mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U /*!< CRYP peripheral encryption mode */
|
||||
#define CRYP_OPERATINGMODE_DECRYPT CRYP_CR_ALGODIR /*!< CRYP peripheral decryption mode */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Exported_Macros CRYP Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Inform about which IP is the current INSTANCE: CRYP or SAES.
|
||||
* @param INSTANCE: specifies the HW instance.
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_CRYP_INSTANCE(INSTANCE) ((INSTANCE) == CRYP)
|
||||
#define IS_SAES_INSTANCE(INSTANCE) ((INSTANCE) == SAES)
|
||||
|
||||
/** @brief Reset CRYP handle state
|
||||
* @param __HANDLE__ specifies the CRYP handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
|
||||
#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) do{\
|
||||
(__HANDLE__)->State = HAL_CRYP_STATE_RESET;\
|
||||
(__HANDLE__)->MspInitCallback = NULL;\
|
||||
(__HANDLE__)->MspDeInitCallback = NULL;\
|
||||
}while(0)
|
||||
#else
|
||||
#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_CRYP_STATE_RESET)
|
||||
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @brief Enable/Disable the CRYP or SAES peripheral.
|
||||
* @param __HANDLE__: specifies the CRYP handle.
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
#define __HAL_CRYP_ENABLE(__HANDLE__) ((IS_CRYP_INSTANCE((__HANDLE__)->Instance)) ? \
|
||||
(((CRYP_TypeDef *)((__HANDLE__)->Instance))->CR |= CRYP_CR_CRYPEN) :\
|
||||
(((SAES_TypeDef *)((__HANDLE__)->Instance))->CR |= SAES_CR_EN))
|
||||
|
||||
#define __HAL_CRYP_DISABLE(__HANDLE__) ((IS_CRYP_INSTANCE((__HANDLE__)->Instance)) ? \
|
||||
(((CRYP_TypeDef *)((__HANDLE__)->Instance))->CR &= ~CRYP_CR_CRYPEN) :\
|
||||
(((SAES_TypeDef *)((__HANDLE__)->Instance))->CR &= ~SAES_CR_EN))
|
||||
|
||||
/** @brief Check whether the specified CRYP or SAES peripheral status flag is set or not.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data
|
||||
* or a key preparation (for AES decryption)
|
||||
* @arg @ref CRYP_FLAG_KEYVALID Key valid flag
|
||||
* @arg @ref CRYP_FLAG_KEIF Key error flag
|
||||
* @arg CRYP_FLAG_IFEM: Input FIFO is empty (CRYP peripheral only)
|
||||
* @arg CRYP_FLAG_IFNF: Input FIFO is not full (CRYP peripheral only)
|
||||
* @arg CRYP_FLAG_INRIS: Input FIFO service raw interrupt is pending (CRYP peripheral only)
|
||||
* @arg CRYP_FLAG_OFNE: Output FIFO is not empty (CRYP peripheral only)
|
||||
* @arg CRYP_FLAG_OFFU: Output FIFO is full (CRYP peripheral only)
|
||||
* @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending (CRYP peripheral only)
|
||||
* @arg @ref CRYP_FLAG_WRERR Write Error flag (SAES peripheral only)
|
||||
* @arg @ref CRYP_FLAG_RDERR Read Error flag (SAES peripheral only)
|
||||
* @arg @ref CRYP_FLAG_CCF Computation Complete flag (SAES peripheral only)
|
||||
* @arg @ref CRYP_FLAG_RWEIF Read/write Error flag (SAES peripheral only)
|
||||
* @arg @ref CRYP_FLAG_RNGEIF RNG Error flag (SAES peripheral only)
|
||||
* @retval The state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define CRYP_FLAG_MASK 0x0000001FU
|
||||
|
||||
#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((IS_CRYP_INSTANCE((__HANDLE__)->Instance)) ?\
|
||||
((__FLAG__) == CRYP_FLAG_KEYVALID )?((((((CRYP_TypeDef *) \
|
||||
((__HANDLE__)->Instance))))->SR \
|
||||
& (CRYP_FLAG_KEYVALID)) == (CRYP_FLAG_KEYVALID)) : \
|
||||
((__FLAG__) == CRYP_FLAG_BUSY )?((((((CRYP_TypeDef *) \
|
||||
((__HANDLE__)->Instance))))->SR \
|
||||
& (CRYP_FLAG_BUSY)) == (CRYP_FLAG_BUSY)) : \
|
||||
((__FLAG__) == CRYP_FLAG_KEIF )?((((((CRYP_TypeDef *) \
|
||||
((__HANDLE__)->Instance))))->SR \
|
||||
& (CRYP_FLAG_KERF)) == (CRYP_FLAG_KERF)) : \
|
||||
((((uint8_t)((__FLAG__) >> 24)) == 0x01U)?(((((CRYP_TypeDef *) \
|
||||
((__HANDLE__)->Instance))->RISR) & ((__FLAG__) & \
|
||||
CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
|
||||
(((((CRYP_TypeDef *)((__HANDLE__)->Instance))->RISR) & ((__FLAG__)\
|
||||
& CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK))) :\
|
||||
(\
|
||||
((__FLAG__) == CRYP_FLAG_KEYVALID )?((((SAES_TypeDef *)\
|
||||
(((SAES_TypeDef *)((__HANDLE__)->Instance))))->SR \
|
||||
& (CRYP_FLAG_KEYVALID)) == (CRYP_FLAG_KEYVALID)) : \
|
||||
((__FLAG__) == CRYP_FLAG_BUSY )?((((SAES_TypeDef *) \
|
||||
((__HANDLE__)->Instance))->SR \
|
||||
& (CRYP_FLAG_BUSY)) == (CRYP_FLAG_BUSY)) : \
|
||||
((__FLAG__) == CRYP_FLAG_WRERR )?((((SAES_TypeDef *) \
|
||||
((__HANDLE__)->Instance))->SR \
|
||||
& (CRYP_FLAG_WRERR & 0x7FFFFFFFU)) == \
|
||||
(CRYP_FLAG_WRERR & 0x7FFFFFFFU)) : \
|
||||
((__FLAG__) == CRYP_FLAG_RDERR )?((((SAES_TypeDef *) \
|
||||
((__HANDLE__)->Instance))->SR \
|
||||
& (CRYP_FLAG_RDERR & 0x7FFFFFFFU)) == \
|
||||
(CRYP_FLAG_RDERR & 0x7FFFFFFFU)) : \
|
||||
((__FLAG__) == CRYP_FLAG_RNGEIF )?((((SAES_TypeDef *) \
|
||||
((__HANDLE__)->Instance))->ISR \
|
||||
& (CRYP_FLAG_RNGEIF)) == (CRYP_FLAG_RNGEIF)) : \
|
||||
((__FLAG__) == CRYP_FLAG_KEIF )?((((SAES_TypeDef *) \
|
||||
((__HANDLE__)->Instance))->ISR \
|
||||
& (CRYP_FLAG_KEIF)) == (CRYP_FLAG_KEIF)) : \
|
||||
((__FLAG__) == CRYP_FLAG_RWEIF )?((((SAES_TypeDef *) \
|
||||
((__HANDLE__)->Instance))->ISR \
|
||||
& (CRYP_FLAG_RWEIF)) == (CRYP_FLAG_RWEIF)) : \
|
||||
((((SAES_TypeDef *)((__HANDLE__)->Instance))->ISR & \
|
||||
(CRYP_FLAG_CCF)) == (CRYP_FLAG_CCF))))
|
||||
|
||||
#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
|
||||
/** @brief Clear the SAES peripheral pending status flag.
|
||||
* @param __HANDLE__ specifies the SAES handle.
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref CRYP_CLEAR_RWEIF Read (RDERR), Write (WRERR) or Read/write (RWEIF) Error Flag Clear
|
||||
* @arg @ref CRYP_CLEAR_CCF Computation Complete Flag (CCF) Clear
|
||||
* @arg @ref CRYP_CLEAR_KEIF Key error interrupt flag clear
|
||||
* @arg @ref CRYP_CLEAR_RNGEIF RNG error interrupt flag clear
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRYP_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG(((SAES_TypeDef *)((__HANDLE__)->Instance))->ICR,\
|
||||
(__FLAG__))
|
||||
#endif /* USE_HAL_SAES_ONLY */
|
||||
|
||||
#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
|
||||
/** @brief Check whether the specified CRYP peripheral interrupt is set or not.
|
||||
* @param __HANDLE__: specifies the CRYP handle.
|
||||
* @param __INTERRUPT__: specifies the interrupt to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CRYP_IT_INI: Input FIFO service masked interrupt status
|
||||
* @arg CRYP_IT_OUTI: Output FIFO service masked interrupt status
|
||||
* @retval The state of __INTERRUPT__ (TRUE or FALSE).
|
||||
*/
|
||||
|
||||
#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) ((((CRYP_TypeDef *)((__HANDLE__)->Instance))->MISR\
|
||||
& (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
#endif /* USE_HAL_CRYP_ONLY */
|
||||
|
||||
/**
|
||||
* @brief Enable the CRYP or SAES peripheral interrupt.
|
||||
* @param __HANDLE__: specifies the CRYP handle.
|
||||
* @param __INTERRUPT__: Interrupt.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref CRYP_IT_INI Input FIFO service interrupt mask (CRYP peripheral only)
|
||||
* @arg @ref CRYP_IT_OUTI Output FIFO service interrupt mask (CRYP peripheral only)
|
||||
* @arg @ref CRYP_IT_RWEIE Error interrupt (used for RDERR and WRERR) (SAES peripheral only)
|
||||
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt (SAES peripheral only)
|
||||
* @arg @ref CRYP_IT_KEIE Key error interrupt (SAES peripheral only)
|
||||
* @arg @ref CRYP_IT_RNGEIE RNG interrupt (SAES peripheral only)
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((IS_CRYP_INSTANCE((__HANDLE__)->Instance)) ?\
|
||||
((((CRYP_TypeDef *)((__HANDLE__)->Instance))->IMSCR) |= \
|
||||
(__INTERRUPT__)) : ((((SAES_TypeDef *) \
|
||||
((__HANDLE__)->Instance))->IER) |= (__INTERRUPT__)))
|
||||
|
||||
/**
|
||||
* @brief Disable the CRYP or SAES peripheral interrupt.
|
||||
* @param __HANDLE__: specifies the CRYP handle.
|
||||
* @param __INTERRUPT__: Interrupt.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref CRYP_IT_INI Input FIFO service interrupt mask (CRYP peripheral only)
|
||||
* @arg @ref CRYP_IT_OUTI Output FIFO service interrupt mask (CRYP peripheral only)
|
||||
* @arg @ref CRYP_IT_RWEIE Error interrupt (used for RDERR and WRERR) (SAES peripheral only)
|
||||
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt (SAES peripheral only)
|
||||
* @arg @ref CRYP_IT_KEIE Key error interrupt (SAES peripheral only)
|
||||
* @arg @ref CRYP_IT_RNGEIE RNG interrupt (SAES peripheral only)
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((IS_CRYP_INSTANCE((__HANDLE__)->Instance)) ?\
|
||||
((((CRYP_TypeDef *)((__HANDLE__)->Instance))->IMSCR) &= \
|
||||
~(__INTERRUPT__)) : ((((SAES_TypeDef *) \
|
||||
((__HANDLE__)->Instance))->IER) &= ~(__INTERRUPT__)))
|
||||
|
||||
#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
|
||||
/** @brief Check whether the specified SAES peripheral interrupt source is enabled or not.
|
||||
* @param __HANDLE__ specifies the CRYP handle.
|
||||
* @param __INTERRUPT__ interrupt source to check
|
||||
* This parameter can be one of the following values for TinyAES:
|
||||
* @arg @ref CRYP_IT_RWEIE Error interrupt (used for RDERR and WRERR)
|
||||
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
|
||||
* @arg @ref CRYP_IT_KEIE Key error interrupt
|
||||
* @arg @ref CRYP_IT_RNGEIE RNG error interrupt
|
||||
* @retval State of interruption (TRUE or FALSE).
|
||||
*/
|
||||
|
||||
#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((SAES_TypeDef *)((__HANDLE__)->Instance))->IER\
|
||||
& (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
#endif /* USE_HAL_SAES_ONLY */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include CRYP HAL Extended module */
|
||||
#include "stm32h7rsxx_hal_cryp_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Exported_Functions CRYP Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRYP_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
|
||||
HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
|
||||
void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
|
||||
void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
|
||||
HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf);
|
||||
HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf);
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
|
||||
HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID,
|
||||
pCRYP_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
|
||||
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
|
||||
void HAL_CRYP_ProcessSuspend(CRYP_HandleTypeDef *hcryp);
|
||||
HAL_StatusTypeDef HAL_CRYP_DMAProcessSuspend(CRYP_HandleTypeDef *hcryp);
|
||||
HAL_StatusTypeDef HAL_CRYP_Suspend(CRYP_HandleTypeDef *hcryp);
|
||||
HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp);
|
||||
#endif /* defined (USE_HAL_CRYP_SUSPEND_RESUME) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CRYP_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* encryption/decryption ***********************************/
|
||||
HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
|
||||
HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
|
||||
HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
|
||||
HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup CRYP_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Interrupt Handler functions **********************************************/
|
||||
void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
|
||||
HAL_CRYP_STATETypeDef HAL_CRYP_GetState(const CRYP_HandleTypeDef *hcryp);
|
||||
void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
|
||||
void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
|
||||
void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
|
||||
uint32_t HAL_CRYP_GetError(const CRYP_HandleTypeDef *hcryp);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros --------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Private_Macros CRYP Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_IS_CRYP_Definitions CRYP Private macros to check input parameters
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_AES_ECB) || \
|
||||
((ALGORITHM) == CRYP_AES_CBC) || \
|
||||
((ALGORITHM) == CRYP_AES_CTR) || \
|
||||
((ALGORITHM) == CRYP_AES_GCM) || \
|
||||
((ALGORITHM) == CRYP_AES_CCM))
|
||||
|
||||
#define IS_CRYP_KEYSIZE(KEYSIZE) (((KEYSIZE) == CRYP_KEYSIZE_128B) || \
|
||||
((KEYSIZE) == CRYP_KEYSIZE_192B) || \
|
||||
((KEYSIZE) == CRYP_KEYSIZE_256B))
|
||||
|
||||
#define IS_CRYP_DATATYPE(DATATYPE) (((DATATYPE) == CRYP_DATATYPE_32B) || \
|
||||
((DATATYPE) == CRYP_DATATYPE_16B) || \
|
||||
((DATATYPE) == CRYP_DATATYPE_8B) || \
|
||||
((DATATYPE) == CRYP_DATATYPE_1B))
|
||||
|
||||
#define IS_CRYP_INIT(CONFIG) (((CONFIG) == CRYP_KEYIVCONFIG_ALWAYS) || \
|
||||
((CONFIG) == CRYP_KEYIVCONFIG_ONCE) || \
|
||||
((CONFIG) == CRYP_KEYNOCONFIG))
|
||||
|
||||
#define IS_CRYP_KEYIVCONFIG(CONFIG) (((KEYSIZE) == CRYP_KEYSIZE_128B) || \
|
||||
((KEYSIZE) == CRYP_KEYSIZE_192B) || \
|
||||
((KEYSIZE) == CRYP_KEYSIZE_256B))
|
||||
|
||||
#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
|
||||
#define IS_CRYP_KEYMODE(MODE) (((MODE) == CRYP_KEYMODE_NORMAL) || \
|
||||
((MODE) == CRYP_KEYMODE_SHARED))
|
||||
|
||||
#define IS_SAES_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_AES_ECB) || \
|
||||
((ALGORITHM) == CRYP_AES_CBC) || \
|
||||
((ALGORITHM) == CRYP_AES_CTR) || \
|
||||
((ALGORITHM) == CRYP_AES_GCM) || \
|
||||
((ALGORITHM) == CRYP_AES_CCM))
|
||||
|
||||
#define IS_SAES_KEYSIZE(KEYSIZE) (((KEYSIZE) == CRYP_KEYSIZE_128B) || \
|
||||
((KEYSIZE) == CRYP_KEYSIZE_256B))
|
||||
|
||||
#define IS_SAES_DATATYPE(DATATYPE) (((DATATYPE) == SAES_DATATYPE_32B) || \
|
||||
((DATATYPE) == SAES_DATATYPE_16B) || \
|
||||
((DATATYPE) == SAES_DATATYPE_8B) || \
|
||||
((DATATYPE) == SAES_DATATYPE_1B))
|
||||
|
||||
#define IS_SAES_KEYMODE(MODE) (((MODE) == CRYP_KEYMODE_NORMAL) || \
|
||||
((MODE) == CRYP_KEYMODE_WRAPPED) || \
|
||||
((MODE) == CRYP_KEYMODE_SHARED))
|
||||
|
||||
#define IS_SAES_KEYPROT(PROTECTION) (((PROTECTION) == CRYP_KEYPROT_ENABLE) || \
|
||||
((PROTECTION) == CRYP_KEYPROT_DISABLE))
|
||||
|
||||
#define IS_SAES_KEYSEL(SELECTION) (((SELECTION) == CRYP_KEYSEL_NORMAL) || \
|
||||
((SELECTION) == CRYP_KEYSEL_HW) || \
|
||||
((SELECTION) == CRYP_KEYSEL_SW) || \
|
||||
((SELECTION) == CRYP_KEYSEL_HSW) || \
|
||||
((SELECTION) == CRYP_KEYSEL_AHK) || \
|
||||
((SELECTION) == CRYP_KEYSEL_DUK_AHK) || \
|
||||
((SELECTION) == CRYP_KEYSEL_TEST_KEY))
|
||||
|
||||
#define IS_SAES_KEYSHARED(PERIPHERAL) ((PERIPHERAL) == CRYP_KEYSHARED_CRYP)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* USE_HAL_SAES_ONLY */
|
||||
|
||||
/** @defgroup SAES_CONV_Definitions SAES Private macros to convert input parameters from CRYP peripheral to
|
||||
SAES peripheral format
|
||||
* @{
|
||||
*/
|
||||
#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
|
||||
#define SAES_CONV_DATATYPE(__DATATYPE__) ((__DATATYPE__) >> (CRYP_CR_DATATYPE_Pos - SAES_CR_DATATYPE_Pos))
|
||||
|
||||
#define SAES_CONV_KEYSIZE(__KEY__) (((__KEY__)\
|
||||
& CRYP_CR_KEYSIZE_1) << (SAES_CR_KEYSIZE_Pos - (CRYP_CR_KEYSIZE_Pos + 1U)))
|
||||
|
||||
#define SAES_CONV_ALGO(__ALGO__) (((__ALGO__)\
|
||||
& (CRYP_CR_ALGOMODE_1 | CRYP_CR_ALGOMODE_0)) << (SAES_CR_CHMOD_Pos - \
|
||||
CRYP_CR_ALGOMODE_Pos))
|
||||
#endif /* USE_HAL_SAES_ONLY */
|
||||
#define CRYP_CONV_ALGODIR(__ALGODIR__) (((__ALGODIR__)\
|
||||
& SAES_CR_MODE_1) >> ((SAES_CR_MODE_Pos + 1U) - CRYP_CR_ALGODIR_Pos))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Private_Constants CRYP Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private defines -----------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Private_Defines CRYP Private Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Private_Variables CRYP Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private functions prototypes ----------------------------------------------*/
|
||||
/** @defgroup CRYP_Private_Functions_Prototypes CRYP Private Functions Prototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Private_Functions CRYP Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#endif /* CRYP */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* STM32H7RSxx_HAL_CRYP_H */
|
||||
|
|
@ -1,129 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7rsxx_hal_cryp_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CRYP HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7RSxx_HAL_CRYP_EX_H
|
||||
#define STM32H7RSxx_HAL_CRYP_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7rsxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H7RSxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
#if defined (CRYP)
|
||||
/** @addtogroup CRYPEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/** @defgroup CRYPEx_Private_Types CRYPEx Private Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup CRYPEx_Private_Variables CRYPEx Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup CRYPEx_Private_Constants CRYPEx Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup CRYPEx_Private_Macros CRYPEx Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRYPEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, const uint32_t *pAuthTag,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, const uint32_t *pAuthTag,
|
||||
uint32_t Timeout);
|
||||
#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
|
||||
HAL_StatusTypeDef HAL_CRYPEx_EncryptSharedKey(CRYP_HandleTypeDef *hcryp, uint32_t *Key, uint32_t *Output,
|
||||
uint32_t ID, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CRYPEx_DecryptSharedKey(CRYP_HandleTypeDef *hcryp, uint32_t *Key, uint32_t ID,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CRYPEx_UnwrapKey(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CRYPEx_WrapKey(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint32_t *Output, uint32_t Timeout);
|
||||
#endif /* USE_HAL_SAES_ONLY */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* CRYP */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7RSxx_HAL_CRYP_EX_H */
|
||||
|
|
@ -1,948 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7rsxx_hal_dcmipp.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of DCMIPP HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32H7RSxx_HAL_DCMIPP_H
|
||||
#define __STM32H7RSxx_HAL_DCMIPP_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7rsxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H7RSxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (DCMIPP)
|
||||
|
||||
/** @addtogroup DCMIPP DCMIPP
|
||||
* @brief DCMIPP HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ----------------------------------------------------------------------------------------------------*/
|
||||
/** @defgroup DCMIPP_Exported_Types DCMIPP Exported Types
|
||||
* @brief DCMIPP Exported Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief DCMIPP Embedded Synchronisation Unmask codes structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t FrameStartUnmask; /*!< Specifies the frame start delimiter unmask. */
|
||||
uint8_t LineStartUnmask; /*!< Specifies the line start delimiter unmask. */
|
||||
uint8_t LineEndUnmask; /*!< Specifies the line end delimiter unmask. */
|
||||
uint8_t FrameEndUnmask; /*!< Specifies the frame end delimiter unmask. */
|
||||
} DCMIPP_EmbeddedSyncUnmaskTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DCMIPP Embedded Synchronisation codes structure definition (CCIR656)
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t FrameStartCode; /*!< Specifies the code of the frame start delimiter. */
|
||||
uint8_t LineStartCode; /*!< Specifies the code of the line start delimiter. */
|
||||
uint8_t LineEndCode; /*!< Specifies the code of the line end delimiter. */
|
||||
uint8_t FrameEndCode; /*!< Specifies the code of the frame end delimiter. */
|
||||
} DCMIPP_EmbeddedSyncCodesTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief HAL DCMIPP Parallel configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Format; /*!< Configures the DCMIPP Format
|
||||
This parameter can be one value of @ref DCMIPP_Format */
|
||||
uint32_t VSPolarity; /*!< Specifies the Vertical synchronization polarity: High or Low.
|
||||
This parameter can be a value of @ref DCMIPP_VSYNC_Polarity */
|
||||
uint32_t HSPolarity; /*!< Specifies the Horizontal synchronization polarity: High or Low.
|
||||
This parameter can be a value of @ref DCMIPP_HSYNC_Polarity */
|
||||
uint32_t PCKPolarity; /*!< Specifies the Pixel clock polarity: Falling or Rising.
|
||||
This parameter can be a value of @ref DCMIPP_PIXCK_Polarity */
|
||||
uint32_t ExtendedDataMode ; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit 14-bit or 16-bits.
|
||||
This parameter can be a value of @ref DCMIPP_Extended_Data_Mode */
|
||||
uint32_t SynchroMode; /*!< Specifies the Synchronization Mode: Hardware or Embedded.
|
||||
This parameter can be a value of @ref DCMIPP_Synchronization_Mode */
|
||||
DCMIPP_EmbeddedSyncCodesTypeDef SynchroCodes; /*!< Specifies the code of the line/frame start delimiter and the
|
||||
line/frame end delimiter */
|
||||
uint32_t SwapBits; /*!< Enable or Disable the Swap Bits.
|
||||
This parameter can be a value of @ref DCMIPP_SWAP_BITS */
|
||||
uint32_t SwapCycles; /*!< Enable or Disable the Swap Cycles.
|
||||
This parameter can be a value of @ref DCMIPP_SWAP_CYCLES */
|
||||
} DCMIPP_ParallelConfTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DCMIPP Pipe configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FrameRate; /*!< Configures the DCMIPP Pipe Frame Rate
|
||||
This parameter can be one value of @ref DCMIPP_Frame_Rates */
|
||||
} DCMIPP_PipeConfTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DCMIPP IPPLUG configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Client; /*!< Configures the DCMIPP IPPLUG Client
|
||||
This parameter can be a value from @ref DCMIPP_IPPLUG_Client */
|
||||
uint32_t MemoryPageSize; /*!< Configures the DCMIPP IPPLUG Memory page size
|
||||
This parameter can be a value from @ref DCMIPP_Memory_Page_Size */
|
||||
uint32_t Traffic; /*!< Configures the DCMIPP IPPLUG Traffic
|
||||
This parameter can be a value from @ref DCMIPP_Traffic_Burst_Size */
|
||||
uint32_t MaxOutstandingTransactions ; /*!< Configures the DCMIPP IPPLUG Maximum outstanding transactions
|
||||
This parameter can be a value from
|
||||
DCMIPP_Maximum_Outstanding_Transactions */
|
||||
uint32_t DPREGStart; /*!< Configures the End word of the FIFO of Clientx
|
||||
This parameter can be a value between 0 and 0x3FF */
|
||||
uint32_t DPREGEnd; /*!< Configures the Start word of the FIFO of Clientx
|
||||
This parameter can be a value between 0 and 0x3FF */
|
||||
uint32_t WLRURatio; /*!< Configures the DCMIPP Ratio for WLRU arbitration
|
||||
This parameter can be a value between 0 and 15 */
|
||||
} DCMIPP_IPPlugConfTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DCMIPP Crop configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t VStart; /*!< Configures the DCMIPP Crop Vertical Start
|
||||
This parameter can be one value between 0 and 4095 */
|
||||
uint32_t HStart; /*!< Configures the DCMIPP Crop Horizontal Start
|
||||
This parameter can be one value between 0 and 4095 */
|
||||
uint32_t VSize; /*!< Configures the DCMIPP Crop Vertical Size
|
||||
This parameter can be one value between 0 and 4095 */
|
||||
uint32_t HSize; /*!< Configures the DCMIPP Crop Horizontal Size
|
||||
This parameter can be one value between 1 and 4095 */
|
||||
uint32_t PipeArea; /*!< Configures the DCMIPP Crop Area for the pipe0
|
||||
This parameter can be one value of @ref DCMIPP_Crop_Area */
|
||||
} DCMIPP_CropConfTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief HAL DCMIPP State enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DCMIPP_STATE_RESET = 0x00U, /*!< DCMIPP not yet initialized or disabled */
|
||||
HAL_DCMIPP_STATE_INIT = 0x01U, /*!< DCMIPP initialized */
|
||||
HAL_DCMIPP_STATE_READY = 0x02U, /*!< DCMIPP configured and ready for use */
|
||||
HAL_DCMIPP_STATE_BUSY = 0x03U, /*!< DCMIPP internal processing is ongoing */
|
||||
HAL_DCMIPP_STATE_ERROR = 0x04U, /*!< DCMIPP state error */
|
||||
} HAL_DCMIPP_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DCMIPP Pipe State enumeration definition
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
HAL_DCMIPP_PIPE_STATE_RESET = 0x00U, /*!< DCMIPP Pipe not yet initialized or disabled */
|
||||
HAL_DCMIPP_PIPE_STATE_READY = 0x01U, /*!< DCMIPP Pipe initialized and ready for use */
|
||||
HAL_DCMIPP_PIPE_STATE_BUSY = 0x02U, /*!< DCMIPP internal processing is ongoing */
|
||||
HAL_DCMIPP_PIPE_STATE_SUSPEND = 0x03U, /*!< DCMIPP pipe process is suspended */
|
||||
HAL_DCMIPP_PIPE_STATE_ERROR = 0x04U, /*!< DCMIPP pipe error state */
|
||||
} HAL_DCMIPP_PipeStateTypeDef;
|
||||
|
||||
#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL DCMIPP common Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DCMIPP_MSPINIT_CB_ID = 0x00U, /*!< DCMIPP MspInit callback ID */
|
||||
HAL_DCMIPP_MSPDEINIT_CB_ID = 0x01U, /*!< DCMIPP MspDeInit callback ID */
|
||||
HAL_DCMIPP_ERROR_CB_ID = 0x02U, /*!< DCMIPP Error callback ID */
|
||||
} HAL_DCMIPP_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DCMIPP pipe Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DCMIPP_PIPE_LIMIT_EVENT_CB_ID = 0x01U, /*!< DCMIPP Pipe Limit event callback ID */
|
||||
HAL_DCMIPP_PIPE_LINE_EVENT_CB_ID = 0x02U, /*!< DCMIPP Pipe Line event callback ID */
|
||||
HAL_DCMIPP_PIPE_FRAME_EVENT_CB_ID = 0x03U, /*!< DCMIPP Pipe Frame event callback ID */
|
||||
HAL_DCMIPP_PIPE_VSYNC_EVENT_CB_ID = 0x04U, /*!< DCMIPP Pipe Vsync event callback ID */
|
||||
HAL_DCMIPP_PIPE_ERROR_CB_ID = 0x05U, /*!< DCMIPP Pipe Error callback ID */
|
||||
} HAL_DCMIPP_PIPE_CallbackIDTypeDef;
|
||||
#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @brief HAL DCMIPP handle structures definition
|
||||
*/
|
||||
#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __DCMIPP_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
|
||||
{
|
||||
DCMIPP_TypeDef *Instance; /*!< Register the DCMIPP base
|
||||
address */
|
||||
__IO HAL_DCMIPP_StateTypeDef State; /*!< DCMIPP state */
|
||||
__IO HAL_DCMIPP_PipeStateTypeDef PipeState[DCMIPP_NUM_OF_PIPES]; /*!< DCMIPP Pipes state */
|
||||
__IO uint32_t ErrorCode; /*!< DCMIPP Error code */
|
||||
#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
|
||||
void (* PIPE_FrameEventCallback)(struct __DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe); /*!< DCMIPP Pipe Frame Event
|
||||
Callback */
|
||||
void (* PIPE_VsyncEventCallback)(struct __DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe); /*!< DCMIPP Pipe Vsync Event
|
||||
Callback */
|
||||
void (* PIPE_LineEventCallback)(struct __DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe); /*!< DCMIPP Pipe Line Event
|
||||
Callback */
|
||||
void (* PIPE_LimitEventCallback)(struct __DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe); /*!< DCMIPP Pipe Limit Event
|
||||
Callback */
|
||||
void (* PIPE_ErrorCallback)(struct __DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe); /*!< DCMIPP Pipe Error
|
||||
Callback */
|
||||
void (* ErrorCallback)(struct __DCMIPP_HandleTypeDef *hdcmipp); /*!< DCMIPP Error Callback */
|
||||
void (* MspInitCallback)(struct __DCMIPP_HandleTypeDef *hdcmipp); /*!< DCMIPP Msp Init
|
||||
Callback */
|
||||
void (* MspDeInitCallback)(struct __DCMIPP_HandleTypeDef *hdcmipp); /*!< DCMIPP Msp DeInit
|
||||
Callback */
|
||||
#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
|
||||
} DCMIPP_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL DCMIPP Callback pointer definition
|
||||
*/
|
||||
typedef void (*pDCMIPP_CallbackTypeDef)(DCMIPP_HandleTypeDef *hdcmipp); /*!< Pointer to a DCMIPP common callback
|
||||
function */
|
||||
typedef void (*pDCMIPP_PIPE_CallbackTypeDef)(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe); /*!< Pointer to a DCMIPP
|
||||
Pipe callback function */
|
||||
#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DCMIPP_Exported_Constants DCMIPP Exported Constants
|
||||
* @brief DCMIPP Exported constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DCMIPP_Pipes DCMIPP Pipes
|
||||
* @{
|
||||
*/
|
||||
#define DCMIPP_PIPE0 0U /*!< DCMIPP Pipe0 (Dump pipe) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMIPP_Error_Codes DCMIPP Error Codes
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DCMIPP_ERROR_NONE (0x00000000U) /*!< No error */
|
||||
#define HAL_DCMIPP_ERROR_AXI_TRANSFER (0x00000001U) /*!< IPPLUG AXI Transfer error */
|
||||
#define HAL_DCMIPP_ERROR_PARALLEL_SYNC (0x00000002U) /*!< Synchronization error */
|
||||
#define HAL_DCMIPP_ERROR_PIPE0_LIMIT (0x00000004U) /*!< Limit error on pipe0 */
|
||||
#define HAL_DCMIPP_ERROR_PIPE0_OVR (0x00000008U) /*!< Overrun error on pipe0 */
|
||||
|
||||
#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_DCMIPP_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMIPP_Capture_Mode DCMIPP Capture Mode
|
||||
* @{
|
||||
*/
|
||||
#define DCMIPP_MODE_CONTINUOUS 0U /*!< DCMIPP continuous mode (preview) */
|
||||
#define DCMIPP_MODE_SNAPSHOT DCMIPP_P0FCTCR_CPTMODE /*!< DCMIPP snapshot mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DCMIPP_IPPLUG_Client DCMIPP IPPLUG Client
|
||||
* @{
|
||||
*/
|
||||
#define DCMIPP_CLIENT1 1U /*!< Client 1 identifier */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMIPP_Traffic_Burst_Size DCMIPP Traffic Burst Size
|
||||
* @{
|
||||
*/
|
||||
#define DCMIPP_TRAFFIC_BURST_SIZE_8BYTES 0U /*!< Traffic Burst size 8 Bytes */
|
||||
#define DCMIPP_TRAFFIC_BURST_SIZE_16BYTES (0x01U << DCMIPP_IPC1R1_TRAFFIC_Pos) /*!< Traffic Burst size 16 Bytes */
|
||||
#define DCMIPP_TRAFFIC_BURST_SIZE_32BYTES (0x02U << DCMIPP_IPC1R1_TRAFFIC_Pos) /*!< Traffic Burst size 32 Bytes */
|
||||
#define DCMIPP_TRAFFIC_BURST_SIZE_64BYTES (0x03U << DCMIPP_IPC1R1_TRAFFIC_Pos) /*!< Traffic Burst size 64 Bytes */
|
||||
#define DCMIPP_TRAFFIC_BURST_SIZE_128BYTES (0x04U << DCMIPP_IPC1R1_TRAFFIC_Pos) /*!< Traffic Burst size 128 Bytes */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMIPP_Memory_Page_Size DCMIPP Memory Page Size
|
||||
* @{
|
||||
*/
|
||||
#define DCMIPP_MEMORY_PAGE_SIZE_64BYTES 0U /*!< Memory Page size 64 Bytes */
|
||||
#define DCMIPP_MEMORY_PAGE_SIZE_128BYTES (0x01U << DCMIPP_IPGR1_MEMORYPAGE_Pos) /*!< Memory Page size 128 Bytes */
|
||||
#define DCMIPP_MEMORY_PAGE_SIZE_256BYTES (0x02U << DCMIPP_IPGR1_MEMORYPAGE_Pos) /*!< Memory Page size 256 Bytes */
|
||||
#define DCMIPP_MEMORY_PAGE_SIZE_512BYTES (0x03U << DCMIPP_IPGR1_MEMORYPAGE_Pos) /*!< Memory Page size 512 Bytes */
|
||||
#define DCMIPP_MEMORY_PAGE_SIZE_1KBYTES (0x04U << DCMIPP_IPGR1_MEMORYPAGE_Pos) /*!< Memory Page size 1 Bytes */
|
||||
#define DCMIPP_MEMORY_PAGE_SIZE_2KBYTES (0x05U << DCMIPP_IPGR1_MEMORYPAGE_Pos) /*!< Memory Page size 2 Bytes */
|
||||
#define DCMIPP_MEMORY_PAGE_SIZE_4KBYTES (0x06U << DCMIPP_IPGR1_MEMORYPAGE_Pos) /*!< Memory Page size 4 Bytes */
|
||||
#define DCMIPP_MEMORY_PAGE_SIZE_8KBYTES (0x07U << DCMIPP_IPGR1_MEMORYPAGE_Pos) /*!< Memory Page size 8 Bytes */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup DCMIPP_Maximum_Outstanding_Transactions DCMIPP Maximum Outstanding Transactions
|
||||
* @{
|
||||
*/
|
||||
#define DCMIPP_OUTSTANDING_TRANSACTION_NONE 0U /*!< Nooutstanding transaction limitation*/
|
||||
#define DCMIPP_OUTSTANDING_TRANSACTION_2 (0x01U << DCMIPP_IPC1R1_OTR_Pos) /*!< Two outstanding transactions */
|
||||
#define DCMIPP_OUTSTANDING_TRANSACTION_3 (0x02U << DCMIPP_IPC1R1_OTR_Pos) /*!< Three outstanding transactions */
|
||||
#define DCMIPP_OUTSTANDING_TRANSACTION_4 (0x03U << DCMIPP_IPC1R1_OTR_Pos) /*!< Four outstanding transactions */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMIPP_Frame_Rates DCMIPP Frame Rates
|
||||
* @{
|
||||
*/
|
||||
#define DCMIPP_FRAME_RATE_ALL 0U /*!< All frames captured */
|
||||
#define DCMIPP_FRAME_RATE_1_OVER_2 (1U << DCMIPP_P0FCTCR_FRATE_Pos) /*!< 1 frame over 2 captured */
|
||||
#define DCMIPP_FRAME_RATE_1_OVER_4 (2U << DCMIPP_P0FCTCR_FRATE_Pos) /*!< 1 frame over 4 captured */
|
||||
#define DCMIPP_FRAME_RATE_1_OVER_8 (3U << DCMIPP_P0FCTCR_FRATE_Pos) /*!< 1 frame over 8 captured */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMIPP_Crop_Area DCMIPP Crop Area
|
||||
* @{
|
||||
*/
|
||||
#define DCMIPP_POSITIVE_AREA 0U /*!< Positive Area chosen for crop */
|
||||
#define DCMIPP_NEGATIVE_AREA DCMIPP_P0SCSZR_POSNEG /*!< Negative Area chosen for crop */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** @defgroup DCMIPP_Format DCMIPP Format
|
||||
* @{
|
||||
*/
|
||||
#define DCMIPP_FORMAT_BYTE 0U /*!< DCMIPP Format BYTE */
|
||||
#define DCMIPP_FORMAT_YUV422 (0x1EU << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format YUV422 */
|
||||
#define DCMIPP_FORMAT_RGB565 (0x22U << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format RGB565 */
|
||||
#define DCMIPP_FORMAT_RGB666 (0x23U << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format RGB666 */
|
||||
#define DCMIPP_FORMAT_RGB888 (0x24U << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format RGB888 */
|
||||
#define DCMIPP_FORMAT_RAW8 (0x2AU << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format RAW8 */
|
||||
#define DCMIPP_FORMAT_RAW10 (0x2BU << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format RAW10 */
|
||||
#define DCMIPP_FORMAT_RAW12 (0x2CU << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format RAW12 */
|
||||
#define DCMIPP_FORMAT_RAW14 (0x2DU << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format RAW14 */
|
||||
#define DCMIPP_FORMAT_MONOCHROME_8B (0x4AU << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format 8-bits */
|
||||
#define DCMIPP_FORMAT_MONOCHROME_10B (0x4BU << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format 10-bits */
|
||||
#define DCMIPP_FORMAT_MONOCHROME_12B (0x4CU << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format 12-bits */
|
||||
#define DCMIPP_FORMAT_MONOCHROME_14B (0x4DU << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format 14-bits */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMIPP_Extended_Data_Mode DCMIPP Extended Data Mode
|
||||
* @{
|
||||
*/
|
||||
#define DCMIPP_INTERFACE_8BITS 0U /*!< Interface captures 8bits on every pixel clock */
|
||||
#define DCMIPP_INTERFACE_10BITS (1U << DCMIPP_PRCR_EDM_Pos) /*!< Interface captures 10bits on every pixel clock */
|
||||
#define DCMIPP_INTERFACE_12BITS (2U << DCMIPP_PRCR_EDM_Pos) /*!< Interface captures 12bits on every pixel clock */
|
||||
#define DCMIPP_INTERFACE_14BITS (3U << DCMIPP_PRCR_EDM_Pos) /*!< Interface captures 14bits on every pixel clock */
|
||||
#define DCMIPP_INTERFACE_16BITS (4U << DCMIPP_PRCR_EDM_Pos) /*!< Interface captures 16bits on every pixel clock */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMIPP_HSYNC_Polarity DCMIPP HSYNC Polarity
|
||||
* @{
|
||||
*/
|
||||
#define DCMIPP_HSPOLARITY_LOW 0U /*!< Horizontal synchronization active Low */
|
||||
#define DCMIPP_HSPOLARITY_HIGH DCMIPP_PRCR_HSPOL /*!< Horizontal synchronization active High */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup DCMIPP_VSYNC_Polarity DCMIPP VSYNC Polarity
|
||||
* @{
|
||||
*/
|
||||
#define DCMIPP_VSPOLARITY_LOW 0U /*!< Vertical synchronization active Low */
|
||||
#define DCMIPP_VSPOLARITY_HIGH DCMIPP_PRCR_VSPOL /*!< Vertical synchronization active High */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup DCMIPP_PIXCK_Polarity DCMIPP PIXCK Polarity
|
||||
* @{
|
||||
*/
|
||||
#define DCMIPP_PCKPOLARITY_FALLING 0U /*!< Pixel clock active on Falling edge */
|
||||
#define DCMIPP_PCKPOLARITY_RISING DCMIPP_PRCR_PCKPOL /*!< Pixel clock active on Rising edge */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMIPP_Synchronization_Mode DCMIPP Synchronization Mode
|
||||
* @{
|
||||
*/
|
||||
#define DCMIPP_SYNCHRO_HARDWARE 0U /*!< Hardware Synchronization */
|
||||
#define DCMIPP_SYNCHRO_EMBEDDED DCMIPP_PRCR_ESS /*!< Embedded Synchronization */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMIPP_SWAP_CYCLES DCMIPP Swap Cycles
|
||||
* @{
|
||||
*/
|
||||
#define DCMIPP_SWAPCYCLES_DISABLE 0U /*!< swap data from cycle 0 vs cycle 1 */
|
||||
#define DCMIPP_SWAPCYCLES_ENABLE (DCMIPP_PRCR_SWAPCYCLES) /*!< swap data from cycle 0 vs cycle 1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMIPP_SWAP_BITS DCMIPP Swap Bits
|
||||
* @{
|
||||
*/
|
||||
#define DCMIPP_SWAPBITS_DISABLE 0U /*!< swap lsb vs msb within each received component */
|
||||
#define DCMIPP_SWAPBITS_ENABLE (DCMIPP_PRCR_SWAPBITS) /*!< swap lsb vs msb within each received component */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMIPP_Pipe_Line_Decimation DCMIPP Pipe Line Decimation
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup DCMIPP_Line_Select_Mode DCMIPP Line Select Mode
|
||||
* @{
|
||||
*/
|
||||
#define DCMIPP_LSM_ALL 0U /*!< Interface captures all received lines */
|
||||
#define DCMIPP_LSM_ALTERNATE_2 (1U << DCMIPP_P0PPCR_LSM_Pos ) /*!< Interface captures one line out of two */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup DCMIPP_Line_Start_Mode DCMIPP Line Start Mode
|
||||
* @{
|
||||
*/
|
||||
#define DCMIPP_OELS_ODD 0U /*!< Interface captures first line from the frame start,
|
||||
second one is dropped */
|
||||
#define DCMIPP_OELS_EVEN (1U << DCMIPP_P0PPCR_OELS_Pos) /*!< Interface captures second line from the frame
|
||||
start, first one is dropped */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMIPP_Pipe_Byte_Decimation DCMIPP Pipe Byte Decimation
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup DCMIPP_Byte_Select_Mode DCMIPP Byte Select Mode
|
||||
* @{
|
||||
*/
|
||||
#define DCMIPP_BSM_ALL 0U /*!< Interface captures all received data */
|
||||
#define DCMIPP_BSM_DATA_OUT_2 (1U << DCMIPP_P0PPCR_BSM_Pos) /*!< Interface captures 1 data out of 2 */
|
||||
#define DCMIPP_BSM_BYTE_OUT_4 (2U << DCMIPP_P0PPCR_BSM_Pos) /*!< Interface captures 1 byte out of 4 */
|
||||
#define DCMIPP_BSM_2BYTE_OUT_4 (3U << DCMIPP_P0PPCR_BSM_Pos) /*!< Interface captures 2 byte out of 4 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup DCMIPP_Byte_Start_Mode DCMIPP Byte Start Mode
|
||||
* @{
|
||||
*/
|
||||
#define DCMIPP_OEBS_ODD 0U /*!< Interface captures first data (byte or double byte)
|
||||
from the frame/line start,second one being dropped */
|
||||
#define DCMIPP_OEBS_EVEN (1U << DCMIPP_P0PPCR_OEBS_Pos) /*!< Interface captures second data (byte or double byte)
|
||||
from the frame/line start, first one is dropped */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMIPP_Memory DCMIPP Memory
|
||||
* @{
|
||||
*/
|
||||
#define DCMIPP_MEMORY_ADDRESS_0 0U /*!< Base destination address */
|
||||
#define DCMIPP_MEMORY_ADDRESS_1 1U /*!< Second destination address */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup DCMIPP_LineMult DCMIPP Line Mult
|
||||
* @{
|
||||
*/
|
||||
#define DCMIPP_MULTILINE_1_LINE 0U /*!< Event after every 1 line */
|
||||
#define DCMIPP_MULTILINE_2_LINES (1U << DCMIPP_P0PPCR_LINEMULT_Pos) /*!< Event after every 2 lines */
|
||||
#define DCMIPP_MULTILINE_4_LINES (2U << DCMIPP_P0PPCR_LINEMULT_Pos) /*!< Event after every 4 lines */
|
||||
#define DCMIPP_MULTILINE_8_LINES (3U << DCMIPP_P0PPCR_LINEMULT_Pos) /*!< Event after every 8 lines */
|
||||
#define DCMIPP_MULTILINE_16_LINES (4U << DCMIPP_P0PPCR_LINEMULT_Pos) /*!< Event after every 16 lines */
|
||||
#define DCMIPP_MULTILINE_32_LINES (5U << DCMIPP_P0PPCR_LINEMULT_Pos) /*!< Event after every 32 lines */
|
||||
#define DCMIPP_MULTILINE_64_LINES (6U << DCMIPP_P0PPCR_LINEMULT_Pos) /*!< Event after every 64 lines */
|
||||
#define DCMIPP_MULTILINE_128_LINES (7U << DCMIPP_P0PPCR_LINEMULT_Pos) /*!< Event after every 128 lines */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup DCMIPP_Interrupt_Sources DCMIPP Interrupt sources
|
||||
* @{
|
||||
*/
|
||||
#define DCMIPP_IT_AXI_TRANSFER_ERROR DCMIPP_CMIER_ATXERRIE /*!< IPPLUG AXI Transfer error interrupt */
|
||||
#define DCMIPP_IT_PARALLEL_SYNC_ERROR DCMIPP_CMIER_PRERRIE /*!< Sync error interrupt on parallel interface */
|
||||
#define DCMIPP_IT_PIPE0_FRAME DCMIPP_CMIER_P0FRAMEIE /*!< Frame capture interrupt complete for pipe0 */
|
||||
#define DCMIPP_IT_PIPE0_VSYNC DCMIPP_CMIER_P0VSYNCIE /*!< Vertical sync interrupt for pipe0 */
|
||||
#define DCMIPP_IT_PIPE0_LINE DCMIPP_CMIER_P0LINEIE /*!< Multiline interrupt for pipe0 */
|
||||
#define DCMIPP_IT_PIPE0_LIMIT DCMIPP_CMIER_P0LIMITIE /*!< Limit interrupt for pipe0 */
|
||||
#define DCMIPP_IT_PIPE0_OVR DCMIPP_CMIER_P0OVRIE /*!< Overrun interrupt for pipe0 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMIPP_Interrupt_Flags DCMIPP Interrupt Flags
|
||||
* @{
|
||||
*/
|
||||
#define DCMIPP_FLAG_AXI_TRANSFER_ERROR DCMIPP_CMSR2_ATXERRF /*!< IPPLUG AXI Transfer error interrupt flag */
|
||||
#define DCMIPP_FLAG_PARALLEL_SYNC_ERROR DCMIPP_CMSR2_PRERRF /*!< Synchronization error interrupt on parallel interface
|
||||
flag */
|
||||
#define DCMIPP_FLAG_PIPE0_FRAME DCMIPP_CMSR2_P0FRAMEF /*!< Frame capture interrupt complete for pipe0 flag */
|
||||
#define DCMIPP_FLAG_PIPE0_VSYNC DCMIPP_CMSR2_P0VSYNCF /*!< Vertical synch interrupt for pipe0 flag */
|
||||
#define DCMIPP_FLAG_PIPE0_LINE DCMIPP_CMSR2_P0LINEF /*!< Multiline interrupt for pipe0 flag */
|
||||
#define DCMIPP_FLAG_PIPE0_LIMIT DCMIPP_CMSR2_P0LIMITF /*!< Limit interrupt for pipe0 flag */
|
||||
#define DCMIPP_FLAG_PIPE0_OVR DCMIPP_CMSR2_P0OVRF /*!< Overrun interrupt for pipe0 flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup DCMIPP_Exported_Macros DCMIPP Exported Macros
|
||||
* @brief DCMIPP Exported Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enable the specified DCMIPP interrupts.
|
||||
* @param __HANDLE__ DCMIPP handle
|
||||
* @param __INTERRUPT__ specifies the DCMIPP interrupt sources to be enabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DCMIPP_IT_AXI_TRANSFER_ERR IPPLUG AXI Transfer error interrupt
|
||||
* @arg DCMIPP_IT_PARALLEL_SYNC_ERR Synchronization error interrupt on parallel interface
|
||||
* @arg DCMIPP_IT_PIPE0_FRAME Frame capture complete interrupt for the pipe0
|
||||
* @arg DCMIPP_IT_PIPE0_VSYNC Vertical sync interrupt for the pipe0
|
||||
* @arg DCMIPP_IT_PIPE0_LINE Multi-line capture complete interrupt for the pipe0
|
||||
* @arg DCMIPP_IT_PIPE0_LIMIT Limit interrupt for the pipe0
|
||||
* @arg DCMIPP_IT_PIPE0_OVR Overrun interrupt for the pipe0
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DCMIPP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CMIER |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the specified DCMIPP interrupts.
|
||||
* @param __HANDLE__ DCMIPP handle
|
||||
* @param __INTERRUPT__ specifies the DCMIPP interrupt sources to be disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DCMIPP_IT_AXI_TRANSFER_ERR IPPLUG AXI Transfer error interrupt
|
||||
* @arg DCMIPP_IT_PARALLEL_SYNC_ERR Synchronization error interrupt on parallel interface
|
||||
* @arg DCMIPP_IT_PIPE0_FRAME Frame capture complete interrupt for the pipe0
|
||||
* @arg DCMIPP_IT_PIPE0_VSYNC Vertical sync interrupt for the pipe0
|
||||
* @arg DCMIPP_IT_PIPE0_LINE Multi-line capture complete interrupt for the pipe0
|
||||
* @arg DCMIPP_IT_PIPE0_LIMIT Limit interrupt for the pipe0
|
||||
* @arg DCMIPP_IT_PIPE0_OVR Overrun interrupt for the pipe0
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DCMIPP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CMIER &= ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Get the DCMIPP pending interrupt flags.
|
||||
* @param __HANDLE__ DCMIPP handle
|
||||
* @param __FLAG__ Get the specified flag.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DCMIPP_FLAG_AXI_TRANSFER_ERR IPPLUG AXI Transfer error interrupt flag
|
||||
* @arg DCMIPP_FLAG_PARALLEL_SYNC_ERR Synchronization error interrupt flag on parallel interface
|
||||
* @arg DCMIPP_FLAG_PIPE0_FRAME Frame capture complete interrupt flag for the pipe0
|
||||
* @arg DCMIPP_FLAG_PIPE0_VSYNC Vertical sync interrupt flag for the pipe0
|
||||
* @arg DCMIPP_FLAG_PIPE0_LINE Multi-line capture complete interrupt flag for the pipe0
|
||||
* @arg DCMIPP_FLAG_PIPE0_LIMIT Limit interrupt flag for the pipe0
|
||||
* @arg DCMIPP_FLAG_PIPE0_OVR Overrun interrupt flag for the pipe0
|
||||
* @retval The state of FLAG (SET or RESET).
|
||||
*/
|
||||
#define __HAL_DCMIPP_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CMSR2 & (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Clear the DCMIPP pending interrupt flags.
|
||||
* @param __HANDLE__ DCMIPP handle
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DCMIPP_FLAG_AXI_TRANSFER_ERR IPPLUG AXI Transfer error interrupt
|
||||
* @arg DCMIPP_FLAG_PARALLEL_SYNC_ERR Synchronization error interrupt on parallel interface
|
||||
* @arg DCMIPP_FLAG_PIPE0_FRAME Frame capture complete interrupt for the pipe0
|
||||
* @arg DCMIPP_FLAG_PIPE0_VSYNC Vertical sync interrupt for the pipe0
|
||||
* @arg DCMIPP_FLAG_PIPE0_LINE Multi-line capture complete interrupt for the pipe0
|
||||
* @arg DCMIPP_FLAG_PIPE0_LIMIT Limit interrupt for the pipe0
|
||||
* @arg DCMIPP_FLAG_PIPE0_OVR Overrun interrupt for the pipe0
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DCMIPP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CMFCR = (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified DCMIPP interrupt is enabled or not.
|
||||
* @param __HANDLE__ DCMIPP handle
|
||||
* @param __INTERRUPT__ specifies the DCMIPP interrupt sources to be checked.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DCMIPP_IT_AXI_TRANSFER_ERR IPPLUG AXI Transfer error interrupt
|
||||
* @arg DCMIPP_IT_PARALLEL_SYNC_ERR Synchronization error interrupt on parallel interface
|
||||
* @arg DCMIPP_IT_PIPE0_FRAME Frame capture complete interrupt for the pipe0
|
||||
* @arg DCMIPP_IT_PIPE0_VSYNC Vertical sync interrupt for the pipe0
|
||||
* @arg DCMIPP_IT_PIPE0_LINE Multi-line capture complete interrupt for the pipe0
|
||||
* @arg DCMIPP_IT_PIPE0_LIMIT Limit interrupt for the pipe0
|
||||
* @arg DCMIPP_IT_PIPE0_OVR Overrun interrupt for the pipe0
|
||||
* @retval The state of DCMIPP interrupt (SET or RESET).
|
||||
*/
|
||||
#define __HAL_DCMIPP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CMIER & \
|
||||
(__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup DCMIPP_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DCMIPP_Initialization_De-Initialization_Functions DCMIPP Initialization De-Initialization Functions
|
||||
* @brief Initialization and De-Initialization Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DCMIPP_Init(DCMIPP_HandleTypeDef *hdcmipp);
|
||||
HAL_StatusTypeDef HAL_DCMIPP_DeInit(DCMIPP_HandleTypeDef *hdcmipp);
|
||||
void HAL_DCMIPP_MspInit(DCMIPP_HandleTypeDef *hdcmipp);
|
||||
void HAL_DCMIPP_MspDeInit(DCMIPP_HandleTypeDef *hdcmipp);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMIPP_Configuration_Functions DCMIPP Configuration Functions
|
||||
* @brief Configuration Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_DCMIPP_PARALLEL_SetConfig(DCMIPP_HandleTypeDef *hdcmipp,
|
||||
const DCMIPP_ParallelConfTypeDef *pParallelConfig);
|
||||
|
||||
HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
|
||||
const DCMIPP_PipeConfTypeDef *pPipeConfig);
|
||||
HAL_StatusTypeDef HAL_DCMIPP_SetIPPlugConfig(DCMIPP_HandleTypeDef *hdcmipp,
|
||||
const DCMIPP_IPPlugConfTypeDef *pIPPlugConfig);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DCMIPP_IO_operation_Functions DCMIPP IO operation Functions
|
||||
* @brief IO Operation Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DCMIPP_PIPE_Start(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t DstAddress,
|
||||
uint32_t CaptureMode);
|
||||
HAL_StatusTypeDef HAL_DCMIPP_PIPE_DoubleBufferStart(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t DstAddress0,
|
||||
uint32_t DstAddress1, uint32_t CaptureMode);
|
||||
HAL_StatusTypeDef HAL_DCMIPP_PIPE_Stop(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
|
||||
HAL_StatusTypeDef HAL_DCMIPP_PIPE_Suspend(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
|
||||
HAL_StatusTypeDef HAL_DCMIPP_PIPE_Resume(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DCMIPP_IRQ_and_Callbacks_Functions DCMIPP IRQ and Callbacks Functions
|
||||
* @brief IRQ and Callbacks functions
|
||||
* @{
|
||||
*/
|
||||
/** @addtogroup DCMIPP_IRQHandler_Functions IRQHandler Functions
|
||||
* @{
|
||||
*/
|
||||
void HAL_DCMIPP_IRQHandler(DCMIPP_HandleTypeDef *hdcmipp);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @addtogroup DCMIPP_Callback_Functions Callback Functions
|
||||
* @{
|
||||
*/
|
||||
void HAL_DCMIPP_PIPE_FrameEventCallback(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
|
||||
void HAL_DCMIPP_PIPE_VsyncEventCallback(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
|
||||
void HAL_DCMIPP_PIPE_LineEventCallback(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
|
||||
void HAL_DCMIPP_PIPE_LimitEventCallback(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
|
||||
void HAL_DCMIPP_PIPE_ErrorCallback(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
|
||||
void HAL_DCMIPP_ErrorCallback(DCMIPP_HandleTypeDef *hdcmipp);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DCMIPP_RegisterCallback_Functions Register Callback Functions
|
||||
* @{
|
||||
*/
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_DCMIPP_RegisterCallback(DCMIPP_HandleTypeDef *hdcmipp, HAL_DCMIPP_CallbackIDTypeDef CallbackID,
|
||||
pDCMIPP_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_DCMIPP_UnRegisterCallback(DCMIPP_HandleTypeDef *hdcmipp,
|
||||
HAL_DCMIPP_CallbackIDTypeDef CallbackID);
|
||||
|
||||
HAL_StatusTypeDef HAL_DCMIPP_PIPE_RegisterCallback(DCMIPP_HandleTypeDef *hdcmipp,
|
||||
HAL_DCMIPP_PIPE_CallbackIDTypeDef CallbackID,
|
||||
pDCMIPP_PIPE_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_DCMIPP_PIPE_UnRegisterCallback(DCMIPP_HandleTypeDef *hdcmipp,
|
||||
HAL_DCMIPP_PIPE_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMIPP_Decimation_Functions DCMIPP Decimation Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetBytesDecimationConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
|
||||
uint32_t SelectStart, uint32_t SelectMode);
|
||||
HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetLinesDecimationConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
|
||||
uint32_t SelectStart, uint32_t SelectMode);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup DCMIPP_Crop_Functions DCMIPP Crop Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetCropConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
|
||||
const DCMIPP_CropConfTypeDef *pCropConfig);
|
||||
HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableCrop(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
|
||||
HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableCrop(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup DCMIPP_Line_Event_Functions DCMIPP Line Event Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableLineEvent(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t Line);
|
||||
HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableLineEvent(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup DCMIPP_LimitEvent_Functions DCMIPP Limit Event Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableLimitEvent(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t Limit);
|
||||
HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableLimitEvent(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMIPP_PeripheralControl_Functions DCMIPP Peripheral Control Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetFrameRate(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t FrameRate);
|
||||
HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetCaptureMode(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t CaptureMode);
|
||||
HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableCapture(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
|
||||
HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetMemoryAddress(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t Memory,
|
||||
uint32_t DstAddress);
|
||||
HAL_StatusTypeDef HAL_DCMIPP_PIPE_PARALLEL_SetInputPixelFormat(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
|
||||
uint32_t InputPixelFormat);
|
||||
HAL_StatusTypeDef HAL_DCMIPP_PARALLEL_SetSyncUnmask(DCMIPP_HandleTypeDef *hdcmipp,
|
||||
const DCMIPP_EmbeddedSyncUnmaskTypeDef *SyncUnmask);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMIPP_Frame_Counter_Functions DCMIPP Frame Counter Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DCMIPP_PIPE_ResetFrameCounter(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
|
||||
HAL_StatusTypeDef HAL_DCMIPP_PIPE_ReadFrameCounter(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
|
||||
uint32_t *pCounter);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup DCMIPP_Data_Counter_Functions DCMIPP Data Counter Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DCMIPP_PIPE_GetDataCounter(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
|
||||
uint32_t *pCounter);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DCMIPP_State_and_Error_Functions DCMIPP State and Error Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_DCMIPP_StateTypeDef HAL_DCMIPP_GetState(const DCMIPP_HandleTypeDef *hdcmipp);
|
||||
HAL_DCMIPP_PipeStateTypeDef HAL_DCMIPP_PIPE_GetState(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
|
||||
uint32_t HAL_DCMIPP_GetError(const DCMIPP_HandleTypeDef *hdcmipp);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup DCMIPP_Private_Macros DCMIPP Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_DCMIPP_PIPE(PIPE) ((PIPE) == DCMIPP_PIPE0)
|
||||
#define IS_DCMIPP_FORMAT(FORMAT) (((FORMAT) == DCMIPP_FORMAT_BYTE) ||\
|
||||
((FORMAT) == DCMIPP_FORMAT_YUV422) ||\
|
||||
((FORMAT) == DCMIPP_FORMAT_RGB565) ||\
|
||||
((FORMAT) == DCMIPP_FORMAT_RGB666) ||\
|
||||
((FORMAT) == DCMIPP_FORMAT_RGB888) ||\
|
||||
((FORMAT) == DCMIPP_FORMAT_RAW8 ) ||\
|
||||
((FORMAT) == DCMIPP_FORMAT_RAW10 ) ||\
|
||||
((FORMAT) == DCMIPP_FORMAT_RAW12 ) ||\
|
||||
((FORMAT) == DCMIPP_FORMAT_RAW14 ) ||\
|
||||
((FORMAT) == DCMIPP_FORMAT_MONOCHROME_8B) ||\
|
||||
((FORMAT) == DCMIPP_FORMAT_MONOCHROME_10B) ||\
|
||||
((FORMAT) == DCMIPP_FORMAT_MONOCHROME_12B) ||\
|
||||
((FORMAT) == DCMIPP_FORMAT_MONOCHROME_14B))
|
||||
|
||||
|
||||
#define IS_DCMIPP_PCKPOLARITY(POLARITY)(((POLARITY) == DCMIPP_PCKPOLARITY_FALLING) || \
|
||||
((POLARITY) == DCMIPP_PCKPOLARITY_RISING))
|
||||
|
||||
#define IS_DCMIPP_VSPOLARITY(POLARITY)(((POLARITY) == DCMIPP_VSPOLARITY_LOW) || \
|
||||
((POLARITY) == DCMIPP_VSPOLARITY_HIGH))
|
||||
|
||||
#define IS_DCMIPP_HSPOLARITY(POLARITY)(((POLARITY) == DCMIPP_HSPOLARITY_LOW) || \
|
||||
((POLARITY) == DCMIPP_HSPOLARITY_HIGH))
|
||||
|
||||
|
||||
#define IS_DCMIPP_EXTENDED_DATA_MODE(INTERFACE)(((INTERFACE) == DCMIPP_INTERFACE_8BITS ) ||\
|
||||
((INTERFACE) == DCMIPP_INTERFACE_10BITS) ||\
|
||||
((INTERFACE) == DCMIPP_INTERFACE_12BITS) ||\
|
||||
((INTERFACE) == DCMIPP_INTERFACE_14BITS) ||\
|
||||
((INTERFACE) == DCMIPP_INTERFACE_16BITS))
|
||||
|
||||
|
||||
#define IS_DCMIPP_SYNC_MODE(SYNC_MODE) (((SYNC_MODE) == DCMIPP_SYNCHRO_HARDWARE) ||\
|
||||
((SYNC_MODE) == DCMIPP_SYNCHRO_EMBEDDED))
|
||||
|
||||
#define IS_DCMIPP_SWAP_BITS(SWAP_BITS) (((SWAP_BITS) == DCMIPP_SWAPBITS_ENABLE) ||\
|
||||
((SWAP_BITS) == DCMIPP_SWAPBITS_DISABLE))
|
||||
|
||||
#define IS_DCMIPP_SWAP_CYCLES(SWAP_CYCLES) (((SWAP_CYCLES) == DCMIPP_SWAPCYCLES_ENABLE) ||\
|
||||
((SWAP_CYCLES) == DCMIPP_SWAPCYCLES_DISABLE))
|
||||
|
||||
|
||||
|
||||
#define IS_DCMIPP_FRAME_RATE(FRAME_RATE) (((FRAME_RATE) == DCMIPP_FRAME_RATE_ALL) ||\
|
||||
((FRAME_RATE) == DCMIPP_FRAME_RATE_1_OVER_2) ||\
|
||||
((FRAME_RATE) == DCMIPP_FRAME_RATE_1_OVER_4) ||\
|
||||
((FRAME_RATE) == DCMIPP_FRAME_RATE_1_OVER_8))
|
||||
|
||||
|
||||
#define IS_DCMIPP_CLIENT(CLIENT) (((CLIENT) == DCMIPP_CLIENT1))
|
||||
|
||||
#define IS_DCMIPP_DPREG_END(DPREG_END) ((DPREG_END) <= 0x1FU)
|
||||
#define IS_DCMIPP_DPREG_START(DPREG_START) ((DPREG_START) <= 0x1FU)
|
||||
|
||||
#define IS_DCMIPP_MAX_OUTSTANDING_TRANSACTIONS(OUTS_TRANS) (((OUTS_TRANS) == DCMIPP_OUTSTANDING_TRANSACTION_NONE )||\
|
||||
((OUTS_TRANS) == DCMIPP_OUTSTANDING_TRANSACTION_2 )||\
|
||||
((OUTS_TRANS) == DCMIPP_OUTSTANDING_TRANSACTION_3 )||\
|
||||
((OUTS_TRANS) == DCMIPP_OUTSTANDING_TRANSACTION_4 ))
|
||||
#define IS_DCMIPP_MEMORY_PAGE_SIZE(MEMORY_PAGE_SIZE) (((MEMORY_PAGE_SIZE) == DCMIPP_MEMORY_PAGE_SIZE_64BYTES) ||\
|
||||
((MEMORY_PAGE_SIZE) == DCMIPP_MEMORY_PAGE_SIZE_128BYTES) ||\
|
||||
((MEMORY_PAGE_SIZE) == DCMIPP_MEMORY_PAGE_SIZE_256BYTES) ||\
|
||||
((MEMORY_PAGE_SIZE) == DCMIPP_MEMORY_PAGE_SIZE_512BYTES) ||\
|
||||
((MEMORY_PAGE_SIZE) == DCMIPP_MEMORY_PAGE_SIZE_1KBYTES) ||\
|
||||
((MEMORY_PAGE_SIZE) == DCMIPP_MEMORY_PAGE_SIZE_2KBYTES) ||\
|
||||
((MEMORY_PAGE_SIZE) == DCMIPP_MEMORY_PAGE_SIZE_4KBYTES) ||\
|
||||
((MEMORY_PAGE_SIZE) == DCMIPP_MEMORY_PAGE_SIZE_8KBYTES))
|
||||
#define IS_DCMIPP_TRAFFIC(TRAFFIC) (((TRAFFIC) == DCMIPP_TRAFFIC_BURST_SIZE_8BYTES ) ||\
|
||||
((TRAFFIC) == DCMIPP_TRAFFIC_BURST_SIZE_16BYTES) ||\
|
||||
((TRAFFIC) == DCMIPP_TRAFFIC_BURST_SIZE_32BYTES) ||\
|
||||
((TRAFFIC) == DCMIPP_TRAFFIC_BURST_SIZE_64BYTES) ||\
|
||||
((TRAFFIC) == DCMIPP_TRAFFIC_BURST_SIZE_128BYTES))
|
||||
#define IS_DCMIPP_WLRU_RATIO(WLRU_RATIO) ((WLRU_RATIO)<= 0xFU)
|
||||
|
||||
#define IS_DCMIPP_CAPTURE_MODE(CAPTURE_MODE) (((CAPTURE_MODE) == DCMIPP_MODE_CONTINUOUS)||\
|
||||
((CAPTURE_MODE) == DCMIPP_MODE_SNAPSHOT))
|
||||
|
||||
#define IS_DCMIPP_PIPE_CROP_AREA(CROP_AREA)(((CROP_AREA) == DCMIPP_POSITIVE_AREA) ||\
|
||||
((CROP_AREA) == DCMIPP_NEGATIVE_AREA))
|
||||
|
||||
#define IS_DCMIPP_PIPE_CROP_HSIZE(CROP_HSIZE) (((CROP_HSIZE) >= 0x1U) && ((CROP_HSIZE) <= 0xFFFU))
|
||||
#define IS_DCMIPP_PIPE_CROP_VSIZE(CROP_VSIZE) (((CROP_VSIZE) >= 0x1U) && ((CROP_VSIZE) <= 0xFFFU))
|
||||
#define IS_DCMIPP_PIPE_CROP_VSTART(CROP_VSTART) ((CROP_VSTART) <= 0xFFFU)
|
||||
#define IS_DCMIPP_PIPE_CROP_HSTART(CROP_HSTART) ((CROP_HSTART) <= 0xFFFU)
|
||||
|
||||
#define IS_DCMIPP_BYTE_SELECT_MODE(BYTE_SELECT) (((BYTE_SELECT) == DCMIPP_BSM_ALL) ||\
|
||||
((BYTE_SELECT) == DCMIPP_BSM_DATA_OUT_2) ||\
|
||||
((BYTE_SELECT) == DCMIPP_BSM_BYTE_OUT_4) ||\
|
||||
((BYTE_SELECT) == DCMIPP_BSM_2BYTE_OUT_4))
|
||||
|
||||
#define IS_DCMIPP_BYTE_SELECT_START(BYTE_START)(((BYTE_START) == DCMIPP_OEBS_ODD) ||\
|
||||
((BYTE_START) == DCMIPP_OEBS_EVEN))
|
||||
|
||||
#define IS_DCMIPP_LINE_SELECT_MODE(LINE_SELECT) (((LINE_SELECT) == DCMIPP_LSM_ALL) ||\
|
||||
((LINE_SELECT) == DCMIPP_LSM_ALTERNATE_2))
|
||||
|
||||
#define IS_DCMIPP_LINE_SELECT_START(LINE__START)(((LINE__START) == DCMIPP_OELS_ODD) ||\
|
||||
((LINE__START) == DCMIPP_OELS_EVEN))
|
||||
|
||||
|
||||
#define IS_DCMIPP_MEMORY_ADDRESS(MEMORY_ADDRESS) (((MEMORY_ADDRESS) == DCMIPP_MEMORY_ADDRESS_0) ||\
|
||||
((MEMORY_ADDRESS) == DCMIPP_MEMORY_ADDRESS_1))
|
||||
|
||||
#define IS_DCMIPP_DATA_LIMIT(DATA_LIMIT) (((DATA_LIMIT) >=1U ) && ((DATA_LIMIT) <= 0xFFFFFFU))
|
||||
|
||||
|
||||
#define IS_DCMIPP_PIPE_MULTILINE(MULTILINE) (((MULTILINE) == DCMIPP_MULTILINE_1_LINE ) ||\
|
||||
((MULTILINE) == DCMIPP_MULTILINE_2_LINES) ||\
|
||||
((MULTILINE) == DCMIPP_MULTILINE_4_LINES) ||\
|
||||
((MULTILINE) == DCMIPP_MULTILINE_8_LINES) ||\
|
||||
((MULTILINE) == DCMIPP_MULTILINE_16_LINES) ||\
|
||||
((MULTILINE) == DCMIPP_MULTILINE_32_LINES) ||\
|
||||
((MULTILINE) == DCMIPP_MULTILINE_64_LINES) ||\
|
||||
((MULTILINE) == DCMIPP_MULTILINE_128_LINES))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* DCMIPP */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32H7RSxx_HAL_DCMIPP_H */
|
||||
|
||||
|
|
@ -1,199 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7rsxx_hal_def.h
|
||||
* @author MCD Application Team
|
||||
* @brief This file contains HAL common defines, enumeration, macros and
|
||||
* structures definitions.
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7RSxx_HAL_DEF_H
|
||||
#define STM32H7RSxx_HAL_DEF_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7rsxx.h"
|
||||
#include "Legacy/stm32_hal_legacy.h" /* Aliases file for old names compatibility */
|
||||
#include <math.h>
|
||||
#include <stddef.h>
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief HAL Status structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_OK = 0x00,
|
||||
HAL_ERROR = 0x01,
|
||||
HAL_BUSY = 0x02,
|
||||
HAL_TIMEOUT = 0x03
|
||||
} HAL_StatusTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL Lock structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_UNLOCKED = 0x00,
|
||||
HAL_LOCKED = 0x01
|
||||
} HAL_LockTypeDef;
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
#if !defined(UNUSED)
|
||||
#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
|
||||
#endif /* UNUSED */
|
||||
|
||||
#define HAL_MAX_DELAY 0xFFFFFFFFU
|
||||
|
||||
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT))
|
||||
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
|
||||
|
||||
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
|
||||
do{ \
|
||||
(__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
|
||||
(__DMA_HANDLE__).Parent = (__HANDLE__); \
|
||||
} while(0)
|
||||
|
||||
/** @brief Reset the Handle's State field.
|
||||
* @param __HANDLE__ specifies the Peripheral Handle.
|
||||
* @note This macro can be used for the following purpose:
|
||||
* - When the Handle is declared as local variable; before passing it as parameter
|
||||
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro
|
||||
* to set to 0 the Handle's "State" field.
|
||||
* Otherwise, "State" field may have any random value and the first time the function
|
||||
* HAL_PPP_Init() is called, the low level hardware initialization will be missed
|
||||
* (i.e. HAL_PPP_MspInit() will not be executed).
|
||||
* - When there is a need to reconfigure the low level hardware: instead of calling
|
||||
* HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
|
||||
* In this later function, when the Handle's "State" field is set to 0, it will execute the function
|
||||
* HAL_PPP_MspInit() which will reconfigure the low level hardware.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
|
||||
|
||||
#if (USE_RTOS == 1)
|
||||
/* Reserved for future use */
|
||||
#error " USE_RTOS should be 0 in the current HAL release "
|
||||
#else
|
||||
#define __HAL_LOCK(__HANDLE__) \
|
||||
do{ \
|
||||
if((__HANDLE__)->Lock == HAL_LOCKED) \
|
||||
{ \
|
||||
return HAL_BUSY; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Lock = HAL_LOCKED; \
|
||||
} \
|
||||
}while (0)
|
||||
|
||||
#define __HAL_UNLOCK(__HANDLE__) \
|
||||
do{ \
|
||||
(__HANDLE__)->Lock = HAL_UNLOCKED; \
|
||||
}while (0)
|
||||
#endif /* USE_RTOS */
|
||||
|
||||
|
||||
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
|
||||
#ifndef __weak
|
||||
#define __weak __attribute__((weak))
|
||||
#endif /* __weak */
|
||||
#ifndef __packed
|
||||
#define __packed __attribute__((packed))
|
||||
#endif /* packed */
|
||||
#elif defined (__GNUC__) /* GNU Compiler */
|
||||
#ifndef __weak
|
||||
#define __weak __attribute__((weak))
|
||||
#endif /* __weak */
|
||||
#ifndef __packed
|
||||
#define __packed __attribute__((__packed__))
|
||||
#endif /* __packed */
|
||||
#endif /* __GNUC__ */
|
||||
|
||||
/* Macro to get buffer 32-bytes aligned (aligned to cache line width) */
|
||||
#define ALIGN_32BYTES(buf) buf __attribute__((aligned(32)))
|
||||
|
||||
/* Macro to get buffer 8-bytes aligned (aligned to double-word width) */
|
||||
/* This alignment is required for double-word DMA transfers */
|
||||
#define ALIGN_8BYTES(buf) buf __attribute__((aligned(8)))
|
||||
|
||||
/* Legacy macros to get variable 4-bytes aligned */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#define __ALIGN_BEGIN
|
||||
#endif /* __ALIGN_BEGIN */
|
||||
#ifndef __ALIGN_END
|
||||
#define __ALIGN_END __attribute__((aligned(4)))
|
||||
#endif /* __ALIGN_END */
|
||||
|
||||
/**
|
||||
* @brief __RAM_FUNC definition
|
||||
*/
|
||||
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
/* ARM Compiler V6
|
||||
---------------
|
||||
RAM functions are defined using the toolchain options.
|
||||
Functions that are executed in RAM should reside in a separate source module.
|
||||
Using the 'Options for File' dialog you can simply change the 'Code / Const'
|
||||
area of a module to a memory space in physical RAM.
|
||||
Available memory areas are declared in the 'Target' tab of the 'Options for Target'
|
||||
dialog.
|
||||
*/
|
||||
#define __RAM_FUNC
|
||||
|
||||
#elif defined (__ICCARM__)
|
||||
/* ICCARM Compiler
|
||||
---------------
|
||||
RAM functions are defined using a specific toolchain keyword "__ramfunc".
|
||||
*/
|
||||
#define __RAM_FUNC __ramfunc
|
||||
|
||||
#elif defined (__GNUC__)
|
||||
/* GNU Compiler
|
||||
------------
|
||||
RAM functions are defined using a specific toolchain attribute
|
||||
"__attribute__((section(".RamFunc")))".
|
||||
*/
|
||||
#define __RAM_FUNC __attribute__((section(".RamFunc")))
|
||||
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
/**
|
||||
* @brief __NOINLINE definition
|
||||
*/
|
||||
#if (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined (__GNUC__)
|
||||
/* ARM V6 & GNU Compiler
|
||||
---------------------
|
||||
*/
|
||||
#define __NOINLINE __attribute__((noinline))
|
||||
|
||||
#elif defined (__ICCARM__)
|
||||
/* ICCARM Compiler
|
||||
---------------
|
||||
*/
|
||||
#define __NOINLINE _Pragma("optimize = no_inline")
|
||||
|
||||
#endif /* __ARMCC_VERSION || __GNUC__ */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7RSxx_HAL_DEF_H */
|
||||
|
|
@ -1,875 +0,0 @@
|
|||
/**
|
||||
**********************************************************************************************************************
|
||||
* @file stm32h7rsxx_hal_dma.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of DMA HAL module.
|
||||
**********************************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
**********************************************************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/
|
||||
#ifndef STM32H7RSxx_HAL_DMA_H
|
||||
#define STM32H7RSxx_HAL_DMA_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ----------------------------------------------------------------------------------------------------------*/
|
||||
#include "stm32h7rsxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H7RSxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/* Exported types ----------------------------------------------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DMA_Exported_Types DMA Exported Types
|
||||
* @brief DMA Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief DMA Transfer Configuration Structure definition.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Request; /*!< Specifies the DMA channel request.
|
||||
This parameter can be a value of @ref DMA_Request_Selection */
|
||||
|
||||
uint32_t BlkHWRequest; /*!< Specifies the Block hardware request mode for DMA channel.
|
||||
Block Hardware request feature can be used only with dedicated peripherals.
|
||||
This parameter can be a value of @ref DMA_Block_Request */
|
||||
|
||||
uint32_t Direction; /*!< Specifies the transfer direction for DMA channel.
|
||||
This parameter can be a value of @ref DMA_Transfer_Direction */
|
||||
|
||||
uint32_t SrcInc; /*!< Specifies the source increment mode for the DMA channel.
|
||||
This parameter can be a value of @ref DMA_Source_Increment_Mode */
|
||||
|
||||
uint32_t DestInc; /*!< Specifies the destination increment mode for the DMA channel.
|
||||
This parameter can be a value of @ref DMA_Destination_Increment_Mode */
|
||||
|
||||
uint32_t SrcDataWidth; /*!< Specifies the source data width for the DMA channel.
|
||||
This parameter can be a value of @ref DMA_Source_Data_Width */
|
||||
|
||||
uint32_t DestDataWidth; /*!< Specifies the destination data width for the DMA channel.
|
||||
This parameter can be a value of @ref DMA_Destination_Data_Width */
|
||||
|
||||
uint32_t Priority; /*!< Specifies the priority level for the DMA channel.
|
||||
This parameter can be a value of @ref DMA_Priority_Level */
|
||||
|
||||
uint32_t SrcBurstLength; /*!< Specifies the source burst length (number of beats within a burst) for the DMA
|
||||
channel.
|
||||
This parameter can be a value between 1 and 64 */
|
||||
|
||||
uint32_t DestBurstLength; /*!< Specifies the destination burst length (number of beats within a burst) for the
|
||||
DMA channel.
|
||||
This parameter can be a value between 1 and 64 */
|
||||
|
||||
uint32_t TransferAllocatedPort; /*!< Specifies the transfer allocated ports.
|
||||
This parameter can be a combination of @ref DMA_Transfer_Allocated_Port */
|
||||
|
||||
uint32_t TransferEventMode; /*!< Specifies the transfer event mode for the DMA channel.
|
||||
This parameter can be a value of @ref DMA_Transfer_Event_Mode */
|
||||
|
||||
uint32_t Mode; /*!< Specifies the transfer mode for the DMA channel.
|
||||
This parameter can be a value of @ref DMA_Transfer_Mode */
|
||||
|
||||
} DMA_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DMA Linked-List Configuration Structure Definition.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Priority; /*!< Specifies the priority level for the DMA channel.
|
||||
This parameter can be a value of @ref DMA_Priority_Level */
|
||||
|
||||
uint32_t LinkStepMode; /*!< Specifies the link step mode for the DMA channel.
|
||||
This parameter can be a value of @ref DMAEx_Link_Step_Mode */
|
||||
|
||||
uint32_t LinkAllocatedPort; /*!< Specifies the linked-list allocated port for the DMA channel.
|
||||
This parameter can be a value of @ref DMAEx_Link_Allocated_Port */
|
||||
|
||||
uint32_t TransferEventMode; /*!< Specifies the transfer event mode for the DMA channel.
|
||||
This parameter can be a value of @ref DMA_Transfer_Event_Mode */
|
||||
|
||||
uint32_t LinkedListMode; /*!< Specifies linked-list transfer mode for the DMA channel.
|
||||
This parameter can be a value of @ref DMAEx_LinkedList_Mode */
|
||||
|
||||
} DMA_InitLinkedListTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DMA State Enumeration Definition.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
|
||||
HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
|
||||
HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
|
||||
HAL_DMA_STATE_ERROR = 0x03U, /*!< DMA error state */
|
||||
HAL_DMA_STATE_ABORT = 0x04U, /*!< DMA Abort state */
|
||||
HAL_DMA_STATE_SUSPEND = 0x05U, /*!< DMA Suspend state */
|
||||
|
||||
} HAL_DMA_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DMA Level Complete Enumeration Definition.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full channel transfer */
|
||||
HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half channel transfer */
|
||||
|
||||
} HAL_DMA_LevelCompleteTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DMA Callbacks IDs Enumeration Definition.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Complete transfer callback ID */
|
||||
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half complete transfer callback ID */
|
||||
HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error transfer callback ID */
|
||||
HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort transfer callback ID */
|
||||
HAL_DMA_XFER_SUSPEND_CB_ID = 0x04U, /*!< Suspend transfer callback ID */
|
||||
HAL_DMA_XFER_ALL_CB_ID = 0x05U /*!< All callback ID */
|
||||
|
||||
} HAL_DMA_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DMA handle Structure definition
|
||||
*/
|
||||
typedef struct __DMA_HandleTypeDef
|
||||
{
|
||||
DMA_Channel_TypeDef *Instance; /*!< Register the DMA channel base address */
|
||||
|
||||
DMA_InitTypeDef Init; /*!< DMA channel init parameters */
|
||||
|
||||
DMA_InitLinkedListTypeDef InitLinkedList; /*!< DMA channel linked-list init parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< DMA locking object */
|
||||
|
||||
uint32_t Mode; /*!< DMA transfer mode */
|
||||
|
||||
__IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< DMA error code */
|
||||
|
||||
void *Parent; /*!< Parent object state */
|
||||
|
||||
void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */
|
||||
|
||||
void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA half transfer complete callback */
|
||||
|
||||
void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */
|
||||
|
||||
void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer Abort callback */
|
||||
|
||||
void (* XferSuspendCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer Suspend callback */
|
||||
|
||||
struct __DMA_QListTypeDef *LinkedListQueue; /*!< DMA linked-list queue */
|
||||
|
||||
} DMA_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported constants ------------------------------------------------------------------------------------------------*/
|
||||
/** @defgroup DMA_Exported_Constants DMA Exported Constants
|
||||
* @brief DMA Exported constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Error_Codes DMA Error Codes
|
||||
* @brief DMA Error Codes
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DMA_ERROR_NONE (0x0000U) /*!< No error */
|
||||
#define HAL_DMA_ERROR_DTE (0x0001U) /*!< Data transfer error */
|
||||
#define HAL_DMA_ERROR_ULE (0x0002U) /*!< Update linked-list item error */
|
||||
#define HAL_DMA_ERROR_USE (0x0004U) /*!< User setting error */
|
||||
#define HAL_DMA_ERROR_TO (0x0008U) /*!< Trigger overrun error */
|
||||
#define HAL_DMA_ERROR_TIMEOUT (0x0010U) /*!< Timeout error */
|
||||
#define HAL_DMA_ERROR_NO_XFER (0x0020U) /*!< No transfer ongoing error */
|
||||
#define HAL_DMA_ERROR_BUSY (0x0040U) /*!< Busy error */
|
||||
#define HAL_DMA_ERROR_INVALID_CALLBACK (0x0080U) /*!< Invalid callback error */
|
||||
#define HAL_DMA_ERROR_NOT_SUPPORTED (0x0100U) /*!< Not supported mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Interrupt_Enable_Definition DMA Interrupt Enable Definition
|
||||
* @brief DMA Interrupt Enable Definition
|
||||
* @{
|
||||
*/
|
||||
#define DMA_IT_TC DMA_CCR_TCIE /*!< Transfer complete interrupt */
|
||||
#define DMA_IT_HT DMA_CCR_HTIE /*!< Half transfer complete interrupt */
|
||||
#define DMA_IT_DTE DMA_CCR_DTEIE /*!< Data transfer error interrupt */
|
||||
#define DMA_IT_ULE DMA_CCR_ULEIE /*!< Update linked-list item error interrupt */
|
||||
#define DMA_IT_USE DMA_CCR_USEIE /*!< User eetting error interrupt */
|
||||
#define DMA_IT_SUSP DMA_CCR_SUSPIE /*!< Completed suspension interrupt */
|
||||
#define DMA_IT_TO DMA_CCR_TOIE /*!< Trigger overrun interrupt */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Flag_Definition DMA Flag Definition
|
||||
* @brief DMA Flag Definition
|
||||
* @{
|
||||
*/
|
||||
#define DMA_FLAG_IDLE DMA_CSR_IDLEF /*!< Idle flag */
|
||||
#define DMA_FLAG_TC DMA_CSR_TCF /*!< Transfer complete flag */
|
||||
#define DMA_FLAG_HT DMA_CSR_HTF /*!< Half transfer complete flag */
|
||||
#define DMA_FLAG_DTE DMA_CSR_DTEF /*!< Data transfer error flag */
|
||||
#define DMA_FLAG_ULE DMA_CSR_ULEF /*!< Update linked-list item error flag */
|
||||
#define DMA_FLAG_USE DMA_CSR_USEF /*!< User setting error flag */
|
||||
#define DMA_FLAG_SUSP DMA_CSR_SUSPF /*!< Completed suspension flag */
|
||||
#define DMA_FLAG_TO DMA_CSR_TOF /*!< Trigger overrun flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Request_Selection DMA Request Selection
|
||||
* @brief DMA Request Selection
|
||||
* @{
|
||||
*/
|
||||
/* HPDMA1 requests */
|
||||
#define HPDMA1_REQUEST_JPEG_RX 0U /*!< HPDMA1 HW request is JPEG_DMA_RX */
|
||||
#define HPDMA1_REQUEST_JPEG_TX 1U /*!< HPDMA1 HW request is JPEG_DMA_TX */
|
||||
#define HPDMA1_REQUEST_XSPI1 2U /*!< HPDMA1 HW request is XSPI1 */
|
||||
#define HPDMA1_REQUEST_XSPI2 3U /*!< HPDMA1 HW request is XSPI2 */
|
||||
#define HPDMA1_REQUEST_SPI3_RX 4U /*!< HPDMA1 HW request is SPI3_RX */
|
||||
#define HPDMA1_REQUEST_SPI3_TX 5U /*!< HPDMA1 HW request is SPI3_TX */
|
||||
#define HPDMA1_REQUEST_SPI4_RX 6U /*!< HPDMA1 HW request is SPI4_RX */
|
||||
#define HPDMA1_REQUEST_SPI4_TX 7U /*!< HPDMA1 HW request is SPI4_TX */
|
||||
#define HPDMA1_REQUEST_ADC1 8U /*!< HPDMA1 HW request is ADC1 */
|
||||
#define HPDMA1_REQUEST_ADC2 9U /*!< HPDMA1 HW request is ADC2 */
|
||||
#define HPDMA1_REQUEST_ADF1_FLT0 10U /*!< HPDMA1 HW request is ADF1_FLT0 */
|
||||
#define HPDMA1_REQUEST_UART4_RX 11U /*!< HPDMA1 HW request is UART4_RX */
|
||||
#define HPDMA1_REQUEST_UART4_TX 12U /*!< HPDMA1 HW request is UART4_TX */
|
||||
#define HPDMA1_REQUEST_UART5_RX 13U /*!< HPDMA1 HW request is UART5_RX */
|
||||
#define HPDMA1_REQUEST_UART5_TX 14U /*!< HPDMA1 HW request is UART5_TX */
|
||||
#define HPDMA1_REQUEST_UART7_RX 15U /*!< HPDMA1 HW request is UART7_RX */
|
||||
#define HPDMA1_REQUEST_UART7_TX 16U /*!< HPDMA1 HW request is UART7_TX */
|
||||
#define HPDMA1_REQUEST_LPTIM2_IC1 17U /*!< HPDMA1 HW request is LPTIM2_IC1 */
|
||||
#define HPDMA1_REQUEST_LPTIM2_IC2 18U /*!< HPDMA1 HW request is LPTIM2_IC2 */
|
||||
#define HPDMA1_REQUEST_LPTIM2_UE 19U /*!< HPDMA1 HW request is LPTIM2_UE */
|
||||
|
||||
/* GPDMA1 requests */
|
||||
#define GPDMA1_REQUEST_ADC1 0U /*!< GPDMA1 HW request is ADC1 */
|
||||
#define GPDMA1_REQUEST_ADC2 1U /*!< GPDMA1 HW request is ADC2 */
|
||||
#define GPDMA1_REQUEST_CRYP_IN 2U /*!< GPDMA1 HW request is CRYP_IN */
|
||||
#define GPDMA1_REQUEST_CRYP_OUT 3U /*!< GPDMA1 HW request is CRYP_OUT */
|
||||
#define GPDMA1_REQUEST_SAES_IN 4U /*!< GPDMA1 HW request is SAES_IN */
|
||||
#define GPDMA1_REQUEST_SAES_OUT 5U /*!< GPDMA1 HW request is SAES_OUT */
|
||||
#define GPDMA1_REQUEST_HASH_IN 6U /*!< GPDMA1 HW request is HASH_IN */
|
||||
#define GPDMA1_REQUEST_TIM1_CH1 7U /*!< GPDMA1 HW request is TIM1_CH1 */
|
||||
#define GPDMA1_REQUEST_TIM1_CH2 8U /*!< GPDMA1 HW request is TIM1_CH2 */
|
||||
#define GPDMA1_REQUEST_TIM1_CH3 9U /*!< GPDMA1 HW request is TIM1_CH3 */
|
||||
#define GPDMA1_REQUEST_TIM1_CH4 10U /*!< GPDMA1 HW request is TIM1_CH4 */
|
||||
#define GPDMA1_REQUEST_TIM1_UP 11U /*!< GPDMA1 HW request is TIM1_UP */
|
||||
#define GPDMA1_REQUEST_TIM1_TRIG 12U /*!< GPDMA1 HW request is TIM1_TRIG */
|
||||
#define GPDMA1_REQUEST_TIM1_COM 13U /*!< GPDMA1 HW request is TIM1_COM */
|
||||
#define GPDMA1_REQUEST_TIM2_CH1 14U /*!< GPDMA1 HW request is TIM2_CH1 */
|
||||
#define GPDMA1_REQUEST_TIM2_CH2 15U /*!< GPDMA1 HW request is TIM2_CH2 */
|
||||
#define GPDMA1_REQUEST_TIM2_CH3 16U /*!< GPDMA1 HW request is TIM2_CH3 */
|
||||
#define GPDMA1_REQUEST_TIM2_CH4 17U /*!< GPDMA1 HW request is TIM2_CH4 */
|
||||
#define GPDMA1_REQUEST_TIM2_UP 18U /*!< GPDMA1 HW request is TIM2_UP */
|
||||
#define GPDMA1_REQUEST_TIM2_TRIG 19U /*!< GPDMA1 HW request is TIM2_TRIG */
|
||||
#define GPDMA1_REQUEST_TIM3_CH1 20U /*!< GPDMA1 HW request is TIM3_CH1 */
|
||||
#define GPDMA1_REQUEST_TIM3_CH2 21U /*!< GPDMA1 HW request is TIM3_CH2 */
|
||||
#define GPDMA1_REQUEST_TIM3_CH3 22U /*!< GPDMA1 HW request is TIM3_CH3 */
|
||||
#define GPDMA1_REQUEST_TIM3_CH4 23U /*!< GPDMA1 HW request is TIM3_CH4 */
|
||||
#define GPDMA1_REQUEST_TIM3_UP 24U /*!< GPDMA1 HW request is TIM3_UP */
|
||||
#define GPDMA1_REQUEST_TIM3_TRIG 25U /*!< GPDMA1 HW request is TIM3_TRIG */
|
||||
#define GPDMA1_REQUEST_TIM4_CH1 26U /*!< GPDMA1 HW request is TIM4_CH1 */
|
||||
#define GPDMA1_REQUEST_TIM4_CH2 27U /*!< GPDMA1 HW request is TIM4_CH2 */
|
||||
#define GPDMA1_REQUEST_TIM4_CH3 28U /*!< GPDMA1 HW request is TIM4_CH3 */
|
||||
#define GPDMA1_REQUEST_TIM4_CH4 29U /*!< GPDMA1 HW request is TIM4_CH4 */
|
||||
#define GPDMA1_REQUEST_TIM4_UP 30U /*!< GPDMA1 HW request is TIM4_UP */
|
||||
#define GPDMA1_REQUEST_TIM4_TRIG 31U /*!< GPDMA1 HW request is TIM4_TRIG */
|
||||
#define GPDMA1_REQUEST_TIM5_CH1 32U /*!< GPDMA1 HW request is TIM5_CH1 */
|
||||
#define GPDMA1_REQUEST_TIM5_CH2 33U /*!< GPDMA1 HW request is TIM5_CH2 */
|
||||
#define GPDMA1_REQUEST_TIM5_CH3 34U /*!< GPDMA1 HW request is TIM5_CH3 */
|
||||
#define GPDMA1_REQUEST_TIM5_CH4 35U /*!< GPDMA1 HW request is TIM5_CH4 */
|
||||
#define GPDMA1_REQUEST_TIM5_UP 36U /*!< GPDMA1 HW request is TIM5_UP */
|
||||
#define GPDMA1_REQUEST_TIM5_TRIG 37U /*!< GPDMA1 HW request is TIM5_TRIG */
|
||||
#define GPDMA1_REQUEST_TIM6_UP 38U /*!< GPDMA1 HW request is TIM6_UP */
|
||||
#define GPDMA1_REQUEST_TIM7_UP 39U /*!< GPDMA1 HW request is TIM7_UP */
|
||||
#define GPDMA1_REQUEST_TIM15_CH1 40U /*!< GPDMA1 HW request is TIM15_CH1 */
|
||||
#define GPDMA1_REQUEST_TIM15_CH2 41U /*!< GPDMA1 HW request is TIM15_CH2 */
|
||||
#define GPDMA1_REQUEST_TIM15_UP 42U /*!< GPDMA1 HW request is TIM15_UP */
|
||||
#define GPDMA1_REQUEST_TIM15_TRIG 43U /*!< GPDMA1 HW request is TIM15_TRIG */
|
||||
#define GPDMA1_REQUEST_TIM15_COM 44U /*!< GPDMA1 HW request is TIM15_COM */
|
||||
#define GPDMA1_REQUEST_TIM16_CH1 45U /*!< GPDMA1 HW request is TIM16_CH1 */
|
||||
#define GPDMA1_REQUEST_TIM16_UP 46U /*!< GPDMA1 HW request is TIM16_UP */
|
||||
#define GPDMA1_REQUEST_TIM16_COM 47U /*!< GPDMA1 HW request is TIM16_COM */
|
||||
#define GPDMA1_REQUEST_TIM17_CH1 48U /*!< GPDMA1 HW request is TIM17_CH1 */
|
||||
#define GPDMA1_REQUEST_TIM17_UP 49U /*!< GPDMA1 HW request is TIM17_UP */
|
||||
#define GPDMA1_REQUEST_TIM17_COM 50U /*!< GPDMA1 HW request is TIM17_COM */
|
||||
#define GPDMA1_REQUEST_SPI1_RX 51U /*!< GPDMA1 HW request is SPI1_RX */
|
||||
#define GPDMA1_REQUEST_SPI1_TX 52U /*!< GPDMA1 HW request is SPI1_TX */
|
||||
#define GPDMA1_REQUEST_SPI2_RX 53U /*!< GPDMA1 HW request is SPI2_RX */
|
||||
#define GPDMA1_REQUEST_SPI2_TX 54U /*!< GPDMA1 HW request is SPI2_TX */
|
||||
#define GPDMA1_REQUEST_SPI3_RX 55U /*!< GPDMA1 HW request is SPI3_RX */
|
||||
#define GPDMA1_REQUEST_SPI3_TX 56U /*!< GPDMA1 HW request is SPI3_TX */
|
||||
#define GPDMA1_REQUEST_SPI4_RX 57U /*!< GPDMA1 HW request is SPI4_RX */
|
||||
#define GPDMA1_REQUEST_SPI4_TX 58U /*!< GPDMA1 HW request is SPI4_TX */
|
||||
#define GPDMA1_REQUEST_SPI5_RX 59U /*!< GPDMA1 HW request is SPI5_RX */
|
||||
#define GPDMA1_REQUEST_SPI5_TX 60U /*!< GPDMA1 HW request is SPI5_TX */
|
||||
#define GPDMA1_REQUEST_SPI6_RX 61U /*!< GPDMA1 HW request is SPI6_RX */
|
||||
#define GPDMA1_REQUEST_SPI6_TX 62U /*!< GPDMA1 HW request is SPI6_TX */
|
||||
#define GPDMA1_REQUEST_SAI1_A 63U /*!< GPDMA1 HW request is SAI1_A */
|
||||
#define GPDMA1_REQUEST_SAI1_B 64U /*!< GPDMA1 HW request is SAI1_B */
|
||||
#define GPDMA1_REQUEST_SAI2_A 65U /*!< GPDMA1 HW request is SAI2_A */
|
||||
#define GPDMA1_REQUEST_SAI2_B 66U /*!< GPDMA1 HW request is SAI2_B */
|
||||
#define GPDMA1_REQUEST_I2C1_RX 67U /*!< GPDMA1 HW request is I2C1_RX */
|
||||
#define GPDMA1_REQUEST_I2C1_TX 68U /*!< GPDMA1 HW request is I2C1_TX */
|
||||
#define GPDMA1_REQUEST_I2C2_RX 69U /*!< GPDMA1 HW request is I2C2_RX */
|
||||
#define GPDMA1_REQUEST_I2C2_TX 70U /*!< GPDMA1 HW request is I2C2_TX */
|
||||
#define GPDMA1_REQUEST_I2C3_RX 71U /*!< GPDMA1 HW request is I2C3_RX */
|
||||
#define GPDMA1_REQUEST_I2C3_TX 72U /*!< GPDMA1 HW request is I2C3_TX */
|
||||
#define GPDMA1_REQUEST_USART1_RX 73U /*!< GPDMA1 HW request is USART1_RX */
|
||||
#define GPDMA1_REQUEST_USART1_TX 74U /*!< GPDMA1 HW request is USART1_TX */
|
||||
#define GPDMA1_REQUEST_USART2_RX 75U /*!< GPDMA1 HW request is USART2_RX */
|
||||
#define GPDMA1_REQUEST_USART2_TX 76U /*!< GPDMA1 HW request is USART2_TX */
|
||||
#define GPDMA1_REQUEST_USART3_RX 77U /*!< GPDMA1 HW request is USART3_RX */
|
||||
#define GPDMA1_REQUEST_USART3_TX 78U /*!< GPDMA1 HW request is USART3_TX */
|
||||
#define GPDMA1_REQUEST_UART4_RX 79U /*!< GPDMA1 HW request is UART4_RX */
|
||||
#define GPDMA1_REQUEST_UART4_TX 80U /*!< GPDMA1 HW request is UART4_TX */
|
||||
#define GPDMA1_REQUEST_UART5_RX 81U /*!< GPDMA1 HW request is UART5_RX */
|
||||
#define GPDMA1_REQUEST_UART5_TX 82U /*!< GPDMA1 HW request is UART5_TX */
|
||||
#define GPDMA1_REQUEST_UART7_RX 83U /*!< GPDMA1 HW request is UART7_RX */
|
||||
#define GPDMA1_REQUEST_UART7_TX 84U /*!< GPDMA1 HW request is UART7_TX */
|
||||
#define GPDMA1_REQUEST_UART8_RX 85U /*!< GPDMA1 HW request is UART8_RX */
|
||||
#define GPDMA1_REQUEST_UART8_TX 86U /*!< GPDMA1 HW request is UART8_TX */
|
||||
#define GPDMA1_REQUEST_CORDIC_READ 87U /*!< GPDMA1 HW request is CORDIC_READ */
|
||||
#define GPDMA1_REQUEST_CORDIC_WRITE 88U /*!< GPDMA1 HW request is CORDIC_WRITE */
|
||||
#define GPDMA1_REQUEST_LPTIM1_IC1 89U /*!< GPDMA1 HW request is LPTIM1_IC1 */
|
||||
#define GPDMA1_REQUEST_LPTIM1_IC2 90U /*!< GPDMA1 HW request is LPTIM1_IC2 */
|
||||
#define GPDMA1_REQUEST_LPTIM1_UE 91U /*!< GPDMA1 HW request is LPTIM1_UE */
|
||||
#define GPDMA1_REQUEST_LPTIM2_IC1 92U /*!< GPDMA1 HW request is LPTIM2_IC1 */
|
||||
#define GPDMA1_REQUEST_LPTIM2_IC2 93U /*!< GPDMA1 HW request is LPTIM2_IC2 */
|
||||
#define GPDMA1_REQUEST_LPTIM2_UE 94U /*!< GPDMA1 HW request is LPTIM2_UE */
|
||||
#define GPDMA1_REQUEST_SPDIF_RX_DT 95U /*!< GPDMA1 HW request is SPDIF_RX_DT */
|
||||
#define GPDMA1_REQUEST_SPDIF_RX_CS 96U /*!< GPDMA1 HW request is SPDIF_RX_CS */
|
||||
#define GPDMA1_REQUEST_ADF1_FLT0 97U /*!< GPDMA1 HW request is ADF1_FLT0 */
|
||||
#define GPDMA1_REQUEST_UCPD1_TX 98U /*!< GPDMA1 HW request is UCPD1_TX */
|
||||
#define GPDMA1_REQUEST_UCPD1_RX 99U /*!< GPDMA1 HW request is UCPD1_RX */
|
||||
#define GPDMA1_REQUEST_PSSI 100U /*!< GPDMA1 HW request is PSSI */
|
||||
#define GPDMA1_REQUEST_LPUART1_RX 101U /*!< GPDMA1 HW request is LPUART1_RX */
|
||||
#define GPDMA1_REQUEST_LPUART1_TX 102U /*!< GPDMA1 HW request is LPUART1_TX */
|
||||
#define GPDMA1_REQUEST_LPTIM3_IC1 103U /*!< GPDMA1 HW request is LPTIM3_IC1 */
|
||||
#define GPDMA1_REQUEST_LPTIM3_IC2 104U /*!< GPDMA1 HW request is LPTIM3_IC2 */
|
||||
#define GPDMA1_REQUEST_LPTIM3_UE 105U /*!< GPDMA1 HW request is LPTIM3_UE */
|
||||
#define GPDMA1_REQUEST_I3C1_RX 106U /*!< GPDMA1 HW request is I3C1_RX */
|
||||
#define GPDMA1_REQUEST_I3C1_TX 107U /*!< GPDMA1 HW request is I3C1_TX */
|
||||
#define GPDMA1_REQUEST_I3C1_TC 108U /*!< GPDMA1 HW request is I3C1_TC */
|
||||
#define GPDMA1_REQUEST_I3C1_RS 109U /*!< GPDMA1 HW request is I3C1_RS */
|
||||
|
||||
#define GPDMA1_MAX_REQUEST 109U
|
||||
|
||||
/* Software request */
|
||||
#define DMA_REQUEST_SW DMA_CTR2_SWREQ /*!< DMA SW request */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Block_Request DMA Block Request
|
||||
* @brief DMA Block Request
|
||||
* @{
|
||||
*/
|
||||
#define DMA_BREQ_SINGLE_BURST 0x00000000U /*!< Hardware request protocol at a single / burst level */
|
||||
#define DMA_BREQ_BLOCK DMA_CTR2_BREQ /*!< Hardware request protocol at a block level */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Transfer_Direction DMA Transfer Direction
|
||||
* @brief DMA transfer direction
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
|
||||
#define DMA_MEMORY_TO_PERIPH DMA_CTR2_DREQ /*!< Memory to peripheral direction */
|
||||
#define DMA_MEMORY_TO_MEMORY DMA_CTR2_SWREQ /*!< Memory to memory direction */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Source_Increment_Mode DMA Source Increment Mode
|
||||
* @brief DMA Source Increment Mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_SINC_FIXED 0x00000000U /*!< Source fixed single / burst */
|
||||
#define DMA_SINC_INCREMENTED DMA_CTR1_SINC /*!< Source incremented single / burst */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Destination_Increment_Mode DMA Destination Increment Mode
|
||||
* @brief DMA Destination Increment Mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_DINC_FIXED 0x00000000U /*!< Destination fixed single / burst */
|
||||
#define DMA_DINC_INCREMENTED DMA_CTR1_DINC /*!< Destination incremented single / burst */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Source_Data_Width DMA Source Data Width
|
||||
* @brief DMA Source Data Width
|
||||
* @{
|
||||
*/
|
||||
#define DMA_SRC_DATAWIDTH_BYTE 0x00000000U /*!< Source data width : Byte */
|
||||
#define DMA_SRC_DATAWIDTH_HALFWORD DMA_CTR1_SDW_LOG2_0 /*!< Source data width : HalfWord */
|
||||
#define DMA_SRC_DATAWIDTH_WORD DMA_CTR1_SDW_LOG2_1 /*!< Source data width : Word */
|
||||
#define DMA_SRC_DATAWIDTH_DOUBLEWORD DMA_CTR1_SDW_LOG2 /*!< Source data width : DoubleWord */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Destination_Data_Width DMA destination Data Width
|
||||
* @brief DMA destination Data Width
|
||||
* @{
|
||||
*/
|
||||
#define DMA_DEST_DATAWIDTH_BYTE 0x00000000U /*!< Destination data width : Byte */
|
||||
#define DMA_DEST_DATAWIDTH_HALFWORD DMA_CTR1_DDW_LOG2_0 /*!< Destination data width : HalfWord */
|
||||
#define DMA_DEST_DATAWIDTH_WORD DMA_CTR1_DDW_LOG2_1 /*!< Destination data width : Word */
|
||||
#define DMA_DEST_DATAWIDTH_DOUBLEWORD DMA_CTR1_DDW_LOG2 /*!< Destination data width : DoubleWord */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Priority_Level DMA Priority Level
|
||||
* @brief DMA Priority Level
|
||||
* @{
|
||||
*/
|
||||
#define DMA_LOW_PRIORITY_LOW_WEIGHT 0x00000000U /*!< Priority level : Low Priority, Low weight */
|
||||
#define DMA_LOW_PRIORITY_MID_WEIGHT DMA_CCR_PRIO_0 /*!< Priority level : Low Priority, Mid weight */
|
||||
#define DMA_LOW_PRIORITY_HIGH_WEIGHT DMA_CCR_PRIO_1 /*!< Priority level : Low Priority, High weight */
|
||||
#define DMA_HIGH_PRIORITY DMA_CCR_PRIO /*!< Priority level : HIGH Priority */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Transfer_Allocated_Port DMA Transfer Allocated Port
|
||||
* @brief DMA Transfer Allocated Port
|
||||
* @{
|
||||
*/
|
||||
#define DMA_SRC_ALLOCATED_PORT0 0x00000000U /*!< Source allocated Port 0 */
|
||||
#define DMA_SRC_ALLOCATED_PORT1 DMA_CTR1_SAP /*!< Source allocated Port 1 */
|
||||
#define DMA_DEST_ALLOCATED_PORT0 0x00000000U /*!< Destination allocated Port 0 */
|
||||
#define DMA_DEST_ALLOCATED_PORT1 DMA_CTR1_DAP /*!< Destination allocated Port 1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Transfer_Event_Mode DMA Transfer Event Mode
|
||||
* @brief DMA Transfer Event Mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_TCEM_BLOCK_TRANSFER 0x00000000U /*!< The TC event is generated at the end of each block and the
|
||||
HT event is generated at the half of each block */
|
||||
#define DMA_TCEM_REPEATED_BLOCK_TRANSFER DMA_CTR2_TCEM_0 /*!< The TC event is generated at the end of the repeated block
|
||||
and the HT event is generated at the half of the repeated
|
||||
block */
|
||||
#define DMA_TCEM_EACH_LL_ITEM_TRANSFER DMA_CTR2_TCEM_1 /*!< The TC event is generated at the end of each linked-list
|
||||
item and the HT event is generated at the half of each
|
||||
linked-list item */
|
||||
#define DMA_TCEM_LAST_LL_ITEM_TRANSFER DMA_CTR2_TCEM /*!< The TC event is generated at the end of the last
|
||||
linked-list item and the HT event is generated at the half
|
||||
of the last linked-list item */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Transfer_Mode DMA Transfer Mode
|
||||
* @brief DMA Transfer Mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_NORMAL (0x00U) /*!< Normal DMA transfer */
|
||||
#define DMA_PFCTRL DMA_CTR2_PFREQ /*!< HW request peripheral flow control mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Channel_Attributes DMA Channel Attributes
|
||||
* @brief DMA Channel Privilege Attribute
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
#define DMA_CHANNEL_PRIV (DMA_CHANNEL_ATTR_PRIV_MASK | (1U<<DMA_CHANNEL_PRIV_VAL_POS)) /*!< Channel is privileged */
|
||||
#define DMA_CHANNEL_NPRIV (DMA_CHANNEL_ATTR_PRIV_MASK) /*!< Channel is unprivileged */
|
||||
|
||||
#define DMA_CHANNEL_ATTRIBUTE_UNLOCKED (0x00U) /*!< Channel attribute is unlocked */
|
||||
#define DMA_CHANNEL_ATTRIBUTE_LOCKED (0x01U) /*!< Channel attribute is locked */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported macro ----------------------------------------------------------------------------------------------------*/
|
||||
/** @defgroup DMA_Exported_Macros DMA Exported Macros
|
||||
* @brief DMA Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset DMA handle state.
|
||||
* @param __HANDLE__ : DMA handle.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) \
|
||||
((__HANDLE__)->State = HAL_DMA_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @brief Enable the specified DMA Channel.
|
||||
* @param __HANDLE__ : DMA handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_ENABLE(__HANDLE__) \
|
||||
((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
|
||||
|
||||
/**
|
||||
* @brief Disable the specified DMA Channel.
|
||||
* @param __HANDLE__ : DMA handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_DISABLE(__HANDLE__) \
|
||||
((__HANDLE__)->Instance->CCR |= (DMA_CCR_SUSP | DMA_CCR_RESET))
|
||||
|
||||
/**
|
||||
* @brief Get the DMA channel pending flags.
|
||||
* @param __HANDLE__ : DMA handle.
|
||||
* @param __FLAG__ : Get the specified flag.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_FLAG_TC : Transfer Complete flag.
|
||||
* @arg DMA_FLAG_HT : Half Transfer Complete flag.
|
||||
* @arg DMA_FLAG_DTE : Data Transfer Error flag.
|
||||
* @arg DMA_FLAG_ULE : Update linked-list Error flag.
|
||||
* @arg DMA_FLAG_USE : User Setting Error flag.
|
||||
* @arg DMA_FLAG_TO : Trigger Overrun flag.
|
||||
* @arg DMA_FLAG_SUSP : Completed Suspension flag.
|
||||
* @arg DMA_FLAG_IDLEF : Idle flag.
|
||||
* @retval The state of FLAG (SET or RESET).
|
||||
*/
|
||||
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) \
|
||||
((__HANDLE__)->Instance->CSR & (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Clear the DMA Channel pending flags.
|
||||
* @param __HANDLE__ : DMA handle.
|
||||
* @param __FLAG__ : Specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_FLAG_TC : Transfer Complete flag.
|
||||
* @arg DMA_FLAG_HT : Half Transfer Complete flag.
|
||||
* @arg DMA_FLAG_DTE : Data Transfer Error flag.
|
||||
* @arg DMA_FLAG_ULE : Update Linked-List Error flag.
|
||||
* @arg DMA_FLAG_USE : User Setting Error flag.
|
||||
* @arg DMA_FLAG_TO : Trigger Overrun flag.
|
||||
* @arg DMA_FLAG_SUSP : Completed Suspension flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
|
||||
((__HANDLE__)->Instance->CFCR = (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Enable the specified DMA Channel interrupts.
|
||||
* @param __HANDLE__ : DMA handle.
|
||||
* @param __INTERRUPT__ : Specifies the DMA interrupt sources to be enabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_IT_TC : Transfer Complete interrupt.
|
||||
* @arg DMA_IT_HT : Half Transfer Complete interrupt.
|
||||
* @arg DMA_IT_DTE : Data Transfer Error interrupt.
|
||||
* @arg DMA_IT_ULE : Update Linked-List Error interrupt.
|
||||
* @arg DMA_IT_USE : User Setting Error interrupt.
|
||||
* @arg DMA_IT_TO : Trigger Overrun interrupt.
|
||||
* @arg DMA_IT_SUSP : Completed Suspension interrupt.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
|
||||
((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the specified DMA Channel interrupts.
|
||||
* @param __HANDLE__ : DMA handle.
|
||||
* @param __INTERRUPT__ : specifies the DMA interrupt sources to be disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_IT_TC : Transfer Complete interrupt.
|
||||
* @arg DMA_IT_HT : Half Transfer Complete interrupt.
|
||||
* @arg DMA_IT_DTE : Data Transfer Error interrupt.
|
||||
* @arg DMA_IT_ULE : Update Linked-List Error interrupt.
|
||||
* @arg DMA_IT_USE : User Setting Error interrupt.
|
||||
* @arg DMA_IT_TO : Trigger Overrun interrupt.
|
||||
* @arg DMA_IT_SUSP : Completed Suspension interrupt.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
|
||||
((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified DMA Channel interrupt is enabled or not.
|
||||
* @param __HANDLE__ : DMA handle.
|
||||
* @param __INTERRUPT__ : specifies the DMA interrupt source to check.
|
||||
* @arg DMA_IT_TC : Transfer Complete interrupt.
|
||||
* @arg DMA_IT_HT : Half Transfer Complete interrupt.
|
||||
* @arg DMA_IT_DTE : Data Transfer Error interrupt.
|
||||
* @arg DMA_IT_ULE : Update Linked-List Error interrupt.
|
||||
* @arg DMA_IT_USE : User Setting Error interrupt.
|
||||
* @arg DMA_IT_TO : Trigger Overrun interrupt.
|
||||
* @arg DMA_IT_SUSP : Completed Suspension interrupt.
|
||||
* @retval The state of DMA_IT (SET or RESET).
|
||||
*/
|
||||
#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
|
||||
(((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
|
||||
|
||||
/**
|
||||
* @brief Writes the block number of bytes to be transferred from the source on the DMA Channel.
|
||||
* @param __HANDLE__ : DMA handle.
|
||||
* @param __COUNTER__ : Number of data bytes to be transferred from the source (from 0 to 65535).
|
||||
*/
|
||||
#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) \
|
||||
MODIFY_REG((__HANDLE__)->Instance->CBR1, DMA_CBR1_BNDT, (__COUNTER__))
|
||||
|
||||
/**
|
||||
* @brief Returns the number of remaining data bytes in the current DMA Channel transfer.
|
||||
* @param __HANDLE__ : DMA handle.
|
||||
* @retval The number of remaining data units in the current DMA Stream transfer.
|
||||
*/
|
||||
#define __HAL_DMA_GET_COUNTER(__HANDLE__) \
|
||||
(((__HANDLE__)->Instance->CBR1) & DMA_CBR1_BNDT)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Include DMA HAL Extension module */
|
||||
#include "stm32h7rsxx_hal_dma_ex.h"
|
||||
|
||||
|
||||
/* Exported functions ------------------------------------------------------------------------------------------------*/
|
||||
/** @defgroup DMA_Exported_Functions DMA Exported Functions
|
||||
* @brief DMA Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Exported_Functions_Group1 Initialization and De-Initialization Functions
|
||||
* @brief Initialization and De-Initialization Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *const hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *const hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Exported_Functions_Group2 I/O Operation Functions
|
||||
* @brief I/O Operation Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *const hdma,
|
||||
uint32_t SrcAddress,
|
||||
uint32_t DstAddress,
|
||||
uint32_t SrcDataSize);
|
||||
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *const hdma,
|
||||
uint32_t SrcAddress,
|
||||
uint32_t DstAddress,
|
||||
uint32_t SrcDataSize);
|
||||
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *const hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *const hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *const hdma,
|
||||
HAL_DMA_LevelCompleteTypeDef CompleteLevel,
|
||||
uint32_t Timeout);
|
||||
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *const hdma,
|
||||
HAL_DMA_CallbackIDTypeDef CallbackID,
|
||||
void (*const pCallback)(DMA_HandleTypeDef *const _hdma));
|
||||
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *const hdma,
|
||||
HAL_DMA_CallbackIDTypeDef CallbackID);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Exported_Functions_Group3 State and Error Functions
|
||||
* @brief State and Error Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef const *const hdma);
|
||||
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef const *const hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Exported_Functions_Group4 DMA Attributes Functions
|
||||
* @brief DMA Attributes Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *const hdma,
|
||||
uint32_t ChannelAttributes);
|
||||
HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *const hdma,
|
||||
uint32_t *const pChannelAttributes);
|
||||
|
||||
HAL_StatusTypeDef HAL_DMA_LockChannelAttributes(DMA_HandleTypeDef const *const hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *const hdma,
|
||||
uint32_t *const pLockState);
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private constants -------------------------------------------------------------------------------------------------*/
|
||||
/** @defgroup DMA_Private_Constants DMA Private Constants
|
||||
* @brief DMA Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define HAL_TIMEOUT_DMA_ABORT (0x00000005U) /* DMA channel abort timeout 5 milli-second */
|
||||
#define HAL_DMA_CHANNEL_START (0x00000050U) /* DMA channel offset */
|
||||
#define HAL_DMA_CHANNEL_SIZE (0x00000080U) /* DMA channel size */
|
||||
#define HAL_DMA_OFFSET_MASK (0x00000FFFU) /* DMA channel offset mask */
|
||||
#define DMA_CHANNEL_ATTR_PRIV_MASK (0x01000000U) /* DMA channel privilege */
|
||||
#define DMA_CHANNEL_PRIV_VAL_POS 0U
|
||||
#define DMA_CHANNEL_BURST_MIN (0x00000001U) /* DMA channel minimum burst size */
|
||||
#define DMA_CHANNEL_BURST_MAX (0x00000040U) /* DMA channel maximum burst size */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private macros ----------------------------------------------------------------------------------------------------*/
|
||||
/** @defgroup DMA_Private_Macros DMA Private Macros
|
||||
* @brief DMA Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define GET_DMA_INSTANCE(__HANDLE__) \
|
||||
((DMA_TypeDef *)((uint32_t)((__HANDLE__)->Instance) & (~HAL_DMA_OFFSET_MASK)))
|
||||
|
||||
#define GET_DMA_CHANNEL(__HANDLE__) \
|
||||
((((uint32_t)((__HANDLE__)->Instance) & HAL_DMA_OFFSET_MASK) - HAL_DMA_CHANNEL_START) / HAL_DMA_CHANNEL_SIZE)
|
||||
|
||||
#define IS_DMA_MODE(MODE) \
|
||||
(((MODE) == DMA_NORMAL) || \
|
||||
((MODE) == DMA_PFCTRL))
|
||||
|
||||
#define IS_DMA_DIRECTION(DIRECTION) \
|
||||
(((DIRECTION) == DMA_PERIPH_TO_MEMORY) || \
|
||||
((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
|
||||
((DIRECTION) == DMA_MEMORY_TO_MEMORY))
|
||||
|
||||
#define IS_DMA_LEVEL_COMPLETE(LEVEL) \
|
||||
(((LEVEL) == HAL_DMA_FULL_TRANSFER) || \
|
||||
((LEVEL) == HAL_DMA_HALF_TRANSFER))
|
||||
|
||||
#define IS_DMA_SOURCE_INC(INC) \
|
||||
(((INC) == DMA_SINC_FIXED) || \
|
||||
((INC) == DMA_SINC_INCREMENTED))
|
||||
|
||||
#define IS_DMA_DESTINATION_INC(INC) \
|
||||
(((INC) == DMA_DINC_FIXED) || \
|
||||
((INC) == DMA_DINC_INCREMENTED))
|
||||
|
||||
#define IS_DMA_SOURCE_DATA_WIDTH(WIDTH) \
|
||||
(((WIDTH) == DMA_SRC_DATAWIDTH_BYTE) || \
|
||||
((WIDTH) == DMA_SRC_DATAWIDTH_HALFWORD) || \
|
||||
((WIDTH) == DMA_SRC_DATAWIDTH_WORD) || \
|
||||
((WIDTH) == DMA_SRC_DATAWIDTH_DOUBLEWORD))
|
||||
|
||||
#define IS_DMA_DESTINATION_DATA_WIDTH(WIDTH) \
|
||||
(((WIDTH) == DMA_DEST_DATAWIDTH_BYTE) || \
|
||||
((WIDTH) == DMA_DEST_DATAWIDTH_HALFWORD) || \
|
||||
((WIDTH) == DMA_DEST_DATAWIDTH_WORD) || \
|
||||
((WIDTH) == DMA_DEST_DATAWIDTH_DOUBLEWORD))
|
||||
|
||||
#define IS_DMA_BURST_LENGTH(LENGTH) \
|
||||
(((LENGTH) >= DMA_CHANNEL_BURST_MIN) && \
|
||||
((LENGTH) <= DMA_CHANNEL_BURST_MAX))
|
||||
|
||||
#define IS_DMA_PRIORITY(PRIORITY) \
|
||||
(((PRIORITY) == DMA_LOW_PRIORITY_LOW_WEIGHT) || \
|
||||
((PRIORITY) == DMA_LOW_PRIORITY_MID_WEIGHT) || \
|
||||
((PRIORITY) == DMA_LOW_PRIORITY_HIGH_WEIGHT) || \
|
||||
((PRIORITY) == DMA_HIGH_PRIORITY))
|
||||
|
||||
#define IS_DMA_TRANSFER_ALLOCATED_PORT(ALLOCATED_PORT) \
|
||||
(((ALLOCATED_PORT) & (~(DMA_CTR1_SAP | DMA_CTR1_DAP))) == 0U)
|
||||
|
||||
#define IS_DMA_REQUEST(REQUEST) \
|
||||
(((REQUEST) == DMA_REQUEST_SW) || \
|
||||
((REQUEST) <= GPDMA1_REQUEST_I3C1_RS))
|
||||
|
||||
#define IS_DMA_BLOCK_HW_REQUEST(MODE) \
|
||||
(((MODE) == DMA_BREQ_SINGLE_BURST) || \
|
||||
((MODE) == DMA_BREQ_BLOCK))
|
||||
|
||||
#define IS_DMA_TCEM_EVENT_MODE(MODE) \
|
||||
(((MODE) == DMA_TCEM_BLOCK_TRANSFER) || \
|
||||
((MODE) == DMA_TCEM_REPEATED_BLOCK_TRANSFER) || \
|
||||
((MODE) == DMA_TCEM_EACH_LL_ITEM_TRANSFER) || \
|
||||
((MODE) == DMA_TCEM_LAST_LL_ITEM_TRANSFER))
|
||||
|
||||
#define IS_DMA_BLOCK_SIZE(SIZE) \
|
||||
(((SIZE) > 0U) && ((SIZE) <= DMA_CBR1_BNDT))
|
||||
|
||||
#define IS_DMA_GLOBAL_ACTIVE_FLAG(INSTANCE, GLOBAL_FLAG) \
|
||||
(((INSTANCE)->MISR & (GLOBAL_FLAG)))
|
||||
#define IS_DMA_ATTRIBUTES(ATTRIBUTE) \
|
||||
(((ATTRIBUTE) == DMA_CHANNEL_PRIV) || \
|
||||
((ATTRIBUTE) == DMA_CHANNEL_NPRIV))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private functions -------------------------------------------------------------------------------------------------*/
|
||||
/** @defgroup DMA_Private_Functions DMA Private Functions
|
||||
* @brief DMA Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7RSxx_HAL_DMA_H */
|
||||
|
|
@ -1,715 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7rsxx_hal_dma2d.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of DMA2D HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7RSxx_HAL_DMA2D_H
|
||||
#define STM32H7RSxx_HAL_DMA2D_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7rsxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H7RSxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (DMA2D)
|
||||
|
||||
/** @addtogroup DMA2D DMA2D
|
||||
* @brief DMA2D HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup DMA2D_Exported_Types DMA2D Exported Types
|
||||
* @{
|
||||
*/
|
||||
#define MAX_DMA2D_LAYER 2U /*!< DMA2D maximum number of layers */
|
||||
|
||||
/**
|
||||
* @brief DMA2D CLUT Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address.*/
|
||||
|
||||
uint32_t CLUTColorMode; /*!< Configures the DMA2D CLUT color mode.
|
||||
This parameter can be one value of @ref DMA2D_CLUT_CM. */
|
||||
|
||||
uint32_t Size; /*!< Configures the DMA2D CLUT size.
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/
|
||||
} DMA2D_CLUTCfgTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DMA2D Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Mode; /*!< Configures the DMA2D transfer mode.
|
||||
This parameter can be one value of @ref DMA2D_Mode. */
|
||||
|
||||
uint32_t ColorMode; /*!< Configures the color format of the output image.
|
||||
This parameter can be one value of @ref DMA2D_Output_Color_Mode. */
|
||||
|
||||
uint32_t OutputOffset; /*!< Specifies the Offset value.
|
||||
This parameter must be a number between
|
||||
Min_Data = 0x0000 and Max_Data = 0x3FFF. */
|
||||
uint32_t AlphaInverted; /*!< Select regular or inverted alpha value for the output pixel format converter.
|
||||
This parameter can be one value of @ref DMA2D_Alpha_Inverted. */
|
||||
|
||||
uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR)
|
||||
for the output pixel format converter.
|
||||
This parameter can be one value of @ref DMA2D_RB_Swap. */
|
||||
|
||||
|
||||
uint32_t BytesSwap; /*!< Select byte regular mode or bytes swap mode (two by two).
|
||||
This parameter can be one value of @ref DMA2D_Bytes_Swap. */
|
||||
|
||||
uint32_t LineOffsetMode; /*!< Configures how is expressed the line offset for the foreground, background and output.
|
||||
This parameter can be one value of @ref DMA2D_Line_Offset_Mode. */
|
||||
|
||||
} DMA2D_InitTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief DMA2D Layer structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t InputOffset; /*!< Configures the DMA2D foreground or background offset.
|
||||
This parameter must be a number between
|
||||
Min_Data = 0x0000 and Max_Data = 0x3FFF. */
|
||||
|
||||
uint32_t InputColorMode; /*!< Configures the DMA2D foreground or background color mode.
|
||||
This parameter can be one value of @ref DMA2D_Input_Color_Mode. */
|
||||
|
||||
uint32_t AlphaMode; /*!< Configures the DMA2D foreground or background alpha mode.
|
||||
This parameter can be one value of @ref DMA2D_Alpha_Mode. */
|
||||
|
||||
uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value
|
||||
in case of A8 or A4 color mode.
|
||||
This parameter must be a number between Min_Data = 0x00
|
||||
and Max_Data = 0xFF except for the color modes detailed below.
|
||||
@note In case of A8 or A4 color mode (ARGB),
|
||||
this parameter must be a number between
|
||||
Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where
|
||||
- InputAlpha[24:31] is the alpha value ALPHA[0:7]
|
||||
- InputAlpha[16:23] is the red value RED[0:7]
|
||||
- InputAlpha[8:15] is the green value GREEN[0:7]
|
||||
- InputAlpha[0:7] is the blue value BLUE[0:7]. */
|
||||
uint32_t AlphaInverted; /*!< Select regular or inverted alpha value.
|
||||
This parameter can be one value of @ref DMA2D_Alpha_Inverted. */
|
||||
|
||||
uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR).
|
||||
This parameter can be one value of @ref DMA2D_RB_Swap. */
|
||||
|
||||
uint32_t ChromaSubSampling; /*!< Configure the chroma sub-sampling mode for the YCbCr color mode
|
||||
This parameter can be one value of @ref DMA2D_Chroma_Sub_Sampling */
|
||||
|
||||
} DMA2D_LayerCfgTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DMA2D State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DMA2D_STATE_RESET = 0x00U, /*!< DMA2D not yet initialized or disabled */
|
||||
HAL_DMA2D_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
|
||||
HAL_DMA2D_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
|
||||
HAL_DMA2D_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
|
||||
HAL_DMA2D_STATE_ERROR = 0x04U, /*!< DMA2D state error */
|
||||
HAL_DMA2D_STATE_SUSPEND = 0x05U /*!< DMA2D process is suspended */
|
||||
} HAL_DMA2D_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DMA2D handle Structure definition
|
||||
*/
|
||||
typedef struct __DMA2D_HandleTypeDef
|
||||
{
|
||||
DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */
|
||||
|
||||
DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */
|
||||
|
||||
void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D transfer complete callback. */
|
||||
|
||||
void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D transfer error callback. */
|
||||
|
||||
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
|
||||
void (* LineEventCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D line event callback. */
|
||||
|
||||
void (* CLUTLoadingCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D CLUT loading completion callback */
|
||||
|
||||
void (* MspInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D Msp Init callback. */
|
||||
|
||||
void (* MspDeInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D Msp DeInit callback. */
|
||||
|
||||
#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
|
||||
|
||||
DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< DMA2D lock. */
|
||||
|
||||
__IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< DMA2D error code. */
|
||||
} DMA2D_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL DMA2D Callback pointer definition
|
||||
*/
|
||||
typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef *hdma2d); /*!< Pointer to a DMA2D common callback function */
|
||||
#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA2D_Error_Code DMA2D Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DMA2D_ERROR_NONE 0x00000000U /*!< No error */
|
||||
#define HAL_DMA2D_ERROR_TE 0x00000001U /*!< Transfer error */
|
||||
#define HAL_DMA2D_ERROR_CE 0x00000002U /*!< Configuration error */
|
||||
#define HAL_DMA2D_ERROR_CAE 0x00000004U /*!< CLUT access error */
|
||||
#define HAL_DMA2D_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
|
||||
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_DMA2D_ERROR_INVALID_CALLBACK 0x00000040U /*!< Invalid callback error */
|
||||
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA2D_Mode DMA2D Mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA2D_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */
|
||||
#define DMA2D_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */
|
||||
#define DMA2D_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */
|
||||
#define DMA2D_R2M (DMA2D_CR_MODE_1 | DMA2D_CR_MODE_0) /*!< DMA2D register to memory transfer mode */
|
||||
#define DMA2D_M2M_BLEND_FG DMA2D_CR_MODE_2 /*!< DMA2D memory to memory with blending transfer mode and fixed color FG */
|
||||
#define DMA2D_M2M_BLEND_BG (DMA2D_CR_MODE_2 | DMA2D_CR_MODE_0) /*!< DMA2D memory to memory with blending transfer mode and fixed color BG */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA2D_OUTPUT_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D color mode */
|
||||
#define DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 DMA2D color mode */
|
||||
#define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 DMA2D color mode */
|
||||
#define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */
|
||||
#define DMA2D_OUTPUT_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 DMA2D color mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA2D_INPUT_ARGB8888 0x00000000U /*!< ARGB8888 color mode */
|
||||
#define DMA2D_INPUT_RGB888 0x00000001U /*!< RGB888 color mode */
|
||||
#define DMA2D_INPUT_RGB565 0x00000002U /*!< RGB565 color mode */
|
||||
#define DMA2D_INPUT_ARGB1555 0x00000003U /*!< ARGB1555 color mode */
|
||||
#define DMA2D_INPUT_ARGB4444 0x00000004U /*!< ARGB4444 color mode */
|
||||
#define DMA2D_INPUT_L8 0x00000005U /*!< L8 color mode */
|
||||
#define DMA2D_INPUT_AL44 0x00000006U /*!< AL44 color mode */
|
||||
#define DMA2D_INPUT_AL88 0x00000007U /*!< AL88 color mode */
|
||||
#define DMA2D_INPUT_L4 0x00000008U /*!< L4 color mode */
|
||||
#define DMA2D_INPUT_A8 0x00000009U /*!< A8 color mode */
|
||||
#define DMA2D_INPUT_A4 0x0000000AU /*!< A4 color mode */
|
||||
#define DMA2D_INPUT_YCBCR 0x0000000BU /*!< YCbCr color mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA2D_NO_MODIF_ALPHA 0x00000000U /*!< No modification of the alpha channel value */
|
||||
#define DMA2D_REPLACE_ALPHA 0x00000001U /*!< Replace original alpha channel value by programmed alpha value */
|
||||
#define DMA2D_COMBINE_ALPHA 0x00000002U /*!< Replace original alpha channel value by programmed alpha value
|
||||
with original alpha channel value */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA2D_Alpha_Inverted DMA2D Alpha Inversion
|
||||
* @{
|
||||
*/
|
||||
#define DMA2D_REGULAR_ALPHA 0x00000000U /*!< No modification of the alpha channel value */
|
||||
#define DMA2D_INVERTED_ALPHA 0x00000001U /*!< Invert the alpha channel value */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA2D_RB_Swap DMA2D Red and Blue Swap
|
||||
* @{
|
||||
*/
|
||||
#define DMA2D_RB_REGULAR 0x00000000U /*!< Select regular mode (RGB or ARGB) */
|
||||
#define DMA2D_RB_SWAP 0x00000001U /*!< Select swap mode (BGR or ABGR) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** @defgroup DMA2D_Line_Offset_Mode DMA2D Line Offset Mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA2D_LOM_PIXELS 0x00000000U /*!< Line offsets expressed in pixels */
|
||||
#define DMA2D_LOM_BYTES DMA2D_CR_LOM /*!< Line offsets expressed in bytes */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA2D_Bytes_Swap DMA2D Bytes Swap
|
||||
* @{
|
||||
*/
|
||||
#define DMA2D_BYTES_REGULAR 0x00000000U /*!< Bytes in regular order in output FIFO */
|
||||
#define DMA2D_BYTES_SWAP DMA2D_OPFCCR_SB /*!< Bytes are swapped two by two in output FIFO */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA2D_Chroma_Sub_Sampling DMA2D Chroma Sub Sampling
|
||||
* @{
|
||||
*/
|
||||
#define DMA2D_NO_CSS 0x00000000U /*!< No chroma sub-sampling 4:4:4 */
|
||||
#define DMA2D_CSS_422 0x00000001U /*!< chroma sub-sampling 4:2:2 */
|
||||
#define DMA2D_CSS_420 0x00000002U /*!< chroma sub-sampling 4:2:0 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA2D_CCM_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D CLUT color mode */
|
||||
#define DMA2D_CCM_RGB888 0x00000001U /*!< RGB888 DMA2D CLUT color mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA2D_Interrupts DMA2D Interrupts
|
||||
* @{
|
||||
*/
|
||||
#define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */
|
||||
#define DMA2D_IT_CTC DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */
|
||||
#define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */
|
||||
#define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */
|
||||
#define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */
|
||||
#define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA2D_Flags DMA2D Flags
|
||||
* @{
|
||||
*/
|
||||
#define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */
|
||||
#define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */
|
||||
#define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */
|
||||
#define DMA2D_FLAG_TW DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */
|
||||
#define DMA2D_FLAG_TC DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */
|
||||
#define DMA2D_FLAG_TE DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL DMA2D common Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DMA2D_MSPINIT_CB_ID = 0x00U, /*!< DMA2D MspInit callback ID */
|
||||
HAL_DMA2D_MSPDEINIT_CB_ID = 0x01U, /*!< DMA2D MspDeInit callback ID */
|
||||
HAL_DMA2D_TRANSFERCOMPLETE_CB_ID = 0x02U, /*!< DMA2D transfer complete callback ID */
|
||||
HAL_DMA2D_TRANSFERERROR_CB_ID = 0x03U, /*!< DMA2D transfer error callback ID */
|
||||
HAL_DMA2D_LINEEVENT_CB_ID = 0x04U, /*!< DMA2D line event callback ID */
|
||||
HAL_DMA2D_CLUTLOADINGCPLT_CB_ID = 0x05U, /*!< DMA2D CLUT loading completion callback ID */
|
||||
} HAL_DMA2D_CallbackIDTypeDef;
|
||||
#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported macros ------------------------------------------------------------*/
|
||||
/** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset DMA2D handle state
|
||||
* @param __HANDLE__ specifies the DMA2D handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
}while(0)
|
||||
#else
|
||||
#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
|
||||
#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable the DMA2D.
|
||||
* @param __HANDLE__ DMA2D handle
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)
|
||||
|
||||
|
||||
/* Interrupt & Flag management */
|
||||
/**
|
||||
* @brief Get the DMA2D pending flags.
|
||||
* @param __HANDLE__ DMA2D handle
|
||||
* @param __FLAG__ flag to check.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA2D_FLAG_CE: Configuration error flag
|
||||
* @arg DMA2D_FLAG_CTC: CLUT transfer complete flag
|
||||
* @arg DMA2D_FLAG_CAE: CLUT access error flag
|
||||
* @arg DMA2D_FLAG_TW: Transfer Watermark flag
|
||||
* @arg DMA2D_FLAG_TC: Transfer complete flag
|
||||
* @arg DMA2D_FLAG_TE: Transfer error flag
|
||||
* @retval The state of FLAG.
|
||||
*/
|
||||
#define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Clear the DMA2D pending flags.
|
||||
* @param __HANDLE__ DMA2D handle
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA2D_FLAG_CE: Configuration error flag
|
||||
* @arg DMA2D_FLAG_CTC: CLUT transfer complete flag
|
||||
* @arg DMA2D_FLAG_CAE: CLUT access error flag
|
||||
* @arg DMA2D_FLAG_TW: Transfer Watermark flag
|
||||
* @arg DMA2D_FLAG_TC: Transfer complete flag
|
||||
* @arg DMA2D_FLAG_TE: Transfer error flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Enable the specified DMA2D interrupts.
|
||||
* @param __HANDLE__ DMA2D handle
|
||||
* @param __INTERRUPT__ specifies the DMA2D interrupt sources to be enabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA2D_IT_CE: Configuration error interrupt mask
|
||||
* @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
|
||||
* @arg DMA2D_IT_CAE: CLUT access error interrupt mask
|
||||
* @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
|
||||
* @arg DMA2D_IT_TC: Transfer complete interrupt mask
|
||||
* @arg DMA2D_IT_TE: Transfer error interrupt mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the specified DMA2D interrupts.
|
||||
* @param __HANDLE__ DMA2D handle
|
||||
* @param __INTERRUPT__ specifies the DMA2D interrupt sources to be disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA2D_IT_CE: Configuration error interrupt mask
|
||||
* @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
|
||||
* @arg DMA2D_IT_CAE: CLUT access error interrupt mask
|
||||
* @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
|
||||
* @arg DMA2D_IT_TC: Transfer complete interrupt mask
|
||||
* @arg DMA2D_IT_TE: Transfer error interrupt mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified DMA2D interrupt source is enabled or not.
|
||||
* @param __HANDLE__ DMA2D handle
|
||||
* @param __INTERRUPT__ specifies the DMA2D interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DMA2D_IT_CE: Configuration error interrupt mask
|
||||
* @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
|
||||
* @arg DMA2D_IT_CAE: CLUT access error interrupt mask
|
||||
* @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
|
||||
* @arg DMA2D_IT_TC: Transfer complete interrupt mask
|
||||
* @arg DMA2D_IT_TE: Transfer error interrupt mask
|
||||
* @retval The state of INTERRUPT source.
|
||||
*/
|
||||
#define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions *******************************/
|
||||
HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);
|
||||
HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d);
|
||||
void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef *hdma2d);
|
||||
void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d);
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID,
|
||||
pDMA2D_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* IO operation functions *******************************************************/
|
||||
HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
|
||||
uint32_t Height);
|
||||
HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2,
|
||||
uint32_t DstAddress, uint32_t Width, uint32_t Height);
|
||||
HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
|
||||
uint32_t Height);
|
||||
HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2,
|
||||
uint32_t DstAddress, uint32_t Width, uint32_t Height);
|
||||
HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
|
||||
HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
|
||||
HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
|
||||
HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg,
|
||||
uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg,
|
||||
uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout);
|
||||
void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d);
|
||||
void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d);
|
||||
void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions *************************************************/
|
||||
HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line);
|
||||
HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d);
|
||||
HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d);
|
||||
HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral State functions ***************************************************/
|
||||
HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(const DMA2D_HandleTypeDef *hdma2d);
|
||||
uint32_t HAL_DMA2D_GetError(const DMA2D_HandleTypeDef *hdma2d);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup DMA2D_Private_Constants DMA2D Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark
|
||||
* @{
|
||||
*/
|
||||
#define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW /*!< DMA2D maximum line watermark */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA2D_Color_Value DMA2D Color Value
|
||||
* @{
|
||||
*/
|
||||
#define DMA2D_COLOR_VALUE 0x000000FFU /*!< Color value mask */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers
|
||||
* @{
|
||||
*/
|
||||
#define DMA2D_MAX_LAYER 2U /*!< DMA2D maximum number of layers */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA2D_Layers DMA2D Layers
|
||||
* @{
|
||||
*/
|
||||
#define DMA2D_BACKGROUND_LAYER 0x00000000U /*!< DMA2D Background Layer (layer 0) */
|
||||
#define DMA2D_FOREGROUND_LAYER 0x00000001U /*!< DMA2D Foreground Layer (layer 1) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA2D_Offset DMA2D Offset
|
||||
* @{
|
||||
*/
|
||||
#define DMA2D_OFFSET DMA2D_FGOR_LO /*!< maximum Line Offset */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA2D_Size DMA2D Size
|
||||
* @{
|
||||
*/
|
||||
#define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U) /*!< DMA2D maximum number of pixels per line */
|
||||
#define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D maximum number of lines */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size
|
||||
* @{
|
||||
*/
|
||||
#define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8U) /*!< DMA2D maximum CLUT size */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup DMA2D_Private_Macros DMA2D Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_DMA2D_LAYER(LAYER) (((LAYER) == DMA2D_BACKGROUND_LAYER)\
|
||||
|| ((LAYER) == DMA2D_FOREGROUND_LAYER))
|
||||
|
||||
#define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \
|
||||
((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M) || \
|
||||
((MODE) == DMA2D_M2M_BLEND_FG) || ((MODE) == DMA2D_M2M_BLEND_BG))
|
||||
|
||||
#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || \
|
||||
((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \
|
||||
((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || \
|
||||
((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \
|
||||
((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444))
|
||||
|
||||
#define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE)
|
||||
#define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE)
|
||||
#define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL)
|
||||
#define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET)
|
||||
|
||||
#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || \
|
||||
((INPUT_CM) == DMA2D_INPUT_RGB888) || \
|
||||
((INPUT_CM) == DMA2D_INPUT_RGB565) || \
|
||||
((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \
|
||||
((INPUT_CM) == DMA2D_INPUT_ARGB4444) || \
|
||||
((INPUT_CM) == DMA2D_INPUT_L8) || \
|
||||
((INPUT_CM) == DMA2D_INPUT_AL44) || \
|
||||
((INPUT_CM) == DMA2D_INPUT_AL88) || \
|
||||
((INPUT_CM) == DMA2D_INPUT_L4) || \
|
||||
((INPUT_CM) == DMA2D_INPUT_A8) || \
|
||||
((INPUT_CM) == DMA2D_INPUT_A4) || \
|
||||
((INPUT_CM) == DMA2D_INPUT_YCBCR))
|
||||
|
||||
#define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
|
||||
((AlphaMode) == DMA2D_REPLACE_ALPHA) || \
|
||||
((AlphaMode) == DMA2D_COMBINE_ALPHA))
|
||||
|
||||
#define IS_DMA2D_ALPHA_INVERTED(Alpha_Inverted) (((Alpha_Inverted) == DMA2D_REGULAR_ALPHA) || \
|
||||
((Alpha_Inverted) == DMA2D_INVERTED_ALPHA))
|
||||
|
||||
#define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \
|
||||
((RB_Swap) == DMA2D_RB_SWAP))
|
||||
|
||||
#define IS_DMA2D_LOM_MODE(LOM) (((LOM) == DMA2D_LOM_PIXELS) || \
|
||||
((LOM) == DMA2D_LOM_BYTES))
|
||||
|
||||
#define IS_DMA2D_BYTES_SWAP(BYTES_SWAP) (((BYTES_SWAP) == DMA2D_BYTES_REGULAR) || \
|
||||
((BYTES_SWAP) == DMA2D_BYTES_SWAP))
|
||||
|
||||
#define IS_DMA2D_CHROMA_SUB_SAMPLING(CSS) (((CSS) == DMA2D_NO_CSS) || \
|
||||
((CSS) == DMA2D_CSS_422) || \
|
||||
((CSS) == DMA2D_CSS_420))
|
||||
|
||||
#define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
|
||||
#define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
|
||||
#define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX)
|
||||
#define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
|
||||
((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
|
||||
((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
|
||||
#define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
|
||||
((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \
|
||||
((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined (DMA2D) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7RSxx_HAL_DMA2D_H */
|
||||
|
|
@ -1,719 +0,0 @@
|
|||
/**
|
||||
**********************************************************************************************************************
|
||||
* @file stm32h7rsxx_hal_dma_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of DMA HAL extension module.
|
||||
**********************************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
**********************************************************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/
|
||||
#ifndef STM32H7RSxx_HAL_DMA_EX_H
|
||||
#define STM32H7RSxx_HAL_DMA_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ----------------------------------------------------------------------------------------------------------*/
|
||||
#include "stm32h7rsxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H7RSxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMAEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ----------------------------------------------------------------------------------------------------*/
|
||||
/** @defgroup DMAEx_Exported_Types DMAEx Exported Types
|
||||
* @brief DMAEx Exported types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief DMAEx Data Handling Configuration Structure Definition.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DataExchange; /*!< Specifies the DMA channel data exchange mode.
|
||||
This parameter can be a value of @ref DMAEx_Data_Exchange */
|
||||
|
||||
uint32_t DataAlignment; /*!< Specifies the DMA channel data padding and alignment mode
|
||||
This parameter can be a value of @ref DMAEx_Data_Alignment */
|
||||
|
||||
} DMA_DataHandlingConfTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DMAEx Trigger Configuration Structure Definition.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t TriggerMode; /*!< Specifies the DMA channel trigger mode.
|
||||
This parameter can be a value of @ref DMAEx_Trigger_Mode */
|
||||
|
||||
uint32_t TriggerPolarity; /*!< Specifies the DMA channel trigger event polarity.
|
||||
This parameter can be a value of @ref DMAEx_Trigger_Polarity */
|
||||
|
||||
uint32_t TriggerSelection; /*!< Specifies the DMA channel trigger event selection.
|
||||
This parameter can be a value of @ref DMAEx_Trigger_Selection */
|
||||
|
||||
} DMA_TriggerConfTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DMAEx Repeated Block Configuration Structure Definition.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t RepeatCount; /*!< Specifies the DMA channel repeat count (the number of repetitions of block).
|
||||
This parameter can be a value between 1 and 2048 */
|
||||
|
||||
int32_t SrcAddrOffset; /*!< Specifies the DMA channel single/burst source address offset :
|
||||
This parameter can be a value between -8191 and 8191.
|
||||
* If source address offset > 0 => Increment the source address by offset from where
|
||||
the last single/burst transfer ends.
|
||||
* If source address offset < 0 => Decrement the source address by offset from where
|
||||
the last single/burst transfer ends.
|
||||
* If source address offset == 0 => The next single/burst source address starts from
|
||||
where the last transfer ends */
|
||||
|
||||
int32_t DestAddrOffset; /*!< Specifies the DMA channel single/burst destination address offset signed value :
|
||||
This parameter can be a value between -8191 and 8191.
|
||||
* If destination address offset > 0 => Increment the destination address by offset
|
||||
from where the last single/burst transfer ends.
|
||||
* If destination address offset < 0 => Decrement the destination address by offset
|
||||
from where the last single/burst transfer ends.
|
||||
* If destination address offset == 0 => The next single/burst destination address
|
||||
starts from where the last transfer ends. */
|
||||
|
||||
int32_t BlkSrcAddrOffset; /*!< Specifies the DMA channel block source address offset signed value :
|
||||
This parameter can be a value between -65535 and 65535.
|
||||
* If block source address offset > 0 => Increment the block source address by offset
|
||||
from where the last block ends.
|
||||
* If block source address offset < 0 => Decrement the next block source address by
|
||||
offset from where the last block ends.
|
||||
* If block source address offset == 0 => the next block source address starts from
|
||||
where the last block ends */
|
||||
|
||||
int32_t BlkDestAddrOffset; /*!< Specifies the DMA channel block destination address offset signed value :
|
||||
This parameter can be a value between -65535 and 65535.
|
||||
* If block destination address offset > 0 => Increment the block destination address
|
||||
by offset from where the last block ends.
|
||||
* If block destination address offset < 0 => Decrement the next block destination
|
||||
address by offset from where the last block ends.
|
||||
* If block destination address offset == 0 => the next block destination address
|
||||
starts from where the last block ends */
|
||||
|
||||
} DMA_RepeatBlockConfTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DMAEx Queue State Enumeration Definition.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DMA_QUEUE_STATE_RESET = 0x00U, /*!< DMA queue empty */
|
||||
HAL_DMA_QUEUE_STATE_READY = 0x01U, /*!< DMA queue ready for use */
|
||||
HAL_DMA_QUEUE_STATE_BUSY = 0x02U /*!< DMA queue execution on going */
|
||||
|
||||
} HAL_DMA_QStateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DMAEx Linked-List Node Configuration Structure Definition.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t NodeType; /*!< Specifies the DMA channel node type.
|
||||
This parameter can be a value of @ref DMAEx_Node_Type */
|
||||
|
||||
DMA_InitTypeDef Init; /*!< Specifies the DMA channel basic configuration */
|
||||
|
||||
DMA_DataHandlingConfTypeDef DataHandlingConfig; /*!< Specifies the DMA channel data handling channel configuration */
|
||||
|
||||
DMA_TriggerConfTypeDef TriggerConfig; /*!< Specifies the DMA channel trigger configuration */
|
||||
|
||||
DMA_RepeatBlockConfTypeDef RepeatBlockConfig; /*!< Specifies the DMA channel repeated block configuration */
|
||||
|
||||
uint32_t SrcAddress; /*!< Specifies the source memory address */
|
||||
uint32_t DstAddress; /*!< Specifies the destination memory address */
|
||||
uint32_t DataSize; /*!< Specifies the source data size in bytes */
|
||||
|
||||
} DMA_NodeConfTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DMAEx Linked-List Node Structure Definition.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t LinkRegisters[8U]; /*!< Physical Node register description */
|
||||
uint32_t NodeInfo; /*!< Node information */
|
||||
|
||||
} DMA_NodeTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DMAEx Linked-List Queue Structure Definition.
|
||||
*/
|
||||
typedef struct __DMA_QListTypeDef
|
||||
{
|
||||
DMA_NodeTypeDef *Head; /*!< Specifies the queue head node */
|
||||
|
||||
DMA_NodeTypeDef *FirstCircularNode; /*!< Specifies the queue first circular node */
|
||||
|
||||
uint32_t NodeNumber; /*!< Specifies the queue node number */
|
||||
|
||||
__IO HAL_DMA_QStateTypeDef State; /*!< Specifies the queue state */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< Specifies the queue error code */
|
||||
|
||||
__IO uint32_t Type; /*!< Specifies whether the queue is static or dynamic */
|
||||
|
||||
} DMA_QListTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants ------------------------------------------------------------------------------------------------*/
|
||||
/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants
|
||||
* @brief DMAEx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup Queue_Error_Codes Queue Error Codes
|
||||
* @brief Queue Error Codes
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DMA_QUEUE_ERROR_NONE (0x00U) /*!< No error */
|
||||
#define HAL_DMA_QUEUE_ERROR_BUSY (0x01U) /*!< Error busy */
|
||||
#define HAL_DMA_QUEUE_ERROR_EMPTY (0x02U) /*!< Error unallowed operation for empty queue */
|
||||
#define HAL_DMA_QUEUE_ERROR_UNSUPPORTED (0x03U) /*!< Error unsupported feature */
|
||||
#define HAL_DMA_QUEUE_ERROR_INVALIDTYPE (0x04U) /*!< Error incompatible node type or circular initialization
|
||||
and queue circular types are incompatible */
|
||||
#define HAL_DMA_QUEUE_ERROR_OUTOFRANGE (0x05U) /*!< Error out of range node memory */
|
||||
#define HAL_DMA_QUEUE_ERROR_NOTFOUND (0x06U) /*!< Error node not found in queue */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_LinkedList_Mode DMAEx LinkedList Mode
|
||||
* @brief DMAEx LinkedList Mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_LINKEDLIST_NORMAL DMA_LINKEDLIST /*!< Linear linked-list DMA channel transfer */
|
||||
#define DMA_LINKEDLIST_CIRCULAR (DMA_LINKEDLIST | (0x01U)) /*!< Circular linked-list DMA channel transfer */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_Data_Alignment DMAEx Data Alignment
|
||||
* @brief DMAEx Data Alignment
|
||||
* @{
|
||||
*/
|
||||
#define DMA_DATA_RIGHTALIGN_ZEROPADDED 0x00000000U /*!< If source data width < destination data width
|
||||
=> Right aligned padded with 0 up to destination data
|
||||
width */
|
||||
#define DMA_DATA_RIGHTALIGN_LEFTTRUNC 0x00000000U /*!< If source data width > destination data width
|
||||
=> Right aligned left Truncated down to destination
|
||||
data width */
|
||||
#define DMA_DATA_RIGHTALIGN_SIGNEXT DMA_CTR1_PAM_0 /*!< If source data width < destination data width
|
||||
=> Right Aligned padded with sign extended up to
|
||||
destination data width */
|
||||
#define DMA_DATA_LEFTALIGN_RIGHTTRUNC DMA_CTR1_PAM_0 /*!< If source data width > destination data width
|
||||
=> Left Aligned Right Truncated down to the
|
||||
destination data width */
|
||||
#define DMA_DATA_PACK DMA_CTR1_PAM_1 /*!< If source data width < destination data width
|
||||
=> Packed at the destination data width */
|
||||
#define DMA_DATA_UNPACK DMA_CTR1_PAM_1 /*!< If source data width > destination data width
|
||||
=> Unpacked at the destination data width */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_Data_Exchange DMAEx Data Exchange
|
||||
* @brief DMAEx Data Exchange
|
||||
* @{
|
||||
*/
|
||||
#define DMA_EXCHANGE_NONE 0x00000000U /*!< No data exchange */
|
||||
#define DMA_EXCHANGE_DEST_BYTE DMA_CTR1_DBX /*!< Destination Byte exchange when destination data width is > Byte */
|
||||
#define DMA_EXCHANGE_DEST_HALFWORD DMA_CTR1_DHX /*!< Destination Half-Word exchange when destination data width is > Half-Word */
|
||||
#define DMA_EXCHANGE_SRC_BYTE DMA_CTR1_SBX /*!< Source Byte endianness exchange when source data width is word */
|
||||
#define DMA_EXCHANGE_DEST_WORD DMA_CTR1_DWX /*!< Destination Word exchange when destination data width is > Word */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_Trigger_Polarity DMAEx Trigger Polarity
|
||||
* @brief DMAEx Trigger Polarity
|
||||
* @{
|
||||
*/
|
||||
#define DMA_TRIG_POLARITY_MASKED 0x00000000U /*!< No trigger of the selected DMA request. Masked trigger event */
|
||||
#define DMA_TRIG_POLARITY_RISING DMA_CTR2_TRIGPOL_0 /*!< Trigger of the selected DMA request on the rising edge of the selected trigger event input */
|
||||
#define DMA_TRIG_POLARITY_FALLING DMA_CTR2_TRIGPOL_1 /*!< Trigger of the selected DMA request on the falling edge of the selected trigger event input */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_Trigger_Mode DMAEx Trigger Mode
|
||||
* @brief DMAEx Trigger Mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_TRIGM_BLOCK_TRANSFER 0x00000000U /*!< A block transfer is conditioned by (at least) one hit trigger */
|
||||
#define DMA_TRIGM_REPEATED_BLOCK_TRANSFER DMA_CTR2_TRIGM_0 /*!< A repeated block transfer is conditioned by (at least) one hit trigger */
|
||||
#define DMA_TRIGM_LLI_LINK_TRANSFER DMA_CTR2_TRIGM_1 /*!< A LLI link transfer is conditioned by (at least) one hit trigger */
|
||||
#define DMA_TRIGM_SINGLE_BURST_TRANSFER DMA_CTR2_TRIGM /*!< A single/burst transfer is conditioned by (at least) one hit trigger */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_Trigger_Selection DMAEx Trigger Selection
|
||||
* @brief DMAEx Trigger Selection
|
||||
* @{
|
||||
*/
|
||||
/* HPDMA1 triggers */
|
||||
#define HPDMA1_TRIGGER_DCMIPP_EVT_FRAMEEND 0U /*!< HPDMA1 HW Trigger signal is DCMIPP_EVT_FRAMEEND */
|
||||
#define HPDMA1_TRIGGER_DCMIPP_EVT_HSYNC 1U /*!< HPDMA1 HW Trigger signal is DCMIPP_EVT_HSYNC */
|
||||
#define HPDMA1_TRIGGER_DCMIPP_EVT_LINEEND 2U /*!< HPDMA1 HW Trigger signal is DCMIPP_EVT_LINEEND */
|
||||
#define HPDMA1_TRIGGER_DCMIPP_EVT_VSYNC 3U /*!< HPDMA1 HW Trigger signal is DCMIPP_EVT_VSYNC */
|
||||
#define HPDMA1_TRIGGER_DMA2D_CTC_FLAG 4U /*!< HPDMA1 HW Trigger signal is DMA2D_CTC_FLAG */
|
||||
#define HPDMA1_TRIGGER_DMA2D_TC_FLAG 5U /*!< HPDMA1 HW Trigger signal is DMA2D_TC_FLAG */
|
||||
#define HPDMA1_TRIGGER_DMA2D_TW_FLAG 6U /*!< HPDMA1 HW Trigger signal is DMA2D_TW_FLAG */
|
||||
#define HPDMA1_TRIGGER_JPEG_EOC_FLAG 7U /*!< HPDMA1 HW Trigger signal is JPEG_EOC_FLAG */
|
||||
#define HPDMA1_TRIGGER_JPEG_IFNF_FLAG 8U /*!< HPDMA1 HW Trigger signal is JPEG_IFNF_FLAG */
|
||||
#define HPDMA1_TRIGGER_JPEG_IFT_FLAG 9U /*!< HPDMA1 HW Trigger signal is JPEG_IFT_FLAG */
|
||||
#define HPDMA1_TRIGGER_JPEG_OFNE_FLAG 10U /*!< HPDMA1 HW Trigger signal is JPEG_OFNE_FLAG */
|
||||
#define HPDMA1_TRIGGER_JPEG_OFT_FLAG 11U /*!< HPDMA1 HW Trigger signal is JPEG_OFT_FLAG */
|
||||
#define HPDMA1_TRIGGER_LCD 12U /*!< HPDMA1 HW Trigger signal is LCD */
|
||||
#define HPDMA1_TRIGGER_GPU2D1_GP_FLAG0 13U /*!< HPDMA1 HW Trigger signal is GPU2D1_GP_FLAG0 */
|
||||
#define HPDMA1_TRIGGER_GPU2D1_GP_FLAG1 14U /*!< HPDMA1 HW Trigger signal is GPU2D1_GP_FLAG1 */
|
||||
#define HPDMA1_TRIGGER_GPU2D1_GP_FLAG2 15U /*!< HPDMA1 HW Trigger signal is GPU2D1_GP_FLAG2 */
|
||||
#define HPDMA1_TRIGGER_GPU2D1_GP_FLAG3 16U /*!< HPDMA1 HW Trigger signal is GPU2D1_GP_FLAG3 */
|
||||
#define HPDMA1_TRIGGER_GFXTIM_0_EVT_4 17U /*!< HPDMA1 HW Trigger signal is GFXTIM_0_EVT_4 */
|
||||
#define HPDMA1_TRIGGER_GFXTIM_0_EVT_3 18U /*!< HPDMA1 HW Trigger signal is GFXTIM_0_EVT_3 */
|
||||
#define HPDMA1_TRIGGER_GFXTIM_0_EVT_2 19U /*!< HPDMA1 HW Trigger signal is GFXTIM_0_EVT_2 */
|
||||
#define HPDMA1_TRIGGER_GFXTIM_0_EVT_1 20U /*!< HPDMA1 HW Trigger signal is GFXTIM_0_EVT_1 */
|
||||
#define HPDMA1_TRIGGER_GPDMA1_CH0_TCF 21U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH0_TCF */
|
||||
#define HPDMA1_TRIGGER_GPDMA1_CH1_TCF 22U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */
|
||||
#define HPDMA1_TRIGGER_GPDMA1_CH2_TCF 23U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH2_TCF */
|
||||
#define HPDMA1_TRIGGER_GPDMA1_CH3_TCF 24U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH3_TCF */
|
||||
#define HPDMA1_TRIGGER_GPDMA1_CH4_TCF 25U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH4_TCF */
|
||||
#define HPDMA1_TRIGGER_GPDMA1_CH5_TCF 26U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH5_TCF */
|
||||
#define HPDMA1_TRIGGER_GPDMA1_CH6_TCF 27U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH6_TCF */
|
||||
#define HPDMA1_TRIGGER_GPDMA1_CH7_TCF 28U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH7_TCF */
|
||||
#define HPDMA1_TRIGGER_GPDMA1_CH8_TCF 29U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH8_TCF */
|
||||
#define HPDMA1_TRIGGER_GPDMA1_CH9_TCF 30U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH9_TCF */
|
||||
#define HPDMA1_TRIGGER_GPDMA1_CH10_TCF 31U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH10_TCF */
|
||||
#define HPDMA1_TRIGGER_GPDMA1_CH11_TCF 32U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH11_TCF */
|
||||
#define HPDMA1_TRIGGER_GPDMA1_CH12_TCF 33U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH12_TCF */
|
||||
#define HPDMA1_TRIGGER_GPDMA1_CH13_TCF 34U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH13_TCF */
|
||||
#define HPDMA1_TRIGGER_GPDMA1_CH14_TCF 35U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH14_TCF */
|
||||
#define HPDMA1_TRIGGER_GPDMA1_CH15_TCF 36U /*!< HPDMA1 HW Trigger signal is GPDMA1_CH15_TCF */
|
||||
#define HPDMA1_TRIGGER_HPDMA1_CH0_TCF 37U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH0_TCF */
|
||||
#define HPDMA1_TRIGGER_HPDMA1_CH1_TCF 38U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH1_TCF */
|
||||
#define HPDMA1_TRIGGER_HPDMA1_CH2_TCF 39U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH2_TCF */
|
||||
#define HPDMA1_TRIGGER_HPDMA1_CH3_TCF 40U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH3_TCF */
|
||||
#define HPDMA1_TRIGGER_HPDMA1_CH4_TCF 41U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH4_TCF */
|
||||
#define HPDMA1_TRIGGER_HPDMA1_CH5_TCF 42U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH5_TCF */
|
||||
#define HPDMA1_TRIGGER_HPDMA1_CH6_TCF 43U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH6_TCF */
|
||||
#define HPDMA1_TRIGGER_HPDMA1_CH7_TCF 44U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH7_TCF */
|
||||
#define HPDMA1_TRIGGER_HPDMA1_CH8_TCF 45U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH8_TCF */
|
||||
#define HPDMA1_TRIGGER_HPDMA1_CH9_TCF 46U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH9_TCF */
|
||||
#define HPDMA1_TRIGGER_HPDMA1_CH10_TCF 47U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH10_TCF */
|
||||
#define HPDMA1_TRIGGER_HPDMA1_CH11_TCF 48U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH11_TCF */
|
||||
#define HPDMA1_TRIGGER_HPDMA1_CH12_TCF 49U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH12_TCF */
|
||||
#define HPDMA1_TRIGGER_HPDMA1_CH13_TCF 50U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH13_TCF */
|
||||
#define HPDMA1_TRIGGER_HPDMA1_CH14_TCF 51U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH14_TCF */
|
||||
#define HPDMA1_TRIGGER_HPDMA1_CH15_TCF 52U /*!< HPDMA1 HW Trigger signal is HPDMA1_CH15_TCF */
|
||||
|
||||
/* GPDMA1 triggers */
|
||||
#define GPDMA1_TRIGGER_HPDMA1_CH0_TCF 0U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH0_TCF */
|
||||
#define GPDMA1_TRIGGER_HPDMA1_CH1_TCF 1U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH1_TCF */
|
||||
#define GPDMA1_TRIGGER_HPDMA1_CH2_TCF 2U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH2_TCF */
|
||||
#define GPDMA1_TRIGGER_HPDMA1_CH3_TCF 3U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH3_TCF */
|
||||
#define GPDMA1_TRIGGER_HPDMA1_CH4_TCF 4U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH4_TCF */
|
||||
#define GPDMA1_TRIGGER_HPDMA1_CH5_TCF 5U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH5_TCF */
|
||||
#define GPDMA1_TRIGGER_HPDMA1_CH6_TCF 6U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH6_TCF */
|
||||
#define GPDMA1_TRIGGER_HPDMA1_CH7_TCF 7U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH7_TCF */
|
||||
#define GPDMA1_TRIGGER_HPDMA1_CH8_TCF 8U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH8_TCF */
|
||||
#define GPDMA1_TRIGGER_HPDMA1_CH9_TCF 9U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH9_TCF */
|
||||
#define GPDMA1_TRIGGER_HPDMA1_CH10_TCF 10U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH10_TCF */
|
||||
#define GPDMA1_TRIGGER_HPDMA1_CH11_TCF 11U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH11_TCF */
|
||||
#define GPDMA1_TRIGGER_HPDMA1_CH12_TCF 12U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH12_TCF */
|
||||
#define GPDMA1_TRIGGER_HPDMA1_CH13_TCF 13U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH13_TCF */
|
||||
#define GPDMA1_TRIGGER_HPDMA1_CH14_TCF 14U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH14_TCF */
|
||||
#define GPDMA1_TRIGGER_HPDMA1_CH15_TCF 15U /*!< GPDMA1 HW Trigger signal is HPDMA1_CH15_TCF */
|
||||
#define GPDMA1_TRIGGER_LPTIM1_CH1 16U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH1 */
|
||||
#define GPDMA1_TRIGGER_LPTIM1_CH2 17U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH2 */
|
||||
#define GPDMA1_TRIGGER_LPTIM2_CH1 18U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH1 */
|
||||
#define GPDMA1_TRIGGER_LPTIM2_CH2 19U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH2 */
|
||||
#define GPDMA1_TRIGGER_LPTIM3_CH1 20U /*!< GPDMA1 HW Trigger signal is LPTIM3_CH1 */
|
||||
#define GPDMA1_TRIGGER_LPTIM3_CH2 21U /*!< GPDMA1 HW Trigger signal is LPTIM3_CH2 */
|
||||
#define GPDMA1_TRIGGER_LPTIM4_OUT 22U /*!< GPDMA1 HW Trigger signal is LPTIM4_OUT */
|
||||
#define GPDMA1_TRIGGER_LPTIM5_OUT 23U /*!< GPDMA1 HW Trigger signal is LPTIM5_OUT */
|
||||
#define GPDMA1_TRIGGER_EXTIT0_SYNC 24U /*!< GPDMA1 HW Trigger signal is EXTIT0_SYNC */
|
||||
#define GPDMA1_TRIGGER_RTC_WKUP 25U /*!< GPDMA1 HW Trigger signal is RTC_WKUP */
|
||||
#define GPDMA1_TRIGGER_LPUART1_IT_R_WUP_ASYNC 26U /*!< GPDMA1 HW Trigger signal is R_WUP_ASYNC */
|
||||
#define GPDMA1_TRIGGER_LPUART1_IT_T_WUP_ASYNC 27U /*!< GPDMA1 HW Trigger signal is T_WUP_ASYNC */
|
||||
#define GPDMA1_TRIGGER_SPI6_IT_OR_SPI6_AIT_SYNC 28U /*!< GPDMA1 HW Trigger signal is SPI6_OR_SPI6_AIT_SYNC */
|
||||
#define GPDMA1_TRIGGER_GPDMA1_CH0_TCF 29U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */
|
||||
#define GPDMA1_TRIGGER_GPDMA1_CH1_TCF 30U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */
|
||||
#define GPDMA1_TRIGGER_GPDMA1_CH2_TCF 31U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH2_TCF */
|
||||
#define GPDMA1_TRIGGER_GPDMA1_CH3_TCF 32U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH3_TCF */
|
||||
#define GPDMA1_TRIGGER_GPDMA1_CH4_TCF 33U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH4_TCF */
|
||||
#define GPDMA1_TRIGGER_GPDMA1_CH5_TCF 34U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH5_TCF */
|
||||
#define GPDMA1_TRIGGER_GPDMA1_CH6_TCF 35U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH6_TCF */
|
||||
#define GPDMA1_TRIGGER_GPDMA1_CH7_TCF 36U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH7_TCF */
|
||||
#define GPDMA1_TRIGGER_GPDMA1_CH8_TCF 37U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH8_TCF */
|
||||
#define GPDMA1_TRIGGER_GPDMA1_CH9_TCF 38U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH9_TCF */
|
||||
#define GPDMA1_TRIGGER_GPDMA1_CH10_TCF 39U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH10_TCF */
|
||||
#define GPDMA1_TRIGGER_GPDMA1_CH11_TCF 40U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH11_TCF */
|
||||
#define GPDMA1_TRIGGER_GPDMA1_CH12_TCF 41U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH12_TCF */
|
||||
#define GPDMA1_TRIGGER_GPDMA1_CH13_TCF 42U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH13_TCF */
|
||||
#define GPDMA1_TRIGGER_GPDMA1_CH14_TCF 43U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH14_TCF */
|
||||
#define GPDMA1_TRIGGER_GPDMA1_CH15_TCF 44U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH15_TCF */
|
||||
#define GPDMA1_TRIGGER_TIM1_TRGO 45U /*!< GPDMA1 HW Trigger signal is TIM1_TRGO */
|
||||
#define GPDMA1_TRIGGER_TIM1_TRGO2 46U /*!< GPDMA1 HW Trigger signal is TIM1_TRGO2 */
|
||||
#define GPDMA1_TRIGGER_TIM2_TRGO 47U /*!< GPDMA1 HW Trigger signal is TIM2_TRGO */
|
||||
#define GPDMA1_TRIGGER_TIM3_TRGO 48U /*!< GPDMA1 HW Trigger signal is TIM3_TRGO */
|
||||
#define GPDMA1_TRIGGER_TIM4_TRGO 49U /*!< GPDMA1 HW Trigger signal is TIM4_TRGO */
|
||||
#define GPDMA1_TRIGGER_TIM5_TRGO 50U /*!< GPDMA1 HW Trigger signal is TIM5_TRGO */
|
||||
#define GPDMA1_TRIGGER_TIM6_TRGO 51U /*!< GPDMA1 HW Trigger signal is TIM6_TRGO */
|
||||
#define GPDMA1_TRIGGER_TIM7_TRGO 52U /*!< GPDMA1 HW Trigger signal is TIM7_TRGO */
|
||||
#define GPDMA1_TRIGGER_TIM9_TRGO 53U /*!< GPDMA1 HW Trigger signal is TIM9_TRGO */
|
||||
#define GPDMA1_TRIGGER_TIM12_TRGO 54U /*!< GPDMA1 HW Trigger signal is TIM12_TRGO */
|
||||
#define GPDMA1_TRIGGER_TIM15_TRGO 55U /*!< GPDMA1 HW Trigger signal is TIM15_TRGO */
|
||||
|
||||
#define GPDMA1_MAX_TRIGGER 55U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_Node_Type DMAEx Node Type
|
||||
* @brief DMAEx Node Type
|
||||
* @{
|
||||
*/
|
||||
#define DMA_GPDMA_LINEAR_NODE (DMA_CHANNEL_TYPE_GPDMA | DMA_CHANNEL_TYPE_LINEAR_ADDR) /*!< Defines the GPDMA linear addressing node type */
|
||||
#define DMA_GPDMA_2D_NODE (DMA_CHANNEL_TYPE_GPDMA | DMA_CHANNEL_TYPE_2D_ADDR) /*!< Defines the GPDMA 2 dimension addressing node type */
|
||||
#define DMA_HPDMA_LINEAR_NODE (DMA_CHANNEL_TYPE_HPDMA | DMA_CHANNEL_TYPE_LINEAR_ADDR) /*!< Defines the HPDMA linear addressing node type */
|
||||
#define DMA_HPDMA_2D_NODE (DMA_CHANNEL_TYPE_HPDMA | DMA_CHANNEL_TYPE_2D_ADDR) /*!< Defines the HPDMA 2 dimension addressing node type */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_Link_Allocated_Port DMAEx Linked-List Allocated Port
|
||||
* @brief DMAEx Linked-List Allocated Port
|
||||
* @{
|
||||
*/
|
||||
#define DMA_LINK_ALLOCATED_PORT0 0x00000000U /*!< Link allocated port 0 */
|
||||
#define DMA_LINK_ALLOCATED_PORT1 DMA_CCR_LAP /*!< Link allocated port 1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_Link_Step_Mode DMAEx Link Step Mode
|
||||
* @brief DMAEx Link Step Mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_LSM_FULL_EXECUTION 0x00000000U /*!< Channel is executed for the full linked-list */
|
||||
#define DMA_LSM_1LINK_EXECUTION DMA_CCR_LSM /*!< Channel is executed once for the current LLI */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions ------------------------------------------------------------------------------------------------*/
|
||||
/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
|
||||
* @brief DMAEx Exported functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_Exported_Functions_Group1 Linked-List Initialization and De-Initialization Functions
|
||||
* @brief Linked-List Initialization and De-Initialization Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_Init(DMA_HandleTypeDef *const hdma);
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_Exported_Functions_Group2 Linked-List IO Operation Functions
|
||||
* @brief Linked-List IO Operation Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_Start(DMA_HandleTypeDef *const hdma);
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_Start_IT(DMA_HandleTypeDef *const hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_Exported_Functions_Group3 Linked-List Management Functions
|
||||
* @brief Linked-List Management Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig,
|
||||
DMA_NodeTypeDef *const pNode);
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig,
|
||||
DMA_NodeTypeDef const *const pNode);
|
||||
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_InsertNode(DMA_QListTypeDef *const pQList,
|
||||
DMA_NodeTypeDef *const pPrevNode,
|
||||
DMA_NodeTypeDef *const pNewNode);
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Head(DMA_QListTypeDef *const pQList,
|
||||
DMA_NodeTypeDef *const pNewNode);
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Tail(DMA_QListTypeDef *const pQList,
|
||||
DMA_NodeTypeDef *const pNewNode);
|
||||
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode(DMA_QListTypeDef *const pQList,
|
||||
DMA_NodeTypeDef *const pNode);
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Head(DMA_QListTypeDef *const pQList);
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Tail(DMA_QListTypeDef *const pQList);
|
||||
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode(DMA_QListTypeDef *const pQList,
|
||||
DMA_NodeTypeDef *const pOldNode,
|
||||
DMA_NodeTypeDef *const pNewNode);
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Head(DMA_QListTypeDef *const pQList,
|
||||
DMA_NodeTypeDef *const pNewNode);
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Tail(DMA_QListTypeDef *const pQList,
|
||||
DMA_NodeTypeDef *const pNewNode);
|
||||
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_ResetQ(DMA_QListTypeDef *const pQList);
|
||||
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_InsertQ(DMA_QListTypeDef *const pSrcQList,
|
||||
DMA_NodeTypeDef const *const pPrevNode,
|
||||
DMA_QListTypeDef *const pDestQList);
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Head(DMA_QListTypeDef *const pSrcQList,
|
||||
DMA_QListTypeDef *const pDestQList);
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Tail(DMA_QListTypeDef *const pSrcQList,
|
||||
DMA_QListTypeDef *const pDestQList);
|
||||
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_SetCircularModeConfig(DMA_QListTypeDef *const pQList,
|
||||
DMA_NodeTypeDef *const pFirstCircularNode);
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_SetCircularMode(DMA_QListTypeDef *const pQList);
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_ClearCircularMode(DMA_QListTypeDef *const pQList);
|
||||
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToDynamic(DMA_QListTypeDef *const pQList);
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToStatic(DMA_QListTypeDef *const pQList);
|
||||
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_LinkQ(DMA_HandleTypeDef *const hdma,
|
||||
DMA_QListTypeDef *const pQList);
|
||||
HAL_StatusTypeDef HAL_DMAEx_List_UnLinkQ(DMA_HandleTypeDef *const hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_Exported_Functions_Group4 Data Handling, Repeated Block and Trigger Configuration Functions
|
||||
* @brief Data Handling, Repeated Block and Trigger Configuration Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMAEx_ConfigDataHandling(DMA_HandleTypeDef *const hdma,
|
||||
DMA_DataHandlingConfTypeDef const *const pConfigDataHandling);
|
||||
HAL_StatusTypeDef HAL_DMAEx_ConfigTrigger(DMA_HandleTypeDef *const hdma,
|
||||
DMA_TriggerConfTypeDef const *const pConfigTrigger);
|
||||
HAL_StatusTypeDef HAL_DMAEx_ConfigRepeatBlock(DMA_HandleTypeDef *const hdma,
|
||||
DMA_RepeatBlockConfTypeDef const *const pConfigRepeatBlock);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_Exported_Functions_Group5 Suspend and Resume Operation Functions
|
||||
* @brief Suspend and Resume Operation Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMAEx_Suspend(DMA_HandleTypeDef *const hdma);
|
||||
HAL_StatusTypeDef HAL_DMAEx_Suspend_IT(DMA_HandleTypeDef *const hdma);
|
||||
HAL_StatusTypeDef HAL_DMAEx_Resume(DMA_HandleTypeDef *const hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_Exported_Functions_Group6 FIFO Status Function
|
||||
* @brief FIFO Status Function
|
||||
* @{
|
||||
*/
|
||||
uint32_t HAL_DMAEx_GetFifoLevel(DMA_HandleTypeDef const *const hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -----------------------------------------------------------------------------------------------------*/
|
||||
/** @defgroup DMAEx_Private_Types DMAEx Private Types
|
||||
* @brief DMAEx Private Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief DMA Node in Queue Information Structure Definition.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t cllr_offset; /* CLLR register offset */
|
||||
|
||||
uint32_t previousnode_addr; /* Previous node address */
|
||||
|
||||
uint32_t currentnode_pos; /* Current node position */
|
||||
|
||||
uint32_t currentnode_addr; /* Current node address */
|
||||
|
||||
uint32_t nextnode_addr; /* Next node address */
|
||||
|
||||
} DMA_NodeInQInfoTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants -------------------------------------------------------------------------------------------------*/
|
||||
/** @defgroup DMAEx_Private_Constants DMAEx Private Constants
|
||||
* @brief DMAEx Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define DMA_LINKEDLIST (0x0080U) /* DMA channel linked-list mode */
|
||||
|
||||
#define DMA_CHANNEL_TYPE_LINEAR_ADDR (0x0001U) /* DMA channel linear addressing mode */
|
||||
#define DMA_CHANNEL_TYPE_2D_ADDR (0x0002U) /* DMA channel 2D addressing mode */
|
||||
#define DMA_CHANNEL_TYPE_GPDMA (0x0020U) /* GPDMA channel node */
|
||||
#define DMA_CHANNEL_TYPE_HPDMA (0x0040U) /* HPDMA channel node */
|
||||
|
||||
#define NODE_TYPE_MASK (0x00FFU) /* DMA channel node type */
|
||||
#define NODE_CLLR_IDX (0x0700U) /* DMA channel node CLLR index mask */
|
||||
#define NODE_CLLR_IDX_POS (0x0008U) /* DMA channel node CLLR index position */
|
||||
|
||||
#define NODE_MAXIMUM_SIZE (0x0008U) /* Amount of registers of the node */
|
||||
|
||||
#define NODE_STATIC_FORMAT (0x0000U) /* DMA channel node static format */
|
||||
#define NODE_DYNAMIC_FORMAT (0x0001U) /* DMA channel node dynamic format */
|
||||
|
||||
#define UPDATE_CLLR_POSITION (0x0000U) /* DMA channel update CLLR position */
|
||||
#define UPDATE_CLLR_VALUE (0x0001U) /* DMA channel update CLLR value */
|
||||
|
||||
#define LASTNODE_ISNOT_CIRCULAR (0x0000U) /* Last node is not first circular node */
|
||||
#define LASTNODE_IS_CIRCULAR (0x0001U) /* Last node is first circular node */
|
||||
|
||||
#define QUEUE_TYPE_STATIC (0x0000U) /* DMA channel static queue */
|
||||
#define QUEUE_TYPE_DYNAMIC (0x0001U) /* DMA channel dynamic queue */
|
||||
|
||||
#define NODE_CTR1_DEFAULT_OFFSET (0x0000U) /* CTR1 default offset */
|
||||
#define NODE_CTR2_DEFAULT_OFFSET (0x0001U) /* CTR2 default offset */
|
||||
#define NODE_CBR1_DEFAULT_OFFSET (0x0002U) /* CBR1 default offset */
|
||||
#define NODE_CSAR_DEFAULT_OFFSET (0x0003U) /* CSAR default offset */
|
||||
#define NODE_CDAR_DEFAULT_OFFSET (0x0004U) /* CDAR default offset */
|
||||
#define NODE_CTR3_DEFAULT_OFFSET (0x0005U) /* CTR3 2D addressing default offset */
|
||||
#define NODE_CBR2_DEFAULT_OFFSET (0x0006U) /* CBR2 2D addressing default offset */
|
||||
#define NODE_CLLR_2D_DEFAULT_OFFSET (0x0007U) /* CLLR 2D addressing default offset */
|
||||
#define NODE_CLLR_LINEAR_DEFAULT_OFFSET (0x0005U) /* CLLR linear addressing default offset */
|
||||
|
||||
#define DMA_BURST_ADDR_OFFSET_MIN (-8192L) /* DMA burst minimum address offset */
|
||||
#define DMA_BURST_ADDR_OFFSET_MAX (8192L) /* DMA burst maximum address offset */
|
||||
#define DMA_BLOCK_ADDR_OFFSET_MIN (-65536L) /* DMA block minimum address offset */
|
||||
#define DMA_BLOCK_ADDR_OFFSET_MAX (65536L) /* DMA block maximum address offset */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ----------------------------------------------------------------------------------------------------*/
|
||||
/** @defgroup DMAEx_Private_Macros DMAEx Private Macros
|
||||
* @brief DMAEx Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_DMA_DATA_ALIGNMENT(ALIGNMENT) \
|
||||
(((ALIGNMENT) == DMA_DATA_RIGHTALIGN_ZEROPADDED) || \
|
||||
((ALIGNMENT) == DMA_DATA_RIGHTALIGN_SIGNEXT) || \
|
||||
((ALIGNMENT) == DMA_DATA_PACK))
|
||||
|
||||
#define IS_DMA_DATA_EXCHANGE(EXCHANGE) \
|
||||
(((EXCHANGE) & (~(DMA_EXCHANGE_SRC_BYTE | DMA_EXCHANGE_DEST_BYTE | DMA_EXCHANGE_DEST_HALFWORD | \
|
||||
DMA_EXCHANGE_DEST_WORD))) == 0U)
|
||||
|
||||
#define IS_DMA_REPEAT_COUNT(COUNT) \
|
||||
(((COUNT) > 0U) && ((COUNT) <= (DMA_CBR1_BRC >> DMA_CBR1_BRC_Pos)))
|
||||
|
||||
#define IS_DMA_BURST_ADDR_OFFSET(BURST_ADDR_OFFSET) \
|
||||
(((BURST_ADDR_OFFSET) > DMA_BURST_ADDR_OFFSET_MIN) && \
|
||||
((BURST_ADDR_OFFSET) < DMA_BURST_ADDR_OFFSET_MAX))
|
||||
|
||||
#define IS_DMA_BLOCK_ADDR_OFFSET(BLOCK_ADDR_OFFSET) \
|
||||
(((BLOCK_ADDR_OFFSET) > DMA_BLOCK_ADDR_OFFSET_MIN) && \
|
||||
((BLOCK_ADDR_OFFSET) < DMA_BLOCK_ADDR_OFFSET_MAX))
|
||||
|
||||
#define IS_DMA_LINK_ALLOCATED_PORT(LINK_ALLOCATED_PORT) \
|
||||
(((LINK_ALLOCATED_PORT) & (~(DMA_CCR_LAP))) == 0U)
|
||||
|
||||
#define IS_DMA_LINK_STEP_MODE(MODE) \
|
||||
(((MODE) == DMA_LSM_FULL_EXECUTION) || \
|
||||
((MODE) == DMA_LSM_1LINK_EXECUTION))
|
||||
|
||||
#define IS_DMA_TRIGGER_MODE(MODE) \
|
||||
(((MODE) == DMA_TRIGM_BLOCK_TRANSFER) || \
|
||||
((MODE) == DMA_TRIGM_REPEATED_BLOCK_TRANSFER) || \
|
||||
((MODE) == DMA_TRIGM_LLI_LINK_TRANSFER) || \
|
||||
((MODE) == DMA_TRIGM_SINGLE_BURST_TRANSFER))
|
||||
|
||||
#define IS_DMA_TCEM_LINKEDLIST_EVENT_MODE(MODE) \
|
||||
(((MODE) == DMA_TCEM_BLOCK_TRANSFER) || \
|
||||
((MODE) == DMA_TCEM_REPEATED_BLOCK_TRANSFER) || \
|
||||
((MODE) == DMA_TCEM_EACH_LL_ITEM_TRANSFER) || \
|
||||
((MODE) == DMA_TCEM_LAST_LL_ITEM_TRANSFER))
|
||||
|
||||
#define IS_DMA_LINKEDLIST_MODE(MODE) \
|
||||
(((MODE) == DMA_LINKEDLIST_NORMAL) || \
|
||||
((MODE) == DMA_LINKEDLIST_CIRCULAR))
|
||||
|
||||
#define IS_DMA_TRIGGER_POLARITY(POLARITY) \
|
||||
(((POLARITY) == DMA_TRIG_POLARITY_MASKED) || \
|
||||
((POLARITY) == DMA_TRIG_POLARITY_RISING) || \
|
||||
((POLARITY) == DMA_TRIG_POLARITY_FALLING))
|
||||
|
||||
#define IS_DMA_TRIGGER_SELECTION(TRIGGER) \
|
||||
((TRIGGER) <= GPDMA1_TRIGGER_TIM15_TRGO)
|
||||
|
||||
#define IS_DMA_NODE_TYPE(TYPE) \
|
||||
(((TYPE) == DMA_GPDMA_LINEAR_NODE) || \
|
||||
((TYPE) == DMA_GPDMA_2D_NODE) || \
|
||||
((TYPE) == DMA_HPDMA_LINEAR_NODE) || \
|
||||
((TYPE) == DMA_HPDMA_2D_NODE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private functions -------------------------------------------------------------------------------------------------*/
|
||||
/** @defgroup DMAEx_Private_Functions DMAEx Private Functions
|
||||
* @brief DMAEx Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* STM32H7RSxx_HAL_DMA_EX_H */
|
||||
|
|
@ -1,546 +0,0 @@
|
|||
/**
|
||||
**********************************************************************************************************************
|
||||
* @file stm32h7rsxx_hal_dts.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of DTS HAL module.
|
||||
**********************************************************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
**********************************************************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/
|
||||
#ifndef STM32H7RSxx_HAL_DTS_H
|
||||
#define STM32H7RSxx_HAL_DTS_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ----------------------------------------------------------------------------------------------------------*/
|
||||
#include "stm32h7rsxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H7RSxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DTS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ----------------------------------------------------------------------------------------------------*/
|
||||
/** @defgroup DTS_Exported_Types DTS Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief DTS Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t QuickMeasure; /*!< Specifies the quick measure option selection of the DTS sensor.
|
||||
This parameter can be a value of @ref DTS_Quick_Measurement */
|
||||
|
||||
uint32_t RefClock; /*!< Specifies the reference clock selection of the DTS sensor.
|
||||
This parameter can be a value of @ref DTS_Reference_Clock_Selection */
|
||||
|
||||
uint32_t TriggerInput; /*!< Specifies the trigger input of the DTS sensor.
|
||||
This parameter can be a value of @ref DTS_TriggerConfig */
|
||||
|
||||
uint32_t SamplingTime; /*!< Specifies the sampling time configuration.
|
||||
This parameter can be a value of @ref DTS_Sampling_Time */
|
||||
|
||||
uint32_t Divider; /*!< Specifies the high speed clock divider ratio.
|
||||
This parameter can be a value from 0 to 127 */
|
||||
|
||||
uint32_t HighThreshold; /*!< Specifies the high threshold of the DTS sensor */
|
||||
|
||||
uint32_t LowThreshold; /*!< Specifies the low threshold of the DTS sensor */
|
||||
|
||||
} DTS_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DTS_STATE_RESET = 0x00UL, /*!< DTS not yet initialized or disabled */
|
||||
HAL_DTS_STATE_READY = 0x01UL, /*!< DTS initialized and ready for use */
|
||||
HAL_DTS_STATE_BUSY = 0x02UL, /*!< DTS is running */
|
||||
HAL_DTS_STATE_TIMEOUT = 0x03UL, /*!< Timeout state */
|
||||
HAL_DTS_STATE_ERROR = 0x04UL /*!< Internal Process error */
|
||||
|
||||
} HAL_DTS_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DTS Handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1U)
|
||||
typedef struct __DTS_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
|
||||
{
|
||||
DTS_TypeDef *Instance; /*!< Register base address */
|
||||
DTS_InitTypeDef Init; /*!< DTS required parameters */
|
||||
HAL_LockTypeDef Lock; /*!< DTS Locking object */
|
||||
__IO HAL_DTS_StateTypeDef State; /*!< DTS peripheral state */
|
||||
|
||||
#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1U)
|
||||
void (* MspInitCallback)(struct __DTS_HandleTypeDef *hdts); /*!< DTS Base Msp Init Callback */
|
||||
void (* MspDeInitCallback)(struct __DTS_HandleTypeDef *hdts); /*!< DTS Base Msp DeInit Callback */
|
||||
void (* EndCallback)(struct __DTS_HandleTypeDef *hdts); /*!< End measure Callback */
|
||||
void (* LowCallback)(struct __DTS_HandleTypeDef *hdts); /*!< low threshold Callback */
|
||||
void (* HighCallback)(struct __DTS_HandleTypeDef *hdts); /*!< high threshold Callback */
|
||||
void (* AsyncEndCallback)(struct __DTS_HandleTypeDef *hdts); /*!< Asynchronous end of measure Callback */
|
||||
void (* AsyncLowCallback)(struct __DTS_HandleTypeDef *hdts); /*!< Asynchronous low threshold Callback */
|
||||
void (* AsyncHighCallback)(struct __DTS_HandleTypeDef *hdts); /*!< Asynchronous high threshold Callback */
|
||||
#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
|
||||
} DTS_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1U)
|
||||
/**
|
||||
* @brief DTS callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DTS_MEAS_COMPLETE_CB_ID = 0x00U, /*!< Measure complete callback ID */
|
||||
HAL_DTS_ASYNC_MEAS_COMPLETE_CB_ID = 0x01U, /*!< Asynchronous measure complete callback ID */
|
||||
HAL_DTS_LOW_THRESHOLD_CB_ID = 0x02U, /*!< Low threshold detection callback ID */
|
||||
HAL_DTS_ASYNC_LOW_THRESHOLD_CB_ID = 0x03U, /*!< Asynchronous low threshold detection callback ID */
|
||||
HAL_DTS_HIGH_THRESHOLD_CB_ID = 0x04U, /*!< High threshold detection callback ID */
|
||||
HAL_DTS_ASYNC_HIGH_THRESHOLD_CB_ID = 0x05U, /*!< Asynchronous high threshold detection callback ID */
|
||||
HAL_DTS_MSPINIT_CB_ID = 0x06U, /*!< MSP init callback ID */
|
||||
HAL_DTS_MSPDEINIT_CB_ID = 0x07U /*!< MSP de-init callback ID */
|
||||
} HAL_DTS_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DTS callback pointers definition
|
||||
*/
|
||||
typedef void (*pDTS_CallbackTypeDef)(DTS_HandleTypeDef *hdts);
|
||||
#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants ------------------------------------------------------------------------------------------------*/
|
||||
/** @defgroup DTS_Exported_Constants DTS Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DTS_TriggerConfig DTS Trigger Configuration
|
||||
* @{
|
||||
*/
|
||||
/* @brief No Hardware trigger detection */
|
||||
#define DTS_TRIGGER_HW_NONE (0UL)
|
||||
|
||||
/* @brief External Interrupt Mode with LPTIMER1 trigger detection */
|
||||
#define DTS_TRIGGER_LPTIMER4 DTS_CFGR1_TS1_INTRIG_SEL_0
|
||||
|
||||
/* @brief External Interrupt Mode with LPTIMER2 trigger detection */
|
||||
#define DTS_TRIGGER_LPTIMER2 DTS_CFGR1_TS1_INTRIG_SEL_1
|
||||
|
||||
/* @brief External Interrupt Mode with LPTIMER3 trigger detection */
|
||||
#define DTS_TRIGGER_LPTIMER3 (DTS_CFGR1_TS1_INTRIG_SEL_0 | DTS_CFGR1_TS1_INTRIG_SEL_1)
|
||||
|
||||
/* @brief External Interrupt Mode with EXTI13 trigger detection */
|
||||
#define DTS_TRIGGER_EXTI13 DTS_CFGR1_TS1_INTRIG_SEL_2
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DTS_Quick_Measurement DTS Quick Measurement
|
||||
* @{
|
||||
*/
|
||||
#define DTS_QUICKMEAS_ENABLE DTS_CFGR1_Q_MEAS_OPT /*!< Enable the Quick Measure (Measure without calibration) */
|
||||
#define DTS_QUICKMEAS_DISABLE (0x0UL) /*!< Disable the Quick Measure (Measure with calibration) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DTS_Reference_Clock_Selection DTS Reference Clock Selection
|
||||
* @{
|
||||
*/
|
||||
#define DTS_REFCLKSEL_LSE DTS_CFGR1_REFCLK_SEL /*!< Low speed REF clock (LSE) */
|
||||
#define DTS_REFCLKSEL_PCLK (0UL) /*!< High speed REF clock (PCLK) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DTS_Sampling_Time DTS Sampling Time
|
||||
* @{
|
||||
*/
|
||||
#define DTS_SMP_TIME_1_CYCLE DTS_CFGR1_TS1_SMP_TIME_0 /*!< 1 clock cycle for the sampling time */
|
||||
#define DTS_SMP_TIME_2_CYCLE DTS_CFGR1_TS1_SMP_TIME_1 /*!< 2 clock cycle for the sampling time */
|
||||
#define DTS_SMP_TIME_3_CYCLE (DTS_CFGR1_TS1_SMP_TIME_0 |\
|
||||
DTS_CFGR1_TS1_SMP_TIME_1) /*!< 3 clock cycle for the sampling time */
|
||||
#define DTS_SMP_TIME_4_CYCLE (DTS_CFGR1_TS1_SMP_TIME_2) /*!< 4 clock cycle for the sampling time */
|
||||
#define DTS_SMP_TIME_5_CYCLE (DTS_CFGR1_TS1_SMP_TIME_0 |\
|
||||
DTS_CFGR1_TS1_SMP_TIME_2) /*!< 5 clock cycle for the sampling time */
|
||||
#define DTS_SMP_TIME_6_CYCLE (DTS_CFGR1_TS1_SMP_TIME_1 |\
|
||||
DTS_CFGR1_TS1_SMP_TIME_2) /*!< 6 clock cycle for the sampling time */
|
||||
#define DTS_SMP_TIME_7_CYCLE (DTS_CFGR1_TS1_SMP_TIME_0 |\
|
||||
DTS_CFGR1_TS1_SMP_TIME_1 |\
|
||||
DTS_CFGR1_TS1_SMP_TIME_2) /*!< 7 clock cycle for the sampling time */
|
||||
#define DTS_SMP_TIME_8_CYCLE (DTS_CFGR1_TS1_SMP_TIME_3) /*!< 8 clock cycle for the sampling time */
|
||||
#define DTS_SMP_TIME_9_CYCLE (DTS_CFGR1_TS1_SMP_TIME_0 |\
|
||||
DTS_CFGR1_TS1_SMP_TIME_3) /*!< 9 clock cycle for the sampling time */
|
||||
#define DTS_SMP_TIME_10_CYCLE (DTS_CFGR1_TS1_SMP_TIME_1 |\
|
||||
DTS_CFGR1_TS1_SMP_TIME_3) /*!< 10 clock cycle for the sampling time */
|
||||
#define DTS_SMP_TIME_11_CYCLE (DTS_CFGR1_TS1_SMP_TIME_0 |\
|
||||
DTS_CFGR1_TS1_SMP_TIME_1 |\
|
||||
DTS_CFGR1_TS1_SMP_TIME_3) /*!< 11 clock cycle for the sampling time */
|
||||
#define DTS_SMP_TIME_12_CYCLE (DTS_CFGR1_TS1_SMP_TIME_2 |\
|
||||
DTS_CFGR1_TS1_SMP_TIME_3) /*!< 12 clock cycle for the sampling time */
|
||||
#define DTS_SMP_TIME_13_CYCLE (DTS_CFGR1_TS1_SMP_TIME_0 |\
|
||||
DTS_CFGR1_TS1_SMP_TIME_2 |\
|
||||
DTS_CFGR1_TS1_SMP_TIME_3) /*!< 13 clock cycle for the sampling time */
|
||||
#define DTS_SMP_TIME_14_CYCLE (DTS_CFGR1_TS1_SMP_TIME_1 |\
|
||||
DTS_CFGR1_TS1_SMP_TIME_2 |\
|
||||
DTS_CFGR1_TS1_SMP_TIME_3) /*!< 14 clock cycle for the sampling time */
|
||||
#define DTS_SMP_TIME_15_CYCLE (DTS_CFGR1_TS1_SMP_TIME_0 |\
|
||||
DTS_CFGR1_TS1_SMP_TIME_1 |\
|
||||
DTS_CFGR1_TS1_SMP_TIME_2 |\
|
||||
DTS_CFGR1_TS1_SMP_TIME_3) /*!< 15 clock cycle for the sampling time */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DTS_Flag_Definitions DTS Flag Definitions
|
||||
* @{
|
||||
*/
|
||||
#define DTS_FLAG_TS1_ITE DTS_SR_TS1_ITEF /*!< Interrupt flag for end of measure for DTS1 */
|
||||
#define DTS_FLAG_TS1_ITL DTS_SR_TS1_ITLF /*!< Interrupt flag for low threshold for DTS1 */
|
||||
#define DTS_FLAG_TS1_ITH DTS_SR_TS1_ITHF /*!< Interrupt flag for high threshold for DTS1 */
|
||||
#define DTS_FLAG_TS1_AITE DTS_SR_TS1_AITEF /*!< Asynchronous Interrupt flag for end of measure for DTS1 */
|
||||
#define DTS_FLAG_TS1_AITL DTS_SR_TS1_AITLF /*!< Asynchronous Interrupt flag for low threshold for DTS1 */
|
||||
#define DTS_FLAG_TS1_AITH DTS_SR_TS1_AITHF /*!< Asynchronous Interrupt flag for high threshold for DTS1 */
|
||||
#define DTS_FLAG_TS1_RDY DTS_SR_TS1_RDY /*!< Ready flag for DTS1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DTS_Interrupts_Definitions DTS Interrupts Definitions
|
||||
* @{
|
||||
*/
|
||||
#define DTS_IT_TS1_ITE DTS_ITENR_TS1_ITEEN /*!< Enable interrupt flag for end of measure for DTS1 */
|
||||
#define DTS_IT_TS1_ITL DTS_ITENR_TS1_ITLEN /*!< Enable interrupt flag for low threshold for DTS1 */
|
||||
#define DTS_IT_TS1_ITH DTS_ITENR_TS1_ITHEN /*!< Enable interrupt flag for high threshold for DTS1 */
|
||||
#define DTS_IT_TS1_AITE DTS_ITENR_TS1_AITEEN /*!< Enable asynchronous interrupt flag for end of measure for DTS1 */
|
||||
#define DTS_IT_TS1_AITL DTS_ITENR_TS1_AITLEN /*!< Enable asynchronous interrupt flag for low threshold for DTS1 */
|
||||
#define DTS_IT_TS1_AITH DTS_ITENR_TS1_AITHEN /*!< Enable asynchronous interrupt flag for high threshold for DTS1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported macros ---------------------------------------------------------------------------------------------------*/
|
||||
/** @defgroup DTS_Exported_Macros DTS Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset DTS handle state
|
||||
* @param __HANDLE__ DTS handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1U)
|
||||
#define __HAL_DTS_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_DTS_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else /* USE_HAL_DTS_REGISTER_CALLBACKS */
|
||||
#define __HAL_DTS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DTS_STATE_RESET)
|
||||
#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @brief Enable the specified DTS sensor
|
||||
* @param __HANDLE__ DTS handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DTS_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CFGR1, DTS_CFGR1_TS1_EN)
|
||||
|
||||
/**
|
||||
* @brief Disable the specified DTS sensor
|
||||
* @param __HANDLE__ DTS handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DTS_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR1, DTS_CFGR1_TS1_EN)
|
||||
|
||||
/**
|
||||
* @brief Enable the DTS EXTI line in interrupt mode
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DTS_EXTI_WAKEUP_ENABLE_IT() SET_BIT(EXTI->IMR2, DTS_EXTI_LINE_DTS1)
|
||||
|
||||
/**
|
||||
* @brief Disable the DTS EXTI line in interrupt mode
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DTS_EXTI_WAKEUP_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, DTS_EXTI_LINE_DTS1)
|
||||
|
||||
/**
|
||||
* @brief Enable the DTS EXTI Line in event mode
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DTS_EXTI_WAKEUP_ENABLE_EVENT() SET_BIT(EXTI->EMR2, DTS_EXTI_LINE_DTS1)
|
||||
|
||||
/**
|
||||
* @brief Disable the DTS EXTI Line in event mode
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DTS_EXTI_WAKEUP_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, DTS_EXTI_LINE_DTS1)
|
||||
|
||||
/** @brief Checks whether the specified DTS flag is set or not.
|
||||
* @param __HANDLE__ specifies the DTS Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DTS_FLAG_TS1_ITE : interrupt flag for end of measure for DTS1
|
||||
* @arg DTS_FLAG_TS1_ITL : interrupt flag for low threshold for DTS1
|
||||
* @arg DTS_FLAG_TS1_ITH : interrupt flag for high threshold for DTS1
|
||||
* @arg DTS_FLAG_TS1_AITE: asynchronous interrupt flag for end of measure for DTS1
|
||||
* @arg DTS_FLAG_TS1_AITL: asynchronous interrupt flag for low threshold for DTS1
|
||||
* @arg DTS_FLAG_TS1_AITH: asynchronous interrupt flag for high threshold for DTS1
|
||||
* @arg DTS_FLAG_TS1_RDY : Ready flag for DTS1
|
||||
* @retval The new state of __FLAG__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_DTS_GET_FLAG(__HANDLE__, __FLAG__) \
|
||||
(((((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)))? SET : RESET)
|
||||
|
||||
|
||||
/** @brief Clears the specified DTS pending flag.
|
||||
* @param __HANDLE__ specifies the DTS Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DTS_FLAG_TS1_ITE : interrupt flag for end of measure for DTS1
|
||||
* @arg DTS_FLAG_TS1_ITL : interrupt flag for low threshold for DTS1
|
||||
* @arg DTS_FLAG_TS1_ITH : interrupt flag for high threshold for DTS1
|
||||
* @arg DTS_FLAG_TS1_AITE: asynchronous interrupt flag for end of measure for DTS1
|
||||
* @arg DTS_FLAG_TS1_AITL: asynchronous interrupt flag for low threshold for DTS1
|
||||
* @arg DTS_FLAG_TS1_AITH: asynchronous interrupt flag for high threshold for DTS1
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DTS_CLEAR_FLAG(__HANDLE__, __FLAG__) \
|
||||
((__HANDLE__)->Instance->ICIFR = (__FLAG__))
|
||||
|
||||
|
||||
/** @brief Enable the specified DTS interrupt.
|
||||
* @param __HANDLE__ specifies the DTS Handle.
|
||||
* @param __INTERRUPT__ specifies the DTS interrupt source to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DTS_IT_TS1_ITE : interrupt flag for end of measure for DTS1
|
||||
* @arg DTS_IT_TS1_ITL : interrupt flag for low of measure for DTS1
|
||||
* @arg DTS_IT_TS1_ITH : interrupt flag for high of measure for DTS1
|
||||
* @arg DTS_IT_TS1_AITE : asynchronous interrupt flag for end of measure for DTS1
|
||||
* @arg DTS_IT_TS1_AITL : asynchronous interrupt flag for low of measure for DTS1
|
||||
* @arg DTS_IT_TS1_AITH : asynchronous interrupt flag for high of measure for DTS1
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DTS_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
|
||||
SET_BIT((__HANDLE__)->Instance->ITENR, __INTERRUPT__)
|
||||
|
||||
|
||||
/** @brief Disable the specified DTS interrupt.
|
||||
* @param __HANDLE__ specifies the DTS Handle.
|
||||
* @param __INTERRUPT__ specifies the DTS interrupt source to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DTS_IT_TS1_ITE : interrupt flag for end of measure for DTS1
|
||||
* @arg DTS_IT_TS1_ITL : interrupt flag for low of measure for DTS1
|
||||
* @arg DTS_IT_TS1_ITH : interrupt flag for high of measure for DTS1
|
||||
* @arg DTS_IT_TS1_AITE : asynchronous interrupt flag for end of measure for DTS1
|
||||
* @arg DTS_IT_TS1_AITL : asynchronous interrupt flag for low of measure for DTS1
|
||||
* @arg DTS_IT_TS1_AITH : asynchronous interrupt flag for high of measure for DTS1
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DTS_DISABLE_IT(__HANDLE__,__INTERRUPT__) \
|
||||
CLEAR_BIT((__HANDLE__)->Instance->ITENR, __INTERRUPT__)
|
||||
|
||||
|
||||
/** @brief Check whether the specified DTS interrupt source is enabled or not.
|
||||
* @param __HANDLE__ DTS handle.
|
||||
* @param __INTERRUPT__ DTS interrupt source to check
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DTS_IT_TS1_ITE : interrupt flag for end of measure for DTS1
|
||||
* @arg DTS_IT_TS1_ITL : interrupt flag for low of measure for DTS1
|
||||
* @arg DTS_IT_TS1_ITH : interrupt flag for high of measure for DTS1
|
||||
* @arg DTS_IT_TS1_AITE : asynchronous interrupt flag for end of measure for DTS1
|
||||
* @arg DTS_IT_TS1_AITL : asynchronous interrupt flag for low of measure for DTS1
|
||||
* @arg DTS_IT_TS1_AITH : asynchronous interrupt flag for high of measure for DTS1
|
||||
* @retval State of interruption (SET or RESET)
|
||||
*/
|
||||
#define __HAL_DTS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
|
||||
(( ((__HANDLE__)->Instance->ITENR & (__INTERRUPT__)) == (__INTERRUPT__))? SET : RESET)
|
||||
|
||||
|
||||
/** @brief Check whether the specified DTS REFCLK is selected
|
||||
* @param __HANDLE__ DTS handle.
|
||||
* @param __REFCLK__ DTS reference clock to check
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DTS_REFCLKSEL_LSE: Low speed REF clock
|
||||
* @arg DTS_REFCLKSEL_PCLK: High speed REF clock
|
||||
* @retval State of the REF clock tested (SET or RESET)
|
||||
*/
|
||||
#define __HAL_DTS_GET_REFCLK(__HANDLE__, __REFCLK__) \
|
||||
((((__HANDLE__)->Instance->CFGR1 & (__REFCLK__)) == (__REFCLK__))? SET : RESET)
|
||||
|
||||
/** @brief Get Trigger
|
||||
* @param __HANDLE__ DTS handle.
|
||||
* @retval One of the following trigger
|
||||
* DTS_TRIGGER_HW_NONE : No HW trigger (SW trigger)
|
||||
* DTS_TRIGGER_LPTIMER1: LPTIMER1 trigger
|
||||
* DTS_TRIGGER_LPTIMER2: LPTIMER2 trigger
|
||||
* DTS_TRIGGER_LPTIMER3: LPTIMER3 trigger
|
||||
* DTS_TRIGGER_EXTI13 : EXTI13 trigger
|
||||
*/
|
||||
#define __HAL_DTS_GET_TRIGGER(__HANDLE__) ((__HANDLE__)->Instance->CFGR1 & (DTS_CFGR1_TS1_INTRIG_SEL))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions ------------------------------------------------------------------------------------------------*/
|
||||
/** @addtogroup DTS_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DTS_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions */
|
||||
HAL_StatusTypeDef HAL_DTS_Init(DTS_HandleTypeDef *hdts);
|
||||
HAL_StatusTypeDef HAL_DTS_DeInit(DTS_HandleTypeDef *hdts);
|
||||
void HAL_DTS_MspInit(DTS_HandleTypeDef *hdts);
|
||||
void HAL_DTS_MspDeInit(DTS_HandleTypeDef *hdts);
|
||||
#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1U)
|
||||
HAL_StatusTypeDef HAL_DTS_RegisterCallback(DTS_HandleTypeDef *hdts,
|
||||
HAL_DTS_CallbackIDTypeDef CallbackID,
|
||||
pDTS_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_DTS_UnRegisterCallback(DTS_HandleTypeDef *hdts,
|
||||
HAL_DTS_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup DTS_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions */
|
||||
HAL_StatusTypeDef HAL_DTS_Start(DTS_HandleTypeDef *hdts);
|
||||
HAL_StatusTypeDef HAL_DTS_Stop(DTS_HandleTypeDef *hdts);
|
||||
HAL_StatusTypeDef HAL_DTS_GetTemperature(DTS_HandleTypeDef *hdts, int32_t *Temperature);
|
||||
HAL_StatusTypeDef HAL_DTS_Start_IT(DTS_HandleTypeDef *hdts);
|
||||
HAL_StatusTypeDef HAL_DTS_Stop_IT(DTS_HandleTypeDef *hdts);
|
||||
void HAL_DTS_IRQHandler(DTS_HandleTypeDef *hdts);
|
||||
|
||||
/* Callback in Interrupt mode */
|
||||
void HAL_DTS_EndCallback(DTS_HandleTypeDef *hdts);
|
||||
void HAL_DTS_LowCallback(DTS_HandleTypeDef *hdts);
|
||||
void HAL_DTS_HighCallback(DTS_HandleTypeDef *hdts);
|
||||
void HAL_DTS_AsyncEndCallback(DTS_HandleTypeDef *hdts);
|
||||
void HAL_DTS_AsyncLowCallback(DTS_HandleTypeDef *hdts);
|
||||
void HAL_DTS_AsyncHighCallback(DTS_HandleTypeDef *hdts);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DTS_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
HAL_DTS_StateTypeDef HAL_DTS_GetState(const DTS_HandleTypeDef *hdts);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -----------------------------------------------------------------------------------------------------*/
|
||||
/* Private constants -------------------------------------------------------------------------------------------------*/
|
||||
/** @defgroup DTS_Private_Constants DTS Private Constants
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup DTS_ExtiLine DTS EXTI Lines
|
||||
* @{
|
||||
*/
|
||||
#define DTS_EXTI_LINE_DTS1 (EXTI_IMR3_IM77) /*!< EXTI line 77 connected to DTS1 output */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ----------------------------------------------------------------------------------------------------*/
|
||||
/** @defgroup DTS_Private_Macros DTS Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DTS_IS_DTS_Definitions DTS Private macros to check input parameters
|
||||
* @{
|
||||
*/
|
||||
#define IS_DTS_QUICKMEAS(__SEL__) (((__SEL__) == DTS_QUICKMEAS_DISABLE) || \
|
||||
((__SEL__) == DTS_QUICKMEAS_ENABLE))
|
||||
|
||||
#define IS_DTS_REFCLK(__SEL__) (((__SEL__) == DTS_REFCLKSEL_LSE) || \
|
||||
((__SEL__) == DTS_REFCLKSEL_PCLK))
|
||||
#define IS_DTS_TRIGGERINPUT(__INPUT__) (((__INPUT__) == DTS_TRIGGER_HW_NONE) || \
|
||||
((__INPUT__) == DTS_TRIGGER_LPTIMER4) || \
|
||||
((__INPUT__) == DTS_TRIGGER_LPTIMER2) || \
|
||||
((__INPUT__) == DTS_TRIGGER_LPTIMER3) || \
|
||||
((__INPUT__) == DTS_TRIGGER_EXTI13))
|
||||
|
||||
#define IS_DTS_THRESHOLD(__THRESHOLD__) ((__THRESHOLD__) <= 0xFFFFUL)
|
||||
|
||||
#define IS_DTS_DIVIDER_RATIO_NUMBER(__NUMBER__) ((__NUMBER__) <= 127UL)
|
||||
|
||||
#define IS_DTS_SAMPLINGTIME(__CYCLE__) (((__CYCLE__) == DTS_SMP_TIME_1_CYCLE) || \
|
||||
((__CYCLE__) == DTS_SMP_TIME_2_CYCLE) || \
|
||||
((__CYCLE__) == DTS_SMP_TIME_3_CYCLE) || \
|
||||
((__CYCLE__) == DTS_SMP_TIME_4_CYCLE) || \
|
||||
((__CYCLE__) == DTS_SMP_TIME_5_CYCLE) || \
|
||||
((__CYCLE__) == DTS_SMP_TIME_6_CYCLE) || \
|
||||
((__CYCLE__) == DTS_SMP_TIME_7_CYCLE) || \
|
||||
((__CYCLE__) == DTS_SMP_TIME_8_CYCLE) || \
|
||||
((__CYCLE__) == DTS_SMP_TIME_9_CYCLE) || \
|
||||
((__CYCLE__) == DTS_SMP_TIME_10_CYCLE) || \
|
||||
((__CYCLE__) == DTS_SMP_TIME_11_CYCLE) || \
|
||||
((__CYCLE__) == DTS_SMP_TIME_12_CYCLE) || \
|
||||
((__CYCLE__) == DTS_SMP_TIME_13_CYCLE) || \
|
||||
((__CYCLE__) == DTS_SMP_TIME_14_CYCLE) || \
|
||||
((__CYCLE__) == DTS_SMP_TIME_15_CYCLE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions -------------------------------------------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7RSxx_HAL_DTS_H */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,366 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7rsxx_hal_eth_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of ETH HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7RSxx_HAL_ETH_EX_H
|
||||
#define STM32H7RSxx_HAL_ETH_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(ETH)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7rsxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H7RSxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ETHEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup ETHEx_Exported_Types ETHEx Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief ETH RX VLAN structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
FunctionalState InnerVLANTagInStatus; /*!< Enables or disables Inner VLAN Tag in Rx Status */
|
||||
|
||||
uint32_t StripInnerVLANTag; /*!< Sets the Inner VLAN Tag Stripping on Receive
|
||||
This parameter can be a value of
|
||||
@ref ETHEx_Rx_Inner_VLAN_Tag_Stripping */
|
||||
|
||||
FunctionalState InnerVLANTag; /*!< Enables or disables Inner VLAN Tag */
|
||||
|
||||
FunctionalState DoubleVLANProcessing; /*!< Enable or Disable double VLAN processing */
|
||||
|
||||
FunctionalState VLANTagHashTableMatch; /*!< Enable or Disable VLAN Tag Hash Table Match */
|
||||
|
||||
FunctionalState VLANTagInStatus; /*!< Enable or Disable VLAN Tag in Rx status */
|
||||
|
||||
uint32_t StripVLANTag; /*!< Set the VLAN Tag Stripping on Receive
|
||||
This parameter can be a value of @ref ETHEx_Rx_VLAN_Tag_Stripping */
|
||||
|
||||
uint32_t VLANTypeCheck; /*!< Enable or Disable VLAN Type Check
|
||||
This parameter can be a value of @ref ETHEx_VLAN_Type_Check */
|
||||
|
||||
FunctionalState VLANTagInverceMatch; /*!< Enable or disable VLAN Tag Inverse Match */
|
||||
} ETH_RxVLANConfigTypeDef;
|
||||
/**
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief ETH TX VLAN structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
FunctionalState SourceTxDesc; /*!< Enable or Disable VLAN tag source from DMA tx descriptors */
|
||||
|
||||
FunctionalState SVLANType; /*!< Enable or Disable insertion of SVLAN type */
|
||||
|
||||
uint32_t VLANTagControl; /*!< Sets the VLAN tag control in tx packets
|
||||
This parameter can be a value of @ref ETHEx_VLAN_Tag_Control */
|
||||
} ETH_TxVLANConfigTypeDef;
|
||||
/**
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief ETH L3 filter structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Protocol; /*!< Sets the L3 filter protocol to IPv4 or IPv6
|
||||
This parameter can be a value of @ref ETHEx_L3_Protocol */
|
||||
|
||||
uint32_t SrcAddrFilterMatch; /*!< Sets the L3 filter source address match
|
||||
This parameter can be a value of @ref ETHEx_L3_Source_Match */
|
||||
|
||||
uint32_t DestAddrFilterMatch; /*!< Sets the L3 filter destination address match
|
||||
This parameter can be a value of @ref ETHEx_L3_Destination_Match */
|
||||
|
||||
uint32_t SrcAddrHigherBitsMatch; /*!< Sets the L3 filter source address higher bits match
|
||||
This parameter can be a value from 0 to 31 */
|
||||
|
||||
uint32_t DestAddrHigherBitsMatch; /*!< Sets the L3 filter destination address higher bits match
|
||||
This parameter can be a value from 0 to 31 */
|
||||
|
||||
uint32_t Ip4SrcAddr; /*!< Sets the L3 filter IPv4 source address if IPv4 protocol is used
|
||||
This parameter can be a value from 0x0 to 0xFFFFFFFF */
|
||||
|
||||
uint32_t Ip4DestAddr; /*!< Sets the L3 filter IPv4 destination address if IPv4 protocol is used
|
||||
This parameter can be a value from 0 to 0xFFFFFFFF */
|
||||
|
||||
uint32_t Ip6Addr[4]; /*!< Sets the L3 filter IPv6 address if IPv6 protocol is used
|
||||
This parameter must be a table of 4 words (4* 32 bits) */
|
||||
} ETH_L3FilterConfigTypeDef;
|
||||
/**
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief ETH L4 filter structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Protocol; /*!< Sets the L4 filter protocol to TCP or UDP
|
||||
This parameter can be a value of @ref ETHEx_L4_Protocol */
|
||||
|
||||
uint32_t SrcPortFilterMatch; /*!< Sets the L4 filter source port match
|
||||
This parameter can be a value of @ref ETHEx_L4_Source_Match */
|
||||
|
||||
uint32_t DestPortFilterMatch; /*!< Sets the L4 filter destination port match
|
||||
This parameter can be a value of @ref ETHEx_L4_Destination_Match */
|
||||
|
||||
uint32_t SourcePort; /*!< Sets the L4 filter source port
|
||||
This parameter must be a value from 0x0 to 0xFFFF */
|
||||
|
||||
uint32_t DestinationPort; /*!< Sets the L4 filter destination port
|
||||
This parameter must be a value from 0x0 to 0xFFFF */
|
||||
} ETH_L4FilterConfigTypeDef;
|
||||
/**
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup ETHEx_Exported_Constants ETHEx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup ETHEx_LPI_Event ETHEx LPI Event
|
||||
* @{
|
||||
*/
|
||||
#define ETH_TX_LPI_ENTRY ETH_MACLCSR_TLPIEN
|
||||
#define ETH_TX_LPI_EXIT ETH_MACLCSR_TLPIEX
|
||||
#define ETH_RX_LPI_ENTRY ETH_MACLCSR_RLPIEN
|
||||
#define ETH_RX_LPI_EXIT ETH_MACLCSR_RLPIEX
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ETHEx_L3_Filter ETHEx L3 Filter
|
||||
* @{
|
||||
*/
|
||||
#define ETH_L3_FILTER_0 0x00000000U
|
||||
#define ETH_L3_FILTER_1 0x0000000CU
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ETHEx_L4_Filter ETHEx L4 Filter
|
||||
* @{
|
||||
*/
|
||||
#define ETH_L4_FILTER_0 0x00000000U
|
||||
#define ETH_L4_FILTER_1 0x0000000CU
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ETHEx_L3_Protocol ETHEx L3 Protocol
|
||||
* @{
|
||||
*/
|
||||
#define ETH_L3_IPV6_MATCH ETH_MACL3L4CR_L3PEN
|
||||
#define ETH_L3_IPV4_MATCH 0x00000000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ETHEx_L3_Source_Match ETHEx L3 Source Match
|
||||
* @{
|
||||
*/
|
||||
#define ETH_L3_SRC_ADDR_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L3SAM
|
||||
#define ETH_L3_SRC_ADDR_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L3SAM | ETH_MACL3L4CR_L3SAIM)
|
||||
#define ETH_L3_SRC_ADDR_MATCH_DISABLE 0x00000000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ETHEx_L3_Destination_Match ETHEx L3 Destination Match
|
||||
* @{
|
||||
*/
|
||||
#define ETH_L3_DEST_ADDR_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L3DAM
|
||||
#define ETH_L3_DEST_ADDR_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L3DAM | ETH_MACL3L4CR_L3DAIM)
|
||||
#define ETH_L3_DEST_ADDR_MATCH_DISABLE 0x00000000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ETHEx_L4_Protocol ETHEx L4 Protocol
|
||||
* @{
|
||||
*/
|
||||
#define ETH_L4_UDP_MATCH ETH_MACL3L4CR_L4PEN
|
||||
#define ETH_L4_TCP_MATCH 0x00000000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ETHEx_L4_Source_Match ETHEx L4 Source Match
|
||||
* @{
|
||||
*/
|
||||
#define ETH_L4_SRC_PORT_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L4SPM
|
||||
#define ETH_L4_SRC_PORT_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L4SPM |ETH_MACL3L4CR_L4SPIM)
|
||||
#define ETH_L4_SRC_PORT_MATCH_DISABLE 0x00000000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ETHEx_L4_Destination_Match ETHEx L4 Destination Match
|
||||
* @{
|
||||
*/
|
||||
#define ETH_L4_DEST_PORT_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L4DPM
|
||||
#define ETH_L4_DEST_PORT_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM)
|
||||
#define ETH_L4_DEST_PORT_MATCH_DISABLE 0x00000000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ETHEx_Rx_Inner_VLAN_Tag_Stripping ETHEx Rx Inner VLAN Tag Stripping
|
||||
* @{
|
||||
*/
|
||||
#define ETH_INNERVLANTAGRXSTRIPPING_NONE ETH_MACVTR_EIVLS_DONOTSTRIP
|
||||
#define ETH_INNERVLANTAGRXSTRIPPING_IFPASS ETH_MACVTR_EIVLS_STRIPIFPASS
|
||||
#define ETH_INNERVLANTAGRXSTRIPPING_IFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS
|
||||
#define ETH_INNERVLANTAGRXSTRIPPING_ALWAYS ETH_MACVTR_EIVLS_ALWAYSSTRIP
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ETHEx_Rx_VLAN_Tag_Stripping ETHEx Rx VLAN Tag Stripping
|
||||
* @{
|
||||
*/
|
||||
#define ETH_VLANTAGRXSTRIPPING_NONE ETH_MACVTR_EVLS_DONOTSTRIP
|
||||
#define ETH_VLANTAGRXSTRIPPING_IFPASS ETH_MACVTR_EVLS_STRIPIFPASS
|
||||
#define ETH_VLANTAGRXSTRIPPING_IFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS
|
||||
#define ETH_VLANTAGRXSTRIPPING_ALWAYS ETH_MACVTR_EVLS_ALWAYSSTRIP
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ETHEx_VLAN_Type_Check ETHEx VLAN Type Check
|
||||
* @{
|
||||
*/
|
||||
#define ETH_VLANTYPECHECK_DISABLE ETH_MACVTR_DOVLTC
|
||||
#define ETH_VLANTYPECHECK_SVLAN (ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL)
|
||||
#define ETH_VLANTYPECHECK_CVLAN 0x00000000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ETHEx_VLAN_Tag_Control ETHEx_VLAN_Tag_Control
|
||||
* @{
|
||||
*/
|
||||
#define ETH_VLANTAGCONTROL_NONE (ETH_MACVIR_VLP | ETH_MACVIR_VLC_NOVLANTAG)
|
||||
#define ETH_VLANTAGCONTROL_DELETE (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGDELETE)
|
||||
#define ETH_VLANTAGCONTROL_INSERT (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGINSERT)
|
||||
#define ETH_VLANTAGCONTROL_REPLACE (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGREPLACE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ETHEx_Tx_VLAN_Tag ETHEx Tx VLAN Tag
|
||||
* @{
|
||||
*/
|
||||
#define ETH_INNER_TX_VLANTAG 0x00000001U
|
||||
#define ETH_OUTER_TX_VLANTAG 0x00000000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup ETHEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ETHEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* MAC ARP Offloading APIs ***************************************************/
|
||||
void HAL_ETHEx_EnableARPOffload(ETH_HandleTypeDef *heth);
|
||||
void HAL_ETHEx_DisableARPOffload(ETH_HandleTypeDef *heth);
|
||||
void HAL_ETHEx_SetARPAddressMatch(ETH_HandleTypeDef *heth, uint32_t IpAddress);
|
||||
|
||||
/* MAC L3 L4 Filtering APIs ***************************************************/
|
||||
void HAL_ETHEx_EnableL3L4Filtering(ETH_HandleTypeDef *heth);
|
||||
void HAL_ETHEx_DisableL3L4Filtering(ETH_HandleTypeDef *heth);
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(const ETH_HandleTypeDef *heth, uint32_t Filter,
|
||||
ETH_L3FilterConfigTypeDef *pL3FilterConfig);
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(const ETH_HandleTypeDef *heth, uint32_t Filter,
|
||||
ETH_L4FilterConfigTypeDef *pL4FilterConfig);
|
||||
HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
|
||||
const ETH_L3FilterConfigTypeDef *pL3FilterConfig);
|
||||
HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
|
||||
const ETH_L4FilterConfigTypeDef *pL4FilterConfig);
|
||||
|
||||
/* MAC VLAN Processing APIs ************************************************/
|
||||
void HAL_ETHEx_EnableVLANProcessing(ETH_HandleTypeDef *heth);
|
||||
void HAL_ETHEx_DisableVLANProcessing(ETH_HandleTypeDef *heth);
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(const ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig);
|
||||
HAL_StatusTypeDef HAL_ETHEx_SetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig);
|
||||
void HAL_ETHEx_SetVLANHashTable(ETH_HandleTypeDef *heth, uint32_t VLANHashTable);
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(const ETH_HandleTypeDef *heth, uint32_t VLANTag,
|
||||
ETH_TxVLANConfigTypeDef *pVlanConfig);
|
||||
HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag,
|
||||
const ETH_TxVLANConfigTypeDef *pVlanConfig);
|
||||
void HAL_ETHEx_SetTxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t VLANTag, uint32_t VLANIdentifier);
|
||||
|
||||
/* Energy Efficient Ethernet APIs *********************************************/
|
||||
void HAL_ETHEx_EnterLPIMode(ETH_HandleTypeDef *heth, FunctionalState TxAutomate,
|
||||
FunctionalState TxClockStop);
|
||||
void HAL_ETHEx_ExitLPIMode(ETH_HandleTypeDef *heth);
|
||||
uint32_t HAL_ETHEx_GetMACLPIEvent(const ETH_HandleTypeDef *heth);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* ETH */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7RSxx_HAL_ETH_EX_H */
|
||||
|
|
@ -1,347 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7rsxx_hal_exti.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of EXTI HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7RSxx_HAL_EXTI_H
|
||||
#define STM32H7RSxx_HAL_EXTI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7rsxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H7RSxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI EXTI
|
||||
* @brief EXTI HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup EXTI_Exported_Types EXTI Exported Types
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_EXTI_COMMON_CB_ID = 0x00U,
|
||||
} EXTI_CallbackIDTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief EXTI Handle structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Line; /*!< Exti line number */
|
||||
void (* PendingCallback)(void); /*!< Exti pending callback */
|
||||
} EXTI_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @brief EXTI Configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Line; /*!< The Exti line to be configured. This parameter
|
||||
can be a value of @ref EXTI_Line */
|
||||
uint32_t Mode; /*!< The Exit Mode to be configured for a core.
|
||||
This parameter can be a combination of @ref EXTI_Mode */
|
||||
uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter
|
||||
can be a value of @ref EXTI_Trigger */
|
||||
uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured.
|
||||
This parameter is only possible for line 0 to 15. It
|
||||
can be a value of @ref EXTI_GPIOSel */
|
||||
} EXTI_ConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Line EXTI Line
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u)
|
||||
#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u)
|
||||
#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u)
|
||||
#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u)
|
||||
#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u)
|
||||
#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u)
|
||||
#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u)
|
||||
#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u)
|
||||
#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u)
|
||||
#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u)
|
||||
#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au)
|
||||
#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu)
|
||||
#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu)
|
||||
#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du)
|
||||
#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu)
|
||||
#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu)
|
||||
#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u)
|
||||
#define EXTI_LINE_17 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x11u)
|
||||
#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u)
|
||||
#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u)
|
||||
#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u)
|
||||
#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u)
|
||||
#define EXTI_LINE_22 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x16u)
|
||||
#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u)
|
||||
#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u)
|
||||
#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u)
|
||||
#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au)
|
||||
#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu)
|
||||
#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu)
|
||||
#define EXTI_LINE_29 (EXTI_RESERVED | EXTI_REG1 | 0x1Du)
|
||||
#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Eu)
|
||||
#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu)
|
||||
#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u)
|
||||
#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u)
|
||||
#define EXTI_LINE_34 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x02u)
|
||||
#define EXTI_LINE_35 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x03u)
|
||||
#define EXTI_LINE_36 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x04u)
|
||||
#define EXTI_LINE_37 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x05u)
|
||||
#define EXTI_LINE_38 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x06u)
|
||||
#define EXTI_LINE_39 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x07u)
|
||||
#define EXTI_LINE_40 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x08u)
|
||||
#define EXTI_LINE_41 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x09u)
|
||||
#define EXTI_LINE_42 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x0Au)
|
||||
#define EXTI_LINE_43 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x0Bu)
|
||||
#define EXTI_LINE_44 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x0Cu)
|
||||
#define EXTI_LINE_45 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x0Du)
|
||||
#define EXTI_LINE_46 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x0Eu)
|
||||
#define EXTI_LINE_47 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x0Fu)
|
||||
#define EXTI_LINE_48 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x10u)
|
||||
#define EXTI_LINE_49 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x11u)
|
||||
#define EXTI_LINE_50 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x12u)
|
||||
#define EXTI_LINE_51 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x13u)
|
||||
#define EXTI_LINE_52 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x14u)
|
||||
#define EXTI_LINE_53 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x15u)
|
||||
#define EXTI_LINE_54 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x16u)
|
||||
#define EXTI_LINE_55 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x17u)
|
||||
#define EXTI_LINE_56 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x18u)
|
||||
#define EXTI_LINE_57 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x19u)
|
||||
#define EXTI_LINE_58 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x1Au)
|
||||
#define EXTI_LINE_59 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x1Bu)
|
||||
#define EXTI_LINE_77 (EXTI_DIRECT | EXTI_REG3 | EXTI_EVENT | 0x0Du)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Mode EXTI Mode
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_MODE_NONE 0x00000000u
|
||||
#define EXTI_MODE_INTERRUPT 0x00000001u
|
||||
#define EXTI_MODE_EVENT 0x00000002u
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Trigger EXTI Trigger
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_TRIGGER_NONE 0x00000000u
|
||||
#define EXTI_TRIGGER_RISING 0x00000001u
|
||||
#define EXTI_TRIGGER_FALLING 0x00000002u
|
||||
#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_GPIOSel EXTI GPIOSel
|
||||
* @brief
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_GPIOA 0x00000000u
|
||||
#define EXTI_GPIOB 0x00000001u
|
||||
#define EXTI_GPIOC 0x00000002u
|
||||
#define EXTI_GPIOD 0x00000003u
|
||||
#define EXTI_GPIOE 0x00000004u
|
||||
#define EXTI_GPIOF 0x00000005u
|
||||
#define EXTI_GPIOG 0x00000006u
|
||||
#define EXTI_GPIOH 0x00000007u
|
||||
#define EXTI_GPIOM 0x0000000Cu
|
||||
#define EXTI_GPION 0x0000000Du
|
||||
#define EXTI_GPIOO 0x0000000Eu
|
||||
#define EXTI_GPIOP 0x0000000Fu
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants --------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Private_Constants EXTI Private Constants
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief EXTI Line property definition
|
||||
*/
|
||||
#define EXTI_PROPERTY_SHIFT 24u
|
||||
#define EXTI_DIRECT (0x01uL << EXTI_PROPERTY_SHIFT)
|
||||
#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)
|
||||
#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
|
||||
#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT)
|
||||
#define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
|
||||
|
||||
/**
|
||||
* @brief EXTI Event presence definition
|
||||
*/
|
||||
#define EXTI_EVENT_PRESENCE_SHIFT 28u
|
||||
#define EXTI_EVENT (0x01uL << EXTI_EVENT_PRESENCE_SHIFT)
|
||||
#define EXTI_EVENT_PRESENCE_MASK (EXTI_EVENT)
|
||||
|
||||
/**
|
||||
* @brief EXTI Register and bit usage
|
||||
*/
|
||||
#define EXTI_REG_SHIFT 16u
|
||||
#define EXTI_REG1 (0x00uL << EXTI_REG_SHIFT)
|
||||
#define EXTI_REG2 (0x01uL << EXTI_REG_SHIFT)
|
||||
#define EXTI_REG3 (0x02uL << EXTI_REG_SHIFT)
|
||||
#define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2 | EXTI_REG3)
|
||||
#define EXTI_PIN_MASK 0x0000001Fu
|
||||
|
||||
/**
|
||||
* @brief EXTI Mask for interrupt & event mode
|
||||
*/
|
||||
#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
|
||||
|
||||
/**
|
||||
* @brief EXTI Mask for trigger possibilities
|
||||
*/
|
||||
#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
|
||||
|
||||
/**
|
||||
* @brief EXTI Line number
|
||||
*/
|
||||
#define EXTI_LINE_NB 78u
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Private_Macros EXTI Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_EVENT_PRESENCE_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00u) && \
|
||||
((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \
|
||||
(((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
|
||||
(((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
|
||||
((((__LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \
|
||||
(((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u))) || \
|
||||
(((__LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x0002000DUL)))
|
||||
|
||||
#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00u) && \
|
||||
(((__LINE__) & ~EXTI_MODE_MASK) == 0x00u))
|
||||
|
||||
#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
|
||||
|
||||
#define IS_EXTI_PENDING_EDGE(__LINE__) ((__LINE__) == EXTI_TRIGGER_RISING_FALLING)
|
||||
|
||||
#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u)
|
||||
|
||||
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
|
||||
((__PORT__) == EXTI_GPIOB) || \
|
||||
((__PORT__) == EXTI_GPIOC) || \
|
||||
((__PORT__) == EXTI_GPIOD) || \
|
||||
((__PORT__) == EXTI_GPIOE) || \
|
||||
((__PORT__) == EXTI_GPIOF) || \
|
||||
((__PORT__) == EXTI_GPIOG) || \
|
||||
((__PORT__) == EXTI_GPIOH) || \
|
||||
((__PORT__) == EXTI_GPIOM) || \
|
||||
((__PORT__) == EXTI_GPION) || \
|
||||
((__PORT__) == EXTI_GPIOO) || \
|
||||
((__PORT__) == EXTI_GPIOP))
|
||||
|
||||
#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
|
||||
* @brief EXTI Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
|
||||
* @brief Configuration functions
|
||||
* @{
|
||||
*/
|
||||
/* Configuration functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
|
||||
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
|
||||
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(const EXTI_HandleTypeDef *hexti);
|
||||
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
|
||||
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
|
||||
* @brief IO operation functions
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
void HAL_EXTI_IRQHandler(const EXTI_HandleTypeDef *hexti);
|
||||
uint32_t HAL_EXTI_GetPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge);
|
||||
void HAL_EXTI_ClearPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge);
|
||||
void HAL_EXTI_GenerateSWI(const EXTI_HandleTypeDef *hexti);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7RSxx_HAL_EXTI_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,831 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7rsxx_hal_flash.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of FLASH HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7RSxx_HAL_FLASH_H
|
||||
#define STM32H7RSxx_HAL_FLASH_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7rsxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H7RSxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Types FLASH Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FLASH Erase structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t TypeErase; /*!< Mass erase or page erase.
|
||||
This parameter can be a value of @ref FLASH_Type_Erase */
|
||||
uint32_t Sector; /*!< Initial Flash sector to erase when sector erase is enabled
|
||||
This parameter must be a value between 0 and (max number of sector - 1)
|
||||
(eg : 15 for 128KB single bank) */
|
||||
uint32_t NbSectors; /*!< Number of sectors to be erased.
|
||||
This parameter must be a value between 1 and
|
||||
(max number of sectors - value of initial page)*/
|
||||
} FLASH_EraseInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FLASH Option Bytes Program structure definition
|
||||
*/
|
||||
#define FLASH_KEY_DATA_NB_REG (8U) /*!< 8 Key data registers */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t OptionType; /*!< Option byte to be configured.
|
||||
This parameter can be a combination of the values of @ref FLASH_OB_TYPE */
|
||||
uint32_t WRPState; /*!< Write protection activation or deactivation (used for OPTIONBYTE_WRP).
|
||||
This parameter can be value of @ref FLASH_OB_WRP_STATE */
|
||||
uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected (used for OPTIONBYTE_WRP).
|
||||
The value of this parameter depend on device used within the same series */
|
||||
uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER).
|
||||
This parameter can be a combination of @ref FLASH_OB_USER_TYPE */
|
||||
uint32_t USERConfig1; /*!< Value of the user option byte (used for OPTIONBYTE_USER).
|
||||
This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEV,
|
||||
@ref FLASH_OB_USER_IWDG_SW, @ref FLASH_OB_USER_nRST_STOP,
|
||||
@ref FLASH_OB_USER_nRST_STDBY, @ref FLASH_OB_USER_XSPI1_HSLV,
|
||||
@ref FLASH_OB_USER_XSPI2_HSLV, @ref FLASH_OB_USER_IWDG_STOP,
|
||||
@ref FLASH_OB_USER_IWDG_STANDBY, @ref FLASH_OB_USER_VDDIO_HSLV */
|
||||
uint32_t USERConfig2; /*!< Value of the user option byte (used for OPTIONBYTE_USER).
|
||||
This parameter can be a combination of @ref FLASH_OB_USER_ITCM_AXI_SHARE,
|
||||
@ref FLASH_OB_USER_DTCM_AXI_SHARE, @ref FLASH_OB_USER_ECC_ON_SRAM,
|
||||
@ref FLASH_OB_USER_I2C_NI3C */
|
||||
uint32_t HDPStartPage; /*!< Start address that contains the first 256-byte block of HDP area (used for OPTIONBYTE_HDP).
|
||||
This parameter must be a value between 0 or 0xFFF */
|
||||
uint32_t HDPEndPage; /*!< End address that contains the last 256-byte block of HDP area (used for OPTIONBYTE_HDP).
|
||||
This parameter must be a value between 0 or 0xFFF */
|
||||
uint32_t NVState; /*!< Value of the non-volatile state (used for OPTIONBYTE_NV).
|
||||
This parameter must be a value of @ref FLASH_OB_NVSTATE */
|
||||
uint32_t ROTConfig; /*!< Value of the RoT status (only used for read configuration).
|
||||
This parameter can be a combination of @ref FLASH_OB_ROT_OEM_PROVD,
|
||||
@ref FLASH_OB_ROT_DBG_AUTH, @ref FLASH_OB_ROT_IROT_SELECT */
|
||||
uint32_t EPOCH; /*!< Value of the epoch (only used for read configuration).
|
||||
This parameter must be a value between 0x0 and 0xFFFFFF */
|
||||
} FLASH_OBProgramInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FLASH handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
HAL_LockTypeDef Lock; /* FLASH locking object */
|
||||
uint32_t ErrorCode; /* FLASH error code */
|
||||
uint32_t ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT
|
||||
context */
|
||||
uint32_t Address; /* Internal variable to save address selected for program in IT context */
|
||||
uint32_t Sector; /* Internal variable to define the current sector which is being erased in
|
||||
IT context */
|
||||
uint32_t NbSectorsToErase; /* Internal variable to save the remaining sectors to erase in IT context */
|
||||
} FLASH_ProcessTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Flags FLASH Flags Definition
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_FLAG_EOP FLASH_ISR_EOPF /*!< FLASH End of program flag */
|
||||
#define FLASH_FLAG_WRPERR FLASH_ISR_WRPERRF /*!< FLASH Write protection error flag */
|
||||
#define FLASH_FLAG_PGSERR FLASH_ISR_PGSERRF /*!< FLASH Programming sequence error flag */
|
||||
#define FLASH_FLAG_STRBERR FLASH_ISR_STRBERRF /*!< FLASH Strobe error flag */
|
||||
#define FLASH_FLAG_OBLERR FLASH_ISR_OBLERRF /*!< FLASH Option byte loading error flag */
|
||||
#define FLASH_FLAG_INCERR FLASH_ISR_INCERRF /*!< FLASH Inconsistency error flag */
|
||||
#define FLASH_FLAG_RDSERR FLASH_ISR_RDSERRF /*!< FLASH Read security error flag */
|
||||
#define FLASH_FLAG_SNECCERR FLASH_ISR_SNECCERRF /*!< FLASH ECC single error flag */
|
||||
#define FLASH_FLAG_DBECCERR FLASH_ISR_DBECCERRF /*!< FLASH ECC double error flag */
|
||||
#define FLASH_FLAG_CRCEND FLASH_ISR_CRCENDF /*!< FLASH CRC end of calculation flag */
|
||||
#define FLASH_FLAG_CRCERR FLASH_ISR_CRCRDERRF /*!< FLASH CRC error flag */
|
||||
#define FLASH_FLAG_KVERR FLASH_OPTISR_KVEF /*!< FLASH Key valid error flag */
|
||||
#define FLASH_FLAG_KTERR FLASH_OPTISR_KTEF /*!< FLASH Key transfer error flag */
|
||||
#define FLASH_FLAG_OPTERR FLASH_OPTISR_OPTERRF /*!< FLASH Options byte change error flag */
|
||||
|
||||
#define FLASH_FLAG_ISR_ERRORS (FLASH_FLAG_WRPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_STRBERR | \
|
||||
FLASH_FLAG_OBLERR | FLASH_FLAG_INCERR | FLASH_FLAG_RDSERR | \
|
||||
FLASH_FLAG_CRCERR)
|
||||
#define FLASH_FLAG_ECC_ERRORS (FLASH_FLAG_SNECCERR | FLASH_FLAG_DBECCERR)
|
||||
#define FLASH_FLAG_OPTISR_ERRORS (FLASH_FLAG_KVERR | FLASH_FLAG_KTERR | FLASH_FLAG_OPTERR)
|
||||
#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_ISR_ERRORS | FLASH_FLAG_ECC_ERRORS | FLASH_FLAG_OPTISR_ERRORS)
|
||||
|
||||
#define FLASH_FLAG_ISR_FLAGS (FLASH_FLAG_ISR_ERRORS | FLASH_FLAG_ECC_ERRORS | FLASH_FLAG_EOP)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Interrupt_definition FLASH Interrupts Definition
|
||||
* @brief FLASH Interrupt definition
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_IT_EOP FLASH_IER_EOPIE /*!< End of program interrupt source */
|
||||
#define FLASH_IT_WRPERR FLASH_IER_WRPERRIE /*!< FLASH Write protection error interrupt source */
|
||||
#define FLASH_IT_PGSERR FLASH_IER_PGSERRIE /*!< FLASH Programming sequence error interrupt source */
|
||||
#define FLASH_IT_STRBERR FLASH_IER_STRBERRIE /*!< FLASH Strobe error interrupt source */
|
||||
#define FLASH_IT_OBLERR FLASH_IER_OBLERRIE /*!< FLASH Option byte loading error interrupt source */
|
||||
#define FLASH_IT_INCERR FLASH_IER_INCERRIE /*!< FLASH Inconsistency error interrupt source */
|
||||
#define FLASH_IT_RDSERR FLASH_IER_RDSERRIE /*!< FLASH Read security error interrupt source */
|
||||
#define FLASH_IT_SNECCERR FLASH_IER_SNECCERRIE /*!< FLASH ECC single error interrupt source */
|
||||
#define FLASH_IT_DBECCERR FLASH_IER_DBECCERRIE /*!< FLASH ECC double error interrupt source */
|
||||
#define FLASH_IT_CRCEND FLASH_IER_CRCENDIE /*!< FLASH CRC end of calculation interrupt source */
|
||||
#define FLASH_IT_CRCERR FLASH_IER_CRCRDERRIE /*!< FLASH CRC error interrupt source */
|
||||
#define FLASH_IT_KVERR FLASH_OPTCR_KVEIE /*!< FLASH Key valid error interrupt source */
|
||||
#define FLASH_IT_KTERR FLASH_OPTCR_KTEIE /*!< FLASH Key transfer error interrupt source */
|
||||
#define FLASH_IT_OPTERR FLASH_OPTCR_OPTERRIE /*!< FLASH Options byte change error interrupt source */
|
||||
|
||||
#define FLASH_IT_IER (FLASH_IT_EOP | FLASH_IT_WRPERR | FLASH_IT_PGSERR | FLASH_IT_STRBERR | \
|
||||
FLASH_IT_OBLERR | FLASH_IT_INCERR | FLASH_IT_RDSERR | FLASH_IT_SNECCERR | \
|
||||
FLASH_IT_DBECCERR | FLASH_IT_CRCEND | FLASH_IT_CRCERR)
|
||||
#define FLASH_IT_OPTCR (FLASH_IT_KVERR | FLASH_IT_KTERR | FLASH_IT_OPTERR)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Error FLASH Error
|
||||
* @{
|
||||
*/
|
||||
#define HAL_FLASH_ERROR_NONE 0x00000000U
|
||||
#define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR
|
||||
#define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR
|
||||
#define HAL_FLASH_ERROR_STRB FLASH_FLAG_STRBERR
|
||||
#define HAL_FLASH_ERROR_OBL FLASH_FLAG_OBLERR
|
||||
#define HAL_FLASH_ERROR_INC FLASH_FLAG_INCERR
|
||||
#define HAL_FLASH_ERROR_RDS FLASH_FLAG_RDSERR
|
||||
#define HAL_FLASH_ERROR_SNECC FLASH_FLAG_SNECCERR
|
||||
#define HAL_FLASH_ERROR_DBECC FLASH_FLAG_DBECCERR
|
||||
#define HAL_FLASH_ERROR_CRC FLASH_FLAG_CRCERR
|
||||
#define HAL_FLASH_ERROR_KV FLASH_FLAG_KVERR
|
||||
#define HAL_FLASH_ERROR_KT FLASH_FLAG_KTERR
|
||||
#define HAL_FLASH_ERROR_OPT FLASH_FLAG_OPTERR
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Type_Erase FLASH Erase Type
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_TYPEERASE_SECTORS FLASH_CR_SER /*!< Sectors erase activation */
|
||||
#define FLASH_TYPEERASE_MASSERASE FLASH_CR_BER /*!< Flash mass erase activation */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Type_Program FLASH Program Type
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_TYPEPROGRAM_BYTE (FLASH_CR_PG | FLASH_CR_FW) /*!< Program a byte (8-bit) at a specified address */
|
||||
#define FLASH_TYPEPROGRAM_HALFWORD (FLASH_HALFWORD_MASK | FLASH_CR_PG | FLASH_CR_FW) /*!< Program a half-word (16-bit) at a specified address */
|
||||
#define FLASH_TYPEPROGRAM_WORD (FLASH_WORD_MASK | FLASH_CR_PG | FLASH_CR_FW) /*!< Program a word (32-bit) at a specified address */
|
||||
#define FLASH_TYPEPROGRAM_DOUBLEWORD (FLASH_DOUBLEWORD_MASK | FLASH_CR_PG | FLASH_CR_FW) /*!< Program a double-word (64-bit) at a specified address */
|
||||
#define FLASH_TYPEPROGRAM_QUADWORD (FLASH_CR_PG) /*!< Program a quad-word (128-bit) at a specified address */
|
||||
#define FLASH_TYPEPROGRAM_OTP_HALFWORD (FLASH_HALFWORD_MASK | FLASH_CR_PG_OTP | FLASH_CR_FW) /*!< Program a half-word (16-bit) at a OTP address */
|
||||
#define FLASH_TYPEPROGRAM_OTP_WORD (FLASH_WORD_MASK | FLASH_CR_PG_OTP | FLASH_CR_FW) /*!< Program a word (32-bit) at a OTP address */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_TYPE FLASH Option Bytes Type
|
||||
* @{
|
||||
*/
|
||||
#define OPTIONBYTE_WRP 0x00000001U /*!< WRP option byte configuration */
|
||||
#define OPTIONBYTE_USER 0x00000002U /*!< User option byte configuration */
|
||||
#define OPTIONBYTE_HDP 0x00000004U /*!< HDP option byte configuration */
|
||||
#define OPTIONBYTE_NV 0x00000008U /*!< Non-Volatile State option byte configuration */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_WRP_STATE FLASH Option Bytes WRP State
|
||||
* @{
|
||||
*/
|
||||
#define OB_WRPSTATE_DISABLE 0x00000000U /*!< Disable the write protection of the desired sectors */
|
||||
#define OB_WRPSTATE_ENABLE 0x00000001U /*!< Enable the write protection of the desired sectors */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_TYPE FLASH Option Bytes User Type
|
||||
* @{
|
||||
*/
|
||||
#define OB_USER_BOR_LEV 0x00000001U /*!< Brownout level */
|
||||
#define OB_USER_IWDG_SW 0x00000002U /*!< IWDG control mode */
|
||||
#define OB_USER_NRST_STOP 0x00000004U /*!< Stop entry reset */
|
||||
#define OB_USER_NRST_STDBY 0x00000008U /*!< Standby entry reset */
|
||||
#define OB_USER_XSPI1_HSLV 0x00000010U /*!< XSPI1 High-speed at low voltage */
|
||||
#define OB_USER_XSPI2_HSLV 0x00000020U /*!< XSPI2 High-speed at low voltage */
|
||||
#define OB_USER_IWDG_STOP 0x00000040U /*!< IWDG Stop mode freeze */
|
||||
#define OB_USER_IWDG_STDBY 0x00000080U /*!< IWDG Standby mode freeze */
|
||||
#define OB_USER_VDDIO_HSLV 0x00000100U /*!< I/O High-speed at low voltage */
|
||||
#define OB_USER_ITCM_AXI_SHARE 0x00000200U /*!< ITCM AXI share */
|
||||
#define OB_USER_DTCM_AXI_SHARE 0x00000400U /*!< DTCM AXI share */
|
||||
#define OB_USER_SRAM_ECC 0x00000800U /*!< ECC on SRAM */
|
||||
#define OB_USER_I2C_NI3C 0x00001000U /*!< I2C Not I3C */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_BOR_LEV FLASH Option Bytes User BOR Level
|
||||
* @{
|
||||
*/
|
||||
#define OB_BOR_LEVEL_0 0x00000000U /*!< BOR OFF, POR/PDR reset threshold level is applied */
|
||||
#define OB_BOR_LEVEL_1 FLASH_OBW1SRP_BOR_LEVEL_0 /*!< BOR Level 1, the threshold level is low (around 2.1 V) */
|
||||
#define OB_BOR_LEVEL_2 FLASH_OBW1SRP_BOR_LEVEL_1 /*!< BOR Level 2, the threshold level is medium (around 2.4 V) */
|
||||
#define OB_BOR_LEVEL_3 FLASH_OBW1SRP_BOR_LEVEL /*!< BOR Level 3, the threshold level is high (around 2.7 V) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG control mode
|
||||
* @{
|
||||
*/
|
||||
#define OB_IWDG_HW 0x00000000U /*!< IWDG watchdog is controlled by hardware */
|
||||
#define OB_IWDG_SW FLASH_OBW1SRP_IWDG_HW /*!< IWDG watchdog is controlled by software */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User stop entry reset
|
||||
* @{
|
||||
*/
|
||||
#define OB_STOP_RST 0x00000000U /*!< Reset generated when entering stop mode */
|
||||
#define OB_STOP_NORST FLASH_OBW1SRP_NRST_STOP /*!< No reset generated when entering stop mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_nRST_STDBY FLASH Option Bytes User standby entry reset
|
||||
* @{
|
||||
*/
|
||||
#define OB_STANDBY_RST 0x00000000U /*!< Reset generated when entering standby mode */
|
||||
#define OB_STANDBY_NORST FLASH_OBW1SRP_NRST_STBY /*!< No reset generated when entering standby mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_XSPI1_HSLV FLASH Option Bytes User XSPI 1 High-Speed at Low-Voltage
|
||||
* @{
|
||||
*/
|
||||
#define OB_XSPI1_HSLV_DISABLE 0x00000000U /*!< I/O speed optimization at low-voltage disabled */
|
||||
#define OB_XSPI1_HSLV_ENABLE FLASH_OBW1SRP_XSPI1_HSLV /*!< I/O speed optimization at low-voltage feature allowed */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_XSPI2_HSLV FLASH Option Bytes User XSPI 2 High-Speed at Low-Voltage
|
||||
* @{
|
||||
*/
|
||||
#define OB_XSPI2_HSLV_DISABLE 0x00000000U /*!< I/O speed optimization at low-voltage disabled */
|
||||
#define OB_XSPI2_HSLV_ENABLE FLASH_OBW1SRP_XSPI2_HSLV /*!< I/O speed optimization at low-voltage feature allowed */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Stop Mode Freeze
|
||||
* @{
|
||||
*/
|
||||
#define OB_IWDG_STOP_FREEZE 0x00000000U /*!< Independent watchdog frozen in Stop mode */
|
||||
#define OB_IWDG_STOP_RUN FLASH_OBW1SRP_IWDG_FZ_STOP /*!< Independent watchdog running in Stop mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Standby Mode Freeze
|
||||
* @{
|
||||
*/
|
||||
#define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< Independent watchdog frozen in Standby mode */
|
||||
#define OB_IWDG_STDBY_RUN FLASH_OBW1SRP_IWDG_FZ_STBY /*!< Independent watchdog running in Standby mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_VDDIO_HSLV FLASH Option Bytes User I/O High-Speed at Low-Voltage
|
||||
* @{
|
||||
*/
|
||||
#define OB_VDDIO_HSLV_DISABLE 0x00000000U /*!< I/O speed optimization at low-voltage disabled */
|
||||
#define OB_VDDIO_HSLV_ENABLE FLASH_OBW1SRP_VDDIO_HSLV /*!< I/O speed optimization at low-voltage feature allowed */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_ITCM_AXI_SHARE FLASH Option Bytes User ITCM AXI share
|
||||
* @{
|
||||
*/
|
||||
#define OB_ITCM_AXI_SHARE_0 0x00000000U
|
||||
#define OB_ITCM_AXI_SHARE_1 FLASH_OBW2SRP_ITCM_AXI_SHARE_0
|
||||
#define OB_ITCM_AXI_SHARE_2 FLASH_OBW2SRP_ITCM_AXI_SHARE_1
|
||||
#define OB_ITCM_AXI_SHARE_3 (FLASH_OBW2SRP_ITCM_AXI_SHARE_0 | FLASH_OBW2SRP_ITCM_AXI_SHARE_1)
|
||||
#define OB_ITCM_AXI_SHARE_4 FLASH_OBW2SRP_ITCM_AXI_SHARE_2
|
||||
#define OB_ITCM_AXI_SHARE_5 (FLASH_OBW2SRP_ITCM_AXI_SHARE_2 | FLASH_OBW2SRP_ITCM_AXI_SHARE_0)
|
||||
#define OB_ITCM_AXI_SHARE_6 (FLASH_OBW2SRP_ITCM_AXI_SHARE_2 | FLASH_OBW2SRP_ITCM_AXI_SHARE_1)
|
||||
#define OB_ITCM_AXI_SHARE_7 FLASH_OBW2SRP_ITCM_AXI_SHARE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_DTCM_AXI_SHARE FLASH Option Bytes User DTCM AXI share
|
||||
* @{
|
||||
*/
|
||||
#define OB_DTCM_AXI_SHARE_0 0x00000000U
|
||||
#define OB_DTCM_AXI_SHARE_1 FLASH_OBW2SRP_DTCM_AXI_SHARE_0
|
||||
#define OB_DTCM_AXI_SHARE_2 FLASH_OBW2SRP_DTCM_AXI_SHARE_1
|
||||
#define OB_DTCM_AXI_SHARE_3 (FLASH_OBW2SRP_DTCM_AXI_SHARE_0 | FLASH_OBW2SRP_DTCM_AXI_SHARE_1)
|
||||
#define OB_DTCM_AXI_SHARE_4 FLASH_OBW2SRP_DTCM_AXI_SHARE_2
|
||||
#define OB_DTCM_AXI_SHARE_5 (FLASH_OBW2SRP_DTCM_AXI_SHARE_2 | FLASH_OBW2SRP_DTCM_AXI_SHARE_0)
|
||||
#define OB_DTCM_AXI_SHARE_6 (FLASH_OBW2SRP_DTCM_AXI_SHARE_2 | FLASH_OBW2SRP_DTCM_AXI_SHARE_1)
|
||||
#define OB_DTCM_AXI_SHARE_7 FLASH_OBW2SRP_DTCM_AXI_SHARE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_ECC_ON_SRAM FLASH Option Bytes User ECC on sRAM
|
||||
* @{
|
||||
*/
|
||||
#define OB_AXISRAM_ECC_DISABLE 0x00000000U /*!< AXISRAM ECC check disable */
|
||||
#define OB_AXISRAM_ECC_ENABLE FLASH_OBW2SRP_ECC_ON_SRAM /*!< AXISRAM ECC check enable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_I2C_NI3C FLASH Option Bytes User I2C Not I3C
|
||||
* @{
|
||||
*/
|
||||
#define OB_I2C_NI3C_I2C FLASH_OBW2SRP_I2C_NI3C
|
||||
#define OB_I2C_NI3C_I3C 0x00000000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_NVSTATE FLASH Option Bytes Non-volatile state
|
||||
* @{
|
||||
*/
|
||||
#define OB_NVSTATE_OPEN (uint8_t)0xB4
|
||||
#define OB_NVSTATE_CLOSE (uint8_t)0x51
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_ROT_OEM_PROVD FLASH Option Bytes Root-Of-Trust OEM Provisioned state
|
||||
* @{
|
||||
*/
|
||||
#define OB_OEM_PROVD_ENABLE (0xB4UL << FLASH_ROTSR_OEM_PROVD_Pos) /*!< Device is in OEM provisioned state */
|
||||
#define OB_OEM_PROVD_DEFAULT (0x6AUL << FLASH_ROTSR_OEM_PROVD_Pos) /*!< Device is not in OEM provisioned state (default value)*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_ROT_DBG_AUTH FLASH Option Bytes Root-Of-Trust Debug authentication method
|
||||
* @{
|
||||
*/
|
||||
#define OB_DBG_AUTH_LOCKED (0xB4UL << FLASH_ROTSR_DBG_AUTH_Pos) /*!< Locked device (no debug allowed) */
|
||||
#define OB_DBG_AUTH_ECDSA_SIGN (0x51UL << FLASH_ROTSR_DBG_AUTH_Pos) /*!< Authentication method using ECDSA signature (NISTP256) */
|
||||
#define OB_DBG_AUTH_PASSWORD (0x8AUL << FLASH_ROTSR_DBG_AUTH_Pos) /*!< Authentication method using password */
|
||||
#define OB_DBG_AUTH_DEFAULT (0xFFUL << FLASH_ROTSR_DBG_AUTH_Pos) /*!< No authentication method selected (default value) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_ROT_IROT_SELECT FLASH Option Bytes iRoT selection
|
||||
* @{
|
||||
*/
|
||||
#define OB_IROT_SELECTION_ST (0xB4UL << FLASH_ROTSR_IROT_SELECT_Pos) /*!< ST iRoT is selected at boot */
|
||||
#define OB_IROT_SELECTION_OEM (0x6AUL << FLASH_ROTSR_IROT_SELECT_Pos) /*!< OEM iRoT is selected at boot */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Latency FLASH Latency
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_LATENCY_0 0U /*!< FLASH Zero wait state */
|
||||
#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One wait state */
|
||||
#define FLASH_LATENCY_2 (FLASH_ACR_LATENCY_1 | FLASH_ACR_WRHIGHFREQ_0) /*!< FLASH Two wait states */
|
||||
#define FLASH_LATENCY_3 (FLASH_ACR_LATENCY_1 | FLASH_ACR_LATENCY_0 | FLASH_ACR_WRHIGHFREQ_0) /*!< FLASH Three wait states */
|
||||
#define FLASH_LATENCY_4 (FLASH_ACR_LATENCY_2 | FLASH_ACR_WRHIGHFREQ_1) /*!< FLASH Four wait states */
|
||||
#define FLASH_LATENCY_5 (FLASH_ACR_LATENCY_2 | FLASH_ACR_LATENCY_0 | FLASH_ACR_WRHIGHFREQ_1) /*!< FLASH Five wait states */
|
||||
#define FLASH_LATENCY_6 (FLASH_ACR_LATENCY_2 | FLASH_ACR_LATENCY_1 | FLASH_ACR_WRHIGHFREQ) /*!< FLASH Six wait state */
|
||||
#define FLASH_LATENCY_7 (FLASH_ACR_LATENCY_2 | FLASH_ACR_LATENCY_1 | FLASH_ACR_LATENCY_0 | FLASH_ACR_WRHIGHFREQ) /*!< FLASH Seven wait states */
|
||||
#define FLASH_LATENCY_8 (FLASH_ACR_LATENCY_3 | FLASH_ACR_WRHIGHFREQ) /*!< FLASH Eight wait states */
|
||||
#define FLASH_LATENCY_9 (FLASH_ACR_LATENCY_3 | FLASH_ACR_LATENCY_0 | FLASH_ACR_WRHIGHFREQ) /*!< FLASH Nine wait states */
|
||||
#define FLASH_LATENCY_10 (FLASH_ACR_LATENCY_3 | FLASH_ACR_LATENCY_1 | FLASH_ACR_WRHIGHFREQ) /*!< FLASH Ten wait states */
|
||||
#define FLASH_LATENCY_11 (FLASH_ACR_LATENCY_3 | FLASH_ACR_LATENCY_1 | FLASH_ACR_LATENCY_0 | FLASH_ACR_WRHIGHFREQ) /*!< FLASH Eleven wait states */
|
||||
#define FLASH_LATENCY_12 (FLASH_ACR_LATENCY_3 | FLASH_ACR_LATENCY_2 | FLASH_ACR_WRHIGHFREQ) /*!< FLASH Twelve wait states */
|
||||
#define FLASH_LATENCY_13 (FLASH_ACR_LATENCY_3 | FLASH_ACR_LATENCY_2 | FLASH_ACR_LATENCY_0 | FLASH_ACR_WRHIGHFREQ) /*!< FLASH Thirteen wait states */
|
||||
#define FLASH_LATENCY_14 (FLASH_ACR_LATENCY_3 | FLASH_ACR_LATENCY_2 | FLASH_ACR_LATENCY_1 | FLASH_ACR_WRHIGHFREQ) /*!< FLASH Fourteen wait states */
|
||||
#define FLASH_LATENCY_15 (FLASH_ACR_LATENCY | FLASH_ACR_WRHIGHFREQ) /*!< FLASH Fifteen wait states */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Keys FLASH Keys
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_KEY1 0x45670123U /*!< Flash key1 */
|
||||
#define FLASH_KEY2 0xCDEF89ABU /*!< Flash key2: used with FLASH_KEY1
|
||||
to unlock the FLASH registers access */
|
||||
|
||||
#define FLASH_OPTKEY1 0x08192A3BU /*!< Flash option byte key1 */
|
||||
#define FLASH_OPTKEY2 0x4C5D6E7FU /*!< Flash option byte key2: used with FLASH_OPTKEY1
|
||||
to allow option bytes operations */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
|
||||
* @brief macros to control FLASH features
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set the FLASH Latency.
|
||||
* @param __LATENCY__ FLASH Latency
|
||||
* This parameter can be one of the following values :
|
||||
* @arg FLASH_LATENCY_0: FLASH Zero wait state
|
||||
* @arg FLASH_LATENCY_1: FLASH One wait state
|
||||
* @arg FLASH_LATENCY_2: FLASH Two wait states
|
||||
* @arg FLASH_LATENCY_3: FLASH Three wait states
|
||||
* @arg FLASH_LATENCY_4: FLASH Four wait states
|
||||
* @arg FLASH_LATENCY_5: FLASH Five wait states
|
||||
* @arg FLASH_LATENCY_6: FLASH Six wait states
|
||||
* @arg FLASH_LATENCY_7: FLASH Seven wait states
|
||||
* @arg FLASH_LATENCY_8: FLASH Eight wait states
|
||||
* @arg FLASH_LATENCY_9: FLASH Nine wait states
|
||||
* @arg FLASH_LATENCY_10: FLASH Ten wait states
|
||||
* @arg FLASH_LATENCY_11: FLASH Eleven wait states
|
||||
* @arg FLASH_LATENCY_12: FLASH Twelve wait states
|
||||
* @arg FLASH_LATENCY_13: FLASH Thirteen wait states
|
||||
* @arg FLASH_LATENCY_14: FLASH Fourteen wait states
|
||||
* @arg FLASH_LATENCY_15: FLASH Fifteen wait states
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FLASH_SET_LATENCY(__LATENCY__) MODIFY_REG(FLASH->ACR, (FLASH_ACR_LATENCY |\
|
||||
FLASH_ACR_WRHIGHFREQ), (__LATENCY__))
|
||||
|
||||
/**
|
||||
* @brief Get the FLASH Latency.
|
||||
* @retval FLASH Latency
|
||||
* This return value can be one of the following values :
|
||||
* @arg FLASH_LATENCY_0: FLASH Zero wait state
|
||||
* @arg FLASH_LATENCY_1: FLASH One wait state
|
||||
* @arg FLASH_LATENCY_2: FLASH Two wait states
|
||||
* @arg FLASH_LATENCY_3: FLASH Three wait states
|
||||
* @arg FLASH_LATENCY_4: FLASH Four wait states
|
||||
* @arg FLASH_LATENCY_5: FLASH Five wait states
|
||||
* @arg FLASH_LATENCY_6: FLASH Six wait states
|
||||
* @arg FLASH_LATENCY_7: FLASH Seven wait states
|
||||
* @arg FLASH_LATENCY_8: FLASH Eight wait states
|
||||
* @arg FLASH_LATENCY_9: FLASH Nine wait states
|
||||
* @arg FLASH_LATENCY_10: FLASH Ten wait states
|
||||
* @arg FLASH_LATENCY_11: FLASH Eleven wait states
|
||||
* @arg FLASH_LATENCY_12: FLASH Twelve wait states
|
||||
* @arg FLASH_LATENCY_13: FLASH Thirteen wait states
|
||||
* @arg FLASH_LATENCY_14: FLASH Fourteen wait states
|
||||
* @arg FLASH_LATENCY_15: FLASH Fifteen wait states
|
||||
*/
|
||||
#define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, (FLASH_ACR_LATENCY | FLASH_ACR_WRHIGHFREQ))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Interrupt FLASH Interrupts Macros
|
||||
* @brief macros to handle FLASH interrupts
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the specified FLASH interrupt.
|
||||
* @param __INTERRUPT__ FLASH interrupt
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg FLASH_IT_EOP: End of program interrupt
|
||||
* @arg FLASH_IT_WRPERR: Write protection error interrupt
|
||||
* @arg FLASH_IT_PGSERR: Programming sequence error interrupt
|
||||
* @arg FLASH_IT_STRBERR: Strobe error interrupt
|
||||
* @arg FLASH_IT_OBLERR: Option byte loading error interrupt
|
||||
* @arg FLASH_IT_INCERR: Inconsistency error interrupt
|
||||
* @arg FLASH_IT_RDSERR: Read security error interrupt
|
||||
* @arg FLASH_IT_SNECCERR: ECC single error interrupt
|
||||
* @arg FLASH_IT_DBECCERR: ECC double error interrupt
|
||||
* @arg FLASH_IT_CRCEND: CRC end of calculation interrupt
|
||||
* @arg FLASH_IT_CRCERR: CRC error interrupt
|
||||
* @arg FLASH_IT_KVERR: Key valid error interrupt
|
||||
* @arg FLASH_IT_KTERR: Key transfer error interrupt
|
||||
* @arg FLASH_IT_OPTERR: Options byte change error interrupt
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_IER) != 0U)\
|
||||
{ SET_BIT(FLASH->IER, ((__INTERRUPT__) & FLASH_IT_IER)); }\
|
||||
if(((__INTERRUPT__) & FLASH_IT_OPTCR) != 0U)\
|
||||
{ SET_BIT(FLASH->OPTCR, ((__INTERRUPT__) & FLASH_IT_OPTCR)); }\
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Disable the specified FLASH interrupt.
|
||||
* @param __INTERRUPT__ FLASH interrupt
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg FLASH_IT_EOP: End of program interrupt
|
||||
* @arg FLASH_IT_WRPERR: Write protection error interrupt
|
||||
* @arg FLASH_IT_PGSERR: Programming sequence error interrupt
|
||||
* @arg FLASH_IT_STRBERR: Strobe error interrupt
|
||||
* @arg FLASH_IT_OBLERR: Option byte loading error interrupt
|
||||
* @arg FLASH_IT_INCERR: Inconsistency error interrupt
|
||||
* @arg FLASH_IT_RDSERR: Read security error interrupt
|
||||
* @arg FLASH_IT_SNECCERR: ECC single error interrupt
|
||||
* @arg FLASH_IT_DBECCERR: ECC double error interrupt
|
||||
* @arg FLASH_IT_CRCEND: CRC end of calculation interrupt
|
||||
* @arg FLASH_IT_CRCERR: CRC error interrupt
|
||||
* @arg FLASH_IT_KVERR: Key valid error interrupt
|
||||
* @arg FLASH_IT_KTERR: Key transfer error interrupt
|
||||
* @arg FLASH_IT_OPTERR: Options byte change error interrupt
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_IER) != 0U)\
|
||||
{ CLEAR_BIT(FLASH->IER, ((__INTERRUPT__) & FLASH_IT_IER)); }\
|
||||
if(((__INTERRUPT__) & FLASH_IT_OPTCR) != 0U)\
|
||||
{ CLEAR_BIT(FLASH->OPTCR, ((__INTERRUPT__) & FLASH_IT_OPTCR)); }\
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified FLASH flag is set or not.
|
||||
* @param __FLAG__ specifies the FLASH flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FLASH_FLAG_EOP: FLASH End of program flag
|
||||
* @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag
|
||||
* @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
|
||||
* @arg FLASH_FLAG_STRBERR: FLASH Strobe error flag
|
||||
* @arg FLASH_FLAG_OBLERR: FLASH Option byte loading error flag
|
||||
* @arg FLASH_FLAG_INCERR: FLASH Inconsistency error flag
|
||||
* @arg FLASH_FLAG_RDSERR: FLASH Read security error flag
|
||||
* @arg FLASH_FLAG_SNECCERR: FLASH ECC single error flag
|
||||
* @arg FLASH_FLAG_DBECCERR: FLASH ECC double error flag
|
||||
* @arg FLASH_FLAG_CRCEND: FLASH CRC end of calculation flag
|
||||
* @arg FLASH_FLAG_CRCERR: FLASH CRC error flag
|
||||
* @arg FLASH_FLAG_KVERR: FLASH Key valid error flag
|
||||
* @arg FLASH_FLAG_KTERR: FLASH Key transfer error flag
|
||||
* @arg FLASH_FLAG_OPTERR: FLASH Options byte change error flag
|
||||
* @retval The new state of FLASH_FLAG (SET or RESET).
|
||||
*/
|
||||
#define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & FLASH_FLAG_OPTISR_ERRORS) != 0U) ? \
|
||||
(READ_BIT(FLASH->OPTISR, (__FLAG__)) == (__FLAG__)) : \
|
||||
(READ_BIT(FLASH->ISR, (__FLAG__)) == (__FLAG__)))
|
||||
|
||||
/**
|
||||
* @brief Clear the FLASH's pending flags.
|
||||
* @param __FLAG__ specifies the FLASH flags to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg FLASH_FLAG_EOP: FLASH End of program flag
|
||||
* @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag
|
||||
* @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
|
||||
* @arg FLASH_FLAG_STRBERR: FLASH Strobe error flag
|
||||
* @arg FLASH_FLAG_OBLERR: FLASH Option byte loading error flag
|
||||
* @arg FLASH_FLAG_INCERR: FLASH Inconsistency error flag
|
||||
* @arg FLASH_FLAG_RDSERR: FLASH Read security error flag
|
||||
* @arg FLASH_FLAG_SNECCERR: FLASH ECC single error flag
|
||||
* @arg FLASH_FLAG_DBECCERR: FLASH ECC double error flag
|
||||
* @arg FLASH_FLAG_CRCEND: FLASH CRC end of calculation flag
|
||||
* @arg FLASH_FLAG_CRCERR: FLASH CRC error flag
|
||||
* @arg FLASH_FLAG_KVERR: FLASH Key valid error flag
|
||||
* @arg FLASH_FLAG_KTERR: FLASH Key transfer error flag
|
||||
* @arg FLASH_FLAG_OPTERR: FLASH Options byte change error flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_OPTISR_ERRORS) != 0U)\
|
||||
{ WRITE_REG(FLASH->OPTICR, ((__FLAG__) & FLASH_FLAG_OPTISR_ERRORS)); }\
|
||||
if(((__FLAG__) & FLASH_FLAG_ISR_FLAGS) != 0U)\
|
||||
{ WRITE_REG(FLASH->ICR, ((__FLAG__) & FLASH_FLAG_ISR_FLAGS)); }\
|
||||
} while(0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include FLASH HAL Extended module */
|
||||
#include "stm32h7rsxx_hal_flash_ex.h"
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup FLASH_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Program operation functions ***********************************************/
|
||||
/** @addtogroup FLASH_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t DataAddress);
|
||||
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t DataAddress);
|
||||
/* FLASH IRQ handler method */
|
||||
void HAL_FLASH_IRQHandler(void);
|
||||
/* Callbacks in non blocking modes */
|
||||
void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
|
||||
void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions **********************************************/
|
||||
/** @addtogroup FLASH_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Unlock(void);
|
||||
HAL_StatusTypeDef HAL_FLASH_Lock(void);
|
||||
/* Option bytes control */
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral State functions ************************************************/
|
||||
/** @addtogroup FLASH_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
uint32_t HAL_FLASH_GetError(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @addtogroup FLASH_Private_Variables FLASH Private Variables
|
||||
* @{
|
||||
*/
|
||||
extern FLASH_ProcessTypeDef pFlash;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants --------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_Constants FLASH Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_BANK_SIZE FLASH_SIZE
|
||||
|
||||
#define FLASH_SECTOR_NB 8U
|
||||
|
||||
#define FLASH_SECTOR_SIZE 0x2000UL /* 8 KB */
|
||||
|
||||
#define FLASH_HDP_BLOCK_NB 0x100U
|
||||
|
||||
#define FLASH_TIMEOUT_VALUE 1000U /* 1 s */
|
||||
|
||||
#define FLASH_BYTE_MASK 0x00000000U
|
||||
#define FLASH_HALFWORD_MASK 0x40000000U
|
||||
#define FLASH_WORD_MASK 0x80000000U
|
||||
#define FLASH_DOUBLEWORD_MASK 0xC0000000U
|
||||
#define FLASH_WORD_SIZE_MASK FLASH_DOUBLEWORD_MASK
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_Macros FLASH Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_SECTORS) ||\
|
||||
((VALUE) == FLASH_TYPEERASE_MASSERASE))
|
||||
|
||||
#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_BYTE) ||\
|
||||
((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) ||\
|
||||
((VALUE) == FLASH_TYPEPROGRAM_WORD) ||\
|
||||
((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD) ||\
|
||||
((VALUE) == FLASH_TYPEPROGRAM_QUADWORD) ||\
|
||||
((VALUE) == FLASH_TYPEPROGRAM_OTP_HALFWORD) ||\
|
||||
((VALUE) == FLASH_TYPEPROGRAM_OTP_WORD))
|
||||
|
||||
#define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE+FLASH_SIZE)))
|
||||
|
||||
#define IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= OTP_AREA_BASE) && ((ADDRESS) < (OTP_AREA_BASE + OTP_SIZE)))
|
||||
|
||||
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) ((IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS)) || (IS_FLASH_OTP_ADDRESS(ADDRESS)))
|
||||
|
||||
#define IS_FLASH_SECTOR(SECTOR) ((SECTOR) < FLASH_SECTOR_NB)
|
||||
|
||||
#define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP |\
|
||||
OPTIONBYTE_USER | OPTIONBYTE_HDP | OPTIONBYTE_NV)))
|
||||
|
||||
#define IS_OB_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || ((VALUE) == OB_WRPSTATE_ENABLE))
|
||||
|
||||
#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= 0x1FFFU) && ((TYPE) != 0U))
|
||||
|
||||
#define IS_OB_USER_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL_0) || ((LEVEL) == OB_BOR_LEVEL_1) || \
|
||||
((LEVEL) == OB_BOR_LEVEL_2) || ((LEVEL) == OB_BOR_LEVEL_3))
|
||||
|
||||
#define IS_OB_USER_IWDG(VALUE) (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW))
|
||||
|
||||
#define IS_OB_USER_STOP(VALUE) (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST))
|
||||
|
||||
#define IS_OB_USER_STANDBY(VALUE) (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST))
|
||||
|
||||
#define IS_OB_USER_XSPI1_HSLV(VALUE) (((VALUE) == OB_XSPI1_HSLV_DISABLE) || ((VALUE) == OB_XSPI1_HSLV_ENABLE))
|
||||
|
||||
#define IS_OB_USER_XSPI2_HSLV(VALUE) (((VALUE) == OB_XSPI2_HSLV_DISABLE) || ((VALUE) == OB_XSPI2_HSLV_ENABLE))
|
||||
|
||||
#define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_RUN))
|
||||
|
||||
#define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_RUN))
|
||||
|
||||
#define IS_OB_USER_VDDIO_HSLV(VALUE) (((VALUE) == OB_VDDIO_HSLV_DISABLE) || ((VALUE) == OB_VDDIO_HSLV_ENABLE))
|
||||
|
||||
#define IS_OB_USER_ITCM_AXI_SHARE(VALUE) (((VALUE) == OB_ITCM_AXI_SHARE_0) || ((VALUE) == OB_ITCM_AXI_SHARE_1) || \
|
||||
((VALUE) == OB_ITCM_AXI_SHARE_2) || ((VALUE) == OB_ITCM_AXI_SHARE_3) || \
|
||||
((VALUE) == OB_ITCM_AXI_SHARE_4) || ((VALUE) == OB_ITCM_AXI_SHARE_5) || \
|
||||
((VALUE) == OB_ITCM_AXI_SHARE_6) || ((VALUE) == OB_ITCM_AXI_SHARE_7))
|
||||
|
||||
#define IS_OB_USER_DTCM_AXI_SHARE(VALUE) (((VALUE) == OB_DTCM_AXI_SHARE_0) || ((VALUE) == OB_DTCM_AXI_SHARE_1) || \
|
||||
((VALUE) == OB_DTCM_AXI_SHARE_2) || ((VALUE) == OB_DTCM_AXI_SHARE_3) || \
|
||||
((VALUE) == OB_DTCM_AXI_SHARE_4) || ((VALUE) == OB_DTCM_AXI_SHARE_5) || \
|
||||
((VALUE) == OB_DTCM_AXI_SHARE_6) || ((VALUE) == OB_DTCM_AXI_SHARE_7))
|
||||
|
||||
#define IS_OB_USER_AXISRAM_ECC(VALUE) (((VALUE) == OB_AXISRAM_ECC_ENABLE) || ((VALUE) == OB_AXISRAM_ECC_DISABLE))
|
||||
|
||||
#define IS_OB_USER_I2C_NI3C(VALUE) (((VALUE) == OB_I2C_NI3C_I2C) || ((VALUE) == OB_I2C_NI3C_I3C))
|
||||
|
||||
#define IS_OB_HDP_PAGE(PAGE) ((PAGE) < FLASH_HDP_BLOCK_NB)
|
||||
|
||||
#define IS_OB_NVSTATE(VALUE) (((VALUE) == OB_NVSTATE_OPEN) || ((VALUE) ==OB_NVSTATE_CLOSE))
|
||||
|
||||
#define IS_OB_ROT_TYPE(VALUE) ((VALUE) <= 0x7U)
|
||||
|
||||
#define IS_OB_OEM_PROVD(VALUE) ((VALUE) <= 0x000000FFU)
|
||||
|
||||
#define IS_OB_DBG_AUTH(VALUE) ((VALUE) <= 0x0000FF00U)
|
||||
|
||||
#define IS_OB_IROT_SELECT(VALUE) ((VALUE) <= 0xFF000000U)
|
||||
|
||||
#define IS_OB_EPOCH(VALUE) ((VALUE) <= 0xFFFFFFU)
|
||||
|
||||
#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || \
|
||||
((LATENCY) == FLASH_LATENCY_2) || ((LATENCY) == FLASH_LATENCY_3) || \
|
||||
((LATENCY) == FLASH_LATENCY_4) || ((LATENCY) == FLASH_LATENCY_5) || \
|
||||
((LATENCY) == FLASH_LATENCY_6) || ((LATENCY) == FLASH_LATENCY_7) || \
|
||||
((LATENCY) == FLASH_LATENCY_8) || ((LATENCY) == FLASH_LATENCY_9) || \
|
||||
((LATENCY) == FLASH_LATENCY_10) || ((LATENCY) == FLASH_LATENCY_11) || \
|
||||
((LATENCY) == FLASH_LATENCY_12) || ((LATENCY) == FLASH_LATENCY_13) || \
|
||||
((LATENCY) == FLASH_LATENCY_14) || ((LATENCY) == FLASH_LATENCY_15))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @addtogroup FLASH_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7RSxx_HAL_FLASH_H */
|
||||
|
|
@ -1,262 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7rsxx_hal_flash_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of FLASH HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7RSxx_HAL_FLASH_EX_H
|
||||
#define STM32H7RSxx_HAL_FLASH_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7rsxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H7RSxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASHEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @addtogroup FLASH_Exported_Types FLASH Exported Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief FLASH Erase structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Index; /*!< Index of the key.
|
||||
This parameter can be a value between 0 and 31 */
|
||||
uint32_t Size; /*!< Size of the key.
|
||||
This parameter must be a value of @ref FLASH_Key_Size */
|
||||
uint32_t HDPLLevel; /*!< HDPL level of the key.
|
||||
This parameter must be a value of @ref FLASH_KEY_Level */
|
||||
} FLASH_KeyConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FLASH CRC configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t TypeCRC; /*!< CRC Selection Type.
|
||||
This parameter can be a value of @ref FLASHEx_CRC_Selection_Type */
|
||||
|
||||
uint32_t BurstSize; /*!< CRC Burst Size.
|
||||
This parameter can be a value of @ref FLASHEx_CRC_Burst_Size */
|
||||
|
||||
uint32_t Sector; /*!< Initial FLASH sector from which starts the CRC computation
|
||||
This parameter must be a value between 0 and (max number of sector - 1)*/
|
||||
|
||||
uint32_t NbSectors; /*!< Number of sectors to be computed.
|
||||
This parameter must be a value between 1 and
|
||||
(max number of sectors - value of Initial sector)*/
|
||||
|
||||
uint32_t CRCStartAddr; /*!< CRC Start address.
|
||||
This parameter must be a value between begin address and end address of a bank */
|
||||
|
||||
uint32_t CRCEndAddr; /*!< CRC End address.
|
||||
This parameter must be a value between CRC Start address and end address of a bank */
|
||||
|
||||
} FLASH_CRCInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FLASH ECC information structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Area; /*!< Area from which an ECC was detected.
|
||||
This parameter can be a value of @ref FLASHEx_ECC_Area */
|
||||
uint32_t Address; /*!< Flash address from which en ECC error was detected.
|
||||
This parameter must be a value between begin address and end address of the Flash */
|
||||
uint32_t MasterID; /*!< Master that initiated transfer on which error was detected
|
||||
This parameter can be a value of @ref FLASHEx_ECC_Master */
|
||||
} FLASH_EccInfoTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @addtogroup FLASHEx_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup FLASH_Key_Size FLASH Option Bytes Key Size
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_KEY_32_BITS 0x0000000U /*!< Key size is 32 bits */
|
||||
#define FLASH_KEY_64_BITS FLASH_OBKCR_OBKSIZE_0 /*!< Key size is 64 bits */
|
||||
#define FLASH_KEY_128_BITS FLASH_OBKCR_OBKSIZE_1 /*!< Key size is 128 bits */
|
||||
#define FLASH_KEY_256_BITS FLASH_OBKCR_OBKSIZE /*!< Key size is 256 bits */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_KEY_Level FLASH Option Bytes Key HDPL level
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_KEY_LEVEL_CURRENT 0x00000000U /*!< Key stored for the HDPL indicated in SBS_HDPLSR */
|
||||
#define FLASH_KEY_LEVEL_NEXT FLASH_OBKCR_NEXTKL_0 /*!< Key stored for the HDPL indicated in SBS_HDPLSR + 1 */
|
||||
#define FLASH_KEY_LEVEL_PLUS_TWO FLASH_OBKCR_NEXTKL_1 /*!< Key stored for the HDPL indicated in SBS_HDPLSR + 2 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_CRC_Selection_Type FLASH CRC Selection Type
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_CRC_ADDR 0x00000000U /*!< CRC selection type by address */
|
||||
#define FLASH_CRC_SECTORS FLASH_CRCCR_CRC_BY_SECT /*!< CRC selection type by sectors */
|
||||
#define FLASH_CRC_BANK (FLASH_CRCCR_ALL_SECT | FLASH_CRCCR_CRC_BY_SECT) /*!< CRC selection type all bank */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_CRC_Burst_Size FLASH CRC Burst Size
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_CRC_BURST_SIZE_4 0x00000000U /*!< Every burst has a size of 4 Flash words (64 Bytes) */
|
||||
#define FLASH_CRC_BURST_SIZE_16 FLASH_CRCCR_CRC_BURST_0 /*!< Every burst has a size of 16 Flash words (256 Bytes) */
|
||||
#define FLASH_CRC_BURST_SIZE_64 FLASH_CRCCR_CRC_BURST_1 /*!< Every burst has a size of 64 Flash words (1 kByte) */
|
||||
#define FLASH_CRC_BURST_SIZE_256 FLASH_CRCCR_CRC_BURST /*!< Every burst has a size of 256 Flash words (4 kBytes) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_ECC_Area FLASH ECC Area
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_ECC_AREA_USER_BANK1 0x00000000U /*!< FLASH bank 1 area */
|
||||
#define FLASH_ECC_AREA_SYSTEM 0x00000001U /*!< System FLASH area */
|
||||
#define FLASH_ECC_AREA_OTP 0x00000002U /*!< FLASH OTP area */
|
||||
#define FLASH_ECC_AREA_READ_ONLY 0x00000004U /*!< FLASH Read-only area */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_ECC_Master FLASH ECC Master
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_ECC_MASTER_CPU1 0x00000000U /*!< ECC error occurs on a CPU1 transaction */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup FLASHEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Extended Program operation functions *************************************/
|
||||
/** @addtogroup FLASHEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASHEx_Erase(const FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError);
|
||||
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(const FLASH_EraseInitTypeDef *pEraseInit);
|
||||
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(const FLASH_OBProgramInitTypeDef *pOBInit);
|
||||
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASHEx_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASHEx_OTPLockConfig(uint32_t OTPLBlock);
|
||||
uint32_t HAL_FLASHEx_GetOTPLock(void);
|
||||
HAL_StatusTypeDef HAL_FLASHEx_KeyConfig(const FLASH_KeyConfigTypeDef *pKeyConfig, const uint32_t *pKey);
|
||||
HAL_StatusTypeDef HAL_FLASHEx_GetKey(const FLASH_KeyConfigTypeDef *pKeyConfig, uint32_t *pKey);
|
||||
HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(const FLASH_CRCInitTypeDef *pCRCInit, uint32_t *CRC_Result);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASHEx_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
void HAL_FLASHEx_EnableEccCorrectionInterrupt(void);
|
||||
void HAL_FLASHEx_DisableEccCorrectionInterrupt(void);
|
||||
void HAL_FLASHEx_EnableEccDetectionInterrupt(void);
|
||||
void HAL_FLASHEx_DisableEccDetectionInterrupt(void);
|
||||
void HAL_FLASHEx_GetEccInfo(FLASH_EccInfoTypeDef *pData);
|
||||
void HAL_FLASHEx_ECCD_IRQHandler(void);
|
||||
void HAL_FLASHEx_EccDetectionCallback(void);
|
||||
void HAL_FLASHEx_EccCorrectionCallback(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private function ----------------------------------------------------------*/
|
||||
/** @addtogroup FLASHEx_Private_Functions FLASHEx Private Functions
|
||||
* @{
|
||||
*/
|
||||
void FLASH_SectorErase(uint32_t Sector);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Private_Macros FLASH Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_KEY_INDEX(VALUE) ((VALUE) < 0x20U)
|
||||
|
||||
#define IS_KEY_SIZE(VALUE) (((VALUE) == FLASH_KEY_32_BITS) || ((VALUE) == FLASH_KEY_64_BITS) || \
|
||||
((VALUE) == FLASH_KEY_128_BITS) || ((VALUE) == FLASH_KEY_256_BITS))
|
||||
|
||||
#define IS_KEY_HDPL_LEVEL(VALUE) (((VALUE) == FLASH_KEY_LEVEL_CURRENT) || \
|
||||
((VALUE) == FLASH_KEY_LEVEL_NEXT) || \
|
||||
((VALUE) == FLASH_KEY_LEVEL_PLUS_TWO))
|
||||
|
||||
#define IS_OB_OTP_BLOCK(VALUE) ((VALUE) <= 0xFFFFU)
|
||||
|
||||
#define IS_FLASH_TYPE_CRC(VALUE) (((VALUE) == FLASH_CRC_ADDR) || ((VALUE) == FLASH_CRC_SECTORS) ||\
|
||||
((VALUE) == FLASH_CRC_BANK))
|
||||
|
||||
#define IS_FLASH_BURST_SIZE_CRC(VALUE) (((VALUE) == FLASH_CRC_BURST_SIZE_4) || ((VALUE) == FLASH_CRC_BURST_SIZE_16) ||\
|
||||
((VALUE) == FLASH_CRC_BURST_SIZE_64) || ((VALUE) == FLASH_CRC_BURST_SIZE_256))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7RSxx_HAL_FLASH_EX_H */
|
||||
|
|
@ -1,370 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7rsxx_hal_gfxmmu.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of GFXMMU HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7RSxx_HAL_GFXMMU_H
|
||||
#define STM32H7RSxx_HAL_GFXMMU_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7rsxx_hal_def.h"
|
||||
|
||||
#if defined(GFXMMU)
|
||||
|
||||
/** @addtogroup STM32H7RSxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GFXMMU
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup GFXMMU_Exported_Types GFXMMU Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HAL GFXMMU states definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_GFXMMU_STATE_RESET = 0x00U, /*!< GFXMMU not initialized. */
|
||||
HAL_GFXMMU_STATE_READY = 0x01U, /*!< GFXMMU initialized and ready for use. */
|
||||
} HAL_GFXMMU_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief GFXMMU buffers structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Buf0Address; /*!< Physical address of buffer 0. */
|
||||
uint32_t Buf1Address; /*!< Physical address of buffer 1. */
|
||||
uint32_t Buf2Address; /*!< Physical address of buffer 2. */
|
||||
uint32_t Buf3Address; /*!< Physical address of buffer 3. */
|
||||
} GFXMMU_BuffersTypeDef;
|
||||
|
||||
/**
|
||||
* @brief GFXMMU interrupts structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
FunctionalState Activation; /*!< Interrupts enable/disable. */
|
||||
uint32_t UsedInterrupts; /*!< Interrupts used.
|
||||
This parameter can be a values combination of @ref GFXMMU_Interrupts.
|
||||
@note: Useful only when interrupts are enabled. */
|
||||
} GFXMMU_InterruptsTypeDef;
|
||||
|
||||
/**
|
||||
* @brief GFXMMU init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t BlockSize; /*!< Size of virtual memory block.
|
||||
This parameter can be a value of @ref GFXMMU_BlockSize. */
|
||||
uint32_t DefaultValue; /*!< Value returned when virtual memory location not physically mapped. */
|
||||
/* @note: Useful only when address translation is enabled. */
|
||||
FunctionalState AddressTranslation; /*!< Address translation enable/disable. */
|
||||
GFXMMU_BuffersTypeDef Buffers; /*!< Physical buffers addresses. */
|
||||
GFXMMU_InterruptsTypeDef Interrupts; /*!< Interrupts parameters. */
|
||||
} GFXMMU_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief GFXMMU handle structure definition
|
||||
*/
|
||||
#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __GFXMMU_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS */
|
||||
{
|
||||
GFXMMU_TypeDef *Instance; /*!< GFXMMU instance. */
|
||||
GFXMMU_InitTypeDef Init; /*!< GFXMMU init parameters. */
|
||||
HAL_GFXMMU_StateTypeDef State; /*!< GFXMMU state. */
|
||||
__IO uint32_t ErrorCode; /*!< GFXMMU error code. */
|
||||
#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
|
||||
void (*ErrorCallback)(struct __GFXMMU_HandleTypeDef *hgfxmmu); /*!< GFXMMU error callback. */
|
||||
void (*MspInitCallback)(struct __GFXMMU_HandleTypeDef *hgfxmmu); /*!< GFXMMU MSP init callback. */
|
||||
void (*MspDeInitCallback)(struct __GFXMMU_HandleTypeDef *hgfxmmu); /*!< GFXMMU MSP de-init callback. */
|
||||
#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS */
|
||||
} GFXMMU_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @brief GFXMMU LUT line structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t LineNumber; /*!< LUT line number.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 1023. */
|
||||
uint32_t LineStatus; /*!< LUT line enable/disable.
|
||||
This parameter can be a value of @ref GFXMMU_LutLineStatus. */
|
||||
uint32_t FirstVisibleBlock; /*!< First visible block on this line.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 255. */
|
||||
uint32_t LastVisibleBlock; /*!< Last visible block on this line.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 255. */
|
||||
int32_t LineOffset; /*!< Offset of block 0 of the current line in physical buffer.
|
||||
This parameter must be a number between Min_Data = -255 and Max_Data = 261888.
|
||||
@note: Line offset has to be computed with the following formula:
|
||||
LineOffset = [(Blocks already used) - (1st visible block)]. */
|
||||
} GFXMMU_LutLineTypeDef;
|
||||
|
||||
/**
|
||||
* @brief GFXMMU packing structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
FunctionalState Buffer0Activation; /*!< Packing on buffer 0 enable/disable. */
|
||||
uint32_t Buffer0Mode; /*!< Buffer 0 packing mode.
|
||||
This parameter can be a value of @ref GFXMMU_PackingModes. */
|
||||
FunctionalState Buffer1Activation; /*!< Packing on buffer 1 enable/disable. */
|
||||
uint32_t Buffer1Mode; /*!< Buffer 1 packing mode.
|
||||
This parameter can be a value of @ref GFXMMU_PackingModes. */
|
||||
FunctionalState Buffer2Activation; /*!< Packing on buffer 2 enable/disable. */
|
||||
uint32_t Buffer2Mode; /*!< Buffer 2 packing mode.
|
||||
This parameter can be a value of @ref GFXMMU_PackingModes. */
|
||||
FunctionalState Buffer3Activation; /*!< Packing on buffer 3 enable/disable. */
|
||||
uint32_t Buffer3Mode; /*!< Buffer 3 packing mode.
|
||||
This parameter can be a value of @ref GFXMMU_PackingModes. */
|
||||
uint32_t DefaultAlpha; /*!< Default alpha value.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 255. */
|
||||
} GFXMMU_PackingTypeDef;
|
||||
|
||||
#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief GFXMMU callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_GFXMMU_ERROR_CB_ID = 0x00U, /*!< GFXMMU error callback ID. */
|
||||
HAL_GFXMMU_MSPINIT_CB_ID = 0x01U, /*!< GFXMMU MSP init callback ID. */
|
||||
HAL_GFXMMU_MSPDEINIT_CB_ID = 0x02U /*!< GFXMMU MSP de-init callback ID. */
|
||||
} HAL_GFXMMU_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief GFXMMU callback pointer definition
|
||||
*/
|
||||
typedef void (*pGFXMMU_CallbackTypeDef)(GFXMMU_HandleTypeDef *hgfxmmu);
|
||||
#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of exported types -----------------------------------------------------*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup GFXMMU_Exported_Constants GFXMMU Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GFXMMU_BlockSize GFXMMU block size
|
||||
* @{
|
||||
*/
|
||||
#define GFXMMU_12BYTE_BLOCKS GFXMMU_CR_BS /*!< Blocks of 12-byte. */
|
||||
#define GFXMMU_16BYTE_BLOCKS 0x00000000U /*!< Blocks of 16-byte. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GFXMMU_Interrupts GFXMMU interrupts
|
||||
* @{
|
||||
*/
|
||||
#define GFXMMU_BUS_MASTER_ERROR_IT GFXMMU_CR_AMEIE /*!< Bus master error interrupt. */
|
||||
#define GFXMMU_BUFFER0_OVERFLOW_IT GFXMMU_CR_B0OIE /*!< Buffer 0 overflow interrupt. */
|
||||
#define GFXMMU_BUFFER1_OVERFLOW_IT GFXMMU_CR_B1OIE /*!< Buffer 1 overflow interrupt. */
|
||||
#define GFXMMU_BUFFER2_OVERFLOW_IT GFXMMU_CR_B2OIE /*!< Buffer 2 overflow interrupt. */
|
||||
#define GFXMMU_BUFFER3_OVERFLOW_IT GFXMMU_CR_B3OIE /*!< Buffer 3 overflow interrupt. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GFXMMU_Error_Code GFXMMU Error Code
|
||||
* @{
|
||||
*/
|
||||
#define GFXMMU_ERROR_NONE 0x00000000U /*!< No error. */
|
||||
#define GFXMMU_ERROR_BUFFER0_OVERFLOW GFXMMU_SR_B0OF /*!< Buffer 0 overflow. */
|
||||
#define GFXMMU_ERROR_BUFFER1_OVERFLOW GFXMMU_SR_B1OF /*!< Buffer 1 overflow. */
|
||||
#define GFXMMU_ERROR_BUFFER2_OVERFLOW GFXMMU_SR_B2OF /*!< Buffer 2 overflow. */
|
||||
#define GFXMMU_ERROR_BUFFER3_OVERFLOW GFXMMU_SR_B3OF /*!< Buffer 3 overflow. */
|
||||
#define GFXMMU_ERROR_BUS_MASTER GFXMMU_SR_AMEF /*!< Bus master error. */
|
||||
#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
|
||||
#define GFXMMU_ERROR_INVALID_CALLBACK 0x00000100U /*!< Invalid callback error. */
|
||||
#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GFXMMU_LutLineStatus GFXMMU LUT line status
|
||||
* @{
|
||||
*/
|
||||
#define GFXMMU_LUT_LINE_DISABLE 0x00000000U /*!< LUT line disabled. */
|
||||
#define GFXMMU_LUT_LINE_ENABLE GFXMMU_LUTxL_EN /*!< LUT line enabled. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GFXMMU_PackingModes GFXMMU packing modes
|
||||
* @{
|
||||
*/
|
||||
#define GFXMMU_PACKING_MSB_REMOVE 0x00000000U /*!< Remove MSB during packing operation. */
|
||||
#define GFXMMU_PACKING_LSB_REMOVE 0x00000001U /*!< Remove LSB during packing operation. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of exported constants -------------------------------------------------*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup GFXMMU_Exported_Macros GFXMMU Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset GFXMMU handle state.
|
||||
* @param __HANDLE__ GFXMMU handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_GFXMMU_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_GFXMMU_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_GFXMMU_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_GFXMMU_STATE_RESET)
|
||||
#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of exported macros ----------------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup GFXMMU_Exported_Functions GFXMMU Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GFXMMU_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
HAL_StatusTypeDef HAL_GFXMMU_Init(GFXMMU_HandleTypeDef *hgfxmmu);
|
||||
HAL_StatusTypeDef HAL_GFXMMU_DeInit(GFXMMU_HandleTypeDef *hgfxmmu);
|
||||
void HAL_GFXMMU_MspInit(GFXMMU_HandleTypeDef *hgfxmmu);
|
||||
void HAL_GFXMMU_MspDeInit(GFXMMU_HandleTypeDef *hgfxmmu);
|
||||
#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
|
||||
/* GFXMMU callbacks register/unregister functions *****************************/
|
||||
HAL_StatusTypeDef HAL_GFXMMU_RegisterCallback(GFXMMU_HandleTypeDef *hgfxmmu,
|
||||
HAL_GFXMMU_CallbackIDTypeDef CallbackID,
|
||||
pGFXMMU_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_GFXMMU_UnRegisterCallback(GFXMMU_HandleTypeDef *hgfxmmu,
|
||||
HAL_GFXMMU_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup GFXMMU_Exported_Functions_Group2 Operations functions
|
||||
* @{
|
||||
*/
|
||||
/* Operation functions ********************************************************/
|
||||
HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(const GFXMMU_HandleTypeDef *hgfxmmu,
|
||||
uint32_t FirstLine,
|
||||
uint32_t LinesNumber,
|
||||
uint32_t Address);
|
||||
|
||||
HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(const GFXMMU_HandleTypeDef *hgfxmmu,
|
||||
uint32_t FirstLine,
|
||||
uint32_t LinesNumber);
|
||||
|
||||
HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(const GFXMMU_HandleTypeDef *hgfxmmu, const GFXMMU_LutLineTypeDef *lutLine);
|
||||
|
||||
HAL_StatusTypeDef HAL_GFXMMU_ModifyBuffers(GFXMMU_HandleTypeDef *hgfxmmu, const GFXMMU_BuffersTypeDef *Buffers);
|
||||
|
||||
HAL_StatusTypeDef HAL_GFXMMU_ConfigPacking(GFXMMU_HandleTypeDef *hgfxmmu, const GFXMMU_PackingTypeDef *pPacking);
|
||||
|
||||
void HAL_GFXMMU_IRQHandler(GFXMMU_HandleTypeDef *hgfxmmu);
|
||||
|
||||
void HAL_GFXMMU_ErrorCallback(GFXMMU_HandleTypeDef *hgfxmmu);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GFXMMU_Exported_Functions_Group3 State functions
|
||||
* @{
|
||||
*/
|
||||
/* State function *************************************************************/
|
||||
HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(const GFXMMU_HandleTypeDef *hgfxmmu);
|
||||
|
||||
uint32_t HAL_GFXMMU_GetError(GFXMMU_HandleTypeDef *hgfxmmu);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of exported functions -------------------------------------------------*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup GFXMMU_Private_Macros GFXMMU Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_GFXMMU_BLOCK_SIZE(VALUE) (((VALUE) == GFXMMU_12BYTE_BLOCKS) || \
|
||||
((VALUE) == GFXMMU_16BYTE_BLOCKS))
|
||||
#define IS_GFXMMU_LUT_LINE_OFFSET(VALUE) (((VALUE) >= -255) && ((VALUE) <= 261888))
|
||||
|
||||
#define IS_GFXMMU_BUFFER_ADDRESS(VALUE) (((VALUE) & 0xFU) == 0U)
|
||||
|
||||
#define IS_GFXMMU_INTERRUPTS(VALUE) (((VALUE) & 0x1FU) != 0U)
|
||||
|
||||
#define IS_GFXMMU_LUT_LINE(VALUE) ((VALUE) < 1024U)
|
||||
|
||||
#define IS_GFXMMU_LUT_LINES_NUMBER(VALUE) (((VALUE) > 0U) && ((VALUE) <= 1024U))
|
||||
|
||||
#define IS_GFXMMU_LUT_LINE_STATUS(VALUE) (((VALUE) == GFXMMU_LUT_LINE_DISABLE) || \
|
||||
((VALUE) == GFXMMU_LUT_LINE_ENABLE))
|
||||
|
||||
#define IS_GFXMMU_LUT_BLOCK(VALUE) ((VALUE) < 256U)
|
||||
|
||||
#define IS_GFXMMU_PACKING_MODE(VALUE) (((VALUE) == GFXMMU_PACKING_MSB_REMOVE) || \
|
||||
((VALUE) == GFXMMU_PACKING_LSB_REMOVE))
|
||||
|
||||
#define IS_GFXMMU_DEFAULT_ALPHA_VALUE(VALUE) ((VALUE) < 256U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of private macros -----------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* GFXMMU */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7RSxx_HAL_GFXMMU_H */
|
||||
|
|
@ -1,929 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7rsxx_hal_gfxtim.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of GFXTIM HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7RSxx_HAL_GFXTIM_H
|
||||
#define STM32H7RSxx_HAL_GFXTIM_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7rsxx_hal_def.h"
|
||||
|
||||
#if defined (GFXTIM)
|
||||
|
||||
/** @addtogroup STM32H7RSxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GFXTIM
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup GFXTIM_Exported_Types GFXTIM Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HAL GFXTIM states definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_GFXTIM_STATE_RESET = 0x00U, /*!< GFXTIM not initialized */
|
||||
HAL_GFXTIM_STATE_READY = 0x01U, /*!< GFXTIM initialized and ready for use */
|
||||
HAL_GFXTIM_STATE_ERROR = 0xFFU /*!< GFXTIM state error */
|
||||
} HAL_GFXTIM_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief GFXTIM initialization structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SynchroSrc; /*!< Synchronization signals (HSYNC and VSYNC) sources.
|
||||
This parameter can be a value of @ref GFXTIM_SynchroSrc */
|
||||
uint32_t TearingEffectSrc; /*!< Tearing effect source
|
||||
This parameter can be a value of @ref GFXTIM_TearingEffectSrc */
|
||||
uint32_t TearingEffectPolarity; /*!< Tearing effect source
|
||||
This parameter can be a value of @ref GFXTIM_TearingEffectPolarity */
|
||||
uint32_t TearingEffectInterrupt; /*!< Tearing effect interrupt Enable or Disable
|
||||
This parameter can be a value of @ref GFXTIM_Interrupt */
|
||||
} GFXTIM_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief GFXTIM handle structure definition
|
||||
*/
|
||||
#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __GFXTIM_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */
|
||||
{
|
||||
GFXTIM_TypeDef *Instance; /*!< GFXTIM instance */
|
||||
__IO HAL_GFXTIM_StateTypeDef State; /*!< GFXTIM state */
|
||||
__IO uint32_t ErrorCode; /*!< GFXTIM error code */
|
||||
GFXTIM_InitTypeDef Init; /*!< GFXTIM initialization */
|
||||
#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1)
|
||||
void (*HAL_GFXTIM_AbsoluteTimer_AFCC1Callback)(struct __GFXTIM_HandleTypeDef *hgfxtim); /*!< GFXTIM Absolute frame counter compare 1 callback */
|
||||
void (*HAL_GFXTIM_AbsoluteTimer_AFCOFCallback)(struct __GFXTIM_HandleTypeDef *hgfxtim); /*!< GFXTIM Absolute frame counter overflow callback */
|
||||
void (*HAL_GFXTIM_AbsoluteTimer_ALCC1Callback)(struct __GFXTIM_HandleTypeDef *hgfxtim); /*!< GFXTIM Absolute line counter compare 1 callback */
|
||||
void (*HAL_GFXTIM_AbsoluteTimer_ALCC2Callback)(struct __GFXTIM_HandleTypeDef *hgfxtim); /*!< GFXTIM Absolute line counter compare 2 callback */
|
||||
void (*HAL_GFXTIM_AbsoluteTimer_ALCOFCallback)(struct __GFXTIM_HandleTypeDef *hgfxtim); /*!< GFXTIM Absolute line counter overflow callback */
|
||||
void (*HAL_GFXTIM_RelativeTimer_RFC1RCallback)(struct __GFXTIM_HandleTypeDef *hgfxtim); /*!< GFXTIM Relative frame counter 1 reload callback */
|
||||
void (*HAL_GFXTIM_RelativeTimer_RFC2RCallback)(struct __GFXTIM_HandleTypeDef *hgfxtim); /*!< GFXTIM Relative frame counter 2 reload callback */
|
||||
void (*HAL_GFXTIM_TECallback)(struct __GFXTIM_HandleTypeDef *hgfxtim); /*!< GFXTIM Tearing effect callback */
|
||||
void (*HAL_GFXTIM_EventGenerator_EV1Callback)(struct __GFXTIM_HandleTypeDef *hgfxtim); /*!< GFXTIM Event events 1 callback */
|
||||
void (*HAL_GFXTIM_EventGenerator_EV2Callback)(struct __GFXTIM_HandleTypeDef *hgfxtim); /*!< GFXTIM Event events 2 callback */
|
||||
void (*HAL_GFXTIM_EventGenerator_EV3Callback)(struct __GFXTIM_HandleTypeDef *hgfxtim); /*!< GFXTIM Event events 3 callback */
|
||||
void (*HAL_GFXTIM_EventGenerator_EV4Callback)(struct __GFXTIM_HandleTypeDef *hgfxtim); /*!< GFXTIM Event events 4 callback */
|
||||
void (*HAL_GFXTIM_WatchdogTimer_AlarmCallback)(struct __GFXTIM_HandleTypeDef *hgfxtim); /*!< GFXTIM Watchdog alarm callback */
|
||||
void (*HAL_GFXTIM_WatchdogTimer_PreAlarmCallback)(struct __GFXTIM_HandleTypeDef *hgfxtim); /*!< GFXTIM Watchdog pre alarm callback */
|
||||
void (*ErrorCallback)(struct __GFXTIM_HandleTypeDef *hgfxtim); /*!< GFXTIM error callback */
|
||||
void (*MspInitCallback)(struct __GFXTIM_HandleTypeDef *hgfxtim); /*!< GFXTIM MSP initialization user callback */
|
||||
void (*MspDeInitCallback)(struct __GFXTIM_HandleTypeDef *hgfxtim); /*!< GFXTIM MSP de-initialization user callback */
|
||||
#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */
|
||||
} GFXTIM_HandleTypeDef;
|
||||
|
||||
|
||||
#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief GFXTIM callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_GFXTIM_AFC_COMPARE1_CB_ID = 1U, /*!< GFXTIM Absolute frame counter compare 1 callback ID */
|
||||
HAL_GFXTIM_AFC_OVERFLOW_CB_ID = 2U, /*!< GFXTIM Absolute frame counter overflow callback ID */
|
||||
HAL_GFXTIM_ALC_COMPARE1_CB_ID = 3U, /*!< GFXTIM Absolute line counter compare 1 callback ID */
|
||||
HAL_GFXTIM_ALC_COMPARE2_CB_ID = 4U, /*!< GFXTIM Absolute line counter compare 2 callback ID */
|
||||
HAL_GFXTIM_ALC_OVERFLOW_CB_ID = 5U, /*!< GFXTIM Absolute line counter overflow callback ID */
|
||||
HAL_GFXTIM_RFC1_RELOAD_CB_ID = 6U, /*!< GFXTIM Relative frame counter 1 reload callback ID */
|
||||
HAL_GFXTIM_RFC2_RELOAD_CB_ID = 7U, /*!< GFXTIM Relative frame counter 2 reload callback ID */
|
||||
HAL_GFXTIM_TE_CB_ID = 8U, /*!< GFXTIM External tearing effect callback ID */
|
||||
HAL_GFXTIM_EVENT1_CB_ID = 9U, /*!< GFXTIM Event events 1 callback ID */
|
||||
HAL_GFXTIM_EVENT2_CB_ID = 10U, /*!< GFXTIM Event events 2 callback ID */
|
||||
HAL_GFXTIM_EVENT3_CB_ID = 11U, /*!< GFXTIM Event events 3 callback ID */
|
||||
HAL_GFXTIM_EVENT4_CB_ID = 12U, /*!< GFXTIM Event events 4 callback ID */
|
||||
HAL_GFXTIM_WDG_ALARM_CB_ID = 13U, /*!< GFXTIM Watchdog alarm callback ID */
|
||||
HAL_GFXTIM_WDG_PREALARM_CB_ID = 14U, /*!< GFXTIM Watchdog pre alarm callback ID */
|
||||
HAL_GFXTIM_ERROR_CB_ID = 15U, /*!< GFXTIM error callback ID */
|
||||
HAL_GFXTIM_MSP_INIT_CB_ID = 16U, /*!< GFXTIM MSP initialization user callback ID */
|
||||
HAL_GFXTIM_MSP_DEINIT_CB_ID = 17U, /*!< GFXTIM MSP de-initialization user callback ID */
|
||||
} HAL_GFXTIM_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief GFXTIM callback pointers definition
|
||||
*/
|
||||
typedef void (*pGFXTIM_CallbackTypeDef)(GFXTIM_HandleTypeDef *hgfxtim);
|
||||
#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */
|
||||
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief GFXTIM clock generator structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t LCCHwReloadSrc; /*!< Line Clock Counter hardware reload source
|
||||
This parameter can be a value of @ref GFXTIM_LCCHwReloadSrc */
|
||||
|
||||
uint32_t LCCReloadValue; /*!< Line Clock Counter reload value (22 bits)
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 4194303 */
|
||||
|
||||
uint32_t LCCClockSrc; /*!< Line Clock Counter Clock Source
|
||||
This parameter can be a value of @ref GFXTIM_LCCClockSrc */
|
||||
|
||||
uint32_t LineClockSrc; /*!< Line Clock Source
|
||||
This parameter can be a value of @ref GFXTIM_LineClockSrc */
|
||||
|
||||
uint32_t FCCHwReloadSrc; /*!< Frame Clock Counter hardware reload source
|
||||
This parameter can be a value of @ref GFXTIM_FCCHwReloadSrc */
|
||||
|
||||
uint32_t FCCReloadValue; /*!< Frame Clock Counter reload value (12 bits)
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 4095 */
|
||||
|
||||
uint32_t FCCClockSrc; /*!< Frame Clock Counter Clock Source
|
||||
This parameter can be a value of @ref GFXTIM_FCCClockSrc */
|
||||
|
||||
uint32_t FrameClockSrc; /*!< Frame Clock Source
|
||||
This parameter can be a value of @ref GFXTIM_FrameClockSrc */
|
||||
|
||||
uint32_t LineClockCalib; /*!< Debug purpose
|
||||
This parameter can be a value of @ref GFXTIM_LineClockCalib */
|
||||
|
||||
uint32_t FrameClockCalib; /*!< Debug purpose
|
||||
This parameter can be a value of @ref GFXTIM_FrameClockCalib */
|
||||
} GFXTIM_ClockGeneratorConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @brief GFXTIM absolute timer configuration structure
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FrameCompare1Value; /*!< Absolute Frame Compare 1 value (20 bits)
|
||||
This parameter must be a number between 1 and 1048575 */
|
||||
|
||||
uint32_t FrameCounterValue; /*!< Absolute Frame Counter initial value (20 bits)
|
||||
This parameter must be a number between 1 and 1048575 */
|
||||
|
||||
uint32_t FrameOverflowInterrupt; /*!< Absolute Frame Counter Overflow Interrupt Enable or Disable
|
||||
This parameter can be a value of @ref GFXTIM_Interrupt */
|
||||
|
||||
uint32_t FrameCompare1Interrupt; /*!< Absolute Frame Compare 1 Interrupt Enable or Disable
|
||||
This parameter can be a value of @ref GFXTIM_Interrupt */
|
||||
|
||||
uint32_t LineCompare1Value; /*!< Absolute Line Compare 1 value (12 bits)
|
||||
This parameter must be a number between 1 and 4095 */
|
||||
|
||||
uint32_t LineCompare2Value; /*!< Absolute Line Compare 2 value (12 bits)
|
||||
This parameter must be a number between 1 and 4095 */
|
||||
|
||||
uint32_t LineCounterValue; /*!< Absolute Line Counter value (12 bits)
|
||||
This parameter must be a number between 1 and 4095 */
|
||||
|
||||
uint32_t LineOverflowInterrupt; /*!< Absolute Line Counter Overflow Interrupt Enable or Disable
|
||||
This parameter can be a value of @ref GFXTIM_Interrupt */
|
||||
|
||||
uint32_t LineCompare1Interrupt; /*!< Absolute Line Compare 1 Interrupt Enable or Disable
|
||||
This parameter can be a value of @ref GFXTIM_Interrupt */
|
||||
|
||||
uint32_t LineCompare2Interrupt; /*!< Absolute Line Compare 2 Interrupt Enable or Disable
|
||||
This parameter can be a value of @ref GFXTIM_Interrupt */
|
||||
} GFXTIM_AbsoluteTimerConfigTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief GFXTIM relative timer configuration structure
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t AutoReloadValue; /*!< Auto reload value (12 bits)
|
||||
This parameter must be a number between 1 and 4095 */
|
||||
|
||||
uint32_t CounterMode; /*!< Counter Mode
|
||||
This parameter can be a value of GFXTIM_RelativeCounterMode */
|
||||
uint32_t ReloadInterrupt; /*!< Relative Frame Counter Reload Interrupt Enable or Disable
|
||||
This parameter can be a value of @ref GFXTIM_Interrupt */
|
||||
} GFXTIM_RelativeTimerConfigTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief GFXTIM event generator configuration structure
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t LineEvent; /*!< Line event selection
|
||||
This parameter can be a value of GFXTIM_EventLine */
|
||||
|
||||
uint32_t FrameEvent; /*!< Frmae event selection
|
||||
This parameter can be a value of GFXTIM_EventFrame */
|
||||
|
||||
uint32_t EventInterrupt; /*!< Event interrupt Enable or Disable
|
||||
This parameter can be a value of @ref GFXTIM_Interrupt */
|
||||
} GFXTIM_EventGeneratorConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @brief GFXTIM watchdog configuration structure
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ClockSrc; /*!< Clock source
|
||||
This parameter can be a value of GFXTIM_WatchdogClockSrc */
|
||||
|
||||
uint32_t AutoReloadValue; /*!< Reload value (16 bits)
|
||||
This parameter must be a number between 1 and 65535 */
|
||||
|
||||
uint32_t HwReloadConfig; /*!< Hardware reload configuration
|
||||
This parameter can be a value of GFXTIM_WatchdogHwReloadConfig */
|
||||
|
||||
uint32_t PreAlarmValue; /*!< Pre-alarm value (16 bits)
|
||||
This parameter must be a number between 1 and 65535 */
|
||||
|
||||
uint32_t AlarmInterrupt; /*!< Interrupt Enable or Disable when watchdog counter reaches 0
|
||||
This parameter can be a value of @ref GFXTIM_Interrupt */
|
||||
|
||||
uint32_t PreAlarmInterrupt; /*!< Interrupt Enable or Disable when watchdog counter reaches pre-alarm value
|
||||
This parameter can be a value of @ref GFXTIM_Interrupt */
|
||||
} GFXTIM_WatchdogConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup GFXTIM_Exported_Constants GFXTIM Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GFXTIM_ErrorCode GFXTIM Error Code
|
||||
* @{
|
||||
*/
|
||||
#define GFXTIM_ERROR_NONE 0U /*!< No error */
|
||||
#define GFXTIM_ERROR_STATE 1U /*!< State error */
|
||||
#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1)
|
||||
#define GFXTIM_ERROR_INVALID_CALLBACK 2U /*!< Invalid callback error occurs */
|
||||
#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GFXTIM_Interrupt GFXTIM Interrupt
|
||||
* @{
|
||||
*/
|
||||
#define GFXTIM_IT_DISABLE 0U /*!< gfxtim_interrupt disable */
|
||||
#define GFXTIM_IT_ENABLE 1U /*!< gfxtim_interrupt enable */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GFXTIM_SynchroSrc GFXTIM Synchronization Source
|
||||
* @{
|
||||
*/
|
||||
#define GFXTIM_SYNC_SRC_HSYNC_VSYNC_0 0U /*!< gfxtim_hsync[0] and gfxtim_vsync[0] are used as synchronization source */
|
||||
#define GFXTIM_SYNC_SRC_HSYNC_VSYNC_1 GFXTIM_CR_SYNCS_0 /*!< gfxtim_hsync[1] and gfxtim_vsync[1] are used as synchronization source */
|
||||
#define GFXTIM_SYNC_SRC_HSYNC_VSYNC_2 GFXTIM_CR_SYNCS_1 /*!< gfxtim_hsync[2] and gfxtim_vsync[2] are used as synchronization source */
|
||||
#define GFXTIM_SYNC_SRC_HSYNC_VSYNC_3 (GFXTIM_CR_SYNCS_0 | GFXTIM_CR_SYNCS_1) /*!< gfxtim_hsync[3] and gfxtim_vsync[3] are used as synchronization source */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GFXTIM_TearingEffectSrc GFXTIM Tearing Effect Source
|
||||
* @{
|
||||
*/
|
||||
#define GFXTIM_TE_SRC_GPIO 0U /*!< Input pad rising */
|
||||
#define GFXTIM_TE_SRC_ITE GFXTIM_CR_TES_0 /*!< gfxtim_ite rising */
|
||||
#define GFXTIM_TE_SRC_HSYNC GFXTIM_CR_TES_1 /*!< HSYNC (see SynchroSrc) rising */
|
||||
#define GFXTIM_TE_SRC_VSYNC (GFXTIM_CR_TES_0 | GFXTIM_CR_TES_1) /*!< VSYNC (see SynchroSrc) rising */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GFXTIM_TearingEffectPolarity GFXTIM Tearing Effect Polarity
|
||||
* @{
|
||||
*/
|
||||
#define GFXTIM_TE_RISING_EDGE 0U /*!< Tearing Effect active on rizing edge */
|
||||
#define GFXTIM_TE_FALLING_EDGE GFXTIM_CR_TEPOL /*!< Tearing Effect active on falling edge */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GFXTIM_LCCHwReloadSrc GFXTIM Line Clock Counter Hardware Reload Source
|
||||
* @{
|
||||
*/
|
||||
#define GFXTIM_LCC_HW_RELOAD_SRC_NONE 0U /*!< No hardware reload */
|
||||
#define GFXTIM_LCC_HW_RELOAD_SRC_FCC_UNDERFLOW GFXTIM_CGCR_LCCHRS_0 /*!< FCC underflow */
|
||||
#define GFXTIM_LCC_HW_RELOAD_SRC_HSYNC_RISING GFXTIM_CGCR_LCCHRS_1 /*!< HSYNC rising */
|
||||
#define GFXTIM_LCC_HW_RELOAD_SRC_HSYNC_FALLING (GFXTIM_CGCR_LCCHRS_0 | GFXTIM_CGCR_LCCHRS_1) /*!< HSYNC falling */
|
||||
#define GFXTIM_LCC_HW_RELOAD_SRC_VSYNC_RISING GFXTIM_CGCR_LCCHRS_2 /*!< VSYNC rising */
|
||||
#define GFXTIM_LCC_HW_RELOAD_SRC_VSYNC_FALLING (GFXTIM_CGCR_LCCHRS_2 | GFXTIM_CGCR_LCCHRS_0) /*!< VSYNC falling */
|
||||
#define GFXTIM_LCC_HW_RELOAD_SRC_TE_RISING (GFXTIM_CGCR_LCCHRS_2 | GFXTIM_CGCR_LCCHRS_1) /*!< TE rising */
|
||||
#define GFXTIM_LCC_HW_RELOAD_SRC_TE_FALLING (GFXTIM_CGCR_LCCHRS_2 | GFXTIM_CGCR_LCCHRS_1 | GFXTIM_CGCR_LCCHRS_0) /*!< TE falling */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GFXTIM_LCCClockSrc GFXTIM Line Clock Counter Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define GFXTIM_LCC_CLK_SRC_DISABLE 0U /*!< Disable line clock counter */
|
||||
#define GFXTIM_LCC_CLK_SRC_SYSCLOCK GFXTIM_CGCR_LCCCS /*!< System clock as line clock counter source*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GFXTIM_LineClockSrc GFXTIM Line Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define GFXTIM_LINE_CLK_SRC_LCC_UNDERFLOW 0U /*!< Line Clock Counter underflow */
|
||||
#define GFXTIM_LINE_CLK_SRC_FCC_UNDERFLOW GFXTIM_CGCR_LCS_0 /*!< Frame Clock Counter underflow */
|
||||
#define GFXTIM_LINE_CLK_SRC_HSYNC_RISING GFXTIM_CGCR_LCS_1 /*!< HSYNC rising edge */
|
||||
#define GFXTIM_LINE_CLK_SRC_HSYNC_FALLING (GFXTIM_CGCR_LCS_0 | GFXTIM_CGCR_LCS_1) /*!< HSYNC falling edge*/
|
||||
#define GFXTIM_LINE_CLK_SRC_VSYNC_RISING GFXTIM_CGCR_LCS_2 /*!< VSYNC rising edge*/
|
||||
#define GFXTIM_LINE_CLK_SRC_VSYNC_FALLING (GFXTIM_CGCR_LCS_2 | GFXTIM_CGCR_LCS_0) /*!< VSYNC falling edge*/
|
||||
#define GFXTIM_LINE_CLK_SRC_TE_RISING (GFXTIM_CGCR_LCS_2 | GFXTIM_CGCR_LCS_1) /*!< TE rising edge*/
|
||||
#define GFXTIM_LINE_CLK_SRC_TE_FALLING (GFXTIM_CGCR_LCS_2 | GFXTIM_CGCR_LCS_1 | GFXTIM_CGCR_LCS_0) /*!< TE falling edge*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GFXTIM_FCCHwReloadSrc GFXTIM Frame Clock Counter Hardware Reload source
|
||||
* @{
|
||||
*/
|
||||
#define GFXTIM_FCC_HW_RELOAD_SRC_NONE 0U /*!< No hardware reload */
|
||||
#define GFXTIM_FCC_HW_RELOAD_SRC_LCC_UNDERFLOW GFXTIM_CGCR_FCCHRS_0 /*!< Line Clock Counter underflow */
|
||||
#define GFXTIM_FCC_HW_RELOAD_SRC_HSYNC_RISING GFXTIM_CGCR_FCCHRS_1 /*!< HSYNC rising edge */
|
||||
#define GFXTIM_FCC_HW_RELOAD_SRC_HSYNC_FALLING (GFXTIM_CGCR_FCCHRS_0 | GFXTIM_CGCR_FCCHRS_1) /*!< HSYNC falling edge */
|
||||
#define GFXTIM_FCC_HW_RELOAD_SRC_VSYNC_RISING GFXTIM_CGCR_FCCHRS_2 /*!< VSYNC rising edge */
|
||||
#define GFXTIM_FCC_HW_RELOAD_SRC_VSYNC_FALLING (GFXTIM_CGCR_FCCHRS_2 | GFXTIM_CGCR_FCCHRS_0) /*!< VSYNC falling edge */
|
||||
#define GFXTIM_FCC_HW_RELOAD_SRC_TE_RISING (GFXTIM_CGCR_FCCHRS_2 | GFXTIM_CGCR_FCCHRS_1) /*!< TE rising edge */
|
||||
#define GFXTIM_FCC_HW_RELOAD_SRC_TE_FALLING (GFXTIM_CGCR_FCCHRS_2 | GFXTIM_CGCR_FCCHRS_1 | GFXTIM_CGCR_FCCHRS_0) /*!< TE falling edge */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GFXTIM_FCCClockSrc GFXTIM Frame CLock Counter Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define GFXTIM_FCC_CLK_SRC_DISABLE 0U /*!< Disable */
|
||||
#define GFXTIM_FCC_CLK_SRC_LCC_UNDERFLOW GFXTIM_CGCR_FCCCS_0 /*!< Line Clock Counter underflow */
|
||||
#define GFXTIM_FCC_CLK_SRC_HSYNC_RISING GFXTIM_CGCR_FCCCS_1 /*!< HSYNC rising edge */
|
||||
#define GFXTIM_FCC_CLK_SRC_HSYNC_FALLING (GFXTIM_CGCR_FCCCS_0 | GFXTIM_CGCR_FCCCS_1) /*!< HSYNC falling edge */
|
||||
#define GFXTIM_FCC_CLK_SRC_VSYNC_RISING GFXTIM_CGCR_FCCCS_2 /*!< VSYNC rising edge */
|
||||
#define GFXTIM_FCC_CLK_SRC_VSYNC_FALLING (GFXTIM_CGCR_FCCCS_2 | GFXTIM_CGCR_FCCCS_0) /*!< VSYNC falling edge */
|
||||
#define GFXTIM_FCC_CLK_SRC_TE_RISING (GFXTIM_CGCR_FCCCS_2 | GFXTIM_CGCR_FCCCS_1) /*!< TE rising edge */
|
||||
#define GFXTIM_FCC_CLK_SRC_TE_FALLING (GFXTIM_CGCR_FCCCS_2 | GFXTIM_CGCR_FCCCS_1 | GFXTIM_CGCR_FCCCS_0) /*!< TE falling edge */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GFXTIM_FrameClockSrc GFXTIM GFXTIM Frame Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define GFXTIM_FRAME_CLK_SRC_LCC_UNDERFLOW 0U /*!< Line Clock Counter underflow */
|
||||
#define GFXTIM_FRAME_CLK_SRC_FCC_UNDERFLOW GFXTIM_CGCR_FCS_0 /*!< Frame Clock Counter underflow */
|
||||
#define GFXTIM_FRAME_CLK_SRC_HSYNC_RISING GFXTIM_CGCR_FCS_1 /*!< HSYNC rising edge */
|
||||
#define GFXTIM_FRAME_CLK_SRC_HSYNC_FALLING (GFXTIM_CGCR_FCS_0 | GFXTIM_CGCR_FCS_1) /*!< HSYNC falling edge */
|
||||
#define GFXTIM_FRAME_CLK_SRC_VSYNC_RISING GFXTIM_CGCR_FCS_2 /*!< VSYNC rising edge */
|
||||
#define GFXTIM_FRAME_CLK_SRC_VSYNC_FALLING (GFXTIM_CGCR_FCS_2 | GFXTIM_CGCR_FCS_0) /*!< VSYNC falling edge */
|
||||
#define GFXTIM_FRAME_CLK_SRC_TE_RISING (GFXTIM_CGCR_FCS_2 | GFXTIM_CGCR_FCS_1) /*!< TE rising edge */
|
||||
#define GFXTIM_FRAME_CLK_SRC_TE_FALLING (GFXTIM_CGCR_FCS_2 | GFXTIM_CGCR_FCS_1 | GFXTIM_CGCR_FCS_0) /*!< TE falling edge */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GFXTIM_LineClockCalib GFXTIM Line Clock Calibration Output
|
||||
* @{
|
||||
*/
|
||||
#define GFXTIM_LINE_CLK_CALIB_DISABLE 0U /*!< Disable Line clock calibration */
|
||||
#define GFXTIM_LINE_CLK_CALIB_ENABLE GFXTIM_CR_LCCOE /*!< Enable Line clock calibration */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GFXTIM_FrameClockCalib GFXTIM Frame Clock Calibration Output (for debug purpose)
|
||||
* @{
|
||||
*/
|
||||
#define GFXTIM_FRAME_CLK_CALIB_DISABLE 0U /*!< Frame clock output calibration Disable */
|
||||
#define GFXTIM_FRAME_CLK_CALIB_ENABLE GFXTIM_CR_FCCOE /*!< Frame clock output calibration Enable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GFXTIM_ClockGeneratorCounter GFXTIM Clock Generator Counter
|
||||
* @{
|
||||
*/
|
||||
#define GFXTIM_LINE_CLK_COUNTER GFXTIM_CGCR_LCCFR /*!< Line clock counter */
|
||||
#define GFXTIM_FRAME_CLK_COUNTER GFXTIM_CGCR_FCCFR /*!< Frame clock counter */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GFXTIM_AbsoluteTime GFXTIM Absolute Time
|
||||
* @{
|
||||
*/
|
||||
#define GFXTIM_ABSOLUTE_GLOBAL_TIME 0x00000014U /*!< Absolute global time (frame and line) counters ATR*/
|
||||
#define GFXTIM_ABSOLUTE_FRAME_TIME 0x00000015U /*!< Absolute frame counter AFCR */
|
||||
#define GFXTIM_ABSOLUTE_LINE_TIME 0x00000016U /*!< Absolute line counter ALCR */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GFXTIM_AbsoluteLineComparator GFXTIM Absolute Line Comparator
|
||||
* @{
|
||||
*/
|
||||
#define GFXTIM_ABSOLUTE_LINE_COMPARE1 0x1CU /*!< Absolute line compare 1 */
|
||||
#define GFXTIM_ABSOLUTE_LINE_COMPARE2 0x1DU /*!< Absolute line compare 2 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup GFXTIM_RelativeCounterMode GFXTIM Relative Frame Counter Mode
|
||||
* @{
|
||||
*/
|
||||
#define GFXTIM_MODE_ONE_SHOT 0U /*!< Relative Frame Counter One Shot Mode*/
|
||||
#define GFXTIM_MODE_CONTINUOUS 1U /*!< Relative Frame Counter Continuous Mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GFXTIM_RelativeTimer GFXTIM Relative Timer
|
||||
* @{
|
||||
*/
|
||||
#define GFXTIM_RELATIVE_TIMER1 0U /*!< Relative Timer 1*/
|
||||
#define GFXTIM_RELATIVE_TIMER2 1U /*!< Relative Timer 2 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GFXTIM_EventLineSrc GFXTIM Event generator Line source selection
|
||||
* @{
|
||||
*/
|
||||
#define GFXTIM_LINE_EVENT_NONE (0U << GFXTIM_EVSR_LES1_Pos) /*!< None */
|
||||
#define GFXTIM_LINE_EVENT_ALC_OVERFLOW (1U << GFXTIM_EVSR_LES1_Pos) /*!< Absolute line counter overflow */
|
||||
#define GFXTIM_LINE_EVENT_TE (2U << GFXTIM_EVSR_LES1_Pos) /*!< Tearing effect */
|
||||
#define GFXTIM_LINE_EVENT_ALC1_COMPARE (4U << GFXTIM_EVSR_LES1_Pos) /*!< Absolute line counter 1 compare */
|
||||
#define GFXTIM_LINE_EVENT_ALC2_COMPARE (5U << GFXTIM_EVSR_LES1_Pos) /*!< Absolute line counter 2 compare */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GFXTIM_EventFrameSrc GFXTIM Event generator Frame Source selection
|
||||
* @{
|
||||
*/
|
||||
#define GFXTIM_FRAME_EVENT_NONE (0U << GFXTIM_EVSR_FES1_Pos ) /*!< None */
|
||||
#define GFXTIM_FRAME_EVENT_AFC_OVERFLOW (1U << GFXTIM_EVSR_FES1_Pos ) /*!< Absolute frame counter overflow */
|
||||
#define GFXTIM_FRAME_EVENT_AFC_COMPARE (2U << GFXTIM_EVSR_FES1_Pos ) /*!< Absolute frame counter compare */
|
||||
#define GFXTIM_FRAME_EVENT_RFC1_RELOAD (4U << GFXTIM_EVSR_FES1_Pos ) /*!< Relative frame counter 1 reload */
|
||||
#define GFXTIM_FRAME_EVENT_RFC2_RELOAD (5U << GFXTIM_EVSR_FES1_Pos ) /*!< Relative frame counter 1 reload */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GFXTIM_EventGenerator GFXTIM Event Generator ID
|
||||
* @{
|
||||
*/
|
||||
#define GFXTIM_EVENT_GENERATOR_1 0U /*!< Event Generator 1 */
|
||||
#define GFXTIM_EVENT_GENERATOR_2 1U /*!< Event Generator 2 */
|
||||
#define GFXTIM_EVENT_GENERATOR_3 2U /*!< Event Generator 3 */
|
||||
#define GFXTIM_EVENT_GENERATOR_4 3U /*!< Event Generator 4 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup GFXTIM_WatchdogHwReloadConfig GFXTIM Watchdog hardware reload configuration
|
||||
* @{
|
||||
*/
|
||||
#define GFXTIM_WATCHDOG_HW_RELOAD_DISABLE (0U << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< Watchdog hardware reload is disable */
|
||||
#define GFXTIM_WATCHDOG_HW_RELOAD_RISING_EDGE (1U << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< Watchdog is reload on rising edge of gfxtim_wrld */
|
||||
#define GFXTIM_WATCHDOG_HW_RELOAD_FALLING_EDGE (2U << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< Watchdog is reload on falling edge of gfxtim_wrld */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GFXTIM_WatchdogClockSrc GFXTIM Watchdog clock source
|
||||
* @{
|
||||
*/
|
||||
#define GFXTIM_WATCHDOG_CLK_SRC_LINE_CLK (0U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Line Clock */
|
||||
#define GFXTIM_WATCHDOG_CLK_SRC_FRAME_CLK (1U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Frame Clock */
|
||||
#define GFXTIM_WATCHDOG_CLK_SRC_HSYNC_RISING (2U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< HSYNC rising edge */
|
||||
#define GFXTIM_WATCHDOG_CLK_SRC_HSYNC_FALLING (3U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< HSYNC falling edge */
|
||||
#define GFXTIM_WATCHDOG_CLK_SRC_VSYNC_RISING (4U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< VSYNC rising edge */
|
||||
#define GFXTIM_WATCHDOG_CLK_SRC_VSYNC_FALLING (5U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< VSYNC falling edge */
|
||||
#define GFXTIM_WATCHDOG_CLK_SRC_TE_RISING (6U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Tearing Effect rising edge */
|
||||
#define GFXTIM_WATCHDOG_CLK_SRC_TE_FALLING (7U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Tearing Effect falling edge */
|
||||
#define GFXTIM_WATCHDOG_CLK_SRC_EVENT_1 (8U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Event Generator 1 output */
|
||||
#define GFXTIM_WATCHDOG_CLK_SRC_EVENT_2 (9U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Event Generator 2 output */
|
||||
#define GFXTIM_WATCHDOG_CLK_SRC_EVENT_3 (10U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Event Generator 3 output */
|
||||
#define GFXTIM_WATCHDOG_CLK_SRC_EVENT_4 (11U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Event Generator 4 output */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GFXTIM_Flag GFXTIM flags
|
||||
* @{
|
||||
*/
|
||||
#define GFXTIM_FLAG_AFCO GFXTIM_ISR_AFCOF /* Absolute Frame Counter Overflow Flag */
|
||||
#define GFXTIM_FLAG_ALCO GFXTIM_ISR_ALCOF /* Absolute Line Counter Overflow Flag */
|
||||
#define GFXTIM_FLAG_TE GFXTIM_ISR_TEF /* Tearing Effect Flag */
|
||||
#define GFXTIM_FLAG_AFCC1 GFXTIM_ISR_AFCC1F /* Absolute Frame Counter Compare 1 Flag */
|
||||
#define GFXTIM_FLAG_ALCC1 GFXTIM_ISR_ALCC1F /* Absolute Line Counter Compare 1 Flag */
|
||||
#define GFXTIM_FLAG_ALCC2 GFXTIM_ISR_ALCC2F /* Absolute Line Counter Compare 2 Flag */
|
||||
#define GFXTIM_FLAG_RFC1R GFXTIM_ISR_RFC1RF /* Relative Frame Counter 1 Reload Flag */
|
||||
#define GFXTIM_FLAG_RFC2R GFXTIM_ISR_RFC2RF /* Relative Frame Counter 2 Reload Flag */
|
||||
#define GFXTIM_FLAG_EV1 GFXTIM_ISR_EV1F /* Event 1 Flag */
|
||||
#define GFXTIM_FLAG_EV2 GFXTIM_ISR_EV2F /* Event 2 Flag */
|
||||
#define GFXTIM_FLAG_EV3 GFXTIM_ISR_EV3F /* Event 3 Flag */
|
||||
#define GFXTIM_FLAG_EV4 GFXTIM_ISR_EV4F /* Event 4 Flag */
|
||||
#define GFXTIM_FLAG_WDGA GFXTIM_ISR_WDGAF /* Watchdog Alarm Flag */
|
||||
#define GFXTIM_FLAG_WDGP GFXTIM_ISR_WDGPF /* Watchdog Pre-alarm Flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup GFXTIM_Private_Macros GFXTIM Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_GFXTIM_INTERRUPT(PARAM) (((PARAM) == GFXTIM_IT_ENABLE ) || \
|
||||
((PARAM) == GFXTIM_IT_DISABLE ))
|
||||
|
||||
#define IS_GFXTIM_SYNC_SRC(PARAM) (((PARAM) == GFXTIM_SYNC_SRC_HSYNC_VSYNC_0) || \
|
||||
((PARAM) == GFXTIM_SYNC_SRC_HSYNC_VSYNC_1) || \
|
||||
((PARAM) == GFXTIM_SYNC_SRC_HSYNC_VSYNC_2) || \
|
||||
((PARAM) == GFXTIM_SYNC_SRC_HSYNC_VSYNC_3))
|
||||
|
||||
#define IS_GFXTIM_TE_SRC(PARAM) (((PARAM) == GFXTIM_TE_SRC_GPIO ) || \
|
||||
((PARAM) == GFXTIM_TE_SRC_ITE ) || \
|
||||
((PARAM) == GFXTIM_TE_SRC_HSYNC ) || \
|
||||
((PARAM) == GFXTIM_TE_SRC_VSYNC ))
|
||||
|
||||
#define IS_GFXTIM_TE_POLARITY(PARAM) (((PARAM) == GFXTIM_TE_RISING_EDGE ) || \
|
||||
((PARAM) == GFXTIM_TE_FALLING_EDGE ))
|
||||
|
||||
#define IS_GFXTIM_LCC_HW_RELOAD_SRC(PARAM) (((PARAM) == GFXTIM_LCC_HW_RELOAD_SRC_NONE ) || \
|
||||
((PARAM) == GFXTIM_LCC_HW_RELOAD_SRC_FCC_UNDERFLOW) || \
|
||||
((PARAM) == GFXTIM_LCC_HW_RELOAD_SRC_HSYNC_RISING ) || \
|
||||
((PARAM) == GFXTIM_LCC_HW_RELOAD_SRC_HSYNC_FALLING) || \
|
||||
((PARAM) == GFXTIM_LCC_HW_RELOAD_SRC_VSYNC_RISING ) || \
|
||||
((PARAM) == GFXTIM_LCC_HW_RELOAD_SRC_VSYNC_FALLING) || \
|
||||
((PARAM) == GFXTIM_LCC_HW_RELOAD_SRC_TE_RISING ) || \
|
||||
((PARAM) == GFXTIM_LCC_HW_RELOAD_SRC_TE_FALLING ))
|
||||
|
||||
#define IS_GFXTIM_LCC_CLK_SRC(PARAM) (((PARAM) == GFXTIM_LCC_CLK_SRC_DISABLE) || \
|
||||
((PARAM) == GFXTIM_LCC_CLK_SRC_SYSCLOCK))
|
||||
|
||||
#define IS_GFXTIM_LINE_CLK_SRC(PARAM) (((PARAM) == GFXTIM_LINE_CLK_SRC_LCC_UNDERFLOW) || \
|
||||
((PARAM) == GFXTIM_LINE_CLK_SRC_FCC_UNDERFLOW) || \
|
||||
((PARAM) == GFXTIM_LINE_CLK_SRC_HSYNC_RISING ) || \
|
||||
((PARAM) == GFXTIM_LINE_CLK_SRC_HSYNC_FALLING) || \
|
||||
((PARAM) == GFXTIM_LINE_CLK_SRC_VSYNC_RISING ) || \
|
||||
((PARAM) == GFXTIM_LINE_CLK_SRC_VSYNC_FALLING) || \
|
||||
((PARAM) == GFXTIM_LINE_CLK_SRC_TE_RISING) || \
|
||||
((PARAM) == GFXTIM_LINE_CLK_SRC_TE_FALLING))
|
||||
|
||||
#define IS_GFXTIM_FCC_HW_RELOAD_SRC(PARAM) (((PARAM) == GFXTIM_FCC_HW_RELOAD_SRC_NONE) || \
|
||||
((PARAM) == GFXTIM_FCC_HW_RELOAD_SRC_LCC_UNDERFLOW) || \
|
||||
((PARAM) == GFXTIM_FCC_HW_RELOAD_SRC_HSYNC_RISING ) || \
|
||||
((PARAM) == GFXTIM_FCC_HW_RELOAD_SRC_HSYNC_FALLING) || \
|
||||
((PARAM) == GFXTIM_FCC_HW_RELOAD_SRC_VSYNC_RISING ) || \
|
||||
((PARAM) == GFXTIM_FCC_HW_RELOAD_SRC_VSYNC_FALLING) || \
|
||||
((PARAM) == GFXTIM_FCC_HW_RELOAD_SRC_TE_RISING) || \
|
||||
((PARAM) == GFXTIM_FCC_HW_RELOAD_SRC_TE_FALLING))
|
||||
|
||||
#define IS_GFXTIM_FCC_CLK_SRC(PARAM) (((PARAM) == GFXTIM_FCC_CLK_SRC_DISABLE) || \
|
||||
((PARAM) == GFXTIM_FCC_CLK_SRC_LCC_UNDERFLOW) || \
|
||||
((PARAM) == GFXTIM_FCC_CLK_SRC_HSYNC_RISING ) || \
|
||||
((PARAM) == GFXTIM_FCC_CLK_SRC_HSYNC_FALLING) || \
|
||||
((PARAM) == GFXTIM_FCC_CLK_SRC_VSYNC_RISING ) || \
|
||||
((PARAM) == GFXTIM_FCC_CLK_SRC_VSYNC_FALLING) || \
|
||||
((PARAM) == GFXTIM_FCC_CLK_SRC_TE_RISING) || \
|
||||
((PARAM) == GFXTIM_FCC_CLK_SRC_TE_FALLING))
|
||||
|
||||
#define IS_GFXTIM_FRAME_CLK_SRC(PARAM) (((PARAM) == GFXTIM_FRAME_CLK_SRC_LCC_UNDERFLOW) || \
|
||||
((PARAM) == GFXTIM_FRAME_CLK_SRC_FCC_UNDERFLOW) || \
|
||||
((PARAM) == GFXTIM_FRAME_CLK_SRC_HSYNC_RISING ) || \
|
||||
((PARAM) == GFXTIM_FRAME_CLK_SRC_HSYNC_FALLING) || \
|
||||
((PARAM) == GFXTIM_FRAME_CLK_SRC_VSYNC_RISING ) || \
|
||||
((PARAM) == GFXTIM_FRAME_CLK_SRC_VSYNC_FALLING) || \
|
||||
((PARAM) == GFXTIM_FRAME_CLK_SRC_TE_RISING) || \
|
||||
((PARAM) == GFXTIM_FRAME_CLK_SRC_TE_FALLING))
|
||||
|
||||
#define IS_GFXTIM_LINE_CLK_CALIB(PARAM) (((PARAM) == GFXTIM_LINE_CLK_CALIB_DISABLE) || \
|
||||
((PARAM) == GFXTIM_LINE_CLK_CALIB_ENABLE))
|
||||
|
||||
#define IS_GFXTIM_FRAME_CLK_CALIB(PARAM) (((PARAM) == GFXTIM_FRAME_CLK_CALIB_DISABLE) || \
|
||||
((PARAM) == GFXTIM_FRAME_CLK_CALIB_ENABLE))
|
||||
|
||||
#define IS_GFXTIM_CLOCK_GENERATOR_COUNTER(PARAM) (((PARAM) == GFXTIM_LINE_CLK_COUNTER) || \
|
||||
((PARAM) == GFXTIM_FRAME_CLK_COUNTER) || \
|
||||
((PARAM) == (GFXTIM_LINE_CLK_COUNTER | \
|
||||
GFXTIM_FRAME_CLK_COUNTER)))
|
||||
|
||||
#define IS_GFXTIM_ABSOLUTE_TIME(PARAM) (((PARAM) == GFXTIM_ABSOLUTE_GLOBAL_TIME) || \
|
||||
((PARAM) == GFXTIM_ABSOLUTE_FRAME_TIME) || \
|
||||
((PARAM) == GFXTIM_ABSOLUTE_LINE_TIME))
|
||||
|
||||
#define IS_GFXTIM_ABSOLUTE_LINE_COMPARATOR(PARAM) (((PARAM) == GFXTIM_ABSOLUTE_LINE_COMPARE1) || \
|
||||
((PARAM) == GFXTIM_ABSOLUTE_LINE_COMPARE2))
|
||||
|
||||
#define IS_GFXTIM_RELATIVE_TIMER(PARAM) (((PARAM) == GFXTIM_RELATIVE_TIMER1) || \
|
||||
((PARAM) == GFXTIM_RELATIVE_TIMER2))
|
||||
|
||||
#define IS_GFXTIM_RELATIVE_COUNTER_MODE(PARAM) (((PARAM) == GFXTIM_MODE_ONE_SHOT) || \
|
||||
((PARAM) == GFXTIM_MODE_CONTINUOUS))
|
||||
|
||||
#define IS_GFXTIM_EVENT_LINE(PARAM) (((PARAM) == GFXTIM_LINE_EVENT_NONE) || \
|
||||
((PARAM) == GFXTIM_LINE_EVENT_ALC_OVERFLOW) || \
|
||||
((PARAM) == GFXTIM_LINE_EVENT_TE) || \
|
||||
((PARAM) == GFXTIM_LINE_EVENT_ALC1_COMPARE) || \
|
||||
((PARAM) == GFXTIM_LINE_EVENT_ALC2_COMPARE))
|
||||
|
||||
#define IS_GFXTIM_EVENT_FRAME(PARAM) (((PARAM) == GFXTIM_FRAME_EVENT_NONE) || \
|
||||
((PARAM) == GFXTIM_FRAME_EVENT_AFC_OVERFLOW) || \
|
||||
((PARAM) == GFXTIM_FRAME_EVENT_AFC_COMPARE) || \
|
||||
((PARAM) == GFXTIM_FRAME_EVENT_RFC1_RELOAD) || \
|
||||
((PARAM) == GFXTIM_FRAME_EVENT_RFC2_RELOAD))
|
||||
|
||||
#define IS_GFXTIM_EVENT_GENERATOR(PARAM) (((PARAM) == GFXTIM_EVENT_GENERATOR_1) || \
|
||||
((PARAM) == GFXTIM_EVENT_GENERATOR_2) || \
|
||||
((PARAM) == GFXTIM_EVENT_GENERATOR_3) || \
|
||||
((PARAM) == GFXTIM_EVENT_GENERATOR_4))
|
||||
|
||||
|
||||
#define IS_GFXTIM_CLOCK_GENERATOR_COUNTER_FORCE_RELOAD(PARAM) (((PARAM) == GFXTIM_LINE_CLK_COUNTER) || \
|
||||
((PARAM) == GFXTIM_FRAME_CLK_COUNTER) || \
|
||||
((PARAM) == (GFXTIM_LINE_CLK_COUNTER | \
|
||||
GFXTIM_FRAME_CLK_COUNTER)))
|
||||
|
||||
|
||||
#define IS_GFXTIM_WATCHDOG_HW_RELOAD_CONFIG(PARAM) (((PARAM) == GFXTIM_WATCHDOG_HW_RELOAD_DISABLE) || \
|
||||
((PARAM) == GFXTIM_WATCHDOG_HW_RELOAD_RISING_EDGE) || \
|
||||
((PARAM) == GFXTIM_WATCHDOG_HW_RELOAD_FALLING_EDGE))
|
||||
|
||||
#define IS_GFXTIM_WATCHDOG_CLOCK_SRC(PARAM) (((PARAM) == GFXTIM_WATCHDOG_CLK_SRC_LINE_CLK) || \
|
||||
((PARAM) == GFXTIM_WATCHDOG_CLK_SRC_FRAME_CLK) || \
|
||||
((PARAM) == GFXTIM_WATCHDOG_CLK_SRC_HSYNC_RISING) || \
|
||||
((PARAM) == GFXTIM_WATCHDOG_CLK_SRC_HSYNC_FALLING) || \
|
||||
((PARAM) == GFXTIM_WATCHDOG_CLK_SRC_VSYNC_RISING) || \
|
||||
((PARAM) == GFXTIM_WATCHDOG_CLK_SRC_VSYNC_FALLING) || \
|
||||
((PARAM) == GFXTIM_WATCHDOG_CLK_SRC_TE_RISING) || \
|
||||
((PARAM) == GFXTIM_WATCHDOG_CLK_SRC_TE_FALLING) || \
|
||||
((PARAM) == GFXTIM_WATCHDOG_CLK_SRC_EVENT_1) || \
|
||||
((PARAM) == GFXTIM_WATCHDOG_CLK_SRC_EVENT_2) || \
|
||||
((PARAM) == GFXTIM_WATCHDOG_CLK_SRC_EVENT_3) || \
|
||||
((PARAM) == GFXTIM_WATCHDOG_CLK_SRC_EVENT_4))
|
||||
#define IS_GFXTIM_WATCHDOG_VALUE(PARAM) ((PARAM) <= 65535U)
|
||||
#define IS_GFXTIM_RELATIVE_FRAME_VALUE(PARAM) ((PARAM) <= 4095U)
|
||||
#define IS_GFXTIM_ABSOLUTE_FRAME_VALUE(PARAM) ((PARAM) <= 1048575U)
|
||||
#define IS_GFXTIM_ABSOLUTE_LINE_VALUE(PARAM) ((PARAM) <= 4095U)
|
||||
#define IS_GFXTIM_LCC_RELOAD_VALUE(PARAM) ((PARAM) <= 4194303U)
|
||||
#define IS_GFXTIM_FCC_RELOAD_VALUE(PARAM) ((PARAM) <= 4095U)
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup GFXTIM_Exported_Macros GFXTIM Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset GFXTIM handle state.
|
||||
* @param __HANDLE__ GFXTIM handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_GFXTIM_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_GFXTIM_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */
|
||||
#define __HAL_GFXTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_GFXTIM_STATE_RESET)
|
||||
#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified GFXTIM flag is set or not.
|
||||
* @param __HANDLE__ GFXTIM handle
|
||||
* @param __FLAG__ GFXTIM flag
|
||||
* This parameter can be one or a combination of the following values:
|
||||
* @arg @ref GFXTIM_FLAG_AFCO Absolute Frame Counter Overflow Flag
|
||||
* @arg @ref GFXTIM_FLAG_ALCO Absolute Line Counter Overflow Flag
|
||||
* @arg @ref GFXTIM_FLAG_TE Tearing Effect Flag
|
||||
* @arg @ref GFXTIM_FLAG_AFCC1 Absolute Frame Counter Compare 1 Flag
|
||||
* @arg @ref GFXTIM_FLAG_ALCC1 Absolute Line Counter Compare 1 Flag
|
||||
* @arg @ref GFXTIM_FLAG_ALCC2 Absolute Line Counter Compare 2 Flag
|
||||
* @arg @ref GFXTIM_FLAG_RFC1R Relative Frame Counter 1 Reload Flag
|
||||
* @arg @ref GFXTIM_FLAG_RFC2R Relative Frame Counter 2 Reload Flag
|
||||
* @arg @ref GFXTIM_FLAG_EV1 Event 1 Flag
|
||||
* @arg @ref GFXTIM_FLAG_EV2 Event 2 Flag
|
||||
* @arg @ref GFXTIM_FLAG_EV3 Event 3 Flag
|
||||
* @arg @ref GFXTIM_FLAG_EV4 Event 4 Flag
|
||||
* @arg @ref GFXTIM_FLAG_WDGA Watchdog Alarm Flag
|
||||
* @arg @ref GFXTIM_FLAG_WDGP Watchdog Pre-alarm Flag
|
||||
* @retval State of flag (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_GFXTIM_GET_FLAG(__HANDLE__, __FLAG__)\
|
||||
((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Clear the specified GFXTIM flag.
|
||||
* @param __HANDLE__ GFXTIM handle
|
||||
* @param __FLAG__ GFXTIM flag
|
||||
* This parameter can be one or a combination of the following values:
|
||||
* @arg @ref GFXTIM_FLAG_AFCO Absolute Frame Counter Overflow Flag
|
||||
* @arg @ref GFXTIM_FLAG_ALCO Absolute Line Counter Overflow Flag
|
||||
* @arg @ref GFXTIM_FLAG_TE Tearing Effect Flag
|
||||
* @arg @ref GFXTIM_FLAG_AFCC1 Absolute Frame Counter Compare 1 Flag
|
||||
* @arg @ref GFXTIM_FLAG_ALCC1 Absolute Line Counter Compare 1 Flag
|
||||
* @arg @ref GFXTIM_FLAG_ALCC2 Absolute Line Counter Compare 2 Flag
|
||||
* @arg @ref GFXTIM_FLAG_RFC1R Relative Frame Counter 1 Reload Flag
|
||||
* @arg @ref GFXTIM_FLAG_RFC2R Relative Frame Counter 2 Reload Flag
|
||||
* @arg @ref GFXTIM_FLAG_EV1 Event 1 Flag
|
||||
* @arg @ref GFXTIM_FLAG_EV2 Event 2 Flag
|
||||
* @arg @ref GFXTIM_FLAG_EV3 Event 3 Flag
|
||||
* @arg @ref GFXTIM_FLAG_EV4 Event 4 Flag
|
||||
* @arg @ref GFXTIM_FLAG_WDGA Watchdog Alarm Flag
|
||||
* @arg @ref GFXTIM_FLAG_WDGP Watchdog Pre-alarm Flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_GFXTIM_CLEAR_FLAG(__HANDLE__, __FLAG__)\
|
||||
(((__HANDLE__)->Instance->ICR) = (__FLAG__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup GFXTIM_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
/** @addtogroup GFXTIM_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_GFXTIM_Init(GFXTIM_HandleTypeDef *hgfxtim);
|
||||
HAL_StatusTypeDef HAL_GFXTIM_DeInit(GFXTIM_HandleTypeDef *hgfxtim);
|
||||
void HAL_GFXTIM_MspInit(GFXTIM_HandleTypeDef *hgfxtim);
|
||||
void HAL_GFXTIM_MspDeInit(GFXTIM_HandleTypeDef *hgfxtim);
|
||||
#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_GFXTIM_RegisterCallback(GFXTIM_HandleTypeDef *hgfxtim,
|
||||
HAL_GFXTIM_CallbackIDTypeDef CallbackID,
|
||||
pGFXTIM_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_GFXTIM_UnRegisterCallback(GFXTIM_HandleTypeDef *hgfxtim,
|
||||
HAL_GFXTIM_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */
|
||||
void HAL_GFXTIM_TECallback(GFXTIM_HandleTypeDef *hgfxtim);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Clock Generator functions *****************************************************/
|
||||
/** @addtogroup GFXTIM_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_GFXTIM_ClockGenerator_Config(GFXTIM_HandleTypeDef *hgfxtim,
|
||||
const GFXTIM_ClockGeneratorConfigTypeDef *pClockGeneratorConfig);
|
||||
HAL_StatusTypeDef HAL_GFXTIM_ClockGenerator_Reload(GFXTIM_HandleTypeDef *hgfxtim, uint32_t ClockGeneratorCounter);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Absolute Timer functions *****************************************/
|
||||
/** @addtogroup GFXTIM_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_GFXTIM_AbsoluteTimer_Config(GFXTIM_HandleTypeDef *hgfxtim,
|
||||
const GFXTIM_AbsoluteTimerConfigTypeDef *pAbsoluteTimerConfig);
|
||||
HAL_StatusTypeDef HAL_GFXTIM_AbsoluteTimer_Start(GFXTIM_HandleTypeDef *hgfxtim);
|
||||
HAL_StatusTypeDef HAL_GFXTIM_AbsoluteTimer_Stop(GFXTIM_HandleTypeDef *hgfxtim);
|
||||
HAL_StatusTypeDef HAL_GFXTIM_AbsoluteTimer_Reset(GFXTIM_HandleTypeDef *hgfxtim);
|
||||
HAL_StatusTypeDef HAL_GFXTIM_AbsoluteTimer_GetCounter(const GFXTIM_HandleTypeDef *hgfxtim, uint32_t AbsoluteTime,
|
||||
uint32_t *pValue);
|
||||
HAL_StatusTypeDef HAL_GFXTIM_AbsoluteTimer_SetFrameCompare(GFXTIM_HandleTypeDef *hgfxtim, uint32_t Value);
|
||||
HAL_StatusTypeDef HAL_GFXTIM_AbsoluteTimer_SetLineCompare(GFXTIM_HandleTypeDef *hgfxtim,
|
||||
uint32_t AbsoluteLineComparator,
|
||||
uint32_t Value);
|
||||
void HAL_GFXTIM_AbsoluteTimer_AFCC1Callback(GFXTIM_HandleTypeDef *hgfxtim);
|
||||
void HAL_GFXTIM_AbsoluteTimer_AFCOFCallback(GFXTIM_HandleTypeDef *hgfxtim);
|
||||
void HAL_GFXTIM_AbsoluteTimer_ALCC1Callback(GFXTIM_HandleTypeDef *hgfxtim);
|
||||
void HAL_GFXTIM_AbsoluteTimer_ALCC2Callback(GFXTIM_HandleTypeDef *hgfxtim);
|
||||
void HAL_GFXTIM_AbsoluteTimer_ALCOFCallback(GFXTIM_HandleTypeDef *hgfxtim);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Relative Timer functions *****************************************/
|
||||
/** @addtogroup GFXTIM_Exported_Functions_Group4
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_GFXTIM_RelativeTimer_Config(GFXTIM_HandleTypeDef *hgfxtim,
|
||||
const GFXTIM_RelativeTimerConfigTypeDef *pRelativeTimerConfig,
|
||||
uint32_t RelativeTimer);
|
||||
HAL_StatusTypeDef HAL_GFXTIM_RelativeTimer_Start(GFXTIM_HandleTypeDef *hgfxtim, uint32_t RelativeTimer);
|
||||
HAL_StatusTypeDef HAL_GFXTIM_RelativeTimer_Stop(GFXTIM_HandleTypeDef *hgfxtim, uint32_t RelativeTimer);
|
||||
HAL_StatusTypeDef HAL_GFXTIM_RelativeTimer_ForceReload(GFXTIM_HandleTypeDef *hgfxtim, uint32_t RelativeTimer);
|
||||
HAL_StatusTypeDef HAL_GFXTIM_RelativeTimer_SetReload(GFXTIM_HandleTypeDef *hgfxtim, uint32_t RelativeTimer,
|
||||
uint32_t Value);
|
||||
HAL_StatusTypeDef HAL_GFXTIM_RelativeTimer_GetCounter(const GFXTIM_HandleTypeDef *hgfxtim, uint32_t RelativeTimer,
|
||||
uint32_t *pValue);
|
||||
void HAL_GFXTIM_RelativeTimer_RFC1RCallback(GFXTIM_HandleTypeDef *hgfxtim);
|
||||
void HAL_GFXTIM_RelativeTimer_RFC2RCallback(GFXTIM_HandleTypeDef *hgfxtim);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Event Generator functions *****************************************/
|
||||
/** @addtogroup GFXTIM_Exported_Functions_Group5
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_GFXTIM_EventGenerator_Config(GFXTIM_HandleTypeDef *hgfxtim, uint32_t EventGenerator,
|
||||
const GFXTIM_EventGeneratorConfigTypeDef *pEventGeneratorConfig);
|
||||
HAL_StatusTypeDef HAL_GFXTIM_EventGenerator_Enable(GFXTIM_HandleTypeDef *hgfxtim, uint32_t EventGenerator);
|
||||
HAL_StatusTypeDef HAL_GFXTIM_EventGenerator_Disable(GFXTIM_HandleTypeDef *hgfxtim, uint32_t EventGenerator);
|
||||
void HAL_GFXTIM_EventGenerator_EV1Callback(GFXTIM_HandleTypeDef *hgfxtim);
|
||||
void HAL_GFXTIM_EventGenerator_EV2Callback(GFXTIM_HandleTypeDef *hgfxtim);
|
||||
void HAL_GFXTIM_EventGenerator_EV3Callback(GFXTIM_HandleTypeDef *hgfxtim);
|
||||
void HAL_GFXTIM_EventGenerator_EV4Callback(GFXTIM_HandleTypeDef *hgfxtim);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Watchdog functions *****************************************/
|
||||
/** @addtogroup GFXTIM_Exported_Functions_Group6
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_GFXTIM_WatchdogTimer_Config(GFXTIM_HandleTypeDef *hgfxtim,
|
||||
const GFXTIM_WatchdogConfigTypeDef *pWatchdogConfig);
|
||||
HAL_StatusTypeDef HAL_GFXTIM_WatchdogTimer_Enable(GFXTIM_HandleTypeDef *hgfxtim);
|
||||
HAL_StatusTypeDef HAL_GFXTIM_WatchdogTimer_Disable(GFXTIM_HandleTypeDef *hgfxtim);
|
||||
HAL_StatusTypeDef HAL_GFXTIM_WatchdogTimer_Refresh(GFXTIM_HandleTypeDef *hgfxtim);
|
||||
void HAL_GFXTIM_WatchdogTimer_AlarmCallback(GFXTIM_HandleTypeDef *hgfxtim);
|
||||
void HAL_GFXTIM_WatchdogTimer_PreAlarmCallback(GFXTIM_HandleTypeDef *hgfxtim);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Generic functions *********************************************************/
|
||||
/** @addtogroup GFXTIM_Exported_Functions_Group7
|
||||
* @{
|
||||
*/
|
||||
void HAL_GFXTIM_IRQHandler(GFXTIM_HandleTypeDef *hgfxtim);
|
||||
void HAL_GFXTIM_ErrorCallback(GFXTIM_HandleTypeDef *hgfxtim);
|
||||
uint32_t HAL_GFXTIM_GetError(const GFXTIM_HandleTypeDef *hgfxtim);
|
||||
HAL_GFXTIM_StateTypeDef HAL_GFXTIM_GetState(const GFXTIM_HandleTypeDef *hgfxtim);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* GFXTIM */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7RSxx_HAL_GFXTIM_H */
|
||||
|
|
@ -1,326 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7rsxx_hal_gpio.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of GPIO HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7RSxx_HAL_GPIO_H
|
||||
#define STM32H7RSxx_HAL_GPIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7rsxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H7RSxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO GPIO
|
||||
* @brief GPIO HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Types GPIO Exported Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief GPIO Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
|
||||
This parameter can be any value of @ref GPIO_pins */
|
||||
|
||||
uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_mode */
|
||||
|
||||
uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_pull */
|
||||
|
||||
uint32_t Speed; /*!< Specifies the speed for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_speed */
|
||||
|
||||
uint32_t Alternate; /*!< Peripheral to be connected to the selected pins
|
||||
This parameter can be a value of @ref GPIOEx_Alternate_function_selection */
|
||||
} GPIO_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief GPIO Bit SET and Bit RESET enumeration
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_PIN_RESET = 0U,
|
||||
GPIO_PIN_SET
|
||||
} GPIO_PinState;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup GPIO_pins GPIO pins
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
|
||||
#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
|
||||
#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
|
||||
#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
|
||||
#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
|
||||
#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
|
||||
#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
|
||||
#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
|
||||
#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
|
||||
#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
|
||||
#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
|
||||
#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
|
||||
#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
|
||||
#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
|
||||
#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
|
||||
#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
|
||||
#define GPIO_PIN_ALL ((uint16_t)0xFFFF) /* All pins selected */
|
||||
|
||||
#define GPIO_PIN_MASK (0x0000FFFFu) /* PIN mask for assert test */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_mode GPIO mode
|
||||
* @brief GPIO Configuration Mode
|
||||
* Elements values convention: 0x00WX00YZ
|
||||
* - W : EXTI trigger detection on 3 bits
|
||||
* - X : EXTI mode (IT or Event) on 2 bits
|
||||
* - Y : Output type (Push Pull or Open Drain) on 1 bit
|
||||
* - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */
|
||||
#define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */
|
||||
#define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */
|
||||
#define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */
|
||||
#define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */
|
||||
#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */
|
||||
#define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */
|
||||
#define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */
|
||||
#define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
|
||||
#define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */
|
||||
#define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */
|
||||
#define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_speed GPIO speed
|
||||
* @brief GPIO Output Maximum frequency
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_SPEED_FREQ_LOW 0x00000000u /*!< Low speed */
|
||||
#define GPIO_SPEED_FREQ_MEDIUM 0x00000001u /*!< Medium speed */
|
||||
#define GPIO_SPEED_FREQ_HIGH 0x00000002u /*!< High speed */
|
||||
#define GPIO_SPEED_FREQ_VERY_HIGH 0x00000003u /*!< Very high speed */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_pull GPIO pull
|
||||
* @brief GPIO Pull-Up or Pull-Down Activation
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_NOPULL 0x00000000u /*!< No Pull-up or Pull-down activation */
|
||||
#define GPIO_PULLUP 0x00000001u /*!< Pull-up activation */
|
||||
#define GPIO_PULLDOWN 0x00000002u /*!< Pull-down activation */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified EXTI line flag is set or not.
|
||||
* @param __EXTI_LINE__ specifies the EXTI line flag to check.
|
||||
* This parameter can be GPIO_PIN_x where x can be(0..15)
|
||||
* @retval The new state of __EXTI_LINE__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Clear the EXTI's line pending flags.
|
||||
* @param __EXTI_LINE__ specifies the EXTI lines flags to clear.
|
||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified EXTI line is asserted or not.
|
||||
* @param __EXTI_LINE__ specifies the EXTI line to check.
|
||||
* This parameter can be GPIO_PIN_x where x can be(0..15)
|
||||
* @retval The new state of __EXTI_LINE__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Clear the EXTI's line pending bits.
|
||||
* @param __EXTI_LINE__ specifies the EXTI lines to clear.
|
||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Generate a Software interrupt on selected EXTI line(s).
|
||||
* @param __EXTI_LINE__ specifies the EXTI line to be set.
|
||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 = (__EXTI_LINE__))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Private_Constants GPIO Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_MODE_Pos 0u
|
||||
#define GPIO_MODE (0x3uL << GPIO_MODE_Pos)
|
||||
#define MODE_INPUT (0x0uL << GPIO_MODE_Pos)
|
||||
#define MODE_OUTPUT (0x1uL << GPIO_MODE_Pos)
|
||||
#define MODE_AF (0x2uL << GPIO_MODE_Pos)
|
||||
#define MODE_ANALOG (0x3uL << GPIO_MODE_Pos)
|
||||
#define OUTPUT_TYPE_Pos 4u
|
||||
#define OUTPUT_TYPE (0x1uL << OUTPUT_TYPE_Pos)
|
||||
#define OUTPUT_PP (0x0uL << OUTPUT_TYPE_Pos)
|
||||
#define OUTPUT_OD (0x1uL << OUTPUT_TYPE_Pos)
|
||||
#define EXTI_MODE_Pos 16u
|
||||
#define EXTI_MODE (0x3uL << EXTI_MODE_Pos)
|
||||
#define EXTI_IT (0x1uL << EXTI_MODE_Pos)
|
||||
#define EXTI_EVT (0x2uL << EXTI_MODE_Pos)
|
||||
#define TRIGGER_MODE_Pos 20u
|
||||
#define TRIGGER_MODE (0x7uL << TRIGGER_MODE_Pos)
|
||||
#define TRIGGER_RISING (0x1uL << TRIGGER_MODE_Pos)
|
||||
#define TRIGGER_FALLING (0x2uL << TRIGGER_MODE_Pos)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Private_Macros GPIO Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
|
||||
|
||||
#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00u) &&\
|
||||
(((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00u))
|
||||
|
||||
#define IS_GPIO_COMMON_PIN(__RESETMASK__, __SETMASK__) \
|
||||
(((uint32_t)(__RESETMASK__) & (uint32_t)(__SETMASK__)) == 0x00u)
|
||||
|
||||
#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\
|
||||
((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\
|
||||
((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\
|
||||
((__MODE__) == GPIO_MODE_AF_PP) ||\
|
||||
((__MODE__) == GPIO_MODE_AF_OD) ||\
|
||||
((__MODE__) == GPIO_MODE_IT_RISING) ||\
|
||||
((__MODE__) == GPIO_MODE_IT_FALLING) ||\
|
||||
((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\
|
||||
((__MODE__) == GPIO_MODE_EVT_RISING) ||\
|
||||
((__MODE__) == GPIO_MODE_EVT_FALLING) ||\
|
||||
((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\
|
||||
((__MODE__) == GPIO_MODE_ANALOG))
|
||||
|
||||
#define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW) ||\
|
||||
((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) ||\
|
||||
((__SPEED__) == GPIO_SPEED_FREQ_HIGH) ||\
|
||||
((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH))
|
||||
|
||||
#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) ||\
|
||||
((__PULL__) == GPIO_PULLUP) || \
|
||||
((__PULL__) == GPIO_PULLDOWN))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include GPIO HAL Extended module */
|
||||
#include "stm32h7rsxx_hal_gpio_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
|
||||
* @brief GPIO Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *GPIO_Init);
|
||||
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
|
||||
* @brief IO operation functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
|
||||
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
|
||||
void HAL_GPIO_WriteMultipleStatePin(GPIO_TypeDef *GPIOx, uint16_t PinReset, uint16_t PinSet);
|
||||
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
|
||||
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
|
||||
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
|
||||
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7RSxx_HAL_GPIO_H */
|
||||
|
||||
|
|
@ -1,266 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7rsxx_hal_gpio_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of GPIO HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7RSxx_HAL_GPIO_EX_H
|
||||
#define STM32H7RSxx_HAL_GPIO_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7rsxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H7RSxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIOEx GPIOEx
|
||||
* @brief GPIO Extended HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Private defines -----------------------------------------------------------*/
|
||||
|
||||
/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief AF 0 selection
|
||||
*/
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO (MCO1 and MCO2) Alternate Function mapping */
|
||||
#define GPIO_AF0_JTAG ((uint8_t)0x00) /*!< JTAG Alternate Function mapping */
|
||||
#define GPIO_AF0_SWD ((uint8_t)0x00) /*!< SWD Alternate Function mapping */
|
||||
#define GPIO_AF0_RTC ((uint8_t)0x00) /*!< RCT_OUT Alternate Function mapping */
|
||||
#define GPIO_AF0_TRACE ((uint8_t)0x00) /*!< TRACE Alternate Function mapping */
|
||||
#define GPIO_AF0_PWR ((uint8_t)0x00) /*!< PWR Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 1 selection
|
||||
*/
|
||||
#define GPIO_AF1_ADF1 ((uint8_t)0x01) /*!< ADF1 Alternate Function mapping */
|
||||
#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /*!< LPTIM1 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /*!< TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM16 ((uint8_t)0x01) /*!< TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM17 ((uint8_t)0x01) /*!< TIM17 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 2 selection
|
||||
*/
|
||||
#define GPIO_AF2_GFXTIM ((uint8_t)0x02) /*!< GFXTIM Alternate Function mapping */
|
||||
#define GPIO_AF2_SAI1 ((uint8_t)0x02) /*!< SAI1 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM3 ((uint8_t)0x02) /*!< TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM4 ((uint8_t)0x02) /*!< TIM4 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM5 ((uint8_t)0x02) /*!< TIM5 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM12 ((uint8_t)0x02) /*!< TIM12 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM15 ((uint8_t)0x02) /*!< TIM15 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 3 selection
|
||||
*/
|
||||
#define GPIO_AF3_ADF1 ((uint8_t)0x03) /*!< ADF1 Alternate Function mapping */
|
||||
#define GPIO_AF3_LPTIM2 ((uint8_t)0x03) /*!< LPTIM2 Alternate Function mapping */
|
||||
#define GPIO_AF3_LPTIM3 ((uint8_t)0x03) /*!< LPTIM3 Alternate Function mapping */
|
||||
#define GPIO_AF3_LPTIM4 ((uint8_t)0x03) /*!< LPTIM4 Alternate Function mapping */
|
||||
#define GPIO_AF3_LPTIM5 ((uint8_t)0x03) /*!< LPTIM5 Alternate Function mapping */
|
||||
#define GPIO_AF3_LPUART1 ((uint8_t)0x03) /*!< LPUART1 Alternate Function mapping */
|
||||
#define GPIO_AF3_TIM9 ((uint8_t)0x03) /*!< TIM9 Alternate Function mapping */
|
||||
#define GPIO_AF3_USART3 ((uint8_t)0x03) /*!< USART3 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 4 selection
|
||||
*/
|
||||
#define GPIO_AF4_CEC ((uint8_t)0x04) /*!< CEC Alternate Function mapping */
|
||||
#define GPIO_AF4_DCMIPP ((uint8_t)0x04) /*!< DCMIPP Alternate Function mapping */
|
||||
#define GPIO_AF4_ETH ((uint8_t)0x04) /*!< ETH Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /*!< I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C2 ((uint8_t)0x04) /*!< I2C2 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C3 ((uint8_t)0x04) /*!< I2C3 Alternate Function mapping */
|
||||
#define GPIO_AF4_I3C1 ((uint8_t)0x04) /*!< I3C1 Alternate Function mapping */
|
||||
#define GPIO_AF4_TIM15 ((uint8_t)0x04) /*!< TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF4_USART1 ((uint8_t)0x04) /*!< USART1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 5 selection
|
||||
*/
|
||||
#define GPIO_AF5_CEC ((uint8_t)0x05) /*!< CEC Alternate Function mapping */
|
||||
#define GPIO_AF5_DCMIPP ((uint8_t)0x05) /*!< DCMIPP Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI1/I2S1 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< SPI2/I2S2 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI3 ((uint8_t)0x05) /*!< SPI3/I2S3 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI4 ((uint8_t)0x05) /*!< SPI4 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI5 ((uint8_t)0x05) /*!< SPI5 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI6 ((uint8_t)0x05) /*!< SPI6/I2S6 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 6 selection
|
||||
*/
|
||||
#define GPIO_AF6_PSSI ((uint8_t)0x06) /*!< PSSI Alternate Function mapping */
|
||||
#define GPIO_AF6_SAI1 ((uint8_t)0x06) /*!< SAI1 Alternate Function mapping */
|
||||
#define GPIO_AF6_SDMMC1 ((uint8_t)0x06) /*!< SDMMC1 Alternate Function mapping */
|
||||
#define GPIO_AF6_SPI3 ((uint8_t)0x06) /*!< SPI3/I2S3 Alternate Function mapping */
|
||||
#define GPIO_AF6_SPI4 ((uint8_t)0x06) /*!< SPI4 Alternate Function mapping */
|
||||
#define GPIO_AF6_UART4 ((uint8_t)0x06) /*!< UART4 Alternate Function mapping */
|
||||
#define GPIO_AF6_UCPD ((uint8_t)0x06) /*!< UCPD Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 7 selection
|
||||
*/
|
||||
#define GPIO_AF7_FMC ((uint8_t)0x07) /*!< FMC Alternate Function mapping */
|
||||
#define GPIO_AF7_SDMMC1 ((uint8_t)0x07) /*!< SDMMC1 Alternate Function mapping */
|
||||
#define GPIO_AF7_SPI2 ((uint8_t)0x07) /*!< SPI2/I2S2 Alternate Function mapping */
|
||||
#define GPIO_AF7_SPI3 ((uint8_t)0x07) /*!< SPI3/I2S3 Alternate Function mapping */
|
||||
#define GPIO_AF7_SPI6 ((uint8_t)0x07) /*!< SPI6/I2S6 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART1 ((uint8_t)0x07) /*!< USART1 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART2 ((uint8_t)0x07) /*!< USART2 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART3 ((uint8_t)0x07) /*!< USART3 Alternate Function mapping */
|
||||
#define GPIO_AF7_UART7 ((uint8_t)0x07) /*!< UART7 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 8 selection
|
||||
*/
|
||||
#define GPIO_AF8_GFXTIM ((uint8_t)0x08) /*!< GFXTIM Alternate Function mapping */
|
||||
#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /*!< LPUART1 Alternate Function mapping */
|
||||
#define GPIO_AF8_PSSI ((uint8_t)0x08) /*!< PSSI Alternate Function mapping */
|
||||
#define GPIO_AF8_SAI2 ((uint8_t)0x08) /*!< SAI2 Alternate Function mapping */
|
||||
#define GPIO_AF8_SDMMC1 ((uint8_t)0x08) /*!< SDMMC1 Alternate Function mapping */
|
||||
#define GPIO_AF8_SPDIFRX ((uint8_t)0x08) /*!< SPDIFRX Alternate Function mapping */
|
||||
#define GPIO_AF8_SPI6 ((uint8_t)0x08) /*!< SPI6/I2S6 Alternate Function mapping */
|
||||
#define GPIO_AF8_UART4 ((uint8_t)0x08) /*!< UART4 Alternate Function mapping */
|
||||
#define GPIO_AF8_UART5 ((uint8_t)0x08) /*!< UART5 Alternate Function mapping */
|
||||
#define GPIO_AF8_UART8 ((uint8_t)0x08) /*!< UART8 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 9 selection
|
||||
*/
|
||||
#define GPIO_AF9_FDCAN1 ((uint8_t)0x09) /*!< FDCAN1 Alternate Function mapping */
|
||||
#define GPIO_AF9_FDCAN2 ((uint8_t)0x09) /*!< FDCAN2 Alternate Function mapping */
|
||||
#define GPIO_AF9_FMC ((uint8_t)0x09) /*!< FMC Alternate Function mapping */
|
||||
#define GPIO_AF9_XSPIM_P1 ((uint8_t)0x09) /*!< XSPIM Manager Port 1 Alternate Function mapping */
|
||||
#define GPIO_AF9_XSPIM_P2 ((uint8_t)0x09) /*!< XSPIM Manager Port 2 Alternate Function mapping */
|
||||
#define GPIO_AF9_PSSI ((uint8_t)0x09) /*!< PSSI Alternate Function mapping */
|
||||
#define GPIO_AF9_SDMMC2 ((uint8_t)0x09) /*!< SDMMC2 Alternate Function mapping */
|
||||
#define GPIO_AF9_SPDIFRX ((uint8_t)0x09) /*!< SPDIFRX Alternate Function mapping */
|
||||
#define GPIO_AF9_SPI5 ((uint8_t)0x09) /*!< SPI5 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM13 ((uint8_t)0x09) /*!< TIM13 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM14 ((uint8_t)0x09) /*!< TIM14 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 10 selection
|
||||
*/
|
||||
#define GPIO_AF10_CRS ((uint8_t)0x0A) /*!< CRS Alternate Function mapping */
|
||||
#define GPIO_AF10_FMC ((uint8_t)0x0A) /*!< FMC Alternate Function mapping */
|
||||
#define GPIO_AF10_LTDC ((uint8_t)0x0A) /*!< LTDC Alternate Function mapping */
|
||||
#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /*!< OTG FS Alternate Function mapping */
|
||||
#define GPIO_AF10_OTG_HS ((uint8_t)0x0A) /*!< OTG HS Alternate Function mapping */
|
||||
#define GPIO_AF10_SAI2 ((uint8_t)0x0A) /*!< SAI2 Alternate Function mapping */
|
||||
#define GPIO_AF10_SDMMC2 ((uint8_t)0x0A) /*!< SDMMC2 Alternate Function mapping */
|
||||
#define GPIO_AF10_SPI1 ((uint8_t)0x0A) /*!< SPI1/I2S1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 11 selection
|
||||
*/
|
||||
#define GPIO_AF11_ETH ((uint8_t)0x0B) /*!< ETH Alternate Function mapping */
|
||||
#define GPIO_AF11_LTDC ((uint8_t)0x0B) /*!< LTDC Alternate Function mapping */
|
||||
#define GPIO_AF11_MDIOS ((uint8_t)0x0B) /*!< MDIOS Alternate Function mapping */
|
||||
#define GPIO_AF11_SDMMC1 ((uint8_t)0x0B) /*!< SDMMC1 Alternate Function mapping */
|
||||
#define GPIO_AF11_SDMMC2 ((uint8_t)0x0B) /*!< SDMMC2 Alternate Function mapping */
|
||||
#define GPIO_AF11_UART7 ((uint8_t)0x0B) /*!< UART7 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 12 selection
|
||||
*/
|
||||
#define GPIO_AF12_FMC ((uint8_t)0x0C) /*!< FMC Alternate Function mapping */
|
||||
#define GPIO_AF12_GFXTIM ((uint8_t)0x0C) /*!< GFXTIM Alternate Function mapping */
|
||||
#define GPIO_AF12_LTDC ((uint8_t)0x0C) /*!< TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /*!< SDMMC1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 13 selection
|
||||
*/
|
||||
#define GPIO_AF13_DCMIPP ((uint8_t)0x0D) /*!< DCMIPP Alternate Function mapping */
|
||||
#define GPIO_AF13_GFXTIM ((uint8_t)0x0D) /*!< GFXTIM Alternate Function mapping */
|
||||
#define GPIO_AF13_LTDC ((uint8_t)0x0D) /*!< TIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 14 selection
|
||||
*/
|
||||
#define GPIO_AF14_FMC ((uint8_t)0x0E) /*!< FMC Alternate Function mapping */
|
||||
#define GPIO_AF14_LTDC ((uint8_t)0x0E) /*!< LTDC Alternate Function mapping */
|
||||
#define GPIO_AF14_MDIOS ((uint8_t)0x0E) /*!< MDIOS Alternate Function mapping */
|
||||
#define GPIO_AF14_PSSI ((uint8_t)0x0E) /*!< PSSI Alternate Function mapping */
|
||||
#define GPIO_AF14_TIM1 ((uint8_t)0x0E) /*!< TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF14_UART5 ((uint8_t)0x0E) /*!< UART5 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 15 selection
|
||||
*/
|
||||
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /*!< EVENTOUT Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIOEx_Get_Port_Index GPIOEx Get Port Index
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_GET_INDEX(__GPIOx__) (((uint32_t )(__GPIOx__) & (~GPIOA_BASE)) >> 10)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7RSxx_HAL_GPIO_EX_H */
|
||||
|
||||
|
|
@ -1,321 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7rsxx_hal_gpu2d.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of GPU2D HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7RSxx_HAL_GPU2D_H
|
||||
#define STM32H7RSxx_HAL_GPU2D_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7rsxx_hal_def.h"
|
||||
|
||||
#if defined (GPU2D)
|
||||
|
||||
/** @addtogroup STM32H7RSxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPU2D GPU2D
|
||||
* @brief GPU2D HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup GPU2D_Exported_Types GPU2D Exported Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief HAL GPU2D State enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_GPU2D_STATE_RESET = 0x00U, /*!< GPU2D not yet initialized or disabled */
|
||||
HAL_GPU2D_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
|
||||
HAL_GPU2D_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
|
||||
HAL_GPU2D_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
|
||||
HAL_GPU2D_STATE_ERROR = 0x04U
|
||||
} HAL_GPU2D_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief GPU2D_TypeDef definition
|
||||
*/
|
||||
typedef uint32_t GPU2D_TypeDef;
|
||||
|
||||
/**
|
||||
* @brief GPU2D handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __GPU2D_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */
|
||||
{
|
||||
GPU2D_TypeDef Instance; /*!< GPU2D register base address. */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< GPU2D lock. */
|
||||
|
||||
__IO HAL_GPU2D_StateTypeDef State; /*!< GPU2D transfer state. */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< GPU2D error code. */
|
||||
|
||||
#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1)
|
||||
void (* CommandListCpltCallback)(struct __GPU2D_HandleTypeDef *hgpu2d, uint32_t CmdListID); /*!< GPU2D Command Complete Callback */
|
||||
|
||||
void (* MspInitCallback)(struct __GPU2D_HandleTypeDef *hgpu2d); /*!< GPU2D Msp Init callback */
|
||||
|
||||
void (* MspDeInitCallback)(struct __GPU2D_HandleTypeDef *hgpu2d); /*!< GPU2D Msp DeInit callback */
|
||||
#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */
|
||||
} GPU2D_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL GPU2D Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_GPU2D_MSPINIT_CB_ID = 0x00U, /*!< GPU2D MspInit callback ID */
|
||||
HAL_GPU2D_MSPDEINIT_CB_ID = 0x01U, /*!< GPU2D MspDeInit callback ID */
|
||||
} HAL_GPU2D_CallbackIDTypeDef;
|
||||
|
||||
/** @defgroup HAL_GPU2D_Callback_pointer_definition HAL GPU2D Callback pointer definition
|
||||
* @brief HAL GPU2D Callback pointer definition
|
||||
* @{
|
||||
*/
|
||||
typedef void (*pGPU2D_CallbackTypeDef)(GPU2D_HandleTypeDef *hgpu2d); /*!< pointer to an GPU2D Callback function */
|
||||
typedef void (*pGPU2D_CommandListCpltCallbackTypeDef)(GPU2D_HandleTypeDef *hgpu2d, uint32_t CmdID); /*!< pointer to an GPU2D Command List Complete Callback function */
|
||||
#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup GPU2D_Exported_Constants GPU2D Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPU2D_Error_Code_definition GPU2D Error Code definition
|
||||
* @brief GPU2D Error Code definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_GPU2D_ERROR_NONE (0x00000000U) /*!< No error */
|
||||
#define HAL_GPU2D_ERROR_TIMEOUT (0x00000001U) /*!< Timeout error */
|
||||
#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_GPU2D_ERROR_INVALID_CALLBACK (0x00000002U) /*!< Invalid callback error */
|
||||
#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPU2D_Interrupt_configuration_definition GPU2D Interrupt configuration definition
|
||||
* @brief GPU2D Interrupt definition
|
||||
* @{
|
||||
*/
|
||||
#define GPU2D_IT_CLC 0x00000001U /*!< Command List Complete Interrupt */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPU2D_Flag_definition GPU2D Flag definition
|
||||
* @brief GPU2D Flags definition
|
||||
* @{
|
||||
*/
|
||||
#define GPU2D_FLAG_CLC 0x00000001U /*!< Command List Complete Interrupt Flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros ------------------------------------------------------------*/
|
||||
/** @defgroup GPU2D_Exported_Macros GPU2D Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset GPU2D handle state
|
||||
* @param __HANDLE__: specifies the GPU2D handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_GPU2D_RESET_HANDLE_STATE(__HANDLE__) do { \
|
||||
(__HANDLE__)->State = HAL_GPU2D_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->CommandListCpltCallback = NULL; \
|
||||
} while(0)
|
||||
#else /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 0 */
|
||||
#define __HAL_GPU2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_GPU2D_STATE_RESET)
|
||||
#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */
|
||||
|
||||
/* Interrupt & Flag management */
|
||||
/**
|
||||
* @brief Get the GPU2D pending flags.
|
||||
* @param __HANDLE__: GPU2D handle
|
||||
* @param __FLAG__: flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg GPU2D_FLAG_CLC: Command List Complete interrupt mask
|
||||
* @retval The state of FLAG.
|
||||
*/
|
||||
#define __HAL_GPU2D_GET_FLAG(__HANDLE__, __FLAG__) (READ_REG(*(__IO uint32_t *)((uint32_t)(__HANDLE__)->Instance\
|
||||
+ GPU2D_ITCTRL)) & (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Clear the GPU2D pending flags.
|
||||
* @param __HANDLE__: GPU2D handle
|
||||
* @param __FLAG__: specifies the flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg GPU2D_FLAG_CLC: Command List Complete interrupt mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_GPU2D_CLEAR_FLAG(__HANDLE__, __FLAG__) do { \
|
||||
__IO uint32_t *tmpreg = \
|
||||
(__IO uint32_t *)((uint32_t)(__HANDLE__)->Instance\
|
||||
+ GPU2D_ITCTRL); \
|
||||
CLEAR_BIT(*tmpreg, __FLAG__); \
|
||||
} while(0U)
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified GPU2D interrupt source is enabled or not.
|
||||
* @param __HANDLE__: GPU2D handle
|
||||
* @param __INTERRUPT__: specifies the GPU2D interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg GPU2D_IT_CLC: Command List Complete interrupt mask
|
||||
* @retval The state of INTERRUPT source.
|
||||
*/
|
||||
#define __HAL_GPU2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_REG(*(__IO uint32_t *)\
|
||||
((uint32_t)(__HANDLE__)->Instance\
|
||||
+ GPU2D_ITCTRL)) & (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup GPU2D_Exported_Functions GPU2D Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPU2D_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions *******************************/
|
||||
HAL_StatusTypeDef HAL_GPU2D_Init(GPU2D_HandleTypeDef *hgpu2d);
|
||||
HAL_StatusTypeDef HAL_GPU2D_DeInit(GPU2D_HandleTypeDef *hgpu2d);
|
||||
void HAL_GPU2D_MspInit(GPU2D_HandleTypeDef *hgpu2d);
|
||||
void HAL_GPU2D_MspDeInit(GPU2D_HandleTypeDef *hgpu2d);
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_GPU2D_RegisterCallback(GPU2D_HandleTypeDef *hgpu2d, HAL_GPU2D_CallbackIDTypeDef CallbackID,
|
||||
pGPU2D_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_GPU2D_UnRegisterCallback(GPU2D_HandleTypeDef *hgpu2d, HAL_GPU2D_CallbackIDTypeDef CallbackID);
|
||||
HAL_StatusTypeDef HAL_GPU2D_RegisterCommandListCpltCallback(GPU2D_HandleTypeDef *hgpu2d,
|
||||
pGPU2D_CommandListCpltCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_GPU2D_UnRegisterCommandListCpltCallback(GPU2D_HandleTypeDef *hgpu2d);
|
||||
#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup GPU2D_Exported_Functions_Group2 IO operation functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* IO operation functions *******************************************************/
|
||||
uint32_t HAL_GPU2D_ReadRegister(const GPU2D_HandleTypeDef *hgpu2d, uint32_t offset);
|
||||
HAL_StatusTypeDef HAL_GPU2D_WriteRegister(GPU2D_HandleTypeDef *hgpu2d, uint32_t offset, uint32_t value);
|
||||
void HAL_GPU2D_IRQHandler(GPU2D_HandleTypeDef *hgpu2d);
|
||||
void HAL_GPU2D_ER_IRQHandler(GPU2D_HandleTypeDef *hgpu2d);
|
||||
void HAL_GPU2D_CommandListCpltCallback(GPU2D_HandleTypeDef *hgpu2d, uint32_t CmdListID);
|
||||
void HAL_GPU2D_ErrorCallback(GPU2D_HandleTypeDef *hgpu2d);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup GPU2D_Exported_Functions_Group3 Peripheral State and Error functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral State functions ***************************************************/
|
||||
HAL_GPU2D_StateTypeDef HAL_GPU2D_GetState(GPU2D_HandleTypeDef const *const hgpu2d);
|
||||
uint32_t HAL_GPU2D_GetError(GPU2D_HandleTypeDef const *const hgpu2d);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup GPU2D_Private_Constants GPU2D Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define GPU2D_ITCTRL (0x0F8U) /*!< GPU2D Interrupt Control Register Offset */
|
||||
#define GPU2D_CLID (0x148U) /*!< GPU2D Last Command List Identifier Register Offset */
|
||||
#define GPU2D_BREAKPOINT (0x080U) /*!< GPU2D Breakpoint Register Offset */
|
||||
#define GPU2D_SYS_INTERRUPT (0xff8U) /*!< GPU2D System Interrupt Register Offset */
|
||||
|
||||
/** @defgroup GPU2D_Offset GPU2D Last Register Offset
|
||||
* @{
|
||||
*/
|
||||
#define GPU2D_OFFSET 0x1000U /*!< Last GPU2D Register Offset */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup GPU2D_Private_Macros GPU2D Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_GPU2D_OFFSET(OFFSET) ((OFFSET) < GPU2D_OFFSET)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined (GPU2D) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7RSxx_HAL_GPU2D_H */
|
||||
|
||||
|
|
@ -1,579 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7rsxx_hal_hash.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of HASH HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7RSxx_HAL_HASH_H
|
||||
#define STM32H7RSxx_HAL_HASH_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7rsxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H7RSxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
#if defined (HASH)
|
||||
/** @defgroup HASH HASH
|
||||
* @brief HASH HAL module driver.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup HASH_Exported_Types HASH Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HASH Configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DataType; /*!< no swap (32-bit data), half word swap (16-bit data), byte swap (8-bit data) or bit swap
|
||||
(1-bit data). This parameter can be a value of @ref HASH_Data_Type. */
|
||||
|
||||
uint32_t KeySize; /*!< The key size is used only in HMAC operation. */
|
||||
|
||||
uint8_t *pKey; /*!< The key is used only in HMAC operation. */
|
||||
|
||||
uint32_t Algorithm; /*!< HASH algorithm MD5, SHA1 or SHA2.
|
||||
This parameter can be a value of @ref HASH_Algorithm_Selection */
|
||||
|
||||
|
||||
} HASH_ConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL State structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_HASH_STATE_RESET = 0x00U, /*!< Peripheral is not initialized */
|
||||
HAL_HASH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
|
||||
HAL_HASH_STATE_BUSY = 0x02U, /*!< Processing (hashing) is ongoing */
|
||||
HAL_HASH_STATE_SUSPENDED = 0x03U /*!< Suspended state */
|
||||
} HAL_HASH_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL phase structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_HASH_PHASE_READY = 0x01U, /*!< HASH peripheral is ready to start */
|
||||
HAL_HASH_PHASE_PROCESS = 0x02U, /*!< HASH peripheral is in HASH processing phase */
|
||||
HAL_HASH_PHASE_HMAC_STEP_1 = 0x03U, /*!< HASH peripheral is in HMAC step 1 processing phase
|
||||
(step 1 consists in entering the inner hash function key)*/
|
||||
HAL_HASH_PHASE_HMAC_STEP_2 = 0x04U, /*!< HASH peripheral is in HMAC step 2 processing phase
|
||||
(step 2 consists in entering the message text) */
|
||||
HAL_HASH_PHASE_HMAC_STEP_3 = 0x05U /*!< HASH peripheral is in HMAC step 3 processing phase
|
||||
(step 3 consists in entering the outer hash function key)*/
|
||||
|
||||
} HAL_HASH_PhaseTypeDef;
|
||||
|
||||
#if (USE_HAL_HASH_SUSPEND_RESUME == 1U)
|
||||
/**
|
||||
* @brief HAL HASH mode suspend definitions
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_HASH_SUSPEND_NONE = 0x00U, /*!< HASH peripheral suspension not requested */
|
||||
HAL_HASH_SUSPEND = 0x01U /*!< HASH peripheral suspension is requested */
|
||||
} HAL_HASH_SuspendTypeDef;
|
||||
#endif /* USE_HAL_HASH_SUSPEND_RESUME */
|
||||
|
||||
|
||||
/**
|
||||
* @brief HASH Handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __HASH_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
|
||||
{
|
||||
HASH_TypeDef *Instance; /*!< HASH Register base address */
|
||||
|
||||
HASH_ConfigTypeDef Init; /*!< HASH required parameters */
|
||||
|
||||
uint8_t const *pHashInBuffPtr; /*!< Pointer to input buffer */
|
||||
|
||||
uint8_t *pHashOutBuffPtr; /*!< Pointer to output buffer (digest) */
|
||||
|
||||
__IO uint32_t HashInCount; /*!< Counter of inputted data */
|
||||
|
||||
uint32_t Size; /*!< Size of buffer to be processed in bytes */
|
||||
|
||||
uint8_t *pHashKeyBuffPtr; /*!< Pointer to key buffer (HMAC only) */
|
||||
|
||||
HAL_HASH_PhaseTypeDef Phase; /*!< HASH peripheral phase */
|
||||
|
||||
DMA_HandleTypeDef *hdmain; /*!< HASH In DMA Handle parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< HASH Error code */
|
||||
|
||||
__IO HAL_HASH_StateTypeDef State; /*!< HASH peripheral state */
|
||||
|
||||
__IO uint32_t Accumulation; /*!< HASH multi buffers accumulation flag */
|
||||
|
||||
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
|
||||
void (* InCpltCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH input completion callback */
|
||||
|
||||
void (* DgstCpltCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH digest computation complete callback */
|
||||
|
||||
void (* ErrorCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH error callback */
|
||||
|
||||
void (* MspInitCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH Msp Init callback */
|
||||
|
||||
void (* MspDeInitCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH Msp DeInit callback */
|
||||
|
||||
#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
|
||||
#if (USE_HAL_HASH_SUSPEND_RESUME == 1U)
|
||||
__IO HAL_HASH_SuspendTypeDef SuspendRequest; /*!< HASH peripheral suspension request flag */
|
||||
|
||||
HASH_ConfigTypeDef Init_saved; /*!< Saved HASH required parameters */
|
||||
|
||||
uint8_t const *pHashInBuffPtr_saved; /*!< Saved pointer to input buffer */
|
||||
|
||||
uint8_t *pHashOutBuffPtr_saved; /*!< Saved pointer to output buffer (digest) */
|
||||
|
||||
__IO uint32_t HashInCount_saved; /*!< Saved counter of inputted data */
|
||||
|
||||
uint32_t Size_saved; /*!< Saved size of buffer to be processed */
|
||||
|
||||
uint8_t *pHashKeyBuffPtr_saved; /*!< Saved pointer to key buffer (HMAC only) */
|
||||
|
||||
HAL_HASH_PhaseTypeDef Phase_saved; /*!< Saved HASH peripheral phase */
|
||||
#endif /* USE_HAL_HASH_SUSPEND_RESUME */
|
||||
|
||||
} HASH_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U)
|
||||
/**
|
||||
* @brief HAL HASH common Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_HASH_MSPINIT_CB_ID = 0x00U, /*!< HASH MspInit callback ID */
|
||||
HAL_HASH_MSPDEINIT_CB_ID = 0x01U, /*!< HASH MspDeInit callback ID */
|
||||
HAL_HASH_INPUTCPLT_CB_ID = 0x02U, /*!< HASH input completion callback ID */
|
||||
HAL_HASH_DGSTCPLT_CB_ID = 0x03U, /*!< HASH digest computation completion callback ID */
|
||||
HAL_HASH_ERROR_CB_ID = 0x04U, /*!< HASH error callback ID */
|
||||
} HAL_HASH_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL HASH Callback pointer definition
|
||||
*/
|
||||
typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef *hhash); /*!< pointer to a HASH common callback functions */
|
||||
|
||||
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup HASH_Exported_Constants HASH Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HASH_Error_Definition HASH Error Definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_HASH_ERROR_NONE 0x00000000U /*!< No error */
|
||||
#define HAL_HASH_ERROR_BUSY 0x00000001U /*!< Busy flag error */
|
||||
#define HAL_HASH_ERROR_DMA 0x00000002U /*!< DMA-based process error */
|
||||
#define HAL_HASH_ERROR_TIMEOUT 0x00000004U /*!< Timeout error */
|
||||
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U)
|
||||
#define HAL_HASH_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HASH_Algorithm_Selection HASH algorithm selection
|
||||
* @{
|
||||
*/
|
||||
#define HASH_ALGOSELECTION_SHA1 0x00000000U /*!< HASH function is SHA1 */
|
||||
#define HASH_ALGOSELECTION_SHA224 HASH_CR_ALGO_1 /*!< HASH function is SHA224 */
|
||||
#define HASH_ALGOSELECTION_SHA256 (HASH_CR_ALGO_0 | HASH_CR_ALGO_1) /*!< HASH function is SHA256 */
|
||||
#define HASH_ALGOSELECTION_SHA384 (HASH_CR_ALGO_2 | HASH_CR_ALGO_3) /*!< HASH function is SHA384 */
|
||||
#define HASH_ALGOSELECTION_SHA512_224 (HASH_CR_ALGO_0 | HASH_CR_ALGO_2 | HASH_CR_ALGO_3)
|
||||
/*!< HASH function is SHA512_224 */
|
||||
#define HASH_ALGOSELECTION_SHA512_256 (HASH_CR_ALGO_1 | HASH_CR_ALGO_2 | HASH_CR_ALGO_3)
|
||||
/*!< HASH function is SHA512_256 */
|
||||
#define HASH_ALGOSELECTION_SHA512 HASH_CR_ALGO /*!< HASH function is SHA512 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HASH_Mode HASH Mode
|
||||
* @{
|
||||
*/
|
||||
#define HASH_ALGOMODE_HASH 0x00000000U /*!< HASH mode */
|
||||
#define HASH_ALGOMODE_HMAC HASH_CR_MODE /*!< HMAC mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HASH_Data_Type HASH Data Type
|
||||
* @{
|
||||
*/
|
||||
#define HASH_NO_SWAP 0x00000000U /*!< 32-bit data. No swapping */
|
||||
#define HASH_HALFWORD_SWAP HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */
|
||||
#define HASH_BYTE_SWAP HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */
|
||||
#define HASH_BIT_SWAP HASH_CR_DATATYPE /*!< 1-bit data. In the word all bits are swapped */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HASH_HMAC_KEY key length only for HMAC mode
|
||||
* @{
|
||||
*/
|
||||
#define HASH_SHORTKEY 0x00000000U /*!< HMAC Key size is <= block size (64 or 128 bytes) */
|
||||
#define HASH_LONGKEY HASH_CR_LKEY /*!< HMAC Key size is > block size (64 or 128 bytes) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HASH_flags_definition HASH flags definitions
|
||||
* @{
|
||||
*/
|
||||
#define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : new block can be entered
|
||||
in the Peripheral */
|
||||
#define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */
|
||||
#define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */
|
||||
#define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy, processing a block of data */
|
||||
#define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : input buffer contains at least one word of data*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HASH_interrupts_definition HASH interrupts definitions
|
||||
* @{
|
||||
*/
|
||||
#define HASH_IT_DINI HASH_IMR_DINIE /*!< A new block can be entered into the input buffer (DIN) */
|
||||
#define HASH_IT_DCI HASH_IMR_DCIE /*!< Digest calculation complete */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup HASH_Exported_Macros HASH Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Check whether or not the specified HASH flag is set.
|
||||
* @param __HANDLE__ specifies the HASH handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.
|
||||
* @arg @ref HASH_FLAG_DCIS Digest calculation complete.
|
||||
* @arg @ref HASH_FLAG_DMAS DMA interface is enabled (DMAE=1) or a transfer is ongoing.
|
||||
* @arg @ref HASH_FLAG_BUSY The hash core is Busy : processing a block of data.
|
||||
* @arg @ref HASH_FLAG_DINNE DIN not empty : the input buffer contains at least one word of data.
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_HASH_GET_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) > 8U) ? \
|
||||
(((__HANDLE__)->Instance->CR & (__FLAG__)) == (__FLAG__)) :\
|
||||
(((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) )
|
||||
|
||||
/** @brief Clear the specified HASH flag.
|
||||
* @param __HANDLE__ specifies the HASH handle.
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.
|
||||
* @arg @ref HASH_FLAG_DCIS Digest calculation complete
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_HASH_CLEAR_FLAG(__HANDLE__, __FLAG__) CLEAR_BIT((__HANDLE__)->Instance->SR, (__FLAG__))
|
||||
|
||||
/** @brief Check whether the specified HASH interrupt source is enabled or not.
|
||||
* @param __HANDLE__ specifies the HASH handle.
|
||||
* @param __INTERRUPT__ HASH interrupt source to check
|
||||
* This parameter can be one of the following values :
|
||||
* @arg @ref HASH_IT_DINI A new block can be entered into the input buffer (DIN)
|
||||
* @arg @ref HASH_IT_DCI Digest calculation complete
|
||||
* @retval State of interruption (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_HASH_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMR\
|
||||
& (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
/** @brief Enable the specified HASH interrupt.
|
||||
* @param __HANDLE__ specifies the HASH handle.
|
||||
* @param __INTERRUPT__ specifies the HASH interrupt source to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref HASH_IT_DINI A new block can be entered into the input buffer (DIN)
|
||||
* @arg @ref HASH_IT_DCI Digest calculation complete
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_HASH_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->IMR, (__INTERRUPT__))
|
||||
|
||||
/** @brief Disable the specified HASH interrupt.
|
||||
* @param __HANDLE__ specifies the HASH handle.
|
||||
* @param __INTERRUPT__ specifies the HASH interrupt source to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref HASH_IT_DINI A new block can be entered into the input buffer (DIN)
|
||||
* @arg @ref HASH_IT_DCI Digest calculation complete
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_HASH_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->IMR, (__INTERRUPT__))
|
||||
|
||||
/** @brief Reset HASH handle state.
|
||||
* @param __HANDLE__ HASH handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) do{\
|
||||
(__HANDLE__)->State = HAL_HASH_STATE_RESET;\
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
}while(0)
|
||||
#else
|
||||
#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HASH_STATE_RESET)
|
||||
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @brief Enable the multi-buffer DMA transfer mode.
|
||||
* @note This bit is set when hashing large files when multiple DMA transfers are needed.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_HASH_SET_MDMAT() SET_BIT(HASH->CR, HASH_CR_MDMAT)
|
||||
|
||||
/**
|
||||
* @brief Disable the multi-buffer DMA transfer mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_HASH_RESET_MDMAT() CLEAR_BIT(HASH->CR, HASH_CR_MDMAT)
|
||||
|
||||
/**
|
||||
* @brief HAL HASH driver version.
|
||||
* @retval None
|
||||
*/
|
||||
#define HAL_HASH_VERSION 200 /*!< HAL HASH driver version 2.0.0*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup HASH_Exported_Functions HASH Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash);
|
||||
HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash);
|
||||
void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash);
|
||||
void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash);
|
||||
HAL_StatusTypeDef HAL_HASH_GetConfig(HASH_HandleTypeDef *hhash, HASH_ConfigTypeDef *pConf);
|
||||
HAL_StatusTypeDef HAL_HASH_SetConfig(HASH_HandleTypeDef *hhash, HASH_ConfigTypeDef *pConf);
|
||||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID,
|
||||
pHASH_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
|
||||
|
||||
HAL_StatusTypeDef HAL_HASH_ProcessSuspend(HASH_HandleTypeDef *hhash);
|
||||
void HAL_HASH_Resume(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer);
|
||||
void HAL_HASH_Suspend(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HASH_Exported_Functions_Group2 HASH processing functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_HASH_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *const pOutBuffer,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *const pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASH_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *const pOutBuffer);
|
||||
|
||||
HAL_StatusTypeDef HAL_HASH_Accumulate(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_AccumulateLast(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *const pOutBuffer,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_AccumulateLast_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *const pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HASH_Exported_Functions_Group3 HMAC processing functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASH_HMAC_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *const pOutBuffer,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_HMAC_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *const pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASH_HMAC_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *const pOutBuffer);
|
||||
|
||||
HAL_StatusTypeDef HAL_HASH_HMAC_Accumulate(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_HMAC_AccumulateLast(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *const pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_HMAC_Accumulate_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASH_HMAC_AccumulateLast_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer,
|
||||
uint32_t Size, uint8_t *const pOutBuffer);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HASH_Exported_Functions_Group4 HASH IRQ handler management
|
||||
* @{
|
||||
*/
|
||||
void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
|
||||
void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash);
|
||||
void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash);
|
||||
void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);
|
||||
HAL_HASH_StateTypeDef HAL_HASH_GetState(const HASH_HandleTypeDef *hhash);
|
||||
uint32_t HAL_HASH_GetError(const HASH_HandleTypeDef *hhash);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros --------------------------------------------------------*/
|
||||
/** @defgroup HASH_Private_Macros HASH Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Return digest length in bytes.
|
||||
* @retval Digest length
|
||||
*/
|
||||
#define HASH_DIGEST_LENGTH(__HANDLE__) (((READ_BIT((__HANDLE__)->Instance->CR, HASH_CR_ALGO) \
|
||||
== HASH_ALGOSELECTION_SHA1) ? 20U : \
|
||||
((READ_BIT((__HANDLE__)->Instance->CR, HASH_CR_ALGO) \
|
||||
== HASH_ALGOSELECTION_SHA224) ? 28U : \
|
||||
((READ_BIT((__HANDLE__)->Instance->CR, HASH_CR_ALGO) \
|
||||
== HASH_ALGOSELECTION_SHA256) ? 32U : \
|
||||
((READ_BIT((__HANDLE__)->Instance->CR, HASH_CR_ALGO) \
|
||||
== HASH_ALGOSELECTION_SHA384) ? 48U : \
|
||||
((READ_BIT((__HANDLE__)->Instance->CR, HASH_CR_ALGO) \
|
||||
== HASH_ALGOSELECTION_SHA512_224) ? 28U : \
|
||||
((READ_BIT((__HANDLE__)->Instance->CR, HASH_CR_ALGO) \
|
||||
== HASH_ALGOSELECTION_SHA512_256) ? 32U : \
|
||||
((READ_BIT((__HANDLE__)->Instance->CR, HASH_CR_ALGO) \
|
||||
== HASH_ALGOSELECTION_SHA512) ? 64U : 20U ) ) ))))))
|
||||
|
||||
/**
|
||||
* @brief Ensure that HASH input data type is valid.
|
||||
* @param __DATATYPE__ HASH input data type.
|
||||
* @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid)
|
||||
*/
|
||||
#define IS_HASH_DATATYPE(__DATATYPE__) (((__DATATYPE__) == HASH_NO_SWAP)|| \
|
||||
((__DATATYPE__) == HASH_HALFWORD_SWAP)|| \
|
||||
((__DATATYPE__) == HASH_BYTE_SWAP) || \
|
||||
((__DATATYPE__) == HASH_BIT_SWAP))
|
||||
|
||||
/**
|
||||
* @brief Ensure that HASH input algorithm is valid.
|
||||
* @param __ALGORITHM__ HASH algorithm.
|
||||
* @retval SET (__ALGORITHM__ is valid) or RESET (__ALGORITHM__ is invalid)
|
||||
*/
|
||||
#define IS_HASH_ALGORITHM(__ALGORITHM__) (((__ALGORITHM__) == HASH_ALGOSELECTION_SHA1)|| \
|
||||
((__ALGORITHM__) == HASH_ALGOSELECTION_SHA224)|| \
|
||||
((__ALGORITHM__) == HASH_ALGOSELECTION_SHA256)|| \
|
||||
((__ALGORITHM__) == HASH_ALGOSELECTION_SHA384)|| \
|
||||
((__ALGORITHM__) == HASH_ALGOSELECTION_SHA512_224)|| \
|
||||
((__ALGORITHM__) == HASH_ALGOSELECTION_SHA512_256)|| \
|
||||
((__ALGORITHM__) == HASH_ALGOSELECTION_SHA512))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup HASH_Private_Constants HASH Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private defines -----------------------------------------------------------*/
|
||||
/** @defgroup HASH_Private_Defines HASH Private Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup HASH_Private_Variables HASH Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private functions -----------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup HASH_Private_Functions HASH Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* HASH*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* STM32H7RSxx_HAL_HASH_H */
|
||||
|
|
@ -1,327 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7rsxx_hal_hcd.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of HCD HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7RSxx_HAL_HCD_H
|
||||
#define STM32H7RSxx_HAL_HCD_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7rsxx_ll_usb.h"
|
||||
|
||||
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
|
||||
/** @addtogroup STM32H7RSxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup HCD HCD
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup HCD_Exported_Types HCD Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HCD_Exported_Types_Group1 HCD State Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_HCD_STATE_RESET = 0x00,
|
||||
HAL_HCD_STATE_READY = 0x01,
|
||||
HAL_HCD_STATE_ERROR = 0x02,
|
||||
HAL_HCD_STATE_BUSY = 0x03,
|
||||
HAL_HCD_STATE_TIMEOUT = 0x04
|
||||
} HCD_StateTypeDef;
|
||||
|
||||
typedef USB_OTG_GlobalTypeDef HCD_TypeDef;
|
||||
typedef USB_OTG_CfgTypeDef HCD_InitTypeDef;
|
||||
typedef USB_OTG_HCTypeDef HCD_HCTypeDef;
|
||||
typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef;
|
||||
typedef USB_OTG_HCStateTypeDef HCD_HCStateTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HCD_Exported_Types_Group2 HCD Handle Structure definition
|
||||
* @{
|
||||
*/
|
||||
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
|
||||
typedef struct __HCD_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
|
||||
{
|
||||
HCD_TypeDef *Instance; /*!< Register base address */
|
||||
HCD_InitTypeDef Init; /*!< HCD required parameters */
|
||||
HCD_HCTypeDef hc[16]; /*!< Host channels parameters */
|
||||
HAL_LockTypeDef Lock; /*!< HCD peripheral status */
|
||||
__IO HCD_StateTypeDef State; /*!< HCD communication state */
|
||||
__IO uint32_t ErrorCode; /*!< HCD Error code */
|
||||
void *pData; /*!< Pointer Stack Handler */
|
||||
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
|
||||
void (* SOFCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD SOF callback */
|
||||
void (* ConnectCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Connect callback */
|
||||
void (* DisconnectCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Disconnect callback */
|
||||
void (* PortEnabledCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Port Enable callback */
|
||||
void (* PortDisabledCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Port Disable callback */
|
||||
void (* HC_NotifyURBChangeCallback)(struct __HCD_HandleTypeDef *hhcd, uint8_t chnum,
|
||||
HCD_URBStateTypeDef urb_state); /*!< USB OTG HCD Host Channel Notify URB Change callback */
|
||||
|
||||
void (* MspInitCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Msp DeInit callback */
|
||||
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
|
||||
} HCD_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup HCD_Exported_Constants HCD Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HCD_Speed HCD Speed
|
||||
* @{
|
||||
*/
|
||||
#define HCD_SPEED_HIGH USBH_HS_SPEED
|
||||
#define HCD_SPEED_FULL USBH_FSLS_SPEED
|
||||
#define HCD_SPEED_LOW USBH_FSLS_SPEED
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HCD_Device_Speed HCD Device Speed
|
||||
* @{
|
||||
*/
|
||||
#define HCD_DEVICE_SPEED_HIGH 0U
|
||||
#define HCD_DEVICE_SPEED_FULL 1U
|
||||
#define HCD_DEVICE_SPEED_LOW 2U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HCD_PHY_Module HCD PHY Module
|
||||
* @{
|
||||
*/
|
||||
#define HCD_PHY_ULPI 1U
|
||||
#define HCD_PHY_EMBEDDED 2U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HCD_Error_Code_definition HCD Error Code definition
|
||||
* @brief HCD Error Code definition
|
||||
* @{
|
||||
*/
|
||||
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
|
||||
#define HAL_HCD_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup HCD_Exported_Macros HCD Exported Macros
|
||||
* @brief macros to handle interrupts and specific clock configurations
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_HCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
|
||||
#define __HAL_HCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
|
||||
|
||||
#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance)\
|
||||
& (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
#define __HAL_HCD_GET_CH_FLAG(__HANDLE__, __chnum__, __INTERRUPT__) \
|
||||
((USB_ReadChInterrupts((__HANDLE__)->Instance, (__chnum__)) & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
|
||||
#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
|
||||
|
||||
#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__))
|
||||
#define __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM)
|
||||
#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)
|
||||
#define __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)
|
||||
#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)
|
||||
#define __HAL_HCD_SET_HC_CSPLT(chnum) (USBx_HC(chnum)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT)
|
||||
#define __HAL_HCD_CLEAR_HC_CSPLT(chnum) (USBx_HC(chnum)->HCSPLT &= ~USB_OTG_HCSPLT_COMPLSPLT)
|
||||
#define __HAL_HCD_CLEAR_HC_SSPLT(chnum) (USBx_HC(chnum)->HCSPLT &= ~USB_OTG_HCSPLT_SPLITEN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup HCD_Exported_Functions HCD Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
|
||||
HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd);
|
||||
HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
|
||||
uint8_t epnum, uint8_t dev_address,
|
||||
uint8_t speed, uint8_t ep_type, uint16_t mps);
|
||||
|
||||
HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
|
||||
void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
|
||||
|
||||
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
|
||||
/** @defgroup HAL_HCD_Callback_ID_enumeration_definition HAL USB OTG HCD Callback ID enumeration definition
|
||||
* @brief HAL USB OTG HCD Callback ID enumeration definition
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_HCD_SOF_CB_ID = 0x01, /*!< USB HCD SOF callback ID */
|
||||
HAL_HCD_CONNECT_CB_ID = 0x02, /*!< USB HCD Connect callback ID */
|
||||
HAL_HCD_DISCONNECT_CB_ID = 0x03, /*!< USB HCD Disconnect callback ID */
|
||||
HAL_HCD_PORT_ENABLED_CB_ID = 0x04, /*!< USB HCD Port Enable callback ID */
|
||||
HAL_HCD_PORT_DISABLED_CB_ID = 0x05, /*!< USB HCD Port Disable callback ID */
|
||||
|
||||
HAL_HCD_MSPINIT_CB_ID = 0x06, /*!< USB HCD MspInit callback ID */
|
||||
HAL_HCD_MSPDEINIT_CB_ID = 0x07 /*!< USB HCD MspDeInit callback ID */
|
||||
|
||||
} HAL_HCD_CallbackIDTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_HCD_Callback_pointer_definition HAL USB OTG HCD Callback pointer definition
|
||||
* @brief HAL USB OTG HCD Callback pointer definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef void (*pHCD_CallbackTypeDef)(HCD_HandleTypeDef *hhcd); /*!< pointer to a common USB OTG HCD callback function */
|
||||
typedef void (*pHCD_HC_NotifyURBChangeCallbackTypeDef)(HCD_HandleTypeDef *hhcd,
|
||||
uint8_t epnum,
|
||||
HCD_URBStateTypeDef urb_state); /*!< pointer to USB OTG HCD host channel callback */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd,
|
||||
HAL_HCD_CallbackIDTypeDef CallbackID,
|
||||
pHCD_CallbackTypeDef pCallback);
|
||||
|
||||
HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd,
|
||||
HAL_HCD_CallbackIDTypeDef CallbackID);
|
||||
|
||||
HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd,
|
||||
pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback);
|
||||
|
||||
HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd);
|
||||
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* I/O operation functions ***************************************************/
|
||||
/** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
|
||||
uint8_t direction, uint8_t ep_type,
|
||||
uint8_t token, uint8_t *pbuff,
|
||||
uint16_t length, uint8_t do_ping);
|
||||
|
||||
HAL_StatusTypeDef HAL_HCD_HC_SetHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
|
||||
uint8_t addr, uint8_t PortNbr);
|
||||
|
||||
HAL_StatusTypeDef HAL_HCD_HC_ClearHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
|
||||
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum,
|
||||
HCD_URBStateTypeDef urb_state);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions **********************************************/
|
||||
/** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
|
||||
HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
|
||||
HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral State functions ************************************************/
|
||||
/** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef const *hhcd);
|
||||
HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef const *hhcd, uint8_t chnum);
|
||||
HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef const *hhcd, uint8_t chnum);
|
||||
uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef const *hhcd, uint8_t chnum);
|
||||
uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
|
||||
uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup HCD_Private_Macros HCD Private Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private functions prototypes ----------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7RSxx_HAL_HCD_H */
|
||||
|
|
@ -1,842 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7rsxx_hal_i2c.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of I2C HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7RSxx_HAL_I2C_H
|
||||
#define STM32H7RSxx_HAL_I2C_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7rsxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H7RSxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup I2C_Exported_Types I2C Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
|
||||
* @brief I2C Configuration Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value.
|
||||
This parameter calculated by referring to I2C initialization section
|
||||
in Reference manual */
|
||||
|
||||
uint32_t OwnAddress1; /*!< Specifies the first device own address.
|
||||
This parameter can be a 7-bit or 10-bit address. */
|
||||
|
||||
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
|
||||
This parameter can be a value of @ref I2C_ADDRESSING_MODE */
|
||||
|
||||
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
|
||||
This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
|
||||
|
||||
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
|
||||
This parameter can be a 7-bit address. */
|
||||
|
||||
uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing
|
||||
mode is selected.
|
||||
This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
|
||||
|
||||
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
|
||||
This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
|
||||
|
||||
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
|
||||
This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
|
||||
|
||||
} I2C_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_state_structure_definition HAL state structure definition
|
||||
* @brief HAL State structure definition
|
||||
* @note HAL I2C State value coding follow below described bitmap :\n
|
||||
* b7-b6 Error information\n
|
||||
* 00 : No Error\n
|
||||
* 01 : Abort (Abort user request on going)\n
|
||||
* 10 : Timeout\n
|
||||
* 11 : Error\n
|
||||
* b5 Peripheral initialization status\n
|
||||
* 0 : Reset (peripheral not initialized)\n
|
||||
* 1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n
|
||||
* b4 (not used)\n
|
||||
* x : Should be set to 0\n
|
||||
* b3\n
|
||||
* 0 : Ready or Busy (No Listen mode ongoing)\n
|
||||
* 1 : Listen (peripheral in Address Listen Mode)\n
|
||||
* b2 Intrinsic process state\n
|
||||
* 0 : Ready\n
|
||||
* 1 : Busy (peripheral busy with some configuration or internal operations)\n
|
||||
* b1 Rx state\n
|
||||
* 0 : Ready (no Rx operation ongoing)\n
|
||||
* 1 : Busy (Rx operation ongoing)\n
|
||||
* b0 Tx state\n
|
||||
* 0 : Ready (no Tx operation ongoing)\n
|
||||
* 1 : Busy (Tx operation ongoing)
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
|
||||
HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
|
||||
HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
|
||||
HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
|
||||
HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
|
||||
HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */
|
||||
HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
|
||||
process is ongoing */
|
||||
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
|
||||
process is ongoing */
|
||||
HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
|
||||
|
||||
} HAL_I2C_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_mode_structure_definition HAL mode structure definition
|
||||
* @brief HAL Mode structure definition
|
||||
* @note HAL I2C Mode value coding follow below described bitmap :\n
|
||||
* b7 (not used)\n
|
||||
* x : Should be set to 0\n
|
||||
* b6\n
|
||||
* 0 : None\n
|
||||
* 1 : Memory (HAL I2C communication is in Memory Mode)\n
|
||||
* b5\n
|
||||
* 0 : None\n
|
||||
* 1 : Slave (HAL I2C communication is in Slave Mode)\n
|
||||
* b4\n
|
||||
* 0 : None\n
|
||||
* 1 : Master (HAL I2C communication is in Master Mode)\n
|
||||
* b3-b2-b1-b0 (not used)\n
|
||||
* xxxx : Should be set to 0000
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */
|
||||
HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */
|
||||
HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
|
||||
HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */
|
||||
|
||||
} HAL_I2C_ModeTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Error_Code_definition I2C Error Code definition
|
||||
* @brief I2C Error Code definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */
|
||||
#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */
|
||||
#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */
|
||||
#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */
|
||||
#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */
|
||||
#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
|
||||
#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
|
||||
#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */
|
||||
#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U) /*!< DMA Parameter Error */
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
#define HAL_I2C_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
|
||||
* @brief I2C handle Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct __I2C_HandleTypeDef
|
||||
{
|
||||
I2C_TypeDef *Instance; /*!< I2C registers base address */
|
||||
|
||||
I2C_InitTypeDef Init; /*!< I2C communication parameters */
|
||||
|
||||
uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
|
||||
|
||||
uint16_t XferSize; /*!< I2C transfer size */
|
||||
|
||||
__IO uint16_t XferCount; /*!< I2C transfer counter */
|
||||
|
||||
__IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can
|
||||
be a value of @ref I2C_XFEROPTIONS */
|
||||
|
||||
__IO uint32_t PreviousState; /*!< I2C communication Previous state */
|
||||
|
||||
HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
|
||||
/*!< I2C transfer IRQ handler function pointer */
|
||||
|
||||
#if defined(HAL_DMA_MODULE_ENABLED)
|
||||
DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
|
||||
|
||||
#endif /*HAL_DMA_MODULE_ENABLED*/
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< I2C locking object */
|
||||
|
||||
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
|
||||
|
||||
__IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< I2C Error code */
|
||||
|
||||
__IO uint32_t AddrEventCount; /*!< I2C Address Event counter */
|
||||
|
||||
__IO uint32_t Devaddress; /*!< I2C Target device address */
|
||||
|
||||
__IO uint32_t Memaddress; /*!< I2C Target memory address */
|
||||
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Master Tx Transfer completed callback */
|
||||
void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Master Rx Transfer completed callback */
|
||||
void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Slave Tx Transfer completed callback */
|
||||
void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Slave Rx Transfer completed callback */
|
||||
void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Listen Complete callback */
|
||||
void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Memory Tx Transfer completed callback */
|
||||
void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Memory Rx Transfer completed callback */
|
||||
void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Error callback */
|
||||
void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Abort callback */
|
||||
|
||||
void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
|
||||
/*!< I2C Slave Address Match callback */
|
||||
|
||||
void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Msp DeInit callback */
|
||||
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
} I2C_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL I2C Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */
|
||||
HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */
|
||||
HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */
|
||||
HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */
|
||||
HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */
|
||||
HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */
|
||||
HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */
|
||||
HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */
|
||||
HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */
|
||||
|
||||
HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */
|
||||
HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */
|
||||
|
||||
} HAL_I2C_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL I2C Callback pointer definition
|
||||
*/
|
||||
typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c);
|
||||
/*!< pointer to an I2C callback function */
|
||||
typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection,
|
||||
uint16_t AddrMatchCode);
|
||||
/*!< pointer to an I2C Address Match callback function */
|
||||
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup I2C_Exported_Constants I2C Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options
|
||||
* @{
|
||||
*/
|
||||
#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)
|
||||
#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
|
||||
#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
|
||||
#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
|
||||
#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
|
||||
#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE)
|
||||
|
||||
/* List of XferOptions in usage of :
|
||||
* 1- Restart condition in all use cases (direction change or not)
|
||||
*/
|
||||
#define I2C_OTHER_FRAME (0x000000AAU)
|
||||
#define I2C_OTHER_AND_LAST_FRAME (0x0000AA00U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_ADDRESSINGMODE_7BIT (0x00000001U)
|
||||
#define I2C_ADDRESSINGMODE_10BIT (0x00000002U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_DUALADDRESS_DISABLE (0x00000000U)
|
||||
#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
|
||||
* @{
|
||||
*/
|
||||
#define I2C_OA2_NOMASK ((uint8_t)0x00U)
|
||||
#define I2C_OA2_MASK01 ((uint8_t)0x01U)
|
||||
#define I2C_OA2_MASK02 ((uint8_t)0x02U)
|
||||
#define I2C_OA2_MASK03 ((uint8_t)0x03U)
|
||||
#define I2C_OA2_MASK04 ((uint8_t)0x04U)
|
||||
#define I2C_OA2_MASK05 ((uint8_t)0x05U)
|
||||
#define I2C_OA2_MASK06 ((uint8_t)0x06U)
|
||||
#define I2C_OA2_MASK07 ((uint8_t)0x07U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_GENERALCALL_DISABLE (0x00000000U)
|
||||
#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_NOSTRETCH_DISABLE (0x00000000U)
|
||||
#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
|
||||
* @{
|
||||
*/
|
||||
#define I2C_MEMADD_SIZE_8BIT (0x00000001U)
|
||||
#define I2C_MEMADD_SIZE_16BIT (0x00000002U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
|
||||
* @{
|
||||
*/
|
||||
#define I2C_DIRECTION_TRANSMIT (0x00000000U)
|
||||
#define I2C_DIRECTION_RECEIVE (0x00000001U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_RELOAD_MODE I2C_CR2_RELOAD
|
||||
#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
|
||||
#define I2C_SOFTEND_MODE (0x00000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_NO_STARTSTOP (0x00000000U)
|
||||
#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
|
||||
#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
|
||||
#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
|
||||
* @brief I2C Interrupt definition
|
||||
* Elements values convention: 0xXXXXXXXX
|
||||
* - XXXXXXXX : Interrupt control mask
|
||||
* @{
|
||||
*/
|
||||
#define I2C_IT_ERRI I2C_CR1_ERRIE
|
||||
#define I2C_IT_TCI I2C_CR1_TCIE
|
||||
#define I2C_IT_STOPI I2C_CR1_STOPIE
|
||||
#define I2C_IT_NACKI I2C_CR1_NACKIE
|
||||
#define I2C_IT_ADDRI I2C_CR1_ADDRIE
|
||||
#define I2C_IT_RXI I2C_CR1_RXIE
|
||||
#define I2C_IT_TXI I2C_CR1_TXIE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Flag_definition I2C Flag definition
|
||||
* @{
|
||||
*/
|
||||
#define I2C_FLAG_TXE I2C_ISR_TXE
|
||||
#define I2C_FLAG_TXIS I2C_ISR_TXIS
|
||||
#define I2C_FLAG_RXNE I2C_ISR_RXNE
|
||||
#define I2C_FLAG_ADDR I2C_ISR_ADDR
|
||||
#define I2C_FLAG_AF I2C_ISR_NACKF
|
||||
#define I2C_FLAG_STOPF I2C_ISR_STOPF
|
||||
#define I2C_FLAG_TC I2C_ISR_TC
|
||||
#define I2C_FLAG_TCR I2C_ISR_TCR
|
||||
#define I2C_FLAG_BERR I2C_ISR_BERR
|
||||
#define I2C_FLAG_ARLO I2C_ISR_ARLO
|
||||
#define I2C_FLAG_OVR I2C_ISR_OVR
|
||||
#define I2C_FLAG_PECERR I2C_ISR_PECERR
|
||||
#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
|
||||
#define I2C_FLAG_ALERT I2C_ISR_ALERT
|
||||
#define I2C_FLAG_BUSY I2C_ISR_BUSY
|
||||
#define I2C_FLAG_DIR I2C_ISR_DIR
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @defgroup I2C_Exported_Macros I2C Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset I2C handle state.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_I2C_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
|
||||
/** @brief Enable the specified I2C interrupt.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __INTERRUPT__ specifies the interrupt source to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref I2C_IT_ERRI Errors interrupt enable
|
||||
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
|
||||
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
|
||||
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
|
||||
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
|
||||
* @arg @ref I2C_IT_RXI RX interrupt enable
|
||||
* @arg @ref I2C_IT_TXI TX interrupt enable
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
|
||||
|
||||
/** @brief Disable the specified I2C interrupt.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __INTERRUPT__ specifies the interrupt source to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref I2C_IT_ERRI Errors interrupt enable
|
||||
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
|
||||
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
|
||||
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
|
||||
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
|
||||
* @arg @ref I2C_IT_RXI RX interrupt enable
|
||||
* @arg @ref I2C_IT_TXI TX interrupt enable
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
|
||||
|
||||
/** @brief Check whether the specified I2C interrupt source is enabled or not.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __INTERRUPT__ specifies the I2C interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref I2C_IT_ERRI Errors interrupt enable
|
||||
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
|
||||
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
|
||||
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
|
||||
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
|
||||
* @arg @ref I2C_IT_RXI RX interrupt enable
|
||||
* @arg @ref I2C_IT_TXI TX interrupt enable
|
||||
*
|
||||
* @retval The new state of __INTERRUPT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & \
|
||||
(__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified I2C flag is set or not.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref I2C_FLAG_TXE Transmit data register empty
|
||||
* @arg @ref I2C_FLAG_TXIS Transmit interrupt status
|
||||
* @arg @ref I2C_FLAG_RXNE Receive data register not empty
|
||||
* @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
|
||||
* @arg @ref I2C_FLAG_AF Acknowledge failure received flag
|
||||
* @arg @ref I2C_FLAG_STOPF STOP detection flag
|
||||
* @arg @ref I2C_FLAG_TC Transfer complete (master mode)
|
||||
* @arg @ref I2C_FLAG_TCR Transfer complete reload
|
||||
* @arg @ref I2C_FLAG_BERR Bus error
|
||||
* @arg @ref I2C_FLAG_ARLO Arbitration lost
|
||||
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
|
||||
* @arg @ref I2C_FLAG_PECERR PEC error in reception
|
||||
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
|
||||
* @arg @ref I2C_FLAG_ALERT SMBus alert
|
||||
* @arg @ref I2C_FLAG_BUSY Bus busy
|
||||
* @arg @ref I2C_FLAG_DIR Transfer direction (slave mode)
|
||||
*
|
||||
* @retval The new state of __FLAG__ (SET or RESET).
|
||||
*/
|
||||
#define I2C_FLAG_MASK (0x0001FFFFU)
|
||||
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \
|
||||
(__FLAG__)) == (__FLAG__)) ? SET : RESET)
|
||||
|
||||
/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref I2C_FLAG_TXE Transmit data register empty
|
||||
* @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
|
||||
* @arg @ref I2C_FLAG_AF Acknowledge failure received flag
|
||||
* @arg @ref I2C_FLAG_STOPF STOP detection flag
|
||||
* @arg @ref I2C_FLAG_BERR Bus error
|
||||
* @arg @ref I2C_FLAG_ARLO Arbitration lost
|
||||
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
|
||||
* @arg @ref I2C_FLAG_PECERR PEC error in reception
|
||||
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
|
||||
* @arg @ref I2C_FLAG_ALERT SMBus alert
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? \
|
||||
((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
|
||||
((__HANDLE__)->Instance->ICR = (__FLAG__)))
|
||||
|
||||
/** @brief Enable the specified I2C peripheral.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
|
||||
|
||||
/** @brief Disable the specified I2C peripheral.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
|
||||
|
||||
/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include I2C HAL Extended module */
|
||||
#include "stm32h7rsxx_hal_i2c_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup I2C_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions******************************/
|
||||
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
|
||||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
|
||||
pI2C_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
|
||||
|
||||
HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions ****************************************************/
|
||||
/******* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
|
||||
uint32_t Timeout);
|
||||
|
||||
/******* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
|
||||
|
||||
#if defined(HAL_DMA_MODULE_ENABLED)
|
||||
/******* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions);
|
||||
#endif /*HAL_DMA_MODULE_ENABLED*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
|
||||
* @{
|
||||
*/
|
||||
/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
|
||||
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
|
||||
void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State, Mode and Error functions *********************************/
|
||||
HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c);
|
||||
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c);
|
||||
uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup I2C_Private_Constants I2C Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup I2C_Private_Macro I2C Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
|
||||
((MODE) == I2C_ADDRESSINGMODE_10BIT))
|
||||
|
||||
#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
|
||||
((ADDRESS) == I2C_DUALADDRESS_ENABLE))
|
||||
|
||||
#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \
|
||||
((MASK) == I2C_OA2_MASK01) || \
|
||||
((MASK) == I2C_OA2_MASK02) || \
|
||||
((MASK) == I2C_OA2_MASK03) || \
|
||||
((MASK) == I2C_OA2_MASK04) || \
|
||||
((MASK) == I2C_OA2_MASK05) || \
|
||||
((MASK) == I2C_OA2_MASK06) || \
|
||||
((MASK) == I2C_OA2_MASK07))
|
||||
|
||||
#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
|
||||
((CALL) == I2C_GENERALCALL_ENABLE))
|
||||
|
||||
#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
|
||||
((STRETCH) == I2C_NOSTRETCH_ENABLE))
|
||||
|
||||
#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
|
||||
((SIZE) == I2C_MEMADD_SIZE_16BIT))
|
||||
|
||||
#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \
|
||||
((MODE) == I2C_AUTOEND_MODE) || \
|
||||
((MODE) == I2C_SOFTEND_MODE))
|
||||
|
||||
#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \
|
||||
((REQUEST) == I2C_GENERATE_START_READ) || \
|
||||
((REQUEST) == I2C_GENERATE_START_WRITE) || \
|
||||
((REQUEST) == I2C_NO_STARTSTOP))
|
||||
|
||||
#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
|
||||
((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
|
||||
((REQUEST) == I2C_NEXT_FRAME) || \
|
||||
((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
|
||||
((REQUEST) == I2C_LAST_FRAME) || \
|
||||
((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \
|
||||
IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
|
||||
|
||||
#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \
|
||||
((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
|
||||
|
||||
#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
|
||||
(uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \
|
||||
I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
|
||||
I2C_CR2_RD_WRN)))
|
||||
|
||||
#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) \
|
||||
>> 16U))
|
||||
#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) \
|
||||
>> 16U))
|
||||
#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
|
||||
#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
|
||||
#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
|
||||
|
||||
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
|
||||
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
|
||||
|
||||
#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \
|
||||
(uint16_t)(0xFF00U))) >> 8U)))
|
||||
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
|
||||
|
||||
#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? \
|
||||
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
|
||||
(I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
|
||||
(~I2C_CR2_RD_WRN)) : \
|
||||
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
|
||||
(I2C_CR2_ADD10) | (I2C_CR2_START) | \
|
||||
(I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)))
|
||||
|
||||
#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \
|
||||
((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
|
||||
#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private Functions ---------------------------------------------------------*/
|
||||
/** @defgroup I2C_Private_Functions I2C Private Functions
|
||||
* @{
|
||||
*/
|
||||
/* Private functions are defined in stm32h7rsxx_hal_i2c.c file */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* STM32H7RSxx_HAL_I2C_H */
|
||||
|
|
@ -1,156 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7rsxx_hal_i2c_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of I2C HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7RSxx_HAL_I2C_EX_H
|
||||
#define STM32H7RSxx_HAL_I2C_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7rsxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H7RSxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2CEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
|
||||
* @{
|
||||
*/
|
||||
#define I2C_ANALOGFILTER_ENABLE 0x00000000U
|
||||
#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
|
||||
* @{
|
||||
*/
|
||||
#define I2C_FASTMODEPLUS_ENABLE 0x00000000U /*!< Enable Fast Mode Plus */
|
||||
#define I2C_FASTMODEPLUS_DISABLE 0x00000001U /*!< Disable Fast Mode Plus */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ************************************************/
|
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
|
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigFastModePlus(I2C_HandleTypeDef *hi2c, uint32_t FastModePlus);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
|
||||
((FILTER) == I2C_ANALOGFILTER_DISABLE))
|
||||
|
||||
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
|
||||
|
||||
#define IS_I2C_FASTMODEPLUS(__CONFIG__) (((__CONFIG__) == (I2C_FASTMODEPLUS_ENABLE)) || \
|
||||
((__CONFIG__) == (I2C_FASTMODEPLUS_DISABLE)))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private Functions ---------------------------------------------------------*/
|
||||
/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
|
||||
* @{
|
||||
*/
|
||||
/* Private functions are defined in stm32h7rsxx_hal_i2c_ex.c file */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7RSxx_HAL_I2C_EX_H */
|
||||
|
|
@ -1,663 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7rsxx_hal_i2s.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of I2S HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7RSxx_HAL_I2S_H
|
||||
#define STM32H7RSxx_HAL_I2S_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7rsxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H7RSxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2S
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup I2S_Exported_Types I2S Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief I2S Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Mode; /*!< Specifies the I2S operating mode.
|
||||
This parameter can be a value of @ref I2S_Mode */
|
||||
|
||||
uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
|
||||
This parameter can be a value of @ref I2S_Standard */
|
||||
|
||||
uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
|
||||
This parameter can be a value of @ref I2S_Data_Format */
|
||||
|
||||
uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
|
||||
This parameter can be a value of @ref I2S_MCLK_Output */
|
||||
|
||||
uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
|
||||
This parameter can be a value of @ref I2S_Audio_Frequency */
|
||||
|
||||
uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
|
||||
This parameter can be a value of @ref I2S_Clock_Polarity */
|
||||
|
||||
uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
|
||||
This parameter can be a value of @ref I2S_MSB_LSB_Transmission */
|
||||
|
||||
uint32_t WSInversion; /*!< Control the Word Select Inversion.
|
||||
This parameter can be a value of @ref I2S_WSInversion */
|
||||
|
||||
uint32_t Data24BitAlignment; /*!< Specifies the Data Padding for 24 bits data length
|
||||
This parameter can be a value of @ref I2S_Data_24Bit_Alignment */
|
||||
|
||||
uint32_t MasterKeepIOState; /*!< Control of Alternate function GPIOs state
|
||||
This parameter can be a value of @ref I2S_Master_Keep_IO_State */
|
||||
|
||||
} I2S_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2S_STATE_RESET = 0x00UL, /*!< I2S not yet initialized or disabled */
|
||||
HAL_I2S_STATE_READY = 0x01UL, /*!< I2S initialized and ready for use */
|
||||
HAL_I2S_STATE_BUSY = 0x02UL, /*!< I2S internal process is ongoing */
|
||||
HAL_I2S_STATE_BUSY_TX = 0x03UL, /*!< Data Transmission process is ongoing */
|
||||
HAL_I2S_STATE_BUSY_RX = 0x04UL, /*!< Data Reception process is ongoing */
|
||||
HAL_I2S_STATE_BUSY_TX_RX = 0x05UL, /*!< Data Transmission and Reception process is ongoing */
|
||||
HAL_I2S_STATE_TIMEOUT = 0x06UL, /*!< I2S timeout state */
|
||||
HAL_I2S_STATE_ERROR = 0x07UL /*!< I2S error state */
|
||||
} HAL_I2S_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief I2S handle Structure definition
|
||||
*/
|
||||
typedef struct __I2S_HandleTypeDef
|
||||
{
|
||||
SPI_TypeDef *Instance; /*!< I2S registers base address */
|
||||
|
||||
I2S_InitTypeDef Init; /*!< I2S communication parameters */
|
||||
|
||||
const uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */
|
||||
|
||||
__IO uint16_t TxXferSize; /*!< I2S Tx transfer size */
|
||||
|
||||
__IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */
|
||||
|
||||
uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */
|
||||
|
||||
__IO uint16_t RxXferSize; /*!< I2S Rx transfer size */
|
||||
|
||||
__IO uint16_t RxXferCount; /*!< I2S Rx transfer counter
|
||||
(This field is initialized at the
|
||||
same value as transfer size at the
|
||||
beginning of the transfer and
|
||||
decremented when a sample is received
|
||||
NbSamplesReceived = RxBufferSize-RxBufferCount) */
|
||||
|
||||
void (*RxISR)(struct __I2S_HandleTypeDef *hi2s); /*!< function pointer on Rx ISR */
|
||||
|
||||
void (*TxISR)(struct __I2S_HandleTypeDef *hi2s); /*!< function pointer on Tx ISR */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */
|
||||
|
||||
__IO HAL_LockTypeDef Lock; /*!< I2S locking object */
|
||||
|
||||
__IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< I2S Error code
|
||||
This parameter can be a value of @ref I2S_Error */
|
||||
|
||||
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
|
||||
void (* TxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Completed callback */
|
||||
void (* RxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Completed callback */
|
||||
void (* TxRxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S TxRx Completed callback */
|
||||
void (* TxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Half Completed callback */
|
||||
void (* RxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Half Completed callback */
|
||||
void (* TxRxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S TxRx Half Completed callback */
|
||||
void (* ErrorCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Error callback */
|
||||
void (* MspInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp DeInit callback */
|
||||
|
||||
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
|
||||
} I2S_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
|
||||
/**
|
||||
|
||||
* @brief HAL I2S Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2S_TX_COMPLETE_CB_ID = 0x00UL, /*!< I2S Tx Completed callback ID */
|
||||
HAL_I2S_RX_COMPLETE_CB_ID = 0x01UL, /*!< I2S Rx Completed callback ID */
|
||||
HAL_I2S_TX_RX_COMPLETE_CB_ID = 0x02UL, /*!< I2S TxRx Completed callback ID */
|
||||
HAL_I2S_TX_HALF_COMPLETE_CB_ID = 0x03UL, /*!< I2S Tx Half Completed callback ID */
|
||||
HAL_I2S_RX_HALF_COMPLETE_CB_ID = 0x04UL, /*!< I2S Rx Half Completed callback ID */
|
||||
HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID = 0x05UL, /*!< I2S TxRx Half Completed callback ID */
|
||||
HAL_I2S_ERROR_CB_ID = 0x06UL, /*!< I2S Error callback ID */
|
||||
HAL_I2S_MSPINIT_CB_ID = 0x07UL, /*!< I2S Msp Init callback ID */
|
||||
HAL_I2S_MSPDEINIT_CB_ID = 0x08UL /*!< I2S Msp DeInit callback ID */
|
||||
|
||||
} HAL_I2S_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL I2S Callback pointer definition
|
||||
*/
|
||||
typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to an I2S callback function */
|
||||
|
||||
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup I2S_Exported_Constants I2S Exported Constants
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup I2S_Error I2S Error
|
||||
* @{
|
||||
*/
|
||||
#define HAL_I2S_ERROR_NONE (0x00000000UL) /*!< No error */
|
||||
#define HAL_I2S_ERROR_TIMEOUT (0x00000001UL) /*!< Timeout error */
|
||||
#define HAL_I2S_ERROR_OVR (0x00000002UL) /*!< OVR error */
|
||||
#define HAL_I2S_ERROR_UDR (0x00000004UL) /*!< UDR error */
|
||||
#define HAL_I2S_ERROR_DMA (0x00000008UL) /*!< DMA transfer error */
|
||||
#define HAL_I2S_ERROR_PRESCALER (0x00000010UL) /*!< Prescaler Calculation error */
|
||||
#define HAL_I2S_ERROR_FRE (0x00000020UL) /*!< FRE error */
|
||||
#define HAL_I2S_ERROR_NO_OGT (0x00000040UL) /*!< No On Going Transfer error */
|
||||
#define HAL_I2S_ERROR_NOT_SUPPORTED (0x00000080UL) /*!< Requested operation not supported */
|
||||
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
|
||||
#define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000100UL) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Mode I2S Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2S_MODE_SLAVE_TX (0x00000000UL)
|
||||
#define I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)
|
||||
#define I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)
|
||||
#define I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1)
|
||||
#define I2S_MODE_SLAVE_FULLDUPLEX (SPI_I2SCFGR_I2SCFG_2)
|
||||
#define I2S_MODE_MASTER_FULLDUPLEX (SPI_I2SCFGR_I2SCFG_2 | SPI_I2SCFGR_I2SCFG_0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Standard I2S Standard
|
||||
* @{
|
||||
*/
|
||||
#define I2S_STANDARD_PHILIPS (0x00000000UL)
|
||||
#define I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)
|
||||
#define I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)
|
||||
#define I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)
|
||||
#define I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Data_Format I2S Data Format
|
||||
* @{
|
||||
*/
|
||||
#define I2S_DATAFORMAT_16B (0x00000000UL)
|
||||
#define I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)
|
||||
#define I2S_DATAFORMAT_24B (SPI_I2SCFGR_DATLEN_0)
|
||||
#define I2S_DATAFORMAT_32B (SPI_I2SCFGR_DATLEN_1)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_MCLK_Output I2S MCLK Output
|
||||
* @{
|
||||
*/
|
||||
#define I2S_MCLKOUTPUT_ENABLE (SPI_I2SCFGR_MCKOE)
|
||||
#define I2S_MCLKOUTPUT_DISABLE (0x00000000UL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Audio_Frequency I2S Audio Frequency
|
||||
* @{
|
||||
*/
|
||||
#define I2S_AUDIOFREQ_192K (192000UL)
|
||||
#define I2S_AUDIOFREQ_96K (96000UL)
|
||||
#define I2S_AUDIOFREQ_48K (48000UL)
|
||||
#define I2S_AUDIOFREQ_44K (44100UL)
|
||||
#define I2S_AUDIOFREQ_32K (32000UL)
|
||||
#define I2S_AUDIOFREQ_22K (22050UL)
|
||||
#define I2S_AUDIOFREQ_16K (16000UL)
|
||||
#define I2S_AUDIOFREQ_11K (11025UL)
|
||||
#define I2S_AUDIOFREQ_8K (8000UL)
|
||||
#define I2S_AUDIOFREQ_DEFAULT (2UL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Clock_Polarity I2S FullDuplex Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2S_CPOL_LOW (0x00000000UL)
|
||||
#define I2S_CPOL_HIGH (SPI_I2SCFGR_CKPOL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_MSB_LSB_Transmission I2S MSB LSB Transmission
|
||||
* @{
|
||||
*/
|
||||
#define I2S_FIRSTBIT_MSB (0x00000000UL)
|
||||
#define I2S_FIRSTBIT_LSB SPI_CFG2_LSBFRST
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_WSInversion I2S Word Select Inversion
|
||||
* @{
|
||||
*/
|
||||
#define I2S_WS_INVERSION_DISABLE (0x00000000UL)
|
||||
#define I2S_WS_INVERSION_ENABLE SPI_I2SCFGR_WSINV
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Data_24Bit_Alignment Data Padding 24Bit
|
||||
* @{
|
||||
*/
|
||||
#define I2S_DATA_24BIT_ALIGNMENT_RIGHT (0x00000000UL)
|
||||
#define I2S_DATA_24BIT_ALIGNMENT_LEFT SPI_I2SCFGR_DATFMT
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Master_Keep_IO_State Keep IO State
|
||||
* @{
|
||||
*/
|
||||
#define I2S_MASTER_KEEP_IO_STATE_DISABLE (0x00000000U)
|
||||
#define I2S_MASTER_KEEP_IO_STATE_ENABLE SPI_CFG2_AFCNTR
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition
|
||||
* @{
|
||||
*/
|
||||
#define I2S_IT_RXP SPI_IER_RXPIE
|
||||
#define I2S_IT_TXP SPI_IER_TXPIE
|
||||
#define I2S_IT_DXP SPI_IER_DXPIE
|
||||
#define I2S_IT_UDR SPI_IER_UDRIE
|
||||
#define I2S_IT_OVR SPI_IER_OVRIE
|
||||
#define I2S_IT_FRE SPI_IER_TIFREIE
|
||||
#define I2S_IT_ERR (SPI_IER_UDRIE | SPI_IER_OVRIE | SPI_IER_TIFREIE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Flags_Definition I2S Flags Definition
|
||||
* @{
|
||||
*/
|
||||
#define I2S_FLAG_RXP SPI_SR_RXP /* I2S status flag : Rx-Packet available flag */
|
||||
#define I2S_FLAG_TXP SPI_SR_TXP /* I2S status flag : Tx-Packet space available flag */
|
||||
#define I2S_FLAG_DXP SPI_SR_DXP /* I2S status flag : Dx-Packet space available flag */
|
||||
#define I2S_FLAG_UDR SPI_SR_UDR /* I2S Error flag : Underrun flag */
|
||||
#define I2S_FLAG_OVR SPI_SR_OVR /* I2S Error flag : Overrun flag */
|
||||
#define I2S_FLAG_FRE SPI_SR_TIFRE /* I2S Error flag : TI mode frame format error flag */
|
||||
|
||||
#define I2S_FLAG_MASK (SPI_SR_RXP | SPI_SR_TXP | SPI_SR_DXP |SPI_SR_UDR | SPI_SR_OVR | SPI_SR_TIFRE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup I2S_Exported_macros I2S Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset I2S handle state
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
|
||||
#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_I2S_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
|
||||
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
|
||||
|
||||
/** @brief Enable the specified SPI peripheral (in I2S mode).
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE))
|
||||
|
||||
/** @brief Disable the specified SPI peripheral (in I2S mode).
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE))
|
||||
|
||||
/** @brief Enable the specified I2S interrupts.
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* This parameter can be I2S where x: 1, 2 or 3 to select the I2S peripheral.
|
||||
* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_IT_RXP : Rx-Packet available interrupt
|
||||
* @arg I2S_IT_TXP : Tx-Packet space available interrupt
|
||||
* @arg I2S_IT_UDR : Underrun interrupt
|
||||
* @arg I2S_IT_OVR : Overrun interrupt
|
||||
* @arg I2S_IT_FRE : TI mode frame format error interrupt
|
||||
* @arg I2S_IT_ERR : Error interrupt enable
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
|
||||
|
||||
/** @brief Disable the specified I2S interrupts.
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* This parameter can be I2S where x: 1, 2 or 3 to select the I2S peripheral.
|
||||
* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_IT_RXP : Rx-Packet available interrupt
|
||||
* @arg I2S_IT_TXP : Tx-Packet space available interrupt
|
||||
* @arg I2S_IT_UDR : Underrun interrupt
|
||||
* @arg I2S_IT_OVR : Overrun interrupt
|
||||
* @arg I2S_IT_FRE : TI mode frame format error interrupt
|
||||
* @arg I2S_IT_ERR : Error interrupt enable
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
|
||||
|
||||
/** @brief Check if the specified I2S interrupt source is enabled or disabled.
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* This parameter can be I2S where x: 1, 2 or 3 to select the I2S peripheral.
|
||||
* @param __INTERRUPT__ specifies the I2S interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_IT_RXP : Rx-Packet available interrupt
|
||||
* @arg I2S_IT_TXP : Tx-Packet space available interrupt
|
||||
* @arg I2S_IT_DXP : Tx-Packet space available interrupt
|
||||
* @arg I2S_IT_UDR : Underrun interrupt
|
||||
* @arg I2S_IT_OVR : Overrun interrupt
|
||||
* @arg I2S_IT_FRE : TI mode frame format error interrupt
|
||||
* @arg I2S_IT_ERR : Error interrupt enable
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\
|
||||
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified I2S flag is set or not.
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* This parameter can be I2S where x: 1, 2 or 3 to select the I2S peripheral.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_FLAG_RXP : Rx-Packet available flag
|
||||
* @arg I2S_FLAG_TXP : Tx-Packet space available flag
|
||||
* @arg I2S_FLAG_UDR : Underrun flag
|
||||
* @arg I2S_FLAG_OVR : Overrun flag
|
||||
* @arg I2S_FLAG_FRE : TI mode frame format error flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clear the I2S OVR pending flag.
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC)
|
||||
|
||||
/** @brief Clear the I2S UDR pending flag.
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC)
|
||||
|
||||
/** @brief Clear the I2S FRE pending flag.
|
||||
* @param __HANDLE__: specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_CLEAR_TIFREFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup I2S_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2S_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
|
||||
HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
|
||||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
|
||||
HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
|
||||
pI2S_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2S_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* I/O operation functions ***************************************************/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, const uint16_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, const uint16_t *pTxData, uint16_t *pRxData,
|
||||
uint16_t Size, uint32_t Timeout);
|
||||
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, const uint16_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, const uint16_t *pTxData, uint16_t *pRxData,
|
||||
uint16_t Size);
|
||||
|
||||
void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
|
||||
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, const uint16_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, const uint16_t *pTxData, uint16_t *pRxData,
|
||||
uint16_t Size);
|
||||
|
||||
HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
|
||||
HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
|
||||
HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
|
||||
|
||||
/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
|
||||
void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2SEx_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2S_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control and State functions ************************************/
|
||||
HAL_I2S_StateTypeDef HAL_I2S_GetState(const I2S_HandleTypeDef *hi2s);
|
||||
uint32_t HAL_I2S_GetError(const I2S_HandleTypeDef *hi2s);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup I2S_Private_Constants I2S Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private Functions ---------------------------------------------------------*/
|
||||
/** @defgroup I2S_Private_Functions I2S Private Functions
|
||||
* @{
|
||||
*/
|
||||
/* Private functions are defined in stm32h7xx_hal_i2S.c file */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup I2S_Private_Macros I2S Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Check whether the specified SPI flag is set or not.
|
||||
* @param __SR__ copy of I2S SR register.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_FLAG_RXP : Rx-Packet available flag
|
||||
* @arg I2S_FLAG_TXP : Tx-Packet space available flag
|
||||
* @arg I2S_FLAG_UDR : Underrun flag
|
||||
* @arg I2S_FLAG_OVR : Overrun flag
|
||||
* @arg I2S_FLAG_FRE : TI mode frame format error flag
|
||||
* @retval SET or RESET.
|
||||
*/
|
||||
#define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__)\
|
||||
& ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK))\
|
||||
? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified SPI Interrupt is set or not.
|
||||
* @param __IER__ copy of I2S IER register.
|
||||
* @param __INTERRUPT__ specifies the SPI interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_IT_RXP : Rx-Packet available interrupt
|
||||
* @arg I2S_IT_TXP : Tx-Packet space available interrupt
|
||||
* @arg I2S_IT_UDR : Underrun interrupt
|
||||
* @arg I2S_IT_OVR : Overrun interrupt
|
||||
* @arg I2S_IT_FRE : TI mode frame format error interrupt
|
||||
* @arg I2S_IT_ERR : Error interrupt enable
|
||||
* @retval SET or RESET.
|
||||
*/
|
||||
#define I2S_CHECK_IT_SOURCE(__IER__, __INTERRUPT__) ((((__IER__)\
|
||||
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Checks if I2S Mode parameter is in allowed range.
|
||||
* @param __MODE__ specifies the I2S Mode.
|
||||
* This parameter can be a value of @ref I2S_Mode
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_I2S_MODE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \
|
||||
((__MODE__) == I2S_MODE_SLAVE_RX) || \
|
||||
((__MODE__) == I2S_MODE_MASTER_TX) || \
|
||||
((__MODE__) == I2S_MODE_MASTER_RX) || \
|
||||
((__MODE__) == I2S_MODE_SLAVE_FULLDUPLEX) || \
|
||||
((__MODE__) == I2S_MODE_MASTER_FULLDUPLEX))
|
||||
|
||||
#define IS_I2S_MASTER(__MODE__) (((__MODE__) == I2S_MODE_MASTER_TX) || \
|
||||
((__MODE__) == I2S_MODE_MASTER_RX) || \
|
||||
((__MODE__) == I2S_MODE_MASTER_FULLDUPLEX))
|
||||
|
||||
#define IS_I2S_SLAVE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \
|
||||
((__MODE__) == I2S_MODE_SLAVE_RX) || \
|
||||
((__MODE__) == I2S_MODE_SLAVE_FULLDUPLEX))
|
||||
|
||||
#define IS_I2S_FULLDUPLEX(__MODE__) (((__MODE__) == I2S_MODE_MASTER_FULLDUPLEX) || \
|
||||
((__MODE__) == I2S_MODE_SLAVE_FULLDUPLEX))
|
||||
|
||||
#define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS) || \
|
||||
((__STANDARD__) == I2S_STANDARD_MSB) || \
|
||||
((__STANDARD__) == I2S_STANDARD_LSB) || \
|
||||
((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \
|
||||
((__STANDARD__) == I2S_STANDARD_PCM_LONG))
|
||||
|
||||
#define IS_I2S_DATA_FORMAT(__FORMAT__) (((__FORMAT__) == I2S_DATAFORMAT_16B) || \
|
||||
((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED) || \
|
||||
((__FORMAT__) == I2S_DATAFORMAT_24B) || \
|
||||
((__FORMAT__) == I2S_DATAFORMAT_32B))
|
||||
|
||||
#define IS_I2S_MCLK_OUTPUT(__OUTPUT__) (((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE) || \
|
||||
((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE))
|
||||
|
||||
#define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K) && \
|
||||
((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \
|
||||
((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))
|
||||
|
||||
#define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) || \
|
||||
((__CPOL__) == I2S_CPOL_HIGH))
|
||||
|
||||
#define IS_I2S_FIRST_BIT(__BIT__) (((__BIT__) == I2S_FIRSTBIT_MSB) || \
|
||||
((__BIT__) == I2S_FIRSTBIT_LSB))
|
||||
|
||||
#define IS_I2S_WS_INVERSION(__WSINV__) (((__WSINV__) == I2S_WS_INVERSION_DISABLE) || \
|
||||
((__WSINV__) == I2S_WS_INVERSION_ENABLE))
|
||||
|
||||
#define IS_I2S_DATA_24BIT_ALIGNMENT(__ALIGNMENT__) (((__ALIGNMENT__) == I2S_DATA_24BIT_ALIGNMENT_RIGHT) || \
|
||||
((__ALIGNMENT__) == I2S_DATA_24BIT_ALIGNMENT_LEFT))
|
||||
|
||||
#define IS_I2S_MASTER_KEEP_IO_STATE(__AFCNTR__) (((__AFCNTR__) == I2S_MASTER_KEEP_IO_STATE_DISABLE) || \
|
||||
((__AFCNTR__) == I2S_MASTER_KEEP_IO_STATE_ENABLE))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7RSxx_HAL_I2S_H */
|
||||
|
||||
|
|
@ -1,26 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7rsxx_hal_i2s_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of I2S HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/**
|
||||
******************************************************************************
|
||||
===== I2S FULL DUPLEX FEATURE =====
|
||||
I2S Full Duplex APIs are available in stm32h7rsxx_hal_i2s.c/.h
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
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Reference in New Issue