[bsp][hc32] support hc32f448

.github/workflows/bsp_buildings.yml

@@ -76,6 +76,7 @@ jobs:
                 - "at32/at32f437-start"
                 - "yichip/yc3122-pos"
                 - "hc32/ev_hc32f4a0_lqfp176"
+                - "hc32/ev_hc32f448_lqfp80"
                 - "hc32/ev_hc32f460_lqfp100_v2"
                 - "hc32l196"
                 - "mm32/mm32f3270-100ask-pitaya"

bsp/hc32/README.md

@@ -9,6 +9,7 @@ HC32 系列 BSP 目前支持情况如下表所示：
 | **F4 系列** |  |
 | [ev_hc32f460_lqfp100_v2](ev_hc32f460_lqfp100_v2) | 小华 官方 EV_F460_LQ100_V2 开发板 |
 | [ev_hc32f4a0_lqfp176](ev_hc32f4a0_lqfp176) | 小华 官方 EV_F4A0_LQ176 开发板 |
+| [ev_hc32f448_lqfp80](ev_hc32f448_lqfp80) | 小华 官方 EV_F448_LQ80 开发板 |
 | **M1 系列** |  |
 | **M4 系列** |  |
 

bsp/hc32/ev_hc32f448_lqfp80/.gitignore

@@ -0,0 +1,42 @@
+*.pyc
+*.map
+*.dblite
+*.elf
+*.bin
+*.hex
+*.axf
+*.exe
+*.pdb
+*.idb
+*.ilk
+*.old
+build
+Debug
+documentation/html
+packages/
+*~
+*.o
+*.obj
+*.out
+*.bak
+*.dep
+*.lib
+*.i
+*.d
+.DS_Stor*
+.config 3
+.config 4
+.config 5
+Midea-X1
+*.uimg
+GPATH
+GRTAGS
+GTAGS
+.vscode
+JLinkLog.txt
+JLinkSettings.ini
+DebugConfig/
+RTE/
+settings/
+*.uvguix*
+cconfig.h

bsp/hc32/ev_hc32f448_lqfp80/.project

@@ -0,0 +1,68 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+  <name>project</name>
+  <comment />
+  <projects>
+	</projects>
+  <buildSpec>
+    <buildCommand>
+      <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+      <triggers>clean,full,incremental,</triggers>
+      <arguments>
+			</arguments>
+    </buildCommand>
+    <buildCommand>
+      <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+      <triggers>full,incremental,</triggers>
+      <arguments>
+			</arguments>
+    </buildCommand>
+  </buildSpec>
+  <natures>
+    <nature>org.eclipse.cdt.core.cnature</nature>
+    <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+    <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+  </natures>
+  <linkedResources>
+    <link>
+      <name>rt-thread</name>
+      <type>2</type>
+      <locationURI>virtual:/virtual</locationURI>
+    </link>
+    <link>
+      <name>rt-thread/bsp</name>
+      <type>2</type>
+      <locationURI>virtual:/virtual</locationURI>
+    </link>
+    <link>
+      <name>rt-thread/components</name>
+      <type>2</type>
+      <locationURI>$%7BPARENT-3-PROJECT_LOC%7D/components</locationURI>
+    </link>
+    <link>
+      <name>rt-thread/include</name>
+      <type>2</type>
+      <locationURI>$%7BPARENT-3-PROJECT_LOC%7D/include</locationURI>
+    </link>
+    <link>
+      <name>rt-thread/libcpu</name>
+      <type>2</type>
+      <locationURI>$%7BPARENT-3-PROJECT_LOC%7D/libcpu</locationURI>
+    </link>
+    <link>
+      <name>rt-thread/src</name>
+      <type>2</type>
+      <locationURI>$%7BPARENT-3-PROJECT_LOC%7D/src</locationURI>
+    </link>
+    <link>
+      <name>rt-thread/bsp/hc32</name>
+      <type>2</type>
+      <locationURI>virtual:/virtual</locationURI>
+    </link>
+    <link>
+      <name>rt-thread/bsp/hc32/libraries</name>
+      <type>2</type>
+      <locationURI>$%7BPARENT-1-PROJECT_LOC%7D/libraries</locationURI>
+    </link>
+  </linkedResources>
+</projectDescription>

bsp/hc32/ev_hc32f448_lqfp80/Kconfig

@@ -0,0 +1,21 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "../libraries/Kconfig"
+source "board/Kconfig"

bsp/hc32/ev_hc32f448_lqfp80/README.md

@@ -0,0 +1,128 @@
+# XHSC EV_F448_LQ80_Rev1.0 开发板 BSP 说明
+
+## 简介
+
+本文档为小华半导体为 EV_F448_LQ80_Rev1.0 开发板提供的 BSP (板级支持包) 说明。
+
+主要内容如下：
+
+- 开发板资源介绍
+- BSP 快速上手
+- 进阶使用方法
+
+通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
+
+## 开发板介绍
+
+EV_F448_LQ80_Rev1.0 是 XHSC 官方推出的开发板，搭载 HC32F448MCTI 芯片，基于 ARM Cortex-M4 内核，最高主频 200 MHz，具有丰富的板载资源，可以充分发挥 HC32F448MCTI 的芯片性能。
+
+开发板外观如下图所示：
+
+ ![board](figures/board.png)
+
+EV_F448_LQ80_Rev1.0 开发板常用 **板载资源** 如下：
+
+- **MCU**
+  - HC32F448MCTI
+  - 主频200MHz
+  - 256KB FLASH
+  - 68KB RAM
+- **外部Memory**
+  - BL24C256（EEPROM, 256Kbits）
+  - W25Q64（SPI NOR，64MB）
+  - IS62WV51216（SRAM， 1MB）
+- **常用外设**
+  - LED: 4 个，User LED（LED0，LED1，LED2，LED3）。
+  - 按键: 5 个，矩阵键盘（K1~K4）， WAKEUP（K5），RESET（K0）
+- **常用接口**
+  - USB转串口
+  - CAN DB9接口 * 2
+  - TFT接口
+  - SmartCard接口
+  - I2C/USART/SPI接口
+- **调试接口**
+  - 板载DAP调试器
+  - 标准JTAG/SWD/Trace
+
+开发板更多详细信息请参考小华半导体半导体[EV_F448_LQ80_Rev1.0](https://www.xhsc.com.cn)
+
+## 外设支持
+
+本 BSP 目前对外设的支持情况如下：
+
+| **板载外设**  | **支持情况** |               **备注**                |
+| :------------ | :-----------: | :-----------------------------------: |
+| USB 转串口    |      支持     |          使用 UART2                  |
+| LED           |     支持     |           LED1~4                   |
+
+| **片上外设**  | **支持情况** |               **备注**                |
+| :------------ | :-----------: | :-----------------------------------: |
+| ADC           |     支持     | ADC1: CH10, CH11, <br>ADC3: CH1 |
+| CAN           |     支持     |              CAN1、CAN2                      |
+| GPIO          |     支持     | PA0, PA1... PH2 ---> PIN: 0, 1...82 |
+| I2C           |     支持     | 软件模拟<br>硬件I2C1~2<br>I2C1支持EEPROM（BL24C256） |
+| Hwtimer           |     支持     | Hwtimer1~5 |
+| SPI           |     支持     | SPI1~3<br>SPI1支持W25Q |
+| UART          |     支持     |              UART1~6<br>UART2为console使用                 |
+
+
+## 使用说明
+
+使用说明分为如下两个章节：
+
+- 快速上手
+
+    本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
+
+- 进阶使用
+
+    本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
+
+
+### 快速上手
+
+本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
+
+#### 硬件连接
+
+使用Type-A to MircoUSB线连接开发板和PC供电。
+
+#### 编译下载
+
+双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
+
+> 工程默认配置使用板载 DAP 下载程序，点击下载按钮即可下载程序到开发板。
+
+#### 运行结果
+
+下载程序成功之后，系统会自动运行，观察开发板上LED的运行效果，绿色LED3会周期性闪烁。
+
+USB虚拟COM端口默认连接串口2，在终端工具里打开相应的串口，复位设备后，可以看到 RT-Thread 的输出信息:
+
+```
+ \ | /
+- RT -     Thread Operating System
+ / | \     5.0.1 build Feb  4 2024 16:44:26
+ 2006 - 2022 Copyright by RT-Thread team
+msh >
+```
+
+### 进阶使用
+
+此 BSP 默认只开启了 GPIO 和 串口 2 的功能，更多高级功能需要利用 env 工具对 BSP 进行配置，步骤如下：
+
+1. 在 bsp 下打开 env 工具。
+
+2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
+
+3. 输入`pkgs --update`命令更新软件包。
+
+4. 输入`scons --target=mdk5/iar` 命令重新生成工程。
+
+## 注意事项
+无
+## 联系人信息
+
+维护人:
+
+-  [小华半导体MCU](https://www.xhsc.com.cn)，邮箱：<xhsc_mcu@xhsc.com.cn>

bsp/hc32/ev_hc32f448_lqfp80/SConscript

@@ -0,0 +1,15 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/hc32/ev_hc32f448_lqfp80/SConstruct

@@ -0,0 +1,62 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM in ['iccarm']:
+    env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/libraries'):
+    libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+hc32_library = 'hc32f448_ddl'
+rtconfig.BSP_LIBRARY_TYPE = hc32_library
+
+# include libraries
+objs.extend(SConscript(os.path.join(libraries_path_prefix, hc32_library, 'SConscript')))
+
+# include drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'hc32_drivers', 'SConscript')))
+
+objs.extend(SConscript(os.path.join(os.getcwd(), 'board', 'ports', 'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/hc32/ev_hc32f448_lqfp80/applications/SConscript

@@ -0,0 +1,15 @@
+from building import *
+import os
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+CPPPATH = [cwd]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+list = os.listdir(cwd)
+for item in list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        group = group + SConscript(os.path.join(item, 'SConscript'))
+
+Return('group')

bsp/hc32/ev_hc32f448_lqfp80/applications/main.c

@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2006-2024, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-02-20     CDT          first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <board.h>
+
+/* defined the LED_GREEN pin: PA2 */
+#define LED_GREEN_PIN GET_PIN(A, 2)
+
+int main(void)
+{
+    /* set LED_GREEN_PIN pin mode to output */
+    rt_pin_mode(LED_GREEN_PIN, PIN_MODE_OUTPUT);
+
+    while (1)
+    {
+        rt_pin_write(LED_GREEN_PIN, PIN_HIGH);
+        rt_thread_mdelay(500);
+        rt_pin_write(LED_GREEN_PIN, PIN_LOW);
+        rt_thread_mdelay(500);
+    }
+}
+

bsp/hc32/ev_hc32f448_lqfp80/applications/xtal32_fcm.c

@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-02-20     CDT          first version
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <board.h>
+
+#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
+
+#define XTAL32_FCM_THREAD_STACK_SIZE    (1024)
+
+/**
+ * @brief This thread is used to monitor whether XTAL32 is stable.
+ *        This thread only runs once after the system starts.
+ *        When stability is detected or 2s times out, the thread will end.
+ *       (When a timeout occurs it will be prompted via rt_kprintf)
+ */
+void xtal32_fcm_thread_entry(void *parameter)
+{
+    stc_fcm_init_t stcFcmInit;
+    uint32_t u32TimeOut = 0UL;
+    uint32_t u32Time = 200UL; /* 200*10ms = 2s */
+
+    /* FCM config */
+    FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, ENABLE);
+    (void)FCM_StructInit(&stcFcmInit);
+    stcFcmInit.u32RefClock       = FCM_REF_CLK_MRC;
+    stcFcmInit.u32RefClockDiv    = FCM_REF_CLK_DIV8192; /* ~1ms cycle */
+    stcFcmInit.u32RefClockEdge   = FCM_REF_CLK_RISING;
+    stcFcmInit.u32TargetClock    = FCM_TARGET_CLK_XTAL32;
+    stcFcmInit.u32TargetClockDiv = FCM_TARGET_CLK_DIV1;
+    stcFcmInit.u16LowerLimit     = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL);
+    stcFcmInit.u16UpperLimit     = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL);
+    (void)FCM_Init(&stcFcmInit);
+    /* Enable FCM, to ensure xtal32 stable */
+    FCM_Cmd(ENABLE);
+
+    while (1)
+    {
+        if (SET == FCM_GetStatus(FCM_FLAG_END))
+        {
+            FCM_ClearStatus(FCM_FLAG_END);
+            if ((SET == FCM_GetStatus(FCM_FLAG_ERR)) || (SET == FCM_GetStatus(FCM_FLAG_OVF)))
+            {
+                FCM_ClearStatus(FCM_FLAG_ERR | FCM_FLAG_OVF);
+            }
+            else
+            {
+                (void)FCM_DeInit();
+                FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE);
+                /* XTAL32 stabled */
+                break;
+            }
+        }
+        u32TimeOut++;
+        if (u32TimeOut > u32Time)
+        {
+            (void)FCM_DeInit();
+            FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE);
+            rt_kprintf("Error: XTAL32 still unstable, timeout.\n");
+            break;
+        }
+        rt_thread_mdelay(10);
+    }
+}
+
+int xtal32_fcm_thread_create(void)
+{
+    rt_thread_t tid;
+
+    tid = rt_thread_create("xtal32_fcm", xtal32_fcm_thread_entry, RT_NULL,
+                           XTAL32_FCM_THREAD_STACK_SIZE, RT_THREAD_PRIORITY_MAX - 2, 10);
+    if (tid != RT_NULL)
+    {
+        rt_thread_startup(tid);
+    }
+    else
+    {
+        rt_kprintf("create xtal32_fcm thread err!");
+    }
+    return RT_EOK;
+}
+INIT_APP_EXPORT(xtal32_fcm_thread_create);
+
+#endif
+
+

bsp/hc32/ev_hc32f448_lqfp80/board/Kconfig

@@ -0,0 +1,652 @@
+menu "Hardware Drivers Config"
+
+config SOC_HC32F448MC
+    bool
+    select SOC_SERIES_HC32F4
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
+
+menu "On-chip Drivers"
+    menuconfig BSP_USING_ON_CHIP_FLASH_CACHE
+        bool "Enable on-chip Flash Cache"
+        default y
+        if BSP_USING_ON_CHIP_FLASH_CACHE
+            config BSP_USING_ON_CHIP_FLASH_ICODE_CACHE
+                bool "Enable on-chip Flash ICODE Cache"
+                default y
+            config BSP_USING_ON_CHIP_FLASH_DCODE_CACHE
+                bool "Enable on-chip Flash DCODE Cache"
+                default y
+            config BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH
+                bool "Enable on-chip Flash ICODE Prefetch"
+                default y
+        endif
+endmenu
+
+menu "Onboard Peripheral Drivers"
+    config BSP_USING_TCA9539
+        bool "Enable TCA9539"
+        select BSP_USING_I2C
+        select BSP_USING_I2C1
+        default n
+
+    config BSP_USING_SPI_FLASH
+        bool "Enable SPI FLASH (w25q64 spi1)"
+        select BSP_USING_SPI
+        select BSP_USING_SPI1
+        select BSP_USING_ON_CHIP_FLASH
+        select RT_USING_SFUD
+        select RT_USING_DFS
+        select RT_USING_FAL
+        select RT_USING_MTD_NOR
+        default n
+
+endmenu
+
+menu "On-chip Peripheral Drivers"
+    config BSP_USING_GPIO
+        bool "Enable GPIO"
+        select RT_USING_PIN
+        default y
+
+    menuconfig BSP_USING_UART
+        bool "Enable UART"
+        default y
+        select RT_USING_SERIAL
+        if BSP_USING_UART
+            menuconfig BSP_USING_UART1
+                bool "Enable UART1"
+                default y
+                if BSP_USING_UART1
+                    config BSP_UART1_RX_USING_DMA
+                        bool "Enable UART1 RX DMA"
+                        depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
+                        default n
+
+                    config BSP_UART1_TX_USING_DMA
+                        bool "Enable UART1 TX DMA"
+                        depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
+                        default n
+
+                    config BSP_UART1_RX_BUFSIZE
+                        int "Set UART1 RX buffer size"
+                        range 64 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 256
+
+                    config BSP_UART1_TX_BUFSIZE
+                        int "Set UART1 TX buffer size"
+                        range 0 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 256
+                endif
+
+            menuconfig BSP_USING_UART2
+                bool "Enable UART2"
+                default n
+                if BSP_USING_UART2
+                    config BSP_UART2_RX_USING_DMA
+                        bool "Enable UART2 RX DMA"
+                        depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
+                        default n
+
+                    config BSP_UART2_TX_USING_DMA
+                        bool "Enable UART2 TX DMA"
+                        depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
+                        default n
+
+                    config BSP_UART2_RX_BUFSIZE
+                        int "Set UART2 RX buffer size"
+                        range 64 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 256
+
+                    config BSP_UART2_TX_BUFSIZE
+                        int "Set UART2 TX buffer size"
+                        range 0 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 0
+                endif
+
+            menuconfig BSP_USING_UART3
+                bool "Enable UART3"
+                default n
+                if BSP_USING_UART3
+                    config BSP_UART3_RX_BUFSIZE
+                        int "Set UART3 RX buffer size"
+                        range 64 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 256
+
+                    config BSP_UART3_TX_BUFSIZE
+                        int "Set UART3 TX buffer size"
+                        range 0 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 0
+                endif
+
+            menuconfig BSP_USING_UART4
+                bool "Enable UART4"
+                default n
+                if BSP_USING_UART4
+                    config BSP_UART4_RX_USING_DMA
+                        bool "Enable UART4 RX DMA"
+                        depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA
+                        default n
+
+                    config BSP_UART4_TX_USING_DMA
+                        bool "Enable UART4 TX DMA"
+                        depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA
+                        default n
+
+                    config BSP_UART4_RX_BUFSIZE
+                        int "Set UART4 RX buffer size"
+                        range 64 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 256
+
+                    config BSP_UART4_TX_BUFSIZE
+                        int "Set UART4 TX buffer size"
+                        range 0 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 256
+                endif
+
+            menuconfig BSP_USING_UART5
+                bool "Enable UART5"
+                default n
+                if BSP_USING_UART5
+                    config BSP_UART5_RX_USING_DMA
+                        bool "Enable UART5 RX DMA"
+                        depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA
+                        default n
+
+                    config BSP_UART5_TX_USING_DMA
+                        bool "Enable UART5 TX DMA"
+                        depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA
+                        default n
+
+                    config BSP_UART5_RX_BUFSIZE
+                        int "Set UART5 RX buffer size"
+                        range 64 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 256
+
+                    config BSP_UART5_TX_BUFSIZE
+                        int "Set UART5 TX buffer size"
+                        range 0 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 256
+                endif
+
+            menuconfig BSP_USING_UART6
+                bool "Enable UART6"
+                default n
+                if BSP_USING_UART6
+                    config BSP_UART6_RX_BUFSIZE
+                        int "Set UART6 RX buffer size"
+                        range 64 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 256
+
+                    config BSP_UART6_TX_BUFSIZE
+                        int "Set UART6 TX buffer size"
+                        range 0 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 0
+                endif
+        endif
+
+    menuconfig BSP_USING_I2C
+        bool "Enable I2C BUS"
+        default n
+        select RT_USING_I2C
+
+        if BSP_USING_I2C
+            menuconfig BSP_USING_I2C1_SW
+                bool "Enable I2C1 BUS (software simulation)"
+                default n
+                select RT_USING_I2C_BITOPS
+                select RT_USING_PIN
+                if BSP_USING_I2C1_SW
+                    config BSP_I2C1_SCL_PIN
+                        int "i2c1 scl pin number"
+                        range 1 176
+                        default 51
+                    config BSP_I2C1_SDA_PIN
+                        int "I2C1 sda pin number"
+                        range 1 176
+                        default 90
+                endif
+        endif
+
+        if BSP_USING_I2C
+            config BSP_I2C_USING_DMA
+                bool
+                default n
+            config BSP_USING_I2C_HW
+                bool
+                default n
+
+            menuconfig BSP_USING_I2C1
+                bool "Enable I2C1 BUS"
+                default n
+                select BSP_USING_I2C_HW
+                if BSP_USING_I2C1
+                    config BSP_I2C1_USING_DMA
+                        bool
+                        default n
+                    config BSP_I2C1_TX_USING_DMA
+                        bool "Enable I2C1 TX DMA"
+                        default n
+                        select BSP_I2C_USING_DMA
+                        select BSP_I2C1_USING_DMA
+                    config BSP_I2C1_RX_USING_DMA
+                        bool "Enable I2C1 RX DMA"
+                        default n
+                        select BSP_I2C_USING_DMA
+                        select BSP_I2C1_USING_DMA
+                endif
+
+            menuconfig BSP_USING_I2C2
+                bool "Enable I2C2 BUS"
+                default n
+                select BSP_USING_I2C_HW
+                if BSP_USING_I2C2
+                    config BSP_I2C2_USING_DMA
+                        bool
+                        default n
+                    config BSP_I2C2_TX_USING_DMA
+                        bool "Enable I2C2 TX DMA"
+                        default n
+                        select BSP_I2C_USING_DMA
+                        select BSP_I2C2_USING_DMA
+                    config BSP_I2C2_RX_USING_DMA
+                        bool "Enable I2C2 RX DMA"
+                        default n
+                        select BSP_I2C_USING_DMA
+                        select BSP_I2C2_USING_DMA
+                endif
+        endif
+
+    config BSP_USING_ON_CHIP_FLASH
+        bool "Enable on-chip FLASH"
+        default n
+
+    menuconfig BSP_USING_SPI
+        bool "Enable SPI BUS"
+        default n
+        select RT_USING_SPI
+        if BSP_USING_SPI
+            config BSP_SPI_USING_DMA
+                bool
+                default n
+
+            menuconfig BSP_USING_SPI1
+                bool "Enable SPI1 BUS"
+                default n
+                if BSP_USING_SPI1
+                    config BSP_SPI1_TX_USING_DMA
+                        bool "Enable SPI1 TX DMA"
+                        select BSP_SPI_USING_DMA
+                        default n
+                    config BSP_SPI1_RX_USING_DMA
+                        bool "Enable SPI1 RX DMA"
+                        select BSP_SPI_USING_DMA
+                        select BSP_SPI1_TX_USING_DMA
+                        default n
+                endif
+
+            menuconfig BSP_USING_SPI2
+                bool "Enable SPI2 BUS"
+                default n
+                if BSP_USING_SPI2
+                    config BSP_SPI2_TX_USING_DMA
+                        bool "Enable SPI2 TX DMA"
+                        select BSP_SPI_USING_DMA
+                        default n
+                    config BSP_SPI2_RX_USING_DMA
+                        bool "Enable SPI2 RX DMA"
+                        select BSP_SPI_USING_DMA
+                        select BSP_SPI2_TX_USING_DMA
+                        default n
+                endif
+
+            menuconfig BSP_USING_SPI3
+                bool "Enable SPI3 BUS"
+                default n
+                if BSP_USING_SPI3
+                    config BSP_SPI3_TX_USING_DMA
+                        bool "Enable SPI3 TX DMA"
+                        select BSP_SPI_USING_DMA
+                        default n
+                    config BSP_SPI3_RX_USING_DMA
+                        bool "Enable SPI3 RX DMA"
+                        select BSP_SPI_USING_DMA
+                        select BSP_SPI3_TX_USING_DMA
+                        default n
+                endif
+        endif
+
+    menuconfig BSP_USING_ADC
+        bool "Enable ADC"
+        default n
+        select RT_USING_ADC
+        if BSP_USING_ADC
+            menuconfig BSP_USING_ADC1
+                bool "Enable ADC1"
+                default n
+                if BSP_USING_ADC1
+                    config BSP_ADC1_USING_DMA
+                        bool "using adc1 dma"
+                        default n
+                endif
+            menuconfig BSP_USING_ADC2
+                bool "Enable ADC2"
+                default n
+                if BSP_USING_ADC2
+                    config BSP_ADC2_USING_DMA
+                        bool "using adc2 dma"
+                        default n
+                endif
+            menuconfig BSP_USING_ADC3
+                bool "Enable ADC3"
+                default n
+                if BSP_USING_ADC3
+                    config BSP_ADC3_USING_DMA
+                        bool "using adc3 dma"
+                        default n
+                endif
+        endif
+
+    menuconfig BSP_USING_DAC
+        bool "Enable DAC"
+        default n
+        select RT_USING_DAC
+        if BSP_USING_DAC
+            config BSP_USING_DAC1
+                bool "using dac1"
+                default n
+            config BSP_USING_DAC2
+                bool "using dac2"
+                default n
+        endif
+
+    menuconfig BSP_USING_CAN
+        bool "Enable CAN"
+        default n
+        select RT_USING_CAN
+        select RT_CAN_USING_HDR
+        select BSP_USING_TCA9539
+        if BSP_USING_CAN
+            config BSP_USING_CAN1
+                bool "using can1"
+                default n
+            config BSP_USING_CAN2
+                bool "using can2"
+                default n
+        endif
+
+    menuconfig BSP_USING_WDT_TMR
+        bool "Enable Watchdog Timer"
+        default n
+        select RT_USING_WDT
+        if BSP_USING_WDT_TMR
+            choice
+                prompt "Select SWDT/WDT"
+                default BSP_USING_SWDT
+
+                config BSP_USING_SWDT
+                    bool "SWDT(3.72hour(max))"
+                config BSP_USING_WDT
+                    bool "WDT(10.7s(max))"
+            endchoice
+
+            config BSP_WDT_CONTINUE_COUNT
+                bool "Low Power Mode Keeps Counting"
+                default n
+        endif
+
+    menuconfig BSP_USING_RTC
+        bool "Enable RTC"
+        select RT_USING_RTC
+        default n
+        if BSP_USING_RTC
+            choice
+                prompt "Select clock source"
+                default BSP_RTC_USING_XTAL32
+
+                config BSP_RTC_USING_XTAL32
+                    bool "RTC USING XTAL32"
+
+                config BSP_RTC_USING_LRC
+                    bool "RTC USING LRC"
+            endchoice
+        endif
+
+    menuconfig BSP_USING_PM
+        bool "Enable PM"
+        default n
+        select RT_USING_PM
+        if BSP_USING_PM
+            choice
+                prompt "Select WKTM Clock Src"
+                default BSP_USING_WKTM_LRC
+
+                config BSP_USING_WKTM_XTAL32
+                    bool "Using Xtal32"
+                config BSP_USING_WKTM_LRC
+                    bool "Using LRC"
+                if BSP_RTC_USING_XTAL32
+                    config BSP_USING_WKTM_64HZ
+                        bool "Using 64HZ(Note:must use XTAL32 and run RTC)"
+                endif
+            endchoice
+        endif
+
+    menuconfig BSP_USING_HWCRYPTO
+        bool "Using Hardware Crypto drivers"
+        default n
+        select RT_USING_HWCRYPTO
+        if BSP_USING_HWCRYPTO
+            config BSP_USING_UQID
+            bool "Enable UQID (unique id)"
+            default n
+
+            config BSP_USING_RNG
+            bool "Using Hardware RNG"
+            default n
+            select RT_HWCRYPTO_USING_RNG
+
+            config BSP_USING_CRC
+            bool "Using Hardware CRC"
+            default n
+            select RT_HWCRYPTO_USING_CRC
+
+            config BSP_USING_AES
+            bool "Using Hardware AES"
+            default n
+            select RT_HWCRYPTO_USING_AES
+            if BSP_USING_AES
+                choice
+                    prompt "Select AES Mode"
+                    default BSP_USING_AES_ECB
+
+                    config BSP_USING_AES_ECB
+                        bool "ECB mode"
+                        select RT_HWCRYPTO_USING_AES_ECB
+                endchoice
+            endif
+
+            config BSP_USING_HASH
+            bool "Using Hardware Hash"
+            default n
+            select RT_HWCRYPTO_USING_SHA2
+            if BSP_USING_HASH
+                choice
+                    prompt "Select Hash Mode"
+                    default BSP_USING_SHA2_256
+
+                    config BSP_USING_SHA2_256
+                        bool "SHA2_256 Mode"
+                        select RT_HWCRYPTO_USING_SHA2_256
+                endchoice
+            endif
+
+        endif
+
+    menuconfig BSP_USING_PWM
+        bool "Enable output PWM"
+        default n
+        select RT_USING_PWM
+        if BSP_USING_PWM
+            menuconfig BSP_USING_PWM_TMRA
+                bool "Enable timerA output PWM"
+                default n
+                if BSP_USING_PWM_TMRA
+                    menuconfig BSP_USING_PWM_TMRA_1
+                        bool "Enable timerA-1 output PWM"
+                        default n
+                        if BSP_USING_PWM_TMRA_1
+                            config BSP_USING_PWM_TMRA_1_CH1
+                                bool "Enable timerA-1 channel1"
+                                default n
+                            config BSP_USING_PWM_TMRA_1_CH2
+                                bool "Enable timerA-1 channel2"
+                                default n
+                        endif
+                    menuconfig BSP_USING_PWM_TMRA_2
+                        bool "Enable timerA-2 output PWM"
+                        default n
+                        if BSP_USING_PWM_TMRA_2
+                            config BSP_USING_PWM_TMRA_2_CH1
+                                bool "Enable timerA-2 channel1"
+                                default n
+                            config BSP_USING_PWM_TMRA_2_CH2
+                                bool "Enable timerA-2 channel2"
+                                default n
+                        endif
+                endif
+            menuconfig BSP_USING_PWM_TMR4
+                bool "Enable timer4 output PWM"
+                default n
+                if BSP_USING_PWM_TMR4
+                    menuconfig BSP_USING_PWM_TMR4_1
+                        bool "Enable timer4-1 output PWM"
+                        default n
+                        if BSP_USING_PWM_TMR4_1
+                            config BSP_USING_PWM_TMR4_1_OUH
+                                bool "Enable TMR4_1_OUH channel0"
+                                default n
+                            config BSP_USING_PWM_TMR4_1_OUL
+                                bool "Enable TMR4_1_OUL channel1"
+                                default n
+                            config BSP_USING_PWM_TMR4_1_OVH
+                                bool "Enable TMR4_1_OVH channel2"
+                                default n
+                            config BSP_USING_PWM_TMR4_1_OVL
+                                bool "Enable TMR4_1_OVL channel3"
+                                default n
+                            config BSP_USING_PWM_TMR4_1_OWH
+                                bool "Enable TMR4_1_OWH channel4"
+                                default n
+                            config BSP_USING_PWM_TMR4_1_OWL
+                                bool "Enable TMR4_1_OWL channel5"
+                                default n
+                        endif
+                endif
+            menuconfig BSP_USING_PWM_TMR6
+                bool "Enable timer6 output PWM"
+                default n
+                if BSP_USING_PWM_TMR6
+                    menuconfig BSP_USING_PWM_TMR6_1
+                        bool "Enable timer6-1 output PWM"
+                        default n
+                        if BSP_USING_PWM_TMR6_1
+                            config BSP_USING_PWM_TMR6_1_A
+                                bool "Enable TMR6_1_A channel0"
+                                default n
+                            config BSP_USING_PWM_TMR6_1_B
+                                bool "Enable TMR6_1_B channel1"
+                                default n
+                        endif
+                endif
+        endif
+
+    menuconfig BSP_USING_QSPI
+        bool "Enable QSPI BUS"
+        select RT_USING_QSPI
+        select RT_USING_SPI
+        default n
+        if BSP_USING_QSPI
+            config BSP_QSPI_USING_DMA
+                bool "Enable QSPI DMA support"
+                default n
+            config BSP_QSPI_USING_SOFT_CS
+                bool "Enable QSPI Soft CS Pin"
+                default n
+        endif
+
+    menuconfig BSP_USING_PULSE_ENCODER
+        bool "Enable Pulse Encoder"
+        default n
+        select RT_USING_PULSE_ENCODER
+        if BSP_USING_PULSE_ENCODER
+            menuconfig BSP_USING_TMRA_PULSE_ENCODER
+                bool "Use TIMERA As The Pulse Encoder"
+                default n
+                if BSP_USING_TMRA_PULSE_ENCODER
+                    config BSP_USING_PULSE_ENCODER_TMRA_1
+                        bool "Use TIMERA_1 As The Pulse Encoder"
+                        default n
+                endif
+            menuconfig BSP_USING_TMR6_PULSE_ENCODER
+                bool "Use TIMER6 As The Pulse Encoder"
+                default n
+                if BSP_USING_TMR6_PULSE_ENCODER
+                    config BSP_USING_PULSE_ENCODER_TMR6_1
+                        bool "Use TIMER6_1 As The Pulse Encoder"
+                        default n
+                endif
+        endif
+
+    menuconfig BSP_USING_HWTIMER
+        bool "Enable Hw Timer"
+        default n
+        select RT_USING_HWTIMER
+        if BSP_USING_HWTIMER
+            config BSP_USING_TMRA_1
+                bool "Use Timer_a1 As The Hw Timer"
+                default n
+            config BSP_USING_TMRA_2
+                bool "Use Timer_a2 As The Hw Timer"
+                default n
+            config BSP_USING_TMRA_3
+                bool "Use Timer_a3 As The Hw Timer"
+                default n
+            config BSP_USING_TMRA_4
+                bool "Use Timer_a4 As The Hw Timer"
+                default n
+            config BSP_USING_TMRA_5
+                bool "Use Timer_a5 As The Hw Timer"
+                default n
+        endif
+
+    menuconfig BSP_USING_SENSOR
+        bool "Enable SENSOR"
+        default n
+        select RT_USING_HWTIMER
+        if BSP_USING_SENSOR
+            config BSP_USING_TMR0_2B
+                bool "Use KEYSCAN"
+                select RT_USING_KEYSCAN
+                default n
+        endif
+endmenu
+
+menu "Board extended module Drivers"
+
+endmenu
+
+endmenu

bsp/hc32/ev_hc32f448_lqfp80/board/SConscript

@@ -0,0 +1,37 @@
+import os
+import rtconfig
+from building import *
+
+Import('SDK_LIB')
+
+cwd = GetCurrentDir()
+
+# add general drivers
+src = Split('''
+board.c
+board_config.c
+''')
+
+if GetDepend(['BSP_USING_TCA9539']):
+    src += Glob('ports/tca9539.c')
+
+if GetDepend(['BSP_USING_SPI_FLASH']):
+    src += Glob('ports/drv_spi_flash.c')
+
+path =  [cwd]
+path += [cwd + '/ports']
+path += [cwd + '/config']
+
+startup_path_prefix = SDK_LIB
+
+if rtconfig.PLATFORM in ['gcc']:
+    src += [startup_path_prefix + '/hc32f448_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/startup_hc32f448.S']
+elif rtconfig.PLATFORM in ['armcc', 'armclang']:
+    src += [startup_path_prefix + '/hc32f448_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/startup_hc32f448.s']
+elif rtconfig.PLATFORM in ['iccarm']:
+    src += [startup_path_prefix + '/hc32f448_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/startup_hc32f448.s']
+
+CPPDEFINES = ['HC32F448', '__DEBUG']
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+
+Return('group')

bsp/hc32/ev_hc32f448_lqfp80/board/board.c

@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-02-20     CDT          first version
+ */
+
+#include "board.h"
+#include "board_config.h"
+
+/* unlock/lock peripheral */
+#define EXAMPLE_PERIPH_WE               (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \
+                                         LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM)
+#define EXAMPLE_PERIPH_WP               (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM)
+
+/** System Base Configuration
+*/
+void SystemBase_Config(void)
+{
+#if defined(BSP_USING_ON_CHIP_FLASH_ICODE_CACHE)
+    EFM_ICacheCmd(ENABLE);
+#endif
+#if defined(BSP_USING_ON_CHIP_FLASH_DCODE_CACHE)
+    EFM_DCacheCmd(ENABLE);
+#endif
+#if defined(BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH)
+    EFM_PrefetchCmd(ENABLE);
+#endif
+}
+
+/** System Clock Configuration
+*/
+void SystemClock_Config(void)
+{
+    stc_clock_xtal_init_t stcXtalInit;
+    stc_clock_pll_init_t stcPLLHInit;
+#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
+    stc_clock_xtal32_init_t stcXtal32Init;
+#endif
+
+    /* PCLK0, HCLK Max 200MHz */
+    /* PCLK1, PCLK4 Max 100MHz */
+    /* PCLK2, EXCLK Max 60MHz */
+    /* PCLK3 Max 50MHz */
+    CLK_SetClockDiv(CLK_BUS_CLK_ALL,
+                    (CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | CLK_PCLK2_DIV4 |
+                     CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2 | CLK_EXCLK_DIV4 |
+                     CLK_HCLK_DIV1));
+
+    GPIO_AnalogCmd(XTAL_PORT, XTAL_IN_PIN | XTAL_OUT_PIN, ENABLE);
+    (void)CLK_XtalStructInit(&stcXtalInit);
+    /* Config Xtal and enable Xtal */
+    stcXtalInit.u8Mode   = CLK_XTAL_MD_OSC;
+    stcXtalInit.u8Drv    = CLK_XTAL_DRV_ULOW;
+    stcXtalInit.u8State  = CLK_XTAL_ON;
+    stcXtalInit.u8StableTime = CLK_XTAL_STB_2MS;
+    (void)CLK_XtalInit(&stcXtalInit);
+
+    (void)CLK_PLLStructInit(&stcPLLHInit);
+    /* VCO = (8/1)*100 = 800MHz*/
+    stcPLLHInit.u8PLLState = CLK_PLL_ON;
+    stcPLLHInit.PLLCFGR = 0UL;
+    stcPLLHInit.PLLCFGR_f.PLLM = 1UL - 1UL;
+    stcPLLHInit.PLLCFGR_f.PLLN = 100UL - 1UL;
+    stcPLLHInit.PLLCFGR_f.PLLP = 4UL - 1UL;
+    stcPLLHInit.PLLCFGR_f.PLLQ = 4UL - 1UL;
+    stcPLLHInit.PLLCFGR_f.PLLR = 4UL - 1UL;
+    stcPLLHInit.PLLCFGR_f.PLLSRC = CLK_PLL_SRC_XTAL;
+    (void)CLK_PLLInit(&stcPLLHInit);
+
+    /* 3 cycles for 150 ~ 200MHz */
+    (void)EFM_SetWaitCycle(EFM_WAIT_CYCLE3);
+    /* 3 cycles for 150 ~ 200MHz */
+    GPIO_SetReadWaitCycle(GPIO_RD_WAIT3);
+    CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL);
+
+#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
+    /* Xtal32 config */
+    GPIO_AnalogCmd(XTAL32_PORT, XTAL32_IN_PIN | XTAL32_OUT_PIN, ENABLE);
+    (void)CLK_Xtal32StructInit(&stcXtal32Init);
+    stcXtal32Init.u8State  = CLK_XTAL32_ON;
+    stcXtal32Init.u8Drv    = CLK_XTAL32_DRV_HIGH;
+    stcXtal32Init.u8Filter = CLK_XTAL32_FILTER_RUN_MD;
+    (void)CLK_Xtal32Init(&stcXtal32Init);
+#endif
+}
+
+/** Peripheral Clock Configuration
+*/
+void PeripheralClock_Config(void)
+{
+#if defined(BSP_USING_CAN1)
+    CLK_SetCANClockSrc(CLK_CAN1, CLK_CANCLK_SYSCLK_DIV6);
+#endif
+#if defined(BSP_USING_CAN2)
+    CLK_SetCANClockSrc(CLK_CAN2, CLK_CANCLK_SYSCLK_DIV6);
+#endif
+
+#if defined(RT_USING_ADC)
+    CLK_SetPeriClockSrc(CLK_PERIPHCLK_PCLK);
+#endif
+}
+
+/** Peripheral Registers Unlock
+*/
+void PeripheralRegister_Unlock(void)
+{
+    LL_PERIPH_WE(EXAMPLE_PERIPH_WE);
+}

bsp/hc32/ev_hc32f448_lqfp80/board/board.h

@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-02-20     CDT          first version
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include <rtthread.h>
+#include "hc32_ll.h"
+#include "drv_gpio.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#define HC32_FLASH_SIZE_GRANULARITY     (8 * 1024)
+#define HC32_FLASH_SIZE                 (256 * 1024)
+#define HC32_FLASH_START_ADDRESS        (0)
+#define HC32_FLASH_END_ADDRESS          (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE)
+
+#define HC32_SRAM_SIZE                  (64)
+#define HC32_SRAM_END                   (0x1FFF8000 + HC32_SRAM_SIZE * 1024)
+
+#ifdef __ARMCC_VERSION
+extern int Image$$RW_IRAM2$$ZI$$Limit;
+#define HEAP_BEGIN                      (&Image$$RW_IRAM2$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="HEAP"
+#define HEAP_BEGIN                      (__segment_end("HEAP"))
+#else
+extern int __bss_end;
+#define HEAP_BEGIN                      (&__bss_end)
+#endif
+
+#define HEAP_END                        HC32_SRAM_END
+
+void PeripheralRegister_Unlock(void);
+void PeripheralClock_Config(void);
+void SystemBase_Config(void);
+void SystemClock_Config(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/hc32/ev_hc32f448_lqfp80/board/board_config.c

@@ -0,0 +1,497 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-02-20     CDT          first version
+ */
+
+#include <rtdevice.h>
+#include "board_config.h"
+#include "tca9539.h"
+
+/**
+ * The below functions will initialize HC32 board.
+ */
+
+#if defined RT_USING_SERIAL
+rt_err_t rt_hw_board_uart_init(CM_USART_TypeDef *USARTx)
+{
+    rt_err_t result = RT_EOK;
+
+    switch ((rt_uint32_t)USARTx)
+    {
+#if defined(BSP_USING_UART1)
+    case (rt_uint32_t)CM_USART1:
+        /* Configure USART RX/TX pin. */
+        GPIO_SetFunc(USART1_RX_PORT, USART1_RX_PIN, USART1_RX_FUNC);
+        GPIO_SetFunc(USART1_TX_PORT, USART1_TX_PIN, USART1_TX_FUNC);
+        break;
+#endif
+#if defined(BSP_USING_UART2)
+    case (rt_uint32_t)CM_USART2:
+        /* Configure USART RX/TX pin. */
+        GPIO_SetFunc(USART2_RX_PORT, USART2_RX_PIN, USART2_RX_FUNC);
+        GPIO_SetFunc(USART2_TX_PORT, USART2_TX_PIN, USART2_TX_FUNC);
+        break;
+#endif
+#if defined(BSP_USING_UART6)
+    case (rt_uint32_t)CM_USART6:
+        /* Configure USART RX/TX pin. */
+        GPIO_SetFunc(USART6_RX_PORT, USART6_RX_PIN, USART6_RX_FUNC);
+        GPIO_SetFunc(USART6_TX_PORT, USART6_TX_PIN, USART6_TX_FUNC);
+        break;
+#endif
+    default:
+        result = -RT_ERROR;
+        break;
+    }
+
+    return result;
+}
+#endif
+
+#if defined(RT_USING_I2C)
+rt_err_t rt_hw_board_i2c_init(CM_I2C_TypeDef *I2Cx)
+{
+    rt_err_t result = RT_EOK;
+    stc_gpio_init_t stcGpioInit;
+    (void)GPIO_StructInit(&stcGpioInit);
+
+    switch ((rt_uint32_t)I2Cx)
+    {
+#if defined(BSP_USING_I2C1)
+    case (rt_uint32_t)CM_I2C1:
+        /* Configure I2C1 SDA/SCL pin. */
+        GPIO_SetFunc(I2C1_SDA_PORT, I2C1_SDA_PIN, I2C1_SDA_FUNC);
+        GPIO_SetFunc(I2C1_SCL_PORT, I2C1_SCL_PIN, I2C1_SCL_FUNC);
+        break;
+#endif
+#if defined(BSP_USING_I2C2) // TODO, ch2 for test only
+    case (rt_uint32_t)CM_I2C2:
+        /* Configure I2C2 SDA/SCL pin. */
+        GPIO_SetFunc(I2C2_SDA_PORT, I2C2_SDA_PIN, I2C2_SDA_FUNC);
+        GPIO_SetFunc(I2C2_SCL_PORT, I2C2_SCL_PIN, I2C2_SCL_FUNC);
+        break;
+#endif
+    default:
+        result = -RT_ERROR;
+        break;
+    }
+    return result;
+}
+#endif
+
+#if defined(RT_USING_ADC)
+rt_err_t rt_hw_board_adc_init(CM_ADC_TypeDef *ADCx)
+{
+    rt_err_t result = RT_EOK;
+    stc_gpio_init_t stcGpioInit;
+
+    (void)GPIO_StructInit(&stcGpioInit);
+    stcGpioInit.u16PinAttr = PIN_ATTR_ANALOG;
+    switch ((rt_uint32_t)ADCx)
+    {
+#if defined(BSP_USING_ADC1)
+    case (rt_uint32_t)CM_ADC1:
+        (void)GPIO_Init(ADC1_CH_PORT, ADC1_CH_PIN, &stcGpioInit);
+        break;
+#endif
+#if defined(BSP_USING_ADC2)
+    case (rt_uint32_t)CM_ADC2:
+        (void)GPIO_Init(ADC2_CH_PORT, ADC2_CH_PIN, &stcGpioInit);
+        break;
+#endif
+#if defined(BSP_USING_ADC3)
+    case (rt_uint32_t)CM_ADC3:
+        (void)GPIO_Init(ADC3_CH_PORT, ADC3_CH_PIN, &stcGpioInit);
+        break;
+#endif
+    default:
+        result = -RT_ERROR;
+        break;
+    }
+
+    return result;
+}
+#endif
+
+#if defined(RT_USING_DAC)
+rt_err_t rt_hw_board_dac_init(CM_DAC_TypeDef *DACx)
+{
+    rt_err_t result = RT_EOK;
+    stc_gpio_init_t stcGpioInit;
+
+    (void)GPIO_StructInit(&stcGpioInit);
+    stcGpioInit.u16PinAttr = PIN_ATTR_ANALOG;
+    switch ((rt_uint32_t)DACx)
+    {
+#if defined(BSP_USING_DAC1)
+    case (rt_uint32_t)CM_DAC1:
+        (void)GPIO_Init(DAC1_CH1_PORT, DAC1_CH1_PIN, &stcGpioInit);
+        (void)GPIO_Init(DAC1_CH2_PORT, DAC1_CH2_PIN, &stcGpioInit);
+        break;
+#endif
+    default:
+        result = -RT_ERROR;
+        break;
+    }
+
+    return result;
+}
+#endif
+
+#if defined(RT_USING_CAN)
+void CanPhyEnable(void)
+{
+#if defined(BSP_USING_CAN1)
+    TCA9539_WritePin(CAN1_STB_PORT, CAN1_STB_PIN, TCA9539_PIN_RESET);
+    TCA9539_ConfigPin(CAN1_STB_PORT, CAN1_STB_PIN, TCA9539_DIR_OUT);
+#endif
+#if defined(BSP_USING_CAN2)
+    TCA9539_WritePin(CAN2_STB_PORT, CAN2_STB_PIN, TCA9539_PIN_RESET);
+    TCA9539_ConfigPin(CAN2_STB_PORT, CAN2_STB_PIN, TCA9539_DIR_OUT);
+#endif
+}
+rt_err_t rt_hw_board_can_init(CM_CAN_TypeDef *CANx)
+{
+    rt_err_t result = RT_EOK;
+
+    switch ((rt_uint32_t)CANx)
+    {
+#if defined(BSP_USING_CAN1)
+    case (rt_uint32_t)CM_CAN1:
+        GPIO_SetFunc(CAN1_TX_PORT, CAN1_TX_PIN, CAN1_TX_PIN_FUNC);
+        GPIO_SetFunc(CAN1_RX_PORT, CAN1_RX_PIN, CAN1_RX_PIN_FUNC);
+        break;
+#endif
+#if defined(BSP_USING_CAN2)
+    case (rt_uint32_t)CM_CAN2:
+        GPIO_SetFunc(CAN2_TX_PORT, CAN2_TX_PIN, CAN2_TX_PIN_FUNC);
+        GPIO_SetFunc(CAN2_RX_PORT, CAN2_RX_PIN, CAN2_RX_PIN_FUNC);
+        break;
+#endif
+    default:
+        result = -RT_ERROR;
+        break;
+    }
+
+    return result;
+}
+#endif
+
+
+#if defined (RT_USING_SPI)
+rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx)
+{
+    rt_err_t result = RT_EOK;
+#if defined(BSP_USING_SPI1)
+    stc_gpio_init_t stcGpioInit;
+#endif
+
+    switch ((rt_uint32_t)CM_SPIx)
+    {
+#if defined(BSP_USING_SPI1)
+    case (rt_uint32_t)CM_SPI1:
+        GPIO_StructInit(&stcGpioInit);
+        stcGpioInit.u16PinState = PIN_STAT_SET;
+        stcGpioInit.u16PinDir   = PIN_DIR_OUT;
+        GPIO_Init(SPI1_WP_PORT, SPI1_WP_PIN, &stcGpioInit);
+        GPIO_Init(SPI1_HOLD_PORT, SPI1_HOLD_PIN, &stcGpioInit);
+
+        (void)GPIO_StructInit(&stcGpioInit);
+        stcGpioInit.u16PinDrv = PIN_HIGH_DRV;
+        stcGpioInit.u16PinInputType = PIN_IN_TYPE_CMOS;
+        (void)GPIO_Init(SPI1_SCK_PORT,  SPI1_SCK_PIN,  &stcGpioInit);
+        (void)GPIO_Init(SPI1_MOSI_PORT, SPI1_MOSI_PIN, &stcGpioInit);
+        (void)GPIO_Init(SPI1_MISO_PORT, SPI1_MISO_PIN, &stcGpioInit);
+        GPIO_SetFunc(SPI1_SCK_PORT,  SPI1_SCK_PIN,  SPI1_SCK_FUNC);
+        GPIO_SetFunc(SPI1_MOSI_PORT, SPI1_MOSI_PIN, SPI1_MOSI_FUNC);
+        GPIO_SetFunc(SPI1_MISO_PORT, SPI1_MISO_PIN, SPI1_MISO_FUNC);
+        break;
+#endif
+    default:
+        result = -RT_ERROR;
+        break;
+    }
+
+    return result;
+}
+#endif
+
+#if defined(RT_USING_PWM)
+#if defined(BSP_USING_PWM_TMRA)
+rt_err_t rt_hw_board_pwm_tmra_init(CM_TMRA_TypeDef *TMRAx)
+{
+    rt_err_t result = RT_EOK;
+    switch ((rt_uint32_t)TMRAx)
+    {
+#if defined(BSP_USING_PWM_TMRA_1)
+    case (rt_uint32_t)CM_TMRA_1:
+#ifdef BSP_USING_PWM_TMRA_1_CH1
+        GPIO_SetFunc(PWM_TMRA_1_CH1_PORT, PWM_TMRA_1_CH1_PIN, PWM_TMRA_1_CH1_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMRA_1_CH2
+        GPIO_SetFunc(PWM_TMRA_1_CH2_PORT, PWM_TMRA_1_CH2_PIN, PWM_TMRA_1_CH2_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMRA_1_CH3
+        GPIO_SetFunc(PWM_TMRA_1_CH3_PORT, PWM_TMRA_1_CH3_PIN, PWM_TMRA_1_CH3_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMRA_1_CH4
+        GPIO_SetFunc(PWM_TMRA_1_CH4_PORT, PWM_TMRA_1_CH4_PIN, PWM_TMRA_1_CH4_PIN_FUNC);
+#endif
+        break;
+#endif
+#if defined(BSP_USING_PWM_TMRA_2)
+    case (rt_uint32_t)CM_TMRA_2:
+#ifdef BSP_USING_PWM_TMRA_2_CH1
+        GPIO_SetFunc(PWM_TMRA_2_CH1_PORT, PWM_TMRA_2_CH1_PIN, PWM_TMRA_2_CH1_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMRA_2_CH2
+        GPIO_SetFunc(PWM_TMRA_2_CH2_PORT, PWM_TMRA_2_CH2_PIN, PWM_TMRA_2_CH2_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMRA_2_CH3
+        GPIO_SetFunc(PWM_TMRA_2_CH3_PORT, PWM_TMRA_2_CH3_PIN, PWM_TMRA_2_CH3_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMRA_2_CH4
+        GPIO_SetFunc(PWM_TMRA_2_CH4_PORT, PWM_TMRA_2_CH4_PIN, PWM_TMRA_2_CH4_PIN_FUNC);
+#endif
+        break;
+#endif
+    default:
+        result = -RT_ERROR;
+        break;
+    }
+
+    return result;
+}
+#endif
+
+#if defined(BSP_USING_PWM_TMR4)
+rt_err_t rt_hw_board_pwm_tmr4_init(CM_TMR4_TypeDef *TMR4x)
+{
+    rt_err_t result = RT_EOK;
+    switch ((rt_uint32_t)TMR4x)
+    {
+#if defined(BSP_USING_PWM_TMR4_1)
+    case (rt_uint32_t)CM_TMR4_1:
+#ifdef BSP_USING_PWM_TMR4_1_OUH
+        GPIO_SetFunc(PWM_TMR4_1_OUH_PORT, PWM_TMR4_1_OUH_PIN, PWM_TMR4_1_OUH_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMR4_1_OUL
+        GPIO_SetFunc(PWM_TMR4_1_OUL_PORT, PWM_TMR4_1_OUL_PIN, PWM_TMR4_1_OUL_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMR4_1_OVH
+        GPIO_SetFunc(PWM_TMR4_1_OVH_PORT, PWM_TMR4_1_OVH_PIN, PWM_TMR4_1_OVH_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMR4_1_OVL
+        GPIO_SetFunc(PWM_TMR4_1_OVL_PORT, PWM_TMR4_1_OVL_PIN, PWM_TMR4_1_OVL_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMR4_1_OWH
+        GPIO_SetFunc(PWM_TMR4_1_OWH_PORT, PWM_TMR4_1_OWH_PIN, PWM_TMR4_1_OWH_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMR4_1_OWL
+        GPIO_SetFunc(PWM_TMR4_1_OWL_PORT, PWM_TMR4_1_OWL_PIN, PWM_TMR4_1_OWL_PIN_FUNC);
+#endif
+        break;
+#endif
+    default:
+        result = -RT_ERROR;
+        break;
+    }
+    return result;
+}
+#endif
+
+#if defined(BSP_USING_PWM_TMR6)
+rt_err_t rt_hw_board_pwm_tmr6_init(CM_TMR6_TypeDef *TMR6x)
+{
+    rt_err_t result = RT_EOK;
+    switch ((rt_uint32_t)TMR6x)
+    {
+#if defined(BSP_USING_PWM_TMR6_1)
+    case (rt_uint32_t)CM_TMR6_1:
+#ifdef BSP_USING_PWM_TMR6_1_A
+        GPIO_SetFunc(PWM_TMR6_1_A_PORT, PWM_TMR6_1_A_PIN, PWM_TMR6_1_A_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMR6_1_B
+        GPIO_SetFunc(PWM_TMR6_1_B_PORT, PWM_TMR6_1_B_PIN, PWM_TMR6_1_B_PIN_FUNC);
+#endif
+        break;
+#endif
+    default:
+        result = -RT_ERROR;
+        break;
+    }
+
+    return result;
+}
+#endif
+#endif
+
+#ifdef RT_USING_PM
+#define EFM_ERASE_TIME_MAX_IN_MILLISECOND                   (20)
+#define PLL_SRC                                             ((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLSRC) >> CMU_PLLHCFGR_PLLSRC_POS)
+
+static void _pm_sleep_common_init(rt_bool_t b_disable_unused_clk)
+{
+    CLK_Xtal32Cmd(ENABLE);
+
+    rt_tick_t tick_start = rt_tick_get_millisecond();
+    rt_err_t rt_stat = RT_EOK;
+    //wait flash idle
+    while (SET != EFM_GetStatus(EFM_FLAG_RDY))
+    {
+        if (rt_tick_get_millisecond() - tick_start > EFM_ERASE_TIME_MAX_IN_MILLISECOND)
+        {
+            rt_stat = RT_ERROR;
+            break;
+        }
+    }
+    RT_ASSERT(rt_stat == RT_EOK);
+
+    if (b_disable_unused_clk)
+    {
+        uint32_t cur_clk_src = READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW);
+
+        switch (cur_clk_src)
+        {
+        case CLK_SYSCLK_SRC_HRC:
+            CLK_PLLCmd(DISABLE);
+            CLK_MrcCmd(DISABLE);
+            CLK_LrcCmd(DISABLE);
+            CLK_XtalCmd(DISABLE);
+            PWC_LDO_Cmd(PWC_LDO_PLL, DISABLE);
+            break;
+        case CLK_SYSCLK_SRC_MRC:
+            CLK_PLLCmd(DISABLE);
+            CLK_HrcCmd(DISABLE);
+            CLK_LrcCmd(DISABLE);
+            CLK_XtalCmd(DISABLE);
+            PWC_LDO_Cmd(PWC_LDO_PLL | PWC_LDO_HRC, DISABLE);
+
+            break;
+        case CLK_SYSCLK_SRC_XTAL:
+            CLK_PLLCmd(DISABLE);
+            CLK_HrcCmd(DISABLE);
+            CLK_MrcCmd(DISABLE);
+            CLK_LrcCmd(DISABLE);
+            PWC_LDO_Cmd(PWC_LDO_PLL | PWC_LDO_HRC, DISABLE);
+
+            break;
+        case CLK_SYSCLK_SRC_XTAL32:
+            CLK_PLLCmd(DISABLE);
+            CLK_HrcCmd(DISABLE);
+            CLK_MrcCmd(DISABLE);
+            CLK_LrcCmd(DISABLE);
+            CLK_XtalCmd(DISABLE);
+            PWC_LDO_Cmd(PWC_LDO_PLL | PWC_LDO_HRC, DISABLE);
+
+            break;
+        case CLK_SYSCLK_SRC_PLL:
+            if (CLK_PLL_SRC_XTAL == PLL_SRC)
+            {
+                CLK_HrcCmd(DISABLE);
+            }
+            else
+            {
+                CLK_XtalCmd(DISABLE);
+            }
+            CLK_MrcCmd(DISABLE);
+            CLK_LrcCmd(DISABLE);
+            PWC_LDO_Cmd(PWC_LDO_HRC, DISABLE);
+
+            break;
+        default:
+            break;
+        }
+    }
+}
+
+void rt_hw_board_pm_sleep_deep_init(void)
+{
+#if (PM_SLEEP_DEEP_CFG_CLK   == PWC_STOP_CLK_KEEP)
+    _pm_sleep_common_init(RT_TRUE);
+#else
+    _pm_sleep_common_init(RT_FALSE);
+    CLK_PLLCmd(DISABLE);
+    CLK_HrcCmd(DISABLE);
+    CLK_LrcCmd(DISABLE);
+    CLK_XtalCmd(DISABLE);
+    PWC_LDO_Cmd(PWC_LDO_PLL | PWC_LDO_HRC, DISABLE);
+#endif
+}
+
+void rt_hw_board_pm_sleep_shutdown_init(void)
+{
+    _pm_sleep_common_init(RT_TRUE);
+}
+
+void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode)
+{
+    switch (run_mode)
+    {
+    case PM_RUN_MODE_HIGH_SPEED:
+    case PM_RUN_MODE_NORMAL_SPEED:
+        SystemClock_Config();
+        break;
+
+    case PM_RUN_MODE_LOW_SPEED:
+        CLK_SetSysClockSrc(CLK_SYSCLK_SRC_XTAL);
+
+    default:
+        break;
+    }
+}
+#endif
+
+#if defined(BSP_USING_QSPI)
+rt_err_t rt_hw_qspi_board_init(void)
+{
+    stc_gpio_init_t stcGpioInit;
+
+    (void)GPIO_StructInit(&stcGpioInit);
+    stcGpioInit.u16PinDrv = PIN_HIGH_DRV;
+#ifndef BSP_QSPI_USING_SOFT_CS
+    (void)GPIO_Init(QSPI_FLASH_CS_PORT,  QSPI_FLASH_CS_PIN,  &stcGpioInit);
+    GPIO_SetFunc(QSPI_FLASH_CS_PORT,  QSPI_FLASH_CS_PIN,  QSPI_FLASH_CS_FUNC);
+#endif
+    (void)GPIO_Init(QSPI_FLASH_SCK_PORT, QSPI_FLASH_SCK_PIN, &stcGpioInit);
+    (void)GPIO_Init(QSPI_FLASH_IO0_PORT, QSPI_FLASH_IO0_PIN, &stcGpioInit);
+    (void)GPIO_Init(QSPI_FLASH_IO1_PORT, QSPI_FLASH_IO1_PIN, &stcGpioInit);
+    (void)GPIO_Init(QSPI_FLASH_IO2_PORT, QSPI_FLASH_IO2_PIN, &stcGpioInit);
+    (void)GPIO_Init(QSPI_FLASH_IO3_PORT, QSPI_FLASH_IO3_PIN, &stcGpioInit);
+    GPIO_SetFunc(QSPI_FLASH_SCK_PORT, QSPI_FLASH_SCK_PIN, QSPI_FLASH_SCK_FUNC);
+    GPIO_SetFunc(QSPI_FLASH_IO0_PORT, QSPI_FLASH_IO0_PIN, QSPI_FLASH_IO0_FUNC);
+    GPIO_SetFunc(QSPI_FLASH_IO1_PORT, QSPI_FLASH_IO1_PIN, QSPI_FLASH_IO1_FUNC);
+    GPIO_SetFunc(QSPI_FLASH_IO2_PORT, QSPI_FLASH_IO2_PIN, QSPI_FLASH_IO2_FUNC);
+    GPIO_SetFunc(QSPI_FLASH_IO3_PORT, QSPI_FLASH_IO3_PIN, QSPI_FLASH_IO3_FUNC);
+
+    return RT_EOK;
+}
+#endif
+
+#if defined(BSP_USING_TMRA_PULSE_ENCODER)
+rt_err_t rt_hw_board_pulse_encoder_tmra_init(void)
+{
+#if defined(BSP_USING_PULSE_ENCODER_TMRA_1)
+    GPIO_SetFunc(PULSE_ENCODER_TMRA_1_A_PORT, PULSE_ENCODER_TMRA_1_A_PIN, PULSE_ENCODER_TMRA_1_A_PIN_FUNC);
+    GPIO_SetFunc(PULSE_ENCODER_TMRA_1_B_PORT, PULSE_ENCODER_TMRA_1_B_PIN, PULSE_ENCODER_TMRA_1_B_PIN_FUNC);
+#endif
+    return RT_EOK;
+}
+#endif
+
+#if defined(BSP_USING_TMR6_PULSE_ENCODER)
+rt_err_t rt_hw_board_pulse_encoder_tmr6_init(void)
+{
+#if defined(BSP_USING_PULSE_ENCODER_TMR6_1)
+    GPIO_SetFunc(PULSE_ENCODER_TMR6_1_A_PORT, PULSE_ENCODER_TMR6_1_A_PIN, PULSE_ENCODER_TMR6_1_A_PIN_FUNC);
+    GPIO_SetFunc(PULSE_ENCODER_TMR6_1_B_PORT, PULSE_ENCODER_TMR6_1_B_PIN, PULSE_ENCODER_TMR6_1_B_PIN_FUNC);
+#endif
+    return RT_EOK;
+}
+#endif

bsp/hc32/ev_hc32f448_lqfp80/board/board_config.h

@@ -0,0 +1,310 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-02-20     CDT          first version
+ */
+
+
+#ifndef __BOARD_CONFIG_H__
+#define __BOARD_CONFIG_H__
+
+#include <rtconfig.h>
+#include "hc32_ll.h"
+#include "drv_config.h"
+
+
+/************************* XTAL port **********************/
+#define XTAL_PORT                       (GPIO_PORT_H)
+#define XTAL_IN_PIN                     (GPIO_PIN_00)
+#define XTAL_OUT_PIN                    (GPIO_PIN_01)
+
+/************************ USART port **********************/
+#if defined(BSP_USING_UART1)
+    #define USART1_RX_PORT                  (GPIO_PORT_A)
+    #define USART1_RX_PIN                   (GPIO_PIN_10)
+    #define USART1_RX_FUNC                  (GPIO_FUNC_33)
+
+    #define USART1_TX_PORT                  (GPIO_PORT_A)
+    #define USART1_TX_PIN                   (GPIO_PIN_09)
+    #define USART1_TX_FUNC                  (GPIO_FUNC_32)
+#endif
+
+#if defined(BSP_USING_UART2)
+    #define USART2_RX_PORT                  (GPIO_PORT_C)
+    #define USART2_RX_PIN                   (GPIO_PIN_11)
+    #define USART2_RX_FUNC                  (GPIO_FUNC_37)
+
+    #define USART2_TX_PORT                  (GPIO_PORT_C)
+    #define USART2_TX_PIN                   (GPIO_PIN_10)
+    #define USART2_TX_FUNC                  (GPIO_FUNC_36)
+#endif
+
+#if defined(BSP_USING_UART6)
+    #define USART6_RX_PORT                  (GPIO_PORT_D)
+    #define USART6_RX_PIN                   (GPIO_PIN_01)
+    #define USART6_RX_FUNC                  (GPIO_FUNC_55)
+
+    #define USART6_TX_PORT                  (GPIO_PORT_D)
+    #define USART6_TX_PIN                   (GPIO_PIN_02)
+    #define USART6_TX_FUNC                  (GPIO_FUNC_54)
+#endif
+
+/************************ I2C port **********************/
+#if defined(BSP_USING_I2C1)
+    #define I2C1_SDA_PORT                   (GPIO_PORT_E)
+    #define I2C1_SDA_PIN                    (GPIO_PIN_00)
+    #define I2C1_SDA_FUNC                   (GPIO_FUNC_48)
+
+    #define I2C1_SCL_PORT                   (GPIO_PORT_E)
+    #define I2C1_SCL_PIN                    (GPIO_PIN_01)
+    #define I2C1_SCL_FUNC                   (GPIO_FUNC_49)
+#endif
+
+#if defined(BSP_USING_I2C2) // TODO, ch2 for test only
+    #define I2C2_SDA_PORT                   (GPIO_PORT_A)
+    #define I2C2_SDA_PIN                    (GPIO_PIN_09)
+    #define I2C2_SDA_FUNC                   (GPIO_FUNC_50)
+
+    #define I2C2_SCL_PORT                   (GPIO_PORT_A)
+    #define I2C2_SCL_PIN                    (GPIO_PIN_10)
+    #define I2C2_SCL_FUNC                   (GPIO_FUNC_51)
+#endif
+
+
+/***********  ADC configure *********/
+#if defined(BSP_USING_ADC1)
+    #define ADC1_CH_PORT                    (GPIO_PORT_C)
+    #define ADC1_CH_PIN                     (GPIO_PIN_00)
+#endif
+
+#if defined(BSP_USING_ADC2)
+    #define ADC2_CH_PORT                    (GPIO_PORT_C)
+    #define ADC2_CH_PIN                     (GPIO_PIN_01)
+#endif
+
+#if defined(BSP_USING_ADC3)
+    #define ADC3_CH_PORT                    (GPIO_PORT_E)
+    #define ADC3_CH_PIN                     (GPIO_PIN_03)
+#endif
+
+/***********  DAC configure *********/
+#if defined(BSP_USING_DAC1)
+    #define DAC1_CH1_PORT                   (GPIO_PORT_A)
+    #define DAC1_CH1_PIN                    (GPIO_PIN_04)
+    #define DAC1_CH2_PORT                   (GPIO_PORT_A)
+    #define DAC1_CH2_PIN                    (GPIO_PIN_05)
+#endif
+
+/***********  CAN configure *********/
+#if defined(BSP_USING_CAN1)
+    #define CAN1_TX_PORT                    (GPIO_PORT_C)
+    #define CAN1_TX_PIN                     (GPIO_PIN_12)
+    #define CAN1_TX_PIN_FUNC                (GPIO_FUNC_56)
+
+    #define CAN1_RX_PORT                    (GPIO_PORT_D)
+    #define CAN1_RX_PIN                     (GPIO_PIN_00)
+    #define CAN1_RX_PIN_FUNC                (GPIO_FUNC_57)
+#endif
+
+#if defined(BSP_USING_CAN2)
+    #define CAN2_TX_PORT                    (GPIO_PORT_H)
+    #define CAN2_TX_PIN                     (GPIO_PIN_02)
+    #define CAN2_TX_PIN_FUNC                (GPIO_FUNC_56)
+
+    #define CAN2_RX_PORT                    (GPIO_PORT_E)
+    #define CAN2_RX_PIN                     (GPIO_PIN_04)
+    #define CAN2_RX_PIN_FUNC                (GPIO_FUNC_57)
+#endif
+
+/************************* SPI port ***********************/
+#if defined(BSP_USING_SPI1)
+    #define SPI1_CS_PORT                (GPIO_PORT_C)
+    #define SPI1_CS_PIN                 (GPIO_PIN_07)
+
+    #define SPI1_SCK_PORT               (GPIO_PORT_B)
+    #define SPI1_SCK_PIN                (GPIO_PIN_14)
+    #define SPI1_SCK_FUNC               (GPIO_FUNC_47)
+
+    #define SPI1_MOSI_PORT              (GPIO_PORT_B)
+    #define SPI1_MOSI_PIN               (GPIO_PIN_13)
+    #define SPI1_MOSI_FUNC              (GPIO_FUNC_44)
+
+    #define SPI1_MISO_PORT              (GPIO_PORT_D)
+    #define SPI1_MISO_PIN               (GPIO_PIN_09)
+    #define SPI1_MISO_FUNC              (GPIO_FUNC_45)
+
+    #define SPI1_WP_PORT                (GPIO_PORT_D)
+    #define SPI1_WP_PIN                 (GPIO_PIN_10)
+
+    #define SPI1_HOLD_PORT              (GPIO_PORT_D)
+    #define SPI1_HOLD_PIN               (GPIO_PIN_11)
+#endif
+
+/************************ RTC/PM *****************************/
+#if defined(BSP_USING_RTC) || defined(RT_USING_PM)
+    #if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
+        #define XTAL32_PORT                     (GPIO_PORT_C)
+        #define XTAL32_IN_PIN                   (GPIO_PIN_14)
+        #define XTAL32_OUT_PIN                  (GPIO_PIN_15)
+    #endif
+#endif
+
+#if defined(RT_USING_PWM)
+    /***********  PWM_TMRA configure *********/
+    #if defined(BSP_USING_PWM_TMRA_1)
+        #if defined(BSP_USING_PWM_TMRA_1_CH1)
+            #define PWM_TMRA_1_CH1_PORT             (GPIO_PORT_A)
+            #define PWM_TMRA_1_CH1_PIN              (GPIO_PIN_08)
+            #define PWM_TMRA_1_CH1_PIN_FUNC         (GPIO_FUNC_4)
+        #endif
+        #if defined(BSP_USING_PWM_TMRA_1_CH2)
+            #define PWM_TMRA_1_CH2_PORT             (GPIO_PORT_A)
+            #define PWM_TMRA_1_CH2_PIN              (GPIO_PIN_09)
+            #define PWM_TMRA_1_CH2_PIN_FUNC         (GPIO_FUNC_4)
+        #endif
+        #if defined(BSP_USING_PWM_TMRA_1_CH3)
+            #define PWM_TMRA_1_CH3_PORT             (GPIO_PORT_A)
+            #define PWM_TMRA_1_CH3_PIN              (GPIO_PIN_10)
+            #define PWM_TMRA_1_CH3_PIN_FUNC         (GPIO_FUNC_4)
+        #endif
+        #if defined(BSP_USING_PWM_TMRA_1_CH4)
+            #define PWM_TMRA_1_CH4_PORT             (GPIO_PORT_A)
+            #define PWM_TMRA_1_CH4_PIN              (GPIO_PIN_11)
+            #define PWM_TMRA_1_CH4_PIN_FUNC         (GPIO_FUNC_4)
+        #endif
+    #endif
+
+    #if defined(BSP_USING_PWM_TMRA_2)
+        #if defined(BSP_USING_PWM_TMRA_2_CH1)
+            #define PWM_TMRA_2_CH1_PORT             (GPIO_PORT_A)
+            #define PWM_TMRA_2_CH1_PIN              (GPIO_PIN_00)
+            #define PWM_TMRA_2_CH1_PIN_FUNC         (GPIO_FUNC_4)
+        #endif
+        #if defined(BSP_USING_PWM_TMRA_2_CH2)
+            #define PWM_TMRA_2_CH2_PORT             (GPIO_PORT_A)
+            #define PWM_TMRA_2_CH2_PIN              (GPIO_PIN_01)
+            #define PWM_TMRA_2_CH2_PIN_FUNC         (GPIO_FUNC_4)
+        #endif
+        #if defined(BSP_USING_PWM_TMRA_2_CH3)
+            #define PWM_TMRA_2_CH3_PORT             (GPIO_PORT_A)
+            #define PWM_TMRA_2_CH3_PIN              (GPIO_PIN_02)
+            #define PWM_TMRA_2_CH3_PIN_FUNC         (GPIO_FUNC_4)
+        #endif
+        #if defined(BSP_USING_PWM_TMRA_2_CH4)
+            #define PWM_TMRA_2_CH4_PORT             (GPIO_PORT_A)
+            #define PWM_TMRA_2_CH4_PIN              (GPIO_PIN_03)
+            #define PWM_TMRA_2_CH4_PIN_FUNC         (GPIO_FUNC_4)
+        #endif
+    #endif
+
+    /***********  PWM_TMR4 configure *********/
+    #if defined(BSP_USING_PWM_TMR4_1)
+        #if defined(BSP_USING_PWM_TMR4_1_OUH)
+            #define PWM_TMR4_1_OUH_PORT             (GPIO_PORT_A)
+            #define PWM_TMR4_1_OUH_PIN              (GPIO_PIN_08)
+            #define PWM_TMR4_1_OUH_PIN_FUNC         (GPIO_FUNC_2)
+        #endif
+        #if defined(BSP_USING_PWM_TMR4_1_OUL)
+            #define PWM_TMR4_1_OUL_PORT             (GPIO_PORT_A)
+            #define PWM_TMR4_1_OUL_PIN              (GPIO_PIN_07)
+            #define PWM_TMR4_1_OUL_PIN_FUNC         (GPIO_FUNC_2)
+        #endif
+        #if defined(BSP_USING_PWM_TMR4_1_OVH)
+            #define PWM_TMR4_1_OVH_PORT             (GPIO_PORT_A)
+            #define PWM_TMR4_1_OVH_PIN              (GPIO_PIN_09)
+            #define PWM_TMR4_1_OVH_PIN_FUNC         (GPIO_FUNC_2)
+        #endif
+        #if defined(BSP_USING_PWM_TMR4_1_OVL)
+            #define PWM_TMR4_1_OVL_PORT             (GPIO_PORT_B)
+            #define PWM_TMR4_1_OVL_PIN              (GPIO_PIN_00)
+            #define PWM_TMR4_1_OVL_PIN_FUNC         (GPIO_FUNC_2)
+        #endif
+        #if defined(BSP_USING_PWM_TMR4_1_OWH)
+            #define PWM_TMR4_1_OWH_PORT             (GPIO_PORT_A)
+            #define PWM_TMR4_1_OWH_PIN              (GPIO_PIN_10)
+            #define PWM_TMR4_1_OWH_PIN_FUNC         (GPIO_FUNC_2)
+        #endif
+        #if defined(BSP_USING_PWM_TMR4_1_OWL)
+            #define PWM_TMR4_1_OWL_PORT             (GPIO_PORT_B)
+            #define PWM_TMR4_1_OWL_PIN              (GPIO_PIN_01)
+            #define PWM_TMR4_1_OWL_PIN_FUNC         (GPIO_FUNC_2)
+        #endif
+    #endif
+
+    /***********  PWM_TMR6 configure *********/
+    #if defined(BSP_USING_PWM_TMR6_1)
+        #if defined(BSP_USING_PWM_TMR6_1_A)
+            #define PWM_TMR6_1_A_PORT               (GPIO_PORT_A)
+            #define PWM_TMR6_1_A_PIN                (GPIO_PIN_08)
+            #define PWM_TMR6_1_A_PIN_FUNC           (GPIO_FUNC_3)
+        #endif
+        #if defined(BSP_USING_PWM_TMR6_1_B)
+            #define PWM_TMR6_1_B_PORT               (GPIO_PORT_A)
+            #define PWM_TMR6_1_B_PIN                (GPIO_PIN_07)
+            #define PWM_TMR6_1_B_PIN_FUNC           (GPIO_FUNC_3)
+        #endif
+    #endif
+
+#endif
+
+#if defined(BSP_USING_QSPI)
+    #ifndef BSP_QSPI_USING_SOFT_CS
+        /* QSSN */
+        #define QSPI_FLASH_CS_PORT              (GPIO_PORT_C)
+        #define QSPI_FLASH_CS_PIN               (GPIO_PIN_07)
+        #define QSPI_FLASH_CS_FUNC              (GPIO_FUNC_7)
+    #endif
+    /* QSCK */
+    #define QSPI_FLASH_SCK_PORT             (GPIO_PORT_B)
+    #define QSPI_FLASH_SCK_PIN              (GPIO_PIN_14)
+    #define QSPI_FLASH_SCK_FUNC             (GPIO_FUNC_7)
+    /* QSIO0 */
+    #define QSPI_FLASH_IO0_PORT             (GPIO_PORT_B)
+    #define QSPI_FLASH_IO0_PIN              (GPIO_PIN_13)
+    #define QSPI_FLASH_IO0_FUNC             (GPIO_FUNC_7)
+    /* QSIO1 */
+    #define QSPI_FLASH_IO1_PORT             (GPIO_PORT_D)
+    #define QSPI_FLASH_IO1_PIN              (GPIO_PIN_09)
+    #define QSPI_FLASH_IO1_FUNC             (GPIO_FUNC_7)
+    /* QSIO2 */
+    #define QSPI_FLASH_IO2_PORT             (GPIO_PORT_D)
+    #define QSPI_FLASH_IO2_PIN              (GPIO_PIN_10)
+    #define QSPI_FLASH_IO2_FUNC             (GPIO_FUNC_7)
+    /* QSIO3 */
+    #define QSPI_FLASH_IO3_PORT             (GPIO_PORT_D)
+    #define QSPI_FLASH_IO3_PIN              (GPIO_PIN_11)
+    #define QSPI_FLASH_IO3_FUNC             (GPIO_FUNC_7)
+#endif
+
+/*********** TMRA_PULSE_ENCODER configure *********/
+#if defined(RT_USING_PULSE_ENCODER)
+    #if defined(BSP_USING_TMRA_PULSE_ENCODER)
+        #if defined(BSP_USING_PULSE_ENCODER_TMRA_1)
+            #define PULSE_ENCODER_TMRA_1_A_PORT      (GPIO_PORT_A)
+            #define PULSE_ENCODER_TMRA_1_A_PIN       (GPIO_PIN_08)
+            #define PULSE_ENCODER_TMRA_1_A_PIN_FUNC  (GPIO_FUNC_4)
+            #define PULSE_ENCODER_TMRA_1_B_PORT      (GPIO_PORT_A)
+            #define PULSE_ENCODER_TMRA_1_B_PIN       (GPIO_PIN_09)
+            #define PULSE_ENCODER_TMRA_1_B_PIN_FUNC  (GPIO_FUNC_4)
+        #endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */
+    #endif /* BSP_USING_TMRA_PULSE_ENCODER */
+
+    #if defined(BSP_USING_TMR6_PULSE_ENCODER)
+        #if defined(BSP_USING_PULSE_ENCODER_TMR6_1)
+            #define PULSE_ENCODER_TMR6_1_A_PORT      (GPIO_PORT_A)
+            #define PULSE_ENCODER_TMR6_1_A_PIN       (GPIO_PIN_08)
+            #define PULSE_ENCODER_TMR6_1_A_PIN_FUNC  (GPIO_FUNC_3)
+            #define PULSE_ENCODER_TMR6_1_B_PORT      (GPIO_PORT_A)
+            #define PULSE_ENCODER_TMR6_1_B_PIN       (GPIO_PIN_07)
+            #define PULSE_ENCODER_TMR6_1_B_PIN_FUNC  (GPIO_FUNC_3)
+        #endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */
+    #endif /* BSP_USING_TMR6_PULSE_ENCODER */
+#endif /* RT_USING_PULSE_ENCODER */
+
+#endif
+

bsp/hc32/ev_hc32f448_lqfp80/board/config/adc_config.h

@@ -0,0 +1,155 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-02-20     CDT          first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+#include "irq_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_ADC1
+#ifndef ADC1_INIT_PARAMS
+#define ADC1_INIT_PARAMS                                                        \
+    {                                                                           \
+       .name                            = "adc1",                               \
+       .vref                            = 3300,                                 \
+       .resolution                      = ADC_RESOLUTION_12BIT,                 \
+       .data_align                      = ADC_DATAALIGN_RIGHT,                  \
+       .eoc_poll_time_max               = 100,                                  \
+       .hard_trig_enable                = RT_FALSE,                             \
+       .hard_trig_src                   = ADC_HARDTRIG_EVT0,                    \
+       .internal_trig0_comtrg0_enable   = RT_FALSE,                             \
+       .internal_trig0_comtrg1_enable   = RT_FALSE,                             \
+       .internal_trig0_sel              = EVT_SRC_TMR0_1_CMP_A,                 \
+       .internal_trig1_comtrg0_enable   = RT_FALSE,                             \
+       .internal_trig1_comtrg1_enable   = RT_FALSE,                             \
+       .internal_trig1_sel              = EVT_SRC_MAX,                          \
+       .continue_conv_mode_enable       = RT_FALSE,                             \
+       .data_reg_auto_clear             = RT_TRUE,                              \
+    }
+#endif /* ADC1_INIT_PARAMS */
+
+#if defined (BSP_ADC1_USING_DMA)
+#ifndef ADC1_EOCA_DMA_CONFIG
+#define ADC1_EOCA_DMA_CONFIG                                                    \
+    {                                                                           \
+        .Instance                       = ADC1_EOCA_DMA_INSTANCE,               \
+        .channel                        = ADC1_EOCA_DMA_CHANNEL,                \
+        .clock                          = ADC1_EOCA_DMA_CLOCK,                  \
+        .trigger_select                 = ADC1_EOCA_DMA_TRIG_SELECT,            \
+        .trigger_event                  = EVT_SRC_ADC1_EOCA,                    \
+        .flag                           = ADC1_EOCA_DMA_TRANS_FLAG,             \
+        .irq_config                     =                                       \
+        {                                                                       \
+            .irq_num                    = ADC1_EOCA_DMA_IRQn,                   \
+            .irq_prio                   = ADC1_EOCA_DMA_INT_PRIO,               \
+            .int_src                    = ADC1_EOCA_DMA_INT_SRC,                \
+        },                                                                      \
+    }
+#endif /* ADC1_EOCA_DMA_CONFIG */
+#endif /* BSP_ADC1_USING_DMA */
+#endif /* BSP_USING_ADC1 */
+
+#ifdef BSP_USING_ADC2
+#ifndef ADC2_INIT_PARAMS
+#define ADC2_INIT_PARAMS                                                        \
+    {                                                                           \
+       .name                            = "adc2",                               \
+       .vref                            = 3300,                                 \
+       .resolution                      = ADC_RESOLUTION_12BIT,                 \
+       .data_align                      = ADC_DATAALIGN_RIGHT,                  \
+       .eoc_poll_time_max               = 100,                                  \
+       .hard_trig_enable                = RT_FALSE,                             \
+       .hard_trig_src                   = ADC_HARDTRIG_EVT0,                    \
+       .internal_trig0_comtrg0_enable   = RT_FALSE,                             \
+       .internal_trig0_comtrg1_enable   = RT_FALSE,                             \
+       .internal_trig0_sel              = EVT_SRC_TMR0_1_CMP_A,                 \
+       .internal_trig1_comtrg0_enable   = RT_FALSE,                             \
+       .internal_trig1_comtrg1_enable   = RT_FALSE,                             \
+       .internal_trig1_sel              = EVT_SRC_MAX,                          \
+       .continue_conv_mode_enable       = RT_FALSE,                             \
+       .data_reg_auto_clear             = RT_TRUE,                              \
+    }
+#endif /* ADC2_INIT_PARAMS */
+
+#if defined (BSP_ADC2_USING_DMA)
+#ifndef ADC2_EOCA_DMA_CONFIG
+#define ADC2_EOCA_DMA_CONFIG                                                    \
+    {                                                                           \
+        .Instance                       = ADC2_EOCA_DMA_INSTANCE,               \
+        .channel                        = ADC2_EOCA_DMA_CHANNEL,                \
+        .clock                          = ADC2_EOCA_DMA_CLOCK,                  \
+        .trigger_select                 = ADC2_EOCA_DMA_TRIG_SELECT,            \
+        .trigger_event                  = EVT_SRC_ADC2_EOCA,                    \
+        .flag                           = ADC2_EOCA_DMA_TRANS_FLAG,             \
+        .irq_config                     =                                       \
+        {                                                                       \
+            .irq_num                    = ADC2_EOCA_DMA_IRQn,                   \
+            .irq_prio                   = ADC2_EOCA_DMA_INT_PRIO,               \
+            .int_src                    = ADC2_EOCA_DMA_INT_SRC,                \
+        },                                                                      \
+    }
+#endif /* ADC2_EOCA_DMA_CONFIG */
+#endif /* BSP_ADC2_USING_DMA */
+#endif /* BSP_USING_ADC2 */
+
+#ifdef BSP_USING_ADC3
+#ifndef ADC3_INIT_PARAMS
+#define ADC3_INIT_PARAMS                                                        \
+    {                                                                           \
+       .name                            = "adc3",                               \
+       .vref                            = 3300,                                 \
+       .resolution                      = ADC_RESOLUTION_12BIT,                 \
+       .data_align                      = ADC_DATAALIGN_RIGHT,                  \
+       .eoc_poll_time_max               = 100,                                  \
+       .hard_trig_enable                = RT_FALSE,                             \
+       .hard_trig_src                   = ADC_HARDTRIG_EVT0,                    \
+       .internal_trig0_comtrg0_enable   = RT_FALSE,                             \
+       .internal_trig0_comtrg1_enable   = RT_FALSE,                             \
+       .internal_trig0_sel              = EVT_SRC_TMR0_1_CMP_A,                 \
+       .internal_trig1_comtrg0_enable   = RT_FALSE,                             \
+       .internal_trig1_comtrg1_enable   = RT_FALSE,                             \
+       .internal_trig1_sel              = EVT_SRC_MAX,                          \
+       .continue_conv_mode_enable       = RT_FALSE,                             \
+       .data_reg_auto_clear             = RT_TRUE,                              \
+    }
+#endif /* ADC3_INIT_PARAMS */
+
+#if defined (BSP_ADC3_USING_DMA)
+#ifndef ADC3_EOCA_DMA_CONFIG
+#define ADC3_EOCA_DMA_CONFIG                                                    \
+    {                                                                           \
+        .Instance                       = ADC3_EOCA_DMA_INSTANCE,               \
+        .channel                        = ADC3_EOCA_DMA_CHANNEL,                \
+        .clock                          = ADC3_EOCA_DMA_CLOCK,                  \
+        .trigger_select                 = ADC3_EOCA_DMA_TRIG_SELECT,            \
+        .trigger_event                  = EVT_SRC_ADC3_EOCA,                    \
+        .flag                           = ADC3_EOCA_DMA_TRANS_FLAG,             \
+        .irq_config                     =                                       \
+        {                                                                       \
+            .irq_num                    = ADC3_EOCA_DMA_IRQn,                   \
+            .irq_prio                   = ADC3_EOCA_DMA_INT_PRIO,               \
+            .int_src                    = ADC3_EOCA_DMA_INT_SRC,                \
+        },                                                                      \
+    }
+#endif /* ADC3_EOCA_DMA_CONFIG */
+#endif /* BSP_ADC3_USING_DMA */
+#endif /* BSP_USING_ADC3 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ADC_CONFIG_H__ */

bsp/hc32/ev_hc32f448_lqfp80/board/config/can_config.h

@@ -0,0 +1,139 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-02-20     CDT          first version
+ */
+
+#ifndef __CAN_CONFIG_H__
+#define __CAN_CONFIG_H__
+
+#include <rtthread.h>
+#include "irq_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_CAN1
+#define CAN1_CLOCK_SEL                  (CAN_CLOCK_SRC_40M)
+#ifdef RT_CAN_USING_CANFD
+#define CAN1_CANFD_MODE                 (CAN_FD_MD_ISO)
+#endif
+#define CAN1_NAME                       ("can1")
+#ifndef CAN1_INIT_PARAMS
+#define CAN1_INIT_PARAMS                                    \
+    {                                                       \
+       .name = CAN1_NAME,                                   \
+       .single_trans_mode = RT_FALSE                        \
+    }
+#endif /* CAN1_INIT_PARAMS */
+#endif /* BSP_USING_CAN1 */
+
+#ifdef BSP_USING_CAN2
+#define CAN2_CLOCK_SEL                  (CAN_CLOCK_SRC_40M)
+#ifdef RT_CAN_USING_CANFD
+#define CAN2_CANFD_MODE                 (CAN_FD_MD_ISO)
+#endif
+#define CAN2_NAME                       ("can2")
+#ifndef CAN2_INIT_PARAMS
+#define CAN2_INIT_PARAMS                                    \
+    {                                                       \
+       .name = CAN2_NAME,                                   \
+       .single_trans_mode = RT_FALSE                        \
+    }
+#endif /* CAN2_INIT_PARAMS */
+#endif /* BSP_USING_CAN2 */
+
+/* Bit time config
+  Restrictions: u32TimeSeg1 >= u32TimeSeg2 + 1, u32TimeSeg2 >= u32SJW.
+
+  Baudrate = CANClock/(u32Prescaler*(u32TimeSeg1 + u32TimeSeg2))
+  TQ = u32Prescaler / CANClock.
+  Bit time = (u32TimeSeg2 + u32TimeSeg2) x TQ.
+
+  The following bit time configures are based on CAN Clock 40M
+*/
+#define CAN_BIT_TIME_CONFIG_1M_BAUD                         \
+    {                                                       \
+        .u32Prescaler = 2,                                  \
+        .u32TimeSeg1 = 16,                                  \
+        .u32TimeSeg2 = 4,                                   \
+        .u32SJW = 4                                         \
+    }
+
+#define CAN_BIT_TIME_CONFIG_800K_BAUD                       \
+    {                                                       \
+        .u32Prescaler = 2,                                  \
+        .u32TimeSeg1 = 20,                                  \
+        .u32TimeSeg2 = 5,                                   \
+        .u32SJW = 4                                         \
+    }
+
+#define CAN_BIT_TIME_CONFIG_500K_BAUD                       \
+    {                                                       \
+        .u32Prescaler = 4,                                  \
+        .u32TimeSeg1 = 16,                                  \
+        .u32TimeSeg2 = 4,                                   \
+        .u32SJW = 4                                         \
+    }
+
+#define CAN_BIT_TIME_CONFIG_250K_BAUD                       \
+    {                                                       \
+        .u32Prescaler = 8,                                  \
+        .u32TimeSeg1 = 16,                                  \
+        .u32TimeSeg2 = 4,                                   \
+        .u32SJW = 4                                         \
+    }
+
+#define CAN_BIT_TIME_CONFIG_125K_BAUD                       \
+    {                                                       \
+        .u32Prescaler = 16,                                 \
+        .u32TimeSeg1 = 16,                                  \
+        .u32TimeSeg2 = 4,                                   \
+        .u32SJW = 4                                         \
+    }
+
+#define CAN_BIT_TIME_CONFIG_100K_BAUD                       \
+    {                                                       \
+        .u32Prescaler = 20,                                 \
+        .u32TimeSeg1 = 16,                                  \
+        .u32TimeSeg2 = 4,                                   \
+        .u32SJW = 4                                         \
+    }
+
+#define CAN_BIT_TIME_CONFIG_50K_BAUD                        \
+    {                                                       \
+        .u32Prescaler = 40,                                 \
+        .u32TimeSeg1 = 16,                                  \
+        .u32TimeSeg2 = 4,                                   \
+        .u32SJW = 4                                         \
+    }
+
+#define CAN_BIT_TIME_CONFIG_20K_BAUD                        \
+    {                                                       \
+        .u32Prescaler = 100,                                \
+        .u32TimeSeg1 = 16,                                  \
+        .u32TimeSeg2 = 4,                                   \
+        .u32SJW = 4                                         \
+    }
+
+#define CAN_BIT_TIME_CONFIG_10K_BAUD                        \
+    {                                                       \
+        .u32Prescaler = 200,                                \
+        .u32TimeSeg1 = 16,                                  \
+        .u32TimeSeg2 = 4,                                   \
+        .u32SJW = 4                                         \
+    }
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CAN_CONFIG_H__ */
+
+

bsp/hc32/ev_hc32f448_lqfp80/board/config/dac_config.h

@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-02-20     CDT          first version
+ */
+
+#ifndef __DAC_CONFIG_H__
+#define __DAC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_DAC1
+#ifndef DAC1_INIT_PARAMS
+#define DAC1_INIT_PARAMS                                                    \
+    {                                                                       \
+       .name                      = "dac1",                                 \
+    }
+#endif /* DAC1_INIT_PARAMS */
+#endif /* BSP_USING_DAC1 */
+
+#ifdef BSP_USING_DAC2
+#ifndef DAC2_INIT_PARAMS
+#define DAC2_INIT_PARAMS                                                    \
+    {                                                                       \
+       .name                      = "dac2",                                 \
+    }
+#endif /* DAC2_INIT_PARAMS */
+#endif /* BSP_USING_DAC2 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DAC_CONFIG_H__ */

bsp/hc32/ev_hc32f448_lqfp80/board/config/dma_config.h

@@ -0,0 +1,263 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-02-20     CDT          first version
+ */
+
+#ifndef __DMA_CONFIG_H__
+#define __DMA_CONFIG_H__
+
+#include <rtthread.h>
+#include "irq_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* DMA1 ch0 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_RX_DMA_INSTANCE            CM_DMA1
+#define SPI1_RX_DMA_CHANNEL             DMA_CH0
+#define SPI1_RX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SPI1_RX_DMA_TRIG_SELECT         AOS_DMA1_0
+#define SPI1_RX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH0
+#define SPI1_RX_DMA_IRQn                BSP_DMA1_CH0_IRQ_NUM
+#define SPI1_RX_DMA_INT_PRIO            BSP_DMA1_CH0_IRQ_PRIO
+#define SPI1_RX_DMA_INT_SRC             INT_SRC_DMA1_TC0
+
+#elif defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
+#define SPI3_RX_DMA_INSTANCE            CM_DMA1
+#define SPI3_RX_DMA_CHANNEL             DMA_CH0
+#define SPI3_RX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SPI3_RX_DMA_TRIG_SELECT         AOS_DMA1_0
+#define SPI3_RX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH0
+#define SPI3_RX_DMA_IRQn                BSP_DMA1_CH0_IRQ_NUM
+#define SPI3_RX_DMA_INT_PRIO            BSP_DMA1_CH0_IRQ_PRIO
+#define SPI3_RX_DMA_INT_SRC             INT_SRC_DMA1_TC0
+
+#elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_INSTANCE)
+#define I2C1_TX_DMA_INSTANCE            CM_DMA1
+#define I2C1_TX_DMA_CHANNEL             DMA_CH0
+#define I2C1_TX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define I2C1_TX_DMA_TRIG_SELECT         AOS_DMA1_0
+#define I2C1_TX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH0
+#define I2C1_TX_DMA_IRQn                BSP_DMA1_CH0_IRQ_NUM
+#define I2C1_TX_DMA_INT_PRIO            BSP_DMA1_CH0_IRQ_PRIO
+#define I2C1_TX_DMA_INT_SRC             INT_SRC_DMA1_TC0
+#endif
+
+/* DMA1 ch1 */
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_TX_DMA_INSTANCE            CM_DMA1
+#define SPI1_TX_DMA_CHANNEL             DMA_CH1
+#define SPI1_TX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SPI1_TX_DMA_TRIG_SELECT         AOS_DMA1_1
+#define SPI1_TX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH1
+#define SPI1_TX_DMA_IRQn                BSP_DMA1_CH1_IRQ_NUM
+#define SPI1_TX_DMA_INT_PRIO            BSP_DMA1_CH1_IRQ_PRIO
+#define SPI1_TX_DMA_INT_SRC             INT_SRC_DMA1_TC1
+
+#elif defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
+#define SPI3_TX_DMA_INSTANCE            CM_DMA1
+#define SPI3_TX_DMA_CHANNEL             DMA_CH1
+#define SPI3_TX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SPI3_TX_DMA_TRIG_SELECT         AOS_DMA1_1
+#define SPI3_TX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH1
+#define SPI3_TX_DMA_IRQn                BSP_DMA1_CH1_IRQ_NUM
+#define SPI3_TX_DMA_INT_PRIO            BSP_DMA1_CH1_IRQ_PRIO
+#define SPI3_TX_DMA_INT_SRC             INT_SRC_DMA1_TC1
+
+#elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_INSTANCE)
+#define I2C1_RX_DMA_INSTANCE            CM_DMA1
+#define I2C1_RX_DMA_CHANNEL             DMA_CH1
+#define I2C1_RX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define I2C1_RX_DMA_TRIG_SELECT         AOS_DMA1_1
+#define I2C1_RX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH1
+#define I2C1_RX_DMA_IRQn                BSP_DMA1_CH1_IRQ_NUM
+#define I2C1_RX_DMA_INT_PRIO            BSP_DMA1_CH1_IRQ_PRIO
+#define I2C1_RX_DMA_INT_SRC             INT_SRC_DMA1_TC1
+#endif
+
+/* DMA1 ch2 */
+#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
+#define SPI2_RX_DMA_INSTANCE            CM_DMA1
+#define SPI2_RX_DMA_CHANNEL             DMA_CH2
+#define SPI2_RX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SPI2_RX_DMA_TRIG_SELECT         AOS_DMA1_2
+#define SPI2_RX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH2
+#define SPI2_RX_DMA_IRQn                BSP_DMA1_CH2_IRQ_NUM
+#define SPI2_RX_DMA_INT_PRIO            BSP_DMA1_CH2_IRQ_PRIO
+#define SPI2_RX_DMA_INT_SRC             INT_SRC_DMA1_TC2
+
+#elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_INSTANCE)
+#define I2C2_TX_DMA_INSTANCE            CM_DMA1
+#define I2C2_TX_DMA_CHANNEL             DMA_CH2
+#define I2C2_TX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define I2C2_TX_DMA_TRIG_SELECT         AOS_DMA1_2
+#define I2C2_TX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH2
+#define I2C2_TX_DMA_IRQn                BSP_DMA1_CH2_IRQ_NUM
+#define I2C2_TX_DMA_INT_PRIO            BSP_DMA1_CH2_IRQ_PRIO
+#define I2C2_TX_DMA_INT_SRC             INT_SRC_DMA1_TC2
+#endif
+
+/* DMA1 ch3 */
+#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
+#define SPI2_TX_DMA_INSTANCE            CM_DMA1
+#define SPI2_TX_DMA_CHANNEL             DMA_CH3
+#define SPI2_TX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SPI2_TX_DMA_TRIG_SELECT         AOS_DMA1_3
+#define SPI2_TX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH3
+#define SPI2_TX_DMA_IRQn                BSP_DMA1_CH3_IRQ_NUM
+#define SPI2_TX_DMA_INT_PRIO            BSP_DMA1_CH3_IRQ_PRIO
+#define SPI2_TX_DMA_INT_SRC             INT_SRC_DMA1_TC3
+
+
+#elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_INSTANCE)
+#define I2C2_RX_DMA_INSTANCE            CM_DMA1
+#define I2C2_RX_DMA_CHANNEL             DMA_CH3
+#define I2C2_RX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define I2C2_RX_DMA_TRIG_SELECT         AOS_DMA1_3
+#define I2C2_RX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH3
+#define I2C2_RX_DMA_IRQn                BSP_DMA1_CH3_IRQ_NUM
+#define I2C2_RX_DMA_INT_PRIO            BSP_DMA1_CH3_IRQ_PRIO
+#define I2C2_RX_DMA_INT_SRC             INT_SRC_DMA1_TC3
+
+#elif defined(BSP_ADC1_USING_DMA) && !defined(ADC1_EOCA_DMA_INSTANCE)
+#define ADC1_EOCA_DMA_INSTANCE          CM_DMA1
+#define ADC1_EOCA_DMA_CHANNEL           DMA_CH3
+#define ADC1_EOCA_DMA_CLOCK             (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define ADC1_EOCA_DMA_TRIG_SELECT       AOS_DMA1_3
+#define ADC1_EOCA_DMA_TRANS_FLAG        DMA_FLAG_TC_CH3
+#define ADC1_EOCA_DMA_IRQn              BSP_DMA1_CH3_IRQ_NUM
+#define ADC1_EOCA_DMA_INT_PRIO          BSP_DMA1_CH3_IRQ_PRIO
+#define ADC1_EOCA_DMA_INT_SRC           INT_SRC_DMA1_TC3
+
+#endif
+
+/* DMA1 ch4 */
+#if defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE)
+#define UART5_RX_DMA_INSTANCE           CM_DMA1
+#define UART5_RX_DMA_CHANNEL            DMA_CH4
+#define UART5_RX_DMA_CLOCK              (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define UART5_RX_DMA_TRIG_SELECT        AOS_DMA1_4
+#define UART5_RX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH4
+#define UART5_RX_DMA_IRQn               BSP_DMA1_CH4_IRQ_NUM
+#define UART5_RX_DMA_INT_PRIO           BSP_DMA1_CH4_IRQ_PRIO
+#define UART5_RX_DMA_INT_SRC            INT_SRC_DMA1_TC4
+
+#elif defined(BSP_ADC2_USING_DMA) && !defined(ADC2_EOCA_DMA_INSTANCE)
+#define ADC2_EOCA_DMA_INSTANCE          CM_DMA1
+#define ADC2_EOCA_DMA_CHANNEL           DMA_CH4
+#define ADC2_EOCA_DMA_CLOCK             (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define ADC2_EOCA_DMA_TRIG_SELECT       AOS_DMA1_4
+#define ADC2_EOCA_DMA_TRANS_FLAG        DMA_FLAG_TC_CH4
+#define ADC2_EOCA_DMA_IRQn              BSP_DMA1_CH4_IRQ_NUM
+#define ADC2_EOCA_DMA_INT_PRIO          BSP_DMA1_CH4_IRQ_PRIO
+#define ADC2_EOCA_DMA_INT_SRC           INT_SRC_DMA1_TC4
+#endif
+
+/* DMA1 ch5 */
+#if defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE)
+#define UART5_TX_DMA_INSTANCE           CM_DMA1
+#define UART5_TX_DMA_CHANNEL            DMA_CH5
+#define UART5_TX_DMA_CLOCK              (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define UART5_TX_DMA_TRIG_SELECT        AOS_DMA1_5
+#define UART5_TX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH5
+#define UART5_TX_DMA_IRQn               BSP_DMA1_CH5_IRQ_NUM
+#define UART5_TX_DMA_INT_PRIO           BSP_DMA1_CH5_IRQ_PRIO
+#define UART5_TX_DMA_INT_SRC            INT_SRC_DMA1_TC5
+
+#elif defined(BSP_ADC3_USING_DMA) && !defined(ADC3_EOCA_DMA_INSTANCE)
+#define ADC3_EOCA_DMA_INSTANCE          CM_DMA1
+#define ADC3_EOCA_DMA_CHANNEL           DMA_CH5
+#define ADC3_EOCA_DMA_CLOCK             (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define ADC3_EOCA_DMA_TRIG_SELECT       AOS_DMA1_5
+#define ADC3_EOCA_DMA_TRANS_FLAG        DMA_FLAG_TC_CH5
+#define ADC3_EOCA_DMA_IRQn              BSP_DMA1_CH5_IRQ_NUM
+#define ADC3_EOCA_DMA_INT_PRIO          BSP_DMA1_CH5_IRQ_PRIO
+#define ADC3_EOCA_DMA_INT_SRC           INT_SRC_DMA1_TC5
+#endif
+
+/* DMA2 ch0 */
+#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_RX_DMA_INSTANCE           CM_DMA2
+#define UART1_RX_DMA_CHANNEL            DMA_CH0
+#define UART1_RX_DMA_CLOCK              (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define UART1_RX_DMA_TRIG_SELECT        AOS_DMA2_0
+#define UART1_RX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH0
+#define UART1_RX_DMA_IRQn               BSP_DMA2_CH0_IRQ_NUM
+#define UART1_RX_DMA_INT_PRIO           BSP_DMA2_CH0_IRQ_PRIO
+#define UART1_RX_DMA_INT_SRC            INT_SRC_DMA2_TC0
+#endif
+
+/* DMA2 ch1 */
+#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
+#define UART1_TX_DMA_INSTANCE           CM_DMA2
+#define UART1_TX_DMA_CHANNEL            DMA_CH1
+#define UART1_TX_DMA_CLOCK              (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define UART1_TX_DMA_TRIG_SELECT        AOS_DMA2_1
+#define UART1_TX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH1
+#define UART1_TX_DMA_IRQn               BSP_DMA2_CH1_IRQ_NUM
+#define UART1_TX_DMA_INT_PRIO           BSP_DMA2_CH1_IRQ_PRIO
+#define UART1_TX_DMA_INT_SRC            INT_SRC_DMA2_TC1
+#endif
+
+/* DMA2 ch2 */
+#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
+#define UART2_RX_DMA_INSTANCE           CM_DMA2
+#define UART2_RX_DMA_CHANNEL            DMA_CH2
+#define UART2_RX_DMA_CLOCK              (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define UART2_RX_DMA_TRIG_SELECT        AOS_DMA2_2
+#define UART2_RX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH2
+#define UART2_RX_DMA_IRQn               BSP_DMA2_CH2_IRQ_NUM
+#define UART2_RX_DMA_INT_PRIO           BSP_DMA2_CH2_IRQ_PRIO
+#define UART2_RX_DMA_INT_SRC            INT_SRC_DMA2_TC2
+#endif
+
+/* DMA2 ch3 */
+#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
+#define UART2_TX_DMA_INSTANCE           CM_DMA2
+#define UART2_TX_DMA_CHANNEL            DMA_CH3
+#define UART2_TX_DMA_CLOCK              (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define UART2_TX_DMA_TRIG_SELECT        AOS_DMA2_3
+#define UART2_TX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH3
+#define UART2_TX_DMA_IRQn               BSP_DMA2_CH3_IRQ_NUM
+#define UART2_TX_DMA_INT_PRIO           BSP_DMA2_CH3_IRQ_PRIO
+#define UART2_TX_DMA_INT_SRC            INT_SRC_DMA2_TC3
+#endif
+
+/* DMA2 ch4 */
+#if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
+#define UART4_RX_DMA_INSTANCE           CM_DMA2
+#define UART4_RX_DMA_CHANNEL            DMA_CH4
+#define UART4_RX_DMA_CLOCK              (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define UART4_RX_DMA_TRIG_SELECT        AOS_DMA2_4
+#define UART4_RX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH4
+#define UART4_RX_DMA_IRQn               BSP_DMA2_CH4_IRQ_NUM
+#define UART4_RX_DMA_INT_PRIO           BSP_DMA2_CH4_IRQ_PRIO
+#define UART4_RX_DMA_INT_SRC            INT_SRC_DMA2_TC4
+#endif
+
+/* DMA2 ch5 */
+#if defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE)
+#define UART4_TX_DMA_INSTANCE           CM_DMA2
+#define UART4_TX_DMA_CHANNEL            DMA_CH5
+#define UART4_TX_DMA_CLOCK              (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define UART4_TX_DMA_TRIG_SELECT        AOS_DMA2_5
+#define UART4_TX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH5
+#define UART4_TX_DMA_IRQn               BSP_DMA2_CH5_IRQ_NUM
+#define UART4_TX_DMA_INT_PRIO           BSP_DMA2_CH5_IRQ_PRIO
+#define UART4_TX_DMA_INT_SRC            INT_SRC_DMA2_TC5
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __DMA_CONFIG_H__ */

bsp/hc32/ev_hc32f448_lqfp80/board/config/gpio_config.h

@@ -0,0 +1,176 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-02-20     CDT          first version
+ */
+
+#ifndef __GPIO_CONFIG_H__
+#define __GPIO_CONFIG_H__
+
+#include <rtthread.h>
+#include "irq_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(RT_USING_PIN)
+
+#ifndef EXTINT0_IRQ_CONFIG
+#define EXTINT0_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = BSP_EXTINT0_IRQ_NUM,                  \
+        .irq_prio   = BSP_EXTINT0_IRQ_PRIO,                 \
+        .int_src    = INT_SRC_PORT_EIRQ0,                   \
+    }
+#endif /* EXTINT1_IRQ_CONFIG */
+
+#ifndef EXTINT1_IRQ_CONFIG
+#define EXTINT1_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = BSP_EXTINT1_IRQ_NUM,                  \
+        .irq_prio   = BSP_EXTINT1_IRQ_PRIO,                 \
+        .int_src    = INT_SRC_PORT_EIRQ1,                   \
+    }
+#endif /* EXTINT1_IRQ_CONFIG */
+
+#ifndef EXTINT2_IRQ_CONFIG
+#define EXTINT2_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = BSP_EXTINT2_IRQ_NUM,                  \
+        .irq_prio   = BSP_EXTINT2_IRQ_PRIO,                 \
+        .int_src    = INT_SRC_PORT_EIRQ2,                   \
+    }
+#endif /* EXTINT2_IRQ_CONFIG */
+
+#ifndef EXTINT3_IRQ_CONFIG
+#define EXTINT3_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = BSP_EXTINT3_IRQ_NUM,                  \
+        .irq_prio   = BSP_EXTINT3_IRQ_PRIO,                 \
+        .int_src    = INT_SRC_PORT_EIRQ3,                   \
+    }
+#endif /* EXTINT3_IRQ_CONFIG */
+
+#ifndef EXTINT4_IRQ_CONFIG
+#define EXTINT4_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = BSP_EXTINT4_IRQ_NUM,                  \
+        .irq_prio   = BSP_EXTINT4_IRQ_PRIO,                 \
+        .int_src    = INT_SRC_PORT_EIRQ4,                   \
+    }
+#endif /* EXTINT4_IRQ_CONFIG */
+
+#ifndef EXTINT5_IRQ_CONFIG
+#define EXTINT5_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = BSP_EXTINT5_IRQ_NUM,                  \
+        .irq_prio   = BSP_EXTINT5_IRQ_PRIO,                 \
+        .int_src    = INT_SRC_PORT_EIRQ5,                   \
+    }
+#endif /* EXTINT5_IRQ_CONFIG */
+
+#ifndef EXTINT6_IRQ_CONFIG
+#define EXTINT6_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = BSP_EXTINT6_IRQ_NUM,                  \
+        .irq_prio   = BSP_EXTINT6_IRQ_PRIO,                 \
+        .int_src    = INT_SRC_PORT_EIRQ6,                   \
+    }
+#endif /* EXTINT6_IRQ_CONFIG */
+
+#ifndef EXTINT7_IRQ_CONFIG
+#define EXTINT7_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = BSP_EXTINT7_IRQ_NUM,                  \
+        .irq_prio   = BSP_EXTINT7_IRQ_PRIO,                 \
+        .int_src    = INT_SRC_PORT_EIRQ7,                   \
+    }
+#endif /* EXTINT7_IRQ_CONFIG */
+
+#ifndef EXTINT8_IRQ_CONFIG
+#define EXTINT8_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = BSP_EXTINT8_IRQ_NUM,                  \
+        .irq_prio   = BSP_EXTINT8_IRQ_PRIO,                 \
+        .int_src    = INT_SRC_PORT_EIRQ8,                   \
+    }
+#endif /* EXTINT8_IRQ_CONFIG */
+
+#ifndef EXTINT9_IRQ_CONFIG
+#define EXTINT9_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = BSP_EXTINT9_IRQ_NUM,                  \
+        .irq_prio   = BSP_EXTINT9_IRQ_PRIO,                 \
+        .int_src    = INT_SRC_PORT_EIRQ9,                   \
+    }
+#endif /* EXTINT9_IRQ_CONFIG */
+
+#ifndef EXTINT10_IRQ_CONFIG
+#define EXTINT10_IRQ_CONFIG                                 \
+    {                                                       \
+        .irq_num    = BSP_EXTINT10_IRQ_NUM,                 \
+        .irq_prio   = BSP_EXTINT10_IRQ_PRIO,                \
+        .int_src    = INT_SRC_PORT_EIRQ10,                  \
+    }
+#endif /* EXTINT10_IRQ_CONFIG */
+
+#ifndef EXTINT11_IRQ_CONFIG
+#define EXTINT11_IRQ_CONFIG                                 \
+    {                                                       \
+        .irq_num    = BSP_EXTINT11_IRQ_NUM,                 \
+        .irq_prio   = BSP_EXTINT11_IRQ_PRIO,                \
+        .int_src    = INT_SRC_PORT_EIRQ11,                  \
+    }
+#endif /* EXTINT11_IRQ_CONFIG */
+
+#ifndef EXTINT12_IRQ_CONFIG
+#define EXTINT12_IRQ_CONFIG                                 \
+    {                                                       \
+        .irq_num    = BSP_EXTINT12_IRQ_NUM,                 \
+        .irq_prio   = BSP_EXTINT12_IRQ_PRIO,                \
+        .int_src    = INT_SRC_PORT_EIRQ12,                  \
+    }
+#endif /* EXTINT12_IRQ_CONFIG */
+
+#ifndef EXTINT13_IRQ_CONFIG
+#define EXTINT13_IRQ_CONFIG                                 \
+    {                                                       \
+        .irq_num    = BSP_EXTINT13_IRQ_NUM,                 \
+        .irq_prio   = BSP_EXTINT13_IRQ_PRIO,                \
+        .int_src    = INT_SRC_PORT_EIRQ13,                  \
+    }
+#endif /* EXTINT13_IRQ_CONFIG */
+
+#ifndef EXTINT14_IRQ_CONFIG
+#define EXTINT14_IRQ_CONFIG                                 \
+    {                                                       \
+        .irq_num    = BSP_EXTINT14_IRQ_NUM,                 \
+        .irq_prio   = BSP_EXTINT14_IRQ_PRIO,                \
+        .int_src    = INT_SRC_PORT_EIRQ14,                  \
+    }
+#endif /* EXTINT14_IRQ_CONFIG */
+
+#ifndef EXTINT15_IRQ_CONFIG
+#define EXTINT15_IRQ_CONFIG                                 \
+    {                                                       \
+        .irq_num    = BSP_EXTINT15_IRQ_NUM,                 \
+        .irq_prio   = BSP_EXTINT15_IRQ_PRIO,                \
+        .int_src    = INT_SRC_PORT_EIRQ15,                  \
+    }
+#endif /* EXTINT15_IRQ_CONFIG */
+
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __GPIO_CONFIG_H__ */

bsp/hc32/ev_hc32f448_lqfp80/board/config/i2c_config.h

@@ -0,0 +1,332 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-02-20     CDT          first version
+ */
+
+#ifndef __I2C_CONFIG_H__
+#define __I2C_CONFIG_H__
+
+#include <rtthread.h>
+#include "irq_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_I2C1)
+#ifndef I2C1_CONFIG
+#define I2C1_CONFIG                                             \
+    {                                                           \
+        .name     = "i2c1",                                     \
+        .Instance = CM_I2C1,                                    \
+        .clock    = FCG1_PERIPH_I2C1,                           \
+        .baudrate = 100000UL,                                   \
+        .timeout  = 10000UL,                                    \
+    }
+#endif /* I2C1_CONFIG */
+#endif
+
+#if defined(BSP_I2C1_USING_DMA)
+#ifndef I2C1_TX_DMA_CONFIG
+#define I2C1_TX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C1_TX_DMA_INSTANCE,                 \
+        .channel        = I2C1_TX_DMA_CHANNEL,                  \
+        .clock          = I2C1_TX_DMA_CLOCK,                    \
+        .trigger_select = I2C1_TX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C1_TEI,                     \
+        .flag           = I2C1_TX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C1_TX_DMA_IRQn,                     \
+            .irq_prio   = I2C1_TX_DMA_INT_PRIO,                 \
+            .int_src    = I2C1_TX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C1_TX_DMA_CONFIG */
+
+#ifndef I2C1_RX_DMA_CONFIG
+#define I2C1_RX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C1_RX_DMA_INSTANCE,                 \
+        .channel        = I2C1_RX_DMA_CHANNEL,                  \
+        .clock          = I2C1_RX_DMA_CLOCK,                    \
+        .trigger_select = I2C1_RX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C1_RXI,                     \
+        .flag           = I2C1_RX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C1_RX_DMA_IRQn,                     \
+            .irq_prio   = I2C1_RX_DMA_INT_PRIO,                 \
+            .int_src    = I2C1_RX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C1_RX_DMA_CONFIG */
+#endif /* BSP_I2C1_USING_DMA */
+
+#if defined(BSP_USING_I2C2)
+#ifndef I2C2_CONFIG
+#define I2C2_CONFIG                                             \
+    {                                                           \
+        .name     = "i2c2",                                     \
+        .Instance = CM_I2C2,                                    \
+        .clock    = FCG1_PERIPH_I2C2,                           \
+        .baudrate = 100000UL,                                   \
+        .timeout  = 10000UL,                                    \
+    }
+#endif /* I2C2_CONFIG */
+
+#if defined(BSP_I2C2_USING_DMA)
+#ifndef I2C2_TX_DMA_CONFIG
+#define I2C2_TX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C2_TX_DMA_INSTANCE,                 \
+        .channel        = I2C2_TX_DMA_CHANNEL,                  \
+        .clock          = I2C2_TX_DMA_CLOCK,                    \
+        .trigger_select = I2C2_TX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C2_TEI,                     \
+        .flag           = I2C2_TX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C2_TX_DMA_IRQn,                     \
+            .irq_prio   = I2C2_TX_DMA_INT_PRIO,                 \
+            .int_src    = I2C2_TX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C2_TX_DMA_CONFIG */
+
+#ifndef I2C2_RX_DMA_CONFIG
+#define I2C2_RX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C2_RX_DMA_INSTANCE,                 \
+        .channel        = I2C2_RX_DMA_CHANNEL,                  \
+        .clock          = I2C2_RX_DMA_CLOCK,                    \
+        .trigger_select = I2C2_RX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C2_RXI,                     \
+        .flag           = I2C2_RX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C2_RX_DMA_IRQn,                     \
+            .irq_prio   = I2C2_RX_DMA_INT_PRIO,                 \
+            .int_src    = I2C2_RX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C2_RX_DMA_CONFIG */
+#endif /* BSP_I2C2_USING_DMA */
+#endif
+
+#if defined(BSP_USING_I2C3)
+#ifndef I2C3_CONFIG
+#define I2C3_CONFIG                                             \
+    {                                                           \
+        .name     = "i2c3",                                     \
+        .Instance = CM_I2C3,                                    \
+        .clock    = FCG1_PERIPH_I2C3,                           \
+        .baudrate = 100000UL,                                   \
+        .timeout  = 10000UL,                                    \
+    }
+#endif /* I2C3_CONFIG */
+
+#if defined(BSP_I2C3_USING_DMA)
+#ifndef I2C3_TX_DMA_CONFIG
+#define I2C3_TX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C3_TX_DMA_INSTANCE,                 \
+        .channel        = I2C3_TX_DMA_CHANNEL,                  \
+        .clock          = I2C3_TX_DMA_CLOCK,                    \
+        .trigger_select = I2C3_TX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C3_TEI,                     \
+        .flag           = I2C3_TX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C3_TX_DMA_IRQn,                     \
+            .irq_prio   = I2C3_TX_DMA_INT_PRIO,                 \
+            .int_src    = I2C3_TX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C3_TX_DMA_CONFIG */
+
+#ifndef I2C3_RX_DMA_CONFIG
+#define I2C3_RX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C3_RX_DMA_INSTANCE,                 \
+        .channel        = I2C3_RX_DMA_CHANNEL,                  \
+        .clock          = I2C3_RX_DMA_CLOCK,                    \
+        .trigger_select = I2C3_RX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C3_RXI,                     \
+        .flag           = I2C3_RX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C3_RX_DMA_IRQn,                     \
+            .irq_prio   = I2C3_RX_DMA_INT_PRIO,                 \
+            .int_src    = I2C3_RX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C3_RX_DMA_CONFIG */
+#endif /* BSP_I2C3_USING_DMA */
+#endif
+
+#if defined(BSP_USING_I2C4)
+#ifndef I2C4_CONFIG
+#define I2C4_CONFIG                                             \
+    {                                                           \
+        .name     = "i2c4",                                     \
+        .Instance = CM_I2C4,                                    \
+        .clock    = FCG1_PERIPH_I2C4,                           \
+        .baudrate = 100000UL,                                   \
+        .timeout  = 10000UL,                                    \
+    }
+#endif /* I2C4_CONFIG */
+
+#if defined(BSP_I2C4_USING_DMA)
+#ifndef I2C4_TX_DMA_CONFIG
+#define I2C4_TX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C4_TX_DMA_INSTANCE,                 \
+        .channel        = I2C4_TX_DMA_CHANNEL,                  \
+        .clock          = I2C4_TX_DMA_CLOCK,                    \
+        .trigger_select = I2C4_TX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C4_TEI,                     \
+        .flag           = I2C4_TX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C4_TX_DMA_IRQn,                     \
+            .irq_prio   = I2C4_TX_DMA_INT_PRIO,                 \
+            .int_src    = I2C4_TX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C4_TX_DMA_CONFIG */
+
+#ifndef I2C4_RX_DMA_CONFIG
+#define I2C4_RX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C4_RX_DMA_INSTANCE,                 \
+        .channel        = I2C4_RX_DMA_CHANNEL,                  \
+        .clock          = I2C4_RX_DMA_CLOCK,                    \
+        .trigger_select = I2C4_RX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C4_RXI,                     \
+        .flag           = I2C4_RX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C4_RX_DMA_IRQn,                     \
+            .irq_prio   = I2C4_RX_DMA_INT_PRIO,                 \
+            .int_src    = I2C4_RX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C4_RX_DMA_CONFIG */
+#endif /* BSP_I2C4_USING_DMA */
+#endif
+
+#if defined(BSP_USING_I2C5)
+#ifndef I2C5_CONFIG
+#define I2C5_CONFIG                                             \
+    {                                                           \
+        .name     = "i2c5",                                     \
+        .Instance = CM_I2C5,                                    \
+        .clock    = FCG1_PERIPH_I2C5,                           \
+        .baudrate = 100000UL,                                   \
+        .timeout  = 10000UL,                                    \
+    }
+#endif /* I2C5_CONFIG */
+
+#if defined(BSP_I2C5_USING_DMA)
+#ifndef I2C5_TX_DMA_CONFIG
+#define I2C5_TX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C5_TX_DMA_INSTANCE,                 \
+        .channel        = I2C5_TX_DMA_CHANNEL,                  \
+        .clock          = I2C5_TX_DMA_CLOCK,                    \
+        .trigger_select = I2C5_TX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C5_TEI,                     \
+        .flag           = I2C5_TX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C5_TX_DMA_IRQn,                     \
+            .irq_prio   = I2C5_TX_DMA_INT_PRIO,                 \
+            .int_src    = I2C5_TX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C5_TX_DMA_CONFIG */
+
+#ifndef I2C5_RX_DMA_CONFIG
+#define I2C5_RX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C5_RX_DMA_INSTANCE,                 \
+        .channel        = I2C5_RX_DMA_CHANNEL,                  \
+        .clock          = I2C5_RX_DMA_CLOCK,                    \
+        .trigger_select = I2C5_RX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C5_RXI,                     \
+        .flag           = I2C5_RX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C5_RX_DMA_IRQn,                     \
+            .irq_prio   = I2C5_RX_DMA_INT_PRIO,                 \
+            .int_src    = I2C5_RX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C5_RX_DMA_CONFIG */
+#endif /* BSP_I2C5_USING_DMA */
+#endif
+
+#if defined(BSP_USING_I2C6)
+#ifndef I2C6_CONFIG
+#define I2C6_CONFIG                                             \
+    {                                                           \
+        .name     = "i2c6",                                     \
+        .Instance = CM_I2C6,                                    \
+        .clock    = FCG1_PERIPH_I2C6,                           \
+        .baudrate = 100000UL,                                   \
+        .timeout  = 10000UL,                                    \
+    }
+#endif /* I2C6_CONFIG */
+
+#if defined(BSP_I2C6_USING_DMA)
+#ifndef I2C6_TX_DMA_CONFIG
+#define I2C6_TX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C6_TX_DMA_INSTANCE,                 \
+        .channel        = I2C6_TX_DMA_CHANNEL,                  \
+        .clock          = I2C6_TX_DMA_CLOCK,                    \
+        .trigger_select = I2C6_TX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C6_TEI,                     \
+        .flag           = I2C6_TX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C6_TX_DMA_IRQn,                     \
+            .irq_prio   = I2C6_TX_DMA_INT_PRIO,                 \
+            .int_src    = I2C6_TX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C6_TX_DMA_CONFIG */
+
+#ifndef I2C6_RX_DMA_CONFIG
+#define I2C6_RX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C6_RX_DMA_INSTANCE,                 \
+        .channel        = I2C6_RX_DMA_CHANNEL,                  \
+        .clock          = I2C6_RX_DMA_CLOCK,                    \
+        .trigger_select = I2C6_RX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C6_RXI,                     \
+        .flag           = I2C6_RX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C6_RX_DMA_IRQn,                     \
+            .irq_prio   = I2C6_RX_DMA_INT_PRIO,                 \
+            .int_src    = I2C6_RX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C6_RX_DMA_CONFIG */
+#endif /* BSP_I2C6_USING_DMA */
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/hc32/ev_hc32f448_lqfp80/board/config/irq_config.h

@@ -0,0 +1,200 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-02-20     CDT          first version
+ */
+
+#ifndef __IRQ_CONFIG_H__
+#define __IRQ_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define BSP_EXTINT0_IRQ_NUM             EXTINT_PORT_EIRQ0_IRQn
+#define BSP_EXTINT0_IRQ_PRIO            DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT1_IRQ_NUM             EXTINT_PORT_EIRQ1_IRQn
+#define BSP_EXTINT1_IRQ_PRIO            DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT2_IRQ_NUM             EXTINT_PORT_EIRQ2_IRQn
+#define BSP_EXTINT2_IRQ_PRIO            DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT3_IRQ_NUM             EXTINT_PORT_EIRQ3_IRQn
+#define BSP_EXTINT3_IRQ_PRIO            DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT4_IRQ_NUM             EXTINT_PORT_EIRQ4_IRQn
+#define BSP_EXTINT4_IRQ_PRIO            DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT5_IRQ_NUM             EXTINT_PORT_EIRQ5_IRQn
+#define BSP_EXTINT5_IRQ_PRIO            DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT6_IRQ_NUM             EXTINT_PORT_EIRQ6_IRQn
+#define BSP_EXTINT6_IRQ_PRIO            DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT7_IRQ_NUM             EXTINT_PORT_EIRQ7_IRQn
+#define BSP_EXTINT7_IRQ_PRIO            DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT8_IRQ_NUM             EXTINT_PORT_EIRQ8_IRQn
+#define BSP_EXTINT8_IRQ_PRIO            DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT9_IRQ_NUM             EXTINT_PORT_EIRQ9_IRQn
+#define BSP_EXTINT9_IRQ_PRIO            DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT10_IRQ_NUM            EXTINT_PORT_EIRQ10_IRQn
+#define BSP_EXTINT10_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT11_IRQ_NUM            EXTINT_PORT_EIRQ11_IRQn
+#define BSP_EXTINT11_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT12_IRQ_NUM            EXTINT_PORT_EIRQ12_IRQn
+#define BSP_EXTINT12_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT13_IRQ_NUM            EXTINT_PORT_EIRQ13_IRQn
+#define BSP_EXTINT13_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT14_IRQ_NUM            EXTINT_PORT_EIRQ14_IRQn
+#define BSP_EXTINT14_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT15_IRQ_NUM            EXTINT_PORT_EIRQ15_IRQn
+#define BSP_EXTINT15_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+
+/* DMA1 ch0 */
+#define BSP_DMA1_CH0_IRQ_NUM            INT000_IRQn
+#define BSP_DMA1_CH0_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+/* DMA1 ch1 */
+#define BSP_DMA1_CH1_IRQ_NUM            INT001_IRQn
+#define BSP_DMA1_CH1_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+/* DMA1 ch2 */
+#define BSP_DMA1_CH2_IRQ_NUM            INT002_IRQn
+#define BSP_DMA1_CH2_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+/* DMA1 ch3 */
+#define BSP_DMA1_CH3_IRQ_NUM            INT003_IRQn
+#define BSP_DMA1_CH3_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+/* DMA1 ch4 */
+#define BSP_DMA1_CH4_IRQ_NUM            INT004_IRQn
+#define BSP_DMA1_CH4_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+/* DMA1 ch5 */
+#define BSP_DMA1_CH5_IRQ_NUM            INT005_IRQn
+#define BSP_DMA1_CH5_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+
+/* DMA2 ch0 */
+#define BSP_DMA2_CH0_IRQ_NUM            INT006_IRQn
+#define BSP_DMA2_CH0_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+/* DMA2 ch1 */
+#define BSP_DMA2_CH1_IRQ_NUM            INT007_IRQn
+#define BSP_DMA2_CH1_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+/* DMA2 ch2 */
+#define BSP_DMA2_CH2_IRQ_NUM            INT008_IRQn
+#define BSP_DMA2_CH2_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+/* DMA2 ch3 */
+#define BSP_DMA2_CH3_IRQ_NUM            INT009_IRQn
+#define BSP_DMA2_CH3_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+/* DMA2 ch4 */
+#define BSP_DMA2_CH4_IRQ_NUM            INT010_IRQn
+#define BSP_DMA2_CH4_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+/* DMA2 ch5 */
+#define BSP_DMA2_CH5_IRQ_NUM            INT011_IRQn
+#define BSP_DMA2_CH5_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+
+#if defined(BSP_USING_UART1)
+#define BSP_UART1_IRQ_NUM               USART1_IRQn
+#define BSP_UART1_IRQ_PRIO              DDL_IRQ_PRIO_DEFAULT
+
+#if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA)) || \
+    defined(RT_USING_SERIAL_V2)
+#define BSP_UART1_TX_CPLT_IRQ_NUM       USART1_TCI_IRQn
+#define BSP_UART1_TX_CPLT_IRQ_PRIO      DDL_IRQ_PRIO_DEFAULT
+#endif
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+#define BSP_UART2_IRQ_NUM               USART2_IRQn
+#define BSP_UART2_IRQ_PRIO              DDL_IRQ_PRIO_DEFAULT
+
+#if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA)) || \
+    defined(RT_USING_SERIAL_V2)
+#define BSP_UART2_TX_CPLT_IRQ_NUM       USART2_TCI_IRQn
+#define BSP_UART2_TX_CPLT_IRQ_PRIO      DDL_IRQ_PRIO_DEFAULT
+#endif
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+#define BSP_UART3_IRQ_NUM               USART3_IRQn
+#define BSP_UART3_IRQ_PRIO              DDL_IRQ_PRIO_DEFAULT
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_USING_UART4)
+#define BSP_UART4_IRQ_NUM               USART4_IRQn
+#define BSP_UART4_IRQ_PRIO              DDL_IRQ_PRIO_DEFAULT
+
+#if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART4_TX_USING_DMA)) || \
+    defined(RT_USING_SERIAL_V2)
+#define BSP_UART4_TX_CPLT_IRQ_NUM       USART4_TCI_IRQn
+#define BSP_UART4_TX_CPLT_IRQ_PRIO      DDL_IRQ_PRIO_DEFAULT
+#endif
+#endif /* BSP_USING_UART4 */
+
+#if defined(BSP_USING_UART5)
+#define BSP_UART5_IRQ_NUM               USART5_IRQn
+#define BSP_UART5_IRQ_PRIO              DDL_IRQ_PRIO_DEFAULT
+
+#if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART5_TX_USING_DMA)) || \
+    defined(RT_USING_SERIAL_V2)
+#define BSP_UART5_TX_CPLT_IRQ_NUM       USART5_TCI_IRQn
+#define BSP_UART5_TX_CPLT_IRQ_PRIO      DDL_IRQ_PRIO_DEFAULT
+#endif
+#endif /* BSP_USING_UART5 */
+
+#if defined(BSP_USING_UART6)
+#define BSP_UART6_IRQ_NUM               USART6_IRQn
+#define BSP_UART6_IRQ_PRIO              DDL_IRQ_PRIO_DEFAULT
+#endif /* BSP_USING_UART6 */
+
+#if defined(BSP_USING_SPI1)
+#define BSP_SPI1_ERR_IRQ_NUM            SPI1_IRQn
+#define BSP_SPI1_ERR_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#endif
+
+#if defined(BSP_USING_SPI2)
+#define BSP_SPI2_ERR_IRQ_NUM            SPI2_IRQn
+#define BSP_SPI2_ERR_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#endif
+
+#if defined(BSP_USING_SPI3)
+#define BSP_SPI3_ERR_IRQ_NUM            SPI3_IRQn
+#define BSP_SPI3_ERR_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#endif
+
+#if defined(BSP_USING_TMRA_1)
+#define BSP_USING_TMRA_1_IRQ_NUM        TMRA_1_OVF_UDF_IRQn
+#define BSP_USING_TMRA_1_IRQ_PRIO       DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_TMRA_1 */
+
+#if defined(BSP_USING_TMRA_2)
+#define BSP_USING_TMRA_2_IRQ_NUM        TMRA_2_OVF_UDF_IRQn
+#define BSP_USING_TMRA_2_IRQ_PRIO       DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_TMRA_2 */
+
+#if defined(BSP_USING_TMRA_3)
+#define BSP_USING_TMRA_3_IRQ_NUM        TMRA_3_OVF_UDF_IRQn
+#define BSP_USING_TMRA_3_IRQ_PRIO       DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_TMRA_3 */
+
+#if defined(BSP_USING_TMRA_4)
+#define BSP_USING_TMRA_4_IRQ_NUM        TMRA_4_OVF_UDF_IRQn
+#define BSP_USING_TMRA_4_IRQ_PRIO       DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_TMRA_4 */
+
+#if defined(BSP_USING_TMRA_5)
+#define BSP_USING_TMRA_5_IRQ_NUM        TMRA_5_OVF_UDF_IRQn
+#define BSP_USING_TMRA_5_IRQ_PRIO       DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_TMRA_5 */
+
+#if defined(BSP_USING_CAN1)
+#define BSP_CAN1_IRQ_NUM                MCAN1_INT0_IRQn
+#define BSP_CAN1_IRQ_PRIO               DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_CAN1 */
+
+#if defined(RT_USING_ALARM)
+#define BSP_RTC_ALARM_IRQ_NUM           RTC_IRQn
+#define BSP_RTC_ALARM_IRQ_PRIO          DDL_IRQ_PRIO_DEFAULT
+#endif/* RT_USING_ALARM */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __IRQ_CONFIG_H__ */

bsp/hc32/ev_hc32f448_lqfp80/board/config/pm_config.h

@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-02-20     CDT          first version
+ */
+
+#ifndef __PM_CONFIG_H__
+#define __PM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_PM
+extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode);
+
+#ifndef PM_TICKLESS_TIMER_ENABLE_MASK
+#define PM_TICKLESS_TIMER_ENABLE_MASK                                          \
+(   (1UL << PM_SLEEP_MODE_IDLE)  |                                             \
+    (1UL << PM_SLEEP_MODE_DEEP))
+#endif
+
+/**
+ * @brief  run mode config @ref pm_run_mode_config structure
+ */
+#ifndef PM_RUN_MODE_CFG
+#define PM_RUN_MODE_CFG                                                        \
+    {                                                                          \
+       .sys_clk_cfg = rt_hw_board_pm_sysclk_cfg                                \
+    }
+#endif /* PM_RUN_MODE_CFG */
+
+/**
+ * @brief  sleep idle config @ref pm_sleep_mode_idle_config structure
+ */
+#ifndef PM_SLEEP_IDLE_CFG
+#define PM_SLEEP_IDLE_CFG                                                      \
+{                                                                              \
+    .pwc_sleep_type = PWC_SLEEP_WFE_INT,                                       \
+}
+#endif /*PM_SLEEP_IDLE_CFG*/
+
+/**
+ * @brief  sleep deep config @ref pm_sleep_mode_deep_config structure
+ */
+#ifndef PM_SLEEP_DEEP_CFG
+#define PM_SLEEP_DEEP_CFG                                                      \
+{                                                                              \
+    {                                                                          \
+        .u16Clock = PWC_STOP_CLK_KEEP,                                         \
+        .u8StopDrv = PWC_STOP_DRV_HIGH,                                        \
+        .u16ExBusHold = PWC_STOP_EXBUS_HIZ,                                    \
+        .u16FlashWait = PWC_STOP_FLASH_WAIT_ON,                                \
+    },                                                                         \
+    .pwc_stop_type = PWC_STOP_WFE_INT,                                         \
+}
+#endif /*PM_SLEEP_DEEP_CFG*/
+
+/**
+ * @brief  sleep standby config @ref pm_sleep_mode_standby_config structure
+ */
+#ifndef PM_SLEEP_STANDBY_CFG
+#define PM_SLEEP_STANDBY_CFG                                                   \
+{                                                                              \
+    {                                                                          \
+        .u8Mode = PWC_PD_MD1,                                                  \
+        .u8IOState = PWC_PD_IO_KEEP1,                                          \
+        .u8VcapCtrl = PWC_PD_VCAP_0P047UF,                                     \
+    },                                                                         \
+}
+#endif /*PM_SLEEP_STANDBY_CFG*/
+
+/**
+ * @brief  sleep shutdown config @ref pm_sleep_mode_shutdown_config structure
+ */
+#ifndef PM_SLEEP_SHUTDOWN_CFG
+#define PM_SLEEP_SHUTDOWN_CFG                                                  \
+{                                                                              \
+    {                                                                          \
+        .u8Mode = PWC_PD_MD3,                                                  \
+        .u8IOState = PWC_PD_IO_KEEP1,                                          \
+        .u8VcapCtrl = PWC_PD_VCAP_0P047UF,                                     \
+    },                                                                         \
+}
+#endif /*PM_SLEEP_SHUTDOWN_CFG*/
+
+#endif /* BSP_USING_PM */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PM_CONFIG_H__ */

bsp/hc32/ev_hc32f448_lqfp80/board/config/pulse_encoder_config.h

@@ -0,0 +1,545 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-02-20     CDT          first version
+ */
+
+#ifndef __PULSE_ENCODER_CONFIG_H__
+#define __PULSE_ENCODER_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(RT_USING_PULSE_ENCODER)
+
+#ifdef BSP_USING_PULSE_ENCODER_TMRA_1
+#ifndef PULSE_ENCODER_TMRA_1_CONFIG
+#define PULSE_ENCODER_TMRA_1_CONFIG                                             \
+    {                                                                           \
+       .tmr_handler     = CM_TMRA_1,                                            \
+       .u32Fcg2Periph   = FCG2_PERIPH_TMRA_1,                                   \
+       .hw_count =                                                              \
+       {                                                                        \
+            .u16CountUpCond     = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING,       \
+            .u16CountDownCond   = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING,     \
+       },                                                                       \
+       .isr =                                                                   \
+       {                                                                        \
+            .enIntSrc_OVF   = INT_SRC_TMRA_1_OVF,                               \
+            .enIRQn_OVF     = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM,             \
+            .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO,            \
+            .enIntSrc_UDF   = INT_SRC_TMRA_1_UDF,                               \
+            .enIRQn_UDF     = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM,             \
+            .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO,            \
+       },                                                                       \
+       .u32PeriodValue      = 1000UL,                                           \
+       .name                = "pulse_a1"                                        \
+    }
+#endif /* PULSE_ENCODER_TMRA_1_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMRA_2
+#ifndef PULSE_ENCODER_TMRA_2_CONFIG
+#define PULSE_ENCODER_TMRA_2_CONFIG                                             \
+    {                                                                           \
+       .tmr_handler     = CM_TMRA_2,                                            \
+       .u32Fcg2Periph   = FCG2_PERIPH_TMRA_2,                                   \
+       .hw_count =                                                              \
+       {                                                                        \
+            .u16CountUpCond     = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING,       \
+            .u16CountDownCond   = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING,     \
+       },                                                                       \
+       .isr =                                                                   \
+       {                                                                        \
+            .enIntSrc_OVF   = INT_SRC_TMRA_2_OVF,                               \
+            .enIRQn_OVF     = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM,             \
+            .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO,            \
+            .enIntSrc_UDF   = INT_SRC_TMRA_2_UDF,                               \
+            .enIRQn_UDF     = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM,             \
+            .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO,            \
+       },                                                                       \
+       .u32PeriodValue  = 1000UL,                                               \
+       .name            = "pulse_a2"                                            \
+    }
+#endif /* PULSE_ENCODER_TMRA_2_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMRA_2 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMRA_3
+#ifndef PULSE_ENCODER_TMRA_3_CONFIG
+#define PULSE_ENCODER_TMRA_3_CONFIG                                             \
+    {                                                                           \
+       .tmr_handler     = CM_TMRA_3,                                            \
+       .u32Fcg2Periph   = FCG2_PERIPH_TMRA_3,                                   \
+       .hw_count =                                                              \
+       {                                                                        \
+            .u16CountUpCond     = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING,       \
+            .u16CountDownCond   = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING,     \
+       },                                                                       \
+       .isr =                                                                   \
+       {                                                                        \
+            .enIntSrc_OVF   = INT_SRC_TMRA_3_OVF,                               \
+            .enIRQn_OVF     = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM,             \
+            .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO,            \
+            .enIntSrc_UDF   = INT_SRC_TMRA_3_UDF,                               \
+            .enIRQn_UDF     = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM,             \
+            .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO,            \
+       },                                                                       \
+       .u32PeriodValue  = 1000UL,                                               \
+       .name            = "pulse_a3"                                            \
+    }
+#endif /* PULSE_ENCODER_TMRA_3_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMRA_3 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMRA_4
+#ifndef PULSE_ENCODER_TMRA_4_CONFIG
+#define PULSE_ENCODER_TMRA_4_CONFIG                                             \
+    {                                                                           \
+       .tmr_handler     = CM_TMRA_4,                                            \
+       .u32Fcg2Periph   = FCG2_PERIPH_TMRA_4,                                   \
+       .hw_count =                                                              \
+       {                                                                        \
+            .u16CountUpCond     = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING,       \
+            .u16CountDownCond   = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING,     \
+       },                                                                       \
+       .isr =                                                                   \
+       {                                                                        \
+            .enIntSrc_OVF   = INT_SRC_TMRA_4_OVF,                               \
+            .enIRQn_OVF     = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM,             \
+            .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO,            \
+            .enIntSrc_UDF   = INT_SRC_TMRA_4_UDF,                               \
+            .enIRQn_UDF     = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM,             \
+            .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO,            \
+       },                                                                       \
+       .u32PeriodValue  = 1000UL,                                               \
+       .name            = "pulse_a4"                                            \
+    }
+#endif /* PULSE_ENCODER_TMRA_4_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMRA_4 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMRA_5
+#ifndef PULSE_ENCODER_TMRA_5_CONFIG
+#define PULSE_ENCODER_TMRA_5_CONFIG                                             \
+    {                                                                           \
+       .tmr_handler     = CM_TMRA_5,                                            \
+       .u32Fcg2Periph   = FCG2_PERIPH_TMRA_5,                                   \
+       .hw_count =                                                              \
+        {                                                                       \
+            .u16CountUpCond     = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING,       \
+            .u16CountDownCond   = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING,     \
+       },                                                                       \
+       .isr =                                                                   \
+       {                                                                        \
+            .enIntSrc_OVF   = INT_SRC_TMRA_5_OVF,                               \
+            .enIRQn_OVF     = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM,             \
+            .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO,            \
+            .enIntSrc_UDF   = INT_SRC_TMRA_5_UDF,                               \
+            .enIRQn_UDF     = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM,             \
+            .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO,            \
+       },                                                                       \
+       .u32PeriodValue  = 1000UL,                                               \
+       .name            = "pulse_a5"                                            \
+    }
+#endif /* PULSE_ENCODER_TMRA_5_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMRA_5 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMRA_6
+#ifndef PULSE_ENCODER_TMRA_6_CONFIG
+#define PULSE_ENCODER_TMRA_6_CONFIG                                             \
+    {                                                                           \
+       .tmr_handler     = CM_TMRA_6,                                            \
+       .u32Fcg2Periph   = FCG2_PERIPH_TMRA_6,                                   \
+       .hw_count =                                                              \
+       {                                                                        \
+            .u16CountUpCond     = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING,       \
+            .u16CountDownCond   = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING,     \
+       },                                                                       \
+       .isr =                                                                   \
+       {                                                                        \
+            .enIntSrc_OVF   = INT_SRC_TMRA_6_OVF,                               \
+            .enIRQn_OVF     = BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_NUM,             \
+            .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_PRIO,            \
+            .enIntSrc_UDF   = INT_SRC_TMRA_6_UDF,                               \
+            .enIRQn_UDF     = BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_NUM,             \
+            .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_PRIO,            \
+       },                                                                       \
+       .u32PeriodValue  = 1000UL,                                               \
+       .name            = "pulse_a6"                                            \
+    }
+#endif /* PULSE_ENCODER_TMRA_6_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMRA_6 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMRA_7
+#ifndef PULSE_ENCODER_TMRA_7_CONFIG
+#define PULSE_ENCODER_TMRA_7_CONFIG                                             \
+    {                                                                           \
+       .tmr_handler     = CM_TMRA_7,                                            \
+       .u32Fcg2Periph   = FCG2_PERIPH_TMRA_7,                                   \
+       .hw_count =                                                              \
+       {                                                                        \
+            .u16CountUpCond     = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING,       \
+            .u16CountDownCond   = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING,     \
+       },                                                                       \
+       .isr =                                                                   \
+       {                                                                        \
+            .enIntSrc_OVF   = INT_SRC_TMRA_7_OVF,                               \
+            .enIRQn_OVF     = BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_NUM,             \
+            .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_PRIO,            \
+            .enIntSrc_UDF   = INT_SRC_TMRA_7_UDF,                               \
+            .enIRQn_UDF     = BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_NUM,             \
+            .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_PRIO,            \
+       },                                                                       \
+       .u32PeriodValue  = 1000UL,                                               \
+       .name            = "pulse_a7"                                            \
+    }
+#endif /* PULSE_ENCODER_TMRA_7_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMRA_7 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMRA_8
+#ifndef PULSE_ENCODER_TMRA_8_CONFIG
+#define PULSE_ENCODER_TMRA_8_CONFIG                                             \
+    {                                                                           \
+       .tmr_handler     = CM_TMRA_8,                                            \
+       .u32Fcg2Periph   = FCG2_PERIPH_TMRA_8,                                   \
+       .hw_count =                                                              \
+        {                                                                       \
+            .u16CountUpCond     = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING,       \
+            .u16CountDownCond   = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING,     \
+       },                                                                       \
+       .isr =                                                                   \
+       {                                                                        \
+            .enIntSrc_OVF   = INT_SRC_TMRA_8_OVF,                               \
+            .enIRQn_OVF     = BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_NUM,             \
+            .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_PRIO,            \
+            .enIntSrc_UDF   = INT_SRC_TMRA_8_UDF,                               \
+            .enIRQn_UDF     = BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_NUM,             \
+            .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_PRIO,            \
+       },                                                                       \
+       .u32PeriodValue  = 1000UL,                                               \
+       .name            = "pulse_a8"                                            \
+    }
+#endif /* PULSE_ENCODER_TMRA_8_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMRA_8 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMRA_9
+#ifndef PULSE_ENCODER_TMRA_9_CONFIG
+#define PULSE_ENCODER_TMRA_9_CONFIG                                             \
+    {                                                                           \
+       .tmr_handler     = CM_TMRA_9,                                            \
+       .u32Fcg2Periph   = FCG2_PERIPH_TMRA_9,                                   \
+       .hw_count =                                                              \
+       {                                                                        \
+            .u16CountUpCond     = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING,       \
+            .u16CountDownCond   = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING,     \
+       },                                                                       \
+       .isr =                                                                   \
+       {                                                                        \
+            .enIntSrc_OVF   = INT_SRC_TMRA_9_OVF,                               \
+            .enIRQn_OVF     = BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_NUM,             \
+            .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_PRIO,            \
+            .enIntSrc_UDF   = INT_SRC_TMRA_9_UDF,                               \
+            .enIRQn_UDF     = BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_NUM,             \
+            .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_PRIO,            \
+       },                                                                       \
+       .u32PeriodValue  = 1000UL,                                               \
+       .name            = "pulse_a9"                                            \
+    }
+#endif /* PULSE_ENCODER_TMRA_9_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMRA_9 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMRA_10
+#ifndef PULSE_ENCODER_TMRA_10_CONFIG
+#define PULSE_ENCODER_TMRA_10_CONFIG                                            \
+    {                                                                           \
+       .tmr_handler     = CM_TMRA_10,                                           \
+       .u32Fcg2Periph   = FCG2_PERIPH_TMRA_10,                                  \
+       .hw_count =                                                              \
+       {                                                                        \
+            .u16CountUpCond     = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING,       \
+            .u16CountDownCond   = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING,     \
+       },                                                                       \
+       .isr =                                                                   \
+       {                                                                        \
+            .enIntSrc_OVF   = INT_SRC_TMRA_10_OVF,                              \
+            .enIRQn_OVF     = BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_NUM,            \
+            .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_PRIO,           \
+            .enIntSrc_UDF   = INT_SRC_TMRA_10_UDF,                              \
+            .enIRQn_UDF     = BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_NUM,            \
+            .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_PRIO,           \
+       },                                                                       \
+       .u32PeriodValue  = 1000UL,                                               \
+       .name            = "pulse_a10"                                           \
+    }
+#endif /* PULSE_ENCODER_TMRA_10_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMRA_10 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMRA_11
+#ifndef PULSE_ENCODER_TMRA_11_CONFIG
+#define PULSE_ENCODER_TMRA_11_CONFIG                                            \
+    {                                                                           \
+       .tmr_handler     = CM_TMRA_11,                                           \
+       .u32Fcg2Periph   = FCG2_PERIPH_TMRA_11,                                  \
+       .hw_count =                                                              \
+       {                                                                        \
+            .u16CountUpCond     = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING,       \
+            .u16CountDownCond   = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING,     \
+       },                                                                       \
+       .isr =                                                                   \
+       {                                                                        \
+            .enIntSrc_OVF   = INT_SRC_TMRA_11_OVF,                              \
+            .enIRQn_OVF     = BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_NUM,            \
+            .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_PRIO,           \
+            .enIntSrc_UDF   = INT_SRC_TMRA_11_UDF,                              \
+            .enIRQn_UDF     = BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_NUM,            \
+            .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_PRIO,           \
+       },                                                                       \
+       .u32PeriodValue  = 1000UL,                                               \
+       .name            = "pulse_a11"                                           \
+    }
+#endif /* PULSE_ENCODER_TMRA_11_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMRA_11 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMRA_12
+#ifndef PULSE_ENCODER_TMRA_12_CONFIG
+#define PULSE_ENCODER_TMRA_12_CONFIG                                            \
+    {                                                                           \
+       .tmr_handler     = CM_TMRA_12,                                           \
+       .u32Fcg2Periph   = FCG2_PERIPH_TMRA_12,                                  \
+       .hw_count =                                                              \
+       {                                                                        \
+            .u16CountUpCond     = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING,       \
+            .u16CountDownCond   = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING,     \
+       },                                                                       \
+       .isr =                                                                   \
+       {                                                                        \
+            .enIntSrc_OVF   = INT_SRC_TMRA_12_OVF,                              \
+            .enIRQn_OVF     = BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_NUM,            \
+            .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_PRIO,           \
+            .enIntSrc_UDF   = INT_SRC_TMRA_12_UDF,                              \
+            .enIRQn_UDF     = BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_NUM,            \
+            .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_PRIO,           \
+       },                                                                       \
+       .u32PeriodValue  = 1000UL,                                               \
+       .name            = "pulse_a12"                                           \
+    }
+#endif /* PULSE_ENCODER_TMRA_12_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMRA_12 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMR6_1
+#ifndef PULSE_ENCODER_TMR6_1_CONFIG
+#define PULSE_ENCODER_TMR6_1_CONFIG                                             \
+    {                                                                           \
+       .tmr_handler     = CM_TMR6_1,                                            \
+       .u32Fcg2Periph   = FCG2_PERIPH_TMR6_1,                                   \
+       .hw_count =                                                              \
+       {                                                                        \
+            .u32CountUpCond     = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING,       \
+            .u32CountDownCond   = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING,     \
+       },                                                                       \
+       .isr =                                                                   \
+       {                                                                        \
+            .enIntSrc_OVF   = INT_SRC_TMR6_1_OVF,                               \
+            .enIRQn_OVF     = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM,             \
+            .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO,            \
+            .enIntSrc_UDF   = INT_SRC_TMR6_1_UDF,                               \
+            .enIRQn_UDF     = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM,             \
+            .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO,            \
+       },                                                                       \
+       .u32PeriodValue  = 1000UL,                                               \
+       .name            = "pulse_61"                                            \
+    }
+#endif /* PULSE_ENCODER_TMR6_1_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMR6_2
+#ifndef PULSE_ENCODER_TMR6_2_CONFIG
+#define PULSE_ENCODER_TMR6_2_CONFIG                                             \
+    {                                                                           \
+       .tmr_handler     = CM_TMR6_2,                                            \
+       .u32Fcg2Periph   = FCG2_PERIPH_TMR6_2,                                   \
+       .hw_count =                                                              \
+       {                                                                        \
+            .u32CountUpCond     = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING,       \
+            .u32CountDownCond   = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING,     \
+       },                                                                       \
+       .isr =                                                                   \
+       {                                                                        \
+            .enIntSrc_OVF   = INT_SRC_TMR6_2_OVF,                               \
+            .enIRQn_OVF     = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM,             \
+            .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO,            \
+            .enIntSrc_UDF   = INT_SRC_TMR6_2_UDF,                               \
+            .enIRQn_UDF     = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM,             \
+            .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO,            \
+       },                                                                       \
+       .u32PeriodValue  = 1000UL,                                               \
+       .name            = "pulse_62"                                            \
+    }
+#endif /* PULSE_ENCODER_TMR6_2_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMR6_2 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMR6_3
+#ifndef PULSE_ENCODER_TMR6_3_CONFIG
+#define PULSE_ENCODER_TMR6_3_CONFIG                                             \
+    {                                                                           \
+       .tmr_handler     = CM_TMR6_3,                                            \
+       .u32Fcg2Periph   = FCG2_PERIPH_TMR6_3,                                   \
+       .hw_count =                                                              \
+       {                                                                        \
+            .u32CountUpCond     = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING,       \
+            .u32CountDownCond   = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING,     \
+       },                                                                       \
+       .isr =                                                                   \
+       {                                                                        \
+            .enIntSrc_OVF   = INT_SRC_TMR6_3_OVF,                               \
+            .enIRQn_OVF     = BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_NUM,             \
+            .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_PRIO,            \
+            .enIntSrc_UDF   = INT_SRC_TMR6_3_UDF,                               \
+            .enIRQn_UDF     = BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_NUM,             \
+            .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_PRIO,            \
+       },                                                                       \
+       .u32PeriodValue  = 1000UL,                                               \
+       .name            = "pulse_63"                                            \
+    }
+#endif /* PULSE_ENCODER_TMR6_3_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMR6_3 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMR6_4
+#ifndef PULSE_ENCODER_TMR6_4_CONFIG
+#define PULSE_ENCODER_TMR6_4_CONFIG                                             \
+    {                                                                           \
+       .tmr_handler     = CM_TMR6_4,                                            \
+       .u32Fcg2Periph   = FCG2_PERIPH_TMR6_4,                                   \
+       .hw_count =                                                              \
+       {                                                                        \
+            .u32CountUpCond     = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING,       \
+            .u32CountDownCond   = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING,     \
+       },                                                                       \
+       .isr =                                                                   \
+       {                                                                        \
+            .enIntSrc_OVF   = INT_SRC_TMR6_4_OVF,                               \
+            .enIRQn_OVF     = BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_NUM,             \
+            .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_PRIO,            \
+            .enIntSrc_UDF   = INT_SRC_TMR6_4_UDF,                               \
+            .enIRQn_UDF     = BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_NUM,             \
+            .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_PRIO,            \
+       },                                                                       \
+       .u32PeriodValue  = 1000UL,                                               \
+       .name            = "pulse_64"                                            \
+    }
+#endif /* PULSE_ENCODER_TMR6_4_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMR6_4 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMR6_5
+#ifndef PULSE_ENCODER_TMR6_5_CONFIG
+#define PULSE_ENCODER_TMR6_5_CONFIG                                             \
+    {                                                                           \
+       .tmr_handler     = CM_TMR6_5,                                            \
+       .u32Fcg2Periph   = FCG2_PERIPH_TMR6_5,                                   \
+       .hw_count =                                                              \
+       {                                                                        \
+            .u32CountUpCond     = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING,       \
+            .u32CountDownCond   = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING,     \
+       },                                                                       \
+       .isr =                                                                   \
+       {                                                                        \
+            .enIntSrc_OVF   = INT_SRC_TMR6_5_OVF,                               \
+            .enIRQn_OVF     = BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_NUM,             \
+            .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_PRIO,            \
+            .enIntSrc_UDF   = INT_SRC_TMR6_5_UDF,                               \
+            .enIRQn_UDF     = BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_NUM,             \
+            .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_PRIO,            \
+       },                                                                       \
+       .u32PeriodValue  = 1000UL,                                               \
+       .name            = "pulse_65"                                            \
+    }
+#endif /* PULSE_ENCODER_TMR6_5_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMR6_5 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMR6_6
+#ifndef PULSE_ENCODER_TMR6_6_CONFIG
+#define PULSE_ENCODER_TMR6_6_CONFIG                                             \
+    {                                                                           \
+       .tmr_handler     = CM_TMR6_6,                                            \
+       .u32Fcg2Periph   = FCG2_PERIPH_TMR6_6,                                   \
+       .hw_count =                                                              \
+       {                                                                        \
+            .u32CountUpCond     = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING,       \
+            .u32CountDownCond   = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING,     \
+       },                                                                       \
+       .isr =                                                                   \
+       {                                                                        \
+            .enIntSrc_OVF   = INT_SRC_TMR6_6_OVF,                               \
+            .enIRQn_OVF     = BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_NUM,             \
+            .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_PRIO,            \
+            .enIntSrc_UDF   = INT_SRC_TMR6_6_UDF,                               \
+            .enIRQn_UDF     = BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_NUM,             \
+            .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_PRIO,            \
+       },                                                                       \
+       .u32PeriodValue  = 1000UL,                                               \
+       .name            = "pulse_66"                                            \
+    }
+#endif /* PULSE_ENCODER_TMR6_6_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMR6_6 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMR6_7
+#ifndef PULSE_ENCODER_TMR6_7_CONFIG
+#define PULSE_ENCODER_TMR6_7_CONFIG                                             \
+    {                                                                           \
+       .tmr_handler     = CM_TMR6_7,                                            \
+       .u32Fcg2Periph   = FCG2_PERIPH_TMR6_7,                                   \
+       .hw_count =                                                              \
+       {                                                                        \
+            .u32CountUpCond     = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING,       \
+            .u32CountDownCond   = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING,     \
+       },                                                                       \
+       .isr =                                                                   \
+       {                                                                        \
+            .enIntSrc_OVF   = INT_SRC_TMR6_7_OVF,                               \
+            .enIRQn_OVF     = BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_NUM,             \
+            .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_PRIO,            \
+            .enIntSrc_UDF   = INT_SRC_TMR6_7_UDF,                               \
+            .enIRQn_UDF     = BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_NUM,             \
+            .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_PRIO,            \
+       },                                                                       \
+       .u32PeriodValue  = 1000UL,                                               \
+       .name            = "pulse_67"                                            \
+    }
+#endif /* PULSE_ENCODER_TMR6_7_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMR6_7 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMR6_8
+#ifndef PULSE_ENCODER_TMR6_8_CONFIG
+#define PULSE_ENCODER_TMR6_8_CONFIG                                             \
+    {                                                                           \
+       .tmr_handler     = CM_TMR6_8,                                            \
+       .u32Fcg2Periph   = FCG2_PERIPH_TMR6_8,                                   \
+       .hw_count =                                                              \
+       {                                                                        \
+            .u32CountUpCond     = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING,       \
+            .u32CountDownCond   = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING,     \
+       },                                                                       \
+       .isr =                                                                   \
+       {                                                                        \
+            .enIntSrc_OVF   = INT_SRC_TMR6_8_OVF,                               \
+            .enIRQn_OVF     = BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_NUM,             \
+            .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_PRIO,            \
+            .enIntSrc_UDF   = INT_SRC_TMR6_8_UDF,                               \
+            .enIRQn_UDF     = BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_NUM,             \
+            .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_PRIO,            \
+       },                                                                       \
+       .u32PeriodValue  = 1000UL,                                               \
+       .name            = "pulse_68"                                            \
+    }
+#endif /* PULSE_ENCODER_TMR6_8_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMR6_8 */
+
+#endif /* RT_USING_PULSE_ENCODER */
+
+#endif /* __PULSE_ENCODER_CONFIG_H__ */

bsp/hc32/ev_hc32f448_lqfp80/board/config/pwm_tmr_config.h

@@ -0,0 +1,882 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-02-20     CDT          first version
+ */
+
+#ifndef __PWM_TMR_CONFIG_H__
+#define __PWM_TMR_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_PWM_TMRA
+
+#ifdef BSP_USING_PWM_TMRA_1
+#ifndef PWM_TMRA_1_CONFIG
+#define PWM_TMRA_1_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_a1",             \
+        .instance                       = CM_TMRA_1,            \
+        .channel                        = 0,                    \
+        .stcTmraInit =                                          \
+        {                                                       \
+            .u8CountSrc                 = TMRA_CNT_SRC_SW,      \
+            .u32PeriodValue             = 0xFFFF,               \
+            .sw_count =                                         \
+            {                                                   \
+                .u8ClockDiv             = TMRA_CLK_DIV1,        \
+                .u8CountMode            = TMRA_MD_SAWTOOTH,     \
+                .u8CountDir             = TMRA_DIR_DOWN,        \
+            },                                                  \
+            .u8CountReload              = TMRA_CNT_RELOAD_ENABLE\
+        },                                                      \
+        .stcPwmInit =                                           \
+        {                                                       \
+            .u32CompareValue            = 0x0000,               \
+            .u16StartPolarity           = TMRA_PWM_LOW,         \
+            .u16StopPolarity            = TMRA_PWM_LOW,         \
+            .u16CompareMatchPolarity    = TMRA_PWM_HIGH,        \
+            .u16PeriodMatchPolarity     = TMRA_PWM_LOW,         \
+        },                                                      \
+    }
+#endif /* PWM_TMRA_1_CONFIG */
+#endif /* BSP_USING_PWM_TMRA_1 */
+
+#ifdef BSP_USING_PWM_TMRA_2
+#ifndef PWM_TMRA_2_CONFIG
+#define PWM_TMRA_2_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_a2",             \
+        .instance                       = CM_TMRA_2,            \
+        .channel                        = 0,                    \
+        .stcTmraInit =                                          \
+        {                                                       \
+            .u8CountSrc                 = TMRA_CNT_SRC_SW,      \
+            .u32PeriodValue             = 0xFFFF,               \
+            .sw_count =                                         \
+            {                                                   \
+                .u8ClockDiv             = TMRA_CLK_DIV1,        \
+                .u8CountMode            = TMRA_MD_SAWTOOTH,     \
+                .u8CountDir             = TMRA_DIR_DOWN,        \
+            },                                                  \
+            .u8CountReload              = TMRA_CNT_RELOAD_ENABLE\
+        },                                                      \
+        .stcPwmInit =                                           \
+        {                                                       \
+            .u32CompareValue            = 0x0000,               \
+            .u16StartPolarity           = TMRA_PWM_LOW,         \
+            .u16StopPolarity            = TMRA_PWM_LOW,         \
+            .u16CompareMatchPolarity    = TMRA_PWM_HIGH,        \
+            .u16PeriodMatchPolarity     = TMRA_PWM_LOW,         \
+        },                                                      \
+    }
+#endif /* PWM_TMRA_2_CONFIG */
+#endif /* BSP_USING_PWM_TMRA_2 */
+
+#ifdef BSP_USING_PWM_TMRA_3
+#ifndef PWM_TMRA_3_CONFIG
+#define PWM_TMRA_3_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_a3",             \
+        .instance                       = CM_TMRA_3,            \
+        .channel                        = 0,                    \
+        .stcTmraInit =                                          \
+        {                                                       \
+            .u8CountSrc                 = TMRA_CNT_SRC_SW,      \
+            .u32PeriodValue             = 0xFFFF,               \
+            .sw_count =                                         \
+            {                                                   \
+                .u8ClockDiv             = TMRA_CLK_DIV1,        \
+                .u8CountMode            = TMRA_MD_SAWTOOTH,     \
+                .u8CountDir             = TMRA_DIR_DOWN,        \
+            },                                                  \
+            .u8CountReload              = TMRA_CNT_RELOAD_ENABLE\
+        },                                                      \
+        .stcPwmInit =                                           \
+        {                                                       \
+            .u32CompareValue            = 0x0000,               \
+            .u16StartPolarity           = TMRA_PWM_LOW,         \
+            .u16StopPolarity            = TMRA_PWM_LOW,         \
+            .u16CompareMatchPolarity    = TMRA_PWM_HIGH,        \
+            .u16PeriodMatchPolarity     = TMRA_PWM_LOW,         \
+        },                                                      \
+    }
+#endif /* PWM_TMRA_3_CONFIG */
+#endif /* BSP_USING_PWM_TMRA_3 */
+
+#ifdef BSP_USING_PWM_TMRA_4
+#ifndef PWM_TMRA_4_CONFIG
+#define PWM_TMRA_4_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_a4",             \
+        .instance                       = CM_TMRA_4,            \
+        .channel                        = 0,                    \
+        .stcTmraInit =                                          \
+        {                                                       \
+            .u8CountSrc                 = TMRA_CNT_SRC_SW,      \
+            .u32PeriodValue             = 0xFFFF,               \
+            .sw_count =                                         \
+            {                                                   \
+                .u8ClockDiv             = TMRA_CLK_DIV1,        \
+                .u8CountMode            = TMRA_MD_SAWTOOTH,     \
+                .u8CountDir             = TMRA_DIR_DOWN,        \
+            },                                                  \
+            .u8CountReload              = TMRA_CNT_RELOAD_ENABLE\
+        },                                                      \
+        .stcPwmInit =                                           \
+        {                                                       \
+            .u32CompareValue            = 0x0000,               \
+            .u16StartPolarity           = TMRA_PWM_LOW,         \
+            .u16StopPolarity            = TMRA_PWM_LOW,         \
+            .u16CompareMatchPolarity    = TMRA_PWM_HIGH,        \
+            .u16PeriodMatchPolarity     = TMRA_PWM_LOW,         \
+        },                                                      \
+    }
+#endif /* PWM_TMRA_4_CONFIG */
+#endif /* BSP_USING_PWM_TMRA_4 */
+
+#ifdef BSP_USING_PWM_TMRA_5
+#ifndef PWM_TMRA_5_CONFIG
+#define PWM_TMRA_5_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_a5",             \
+        .instance                       = CM_TMRA_5,            \
+        .channel                        = 0,                    \
+        .stcTmraInit =                                          \
+        {                                                       \
+            .u8CountSrc                 = TMRA_CNT_SRC_SW,      \
+            .u32PeriodValue             = 0xFFFF,               \
+            .sw_count =                                         \
+            {                                                   \
+                .u8ClockDiv             = TMRA_CLK_DIV1,        \
+                .u8CountMode            = TMRA_MD_SAWTOOTH,     \
+                .u8CountDir             = TMRA_DIR_DOWN,        \
+            },                                                  \
+            .u8CountReload              = TMRA_CNT_RELOAD_ENABLE\
+        },                                                      \
+        .stcPwmInit =                                           \
+        {                                                       \
+            .u32CompareValue            = 0x0000,               \
+            .u16StartPolarity           = TMRA_PWM_LOW,         \
+            .u16StopPolarity            = TMRA_PWM_LOW,         \
+            .u16CompareMatchPolarity    = TMRA_PWM_HIGH,        \
+            .u16PeriodMatchPolarity     = TMRA_PWM_LOW,         \
+        },                                                      \
+    }
+#endif /* PWM_TMRA_5_CONFIG */
+#endif /* BSP_USING_PWM_TMRA_5 */
+
+#ifdef BSP_USING_PWM_TMRA_6
+#ifndef PWM_TMRA_6_CONFIG
+#define PWM_TMRA_6_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_a6",             \
+        .instance                       = CM_TMRA_6,            \
+        .channel                        = 0,                    \
+        .stcTmraInit =                                          \
+        {                                                       \
+            .u8CountSrc                 = TMRA_CNT_SRC_SW,      \
+            .u32PeriodValue             = 0xFFFF,               \
+            .sw_count =                                         \
+            {                                                   \
+                .u8ClockDiv             = TMRA_CLK_DIV1,        \
+                .u8CountMode            = TMRA_MD_SAWTOOTH,     \
+                .u8CountDir             = TMRA_DIR_DOWN,        \
+            },                                                  \
+            .u8CountReload              = TMRA_CNT_RELOAD_ENABLE\
+        },                                                      \
+        .stcPwmInit =                                           \
+        {                                                       \
+            .u32CompareValue            = 0x0000,               \
+            .u16StartPolarity           = TMRA_PWM_LOW,         \
+            .u16StopPolarity            = TMRA_PWM_LOW,         \
+            .u16CompareMatchPolarity    = TMRA_PWM_HIGH,        \
+            .u16PeriodMatchPolarity     = TMRA_PWM_LOW,         \
+        },                                                      \
+    }
+#endif /* PWM_TMRA_6_CONFIG */
+#endif /* BSP_USING_PWM_TMRA_6 */
+
+#ifdef BSP_USING_PWM_TMRA_7
+#ifndef PWM_TMRA_7_CONFIG
+#define PWM_TMRA_7_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_a7",             \
+        .instance                       = CM_TMRA_7,            \
+        .channel                        = 0,                    \
+        .stcTmraInit =                                          \
+        {                                                       \
+            .u8CountSrc                 = TMRA_CNT_SRC_SW,      \
+            .u32PeriodValue             = 0xFFFF,               \
+            .sw_count =                                         \
+            {                                                   \
+                .u8ClockDiv             = TMRA_CLK_DIV1,        \
+                .u8CountMode            = TMRA_MD_SAWTOOTH,     \
+                .u8CountDir             = TMRA_DIR_DOWN,        \
+            },                                                  \
+            .u8CountReload              = TMRA_CNT_RELOAD_ENABLE\
+        },                                                      \
+        .stcPwmInit =                                           \
+        {                                                       \
+            .u32CompareValue            = 0x0000,               \
+            .u16StartPolarity           = TMRA_PWM_LOW,         \
+            .u16StopPolarity            = TMRA_PWM_LOW,         \
+            .u16CompareMatchPolarity    = TMRA_PWM_HIGH,        \
+            .u16PeriodMatchPolarity     = TMRA_PWM_LOW,         \
+        },                                                      \
+    }
+#endif /* PWM_TMRA_7_CONFIG */
+#endif /* BSP_USING_PWM_TMRA_7 */
+
+#ifdef BSP_USING_PWM_TMRA_8
+#ifndef PWM_TMRA_8_CONFIG
+#define PWM_TMRA_8_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_a8",             \
+        .instance                       = CM_TMRA_8,            \
+        .channel                        = 0,                    \
+        .stcTmraInit =                                          \
+        {                                                       \
+            .u8CountSrc                 = TMRA_CNT_SRC_SW,      \
+            .u32PeriodValue             = 0xFFFF,               \
+            .sw_count =                                         \
+            {                                                   \
+                .u8ClockDiv             = TMRA_CLK_DIV1,        \
+                .u8CountMode            = TMRA_MD_SAWTOOTH,     \
+                .u8CountDir             = TMRA_DIR_DOWN,        \
+            },                                                  \
+            .u8CountReload              = TMRA_CNT_RELOAD_ENABLE\
+        },                                                      \
+        .stcPwmInit =                                           \
+        {                                                       \
+            .u32CompareValue            = 0x0000,               \
+            .u16StartPolarity           = TMRA_PWM_LOW,         \
+            .u16StopPolarity            = TMRA_PWM_LOW,         \
+            .u16CompareMatchPolarity    = TMRA_PWM_HIGH,        \
+            .u16PeriodMatchPolarity     = TMRA_PWM_LOW,         \
+        },                                                      \
+    }
+#endif /* PWM_TMRA_8_CONFIG */
+#endif /* BSP_USING_PWM_TMRA_8 */
+
+#ifdef BSP_USING_PWM_TMRA_9
+#ifndef PWM_TMRA_9_CONFIG
+#define PWM_TMRA_9_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_a9",             \
+        .instance                       = CM_TMRA_9,            \
+        .channel                        = 0,                    \
+        .stcTmraInit =                                          \
+        {                                                       \
+            .u8CountSrc                 = TMRA_CNT_SRC_SW,      \
+            .u32PeriodValue             = 0xFFFF,               \
+            .sw_count =                                         \
+            {                                                   \
+                .u8ClockDiv             = TMRA_CLK_DIV1,        \
+                .u8CountMode            = TMRA_MD_SAWTOOTH,     \
+                .u8CountDir             = TMRA_DIR_DOWN,        \
+            },                                                  \
+            .u8CountReload              = TMRA_CNT_RELOAD_ENABLE\
+        },                                                      \
+        .stcPwmInit =                                           \
+        {                                                       \
+            .u32CompareValue            = 0x0000,               \
+            .u16StartPolarity           = TMRA_PWM_LOW,         \
+            .u16StopPolarity            = TMRA_PWM_LOW,         \
+            .u16CompareMatchPolarity    = TMRA_PWM_HIGH,        \
+            .u16PeriodMatchPolarity     = TMRA_PWM_LOW,         \
+        },                                                      \
+    }
+#endif /* PWM_TMRA_9_CONFIG */
+#endif /* BSP_USING_PWM_TMRA_9 */
+
+#ifdef BSP_USING_PWM_TMRA_10
+#ifndef PWM_TMRA_10_CONFIG
+#define PWM_TMRA_10_CONFIG                                      \
+    {                                                           \
+        .name                           = "pwm_a10",            \
+        .instance                       = CM_TMRA_10,           \
+        .channel                        = 0,                    \
+        .stcTmraInit =                                          \
+        {                                                       \
+            .u8CountSrc                 = TMRA_CNT_SRC_SW,      \
+            .u32PeriodValue             = 0xFFFF,               \
+            .sw_count =                                         \
+            {                                                   \
+                .u8ClockDiv             = TMRA_CLK_DIV1,        \
+                .u8CountMode            = TMRA_MD_SAWTOOTH,     \
+                .u8CountDir             = TMRA_DIR_DOWN,        \
+            },                                                  \
+            .u8CountReload              = TMRA_CNT_RELOAD_ENABLE\
+        },                                                      \
+        .stcPwmInit =                                           \
+        {                                                       \
+            .u32CompareValue            = 0x0000,               \
+            .u16StartPolarity           = TMRA_PWM_LOW,         \
+            .u16StopPolarity            = TMRA_PWM_LOW,         \
+            .u16CompareMatchPolarity    = TMRA_PWM_HIGH,        \
+            .u16PeriodMatchPolarity     = TMRA_PWM_LOW,         \
+        },                                                      \
+    }
+#endif /* PWM_TMRA_10_CONFIG */
+#endif /* BSP_USING_PWM_TMRA_10 */
+
+#ifdef BSP_USING_PWM_TMRA_11
+#ifndef PWM_TMRA_11_CONFIG
+#define PWM_TMRA_11_CONFIG                                      \
+    {                                                           \
+        .name                           = "pwm_a11",            \
+        .instance                       = CM_TMRA_11,           \
+        .channel                        = 0,                    \
+        .stcTmraInit =                                          \
+        {                                                       \
+            .u8CountSrc                 = TMRA_CNT_SRC_SW,      \
+            .u32PeriodValue             = 0xFFFF,               \
+            .sw_count =                                         \
+            {                                                   \
+                .u8ClockDiv             = TMRA_CLK_DIV1,        \
+                .u8CountMode            = TMRA_MD_SAWTOOTH,     \
+                .u8CountDir             = TMRA_DIR_DOWN,        \
+            },                                                  \
+            .u8CountReload              = TMRA_CNT_RELOAD_ENABLE\
+        },                                                      \
+        .stcPwmInit =                                           \
+        {                                                       \
+            .u32CompareValue            = 0x0000,               \
+            .u16StartPolarity           = TMRA_PWM_LOW,         \
+            .u16StopPolarity            = TMRA_PWM_LOW,         \
+            .u16CompareMatchPolarity    = TMRA_PWM_HIGH,        \
+            .u16PeriodMatchPolarity     = TMRA_PWM_LOW,         \
+        },                                                      \
+    }
+#endif /* PWM_TMRA_11_CONFIG */
+#endif /* BSP_USING_PWM_TMRA_11 */
+
+#ifdef BSP_USING_PWM_TMRA_12
+#ifndef PWM_TMRA_12_CONFIG
+#define PWM_TMRA_12_CONFIG                                      \
+    {                                                           \
+        .name                           = "pwm_a12",            \
+        .instance                       = CM_TMRA_12,           \
+        .channel                        = 0,                    \
+        .stcTmraInit =                                          \
+        {                                                       \
+            .u8CountSrc                 = TMRA_CNT_SRC_SW,      \
+            .u32PeriodValue             = 0xFFFF,               \
+            .sw_count =                                         \
+            {                                                   \
+                .u8ClockDiv             = TMRA_CLK_DIV1,        \
+                .u8CountMode            = TMRA_MD_SAWTOOTH,     \
+                .u8CountDir             = TMRA_DIR_DOWN,        \
+            },                                                  \
+            .u8CountReload              = TMRA_CNT_RELOAD_ENABLE\
+        },                                                      \
+        .stcPwmInit =                                           \
+        {                                                       \
+            .u32CompareValue            = 0x0000,               \
+            .u16StartPolarity           = TMRA_PWM_LOW,         \
+            .u16StopPolarity            = TMRA_PWM_LOW,         \
+            .u16CompareMatchPolarity    = TMRA_PWM_HIGH,        \
+            .u16PeriodMatchPolarity     = TMRA_PWM_LOW,         \
+        },                                                      \
+    }
+#endif /* PWM_TMRA_12_CONFIG */
+#endif /* BSP_USING_PWM_TMRA_12 */
+
+#endif /* BSP_USING_PWM_TMRA */
+
+#ifdef BSP_USING_PWM_TMR4
+
+#ifdef BSP_USING_PWM_TMR4_1
+#ifndef PWM_TMR4_1_CONFIG
+#define PWM_TMR4_1_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_t41",            \
+        .instance                       = CM_TMR4_1,            \
+        .channel                        = 0,                    \
+        .stcTmr4Init =                                          \
+        {                                                       \
+            .u16ClockDiv                = TMR4_CLK_DIV1,        \
+            .u16PeriodValue             = 0xFFFFU,              \
+            .u16CountMode               = TMR4_MD_SAWTOOTH,     \
+            .u16ClockSrc               = TMR4_CLK_SRC_INTERNCLK,\
+        },                                                      \
+        .stcTmr4OcInit =                                        \
+        {                                                       \
+            .u16CompareValue            = 0x0000,               \
+            .u16OcInvalidPolarity       = TMR4_OC_INVD_LOW,     \
+            .u16CompareModeBufCond     = TMR4_OC_BUF_COND_IMMED,\
+            .u16CompareValueBufCond    = TMR4_OC_BUF_COND_PEAK, \
+            .u16BufLinkTransObject      = 0U,                   \
+        },                                                      \
+        .stcTmr4PwmInit =                                       \
+        {                                                       \
+            .u16Mode                    = TMR4_PWM_MD_THROUGH,  \
+            .u16ClockDiv                = TMR4_PWM_CLK_DIV1,    \
+            .u16Polarity           = TMR4_PWM_OXH_HOLD_OXL_HOLD,\
+        },                                                      \
+    }
+#endif /* PWM_TMR4_1_CONFIG */
+#endif /* BSP_USING_PWM_TMR4_1 */
+
+#ifdef BSP_USING_PWM_TMR4_2
+#ifndef PWM_TMR4_2_CONFIG
+#define PWM_TMR4_2_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_t42",            \
+        .instance                       = CM_TMR4_2,            \
+        .channel                        = 0,                    \
+        .stcTmr4Init =                                          \
+        {                                                       \
+            .u16ClockDiv                = TMR4_CLK_DIV1,        \
+            .u16PeriodValue             = 0xFFFFU,              \
+            .u16CountMode               = TMR4_MD_SAWTOOTH,     \
+            .u16ClockSrc               = TMR4_CLK_SRC_INTERNCLK,\
+        },                                                      \
+        .stcTmr4OcInit =                                        \
+        {                                                       \
+            .u16CompareValue            = 0x0000,               \
+            .u16OcInvalidPolarity       = TMR4_OC_INVD_LOW,     \
+            .u16CompareModeBufCond     = TMR4_OC_BUF_COND_IMMED,\
+            .u16CompareValueBufCond    = TMR4_OC_BUF_COND_PEAK, \
+            .u16BufLinkTransObject      = 0U,                   \
+        },                                                      \
+        .stcTmr4PwmInit =                                       \
+        {                                                       \
+            .u16Mode                    = TMR4_PWM_MD_THROUGH,  \
+            .u16ClockDiv                = TMR4_PWM_CLK_DIV1,    \
+            .u16Polarity           = TMR4_PWM_OXH_HOLD_OXL_HOLD,\
+        },                                                      \
+    }
+#endif /* PWM_TMR4_2_CONFIG */
+#endif /* BSP_USING_PWM_TMR4_2 */
+
+#ifdef BSP_USING_PWM_TMR4_3
+#ifndef PWM_TMR4_3_CONFIG
+#define PWM_TMR4_3_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_t43",            \
+        .instance                       = CM_TMR4_3,            \
+        .channel                        = 0,                    \
+        .stcTmr4Init =                                          \
+        {                                                       \
+            .u16ClockDiv                = TMR4_CLK_DIV1,        \
+            .u16PeriodValue             = 0xFFFFU,              \
+            .u16CountMode               = TMR4_MD_SAWTOOTH,     \
+            .u16ClockSrc               = TMR4_CLK_SRC_INTERNCLK,\
+        },                                                      \
+        .stcTmr4OcInit =                                        \
+        {                                                       \
+            .u16CompareValue            = 0x0000,               \
+            .u16OcInvalidPolarity       = TMR4_OC_INVD_LOW,     \
+            .u16CompareModeBufCond     = TMR4_OC_BUF_COND_IMMED,\
+            .u16CompareValueBufCond    = TMR4_OC_BUF_COND_PEAK, \
+            .u16BufLinkTransObject      = 0U,                   \
+        },                                                      \
+        .stcTmr4PwmInit =                                       \
+        {                                                       \
+            .u16Mode                    = TMR4_PWM_MD_THROUGH,  \
+            .u16ClockDiv                = TMR4_PWM_CLK_DIV1,    \
+            .u16Polarity           = TMR4_PWM_OXH_HOLD_OXL_HOLD,\
+        },                                                      \
+    }
+#endif /* PWM_TMR4_3_CONFIG */
+#endif /* BSP_USING_PWM_TMR4_3 */
+
+#endif /* BSP_USING_PWM_TMR4 */
+
+#ifdef BSP_USING_PWM_TMR6
+
+#ifdef BSP_USING_PWM_TMR6_1
+#ifndef PWM_TMR6_1_CONFIG
+#define PWM_TMR6_1_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_t61",            \
+        .instance                       = CM_TMR6_1,            \
+        .channel                        = 0,                    \
+        .stcTmr6Init =                                          \
+        {                                                       \
+            .u8CountSrc                 = TMR6_CNT_SRC_SW,      \
+            .sw_count =                                         \
+            {                                                   \
+                .u32ClockDiv            = TMR6_CLK_DIV1,        \
+                .u32CountMode           = TMR6_MD_SAWTOOTH,     \
+                .u32CountDir            = TMR6_CNT_DOWN,        \
+            },                                                  \
+            .u32PeriodValue             = 0xFFFF,               \
+            .u32CountReload             = TMR6_CNT_RELOAD_ON,   \
+        },                                                      \
+        .stcPwmInit =                                           \
+        {                                                       \
+            {                                                   \
+                .u32CompareValue            = 0x0000,           \
+                .u32StartPolarity           = TMR6_PWM_LOW,     \
+                .u32StopPolarity            = TMR6_PWM_LOW,     \
+                .u32CountUpMatchAPolarity   = TMR6_PWM_HIGH,    \
+                .u32CountDownMatchAPolarity = TMR6_PWM_HIGH,    \
+                .u32CountUpMatchBPolarity   = TMR6_PWM_HOLD,    \
+                .u32CountDownMatchBPolarity = TMR6_PWM_HOLD,    \
+                .u32UdfPolarity             = TMR6_PWM_LOW,     \
+                .u32OvfPolarity             = TMR6_PWM_LOW,     \
+            },                                                  \
+            {                                                   \
+                .u32CompareValue            = 0x0000,           \
+                .u32StartPolarity           = TMR6_PWM_LOW,     \
+                .u32StopPolarity            = TMR6_PWM_LOW,     \
+                .u32CountUpMatchAPolarity   = TMR6_PWM_HOLD,    \
+                .u32CountDownMatchAPolarity = TMR6_PWM_HOLD,    \
+                .u32CountUpMatchBPolarity   = TMR6_PWM_HIGH,    \
+                .u32CountDownMatchBPolarity = TMR6_PWM_HIGH,    \
+                .u32UdfPolarity             = TMR6_PWM_LOW,     \
+                .u32OvfPolarity             = TMR6_PWM_LOW,     \
+            }                                                   \
+        },                                                      \
+    }
+#endif /* PWM_TMR6_1_CONFIG */
+#endif /* BSP_USING_PWM_TMR6_1 */
+#ifdef BSP_USING_PWM_TMR6_2
+#ifndef PWM_TMR6_2_CONFIG
+#define PWM_TMR6_2_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_t61",            \
+        .instance                       = CM_TMR6_2,            \
+        .channel                        = 0,                    \
+        .stcTmr6Init =                                          \
+        {                                                       \
+            .u8CountSrc                 = TMR6_CNT_SRC_SW,      \
+            .sw_count =                                         \
+            {                                                   \
+                .u32ClockDiv            = TMR6_CLK_DIV1,        \
+                .u32CountMode           = TMR6_MD_SAWTOOTH,     \
+                .u32CountDir            = TMR6_CNT_DOWN,        \
+            },                                                  \
+            .u32PeriodValue             = 0xFFFF,               \
+            .u32CountReload             = TMR6_CNT_RELOAD_ON,   \
+        },                                                      \
+        .stcPwmInit =                                           \
+        {                                                       \
+            {                                                   \
+                .u32CompareValue            = 0x0000,           \
+                .u32StartPolarity           = TMR6_PWM_LOW,     \
+                .u32StopPolarity            = TMR6_PWM_LOW,     \
+                .u32CountUpMatchAPolarity   = TMR6_PWM_HIGH,    \
+                .u32CountDownMatchAPolarity = TMR6_PWM_HIGH,    \
+                .u32CountUpMatchBPolarity   = TMR6_PWM_HOLD,    \
+                .u32CountDownMatchBPolarity = TMR6_PWM_HOLD,    \
+                .u32UdfPolarity             = TMR6_PWM_LOW,     \
+                .u32OvfPolarity             = TMR6_PWM_LOW,     \
+            },                                                  \
+            {                                                   \
+                .u32CompareValue            = 0x0000,           \
+                .u32StartPolarity           = TMR6_PWM_LOW,     \
+                .u32StopPolarity            = TMR6_PWM_LOW,     \
+                .u32CountUpMatchAPolarity   = TMR6_PWM_HOLD,    \
+                .u32CountDownMatchAPolarity = TMR6_PWM_HOLD,    \
+                .u32CountUpMatchBPolarity   = TMR6_PWM_HIGH,    \
+                .u32CountDownMatchBPolarity = TMR6_PWM_HIGH,    \
+                .u32UdfPolarity             = TMR6_PWM_LOW,     \
+                .u32OvfPolarity             = TMR6_PWM_LOW,     \
+            }                                                   \
+        },                                                      \
+    }
+#endif /* PWM_TMR6_2_CONFIG */
+#endif /* BSP_USING_PWM_TMR6_2 */
+#ifdef BSP_USING_PWM_TMR6_3
+#ifndef PWM_TMR6_3_CONFIG
+#define PWM_TMR6_3_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_t61",            \
+        .instance                       = CM_TMR6_3,            \
+        .channel                        = 0,                    \
+        .stcTmr6Init =                                          \
+        {                                                       \
+            .u8CountSrc                 = TMR6_CNT_SRC_SW,      \
+            .sw_count =                                         \
+            {                                                   \
+                .u32ClockDiv            = TMR6_CLK_DIV1,        \
+                .u32CountMode           = TMR6_MD_SAWTOOTH,     \
+                .u32CountDir            = TMR6_CNT_DOWN,        \
+            },                                                  \
+            .u32PeriodValue             = 0xFFFF,               \
+            .u32CountReload             = TMR6_CNT_RELOAD_ON,   \
+        },                                                      \
+        .stcPwmInit =                                           \
+        {                                                       \
+            {                                                   \
+                .u32CompareValue            = 0x0000,           \
+                .u32StartPolarity           = TMR6_PWM_LOW,     \
+                .u32StopPolarity            = TMR6_PWM_LOW,     \
+                .u32CountUpMatchAPolarity   = TMR6_PWM_HIGH,    \
+                .u32CountDownMatchAPolarity = TMR6_PWM_HIGH,    \
+                .u32CountUpMatchBPolarity   = TMR6_PWM_HOLD,    \
+                .u32CountDownMatchBPolarity = TMR6_PWM_HOLD,    \
+                .u32UdfPolarity             = TMR6_PWM_LOW,     \
+                .u32OvfPolarity             = TMR6_PWM_LOW,     \
+            },                                                  \
+            {                                                   \
+                .u32CompareValue            = 0x0000,           \
+                .u32StartPolarity           = TMR6_PWM_LOW,     \
+                .u32StopPolarity            = TMR6_PWM_LOW,     \
+                .u32CountUpMatchAPolarity   = TMR6_PWM_HOLD,    \
+                .u32CountDownMatchAPolarity = TMR6_PWM_HOLD,    \
+                .u32CountUpMatchBPolarity   = TMR6_PWM_HIGH,    \
+                .u32CountDownMatchBPolarity = TMR6_PWM_HIGH,    \
+                .u32UdfPolarity             = TMR6_PWM_LOW,     \
+                .u32OvfPolarity             = TMR6_PWM_LOW,     \
+            }                                                   \
+        },                                                      \
+    }
+#endif /* PWM_TMR6_3_CONFIG */
+#endif /* BSP_USING_PWM_TMR6_3 */
+#ifdef BSP_USING_PWM_TMR6_4
+#ifndef PWM_TMR6_4_CONFIG
+#define PWM_TMR6_4_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_t61",            \
+        .instance                       = CM_TMR6_4,            \
+        .channel                        = 0,                    \
+        .stcTmr6Init =                                          \
+        {                                                       \
+            .u8CountSrc                 = TMR6_CNT_SRC_SW,      \
+            .sw_count =                                         \
+            {                                                   \
+                .u32ClockDiv            = TMR6_CLK_DIV1,        \
+                .u32CountMode           = TMR6_MD_SAWTOOTH,     \
+                .u32CountDir            = TMR6_CNT_DOWN,        \
+            },                                                  \
+            .u32PeriodValue             = 0xFFFF,               \
+            .u32CountReload             = TMR6_CNT_RELOAD_ON,   \
+        },                                                      \
+        .stcPwmInit =                                           \
+        {                                                       \
+            {                                                   \
+                .u32CompareValue            = 0x0000,           \
+                .u32StartPolarity           = TMR6_PWM_LOW,     \
+                .u32StopPolarity            = TMR6_PWM_LOW,     \
+                .u32CountUpMatchAPolarity   = TMR6_PWM_HIGH,    \
+                .u32CountDownMatchAPolarity = TMR6_PWM_HIGH,    \
+                .u32CountUpMatchBPolarity   = TMR6_PWM_HOLD,    \
+                .u32CountDownMatchBPolarity = TMR6_PWM_HOLD,    \
+                .u32UdfPolarity             = TMR6_PWM_LOW,     \
+                .u32OvfPolarity             = TMR6_PWM_LOW,     \
+            },                                                  \
+            {                                                   \
+                .u32CompareValue            = 0x0000,           \
+                .u32StartPolarity           = TMR6_PWM_LOW,     \
+                .u32StopPolarity            = TMR6_PWM_LOW,     \
+                .u32CountUpMatchAPolarity   = TMR6_PWM_HOLD,    \
+                .u32CountDownMatchAPolarity = TMR6_PWM_HOLD,    \
+                .u32CountUpMatchBPolarity   = TMR6_PWM_HIGH,    \
+                .u32CountDownMatchBPolarity = TMR6_PWM_HIGH,    \
+                .u32UdfPolarity             = TMR6_PWM_LOW,     \
+                .u32OvfPolarity             = TMR6_PWM_LOW,     \
+            }                                                   \
+        },                                                      \
+    }
+#endif /* PWM_TMR6_4_CONFIG */
+#endif /* BSP_USING_PWM_TMR6_4 */
+#ifdef BSP_USING_PWM_TMR6_5
+#ifndef PWM_TMR6_5_CONFIG
+#define PWM_TMR6_5_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_t61",            \
+        .instance                       = CM_TMR6_5,            \
+        .channel                        = 0,                    \
+        .stcTmr6Init =                                          \
+        {                                                       \
+            .u8CountSrc                 = TMR6_CNT_SRC_SW,      \
+            .sw_count =                                         \
+            {                                                   \
+                .u32ClockDiv            = TMR6_CLK_DIV1,        \
+                .u32CountMode           = TMR6_MD_SAWTOOTH,     \
+                .u32CountDir            = TMR6_CNT_DOWN,        \
+            },                                                  \
+            .u32PeriodValue             = 0xFFFF,               \
+            .u32CountReload             = TMR6_CNT_RELOAD_ON,   \
+        },                                                      \
+        .stcPwmInit =                                           \
+        {                                                       \
+            {                                                   \
+                .u32CompareValue            = 0x0000,           \
+                .u32StartPolarity           = TMR6_PWM_LOW,     \
+                .u32StopPolarity            = TMR6_PWM_LOW,     \
+                .u32CountUpMatchAPolarity   = TMR6_PWM_HIGH,    \
+                .u32CountDownMatchAPolarity = TMR6_PWM_HIGH,    \
+                .u32CountUpMatchBPolarity   = TMR6_PWM_HOLD,    \
+                .u32CountDownMatchBPolarity = TMR6_PWM_HOLD,    \
+                .u32UdfPolarity             = TMR6_PWM_LOW,     \
+                .u32OvfPolarity             = TMR6_PWM_LOW,     \
+            },                                                  \
+            {                                                   \
+                .u32CompareValue            = 0x0000,           \
+                .u32StartPolarity           = TMR6_PWM_LOW,     \
+                .u32StopPolarity            = TMR6_PWM_LOW,     \
+                .u32CountUpMatchAPolarity   = TMR6_PWM_HOLD,    \
+                .u32CountDownMatchAPolarity = TMR6_PWM_HOLD,    \
+                .u32CountUpMatchBPolarity   = TMR6_PWM_HIGH,    \
+                .u32CountDownMatchBPolarity = TMR6_PWM_HIGH,    \
+                .u32UdfPolarity             = TMR6_PWM_LOW,     \
+                .u32OvfPolarity             = TMR6_PWM_LOW,     \
+            }                                                   \
+        },                                                      \
+    }
+#endif /* PWM_TMR6_5_CONFIG */
+#endif /* BSP_USING_PWM_TMR6_5 */
+#ifdef BSP_USING_PWM_TMR6_6
+#ifndef PWM_TMR6_6_CONFIG
+#define PWM_TMR6_6_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_t61",            \
+        .instance                       = CM_TMR6_6,            \
+        .channel                        = 0,                    \
+        .stcTmr6Init =                                          \
+        {                                                       \
+            .u8CountSrc                 = TMR6_CNT_SRC_SW,      \
+            .sw_count =                                         \
+            {                                                   \
+                .u32ClockDiv            = TMR6_CLK_DIV1,        \
+                .u32CountMode           = TMR6_MD_SAWTOOTH,     \
+                .u32CountDir            = TMR6_CNT_DOWN,        \
+            },                                                  \
+            .u32PeriodValue             = 0xFFFF,               \
+            .u32CountReload             = TMR6_CNT_RELOAD_ON,   \
+        },                                                      \
+        .stcPwmInit =                                           \
+        {                                                       \
+            {                                                   \
+                .u32CompareValue            = 0x0000,           \
+                .u32StartPolarity           = TMR6_PWM_LOW,     \
+                .u32StopPolarity            = TMR6_PWM_LOW,     \
+                .u32CountUpMatchAPolarity   = TMR6_PWM_HIGH,    \
+                .u32CountDownMatchAPolarity = TMR6_PWM_HIGH,    \
+                .u32CountUpMatchBPolarity   = TMR6_PWM_HOLD,    \
+                .u32CountDownMatchBPolarity = TMR6_PWM_HOLD,    \
+                .u32UdfPolarity             = TMR6_PWM_LOW,     \
+                .u32OvfPolarity             = TMR6_PWM_LOW,     \
+            },                                                  \
+            {                                                   \
+                .u32CompareValue            = 0x0000,           \
+                .u32StartPolarity           = TMR6_PWM_LOW,     \
+                .u32StopPolarity            = TMR6_PWM_LOW,     \
+                .u32CountUpMatchAPolarity   = TMR6_PWM_HOLD,    \
+                .u32CountDownMatchAPolarity = TMR6_PWM_HOLD,    \
+                .u32CountUpMatchBPolarity   = TMR6_PWM_HIGH,    \
+                .u32CountDownMatchBPolarity = TMR6_PWM_HIGH,    \
+                .u32UdfPolarity             = TMR6_PWM_LOW,     \
+                .u32OvfPolarity             = TMR6_PWM_LOW,     \
+            }                                                   \
+        },                                                      \
+    }
+#endif /* PWM_TMR6_6_CONFIG */
+#endif /* BSP_USING_PWM_TMR6_6 */
+#ifdef BSP_USING_PWM_TMR6_7
+#ifndef PWM_TMR6_7_CONFIG
+#define PWM_TMR6_7_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_t61",            \
+        .instance                       = CM_TMR6_7,            \
+        .channel                        = 0,                    \
+        .stcTmr6Init =                                          \
+        {                                                       \
+            .u8CountSrc                 = TMR6_CNT_SRC_SW,      \
+            .sw_count =                                         \
+            {                                                   \
+                .u32ClockDiv            = TMR6_CLK_DIV1,        \
+                .u32CountMode           = TMR6_MD_SAWTOOTH,     \
+                .u32CountDir            = TMR6_CNT_DOWN,        \
+            },                                                  \
+            .u32PeriodValue             = 0xFFFF,               \
+            .u32CountReload             = TMR6_CNT_RELOAD_ON,   \
+        },                                                      \
+        .stcPwmInit =                                           \
+        {                                                       \
+            {                                                   \
+                .u32CompareValue            = 0x0000,           \
+                .u32StartPolarity           = TMR6_PWM_LOW,     \
+                .u32StopPolarity            = TMR6_PWM_LOW,     \
+                .u32CountUpMatchAPolarity   = TMR6_PWM_HIGH,    \
+                .u32CountDownMatchAPolarity = TMR6_PWM_HIGH,    \
+                .u32CountUpMatchBPolarity   = TMR6_PWM_HOLD,    \
+                .u32CountDownMatchBPolarity = TMR6_PWM_HOLD,    \
+                .u32UdfPolarity             = TMR6_PWM_LOW,     \
+                .u32OvfPolarity             = TMR6_PWM_LOW,     \
+            },                                                  \
+            {                                                   \
+                .u32CompareValue            = 0x0000,           \
+                .u32StartPolarity           = TMR6_PWM_LOW,     \
+                .u32StopPolarity            = TMR6_PWM_LOW,     \
+                .u32CountUpMatchAPolarity   = TMR6_PWM_HOLD,    \
+                .u32CountDownMatchAPolarity = TMR6_PWM_HOLD,    \
+                .u32CountUpMatchBPolarity   = TMR6_PWM_HIGH,    \
+                .u32CountDownMatchBPolarity = TMR6_PWM_HIGH,    \
+                .u32UdfPolarity             = TMR6_PWM_LOW,     \
+                .u32OvfPolarity             = TMR6_PWM_LOW,     \
+            }                                                   \
+        },                                                      \
+    }
+#endif /* PWM_TMR6_7_CONFIG */
+#endif /* BSP_USING_PWM_TMR6_7 */
+#ifdef BSP_USING_PWM_TMR6_8
+#ifndef PWM_TMR6_8_CONFIG
+#define PWM_TMR6_8_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_t61",            \
+        .instance                       = CM_TMR6_8,            \
+        .channel                        = 0,                    \
+        .stcTmr6Init =                                          \
+        {                                                       \
+            .u8CountSrc                 = TMR6_CNT_SRC_SW,      \
+            .sw_count =                                         \
+            {                                                   \
+                .u32ClockDiv            = TMR6_CLK_DIV1,        \
+                .u32CountMode           = TMR6_MD_SAWTOOTH,     \
+                .u32CountDir            = TMR6_CNT_DOWN,        \
+            },                                                  \
+            .u32PeriodValue             = 0xFFFF,               \
+            .u32CountReload             = TMR6_CNT_RELOAD_ON,   \
+        },                                                      \
+        .stcPwmInit =                                           \
+        {                                                       \
+            {                                                   \
+                .u32CompareValue            = 0x0000,           \
+                .u32StartPolarity           = TMR6_PWM_LOW,     \
+                .u32StopPolarity            = TMR6_PWM_LOW,     \
+                .u32CountUpMatchAPolarity   = TMR6_PWM_HIGH,    \
+                .u32CountDownMatchAPolarity = TMR6_PWM_HIGH,    \
+                .u32CountUpMatchBPolarity   = TMR6_PWM_HOLD,    \
+                .u32CountDownMatchBPolarity = TMR6_PWM_HOLD,    \
+                .u32UdfPolarity             = TMR6_PWM_LOW,     \
+                .u32OvfPolarity             = TMR6_PWM_LOW,     \
+            },                                                  \
+            {                                                   \
+                .u32CompareValue            = 0x0000,           \
+                .u32StartPolarity           = TMR6_PWM_LOW,     \
+                .u32StopPolarity            = TMR6_PWM_LOW,     \
+                .u32CountUpMatchAPolarity   = TMR6_PWM_HOLD,    \
+                .u32CountDownMatchAPolarity = TMR6_PWM_HOLD,    \
+                .u32CountUpMatchBPolarity   = TMR6_PWM_HIGH,    \
+                .u32CountDownMatchBPolarity = TMR6_PWM_HIGH,    \
+                .u32UdfPolarity             = TMR6_PWM_LOW,     \
+                .u32OvfPolarity             = TMR6_PWM_LOW,     \
+            }                                                   \
+        },                                                      \
+    }
+#endif /* PWM_TMR6_8_CONFIG */
+#endif /* BSP_USING_PWM_TMR6_8 */
+
+#endif /* BSP_USING_PWM_TMR6 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PWM_TMRA_CONFIG_H__ */

bsp/hc32/ev_hc32f448_lqfp80/board/config/qspi_config.h

@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-02-20     CDT          first version
+ */
+
+#ifndef __QSPI_CONFIG_H__
+#define __QSPI_CONFIG_H__
+
+#include <rtthread.h>
+#include "irq_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_QSPI
+#ifndef QSPI_BUS_CONFIG
+#define QSPI_BUS_CONFIG                                     \
+    {                                                       \
+        .Instance = CM_QSPI,                                \
+        .clock    = FCG1_PERIPH_QSPI,                       \
+        .timeout  = 5000UL,                                 \
+        .err_irq.irq_config =                               \
+        {                                                   \
+            .irq_num    = BSP_QSPI_ERR_IRQ_NUM,             \
+            .irq_prio   = BSP_QSPI_ERR_IRQ_PRIO,            \
+            .int_src    = INT_SRC_QSPI_INTR,                \
+        },                                                  \
+    }
+#endif /* QSPI_BUS_CONFIG */
+
+#ifndef QSPI_INIT_PARAMS
+#define QSPI_INIT_PARAMS                                        \
+    {                                                           \
+        .u32PrefetchMode   = QSPI_PREFETCH_MD_INVD,             \
+        .u32SetupTime      = QSPI_QSSN_SETUP_ADVANCE_QSCK0P5,   \
+        .u32ReleaseTime    = QSPI_QSSN_RELEASE_DELAY_QSCK32,    \
+        .u32IntervalTime   = QSPI_QSSN_INTERVAL_QSCK1,          \
+    }
+#endif /* QSPI_INIT_PARAMS */
+
+#define QSPI_WP_PIN_LEVEL               QSPI_WP_PIN_HIGH
+
+#ifdef BSP_QSPI_USING_DMA
+#ifndef QSPI_DMA_CONFIG
+#define QSPI_DMA_CONFIG                                     \
+    {                                                       \
+        .Instance       = QSPI_DMA_INSTANCE,                \
+        .channel        = QSPI_DMA_CHANNEL,                 \
+        .clock          = QSPI_DMA_CLOCK,                   \
+        .trigger_select = QSPI_DMA_TRIG_SELECT,             \
+        .trigger_event  = EVT_SRC_AOS_STRG,                 \
+        .flag           = QSPI_DMA_TRANS_FLAG,              \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = QSPI_DMA_IRQn,                    \
+            .irq_prio   = QSPI_DMA_INT_PRIO,                \
+            .int_src    = QSPI_DMA_INT_SRC,                 \
+        }                                                   \
+    }
+#endif /* QSPI_DMA_CONFIG */
+#endif /* BSP_QSPI_USING_DMA */
+#endif /* BSP_USING_SPI1 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__QSPI_CONFIG_H__ */

bsp/hc32/ev_hc32f448_lqfp80/board/config/spi_config.h

@@ -0,0 +1,377 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-02-20     CDT          first version
+ */
+
+#ifndef __SPI_CONFIG_H__
+#define __SPI_CONFIG_H__
+
+#include <rtthread.h>
+#include "irq_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#ifdef BSP_USING_SPI1
+#ifndef SPI1_BUS_CONFIG
+#define SPI1_BUS_CONFIG                                     \
+    {                                                       \
+        .Instance = CM_SPI1,                                \
+        .bus_name = "spi1",                                 \
+        .clock    = FCG1_PERIPH_SPI1,                       \
+        .timeout  = 5000UL,                                 \
+        .err_irq.irq_config =                               \
+        {                                                   \
+            .irq_num    = BSP_SPI1_ERR_IRQ_NUM,             \
+            .irq_prio   = BSP_SPI1_ERR_IRQ_PRIO,            \
+            .int_src    = INT_SRC_SPI1_SPEI,                \
+        },                                                  \
+    }
+#endif /* SPI1_BUS_CONFIG */
+#endif /* BSP_USING_SPI1 */
+
+#ifdef BSP_SPI1_TX_USING_DMA
+#ifndef SPI1_TX_DMA_CONFIG
+#define SPI1_TX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI1_TX_DMA_INSTANCE,             \
+        .channel        = SPI1_TX_DMA_CHANNEL,              \
+        .clock          = SPI1_TX_DMA_CLOCK,                \
+        .trigger_select = SPI1_TX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI1_SPTI,                \
+        .flag           = SPI1_TX_DMA_TRANS_FLAG,           \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI1_TX_DMA_IRQn,                 \
+            .irq_prio   = SPI1_TX_DMA_INT_PRIO,             \
+            .int_src    = SPI1_TX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI1_TX_DMA_CONFIG */
+#endif /* BSP_SPI1_TX_USING_DMA */
+
+#ifdef BSP_SPI1_RX_USING_DMA
+#ifndef SPI1_RX_DMA_CONFIG
+#define SPI1_RX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI1_RX_DMA_INSTANCE,             \
+        .channel        = SPI1_RX_DMA_CHANNEL,              \
+        .clock          = SPI1_RX_DMA_CLOCK,                \
+        .trigger_select = SPI1_RX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI1_SPRI,                \
+        .flag           = SPI1_RX_DMA_TRANS_FLAG,           \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI1_RX_DMA_IRQn,                 \
+            .irq_prio   = SPI1_RX_DMA_INT_PRIO,             \
+            .int_src    = SPI1_RX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI1_RX_DMA_CONFIG */
+#endif /* BSP_SPI1_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI2
+#ifndef SPI2_BUS_CONFIG
+#define SPI2_BUS_CONFIG                                     \
+    {                                                       \
+        .Instance = CM_SPI2,                                \
+        .bus_name = "spi2",                                 \
+        .clock    = FCG1_PERIPH_SPI2,                       \
+        .timeout  = 5000UL,                                 \
+        .err_irq.irq_config =                               \
+        {                                                   \
+            .irq_num    = BSP_SPI2_ERR_IRQ_NUM,             \
+            .irq_prio   = BSP_SPI2_ERR_IRQ_PRIO,            \
+            .int_src    = INT_SRC_SPI2_SPEI,                \
+        },                                                  \
+    }
+#endif /* SPI2_BUS_CONFIG */
+#endif /* BSP_USING_SPI2 */
+
+#ifdef BSP_SPI2_TX_USING_DMA
+#ifndef SPI2_TX_DMA_CONFIG
+#define SPI2_TX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI2_TX_DMA_INSTANCE,             \
+        .channel        = SPI2_TX_DMA_CHANNEL,              \
+        .clock          = SPI2_TX_DMA_CLOCK,                \
+        .trigger_select = SPI2_TX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI2_SPTI,                \
+        .flag           = SPI2_TX_DMA_TRANS_FLAG,           \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI2_TX_DMA_IRQn,                 \
+            .irq_prio   = SPI2_TX_DMA_INT_PRIO,             \
+            .int_src    = SPI2_TX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI2_TX_DMA_CONFIG */
+#endif /* BSP_SPI2_TX_USING_DMA */
+
+#ifdef BSP_SPI2_RX_USING_DMA
+#ifndef SPI2_RX_DMA_CONFIG
+#define SPI2_RX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI2_RX_DMA_INSTANCE,             \
+        .channel        = SPI2_RX_DMA_CHANNEL,              \
+        .clock          = SPI2_RX_DMA_CLOCK,                \
+        .trigger_select = SPI2_RX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI2_SPRI,                \
+        .flag           = SPI2_RX_DMA_TRANS_FLAG,           \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI2_RX_DMA_IRQn,                 \
+            .irq_prio   = SPI2_RX_DMA_INT_PRIO,             \
+            .int_src    = SPI2_RX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI2_RX_DMA_CONFIG */
+#endif /* BSP_SPI2_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI3
+#ifndef SPI3_BUS_CONFIG
+#define SPI3_BUS_CONFIG                                     \
+    {                                                       \
+        .Instance = CM_SPI3,                                \
+        .bus_name = "spi3",                                 \
+        .clock    = FCG1_PERIPH_SPI3,                       \
+        .timeout  = 5000UL,                                 \
+        .err_irq.irq_config =                               \
+        {                                                   \
+            .irq_num    = BSP_SPI3_ERR_IRQ_NUM,             \
+            .irq_prio   = BSP_SPI3_ERR_IRQ_PRIO,            \
+            .int_src    = INT_SRC_SPI3_SPEI,                \
+        },                                                  \
+    }
+#endif /* SPI3_BUS_CONFIG */
+#endif /* BSP_USING_SPI3 */
+
+
+#ifdef BSP_SPI3_TX_USING_DMA
+#ifndef SPI3_TX_DMA_CONFIG
+#define SPI3_TX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI3_TX_DMA_INSTANCE,             \
+        .channel        = SPI3_TX_DMA_CHANNEL,              \
+        .clock          = SPI3_TX_DMA_CLOCK,                \
+        .trigger_select = SPI3_TX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI3_SPTI,                \
+        .flag           = SPI3_TX_DMA_TRANS_FLAG,           \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI3_TX_DMA_IRQn,                 \
+            .irq_prio   = SPI3_TX_DMA_INT_PRIO,             \
+            .int_src    = SPI3_TX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI3_TX_DMA_CONFIG */
+#endif /* BSP_SPI3_TX_USING_DMA */
+
+#ifdef BSP_SPI3_RX_USING_DMA
+#ifndef SPI3_RX_DMA_CONFIG
+#define SPI3_RX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI3_RX_DMA_INSTANCE,             \
+        .channel        = SPI3_RX_DMA_CHANNEL,              \
+        .clock          = SPI3_RX_DMA_CLOCK,                \
+        .trigger_select = SPI3_RX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI3_SPRI,                \
+        .flag           = SPI3_RX_DMA_TRANS_FLAG,           \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI3_RX_DMA_IRQn,                 \
+            .irq_prio   = SPI3_RX_DMA_INT_PRIO,             \
+            .int_src    = SPI3_RX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI3_RX_DMA_CONFIG */
+#endif /* BSP_SPI3_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI4
+#ifndef SPI4_BUS_CONFIG
+#define SPI4_BUS_CONFIG                                     \
+    {                                                       \
+        .Instance = CM_SPI4,                                \
+        .bus_name = "spi4",                                 \
+        .clock    = FCG1_PERIPH_SPI4,                       \
+        .timeout  = 5000UL,                                 \
+        .err_irq.irq_config =                               \
+        {                                                   \
+            .irq_num    = BSP_SPI4_ERR_IRQ_NUM,             \
+            .irq_prio   = BSP_SPI4_ERR_IRQ_PRIO,            \
+            .int_src    = INT_SRC_SPI4_SPEI,                \
+        },                                                  \
+    }
+#endif /* SPI4_BUS_CONFIG */
+#endif /* BSP_USING_SPI4 */
+
+#ifdef BSP_SPI4_TX_USING_DMA
+#ifndef SPI4_TX_DMA_CONFIG
+#define SPI4_TX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI4_TX_DMA_INSTANCE,             \
+        .channel        = SPI4_TX_DMA_CHANNEL,              \
+        .clock          = SPI4_TX_DMA_CLOCK,                \
+        .trigger_select = SPI4_TX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI4_SPTI,                \
+        .flag           = SPI4_TX_DMA_TRANS_FLAG,           \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI4_TX_DMA_IRQn,                 \
+            .irq_prio   = SPI4_TX_DMA_INT_PRIO,             \
+            .int_src    = SPI4_TX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI4_TX_DMA_CONFIG */
+#endif /* BSP_SPI4_TX_USING_DMA */
+
+#ifdef BSP_SPI4_RX_USING_DMA
+#ifndef SPI4_RX_DMA_CONFIG
+#define SPI4_RX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI4_RX_DMA_INSTANCE,             \
+        .channel        = SPI4_RX_DMA_CHANNEL,              \
+        .clock          = SPI4_RX_DMA_CLOCK,                \
+        .trigger_select = SPI4_RX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI4_SPRI,                \
+        .flag           = SPI4_RX_DMA_TRANS_FLAG,           \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI4_RX_DMA_IRQn,                 \
+            .irq_prio   = SPI4_RX_DMA_INT_PRIO,             \
+            .int_src    = SPI4_RX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI4_RX_DMA_CONFIG */
+#endif /* BSP_SPI4_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI5
+#ifndef SPI5_BUS_CONFIG
+#define SPI5_BUS_CONFIG                                     \
+    {                                                       \
+        .Instance = CM_SPI5,                                \
+        .bus_name = "spi5",                                 \
+        .clock    = FCG1_PERIPH_SPI5,                       \
+        .timeout  = 5000UL,                                 \
+        .err_irq.irq_config =                               \
+        {                                                   \
+            .irq_num    = BSP_SPI5_ERR_IRQ_NUM,             \
+            .irq_prio   = BSP_SPI5_ERR_IRQ_PRIO,            \
+            .int_src    = INT_SRC_SPI5_SPEI,                \
+        },                                                  \
+    }
+#endif /* SPI5_BUS_CONFIG */
+#endif /* BSP_USING_SPI5 */
+
+#ifdef BSP_SPI5_TX_USING_DMA
+#ifndef SPI5_TX_DMA_CONFIG
+#define SPI5_TX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI5_TX_DMA_INSTANCE,             \
+        .channel        = SPI5_TX_DMA_CHANNEL,              \
+        .clock          = SPI5_TX_DMA_CLOCK,                \
+        .trigger_select = SPI5_TX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI5_SPTI,                \
+        .flag           = SPI5_TX_DMA_TRANS_FLAG,           \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI5_TX_DMA_IRQn,                 \
+            .irq_prio   = SPI5_TX_DMA_INT_PRIO,             \
+            .int_src    = SPI5_TX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI5_TX_DMA_CONFIG */
+#endif /* BSP_SPI5_TX_USING_DMA */
+
+#ifdef BSP_SPI5_RX_USING_DMA
+#ifndef SPI5_RX_DMA_CONFIG
+#define SPI5_RX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI5_RX_DMA_INSTANCE,             \
+        .channel        = SPI5_RX_DMA_CHANNEL,              \
+        .clock          = SPI5_RX_DMA_CLOCK,                \
+        .trigger_select = SPI5_RX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI5_SPRI,                \
+        .flag           = SPI5_RX_DMA_TRANS_FLAG,           \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI5_RX_DMA_IRQn,                 \
+            .irq_prio   = SPI5_RX_DMA_INT_PRIO,             \
+            .int_src    = SPI5_RX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI5_RX_DMA_CONFIG */
+#endif /* BSP_SPI5_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI6
+#ifndef SPI6_BUS_CONFIG
+#define SPI6_BUS_CONFIG                                     \
+    {                                                       \
+        .Instance = CM_SPI6,                                \
+        .bus_name = "spi6",                                 \
+        .clock    = FCG1_PERIPH_SPI6,                       \
+        .timeout  = 5000UL,                                 \
+        .err_irq.irq_config =                               \
+        {                                                   \
+            .irq_num    = BSP_SPI6_ERR_IRQ_NUM,             \
+            .irq_prio   = BSP_SPI6_ERR_IRQ_PRIO,            \
+            .int_src    = INT_SRC_SPI6_SPEI,                \
+        },                                                  \
+    }
+#endif /* SPI6_BUS_CONFIG */
+#endif /* BSP_USING_SPI6 */
+
+#ifdef BSP_SPI6_TX_USING_DMA
+#ifndef SPI6_TX_DMA_CONFIG
+#define SPI6_TX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI6_TX_DMA_INSTANCE,             \
+        .channel        = SPI6_TX_DMA_CHANNEL,              \
+        .clock          = SPI6_TX_DMA_CLOCK,                \
+        .trigger_select = SPI6_TX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI6_SPTI,                \
+        .flag           = SPI6_TX_DMA_TRANS_FLAG,           \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI6_TX_DMA_IRQn,                 \
+            .irq_prio   = SPI6_TX_DMA_INT_PRIO,             \
+            .int_src    = SPI6_TX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI6_TX_DMA_CONFIG */
+#endif /* BSP_SPI6_TX_USING_DMA */
+
+#ifdef BSP_SPI6_RX_USING_DMA
+#ifndef SPI6_RX_DMA_CONFIG
+#define SPI6_RX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI6_RX_DMA_INSTANCE,             \
+        .channel        = SPI6_RX_DMA_CHANNEL,              \
+        .clock          = SPI6_RX_DMA_CLOCK,                \
+        .trigger_select = SPI6_RX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI6_SPRI,                \
+        .flag           = SPI6_RX_DMA_TRANS_FLAG,           \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI6_RX_DMA_IRQn,                 \
+            .irq_prio   = SPI6_RX_DMA_INT_PRIO,             \
+            .int_src    = SPI6_RX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI6_RX_DMA_CONFIG */
+#endif /* BSP_SPI6_RX_USING_DMA */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SPI_CONFIG_H__ */

bsp/hc32/ev_hc32f448_lqfp80/board/config/timer_config.h

@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-02-20     CDT          first version
+ */
+
+#ifndef __TMR_CONFIG_H__
+#define __TMR_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_TMRA_1
+#ifndef TMRA_1_CONFIG
+#define TMRA_1_CONFIG                                       \
+    {                                                       \
+       .tmr_handle      = CM_TMRA_1,                        \
+       .clock_source    = CLK_BUS_PCLK0,                    \
+       .clock           = FCG2_PERIPH_TMRA_1,               \
+       .flag            = TMRA_FLAG_OVF,                    \
+       .isr             =                                   \
+       {                                                    \
+            .enIntSrc   = INT_SRC_TMRA_1_OVF,               \
+            .enIRQn     = BSP_USING_TMRA_1_IRQ_NUM,         \
+            .u8Int_Prio = BSP_USING_TMRA_1_IRQ_PRIO,        \
+       },                                                   \
+       .name            = "tmra_1"                          \
+    }
+#endif /* TMRA_1_CONFIG */
+#endif /* BSP_USING_TMRA_1 */
+
+#ifdef BSP_USING_TMRA_2
+#ifndef TMRA_2_CONFIG
+#define TMRA_2_CONFIG                                       \
+    {                                                       \
+       .tmr_handle      = CM_TMRA_2,                        \
+       .clock_source    = CLK_BUS_PCLK0,                    \
+       .clock           = FCG2_PERIPH_TMRA_2,               \
+       .flag            = TMRA_FLAG_OVF,                    \
+       .isr             =                                   \
+       {                                                    \
+            .enIntSrc   = INT_SRC_TMRA_2_OVF,               \
+            .enIRQn     = BSP_USING_TMRA_2_IRQ_NUM,         \
+            .u8Int_Prio = BSP_USING_TMRA_2_IRQ_PRIO,        \
+       },                                                   \
+       .name            = "tmra_2"                          \
+    }
+#endif /* TMRA_2_CONFIG */
+#endif /* BSP_USING_TMRA_2 */
+
+#ifdef BSP_USING_TMRA_3
+#ifndef TMRA_3_CONFIG
+#define TMRA_3_CONFIG                                       \
+    {                                                       \
+       .tmr_handle      = CM_TMRA_3,                        \
+       .clock_source    = CLK_BUS_PCLK0,                    \
+       .clock           = FCG2_PERIPH_TMRA_3,               \
+       .flag            = TMRA_FLAG_OVF,                    \
+       .isr             =                                   \
+       {                                                    \
+            .enIntSrc   = INT_SRC_TMRA_3_OVF,               \
+            .enIRQn     = BSP_USING_TMRA_3_IRQ_NUM,         \
+            .u8Int_Prio = BSP_USING_TMRA_3_IRQ_PRIO,        \
+       },                                                   \
+       .name            = "tmra_3"                          \
+    }
+#endif /* TMRA_3_CONFIG */
+#endif /* BSP_USING_TMRA_3 */
+
+#ifdef BSP_USING_TMRA_4
+#ifndef TMRA_4_CONFIG
+#define TMRA_4_CONFIG                                       \
+    {                                                       \
+       .tmr_handle      = CM_TMRA_4,                        \
+       .clock_source    = CLK_BUS_PCLK0,                    \
+       .clock           = FCG2_PERIPH_TMRA_4,               \
+       .flag            = TMRA_FLAG_OVF,                    \
+       .isr             =                                   \
+       {                                                    \
+            .enIntSrc   = INT_SRC_TMRA_4_OVF,               \
+            .enIRQn     = BSP_USING_TMRA_4_IRQ_NUM,         \
+            .u8Int_Prio = BSP_USING_TMRA_4_IRQ_PRIO,        \
+       },                                                   \
+       .name            = "tmra_4"                          \
+    }
+#endif /* TMRA_4_CONFIG */
+#endif /* BSP_USING_TMRA_4 */
+
+#ifdef BSP_USING_TMRA_5
+#ifndef TMRA_5_CONFIG
+#define TMRA_5_CONFIG                                       \
+    {                                                       \
+       .tmr_handle      = CM_TMRA_5,                        \
+       .clock_source    = CLK_BUS_PCLK1,                    \
+       .clock           = FCG2_PERIPH_TMRA_5,               \
+       .flag            = TMRA_FLAG_OVF,                    \
+       .isr             =                                   \
+       {                                                    \
+            .enIntSrc   = INT_SRC_TMRA_5_OVF,               \
+            .enIRQn     = BSP_USING_TMRA_5_IRQ_NUM,         \
+            .u8Int_Prio = BSP_USING_TMRA_5_IRQ_PRIO,        \
+       },                                                   \
+       .name            = "tmra_5"                          \
+    }
+#endif /* TMRA_5_CONFIG */
+#endif /* BSP_USING_TMRA_5 */
+#endif /* __TMR_CONFIG_H__ */

bsp/hc32/ev_hc32f448_lqfp80/board/config/uart_config.h

@@ -0,0 +1,449 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-02-20     CDT          first version
+ */
+
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+#include "irq_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG
+#define UART1_CONFIG                                            \
+    {                                                           \
+        .name     = "uart1",                                    \
+        .Instance = CM_USART1,                                  \
+        .clock    = FCG3_PERIPH_USART1,                         \
+        .irq_num  = BSP_UART1_IRQ_NUM,                          \
+        .rxerr_int_src = INT_SRC_USART1_EI,                     \
+        .rx_int_src    = INT_SRC_USART1_RI,                     \
+        .tx_int_src    = INT_SRC_USART1_TI,                     \
+    }
+#endif /* UART1_CONFIG */
+
+#if defined(BSP_UART1_RX_USING_DMA)
+#ifndef UART1_DMA_RX_CONFIG
+#define UART1_DMA_RX_CONFIG                                     \
+    {                                                           \
+        .Instance       = UART1_RX_DMA_INSTANCE,                \
+        .channel        = UART1_RX_DMA_CHANNEL,                 \
+        .clock          = UART1_RX_DMA_CLOCK,                   \
+        .trigger_select = UART1_RX_DMA_TRIG_SELECT,             \
+        .trigger_event  = EVT_SRC_USART1_RI,                    \
+        .flag           = UART1_RX_DMA_TRANS_FLAG,              \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = UART1_RX_DMA_IRQn,                    \
+            .irq_prio   = UART1_RX_DMA_INT_PRIO,                \
+            .int_src    = UART1_RX_DMA_INT_SRC,                 \
+        },                                                      \
+    }
+#endif /* UART1_DMA_RX_CONFIG */
+
+#ifndef UART1_RXTO_CONFIG
+#define UART1_RXTO_CONFIG                                       \
+    {                                                           \
+        .TMR0_Instance = CM_TMR0_1,                             \
+        .channel       = TMR0_CH_A,                             \
+        .clock         = FCG2_PERIPH_TMR0_1,                    \
+        .timeout_bits  = 20UL,                                  \
+    }
+#endif /* UART1_RXTO_CONFIG */
+#endif /* BSP_UART1_RX_USING_DMA */
+
+#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA)
+#ifndef UART1_TX_CPLT_CONFIG
+#define UART1_TX_CPLT_CONFIG                                    \
+    {                                                           \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = BSP_UART1_TX_CPLT_IRQ_NUM,            \
+            .irq_prio   = BSP_UART1_TX_CPLT_IRQ_PRIO,           \
+            .int_src    = INT_SRC_USART1_TCI,                   \
+        },                                                      \
+    }
+#endif
+#elif defined(RT_USING_SERIAL_V2)
+#ifndef UART1_TX_CPLT_CONFIG
+#define UART1_TX_CPLT_CONFIG                                    \
+    {                                                           \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = BSP_UART1_TX_CPLT_IRQ_NUM,            \
+            .irq_prio   = BSP_UART1_TX_CPLT_IRQ_PRIO,           \
+            .int_src    = INT_SRC_USART1_TCI,                   \
+        },                                                      \
+    }
+#endif
+#endif /* UART1_TX_CPLT_CONFIG */
+
+#if defined(BSP_UART1_TX_USING_DMA)
+#ifndef UART1_DMA_TX_CONFIG
+#define UART1_DMA_TX_CONFIG                                     \
+    {                                                           \
+        .Instance       = UART1_TX_DMA_INSTANCE,                \
+        .channel        = UART1_TX_DMA_CHANNEL,                 \
+        .clock          = UART1_TX_DMA_CLOCK,                   \
+        .trigger_select = UART1_TX_DMA_TRIG_SELECT,             \
+        .trigger_event  = EVT_SRC_USART1_TI,                    \
+        .flag           = UART1_TX_DMA_TRANS_FLAG,              \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = UART1_TX_DMA_IRQn,                    \
+            .irq_prio   = UART1_TX_DMA_INT_PRIO,                \
+            .int_src    = UART1_TX_DMA_INT_SRC,                 \
+        },                                                      \
+    }
+#endif /* UART1_DMA_TX_CONFIG */
+#endif /* BSP_UART1_TX_USING_DMA */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                                            \
+    {                                                           \
+        .name     = "uart2",                                    \
+        .Instance = CM_USART2,                                  \
+        .clock    = FCG3_PERIPH_USART2,                         \
+        .irq_num  = BSP_UART2_IRQ_NUM,                          \
+        .rxerr_int_src = INT_SRC_USART2_EI,                     \
+        .rx_int_src    = INT_SRC_USART2_RI,                     \
+        .tx_int_src    = INT_SRC_USART2_TI,                     \
+    }
+#endif /* UART2_CONFIG */
+
+#if defined(BSP_UART2_RX_USING_DMA)
+#ifndef UART2_DMA_RX_CONFIG
+#define UART2_DMA_RX_CONFIG                                     \
+    {                                                           \
+        .Instance       = UART2_RX_DMA_INSTANCE,                \
+        .channel        = UART2_RX_DMA_CHANNEL,                 \
+        .clock          = UART2_RX_DMA_CLOCK,                   \
+        .trigger_select = UART2_RX_DMA_TRIG_SELECT,             \
+        .trigger_event  = EVT_SRC_USART2_RI,                    \
+        .flag           = UART2_RX_DMA_TRANS_FLAG,              \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = UART2_RX_DMA_IRQn,                    \
+            .irq_prio   = UART2_RX_DMA_INT_PRIO,                \
+            .int_src    = UART2_RX_DMA_INT_SRC,                 \
+        },                                                      \
+    }
+#endif /* UART2_DMA_RX_CONFIG */
+
+#ifndef UART2_RXTO_CONFIG
+#define UART2_RXTO_CONFIG                                       \
+    {                                                           \
+        .TMR0_Instance = CM_TMR0_1,                             \
+        .channel       = TMR0_CH_B,                             \
+        .clock         = FCG2_PERIPH_TMR0_1,                    \
+        .timeout_bits  = 20UL,                                  \
+    }
+#endif /* UART2_RXTO_CONFIG */
+#endif /* BSP_UART2_RX_USING_DMA */
+
+#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA)
+#ifndef UART2_TX_CPLT_CONFIG
+#define UART2_TX_CPLT_CONFIG                                    \
+    {                                                           \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = BSP_UART2_TX_CPLT_IRQ_NUM,            \
+            .irq_prio   = BSP_UART2_TX_CPLT_IRQ_PRIO,           \
+            .int_src    = INT_SRC_USART2_TCI,                   \
+        },                                                      \
+    }
+#endif
+#elif defined(RT_USING_SERIAL_V2)
+#ifndef UART2_TX_CPLT_CONFIG
+#define UART2_TX_CPLT_CONFIG                                    \
+    {                                                           \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = BSP_UART2_TX_CPLT_IRQ_NUM,            \
+            .irq_prio   = BSP_UART2_TX_CPLT_IRQ_PRIO,           \
+            .int_src    = INT_SRC_USART2_TCI,                   \
+        },                                                      \
+    }
+#endif
+#endif /* UART2_TX_CPLT_CONFIG */
+
+#if defined(BSP_UART2_TX_USING_DMA)
+#ifndef UART2_DMA_TX_CONFIG
+#define UART2_DMA_TX_CONFIG                                     \
+    {                                                           \
+        .Instance       = UART2_TX_DMA_INSTANCE,                \
+        .channel        = UART2_TX_DMA_CHANNEL,                 \
+        .clock          = UART2_TX_DMA_CLOCK,                   \
+        .trigger_select = UART2_TX_DMA_TRIG_SELECT,             \
+        .trigger_event  = EVT_SRC_USART2_TI,                    \
+        .flag           = UART2_TX_DMA_TRANS_FLAG,              \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = UART2_TX_DMA_IRQn,                    \
+            .irq_prio   = UART2_TX_DMA_INT_PRIO,                \
+            .int_src    = UART2_TX_DMA_INT_SRC,                 \
+        },                                                      \
+    }
+#endif /* UART2_DMA_TX_CONFIG */
+#endif /* BSP_UART2_TX_USING_DMA */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+#ifndef UART3_CONFIG
+#define UART3_CONFIG                                            \
+    {                                                           \
+        .name     = "uart3",                                    \
+        .Instance = CM_USART3,                                  \
+        .clock    = FCG3_PERIPH_USART3,                         \
+        .irq_num  = BSP_UART3_IRQ_NUM,                          \
+        .rxerr_int_src = INT_SRC_USART3_EI,                     \
+        .rx_int_src    = INT_SRC_USART3_RI,                     \
+        .tx_int_src    = INT_SRC_USART3_TI,                     \
+    }
+#endif /* UART3_CONFIG */
+
+#if defined(RT_USING_SERIAL_V2)
+#ifndef UART3_TX_CPLT_CONFIG
+#define UART3_TX_CPLT_CONFIG                                    \
+    {                                                           \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = BSP_UART3_TX_CPLT_IRQ_NUM,            \
+            .irq_prio   = BSP_UART3_TX_CPLT_IRQ_PRIO,           \
+            .int_src    = INT_SRC_USART3_TCI,                   \
+        },                                                      \
+    }
+#endif
+#endif /* UART3_TX_CPLT_CONFIG */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_USING_UART4)
+#ifndef UART4_CONFIG
+#define UART4_CONFIG                                            \
+    {                                                           \
+        .name     = "uart4",                                    \
+        .Instance = CM_USART4,                                  \
+        .clock    = FCG3_PERIPH_USART4,                         \
+        .irq_num  = BSP_UART4_IRQ_NUM,                          \
+        .rxerr_int_src = INT_SRC_USART4_EI,                     \
+        .rx_int_src    = INT_SRC_USART4_RI,                     \
+        .tx_int_src    = INT_SRC_USART4_TI,                     \
+    }
+#endif /* UART4_CONFIG */
+
+#if defined(BSP_UART4_RX_USING_DMA)
+#ifndef UART4_DMA_RX_CONFIG
+#define UART4_DMA_RX_CONFIG                                     \
+    {                                                           \
+        .Instance       = UART4_RX_DMA_INSTANCE,                \
+        .channel        = UART4_RX_DMA_CHANNEL,                 \
+        .clock          = UART4_RX_DMA_CLOCK,                   \
+        .trigger_select = UART4_RX_DMA_TRIG_SELECT,             \
+        .trigger_event  = EVT_SRC_USART4_RI,                    \
+        .flag           = UART4_RX_DMA_TRANS_FLAG,              \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = UART4_RX_DMA_IRQn,                    \
+            .irq_prio   = UART4_RX_DMA_INT_PRIO,                \
+            .int_src    = UART4_RX_DMA_INT_SRC,                 \
+        },                                                      \
+    }
+#endif /* UART4_DMA_RX_CONFIG */
+
+#ifndef UART4_RXTO_CONFIG
+#define UART4_RXTO_CONFIG                                       \
+    {                                                           \
+        .TMR0_Instance = CM_TMR0_2,                             \
+        .channel       = TMR0_CH_A,                             \
+        .clock         = FCG2_PERIPH_TMR0_2,                    \
+        .timeout_bits  = 20UL,                                  \
+    }
+#endif /* UART4_RXTO_CONFIG */
+#endif /* BSP_UART4_RX_USING_DMA */
+
+#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART4_TX_USING_DMA)
+#ifndef UART4_TX_CPLT_CONFIG
+#define UART4_TX_CPLT_CONFIG                                    \
+    {                                                           \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = BSP_UART4_TX_CPLT_IRQ_NUM,            \
+            .irq_prio   = BSP_UART4_TX_CPLT_IRQ_PRIO,           \
+            .int_src    = INT_SRC_USART4_TCI,                   \
+        },                                                      \
+    }
+#endif
+#elif defined(RT_USING_SERIAL_V2)
+#ifndef UART4_TX_CPLT_CONFIG
+#define UART4_TX_CPLT_CONFIG                                    \
+    {                                                           \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = BSP_UART4_TX_CPLT_IRQ_NUM,            \
+            .irq_prio   = BSP_UART4_TX_CPLT_IRQ_PRIO,           \
+            .int_src    = INT_SRC_USART4_TCI,                   \
+        },                                                      \
+    }
+#endif
+#endif /* UART4_TX_CPLT_CONFIG */
+
+#if defined(BSP_UART4_TX_USING_DMA)
+#ifndef UART4_DMA_TX_CONFIG
+#define UART4_DMA_TX_CONFIG                                     \
+    {                                                           \
+        .Instance       = UART4_TX_DMA_INSTANCE,                \
+        .channel        = UART4_TX_DMA_CHANNEL,                 \
+        .clock          = UART4_TX_DMA_CLOCK,                   \
+        .trigger_select = UART4_TX_DMA_TRIG_SELECT,             \
+        .trigger_event  = EVT_SRC_USART4_TI,                    \
+        .flag           = UART4_TX_DMA_TRANS_FLAG,              \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = UART4_TX_DMA_IRQn,                    \
+            .irq_prio   = UART4_TX_DMA_INT_PRIO,                \
+            .int_src    = UART4_TX_DMA_INT_SRC,                 \
+        },                                                      \
+    }
+#endif /* UART4_DMA_TX_CONFIG */
+#endif /* BSP_UART4_TX_USING_DMA */
+#endif /* BSP_USING_UART4 */
+
+#if defined(BSP_USING_UART5)
+#ifndef UART5_CONFIG
+#define UART5_CONFIG                                            \
+    {                                                           \
+        .name     = "uart5",                                    \
+        .Instance = CM_USART5,                                  \
+        .clock    = FCG3_PERIPH_USART5,                         \
+        .irq_num  = BSP_UART5_IRQ_NUM,                          \
+        .rxerr_int_src = INT_SRC_USART5_EI,                     \
+        .rx_int_src    = INT_SRC_USART5_RI,                     \
+        .tx_int_src    = INT_SRC_USART5_TI,                     \
+    }
+#endif /* UART5_CONFIG */
+
+#if defined(BSP_UART5_RX_USING_DMA)
+#ifndef UART5_DMA_RX_CONFIG
+#define UART5_DMA_RX_CONFIG                                     \
+    {                                                           \
+        .Instance       = UART5_RX_DMA_INSTANCE,                \
+        .channel        = UART5_RX_DMA_CHANNEL,                 \
+        .clock          = UART5_RX_DMA_CLOCK,                   \
+        .trigger_select = UART5_RX_DMA_TRIG_SELECT,             \
+        .trigger_event  = EVT_SRC_USART5_RI,                    \
+        .flag           = UART5_RX_DMA_TRANS_FLAG,              \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = UART5_RX_DMA_IRQn,                    \
+            .irq_prio   = UART5_RX_DMA_INT_PRIO,                \
+            .int_src    = UART5_RX_DMA_INT_SRC,                 \
+        },                                                      \
+    }
+#endif /* UART5_DMA_RX_CONFIG */
+
+#ifndef UART5_RXTO_CONFIG
+#define UART5_RXTO_CONFIG                                       \
+    {                                                           \
+        .TMR0_Instance = CM_TMR0_2,                             \
+        .channel       = TMR0_CH_B,                             \
+        .clock         = FCG2_PERIPH_TMR0_2,                    \
+        .timeout_bits  = 20UL,                                  \
+    }
+#endif /* UART5_RXTO_CONFIG */
+#endif /* BSP_UART5_RX_USING_DMA */
+
+#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART5_TX_USING_DMA)
+#ifndef UART5_TX_CPLT_CONFIG
+#define UART5_TX_CPLT_CONFIG                                    \
+    {                                                           \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = BSP_UART5_TX_CPLT_IRQ_NUM,            \
+            .irq_prio   = BSP_UART5_TX_CPLT_IRQ_PRIO,           \
+            .int_src    = INT_SRC_USART5_TCI,                   \
+        },                                                      \
+    }
+#endif
+#elif defined(RT_USING_SERIAL_V2)
+#ifndef UART5_TX_CPLT_CONFIG
+#define UART5_TX_CPLT_CONFIG                                    \
+    {                                                           \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = BSP_UART5_TX_CPLT_IRQ_NUM,            \
+            .irq_prio   = BSP_UART5_TX_CPLT_IRQ_PRIO,           \
+            .int_src    = INT_SRC_USART5_TCI,                   \
+        },                                                      \
+    }
+#endif
+#endif /* UART5_TX_CPLT_CONFIG */
+
+#if defined(BSP_UART5_TX_USING_DMA)
+#ifndef UART5_DMA_TX_CONFIG
+#define UART5_DMA_TX_CONFIG                                     \
+    {                                                           \
+        .Instance       = UART5_TX_DMA_INSTANCE,                \
+        .channel        = UART5_TX_DMA_CHANNEL,                 \
+        .clock          = UART5_TX_DMA_CLOCK,                   \
+        .trigger_select = UART5_TX_DMA_TRIG_SELECT,             \
+        .trigger_event  = EVT_SRC_USART5_TI,                    \
+        .flag           = UART5_TX_DMA_TRANS_FLAG,              \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = UART5_TX_DMA_IRQn,                    \
+            .irq_prio   = UART5_TX_DMA_INT_PRIO,                \
+            .int_src    = UART5_TX_DMA_INT_SRC,                 \
+        },                                                      \
+    }
+#endif /* UART5_DMA_TX_CONFIG */
+#endif /* BSP_UART5_TX_USING_DMA */
+#endif /* BSP_USING_UART5 */
+
+#if defined(BSP_USING_UART6)
+#ifndef UART6_CONFIG
+#define UART6_CONFIG                                            \
+    {                                                           \
+        .name     = "uart6",                                    \
+        .Instance = CM_USART6,                                  \
+        .clock    = FCG3_PERIPH_USART6,                         \
+        .irq_num  = BSP_UART6_IRQ_NUM,                          \
+        .rxerr_int_src = INT_SRC_USART6_EI,                     \
+        .rx_int_src    = INT_SRC_USART6_RI,                     \
+        .tx_int_src    = INT_SRC_USART6_TI,                     \
+    }
+#endif /* UART6_CONFIG */
+
+#if defined(RT_USING_SERIAL_V2)
+#ifndef UART6_TX_CPLT_CONFIG
+#define UART6_TX_CPLT_CONFIG                                    \
+    {                                                           \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = BSP_UART6_TX_CPLT_IRQ_NUM,            \
+            .irq_prio   = BSP_UART6_TX_CPLT_IRQ_PRIO,           \
+            .int_src    = INT_SRC_USART6_TCI,                   \
+        },                                                      \
+    }
+#endif
+#endif /* UART6_TX_CPLT_CONFIG */
+#endif /* BSP_USING_UART6 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/hc32/ev_hc32f448_lqfp80/board/drv_config.h

@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-02-20     CDT          first version
+ */
+
+#ifndef __DRV_CONFIG_H__
+#define __DRV_CONFIG_H__
+
+#include <board.h>
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "dma_config.h"
+#include "uart_config.h"
+#include "spi_config.h"
+#include "adc_config.h"
+#include "dac_config.h"
+#include "gpio_config.h"
+#include "can_config.h"
+#include "pm_config.h"
+#include "i2c_config.h"
+#include "qspi_config.h"
+#include "pulse_encoder_config.h"
+#include "timer_config.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/hc32/ev_hc32f448_lqfp80/board/hc32f4xx_conf.h

@@ -0,0 +1,136 @@
+/**
+ *******************************************************************************
+ * @file  template/source/hc32f4xx_conf.h
+ * @brief This file contains HC32 Series Device Driver Library usage management.
+ @verbatim
+   Change Logs:
+   Date             Author          Notes
+   2023-05-31       CDT             First version
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                    opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32F4XX_CONF_H__
+#define __HC32F4XX_CONF_H__
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include <rtconfig.h>
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+/**
+ * @brief This is the list of modules to be used in the Device Driver Library.
+ * Select the modules you need to use to DDL_ON.
+ * @note LL_ICG_ENABLE must be turned on(DDL_ON) to ensure that the chip works
+ * properly.
+ * @note LL_UTILITY_ENABLE must be turned on(DDL_ON) if using Device Driver
+ * Library.
+ * @note LL_PRINT_ENABLE must be turned on(DDL_ON) if using printf function.
+ */
+#define LL_ICG_ENABLE                               (DDL_ON)
+#define LL_UTILITY_ENABLE                           (DDL_ON)
+#define LL_PRINT_ENABLE                             (DDL_OFF)
+
+#define LL_ADC_ENABLE                               (DDL_ON)
+#define LL_AES_ENABLE                               (DDL_ON)
+#define LL_AOS_ENABLE                               (DDL_ON)
+#define LL_CLK_ENABLE                               (DDL_ON)
+#define LL_CMP_ENABLE                               (DDL_ON)
+#define LL_CRC_ENABLE                               (DDL_ON)
+#define LL_CTC_ENABLE                               (DDL_ON)
+#define LL_DAC_ENABLE                               (DDL_ON)
+#define LL_DBGC_ENABLE                              (DDL_OFF)
+#define LL_DCU_ENABLE                               (DDL_ON)
+#define LL_DMA_ENABLE                               (DDL_ON)
+#define LL_EFM_ENABLE                               (DDL_ON)
+#define LL_EMB_ENABLE                               (DDL_ON)
+#define LL_EVENT_PORT_ENABLE                        (DDL_OFF)
+#define LL_FCG_ENABLE                               (DDL_ON)
+#define LL_FCM_ENABLE                               (DDL_ON)
+#define LL_GPIO_ENABLE                              (DDL_ON)
+#define LL_HASH_ENABLE                              (DDL_ON)
+#define LL_I2C_ENABLE                               (DDL_ON)
+#define LL_INTERRUPTS_ENABLE                        (DDL_ON)
+#define LL_KEYSCAN_ENABLE                           (DDL_ON)
+#define LL_MCAN_ENABLE                              (DDL_ON)
+#define LL_MPU_ENABLE                               (DDL_ON)
+#define LL_PWC_ENABLE                               (DDL_ON)
+#define LL_QSPI_ENABLE                              (DDL_ON)
+#define LL_RMU_ENABLE                               (DDL_ON)
+#define LL_RTC_ENABLE                               (DDL_ON)
+#define LL_SMC_ENABLE                               (DDL_ON)
+#define LL_SPI_ENABLE                               (DDL_ON)
+#define LL_SRAM_ENABLE                              (DDL_ON)
+#define LL_SWDT_ENABLE                              (DDL_ON)
+#define LL_TMR0_ENABLE                              (DDL_ON)
+#define LL_TMR4_ENABLE                              (DDL_ON)
+#define LL_TMR6_ENABLE                              (DDL_ON)
+#define LL_TMRA_ENABLE                              (DDL_ON)
+#define LL_TRNG_ENABLE                              (DDL_ON)
+#define LL_USART_ENABLE                             (DDL_ON)
+#define LL_WDT_ENABLE                               (DDL_ON)
+
+/**
+ * @brief The following is a list of currently supported BSP boards.
+ */
+#define BSP_EV_HC32F448_LQFP80                      (9U)
+
+/**
+ * @brief The macro BSP_EV_HC32F4XX is used to specify the BSP board currently
+ * in use.
+ * The value should be set to one of the list of currently supported BSP boards.
+ * @note  If there is no supported BSP board or the BSP function is not used,
+ * the value needs to be set to 0U.
+ */
+#define BSP_EV_HC32F4XX                             (BSP_EV_HC32F448_LQFP80)
+
+/**
+ * @brief This is the list of BSP components to be used.
+ * Select the components you need to use to DDL_ON.
+ */
+#define BSP_24CXX_ENABLE                            (DDL_OFF)
+#define BSP_GT9XX_ENABLE                            (DDL_OFF)
+#define BSP_IS61LV6416_ENABLE                       (DDL_OFF)
+#define BSP_NT35510_ENABLE                          (DDL_OFF)
+#define BSP_TCA9539_ENABLE                          (DDL_OFF)
+#define BSP_W25QXX_ENABLE                           (DDL_OFF)
+#define BSP_INT_KEY_ENABLE                          (DDL_OFF)
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global function prototypes (definition in C source)
+ ******************************************************************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32F4XX_CONF_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/

bsp/hc32/ev_hc32f448_lqfp80/board/linker_scripts/link.icf

@@ -0,0 +1,103 @@
+/***************************************************************************//**
+ * \file HC32F448.icf
+ * \version 1.0
+ *
+ * \brief Linker file for the IAR compiler.
+ *
+********************************************************************************
+* \copyright
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                    opensource.org/licenses/BSD-3-Clause
+*******************************************************************************/
+
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
+
+// Check that necessary symbols have been passed to linker via command line interface
+if((!isdefinedsymbol(_LINK_RAM_)) && (!isdefinedsymbol(_LINK_FLASH_))) {
+  error "Link location not defined or not supported!";
+}
+if((!isdefinedsymbol(_HC32F448_256K_)) && (!isdefinedsymbol(_HC32F448_128K_))) {
+  error "Mcu type or size not defined or not supported!";
+}
+
+
+/*******************************************************************************
+ * Memory address and size definitions
+ ******************************************************************************/
+define symbol ram1_base_address = 0x1FFF8000;
+define symbol ram1_end_address  = 0x20007FFF;
+if(isdefinedsymbol(_LINK_RAM_)) {
+  define symbol ram_start_reserve = 0x8000;
+  define symbol rom1_base_address = ram1_base_address;
+  define symbol rom1_end_address  = rom1_base_address + ram_start_reserve - 0x01;
+  define symbol rom2_base_address = 0x0;
+  define symbol rom2_end_address  = 0x0;
+} else {
+  define symbol ram_start_reserve = 0x0;
+  define symbol rom1_base_address = 0x0;
+  define symbol rom2_base_address = 0x03000C00;
+  define symbol rom2_end_address = 0x03000FFF;
+
+  if(isdefinedsymbol(_HC32F448_256K_)) {
+    define symbol rom1_end_address  = 0x0003FFFF;
+  } else if (isdefinedsymbol(_HC32F448_128K_)) {
+    define symbol rom1_end_address  = 0x0001FFFF;
+  }
+}
+
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = rom1_base_address;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_IROM1_start__ = rom1_base_address;
+define symbol __ICFEDIT_region_IROM1_end__   = rom1_end_address;
+define symbol __ICFEDIT_region_IROM2_start__ = rom2_base_address;
+define symbol __ICFEDIT_region_IROM2_end__   = rom2_end_address;
+define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM1_end__   = 0x0;
+define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_end__   = 0x0;
+define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_end__   = 0x0;
+define symbol __ICFEDIT_region_IRAM1_start__ = ram1_base_address + ram_start_reserve;
+define symbol __ICFEDIT_region_IRAM1_end__   = ram1_end_address;
+define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000;
+define symbol __ICFEDIT_region_IRAM2_end__   = 0x200F0FFF;
+define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_end__   = 0x0;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0xC00;
+define symbol __ICFEDIT_size_proc_stack__ = 0x0;
+define symbol __ICFEDIT_size_heap__   = 0x400;
+/**** End of ICF editor section. ###ICF###*/
+
+/*******************************************************************************
+ * Memory definitions
+ ******************************************************************************/
+define memory mem with size = 4G;
+define region ROM_region       =   mem:[from __ICFEDIT_region_IROM1_start__   to __ICFEDIT_region_IROM1_end__];
+define region OTP_region       =   mem:[from __ICFEDIT_region_IROM2_start__   to __ICFEDIT_region_IROM2_end__];
+define region RAM_region       =   mem:[from __ICFEDIT_region_IRAM1_start__   to __ICFEDIT_region_IRAM1_end__]
+                                 | mem:[from __ICFEDIT_region_IRAM2_start__   to __ICFEDIT_region_IRAM2_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in OTP_region   { readonly section .otp_data };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };

bsp/hc32/ev_hc32f448_lqfp80/board/linker_scripts/link.ld

@@ -0,0 +1,270 @@
+/******************************************************************************
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                    opensource.org/licenses/BSD-3-Clause
+ *
+ */
+/*****************************************************************************/
+/*  File        HC32F448xC.ld                                                */
+/*  Abstract    Linker script for HC32F448 Device with                       */
+/*              256KByte FLASH, 68KByte RAM                                  */
+/*  Version     V1.0                                                         */
+/*  Date        2023-05-31                                                   */
+/*****************************************************************************/
+
+/* Custom defines, according to section 7.7 of the user manual.
+   Take OTP sector 16 for example. */
+__OTP_DATA_START = 0x03000C00;
+__OTP_DATA_SIZE  = 1024;
+__OTP_LOCK_START = 0x03000A80;
+__OTP_LOCK_SIZE  = 128;
+
+/* Use contiguous memory regions for simple. */
+MEMORY
+{
+    FLASH       (rx): ORIGIN = 0x00000000, LENGTH = 256K
+    OTP_DATA    (rx): ORIGIN = __OTP_DATA_START, LENGTH = __OTP_DATA_SIZE
+    OTP_LOCK    (rx): ORIGIN = __OTP_LOCK_START, LENGTH = __OTP_LOCK_SIZE
+    RAM        (rwx): ORIGIN = 0x1FFF8000, LENGTH = 64K
+    RAMB       (rwx): ORIGIN = 0x200F0000, LENGTH = 4K
+}
+
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .vectors :
+    {
+        . = ALIGN(4);
+        KEEP(*(.vectors))
+        . = ALIGN(4);
+    } >FLASH
+
+    .icg_sec 0x00000400 :
+    {
+        KEEP(*(.icg_sec))
+    } >FLASH
+
+    .text :
+    {
+        . = ALIGN(4);
+        _stext = .;
+        KEEP(*(.isr_vector))            /* Startup code */
+        . = ALIGN(4);
+        *(.text)                        /* remaining code */
+        *(.text.*)                      /* remaining code */
+        *(.rodata)                      /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gnu.linkonce.t*)
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        /* section information for initial. */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(4);
+
+        . = ALIGN(4);
+        _etext = .;
+    } >FLASH
+
+    .rodata :
+    {
+        . = ALIGN(4);
+        *(.rodata)
+        *(.rodata*)
+        . = ALIGN(4);
+    } >FLASH
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } >FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } >FLASH
+    __exidx_end = .;
+
+    .preinit_array :
+    {
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+        . = ALIGN(4);
+    } >FLASH
+
+    .init_array :
+    {
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+        . = ALIGN(4);
+    } >FLASH
+
+    .fini_array :
+    {
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+        . = ALIGN(4);
+    } >FLASH
+
+    __etext = ALIGN(4);
+
+    .otp_data_sec :
+    {
+        KEEP(*(.otp_data_sec))
+    } >OTP_DATA
+
+    .otp_lock_sec :
+    {
+        KEEP(*(.otp_lock_sec))
+    } >OTP_LOCK
+
+    .data : AT (__etext)
+    {
+        . = ALIGN(4);
+        __data_start__ = .;
+        *(vtable)
+        *(.data)
+        *(.data*)
+        *(.gnu.linkonce.d*)
+        . = ALIGN(4);
+        *(.ramfunc)
+        *(.ramfunc*)
+        . = ALIGN(4);
+        __data_end__ = .;
+    } >RAM
+
+    .heap_stack (COPY) :
+    {
+        . = ALIGN(8);
+        __end__ = .;
+        PROVIDE(end = .);
+        PROVIDE(_end = .);
+        *(.heap*)
+        . = ALIGN(8);
+        __HeapLimit = .;
+
+        __StackLimit = .;
+        *(.stack*)
+        . = ALIGN(8);
+        __StackTop = .;
+    } >RAM
+
+    __etext_ramb = __etext + ALIGN (SIZEOF(.data), 4);
+    .ramb_data : AT (__etext_ramb)
+    {
+        . = ALIGN(4);
+        __data_start_ramb__ = .;
+        *(.ramb_data)
+        *(.ramb_data*)
+        . = ALIGN(4);
+        __data_end_ramb__ = .;
+    } >RAMB
+
+    __bss_start = .;
+    .bss __StackTop (NOLOAD):
+    {
+        . = ALIGN(4);
+        _sbss = .;
+        __bss_start__ = _sbss;
+        *(.bss)
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = .;
+        __bss_end__ = _ebss;
+        . = ALIGN(4);
+        *(.noinit*)
+        . = ALIGN(4);
+    } >RAM
+    __bss_end = .;
+
+    .ramb_bss :
+    {
+        . = ALIGN(4);
+        __bss_start_ramb__ = .;
+        *(.ramb_bss)
+        *(.ramb_bss*)
+        . = ALIGN(4);
+        __bss_end_ramb__ = .;
+    } >RAMB
+
+    /DISCARD/ :
+    {
+        libc.a (*)
+        libm.a (*)
+        libgcc.a (*)
+    }
+
+    .ARM.attributes 0 : { *(.ARM.attributes) }
+
+    PROVIDE(_stack = __StackTop);
+    PROVIDE(_Min_Heap_Size = __HeapLimit - __HeapBase);
+    PROVIDE(_Min_Stack_Size = __StackTop - __StackLimit);
+
+    __RamEnd = ORIGIN(RAM) + LENGTH(RAM);
+    ASSERT(__StackTop <= __RamEnd, "region RAM overflowed with stack")
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}

bsp/hc32/ev_hc32f448_lqfp80/board/linker_scripts/link.sct

@@ -0,0 +1,22 @@
+; ****************************************************************
+; Scatter-Loading Description File
+; ****************************************************************
+LR_IROM1 0x00000000 0x00040000  {    ; load region size_region
+    ER_IROM1 0x00000000 0x00040000  {  ; load address = execution address
+        *.o (RESET, +First)
+        *(InRoot$$Sections)
+        .ANY (+RO)
+        .ANY (+XO)
+    }
+    RW_IRAM1 0x1FFF8000 UNINIT 0x00000008  {  ; RW data
+        *(.bss.noinit)
+    }
+    RW_IRAM2 0x1FFF8008 0x0000FFF8  {  ; RW data
+        .ANY (+RW +ZI)
+        .ANY (RAMCODE)
+    }
+    RW_IRAMB 0x200F0000 0x00001000  {  ; RW data
+        .ANY (+RW +ZI)
+    }
+}
+

bsp/hc32/ev_hc32f448_lqfp80/board/ports/SConscript

@@ -0,0 +1,12 @@
+import os
+from building import *
+
+objs = []
+cwd  = GetCurrentDir()
+
+list = os.listdir(cwd)
+for item in list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        objs = objs + SConscript(os.path.join(item, 'SConscript'))
+
+Return('objs')

bsp/hc32/ev_hc32f448_lqfp80/board/ports/drv_spi_flash.c

@@ -0,0 +1,123 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-02-20     CDT          first version
+ */
+
+#include <board.h>
+#include <drv_spi.h>
+#include <rtdevice.h>
+#include <rthw.h>
+#include <finsh.h>
+#include <dfs_fs.h>
+#include <fal.h>
+
+#ifdef BSP_USING_SPI_FLASH
+
+#include "spi_flash.h"
+#ifdef RT_USING_SFUD
+    #include "spi_flash_sfud.h"
+#endif
+
+#define SPI_BUS_NAME                    "spi1"
+#define SPI_FLASH_DEVICE_NAME           "spi10"
+#define SPI_FLASH_CHIP                  "w25q64"
+#define SPI_FLASH_SS_PORT               GPIO_PORT_C
+#define SPI_FLASH_SS_PIN                GPIO_PIN_07
+/* Partition Name */
+#define FS_PARTITION_NAME              "filesystem"
+
+#ifdef RT_USING_SFUD
+static void rt_hw_spi_flash_reset(char *spi_dev_name)
+{
+    struct rt_spi_device *spi_dev_w25;
+    rt_uint8_t w25_en_reset = 0x66;
+    rt_uint8_t w25_reset_dev = 0x99;
+
+    spi_dev_w25 = (struct rt_spi_device *)rt_device_find(spi_dev_name);
+    if (!spi_dev_w25)
+    {
+        rt_kprintf("Can't find %s device!\n", spi_dev_name);
+    }
+    else
+    {
+        rt_spi_send(spi_dev_w25, &w25_en_reset, 1U);
+        rt_spi_send(spi_dev_w25, &w25_reset_dev, 1U);
+        DDL_DelayMS(1U);
+        rt_kprintf("Reset ext flash!\n");
+    }
+}
+
+static int rt_hw_spi_flash_with_sfud_init(void)
+{
+    rt_hw_spi_device_attach(SPI_BUS_NAME, SPI_FLASH_DEVICE_NAME, SPI_FLASH_SS_PORT, SPI_FLASH_SS_PIN);
+
+    if (RT_NULL == rt_sfud_flash_probe(SPI_FLASH_CHIP, SPI_FLASH_DEVICE_NAME))
+    {
+        rt_hw_spi_flash_reset(SPI_FLASH_DEVICE_NAME);
+        if (RT_NULL == rt_sfud_flash_probe(SPI_FLASH_CHIP, SPI_FLASH_DEVICE_NAME))
+        {
+            return -RT_ERROR;
+        }
+    }
+
+    return RT_EOK;
+}
+INIT_COMPONENT_EXPORT(rt_hw_spi_flash_with_sfud_init);
+
+static int rt_hw_fs_init(void)
+{
+    struct rt_device *mtd_dev = RT_NULL;
+
+    /* 初始化 fal */
+    fal_init();
+    /* 生成 mtd 设备 */
+    mtd_dev = fal_mtd_nor_device_create(FS_PARTITION_NAME);
+    if (!mtd_dev)
+    {
+        LOG_E("Can't create a mtd device on '%s' partition.", FS_PARTITION_NAME);
+        return -RT_ERROR;
+    }
+    else
+    {
+        /* 挂载 littlefs */
+        if (RT_EOK == dfs_mount(FS_PARTITION_NAME, "/", "lfs", 0, 0))
+        {
+            LOG_I("Filesystem initialized!");
+            return RT_EOK;
+        }
+        else
+        {
+            /* 格式化文件系统 */
+            if (RT_EOK == dfs_mkfs("lfs", FS_PARTITION_NAME))
+            {
+                /* 挂载 littlefs */
+                if (RT_EOK == dfs_mount(FS_PARTITION_NAME, "/", "lfs", 0, 0))
+                {
+                    LOG_I("Filesystem initialized!");
+                    return RT_EOK;
+                }
+                else
+                {
+                    LOG_E("Failed to initialize filesystem!");
+                    return -RT_ERROR;
+                }
+            }
+            else
+            {
+                LOG_E("Failed to Format fs!");
+                return -RT_ERROR;
+            }
+        }
+    }
+}
+INIT_APP_EXPORT(rt_hw_fs_init);
+
+#endif /* RT_USING_SFUD */
+
+#endif /* BSP_USING_SPI_FLASH */

bsp/hc32/ev_hc32f448_lqfp80/board/ports/fal/SConscript

@@ -0,0 +1,20 @@
+
+from building import *
+import rtconfig
+
+cwd     = GetCurrentDir()
+
+src = []
+
+src     += Glob('*.c')
+CPPPATH = [cwd]
+LOCAL_CFLAGS = ''
+
+if rtconfig.PLATFORM in ['gcc', 'armclang']:
+    LOCAL_CFLAGS += ' -std=c99'
+elif rtconfig.PLATFORM in ['armcc']:
+    LOCAL_CFLAGS += ' --c99'
+
+group = DefineGroup('FAL', src, depend = ['RT_USING_FAL'], CPPPATH = CPPPATH, LOCAL_CFLAGS = LOCAL_CFLAGS)
+
+Return('group')

bsp/hc32/ev_hc32f448_lqfp80/board/ports/fal/fal_cfg.h

@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-02-20     CDT          first version
+ */
+
+#ifndef _FAL_CFG_H_
+#define _FAL_CFG_H_
+
+#include <rtthread.h>
+#include <board.h>
+
+/* enable hc32f4 onchip flash driver sample */
+#define FAL_FLASH_PORT_DRIVER_HC32F4
+/* enable SFUD flash driver sample */
+#define FAL_FLASH_PORT_DRIVER_SFUD
+
+extern const struct fal_flash_dev hc32_onchip_flash;
+extern struct fal_flash_dev ext_nor_flash0;
+
+/* flash device table */
+#define FAL_FLASH_DEV_TABLE                                          \
+{                                                                    \
+    &hc32_onchip_flash,                                              \
+    &ext_nor_flash0,                                                 \
+}
+
+/* ====================== Partition Configuration ========================== */
+#ifdef FAL_PART_HAS_TABLE_CFG
+/* partition table */
+#define FAL_PART_TABLE                                                                 \
+{                                                                                      \
+    {FAL_PART_MAGIC_WROD,          "app",   "onchip_flash",   0,  256 * 1024, 0},      \
+    {FAL_PART_MAGIC_WROD,   "filesystem",         "w25q64",   0,  8 * 1024 * 1024, 0}, \
+}
+#endif /* FAL_PART_HAS_TABLE_CFG */
+
+#endif /* _FAL_CFG_H_ */

bsp/hc32/ev_hc32f448_lqfp80/board/ports/fal/fal_flash_sfud_port.c

@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-02-20     CDT          first version
+ */
+
+#include <fal.h>
+
+#include <sfud.h>
+#ifdef RT_USING_SFUD
+    #include <spi_flash_sfud.h>
+#endif
+
+#ifndef FAL_USING_NOR_FLASH_DEV_NAME
+    #define FAL_USING_NOR_FLASH_DEV_NAME            "w25q64"
+#endif
+
+static int init(void);
+static int read(long offset, uint8_t *buf, size_t size);
+static int write(long offset, const uint8_t *buf, size_t size);
+static int erase(long offset, size_t size);
+
+static sfud_flash_t sfud_dev = NULL;
+struct fal_flash_dev ext_nor_flash0 =
+{
+    .name       = FAL_USING_NOR_FLASH_DEV_NAME,
+    .addr       = 0,
+    .len        = 8 * 1024 * 1024,
+    .blk_size   = 4096,
+    .ops        = {init, read, write, erase},
+    .write_gran = 1
+};
+
+static int init(void)
+{
+    /* RT-Thread RTOS platform */
+    sfud_dev = rt_sfud_flash_find_by_dev_name(FAL_USING_NOR_FLASH_DEV_NAME);
+    if (NULL == sfud_dev)
+    {
+        return -1;
+    }
+    /* update the flash chip information */
+    ext_nor_flash0.blk_size = sfud_dev->chip.erase_gran;
+    ext_nor_flash0.len      = sfud_dev->chip.capacity;
+
+    return 0;
+}
+
+static int read(long offset, uint8_t *buf, size_t size)
+{
+    assert(sfud_dev);
+    assert(sfud_dev->init_ok);
+    sfud_read(sfud_dev, ext_nor_flash0.addr + offset, size, buf);
+
+    return size;
+}
+
+static int write(long offset, const uint8_t *buf, size_t size)
+{
+    assert(sfud_dev);
+    assert(sfud_dev->init_ok);
+    if (sfud_write(sfud_dev, ext_nor_flash0.addr + offset, size, buf) != SFUD_SUCCESS)
+    {
+        return -1;
+    }
+
+    return size;
+}
+
+static int erase(long offset, size_t size)
+{
+    assert(sfud_dev);
+    assert(sfud_dev->init_ok);
+    if (sfud_erase(sfud_dev, ext_nor_flash0.addr + offset, size) != SFUD_SUCCESS)
+    {
+        return -1;
+    }
+
+    return size;
+}

bsp/hc32/ev_hc32f448_lqfp80/board/ports/tca9539.c

@@ -0,0 +1,320 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-02-20     CDT          first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <rtdbg.h>
+
+#ifdef BSP_USING_TCA9539
+
+#include "tca9539.h"
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/* Define for TCA9539 */
+#define BSP_TCA9539_I2C_BUS_NAME        "i2c1"
+#define BSP_TCA9539_DEV_ADDR            (0x74U)
+
+#define TCA9539_RST_PIN                 (32)    /* PB15 */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+static struct rt_i2c_bus_device *i2c_bus = RT_NULL;
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+/**
+ * @brief  BSP TCA9539 write data.
+ * @param  [in] bus:                    Pointer to the i2c bus device.
+ * @param  [in] reg:                    Register to be written.
+ * @param  [in] data:                   The pointer to the buffer contains the data to be written.
+ * @param  [in] len:                    Buffer size in byte.
+ * @retval rt_err_t:
+ *           - RT_EOK
+ *           - -RT_ERROR
+ */
+static rt_err_t BSP_TCA9539_I2C_Write(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint8_t *data, rt_uint16_t len)
+{
+    struct rt_i2c_msg msgs;
+    rt_uint8_t buf[6];
+
+    buf[0] = reg;
+    if (len > 0)
+    {
+        if (len < 6)
+        {
+            rt_memcpy(buf + 1, data, len);
+        }
+        else
+        {
+            return -RT_ERROR;
+        }
+    }
+    msgs.addr   = BSP_TCA9539_DEV_ADDR;
+    msgs.flags  = RT_I2C_WR;
+    msgs.buf    = buf;
+    msgs.len    = len + 1;
+    if (rt_i2c_transfer(bus, &msgs, 1) == 1)
+    {
+        return RT_EOK;
+    }
+    else
+    {
+        return -RT_ERROR;
+    }
+}
+
+/**
+ * @brief  BSP TCA9539 Read data.
+ * @param  [in] bus:                    Pointer to the i2c bus device.
+ * @param  [in] reg:                    Register to be read.
+ * @param  [out] data:                  The pointer to the buffer contains the data to be read.
+ * @param  [in] len:                    Buffer size in byte.
+ * @retval rt_err_t:
+ *           - RT_EOK
+ *           - -RT_ERROR
+ */
+static rt_err_t BSP_TCA9539_I2C_Read(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint8_t *data, rt_uint16_t len)
+{
+    struct rt_i2c_msg msgs;
+
+    if (RT_EOK != BSP_TCA9539_I2C_Write(bus, reg, RT_NULL, 0))
+    {
+        return -RT_ERROR;
+    }
+    msgs.addr   = BSP_TCA9539_DEV_ADDR;
+    msgs.flags  = RT_I2C_RD;
+    msgs.buf    = data;
+    msgs.len    = len;
+    if (rt_i2c_transfer(bus, &msgs, 1) == 1)
+    {
+        return RT_EOK;
+    }
+    else
+    {
+        return -RT_ERROR;
+    }
+}
+
+
+/**
+ * @brief  Reset TCA9539.
+ * @param  [in] None
+ * @retval None
+ */
+static void TCA9539_Reset(void)
+{
+    rt_pin_mode(TCA9539_RST_PIN, PIN_MODE_OUTPUT);
+    /* Reset the device */
+    rt_pin_write(TCA9539_RST_PIN, PIN_LOW);
+    rt_thread_mdelay(3U);
+    rt_pin_write(TCA9539_RST_PIN, PIN_HIGH);
+}
+
+/**
+ * @brief  Write TCA9539 pin output value.
+ * @param  [in] u8Port                  Port number.
+ *         This parameter can be one of the following values:
+ *           @arg @ref TCA9539_Port_Definition
+ * @param  [in] u8Pin                   Pin number.
+ *         This parameter can be one or any combination of the following values:
+ *           @arg @ref TCA9539_Pin_Definition
+ * @param  [in] u8PinState              Pin state to be written.
+ *         This parameter can be one of the following values:
+ *           @arg @ref TCA9539_Pin_State_Definition
+ * @retval rt_err_t:
+ *           - RT_ERROR
+ *           - RT_EOK
+ */
+rt_err_t TCA9539_WritePin(uint8_t u8Port, uint8_t u8Pin, uint8_t u8PinState)
+{
+    uint8_t u8TempData[2];
+
+    u8TempData[0] = u8Port + TCA9539_REG_OUTPUT_PORT0;
+    if (RT_EOK != BSP_TCA9539_I2C_Read(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
+    {
+        return -RT_ERROR;
+    }
+    if (0U == u8PinState)
+    {
+        u8TempData[1] &= (uint8_t)(~u8Pin);
+    }
+    else
+    {
+        u8TempData[1] |= u8Pin;
+    }
+    if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
+    {
+        return -RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+
+/**
+ * @brief  Read TCA9539 pin input value.
+ * @param  [in] u8Port                  Port number.
+ *         This parameter can be one of the following values:
+ *           @arg @ref TCA9539_Port_Definition
+ * @param  [in] u8Pin                   Pin number.
+ *         This parameter can be one or any combination of the following values:
+ *           @arg @ref TCA9539_Pin_Definition
+ * @param  [in] u8PinState              Pin state to be written.
+ *         This parameter can be one of the following values:
+ *           @arg @ref TCA9539_Pin_State_Definition
+ * @retval rt_err_t:
+ *           - RT_ERROR
+ *           - RT_EOK
+ */
+rt_err_t TCA9539_ReadPin(uint8_t u8Port, uint8_t u8Pin, uint8_t *pu8PinState)
+{
+    uint8_t u8TempData[2];
+
+    u8TempData[0] = u8Port + TCA9539_REG_INPUT_PORT0;
+    if (RT_EOK != BSP_TCA9539_I2C_Read(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
+    {
+        return -RT_ERROR;
+    }
+    if (0U != (u8TempData[1] & u8Pin))
+    {
+        *pu8PinState = TCA9539_PIN_SET;
+    }
+    else
+    {
+        *pu8PinState = TCA9539_PIN_RESET;
+    }
+
+    return RT_EOK;
+}
+
+/**
+ * @brief  Toggle TCA9539 pin output value.
+ * @param  [in] u8Port                  Port number.
+ *         This parameter can be one of the following values:
+ *           @arg @ref TCA9539_Port_Definition
+ * @param  [in] u8Pin                   Pin number.
+ *         This parameter can be one or any combination of the following values:
+ *           @arg @ref TCA9539_Pin_Definition
+ * @retval rt_err_t:
+ *           - -RT_ERROR
+ *           - RT_EOK
+ */
+rt_err_t TCA9539_TogglePin(uint8_t u8Port, uint8_t u8Pin)
+{
+    uint8_t u8TempData[2];
+
+    u8TempData[0] = u8Port + TCA9539_REG_OUTPUT_PORT0;
+    if (RT_EOK != BSP_TCA9539_I2C_Read(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
+    {
+        return -RT_ERROR;
+    }
+    u8TempData[1] ^= u8Pin;
+    if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
+    {
+        return -RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+
+/**
+ * @brief  Configuration TCA9539 pin.
+ * @param  [in] u8Port                  Port number.
+ *         This parameter can be one of the following values:
+ *           @arg @ref TCA9539_Port_Definition
+ * @param  [in] u8Pin                   Pin number.
+ *         This parameter can be one or any combination of the following values:
+ *           @arg @ref TCA9539_Pin_Definition
+ * @param  [in] u8Dir                   Pin output direction.
+ *         This parameter can be one of the following values:
+ *           @arg @ref TCA9539_Direction_Definition
+ * @retval rt_err_t:
+ *           - -RT_ERROR
+ *           - RT_EOK
+ */
+rt_err_t TCA9539_ConfigPin(uint8_t u8Port, uint8_t u8Pin, uint8_t u8Dir)
+{
+    uint8_t u8TempData[2];
+
+    u8TempData[0] = u8Port + TCA9539_REG_CONFIG_PORT0;
+    if (RT_EOK != BSP_TCA9539_I2C_Read(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
+    {
+        return -RT_ERROR;
+    }
+    if (TCA9539_DIR_OUT == u8Dir)
+    {
+        u8TempData[1] &= (uint8_t)(~u8Pin);
+    }
+    else
+    {
+        u8TempData[1] |= u8Pin;
+    }
+    if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
+    {
+        return -RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+
+/**
+ * @brief  Initialize TCA9539.
+ * @param  [in] None
+ * @retval rt_err_t:
+ *           - -RT_ERROR
+ *           - RT_EOK
+ */
+int TCA9539_Init(void)
+{
+    char name[RT_NAME_MAX];
+    uint8_t u8TempData[2];
+
+    TCA9539_Reset();
+    rt_strncpy(name, BSP_TCA9539_I2C_BUS_NAME, RT_NAME_MAX);
+    i2c_bus = (struct rt_i2c_bus_device *)rt_device_find(name);
+    if (i2c_bus == RT_NULL)
+    {
+        rt_kprintf("can't find %s device!\n", BSP_TCA9539_I2C_BUS_NAME);
+        return -RT_ERROR;
+    }
+    /* All Pins are input as default */
+    u8TempData[0] = TCA9539_REG_CONFIG_PORT0;
+    u8TempData[1] = 0xFFU;
+    if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
+    {
+        return -RT_ERROR;
+    }
+    u8TempData[0] = TCA9539_REG_CONFIG_PORT1;
+    if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
+    {
+        return -RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+INIT_PREV_EXPORT(TCA9539_Init);
+
+#endif /* BSP_USING_TCA9539 */

bsp/hc32/ev_hc32f448_lqfp80/board/ports/tca9539.h

@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-02-20     CDT          first version
+ */
+
+#ifndef __TCA9539_H__
+#define __TCA9539_H__
+
+#include <rtdevice.h>
+
+/**
+ * @defgroup TCA9539_REGISTER_Definition TCA9539 Register Definition
+ * @{
+ */
+#define TCA9539_REG_INPUT_PORT0         (0x00U)
+#define TCA9539_REG_INPUT_PORT1         (0x01U)
+#define TCA9539_REG_OUTPUT_PORT0        (0x02U)
+#define TCA9539_REG_OUTPUT_PORT1        (0x03U)
+#define TCA9539_REG_INVERT_PORT0        (0x04U)
+#define TCA9539_REG_INVERT_PORT1        (0x05U)
+#define TCA9539_REG_CONFIG_PORT0        (0x06U)
+#define TCA9539_REG_CONFIG_PORT1        (0x07U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TCA9539_Port_Definition TCA9539 Port Definition
+ * @{
+ */
+#define TCA9539_IO_PORT0                (0x00U)
+#define TCA9539_IO_PORT1                (0x01U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TCA9539_Pin_Definition TCA9539 Pin Definition
+ * @{
+ */
+#define TCA9539_IO_PIN0                 (0x01U)
+#define TCA9539_IO_PIN1                 (0x02U)
+#define TCA9539_IO_PIN2                 (0x04U)
+#define TCA9539_IO_PIN3                 (0x08U)
+#define TCA9539_IO_PIN4                 (0x10U)
+#define TCA9539_IO_PIN5                 (0x20U)
+#define TCA9539_IO_PIN6                 (0x40U)
+#define TCA9539_IO_PIN7                 (0x80U)
+#define TCA9539_IO_PIN_ALL              (0xFFU)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TCA9539_Direction_Definition TCA9539 Direction Definition
+ * @{
+ */
+#define TCA9539_DIR_OUT                 (0x00U)
+#define TCA9539_DIR_IN                  (0x01U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TCA9539_Pin_State_Definition TCA9539 Pin State Definition
+ * @{
+ */
+#define TCA9539_PIN_RESET               (0x00U)
+#define TCA9539_PIN_SET                 (0x01U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup HC32F448_EV_IO_Function_Sel Expand IO function definition
+ * @{
+ */
+#define EIO_SCI_CD                      (TCA9539_IO_PIN1)   /* Smart card detect, input */
+#define EIO_TOUCH_INT                   (TCA9539_IO_PIN2)   /* Touch screen interrupt, input */
+#define EIO_TOUCH_CTRST                 (TCA9539_IO_PIN5)   /* 'Reset' for Cap touch panel, output */
+#define EIO_LCD_RST                     (TCA9539_IO_PIN6)   /* LCD panel reset, output */
+#define EIO_LCD_BKL                     (TCA9539_IO_PIN7)   /* LCD panel back light, output */
+
+#define EIO_LIN_SLEEP                   (TCA9539_IO_PIN1)   /* LIN PHY sleep, output */
+#define EIO_CAN1_STB                    (TCA9539_IO_PIN2)   /* CAN1 PHY standby, output */
+#define EIO_CAN2_STB                    (TCA9539_IO_PIN3)   /* CAN2 PHY standby, output */
+#define EIO_LED_RED                     (TCA9539_IO_PIN5)   /* Red LED, output */
+#define EIO_LED_YELLOW                  (TCA9539_IO_PIN6)   /* Yellow LED, output */
+#define EIO_LED_BLUE                    (TCA9539_IO_PIN7)   /* Blue LED, output */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup BSP_LED_PortPin_Sel BSP LED port/pin definition
+ * @{
+ */
+#define LED_PORT                        (TCA9539_IO_PORT1)
+#define LED_RED_PORT                    (TCA9539_IO_PORT1)
+#define LED_RED_PIN                     (EIO_LED_RED)
+#define LED_YELLOW_PORT                 (TCA9539_IO_PORT1)
+#define LED_YELLOW_PIN                  (EIO_LED_YELLOW)
+#define LED_BLUE_PORT                   (TCA9539_IO_PORT1)
+#define LED_BLUE_PIN                    (EIO_LED_BLUE)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup  BSP CAN PHY STB port/pin definition
+ * @{
+ */
+#define CAN1_STB_PORT                   (TCA9539_IO_PORT1)
+#define CAN1_STB_PIN                    (EIO_CAN1_STB)
+#define CAN2_STB_PORT                   (TCA9539_IO_PORT1)
+#define CAN2_STB_PIN                    (EIO_CAN2_STB)
+/**
+ * @}
+ */
+
+int TCA9539_Init(void);
+rt_err_t TCA9539_WritePin(uint8_t u8Port, uint8_t u8Pin, uint8_t u8PinState);
+rt_err_t TCA9539_ReadPin(uint8_t u8Port, uint8_t u8Pin, uint8_t *pu8PinState);
+rt_err_t TCA9539_TogglePin(uint8_t u8Port, uint8_t u8Pin);
+rt_err_t TCA9539_ConfigPin(uint8_t u8Port, uint8_t u8Pin, uint8_t u8Dir);
+
+#endif

bsp/hc32/ev_hc32f448_lqfp80/jlink/ev_hc32f448_lqfp80 Debug.launch

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+    <intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+    <stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
+    <stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/rtthread.elf"/>
+    <stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="project"/>
+    <booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
+    <stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.553091094"/>
+    <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+        <listEntry value="/project"/>
+    </listAttribute>
+    <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+        <listEntry value="4"/>
+    </listAttribute>
+    <stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;Context string&quot;/&gt;&#13;&#10;"/>
+    <stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>

bsp/hc32/ev_hc32f448_lqfp80/project.eww

@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+  <project>
+    <path>$WS_DIR$\project.ewp</path>
+  </project>
+  <batchBuild/>
+</workspace>
+
+

bsp/hc32/ev_hc32f448_lqfp80/project.uvoptx

@@ -0,0 +1,189 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj; *.o</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc; *.md</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+    <nMigrate>0</nMigrate>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>rt-thread</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>8000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\build\keil\List\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <bEvRecOn>1</bEvRecOn>
+        <bSchkAxf>0</bSchkAxf>
+        <bTchkAxf>0</bTchkAxf>
+        <nTsel>3</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\CMSIS_AGDI.dll</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>CMSIS_AGDI</Key>
+          <Name>-X"" -O206 -S0 -C0 -P00 -FO15 -FD1FFF8000 -FC4000 -FN2 -FF0HC32F448_256K -FS00 -FL080000 -FP0($$Device:HC32F448MCTI$FlashARM\HC32F448_256K.FLM) -FF1HC32F448_otp -FS13000C00 -FL1400 -FP1($$Device:HC32F448MCTI$FlashARM\HC32F448_otp.FLM)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>UL2CM3(-S0 -C0 -P0 -FD1FFF8000 -FC1000 -FN1 -FF0HC32F448_256K -FS00 -FL080000 -FP0($$Device:HC32F448MCTI$FlashARM\HC32F448_256K.FLM))</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>CMSIS_AGDI</Key>
+          <Name>-X"" -O206 -S0 -C0 -P00 -FO15 -FD1FFF8000 -FC4000 -FN2 -FF0HC32F448_256K -FS00 -FL080000 -FP0($$Device:HC32F448MCTI$FlashARM\HC32F448_256K.FLM) -FF1HC32F448_otp -FS13000C00 -FL1400 -FP1($$Device:HC32F448MCTI$FlashARM\HC32F448_otp.FLM)</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+      <bAutoGenD>0</bAutoGenD>
+      <LntExFlags>0</LntExFlags>
+      <pMisraName></pMisraName>
+      <pszMrule></pszMrule>
+      <pSingCmds></pSingCmds>
+      <pMultCmds></pMultCmds>
+      <pMisraNamep></pMisraNamep>
+      <pszMrulep></pszMrulep>
+      <pSingCmdsp></pSingCmdsp>
+      <pMultCmdsp></pMultCmdsp>
+      <DebugDescription>
+        <Enable>1</Enable>
+        <EnableFlashSeq>0</EnableFlashSeq>
+        <EnableLog>0</EnableLog>
+        <Protocol>2</Protocol>
+        <DbgClock>1000000</DbgClock>
+      </DebugDescription>
+    </TargetOption>
+  </Target>
+
+</ProjectOpt>

bsp/hc32/ev_hc32f448_lqfp80/project.uvprojx

@@ -0,0 +1,867 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+  <SchemaVersion>2.1</SchemaVersion>
+  <Header>### uVision Project, (C) Keil Software</Header>
+  <Targets>
+    <Target>
+      <TargetName>rt-thread</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
+      <uAC6>0</uAC6>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>HC32F448MCTI</Device>
+          <Vendor>HDSC</Vendor>
+          <PackID>HDSC.HC32F448.1.0.0</PackID>
+          <PackURL>https://raw.githubusercontent.com/hdscmcu/pack/master/</PackURL>
+          <Cpu>IROM1(0x00000000,0x40000) IROM2(0x03000C00,0x400) IRAM1(0x1FFF8000,0x10000) IRAM2(0x200F0000,0x1000) CPUTYPE("Cortex-M4") FPU2 CLOCK(8000000) ESEL ELITTLE</Cpu>
+          <FlashUtilSpec />
+          <StartupFile />
+          <FlashDriverDll>CMSIS_AGDI(-S0 -C0 -P00 -FO15 -FD1FFF8000 -FC4000 -FN2 -FF0HC32F448_256K -FS00 -FL0080000 -FP0($$Device:HC32F448PETB$FlashARM\HC32F448_256K.FLM) -FF1HC32F448_otp -FS13000C00 -FL1400 -FP1($$Device:HC32F448MCTI$FlashARM\HC32F448_otp.FLM))</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:HC32F448MCTI$Device\Include\HC32F448MCTI.h</RegisterFile>
+          <MemoryEnv />
+          <Cmp />
+          <Asm />
+          <Linker />
+          <OHString />
+          <InfinionOptionDll />
+          <SLE66CMisc />
+          <SLE66AMisc />
+          <SLE66LinkerMisc />
+          <SFDFile>../libraries/hc32f448_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/sfr/HC32F448.SFR</SFDFile>
+          <bCustSvd>1</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath />
+          <IncludePath />
+          <LibPath />
+          <RegisterFilePath />
+          <DBRegisterFilePath />
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\build\keil\Obj\</OutputDirectory>
+          <OutputName>rt-thread</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>1</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>0</BrowseInformation>
+          <ListingPath>.\build\keil\List\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name />
+            <UserProg2Name />
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name />
+            <UserProg2Name />
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>1</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
+            <UserProg2Name />
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString />
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument />
+          <IncludeLibraryModules />
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments> -REMAP -MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments> -MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3 />
+          <Flash4 />
+          <pFcarmOut />
+          <pFcarmGrp />
+          <pFcArmRoot />
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M4"</AdsCpuType>
+            <RvctDeviceName />
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>1</RvdsVP>
+            <RvdsMve>0</RvdsMve>
+            <RvdsCdeCp>0</RvdsCdeCp>
+            <hadIRAM2>1</hadIRAM2>
+            <hadIROM2>1</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>1</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x1FFF8000</StartAddress>
+                <Size>0x10000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x03000C00</StartAddress>
+                <Size>0x400</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x1FFF8000</StartAddress>
+                <Size>0x10000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x200F0000</StartAddress>
+                <Size>0x1000</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector />
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <uGnu>0</uGnu>
+            <useXO>0</useXO>
+            <v6Lang>0</v6Lang>
+            <v6LangP>0</v6LangP>
+            <vShortEn>0</vShortEn>
+            <vShortWch>0</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls />
+              <Define>__STDC_LIMIT_MACROS, RT_USING_ARMLIBC, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, USE_DDL_DRIVER, __RTTHREAD__, __DEBUG, HC32F448</Define>
+              <Undefine />
+              <IncludePath>applications;board;..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\inc;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\libraries\hc32f448_ddl\drivers\cmsis\Include;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\libc\posix\ipc;..\libraries\hc32_drivers;..\..\..\components\finsh;.;..\..\..\include;board\ports;..\..\..\components\libc\compilers\common\include;..\..\..\components\libc\posix\io\epoll;..\..\..\libcpu\arm\cortex-m4;board\config;..\..\..\libcpu\arm\common;..\..\..\components\libc\posix\io\eventfd;..\libraries\hc32f448_ddl\drivers\cmsis\Device\HDSC\hc32f4xx\Include;..\..\..\components\libc\compilers\common\extension;..\..\..\components\libc\posix\io\poll</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <uClangAs>0</uClangAs>
+            <VariousControls>
+              <MiscControls />
+              <Define />
+              <Undefine />
+              <IncludePath />
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>0</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x1FFF8000</DataAddressRange>
+            <pXoBase />
+            <ScatterFile>.\board\linker_scripts\link.sct</ScatterFile>
+            <IncludeLibs />
+            <IncludeLibsPath />
+            <Misc />
+            <LinkerInputFile />
+            <DisabledWarnings />
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Applications</GroupName>
+          <Files>
+            <File>
+              <FileName>xtal32_fcm.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>applications\xtal32_fcm.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>applications\main.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Compiler</GroupName>
+          <Files>
+            <File>
+              <FileName>syscall_mem.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\libc\compilers\armlibc\syscall_mem.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>syscalls.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\libc\compilers\armlibc\syscalls.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>cctype.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\libc\compilers\common\cctype.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>cstdlib.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\libc\compilers\common\cstdlib.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>cstring.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\libc\compilers\common\cstring.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>ctime.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\libc\compilers\common\ctime.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>cunistd.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\libc\compilers\common\cunistd.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>cwchar.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\libc\compilers\common\cwchar.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>DeviceDrivers</GroupName>
+          <Files>
+            <File>
+              <FileName>device.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\core\device.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>completion.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\ipc\completion.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>dataqueue.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\ipc\dataqueue.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>pipe.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\ipc\pipe.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>ringblk_buf.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\ipc\ringblk_buf.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>ringbuffer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\ipc\ringbuffer.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>waitqueue.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\ipc\waitqueue.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>workqueue.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\ipc\workqueue.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>pin.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\misc\pin.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>serial.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\serial\serial.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Drivers</GroupName>
+          <Files>
+            <File>
+              <FileName>board.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>board\board.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>board_config.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>board\board_config.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>startup_hc32f448.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\libraries\hc32f448_ddl\drivers\cmsis\Device\HDSC\hc32f4xx\Source\ARM\startup_hc32f448.s</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>drv_common.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\hc32_drivers\drv_common.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>drv_gpio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\hc32_drivers\drv_gpio.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>drv_irq.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\hc32_drivers\drv_irq.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>drv_usart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\hc32_drivers\drv_usart.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Finsh</GroupName>
+          <Files>
+            <File>
+              <FileName>shell.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\finsh\shell.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>msh.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\finsh\msh.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>msh_parse.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\finsh\msh_parse.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>cmd.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\finsh\cmd.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Kernel</GroupName>
+          <Files>
+            <File>
+              <FileName>clock.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\clock.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>components.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\components.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>idle.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\idle.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>ipc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\ipc.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>irq.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\irq.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>kservice.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\kservice.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>mem.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\mem.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>mempool.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\mempool.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>object.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\object.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>scheduler_up.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\scheduler_up.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>thread.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\thread.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>timer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\timer.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>libcpu</GroupName>
+          <Files>
+            <File>
+              <FileName>atomic_arm.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\libcpu\arm\common\atomic_arm.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>div0.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\libcpu\arm\common\div0.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>showmem.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\libcpu\arm\common\showmem.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>context_rvds.S</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\..\..\libcpu\arm\cortex-m4\context_rvds.S</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>cpuport.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\libcpu\arm\cortex-m4\cpuport.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Libraries</GroupName>
+          <Files>
+            <File>
+              <FileName>hc32_ll_clk.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\src\hc32_ll_clk.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>hc32_ll_icg.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\src\hc32_ll_icg.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>hc32_ll_utility.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\src\hc32_ll_utility.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>hc32_ll_fcg.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\src\hc32_ll_fcg.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>hc32_ll_interrupts.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\src\hc32_ll_interrupts.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>hc32_ll_sram.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\src\hc32_ll_sram.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>hc32_ll_pwc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\src\hc32_ll_pwc.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>hc32_ll_aos.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\src\hc32_ll_aos.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>hc32_ll_fcm.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\src\hc32_ll_fcm.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>hc32_ll.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\src\hc32_ll.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>system_hc32f448.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\hc32f448_ddl\drivers\cmsis\Device\HDSC\hc32f4xx\Source\system_hc32f448.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>hc32_ll_efm.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\src\hc32_ll_efm.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>hc32_ll_gpio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\src\hc32_ll_gpio.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>hc32_ll_usart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\src\hc32_ll_usart.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>hc32_ll_rmu.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\src\hc32_ll_rmu.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>hc32_ll_tmr0.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\src\hc32_ll_tmr0.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>hc32_ll_dma.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\src\hc32_ll_dma.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+  <RTE>
+    <apis />
+    <components />
+    <files />
+  </RTE>
+</Project>

bsp/hc32/ev_hc32f448_lqfp80/rtconfig.h

@@ -0,0 +1,276 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_CPUS_NR 1
+#define RT_ALIGN_SIZE 8
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 1000
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_HOOK_USING_FUNC_PTR
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 256
+
+/* kservice optimization */
+
+#define RT_USING_DEBUG
+#define RT_DEBUGING_COLOR
+#define RT_DEBUGING_CONTEXT
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_SMALL_MEM_AS_HEAP
+#define RT_USING_HEAP
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart2"
+#define RT_VER_NUM 0x50100
+#define RT_BACKTRACE_LEVEL_MAX_NR 32
+#define RT_USING_HW_ATOMIC
+#define RT_USING_CPU_FFS
+#define ARCH_ARM
+#define ARCH_ARM_CORTEX_M
+#define ARCH_ARM_CORTEX_M4
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+#define RT_USING_MSH
+#define RT_USING_FINSH
+#define FINSH_USING_MSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_CMD_SIZE 80
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
+#define FINSH_ARG_MAX 10
+#define FINSH_USING_OPTION_COMPLETION
+
+/* DFS: device virtual file system */
+
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_UNAMED_PIPE_NUMBER 64
+#define RT_USING_SYSTEM_WORKQUEUE
+#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
+#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
+#define RT_USING_SERIAL
+#define RT_USING_SERIAL_V1
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+
+/* Using USB */
+
+
+/* C/C++ and POSIX layer */
+
+/* ISO-ANSI C layer */
+
+/* Timezone and Daylight Saving Time */
+
+#define RT_LIBC_USING_LIGHT_TZ_DST
+#define RT_LIBC_TZ_DEFAULT_HOUR 8
+#define RT_LIBC_TZ_DEFAULT_MIN 0
+#define RT_LIBC_TZ_DEFAULT_SEC 0
+
+/* POSIX (Portable Operating System Interface) layer */
+
+
+/* Interprocess Communication (IPC) */
+
+
+/* Socket is in the 'Network' category */
+
+
+/* Network */
+
+
+/* Memory protection */
+
+
+/* Utilities */
+
+
+/* RT-Thread Utestcases */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* CYW43012 WiFi */
+
+
+/* BL808 WiFi */
+
+
+/* CYW43439 WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
+
+
+/* XML: Extensible Markup Language */
+
+
+/* multimedia packages */
+
+/* LVGL: powerful and easy-to-use embedded GUI library */
+
+
+/* u8g2: a monochrome graphic library */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+/* enhanced kernel services */
+
+
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
+
+/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
+
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
+/* peripheral libraries and drivers */
+
+/* sensors drivers */
+
+
+/* touch drivers */
+
+
+/* Kendryte SDK */
+
+
+/* AI packages */
+
+
+/* Signal Processing and Control Algorithm Packages */
+
+
+/* miscellaneous packages */
+
+/* project laboratory */
+
+/* samples: kernel and components samples */
+
+
+/* entertainment: terminal games and other interesting software packages */
+
+
+/* Arduino libraries */
+
+
+/* Projects and Demos */
+
+
+/* Sensors */
+
+
+/* Display */
+
+
+/* Timing */
+
+
+/* Data Processing */
+
+
+/* Data Storage */
+
+/* Communication */
+
+
+/* Device Control */
+
+
+/* Other */
+
+
+/* Signal IO */
+
+
+/* Uncategorized */
+
+#define SOC_FAMILY_HC32
+#define SOC_SERIES_HC32F4
+
+/* Hardware Drivers Config */
+
+#define SOC_HC32F448MC
+
+/* On-chip Drivers */
+
+#define BSP_USING_ON_CHIP_FLASH_CACHE
+#define BSP_USING_ON_CHIP_FLASH_ICODE_CACHE
+#define BSP_USING_ON_CHIP_FLASH_DCODE_CACHE
+#define BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH
+
+/* Onboard Peripheral Drivers */
+
+
+/* On-chip Peripheral Drivers */
+
+#define BSP_USING_GPIO
+#define BSP_USING_UART
+#define BSP_USING_UART2
+#define BSP_UART2_RX_USING_DMA
+#define BSP_UART2_TX_USING_DMA
+
+/* Board extended module Drivers */
+
+
+#endif

bsp/hc32/ev_hc32f448_lqfp80/rtconfig.py

@@ -0,0 +1,150 @@
+import os
+
+# toolchains options
+ARCH='arm'
+CPU='cortex-m4'
+CROSS_TOOL='gcc'
+
+# bsp lib config
+BSP_LIBRARY_TYPE = None
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
+if  CROSS_TOOL == 'gcc':
+    PLATFORM    = 'gcc'
+    if os.getenv('RTT_EXEC_PATH'):
+        EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+    else:
+        EXEC_PATH   = r'C:/Users/XXYYZZ'
+elif CROSS_TOOL == 'keil':
+    PLATFORM    = 'armcc'
+    EXEC_PATH   = r'C:/Keil_v5'
+elif CROSS_TOOL == 'iar':
+    PLATFORM    = 'iccarm'
+    EXEC_PATH   = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.4'
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'arm-none-eabi-'
+    CC = PREFIX + 'gcc'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    CXX = PREFIX + 'g++'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+
+    DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections'
+    CFLAGS = DEVICE + ' -Dgcc'
+    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.ld'
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2 -g'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    CXXFLAGS = CFLAGS 
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+    # toolchains
+    CC = 'armcc'
+    CXX = 'armcc'
+    AS = 'armasm'
+    AR = 'armar'
+    LINK = 'armlink'
+    TARGET_EXT = 'axf'
+
+    DEVICE = ' --cpu Cortex-M4.fp '
+    CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
+    AFLAGS = DEVICE + ' --apcs=interwork '
+    LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict'
+    CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
+    LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib'
+
+    CFLAGS += ' -D__MICROLIB '
+    AFLAGS += ' --pd "__MICROLIB SETA 1" '
+    LFLAGS += ' --library_type=microlib '
+    EXEC_PATH += '/ARM/ARMCC/bin/'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -g -O0'
+        AFLAGS += ' -g'
+    else:
+        CFLAGS += ' -O2'
+
+    CXXFLAGS = CFLAGS 
+    CFLAGS += ' -std=c99'
+
+    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+
+elif PLATFORM == 'iccarm':
+    # toolchains
+    CC = 'iccarm'
+    CXX = 'iccarm'
+    AS = 'iasmarm'
+    AR = 'iarchive'
+    LINK = 'ilinkarm'
+    TARGET_EXT = 'out'
+
+    DEVICE = '-Dewarm'
+
+    CFLAGS = DEVICE
+    CFLAGS += ' --diag_suppress Pa050'
+    CFLAGS += ' --no_cse'
+    CFLAGS += ' --no_unroll'
+    CFLAGS += ' --no_inline'
+    CFLAGS += ' --no_code_motion'
+    CFLAGS += ' --no_tbaa'
+    CFLAGS += ' --no_clustering'
+    CFLAGS += ' --no_scheduling'
+    CFLAGS += ' --endian=little'
+    CFLAGS += ' --cpu=Cortex-M4'
+    CFLAGS += ' -e'
+    CFLAGS += ' --fpu=VFPv4_sp'
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
+    CFLAGS += ' --silent'
+
+    AFLAGS = DEVICE
+    AFLAGS += ' -s+'
+    AFLAGS += ' -w+'
+    AFLAGS += ' -r'
+    AFLAGS += ' --cpu Cortex-M4'
+    AFLAGS += ' --fpu VFPv4_sp'
+    AFLAGS += ' -S'
+
+    if BUILD == 'debug':
+        CFLAGS += ' --debug'
+        CFLAGS += ' -On'
+    else:
+        CFLAGS += ' -Oh'
+
+    LFLAGS = ' --config "board/linker_scripts/link.icf"'
+    LFLAGS += ' --entry __iar_program_start'
+
+    CXXFLAGS = CFLAGS
+    
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
+    POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
+
+def dist_handle(BSP_ROOT, dist_dir):
+    import sys
+    cwd_path = os.getcwd()
+    sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
+    from sdk_dist import dist_do_building
+    dist_do_building(BSP_ROOT, dist_dir)

bsp/hc32/ev_hc32f448_lqfp80/template.eww

@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+  <project>
+    <path>$WS_DIR$\template.ewp</path>
+  </project>
+  <batchBuild/>
+</workspace>
+
+

bsp/hc32/ev_hc32f448_lqfp80/template.uvoptx

@@ -0,0 +1,189 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj; *.o</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc; *.md</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+    <nMigrate>0</nMigrate>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>rt-thread</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>8000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\build\keil\List\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <bEvRecOn>1</bEvRecOn>
+        <bSchkAxf>0</bSchkAxf>
+        <bTchkAxf>0</bTchkAxf>
+        <nTsel>3</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\CMSIS_AGDI.dll</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>CMSIS_AGDI</Key>
+          <Name>-X"" -O206 -S0 -C0 -P00 -FO15 -FD1FFF8000 -FC4000 -FN2 -FF0HC32F448_256K -FS00 -FL080000 -FP0($$Device:HC32F448MCTI$FlashARM\HC32F448_256K.FLM) -FF1HC32F448_otp -FS13000C00 -FL1400 -FP1($$Device:HC32F448MCTI$FlashARM\HC32F448_otp.FLM)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>UL2CM3(-S0 -C0 -P0 -FD1FFF8000 -FC1000 -FN1 -FF0HC32F448_256K -FS00 -FL080000 -FP0($$Device:HC32F448MCTI$FlashARM\HC32F448_256K.FLM))</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>CMSIS_AGDI</Key>
+          <Name>-X"" -O206 -S0 -C0 -P00 -FO15 -FD1FFF8000 -FC4000 -FN2 -FF0HC32F448_256K -FS00 -FL080000 -FP0($$Device:HC32F448MCTI$FlashARM\HC32F448_256K.FLM) -FF1HC32F448_otp -FS13000C00 -FL1400 -FP1($$Device:HC32F448MCTI$FlashARM\HC32F448_otp.FLM)</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+      <bAutoGenD>0</bAutoGenD>
+      <LntExFlags>0</LntExFlags>
+      <pMisraName></pMisraName>
+      <pszMrule></pszMrule>
+      <pSingCmds></pSingCmds>
+      <pMultCmds></pMultCmds>
+      <pMisraNamep></pMisraNamep>
+      <pszMrulep></pszMrulep>
+      <pSingCmdsp></pSingCmdsp>
+      <pMultCmdsp></pMultCmdsp>
+      <DebugDescription>
+        <Enable>1</Enable>
+        <EnableFlashSeq>0</EnableFlashSeq>
+        <EnableLog>0</EnableLog>
+        <Protocol>2</Protocol>
+        <DbgClock>1000000</DbgClock>
+      </DebugDescription>
+    </TargetOption>
+  </Target>
+
+</ProjectOpt>

bsp/hc32/ev_hc32f448_lqfp80/template.uvprojx

@@ -0,0 +1,391 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>rt-thread</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
+      <uAC6>0</uAC6>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>HC32F448MCTI</Device>
+          <Vendor>HDSC</Vendor>
+          <PackID>HDSC.HC32F448.1.0.0</PackID>
+          <PackURL>https://raw.githubusercontent.com/hdscmcu/pack/master/</PackURL>
+          <Cpu>IROM1(0x00000000,0x40000) IROM2(0x03000C00,0x400) IRAM1(0x1FFF8000,0x10000) IRAM2(0x200F0000,0x1000) CPUTYPE("Cortex-M4") FPU2 CLOCK(8000000) ESEL ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>CMSIS_AGDI(-S0 -C0 -P00 -FO15 -FD1FFF8000 -FC4000 -FN2 -FF0HC32F448_256K -FS00 -FL0080000 -FP0($$Device:HC32F448PETB$FlashARM\HC32F448_256K.FLM) -FF1HC32F448_otp -FS13000C00 -FL1400 -FP1($$Device:HC32F448MCTI$FlashARM\HC32F448_otp.FLM))</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:HC32F448MCTI$Device\Include\HC32F448MCTI.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>../libraries/hc32f448_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/sfr/HC32F448.SFR</SFDFile>
+          <bCustSvd>1</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\build\keil\Obj\</OutputDirectory>
+          <OutputName>rt-thread</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>1</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>0</BrowseInformation>
+          <ListingPath>.\build\keil\List\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>1</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments> -REMAP -MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments> -MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M4"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>1</RvdsVP>
+            <RvdsMve>0</RvdsMve>
+            <RvdsCdeCp>0</RvdsCdeCp>
+            <hadIRAM2>1</hadIRAM2>
+            <hadIROM2>1</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>1</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x1FFF8000</StartAddress>
+                <Size>0x10000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x03000C00</StartAddress>
+                <Size>0x400</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x1FFF8000</StartAddress>
+                <Size>0x10000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x200F0000</StartAddress>
+                <Size>0x1000</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <uGnu>0</uGnu>
+            <useXO>0</useXO>
+            <v6Lang>0</v6Lang>
+            <v6LangP>0</v6LangP>
+            <vShortEn>0</vShortEn>
+            <vShortWch>0</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <uClangAs>0</uClangAs>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>0</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x1FFF8000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile>.\board\linker_scripts\link.sct</ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components/>
+    <files/>
+  </RTE>
+
+</Project>

bsp/hc32/ev_hc32f4a0_lqfp176/board/Kconfig

@@ -64,11 +64,22 @@ menu "Onboard Peripheral Drivers"
                 endif
         endif
 
-    config BSP_USING_TCA9539
-        bool "Enable TCA9539"
-        select BSP_USING_I2C
-        select BSP_USING_I2C1
+    config BSP_USING_EXMC
+        bool "Enable EXMC"
         default n
+        if BSP_USING_EXMC
+            choice
+                prompt "Using SDRAM or NAND"
+                default BSP_USING_NAND
+
+                config BSP_USING_NAND
+                    bool "Using NAND (MT29F2G08AB)"
+                    select RT_USING_MTD_NAND
+
+                config BSP_USING_SDRAM
+                    bool "Using SDRAM (IS42S16400J7TLI)"
+            endchoice
+        endif
 
     config BSP_USING_SPI_FLASH
         bool "Enable SPI FLASH (w25q64 spi1)"
@@ -81,11 +92,10 @@ menu "Onboard Peripheral Drivers"
         select RT_USING_MTD_NOR
         default n
 
-    config BSP_USING_MT29F2G08AB
-        bool "Enable NAND FLASH (MT29F2G08AB)"
-        select BSP_USING_EXMC
-        select BSP_USING_NAND
-        select RT_USING_MTD_NAND
+    config BSP_USING_TCA9539
+        bool "Enable TCA9539"
+        select BSP_USING_I2C
+        select BSP_USING_I2C1
         default n
 
 endmenu
@@ -633,24 +643,6 @@ menu "On-chip Peripheral Drivers"
                 default n
         endif
 
-    menuconfig BSP_USING_EXMC
-        bool "Enable EXMC"
-        default n
-        select BSP_USING_EXMC
-        if BSP_USING_EXMC
-            choice
-                prompt "Using SDRAM or Nand"
-                default BSP_USING_SDRAM
-
-                config BSP_USING_SDRAM
-                    bool "Using SDRAM"
-
-                config BSP_USING_NAND
-                    bool "Using Nand"
-                    select RT_USING_MTD_NAND
-            endchoice
-        endif
-
     menuconfig BSP_USING_PM
         bool "Enable PM"
         default n

bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/sdram_port.h

@@ -6,6 +6,8 @@
  * Change Logs:
  * Date           Author       Notes
  * 2023-02-24     CDT          first version
+ * 2024-02-20     CDT          modify timing configuration for using exclk clock frequency 30MHz
+ *                             add t_rcd/t_rfc/t_rp configuration macros-definition
  */
 
 #ifndef __SDRAM_PORT_H__
@@ -39,21 +41,24 @@
 /* write burst mode: SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED/SINGLE */
 #define SDRAM_MODEREG_WRITEBURST_MODE   SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED
 
-/* timing configuration(EXCLK clock frequency: 60MHz) for IS42S16400J-7TLI */
+/* timing configuration(EXCLK clock frequency: 30MHz) for IS42S16400J-7TLI */
 /* refresh rate counter (EXCLK clock) */
-#define SDRAM_REFRESH_COUNT             (900U)
+#define SDRAM_REFRESH_COUNT             (450U)
 /* TMDR: mode register command time (EXCLK clock) */
 #define SDRAM_TMDR                      2U
 /* TRAS: RAS to precharge delay time (EXCLK clock) */
-#define SDRAM_TRAS                      3U
+#define SDRAM_TRAS                      2U
 /* TRC:  active bank x to active bank x delay time (EXCLK clock) */
-#define SDRAM_TRC                       4U
+#define SDRAM_TRC                       2U
 /* TRCD: RAS to CAS minimum delay time (EXCLK clock) */
-#define SDRAM_TRCD                      1U
+#define SDRAM_TRCD_B                    3U
+#define SDRAM_TRCD_P                    0U
 /* TRFC: autorefresh command time (EXCLK clock) */
-#define SDRAM_TRFC                      4U
+#define SDRAM_TRFC_B                    3U
+#define SDRAM_TRFC_P                    0U
 /* TRP:  precharge to RAS delay time (EXCLK clock) */
-#define SDRAM_TRP                       1U
+#define SDRAM_TRP_B                     3U
+#define SDRAM_TRP_P                     0U
 /* TRRD: active bank x to active bank y delay time (EXCLK clock) */
 #define SDRAM_TRRD                      1U
 /* TWR: write to precharge delay time (EXCLK clock). */

bsp/hc32/libraries/.ignore_format.yml

@@ -5,3 +5,4 @@
 dir_path:
 - hc32f4a0_ddl
 - hc32f460_ddl
+- hc32f448_ddl

bsp/hc32/libraries/hc32_drivers/drv_adc.c

@@ -8,6 +8,8 @@
  * 2022-04-28     CDT                  first version
  * 2022-06-08     xiaoxiaolisunny      add hc32f460 series
  * 2022-06-14     CDT                  fix a bug of internal trigger
+ * 2024-02-20     CDT                  support HC32F448
+ *                                     add function for associating with the dma
  */
 
 #include <board.h>
@@ -29,6 +31,19 @@ typedef struct
 
 #if defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2) || defined(BSP_USING_ADC3)
 
+enum
+{
+#ifdef BSP_USING_ADC1
+    ADC1_INDEX,
+#endif
+#ifdef BSP_USING_ADC2
+    ADC2_INDEX,
+#endif
+#ifdef BSP_USING_ADC3
+    ADC3_INDEX,
+#endif
+};
+
 static adc_device _g_adc_dev_array[] =
 {
 #ifdef BSP_USING_ADC1
@@ -116,12 +131,24 @@ static rt_err_t _adc_enable(struct rt_adc_device *device, rt_int8_t channel, rt_
 {
     adc_device *p_adc_dev = rt_container_of(device, adc_device, rt_adc);
     ADC_ChCmd(p_adc_dev->instance, ADC_SEQ_A, channel, (en_functional_state_t)enabled);
+
+    /* user_data != NULL */
+    if (device->parent.user_data != RT_NULL)
+    {
+        struct adc_dev_priv_params *adc_dev_priv = device->parent.user_data;
+        if ((ADC_USING_EOCA_DMA_FLAG == adc_dev_priv->flag) && (adc_dev_priv->ops->dma_trig_config != RT_NULL))
+        {
+            adc_dev_priv->ops->dma_trig_config();
+        }
+    }
+
     return 0;
 }
 
 static rt_err_t _adc_convert(struct rt_adc_device *device, rt_int8_t channel, rt_uint32_t *value)
 {
     rt_err_t rt_ret = -RT_ERROR;
+    rt_uint32_t timeCnt;
 
     if (!value)
     {
@@ -129,7 +156,9 @@ static rt_err_t _adc_convert(struct rt_adc_device *device, rt_int8_t channel, rt
     }
 
     adc_device *p_adc_dev = rt_container_of(device, adc_device, rt_adc);
-    if (p_adc_dev->init.hard_trig_enable == RT_FALSE && p_adc_dev->instance->STR == 0)
+    if (p_adc_dev->init.hard_trig_enable == RT_FALSE)
+    {
+        if (p_adc_dev->instance->STR == 0)
         {
             ADC_Start(p_adc_dev->instance);
         }
@@ -151,6 +180,45 @@ static rt_err_t _adc_convert(struct rt_adc_device *device, rt_int8_t channel, rt
             /* Get any ADC value of sequence A channel that needed. */
             *value = ADC_GetValue(p_adc_dev->instance, channel);
         }
+    }
+    else if (p_adc_dev->init.hard_trig_enable == RT_TRUE)
+    {
+        /* DMA src/dest/tc... config; start/stop trigger */
+        if (p_adc_dev->init.adc_eoca_dma != RT_NULL)
+        {
+            if (p_adc_dev->rt_adc.parent.user_data != RT_NULL)
+            {
+                struct adc_dev_priv_params *adc_dev_priv = device->parent.user_data;
+                struct dma_config *adc_eoca_dma;
+                adc_eoca_dma = p_adc_dev->init.adc_eoca_dma;
+                if ((ADC_USING_EOCA_DMA_FLAG == adc_dev_priv->flag) && (adc_dev_priv->ops->dma_trig_start != RT_NULL))
+                {
+                    DMA_ClearTransCompleteStatus(adc_eoca_dma->Instance, adc_eoca_dma->flag);
+                    (void)DMA_SetTransCount(adc_eoca_dma->Instance, adc_eoca_dma->channel, 1U);
+                    (void)DMA_SetSrcAddr(adc_eoca_dma->Instance, adc_eoca_dma->channel, (uint32_t)(&p_adc_dev->instance->DR0) + channel * 2);
+                    (void)DMA_SetDestAddr(adc_eoca_dma->Instance, adc_eoca_dma->channel, (uint32_t)(value));
+                    (void)DMA_ChCmd(adc_eoca_dma->Instance, adc_eoca_dma->channel, ENABLE);
+                    adc_dev_priv->ops->dma_trig_start();
+                    timeCnt = 0;
+                    /* wait DMA transfer completed */
+                    while (RESET == DMA_GetTransCompleteStatus(adc_eoca_dma->Instance, adc_eoca_dma->flag) && (timeCnt < p_adc_dev->init.eoc_poll_time_max))
+                    {
+                        rt_thread_mdelay(1);
+                        timeCnt++;
+                    }
+                    if (timeCnt >= p_adc_dev->init.eoc_poll_time_max)
+                    {
+                        (void)DMA_ChCmd(adc_eoca_dma->Instance, adc_eoca_dma->channel, DISABLE);
+                        rt_ret = -RT_ETIMEOUT;
+                    }
+                    if (adc_dev_priv->ops->dma_trig_stop != RT_NULL)
+                    {
+                        adc_dev_priv->ops->dma_trig_stop();
+                    }
+                }
+            }
+        }
+    }
 
     return rt_ret;
 }
@@ -212,6 +280,51 @@ static void _adc_clock_enable(void)
 #endif
 }
 
+static void hc32_adc_get_dma_info(void)
+{
+#ifdef  BSP_ADC1_USING_DMA
+    static struct dma_config adc1_eoca_dma = ADC1_EOCA_DMA_CONFIG;
+    _g_adc_dev_array[ADC1_INDEX].init.adc_eoca_dma = &adc1_eoca_dma;
+#endif
+
+#ifdef  BSP_ADC2_USING_DMA
+    static struct dma_config adc2_eoca_dma = ADC2_EOCA_DMA_CONFIG;
+    _g_adc_dev_array[ADC2_INDEX].init.adc_eoca_dma = &adc2_eoca_dma;
+#endif
+
+#ifdef  BSP_ADC3_USING_DMA
+    static struct dma_config adc3_eoca_dma = ADC3_EOCA_DMA_CONFIG;
+    _g_adc_dev_array[ADC3_INDEX].init.adc_eoca_dma = &adc3_eoca_dma;
+#endif
+}
+
+static void hc32_adc_dma_config(adc_device *p_adc_dev)
+{
+    stc_dma_init_t stcDmaInit;
+
+    /* DMA/AOS FCG enable */
+    FCG_Fcg0PeriphClockCmd(p_adc_dev->init.adc_eoca_dma->clock, ENABLE);
+
+    (void)DMA_StructInit(&stcDmaInit);
+    stcDmaInit.u32BlockSize  = 1UL;
+    stcDmaInit.u32TransCount = 1UL;
+    stcDmaInit.u32DataWidth  = DMA_DATAWIDTH_16BIT;
+    stcDmaInit.u32SrcAddrInc  = DMA_SRC_ADDR_FIX;
+    stcDmaInit.u32DestAddrInc = DMA_DEST_ADDR_FIX;
+    stcDmaInit.u32SrcAddr     = (uint32_t)RT_NULL;
+    stcDmaInit.u32DestAddr    = (uint32_t)RT_NULL;
+    if (LL_OK != DMA_Init(p_adc_dev->init.adc_eoca_dma->Instance, p_adc_dev->init.adc_eoca_dma->channel, &stcDmaInit))
+    {
+        rt_kprintf("[%s:%d]ADC DMA init error!\n", __func__, __LINE__);
+    }
+    AOS_SetTriggerEventSrc(p_adc_dev->init.adc_eoca_dma->trigger_select, p_adc_dev->init.adc_eoca_dma->trigger_event);
+
+    /* Clear DMA TC flag */
+    DMA_ClearTransCompleteStatus(p_adc_dev->init.adc_eoca_dma->Instance, p_adc_dev->init.adc_eoca_dma->flag);
+    /* Enable DMA unit */
+    DMA_Cmd(p_adc_dev->init.adc_eoca_dma->Instance, ENABLE);
+}
+
 extern rt_err_t rt_hw_board_adc_init(CM_ADC_TypeDef *ADCx);
 int rt_hw_adc_init(void)
 {
@@ -220,6 +333,7 @@ int rt_hw_adc_init(void)
     int32_t ll_ret = 0;
 
     _adc_clock_enable();
+    hc32_adc_get_dma_info();
     uint32_t dev_cnt = sizeof(_g_adc_dev_array) / sizeof(_g_adc_dev_array[0]);
     for (; i < dev_cnt; i++)
     {
@@ -243,6 +357,11 @@ int rt_hw_adc_init(void)
             _adc_internal_trigger1_set(&_g_adc_dev_array[i]);
         }
 
+        if (_g_adc_dev_array[i].init.adc_eoca_dma != RT_NULL)
+        {
+            hc32_adc_dma_config(&_g_adc_dev_array[i]);
+        }
+
         rt_hw_board_adc_init((void *)_g_adc_dev_array[i].instance);
         ret = rt_hw_adc_register(&_g_adc_dev_array[i].rt_adc, \
                                  (const char *)_g_adc_dev_array[i].init.name, \

bsp/hc32/libraries/hc32_drivers/drv_adc.h

@@ -6,6 +6,7 @@
  * Change Logs:
  * Date           Author       Notes
  * 2022-04-28     CDT          first version
+ * 2024-02-20     CDT          add structure for associating with the dma
  */
 
 
@@ -16,7 +17,10 @@
  * Include files
  ******************************************************************************/
 #include <rtthread.h>
-#include "rtdevice.h"
+#include <rtdevice.h>
+#include "board_config.h"
+#include "drv_irq.h"
+#include "drv_dma.h"
 
 #include "hc32_ll.h"
 
@@ -51,11 +55,26 @@ struct adc_dev_init_params
     rt_bool_t continue_conv_mode_enable;
     rt_bool_t data_reg_auto_clear;
     uint32_t eoc_poll_time_max;
+    struct dma_config *adc_eoca_dma;
+};
+
+struct adc_dev_dma_priv_ops
+{
+    rt_err_t (*dma_trig_start)(void);
+    rt_err_t (*dma_trig_stop)(void);
+    rt_err_t (*dma_trig_config)(void);
+};
+
+struct adc_dev_priv_params
+{
+    uint32_t flag;
+    struct adc_dev_dma_priv_ops *ops;
 };
 
 /*******************************************************************************
  * Global pre-processor symbols/macros ('#define')
  ******************************************************************************/
+#define ADC_USING_EOCA_DMA_FLAG     (1U)
 
 /*******************************************************************************
  * Global variable definitions ('extern')

bsp/hc32/libraries/hc32_drivers/drv_gpio.c

@@ -6,6 +6,7 @@
  * Change Logs:
  * Date           Author       Notes
  * 2022-04-28     CDT          first version
+ * 2023-10-09     CDT          support HC32F448
  */
 
 #include <rtthread.h>
@@ -26,6 +27,8 @@
     #define PIN_MAX_NUM                     ((GPIO_PORT_I * 16) + (__CLZ(__RBIT(GPIO_PIN_13))) + 1)
 #elif defined (HC32F460)
     #define PIN_MAX_NUM                     ((GPIO_PORT_H * 16) + (__CLZ(__RBIT(GPIO_PIN_02))) + 1)
+#elif defined (HC32F448)
+    #define PIN_MAX_NUM                     ((GPIO_PORT_H * 16) + (__CLZ(__RBIT(GPIO_PIN_02))) + 1)
 #endif
 
 #define ITEM_NUM(items)                 sizeof(items) / sizeof(items[0])

bsp/hc32/libraries/hc32_drivers/drv_hwtimer.c

@@ -6,6 +6,7 @@
  * Change Logs:
  * Date           Author            Notes
  * 2023-06-21     CDT               first version
+ * 2024-02-20     CDT               support HC32F448
  */
 
 #include <rtdevice.h>
@@ -144,12 +145,20 @@ static void _timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state)
         (void)TMRA_Init(tmr_device->tmr_handle, &stcTmraInit);
 
         TMRA_IntCmd(tmr_device->tmr_handle, TMRA_INT_OVF, ENABLE);
+#if defined (HC32F460) || defined (HC32F4A0)
         hc32_install_irq_handler(&irq_config, tmr_device->isr.irq_callback, RT_TRUE);
+#elif defined (HC32F448)
+        hc32_install_independ_irq_handler(&irq_config, RT_TRUE);
+#endif
     }
     else    /* close */
     {
         TMRA_DeInit(tmr_device->tmr_handle);
+#if defined (HC32F460) || defined (HC32F4A0)
         hc32_install_irq_handler(&irq_config, tmr_device->isr.irq_callback, RT_FALSE);
+#elif defined (HC32F448)
+        hc32_install_independ_irq_handler(&irq_config, RT_FALSE);
+#endif
         FCG_Fcg2PeriphClockCmd(tmr_device->clock, DISABLE);
     }
 }
@@ -238,84 +247,130 @@ static void TMRA_1_callback(void)
     TMRA_ClearStatus(hc32_hwtimer_obj[TMRA_1_INDEX].tmr_handle, hc32_hwtimer_obj[TMRA_1_INDEX].flag);
     rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_1_INDEX].time_device);
 }
-#endif
+
+#if defined (HC32F448)
+void TMRA_1_Ovf_Udf_Handler(void)
+{
+    TMRA_1_callback();
+}
+#endif /* HC32F448 */
+#endif /* BSP_USING_TMRA_1 */
+
 #ifdef BSP_USING_TMRA_2
 static void TMRA_2_callback(void)
 {
     TMRA_ClearStatus(hc32_hwtimer_obj[TMRA_2_INDEX].tmr_handle, hc32_hwtimer_obj[TMRA_2_INDEX].flag);
     rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_2_INDEX].time_device);
 }
-#endif
+
+#if defined (HC32F448)
+void TMRA_2_Ovf_Udf_Handler(void)
+{
+    TMRA_2_callback();
+}
+#endif /* HC32F448 */
+#endif /* BSP_USING_TMRA_2 */
+
 #ifdef BSP_USING_TMRA_3
 static void TMRA_3_callback(void)
 {
     TMRA_ClearStatus(hc32_hwtimer_obj[TMRA_3_INDEX].tmr_handle, hc32_hwtimer_obj[TMRA_3_INDEX].flag);
     rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_3_INDEX].time_device);
 }
-#endif
+
+#if defined (HC32F448)
+void TMRA_3_Ovf_Udf_Handler(void)
+{
+    TMRA_3_callback();
+}
+#endif /* HC32F448 */
+#endif /* BSP_USING_TMRA_3 */
+
 #ifdef BSP_USING_TMRA_4
 static void TMRA_4_callback(void)
 {
     TMRA_ClearStatus(hc32_hwtimer_obj[TMRA_4_INDEX].tmr_handle, hc32_hwtimer_obj[TMRA_4_INDEX].flag);
     rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_4_INDEX].time_device);
 }
-#endif
+
+#if defined (HC32F448)
+void TMRA_4_Ovf_Udf_Handler(void)
+{
+    TMRA_4_callback();
+}
+#endif /* HC32F448 */
+#endif /* BSP_USING_TMRA_4 */
+
 #ifdef BSP_USING_TMRA_5
 static void TMRA_5_callback(void)
 {
     TMRA_ClearStatus(hc32_hwtimer_obj[TMRA_5_INDEX].tmr_handle, hc32_hwtimer_obj[TMRA_5_INDEX].flag);
     rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_5_INDEX].time_device);
 }
-#endif
+
+#if defined (HC32F448)
+void TMRA_5_Ovf_Udf_Handler(void)
+{
+    TMRA_5_callback();
+}
+#endif /* HC32F448 */
+#endif /* BSP_USING_TMRA_5 */
+
 #ifdef BSP_USING_TMRA_6
 static void TMRA_6_callback(void)
 {
     TMRA_ClearStatus(hc32_hwtimer_obj[TMRA_6_INDEX].tmr_handle, hc32_hwtimer_obj[TMRA_6_INDEX].flag);
     rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_6_INDEX].time_device);
 }
-#endif
+#endif /* BSP_USING_TMRA_6 */
+
 #ifdef BSP_USING_TMRA_7
 static void TMRA_7_callback(void)
 {
     TMRA_ClearStatus(hc32_hwtimer_obj[TMRA_7_INDEX].tmr_handle, hc32_hwtimer_obj[TMRA_7_INDEX].flag);
     rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_7_INDEX].time_device);
 }
-#endif
+#endif /* BSP_USING_TMRA_7 */
+
 #ifdef BSP_USING_TMRA_8
 static void TMRA_8_callback(void)
 {
     TMRA_ClearStatus(hc32_hwtimer_obj[TMRA_8_INDEX].tmr_handle, hc32_hwtimer_obj[TMRA_8_INDEX].flag);
     rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_8_INDEX].time_device);
 }
-#endif
+#endif /* BSP_USING_TMRA_8 */
+
 #ifdef BSP_USING_TMRA_9
 static void TMRA_9_callback(void)
 {
     TMRA_ClearStatus(hc32_hwtimer_obj[TMRA_9_INDEX].tmr_handle, hc32_hwtimer_obj[TMRA_9_INDEX].flag);
     rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_9_INDEX].time_device);
 }
-#endif
+#endif /* BSP_USING_TMRA_9 */
+
 #ifdef BSP_USING_TMRA_10
 static void TMRA_10_callback(void)
 {
     TMRA_ClearStatus(hc32_hwtimer_obj[TMRA_10_INDEX].tmr_handle, hc32_hwtimer_obj[TMRA_10_INDEX].flag);
     rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_10_INDEX].time_device);
 }
-#endif
+#endif /* BSP_USING_TMRA_10 */
+
 #ifdef BSP_USING_TMRA_11
 static void TMRA_11_callback(void)
 {
     TMRA_ClearStatus(hc32_hwtimer_obj[TMRA_11_INDEX].tmr_handle, hc32_hwtimer_obj[TMRA_11_INDEX].flag);
     rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_11_INDEX].time_device);
 }
-#endif
+#endif /* BSP_USING_TMRA_11 */
+
 #ifdef BSP_USING_TMRA_12
 static void TMRA_12_callback(void)
 {
     TMRA_ClearStatus(hc32_hwtimer_obj[TMRA_12_INDEX].tmr_handle, hc32_hwtimer_obj[TMRA_12_INDEX].flag);
     rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_12_INDEX].time_device);
 }
-#endif
+#endif /* BSP_USING_TMRA_12 */
 
 static struct rt_hwtimer_info _info[sizeof(hc32_hwtimer_obj) / sizeof(hc32_hwtimer_obj[0])];
 

bsp/hc32/libraries/hc32_drivers/drv_i2c.c

@@ -317,6 +317,7 @@ static int I2C_Master_Transmit_DMA(struct hc32_i2c *i2c_obj, struct rt_i2c_msg *
 
     if (msg->len > 1U)
     {
+        DMA_ClearTransCompleteStatus(i2c_tx_dma->Instance, i2c_tx_dma->flag);
         (void)DMA_SetTransCount(i2c_tx_dma->Instance, i2c_tx_dma->channel, msg->len - 1U);
         (void)DMA_SetSrcAddr(i2c_tx_dma->Instance, i2c_tx_dma->channel, (uint32_t)(&msg->buf[1]));
         (void)DMA_ChCmd(i2c_tx_dma->Instance, i2c_tx_dma->channel, ENABLE);
@@ -362,6 +363,7 @@ static int I2C_Master_Receive_DMA(struct hc32_i2c *i2c_obj, struct rt_i2c_msg *m
     }
     else if (msg->len > 2U)
     {
+        DMA_ClearTransCompleteStatus(i2c_rx_dma->Instance, i2c_rx_dma->flag);
         (void)DMA_SetTransCount(i2c_rx_dma->Instance, i2c_rx_dma->channel, msg->len - 2U);
         (void)DMA_SetDestAddr(i2c_rx_dma->Instance, i2c_rx_dma->channel, (uint32_t)(&msg->buf[0]));
         (void)DMA_ChCmd(i2c_rx_dma->Instance, i2c_rx_dma->channel, ENABLE);

bsp/hc32/libraries/hc32_drivers/drv_irq.c

@@ -68,6 +68,28 @@ rt_err_t hc32_install_irq_handler(struct hc32_irq_config *irq_config,
     return result;
 }
 
+#if defined (HC32F448)
+rt_err_t hc32_install_independ_irq_handler(struct hc32_irq_config *irq_config,
+        rt_bool_t irq_enable)
+{
+    RT_ASSERT(RT_NULL != irq_config);
+
+    NVIC_ClearPendingIRQ(irq_config->irq_num);
+    NVIC_SetPriority(irq_config->irq_num, irq_config->irq_prio);
+    if (RT_TRUE == irq_enable)
+    {
+        INTC_IntSrcCmd(irq_config->int_src, ENABLE);
+        NVIC_EnableIRQ(irq_config->irq_num);
+    }
+    else
+    {
+        INTC_IntSrcCmd(irq_config->int_src, DISABLE);
+        NVIC_DisableIRQ(irq_config->irq_num);
+    }
+    return RT_EOK;
+}
+#endif
+
 /*******************************************************************************
  * EOF (not truncated)
  ******************************************************************************/

bsp/hc32/libraries/hc32_drivers/drv_irq.h

@@ -47,6 +47,10 @@ struct hc32_irq_config
 rt_err_t hc32_install_irq_handler(struct hc32_irq_config *irq_config,
                                   void (*irq_hdr)(void),
                                   rt_bool_t irq_enable);
+#if defined (HC32F448)
+rt_err_t hc32_install_independ_irq_handler(struct hc32_irq_config *irq_config,
+        rt_bool_t irq_enable);
+#endif
 
 #ifdef __cplusplus
 }

bsp/hc32/libraries/hc32_drivers/drv_pm.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd.
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/hc32/libraries/hc32_drivers/drv_sdram.c

@@ -6,6 +6,8 @@
  * Change Logs:
  * Date           Author       Notes
  * 2023-02-24     CDT          first version
+ * 2024-02-20     CDT          modify exclk clock max frequency to 40MHz for HC32F4A0
+ *                             add t_rcd_p/t_rfc_p/t_rp_p configuration
  */
 
 
@@ -82,8 +84,8 @@ static rt_int32_t _sdram_verify_clock_frequency(void)
     rt_int32_t ret = RT_EOK;
 
 #if defined (HC32F4A0)
-    /* EXCLK max frequency for SDRAM: 60MHz */
-    if (CLK_GetBusClockFreq(CLK_BUS_EXCLK) > (60 * 1000000))
+    /* EXCLK max frequency for SDRAM: 40MHz */
+    if (CLK_GetBusClockFreq(CLK_BUS_EXCLK) > (40 * 1000000))
     {
         ret = -RT_ERROR;
     }
@@ -131,12 +133,12 @@ static rt_int32_t _sdram_init(void)
     stcDmcInit.stcTimingConfig.u8MRD   = SDRAM_TMDR;
     stcDmcInit.stcTimingConfig.u8RAS   = SDRAM_TRAS;
     stcDmcInit.stcTimingConfig.u8RC    = SDRAM_TRC;
-    stcDmcInit.stcTimingConfig.u8RCD_B = SDRAM_TRCD;
-    stcDmcInit.stcTimingConfig.u8RCD_P = 0U;
-    stcDmcInit.stcTimingConfig.u8RFC_B = SDRAM_TRFC;
-    stcDmcInit.stcTimingConfig.u8RFC_P = 0U;
-    stcDmcInit.stcTimingConfig.u8RP_B  = SDRAM_TRP;
-    stcDmcInit.stcTimingConfig.u8RP_P  = 0U;
+    stcDmcInit.stcTimingConfig.u8RCD_B = SDRAM_TRCD_B;
+    stcDmcInit.stcTimingConfig.u8RCD_P = SDRAM_TRCD_P;
+    stcDmcInit.stcTimingConfig.u8RFC_B = SDRAM_TRFC_B;
+    stcDmcInit.stcTimingConfig.u8RFC_P = SDRAM_TRFC_P;
+    stcDmcInit.stcTimingConfig.u8RP_B  = SDRAM_TRP_B;
+    stcDmcInit.stcTimingConfig.u8RP_P  = SDRAM_TRP_P;
     stcDmcInit.stcTimingConfig.u8RRD   = SDRAM_TRRD;
     stcDmcInit.stcTimingConfig.u8WR    = SDRAM_TWR;
     stcDmcInit.stcTimingConfig.u8WTR   = SDRAM_TWTR;

bsp/hc32/libraries/hc32_drivers/drv_spi.c

@@ -7,6 +7,7 @@
  * Date           Author       Notes
  * 2022-04-28     CDT          first version
  * 2023-09-30     CDT          Delete dma transmit interrupt
+ * 2024-02-20     CDT          support HC32F448
  */
 
 /*******************************************************************************
@@ -292,6 +293,9 @@ static rt_err_t hc32_spi_init(struct hc32_spi *spi_drv, struct rt_spi_configurat
 #endif
 
     /* Enable error interrupt */
+#if defined (HC32F448)
+    INTC_IntSrcCmd(spi_drv->config->err_irq.irq_config.int_src, ENABLE);
+#endif
     NVIC_EnableIRQ(spi_drv->config->err_irq.irq_config.irq_num);
     SPI_IntCmd(spi_instance, SPI_INT_ERR, ENABLE);
 
@@ -302,14 +306,24 @@ static rt_err_t hc32_spi_init(struct hc32_spi *spi_drv, struct rt_spi_configurat
 static void hc32_spi_enable(CM_SPI_TypeDef *SPIx)
 {
     /* Check if the SPI is already enabled */
+#if defined (HC32F460) || defined (HC32F4A0)
     if ((SPIx->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
     {
         SPI_Cmd(SPIx, ENABLE);
     }
+#elif defined (HC32F448)
+    if ((SPIx->CR & SPI_CR_SPE) != SPI_CR_SPE)
+    {
+        SPI_Cmd(SPIx, ENABLE);
+    }
+#else
+#error "Please select first the target HC32xxxx device used in your application."
+#endif
 }
 
 static void hc32_spi_set_trans_mode(CM_SPI_TypeDef *SPIx, uint32_t u32Mode)
 {
+#if defined (HC32F460) || defined (HC32F4A0)
     if (SPI_SEND_ONLY == u32Mode)
     {
         SET_REG32_BIT(SPIx->CR1, SPI_CR1_TXMDS);
@@ -318,12 +332,30 @@ static void hc32_spi_set_trans_mode(CM_SPI_TypeDef *SPIx, uint32_t u32Mode)
     {
         CLR_REG32_BIT(SPIx->CR1, SPI_CR1_TXMDS);
     }
+#elif defined (HC32F448)
+    if (SPI_SEND_ONLY == u32Mode)
+    {
+        SET_REG32_BIT(SPIx->CR, SPI_CR_TXMDS);
+    }
+    else
+    {
+        CLR_REG32_BIT(SPIx->CR, SPI_CR_TXMDS);
+    }
+#else
+#error "Please select first the target HC32xxxx device used in your application."
+#endif
 }
 
 #ifdef BSP_SPI_USING_DMA
 static uint32_t hc32_spi_get_trans_mode(CM_SPI_TypeDef *SPIx)
 {
+#if defined (HC32F460) || defined (HC32F4A0)
     return READ_REG32_BIT(SPIx->CR1, SPI_CR1_TXMDS);
+#elif defined (HC32F448)
+    return READ_REG32_BIT(SPIx->CR, SPI_CR_TXMDS);
+#else
+#error "Please select first the target HC32xxxx device used in your application."
+#endif
 }
 
 /**
@@ -647,6 +679,10 @@ rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name,
 
 static void hc32_spi_err_irq_handle(struct hc32_spi *spi)
 {
+#if defined (HC32F448)
+#define SPI_FLAG_OVERLOAD       SPI_FLAG_OVERRUN
+#define SPI_FLAG_UNDERLOAD      SPI_FLAG_UNDERRUN
+#endif
     __UNUSED uint32_t UnusedData;
     CM_SPI_TypeDef *spi_instance = spi->config->Instance;
 
@@ -678,7 +714,15 @@ static void hc32_spi1_err_irq_handler(void)
     /* leave interrupt */
     rt_interrupt_leave();
 }
-#endif
+
+#if defined (HC32F448)
+void SPI1_Handler(void)
+{
+    hc32_spi1_err_irq_handler();
+}
+#endif /* HC32F448 */
+
+#endif /* BSP_USING_SPI1 */
 
 #if defined(BSP_USING_SPI2)
 static void hc32_spi2_err_irq_handler(void)
@@ -689,7 +733,14 @@ static void hc32_spi2_err_irq_handler(void)
     /* leave interrupt */
     rt_interrupt_leave();
 }
-#endif
+#if defined (HC32F448)
+void SPI2_Handler(void)
+{
+    hc32_spi2_err_irq_handler();
+}
+#endif /* HC32F448 */
+
+#endif /* BSP_USING_SPI2 */
 
 #if defined(BSP_USING_SPI3)
 static void hc32_spi3_err_irq_handler(void)
@@ -700,7 +751,14 @@ static void hc32_spi3_err_irq_handler(void)
     /* leave interrupt */
     rt_interrupt_leave();
 }
-#endif
+#if defined (HC32F448)
+void SPI3_Handler(void)
+{
+    hc32_spi3_err_irq_handler();
+}
+#endif /* HC32F448 */
+
+#endif /* BSP_USING_SPI3 */
 
 #if defined(BSP_USING_SPI4)
 static void hc32_spi4_err_irq_handler(void)
@@ -711,7 +769,7 @@ static void hc32_spi4_err_irq_handler(void)
     /* leave interrupt */
     rt_interrupt_leave();
 }
-#endif
+#endif /* BSP_USING_SPI4 */
 
 #if defined(BSP_USING_SPI5)
 static void hc32_spi5_err_irq_handler(void)
@@ -722,7 +780,7 @@ static void hc32_spi5_err_irq_handler(void)
     /* leave interrupt */
     rt_interrupt_leave();
 }
-#endif
+#endif /* BSP_USING_SPI5 */
 
 #if defined(BSP_USING_SPI6)
 static void hc32_spi6_err_irq_handler(void)
@@ -733,7 +791,7 @@ static void hc32_spi6_err_irq_handler(void)
     /* leave interrupt */
     rt_interrupt_leave();
 }
-#endif
+#endif /* BSP_USING_SPI6 */
 
 
 /**
@@ -848,7 +906,12 @@ static int hc32_hw_spi_bus_init(void)
         spi_bus_obj[i].config = &spi_config[i];
         spi_bus_obj[i].spi_bus.parent.user_data = &spi_config[i];
         /* register the handle */
+#if defined (HC32F460) || defined (HC32F4A0)
         hc32_install_irq_handler(&spi_config[i].err_irq.irq_config, spi_config[i].err_irq.irq_callback, RT_FALSE);
+#elif defined (HC32F488)
+        INTC_IntSrcCmd(spi_config[i].err_irq.irq_config.int_src, DISABLE);
+        NVIC_DisableIRQ(spi_config[i].err_irq.irq_config.irq_num);
+#endif
         result = rt_spi_bus_register(&spi_bus_obj[i].spi_bus, spi_config[i].bus_name, &hc32_spi_ops);
         LOG_D("%s bus init done", spi_config[i].bus_name);
     }

bsp/hc32/libraries/hc32_drivers/drv_usart.c

@@ -6,6 +6,7 @@
  * Change Logs:
  * Date           Author       Notes
  * 2022-04-28     CDT          first version
+ * 2023-10-09     CDT          support HC32F448
  */
 
 /*******************************************************************************
@@ -17,10 +18,10 @@
 
 #ifdef RT_USING_SERIAL
 
-#if defined(BSP_USING_UART1) || defined(BSP_USING_UART2) || defined(BSP_USING_UART3) || \
-    defined(BSP_USING_UART4) || defined(BSP_USING_UART5) || defined(BSP_USING_UART6) || \
-    defined(BSP_USING_UART7) || defined(BSP_USING_UART8) || defined(BSP_USING_UART9) || \
-    defined(BSP_USING_UART10)
+#if defined (BSP_USING_UART1) || defined (BSP_USING_UART2) || defined (BSP_USING_UART3) || \
+    defined (BSP_USING_UART4) || defined (BSP_USING_UART5) || defined (BSP_USING_UART6) || \
+    defined (BSP_USING_UART7) || defined (BSP_USING_UART8) || defined (BSP_USING_UART9) || \
+    defined (BSP_USING_UART10)
 
 #include "drv_usart.h"
 #include "board_config.h"
@@ -41,16 +42,12 @@
 #define DMA_TRANS_CNT(unit, ch)                                                \
     (READ_REG32(DMA_CH_REG((unit)->MONDTCTL0, (ch))) >> DMA_DTCTL_CNT_POS)
 
-#define USART_TCI_ENABLE(unit)                                                 \
-    SET_REG32_BIT(unit->CR1, USART_INT_TX_CPLT)
-
-
 #define UART_BAUDRATE_ERR_MAX           (0.025F)
 
 #if defined (HC32F460)
     #define FCG_USART_CLK               FCG_Fcg1PeriphClockCmd
 
-#elif defined (HC32F4A0)
+#elif defined (HC32F4A0) || defined (HC32F448)
     #define FCG_USART_CLK               FCG_Fcg3PeriphClockCmd
 
 #endif
@@ -165,6 +162,9 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_co
 #elif defined (HC32F460)
     if ((CM_USART1 == uart->config->Instance) || (CM_USART2 == uart->config->Instance) || \
             (CM_USART3 == uart->config->Instance) || (CM_USART4 == uart->config->Instance))
+#elif defined (HC32F448)
+    if ((CM_USART1 == uart->config->Instance) || (CM_USART2 == uart->config->Instance) || \
+            (CM_USART4 == uart->config->Instance) || (CM_USART5 == uart->config->Instance))
 #endif
     {
         uart_init.u32CKOutput = USART_CK_OUTPUT_ENABLE;
@@ -220,7 +220,7 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_co
     {
         uart_init.u32FirstBit = USART_FIRST_BIT_MSB;
     }
-#if defined (HC32F4A0)
+#if defined (HC32F4A0) || defined (HC32F448)
     switch (cfg->flowcontrol)
     {
     case RT_SERIAL_FLOWCONTROL_NONE:
@@ -238,7 +238,7 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_co
 #ifdef RT_SERIAL_USING_DMA
     if (!(serial->parent.open_flag & RT_DEVICE_OFLAG_OPEN))
     {
-        uart->dma_rx_remain_index = (serial->config.bufsz <= 1UL) ? serial->config.bufsz : serial->config.bufsz / 2;
+        uart->dma_rx_remaining_cnt = (serial->config.bufsz <= 1UL) ? serial->config.bufsz : serial->config.bufsz / 2;
     }
 #endif
     /* Enable USART clock */
@@ -271,6 +271,11 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_co
     /* Enable error interrupt */
 #if defined (HC32F460) || defined (HC32F4A0)
     NVIC_EnableIRQ(uart->config->rxerr_irq.irq_config.irq_num);
+#elif defined (HC32F448)
+    INTC_IntSrcCmd(uart->config->tx_int_src, ENABLE);
+    INTC_IntSrcCmd(uart->config->rx_int_src, DISABLE);
+    INTC_IntSrcCmd(uart->config->rxerr_int_src, ENABLE);
+    NVIC_EnableIRQ(uart->config->irq_num);
 #endif
     USART_FuncCmd(uart->config->Instance, USART_TX | USART_RX | USART_INT_RX, ENABLE);
 
@@ -294,8 +299,9 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg
         {
 #if defined (HC32F460) || defined (HC32F4A0)
             NVIC_DisableIRQ(uart->config->rx_irq.irq_config.irq_num);
-            USART_FuncCmd(uart->config->Instance, USART_INT_RX, DISABLE);
             INTC_IrqSignOut(uart->config->rx_irq.irq_config.irq_num);
+#elif defined (HC32F448)
+            INTC_IntSrcCmd(uart->config->rx_int_src, DISABLE);
 #endif
         }
         else if (RT_DEVICE_FLAG_INT_TX == ctrl_arg)
@@ -304,6 +310,8 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg
             NVIC_DisableIRQ(uart->config->tx_irq.irq_config.irq_num);
             USART_FuncCmd(uart->config->Instance, USART_INT_TX_EMPTY, DISABLE);
             INTC_IrqSignOut(uart->config->tx_irq.irq_config.irq_num);
+#elif defined (HC32F448)
+            USART_FuncCmd(uart->config->Instance, USART_INT_TX_EMPTY, DISABLE);
 #endif
         }
 #ifdef RT_SERIAL_USING_DMA
@@ -313,6 +321,7 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg
         }
         else if (RT_DEVICE_FLAG_DMA_TX == ctrl_arg)
         {
+            USART_FuncCmd(uart->config->Instance, USART_INT_TX_CPLT, DISABLE);
             NVIC_DisableIRQ(uart->config->dma_tx->irq_config.irq_num);
         }
 #endif
@@ -327,10 +336,23 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg
         }
         else
         {
+            INTC_IrqSignOut(uart->config->tx_irq.irq_config.irq_num);
             hc32_install_irq_handler(&uart->config->tx_irq.irq_config, uart->config->tx_irq.irq_callback, RT_TRUE);
             USART_FuncCmd(uart->config->Instance, USART_TX, DISABLE);
             USART_FuncCmd(uart->config->Instance, USART_TX | USART_INT_TX_EMPTY, ENABLE);
         }
+#elif defined (HC32F448)
+        /* NVIC config */
+        if (RT_DEVICE_FLAG_INT_RX == ctrl_arg)
+        {
+            /* intsrc enable */
+            INTC_IntSrcCmd(uart->config->rx_int_src, ENABLE);
+            USART_FuncCmd(uart->config->Instance, USART_INT_RX, ENABLE);
+        }
+        else
+        {
+            USART_FuncCmd(uart->config->Instance, USART_TX | USART_INT_TX_EMPTY, ENABLE);
+        }
 #endif
         break;
 #ifdef RT_SERIAL_USING_DMA
@@ -388,7 +410,10 @@ static int hc32_getc(struct rt_serial_device *serial)
     return ch;
 }
 
-static rt_ssize_t hc32_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction)
+static rt_ssize_t hc32_dma_transmit(struct rt_serial_device *serial,
+                                    rt_uint8_t *buf,
+                                    rt_size_t size,
+                                    int direction)
 {
 #ifdef RT_SERIAL_USING_DMA
     struct hc32_uart *uart;
@@ -397,7 +422,7 @@ static rt_ssize_t hc32_dma_transmit(struct rt_serial_device *serial, rt_uint8_t
     RT_ASSERT(RT_NULL != serial);
     RT_ASSERT(RT_NULL != buf);
 
-    if (size == 0)
+    if (0 == size)
     {
         return 0;
     }
@@ -455,10 +480,12 @@ static void hc32_uart_rxerr_irq_handler(struct hc32_uart *uart)
 static void hc32_uart_rx_timeout(struct rt_serial_device *serial)
 {
     struct hc32_uart *uart;
-    uint32_t cmp_val;
     CM_TMR0_TypeDef *TMR0_Instance;
     uint8_t ch;
-    uint32_t timeout_bits;
+    uint32_t rtb;
+    uint32_t alpha;
+    uint32_t ckdiv;
+    uint32_t cmp_val;
     stc_tmr0_init_t stcTmr0Init;
 
     RT_ASSERT(RT_NULL != serial);
@@ -467,7 +494,7 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial)
 
     TMR0_Instance = uart->config->rx_timeout->TMR0_Instance;
     ch            = uart->config->rx_timeout->channel;
-    timeout_bits  = uart->config->rx_timeout->timeout_bits;
+    rtb           = uart->config->rx_timeout->timeout_bits;
 #if defined (HC32F460)
     if ((CM_USART1 == uart->config->Instance) || (CM_USART3 == uart->config->Instance))
     {
@@ -486,6 +513,15 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial)
     {
         RT_ASSERT(TMR0_CH_B == ch);
     }
+#elif defined (HC32F448)
+    if ((CM_USART1 == uart->config->Instance) || (CM_USART4 == uart->config->Instance))
+    {
+        RT_ASSERT(TMR0_CH_A == ch);
+    }
+    else if ((CM_USART2 == uart->config->Instance) || (CM_USART5 == uart->config->Instance))
+    {
+        RT_ASSERT(TMR0_CH_B == ch);
+    }
 #endif
 
     FCG_TMR0_CLK(uart->config->rx_timeout->clock, ENABLE);
@@ -497,16 +533,25 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial)
     stcTmr0Init.u32ClockSrc = TMR0_CLK_SRC_XTAL32;
     if (TMR0_CLK_DIV1 == stcTmr0Init.u32ClockDiv)
     {
-        cmp_val = (timeout_bits - 4UL);
+        alpha = 7UL;
     }
     else if (TMR0_CLK_DIV2 == stcTmr0Init.u32ClockDiv)
     {
-        cmp_val = (timeout_bits / 2UL - 2UL);
+        alpha = 5UL;
+    }
+    else if ((TMR0_CLK_DIV4 == stcTmr0Init.u32ClockDiv) || \
+             (TMR0_CLK_DIV8 == stcTmr0Init.u32ClockDiv) || \
+             (TMR0_CLK_DIV16 == stcTmr0Init.u32ClockDiv))
+    {
+        alpha = 3UL;
     }
     else
     {
-        cmp_val = (timeout_bits / (1UL << (stcTmr0Init.u32ClockDiv >> TMR0_BCONR_CKDIVA_POS)) - 1UL);
+        alpha = 2UL;
     }
+    /* TMR0_CMPA<B>R calculation formula: CMPA<B>R = (RTB / (2 ^ CKDIVA<B>)) - alpha */
+    ckdiv   = 1UL << (stcTmr0Init.u32ClockDiv >> TMR0_BCONR_CKDIVA_POS);
+    cmp_val = ((rtb + ckdiv - 1UL) / ckdiv) - alpha;
     DDL_ASSERT(cmp_val <= 0xFFFFUL);
     stcTmr0Init.u16CompareValue = (uint16_t)(cmp_val);
     TMR0_Init(TMR0_Instance, ch, &stcTmr0Init);
@@ -524,7 +569,7 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial)
 
 static void hc32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
 {
-    rt_uint32_t u32TransCount = (serial->config.bufsz <= 1UL) ? serial->config.bufsz : serial->config.bufsz / 2UL;
+    rt_uint32_t trans_count = (serial->config.bufsz <= 1UL) ? serial->config.bufsz : serial->config.bufsz / 2UL;
     struct hc32_uart *uart;
     stc_dma_init_t dma_init;
     struct dma_config *uart_dma;
@@ -541,6 +586,11 @@ static void hc32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
 
         RT_ASSERT(RT_NULL != uart->config->rx_timeout->TMR0_Instance);
         RT_ASSERT(RT_NULL != uart->config->dma_rx->Instance);
+        RT_ASSERT(RT_NULL != rx_fifo);
+
+#if defined (HC32F448)
+        INTC_IntSrcCmd(uart->config->rx_int_src, DISABLE);
+#endif
 
         uart_dma = uart->config->dma_rx;
         /* Initialization uart rx timeout for DMA */
@@ -556,7 +606,7 @@ static void hc32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
         dma_init.u32DestAddr    = (uint32_t)rx_fifo->buffer;
         dma_init.u32DataWidth   = DMA_DATAWIDTH_8BIT;
         dma_init.u32BlockSize   = 1UL;
-        dma_init.u32TransCount  = u32TransCount;
+        dma_init.u32TransCount  = trans_count;
         dma_init.u32SrcAddrInc  = DMA_SRC_ADDR_FIX;
         dma_init.u32DestAddrInc = DMA_DEST_ADDR_INC;
         DMA_Init(uart_dma->Instance, uart_dma->channel, &dma_init);
@@ -617,26 +667,28 @@ static void hc32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
         /* Enable DMA module */
         DMA_Cmd(uart_dma->Instance, ENABLE);
         AOS_SetTriggerEventSrc(uart_dma->trigger_select, uart_dma->trigger_event);
-        USART_FuncCmd(uart->config->Instance, USART_TX | USART_INT_TX_CPLT, DISABLE);
+        USART_FuncCmd(uart->config->Instance, (USART_TX | USART_INT_TX_EMPTY | USART_INT_TX_CPLT), DISABLE);
         NVIC_EnableIRQ(uart->config->tc_irq->irq_config.irq_num);
     }
 }
 
-#if defined(BSP_UART1_RX_USING_DMA) || defined(BSP_UART2_RX_USING_DMA) || defined(BSP_UART3_RX_USING_DMA) || \
-    defined(BSP_UART4_RX_USING_DMA) || defined(BSP_UART6_RX_USING_DMA) || defined(BSP_UART7_RX_USING_DMA)
+#if defined (BSP_UART1_RX_USING_DMA) || defined (BSP_UART2_RX_USING_DMA) || defined (BSP_UART3_RX_USING_DMA) || \
+    defined (BSP_UART4_RX_USING_DMA) || defined (BSP_UART5_RX_USING_DMA) || defined (BSP_UART6_RX_USING_DMA) || \
+    defined (BSP_UART7_RX_USING_DMA)
 static void hc32_uart_dma_rx_irq_handler(struct hc32_uart *uart)
 {
-    struct rt_serial_device *serial;
-    rt_size_t recv_len;
     rt_base_t level;
+    rt_size_t recv_len;
+    struct rt_serial_device *serial;
 
     RT_ASSERT(RT_NULL != uart);
     RT_ASSERT(RT_NULL != uart->config->Instance);
 
     serial = &uart->serial;
+    RT_ASSERT(RT_NULL != serial);
     level = rt_hw_interrupt_disable();
-    recv_len = uart->dma_rx_remain_index;
-    uart->dma_rx_remain_index = DMA_TRANS_SET_CNT(uart->config->dma_rx->Instance, uart->config->dma_rx->channel);;
+    recv_len = uart->dma_rx_remaining_cnt;
+    uart->dma_rx_remaining_cnt = DMA_TRANS_SET_CNT(uart->config->dma_rx->Instance, uart->config->dma_rx->channel);
 
     if (recv_len)
     {
@@ -650,24 +702,28 @@ static void hc32_uart_rxto_irq_handler(struct hc32_uart *uart)
     rt_base_t level;
     rt_size_t dma_set_cnt, cnt;
     rt_size_t recv_len;
+    struct rt_serial_device *serial;
+
+    serial = &uart->serial;
+    RT_ASSERT(serial != RT_NULL);
 
     cnt = DMA_TRANS_CNT(uart->config->dma_rx->Instance, uart->config->dma_rx->channel);
     dma_set_cnt = DMA_TRANS_SET_CNT(uart->config->dma_rx->Instance, uart->config->dma_rx->channel);
 
     level = rt_hw_interrupt_disable();
-    if (cnt <= (uart->dma_rx_remain_index))
+    if (cnt <= uart->dma_rx_remaining_cnt)
     {
-        recv_len = uart->dma_rx_remain_index - cnt;
+        recv_len = uart->dma_rx_remaining_cnt - cnt;
     }
     else
     {
-        recv_len = uart->dma_rx_remain_index + dma_set_cnt - cnt;
+        recv_len = uart->dma_rx_remaining_cnt + dma_set_cnt - cnt;
     }
 
     if (recv_len)
     {
-        uart->dma_rx_remain_index = cnt;
-        rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
+        uart->dma_rx_remaining_cnt = cnt;
+        rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
     }
     rt_hw_interrupt_enable(level);
     TMR0_Stop(uart->config->rx_timeout->TMR0_Instance, uart->config->rx_timeout->channel);
@@ -675,8 +731,9 @@ static void hc32_uart_rxto_irq_handler(struct hc32_uart *uart)
 }
 #endif
 
-#if defined(BSP_UART1_TX_USING_DMA) || defined(BSP_UART2_TX_USING_DMA) || defined(BSP_UART3_TX_USING_DMA) || \
-    defined(BSP_UART4_TX_USING_DMA) || defined(BSP_UART6_TX_USING_DMA) || defined(BSP_UART7_TX_USING_DMA)
+#if defined (BSP_UART1_RX_USING_DMA) || defined (BSP_UART2_RX_USING_DMA) || defined (BSP_UART3_RX_USING_DMA) || \
+    defined (BSP_UART4_RX_USING_DMA) || defined (BSP_UART5_RX_USING_DMA) || defined (BSP_UART6_RX_USING_DMA) || \
+    defined (BSP_UART7_RX_USING_DMA)
 static void hc32_uart_tc_irq_handler(struct hc32_uart *uart)
 {
     RT_ASSERT(uart != RT_NULL);
@@ -691,7 +748,46 @@ static void hc32_uart_tc_irq_handler(struct hc32_uart *uart)
 #endif
 #endif
 
-#if defined(BSP_USING_UART1)
+#if defined (HC32F448)
+static void hc32_usart_handler(struct hc32_uart *uart)
+{
+    RT_ASSERT(RT_NULL != uart);
+
+#if defined (RT_SERIAL_USING_DMA)
+    if ((SET == USART_GetStatus(uart->config->Instance, USART_FLAG_RX_TIMEOUT)) && \
+            (ENABLE == USART_GetFuncState(uart->config->Instance, USART_RX_TIMEOUT)) && \
+            (ENABLE == INTC_GetIntSrcState(uart->config->rxto_int_src)))
+    {
+        hc32_uart_rxto_irq_handler(uart);
+    }
+#endif
+
+    if ((SET == USART_GetStatus(uart->config->Instance, USART_FLAG_RX_FULL)) && \
+            (ENABLE == USART_GetFuncState(uart->config->Instance, USART_INT_RX)) && \
+            (ENABLE == INTC_GetIntSrcState(uart->config->rx_int_src)))
+    {
+        hc32_uart_rx_irq_handler(uart);
+    }
+
+    if ((SET == USART_GetStatus(uart->config->Instance, USART_FLAG_TX_EMPTY)) && \
+            (ENABLE == USART_GetFuncState(uart->config->Instance, USART_INT_TX_EMPTY)) && \
+            (ENABLE == INTC_GetIntSrcState(uart->config->tx_int_src)))
+    {
+        hc32_uart_tx_irq_handler(uart);
+    }
+
+    if ((SET == USART_GetStatus(uart->config->Instance, (USART_FLAG_OVERRUN | \
+                                USART_FLAG_FRAME_ERR | USART_FLAG_PARITY_ERR))) && \
+            (ENABLE == USART_GetFuncState(uart->config->Instance, USART_INT_RX))  && \
+            (ENABLE == INTC_GetIntSrcState(uart->config->rxerr_int_src)))
+    {
+        hc32_uart_rxerr_irq_handler(uart);
+    }
+}
+#endif
+
+#if defined (BSP_USING_UART1)
+#if defined (HC32F460) || defined (HC32F4A0)
 static void hc32_uart1_rx_irq_handler(void)
 {
     /* enter interrupt */
@@ -724,9 +820,31 @@ static void hc32_uart1_rxerr_irq_handler(void)
     /* leave interrupt */
     rt_interrupt_leave();
 }
+#endif /* HC32F460, HC32F4A0 */
 
-#if defined(RT_SERIAL_USING_DMA)
-#if defined(BSP_UART1_RX_USING_DMA)
+#if defined (RT_SERIAL_USING_DMA)
+#if defined (BSP_UART1_TX_USING_DMA)
+static void hc32_uart1_tc_irq_handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    hc32_uart_tc_irq_handler(&uart_obj[UART1_INDEX]);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+#if defined (HC32F448)
+void USART1_TxComplete_Handler(void)
+{
+    hc32_uart1_tc_irq_handler();
+}
+#endif
+#endif /* BSP_UART1_TX_USING_DMA */
+
+#if defined (BSP_UART1_RX_USING_DMA)
+#if defined (HC32F460) || defined (HC32F4A0)
 static void hc32_uart1_rxto_irq_handler(void)
 {
     /* enter interrupt */
@@ -737,6 +855,7 @@ static void hc32_uart1_rxto_irq_handler(void)
     /* leave interrupt */
     rt_interrupt_leave();
 }
+#endif /* HC32F460, HC32F4A0 */
 
 static void hc32_uart1_dma_rx_irq_handler(void)
 {
@@ -749,24 +868,23 @@ static void hc32_uart1_dma_rx_irq_handler(void)
     rt_interrupt_leave();
 }
 #endif /* BSP_UART1_RX_USING_DMA */
+#endif /* RT_SERIAL_USING_DMA */
 
-#if defined(BSP_UART1_TX_USING_DMA)
-static void hc32_uart1_tc_irq_handler(void)
+#if defined (HC32F448)
+void USART1_Handler(void)
 {
     /* enter interrupt */
     rt_interrupt_enter();
 
-    hc32_uart_tc_irq_handler(&uart_obj[UART1_INDEX]);
+    hc32_usart_handler(&uart_obj[UART1_INDEX]);
 
     /* leave interrupt */
     rt_interrupt_leave();
 }
-#endif /* BSP_UART1_RX_USING_DMA */
-#endif /* RT_SERIAL_USING_DMA */
-
+#endif /* HC32F448 */
 #endif /* BSP_USING_UART1 */
 
-#if defined(BSP_USING_UART2)
+#if defined (BSP_USING_UART2)
 #if defined (HC32F460) || defined (HC32F4A0)
 static void hc32_uart2_rx_irq_handler(void)
 {
@@ -802,8 +920,8 @@ static void hc32_uart2_rxerr_irq_handler(void)
 }
 #endif /* HC32F460, HC32F4A0 */
 
-#if defined(RT_SERIAL_USING_DMA)
-#if defined(BSP_UART2_TX_USING_DMA)
+#if defined (RT_SERIAL_USING_DMA)
+#if defined (BSP_UART2_TX_USING_DMA)
 static void hc32_uart2_tc_irq_handler(void)
 {
     /* enter interrupt */
@@ -814,9 +932,16 @@ static void hc32_uart2_tc_irq_handler(void)
     /* leave interrupt */
     rt_interrupt_leave();
 }
+
+#if defined (HC32F448)
+void USART2_TxComplete_Handler(void)
+{
+    hc32_uart2_tc_irq_handler();
+}
+#endif
 #endif /* BSP_UART2_TX_USING_DMA */
 
-#if defined(BSP_UART2_RX_USING_DMA)
+#if defined (BSP_UART2_RX_USING_DMA)
 #if defined (HC32F460) || defined (HC32F4A0)
 static void hc32_uart2_rxto_irq_handler(void)
 {
@@ -828,7 +953,7 @@ static void hc32_uart2_rxto_irq_handler(void)
     /* leave interrupt */
     rt_interrupt_leave();
 }
-#endif
+#endif /* HC32F460, HC32F4A0 */
 
 static void hc32_uart2_dma_rx_irq_handler(void)
 {
@@ -839,14 +964,26 @@ static void hc32_uart2_dma_rx_irq_handler(void)
 
     /* leave interrupt */
     rt_interrupt_leave();
-
 }
 #endif /* BSP_UART2_RX_USING_DMA */
 #endif /* RT_SERIAL_USING_DMA */
 
+#if defined (HC32F448)
+void USART2_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    hc32_usart_handler(&uart_obj[UART2_INDEX]);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* HC32F448 */
 #endif /* BSP_USING_UART2 */
 
-#if defined(BSP_USING_UART3)
+#if defined (BSP_USING_UART3)
+#if defined (HC32F460) || defined (HC32F4A0)
 static void hc32_uart3_rx_irq_handler(void)
 {
     /* enter interrupt */
@@ -880,8 +1017,8 @@ static void hc32_uart3_rxerr_irq_handler(void)
     rt_interrupt_leave();
 }
 
-#if defined(RT_SERIAL_USING_DMA)
-#if defined(BSP_UART3_TX_USING_DMA)
+#if defined (RT_SERIAL_USING_DMA)
+#if defined (BSP_UART3_TX_USING_DMA)
 static void hc32_uart3_tc_irq_handler(void)
 {
     /* enter interrupt */
@@ -894,7 +1031,7 @@ static void hc32_uart3_tc_irq_handler(void)
 }
 #endif /* BSP_UART3_TX_USING_DMA */
 
-#if defined(BSP_UART3_RX_USING_DMA)
+#if defined (BSP_UART3_RX_USING_DMA)
 static void hc32_uart3_rxto_irq_handler(void)
 {
     /* enter interrupt */
@@ -919,9 +1056,24 @@ static void hc32_uart3_dma_rx_irq_handler(void)
 }
 #endif /* BSP_UART3_RX_USING_DMA */
 #endif /* RT_SERIAL_USING_DMA */
+#endif /* HC32F460, HC32F4A0 */
+
+#if defined (HC32F448)
+void USART3_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    hc32_usart_handler(&uart_obj[UART3_INDEX]);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* HC32F448 */
 #endif /* BSP_USING_UART3 */
 
-#if defined(BSP_USING_UART4)
+#if defined (BSP_USING_UART4)
+#if defined (HC32F460) || defined (HC32F4A0)
 static void hc32_uart4_rx_irq_handler(void)
 {
     /* enter interrupt */
@@ -954,8 +1106,10 @@ static void hc32_uart4_rxerr_irq_handler(void)
     /* leave interrupt */
     rt_interrupt_leave();
 }
-#if defined(RT_SERIAL_USING_DMA)
-#if defined(BSP_UART4_TX_USING_DMA)
+#endif /* HC32F460, HC32F4A0 */
+
+#if defined (RT_SERIAL_USING_DMA)
+#if defined (BSP_UART4_TX_USING_DMA)
 static void hc32_uart4_tc_irq_handler(void)
 {
     /* enter interrupt */
@@ -966,9 +1120,17 @@ static void hc32_uart4_tc_irq_handler(void)
     /* leave interrupt */
     rt_interrupt_leave();
 }
+
+#if defined (HC32F448)
+void USART4_TxComplete_Handler(void)
+{
+    hc32_uart4_tc_irq_handler();
+}
+#endif /* HC32F448 */
 #endif /* BSP_UART4_TX_USING_DMA */
 
-#if defined(BSP_UART4_RX_USING_DMA)
+#if defined (BSP_UART4_RX_USING_DMA)
+#if defined (HC32F460) || defined (HC32F4A0)
 static void hc32_uart4_rxto_irq_handler(void)
 {
     /* enter interrupt */
@@ -979,6 +1141,7 @@ static void hc32_uart4_rxto_irq_handler(void)
     /* leave interrupt */
     rt_interrupt_leave();
 }
+#endif /* HC32F460, HC32F4A0 */
 
 static void hc32_uart4_dma_rx_irq_handler(void)
 {
@@ -989,13 +1152,26 @@ static void hc32_uart4_dma_rx_irq_handler(void)
 
     /* leave interrupt */
     rt_interrupt_leave();
-
 }
 #endif /* BSP_UART4_RX_USING_DMA */
 #endif /* RT_SERIAL_USING_DMA */
+
+#if defined (HC32F448)
+void USART4_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    hc32_usart_handler(&uart_obj[UART4_INDEX]);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* HC32F448 */
 #endif /* BSP_USING_UART4 */
 
-#if defined(BSP_USING_UART5)
+#if defined (BSP_USING_UART5)
+#if defined (HC32F460) || defined (HC32F4A0)
 static void hc32_uart5_rx_irq_handler(void)
 {
     /* enter interrupt */
@@ -1028,9 +1204,57 @@ static void hc32_uart5_rxerr_irq_handler(void)
     /* leave interrupt */
     rt_interrupt_leave();
 }
+#endif /* HC32F460, HC32F4A0 */
+
+#if defined (HC32F448)
+#if defined (RT_SERIAL_USING_DMA)
+#if defined (BSP_UART5_TX_USING_DMA)
+static void hc32_uart5_tc_irq_handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    hc32_uart_tc_irq_handler(&uart_obj[UART5_INDEX]);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+void USART5_TxComplete_Handler(void)
+{
+    hc32_uart5_tc_irq_handler();
+}
+#endif /* BSP_UART5_TX_USING_DMA */
+
+#if defined (BSP_UART5_RX_USING_DMA)
+static void hc32_uart5_dma_rx_irq_handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    hc32_uart_dma_rx_irq_handler(&uart_obj[UART5_INDEX]);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* BSP_UART5_RX_USING_DMA */
+#endif /* RT_SERIAL_USING_DMA */
+
+void USART5_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    hc32_usart_handler(&uart_obj[UART5_INDEX]);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* HC32F448 */
 #endif /* BSP_USING_UART5 */
 
-#if defined(BSP_USING_UART6)
+#if defined (BSP_USING_UART6)
+#if defined (HC32F460) || defined (HC32F4A0)
 static void hc32_uart6_rx_irq_handler(void)
 {
     /* enter interrupt */
@@ -1064,8 +1288,8 @@ static void hc32_uart6_rxerr_irq_handler(void)
     rt_interrupt_leave();
 }
 
-#if defined(RT_SERIAL_USING_DMA)
-#if defined(BSP_UART6_TX_USING_DMA)
+#if defined (RT_SERIAL_USING_DMA)
+#if defined (BSP_UART6_TX_USING_DMA)
 static void hc32_uart6_tc_irq_handler(void)
 {
     /* enter interrupt */
@@ -1102,9 +1326,23 @@ static void hc32_uart6_dma_rx_irq_handler(void)
 }
 #endif /* BSP_UART6_RX_USING_DMA */
 #endif /* RT_SERIAL_USING_DMA */
+#endif /* HC32F460, HC32F4A0 */
+
+#if defined (HC32F448)
+void USART6_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    hc32_usart_handler(&uart_obj[UART6_INDEX]);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* HC32F448 */
 #endif /* BSP_USING_UART6 */
 
-#if defined(BSP_USING_UART7)
+#if defined (BSP_USING_UART7)
 static void hc32_uart7_rx_irq_handler(void)
 {
     /* enter interrupt */
@@ -1138,8 +1376,8 @@ static void hc32_uart7_rxerr_irq_handler(void)
     rt_interrupt_leave();
 }
 
-#if defined(RT_SERIAL_USING_DMA)
-#if defined(BSP_UART7_TX_USING_DMA)
+#if defined (RT_SERIAL_USING_DMA)
+#if defined (BSP_UART7_TX_USING_DMA)
 static void hc32_uart7_tc_irq_handler(void)
 {
     /* enter interrupt */
@@ -1152,7 +1390,7 @@ static void hc32_uart7_tc_irq_handler(void)
 }
 #endif /* BSP_UART7_TX_USING_DMA */
 
-#if defined(BSP_UART7_RX_USING_DMA)
+#if defined (BSP_UART7_RX_USING_DMA)
 static void hc32_uart7_rxto_irq_handler(void)
 {
     /* enter interrupt */
@@ -1178,7 +1416,7 @@ static void hc32_uart7_dma_rx_irq_handler(void)
 #endif /* RT_SERIAL_USING_DMA */
 #endif /* BSP_USING_UART7 */
 
-#if defined(BSP_USING_UART8)
+#if defined (BSP_USING_UART8)
 static void hc32_uart8_rx_irq_handler(void)
 {
     /* enter interrupt */
@@ -1213,7 +1451,7 @@ static void hc32_uart8_rxerr_irq_handler(void)
 }
 #endif /* BSP_USING_UART8 */
 
-#if defined(BSP_USING_UART9)
+#if defined (BSP_USING_UART9)
 static void hc32_uart9_rx_irq_handler(void)
 {
     /* enter interrupt */
@@ -1248,7 +1486,7 @@ static void hc32_uart9_rxerr_irq_handler(void)
 }
 #endif /* BSP_USING_UART9 */
 
-#if defined(BSP_USING_UART10)
+#if defined (BSP_USING_UART10)
 static void hc32_uart10_rx_irq_handler(void)
 {
     /* enter interrupt */
@@ -1298,7 +1536,9 @@ static void hc32_uart_get_dma_info(void)
     static struct dma_config uart1_dma_rx = UART1_DMA_RX_CONFIG;
     static struct hc32_uart_rxto uart1_rx_timeout = UART1_RXTO_CONFIG;
     uart1_dma_rx.irq_callback = hc32_uart1_dma_rx_irq_handler;
+#if defined (HC32F460) || defined (HC32F4A0)
     uart1_rx_timeout.irq_callback = hc32_uart1_rxto_irq_handler;
+#endif
     uart_config[UART1_INDEX].rx_timeout = &uart1_rx_timeout;
     uart_config[UART1_INDEX].dma_rx = &uart1_dma_rx;
 #endif
@@ -1337,6 +1577,7 @@ static void hc32_uart_get_dma_info(void)
 
 #ifdef BSP_USING_UART3
     uart_obj[UART3_INDEX].uart_dma_flag = 0;
+#if defined (HC32F460) || defined (HC32F4A0)
 #ifdef BSP_UART3_RX_USING_DMA
     uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
     static struct dma_config uart3_dma_rx = UART3_DMA_RX_CONFIG;
@@ -1355,6 +1596,7 @@ static void hc32_uart_get_dma_info(void)
     uart_config[UART3_INDEX].tc_irq = &uart3_tc_irq;
 #endif
 #endif
+#endif
 
 #ifdef BSP_USING_UART4
     uart_obj[UART4_INDEX].uart_dma_flag = 0;
@@ -1363,7 +1605,9 @@ static void hc32_uart_get_dma_info(void)
     static struct dma_config uart4_dma_rx = UART4_DMA_RX_CONFIG;
     static struct hc32_uart_rxto uart4_rx_timeout = UART4_RXTO_CONFIG;
     uart4_dma_rx.irq_callback = hc32_uart4_dma_rx_irq_handler;
+#if defined (HC32F460) || defined (HC32F4A0)
     uart4_rx_timeout.irq_callback = hc32_uart4_rxto_irq_handler;
+#endif
     uart_config[UART4_INDEX].rx_timeout = &uart4_rx_timeout;
     uart_config[UART4_INDEX].dma_rx = &uart4_dma_rx;
 #endif
@@ -1377,8 +1621,31 @@ static void hc32_uart_get_dma_info(void)
 #endif
 #endif
 
+#ifdef BSP_USING_UART5
+    uart_obj[UART5_INDEX].uart_dma_flag = 0;
+#if defined (HC32F448)
+#ifdef BSP_UART5_RX_USING_DMA
+    uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
+    static struct dma_config uart5_dma_rx = UART5_DMA_RX_CONFIG;
+    static struct hc32_uart_rxto uart5_rx_timeout = UART5_RXTO_CONFIG;
+    uart5_dma_rx.irq_callback = hc32_uart5_dma_rx_irq_handler;
+    uart_config[UART5_INDEX].rx_timeout = &uart5_rx_timeout;
+    uart_config[UART5_INDEX].dma_rx = &uart5_dma_rx;
+#endif
+#ifdef BSP_UART5_TX_USING_DMA
+    uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
+    static struct dma_config uart5_dma_tx = UART5_DMA_TX_CONFIG;
+    uart_config[UART5_INDEX].dma_tx = &uart5_dma_tx;
+    static struct hc32_uart_irq_config uart5_tc_irq = UART5_TX_CPLT_CONFIG;
+    uart5_tc_irq.irq_callback = hc32_uart5_tc_irq_handler;
+    uart_config[UART5_INDEX].tc_irq = &uart5_tc_irq;
+#endif
+#endif
+#endif
+
 #ifdef BSP_USING_UART6
     uart_obj[UART6_INDEX].uart_dma_flag = 0;
+#if defined (HC32F460) || defined (HC32F4A0)
 #ifdef BSP_UART6_RX_USING_DMA
     uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
     static struct dma_config uart6_dma_rx = UART6_DMA_RX_CONFIG;
@@ -1397,6 +1664,7 @@ static void hc32_uart_get_dma_info(void)
     uart_config[UART6_INDEX].tc_irq = &uart6_tc_irq;
 #endif
 #endif
+#endif
 
 #ifdef BSP_USING_UART7
     uart_obj[UART7_INDEX].uart_dma_flag = 0;
@@ -1418,6 +1686,18 @@ static void hc32_uart_get_dma_info(void)
     uart_config[UART7_INDEX].tc_irq = &uart7_tc_irq;
 #endif
 #endif
+
+#ifdef BSP_USING_UART8
+    uart_obj[UART8_INDEX].uart_dma_flag = 0;
+#endif
+
+#ifdef BSP_USING_UART9
+    uart_obj[UART9_INDEX].uart_dma_flag = 0;
+#endif
+
+#ifdef BSP_USING_UART10
+    uart_obj[UART10_INDEX].uart_dma_flag = 0;
+#endif
 }
 
 #if defined (HC32F460) || defined (HC32F4A0)

bsp/hc32/libraries/hc32_drivers/drv_usart.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd.
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -57,6 +57,14 @@ struct hc32_uart_config
     struct hc32_uart_irq_config rxerr_irq;
     struct hc32_uart_irq_config rx_irq;
     struct hc32_uart_irq_config tx_irq;
+#elif defined (HC32F448)
+    IRQn_Type                   irq_num;
+    en_int_src_t                rxerr_int_src;
+    en_int_src_t                tx_int_src;
+    en_int_src_t                rx_int_src;
+#ifdef RT_SERIAL_USING_DMA
+    en_int_src_t                rxto_int_src;
+#endif
 #endif
 
 #ifdef RT_SERIAL_USING_DMA
@@ -73,7 +81,7 @@ struct hc32_uart
 {
     struct hc32_uart_config *config;
 #ifdef RT_SERIAL_USING_DMA
-    rt_size_t               dma_rx_remain_index;
+    rt_size_t               dma_rx_remaining_cnt;
 #endif
     rt_uint16_t             uart_dma_flag;
     struct rt_serial_device serial;

bsp/hc32/libraries/hc32_drivers/drv_usart_v2.c

@@ -6,6 +6,7 @@
  * Change Logs:
  * Date           Author       Notes
  * 2022-04-28     CDT          first version
+ * 2024-02-06     CDT          support HC32F448
  */
 
 /*******************************************************************************
@@ -17,14 +18,13 @@
 
 #ifdef RT_USING_SERIAL_V2
 
-#if defined(BSP_USING_UART1) || defined(BSP_USING_UART2) || defined(BSP_USING_UART3) || \
-    defined(BSP_USING_UART4) || defined(BSP_USING_UART5) || defined(BSP_USING_UART6) || \
-    defined(BSP_USING_UART7) || defined(BSP_USING_UART8) || defined(BSP_USING_UART9) || \
-    defined(BSP_USING_UART10)
+#if defined (BSP_USING_UART1) || defined (BSP_USING_UART2) || defined (BSP_USING_UART3) || \
+    defined (BSP_USING_UART4) || defined (BSP_USING_UART5) || defined (BSP_USING_UART6) || \
+    defined (BSP_USING_UART7) || defined (BSP_USING_UART8) || defined (BSP_USING_UART9) || \
+    defined (BSP_USING_UART10)
 
 #include "drv_usart_v2.h"
 #include "board_config.h"
-#include "board.h"
 
 /*******************************************************************************
  * Local type definitions ('typedef')
@@ -42,16 +42,12 @@
 #define DMA_TRANS_CNT(unit, ch)                                                \
     (READ_REG32(DMA_CH_REG((unit)->MONDTCTL0, (ch))) >> DMA_DTCTL_CNT_POS)
 
-#define USART_TCI_ENABLE(unit)                                                 \
-    SET_REG32_BIT(unit->CR1, USART_INT_TX_CPLT)
-
-
 #define UART_BAUDRATE_ERR_MAX           (0.025F)
 
 #if defined (HC32F460)
     #define FCG_USART_CLK               FCG_Fcg1PeriphClockCmd
 
-#elif defined(HC32F4A0)
+#elif defined(HC32F4A0) || defined (HC32F448)
     #define FCG_USART_CLK               FCG_Fcg3PeriphClockCmd
 
 #endif
@@ -166,6 +162,9 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_co
 #elif defined (HC32F460)
     if ((CM_USART1 == uart->config->Instance) || (CM_USART2 == uart->config->Instance) || \
             (CM_USART3 == uart->config->Instance) || (CM_USART4 == uart->config->Instance))
+#elif defined (HC32F448)
+    if ((CM_USART1 == uart->config->Instance) || (CM_USART2 == uart->config->Instance) || \
+            (CM_USART4 == uart->config->Instance) || (CM_USART5 == uart->config->Instance))
 #endif
     {
         uart_init.u32CKOutput = USART_CK_OUTPUT_ENABLE;
@@ -221,7 +220,7 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_co
     {
         uart_init.u32FirstBit = USART_FIRST_BIT_MSB;
     }
-#if defined (HC32F4A0)
+#if defined (HC32F4A0) || defined (HC32F448)
     switch (cfg->flowcontrol)
     {
     case RT_SERIAL_FLOWCONTROL_NONE:
@@ -269,6 +268,12 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_co
     /* Enable error interrupt */
 #if defined (HC32F460) || defined (HC32F4A0)
     NVIC_EnableIRQ(uart->config->rxerr_irq.irq_config.irq_num);
+#elif defined (HC32F448)
+    INTC_IntSrcCmd(uart->config->tx_int_src, ENABLE);
+    INTC_IntSrcCmd(uart->config->rx_int_src, DISABLE);
+    INTC_IntSrcCmd(uart->config->rxerr_int_src, ENABLE);
+    NVIC_EnableIRQ(uart->config->irq_num);
+    INTC_IntSrcCmd(uart->config->tc_irq.irq_config.int_src, ENABLE);
 #endif
     USART_FuncCmd(uart->config->Instance, USART_TX | USART_RX | USART_INT_RX, ENABLE);
 
@@ -287,17 +292,25 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg
     if (ctrl_arg & (RT_DEVICE_FLAG_RX_BLOCKING | RT_DEVICE_FLAG_RX_NON_BLOCKING))
     {
         if (uart->uart_dma_flag & RT_DEVICE_FLAG_DMA_RX)
+        {
             ctrl_arg = RT_DEVICE_FLAG_DMA_RX;
+        }
         else
+        {
             ctrl_arg = RT_DEVICE_FLAG_INT_RX;
         }
+    }
     else if (ctrl_arg & (RT_DEVICE_FLAG_TX_BLOCKING | RT_DEVICE_FLAG_TX_NON_BLOCKING))
     {
         if (uart->uart_dma_flag & RT_DEVICE_FLAG_DMA_TX)
+        {
             ctrl_arg = RT_DEVICE_FLAG_DMA_TX;
+        }
         else
+        {
             ctrl_arg = RT_DEVICE_FLAG_INT_TX;
         }
+    }
 
     switch (cmd)
     {
@@ -307,8 +320,9 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg
         {
 #if defined (HC32F460) || defined (HC32F4A0)
             NVIC_DisableIRQ(uart->config->rx_irq.irq_config.irq_num);
-            USART_FuncCmd(uart->config->Instance, USART_INT_RX, DISABLE);
             INTC_IrqSignOut(uart->config->rx_irq.irq_config.irq_num);
+#elif defined (HC32F448)
+            INTC_IntSrcCmd(uart->config->rx_int_src, DISABLE);
 #endif
         }
         else if (RT_DEVICE_FLAG_INT_TX == ctrl_arg)
@@ -319,6 +333,10 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg
             USART_FuncCmd(uart->config->Instance, (USART_INT_TX_EMPTY | USART_INT_TX_CPLT), DISABLE);
             INTC_IrqSignOut(uart->config->tx_irq.irq_config.irq_num);
             INTC_IrqSignOut(uart->config->tc_irq.irq_config.irq_num);
+#elif defined (HC32F448)
+            NVIC_DisableIRQ(uart->config->tc_irq.irq_config.irq_num);
+            INTC_IrqSignOut(uart->config->tc_irq.irq_config.irq_num);
+            USART_FuncCmd(uart->config->Instance, (USART_INT_TX_EMPTY | USART_INT_TX_CPLT), DISABLE);
 #endif
         }
 #ifdef RT_SERIAL_USING_DMA
@@ -344,11 +362,26 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg
         else
         {
             INTC_IrqSignOut(uart->config->tx_irq.irq_config.irq_num);
+            INTC_IrqSignOut(uart->config->tc_irq.irq_config.irq_num);
             hc32_install_irq_handler(&uart->config->tx_irq.irq_config, uart->config->tx_irq.irq_callback, RT_TRUE);
             hc32_install_irq_handler(&uart->config->tc_irq.irq_config, uart->config->tc_irq.irq_callback, RT_TRUE);
             USART_FuncCmd(uart->config->Instance, USART_TX, DISABLE);
             USART_FuncCmd(uart->config->Instance, USART_TX | USART_INT_TX_EMPTY, ENABLE);
         }
+#elif defined (HC32F448)
+        /* NVIC config */
+        if (RT_DEVICE_FLAG_INT_RX == ctrl_arg)
+        {
+            /* intsrc enable */
+            INTC_IntSrcCmd(uart->config->rx_int_src, ENABLE);
+            USART_FuncCmd(uart->config->Instance, USART_INT_RX, ENABLE);
+        }
+        else
+        {
+            NVIC_ClearPendingIRQ(uart->config->tc_irq.irq_config.irq_num);
+            NVIC_EnableIRQ(uart->config->tc_irq.irq_config.irq_num);
+            USART_FuncCmd(uart->config->Instance, USART_TX | USART_INT_TX_EMPTY, ENABLE);
+        }
 #endif
         break;
     case RT_DEVICE_CTRL_CONFIG:
@@ -417,19 +450,19 @@ static rt_ssize_t hc32_transmit(struct rt_serial_device  *serial,
                                 rt_size_t                 size,
                                 rt_uint32_t               tx_flag)
 {
-
     struct hc32_uart *uart;
 #ifdef RT_SERIAL_USING_DMA
     struct dma_config *uart_dma;
 #endif
 
-    RT_ASSERT(serial != RT_NULL);
-    RT_ASSERT(buf != RT_NULL);
+    RT_ASSERT(RT_NULL != serial);
+    RT_ASSERT(RT_NULL != buf);
 
-    if (size == 0)
+    if (0 == size)
     {
         return 0;
     }
+
     uart = rt_container_of(serial, struct hc32_uart, serial);
     if (uart->uart_dma_flag & RT_DEVICE_FLAG_DMA_TX)
     {
@@ -495,18 +528,19 @@ static void hc32_uart_rxerr_irq_handler(struct hc32_uart *uart)
 
 static void hc32_uart_tc_irq_handler(struct hc32_uart *uart)
 {
-    RT_ASSERT(uart != RT_NULL);
+    RT_ASSERT(RT_NULL != uart);
+
+    USART_FuncCmd(uart->config->Instance, (USART_TX | USART_INT_TX_CPLT), DISABLE);
+
     if (uart->uart_dma_flag & RT_DEVICE_FLAG_DMA_TX)
     {
 #ifdef RT_SERIAL_USING_DMA
         DMA_ClearTransCompleteStatus(uart->config->dma_tx->Instance, (DMA_FLAG_TC_CH0 | DMA_FLAG_BTC_CH0) << uart->config->dma_tx->channel);
 #endif
-        USART_FuncCmd(uart->config->Instance, (USART_TX | USART_INT_TX_CPLT), DISABLE);
         rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_TX_DMADONE);
     }
     else
     {
-        USART_FuncCmd(uart->config->Instance, (USART_TX | USART_INT_TX_CPLT), DISABLE);
         rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_TX_DONE);
     }
 }
@@ -515,10 +549,12 @@ static void hc32_uart_tc_irq_handler(struct hc32_uart *uart)
 static void hc32_uart_rx_timeout(struct rt_serial_device *serial)
 {
     struct hc32_uart *uart;
-    uint32_t cmp_val;
     CM_TMR0_TypeDef *TMR0_Instance;
     uint8_t ch;
-    uint32_t timeout_bits;
+    uint32_t rtb;
+    uint32_t alpha;
+    uint32_t ckdiv;
+    uint32_t cmp_val;
     stc_tmr0_init_t stcTmr0Init;
 
     RT_ASSERT(RT_NULL != serial);
@@ -527,7 +563,7 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial)
 
     TMR0_Instance = uart->config->rx_timeout->TMR0_Instance;
     ch            = uart->config->rx_timeout->channel;
-    timeout_bits  = uart->config->rx_timeout->timeout_bits;
+    rtb           = uart->config->rx_timeout->timeout_bits;
 #if defined (HC32F460)
     if ((CM_USART1 == uart->config->Instance) || (CM_USART3 == uart->config->Instance))
     {
@@ -546,6 +582,15 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial)
     {
         RT_ASSERT(TMR0_CH_B == ch);
     }
+#elif defined (HC32F448)
+    if ((CM_USART1 == uart->config->Instance) || (CM_USART4 == uart->config->Instance))
+    {
+        RT_ASSERT(TMR0_CH_A == ch);
+    }
+    else if ((CM_USART2 == uart->config->Instance) || (CM_USART5 == uart->config->Instance))
+    {
+        RT_ASSERT(TMR0_CH_B == ch);
+    }
 #endif
 
     FCG_TMR0_CLK(uart->config->rx_timeout->clock, ENABLE);
@@ -557,16 +602,25 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial)
     stcTmr0Init.u32ClockSrc = TMR0_CLK_SRC_XTAL32;
     if (TMR0_CLK_DIV1 == stcTmr0Init.u32ClockDiv)
     {
-        cmp_val = (timeout_bits - 4UL);
+        alpha = 7UL;
     }
     else if (TMR0_CLK_DIV2 == stcTmr0Init.u32ClockDiv)
     {
-        cmp_val = (timeout_bits / 2UL - 2UL);
+        alpha = 5UL;
+    }
+    else if ((TMR0_CLK_DIV4 == stcTmr0Init.u32ClockDiv) || \
+             (TMR0_CLK_DIV8 == stcTmr0Init.u32ClockDiv) || \
+             (TMR0_CLK_DIV16 == stcTmr0Init.u32ClockDiv))
+    {
+        alpha = 3UL;
     }
     else
     {
-        cmp_val = (timeout_bits / (1UL << (stcTmr0Init.u32ClockDiv >> TMR0_BCONR_CKDIVA_POS)) - 1UL);
+        alpha = 2UL;
     }
+    /* TMR0_CMPA<B>R calculation formula: CMPA<B>R = (RTB / (2 ^ CKDIVA<B>)) - alpha */
+    ckdiv   = 1UL << (stcTmr0Init.u32ClockDiv >> TMR0_BCONR_CKDIVA_POS);
+    cmp_val = ((rtb + ckdiv - 1UL) / ckdiv) - alpha;
     DDL_ASSERT(cmp_val <= 0xFFFFUL);
     stcTmr0Init.u16CompareValue = (uint16_t)(cmp_val);
     TMR0_Init(TMR0_Instance, ch, &stcTmr0Init);
@@ -601,7 +655,11 @@ static void hc32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
 
         RT_ASSERT(RT_NULL != uart->config->rx_timeout->TMR0_Instance);
         RT_ASSERT(RT_NULL != uart->config->dma_rx->Instance);
-        RT_ASSERT(rx_fifo != RT_NULL);
+        RT_ASSERT(RT_NULL != rx_fifo);
+
+#if defined (HC32F448)
+        INTC_IntSrcCmd(uart->config->rx_int_src, DISABLE);
+#endif
 
         uart_dma = uart->config->dma_rx;
         /* Initialization uart rx timeout for DMA */
@@ -678,24 +736,29 @@ static void hc32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
         /* Enable DMA module */
         DMA_Cmd(uart_dma->Instance, ENABLE);
         AOS_SetTriggerEventSrc(uart_dma->trigger_select, uart_dma->trigger_event);
-        USART_FuncCmd(uart->config->Instance, USART_TX | USART_INT_TX_CPLT, DISABLE);
+        USART_FuncCmd(uart->config->Instance, (USART_TX | USART_INT_TX_EMPTY | USART_INT_TX_CPLT), DISABLE);
         NVIC_EnableIRQ(uart->config->tc_irq.irq_config.irq_num);
     }
 }
 
-#if defined(BSP_UART1_RX_USING_DMA) || defined(BSP_UART2_RX_USING_DMA) || defined(BSP_UART3_RX_USING_DMA) || \
-    defined(BSP_UART4_RX_USING_DMA) || defined(BSP_UART6_RX_USING_DMA) || defined(BSP_UART7_RX_USING_DMA)
+#if defined (BSP_UART1_RX_USING_DMA) || defined (BSP_UART2_RX_USING_DMA) || defined (BSP_UART3_RX_USING_DMA) || \
+    defined (BSP_UART4_RX_USING_DMA) || defined (BSP_UART5_RX_USING_DMA) || defined (BSP_UART6_RX_USING_DMA) || \
+    defined (BSP_UART7_RX_USING_DMA)
 static void hc32_uart_dma_rx_irq_handler(struct hc32_uart *uart)
 {
     rt_base_t level;
     rt_size_t recv_len;
     struct rt_serial_device *serial;
 
+    RT_ASSERT(RT_NULL != uart);
+    RT_ASSERT(RT_NULL != uart->config->Instance);
+
     serial = &uart->serial;
-    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(RT_NULL != serial);
     level = rt_hw_interrupt_disable();
     recv_len = uart->dma_rx_remaining_cnt;
     uart->dma_rx_remaining_cnt = DMA_TRANS_SET_CNT(uart->config->dma_rx->Instance, uart->config->dma_rx->channel);
+
     if (recv_len)
     {
         rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
@@ -706,28 +769,29 @@ static void hc32_uart_dma_rx_irq_handler(struct hc32_uart *uart)
 static void hc32_uart_rxto_irq_handler(struct hc32_uart *uart)
 {
     rt_base_t level;
-    rt_size_t recv_len, counter, dam_set_count;
+    rt_size_t dma_set_cnt, cnt;
+    rt_size_t recv_len;
     struct rt_serial_device *serial;
 
     serial = &uart->serial;
     RT_ASSERT(serial != RT_NULL);
 
-    counter = DMA_TRANS_CNT(uart->config->dma_rx->Instance, uart->config->dma_rx->channel);
-    dam_set_count = DMA_TRANS_SET_CNT(uart->config->dma_rx->Instance, uart->config->dma_rx->channel);
-    level = rt_hw_interrupt_disable();
+    cnt = DMA_TRANS_CNT(uart->config->dma_rx->Instance, uart->config->dma_rx->channel);
+    dma_set_cnt = DMA_TRANS_SET_CNT(uart->config->dma_rx->Instance, uart->config->dma_rx->channel);
 
-    if (counter <= (uart->dma_rx_remaining_cnt))
+    level = rt_hw_interrupt_disable();
+    if (cnt <= uart->dma_rx_remaining_cnt)
     {
-        recv_len = uart->dma_rx_remaining_cnt - counter;
+        recv_len = uart->dma_rx_remaining_cnt - cnt;
     }
     else
     {
-        recv_len = uart->dma_rx_remaining_cnt + dam_set_count - counter;
+        recv_len = uart->dma_rx_remaining_cnt + dma_set_cnt - cnt;
     }
 
     if (recv_len)
     {
-        uart->dma_rx_remaining_cnt = counter;
+        uart->dma_rx_remaining_cnt = cnt;
         rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
     }
     rt_hw_interrupt_enable(level);
@@ -737,7 +801,46 @@ static void hc32_uart_rxto_irq_handler(struct hc32_uart *uart)
 #endif
 #endif
 
-#if defined(BSP_USING_UART1)
+#if defined (HC32F448)
+static void hc32_usart_handler(struct hc32_uart *uart)
+{
+    RT_ASSERT(RT_NULL != uart);
+
+#if defined (RT_SERIAL_USING_DMA)
+    if ((SET == USART_GetStatus(uart->config->Instance, USART_FLAG_RX_TIMEOUT)) && \
+            (ENABLE == USART_GetFuncState(uart->config->Instance, USART_RX_TIMEOUT)) && \
+            (ENABLE == INTC_GetIntSrcState(uart->config->rxto_int_src)))
+    {
+        hc32_uart_rxto_irq_handler(uart);
+    }
+#endif
+
+    if ((SET == USART_GetStatus(uart->config->Instance, USART_FLAG_RX_FULL)) && \
+            (ENABLE == USART_GetFuncState(uart->config->Instance, USART_INT_RX)) && \
+            (ENABLE == INTC_GetIntSrcState(uart->config->rx_int_src)))
+    {
+        hc32_uart_rx_irq_handler(uart);
+    }
+
+    if ((SET == USART_GetStatus(uart->config->Instance, USART_FLAG_TX_EMPTY)) && \
+            (ENABLE == USART_GetFuncState(uart->config->Instance, USART_INT_TX_EMPTY)) && \
+            (ENABLE == INTC_GetIntSrcState(uart->config->tx_int_src)))
+    {
+        hc32_uart_tx_irq_handler(uart);
+    }
+
+    if ((SET == USART_GetStatus(uart->config->Instance, (USART_FLAG_OVERRUN | \
+                                USART_FLAG_FRAME_ERR | USART_FLAG_PARITY_ERR))) && \
+            (ENABLE == USART_GetFuncState(uart->config->Instance, USART_INT_RX))  && \
+            (ENABLE == INTC_GetIntSrcState(uart->config->rxerr_int_src)))
+    {
+        hc32_uart_rxerr_irq_handler(uart);
+    }
+}
+#endif
+
+#if defined (BSP_USING_UART1)
+#if defined (HC32F460) || defined (HC32F4A0)
 static void hc32_uart1_rx_irq_handler(void)
 {
     /* enter interrupt */
@@ -770,6 +873,7 @@ static void hc32_uart1_rxerr_irq_handler(void)
     /* leave interrupt */
     rt_interrupt_leave();
 }
+#endif /* HC32F460, HC32F4A0 */
 
 static void hc32_uart1_tc_irq_handler(void)
 {
@@ -782,8 +886,9 @@ static void hc32_uart1_tc_irq_handler(void)
     rt_interrupt_leave();
 }
 
-#if defined(RT_SERIAL_USING_DMA)
-#if defined(BSP_UART1_RX_USING_DMA)
+#if defined (RT_SERIAL_USING_DMA)
+#if defined (BSP_UART1_RX_USING_DMA)
+#if defined (HC32F460) || defined (HC32F4A0)
 static void hc32_uart1_rxto_irq_handler(void)
 {
     /* enter interrupt */
@@ -794,6 +899,7 @@ static void hc32_uart1_rxto_irq_handler(void)
     /* leave interrupt */
     rt_interrupt_leave();
 }
+#endif /* HC32F460, HC32F4A0 */
 
 static void hc32_uart1_dma_rx_irq_handler(void)
 {
@@ -806,11 +912,34 @@ static void hc32_uart1_dma_rx_irq_handler(void)
     rt_interrupt_leave();
 }
 #endif /* BSP_UART1_RX_USING_DMA */
-
 #endif /* RT_SERIAL_USING_DMA */
+
+#if defined (HC32F448)
+void USART1_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    hc32_usart_handler(&uart_obj[UART1_INDEX]);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+void USART1_TxComplete_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    hc32_uart1_tc_irq_handler();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* HC32F448 */
 #endif /* BSP_USING_UART1 */
 
-#if defined(BSP_USING_UART2)
+#if defined (BSP_USING_UART2)
 #if defined (HC32F460) || defined (HC32F4A0)
 static void hc32_uart2_rx_irq_handler(void)
 {
@@ -844,7 +973,7 @@ static void hc32_uart2_rxerr_irq_handler(void)
     /* leave interrupt */
     rt_interrupt_leave();
 }
-#endif /* defined (HC32F460) || defined (HC32F4A0) */
+#endif /* HC32F460, HC32F4A0 */
 
 static void hc32_uart2_tc_irq_handler(void)
 {
@@ -857,8 +986,8 @@ static void hc32_uart2_tc_irq_handler(void)
     rt_interrupt_leave();
 }
 
-#if defined(RT_SERIAL_USING_DMA)
-#if defined(BSP_UART2_RX_USING_DMA)
+#if defined (RT_SERIAL_USING_DMA)
+#if defined (BSP_UART2_RX_USING_DMA)
 #if defined (HC32F460) || defined (HC32F4A0)
 static void hc32_uart2_rxto_irq_handler(void)
 {
@@ -870,7 +999,7 @@ static void hc32_uart2_rxto_irq_handler(void)
     /* leave interrupt */
     rt_interrupt_leave();
 }
-#endif
+#endif /* HC32F460, HC32F4A0 */
 
 static void hc32_uart2_dma_rx_irq_handler(void)
 {
@@ -881,15 +1010,37 @@ static void hc32_uart2_dma_rx_irq_handler(void)
 
     /* leave interrupt */
     rt_interrupt_leave();
-
 }
-
 #endif /* BSP_UART2_RX_USING_DMA */
 #endif /* RT_SERIAL_USING_DMA */
 
+#if defined (HC32F448)
+void USART2_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    hc32_usart_handler(&uart_obj[UART2_INDEX]);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+void USART2_TxComplete_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    hc32_uart2_tc_irq_handler();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* HC32F448 */
 #endif /* BSP_USING_UART2 */
 
-#if defined(BSP_USING_UART3)
+#if defined (BSP_USING_UART3)
+#if defined (HC32F460) || defined (HC32F4A0)
 static void hc32_uart3_rx_irq_handler(void)
 {
     /* enter interrupt */
@@ -922,6 +1073,7 @@ static void hc32_uart3_rxerr_irq_handler(void)
     /* leave interrupt */
     rt_interrupt_leave();
 }
+#endif /* HC32F460, HC32F4A0 */
 
 static void hc32_uart3_tc_irq_handler(void)
 {
@@ -934,8 +1086,9 @@ static void hc32_uart3_tc_irq_handler(void)
     rt_interrupt_leave();
 }
 
-#if defined(RT_SERIAL_USING_DMA)
-#if defined(BSP_UART3_RX_USING_DMA)
+#if defined (RT_SERIAL_USING_DMA)
+#if defined (BSP_UART3_RX_USING_DMA)
+#if defined (HC32F460) || defined (HC32F4A0)
 static void hc32_uart3_rxto_irq_handler(void)
 {
     /* enter interrupt */
@@ -958,11 +1111,37 @@ static void hc32_uart3_dma_rx_irq_handler(void)
     rt_interrupt_leave();
 
 }
+#endif /* HC32F460, HC32F4A0 */
 #endif /* BSP_UART3_RX_USING_DMA */
 #endif /* RT_SERIAL_USING_DMA */
+
+#if defined (HC32F448)
+void USART3_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    hc32_usart_handler(&uart_obj[UART3_INDEX]);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+void USART3_TxComplete_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    hc32_uart3_tc_irq_handler();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* HC32F448 */
 #endif /* BSP_USING_UART3 */
 
-#if defined(BSP_USING_UART4)
+#if defined (BSP_USING_UART4)
+#if defined (HC32F460) || defined (HC32F4A0)
 static void hc32_uart4_rx_irq_handler(void)
 {
     /* enter interrupt */
@@ -995,6 +1174,7 @@ static void hc32_uart4_rxerr_irq_handler(void)
     /* leave interrupt */
     rt_interrupt_leave();
 }
+#endif /* HC32F460, HC32F4A0 */
 
 static void hc32_uart4_tc_irq_handler(void)
 {
@@ -1007,8 +1187,9 @@ static void hc32_uart4_tc_irq_handler(void)
     rt_interrupt_leave();
 }
 
-#if defined(RT_SERIAL_USING_DMA)
-#if defined(BSP_UART4_RX_USING_DMA)
+#if defined (RT_SERIAL_USING_DMA)
+#if defined (BSP_UART4_RX_USING_DMA)
+#if defined (HC32F460) || defined (HC32F4A0)
 static void hc32_uart4_rxto_irq_handler(void)
 {
     /* enter interrupt */
@@ -1019,6 +1200,7 @@ static void hc32_uart4_rxto_irq_handler(void)
     /* leave interrupt */
     rt_interrupt_leave();
 }
+#endif /* HC32F460, HC32F4A0 */
 
 static void hc32_uart4_dma_rx_irq_handler(void)
 {
@@ -1029,13 +1211,37 @@ static void hc32_uart4_dma_rx_irq_handler(void)
 
     /* leave interrupt */
     rt_interrupt_leave();
-
 }
 #endif /* BSP_UART4_RX_USING_DMA */
 #endif /* RT_SERIAL_USING_DMA */
+
+#if defined (HC32F448)
+void USART4_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    hc32_usart_handler(&uart_obj[UART4_INDEX]);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+void USART4_TxComplete_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    hc32_uart4_tc_irq_handler();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* HC32F448 */
 #endif /* BSP_USING_UART4 */
 
-#if defined(BSP_USING_UART5)
+#if defined (BSP_USING_UART5)
+#if defined (HC32F460) || defined (HC32F4A0)
 static void hc32_uart5_rx_irq_handler(void)
 {
     /* enter interrupt */
@@ -1068,6 +1274,7 @@ static void hc32_uart5_rxerr_irq_handler(void)
     /* leave interrupt */
     rt_interrupt_leave();
 }
+#endif /* HC32F460, HC32F4A0 */
 
 static void hc32_uart5_tc_irq_handler(void)
 {
@@ -1079,9 +1286,49 @@ static void hc32_uart5_tc_irq_handler(void)
     /* leave interrupt */
     rt_interrupt_leave();
 }
+
+#if defined (HC32F448)
+#if defined (RT_SERIAL_USING_DMA)
+#if defined (BSP_UART5_RX_USING_DMA)
+static void hc32_uart5_dma_rx_irq_handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    hc32_uart_dma_rx_irq_handler(&uart_obj[UART5_INDEX]);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* BSP_UART5_RX_USING_DMA */
+#endif /* RT_SERIAL_USING_DMA */
+
+void USART5_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    hc32_usart_handler(&uart_obj[UART5_INDEX]);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+void USART5_TxComplete_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    hc32_uart5_tc_irq_handler();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* HC32F448 */
 #endif /* BSP_USING_UART5 */
 
-#if defined(BSP_USING_UART6)
+#if defined (BSP_USING_UART6)
+#if defined (HC32F460) || defined (HC32F4A0)
 static void hc32_uart6_rx_irq_handler(void)
 {
     /* enter interrupt */
@@ -1114,6 +1361,7 @@ static void hc32_uart6_rxerr_irq_handler(void)
     /* leave interrupt */
     rt_interrupt_leave();
 }
+#endif /* HC32F460, HC32F4A0 */
 
 static void hc32_uart6_tc_irq_handler(void)
 {
@@ -1126,8 +1374,9 @@ static void hc32_uart6_tc_irq_handler(void)
     rt_interrupt_leave();
 }
 
-#if defined(RT_SERIAL_USING_DMA)
-#if defined(BSP_UART6_RX_USING_DMA)
+#if defined (RT_SERIAL_USING_DMA)
+#if defined (BSP_UART6_RX_USING_DMA)
+#if defined (HC32F460) || defined (HC32F4A0)
 static void hc32_uart6_rxto_irq_handler(void)
 {
     /* enter interrupt */
@@ -1149,11 +1398,36 @@ static void hc32_uart6_dma_rx_irq_handler(void)
     /* leave interrupt */
     rt_interrupt_leave();
 }
+#endif /* HC32F460, HC32F4A0 */
 #endif /* BSP_UART6_RX_USING_DMA */
 #endif /* RT_SERIAL_USING_DMA */
+
+#if defined (HC32F448)
+void USART6_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    hc32_usart_handler(&uart_obj[UART6_INDEX]);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+void USART6_TxComplete_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    hc32_uart6_tc_irq_handler();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* HC32F448 */
 #endif /* BSP_USING_UART6 */
 
-#if defined(BSP_USING_UART7)
+#if defined (BSP_USING_UART7)
 static void hc32_uart7_rx_irq_handler(void)
 {
     /* enter interrupt */
@@ -1198,8 +1472,8 @@ static void hc32_uart7_tc_irq_handler(void)
     rt_interrupt_leave();
 }
 
-#if defined(RT_SERIAL_USING_DMA)
-#if defined(BSP_UART7_RX_USING_DMA)
+#if defined (RT_SERIAL_USING_DMA)
+#if defined (BSP_UART7_RX_USING_DMA)
 static void hc32_uart7_rxto_irq_handler(void)
 {
     /* enter interrupt */
@@ -1225,7 +1499,7 @@ static void hc32_uart7_dma_rx_irq_handler(void)
 #endif /* RT_SERIAL_USING_DMA */
 #endif /* BSP_USING_UART7 */
 
-#if defined(BSP_USING_UART8)
+#if defined (BSP_USING_UART8)
 static void hc32_uart8_rx_irq_handler(void)
 {
     /* enter interrupt */
@@ -1271,7 +1545,7 @@ static void hc32_uart8_tc_irq_handler(void)
 }
 #endif /* BSP_USING_UART8 */
 
-#if defined(BSP_USING_UART9)
+#if defined (BSP_USING_UART9)
 static void hc32_uart9_rx_irq_handler(void)
 {
     /* enter interrupt */
@@ -1317,7 +1591,7 @@ static void hc32_uart9_tc_irq_handler(void)
 }
 #endif /* BSP_USING_UART9 */
 
-#if defined(BSP_USING_UART10)
+#if defined (BSP_USING_UART10)
 static void hc32_uart10_rx_irq_handler(void)
 {
     /* enter interrupt */
@@ -1383,7 +1657,9 @@ static void hc32_uart_get_info(void)
     static struct dma_config uart1_dma_rx = UART1_DMA_RX_CONFIG;
     static struct hc32_uart_rxto uart1_rx_timeout = UART1_RXTO_CONFIG;
     uart1_dma_rx.irq_callback = hc32_uart1_dma_rx_irq_handler;
+#if defined (HC32F460) || defined (HC32F4A0)
     uart1_rx_timeout.irq_callback = hc32_uart1_rxto_irq_handler;
+#endif
     uart_config[UART1_INDEX].rx_timeout = &uart1_rx_timeout;
     uart_config[UART1_INDEX].dma_rx = &uart1_dma_rx;
 #endif
@@ -1422,6 +1698,7 @@ static void hc32_uart_get_info(void)
     uart_obj[UART3_INDEX].serial.config = config;
     uart_obj[UART3_INDEX].serial.config.rx_bufsz = BSP_UART3_RX_BUFSIZE;
     uart_obj[UART3_INDEX].serial.config.tx_bufsz = BSP_UART3_TX_BUFSIZE;
+#if defined (HC32F460) || defined (HC32F4A0)
 #ifdef BSP_UART3_RX_USING_DMA
     uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
     static struct dma_config uart3_dma_rx = UART3_DMA_RX_CONFIG;
@@ -1437,6 +1714,7 @@ static void hc32_uart_get_info(void)
     uart_config[UART3_INDEX].dma_tx = &uart3_dma_tx;
 #endif
 #endif
+#endif
 
 #ifdef BSP_USING_UART4
     uart_obj[UART4_INDEX].uart_dma_flag = 0;
@@ -1448,7 +1726,9 @@ static void hc32_uart_get_info(void)
     static struct dma_config uart4_dma_rx = UART4_DMA_RX_CONFIG;
     static struct hc32_uart_rxto uart4_rx_timeout = UART4_RXTO_CONFIG;
     uart4_dma_rx.irq_callback = hc32_uart4_dma_rx_irq_handler;
+#if defined (HC32F460) || defined (HC32F4A0)
     uart4_rx_timeout.irq_callback = hc32_uart4_rxto_irq_handler;
+#endif
     uart_config[UART4_INDEX].rx_timeout = &uart4_rx_timeout;
     uart_config[UART4_INDEX].dma_rx = &uart4_dma_rx;
 #endif
@@ -1464,6 +1744,21 @@ static void hc32_uart_get_info(void)
     uart_obj[UART5_INDEX].serial.config = config;
     uart_obj[UART5_INDEX].serial.config.rx_bufsz = BSP_UART5_RX_BUFSIZE;
     uart_obj[UART5_INDEX].serial.config.tx_bufsz = BSP_UART5_TX_BUFSIZE;
+#if defined (HC32F460)
+#ifdef BSP_UART5_RX_USING_DMA
+    uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
+    static struct dma_config uart5_dma_rx = UART5_DMA_RX_CONFIG;
+    static struct hc32_uart_rxto uart5_rx_timeout = UART5_RXTO_CONFIG;
+    uart5_dma_rx.irq_callback = hc32_uart5_dma_rx_irq_handler;
+    uart_config[UART5_INDEX].rx_timeout = &uart5_rx_timeout;
+    uart_config[UART5_INDEX].dma_rx = &uart5_dma_rx;
+#endif
+#ifdef BSP_UART5_TX_USING_DMA
+    uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
+    static struct dma_config uart5_dma_tx = UART5_DMA_TX_CONFIG;
+    uart_config[UART5_INDEX].dma_tx = &uart5_dma_tx;
+#endif
+#endif
 #endif
 
 #ifdef BSP_USING_UART6
@@ -1471,6 +1766,7 @@ static void hc32_uart_get_info(void)
     uart_obj[UART6_INDEX].serial.config = config;
     uart_obj[UART6_INDEX].serial.config.rx_bufsz = BSP_UART6_RX_BUFSIZE;
     uart_obj[UART6_INDEX].serial.config.tx_bufsz = BSP_UART6_TX_BUFSIZE;
+#if defined (HC32F460) || defined (HC32F4A0)
 #ifdef BSP_UART6_RX_USING_DMA
     uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
     static struct dma_config uart6_dma_rx = UART6_DMA_RX_CONFIG;
@@ -1486,6 +1782,7 @@ static void hc32_uart_get_info(void)
     uart_config[UART6_INDEX].dma_tx = &uart6_dma_tx;
 #endif
 #endif
+#endif
 
 #ifdef BSP_USING_UART7
     uart_obj[UART7_INDEX].uart_dma_flag = 0;
@@ -1619,7 +1916,46 @@ static void hc32_get_uart_callback(void)
     uart_config[UART10_INDEX].tc_irq.irq_callback = hc32_uart10_tc_irq_handler;
 #endif
 }
-#endif /* defined (HC32F460) || defined (HC32F4A0) */
+#elif defined (HC32F448)
+/**
+  * @brief  This function gets uart irq handle.
+  * @param  None
+  * @retval None
+  */
+static void hc32_get_uart_callback(void)
+{
+#ifdef BSP_USING_UART1
+    struct hc32_uart_irq_config uart1_tc_irq = UART1_TX_CPLT_CONFIG;
+    uart_config[UART1_INDEX].tc_irq = uart1_tc_irq;
+    uart_config[UART1_INDEX].tc_irq.irq_callback = hc32_uart1_tc_irq_handler;
+#endif
+#ifdef BSP_USING_UART2
+    struct hc32_uart_irq_config uart2_tc_irq = UART2_TX_CPLT_CONFIG;
+    uart_config[UART2_INDEX].tc_irq = uart2_tc_irq;
+    uart_config[UART2_INDEX].tc_irq.irq_callback = hc32_uart2_tc_irq_handler;
+#endif
+#ifdef BSP_USING_UART3
+    struct hc32_uart_irq_config uart3_tc_irq = UART3_TX_CPLT_CONFIG;
+    uart_config[UART3_INDEX].tc_irq = uart3_tc_irq;
+    uart_config[UART3_INDEX].tc_irq.irq_callback = hc32_uart3_tc_irq_handler;
+#endif
+#ifdef BSP_USING_UART4
+    struct hc32_uart_irq_config uart4_tc_irq = UART4_TX_CPLT_CONFIG;
+    uart_config[UART4_INDEX].tc_irq = uart4_tc_irq;
+    uart_config[UART4_INDEX].tc_irq.irq_callback = hc32_uart4_tc_irq_handler;
+#endif
+#ifdef BSP_USING_UART5
+    struct hc32_uart_irq_config uart5_tc_irq = UART5_TX_CPLT_CONFIG;
+    uart_config[UART5_INDEX].tc_irq = uart5_tc_irq;
+    uart_config[UART5_INDEX].tc_irq.irq_callback = hc32_uart5_tc_irq_handler;
+#endif
+#ifdef BSP_USING_UART6
+    struct hc32_uart_irq_config uart6_tc_irq = UART6_TX_CPLT_CONFIG;
+    uart_config[UART6_INDEX].tc_irq = uart6_tc_irq;
+    uart_config[UART6_INDEX].tc_irq.irq_callback = hc32_uart6_tc_irq_handler;
+#endif
+}
+#endif /* HC32F448 */
 
 static const struct rt_uart_ops hc32_uart_ops =
 {
@@ -1636,9 +1972,7 @@ int rt_hw_usart_init(void)
     rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct hc32_uart);
 
     hc32_uart_get_info();
-#if defined (HC32F460) || defined (HC32F4A0)
     hc32_get_uart_callback();
-#endif
 
     for (int i = 0; i < obj_num; i++)
     {

bsp/hc32/libraries/hc32_drivers/drv_usart_v2.h

@@ -57,6 +57,14 @@ struct hc32_uart_config
     struct hc32_uart_irq_config rxerr_irq;
     struct hc32_uart_irq_config rx_irq;
     struct hc32_uart_irq_config tx_irq;
+#elif defined (HC32F448)
+    IRQn_Type                   irq_num;
+    en_int_src_t                rxerr_int_src;
+    en_int_src_t                tx_int_src;
+    en_int_src_t                rx_int_src;
+#ifdef RT_SERIAL_USING_DMA
+    en_int_src_t                rxto_int_src;
+#endif
 #endif
     struct hc32_uart_irq_config tc_irq;
 

bsp/hc32/libraries/hc32_drivers/drv_wktm.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd.
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -30,7 +30,7 @@
 #else
     #if defined(HC32F4A0)
         #define PWC_WKT_CLK_SRC             (PWC_WKT_CLK_SRC_RTCLRC)
-    #elif defined(HC32F460)
+    #elif defined(HC32F460) || defined(HC32F448)
         #define PWC_WKT_CLK_SRC             (PWC_WKT_CLK_SRC_LRC)
     #endif
     #define PWC_WKT_COUNT_FRQ           (32768UL)

bsp/hc32/libraries/hc32_drivers/drv_wktm.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd.
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/hc32/libraries/hc32f448_ddl/ChangeLog.md

@@ -0,0 +1,362 @@
+# Update History
+------
+## V1.1.0  Dec 15, 2023
+#### documents
+#### drivers
+- ##### bsp/components
+  - **24cxx**
+    - Add null pointer check
+  - **gt9xx**
+    - Add null pointer check
+  - **nt35510**
+    - Add null pointer check
+  - **tca9539**
+    - Add null pointer check
+  - **w25qxx**
+    - Add null pointer check
+- ##### bsp/ev_hc32f448_lqfp80
+  - Add API BSP_XTAL32_Init()
+  - Optimize function BSP_I2C_Init()
+  - Update EXCLK clock frequency: 100MHz -> 50MHZ in function BSP_CLK_Init()
+  - Add include file named hc32_ll_fcm.h and add declaration of BSP_XTAL32_Init()
+  - Modify I2C baudrate: 400000 -> 100000
+  - Modify the timing: EXCLK 100MHz -> 40MHz
+- ##### cmsis/Device
+  - Optimize TMR4_OCMRxx
+  - Rename EMB_CTL1 register bit: SRAMERREN -> SRAMECCERREN
+- ##### hc32_ll_driver
+  - **adc**
+    - Modify typo
+    - API fixed: ADC_DeInit()
+    - Add declaration of API ADC_MxChCmd(), ADC_ConvDataAverageMxChCmd(), and add defgroup ADC_Mx_Channel
+    - Add declaration of API ADC_GetResolution()
+    - Add API ADC_MxChCmd(),ADC_ConvDataAverageMxChCmd
+    - Add API ADC_GetResolution()
+  - **clk**
+    - Modify comment
+    - Refine API CLK_XtalStdInit. and add API CLK_XtalStdCmd, CLK_SetXtalStdExceptionType
+    - Modify API CLK_Xtal32Cmd(), CLK_MrcCmd() and CLK_LrcCmd(), use DDL_DelayUS() to replace CLK_Delay()
+  - **cmp**
+    - Modify typo
+  - **ctc**
+    - Modify typo
+  - **dac**
+    - Refine data validation
+    - Add assert for set DAC source and modify IS_AMP_CTRL_ALLOWED()
+  - **dbgc**
+    - Remove API DBGC_GetChipID()
+    - Add macro definition DBGC_Trace_Mode
+    - Add declaration of API DBGC_TraceIoCmd,DBGC_TraceModeConfig
+    - Remove API DBGC_GetChipID()A
+    - Add assert to DBGC_PeriphCmd & DBGC_Periph2Cmd
+    - Add assert IS_DGBC_TRACE_MD and add API DBGC_TraceIoCmd,DBGC_TraceModeConfig
+  - **dcu**
+    - Modify typo
+    - Modify function DCU_IntCmd() for misra
+  - **dma**
+    - Add API DMA_SetDataWidth()
+    - Delete group DMA_AHB_HPROT_Config
+    - Delete API DMA_AHB_HProtPrivilegeCmd()
+    - Modify API input param type:u16->u32
+    - Add structure stc_dma_rc_nonseq_init_t
+    - Add API DMA_ReconfigNonSeqStructInit() & DMA_ReconfigNonSeqInit()
+    - Optimize set blocksize & repeat count process
+    - Add DMA Repeat size assert
+    - Use macros replace immediate data, modify IS_DMA_NON_SEQ_TRANS_CNT
+  - **efm**
+    - Rename EFM_DataCacheResetCmd() as EFM_CacheRamReset() and modify comment
+    - Optimized macro group EFM_Remap_Size definitions
+    - Add structure of stc_efm_location_t and declaration of API EFM_GetWaferID(), EFM_GetLocation(), EFM_GetLotID()
+    - Modify typo
+    - Remove address assert from EFM_ReadByte()
+    - Refine EFM_SequenceProgram() & EFM_ChipErase(), and put them in RAM
+    - Add API EFM_GetWaferID(), EFM_GetLocation(), EFM_GetLotID()
+    - Modify flash sector number defined and API EFM_SequenceSectorOperateCmd()
+  - **emb**
+    - Update EMB_CTL1_CMPEN0~3 to EMB_CTL1_CMPEN1~4
+    - Add stc_emb_monitor_sys_t to combine osc, sram, lockup, lvd
+    - Replace macro: EMB_CTL1_SRAMERREN -> EMB_CTL1_SRAMECCERREN
+    - Add marco EMB_FLAG_CLR_ALL
+    - Function EMB_TMR4_Init don't call EMB_DeInit
+    - Function EMB_TMR6_Init don't call EMB_DeInit
+    - Modify stc_emb_monitor_sys_t structure relevant code
+    - Modify API EMB_ClearStatus assert
+  - **gpio**
+    - Modify GPIO_SetFunc()
+    - Rename GPIO_ExIntCmd() as GPIO_ExtIntCmd
+    - Optimize API: GPIO_Init(), GPIO_SetFunc(), GPIO_SubFuncCmd(), GPIO_InputMOSCmd(), GPIO_AnalogCmd(), GPIO_ExtIntCmd()
+    - Add assert for GPIO register lock status in API GPIO_AnalogCmd(), GPIO_ExtIntCmd()
+  - **i2c**
+    - Move macro define I2C_SRC_CLK to head file and add marco I2C_WIDTH_MAX_IMME
+    - Rename I2C_FIFO_FLAG_xx as I2C_FLAG_xx_FIFO_xx, I2C_INT_RFREQ as I2C_INT_RX_FIFO_REQ
+    - Adjust I2C_FLAG_ALL & I2C_FLAG_CLR_ALL & I2C_INT_ALL
+    - Add I2C_Flag_Clear def group
+    - Remove API I2C_FIFO_ClearRequestStatus() & I2C_FIFO_GetStatus
+    - Fix I2C_Deinit
+    - Move macro define I2C_SRC_CLK to head file
+    - Modify I2C_Restart()
+    - Refine I2C Flag & API I2C_SlaveAddrConfig/I2C_SlaveMaskAddrConfig
+  - **icg**
+    - Modify macro defineICG_SWDT_LPM_CNT_CONTINUE -> ICG_SWDT_LPM_CNT_CONT
+  - **interrupts**
+    - Add declaration of API INTC_GetIntSrcState()
+    - Remove space line
+    - Add API INTC_GetIntSrcState()
+  - **mcan**
+    - Removed definitions related to BEC and BEU.
+    - Optimized driver:
+    - 1. Integrated stc_mcan_classic_config_t and stc_mcan_fd_config_t into stc_mcan_bit_time_config_t
+    - 2. Integrated u32FdIso into u32FrameFormat.
+    - 3. Removed API MCAN_SetFdIsoOperation(), added API MCAN_SetFrameFormat().
+    - 4. Optimized the handling of the parameter stc_mcan_filter_t.u32FilterIndex
+    - 5. Add 5 APIs for better get protocol status(register PSR):
+    - MCAN_GetTdcValue(), MCAN_GetDataLastErrorCode(), MCAN_GetLastErrorCode(),
+    - MCAN_GetComState(), MCAN_GetProtocolFlagStatus()
+    - 6. Changed u8Activity of stc_mcan_protocol_status_t to u8ComState.
+    - 7. Changed MCAN_Comm_State to MCAN_Com_State and optimized the macros definitions.
+    - 8. Changed u8MsgStorageIndex of stc_mcan_hpm_status_t to u8MsgIndex. Optimized MCAN_HPM_Storage macros definitions.
+    - 7. Changed u8MsgStorageIndex of stc_mcan_hpm_status_t to u8MsgIndex.
+    - 8. Optimized local function MCAN_FilterInitConfig()
+    - 9. When the frame to be transmitted is a remote frame, do not write the data field to the message RAM.
+    - When the received frame is a remote frame, do not read the data field from the message RAM.
+    - Optimized comments.
+  - **mpu**
+    - Add structure stc_mpu_unit_init_t, and declaration of MPU_UnitInit(), MPU_UnitStructInit()
+    - Refine def group MPU_Flag
+    - Optimize MPU_ClearStatus function
+    - Add API MPU_UnitInit(), MPU_UnitStructInit()
+  - **pwc**
+    - Modify group PWC_Stop_Type
+    - Add function PWC_LVD_DeInit
+    - Modify the PWC_LVD_Detection_Voltage_Sel comment
+    - Modify PWC_RAM_PD_CAN1 as PWC_RAM_PD_MCAN
+    - Refine API PWC_SLEEP_Enter()
+    - Remove redundant assert
+    - Modify API PWC_PD_Enter() #use assert to replace the unlock, and add return value
+    - Modify API PWC_WKT_SetCompareValue()
+    - Refine PWC_SLEEP_Enter()
+    - Add API PWC_PD_SetIoState() & PWC_PD_SetMode()
+  - **qspi**
+    - Optimize QSPI_ClearStatus function
+  - **spi**
+    - Rename SPI_FLAG_OVERLOAD as SPI_FLAG_OVERRUN, SPI_FLAG_UNDERLOAD as SPI_FLAG_UNDERRUN
+    - Modify some assert
+    - Rename some API SPI_xxxConfig as SPI_Setxxx
+    - Add Send restriction in SPI_TxRx function
+  - **sram**
+    - Modify typo
+    - Refine def group SRAM_ECC_Mode, and refine def group SRAM_Err_Mode as SRAM_Exception_Type
+    - Remove wait cycle relevant code
+    - API fixed: SRAM_ClearStatus()
+    - Refine SRAM_SetEccMode, and refine SRAM_SetErrorMode() as SRAM_SetExceptionType
+  - **swdt**
+    - Modify macro define: SWDT_LPM_CNT_CONTINUE -> SWDT_LPM_CNT_CONT
+    - Optimize SWDT_ClearStatus function timeout
+  - **tmr6**
+    - Modify macro define for group TMR6_Emb_Ch_Define
+    - Modify for headfile update: CM_TMR6CR -> CM_TMR6_COMMON
+    - Modify typo
+  - **usart**
+    - Remove u32StopBit param from stc_usart_smartcard_init_t structure
+    - Add the declaration of API USART_GetFuncState()
+    - Modify return type of function USART_DeInit()
+    - Modify USART_SmartCard_Init() for stc_usart_smartcard_init_t has modified(u32StopBit has removed)
+    - Fix bug: did not enable MP while USART_MultiProcessor_Init()
+    - API refined: USART_SetBaudrate()
+    - Add API USART_GetFuncState()
+  - **utility**
+    - Modify register USART DR to USART TDR
+    - Prohibit DDL_DelayMS and DDL_DelayUS functions from being optimized
+  - **wdt**
+    - Modify macro define: WDT_LPM_CNT_CONTINUE -> WDT_LPM_CNT_CONT
+    - Optimize WDT_ClearStatus function timeout
+#### midwares
+#### projects
+- ##### ev_hc32f448_lqfp80/applications
+  - **functional_safety/iec60730_class_b**
+    - Initialize XTAL32 using BSP_XTAL32_Init
+  - **iap/iap_boot**
+    - Removed SRAM wait cycle relevant code
+  - **iap/iap_ymodem_boot**
+    - Removed SRAM wait cycle relevant code
+- ##### ev_hc32f448_lqfp80/examples
+  - **adc/adc_awd**
+    - Set XTAL as system clock source
+  - **adc/adc_base**
+    - Set XTAL as system clock source
+  - **adc/adc_buffer_mode**
+    - Set XTAL as system clock source
+  - **adc/adc_channel_remap**
+    - Set XTAL as system clock source
+  - **adc/adc_dma**
+    - Set XTAL as system clock source
+  - **adc/adc_hard_trigger**
+    - Set XTAL as system clock source
+  - **adc/adc_internal_analog_channel**
+    - Set XTAL as system clock source
+  - **adc/adc_over_sample**
+    - Set XTAL as system clock source
+  - **adc/adc_sync_mode**
+    - Removed SRAM wait cycle relevant code
+  - **aes/aes_base**
+    - Set XTAL as system clock source
+  - **clk/clk_switch_sysclk**
+    - Modify XTAL32 initialize process
+    - Removed SRAM wait cycle relevant code
+  - **clk/clk_xtalstop_detect**
+    - Use CLK_XtalStdInit() to replace XtalStopDetctInit()
+    - Modify XTAL_STOP_IrqCallback
+  - **ctc/ctc_ctcref_single_trimming**
+    - Initialize XTAL32 using BSP_XTAL32_Init
+  - **ctc/ctc_xtal32_trimming**
+    - Initialize XTAL32 using BSP_XTAL32_Init
+  - **dmac/dmac_base**
+    - Optimize DMA2_Error_Handler()
+  - **dmac/dmac_non_sequence**
+    - Fixed bug #revert test code.
+  - **efm/efm_chip_erase**
+    - Fixed bug # release write protect before sector erase
+  - **efm/efm_dbus**
+    - Set API DBUS_Protect_test optimization level
+  - **efm/efm_sequence_program**
+    - Re-structure
+  - **efm/efm_swap**
+    - Use EFM_GetSwapStatus to judge
+  - **emb/emb_cmp_brake_timer4**
+    - Fix magic number
+    - Modify TMR4_PwmConfig: enable main output following PWM initialization
+  - **emb/emb_cmp_brake_timer6**
+    - Fix magic number
+  - **emb/emb_lockup_brake_timer4**
+    - Modify TMR4_PwmConfig: enable main output following PWM initialization
+    - Optimize comments: HardFault_Generate and HardFault_Handler
+  - **emb/emb_lockup_brake_timer6**
+    - Optimize comments: HardFault_Generate and HardFault_Handler
+  - **emb/emb_lvd_brake_timer4**
+    - Modify TMR4_PwmConfig: enable main output following PWM initialization
+  - **emb/emb_osc_brake_timer4**
+    - Modify TMR4_PwmConfig: enable main output following PWM initialization
+  - **emb/emb_port_brake_timer4**
+    - Modify TMR4_PwmConfig: enable main output following PWM initialization
+  - **emb/emb_pwm_brake_timer4**
+    - Modify TMR4_PwmConfig: enable main output following PWM initialization
+  - **emb/emb_sram_brake_timer4**
+    - Modify TMR4_PwmConfig: enable main output following PWM initialization
+    - Optimize the 2nd data in SRAM_GenerateError()
+  - **emb/emb_sram_brake_timer6**
+    - Optimize the 2nd data in SRAM_GenerateError()
+  - **emb/emb_sw_brake_timer4**
+    - Modify TMR4_PwmConfig: enable main output following PWM initialization
+  - **event_port/ep_inout**
+    - Comment revise
+  - **exmc/exmc_smc_lcd_nt35510**
+    - Re-implement BSP_CLK_Init()
+  - **exmc/exmc_smc_sram_is61lv6416**
+    - Fix typos and modify file brief
+    - Fix memory address printf value
+    - Re-implement BSP_CLK_Init()
+  - **exmc/exmc_smc_sram_is61lv6416_dma**
+    - Add exmc_smc_sram_is61lv6416_dma example
+  - **hash/hash_base**
+    - Set XTAL as system clock source
+  - **i2c/i2c_master_dma**
+    - Add definition I2C_ADDR_MD as address condition select
+    - Configure DMA interrupt disable in I2C_DMA_Initialize() function
+  - **i2c/i2c_master_polling**
+    - Add definition I2C_ADDR_MD as address condition select
+  - **i2c/i2c_master_polling_fifo**
+    - Add definition I2C_ADDR_MD as address condition select
+  - **i2c/i2c_slave_dma**
+    - Remove redundant process for slave address commands
+    - Add definition I2C_ADDR_MD as address condition select
+    - Configure DMA interrupt disable in I2C_DMA_Initialize() function
+  - **i2c/i2c_slave_int**
+    - Remove redundant process for slave address commands
+    - Add definition I2C_ADDR_MD as address condition select
+  - **i2c/i2c_slave_polling**
+    - Add definition I2C_ADDR_MD as address condition select
+  - **i2c/i2c_slave_polling_fifo**
+    - Remove redundant process for slave address commands
+    - Add definition I2C_ADDR_MD as address condition select
+  - **icg/icg_wdt_interrupt_hw_startup**
+    - Add delay before WDT_GetStatus function
+  - **intc/intc_nmi_xtalstop**
+    - optimize function NMI_Xtal_Init
+  - **mcan/mcan_classical**
+    - Updates related to MCAN driver optimization.
+    - Peripheral SRAMC not used, removed related code.
+    - Code and comments optimized.
+  - **mcan/mcan_fd**
+    - Updates related to MCAN driver optimization.
+    - Peripheral SRAMC not used, removed related code.
+    - Code and comments optimized.
+  - **mcan/mcan_loopback**
+    - Optimized the example.
+  - **mpu/mpu_core_write_protect**
+    - Fixed parameters error of Core_MPU_Region_Size
+    - Modify trigger condition for RTC protection
+    - Optimize RTC init sequence
+  - **mpu/mpu_dma_write_protect**
+    - Remove key jitter
+  - **mpu/mpu_ip_read_protect**
+    - Optimize RTC init sequence
+  - **pwc/pwc_lpc**
+    - Disable HRC when enter sleep mode
+  - **pwc/pwc_stop_wake**
+    - Delete redundant code
+  - **qspi/qspi_base**
+    - Add read function of direct communication mode
+  - **rtc/rtc_alarm**
+    - Optimize RTC init sequence
+    - Replace XTAL32_ClkInit to BSP_XTAL32_Init
+  - **rtc/rtc_calendar**
+    - Optimize RTC init sequence
+  - **rtc/rtc_calibration_output**
+    - Optimize RTC init sequence
+    - Replace XTAL32_ClkInit to BSP_XTAL32_Init
+  - **rtc/rtc_low_power**
+    - Optimize RTC init sequence
+  - **sram/sram_error_check**
+    - sample code changed according to driver change
+  - **timer0/timer0_basetimer**
+    - Replace XTAL32_Config to BSP_XTAL32_Init
+  - **timer4/timer4_pwm_through**
+    - Modify the initial configuration to achieve 0% or 100% duty cycle
+  - **timer6/timer6_cmp_deadtime**
+    - Remove redundant code
+  - **timer6/timer6_cmp_sawtooth**
+    - Remove redundant code
+  - **timer6/timer6_cmp_sawtooth_dual_buf**
+    - Remove redundant code
+    - Modify compare register buffer initialization value
+  - **timer6/timer6_cmp_triangular_buf**
+    - Remove redundant code
+    - Modify compare register buffer initialization value
+  - **timer6/timer6_pwm_dynamic_dutycycle**
+    - Add timer6_pwm_dynamic_dutycycle example
+  - **timer6/timer6_valid_period**
+    - Modify compare register buffer initialization value
+  - **timera/timera_capture**
+    - Set XTAL as system clock source
+  - **timera/timera_compare_value_buffer**
+    - Set XTAL as system clock source
+  - **timera/timera_position_overflow_count**
+    - Set XTAL as system clock source
+  - **trng/trng_base**
+    - TRNG_Handler add __DSB for Arm Errata 838869
+    - Add TRNG_Cmd function
+    - Set XTAL as system clock source
+  - **usart/usart_clocksync_dma**
+    - Fix bug: possible null pointer for ClockSync_DMAConfig parameter pstcHandle
+  - **usart/usart_smartcard_atr**
+    - Remove u32StopBit from stcSmartCardInit structure
+  - **usart/usart_uart_dma**
+    - Optimize function: USART_TxComplete_IrqCallback
+  - **usart/usart_uart_multiprocessor**
+    - Optimize the RX process
+  - **wdt/wdt_interrupt_sw_startup**
+    - Add delay before WDT_GetStatus function
+#### utils
+------
+## V1.0.0  May 31, 2023
+- Initial release.

bsp/hc32/libraries/hc32f448_ddl/LICENSE

@@ -0,0 +1,29 @@
+BSD 3-Clause License
+
+Copyright (c) 2022-2023, Xiaohua Semiconductor Co., Ltd. ("XHSC")
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+  list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright notice,
+  this list of conditions and the following disclaimer in the documentation
+  and/or other materials provided with the distribution.
+
+* Neither the name of the copyright holder nor the names of its
+  contributors may be used to endorse or promote products derived from
+  this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

bsp/hc32/libraries/hc32f448_ddl/SConscript

@@ -0,0 +1,97 @@
+import rtconfig
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+
+# The set of source files associated with this SConscript file.
+
+src = Split('''
+drivers/cmsis/Device/HDSC/hc32f4xx/Source/system_hc32f448.c
+drivers/hc32_ll_driver/src/hc32_ll.c
+drivers/hc32_ll_driver/src/hc32_ll_aos.c
+drivers/hc32_ll_driver/src/hc32_ll_clk.c
+drivers/hc32_ll_driver/src/hc32_ll_dma.c
+drivers/hc32_ll_driver/src/hc32_ll_efm.c
+drivers/hc32_ll_driver/src/hc32_ll_fcg.c
+drivers/hc32_ll_driver/src/hc32_ll_fcm.c
+drivers/hc32_ll_driver/src/hc32_ll_gpio.c
+drivers/hc32_ll_driver/src/hc32_ll_icg.c
+drivers/hc32_ll_driver/src/hc32_ll_interrupts.c
+drivers/hc32_ll_driver/src/hc32_ll_pwc.c
+drivers/hc32_ll_driver/src/hc32_ll_rmu.c
+drivers/hc32_ll_driver/src/hc32_ll_sram.c
+drivers/hc32_ll_driver/src/hc32_ll_utility.c
+''')
+
+if GetDepend(['RT_USING_SERIAL']):
+    src += ['drivers/hc32_ll_driver/src/hc32_ll_usart.c']
+    src += ['drivers/hc32_ll_driver/src/hc32_ll_tmr0.c']
+
+if GetDepend(['RT_USING_I2C']):
+    src += ['drivers/hc32_ll_driver/src/hc32_ll_i2c.c']
+
+if GetDepend(['RT_USING_SPI']):
+    src += ['drivers/hc32_ll_driver/src/hc32_ll_spi.c']
+
+if GetDepend(['RT_USING_QSPI']):
+    src += ['drivers/hc32_ll_driver/src/hc32_ll_qspi.c']
+
+if GetDepend(['RT_USING_CAN']):
+    src += ['drivers/hc32_ll_driver/src/hc32_ll_mcan.c']
+
+if GetDepend(['RT_USING_ADC']):
+    src += ['drivers/hc32_ll_driver/src/hc32_ll_adc.c']
+
+if GetDepend(['RT_USING_DAC']):
+    src += ['drivers/hc32_ll_driver/src/hc32_ll_dac.c']
+
+if GetDepend(['RT_USING_RTC']):
+    src += ['drivers/hc32_ll_driver/src/hc32_ll_rtc.c']
+
+if GetDepend(['RT_USING_WDT']):
+    src += ['drivers/hc32_ll_driver/src/hc32_ll_swdt.c']
+    src += ['drivers/hc32_ll_driver/src/hc32_ll_wdt.c']
+
+if GetDepend(['RT_USING_ON_CHIP_FLASH']):
+    src += ['drivers/hc32_ll_driver/src/hc32_ll_efm.c']
+
+if GetDepend(['RT_USING_HWTIMER']):
+    src += ['drivers/hc32_ll_driver/src/hc32_ll_tmr4.c']
+    src += ['drivers/hc32_ll_driver/src/hc32_ll_tmr6.c']
+    src += ['drivers/hc32_ll_driver/src/hc32_ll_tmra.c']
+
+if GetDepend(['RT_USING_PULSE_ENCODER']):
+    src += ['drivers/hc32_ll_driver/src/hc32_ll_tmr6.c']
+    src += ['drivers/hc32_ll_driver/src/hc32_ll_tmra.c']
+
+if GetDepend(['RT_USING_PWM']):
+    src += ['drivers/hc32_ll_driver/src/hc32_ll_tmr4.c']
+    src += ['drivers/hc32_ll_driver/src/hc32_ll_tmr6.c']
+    src += ['drivers/hc32_ll_driver/src/hc32_ll_tmra.c']
+
+if GetDepend(['RT_HWCRYPTO_USING_RNG']):
+    src += ['drivers/hc32_ll_driver/src/hc32_ll_trng.c']
+
+if GetDepend(['RT_HWCRYPTO_USING_CRC']):
+    src += ['drivers/hc32_ll_driver/src/hc32_ll_crc.c']
+
+if GetDepend(['RT_HWCRYPTO_USING_AES']):
+    src += ['drivers/hc32_ll_driver/src/hc32_ll_aes.c']
+
+if GetDepend(['RT_HWCRYPTO_USING_SHA2']):
+    src += ['drivers/hc32_ll_driver/src/hc32_ll_hash.c']
+
+if GetDepend(['BSP_RTC_USING_XTAL32']) or GetDepend(['RT_USING_PM']):
+    src += ['drivers/hc32_ll_driver/src/hc32_ll_fcm.c']
+
+path = [
+    cwd + '/drivers/cmsis/Device/HDSC/hc32f4xx/Include',
+    cwd + '/drivers/cmsis/Include',
+    cwd + '/drivers/hc32_ll_driver/inc',]
+
+CPPDEFINES = ['USE_DDL_DRIVER']
+
+group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+
+Return('group')

bsp/hc32/libraries/hc32f448_ddl/config/flashloader/FlashHC32F448.mac

@@ -0,0 +1,16 @@
+setup()
+{
+  ;
+}
+
+execUserPreload()
+{
+  __message "----- Prepare hardware for Flashloader -----\n";
+  setup();
+}
+execUserFlashInit()  // Called by debugger before loading flash loader in RAM.
+{
+  __message "----- Prepare hardware for Flashloader -----\n";
+  setup();
+}
+

bsp/hc32/libraries/hc32f448_ddl/config/flashloader/FlashHC32F448_otp.flash

@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<flash_device>
+  <exe>$PROJ_DIR$\..\libraries\hc32f448_ddl\drivers\cmsis\Device\HDSC\hc32f4xx\Source\IAR\flashloader\FlashHC32F448_otp.out</exe>
+  <page>4</page>
+  <block>1 0x400</block>
+  <flash_base>0x03000C00</flash_base>
+  <macro>$PROJ_DIR$\..\libraries\hc32f448_ddl\drivers\cmsis\Device\HDSC\hc32f4xx\Source\IAR\flashloader\FlashHC32F448_otp.mac</macro>
+  <aggregate>0</aggregate>
+</flash_device>

bsp/hc32/libraries/hc32f448_ddl/config/flashloader/FlashHC32F448_qspi.flash

@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<flash_device>
+  <exe>$PROJ_DIR$\..\libraries\hc32f448_ddl\config\flashloader\FlashHC32F448_qspi.out</exe>
+  <page>256</page>
+  <block>2048 0x1000</block>
+  <flash_base>0x98000000</flash_base>
+  <aggregate>0</aggregate>
+</flash_device>

bsp/hc32/libraries/hc32f448_ddl/config/flashloader/FlashHC32F448xA.board

@@ -0,0 +1,16 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<flash_board>
+  <pass>
+    <loader>$PROJ_DIR$\..\libraries\hc32f448_ddl\config\flashloader\FlashHC32F448xA.flash</loader>
+    <range>CODE 0x0 0x1FFFF</range>
+  </pass>
+  <pass>
+    <loader>$PROJ_DIR$\..\libraries\hc32f448_ddl\config\flashloader\FlashHC32F448_otp.flash</loader>
+    <range>CODE 0x03000C00 0x03000FFF</range>
+  </pass>
+  <pass>
+    <loader>$PROJ_DIR$\..\libraries\hc32f448_ddl\config\flashloader\FlashHC32F448_qspi.flash</loader>
+    <range>CODE 0x98000000 0x987FFFFF</range>
+  </pass>
+</flash_board>

bsp/hc32/libraries/hc32f448_ddl/config/flashloader/FlashHC32F448xA.flash

@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<flash_device>
+  <exe>$PROJ_DIR$\..\libraries\hc32f448_ddl\drivers\cmsis\Device\HDSC\hc32f4xx\Source\IAR\flashloader\FlashHC32F448.out</exe>
+  <page>4</page>
+  <block>16 0x2000</block>
+  <flash_base>0x00000000</flash_base>
+  <macro>$PROJ_DIR$\..\libraries\hc32f448_ddl\drivers\cmsis\Device\HDSC\hc32f4xx\Source\IAR\flashloader\FlashHC32F448.mac</macro>
+  <aggregate>0</aggregate>
+</flash_device>

bsp/hc32/libraries/hc32f448_ddl/config/flashloader/FlashHC32F448xC.board

@@ -0,0 +1,16 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<flash_board>
+  <pass>
+    <loader>$PROJ_DIR$\..\libraries\hc32f448_ddl\config\flashloader\FlashHC32F448xC.flash</loader>
+    <range>CODE 0x0 0x3FFFF</range>
+  </pass>
+  <pass>
+    <loader>$PROJ_DIR$\..\libraries\hc32f448_ddl\config\flashloader\FlashHC32F448_otp.flash</loader>
+    <range>CODE 0x03000C00 0x03000FFF</range>
+  </pass>
+  <pass>
+    <loader>$PROJ_DIR$\..\libraries\hc32f448_ddl\config\flashloader\FlashHC32F448_qspi.flash</loader>
+    <range>CODE 0x98000000 0x987FFFFF</range>
+  </pass>
+</flash_board>

bsp/hc32/libraries/hc32f448_ddl/config/flashloader/FlashHC32F448xC.flash

@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<flash_device>
+  <exe>$PROJ_DIR$\..\libraries\hc32f448_ddl\drivers\cmsis\Device\HDSC\hc32f4xx\Source\IAR\flashloader\FlashHC32F448.out</exe>
+  <page>4</page>
+  <block>32 0x2000</block>
+  <flash_base>0x00000000</flash_base>
+  <macro>$PROJ_DIR$\..\libraries\hc32f448_ddl\drivers\cmsis\Device\HDSC\hc32f4xx\Source\IAR\flashloader\FlashHC32F448.mac</macro>
+  <aggregate>0</aggregate>
+</flash_device>

bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/components/24cxx/24cxx.c

@@ -0,0 +1,278 @@
+/**
+ *******************************************************************************
+ * @file  24cxx.c
+ * @brief This midware file provides firmware functions to 24cxx EEPROM.
+ @verbatim
+   Change Logs:
+   Date             Author          Notes
+   2022-03-31       CDT             First version
+   2023-12-15       CDT             Add null pointer check
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                    opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "24cxx.h"
+
+/**
+ * @addtogroup BSP
+ * @{
+ */
+
+/**
+ * @addtogroup Components
+ * @{
+ */
+
+/**
+ * @defgroup 24CXX EEPROM Driver for 24CXX
+ * @{
+ */
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup 24CXX_Local_Macros 24CXX Local Macros
+ * @{
+ */
+#define EE_24CXX_WAIT_TIMEOUT           (0x20000UL)
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+/**
+ * @defgroup 24CXX_Local_Types 24CXX Local Types
+ * @{
+ */
+static uint32_t u32PageSize;
+static uint32_t u32Capacity;
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+
+/**
+ * @defgroup 24CXX_Global_Functions 24CXX Global Functions
+ * @{
+ */
+
+/**
+ * @brief  Initializes I2C for 24CXX.
+ * @param  [in] pstc24cxxLL         Pointer to a @ref stc_24cxx_ll_t structure.
+ * @retval int32_t:
+ *         - LL_OK:                 Success
+ *         - LL_ERR_INVD_PARAM:     Invalid parameter
+ */
+int32_t EE_24CXX_Init(const stc_24cxx_ll_t *pstc24cxxLL)
+{
+    int32_t i32Ret;
+    if ((pstc24cxxLL == NULL) || (pstc24cxxLL->u32PageSize == 0U) || (pstc24cxxLL->u32Capacity == 0U) ||
+        (pstc24cxxLL->Init == NULL)) {
+        i32Ret = LL_ERR_INVD_PARAM;
+    } else {
+        u32PageSize = pstc24cxxLL->u32PageSize;
+        u32Capacity = pstc24cxxLL->u32Capacity;
+        i32Ret = pstc24cxxLL->Init();
+    }
+    return i32Ret;
+}
+
+/**
+ * @brief  De-Initializes I2C for 24CXX.
+ * @param  [in] pstc24cxxLL         Pointer to a @ref stc_24cxx_ll_t structure.
+ * @retval int32_t:
+ *         - LL_OK:                 Success
+ *         - LL_ERR_INVD_PARAM:     Invalid parameter
+ */
+int32_t EE_24CXX_DeInit(const stc_24cxx_ll_t *pstc24cxxLL)
+{
+    int32_t i32Ret = LL_OK;
+    if ((pstc24cxxLL == NULL) || (pstc24cxxLL->DeInit == NULL)) {
+        i32Ret = LL_ERR_INVD_PARAM;
+    } else {
+        pstc24cxxLL->DeInit();
+    }
+    return i32Ret;
+}
+
+/**
+ * @brief  24CXX read data.
+ * @param  [in] pstc24cxxLL         Pointer to a @ref stc_24cxx_ll_t structure.
+ * @param  [in] u16Addr:            The start address of the data to be read.
+ * @param  [in] pu8Buf:             The pointer to the buffer contains the data to be stored.
+ * @param  [in] u32Len:             Buffer size in byte.
+ * @retval int32_t:
+ *         - LL_OK:                 Success
+ *         - LL_ERR:                Receive NACK
+ *         - LL_ERR_TIMEOUT:        Timeout
+ *         - LL_ERR_INVD_PARAM:     Invalid parameter
+ */
+int32_t EE_24CXX_Read(const stc_24cxx_ll_t *pstc24cxxLL, uint16_t u16Addr, uint8_t *pu8Buf, uint32_t u32Len)
+{
+    int32_t i32Ret;
+
+    if (((u16Addr + u32Len) > u32Capacity) || (pstc24cxxLL == NULL) || (pstc24cxxLL->Read == NULL) ||
+        (pu8Buf == NULL)) {
+        i32Ret = LL_ERR_INVD_PARAM;
+    } else {
+        i32Ret = pstc24cxxLL->Read(u16Addr, pu8Buf, u32Len);
+    }
+    return i32Ret;
+}
+
+/**
+ * @brief  24CXX write data.
+ * @param  [in] pstc24cxxLL         Pointer to a @ref stc_24cxx_ll_t structure.
+ * @param  [in] u16Addr:            The start address of the data to be write.
+ * @param  [in] pu8Buf:             The pointer to the buffer contains the data to be write.
+ * @param  [in] u32Len:             Buffer size in byte.
+ * @retval int32_t:
+ *         - LL_OK:                 Success
+ *         - LL_ERR:                Receive NACK
+ *         - LL_ERR_TIMEOUT:        Timeout
+ *         - LL_ERR_INVD_PARAM:     Invalid parameter
+ */
+int32_t EE_24CXX_Write(const stc_24cxx_ll_t *pstc24cxxLL, uint16_t u16Addr, const uint8_t *pu8Buf, uint32_t u32Len)
+{
+    uint32_t u32PageNum;
+    uint8_t u8SingleNumStart;
+    uint8_t u8SingleNumEnd;
+    uint32_t u32NumRemainTemp = u32Len;
+    uint32_t u32WriteOffset = 0UL;
+    uint16_t u16WriteAddrTemp = u16Addr;
+    int32_t i32Ret = LL_OK;
+    uint32_t i;
+
+    if (((u16Addr + u32Len) > u32Capacity) || (u32PageSize == 0U) || (pstc24cxxLL == NULL) ||
+        (pstc24cxxLL->WritePage == NULL) || (pstc24cxxLL->Delay == NULL) || (pu8Buf == NULL)) {
+        return LL_ERR_INVD_PARAM;
+    }
+
+    /* If start write address is align with page size */
+    if (0U == (u16WriteAddrTemp % u32PageSize)) {
+        /* If Write number is less than page size */
+        if (u32Len < u32PageSize) {
+            u8SingleNumStart = (uint8_t)u32Len;
+        } else {
+            /* If Write number is more than page size */
+            u8SingleNumStart = 0U;
+        }
+        u32NumRemainTemp -= (uint32_t)u8SingleNumStart;
+    } else {
+        /* If start write address is not align with page size */
+        u8SingleNumStart = (uint8_t)(u32PageSize - (u16WriteAddrTemp % u32PageSize));
+        if ((uint32_t)u8SingleNumStart > u32Len) {
+            u8SingleNumStart = (uint8_t)u32Len;
+        }
+        u32NumRemainTemp -= (uint32_t)u8SingleNumStart;
+    }
+
+    u32PageNum = u32NumRemainTemp / u32PageSize;
+    u8SingleNumEnd = (uint8_t)(u32NumRemainTemp % u32PageSize);
+
+    if (0UL != u8SingleNumStart) {
+        i32Ret = pstc24cxxLL->WritePage(u16WriteAddrTemp, &pu8Buf[u32WriteOffset], (uint32_t)u8SingleNumStart);
+        /* Delay about 5ms for EEPROM */
+        pstc24cxxLL->Delay(5000U);
+        u16WriteAddrTemp += u8SingleNumStart;
+        u32WriteOffset += (uint32_t)u8SingleNumStart;
+    }
+
+    if (LL_OK == i32Ret) {
+        if (0UL != u32PageNum) {
+            for (i = 0UL; i < u32PageNum; i++) {
+                i32Ret = pstc24cxxLL->WritePage(u16WriteAddrTemp, &pu8Buf[u32WriteOffset], u32PageSize);
+                /* Delay about 5ms for EEPROM */
+                pstc24cxxLL->Delay(5000U);
+                u16WriteAddrTemp += (uint16_t)u32PageSize;
+                u32WriteOffset += u32PageSize;
+                if (LL_OK != i32Ret) {
+                    break;
+                }
+            }
+        }
+
+        if (LL_OK == i32Ret) {
+            if (0UL != u8SingleNumEnd) {
+                i32Ret = pstc24cxxLL->WritePage(u16WriteAddrTemp, &pu8Buf[u32WriteOffset], (uint32_t)u8SingleNumEnd);
+                /* Delay about 5ms for EEPROM */
+                pstc24cxxLL->Delay(5000U);
+            }
+        }
+    }
+    return i32Ret;
+}
+
+/**
+ * @brief  24CXX wait idle.
+ * @param  [in] pstc24cxxLL         Pointer to a @ref stc_24cxx_ll_t structure.
+ * @retval int32_t:
+ *         - LL_OK:                 Success
+ *         - LL_ERR_TIMEOUT:        Failed
+ *         - LL_ERR_INVD_PARAM:     Invalid parameter
+ */
+int32_t EE_24CXX_WaitIdle(const stc_24cxx_ll_t *pstc24cxxLL)
+{
+    int32_t i32Ret = LL_OK;
+    volatile uint32_t u32Tmp = 0UL;
+
+    if ((pstc24cxxLL == NULL) || (pstc24cxxLL->GetStatus == NULL)) {
+        return LL_ERR_INVD_PARAM;
+    }
+    while (LL_OK != pstc24cxxLL->GetStatus()) {
+        if (EE_24CXX_WAIT_TIMEOUT == u32Tmp++) {
+            i32Ret = LL_ERR_TIMEOUT;
+            break;
+        }
+    }
+    return i32Ret;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/

bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/components/24cxx/24cxx.h

@@ -0,0 +1,121 @@
+/**
+ *******************************************************************************
+ * @file  24cxx.h
+ * @brief This file provides firmware functions to 24CXX EEPROM.
+ @verbatim
+   Change Logs:
+   Date             Author          Notes
+   2022-03-31       CDT             First version
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                    opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __24CXX_H__
+#define __24CXX_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+/**
+ * @addtogroup BSP
+ * @{
+ */
+
+/**
+ * @addtogroup Components
+ * @{
+ */
+
+/**
+ * @addtogroup 24CXX
+ * @{
+ */
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ * @defgroup 24CXX_Global_Types 24CXX Global Types
+ * @{
+ */
+
+/**
+ * @brief 24CXX low layer structure definition
+ */
+typedef struct {
+    /* Properties */
+    uint32_t u32PageSize;
+    uint32_t u32Capacity;
+    /* Methods */
+    void (*Delay)(uint32_t);
+    int32_t (*Init)(void);
+    void (*DeInit)(void);
+    int32_t (*WritePage)(uint16_t u16Addr, const uint8_t *pu8Buf, uint32_t u32Len);
+    int32_t (*Read)(uint16_t u16Addr, uint8_t *pu8Buf, uint32_t u32Len);
+    int32_t (*GetStatus)(void);
+} stc_24cxx_ll_t;
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+  Global function prototypes (definition in C source)
+ ******************************************************************************/
+/**
+ * @addtogroup 24CXX_Global_Functions 24CXX Global Functions
+ * @{
+ */
+int32_t EE_24CXX_Init(const stc_24cxx_ll_t *pstc24cxxLL);
+int32_t EE_24CXX_DeInit(const stc_24cxx_ll_t *pstc24cxxLL);
+int32_t EE_24CXX_Read(const stc_24cxx_ll_t *pstc24cxxLL, uint16_t u16Addr, uint8_t *pu8Buf, uint32_t u32Len);
+int32_t EE_24CXX_Write(const stc_24cxx_ll_t *pstc24cxxLL, uint16_t u16Addr, const uint8_t *pu8Buf, uint32_t u32Len);
+int32_t EE_24CXX_WaitIdle(const stc_24cxx_ll_t *pstc24cxxLL);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __24CXX_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/

bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/components/gt9xx/gt9xx.c

@@ -0,0 +1,183 @@
+/**
+ *******************************************************************************
+ * @file  gt9xx.c
+ * @brief This file provides firmware functions for Touch Pad GT9XX.
+ @verbatim
+   Change Logs:
+   Date             Author          Notes
+   2022-12-31       CDT             First version
+   2023-12-15       CDT             Add null pointer check
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                    opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "gt9xx.h"
+
+/**
+ * @addtogroup BSP
+ * @{
+ */
+
+/**
+ * @addtogroup Components
+ * @{
+ */
+
+/**
+ * @defgroup GT9XX Touch Pad GT9XX
+ * @{
+ */
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+
+/**
+ * @defgroup GT9XX_Global_Functions GT9XX Global Functions
+ * @{
+ */
+
+/**
+ * @brief  Read register on touch pad register.
+ * @param  [in]  pstcGt9xxLL            Pointer to a @ref stc_gt9xx_ll_t structure
+ * @param  [in]  u16Reg                 Register to be read
+ * @param  [out] pu8RegValue            The buffer for reading
+ * @param  [in]  u32Len                 The buffer size for bytes
+ * @retval None
+ */
+void GT9XX_REG_Read(const stc_gt9xx_ll_t *pstcGt9xxLL, uint16_t u16Reg, uint8_t *pu8RegValue, uint32_t u32Len)
+{
+    uint8_t au8RegAddr[2];
+
+    if ((NULL != pstcGt9xxLL) && (NULL != pstcGt9xxLL->Read) && (NULL != pu8RegValue)) {
+        au8RegAddr[0] = (uint8_t)((u16Reg & 0xFF00U) >> 8);
+        au8RegAddr[1] = (uint8_t)(u16Reg & 0x00FFU);
+        (void)pstcGt9xxLL->Read(au8RegAddr, ARRAY_SZ(au8RegAddr), pu8RegValue, u32Len);
+    }
+}
+
+/**
+ * @brief  Write register on touch pad register.
+ * @param  [in]  pstcGt9xxLL            Pointer to a @ref stc_gt9xx_ll_t structure
+ * @param  [in]  u16Reg                 Register to be write
+ * @param  [in]  pu8RegValue            The buffer for writing
+ * @param  [in]  u32Len                 The buffer size for bytes
+ * @retval None
+ */
+void GT9XX_REG_Write(const stc_gt9xx_ll_t *pstcGt9xxLL, uint16_t u16Reg, const uint8_t *pu8RegValue, uint32_t u32Len)
+{
+    uint8_t au8RegAddr[2];
+
+    if ((NULL != pstcGt9xxLL) && (NULL != pstcGt9xxLL->Write) && (NULL != pu8RegValue)) {
+        au8RegAddr[0] = (uint8_t)((u16Reg & 0xFF00U) >> 8);
+        au8RegAddr[1] = (uint8_t)(u16Reg & 0x00FFU);
+        (void)pstcGt9xxLL->Write(au8RegAddr, ARRAY_SZ(au8RegAddr), pu8RegValue, u32Len);
+    }
+}
+
+/**
+ * @brief  Reset GT9XX.
+ * @param  [in] pstcGt9xxLL             Pointer to a @ref stc_gt9xx_ll_t structure.
+ * @retval None
+ */
+void GT9XX_SoftReset(const stc_gt9xx_ll_t *pstcGt9xxLL)
+{
+    uint8_t u8RegValue = 0x02U;
+
+    GT9XX_REG_Write(pstcGt9xxLL, GT9XX_COMMAND, &u8RegValue, 1UL);
+}
+
+/**
+ * @brief  Read GT9XX touch status.
+ * @param  [in] pstcGt9xxLL             Pointer to a @ref stc_gt9xx_ll_t structure.
+ * @retval Touch status
+ */
+uint8_t GT9XX_ReadTouchStatus(const stc_gt9xx_ll_t *pstcGt9xxLL)
+{
+    uint8_t u8Status = 0U;
+
+    GT9XX_REG_Read(pstcGt9xxLL, GT9XX_TOUCH_STATUS, &u8Status, 1UL);
+    return u8Status;
+}
+
+/**
+ * @brief  Read GT9XX ID.
+ * @param  [in] pstcGt9xxLL             Pointer to a @ref stc_gt9xx_ll_t structure.
+ * @param  [out] pu8IDValue             The buffer for reading ID
+ * @param  [in]  u32Len                 The buffer size for bytes
+ * @retval None
+ */
+void GT9XX_ReadProductID(const stc_gt9xx_ll_t *pstcGt9xxLL, uint8_t *pu8IDValue, uint32_t u32Len)
+{
+    GT9XX_REG_Read(pstcGt9xxLL, GT9XX_PRODUCT_ID, pu8IDValue, u32Len);
+}
+
+/**
+ * @brief  Read GT9XX point.
+ * @param  [in]  pstcGt9xxLL            Pointer to a @ref stc_gt9xx_ll_t structure.
+ * @param  [in]  u16Point               Touch pad point
+ * @param  [out] pu16X                  Point x coordinate
+ * @param  [out] pu16Y                  Point y coordinate
+ * @retval None
+ */
+void GT9XX_GetXY(const stc_gt9xx_ll_t *pstcGt9xxLL, uint16_t u16Point, uint16_t *pu16X, uint16_t *pu16Y)
+{
+    uint8_t au8Tmp[4];
+
+    if ((pu16X != NULL) && (pu16Y != NULL)) {
+        GT9XX_REG_Read(pstcGt9xxLL, u16Point, au8Tmp, 4UL);
+        (*pu16X) = (uint16_t)au8Tmp[0] | ((uint16_t)au8Tmp[1] << 8);
+        (*pu16Y) = (uint16_t)au8Tmp[2] | ((uint16_t)au8Tmp[3] << 8);
+    }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************************************************************************
+ * EOF (not truncated)
+ *****************************************************************************/

bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/components/gt9xx/gt9xx.h

@@ -0,0 +1,150 @@
+/**
+ *******************************************************************************
+ * @file  gt9XX.h
+ * @brief This file contains all the functions prototypes of the touch pad GT9XX
+ *        driver library.
+ @verbatim
+   Change Logs:
+   Date             Author          Notes
+   2022-12-31       CDT             First version
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                    opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __GT9XX_H__
+#define __GT9XX_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+/**
+ * @addtogroup BSP
+ * @{
+ */
+
+/**
+ * @addtogroup Components
+ * @{
+ */
+
+/**
+ * @addtogroup GT9XX
+ * @{
+ */
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ * @defgroup GT9XX_Global_Types GT9XX Global Types
+ * @{
+ */
+
+/**
+ * @brief GT9XX low layer structure definition
+ */
+typedef struct {
+    /* Methods */
+    void (*Init)(void);
+    void (*Read)(const uint8_t *pu8Reg, uint8_t u8RegLen, uint8_t *pu8Buf, uint32_t u32Len);
+    void (*Write)(const uint8_t *pu8Reg, uint8_t u8RegLen, const uint8_t *pu8Buf, uint32_t u32Len);
+} stc_gt9xx_ll_t;
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup GT9XX_Global_Macros GT9XX Global Macros
+ * @{
+ */
+/**
+ * @defgroup GT9XX_Local_Macros GT9XX Local Macros
+ * @{
+ */
+#define GT9XX_COMMAND                       (0x8040U)
+#define GT9XX_CONFIG                        (0x8047U)
+
+#define GT9XX_CHECK_SUM                     (0X80FF)
+
+#define GT9XX_PRODUCT_ID                    (0x8140U)
+#define GT9XX_TOUCH_STATUS                  (0x814EU)
+
+#define GT9XX_POINT1                        (0x8150U)
+#define GT9XX_POINT2                        (0x8158U)
+#define GT9XX_POINT3                        (0X8160U)
+#define GT9XX_POINT4                        (0X8168U)
+#define GT9XX_POINT5                        (0X8170U)
+#define GT9XX_POINT6                        (0X8178U)
+#define GT9XX_POINT7                        (0X8180U)
+#define GT9XX_POINT8                        (0X8188U)
+#define GT9XX_POINT9                        (0X8190U)
+#define GT9XX_POINT10                       (0X8198U)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+  Global function prototypes (definition in C source)
+ ******************************************************************************/
+/**
+ * @addtogroup GT9XX_Global_Functions
+ * @{
+ */
+void GT9XX_REG_Read(const stc_gt9xx_ll_t *pstcGt9xxLL, uint16_t u16Reg, uint8_t *pu8RegValue, uint32_t u32Len);
+void GT9XX_REG_Write(const stc_gt9xx_ll_t *pstcGt9xxLL, uint16_t u16Reg, const uint8_t *pu8RegValue, uint32_t u32Len);
+void GT9XX_SoftReset(const stc_gt9xx_ll_t *pstcGt9xxLL);
+uint8_t GT9XX_ReadTouchStatus(const stc_gt9xx_ll_t *pstcGt9xxLL);
+void GT9XX_ReadProductID(const stc_gt9xx_ll_t *pstcGt9xxLL, uint8_t *pu8IDValue, uint32_t u32Len);
+void GT9XX_GetXY(const stc_gt9xx_ll_t *pstcGt9xxLL, uint16_t u16Point, uint16_t *pu16X, uint16_t *pu16Y);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __GT9XX_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/

bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/components/nt35510/nt35510.h

@@ -0,0 +1,202 @@
+/**
+ *******************************************************************************
+ * @file  nt35510.h
+ * @brief This file contains all the functions prototypes of the LCD NT35510
+ *        driver library.
+ @verbatim
+   Change Logs:
+   Date             Author          Notes
+   2022-03-31       CDT             First version
+   2023-05-31       CDT             Optimize function arguments
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                    opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __NT35510_H__
+#define __NT35510_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+/**
+ * @addtogroup BSP
+ * @{
+ */
+
+/**
+ * @addtogroup Components
+ * @{
+ */
+
+/**
+ * @addtogroup NT35510
+ * @{
+ */
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ * @defgroup NT35510_Global_Types NT35510 Global Types
+ * @{
+ */
+
+/**
+ * @brief LCD Device Controller Structure Definition
+ */
+typedef struct {
+    volatile uint16_t u16REG;
+    volatile uint16_t u16RAM;
+} stc_lcd_controller_t;
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup NT35510_Global_Macros NT35510 Global Macros
+ * @{
+ */
+
+/**
+ * @defgroup LCD_Scan_Direction LCD Scan Direction
+ * @{
+ */
+#define LCD_SCAN_DIR_L2R_U2D            (0U)    /* From left to right && from up to down */
+#define LCD_SCAN_DIR_L2R_D2U            (1U)    /* From left to right && from down to up */
+#define LCD_SCAN_DIR_R2L_U2D            (2U)    /* From right to left && from up to down */
+#define LCD_SCAN_DIR_R2L_D2U            (3U)    /* From right to left && from down to up */
+#define LCD_SCAN_DIR_U2D_L2R            (4U)    /* From up to down && from left to right */
+#define LCD_SCAN_DIR_U2D_R2L            (5U)    /* From up to down && from right to left */
+#define LCD_SCAN_DIR_D2U_L2R            (6U)    /* From down to up && from left to right */
+#define LCD_SCAN_DIR_D2U_R2L            (7U)    /* From down to up && from right to left */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup LCD_Display_Direction LCD Display Direction
+ * @{
+ */
+#define LCD_DISPLAY_VERTICAL            (0x0000U)
+#define LCD_DISPLAY_HORIZONTAL          (0x0001U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup LCD_Color LCD Color
+ * @{
+ */
+#define LCD_COLOR_WHITE                 (0xFFFFU)
+#define LCD_COLOR_BLACK                 (0x0000U)
+#define LCD_COLOR_BLUE                  (0x001FU)
+#define LCD_COLOR_BRED                  (0xF81FU)
+#define LCD_COLOR_GRED                  (0xFFE0U)
+#define LCD_COLOR_GBLUE                 (0x07FFU)
+#define LCD_COLOR_RED                   (0xF800U)
+#define LCD_COLOR_MAGENTA               (0xF81FU)
+#define LCD_COLOR_GREEN                 (0x07E0U)
+#define LCD_COLOR_CYAN                  (0x7FFFU)
+#define LCD_COLOR_YELLOW                (0xFFE0U)
+#define LCD_COLOR_BROWN                 (0xBC40U)
+#define LCD_COLOR_BRRED                 (0xFC07U)
+#define LCD_COLOR_GRAY                  (0x8430U)
+
+#define LCD_COLOR_DARKBLUE              (0x01CFU)
+#define LCD_COLOR_LIGHTBLUE             (0x7D7CU)
+#define LCD_COLOR_GRAYBLUE              (0x5458U)
+
+#define LCD_COLOR_LIGHTGREEN            (0x841FU)
+#define LCD_COLOR_LIGHTGRAY             (0xEF5BU)
+#define LCD_COLOR_LGRAY                 (0xC618U)
+#define LCD_COLOR_LGRAYBLUE             (0xA651U)
+#define LCD_COLOR_LBBLUE                (0x2B12U)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+  Global function prototypes (definition in C source)
+ ******************************************************************************/
+/**
+ * @addtogroup NT35510_Global_Functions
+ * @{
+ */
+void NT35510_Init(stc_lcd_controller_t *pstcLCD);
+void NT35510_WriteData(stc_lcd_controller_t *pstcLCD, uint16_t u16Data);
+void NT35510_WriteReg(stc_lcd_controller_t *pstcLCD, uint16_t u16Reg);
+uint16_t NT35510_ReadData(stc_lcd_controller_t *pstcLCD);
+void NT35510_WriteRegData(stc_lcd_controller_t *pstcLCD, uint16_t u16Reg, uint16_t u16Data);
+uint16_t NT35510_ReadRegData(stc_lcd_controller_t *pstcLCD, uint16_t u16Reg);
+uint16_t NT35510_ReadID(stc_lcd_controller_t *pstcLCD);
+void NT35510_DisplayOn(stc_lcd_controller_t *pstcLCD);
+void NT35510_DisplayOff(stc_lcd_controller_t *pstcLCD);
+uint16_t NT35510_GetPixelWidth(void);
+uint16_t NT35510_GetPixelHeight(void);
+void NT35510_SetScanDir(stc_lcd_controller_t *pstcLCD, uint16_t u16Dir);
+void NT35510_SetDisplayDir(stc_lcd_controller_t *pstcLCD, uint16_t u16Dir);
+void NT35510_PrepareWriteRAM(stc_lcd_controller_t *pstcLCD);
+void NT35510_SetBackLight(stc_lcd_controller_t *pstcLCD, uint8_t u8PWM);
+void NT35510_SetCursor(stc_lcd_controller_t *pstcLCD, uint16_t u16Xpos, uint16_t u16Ypos);
+void NT35510_WritePixel(stc_lcd_controller_t *pstcLCD, uint16_t u16Xpos, uint16_t u16Ypos, uint16_t u16RGBCode);
+void NT35510_DrawLine(stc_lcd_controller_t *pstcLCD, uint16_t u16X1, uint16_t u16Y1,
+                      uint16_t u16X2, uint16_t u16Y2, uint16_t u16RGBCode);
+void NT35510_DrawCircle(stc_lcd_controller_t *pstcLCD, uint16_t u16Xpos, uint16_t u16Ypos,
+                        uint16_t u16Radius, uint16_t u16RGBCode);
+void NT35510_FillTriangle(stc_lcd_controller_t *pstcLCD, uint16_t u16X1, uint16_t u16Y1,
+                          uint16_t u16X2, uint16_t u16Y2, uint16_t u16X3, uint16_t u16Y3, uint16_t u16RGBCode);
+void NT35510_DrawRectangle(stc_lcd_controller_t *pstcLCD, uint16_t u16X1, uint16_t u16Y1,
+                           uint16_t u16X2, uint16_t u16Y2, uint16_t u16RGBCode);
+void NT35510_Clear(stc_lcd_controller_t *pstcLCD, uint16_t u16RGBCode);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NT35510_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/

bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/components/tca9539/tca9539.c

@@ -0,0 +1,337 @@
+/**
+ *******************************************************************************
+ * @file  tca9539.c
+ * @brief This file provides firmware functions for IO expand IC TCA9539.
+ @verbatim
+   Change Logs:
+   Date             Author          Notes
+   2022-03-31       CDT             First version
+   2023-12-15       CDT             Add null pointer check
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                    opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "tca9539.h"
+
+/**
+ * @addtogroup BSP
+ * @{
+ */
+
+/**
+ * @addtogroup Components
+ * @{
+ */
+
+/**
+ * @defgroup TCA9539 IO Expand IC TCA9539
+ * @{
+ */
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+/**
+ * @defgroup TCA9539_Global_Functions TCA9539 Global Functions
+ * @{
+ */
+
+/**
+ * @brief  Initialize TCA9539.
+ * @param  [in] pstcTca9539LL           Pointer to a @ref stc_tca9539_ll_t structure.
+ * @retval int32_t:
+ *           - LL_OK: Initialize success
+ *           - LL_ERR_INVD_PARAM: Invalid parameter
+ */
+int32_t TCA9539_Init(const stc_tca9539_ll_t *pstcTca9539LL)
+{
+    int32_t i32Ret = LL_OK;
+    uint8_t u8TempData[2];
+
+    if ((pstcTca9539LL == NULL) || (pstcTca9539LL->Reset == NULL) || (pstcTca9539LL->Init == NULL) ||
+        (pstcTca9539LL->Write == NULL)) {
+        i32Ret = LL_ERR_INVD_PARAM;
+    } else {
+        pstcTca9539LL->Reset();
+        pstcTca9539LL->Init();
+        /* All Pins are input as default */
+        u8TempData[1] = 0xFFU;
+        u8TempData[0] = TCA9539_REG_CONFIG_PORT0;
+        pstcTca9539LL->Write(&u8TempData[0], &u8TempData[1], 1U);
+        u8TempData[0] = TCA9539_REG_CONFIG_PORT1;
+        pstcTca9539LL->Write(&u8TempData[0], &u8TempData[1], 1U);
+    }
+
+    return i32Ret;
+}
+
+/**
+ * @brief  Initialize TCA9539 interrupt.
+ * @param  [in] pstcTca9539LL           Pointer to a @ref stc_tca9539_ll_t structure.
+ * @retval int32_t:
+ *           - LL_OK: Initialize success
+ *           - LL_ERR_INVD_PARAM: Invalid parameter
+ */
+int32_t TCA9539_IntInit(const stc_tca9539_ll_t *pstcTca9539LL)
+{
+    int32_t i32Ret = LL_OK;
+
+    if ((pstcTca9539LL == NULL) || (pstcTca9539LL->IntInit == NULL)) {
+        i32Ret = LL_ERR_INVD_PARAM;
+    } else {
+        pstcTca9539LL->IntInit();
+    }
+
+    return i32Ret;
+}
+
+/**
+ * @brief  Reset TCA9539.
+ * @param  [in] pstcTca9539LL           Pointer to a @ref stc_tca9539_ll_t structure.
+ * @retval int32_t:
+ *           - LL_OK: Reset success
+ *           - LL_ERR_INVD_PARAM: Invalid parameter
+ */
+int32_t TCA9539_Reset(const stc_tca9539_ll_t *pstcTca9539LL)
+{
+    int32_t i32Ret = LL_OK;
+
+    if ((pstcTca9539LL == NULL) || (pstcTca9539LL->Reset == NULL)) {
+        i32Ret = LL_ERR_INVD_PARAM;
+    } else {
+        pstcTca9539LL->Reset();
+    }
+
+    return i32Ret;
+}
+
+/**
+ * @brief  Write TCA9539 pin output value.
+ * @param  [in] pstcTca9539LL           Pointer to a @ref stc_tca9539_ll_t structure.
+ * @param  [in] u8Port                  Port number.
+ *         This parameter can be one of the following values:
+ *           @arg TCA9539_IO_PORT0
+ *           @arg TCA9539_IO_PORT1
+ * @param  [in] u8Pin                   Pin number.
+ *         This parameter can be one of the following values:
+ *           @arg TCA9539_IO_PIN0
+ *           @arg TCA9539_IO_PIN1
+ *           @arg TCA9539_IO_PIN2
+ *           @arg TCA9539_IO_PIN3
+ *           @arg TCA9539_IO_PIN4
+ *           @arg TCA9539_IO_PIN5
+ *           @arg TCA9539_IO_PIN6
+ *           @arg TCA9539_IO_PIN7
+ *           @arg TCA9539_IO_PIN_ALL:   All of the above
+ * @param  [in] u8PinState              Pin state to be written.
+ *         This parameter can be one of the following values:
+ *           @arg TCA9539_PIN_RESET
+ *           @arg TCA9539_PIN_SET
+ * @retval int32_t:
+ *           - LL_OK: Operation success
+ *           - LL_ERR_INVD_PARAM: Invalid parameter
+ */
+int32_t TCA9539_WritePin(const stc_tca9539_ll_t *pstcTca9539LL, uint8_t u8Port, uint8_t u8Pin, uint8_t u8PinState)
+{
+    int32_t i32Ret = LL_OK;
+    uint8_t u8TempData[2];
+
+    if ((pstcTca9539LL == NULL) || (pstcTca9539LL->Read == NULL) || (pstcTca9539LL->Write == NULL)) {
+        i32Ret = LL_ERR_INVD_PARAM;
+    } else {
+        u8TempData[0] = u8Port + TCA9539_REG_OUTPUT_PORT0;
+        pstcTca9539LL->Read(&u8TempData[0], &u8TempData[1], 1U);
+        if (0U == u8PinState) {
+            u8TempData[1] &= (uint8_t)(~u8Pin);
+        } else {
+            u8TempData[1] |= u8Pin;
+        }
+        pstcTca9539LL->Write(&u8TempData[0], &u8TempData[1], 1U);
+    }
+
+    return i32Ret;
+}
+
+/**
+ * @brief  Read TCA9539 pin input value.
+ * @param  [in] pstcTca9539LL           Pointer to a @ref stc_tca9539_ll_t structure.
+ * @param  [in] u8Port                  Port number.
+ *         This parameter can be one of the following values:
+ *           @arg TCA9539_IO_PORT0
+ *           @arg TCA9539_IO_PORT1
+ * @param  [in] u8Pin                   Pin number.
+ *         This parameter can be one of the following values:
+ *           @arg TCA9539_IO_PIN0
+ *           @arg TCA9539_IO_PIN1
+ *           @arg TCA9539_IO_PIN2
+ *           @arg TCA9539_IO_PIN3
+ *           @arg TCA9539_IO_PIN4
+ *           @arg TCA9539_IO_PIN5
+ *           @arg TCA9539_IO_PIN6
+ *           @arg TCA9539_IO_PIN7
+ *           @arg TCA9539_IO_PIN_ALL:   All of the above
+ * @param  [out] pu8PinState            Pin state to be read.
+ *         This parameter can be one of the following values:
+ *           @arg TCA9539_PIN_RESET
+ *           @arg TCA9539_PIN_SET
+ * @retval int32_t:
+ *           - LL_OK: Operation success
+ *           - LL_ERR_INVD_PARAM: Invalid parameter
+ */
+int32_t TCA9539_ReadPin(const stc_tca9539_ll_t *pstcTca9539LL, uint8_t u8Port, uint8_t u8Pin, uint8_t *pu8PinState)
+{
+    int32_t i32Ret = LL_OK;
+    uint8_t u8TempData[2];
+
+    if ((pstcTca9539LL == NULL) || (pstcTca9539LL->Read == NULL) || (pu8PinState == NULL)) {
+        i32Ret = LL_ERR_INVD_PARAM;
+    } else {
+        u8TempData[0] = u8Port + TCA9539_REG_INPUT_PORT0;
+        pstcTca9539LL->Read(&u8TempData[0], &u8TempData[1], 1U);
+        if (0U != (u8TempData[1] & u8Pin)) {
+            *pu8PinState = TCA9539_PIN_SET;
+        } else {
+            *pu8PinState = TCA9539_PIN_RESET;
+        }
+    }
+
+    return i32Ret;
+}
+
+/**
+ * @brief  Toggle TCA9539 pin output value.
+ * @param  [in] pstcTca9539LL           Pointer to a @ref stc_tca9539_ll_t structure.
+ * @param  [in] u8Port                  Port number.
+ *         This parameter can be one of the following values:
+ *           @arg TCA9539_IO_PORT0
+ *           @arg TCA9539_IO_PORT1
+ * @param  [in] u8Pin                   Pin number.
+ *         This parameter can be one of the following values:
+ *           @arg TCA9539_IO_PIN0
+ *           @arg TCA9539_IO_PIN1
+ *           @arg TCA9539_IO_PIN2
+ *           @arg TCA9539_IO_PIN3
+ *           @arg TCA9539_IO_PIN4
+ *           @arg TCA9539_IO_PIN5
+ *           @arg TCA9539_IO_PIN6
+ *           @arg TCA9539_IO_PIN7
+ *           @arg TCA9539_IO_PIN_ALL:   All of the above
+ * @retval int32_t:
+ *           - LL_OK: Operation success
+ *           - LL_ERR_INVD_PARAM: Invalid parameter
+ */
+int32_t TCA9539_TogglePin(const stc_tca9539_ll_t *pstcTca9539LL, uint8_t u8Port, uint8_t u8Pin)
+{
+    int32_t i32Ret = LL_OK;
+    uint8_t u8TempData[2];
+
+    if ((pstcTca9539LL == NULL) || (pstcTca9539LL->Read == NULL) || (pstcTca9539LL->Write == NULL)) {
+        i32Ret = LL_ERR_INVD_PARAM;
+    } else {
+        u8TempData[0] = u8Port + TCA9539_REG_OUTPUT_PORT0;
+        pstcTca9539LL->Read(&u8TempData[0], &u8TempData[1], 1U);
+        u8TempData[1] ^= u8Pin;
+        pstcTca9539LL->Write(&u8TempData[0], &u8TempData[1], 1U);
+    }
+
+    return i32Ret;
+}
+
+/**
+ * @brief  Configuration TCA9539 pin.
+ * @param  [in] pstcTca9539LL           Pointer to a @ref stc_tca9539_ll_t structure.
+ * @param  [in] u8Port                  Port number.
+ *         This parameter can be one of the following values:
+ *           @arg TCA9539_IO_PORT0
+ *           @arg TCA9539_IO_PORT1
+ * @param  [in] u8Pin                   Pin number.
+ *         This parameter can be one of the following values:
+ *           @arg TCA9539_IO_PIN0
+ *           @arg TCA9539_IO_PIN1
+ *           @arg TCA9539_IO_PIN2
+ *           @arg TCA9539_IO_PIN3
+ *           @arg TCA9539_IO_PIN4
+ *           @arg TCA9539_IO_PIN5
+ *           @arg TCA9539_IO_PIN6
+ *           @arg TCA9539_IO_PIN7
+ *           @arg TCA9539_IO_PIN_ALL:   All of the above
+ * @param  [in] u8Dir                   Pin output direction.
+ *         This parameter can be one of the following values:
+ *           @arg TCA9539_DIR_OUT
+ *           @arg TCA9539_DIR_IN
+ * @retval int32_t:
+ *           - LL_OK: Operation success
+ *           - LL_ERR_INVD_PARAM: Invalid parameter
+ */
+int32_t TCA9539_ConfigPin(const stc_tca9539_ll_t *pstcTca9539LL, uint8_t u8Port, uint8_t u8Pin, uint8_t u8Dir)
+{
+    int32_t i32Ret = LL_OK;
+    uint8_t u8TempData[2];
+
+    if ((pstcTca9539LL == NULL) || (pstcTca9539LL->Read == NULL) || (pstcTca9539LL->Write == NULL)) {
+        i32Ret = LL_ERR_INVD_PARAM;
+    } else {
+        u8TempData[0] = u8Port + TCA9539_REG_CONFIG_PORT0;
+        pstcTca9539LL->Read(&u8TempData[0], &u8TempData[1], 1U);
+        if (TCA9539_DIR_OUT == u8Dir) {
+            u8TempData[1] &= (uint8_t)(~u8Pin);
+        } else {
+            u8TempData[1] |= u8Pin;
+        }
+        pstcTca9539LL->Write(&u8TempData[0], &u8TempData[1], 1U);
+    }
+
+    return i32Ret;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/******************************************************************************
+ * EOF (not truncated)
+ *****************************************************************************/

bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/components/tca9539/tca9539.h

@@ -0,0 +1,193 @@
+/**
+ *******************************************************************************
+ * @file  tca9539.h
+ * @brief This file contains all the functions prototypes of the TCA9539 driver
+ *        library.
+ @verbatim
+   Change Logs:
+   Date             Author          Notes
+   2022-03-31       CDT             First version
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                    opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __TCA9539_H__
+#define __TCA9539_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+/**
+ * @addtogroup BSP
+ * @{
+ */
+
+/**
+ * @addtogroup Components
+ * @{
+ */
+
+/**
+ * @addtogroup TCA9539
+  * @{
+  */
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ * @defgroup TCA9539_Global_Types TCA9539 Global Types
+ * @{
+ */
+
+/**
+ * @brief TCA9539 low layer structure definition
+ */
+typedef struct {
+    /* Methods */
+    void (*Init)(void);
+    void (*Write)(const uint8_t *, const uint8_t *, uint32_t);
+    void (*Read)(const uint8_t *, uint8_t *, uint32_t);
+    void (*Reset)(void);
+    void (*IntInit)(void);
+} stc_tca9539_ll_t;
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup TCA9539_Global_Macros TCA9539 Global Macros
+ * @{
+ */
+
+/**
+ * @defgroup TCA9539_REGISTER_Definition TCA9539 Register Definition
+ * @{
+ */
+#define TCA9539_REG_INPUT_PORT0         (0x00U)
+#define TCA9539_REG_INPUT_PORT1         (0x01U)
+#define TCA9539_REG_OUTPUT_PORT0        (0x02U)
+#define TCA9539_REG_OUTPUT_PORT1        (0x03U)
+#define TCA9539_REG_INVERT_PORT0        (0x04U)
+#define TCA9539_REG_INVERT_PORT1        (0x05U)
+#define TCA9539_REG_CONFIG_PORT0        (0x06U)
+#define TCA9539_REG_CONFIG_PORT1        (0x07U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TCA9539_Port_Definition TCA9539 Port Definition
+ * @{
+ */
+#define TCA9539_IO_PORT0                (0x00U)
+#define TCA9539_IO_PORT1                (0x01U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TCA9539_Pin_Definition TCA9539 Pin Definition
+ * @{
+ */
+#define TCA9539_IO_PIN0                 (0x01U)
+#define TCA9539_IO_PIN1                 (0x02U)
+#define TCA9539_IO_PIN2                 (0x04U)
+#define TCA9539_IO_PIN3                 (0x08U)
+#define TCA9539_IO_PIN4                 (0x10U)
+#define TCA9539_IO_PIN5                 (0x20U)
+#define TCA9539_IO_PIN6                 (0x40U)
+#define TCA9539_IO_PIN7                 (0x80U)
+#define TCA9539_IO_PIN_ALL              (0xFFU)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TCA9539_Direction_Definition TCA9539 Direction Definition
+ * @{
+ */
+#define TCA9539_DIR_OUT                 (0x00U)
+#define TCA9539_DIR_IN                  (0x01U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TCA9539_Pin_State_Definition TCA9539 Pin State Definition
+ * @{
+ */
+#define TCA9539_PIN_RESET               (0x00U)
+#define TCA9539_PIN_SET                 (0x01U)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+  Global function prototypes (definition in C source)
+ ******************************************************************************/
+/**
+ * @defgroup TCA9539_Global_Functions TCA9539 Global Functions
+ * @{
+ */
+int32_t TCA9539_Init(const stc_tca9539_ll_t *pstcTca9539LL);
+int32_t TCA9539_IntInit(const stc_tca9539_ll_t *pstcTca9539LL);
+int32_t TCA9539_Reset(const stc_tca9539_ll_t *pstcTca9539LL);
+
+int32_t TCA9539_WritePin(const stc_tca9539_ll_t *pstcTca9539LL, uint8_t u8Port, uint8_t u8Pin, uint8_t u8PinState);
+int32_t TCA9539_ReadPin(const stc_tca9539_ll_t *pstcTca9539LL, uint8_t u8Port, uint8_t u8Pin, uint8_t *pu8PinState);
+int32_t TCA9539_TogglePin(const stc_tca9539_ll_t *pstcTca9539LL, uint8_t u8Port, uint8_t u8Pin);
+int32_t TCA9539_ConfigPin(const stc_tca9539_ll_t *pstcTca9539LL, uint8_t u8Port, uint8_t u8Pin, uint8_t u8Dir);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TCA9539_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/

bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/components/w25qxx/w25qxx.c

@@ -0,0 +1,596 @@
+/**
+ *******************************************************************************
+ * @file  w25qxx.c
+ * @brief This midware file provides firmware functions to W25QXX group spi flash.
+ @verbatim
+   Change Logs:
+   Date             Author          Notes
+   2022-03-31       CDT             First version
+   2023-12-15       CDT             Add null pointer check
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                    opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "w25qxx.h"
+
+/**
+ * @addtogroup BSP
+ * @{
+ */
+
+/**
+ * @addtogroup Components
+ * @{
+ */
+
+/**
+ * @defgroup W25QXX Flash Driver for W25QXX
+ * @{
+ */
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup W25QXX_Local_Macros W25QXX Local Macros
+ * @{
+ */
+#define W25QXX_FLAG_BUSY            (1UL << 0U)
+#define W25QXX_FLAG_WEL             (1UL << 1U)         /*!< Write Enable Latch */
+#define W25QXX_FLAG_SUSPEND         (1UL << 15U)        /*!< Write Enable Latch */
+
+#define LOAD_CMD(a, cmd, addr)      do {                                    \
+                                        (a)[0U] = (cmd);                    \
+                                        (a)[1U] = (uint8_t)((addr) >> 16U); \
+                                        (a)[2U] = (uint8_t)((addr) >> 8U);  \
+                                        (a)[3U] = (uint8_t)(addr);          \
+                                    } while (0U)
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+/**
+ * @addtogroup W25QXX_Local_Functions W25QXX Local Functions
+ * @{
+ */
+
+/**
+ * @brief  W25QXX write command.
+ * @param  [in]  pstcW25qxxLL           Pointer to a @ref stc_w25qxx_ll_t structure.
+ * @param  [in]  u8Cmd                  Command of W25QXX.
+ * @param  [in]  pu8CmdData             Pointer to a buffer that contains the data following the command.
+ * @param  [in]  u32CmdDataLen          The length of the command data in bytes.
+ * @retval int32_t:
+ *           - LL_OK:                   No error occurred.
+ *           - LL_ERR_TIMEOUT:          SPI timeout.
+ *           - LL_ERR_INVD_PARAM:       Invalid parameter.
+ */
+static int32_t W25QXX_WriteCmd(const stc_w25qxx_ll_t *pstcW25qxxLL, \
+                               uint8_t u8Cmd, const uint8_t *pu8CmdData, uint32_t u32CmdDataLen)
+{
+    int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+    if (pstcW25qxxLL == NULL) {
+        return i32Ret;
+    }
+
+    if ((pstcW25qxxLL->Active != NULL) && (pstcW25qxxLL->Trans != NULL) && (pstcW25qxxLL->Inactive != NULL)) {
+        pstcW25qxxLL->Active();
+        i32Ret = pstcW25qxxLL->Trans(&u8Cmd, 1U);
+        if ((i32Ret == LL_OK) && (pu8CmdData != NULL) && (u32CmdDataLen > 0UL)) {
+            i32Ret = pstcW25qxxLL->Trans(pu8CmdData, u32CmdDataLen);
+        }
+        pstcW25qxxLL->Inactive();
+    }
+
+    return i32Ret;
+}
+
+/**
+ * @brief  W25QXX read command.
+ * @param  [in]  pstcW25qxxLL           Pointer to a @ref stc_w25qxx_ll_t structure.
+ * @param  [in]  u8Cmd                  Command of W25QXX.
+ * @param  [in]  pu8CmdData             Pointer to a buffer that contains the data following the command.
+ * @param  [in]  u32CmdDataLen          The length of the command data in bytes.
+ * @param  [in]  pu8Info                The information of the command.
+ * @param  [in]  u8InfoLen              The length of the information.
+ * @retval int32_t:
+ *           - LL_OK:                   No error occurred.
+ *           - LL_ERR_TIMEOUT:          SPI timeout.
+ *           - LL_ERR_INVD_PARAM:       Invalid parameter.
+ */
+static int32_t W25QXX_ReadCmd(const stc_w25qxx_ll_t *pstcW25qxxLL, \
+                              uint8_t u8Cmd, uint8_t *pu8CmdData, uint32_t u32CmdDataLen,
+                              uint8_t *pu8Info, uint8_t u8InfoLen)
+{
+    int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+    if (pstcW25qxxLL == NULL) {
+        return i32Ret;
+    }
+
+    if ((pstcW25qxxLL->Active != NULL) && (pstcW25qxxLL->Trans != NULL) && (pstcW25qxxLL->Receive != NULL) &&
+        (pstcW25qxxLL->Inactive != NULL)) {
+        pstcW25qxxLL->Active();
+        i32Ret = pstcW25qxxLL->Trans(&u8Cmd, 1U);
+        if ((i32Ret == LL_OK) && (pu8CmdData != NULL) && (u32CmdDataLen > 0UL)) {
+            i32Ret = pstcW25qxxLL->Trans(pu8CmdData, u32CmdDataLen);
+        }
+        if ((i32Ret == LL_OK) && (pu8Info != NULL) && (u8InfoLen > 0UL)) {
+            i32Ret = pstcW25qxxLL->Receive(pu8Info, (uint32_t)u8InfoLen);
+        }
+        pstcW25qxxLL->Inactive();
+    }
+
+    return i32Ret;
+}
+
+/**
+ * @brief  W25QXX write data.
+ * @param  [in]  pstcW25qxxLL           Pointer to a @ref stc_w25qxx_ll_t structure.
+ * @param  [in]  u8Cmd                  Command of W25QXX.
+ * @param  [in]  u32Addr                The start address of the data to be written.
+ * @param  [in]  pu8Data                The data to be written.
+ * @param  [in]  u32DataLen             The length of the data in bytes.
+ * @retval int32_t:
+ *           - LL_OK:                   No error occurred.
+ *           - LL_ERR_TIMEOUT:          SPI timeout.
+ *           - LL_ERR_INVD_PARAM:       Invalid parameter.
+ */
+static int32_t W25QXX_Wt(const stc_w25qxx_ll_t *pstcW25qxxLL, \
+                         uint8_t u8Cmd, uint32_t u32Addr, \
+                         const uint8_t *pu8Data, uint32_t u32DataLen)
+{
+    uint8_t au8Cmd[4U];
+    int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+    if (pstcW25qxxLL == NULL) {
+        return i32Ret;
+    }
+
+    if ((pstcW25qxxLL->Active != NULL) && (pstcW25qxxLL->Trans != NULL) && (pstcW25qxxLL->Inactive != NULL)) {
+        LOAD_CMD(au8Cmd, u8Cmd, u32Addr);
+        pstcW25qxxLL->Active();
+        i32Ret = pstcW25qxxLL->Trans(au8Cmd, 4U);
+        if ((i32Ret == LL_OK) && (pu8Data != NULL) && (u32DataLen > 0UL)) {
+            i32Ret = pstcW25qxxLL->Trans(pu8Data, u32DataLen);
+        }
+        pstcW25qxxLL->Inactive();
+    }
+
+    return i32Ret;
+}
+
+/**
+ * @brief  W25QXX read data.
+ * @param  [in]  pstcW25qxxLL           Pointer to a @ref stc_w25qxx_ll_t structure.
+ * @param  [in]  u8Cmd                  Command of W25QXX.
+ * @param  [in]  u32Addr                The start address of the data to be written.
+ * @param  [in]  pu8Data                The data to be stored.
+ * @param  [in]  u32DataLen             The length of the data in bytes.
+ * @retval int32_t:
+ *           - LL_OK:                   No error occurred.
+ *           - LL_ERR_TIMEOUT:          SPI timeout.
+ *           - LL_ERR_INVD_PARAM:       Invalid parameter.
+ */
+static int32_t W25QXX_Rd(const stc_w25qxx_ll_t *pstcW25qxxLL, \
+                         uint8_t u8Cmd, uint32_t u32Addr, \
+                         uint8_t *pu8Data, uint32_t u32DataLen)
+{
+    uint8_t au8Cmd[4U];
+    int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+    if (pstcW25qxxLL == NULL) {
+        return i32Ret;
+    }
+
+    if ((pstcW25qxxLL->Active != NULL) && (pstcW25qxxLL->Trans != NULL) && (pstcW25qxxLL->Receive != NULL) &&
+        (pstcW25qxxLL->Inactive != NULL)) {
+        LOAD_CMD(au8Cmd, u8Cmd, u32Addr);
+        pstcW25qxxLL->Active();
+        i32Ret = pstcW25qxxLL->Trans(au8Cmd, 4U);
+        if (i32Ret == LL_OK) {
+            i32Ret = pstcW25qxxLL->Receive(pu8Data, u32DataLen);
+        }
+        pstcW25qxxLL->Inactive();
+    }
+
+    return i32Ret;
+}
+
+/**
+ * @brief  W25QXX Write enable.
+ * @param  [in]  pstcW25qxxLL           Pointer to a @ref stc_w25qxx_ll_t structure.
+ * @retval int32_t:
+ *           - LL_OK:                   No error occurred.
+ *           - LL_ERR_TIMEOUT:          SPI timeout.
+ */
+static int32_t W25QXX_WriteEnable(const stc_w25qxx_ll_t *pstcW25qxxLL)
+{
+    return W25QXX_WriteCmd(pstcW25qxxLL, W25QXX_WRITE_ENABLE, NULL, 0U);
+}
+
+/**
+ * @brief  W25QXX Write disable.
+ * @param  [in]  pstcW25qxxLL           Pointer to a @ref stc_w25qxx_ll_t structure.
+ * @retval int32_t:
+ *           - LL_OK:                   No error occurred.
+ *           - LL_ERR_TIMEOUT:          SPI timeout.
+ */
+static int32_t W25QXX_WriteDisable(const stc_w25qxx_ll_t *pstcW25qxxLL)
+{
+    return W25QXX_WriteCmd(pstcW25qxxLL, W25QXX_WRITE_DISABLE, NULL, 0U);
+}
+
+/**
+ * @brief  Wait for processing done.
+ * @param  [in]  pstcW25qxxLL           Pointer to a @ref stc_w25qxx_ll_t structure.
+ * @retval int32_t:
+ *           - LL_OK:                   No error occurred.
+ *           - LL_ERR_TIMEOUT:          SPI timeout or W25QXX timeout.
+ */
+static int32_t W25QXX_WaitProcessDone(const stc_w25qxx_ll_t *pstcW25qxxLL)
+{
+    uint8_t u8Status;
+    int32_t i32Ret = LL_ERR_TIMEOUT;
+    volatile uint32_t u32Timecount = W25QXX_TIMEOUT;
+
+    while (u32Timecount-- != 0UL) {
+        i32Ret = W25QXX_ReadStatus(pstcW25qxxLL, W25QXX_READ_STATUS_REGISTER_1, &u8Status);
+        if ((i32Ret == LL_OK) && ((u8Status & W25QXX_FLAG_BUSY) == 0U)) {
+            break;
+        }
+    }
+
+    return i32Ret;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup W25QXX_Global_Functions W25QXX Global Functions
+ * @{
+ */
+/**
+ * @brief  Initializes W25QXX.
+ * @param  [in]  pstcW25qxxLL           Pointer to a @ref stc_w25qxx_ll_t structure.
+ * @retval int32_t:
+ *           - LL_OK:                   No error occurred.
+ *           - LL_ERR_INVD_PARAM:       Invalid parameter
+ */
+int32_t W25QXX_Init(const stc_w25qxx_ll_t *pstcW25qxxLL)
+{
+    int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+    if ((pstcW25qxxLL != NULL) && (pstcW25qxxLL->Init != NULL)) {
+        pstcW25qxxLL->Init();
+        i32Ret = LL_OK;
+    }
+
+    return i32Ret;
+}
+
+/**
+ * @brief  De-Initialize W25QXX.
+ * @param  [in]  pstcW25qxxLL           Pointer to a @ref stc_w25qxx_ll_t structure.
+ * @retval int32_t:
+ *           - LL_OK:                   No error occurred.
+ *           - LL_ERR_INVD_PARAM:       Invalid parameter
+ */
+int32_t W25QXX_DeInit(const stc_w25qxx_ll_t *pstcW25qxxLL)
+{
+    int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+    if ((pstcW25qxxLL != NULL) && (pstcW25qxxLL->DeInit != NULL)) {
+        pstcW25qxxLL->DeInit();
+        i32Ret = LL_OK;
+    }
+
+    return i32Ret;
+}
+
+/**
+ * @brief  Read manufacturer device ID.
+ * @param  [in]  pstcW25qxxLL           Pointer to a @ref stc_w25qxx_ll_t structure.
+ * @param  [out] pu16ID                 Pointer to an address to store the device ID.
+ * @retval int32_t:
+ *           - LL_OK:                   No error occurred.
+ *           - LL_ERR_INVD_PARAM:       Invalid parameter.
+ *           - LL_ERR_TIMEOUT:          SPI timeout.
+ */
+int32_t W25QXX_GetManDeviceId(const stc_w25qxx_ll_t *pstcW25qxxLL, uint16_t *pu16ID)
+{
+    uint8_t au8TempId[2U];
+    uint8_t au8Dummy[3U] = {0U};
+    uint16_t u16ManID;
+    int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+    if ((pstcW25qxxLL != NULL) && (pu16ID != NULL)) {
+        i32Ret = W25QXX_ReadCmd(pstcW25qxxLL, W25QXX_MANUFACTURER_DEVICE_ID, au8Dummy, 3U, au8TempId, 2U);
+        if (i32Ret == LL_OK) {
+            u16ManID  = (uint16_t)au8TempId[0U] << 8U;
+            u16ManID |= au8TempId[1U];
+            *pu16ID   = u16ManID;
+        }
+    }
+
+    return i32Ret;
+}
+
+/**
+ * @brief  Read unique ID.
+ * @param  [in]  pstcW25qxxLL           Pointer to a @ref stc_w25qxx_ll_t structure.
+ * @param  [out] pu8UniqueId            Pointer to a buffer the 64 bit unique ID to be stored.
+ * @retval int32_t:
+ *           - LL_OK:                   No error occurred.
+ *           - LL_ERR_INVD_PARAM:       Invalid parameter.
+ *           - LL_ERR_TIMEOUT:          SPI timeout.
+ */
+int32_t W25QXX_GetUniqueId(const stc_w25qxx_ll_t *pstcW25qxxLL, uint8_t *pu8UniqueId)
+{
+    uint8_t au8Dummy[4U] = {0U};
+    int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+    if ((pstcW25qxxLL != NULL) && (pu8UniqueId != NULL)) {
+        i32Ret = W25QXX_ReadCmd(pstcW25qxxLL, W25QXX_READ_UNIQUE_ID, au8Dummy, 4U, pu8UniqueId, 8U);
+    }
+
+    return i32Ret;
+}
+
+/**
+ * @brief  Read status register.
+ * @param  [in]  pstcW25qxxLL           Pointer to a @ref stc_w25qxx_ll_t structure.
+ * @param  [in]  u8SrRdCmd              Command of reading status register.
+ *   @arg  W25QXX_READ_STATUS_REGISTER_1: Read status register 1.
+ *   @arg  W25QXX_READ_STATUS_REGISTER_2: Read status register 2.
+ *   @arg  W25QXX_READ_STATUS_REGISTER_3: Read status register 3.
+ * @param  [out] pu8Status              Pointer to an address the status value to be stored.
+ * @retval int32_t:
+ *           - LL_OK:                   No error occurred.
+ *           - LL_ERR_INVD_PARAM:       Invalid parameter.
+ *           - LL_ERR_TIMEOUT:          SPI timeout.
+ */
+int32_t W25QXX_ReadStatus(const stc_w25qxx_ll_t *pstcW25qxxLL, uint8_t u8SrRdCmd, uint8_t *pu8Status)
+{
+    int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+    if ((pstcW25qxxLL != NULL) && (pu8Status != NULL)) {
+        i32Ret = W25QXX_ReadCmd(pstcW25qxxLL, u8SrRdCmd, NULL, 0U, pu8Status, 1U);
+    }
+
+    return i32Ret;
+}
+
+/**
+ * @brief  Write status register.
+ * @param  [in]  pstcW25qxxLL           Pointer to a @ref stc_w25qxx_ll_t structure.
+ * @param  [in]  u8SrWtCmd              Command of writting status register.
+ *   @arg  W25QXX_WRITE_STATUS_REGISTER_1: Write status register 1.
+ *   @arg  W25QXX_WRITE_STATUS_REGISTER_2: Write status register 2.
+ *   @arg  W25QXX_WRITE_STATUS_REGISTER_3: Write status register 3.
+ * @param  [in]  u8Value                8bit value of the specified status register.
+ * @retval int32_t:
+ *           - LL_OK:                   No error occurred.
+ *           - LL_ERR_INVD_PARAM:       Invalid parameter.
+ *           - LL_ERR_TIMEOUT:          SPI timeout.
+ */
+int32_t W25QXX_WriteStatus(const stc_w25qxx_ll_t *pstcW25qxxLL, uint8_t u8SrWtCmd, uint8_t u8Value)
+{
+    int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+    if (pstcW25qxxLL != NULL) {
+        i32Ret = W25QXX_WriteCmd(pstcW25qxxLL, u8SrWtCmd, &u8Value, 1U);
+    }
+
+    return i32Ret;
+}
+
+/**
+ * @brief  Power down.
+ * @param  [in]  pstcW25qxxLL           Pointer to a @ref stc_w25qxx_ll_t structure.
+ * @retval int32_t:
+ *           - LL_OK:                   No error occurred.
+ *           - LL_ERR_INVD_PARAM:       Invalid parameter.
+ *           - LL_ERR_TIMEOUT:          SPI timeout.
+ */
+int32_t W25QXX_PowerDown(const stc_w25qxx_ll_t *pstcW25qxxLL)
+{
+    int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+    if ((pstcW25qxxLL != NULL) && (pstcW25qxxLL->Delay != NULL)) {
+        i32Ret = W25QXX_WriteCmd(pstcW25qxxLL, W25QXX_POWER_DOWN, NULL, 0U);
+        if (i32Ret == LL_OK) {
+            pstcW25qxxLL->Delay(1U);
+        }
+    }
+
+    return i32Ret;
+}
+
+/**
+ * @brief  Release power down.
+ * @param  [in]  pstcW25qxxLL           Pointer to a @ref stc_w25qxx_ll_t structure.
+ * @retval int32_t:
+ *           - LL_OK:                   No error occurred.
+ *           - LL_ERR_INVD_PARAM:       Invalid parameter.
+ *           - LL_ERR_TIMEOUT:          SPI timeout.
+ */
+int32_t W25QXX_ReleasePowerDown(const stc_w25qxx_ll_t *pstcW25qxxLL)
+{
+    int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+    if ((pstcW25qxxLL != NULL) && (pstcW25qxxLL->Delay != NULL)) {
+        i32Ret = W25QXX_WriteCmd(pstcW25qxxLL, W25QXX_RELEASE_POWER_DOWN_ID, NULL, 0U);
+        if (i32Ret == LL_OK) {
+            pstcW25qxxLL->Delay(1U);
+        }
+    }
+
+    return i32Ret;
+}
+
+/**
+ * @brief  Ease chip.
+ * @param  [in]  pstcW25qxxLL           Pointer to a @ref stc_w25qxx_ll_t structure.
+ * @retval int32_t:
+ *           - LL_OK:                   No error occurred.
+ *           - LL_ERR_INVD_PARAM:       Invalid parameter.
+ *           - LL_ERR_TIMEOUT:          SPI timeout or W25QXX timeout.
+ */
+int32_t W25QXX_EraseChip(const stc_w25qxx_ll_t *pstcW25qxxLL)
+{
+    int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+    if (pstcW25qxxLL != NULL) {
+        i32Ret = W25QXX_WriteEnable(pstcW25qxxLL);
+        if (i32Ret == LL_OK) {
+            i32Ret = W25QXX_WaitProcessDone(pstcW25qxxLL);
+        }
+        if (i32Ret == LL_OK) {
+            i32Ret = W25QXX_WriteCmd(pstcW25qxxLL, W25QXX_CHIP_ERASE, NULL, 0U);
+        }
+        if (i32Ret == LL_OK) {
+            i32Ret = W25QXX_WaitProcessDone(pstcW25qxxLL);
+        }
+    }
+
+    return i32Ret;
+}
+
+/**
+ * @brief  Ease sector.
+ * @param  [in]  pstcW25qxxLL           Pointer to a @ref stc_w25qxx_ll_t structure.
+ * @param  [in]  u32Addr                Any address of the specified sector.
+ * @retval int32_t:
+ *           - LL_OK:                   No error occurred.
+ *           - LL_ERR_INVD_PARAM:       Invalid parameter.
+ *           - LL_ERR_TIMEOUT:          SPI timeout or W25QXX timeout.
+ */
+int32_t W25QXX_EraseSector(const stc_w25qxx_ll_t *pstcW25qxxLL, uint32_t u32Addr)
+{
+    int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+    if (pstcW25qxxLL != NULL) {
+        i32Ret = W25QXX_WriteEnable(pstcW25qxxLL);
+        if (i32Ret == LL_OK) {
+            i32Ret = W25QXX_WaitProcessDone(pstcW25qxxLL);
+        }
+        if (i32Ret == LL_OK) {
+            i32Ret = W25QXX_Wt(pstcW25qxxLL, W25QXX_SECTOR_ERASE, u32Addr, NULL, 0U);
+        }
+        if (i32Ret == LL_OK) {
+            i32Ret = W25QXX_WaitProcessDone(pstcW25qxxLL);
+        }
+        if (i32Ret == LL_OK) {
+            i32Ret = W25QXX_WriteDisable(pstcW25qxxLL);
+        }
+    }
+
+    return i32Ret;
+}
+
+/**
+ * @brief  W25QXX read data.
+ * @param  [in]  pstcW25qxxLL           Pointer to a @ref stc_w25qxx_ll_t structure.
+ * @param  [in]  u32Addr                The start address of the data to be read.
+ * @param  [in]  pu8ReadBuf             The pointer to the buffer contains the data to be stored.
+ * @param  [in]  u32NumByteToRead       Buffer size in bytes.
+ * @retval int32_t:
+ *           - LL_OK:                   No error occurred.
+ *           - LL_ERR_INVD_PARAM:       Invalid parameter.
+ *           - LL_ERR_TIMEOUT:          SPI timeout.
+ */
+int32_t W25QXX_ReadData(const stc_w25qxx_ll_t *pstcW25qxxLL, uint32_t u32Addr, \
+                        uint8_t *pu8ReadBuf, uint32_t u32NumByteToRead)
+{
+    int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+    if ((pstcW25qxxLL != NULL) && (pu8ReadBuf != NULL) && (u32NumByteToRead != 0UL)) {
+        i32Ret = W25QXX_Rd(pstcW25qxxLL, W25QXX_READ_DATA, u32Addr, pu8ReadBuf, u32NumByteToRead);
+    }
+
+    return i32Ret;
+}
+
+/**
+ * @brief  W25QXX page program.
+ * @param  [in]  pstcW25qxxLL           Pointer to a @ref stc_w25qxx_ll_t structure.
+ * @param  [in]  u32Addr                Start address of the page.
+ * @param  [in]  pu8Data                Pointer to a buffer that contains the data to be written.
+ * @param  [in]  u32NumByteToProgram    Size of the buffer.
+ * @retval int32_t:
+ *           - LL_OK:                   No error occurred.
+ *           - LL_ERR_INVD_PARAM:       Invalid parameter.
+ *           - LL_ERR_TIMEOUT:          SPI timeout or W25QXX timeout.
+ */
+int32_t W25QXX_PageProgram(const stc_w25qxx_ll_t *pstcW25qxxLL, uint32_t u32Addr, \
+                           const uint8_t *pu8Data, uint32_t u32NumByteToProgram)
+{
+    int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+    if ((pstcW25qxxLL != NULL) && (pu8Data != NULL) && (u32NumByteToProgram != 0UL)) {
+        i32Ret = W25QXX_WriteEnable(pstcW25qxxLL);
+        if (i32Ret == LL_OK) {
+            i32Ret = W25QXX_Wt(pstcW25qxxLL, W25QXX_PAGE_PROGRAM, u32Addr, pu8Data, u32NumByteToProgram);
+        }
+        if (i32Ret == LL_OK) {
+            i32Ret = W25QXX_WaitProcessDone(pstcW25qxxLL);
+        }
+    }
+
+    return i32Ret;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/

bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/components/w25qxx/w25qxx.h

@@ -0,0 +1,199 @@
+/**
+ *******************************************************************************
+ * @file  w25qxx.h
+ * @brief This file provides firmware functions to W25QXX group spi flash.
+ @verbatim
+   Change Logs:
+   Date             Author          Notes
+   2022-03-31       CDT             First version
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                    opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __W25QXX_H__
+#define __W25QXX_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+/**
+ * @addtogroup BSP
+ * @{
+ */
+
+/**
+ * @addtogroup Components
+ * @{
+ */
+
+/**
+ * @addtogroup W25QXX
+ * @{
+ */
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ * @defgroup W25QXX_Global_Types W25QXX Global Types
+ * @{
+ */
+
+/**
+ * @brief W25QXX low layer structure definition
+ */
+typedef struct {
+    void (*Delay)(uint32_t);
+    void (*Init)(void);
+    void (*DeInit)(void);
+    void (*Active)(void);
+    void (*Inactive)(void);
+    int32_t (*Trans)(const uint8_t *, uint32_t);
+    int32_t (*Receive)(uint8_t *, uint32_t);
+} stc_w25qxx_ll_t;
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup W25QXX_Global_Macros W25QXX Global Macros
+ * @{
+ */
+
+/**
+ * @defgroup W25QXX_ID W25QXX ID
+ * @{
+ */
+#define W25Q80                  (0xEF13U)
+#define W25Q16                  (0xEF14U)
+#define W25Q32                  (0xEF15U)
+#define W25Q64                  (0xEF16U)
+#define W25Q128                 (0xEF17U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup W25QXX_Command W25QXX Command
+ * @{
+ */
+#define W25QXX_WRITE_ENABLE                     (0x06U)
+#define W25QXX_VOLATILE_SR_WRITE_ENABLE         (0x50U)
+#define W25QXX_WRITE_DISABLE                    (0x04U)
+#define W25QXX_RELEASE_POWER_DOWN_ID            (0xABU)
+#define W25QXX_MANUFACTURER_DEVICE_ID           (0x90U)
+#define W25QXX_JEDEC_ID                         (0x9FU)
+#define W25QXX_READ_UNIQUE_ID                   (0x4BU)
+#define W25QXX_READ_DATA                        (0x03U)
+#define W25QXX_FAST_READ                        (0x0BU)
+#define W25QXX_PAGE_PROGRAM                     (0x02U)
+#define W25QXX_SECTOR_ERASE                     (0x20U)
+#define W25QXX_BLOCK_ERASE_32KB                 (0x52U)
+#define W25QXX_BLOCK_ERASE_64KB                 (0xD8U)
+#define W25QXX_CHIP_ERASE                       (0xC7U)
+#define W25QXX_READ_STATUS_REGISTER_1           (0x05U)
+#define W25QXX_WRITE_STATUS_REGISTER_1          (0x01U)
+#define W25QXX_READ_STATUS_REGISTER_2           (0x35U)
+#define W25QXX_WRITE_STATUS_REGISTER_2          (0x31U)
+#define W25QXX_READ_STATUS_REGISTER_3           (0x15U)
+#define W25QXX_WRITE_STATUS_REGISTER_3          (0x11U)
+#define W25QXX_READ_SFDP_REGISTER               (0x5AU)
+#define W25QXX_ERASE_SECURITY_REGISTER          (0x44U)
+#define W25QXX_PROGRAM_SECURITY_REGISTER        (0x42U)
+#define W25QXX_READ_SECURITY_REGISTER           (0x48U)
+#define W25QXX_GLOBAL_BLOCK_LOCK                (0x7EU)
+#define W25QXX_GLOBAL_BLOCK_UNLOCK              (0x98U)
+#define W25QXX_READ_BLOCK_LOCK                  (0x3DU)
+#define W25QXX_INDIVIDUAL_BLOCK_LOCK            (0x36U)
+#define W25QXX_INDIVIDUAL_BLOCK_UNLOCK          (0x39U)
+#define W25QXX_ERASE_PROGRAM_SUSPEND            (0x75U)
+#define W25QXX_ERASE_PROGRAM_RESUME             (0x7AU)
+#define W25QXX_POWER_DOWN                       (0xB9U)
+#define W25QXX_ENABLE_RESET                     (0x66U)
+#define W25QXX_RESET_DEVICE                     (0x99U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup W25QXX_Timeout_Value W25QXX Timeout Value
+ * @{
+ */
+#define W25QXX_TIMEOUT                          (100000UL)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+  Global function prototypes (definition in C source)
+ ******************************************************************************/
+/**
+ * @addtogroup W25QXX_Global_Functions W25QXX Global Functions
+ * @{
+ */
+
+int32_t W25QXX_Init(const stc_w25qxx_ll_t *pstcW25qxxLL);
+int32_t W25QXX_DeInit(const stc_w25qxx_ll_t *pstcW25qxxLL);
+int32_t W25QXX_GetManDeviceId(const stc_w25qxx_ll_t *pstcW25qxxLL, uint16_t *pu16ID);
+int32_t W25QXX_GetUniqueId(const stc_w25qxx_ll_t *pstcW25qxxLL, uint8_t *pu8UniqueId);
+int32_t W25QXX_ReadStatus(const stc_w25qxx_ll_t *pstcW25qxxLL, uint8_t u8SrRdCmd, uint8_t *pu8Status);
+int32_t W25QXX_WriteStatus(const stc_w25qxx_ll_t *pstcW25qxxLL, uint8_t u8SrWtCmd, uint8_t u8Value);
+int32_t W25QXX_PowerDown(const stc_w25qxx_ll_t *pstcW25qxxLL);
+int32_t W25QXX_ReleasePowerDown(const stc_w25qxx_ll_t *pstcW25qxxLL);
+int32_t W25QXX_EraseChip(const stc_w25qxx_ll_t *pstcW25qxxLL);
+int32_t W25QXX_EraseSector(const stc_w25qxx_ll_t *pstcW25qxxLL, uint32_t u32Addr);
+int32_t W25QXX_ReadData(const stc_w25qxx_ll_t *pstcW25qxxLL, uint32_t u32Addr, uint8_t *pu8ReadBuf, uint32_t u32NumByteToRead);
+int32_t W25QXX_PageProgram(const stc_w25qxx_ll_t *pstcW25qxxLL, uint32_t u32Addr, const uint8_t *pu8Data, uint32_t u32NumByteToProgram);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __W25QXX_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/