mirror of https://github.com/RT-Thread/rt-thread
[bsp][STM32] Add bsp based on new framework
This commit is contained in:
SummerGift
parent
07fce42479
commit
739b2ba51c
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# STM32 BSP 说明
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STM32 系列 BSP 目前支持情况如下表所示：
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| 文件夹名称 | 开发板名称 |
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| ------------------------- | -------------------------- |
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| stm32f103-atk-nano | 正点原子 F103 NANO 开发板 |
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| stm32f103-fire-arbitrary | 野火 F103 霸道开发板 |
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| stm32f407-atk-explorer | 正点原子 F407 探索者开发板 |
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| stm32f429-atk-apollo | 正点原子 F429 阿波罗开发板 |
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| stm32f429-fire-challenger | 野火 F429 挑战者开发板 |
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Import('RTT_ROOT')
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Import('rtconfig')
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from building import *
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cwd = GetCurrentDir()
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# add the general drivers.
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src = Split("""
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""")
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if GetDepend(['RT_USING_PIN']):
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src += ['drv_gpio.c']
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if GetDepend(['RT_USING_SERIAL']):
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src += ['drv_usart.c']
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if GetDepend(['RT_USING_SPI']):
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src += ['drv_spi.c']
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if GetDepend(['RT_USING_QSPI']):
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src += ['drv_qspi.c']
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if GetDepend(['RT_USING_USB_DEVICE']):
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src += ['drv_usb.c']
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if GetDepend(['RT_USING_SDCARD']):
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src += ['drv_sdcard.c']
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if GetDepend(['RT_USING_I2C', 'RT_USING_I2C_BITOPS']):
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src += ['drv_soft_i2c.c']
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if GetDepend(['RT_USING_WDT']):
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src += ['drv_iwg.c']
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if GetDepend('RT_USING_LWIP'):
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src += ['drv_emac.c']
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src += ['drv_common.c']
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path = [cwd]
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path +=[cwd + '/config']
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group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
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Return('group')
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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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*
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* Change Logs:
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* Date Author Notes
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* 2018-11-06 SummerGift change to new framework
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*/
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#ifndef __SPI_CONFIG_H__
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#define __SPI_CONFIG_H__
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#include <rtthread.h>
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#ifdef BSP_USING_SPI1
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#define SPI1_BUS_CONFIG \
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{ \
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.Instance = SPI1, \
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.bus_name = "spi1", \
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.dma_rx.dma_rcc = RCC_AHBENR_DMA1EN, \
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.dma_tx.dma_rcc = RCC_AHBENR_DMA1EN, \
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.dma_rx.Instance = DMA1_Channel2, \
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.dma_rx.dma_irq = DMA1_Channel2_IRQn, \
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.dma_tx.Instance = DMA1_Channel3, \
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.dma_tx.dma_irq = DMA1_Channel3_IRQn, \
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}
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#define SPI1_DMA_RX_IRQHandler DMA1_Channel2_IRQHandler
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#define SPI1_DMA_TX_IRQHandler DMA1_Channel3_IRQHandler
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#endif
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#ifdef BSP_USING_SPI2
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#define SPI2_BUS_CONFIG \
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{ \
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.Instance = SPI2, \
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.bus_name = "spi2", \
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.dma_rx.dma_rcc = RCC_AHBENR_DMA1EN, \
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.dma_tx.dma_rcc = RCC_AHBENR_DMA1EN, \
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.dma_rx.Instance = DMA1_Channel4, \
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.dma_rx.dma_irq = DMA1_Channel4_IRQn, \
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.dma_tx.Instance = DMA1_Channel5, \
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.dma_tx.dma_irq = DMA1_Channel5_IRQn, \
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}
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#define SPI2_DMA_RX_IRQHandler DMA1_Channel4_IRQHandler
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#define SPI2_DMA_TX_IRQHandler DMA1_Channel5_IRQHandler
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#endif
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#ifdef BSP_USING_SPI3
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#define SPI3_BUS_CONFIG \
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{ \
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.Instance = SPI3, \
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.bus_name = "spi3", \
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.dma_rx.dma_rcc = RCC_AHBENR_DMA2EN, \
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.dma_tx.dma_rcc = RCC_AHBENR_DMA2EN, \
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.dma_rx.Instance = DMA2_Channel1, \
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.dma_rx.dma_irq = DMA2_Channel1_IRQn, \
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.dma_tx.Instance = DMA2_Channel2, \
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.dma_tx.dma_irq = DMA2_Channel2_IRQn, \
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}
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#define SPI3_DMA_RX_IRQHandler DMA2_Channel1_IRQHandler
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#define SPI3_DMA_TX_IRQHandler DMA2_Channel2_IRQHandler
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#endif
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#endif /*__SPI_CONFIG_H__ */
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@ -0,0 +1,86 @@
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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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*
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* Change Logs:
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* Date Author Notes
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* 2018-10-30 BalanceTWK change to new framework
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*/
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#ifndef __UART_CONFIG_H__
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#define __UART_CONFIG_H__
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#include <rtthread.h>
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#if defined(BSP_USING_UART1)
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#define UART1_CONFIG \
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{ \
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.name = "uart1", \
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.Instance = USART1, \
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.irq_type = USART1_IRQn, \
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.dma.channel.Instance = DMA1_Channel5, \
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.dma_rcc = RCC_AHBENR_DMA1EN, \
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.dma_irq = DMA1_Channel5_IRQn, \
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}
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#define USART1_RX_DMA_ISR DMA1_Channel5_IRQHandler
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#endif
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#if defined(BSP_USING_UART2)
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#define UART2_CONFIG \
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{ \
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.name = "uart2", \
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.Instance = USART2, \
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.irq_type = USART2_IRQn, \
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.dma.channel.Instance = DMA1_Channel6, \
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.dma_rcc = RCC_AHBENR_DMA1EN, \
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.dma_irq = DMA1_Channel6_IRQn, \
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}
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#define USART2_RX_DMA_ISR DMA1_Channel6_IRQHandler
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#endif
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#if defined(BSP_USING_UART3)
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#define UART3_CONFIG \
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{ \
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.name = "uart3", \
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.Instance = USART3, \
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.irq_type = USART3_IRQn, \
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.dma.channel.Instance = DMA1_Channel3, \
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.dma_rcc = RCC_AHBENR_DMA1EN, \
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.dma_irq = DMA1_Channel3_IRQn, \
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}
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#define USART3_RX_DMA_ISR DMA1_Channel3_IRQHandler
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#endif
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#if defined(BSP_USING_UART4)
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#define UART4_CONFIG \
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{ \
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.name = "uart4", \
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.Instance = UART4, \
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.irq_type = UART4_IRQn, \
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.dma.channel.Instance = DMA2_Channel3, \
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.dma_rcc = RCC_AHBENR_DMA2EN, \
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.dma_irq = DMA2_Channel3_IRQn, \
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}
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#define USART4_RX_DMA_ISR DMA2_Channel3_IRQHandler
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#endif
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#if defined(BSP_USING_UART5)
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#define UART5_CONFIG \
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{ \
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.name = "uart5", \
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.Instance = UART5, \
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.irq_type = UART5_IRQn, \
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.dma.channel.Instance = DMA_NOT_AVAILABLE, \
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}
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#endif
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#endif
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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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*
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* Change Logs:
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* Date Author Notes
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* 2018-11-06 SummerGift change to new framework
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*/
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#ifndef __SPI_CONFIG_H__
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#define __SPI_CONFIG_H__
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#include <rtthread.h>
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#ifdef BSP_USING_SPI1
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#define SPI1_BUS_CONFIG \
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{ \
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.Instance = SPI1, \
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.bus_name = "spi1", \
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.dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
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.dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
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.dma_rx.Instance = DMA2_Stream2, \
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.dma_rx.channel = DMA_CHANNEL_3, \
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.dma_rx.dma_irq = DMA2_Stream2_IRQn, \
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.dma_tx.Instance = DMA2_Stream3, \
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.dma_tx.channel = DMA_CHANNEL_3, \
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.dma_tx.dma_irq = DMA2_Stream3_IRQn, \
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}
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#define SPI1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler
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#define SPI1_DMA_TX_IRQHandler DMA2_Stream3_IRQHandler
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#endif
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#ifdef BSP_USING_SPI2
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#define SPI2_BUS_CONFIG \
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{ \
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.Instance = SPI2, \
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.bus_name = "spi2", \
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.dma_rx.dma_rx.dma_rcc = RCC_AHB1ENR_DMA1EN, \
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.dma_tx.dma_rx.dma_rcc = RCC_AHB1ENR_DMA1EN, \
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.dma_rx.Instance = DMA1_Stream3, \
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.dma_rx.channel = DMA_CHANNEL_0, \
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.dma_rx.dma_irq = DMA1_Stream3_IRQn, \
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.dma_tx.Instance = DMA1_Stream4, \
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.dma_tx.channel = DMA_CHANNEL_0, \
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.dma_tx.dma_irq = DMA1_Stream4_IRQn, \
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}
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#define SPI2_DMA_RX_IRQHandler DMA1_Stream3_IRQHandler
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#define SPI2_DMA_TX_IRQHandler DMA1_Stream4_IRQHandler
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#endif
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#ifdef BSP_USING_SPI3
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#define SPI3_BUS_CONFIG \
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{ \
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.Instance = SPI3, \
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.bus_name = "spi3", \
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.dma_rx.dma_rcc = RCC_AHB1ENR_DMA1EN, \
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.dma_tx.dma_rcc = RCC_AHB1ENR_DMA1EN, \
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.dma_rx.Instance = DMA1_Stream0, \
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.dma_rx.channel = DMA_CHANNEL_0, \
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.dma_rx.dma_irq = DMA1_Stream0_IRQn, \
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.dma_tx.Instance = DMA1_Stream2, \
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.dma_tx.channel = DMA_CHANNEL_0, \
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.dma_tx.dma_irq = DMA1_Stream2_IRQn, \
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}
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#define SPI3_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler
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#define SPI3_DMA_TX_IRQHandler DMA1_Stream2_IRQHandler
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#endif
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#ifdef BSP_USING_SPI4
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#define SPI4_BUS_CONFIG \
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{ \
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.Instance = SPI4, \
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.bus_name = "spi4", \
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.dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
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.dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
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.dma_rx.Instance = DMA2_Stream0, \
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.dma_rx.channel = DMA_CHANNEL_4, \
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.dma_rx.dma_irq = DMA2_Stream0_IRQn, \
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.dma_tx.Instance = DMA2_Stream1, \
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.dma_tx.channel = DMA_CHANNEL_4, \
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.dma_tx.dma_irq = DMA2_Stream1_IRQn, \
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}
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#define SPI4_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler
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#define SPI4_DMA_TX_IRQHandler DMA2_Stream1_IRQHandler
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#endif
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#ifdef BSP_USING_SPI5
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#define SPI5_BUS_CONFIG \
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{ \
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.Instance = SPI5, \
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.bus_name = "spi5", \
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.dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
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.dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
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.dma_rx.Instance = DMA2_Stream3, \
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.dma_rx.channel = DMA_CHANNEL_2, \
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.dma_rx.dma_irq = DMA2_Stream3_IRQn, \
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.dma_tx.Instance = DMA2_Stream4, \
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.dma_tx.channel = DMA_CHANNEL_2, \
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.dma_tx.dma_irq = DMA2_Stream4_IRQn, \
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}
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#define SPI5_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler
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#define SPI5_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler
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#endif
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#endif /*__SPI_CONFIG_H__ */
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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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*
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* Change Logs:
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* Date Author Notes
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* 2018-10-30 SummerGift change to new framework
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*/
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#ifndef __UART_CONFIG_H__
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#define __UART_CONFIG_H__
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#include <rtthread.h>
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#if defined(BSP_USING_UART1)
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#define UART1_CONFIG \
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{ \
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.name = "uart1", \
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.Instance = USART1, \
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.irq_type = USART1_IRQn, \
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.dma.stream_channel.Instance = DMA2_Stream5, \
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.dma.stream_channel.channel = DMA_CHANNEL_4, \
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.dma_rcc = RCC_AHB1ENR_DMA2EN, \
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.dma_irq = DMA2_Stream5_IRQn, \
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}
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#define USART1_RX_DMA_ISR DMA2_Stream5_IRQHandler
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#endif
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#if defined(BSP_USING_UART2)
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#define UART2_CONFIG \
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{ \
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.name = "uart2", \
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.Instance = USART2, \
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.irq_type = USART2_IRQn, \
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.dma.stream_channel.Instance = DMA1_Stream5, \
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.dma.stream_channel.channel = DMA_CHANNEL_4, \
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.dma_rcc = RCC_AHB1ENR_DMA1EN, \
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||||||
|
.dma_irq = DMA1_Stream5_IRQn, \
|
||||||
|
}
|
||||||
|
|
||||||
|
#define USART2_RX_DMA_ISR DMA1_Stream5_IRQHandler
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(BSP_USING_UART3)
|
||||||
|
#define UART3_CONFIG \
|
||||||
|
{ \
|
||||||
|
.name = "uart3", \
|
||||||
|
.Instance = USART3, \
|
||||||
|
.irq_type = USART3_IRQn, \
|
||||||
|
.dma.stream_channel.Instance = DMA1_Stream1, \
|
||||||
|
.dma.stream_channel.channel = DMA_CHANNEL_4, \
|
||||||
|
.dma_rcc = RCC_AHB1ENR_DMA1EN, \
|
||||||
|
.dma_irq = DMA1_Stream1_IRQn, \
|
||||||
|
}
|
||||||
|
|
||||||
|
#define USART3_RX_DMA_ISR DMA1_Stream1_IRQHandler
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(BSP_USING_UART4)
|
||||||
|
#define UART4_CONFIG \
|
||||||
|
{ \
|
||||||
|
.name = "uart4", \
|
||||||
|
.Instance = UART4, \
|
||||||
|
.irq_type = UART4_IRQn, \
|
||||||
|
.dma.stream_channel.Instance = DMA1_Stream2, \
|
||||||
|
.dma.stream_channel.channel = DMA_CHANNEL_4, \
|
||||||
|
.dma_rcc = RCC_AHB1ENR_DMA1EN, \
|
||||||
|
.dma_irq = DMA1_Stream2_IRQn, \
|
||||||
|
}
|
||||||
|
|
||||||
|
#define USART4_RX_DMA_ISR DMA1_Stream2_IRQHandler
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(BSP_USING_UART5)
|
||||||
|
#define UART5_CONFIG \
|
||||||
|
{ \
|
||||||
|
.name = "uart5", \
|
||||||
|
.Instance = UART5, \
|
||||||
|
.irq_type = UART5_IRQn, \
|
||||||
|
.dma.stream_channel.Instance = DMA1_Stream0, \
|
||||||
|
.dma.stream_channel.channel = DMA_CHANNEL_4, \
|
||||||
|
.dma_rcc = RCC_AHB1ENR_DMA1EN, \
|
||||||
|
.dma_irq = DMA1_Stream0_IRQn, \
|
||||||
|
}
|
||||||
|
|
||||||
|
#define USART5_RX_DMA_ISR DMA1_Stream0_IRQHandler
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,71 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* Change Logs:
|
||||||
|
* Date Author Notes
|
||||||
|
* 2018-11-06 SummerGift change to new framework
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __SPI_CONFIG_H__
|
||||||
|
#define __SPI_CONFIG_H__
|
||||||
|
|
||||||
|
#include <rtthread.h>
|
||||||
|
|
||||||
|
#ifdef BSP_USING_SPI1
|
||||||
|
#define SPI1_BUS_CONFIG \
|
||||||
|
{ \
|
||||||
|
.Instance = SPI1, \
|
||||||
|
.bus_name = "spi1", \
|
||||||
|
.dma_rx.dma_rcc = RCC_AHB1ENR_DMA1EN, \
|
||||||
|
.dma_tx.dma_rcc = RCC_AHB1ENR_DMA1EN, \
|
||||||
|
.dma_rx.Instance = DMA1_Channel2, \
|
||||||
|
.dma_rx.request = DMA_REQUEST_1, \
|
||||||
|
.dma_rx.dma_irq = DMA1_Channel2_IRQn, \
|
||||||
|
.dma_tx.Instance = DMA1_Channel3, \
|
||||||
|
.dma_tx.request = DMA_REQUEST_1, \
|
||||||
|
.dma_tx.dma_irq = DMA1_Channel3_IRQn, \
|
||||||
|
}
|
||||||
|
#define SPI1_DMA_RX_IRQHandler DMA1_Channel2_IRQHandler
|
||||||
|
#define SPI1_DMA_TX_IRQHandler DMA1_Channel3_IRQHandler
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef BSP_USING_SPI2
|
||||||
|
#define SPI2_BUS_CONFIG \
|
||||||
|
{ \
|
||||||
|
.Instance = SPI2, \
|
||||||
|
.bus_name = "spi2", \
|
||||||
|
.dma_rx.dma_rcc = RCC_AHB1ENR_DMA1EN, \
|
||||||
|
.dma_tx.dma_rcc = RCC_AHB1ENR_DMA1EN, \
|
||||||
|
.dma_rx.Instance = DMA1_Channel4, \
|
||||||
|
.dma_rx.request = DMA_REQUEST_1, \
|
||||||
|
.dma_rx.dma_irq = DMA1_Channel4_IRQn, \
|
||||||
|
.dma_tx.Instance = DMA1_Channel5, \
|
||||||
|
.dma_tx.request = DMA_REQUEST_1, \
|
||||||
|
.dma_tx.dma_irq = DMA1_Channel5_IRQn, \
|
||||||
|
}
|
||||||
|
#define SPI2_DMA_RX_IRQHandler DMA1_Channel4_IRQHandler
|
||||||
|
#define SPI2_DMA_TX_IRQHandler DMA1_Channel5_IRQHandler
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef BSP_USING_SPI3
|
||||||
|
#define SPI3_BUS_CONFIG \
|
||||||
|
{ \
|
||||||
|
.Instance = SPI3, \
|
||||||
|
.bus_name = "spi3", \
|
||||||
|
.dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
|
||||||
|
.dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
|
||||||
|
.dma_rx.Instance = DMA2_Channel1, \
|
||||||
|
.dma_rx.request = DMA_REQUEST_3, \
|
||||||
|
.dma_rx.dma_irq = DMA2_Channel1_IRQn, \
|
||||||
|
.dma_tx.Instance = DMA2_Channel2, \
|
||||||
|
.dma_tx.request = DMA_REQUEST_3, \
|
||||||
|
.dma_tx.dma_irq = DMA2_Channel2_IRQn, \
|
||||||
|
}
|
||||||
|
#define SPI3_DMA_RX_IRQHandler DMA2_Channel1_IRQHandler
|
||||||
|
#define SPI3_DMA_TX_IRQHandler DMA2_Channel2_IRQHandler
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /*__SPI_CONFIG_H__ */
|
||||||
|
|
@ -0,0 +1,49 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* Change Logs:
|
||||||
|
* Date Author Notes
|
||||||
|
* 2018-11-06 SummerGift change to new framework
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __UART_CONFIG_H__
|
||||||
|
#define __UART_CONFIG_H__
|
||||||
|
|
||||||
|
#include <rtthread.h>
|
||||||
|
|
||||||
|
#if defined(BSP_USING_UART1)
|
||||||
|
|
||||||
|
#define UART1_CONFIG \
|
||||||
|
{ \
|
||||||
|
.name = "uart1", \
|
||||||
|
.Instance = USART1, \
|
||||||
|
.irq_type = USART1_IRQn, \
|
||||||
|
.dma.channel_request.Instance = DMA2_Channel7, \
|
||||||
|
.dma.channel_request.request = DMA_REQUEST_2, \
|
||||||
|
.dma_rcc = RCC_AHB1ENR_DMA2EN, \
|
||||||
|
.dma_irq = DMA2_Channel7_IRQn, \
|
||||||
|
}
|
||||||
|
|
||||||
|
#define USART1_RX_DMA_ISR DMA2_Channel7_IRQHandler
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(BSP_USING_UART2)
|
||||||
|
|
||||||
|
#define UART2_CONFIG \
|
||||||
|
{ \
|
||||||
|
.name = "uart2", \
|
||||||
|
.Instance = USART2, \
|
||||||
|
.irq_type = USART2_IRQn, \
|
||||||
|
.dma.channel_request.Instance = DMA1_Channel6, \
|
||||||
|
.dma.channel_request.request = DMA_REQUEST_2, \
|
||||||
|
.dma_rcc = RCC_AHB1SMENR_DMA1SMEN, \
|
||||||
|
.dma_irq = DMA1_Channel6_IRQn, \
|
||||||
|
}
|
||||||
|
|
||||||
|
#define USART2_RX_DMA_ISR DMA1_Channel6_IRQHandler
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,134 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* Change Logs:
|
||||||
|
* Date Author Notes
|
||||||
|
* 2018-11-7 SummerGift change to new framework
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "drv_common.h"
|
||||||
|
|
||||||
|
#ifdef RT_USING_PIN
|
||||||
|
#include "drv_gpio.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef RT_USING_SERIAL
|
||||||
|
#include "drv_usart.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef RT_USING_FINSH
|
||||||
|
#include <finsh.h>
|
||||||
|
static void reboot(uint8_t argc, char **argv)
|
||||||
|
{
|
||||||
|
rt_hw_cpu_reset();
|
||||||
|
}
|
||||||
|
FINSH_FUNCTION_EXPORT_ALIAS(reboot, __cmd_reboot, Reboot System);
|
||||||
|
#endif /* RT_USING_FINSH */
|
||||||
|
|
||||||
|
/* SysTick configuration */
|
||||||
|
void rt_hw_systick_init(void)
|
||||||
|
{
|
||||||
|
HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / RT_TICK_PER_SECOND);
|
||||||
|
HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
|
||||||
|
HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* This is the timer interrupt service routine.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void SysTick_Handler(void)
|
||||||
|
{
|
||||||
|
/* enter interrupt */
|
||||||
|
rt_interrupt_enter();
|
||||||
|
|
||||||
|
HAL_IncTick();
|
||||||
|
rt_tick_increase();
|
||||||
|
|
||||||
|
/* leave interrupt */
|
||||||
|
rt_interrupt_leave();
|
||||||
|
}
|
||||||
|
|
||||||
|
uint32_t HAL_GetTick(void)
|
||||||
|
{
|
||||||
|
return rt_tick_get() * 1000 / RT_TICK_PER_SECOND;
|
||||||
|
}
|
||||||
|
|
||||||
|
void HAL_SuspendTick(void)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
void HAL_ResumeTick(void)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
void HAL_Delay(__IO uint32_t Delay)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
/* re-implement tick interface for STM32 HAL */
|
||||||
|
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
||||||
|
{
|
||||||
|
/* Return function status */
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function is executed in case of error occurrence.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void _Error_Handler(char *s, int num)
|
||||||
|
{
|
||||||
|
/* USER CODE BEGIN Error_Handler */
|
||||||
|
/* User can add his own implementation to report the HAL error return state */
|
||||||
|
while(1)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
/* USER CODE END Error_Handler */
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* This function will initial STM32 board.
|
||||||
|
*/
|
||||||
|
RT_WEAK void rt_hw_board_init()
|
||||||
|
{
|
||||||
|
/* HAL_Init() function is called at the beginning of the program */
|
||||||
|
HAL_Init();
|
||||||
|
|
||||||
|
/* System clock initialization */
|
||||||
|
SystemClock_Config();
|
||||||
|
rt_hw_systick_init();
|
||||||
|
|
||||||
|
/* Hardware GPIO initialization */
|
||||||
|
MX_GPIO_Init();
|
||||||
|
|
||||||
|
/* Heap initialization */
|
||||||
|
#if defined(RT_USING_HEAP)
|
||||||
|
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Pin driver initialization is open by default */
|
||||||
|
#ifdef RT_USING_PIN
|
||||||
|
rt_hw_pin_init();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* USART driver initialization is open by default */
|
||||||
|
#ifdef RT_USING_SERIAL
|
||||||
|
rt_hw_usart_init();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Set the shell console output device */
|
||||||
|
#ifdef RT_USING_CONSOLE
|
||||||
|
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Board underlying hardware initialization */
|
||||||
|
#ifdef RT_USING_COMPONENTS_INIT
|
||||||
|
rt_components_board_init();
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
|
@ -0,0 +1,28 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* Change Logs:
|
||||||
|
* Date Author Notes
|
||||||
|
* 2018-11-7 SummerGift change to new framework
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __DRV_COMMON_H__
|
||||||
|
#define __DRV_COMMON_H__
|
||||||
|
|
||||||
|
#include <rtthread.h>
|
||||||
|
#include <rthw.h>
|
||||||
|
#include <rtdevice.h>
|
||||||
|
#include <board.h>
|
||||||
|
|
||||||
|
void _Error_Handler(char *s, int num);
|
||||||
|
|
||||||
|
#ifndef Error_Handler
|
||||||
|
#define Error_Handler() _Error_Handler(__FILE__, __LINE__)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define DMA_NOT_AVAILABLE ((DMA_INSTANCE_TYPE *)0xFFFFFFFFU)
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,29 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* Change Logs:
|
||||||
|
* Date Author Notes
|
||||||
|
* 2018-10-30 SummerGift change to new framework
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __DRV_CONFIG_H__
|
||||||
|
#define __DRV_CONFIG_H__
|
||||||
|
|
||||||
|
#include <board.h>
|
||||||
|
#include <rtthread.h>
|
||||||
|
|
||||||
|
#if defined(SOC_SERIES_STM32F1)
|
||||||
|
#include "f1/uart_config.h"
|
||||||
|
#include "f1/spi_config.h"
|
||||||
|
#elif defined(SOC_SERIES_STM32F4)
|
||||||
|
#include "f4/uart_config.h"
|
||||||
|
#include "f4/spi_config.h"
|
||||||
|
#elif defined(SOC_SERIES_STM32L4)
|
||||||
|
#include "l4/uart_config.h"
|
||||||
|
#include "l4/spi_config.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,41 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* Change Logs:
|
||||||
|
* Date Author Notes
|
||||||
|
* 2018-11-10 SummerGift change to new framework
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __DRV_DMA_H_
|
||||||
|
#define __DRV_DMA_H_
|
||||||
|
|
||||||
|
#include <rtthread.h>
|
||||||
|
#include "rtdevice.h"
|
||||||
|
#include <rthw.h>
|
||||||
|
#include <drv_common.h>
|
||||||
|
|
||||||
|
#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4)
|
||||||
|
#define DMA_INSTANCE_TYPE DMA_Channel_TypeDef
|
||||||
|
#elif defined(SOC_SERIES_STM32F4)
|
||||||
|
#define DMA_INSTANCE_TYPE DMA_Stream_TypeDef
|
||||||
|
#endif /* defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) */
|
||||||
|
|
||||||
|
struct dma_config {
|
||||||
|
DMA_INSTANCE_TYPE *Instance;
|
||||||
|
rt_uint32_t dma_rcc;
|
||||||
|
IRQn_Type dma_irq;
|
||||||
|
|
||||||
|
#if defined(SOC_SERIES_STM32F4)
|
||||||
|
rt_uint32_t channel;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(SOC_SERIES_STM32L4)
|
||||||
|
rt_uint32_t request;
|
||||||
|
#endif
|
||||||
|
};
|
||||||
|
|
||||||
|
|
||||||
|
#endif /*__DRV_DMA_H_ */
|
||||||
|
|
@ -0,0 +1,609 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* Change Logs:
|
||||||
|
* Date Author Notes
|
||||||
|
* 2018-11-19 SummerGift first version
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "board.h"
|
||||||
|
#include "drv_config.h"
|
||||||
|
#include <netif/ethernetif.h>
|
||||||
|
#include "lwipopts.h"
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Emac driver uses CubeMX tool to generate emac and phy's configuration,
|
||||||
|
* the configuration files can be found in CubeMX_Config floder.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* debug option */
|
||||||
|
//#define ETH_RX_DUMP
|
||||||
|
//#define ETH_TX_DUMP
|
||||||
|
//#define DRV_DEBUG
|
||||||
|
#define LOG_TAG "drv.emac"
|
||||||
|
#include <drv_log.h>
|
||||||
|
|
||||||
|
#define MAX_ADDR_LEN 6
|
||||||
|
|
||||||
|
struct rt_stm32_eth
|
||||||
|
{
|
||||||
|
/* inherit from ethernet device */
|
||||||
|
struct eth_device parent;
|
||||||
|
|
||||||
|
/* interface address info. */
|
||||||
|
rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */
|
||||||
|
|
||||||
|
uint32_t ETH_Speed; /*!< @ref ETH_Speed */
|
||||||
|
uint32_t ETH_Mode; /*!< @ref ETH_Duplex_Mode */
|
||||||
|
};
|
||||||
|
|
||||||
|
static ETH_DMADescTypeDef *DMARxDscrTab, *DMATxDscrTab;
|
||||||
|
static rt_uint8_t *Rx_Buff, *Tx_Buff;
|
||||||
|
static rt_bool_t tx_is_waiting = RT_FALSE;
|
||||||
|
static ETH_HandleTypeDef EthHandle;
|
||||||
|
static struct rt_stm32_eth stm32_eth_device;
|
||||||
|
static struct rt_semaphore tx_wait;
|
||||||
|
|
||||||
|
#if defined(ETH_RX_DUMP) || defined(ETH_TX_DUMP)
|
||||||
|
#define __is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ')
|
||||||
|
static void dump_hex(const rt_uint8_t *ptr, rt_size_t buflen)
|
||||||
|
{
|
||||||
|
unsigned char *buf = (unsigned char*)ptr;
|
||||||
|
int i, j;
|
||||||
|
|
||||||
|
for (i = 0; i < buflen; i += 16)
|
||||||
|
{
|
||||||
|
rt_kprintf("%08X: ", i);
|
||||||
|
|
||||||
|
for (j = 0; j < 16; j++)
|
||||||
|
if (i + j < buflen)
|
||||||
|
rt_kprintf("%02X ", buf[i + j]);
|
||||||
|
else
|
||||||
|
rt_kprintf(" ");
|
||||||
|
rt_kprintf(" ");
|
||||||
|
|
||||||
|
for (j = 0; j < 16; j++)
|
||||||
|
if (i + j < buflen)
|
||||||
|
rt_kprintf("%c", __is_print(buf[i + j]) ? buf[i + j] : '.');
|
||||||
|
rt_kprintf("\n");
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
extern void phy_reset(void);
|
||||||
|
/* EMAC initialization function */
|
||||||
|
static rt_err_t rt_stm32_eth_init(rt_device_t dev)
|
||||||
|
{
|
||||||
|
__HAL_RCC_ETH_CLK_ENABLE();
|
||||||
|
|
||||||
|
phy_reset();
|
||||||
|
|
||||||
|
/* ETHERNET Configuration --------------------------------------------------*/
|
||||||
|
EthHandle.Instance = ETH;
|
||||||
|
EthHandle.Init.MACAddr = (rt_uint8_t*)&stm32_eth_device.dev_addr[0];
|
||||||
|
EthHandle.Init.AutoNegotiation = ETH_AUTONEGOTIATION_ENABLE;
|
||||||
|
EthHandle.Init.Speed = ETH_SPEED_100M;
|
||||||
|
EthHandle.Init.DuplexMode = ETH_MODE_FULLDUPLEX;
|
||||||
|
EthHandle.Init.MediaInterface = ETH_MEDIA_INTERFACE_RMII;
|
||||||
|
EthHandle.Init.RxMode = ETH_RXINTERRUPT_MODE;
|
||||||
|
EthHandle.Init.ChecksumMode = ETH_CHECKSUM_BY_SOFTWARE;
|
||||||
|
//EthHandle.Init.ChecksumMode = ETH_CHECKSUM_BY_HARDWARE;
|
||||||
|
EthHandle.Init.PhyAddress = EXTERNAL_PHY_ADDRESS;
|
||||||
|
|
||||||
|
HAL_ETH_DeInit(&EthHandle);
|
||||||
|
|
||||||
|
/* configure ethernet peripheral (GPIOs, clocks, MAC, DMA) */
|
||||||
|
if (HAL_ETH_Init(&EthHandle) == HAL_OK)
|
||||||
|
{
|
||||||
|
LOG_D("emac hardware init sucess");
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
LOG_D("emac hardware init faild");
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Initialize Tx Descriptors list: Chain Mode */
|
||||||
|
HAL_ETH_DMATxDescListInit(&EthHandle, DMATxDscrTab, Tx_Buff, ETH_TXBUFNB);
|
||||||
|
|
||||||
|
/* Initialize Rx Descriptors list: Chain Mode */
|
||||||
|
HAL_ETH_DMARxDescListInit(&EthHandle, DMARxDscrTab, Rx_Buff, ETH_RXBUFNB);
|
||||||
|
|
||||||
|
/* Enable MAC and DMA transmission and reception */
|
||||||
|
if (HAL_ETH_Start(&EthHandle) == HAL_OK)
|
||||||
|
{
|
||||||
|
LOG_D("emac hardware start");
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
LOG_D("emac hardware start faild");
|
||||||
|
}
|
||||||
|
|
||||||
|
/* ETH interrupt Init */
|
||||||
|
HAL_NVIC_SetPriority(ETH_IRQn, 0x07, 0);
|
||||||
|
HAL_NVIC_EnableIRQ(ETH_IRQn);
|
||||||
|
|
||||||
|
return RT_EOK;
|
||||||
|
}
|
||||||
|
|
||||||
|
static rt_err_t rt_stm32_eth_open(rt_device_t dev, rt_uint16_t oflag)
|
||||||
|
{
|
||||||
|
LOG_D("emac open");
|
||||||
|
return RT_EOK;
|
||||||
|
}
|
||||||
|
|
||||||
|
static rt_err_t rt_stm32_eth_close(rt_device_t dev)
|
||||||
|
{
|
||||||
|
LOG_D("emac close");
|
||||||
|
return RT_EOK;
|
||||||
|
}
|
||||||
|
|
||||||
|
static rt_size_t rt_stm32_eth_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
|
||||||
|
{
|
||||||
|
LOG_D("emac read");
|
||||||
|
rt_set_errno(-RT_ENOSYS);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static rt_size_t rt_stm32_eth_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
|
||||||
|
{
|
||||||
|
LOG_D("emac write");
|
||||||
|
rt_set_errno(-RT_ENOSYS);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static rt_err_t rt_stm32_eth_control(rt_device_t dev, int cmd, void *args)
|
||||||
|
{
|
||||||
|
switch(cmd)
|
||||||
|
{
|
||||||
|
case NIOCTL_GADDR:
|
||||||
|
/* get mac address */
|
||||||
|
if(args) rt_memcpy(args, stm32_eth_device.dev_addr, 6);
|
||||||
|
else return -RT_ERROR;
|
||||||
|
break;
|
||||||
|
|
||||||
|
default :
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
return RT_EOK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* ethernet device interface */
|
||||||
|
/* transmit data*/
|
||||||
|
rt_err_t rt_stm32_eth_tx( rt_device_t dev, struct pbuf* p)
|
||||||
|
{
|
||||||
|
rt_err_t ret = RT_ERROR;
|
||||||
|
HAL_StatusTypeDef state;
|
||||||
|
struct pbuf *q;
|
||||||
|
uint8_t *buffer = (uint8_t *)(EthHandle.TxDesc->Buffer1Addr);
|
||||||
|
__IO ETH_DMADescTypeDef *DmaTxDesc;
|
||||||
|
uint32_t framelength = 0;
|
||||||
|
uint32_t bufferoffset = 0;
|
||||||
|
uint32_t byteslefttocopy = 0;
|
||||||
|
uint32_t payloadoffset = 0;
|
||||||
|
|
||||||
|
DmaTxDesc = EthHandle.TxDesc;
|
||||||
|
bufferoffset = 0;
|
||||||
|
|
||||||
|
/* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
|
||||||
|
while ((DmaTxDesc->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
|
||||||
|
{
|
||||||
|
rt_err_t result;
|
||||||
|
rt_uint32_t level;
|
||||||
|
|
||||||
|
level = rt_hw_interrupt_disable();
|
||||||
|
tx_is_waiting = RT_TRUE;
|
||||||
|
rt_hw_interrupt_enable(level);
|
||||||
|
|
||||||
|
/* it's own bit set, wait it */
|
||||||
|
result = rt_sem_take(&tx_wait, RT_WAITING_FOREVER);
|
||||||
|
if (result == RT_EOK) break;
|
||||||
|
if (result == -RT_ERROR) return -RT_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* copy frame from pbufs to driver buffers */
|
||||||
|
for(q = p; q != NULL; q = q->next)
|
||||||
|
{
|
||||||
|
/* Is this buffer available? If not, goto error */
|
||||||
|
if((DmaTxDesc->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
|
||||||
|
{
|
||||||
|
LOG_D("buffer not valid");
|
||||||
|
ret = ERR_USE;
|
||||||
|
goto error;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Get bytes in current lwIP buffer */
|
||||||
|
byteslefttocopy = q->len;
|
||||||
|
payloadoffset = 0;
|
||||||
|
|
||||||
|
/* Check if the length of data to copy is bigger than Tx buffer size*/
|
||||||
|
while( (byteslefttocopy + bufferoffset) > ETH_TX_BUF_SIZE )
|
||||||
|
{
|
||||||
|
/* Copy data to Tx buffer*/
|
||||||
|
memcpy( (uint8_t*)((uint8_t*)buffer + bufferoffset), (uint8_t*)((uint8_t*)q->payload + payloadoffset), (ETH_TX_BUF_SIZE - bufferoffset) );
|
||||||
|
|
||||||
|
/* Point to next descriptor */
|
||||||
|
DmaTxDesc = (ETH_DMADescTypeDef *)(DmaTxDesc->Buffer2NextDescAddr);
|
||||||
|
|
||||||
|
/* Check if the buffer is available */
|
||||||
|
if((DmaTxDesc->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
|
||||||
|
{
|
||||||
|
LOG_D("dma tx desc buffer is not valid");
|
||||||
|
ret = ERR_USE;
|
||||||
|
goto error;
|
||||||
|
}
|
||||||
|
|
||||||
|
buffer = (uint8_t *)(DmaTxDesc->Buffer1Addr);
|
||||||
|
|
||||||
|
byteslefttocopy = byteslefttocopy - (ETH_TX_BUF_SIZE - bufferoffset);
|
||||||
|
payloadoffset = payloadoffset + (ETH_TX_BUF_SIZE - bufferoffset);
|
||||||
|
framelength = framelength + (ETH_TX_BUF_SIZE - bufferoffset);
|
||||||
|
bufferoffset = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Copy the remaining bytes */
|
||||||
|
memcpy( (uint8_t*)((uint8_t*)buffer + bufferoffset), (uint8_t*)((uint8_t*)q->payload + payloadoffset), byteslefttocopy );
|
||||||
|
bufferoffset = bufferoffset + byteslefttocopy;
|
||||||
|
framelength = framelength + byteslefttocopy;
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef ETH_TX_DUMP
|
||||||
|
dump_hex(buffer, p->tot_len);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Prepare transmit descriptors to give to DMA */
|
||||||
|
/* TODO Optimize data send speed*/
|
||||||
|
LOG_D("transmit frame lenth :%d", framelength);
|
||||||
|
rt_thread_mdelay(1);
|
||||||
|
|
||||||
|
state = HAL_ETH_TransmitFrame(&EthHandle, framelength);
|
||||||
|
if (state != HAL_OK)
|
||||||
|
{
|
||||||
|
LOG_D("eth transmit frame faild: %d", state);
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = ERR_OK;
|
||||||
|
|
||||||
|
error:
|
||||||
|
|
||||||
|
/* When Transmit Underflow flag is set, clear it and issue a Transmit Poll Demand to resume transmission */
|
||||||
|
if ((EthHandle.Instance->DMASR & ETH_DMASR_TUS) != (uint32_t)RESET)
|
||||||
|
{
|
||||||
|
/* Clear TUS ETHERNET DMA flag */
|
||||||
|
EthHandle.Instance->DMASR = ETH_DMASR_TUS;
|
||||||
|
|
||||||
|
/* Resume DMA transmission*/
|
||||||
|
EthHandle.Instance->DMATPDR = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* receive data*/
|
||||||
|
struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
|
||||||
|
{
|
||||||
|
|
||||||
|
struct pbuf *p = NULL;
|
||||||
|
struct pbuf *q = NULL;
|
||||||
|
HAL_StatusTypeDef state;
|
||||||
|
uint16_t len = 0;
|
||||||
|
uint8_t *buffer;
|
||||||
|
__IO ETH_DMADescTypeDef *dmarxdesc;
|
||||||
|
uint32_t bufferoffset = 0;
|
||||||
|
uint32_t payloadoffset = 0;
|
||||||
|
uint32_t byteslefttocopy = 0;
|
||||||
|
uint32_t i = 0;
|
||||||
|
|
||||||
|
/* Get received frame */
|
||||||
|
state = HAL_ETH_GetReceivedFrame_IT(&EthHandle);
|
||||||
|
if (state != HAL_OK)
|
||||||
|
{
|
||||||
|
LOG_D("receive frame faild");
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Obtain the size of the packet and put it into the "len" variable. */
|
||||||
|
len = EthHandle.RxFrameInfos.length;
|
||||||
|
buffer = (uint8_t *)EthHandle.RxFrameInfos.buffer;
|
||||||
|
|
||||||
|
LOG_D("receive frame len : %d", len);
|
||||||
|
|
||||||
|
if (len > 0)
|
||||||
|
{
|
||||||
|
/* We allocate a pbuf chain of pbufs from the Lwip buffer pool */
|
||||||
|
p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef ETH_RX_DUMP
|
||||||
|
dump_hex(buffer, p->tot_len);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
if (p != NULL)
|
||||||
|
{
|
||||||
|
dmarxdesc = EthHandle.RxFrameInfos.FSRxDesc;
|
||||||
|
bufferoffset = 0;
|
||||||
|
for(q = p; q != NULL; q = q->next)
|
||||||
|
{
|
||||||
|
byteslefttocopy = q->len;
|
||||||
|
payloadoffset = 0;
|
||||||
|
|
||||||
|
/* Check if the length of bytes to copy in current pbuf is bigger than Rx buffer size*/
|
||||||
|
while( (byteslefttocopy + bufferoffset) > ETH_RX_BUF_SIZE )
|
||||||
|
{
|
||||||
|
/* Copy data to pbuf */
|
||||||
|
memcpy( (uint8_t*)((uint8_t*)q->payload + payloadoffset), (uint8_t*)((uint8_t*)buffer + bufferoffset), (ETH_RX_BUF_SIZE - bufferoffset));
|
||||||
|
|
||||||
|
/* Point to next descriptor */
|
||||||
|
dmarxdesc = (ETH_DMADescTypeDef *)(dmarxdesc->Buffer2NextDescAddr);
|
||||||
|
buffer = (uint8_t *)(dmarxdesc->Buffer1Addr);
|
||||||
|
|
||||||
|
byteslefttocopy = byteslefttocopy - (ETH_RX_BUF_SIZE - bufferoffset);
|
||||||
|
payloadoffset = payloadoffset + (ETH_RX_BUF_SIZE - bufferoffset);
|
||||||
|
bufferoffset = 0;
|
||||||
|
}
|
||||||
|
/* Copy remaining data in pbuf */
|
||||||
|
memcpy( (uint8_t*)((uint8_t*)q->payload + payloadoffset), (uint8_t*)((uint8_t*)buffer + bufferoffset), byteslefttocopy);
|
||||||
|
bufferoffset = bufferoffset + byteslefttocopy;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Release descriptors to DMA */
|
||||||
|
/* Point to first descriptor */
|
||||||
|
dmarxdesc = EthHandle.RxFrameInfos.FSRxDesc;
|
||||||
|
/* Set Own bit in Rx descriptors: gives the buffers back to DMA */
|
||||||
|
for (i = 0; i < EthHandle.RxFrameInfos.SegCount; i++)
|
||||||
|
{
|
||||||
|
dmarxdesc->Status |= ETH_DMARXDESC_OWN;
|
||||||
|
dmarxdesc = (ETH_DMADescTypeDef *)(dmarxdesc->Buffer2NextDescAddr);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Clear Segment_Count */
|
||||||
|
EthHandle.RxFrameInfos.SegCount = 0;
|
||||||
|
|
||||||
|
/* When Rx Buffer unavailable flag is set: clear it and resume reception */
|
||||||
|
if ((EthHandle.Instance->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET)
|
||||||
|
{
|
||||||
|
/* Clear RBUS ETHERNET DMA flag */
|
||||||
|
EthHandle.Instance->DMASR = ETH_DMASR_RBUS;
|
||||||
|
/* Resume DMA reception */
|
||||||
|
EthHandle.Instance->DMARPDR = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
return p;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* interrupt service routine */
|
||||||
|
void ETH_IRQHandler(void)
|
||||||
|
{
|
||||||
|
/* enter interrupt */
|
||||||
|
rt_interrupt_enter();
|
||||||
|
|
||||||
|
HAL_ETH_IRQHandler(&EthHandle);
|
||||||
|
|
||||||
|
/* leave interrupt */
|
||||||
|
rt_interrupt_leave();
|
||||||
|
}
|
||||||
|
|
||||||
|
void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
|
||||||
|
{
|
||||||
|
if (tx_is_waiting == RT_TRUE)
|
||||||
|
{
|
||||||
|
tx_is_waiting = RT_FALSE;
|
||||||
|
rt_sem_release(&tx_wait);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
|
||||||
|
{
|
||||||
|
rt_err_t result;
|
||||||
|
result = eth_device_ready(&(stm32_eth_device.parent));
|
||||||
|
if( result != RT_EOK )
|
||||||
|
LOG_D("RX err = %d", result );
|
||||||
|
}
|
||||||
|
|
||||||
|
void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
|
||||||
|
{
|
||||||
|
LOG_D("eth err");
|
||||||
|
}
|
||||||
|
|
||||||
|
/* PHY: LAN8720 */
|
||||||
|
static uint8_t phy_speed = 0;
|
||||||
|
#define PHY_LINK_MASK (1<<0)
|
||||||
|
#define PHY_100M_MASK (1<<1)
|
||||||
|
#define PHY_DUPLEX_MASK (1<<2)
|
||||||
|
static void phy_monitor_thread_entry(void *parameter)
|
||||||
|
{
|
||||||
|
uint8_t phy_addr = 0xFF;
|
||||||
|
uint8_t phy_speed_new = 0;
|
||||||
|
|
||||||
|
/* phy search */
|
||||||
|
rt_uint32_t i, temp;
|
||||||
|
for(i=0; i<=0x1F; i++)
|
||||||
|
{
|
||||||
|
HAL_ETH_ReadPHYRegister(&EthHandle, 0x02, (uint32_t *)&temp);
|
||||||
|
|
||||||
|
if( temp != 0xFFFF )
|
||||||
|
{
|
||||||
|
phy_addr = i;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if(phy_addr == 0xFF)
|
||||||
|
{
|
||||||
|
LOG_D("phy not probe!\r\n");
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
LOG_D("found a phy, address:0x%02X\r\n", phy_addr);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* RESET PHY */
|
||||||
|
LOG_D("RESET PHY!");
|
||||||
|
HAL_ETH_WritePHYRegister(&EthHandle, PHY_BCR, PHY_RESET);
|
||||||
|
rt_thread_delay(RT_TICK_PER_SECOND * 2);
|
||||||
|
HAL_ETH_WritePHYRegister(&EthHandle, PHY_BCR, PHY_AUTONEGOTIATION);
|
||||||
|
|
||||||
|
while(1)
|
||||||
|
{
|
||||||
|
rt_uint32_t status;
|
||||||
|
HAL_ETH_ReadPHYRegister(&EthHandle, PHY_BSR, (uint32_t *)&status);
|
||||||
|
LOG_D("LAN8720 status:0x%04X\r\n", status);
|
||||||
|
|
||||||
|
phy_speed_new = 0;
|
||||||
|
|
||||||
|
if(status & (PHY_AUTONEGO_COMPLETE | PHY_LINKED_STATUS))
|
||||||
|
{
|
||||||
|
rt_uint32_t SR;
|
||||||
|
|
||||||
|
SR = HAL_ETH_ReadPHYRegister(&EthHandle, 31, (uint32_t *)&SR);
|
||||||
|
LOG_D("LAN8720 REG 31:0x%04X ", SR);
|
||||||
|
|
||||||
|
SR = (SR >> 2) & 0x07; /* LAN8720, REG31[4:2], Speed Indication. */
|
||||||
|
phy_speed_new = PHY_LINK_MASK;
|
||||||
|
|
||||||
|
if((SR & 0x03) == 2)
|
||||||
|
{
|
||||||
|
phy_speed_new |= PHY_100M_MASK;
|
||||||
|
}
|
||||||
|
|
||||||
|
if(SR & 0x04)
|
||||||
|
{
|
||||||
|
phy_speed_new |= PHY_DUPLEX_MASK;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* linkchange */
|
||||||
|
if(phy_speed_new != phy_speed)
|
||||||
|
{
|
||||||
|
if(phy_speed_new & PHY_LINK_MASK)
|
||||||
|
{
|
||||||
|
LOG_D("link up ");
|
||||||
|
|
||||||
|
if(phy_speed_new & PHY_100M_MASK)
|
||||||
|
{
|
||||||
|
LOG_D("100Mbps");
|
||||||
|
stm32_eth_device.ETH_Speed = ETH_SPEED_100M;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
stm32_eth_device.ETH_Speed = ETH_SPEED_10M;
|
||||||
|
LOG_D("10Mbps");
|
||||||
|
}
|
||||||
|
|
||||||
|
if(phy_speed_new & PHY_DUPLEX_MASK)
|
||||||
|
{
|
||||||
|
LOG_D("full-duplex");
|
||||||
|
stm32_eth_device.ETH_Mode = ETH_MODE_FULLDUPLEX;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
LOG_D("half-duplex");
|
||||||
|
stm32_eth_device.ETH_Mode = ETH_MODE_HALFDUPLEX;
|
||||||
|
}
|
||||||
|
rt_stm32_eth_init((rt_device_t)&stm32_eth_device);
|
||||||
|
|
||||||
|
/* send link up. */
|
||||||
|
eth_device_linkchange(&stm32_eth_device.parent, RT_TRUE);
|
||||||
|
} /* link up. */
|
||||||
|
else
|
||||||
|
{
|
||||||
|
LOG_D("link down\r\n");
|
||||||
|
/* send link down. */
|
||||||
|
eth_device_linkchange(&stm32_eth_device.parent, RT_FALSE);
|
||||||
|
}
|
||||||
|
phy_speed = phy_speed_new;
|
||||||
|
}
|
||||||
|
|
||||||
|
rt_thread_delay(RT_TICK_PER_SECOND);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Register the EMAC device */
|
||||||
|
static int rt_hw_stm32_eth_init(void)
|
||||||
|
{
|
||||||
|
/* Prepare receive and send buffers */
|
||||||
|
Rx_Buff = (rt_uint8_t *)rt_calloc(ETH_RXBUFNB, ETH_MAX_PACKET_SIZE);
|
||||||
|
if (Rx_Buff == RT_NULL)
|
||||||
|
{
|
||||||
|
LOG_E("No memory");
|
||||||
|
}
|
||||||
|
|
||||||
|
Tx_Buff = (rt_uint8_t *)rt_calloc(ETH_TXBUFNB, ETH_MAX_PACKET_SIZE);
|
||||||
|
if (Rx_Buff == RT_NULL)
|
||||||
|
{
|
||||||
|
LOG_E("No memory");
|
||||||
|
}
|
||||||
|
|
||||||
|
DMARxDscrTab = (ETH_DMADescTypeDef * )rt_calloc(ETH_RXBUFNB, sizeof(ETH_DMADescTypeDef));
|
||||||
|
if (DMARxDscrTab == RT_NULL)
|
||||||
|
{
|
||||||
|
LOG_E("No memory");
|
||||||
|
}
|
||||||
|
|
||||||
|
DMATxDscrTab = (ETH_DMADescTypeDef * )rt_calloc(ETH_TXBUFNB, sizeof(ETH_DMADescTypeDef));
|
||||||
|
if (DMATxDscrTab == RT_NULL)
|
||||||
|
{
|
||||||
|
LOG_E("No memory");
|
||||||
|
}
|
||||||
|
|
||||||
|
rt_err_t state;
|
||||||
|
|
||||||
|
stm32_eth_device.ETH_Speed = ETH_SPEED_100M;
|
||||||
|
stm32_eth_device.ETH_Mode = ETH_MODE_FULLDUPLEX;
|
||||||
|
|
||||||
|
/* OUI 00-80-E1 STMICROELECTRONICS. */
|
||||||
|
stm32_eth_device.dev_addr[0] = 0x00;
|
||||||
|
stm32_eth_device.dev_addr[1] = 0x80;
|
||||||
|
stm32_eth_device.dev_addr[2] = 0xE1;
|
||||||
|
/* generate MAC addr from 96bit unique ID (only for test). */
|
||||||
|
stm32_eth_device.dev_addr[3] = *(rt_uint8_t*)(UID_BASE + 4);
|
||||||
|
stm32_eth_device.dev_addr[4] = *(rt_uint8_t*)(UID_BASE + 2);
|
||||||
|
stm32_eth_device.dev_addr[5] = *(rt_uint8_t*)(UID_BASE + 0);
|
||||||
|
|
||||||
|
stm32_eth_device.parent.parent.init = rt_stm32_eth_init;
|
||||||
|
stm32_eth_device.parent.parent.open = rt_stm32_eth_open;
|
||||||
|
stm32_eth_device.parent.parent.close = rt_stm32_eth_close;
|
||||||
|
stm32_eth_device.parent.parent.read = rt_stm32_eth_read;
|
||||||
|
stm32_eth_device.parent.parent.write = rt_stm32_eth_write;
|
||||||
|
stm32_eth_device.parent.parent.control = rt_stm32_eth_control;
|
||||||
|
stm32_eth_device.parent.parent.user_data = RT_NULL;
|
||||||
|
|
||||||
|
stm32_eth_device.parent.eth_rx = rt_stm32_eth_rx;
|
||||||
|
stm32_eth_device.parent.eth_tx = rt_stm32_eth_tx;
|
||||||
|
|
||||||
|
/* init tx semaphore */
|
||||||
|
rt_sem_init(&tx_wait, "tx_wait", 0, RT_IPC_FLAG_FIFO);
|
||||||
|
LOG_D("initialize tx wait semaphore");
|
||||||
|
|
||||||
|
/* register eth device */
|
||||||
|
state = eth_device_init(&(stm32_eth_device.parent), "e0");
|
||||||
|
if (RT_EOK == state)
|
||||||
|
{
|
||||||
|
LOG_D("emac device init success");
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
LOG_D("emac device init faild: %d", state);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* start phy monitor */
|
||||||
|
rt_thread_t tid;
|
||||||
|
tid = rt_thread_create("phy",
|
||||||
|
phy_monitor_thread_entry,
|
||||||
|
RT_NULL,
|
||||||
|
1024,
|
||||||
|
RT_THREAD_PRIORITY_MAX - 2,
|
||||||
|
2);
|
||||||
|
if (tid != RT_NULL)
|
||||||
|
{
|
||||||
|
rt_thread_startup(tid);
|
||||||
|
}
|
||||||
|
|
||||||
|
return state;
|
||||||
|
}
|
||||||
|
INIT_APP_EXPORT(rt_hw_stm32_eth_init);
|
||||||
|
|
@ -0,0 +1,655 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* Change Logs:
|
||||||
|
* Date Author Notes
|
||||||
|
* 2018-11-06 balanceTWK change to new framework
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <board.h>
|
||||||
|
#include "drv_gpio.h"
|
||||||
|
|
||||||
|
#ifdef RT_USING_PIN
|
||||||
|
|
||||||
|
static const struct pin_index pins[] =
|
||||||
|
{
|
||||||
|
#ifdef GPIOA
|
||||||
|
__STM32_PIN(0 , A, 0 ),
|
||||||
|
__STM32_PIN(1 , A, 1 ),
|
||||||
|
__STM32_PIN(2 , A, 2 ),
|
||||||
|
__STM32_PIN(3 , A, 3 ),
|
||||||
|
__STM32_PIN(4 , A, 4 ),
|
||||||
|
__STM32_PIN(5 , A, 5 ),
|
||||||
|
__STM32_PIN(6 , A, 6 ),
|
||||||
|
__STM32_PIN(7 , A, 7 ),
|
||||||
|
__STM32_PIN(8 , A, 8 ),
|
||||||
|
__STM32_PIN(9 , A, 9 ),
|
||||||
|
__STM32_PIN(10, A, 10),
|
||||||
|
__STM32_PIN(11, A, 11),
|
||||||
|
__STM32_PIN(12, A, 12),
|
||||||
|
__STM32_PIN(13, A, 13),
|
||||||
|
__STM32_PIN(14, A, 14),
|
||||||
|
__STM32_PIN(15, A, 15),
|
||||||
|
#endif
|
||||||
|
#ifdef GPIOB
|
||||||
|
__STM32_PIN(16, B, 0),
|
||||||
|
__STM32_PIN(17, B, 1),
|
||||||
|
__STM32_PIN(18, B, 2),
|
||||||
|
__STM32_PIN(19, B, 3),
|
||||||
|
__STM32_PIN(20, B, 4),
|
||||||
|
__STM32_PIN(21, B, 5),
|
||||||
|
__STM32_PIN(22, B, 6),
|
||||||
|
__STM32_PIN(23, B, 7),
|
||||||
|
__STM32_PIN(24, B, 8),
|
||||||
|
__STM32_PIN(25, B, 9),
|
||||||
|
__STM32_PIN(26, B, 10),
|
||||||
|
__STM32_PIN(27, B, 11),
|
||||||
|
__STM32_PIN(28, B, 12),
|
||||||
|
__STM32_PIN(29, B, 13),
|
||||||
|
__STM32_PIN(30, B, 14),
|
||||||
|
__STM32_PIN(31, B, 15),
|
||||||
|
#endif
|
||||||
|
#ifdef GPIOC
|
||||||
|
__STM32_PIN(32, C, 0),
|
||||||
|
__STM32_PIN(33, C, 1),
|
||||||
|
__STM32_PIN(34, C, 2),
|
||||||
|
__STM32_PIN(35, C, 3),
|
||||||
|
__STM32_PIN(36, C, 4),
|
||||||
|
__STM32_PIN(37, C, 5),
|
||||||
|
__STM32_PIN(38, C, 6),
|
||||||
|
__STM32_PIN(39, C, 7),
|
||||||
|
__STM32_PIN(40, C, 8),
|
||||||
|
__STM32_PIN(41, C, 9),
|
||||||
|
__STM32_PIN(42, C, 10),
|
||||||
|
__STM32_PIN(43, C, 11),
|
||||||
|
__STM32_PIN(44, C, 12),
|
||||||
|
__STM32_PIN(45, C, 13),
|
||||||
|
__STM32_PIN(46, C, 14),
|
||||||
|
__STM32_PIN(47, C, 15),
|
||||||
|
#endif
|
||||||
|
#ifdef GPIOD
|
||||||
|
__STM32_PIN(48, D, 0),
|
||||||
|
__STM32_PIN(49, D, 1),
|
||||||
|
__STM32_PIN(50, D, 2),
|
||||||
|
__STM32_PIN(51, D, 3),
|
||||||
|
__STM32_PIN(52, D, 4),
|
||||||
|
__STM32_PIN(53, D, 5),
|
||||||
|
__STM32_PIN(54, D, 6),
|
||||||
|
__STM32_PIN(55, D, 7),
|
||||||
|
__STM32_PIN(56, D, 8),
|
||||||
|
__STM32_PIN(57, D, 9),
|
||||||
|
__STM32_PIN(58, D, 10),
|
||||||
|
__STM32_PIN(59, D, 11),
|
||||||
|
__STM32_PIN(60, D, 12),
|
||||||
|
__STM32_PIN(61, D, 13),
|
||||||
|
__STM32_PIN(62, D, 14),
|
||||||
|
__STM32_PIN(63, D, 15),
|
||||||
|
#endif
|
||||||
|
#ifdef GPIOE
|
||||||
|
__STM32_PIN(64, E, 0),
|
||||||
|
__STM32_PIN(65, E, 1),
|
||||||
|
__STM32_PIN(66, E, 2),
|
||||||
|
__STM32_PIN(67, E, 3),
|
||||||
|
__STM32_PIN(68, E, 4),
|
||||||
|
__STM32_PIN(69, E, 5),
|
||||||
|
__STM32_PIN(70, E, 6),
|
||||||
|
__STM32_PIN(71, E, 7),
|
||||||
|
__STM32_PIN(72, E, 8),
|
||||||
|
__STM32_PIN(73, E, 9),
|
||||||
|
__STM32_PIN(74, E, 10),
|
||||||
|
__STM32_PIN(75, E, 11),
|
||||||
|
__STM32_PIN(76, E, 12),
|
||||||
|
__STM32_PIN(77, E, 13),
|
||||||
|
__STM32_PIN(78, E, 14),
|
||||||
|
__STM32_PIN(79, E, 15),
|
||||||
|
#endif
|
||||||
|
#ifdef GPIOF
|
||||||
|
__STM32_PIN(80, F, 0),
|
||||||
|
__STM32_PIN(81, F, 1),
|
||||||
|
__STM32_PIN(82, F, 2),
|
||||||
|
__STM32_PIN(83, F, 3),
|
||||||
|
__STM32_PIN(84, F, 4),
|
||||||
|
__STM32_PIN(85, F, 5),
|
||||||
|
__STM32_PIN(86, F, 6),
|
||||||
|
__STM32_PIN(87, F, 7),
|
||||||
|
__STM32_PIN(88, F, 8),
|
||||||
|
__STM32_PIN(89, F, 9),
|
||||||
|
__STM32_PIN(90, F, 10),
|
||||||
|
__STM32_PIN(91, F, 11),
|
||||||
|
__STM32_PIN(92, F, 12),
|
||||||
|
__STM32_PIN(93, F, 13),
|
||||||
|
__STM32_PIN(94, F, 14),
|
||||||
|
__STM32_PIN(95, F, 15),
|
||||||
|
#endif
|
||||||
|
#ifdef GPIOG
|
||||||
|
__STM32_PIN(96, G, 0),
|
||||||
|
__STM32_PIN(97, G, 1),
|
||||||
|
__STM32_PIN(98, G, 2),
|
||||||
|
__STM32_PIN(99, G, 3),
|
||||||
|
__STM32_PIN(100, G, 4),
|
||||||
|
__STM32_PIN(101, G, 5),
|
||||||
|
__STM32_PIN(102, G, 6),
|
||||||
|
__STM32_PIN(103, G, 7),
|
||||||
|
__STM32_PIN(104, G, 8),
|
||||||
|
__STM32_PIN(105, G, 9),
|
||||||
|
__STM32_PIN(106, G, 10),
|
||||||
|
__STM32_PIN(107, G, 11),
|
||||||
|
__STM32_PIN(108, G, 12),
|
||||||
|
__STM32_PIN(109, G, 13),
|
||||||
|
__STM32_PIN(110, G, 14),
|
||||||
|
__STM32_PIN(111, G, 15),
|
||||||
|
#endif
|
||||||
|
#ifdef GPIOH
|
||||||
|
__STM32_PIN(112, H, 0),
|
||||||
|
__STM32_PIN(113, H, 1),
|
||||||
|
__STM32_PIN(114, H, 2),
|
||||||
|
__STM32_PIN(115, H, 3),
|
||||||
|
__STM32_PIN(116, H, 4),
|
||||||
|
__STM32_PIN(117, H, 5),
|
||||||
|
__STM32_PIN(118, H, 6),
|
||||||
|
__STM32_PIN(119, H, 7),
|
||||||
|
__STM32_PIN(120, H, 8),
|
||||||
|
__STM32_PIN(121, H, 9),
|
||||||
|
__STM32_PIN(122, H, 10),
|
||||||
|
__STM32_PIN(124, H, 11),
|
||||||
|
__STM32_PIN(125, H, 12),
|
||||||
|
__STM32_PIN(126, H, 13),
|
||||||
|
__STM32_PIN(127, H, 14),
|
||||||
|
__STM32_PIN(128, H, 15),
|
||||||
|
#endif
|
||||||
|
#ifdef GPIOI
|
||||||
|
__STM32_PIN(129, I, 0),
|
||||||
|
__STM32_PIN(130, I, 1),
|
||||||
|
__STM32_PIN(131, I, 2),
|
||||||
|
__STM32_PIN(132, I, 3),
|
||||||
|
__STM32_PIN(133, I, 4),
|
||||||
|
__STM32_PIN(134, I, 5),
|
||||||
|
__STM32_PIN(135, I, 6),
|
||||||
|
__STM32_PIN(136, I, 7),
|
||||||
|
__STM32_PIN(137, I, 8),
|
||||||
|
__STM32_PIN(138, I, 9),
|
||||||
|
__STM32_PIN(139, I, 10),
|
||||||
|
__STM32_PIN(140, I, 11),
|
||||||
|
__STM32_PIN(141, I, 12),
|
||||||
|
__STM32_PIN(142, I, 13),
|
||||||
|
__STM32_PIN(143, I, 14),
|
||||||
|
__STM32_PIN(144, I, 15),
|
||||||
|
#endif
|
||||||
|
#ifdef GPIOJ
|
||||||
|
__STM32_PIN(145, J, 0),
|
||||||
|
__STM32_PIN(146, J, 1),
|
||||||
|
__STM32_PIN(147, J, 2),
|
||||||
|
__STM32_PIN(148, J, 3),
|
||||||
|
__STM32_PIN(149, J, 4),
|
||||||
|
__STM32_PIN(150, J, 5),
|
||||||
|
__STM32_PIN(151, J, 6),
|
||||||
|
__STM32_PIN(152, J, 7),
|
||||||
|
__STM32_PIN(153, J, 8),
|
||||||
|
__STM32_PIN(154, J, 9),
|
||||||
|
__STM32_PIN(155, J, 10),
|
||||||
|
__STM32_PIN(156, J, 11),
|
||||||
|
__STM32_PIN(157, J, 12),
|
||||||
|
__STM32_PIN(158, J, 13),
|
||||||
|
__STM32_PIN(159, J, 14),
|
||||||
|
__STM32_PIN(160, J, 15),
|
||||||
|
#endif
|
||||||
|
#ifdef GPIOK
|
||||||
|
__STM32_PIN(161, K, 0),
|
||||||
|
__STM32_PIN(162, K, 1),
|
||||||
|
__STM32_PIN(163, K, 2),
|
||||||
|
__STM32_PIN(164, K, 3),
|
||||||
|
__STM32_PIN(165, K, 4),
|
||||||
|
__STM32_PIN(166, K, 5),
|
||||||
|
__STM32_PIN(167, K, 6),
|
||||||
|
__STM32_PIN(168, K, 7),
|
||||||
|
__STM32_PIN(169, K, 8),
|
||||||
|
__STM32_PIN(170, K, 9),
|
||||||
|
__STM32_PIN(171, K, 10),
|
||||||
|
__STM32_PIN(172, K, 11),
|
||||||
|
__STM32_PIN(173, K, 12),
|
||||||
|
__STM32_PIN(174, K, 13),
|
||||||
|
__STM32_PIN(175, K, 14),
|
||||||
|
__STM32_PIN(176, K, 15),
|
||||||
|
#endif
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct pin_irq_map pin_irq_map[] =
|
||||||
|
{
|
||||||
|
{GPIO_PIN_0, EXTI0_IRQn},
|
||||||
|
{GPIO_PIN_1, EXTI1_IRQn},
|
||||||
|
{GPIO_PIN_2, EXTI2_IRQn},
|
||||||
|
{GPIO_PIN_3, EXTI3_IRQn},
|
||||||
|
{GPIO_PIN_4, EXTI4_IRQn},
|
||||||
|
{GPIO_PIN_5, EXTI9_5_IRQn},
|
||||||
|
{GPIO_PIN_6, EXTI9_5_IRQn},
|
||||||
|
{GPIO_PIN_7, EXTI9_5_IRQn},
|
||||||
|
{GPIO_PIN_8, EXTI9_5_IRQn},
|
||||||
|
{GPIO_PIN_9, EXTI9_5_IRQn},
|
||||||
|
{GPIO_PIN_10, EXTI15_10_IRQn},
|
||||||
|
{GPIO_PIN_11, EXTI15_10_IRQn},
|
||||||
|
{GPIO_PIN_12, EXTI15_10_IRQn},
|
||||||
|
{GPIO_PIN_13, EXTI15_10_IRQn},
|
||||||
|
{GPIO_PIN_14, EXTI15_10_IRQn},
|
||||||
|
{GPIO_PIN_15, EXTI15_10_IRQn},
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
|
||||||
|
{
|
||||||
|
{-1, 0, RT_NULL, RT_NULL},
|
||||||
|
{-1, 0, RT_NULL, RT_NULL},
|
||||||
|
{-1, 0, RT_NULL, RT_NULL},
|
||||||
|
{-1, 0, RT_NULL, RT_NULL},
|
||||||
|
{-1, 0, RT_NULL, RT_NULL},
|
||||||
|
{-1, 0, RT_NULL, RT_NULL},
|
||||||
|
{-1, 0, RT_NULL, RT_NULL},
|
||||||
|
{-1, 0, RT_NULL, RT_NULL},
|
||||||
|
{-1, 0, RT_NULL, RT_NULL},
|
||||||
|
{-1, 0, RT_NULL, RT_NULL},
|
||||||
|
{-1, 0, RT_NULL, RT_NULL},
|
||||||
|
{-1, 0, RT_NULL, RT_NULL},
|
||||||
|
{-1, 0, RT_NULL, RT_NULL},
|
||||||
|
{-1, 0, RT_NULL, RT_NULL},
|
||||||
|
{-1, 0, RT_NULL, RT_NULL},
|
||||||
|
{-1, 0, RT_NULL, RT_NULL},
|
||||||
|
};
|
||||||
|
|
||||||
|
#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
|
||||||
|
static const struct pin_index *get_pin(uint8_t pin)
|
||||||
|
{
|
||||||
|
const struct pin_index *index;
|
||||||
|
|
||||||
|
if (pin < ITEM_NUM(pins))
|
||||||
|
{
|
||||||
|
index = &pins[pin];
|
||||||
|
if (index->index == -1)
|
||||||
|
index = RT_NULL;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
index = RT_NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
return index;
|
||||||
|
};
|
||||||
|
|
||||||
|
static void stm32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
|
||||||
|
{
|
||||||
|
const struct pin_index *index;
|
||||||
|
|
||||||
|
index = get_pin(pin);
|
||||||
|
if (index == RT_NULL)
|
||||||
|
{
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
HAL_GPIO_WritePin(index->gpio, index->pin, (GPIO_PinState)value);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int stm32_pin_read(rt_device_t dev, rt_base_t pin)
|
||||||
|
{
|
||||||
|
int value;
|
||||||
|
const struct pin_index *index;
|
||||||
|
|
||||||
|
value = PIN_LOW;
|
||||||
|
|
||||||
|
index = get_pin(pin);
|
||||||
|
if (index == RT_NULL)
|
||||||
|
{
|
||||||
|
return value;
|
||||||
|
}
|
||||||
|
|
||||||
|
value = HAL_GPIO_ReadPin(index->gpio, index->pin);
|
||||||
|
|
||||||
|
return value;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void stm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
|
||||||
|
{
|
||||||
|
const struct pin_index *index;
|
||||||
|
GPIO_InitTypeDef GPIO_InitStruct;
|
||||||
|
|
||||||
|
index = get_pin(pin);
|
||||||
|
if (index == RT_NULL)
|
||||||
|
{
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Configure GPIO_InitStructure */
|
||||||
|
GPIO_InitStruct.Pin = index->pin;
|
||||||
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
||||||
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||||
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
||||||
|
|
||||||
|
if (mode == PIN_MODE_OUTPUT)
|
||||||
|
{
|
||||||
|
/* output setting */
|
||||||
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
||||||
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||||
|
}
|
||||||
|
else if (mode == PIN_MODE_INPUT)
|
||||||
|
{
|
||||||
|
/* input setting: not pull. */
|
||||||
|
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
||||||
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||||
|
}
|
||||||
|
else if (mode == PIN_MODE_INPUT_PULLUP)
|
||||||
|
{
|
||||||
|
/* input setting: pull up. */
|
||||||
|
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
||||||
|
GPIO_InitStruct.Pull = GPIO_PULLUP;
|
||||||
|
}
|
||||||
|
else if (mode == PIN_MODE_INPUT_PULLDOWN)
|
||||||
|
{
|
||||||
|
/* input setting: pull down. */
|
||||||
|
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
||||||
|
GPIO_InitStruct.Pull = GPIO_PULLDOWN;
|
||||||
|
}
|
||||||
|
else if (mode == PIN_MODE_OUTPUT_OD)
|
||||||
|
{
|
||||||
|
/* output setting: od. */
|
||||||
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
|
||||||
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
HAL_GPIO_Init(index->gpio, &GPIO_InitStruct);
|
||||||
|
}
|
||||||
|
|
||||||
|
rt_inline rt_int32_t bit2bitno(rt_uint32_t bit)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
for (i = 0; i < 32; i++)
|
||||||
|
{
|
||||||
|
if ((0x01 << i) == bit)
|
||||||
|
{
|
||||||
|
return i;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
|
||||||
|
{
|
||||||
|
rt_int32_t mapindex = bit2bitno(pinbit);
|
||||||
|
if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map))
|
||||||
|
{
|
||||||
|
return RT_NULL;
|
||||||
|
}
|
||||||
|
return &pin_irq_map[mapindex];
|
||||||
|
};
|
||||||
|
|
||||||
|
static rt_err_t stm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
|
||||||
|
rt_uint32_t mode, void (*hdr)(void *args), void *args)
|
||||||
|
{
|
||||||
|
const struct pin_index *index;
|
||||||
|
rt_base_t level;
|
||||||
|
rt_int32_t irqindex = -1;
|
||||||
|
|
||||||
|
index = get_pin(pin);
|
||||||
|
if (index == RT_NULL)
|
||||||
|
{
|
||||||
|
return RT_ENOSYS;
|
||||||
|
}
|
||||||
|
irqindex = bit2bitno(index->pin);
|
||||||
|
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
|
||||||
|
{
|
||||||
|
return RT_ENOSYS;
|
||||||
|
}
|
||||||
|
|
||||||
|
level = rt_hw_interrupt_disable();
|
||||||
|
if (pin_irq_hdr_tab[irqindex].pin == pin &&
|
||||||
|
pin_irq_hdr_tab[irqindex].hdr == hdr &&
|
||||||
|
pin_irq_hdr_tab[irqindex].mode == mode &&
|
||||||
|
pin_irq_hdr_tab[irqindex].args == args)
|
||||||
|
{
|
||||||
|
rt_hw_interrupt_enable(level);
|
||||||
|
return RT_EOK;
|
||||||
|
}
|
||||||
|
if (pin_irq_hdr_tab[irqindex].pin != -1)
|
||||||
|
{
|
||||||
|
rt_hw_interrupt_enable(level);
|
||||||
|
return RT_EBUSY;
|
||||||
|
}
|
||||||
|
pin_irq_hdr_tab[irqindex].pin = pin;
|
||||||
|
pin_irq_hdr_tab[irqindex].hdr = hdr;
|
||||||
|
pin_irq_hdr_tab[irqindex].mode = mode;
|
||||||
|
pin_irq_hdr_tab[irqindex].args = args;
|
||||||
|
rt_hw_interrupt_enable(level);
|
||||||
|
|
||||||
|
return RT_EOK;
|
||||||
|
}
|
||||||
|
|
||||||
|
static rt_err_t stm32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
|
||||||
|
{
|
||||||
|
const struct pin_index *index;
|
||||||
|
rt_base_t level;
|
||||||
|
rt_int32_t irqindex = -1;
|
||||||
|
|
||||||
|
index = get_pin(pin);
|
||||||
|
if (index == RT_NULL)
|
||||||
|
{
|
||||||
|
return RT_ENOSYS;
|
||||||
|
}
|
||||||
|
irqindex = bit2bitno(index->pin);
|
||||||
|
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
|
||||||
|
{
|
||||||
|
return RT_ENOSYS;
|
||||||
|
}
|
||||||
|
|
||||||
|
level = rt_hw_interrupt_disable();
|
||||||
|
if (pin_irq_hdr_tab[irqindex].pin == -1)
|
||||||
|
{
|
||||||
|
rt_hw_interrupt_enable(level);
|
||||||
|
return RT_EOK;
|
||||||
|
}
|
||||||
|
pin_irq_hdr_tab[irqindex].pin = -1;
|
||||||
|
pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
|
||||||
|
pin_irq_hdr_tab[irqindex].mode = 0;
|
||||||
|
pin_irq_hdr_tab[irqindex].args = RT_NULL;
|
||||||
|
rt_hw_interrupt_enable(level);
|
||||||
|
|
||||||
|
return RT_EOK;
|
||||||
|
}
|
||||||
|
|
||||||
|
static rt_err_t stm32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
|
||||||
|
rt_uint32_t enabled)
|
||||||
|
{
|
||||||
|
const struct pin_index *index;
|
||||||
|
const struct pin_irq_map *irqmap;
|
||||||
|
rt_base_t level;
|
||||||
|
rt_int32_t irqindex = -1;
|
||||||
|
GPIO_InitTypeDef GPIO_InitStruct;
|
||||||
|
|
||||||
|
index = get_pin(pin);
|
||||||
|
if (index == RT_NULL)
|
||||||
|
{
|
||||||
|
return RT_ENOSYS;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (enabled == PIN_IRQ_ENABLE)
|
||||||
|
{
|
||||||
|
irqindex = bit2bitno(index->pin);
|
||||||
|
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
|
||||||
|
{
|
||||||
|
return RT_ENOSYS;
|
||||||
|
}
|
||||||
|
|
||||||
|
level = rt_hw_interrupt_disable();
|
||||||
|
|
||||||
|
if (pin_irq_hdr_tab[irqindex].pin == -1)
|
||||||
|
{
|
||||||
|
rt_hw_interrupt_enable(level);
|
||||||
|
return RT_ENOSYS;
|
||||||
|
}
|
||||||
|
|
||||||
|
irqmap = &pin_irq_map[irqindex];
|
||||||
|
|
||||||
|
/* Configure GPIO_InitStructure */
|
||||||
|
GPIO_InitStruct.Pin = index->pin;
|
||||||
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||||
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
||||||
|
switch (pin_irq_hdr_tab[irqindex].mode)
|
||||||
|
{
|
||||||
|
case PIN_IRQ_MODE_RISING:
|
||||||
|
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
|
||||||
|
break;
|
||||||
|
case PIN_IRQ_MODE_FALLING:
|
||||||
|
GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
|
||||||
|
break;
|
||||||
|
case PIN_IRQ_MODE_RISING_FALLING:
|
||||||
|
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
HAL_GPIO_Init(index->gpio, &GPIO_InitStruct);
|
||||||
|
|
||||||
|
HAL_NVIC_SetPriority(irqmap->irqno, 5, 0);
|
||||||
|
HAL_NVIC_EnableIRQ(irqmap->irqno);
|
||||||
|
|
||||||
|
rt_hw_interrupt_enable(level);
|
||||||
|
}
|
||||||
|
else if (enabled == PIN_IRQ_DISABLE)
|
||||||
|
{
|
||||||
|
irqmap = get_pin_irq_map(index->pin);
|
||||||
|
if (irqmap == RT_NULL)
|
||||||
|
{
|
||||||
|
return RT_ENOSYS;
|
||||||
|
}
|
||||||
|
|
||||||
|
HAL_NVIC_DisableIRQ(irqmap->irqno);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return RT_ENOSYS;
|
||||||
|
}
|
||||||
|
|
||||||
|
return RT_EOK;
|
||||||
|
}
|
||||||
|
const static struct rt_pin_ops _stm32_pin_ops =
|
||||||
|
{
|
||||||
|
stm32_pin_mode,
|
||||||
|
stm32_pin_write,
|
||||||
|
stm32_pin_read,
|
||||||
|
stm32_pin_attach_irq,
|
||||||
|
stm32_pin_dettach_irq,
|
||||||
|
stm32_pin_irq_enable,
|
||||||
|
};
|
||||||
|
|
||||||
|
rt_inline void pin_irq_hdr(int irqno)
|
||||||
|
{
|
||||||
|
if (pin_irq_hdr_tab[irqno].hdr)
|
||||||
|
{
|
||||||
|
pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
|
||||||
|
{
|
||||||
|
pin_irq_hdr(bit2bitno(GPIO_Pin));
|
||||||
|
}
|
||||||
|
|
||||||
|
void EXTI0_IRQHandler(void)
|
||||||
|
{
|
||||||
|
rt_interrupt_enter();
|
||||||
|
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_0);
|
||||||
|
rt_interrupt_leave();
|
||||||
|
}
|
||||||
|
|
||||||
|
void EXTI1_IRQHandler(void)
|
||||||
|
{
|
||||||
|
rt_interrupt_enter();
|
||||||
|
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_1);
|
||||||
|
rt_interrupt_leave();
|
||||||
|
}
|
||||||
|
|
||||||
|
void EXTI2_IRQHandler(void)
|
||||||
|
{
|
||||||
|
rt_interrupt_enter();
|
||||||
|
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_2);
|
||||||
|
rt_interrupt_leave();
|
||||||
|
}
|
||||||
|
|
||||||
|
void EXTI3_IRQHandler(void)
|
||||||
|
{
|
||||||
|
rt_interrupt_enter();
|
||||||
|
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_3);
|
||||||
|
rt_interrupt_leave();
|
||||||
|
}
|
||||||
|
|
||||||
|
void EXTI4_IRQHandler(void)
|
||||||
|
{
|
||||||
|
rt_interrupt_enter();
|
||||||
|
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_4);
|
||||||
|
rt_interrupt_leave();
|
||||||
|
}
|
||||||
|
|
||||||
|
void EXTI9_5_IRQHandler(void)
|
||||||
|
{
|
||||||
|
rt_interrupt_enter();
|
||||||
|
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_5);
|
||||||
|
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_6);
|
||||||
|
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_7);
|
||||||
|
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_8);
|
||||||
|
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_9);
|
||||||
|
rt_interrupt_leave();
|
||||||
|
}
|
||||||
|
|
||||||
|
void EXTI15_10_IRQHandler(void)
|
||||||
|
{
|
||||||
|
rt_interrupt_enter();
|
||||||
|
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_10);
|
||||||
|
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_11);
|
||||||
|
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_12);
|
||||||
|
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_13);
|
||||||
|
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_14);
|
||||||
|
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_15);
|
||||||
|
rt_interrupt_leave();
|
||||||
|
}
|
||||||
|
|
||||||
|
int rt_hw_pin_init(void)
|
||||||
|
{
|
||||||
|
#if defined(__HAL_RCC_GPIOA_CLK_ENABLE)
|
||||||
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(__HAL_RCC_GPIOB_CLK_ENABLE)
|
||||||
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(__HAL_RCC_GPIOC_CLK_ENABLE)
|
||||||
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(__HAL_RCC_GPIOD_CLK_ENABLE)
|
||||||
|
__HAL_RCC_GPIOD_CLK_ENABLE();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(__HAL_RCC_GPIOE_CLK_ENABLE)
|
||||||
|
__HAL_RCC_GPIOE_CLK_ENABLE();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(__HAL_RCC_GPIOF_CLK_ENABLE)
|
||||||
|
__HAL_RCC_GPIOF_CLK_ENABLE();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(__HAL_RCC_GPIOG_CLK_ENABLE)
|
||||||
|
__HAL_RCC_GPIOG_CLK_ENABLE();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(__HAL_RCC_GPIOH_CLK_ENABLE)
|
||||||
|
__HAL_RCC_GPIOH_CLK_ENABLE();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(__HAL_RCC_GPIOI_CLK_ENABLE)
|
||||||
|
__HAL_RCC_GPIOI_CLK_ENABLE();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(__HAL_RCC_GPIOJ_CLK_ENABLE)
|
||||||
|
__HAL_RCC_GPIOJ_CLK_ENABLE();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
return rt_device_pin_register("pin", &_stm32_pin_ops, RT_NULL);
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* RT_USING_PIN */
|
||||||
|
|
@ -0,0 +1,48 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* Change Logs:
|
||||||
|
* Date Author Notes
|
||||||
|
* 2018-11-06 balanceTWK change to new framework
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __DRV_GPIO_H__
|
||||||
|
#define __DRV_GPIO_H__
|
||||||
|
|
||||||
|
#include <drv_common.h>
|
||||||
|
|
||||||
|
#define __STM32_PORT(port) GPIO##port
|
||||||
|
|
||||||
|
#define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__STM32_PORT(PORTx) - (rt_base_t)GPIOA)/(0x0400UL) )) + PIN)
|
||||||
|
|
||||||
|
#define __STM32_PIN(index, gpio, gpio_index) \
|
||||||
|
{ \
|
||||||
|
index, GPIO##gpio, GPIO_PIN_##gpio_index \
|
||||||
|
}
|
||||||
|
|
||||||
|
#define __STM32_PIN_RESERVE \
|
||||||
|
{ \
|
||||||
|
-1, 0, 0 \
|
||||||
|
}
|
||||||
|
|
||||||
|
/* STM32 GPIO driver */
|
||||||
|
struct pin_index
|
||||||
|
{
|
||||||
|
int index;
|
||||||
|
GPIO_TypeDef *gpio;
|
||||||
|
uint32_t pin;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct pin_irq_map
|
||||||
|
{
|
||||||
|
rt_uint16_t pinbit;
|
||||||
|
IRQn_Type irqno;
|
||||||
|
};
|
||||||
|
|
||||||
|
int rt_hw_pin_init(void);
|
||||||
|
|
||||||
|
#endif /* __DRV_GPIO_H__ */
|
||||||
|
|
||||||
|
|
@ -0,0 +1,30 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Change Logs:
|
||||||
|
* Date Author Notes
|
||||||
|
* 2018-11-15 SummerGift change to new framework
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* NOTE: DO NOT include this file on the header file.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define DBG_ENABLE
|
||||||
|
#define DBG_COLOR
|
||||||
|
|
||||||
|
#ifndef LOG_TAG
|
||||||
|
#define DBG_SECTION_NAME "drv"
|
||||||
|
#else
|
||||||
|
#define DBG_SECTION_NAME LOG_TAG
|
||||||
|
#endif /* LOG_TAG */
|
||||||
|
|
||||||
|
#ifdef DRV_DEBUG
|
||||||
|
#define DBG_LEVEL DBG_LOG
|
||||||
|
#else
|
||||||
|
#define DBG_LEVEL DBG_INFO
|
||||||
|
#endif /* DRV_DEBUG */
|
||||||
|
|
||||||
|
#include <rtdbg.h>
|
||||||
|
|
@ -0,0 +1,342 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* Change Logs:
|
||||||
|
* Date Author Notes
|
||||||
|
* 2018-11-27 zylx change to new framework
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "board.h"
|
||||||
|
#include "drv_qspi.h"
|
||||||
|
#include "drv_config.h"
|
||||||
|
|
||||||
|
#ifdef RT_USING_QSPI
|
||||||
|
|
||||||
|
#define DRV_DEBUG
|
||||||
|
#define LOG_TAG "drv.qspi"
|
||||||
|
#include <drv_log.h>
|
||||||
|
|
||||||
|
#if !defined(BSP_USING_QSPI)
|
||||||
|
#error "Please define at least one BSP_USING_QSPI"
|
||||||
|
/* this driver can be disabled at menuconfig ? RT-Thread Components ? Device Drivers */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
struct stm32_hw_spi_cs
|
||||||
|
{
|
||||||
|
uint16_t Pin;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct stm32_qspi_bus
|
||||||
|
{
|
||||||
|
QSPI_HandleTypeDef QSPI_Handler;
|
||||||
|
char *bus_name;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct rt_spi_bus _qspi_bus1;
|
||||||
|
struct stm32_qspi_bus _stm32_qspi_bus;
|
||||||
|
|
||||||
|
static int stm32_qspi_init(struct rt_qspi_device *device, struct rt_qspi_configuration *qspi_cfg)
|
||||||
|
{
|
||||||
|
int result = RT_EOK;
|
||||||
|
unsigned int i = 1;
|
||||||
|
|
||||||
|
RT_ASSERT(device != RT_NULL);
|
||||||
|
RT_ASSERT(qspi_cfg != RT_NULL);
|
||||||
|
|
||||||
|
struct rt_spi_configuration *cfg = &qspi_cfg->parent;
|
||||||
|
struct stm32_qspi_bus *qspi_bus = device->parent.bus->parent.user_data;
|
||||||
|
rt_memset(&qspi_bus->QSPI_Handler, 0, sizeof(qspi_bus->QSPI_Handler));
|
||||||
|
|
||||||
|
while (cfg->max_hz < HAL_RCC_GetHCLKFreq() / (i + 1))
|
||||||
|
{
|
||||||
|
i++;
|
||||||
|
if (i == 255)
|
||||||
|
{
|
||||||
|
LOG_E("QSPI init failed, QSPI frequency(%d) is too low.", cfg->max_hz);
|
||||||
|
return -RT_ERROR;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
/* 80/(1+i) */
|
||||||
|
qspi_bus->QSPI_Handler.Init.ClockPrescaler = i;
|
||||||
|
|
||||||
|
if (!(cfg->mode & RT_SPI_CPOL))
|
||||||
|
{
|
||||||
|
/* QSPI MODE0 */
|
||||||
|
qspi_bus->QSPI_Handler.Init.ClockMode = QSPI_CLOCK_MODE_0;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* QSPI MODE3 */
|
||||||
|
qspi_bus->QSPI_Handler.Init.ClockMode = QSPI_CLOCK_MODE_3;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* flash size */
|
||||||
|
qspi_bus->QSPI_Handler.Init.FlashSize = POSITION_VAL(qspi_cfg->medium_size) - 1;
|
||||||
|
|
||||||
|
qspi_bus->QSPI_Handler.Instance = QUADSPI;
|
||||||
|
/* fifo threshold is 4 byte */
|
||||||
|
qspi_bus->QSPI_Handler.Init.FifoThreshold = 4;
|
||||||
|
/* Sampling shift half a cycle */
|
||||||
|
qspi_bus->QSPI_Handler.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE;
|
||||||
|
/* cs high time */
|
||||||
|
qspi_bus->QSPI_Handler.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_4_CYCLE;
|
||||||
|
|
||||||
|
result = HAL_QSPI_Init(&qspi_bus->QSPI_Handler);
|
||||||
|
if (result == HAL_OK)
|
||||||
|
{
|
||||||
|
LOG_D("qspi init succsee!");
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
LOG_E("qspi init failed (%d)!", result);
|
||||||
|
}
|
||||||
|
|
||||||
|
return result;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void qspi_send_cmd(struct stm32_qspi_bus *qspi_bus, struct rt_qspi_message *message)
|
||||||
|
{
|
||||||
|
RT_ASSERT(qspi_bus != RT_NULL);
|
||||||
|
RT_ASSERT(message != RT_NULL);
|
||||||
|
|
||||||
|
QSPI_CommandTypeDef Cmdhandler;
|
||||||
|
|
||||||
|
/* set QSPI cmd struct */
|
||||||
|
Cmdhandler.Instruction = message->instruction.content;
|
||||||
|
Cmdhandler.Address = message->address.content;
|
||||||
|
Cmdhandler.DummyCycles = message->dummy_cycles;
|
||||||
|
if (message->instruction.qspi_lines == 0)
|
||||||
|
{
|
||||||
|
Cmdhandler.InstructionMode = QSPI_INSTRUCTION_NONE;
|
||||||
|
}
|
||||||
|
else if (message->instruction.qspi_lines == 1)
|
||||||
|
{
|
||||||
|
Cmdhandler.InstructionMode = QSPI_INSTRUCTION_1_LINE;
|
||||||
|
}
|
||||||
|
else if (message->instruction.qspi_lines == 2)
|
||||||
|
{
|
||||||
|
Cmdhandler.InstructionMode = QSPI_INSTRUCTION_2_LINES;
|
||||||
|
}
|
||||||
|
else if (message->instruction.qspi_lines == 4)
|
||||||
|
{
|
||||||
|
Cmdhandler.InstructionMode = QSPI_INSTRUCTION_4_LINES;
|
||||||
|
}
|
||||||
|
if (message->address.qspi_lines == 0)
|
||||||
|
{
|
||||||
|
Cmdhandler.AddressMode = QSPI_ADDRESS_NONE;
|
||||||
|
}
|
||||||
|
else if (message->address.qspi_lines == 1)
|
||||||
|
{
|
||||||
|
Cmdhandler.AddressMode = QSPI_ADDRESS_1_LINE;
|
||||||
|
}
|
||||||
|
else if (message->address.qspi_lines == 2)
|
||||||
|
{
|
||||||
|
Cmdhandler.AddressMode = QSPI_ADDRESS_2_LINES;
|
||||||
|
}
|
||||||
|
else if (message->address.qspi_lines == 4)
|
||||||
|
{
|
||||||
|
Cmdhandler.AddressMode = QSPI_ADDRESS_4_LINES;
|
||||||
|
}
|
||||||
|
if (message->address.size == 24)
|
||||||
|
{
|
||||||
|
Cmdhandler.AddressSize = QSPI_ADDRESS_24_BITS;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
Cmdhandler.AddressSize = QSPI_ADDRESS_32_BITS;
|
||||||
|
}
|
||||||
|
if (message->qspi_data_lines == 0)
|
||||||
|
{
|
||||||
|
Cmdhandler.DataMode = QSPI_DATA_NONE;
|
||||||
|
}
|
||||||
|
else if (message->qspi_data_lines == 1)
|
||||||
|
{
|
||||||
|
Cmdhandler.DataMode = QSPI_DATA_1_LINE;
|
||||||
|
}
|
||||||
|
else if (message->qspi_data_lines == 2)
|
||||||
|
{
|
||||||
|
Cmdhandler.DataMode = QSPI_DATA_2_LINES;
|
||||||
|
}
|
||||||
|
else if (message->qspi_data_lines == 4)
|
||||||
|
{
|
||||||
|
Cmdhandler.DataMode = QSPI_DATA_4_LINES;
|
||||||
|
}
|
||||||
|
|
||||||
|
Cmdhandler.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
|
||||||
|
Cmdhandler.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
|
||||||
|
Cmdhandler.DdrMode = QSPI_DDR_MODE_DISABLE;
|
||||||
|
Cmdhandler.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
|
||||||
|
Cmdhandler.NbData = message->parent.length;
|
||||||
|
HAL_QSPI_Command(&qspi_bus->QSPI_Handler, &Cmdhandler, 5000);
|
||||||
|
}
|
||||||
|
|
||||||
|
static rt_uint32_t qspixfer(struct rt_spi_device *device, struct rt_spi_message *message)
|
||||||
|
{
|
||||||
|
rt_size_t len = 0;
|
||||||
|
|
||||||
|
RT_ASSERT(device != RT_NULL);
|
||||||
|
RT_ASSERT(device->bus != RT_NULL);
|
||||||
|
|
||||||
|
struct rt_qspi_message *qspi_message = (struct rt_qspi_message *)message;
|
||||||
|
struct stm32_qspi_bus *qspi_bus = device->bus->parent.user_data;
|
||||||
|
#ifdef BSP_QSPI_USING_SOFTCS
|
||||||
|
struct stm32_hw_spi_cs *cs = device->parent.user_data;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
const rt_uint8_t *sndb = message->send_buf;
|
||||||
|
rt_uint8_t *rcvb = message->recv_buf;
|
||||||
|
rt_int32_t length = message->length;
|
||||||
|
|
||||||
|
#ifdef BSP_QSPI_USING_SOFTCS
|
||||||
|
if (message->cs_take)
|
||||||
|
{
|
||||||
|
rt_pin_write(cs->pin, 0);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* send data */
|
||||||
|
if (sndb)
|
||||||
|
{
|
||||||
|
qspi_send_cmd(qspi_bus, qspi_message);
|
||||||
|
if (qspi_message->parent.length != 0)
|
||||||
|
{
|
||||||
|
if (HAL_QSPI_Transmit(&qspi_bus->QSPI_Handler, (rt_uint8_t *)sndb, 5000) == HAL_OK)
|
||||||
|
{
|
||||||
|
|
||||||
|
len = length;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
LOG_E("QSPI send data failed(%d)!", qspi_bus->QSPI_Handler.ErrorCode);
|
||||||
|
qspi_bus->QSPI_Handler.State = HAL_QSPI_STATE_READY;
|
||||||
|
goto __exit;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
len = 1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else if (rcvb)/* recv data */
|
||||||
|
{
|
||||||
|
|
||||||
|
qspi_send_cmd(qspi_bus, qspi_message);
|
||||||
|
|
||||||
|
if (HAL_QSPI_Receive(&qspi_bus->QSPI_Handler, rcvb, 5000) == HAL_OK)
|
||||||
|
{
|
||||||
|
len = length;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
LOG_E("QSPI recv data failed(%d)!", qspi_bus->QSPI_Handler.ErrorCode);
|
||||||
|
qspi_bus->QSPI_Handler.State = HAL_QSPI_STATE_READY;
|
||||||
|
goto __exit;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
__exit:
|
||||||
|
#ifdef BSP_QSPI_USING_SOFTCS
|
||||||
|
if (message->cs_release)
|
||||||
|
{
|
||||||
|
rt_pin_write(cs->pin, 1);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
return len;
|
||||||
|
}
|
||||||
|
|
||||||
|
static rt_err_t qspi_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration)
|
||||||
|
{
|
||||||
|
RT_ASSERT(device != RT_NULL);
|
||||||
|
RT_ASSERT(configuration != RT_NULL);
|
||||||
|
|
||||||
|
struct rt_qspi_device *qspi_device = (struct rt_qspi_device *)device;
|
||||||
|
return stm32_qspi_init(qspi_device, &qspi_device->config);
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct rt_spi_ops stm32_qspi_ops =
|
||||||
|
{
|
||||||
|
.configure = qspi_configure,
|
||||||
|
.xfer = qspixfer,
|
||||||
|
};
|
||||||
|
|
||||||
|
static int stm32_qspi_register_bus(struct stm32_qspi_bus *qspi_bus, const char *name)
|
||||||
|
{
|
||||||
|
RT_ASSERT(qspi_bus != RT_NULL);
|
||||||
|
RT_ASSERT(name != RT_NULL);
|
||||||
|
|
||||||
|
_qspi_bus1.parent.user_data = qspi_bus;
|
||||||
|
return rt_qspi_bus_register(&_qspi_bus1, name, &stm32_qspi_ops);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function attach device to QSPI bus.
|
||||||
|
* @param device_name QSPI device name
|
||||||
|
* @param pin QSPI cs pin number
|
||||||
|
* @param data_line_width QSPI data lines width, such as 1, 2, 4
|
||||||
|
* @param enter_qspi_mode Callback function that lets FLASH enter QSPI mode
|
||||||
|
* @param exit_qspi_mode Callback function that lets FLASH exit QSPI mode
|
||||||
|
* @retval 0 : success
|
||||||
|
* -1 : failed
|
||||||
|
*/
|
||||||
|
rt_err_t stm32_qspi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin, rt_uint8_t data_line_width, void (*enter_qspi_mode)(), void (*exit_qspi_mode)())
|
||||||
|
{
|
||||||
|
rt_err_t result = RT_EOK;
|
||||||
|
|
||||||
|
RT_ASSERT(bus_name != RT_NULL);
|
||||||
|
RT_ASSERT(device_name != RT_NULL);
|
||||||
|
RT_ASSERT(data_line_width == 1 || data_line_width == 2 || data_line_width == 4);
|
||||||
|
|
||||||
|
struct rt_qspi_device *qspi_device = (struct rt_qspi_device *)rt_malloc(sizeof(struct rt_qspi_device));
|
||||||
|
if (qspi_device == RT_NULL)
|
||||||
|
{
|
||||||
|
LOG_E("no memory, qspi bus attach device failed!");
|
||||||
|
result = RT_ENOMEM;
|
||||||
|
goto __exit;
|
||||||
|
}
|
||||||
|
struct stm32_hw_spi_cs *cs_pin = (struct stm32_hw_spi_cs *)rt_malloc(sizeof(struct stm32_hw_spi_cs));
|
||||||
|
if (qspi_device == RT_NULL)
|
||||||
|
{
|
||||||
|
LOG_E("no memory, qspi bus attach device failed!");
|
||||||
|
result = RT_ENOMEM;
|
||||||
|
goto __exit;
|
||||||
|
}
|
||||||
|
|
||||||
|
qspi_device->enter_qspi_mode = enter_qspi_mode;
|
||||||
|
qspi_device->exit_qspi_mode = exit_qspi_mode;
|
||||||
|
qspi_device->config.qspi_dl_width = data_line_width;
|
||||||
|
|
||||||
|
cs_pin->Pin = pin;
|
||||||
|
#ifdef BSP_QSPI_USING_SOFTCS
|
||||||
|
rt_pin_mode(pin, PIN_MODE_OUTPUT);
|
||||||
|
rt_pin_write(pin, 1);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
result = rt_spi_bus_attach_device(&qspi_device->parent, device_name, bus_name, (void *)cs_pin);
|
||||||
|
|
||||||
|
__exit:
|
||||||
|
if (result != RT_EOK)
|
||||||
|
{
|
||||||
|
if (qspi_device)
|
||||||
|
{
|
||||||
|
rt_free(qspi_device);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (cs_pin)
|
||||||
|
{
|
||||||
|
rt_free(cs_pin);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return result;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int rt_hw_qspi_bus_init(void)
|
||||||
|
{
|
||||||
|
return stm32_qspi_register_bus(&_stm32_qspi_bus, "qspi1");
|
||||||
|
}
|
||||||
|
INIT_BOARD_EXPORT(rt_hw_qspi_bus_init);
|
||||||
|
|
||||||
|
#endif /* RT_USING_QSPI */
|
||||||
|
|
@ -0,0 +1,18 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* Change Logs:
|
||||||
|
* Date Author Notes
|
||||||
|
* 2018-11-27 zylx change to new framework
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __DRV_QSPI_H_
|
||||||
|
#define __DRV_QSPI_H_
|
||||||
|
#include <rtthread.h>
|
||||||
|
|
||||||
|
rt_err_t stm32_qspi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin, rt_uint8_t data_line_width, void (*enter_qspi_mode)(), void (*exit_qspi_mode)());
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,218 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Change Logs:
|
||||||
|
* Date Author Notes
|
||||||
|
* 2018-11-08 balanceTWK change to new framework
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <board.h>
|
||||||
|
#include "drv_soft_i2c.h"
|
||||||
|
#include "drv_config.h"
|
||||||
|
|
||||||
|
#ifdef RT_USING_I2C
|
||||||
|
|
||||||
|
//#define DRV_DEBUG
|
||||||
|
#define LOG_TAG "drv.i2c"
|
||||||
|
#include <drv_log.h>
|
||||||
|
|
||||||
|
#if !defined(BSP_USING_I2C1) && !defined(BSP_USING_I2C2) && !defined(BSP_USING_I2C3)
|
||||||
|
#error "Please define at least one BSP_USING_I2Cx"
|
||||||
|
/* this driver can be disabled at menuconfig → RT-Thread Components → Device Drivers */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
static const struct stm32_soft_i2c_config soft_i2c_config[] =
|
||||||
|
{
|
||||||
|
#ifdef BSP_USING_I2C1
|
||||||
|
I2C1_BUS_CONFIG,
|
||||||
|
#endif
|
||||||
|
#ifdef BSP_USING_I2C2
|
||||||
|
I2C2_BUS_CONFIG,
|
||||||
|
#endif
|
||||||
|
#ifdef BSP_USING_I2C3
|
||||||
|
I2C2_BUS_CONFIG,
|
||||||
|
#endif
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct stm32_i2c i2c_obj[sizeof(soft_i2c_config) / sizeof(soft_i2c_config[0])];
|
||||||
|
|
||||||
|
/**
|
||||||
|
* This function initializes the i2c pin.
|
||||||
|
*
|
||||||
|
* @param Stm32 i2c dirver class.
|
||||||
|
*/
|
||||||
|
static void stm32_i2c_gpio_init(struct stm32_i2c *i2c)
|
||||||
|
{
|
||||||
|
struct stm32_soft_i2c_config* cfg = (struct stm32_soft_i2c_config*)i2c->ops.data;
|
||||||
|
|
||||||
|
rt_pin_mode(cfg->scl, PIN_MODE_OUTPUT_OD);
|
||||||
|
rt_pin_mode(cfg->sda, PIN_MODE_OUTPUT_OD);
|
||||||
|
|
||||||
|
rt_pin_write(cfg->scl, PIN_HIGH);
|
||||||
|
rt_pin_write(cfg->sda, PIN_HIGH);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* This function sets the sda pin.
|
||||||
|
*
|
||||||
|
* @param Stm32 config class.
|
||||||
|
* @param The sda pin state.
|
||||||
|
*/
|
||||||
|
static void stm32_set_sda(void *data, rt_int32_t state)
|
||||||
|
{
|
||||||
|
struct stm32_soft_i2c_config* cfg = (struct stm32_soft_i2c_config*)data;
|
||||||
|
if (state)
|
||||||
|
{
|
||||||
|
rt_pin_write(cfg->sda, PIN_HIGH);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
rt_pin_write(cfg->sda, PIN_LOW);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* This function sets the scl pin.
|
||||||
|
*
|
||||||
|
* @param Stm32 config class.
|
||||||
|
* @param The scl pin state.
|
||||||
|
*/
|
||||||
|
static void stm32_set_scl(void *data, rt_int32_t state)
|
||||||
|
{
|
||||||
|
struct stm32_soft_i2c_config* cfg = (struct stm32_soft_i2c_config*)data;
|
||||||
|
if (state)
|
||||||
|
{
|
||||||
|
rt_pin_write(cfg->scl, PIN_HIGH);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
rt_pin_write(cfg->scl, PIN_LOW);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* This function gets the sda pin state.
|
||||||
|
*
|
||||||
|
* @param The sda pin state.
|
||||||
|
*/
|
||||||
|
static rt_int32_t stm32_get_sda(void *data)
|
||||||
|
{
|
||||||
|
struct stm32_soft_i2c_config* cfg = (struct stm32_soft_i2c_config*)data;
|
||||||
|
return rt_pin_read(cfg->sda);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* This function gets the scl pin state.
|
||||||
|
*
|
||||||
|
* @param The scl pin state.
|
||||||
|
*/
|
||||||
|
static rt_int32_t stm32_get_scl(void *data)
|
||||||
|
{
|
||||||
|
struct stm32_soft_i2c_config* cfg = (struct stm32_soft_i2c_config*)data;
|
||||||
|
return rt_pin_read(cfg->scl);
|
||||||
|
}
|
||||||
|
/**
|
||||||
|
* The time delay function.
|
||||||
|
*
|
||||||
|
* @param microseconds.
|
||||||
|
*/
|
||||||
|
static void stm32_udelay(rt_uint32_t us)
|
||||||
|
{
|
||||||
|
rt_uint32_t ticks;
|
||||||
|
rt_uint32_t told, tnow, tcnt = 0;
|
||||||
|
rt_uint32_t reload = SysTick->LOAD;
|
||||||
|
|
||||||
|
ticks = us * reload / (1000000 / RT_TICK_PER_SECOND);
|
||||||
|
told = SysTick->VAL;
|
||||||
|
while (1)
|
||||||
|
{
|
||||||
|
tnow = SysTick->VAL;
|
||||||
|
if (tnow != told)
|
||||||
|
{
|
||||||
|
if (tnow < told)
|
||||||
|
{
|
||||||
|
tcnt += told - tnow;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
tcnt += reload - tnow + told;
|
||||||
|
}
|
||||||
|
told = tnow;
|
||||||
|
if (tcnt >= ticks)
|
||||||
|
{
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct rt_i2c_bit_ops stm32_bit_ops_default =
|
||||||
|
{
|
||||||
|
.data = RT_NULL,
|
||||||
|
.set_sda = stm32_set_sda,
|
||||||
|
.set_scl = stm32_set_scl,
|
||||||
|
.get_sda = stm32_get_sda,
|
||||||
|
.get_scl = stm32_get_scl,
|
||||||
|
.udelay = stm32_udelay,
|
||||||
|
.delay_us = 1,
|
||||||
|
.timeout = 100
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* if i2c is locked, this function will unlock it
|
||||||
|
*
|
||||||
|
* @param stm32 config class
|
||||||
|
*
|
||||||
|
* @return RT_EOK indicates successful unlock.
|
||||||
|
*/
|
||||||
|
static rt_err_t stm32_i2c_bus_unlock(const struct stm32_soft_i2c_config *cfg)
|
||||||
|
{
|
||||||
|
rt_int32_t i = 0;
|
||||||
|
|
||||||
|
if (PIN_LOW == rt_pin_read(cfg->sda))
|
||||||
|
{
|
||||||
|
while (i++ < 9)
|
||||||
|
{
|
||||||
|
rt_pin_write(cfg->scl, PIN_HIGH);
|
||||||
|
stm32_udelay(100);
|
||||||
|
rt_pin_write(cfg->scl, PIN_LOW);
|
||||||
|
stm32_udelay(100);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
if (PIN_LOW == rt_pin_read(cfg->sda))
|
||||||
|
{
|
||||||
|
return -RT_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
return RT_EOK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* I2C initialization function */
|
||||||
|
int rt_hw_i2c_init(void)
|
||||||
|
{
|
||||||
|
rt_size_t obj_num = sizeof(i2c_obj) / sizeof(struct stm32_i2c);
|
||||||
|
rt_err_t result;
|
||||||
|
|
||||||
|
for (int i = 0; i < obj_num; i++)
|
||||||
|
{
|
||||||
|
i2c_obj[i].ops = stm32_bit_ops_default;
|
||||||
|
i2c_obj[i].ops.data = (void*)&soft_i2c_config[i];
|
||||||
|
i2c_obj[i].i2c2_bus.priv = &i2c_obj[i].ops;
|
||||||
|
stm32_i2c_gpio_init(&i2c_obj[i]);
|
||||||
|
result = rt_i2c_bit_add_bus(&i2c_obj[i].i2c2_bus, soft_i2c_config[i].bus_name);
|
||||||
|
RT_ASSERT(result == RT_EOK);
|
||||||
|
stm32_i2c_bus_unlock(&soft_i2c_config[i]);
|
||||||
|
|
||||||
|
LOG_D("software simulation %s init done, pin scl: %d, pin sda %d",
|
||||||
|
soft_i2c_config[i].bus_name,
|
||||||
|
soft_i2c_config[i].scl,
|
||||||
|
soft_i2c_config[i].sda);
|
||||||
|
}
|
||||||
|
|
||||||
|
return RT_EOK;
|
||||||
|
}
|
||||||
|
INIT_BOARD_EXPORT(rt_hw_i2c_init);
|
||||||
|
|
||||||
|
#endif /* RT_USING_I2C */
|
||||||
|
|
@ -0,0 +1,61 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Change Logs:
|
||||||
|
* Date Author Notes
|
||||||
|
* 2018-11-08 balanceTWK change to new framework
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __DRV_I2C__
|
||||||
|
#define __DRV_I2C__
|
||||||
|
|
||||||
|
#include <rtthread.h>
|
||||||
|
#include <rthw.h>
|
||||||
|
#include <rtdevice.h>
|
||||||
|
|
||||||
|
/* stm32 config class */
|
||||||
|
struct stm32_soft_i2c_config
|
||||||
|
{
|
||||||
|
rt_uint8_t scl;
|
||||||
|
rt_uint8_t sda;
|
||||||
|
const char *bus_name;
|
||||||
|
};
|
||||||
|
/* stm32 i2c dirver class */
|
||||||
|
struct stm32_i2c
|
||||||
|
{
|
||||||
|
struct rt_i2c_bit_ops ops;
|
||||||
|
struct rt_i2c_bus_device i2c2_bus;
|
||||||
|
};
|
||||||
|
|
||||||
|
#ifdef BSP_USING_I2C1
|
||||||
|
#define I2C1_BUS_CONFIG \
|
||||||
|
{ \
|
||||||
|
.scl = BSP_I2C1_SCL_PIN, \
|
||||||
|
.sda = BSP_I2C1_SDA_PIN, \
|
||||||
|
.bus_name = "i2c1", \
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef BSP_USING_I2C2
|
||||||
|
#define I2C2_BUS_CONFIG \
|
||||||
|
{ \
|
||||||
|
.scl = BSP_I2C2_SCL_PIN, \
|
||||||
|
.sda = BSP_I2C2_SDA_PIN, \
|
||||||
|
.bus_name = "i2c2", \
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef BSP_USING_I2C3
|
||||||
|
#define I2C3_BUS_CONFIG \
|
||||||
|
{ \
|
||||||
|
.scl = BSP_I2C3_SCL_PIN, \
|
||||||
|
.sda = BSP_I2C3_SDA_PIN, \
|
||||||
|
.bus_name = "i2c3", \
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
int rt_hw_i2c_init(void);
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,720 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* Change Logs:
|
||||||
|
* Date Author Notes
|
||||||
|
* 2018-11-5 SummerGift change to new framework
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "board.h"
|
||||||
|
|
||||||
|
#ifdef RT_USING_SPI
|
||||||
|
|
||||||
|
#if defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2) || defined(BSP_USING_SPI3) || defined(BSP_USING_SPI4) || defined(BSP_USING_SPI5)
|
||||||
|
/* this driver can be disabled at menuconfig → RT-Thread Components → Device Drivers */
|
||||||
|
|
||||||
|
#include "drv_spi.h"
|
||||||
|
#include "drv_config.h"
|
||||||
|
|
||||||
|
//#define DRV_DEBUG
|
||||||
|
#define LOG_TAG "drv.spi"
|
||||||
|
#include <drv_log.h>
|
||||||
|
|
||||||
|
enum
|
||||||
|
{
|
||||||
|
#ifdef BSP_USING_SPI1
|
||||||
|
SPI1_INDEX,
|
||||||
|
#endif
|
||||||
|
#ifdef BSP_USING_SPI2
|
||||||
|
SPI2_INDEX,
|
||||||
|
#endif
|
||||||
|
#ifdef BSP_USING_SPI3
|
||||||
|
SPI3_INDEX,
|
||||||
|
#endif
|
||||||
|
#ifdef BSP_USING_SPI4
|
||||||
|
SPI4_INDEX,
|
||||||
|
#endif
|
||||||
|
#ifdef BSP_USING_SPI5
|
||||||
|
SPI5_INDEX,
|
||||||
|
#endif
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct stm32_spi_config spi_config[] =
|
||||||
|
{
|
||||||
|
#ifdef BSP_USING_SPI1
|
||||||
|
SPI1_BUS_CONFIG,
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef BSP_USING_SPI2
|
||||||
|
SPI2_BUS_CONFIG,
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef BSP_USING_SPI3
|
||||||
|
SPI3_BUS_CONFIG,
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef BSP_USING_SPI4
|
||||||
|
SPI4_BUS_CONFIG,
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef BSP_USING_SPI5
|
||||||
|
SPI5_BUS_CONFIG,
|
||||||
|
#endif
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct stm32_spi spi_bus_obj[sizeof(spi_config) / sizeof(spi_config[0])];
|
||||||
|
|
||||||
|
static rt_err_t stm32_spi_init(struct stm32_spi *spi_drv, struct rt_spi_configuration *cfg)
|
||||||
|
{
|
||||||
|
RT_ASSERT(spi_drv != RT_NULL);
|
||||||
|
RT_ASSERT(cfg != RT_NULL);
|
||||||
|
|
||||||
|
SPI_HandleTypeDef *spi_handle = &spi_drv->handle;
|
||||||
|
|
||||||
|
if (cfg->mode & RT_SPI_SLAVE)
|
||||||
|
{
|
||||||
|
spi_handle->Init.Mode = SPI_MODE_SLAVE;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
spi_handle->Init.Mode = SPI_MODE_MASTER;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (cfg->mode & RT_SPI_3WIRE)
|
||||||
|
{
|
||||||
|
spi_handle->Init.Direction = SPI_DIRECTION_1LINE;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
spi_handle->Init.Direction = SPI_DIRECTION_2LINES;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (cfg->data_width == 8)
|
||||||
|
{
|
||||||
|
spi_handle->Init.DataSize = SPI_DATASIZE_8BIT;
|
||||||
|
spi_handle->TxXferSize = 8;
|
||||||
|
spi_handle->RxXferSize = 8;
|
||||||
|
}
|
||||||
|
else if (cfg->data_width == 16)
|
||||||
|
{
|
||||||
|
spi_handle->Init.DataSize = SPI_DATASIZE_16BIT;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return RT_EIO;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (cfg->mode & RT_SPI_CPHA)
|
||||||
|
{
|
||||||
|
spi_handle->Init.CLKPhase = SPI_PHASE_2EDGE;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
spi_handle->Init.CLKPhase = SPI_PHASE_1EDGE;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (cfg->mode & RT_SPI_CPOL)
|
||||||
|
{
|
||||||
|
spi_handle->Init.CLKPolarity = SPI_POLARITY_HIGH;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
spi_handle->Init.CLKPolarity = SPI_POLARITY_LOW;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (cfg->mode & RT_SPI_NO_CS)
|
||||||
|
{
|
||||||
|
spi_handle->Init.NSS = SPI_NSS_SOFT;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
spi_handle->Init.NSS = SPI_NSS_SOFT;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint32_t SPI_APB_CLOCK;
|
||||||
|
|
||||||
|
SPI_APB_CLOCK = HAL_RCC_GetPCLK2Freq();
|
||||||
|
|
||||||
|
if (cfg->max_hz >= SPI_APB_CLOCK / 2)
|
||||||
|
{
|
||||||
|
spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
|
||||||
|
}
|
||||||
|
else if (cfg->max_hz >= SPI_APB_CLOCK / 4)
|
||||||
|
{
|
||||||
|
spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_4;
|
||||||
|
}
|
||||||
|
else if (cfg->max_hz >= SPI_APB_CLOCK / 8)
|
||||||
|
{
|
||||||
|
spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_8;
|
||||||
|
}
|
||||||
|
else if (cfg->max_hz >= SPI_APB_CLOCK / 16)
|
||||||
|
{
|
||||||
|
spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16;
|
||||||
|
}
|
||||||
|
else if (cfg->max_hz >= SPI_APB_CLOCK / 32)
|
||||||
|
{
|
||||||
|
spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_32;
|
||||||
|
}
|
||||||
|
else if (cfg->max_hz >= SPI_APB_CLOCK / 64)
|
||||||
|
{
|
||||||
|
spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_64;
|
||||||
|
}
|
||||||
|
else if (cfg->max_hz >= SPI_APB_CLOCK / 128)
|
||||||
|
{
|
||||||
|
spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_128;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* min prescaler 256 */
|
||||||
|
spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_256;
|
||||||
|
}
|
||||||
|
|
||||||
|
LOG_D("sys freq: %d, pclk2 freq: %d, SPI limiting freq: %d, BaudRatePrescaler: %d",
|
||||||
|
HAL_RCC_GetSysClockFreq(),
|
||||||
|
SPI_APB_CLOCK,
|
||||||
|
cfg->max_hz,
|
||||||
|
spi_handle->Init.BaudRatePrescaler);
|
||||||
|
|
||||||
|
if (cfg->mode & RT_SPI_MSB)
|
||||||
|
{
|
||||||
|
spi_handle->Init.FirstBit = SPI_FIRSTBIT_MSB;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
spi_handle->Init.FirstBit = SPI_FIRSTBIT_LSB;
|
||||||
|
}
|
||||||
|
|
||||||
|
spi_handle->Init.TIMode = SPI_TIMODE_DISABLE;
|
||||||
|
spi_handle->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
|
||||||
|
spi_handle->State = HAL_SPI_STATE_RESET;
|
||||||
|
if (HAL_SPI_Init(spi_handle) != HAL_OK)
|
||||||
|
{
|
||||||
|
return RT_EIO;
|
||||||
|
}
|
||||||
|
|
||||||
|
#if defined(SOC_SERIES_STM32L4)
|
||||||
|
SET_BIT(spi_handle->Instance->CR2, SPI_RXFIFO_THRESHOLD_HF);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
__HAL_SPI_ENABLE(spi_handle);
|
||||||
|
|
||||||
|
LOG_D("%s init done", spi_drv->config->bus_name);
|
||||||
|
return RT_EOK;
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef BSP_SPI_USING_DMA
|
||||||
|
static uint8_t dummy = 0xFF;
|
||||||
|
static void spi_dma_transfer_prepare(struct rt_spi_bus * spi_bus, struct rt_spi_message* message)
|
||||||
|
{
|
||||||
|
struct stm32_spi *spi_drv = rt_container_of(spi_bus, struct stm32_spi, spi_bus);
|
||||||
|
|
||||||
|
DMA_HandleTypeDef * hdma_tx = (DMA_HandleTypeDef *)&spi_drv->dma.handle_tx;
|
||||||
|
DMA_HandleTypeDef * hdma_rx = (DMA_HandleTypeDef *)&spi_drv->dma.handle_rx;
|
||||||
|
|
||||||
|
HAL_DMA_DeInit(hdma_tx);
|
||||||
|
HAL_DMA_DeInit(hdma_rx);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Check if the DMA Stream is disabled before enabling it.
|
||||||
|
* Note that this step is useful when the same Stream is used multiple times.
|
||||||
|
*/
|
||||||
|
#if defined(SOC_SERIES_STM32F4)
|
||||||
|
while (hdma_tx->Instance->CR & DMA_SxCR_EN);
|
||||||
|
while (hdma_rx->Instance->CR & DMA_SxCR_EN);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
if(message->recv_buf != RT_NULL)
|
||||||
|
{
|
||||||
|
hdma_rx->Init.MemInc = DMA_MINC_ENABLE;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
message->recv_buf = &dummy;
|
||||||
|
hdma_rx->Init.MemInc = DMA_MINC_DISABLE;
|
||||||
|
}
|
||||||
|
HAL_DMA_Init(hdma_rx);
|
||||||
|
|
||||||
|
__HAL_LINKDMA(&spi_drv->handle, hdmarx, spi_drv->dma.handle_rx);
|
||||||
|
|
||||||
|
if(message->send_buf != RT_NULL)
|
||||||
|
{
|
||||||
|
hdma_tx->Init.MemInc = DMA_MINC_ENABLE;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
dummy = 0xFF;
|
||||||
|
message->send_buf = &dummy;
|
||||||
|
hdma_tx->Init.MemInc = DMA_MINC_DISABLE;
|
||||||
|
}
|
||||||
|
HAL_DMA_Init(hdma_tx);
|
||||||
|
|
||||||
|
/* link DMA with SPI */
|
||||||
|
__HAL_LINKDMA(&spi_drv->handle, hdmatx, spi_drv->dma.handle_tx);
|
||||||
|
|
||||||
|
LOG_D("%s RX Instance: %x, TX Instance: %x", spi_drv->config->bus_name, hdma_rx->Instance, hdma_tx->Instance);
|
||||||
|
LOG_D("%s dma config done, TX dma_irq number: %d, RX dma_irq number: %d",
|
||||||
|
spi_drv->config->bus_name,
|
||||||
|
spi_drv->config->dma_tx.dma_irq,
|
||||||
|
spi_drv->config->dma_rx.dma_irq);
|
||||||
|
|
||||||
|
/* NVIC configuration for DMA transfer complete interrupt*/
|
||||||
|
HAL_NVIC_SetPriority(spi_drv->config->dma_tx.dma_irq, 0, 1);
|
||||||
|
HAL_NVIC_EnableIRQ(spi_drv->config->dma_tx.dma_irq);
|
||||||
|
|
||||||
|
/* NVIC configuration for DMA transfer complete interrupt*/
|
||||||
|
HAL_NVIC_SetPriority(spi_drv->config->dma_rx.dma_irq, 0, 0);
|
||||||
|
HAL_NVIC_EnableIRQ(spi_drv->config->dma_rx.dma_irq);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
|
||||||
|
{
|
||||||
|
RT_ASSERT(device != RT_NULL);
|
||||||
|
RT_ASSERT(device->bus != RT_NULL);
|
||||||
|
RT_ASSERT(device->bus->parent.user_data != RT_NULL);
|
||||||
|
RT_ASSERT(message != RT_NULL);
|
||||||
|
|
||||||
|
struct stm32_spi *spi_drv = rt_container_of(device->bus, struct stm32_spi, spi_bus);
|
||||||
|
SPI_HandleTypeDef * spi_handle = &spi_drv->handle;
|
||||||
|
struct stm32_hw_spi_cs *cs = device->parent.user_data;
|
||||||
|
rt_int32_t length = message->length;
|
||||||
|
rt_int32_t data_width = spi_drv->cfg->data_width;
|
||||||
|
|
||||||
|
if (message->cs_take)
|
||||||
|
{
|
||||||
|
HAL_GPIO_WritePin(cs->GPIOx, cs->GPIO_Pin, GPIO_PIN_RESET);
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef BSP_SPI_USING_DMA
|
||||||
|
if(message->length > 32)
|
||||||
|
{
|
||||||
|
if(data_width <= 8)
|
||||||
|
{
|
||||||
|
HAL_StatusTypeDef state;
|
||||||
|
LOG_D("%s dma transfer prepare and start", spi_drv->config->bus_name);
|
||||||
|
LOG_D("%s sendbuf: %X, recvbuf: %X, length: %d",
|
||||||
|
spi_drv->config->bus_name,
|
||||||
|
(uint32_t)message->send_buf,
|
||||||
|
(uint32_t)message->recv_buf, message->length);
|
||||||
|
|
||||||
|
spi_dma_transfer_prepare(device->bus, message);
|
||||||
|
/* start once data exchange in DMA mode */
|
||||||
|
state = HAL_SPI_TransmitReceive_DMA(spi_handle,
|
||||||
|
(uint8_t*)message->send_buf,
|
||||||
|
(uint8_t*)message->recv_buf,
|
||||||
|
message->length);
|
||||||
|
if (state != HAL_OK)
|
||||||
|
{
|
||||||
|
LOG_D("spi flash configuration error : %d", state);
|
||||||
|
message->length = 0;
|
||||||
|
//while(1);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
LOG_D("%s dma transfer done", spi_drv->config->bus_name);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* For simplicity reasons, this example is just waiting till the end of the
|
||||||
|
transfer, but application may perform other tasks while transfer operation
|
||||||
|
is ongoing. */
|
||||||
|
while (HAL_SPI_GetState(spi_handle) != HAL_SPI_STATE_READY);
|
||||||
|
LOG_D("%s get state done", spi_drv->config->bus_name);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
// TODO
|
||||||
|
}
|
||||||
|
} else
|
||||||
|
#endif
|
||||||
|
{
|
||||||
|
if (data_width == 8)
|
||||||
|
{
|
||||||
|
const rt_uint8_t * send_ptr = message->send_buf;
|
||||||
|
rt_uint8_t * recv_ptr = message->recv_buf;
|
||||||
|
|
||||||
|
while (length--)
|
||||||
|
{
|
||||||
|
rt_uint8_t data = ~0;
|
||||||
|
|
||||||
|
if(send_ptr != RT_NULL)
|
||||||
|
{
|
||||||
|
data = *send_ptr++;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* send data once */
|
||||||
|
while (__HAL_SPI_GET_FLAG(spi_handle, SPI_FLAG_TXE) == RESET);
|
||||||
|
*(volatile rt_uint8_t *)(&spi_handle->Instance->DR) = data;
|
||||||
|
|
||||||
|
/* receive data once */
|
||||||
|
#if defined(SOC_SERIES_STM32L4)
|
||||||
|
SET_BIT(spi_handle->Instance->CR2, SPI_RXFIFO_THRESHOLD_HF);
|
||||||
|
#endif
|
||||||
|
while (__HAL_SPI_GET_FLAG(spi_handle, SPI_FLAG_RXNE) == RESET);
|
||||||
|
data = *(volatile rt_uint8_t *)(&spi_handle->Instance->DR);
|
||||||
|
|
||||||
|
if(recv_ptr != RT_NULL)
|
||||||
|
{
|
||||||
|
*recv_ptr++ = data;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
} else
|
||||||
|
{
|
||||||
|
const rt_uint16_t * send_ptr = message->send_buf;
|
||||||
|
rt_uint16_t * recv_ptr = message->recv_buf;
|
||||||
|
|
||||||
|
while (length--)
|
||||||
|
{
|
||||||
|
rt_uint16_t data = ~0;
|
||||||
|
|
||||||
|
if(send_ptr != RT_NULL)
|
||||||
|
{
|
||||||
|
data = *send_ptr++;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* send data once */
|
||||||
|
while (__HAL_SPI_GET_FLAG(spi_handle, SPI_FLAG_TXE) == RESET);
|
||||||
|
*(volatile rt_uint16_t *)(&spi_handle->Instance->DR) = data;
|
||||||
|
|
||||||
|
/* receive data once */
|
||||||
|
#if defined(SOC_SERIES_STM32L4)
|
||||||
|
SET_BIT(spi_handle->Instance->CR2, SPI_RXFIFO_THRESHOLD_HF);
|
||||||
|
#endif
|
||||||
|
while (__HAL_SPI_GET_FLAG(spi_handle, SPI_FLAG_RXNE) == RESET);
|
||||||
|
data = *(volatile rt_uint16_t *)(&spi_handle->Instance->DR);
|
||||||
|
|
||||||
|
if(recv_ptr != RT_NULL)
|
||||||
|
{
|
||||||
|
*recv_ptr++ = data;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Wait until Busy flag is reset before disabling SPI */
|
||||||
|
while (__HAL_SPI_GET_FLAG(spi_handle, SPI_FLAG_BSY) == SET);
|
||||||
|
|
||||||
|
if (message->cs_release)
|
||||||
|
{
|
||||||
|
HAL_GPIO_WritePin(cs->GPIOx, cs->GPIO_Pin, GPIO_PIN_SET);
|
||||||
|
}
|
||||||
|
|
||||||
|
return message->length;
|
||||||
|
}
|
||||||
|
|
||||||
|
static rt_err_t spi_configure(struct rt_spi_device *device,
|
||||||
|
struct rt_spi_configuration *configuration)
|
||||||
|
{
|
||||||
|
RT_ASSERT(device != RT_NULL);
|
||||||
|
RT_ASSERT(configuration != RT_NULL);
|
||||||
|
|
||||||
|
struct stm32_spi *spi_drv = rt_container_of(device->bus, struct stm32_spi, spi_bus);
|
||||||
|
spi_drv->cfg = configuration;
|
||||||
|
|
||||||
|
return stm32_spi_init(spi_drv, configuration);
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct rt_spi_ops stm_spi_ops =
|
||||||
|
{
|
||||||
|
.configure = spi_configure,
|
||||||
|
.xfer = spixfer,
|
||||||
|
};
|
||||||
|
|
||||||
|
static int rt_hw_spi_bus_init(void)
|
||||||
|
{
|
||||||
|
rt_err_t result;
|
||||||
|
for (int i = 0; i < sizeof(spi_config) / sizeof(spi_config[0]); i++)
|
||||||
|
{
|
||||||
|
spi_bus_obj[i].config = &spi_config[i];
|
||||||
|
spi_bus_obj[i].spi_bus.parent.user_data = &spi_config[i];
|
||||||
|
spi_bus_obj[i].handle.Instance = spi_config[i].Instance;
|
||||||
|
|
||||||
|
#ifdef BSP_SPI_USING_DMA
|
||||||
|
/* Configure the DMA handler for Transmission process */
|
||||||
|
spi_bus_obj[i].dma.handle_tx.Instance = spi_config[i].dma_tx.Instance;
|
||||||
|
#if defined(SOC_SERIES_STM32F4)
|
||||||
|
spi_bus_obj[i].dma.handle_tx.Init.Channel = spi_config[i].dma_tx.channel;
|
||||||
|
#elif defined(SOC_SERIES_STM32L4)
|
||||||
|
spi_bus_obj[i].dma.handle_tx.Init.Request = spi_config[i].dma_tx.request;
|
||||||
|
#endif
|
||||||
|
spi_bus_obj[i].dma.handle_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
|
||||||
|
spi_bus_obj[i].dma.handle_tx.Init.PeriphInc = DMA_PINC_DISABLE;
|
||||||
|
spi_bus_obj[i].dma.handle_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
|
||||||
|
spi_bus_obj[i].dma.handle_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
|
||||||
|
spi_bus_obj[i].dma.handle_tx.Init.Mode = DMA_NORMAL;
|
||||||
|
spi_bus_obj[i].dma.handle_tx.Init.Priority = DMA_PRIORITY_LOW;
|
||||||
|
#if defined(SOC_SERIES_STM32F4)
|
||||||
|
spi_bus_obj[i].dma.handle_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
|
||||||
|
spi_bus_obj[i].dma.handle_tx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
|
||||||
|
spi_bus_obj[i].dma.handle_tx.Init.MemBurst = DMA_MBURST_INC4;
|
||||||
|
spi_bus_obj[i].dma.handle_tx.Init.PeriphBurst = DMA_PBURST_INC4;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
spi_bus_obj[i].dma.handle_rx.Instance = spi_config[i].dma_rx.Instance;
|
||||||
|
#if defined(SOC_SERIES_STM32F4)
|
||||||
|
spi_bus_obj[i].dma.handle_rx.Init.Channel = spi_config[i].dma_rx.channel;
|
||||||
|
#elif defined(SOC_SERIES_STM32L4)
|
||||||
|
spi_bus_obj[i].dma.handle_rx.Init.Request = spi_config[i].dma_rx.request;
|
||||||
|
#endif
|
||||||
|
spi_bus_obj[i].dma.handle_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
|
||||||
|
spi_bus_obj[i].dma.handle_rx.Init.PeriphInc = DMA_PINC_DISABLE;
|
||||||
|
spi_bus_obj[i].dma.handle_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
|
||||||
|
spi_bus_obj[i].dma.handle_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
|
||||||
|
spi_bus_obj[i].dma.handle_rx.Init.Mode = DMA_NORMAL;
|
||||||
|
spi_bus_obj[i].dma.handle_rx.Init.Priority = DMA_PRIORITY_HIGH;
|
||||||
|
#if defined(SOC_SERIES_STM32F4)
|
||||||
|
spi_bus_obj[i].dma.handle_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
|
||||||
|
spi_bus_obj[i].dma.handle_rx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
|
||||||
|
spi_bus_obj[i].dma.handle_rx.Init.MemBurst = DMA_MBURST_INC4;
|
||||||
|
spi_bus_obj[i].dma.handle_rx.Init.PeriphBurst = DMA_PBURST_INC4;
|
||||||
|
#endif
|
||||||
|
{
|
||||||
|
rt_uint32_t tmpreg = 0x00U;
|
||||||
|
#if defined(SOC_SERIES_STM32F1)
|
||||||
|
/* enable DMA clock && Delay after an RCC peripheral clock enabling*/
|
||||||
|
SET_BIT(RCC->AHBENR, spi_config[i].dma_rx.dma_rcc);
|
||||||
|
tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_rx.dma_rcc);
|
||||||
|
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L4)
|
||||||
|
SET_BIT(RCC->AHB1ENR, spi_config[i].dma_rx.dma_rcc);
|
||||||
|
/* Delay after an RCC peripheral clock enabling */
|
||||||
|
tmpreg = READ_BIT(RCC->AHB1ENR, spi_config[i].dma_rx.dma_rcc);
|
||||||
|
#endif
|
||||||
|
UNUSED(tmpreg); /* To avoid compiler warnings */
|
||||||
|
}
|
||||||
|
|
||||||
|
LOG_D("%s DMA clock init done", spi_config[i].bus_name);
|
||||||
|
#endif /* BSP_SPI_USING_DMA */
|
||||||
|
|
||||||
|
result = rt_spi_bus_register(&spi_bus_obj[i].spi_bus, spi_config[i].bus_name, &stm_spi_ops);
|
||||||
|
RT_ASSERT(result == RT_EOK);
|
||||||
|
|
||||||
|
LOG_D("%s bus init done", spi_config[i].bus_name);
|
||||||
|
}
|
||||||
|
|
||||||
|
return result;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Attach the spi device to SPI bus, this function must be used after initialization.
|
||||||
|
*/
|
||||||
|
rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, GPIO_TypeDef* cs_gpiox, uint16_t cs_gpio_pin)
|
||||||
|
{
|
||||||
|
RT_ASSERT(bus_name != RT_NULL);
|
||||||
|
RT_ASSERT(device_name != RT_NULL);
|
||||||
|
|
||||||
|
rt_err_t result;
|
||||||
|
struct rt_spi_device *spi_device;
|
||||||
|
struct stm32_hw_spi_cs *cs_pin;
|
||||||
|
|
||||||
|
/* initialize the cs pin && select the slave*/
|
||||||
|
GPIO_InitTypeDef GPIO_Initure;
|
||||||
|
GPIO_Initure.Pin = cs_gpio_pin;
|
||||||
|
GPIO_Initure.Mode = GPIO_MODE_OUTPUT_PP;
|
||||||
|
GPIO_Initure.Pull = GPIO_PULLUP;
|
||||||
|
GPIO_Initure.Speed = GPIO_SPEED_FREQ_HIGH;
|
||||||
|
HAL_GPIO_Init(cs_gpiox, &GPIO_Initure);
|
||||||
|
HAL_GPIO_WritePin(cs_gpiox, cs_gpio_pin, GPIO_PIN_SET);
|
||||||
|
|
||||||
|
/* attach the device to spi bus*/
|
||||||
|
spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
|
||||||
|
RT_ASSERT(spi_device != RT_NULL);
|
||||||
|
cs_pin = (struct stm32_hw_spi_cs *)rt_malloc(sizeof(struct stm32_hw_spi_cs));
|
||||||
|
RT_ASSERT(cs_pin != RT_NULL);
|
||||||
|
cs_pin->GPIOx = cs_gpiox;
|
||||||
|
cs_pin->GPIO_Pin = cs_gpio_pin;
|
||||||
|
result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin);
|
||||||
|
|
||||||
|
if (result != RT_EOK)
|
||||||
|
{
|
||||||
|
LOG_E("%s attach to %s faild, %d\n", device_name, bus_name, result);
|
||||||
|
}
|
||||||
|
|
||||||
|
RT_ASSERT(result == RT_EOK);
|
||||||
|
|
||||||
|
LOG_D("%s attach to %s done", device_name, bus_name);
|
||||||
|
|
||||||
|
return result;
|
||||||
|
}
|
||||||
|
|
||||||
|
#if defined(BSP_USING_SPI1) && defined(BSP_SPI_USING_DMA)
|
||||||
|
/**
|
||||||
|
* @brief This function handles DMA Rx interrupt request.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SPI1_DMA_RX_IRQHandler(void)
|
||||||
|
{
|
||||||
|
/* enter interrupt */
|
||||||
|
rt_interrupt_enter();
|
||||||
|
|
||||||
|
HAL_DMA_IRQHandler(&spi_bus_obj[SPI1_INDEX].dma.handle_rx);
|
||||||
|
|
||||||
|
/* leave interrupt */
|
||||||
|
rt_interrupt_leave();
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function handles DMA Tx interrupt request.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SPI1_DMA_TX_IRQHandler(void)
|
||||||
|
{
|
||||||
|
/* enter interrupt */
|
||||||
|
rt_interrupt_enter();
|
||||||
|
|
||||||
|
HAL_DMA_IRQHandler(&spi_bus_obj[SPI1_INDEX].dma.handle_tx);
|
||||||
|
|
||||||
|
/* leave interrupt */
|
||||||
|
rt_interrupt_leave();
|
||||||
|
}
|
||||||
|
#endif /* defined(BSP_USING_SPI1) && defined(BSP_SPI_USING_DMA) */
|
||||||
|
|
||||||
|
#if defined(BSP_USING_SPI2) && defined(BSP_SPI_USING_DMA)
|
||||||
|
/**
|
||||||
|
* @brief This function handles DMA Rx interrupt request.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SPI2_DMA_RX_IRQHandler(void)
|
||||||
|
{
|
||||||
|
/* enter interrupt */
|
||||||
|
rt_interrupt_enter();
|
||||||
|
|
||||||
|
HAL_DMA_IRQHandler(&spi_bus_obj[SPI2_INDEX].dma.handle_rx);
|
||||||
|
|
||||||
|
/* leave interrupt */
|
||||||
|
rt_interrupt_leave();
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function handles DMA Tx interrupt request.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SPI2_DMA_TX_IRQHandler(void)
|
||||||
|
{
|
||||||
|
/* enter interrupt */
|
||||||
|
rt_interrupt_enter();
|
||||||
|
|
||||||
|
HAL_DMA_IRQHandler(&spi_bus_obj[SPI2_INDEX].dma.handle_tx);
|
||||||
|
|
||||||
|
/* leave interrupt */
|
||||||
|
rt_interrupt_leave();
|
||||||
|
}
|
||||||
|
#endif /* defined(BSP_USING_SPI2) && defined(BSP_SPI_USING_DMA) */
|
||||||
|
|
||||||
|
#if defined(BSP_USING_SPI3) && defined(BSP_SPI_USING_DMA)
|
||||||
|
/**
|
||||||
|
* @brief This function handles DMA Rx interrupt request.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SPI3_DMA_RX_IRQHandler(void)
|
||||||
|
{
|
||||||
|
/* enter interrupt */
|
||||||
|
rt_interrupt_enter();
|
||||||
|
|
||||||
|
HAL_DMA_IRQHandler(&spi_bus_obj[SPI3_INDEX].dma.handle_rx);
|
||||||
|
|
||||||
|
/* leave interrupt */
|
||||||
|
rt_interrupt_leave();
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function handles DMA Tx interrupt request.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SPI3_DMA_TX_IRQHandler(void)
|
||||||
|
{
|
||||||
|
/* enter interrupt */
|
||||||
|
rt_interrupt_enter();
|
||||||
|
|
||||||
|
HAL_DMA_IRQHandler(&spi_bus_obj[SPI3_INDEX].dma.handle_tx);
|
||||||
|
|
||||||
|
/* leave interrupt */
|
||||||
|
rt_interrupt_leave();
|
||||||
|
}
|
||||||
|
#endif /* defined(BSP_USING_SPI3) && defined(BSP_SPI_USING_DMA) */
|
||||||
|
|
||||||
|
|
||||||
|
#if defined(BSP_USING_SPI4) && defined(BSP_SPI_USING_DMA)
|
||||||
|
/**
|
||||||
|
* @brief This function handles DMA Rx interrupt request.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SPI4_DMA_RX_IRQHandler(void)
|
||||||
|
{
|
||||||
|
/* enter interrupt */
|
||||||
|
rt_interrupt_enter();
|
||||||
|
|
||||||
|
HAL_DMA_IRQHandler(&spi_bus_obj[SPI4_INDEX].dma.handle_rx);
|
||||||
|
|
||||||
|
/* leave interrupt */
|
||||||
|
rt_interrupt_leave();
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function handles DMA Tx interrupt request.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SPI4_DMA_TX_IRQHandler(void)
|
||||||
|
{
|
||||||
|
/* enter interrupt */
|
||||||
|
rt_interrupt_enter();
|
||||||
|
|
||||||
|
HAL_DMA_IRQHandler(&spi_bus_obj[SPI4_INDEX].dma.handle_tx);
|
||||||
|
|
||||||
|
/* leave interrupt */
|
||||||
|
rt_interrupt_leave();
|
||||||
|
}
|
||||||
|
#endif /* defined(BSP_USING_SPI4) && defined(BSP_SPI_USING_DMA) */
|
||||||
|
|
||||||
|
#if defined(BSP_USING_SPI5) && defined(BSP_SPI_USING_DMA)
|
||||||
|
/**
|
||||||
|
* @brief This function handles DMA Rx interrupt request.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SPI5_DMA_RX_IRQHandler(void)
|
||||||
|
{
|
||||||
|
/* enter interrupt */
|
||||||
|
rt_interrupt_enter();
|
||||||
|
|
||||||
|
HAL_DMA_IRQHandler(&spi_bus_obj[SPI5_INDEX].dma.handle_rx);
|
||||||
|
|
||||||
|
/* leave interrupt */
|
||||||
|
rt_interrupt_leave();
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function handles DMA Tx interrupt request.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SPI5_DMA_TX_IRQHandler(void)
|
||||||
|
{
|
||||||
|
/* enter interrupt */
|
||||||
|
rt_interrupt_enter();
|
||||||
|
|
||||||
|
HAL_DMA_IRQHandler(&spi_bus_obj[SPI5_INDEX].dma.handle_tx);
|
||||||
|
|
||||||
|
/* leave interrupt */
|
||||||
|
rt_interrupt_leave();
|
||||||
|
}
|
||||||
|
#endif /* defined(BSP_USING_SPI5) && defined(BSP_SPI_USING_DMA) */
|
||||||
|
|
||||||
|
int rt_hw_spi_init(void)
|
||||||
|
{
|
||||||
|
return rt_hw_spi_bus_init();
|
||||||
|
}
|
||||||
|
INIT_BOARD_EXPORT(rt_hw_spi_init);
|
||||||
|
|
||||||
|
#endif /* BSP_USING_SPI1 || BSP_USING_SPI2 || BSP_USING_SPI3 || BSP_USING_SPI4 || BSP_USING_SPI5 */
|
||||||
|
#endif /* RT_USING_SPI */
|
||||||
|
|
@ -0,0 +1,61 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* Change Logs:
|
||||||
|
* Date Author Notes
|
||||||
|
* 2018-11-5 SummerGift change to new framework
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __DRV_SPI_H_
|
||||||
|
#define __DRV_SPI_H_
|
||||||
|
|
||||||
|
#include <rtthread.h>
|
||||||
|
#include "rtdevice.h"
|
||||||
|
#include <rthw.h>
|
||||||
|
#include <drv_common.h>
|
||||||
|
#include "drv_dma.h"
|
||||||
|
|
||||||
|
rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, GPIO_TypeDef* cs_gpiox, uint16_t cs_gpio_pin);
|
||||||
|
|
||||||
|
struct stm32_hw_spi_cs
|
||||||
|
{
|
||||||
|
GPIO_TypeDef* GPIOx;
|
||||||
|
uint16_t GPIO_Pin;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct stm32_spi_config
|
||||||
|
{
|
||||||
|
SPI_TypeDef *Instance;
|
||||||
|
char *bus_name;
|
||||||
|
struct dma_config dma_rx, dma_tx;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct stm32_spi_device
|
||||||
|
{
|
||||||
|
rt_uint32_t pin;
|
||||||
|
char *bus_name;
|
||||||
|
char *device_name;
|
||||||
|
};
|
||||||
|
|
||||||
|
/* stm32 spi dirver class */
|
||||||
|
struct stm32_spi
|
||||||
|
{
|
||||||
|
SPI_HandleTypeDef handle;
|
||||||
|
const struct stm32_spi_config *config;
|
||||||
|
struct rt_spi_configuration *cfg;
|
||||||
|
|
||||||
|
#ifdef BSP_SPI_USING_DMA
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
DMA_HandleTypeDef handle_rx;
|
||||||
|
DMA_HandleTypeDef handle_tx;
|
||||||
|
} dma;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
struct rt_spi_bus spi_bus;
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif /*__DRV_SPI_H_ */
|
||||||
|
|
@ -0,0 +1,599 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* Change Logs:
|
||||||
|
* Date Author Notes
|
||||||
|
* 2018-10-30 SummerGift change to new framework
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "board.h"
|
||||||
|
#include "drv_usart.h"
|
||||||
|
#include "drv_config.h"
|
||||||
|
|
||||||
|
#ifdef RT_USING_SERIAL
|
||||||
|
|
||||||
|
//#define DRV_DEBUG
|
||||||
|
#define LOG_TAG "drv.usart"
|
||||||
|
#include <drv_log.h>
|
||||||
|
|
||||||
|
#if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3) && !defined(BSP_USING_UART4) && !defined(BSP_USING_UART5)
|
||||||
|
#error "Please define at least one BSP_USING_UARTx"
|
||||||
|
/* this driver can be disabled at menuconfig → RT-Thread Components → Device Drivers */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef BSP_UART_USING_DMA_RX
|
||||||
|
static void stm32_dma_config(struct rt_serial_device *serial);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
enum
|
||||||
|
{
|
||||||
|
#ifdef BSP_USING_UART1
|
||||||
|
UART1_INDEX,
|
||||||
|
#endif
|
||||||
|
#ifdef BSP_USING_UART2
|
||||||
|
UART2_INDEX,
|
||||||
|
#endif
|
||||||
|
#ifdef BSP_USING_UART3
|
||||||
|
UART3_INDEX,
|
||||||
|
#endif
|
||||||
|
#ifdef BSP_USING_UART4
|
||||||
|
UART4_INDEX,
|
||||||
|
#endif
|
||||||
|
#ifdef BSP_USING_UART5
|
||||||
|
UART5_INDEX,
|
||||||
|
#endif
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct stm32_uart_config uart_config[] =
|
||||||
|
{
|
||||||
|
#ifdef BSP_USING_UART1
|
||||||
|
UART1_CONFIG,
|
||||||
|
#endif
|
||||||
|
#ifdef BSP_USING_UART2
|
||||||
|
UART2_CONFIG,
|
||||||
|
#endif
|
||||||
|
#ifdef BSP_USING_UART3
|
||||||
|
UART3_CONFIG,
|
||||||
|
#endif
|
||||||
|
#ifdef BSP_USING_UART4
|
||||||
|
UART4_CONFIG,
|
||||||
|
#endif
|
||||||
|
#ifdef BSP_USING_UART5
|
||||||
|
UART5_CONFIG,
|
||||||
|
#endif
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct stm32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])];
|
||||||
|
|
||||||
|
static rt_err_t stm32_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
|
||||||
|
{
|
||||||
|
struct stm32_uart *uart;
|
||||||
|
RT_ASSERT(serial != RT_NULL);
|
||||||
|
RT_ASSERT(cfg != RT_NULL);
|
||||||
|
uart = (struct stm32_uart *)serial->parent.user_data;
|
||||||
|
RT_ASSERT(uart != RT_NULL);
|
||||||
|
|
||||||
|
uart->handle.Instance = uart->config->Instance;
|
||||||
|
uart->handle.Init.BaudRate = cfg->baud_rate;
|
||||||
|
uart->handle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
||||||
|
uart->handle.Init.Mode = UART_MODE_TX_RX;
|
||||||
|
uart->handle.Init.OverSampling = UART_OVERSAMPLING_16;
|
||||||
|
switch (cfg->data_bits)
|
||||||
|
{
|
||||||
|
case DATA_BITS_8:
|
||||||
|
uart->handle.Init.WordLength = UART_WORDLENGTH_8B;
|
||||||
|
break;
|
||||||
|
case DATA_BITS_9:
|
||||||
|
uart->handle.Init.WordLength = UART_WORDLENGTH_9B;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
uart->handle.Init.WordLength = UART_WORDLENGTH_8B;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
switch (cfg->stop_bits)
|
||||||
|
{
|
||||||
|
case STOP_BITS_1:
|
||||||
|
uart->handle.Init.StopBits = UART_STOPBITS_1;
|
||||||
|
break;
|
||||||
|
case STOP_BITS_2:
|
||||||
|
uart->handle.Init.StopBits = UART_STOPBITS_2;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
uart->handle.Init.StopBits = UART_STOPBITS_1;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
switch (cfg->parity)
|
||||||
|
{
|
||||||
|
case PARITY_NONE:
|
||||||
|
uart->handle.Init.Parity = UART_PARITY_NONE;
|
||||||
|
break;
|
||||||
|
case PARITY_ODD:
|
||||||
|
uart->handle.Init.Parity = UART_PARITY_ODD;
|
||||||
|
break;
|
||||||
|
case PARITY_EVEN:
|
||||||
|
uart->handle.Init.Parity = UART_PARITY_EVEN;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
uart->handle.Init.Parity = UART_PARITY_NONE;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (HAL_UART_Init(&uart->handle) != HAL_OK)
|
||||||
|
{
|
||||||
|
return -RT_ERROR;
|
||||||
|
}
|
||||||
|
__HAL_UART_CLEAR_FLAG(&(uart->handle), UART_FLAG_TC);
|
||||||
|
return RT_EOK;
|
||||||
|
}
|
||||||
|
|
||||||
|
static rt_err_t stm32_control(struct rt_serial_device *serial, int cmd, void *arg)
|
||||||
|
{
|
||||||
|
struct stm32_uart *uart;
|
||||||
|
#ifdef BSP_UART_USING_DMA_RX
|
||||||
|
rt_ubase_t ctrl_arg = (rt_ubase_t)arg;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
RT_ASSERT(serial != RT_NULL);
|
||||||
|
uart = (struct stm32_uart *)serial->parent.user_data;
|
||||||
|
RT_ASSERT(uart != RT_NULL);
|
||||||
|
|
||||||
|
switch (cmd)
|
||||||
|
{
|
||||||
|
/* disable interrupt */
|
||||||
|
case RT_DEVICE_CTRL_CLR_INT:
|
||||||
|
/* disable rx irq */
|
||||||
|
NVIC_DisableIRQ(uart->config->irq_type);
|
||||||
|
/* disable interrupt */
|
||||||
|
__HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_RXNE);
|
||||||
|
break;
|
||||||
|
/* enable interrupt */
|
||||||
|
case RT_DEVICE_CTRL_SET_INT:
|
||||||
|
/* enable rx irq */
|
||||||
|
NVIC_EnableIRQ(uart->config->irq_type);
|
||||||
|
/* enable interrupt */
|
||||||
|
__HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_RXNE);
|
||||||
|
break;
|
||||||
|
|
||||||
|
#ifdef BSP_UART_USING_DMA_RX
|
||||||
|
case RT_DEVICE_CTRL_CONFIG:
|
||||||
|
if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX)
|
||||||
|
{
|
||||||
|
stm32_dma_config(serial);
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
return RT_EOK;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int stm32_putc(struct rt_serial_device *serial, char c)
|
||||||
|
{
|
||||||
|
struct stm32_uart *uart;
|
||||||
|
RT_ASSERT(serial != RT_NULL);
|
||||||
|
|
||||||
|
uart = (struct stm32_uart *)serial->parent.user_data;
|
||||||
|
#if defined(SOC_SERIES_STM32L4)
|
||||||
|
uart->handle.Instance->TDR = c;
|
||||||
|
#else
|
||||||
|
uart->handle.Instance->DR = c;
|
||||||
|
#endif
|
||||||
|
while (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TC) == RESET);
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int stm32_getc(struct rt_serial_device *serial)
|
||||||
|
{
|
||||||
|
int ch;
|
||||||
|
struct stm32_uart *uart;
|
||||||
|
RT_ASSERT(serial != RT_NULL);
|
||||||
|
uart = (struct stm32_uart *)serial->parent.user_data;
|
||||||
|
RT_ASSERT(uart != RT_NULL);
|
||||||
|
|
||||||
|
ch = -1;
|
||||||
|
if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET)
|
||||||
|
{
|
||||||
|
#if defined(SOC_SERIES_STM32L4)
|
||||||
|
ch = uart->handle.Instance->RDR & 0xff;
|
||||||
|
#else
|
||||||
|
ch = uart->handle.Instance->DR & 0xff;
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
return ch;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct rt_uart_ops stm32_uart_ops =
|
||||||
|
{
|
||||||
|
.configure = stm32_configure,
|
||||||
|
.control = stm32_control,
|
||||||
|
.putc = stm32_putc,
|
||||||
|
.getc = stm32_getc,
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Uart common interrupt process. This need add to uart ISR.
|
||||||
|
*
|
||||||
|
* @param serial serial device
|
||||||
|
*/
|
||||||
|
static void uart_isr(struct rt_serial_device *serial)
|
||||||
|
{
|
||||||
|
struct stm32_uart *uart;
|
||||||
|
#ifdef BSP_UART_USING_DMA_RX
|
||||||
|
rt_size_t recv_total_index, recv_len;
|
||||||
|
rt_base_t level;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
RT_ASSERT(serial != RT_NULL);
|
||||||
|
|
||||||
|
uart = (struct stm32_uart *) serial->parent.user_data;
|
||||||
|
RT_ASSERT(uart != RT_NULL);
|
||||||
|
|
||||||
|
/* UART in mode Receiver -------------------------------------------------*/
|
||||||
|
if ((__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET) &&
|
||||||
|
(__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_RXNE) != RESET))
|
||||||
|
{
|
||||||
|
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
|
||||||
|
/* Clear RXNE interrupt flag */
|
||||||
|
__HAL_UART_CLEAR_FLAG(&(uart->handle), UART_FLAG_RXNE);
|
||||||
|
}
|
||||||
|
#ifdef BSP_UART_USING_DMA_RX
|
||||||
|
else if ((__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_IDLE) != RESET) &&
|
||||||
|
(__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_IDLE) != RESET))
|
||||||
|
{
|
||||||
|
level = rt_hw_interrupt_disable();
|
||||||
|
recv_total_index = serial->config.bufsz - __HAL_DMA_GET_COUNTER(&(uart->dma.handle));
|
||||||
|
recv_len = recv_total_index - uart->dma.last_index;
|
||||||
|
uart->dma.last_index = recv_total_index;
|
||||||
|
rt_hw_interrupt_enable(level);
|
||||||
|
|
||||||
|
if (recv_len)
|
||||||
|
{
|
||||||
|
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
|
||||||
|
}
|
||||||
|
|
||||||
|
__HAL_UART_CLEAR_FLAG(&(uart->handle), UART_FLAG_IDLE);
|
||||||
|
rt_uint32_t ch;
|
||||||
|
#if defined(SOC_SERIES_STM32L4)
|
||||||
|
ch = uart->handle.Instance->RDR;
|
||||||
|
#else
|
||||||
|
ch = uart->handle.Instance->DR;
|
||||||
|
#endif
|
||||||
|
ch = ch;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
else
|
||||||
|
{
|
||||||
|
if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_ORE) != RESET)
|
||||||
|
{
|
||||||
|
__HAL_UART_CLEAR_FLAG(&(uart->handle), UART_FLAG_ORE);
|
||||||
|
}
|
||||||
|
if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_NE) != RESET)
|
||||||
|
{
|
||||||
|
__HAL_UART_CLEAR_FLAG(&(uart->handle), UART_FLAG_NE);
|
||||||
|
}
|
||||||
|
if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_FE) != RESET)
|
||||||
|
{
|
||||||
|
__HAL_UART_CLEAR_FLAG(&(uart->handle), UART_FLAG_FE);
|
||||||
|
}
|
||||||
|
if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_PE) != RESET)
|
||||||
|
{
|
||||||
|
__HAL_UART_CLEAR_FLAG(&(uart->handle), UART_FLAG_PE);
|
||||||
|
}
|
||||||
|
if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_CTS) != RESET)
|
||||||
|
{
|
||||||
|
__HAL_UART_CLEAR_FLAG(&(uart->handle), UART_FLAG_CTS);
|
||||||
|
}
|
||||||
|
#if !defined(SOC_SERIES_STM32L4)
|
||||||
|
if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_LBD) != RESET)
|
||||||
|
{
|
||||||
|
__HAL_UART_CLEAR_FLAG(&(uart->handle), UART_FLAG_LBD);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TXE) != RESET)
|
||||||
|
{
|
||||||
|
__HAL_UART_CLEAR_FLAG(&(uart->handle), UART_FLAG_TXE);
|
||||||
|
}
|
||||||
|
if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TC) != RESET)
|
||||||
|
{
|
||||||
|
__HAL_UART_CLEAR_FLAG(&(uart->handle), UART_FLAG_TC);
|
||||||
|
}
|
||||||
|
if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET)
|
||||||
|
{
|
||||||
|
__HAL_UART_CLEAR_FLAG(&(uart->handle), UART_FLAG_RXNE);
|
||||||
|
}
|
||||||
|
if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_IDLE) != RESET)
|
||||||
|
{
|
||||||
|
__HAL_UART_CLEAR_FLAG(&(uart->handle), UART_FLAG_IDLE);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
#if defined(BSP_USING_UART1)
|
||||||
|
void USART1_IRQHandler(void)
|
||||||
|
{
|
||||||
|
/* enter interrupt */
|
||||||
|
rt_interrupt_enter();
|
||||||
|
|
||||||
|
uart_isr(&(uart_obj[UART1_INDEX].serial));
|
||||||
|
|
||||||
|
/* leave interrupt */
|
||||||
|
rt_interrupt_leave();
|
||||||
|
}
|
||||||
|
#if defined(BSP_UART_USING_DMA_RX) && defined(USART1_RX_DMA_ISR)
|
||||||
|
void USART1_RX_DMA_ISR(void)
|
||||||
|
{
|
||||||
|
/* enter interrupt */
|
||||||
|
rt_interrupt_enter();
|
||||||
|
|
||||||
|
HAL_DMA_IRQHandler(&uart_obj[UART1_INDEX].dma.handle);
|
||||||
|
|
||||||
|
/* leave interrupt */
|
||||||
|
rt_interrupt_leave();
|
||||||
|
}
|
||||||
|
#endif /* defined(BSP_UART_USING_DMA_RX) && defined(USART1_RX_DMA_ISR) */
|
||||||
|
#endif /* BSP_USING_UART1 */
|
||||||
|
|
||||||
|
#if defined(BSP_USING_UART2)
|
||||||
|
void USART2_IRQHandler(void)
|
||||||
|
{
|
||||||
|
/* enter interrupt */
|
||||||
|
rt_interrupt_enter();
|
||||||
|
|
||||||
|
uart_isr(&(uart_obj[UART2_INDEX].serial));
|
||||||
|
|
||||||
|
/* leave interrupt */
|
||||||
|
rt_interrupt_leave();
|
||||||
|
}
|
||||||
|
#if defined(BSP_UART_USING_DMA_RX) && defined(USART2_RX_DMA_ISR)
|
||||||
|
void USART2_RX_DMA_ISR(void)
|
||||||
|
{
|
||||||
|
/* enter interrupt */
|
||||||
|
rt_interrupt_enter();
|
||||||
|
|
||||||
|
HAL_DMA_IRQHandler(&uart_obj[UART2_INDEX].dma.handle);
|
||||||
|
|
||||||
|
/* leave interrupt */
|
||||||
|
rt_interrupt_leave();
|
||||||
|
}
|
||||||
|
#endif /* defined(BSP_UART_USING_DMA_RX) && defined(USART2_RX_DMA_ISR) */
|
||||||
|
#endif /* BSP_USING_UART2 */
|
||||||
|
|
||||||
|
#if defined(BSP_USING_UART3)
|
||||||
|
void USART3_IRQHandler(void)
|
||||||
|
{
|
||||||
|
/* enter interrupt */
|
||||||
|
rt_interrupt_enter();
|
||||||
|
|
||||||
|
uart_isr(&(uart_obj[UART3_INDEX].serial));
|
||||||
|
|
||||||
|
/* leave interrupt */
|
||||||
|
rt_interrupt_leave();
|
||||||
|
}
|
||||||
|
#if defined(BSP_UART_USING_DMA_RX) && defined(USART3_RX_DMA_ISR)
|
||||||
|
void USART3_RX_DMA_ISR(void)
|
||||||
|
{
|
||||||
|
/* enter interrupt */
|
||||||
|
rt_interrupt_enter();
|
||||||
|
|
||||||
|
HAL_DMA_IRQHandler(&uart_obj[UART3_INDEX].dma.handle);
|
||||||
|
|
||||||
|
/* leave interrupt */
|
||||||
|
rt_interrupt_leave();
|
||||||
|
}
|
||||||
|
#endif /* defined(BSP_UART_USING_DMA_RX) && defined(USART3_RX_DMA_ISR) */
|
||||||
|
#endif /* BSP_USING_UART3*/
|
||||||
|
|
||||||
|
#if defined(BSP_USING_UART4)
|
||||||
|
void UART4_IRQHandler(void)
|
||||||
|
{
|
||||||
|
/* enter interrupt */
|
||||||
|
rt_interrupt_enter();
|
||||||
|
|
||||||
|
uart_isr(&(uart_obj[UART4_INDEX].serial));
|
||||||
|
|
||||||
|
/* leave interrupt */
|
||||||
|
rt_interrupt_leave();
|
||||||
|
}
|
||||||
|
#if defined(BSP_UART_USING_DMA_RX) && defined(USART1_RX_DMA_ISR)
|
||||||
|
void USART4_RX_DMA_ISR(void)
|
||||||
|
{
|
||||||
|
/* enter interrupt */
|
||||||
|
rt_interrupt_enter();
|
||||||
|
|
||||||
|
HAL_DMA_IRQHandler(&uart_obj[UART4_INDEX].dma.handle);
|
||||||
|
|
||||||
|
/* leave interrupt */
|
||||||
|
rt_interrupt_leave();
|
||||||
|
}
|
||||||
|
#endif /* defined(BSP_UART_USING_DMA_RX) && defined(USART4_RX_DMA_ISR) */
|
||||||
|
#endif /* BSP_USING_UART4*/
|
||||||
|
|
||||||
|
#if defined(BSP_USING_UART5)
|
||||||
|
void UART5_IRQHandler(void)
|
||||||
|
{
|
||||||
|
/* enter interrupt */
|
||||||
|
rt_interrupt_enter();
|
||||||
|
|
||||||
|
uart_isr(&(uart_obj[UART5_INDEX].serial));
|
||||||
|
|
||||||
|
/* leave interrupt */
|
||||||
|
rt_interrupt_leave();
|
||||||
|
}
|
||||||
|
#if defined(BSP_UART_USING_DMA_RX) && defined(USART5_RX_DMA_ISR)
|
||||||
|
void USART5_RX_DMA_ISR(void)
|
||||||
|
{
|
||||||
|
/* enter interrupt */
|
||||||
|
rt_interrupt_enter();
|
||||||
|
|
||||||
|
HAL_DMA_IRQHandler(&uart_obj[UART5_INDEX].dma.handle);
|
||||||
|
|
||||||
|
/* leave interrupt */
|
||||||
|
rt_interrupt_leave();
|
||||||
|
}
|
||||||
|
#endif /* defined(BSP_UART_USING_DMA_RX) && defined(USART5_RX_DMA_ISR) */
|
||||||
|
#endif /* BSP_USING_UART5*/
|
||||||
|
|
||||||
|
#ifdef BSP_UART_USING_DMA_RX
|
||||||
|
static void stm32_dma_config(struct rt_serial_device *serial)
|
||||||
|
{
|
||||||
|
RT_ASSERT(serial != RT_NULL);
|
||||||
|
struct stm32_uart *uart = (struct stm32_uart *)serial->parent.user_data;
|
||||||
|
RT_ASSERT(uart != RT_NULL);
|
||||||
|
struct rt_serial_rx_fifo *rx_fifo;
|
||||||
|
|
||||||
|
LOG_D("%s dma config start", uart->config->name);
|
||||||
|
|
||||||
|
{
|
||||||
|
rt_uint32_t tmpreg= 0x00U;
|
||||||
|
#if defined(SOC_SERIES_STM32F1)
|
||||||
|
/* enable DMA clock && Delay after an RCC peripheral clock enabling*/
|
||||||
|
SET_BIT(RCC->AHBENR, uart->config->dma_rcc);
|
||||||
|
tmpreg = READ_BIT(RCC->AHBENR, uart->config->dma_rcc);
|
||||||
|
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L4)
|
||||||
|
/* enable DMA clock && Delay after an RCC peripheral clock enabling*/
|
||||||
|
SET_BIT(RCC->AHB1ENR, uart->config->dma_rcc);
|
||||||
|
tmpreg = READ_BIT(RCC->AHB1ENR, uart->config->dma_rcc);
|
||||||
|
#endif
|
||||||
|
UNUSED(tmpreg); /* To avoid compiler warnings */
|
||||||
|
}
|
||||||
|
|
||||||
|
__HAL_LINKDMA(&(uart->handle), hdmarx, uart->dma.handle);
|
||||||
|
|
||||||
|
#if defined(SOC_SERIES_STM32F1)
|
||||||
|
uart->dma.handle.Instance = uart->config->dma.Instance;
|
||||||
|
#elif defined(SOC_SERIES_STM32F4)
|
||||||
|
uart->dma.handle.Instance = uart->config->dma.Instance;
|
||||||
|
uart->dma.handle.Init.Channel = uart->config->dma.stream_channel.channel;
|
||||||
|
#elif defined(SOC_SERIES_STM32L4)
|
||||||
|
uart->dma.handle.Instance = uart->config->dma.Instance;
|
||||||
|
uart->dma.handle.Init.Request = uart->config->dma.channel_request.request;
|
||||||
|
#endif
|
||||||
|
uart->dma.handle.Init.Direction = DMA_PERIPH_TO_MEMORY;
|
||||||
|
uart->dma.handle.Init.PeriphInc = DMA_PINC_DISABLE;
|
||||||
|
uart->dma.handle.Init.MemInc = DMA_MINC_ENABLE;
|
||||||
|
uart->dma.handle.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
|
||||||
|
uart->dma.handle.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
|
||||||
|
uart->dma.handle.Init.Mode = DMA_CIRCULAR;
|
||||||
|
uart->dma.handle.Init.Priority = DMA_PRIORITY_MEDIUM;
|
||||||
|
#if defined(SOC_SERIES_STM32F4)
|
||||||
|
uart->dma.handle.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
|
||||||
|
#endif
|
||||||
|
if (HAL_DMA_DeInit(&(uart->dma.handle)) != HAL_OK)
|
||||||
|
{
|
||||||
|
RT_ASSERT(0);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (HAL_DMA_Init(&(uart->dma.handle)) != HAL_OK)
|
||||||
|
{
|
||||||
|
RT_ASSERT(0);
|
||||||
|
}
|
||||||
|
|
||||||
|
rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
|
||||||
|
|
||||||
|
/* Start DMA transfer */
|
||||||
|
if (HAL_UART_Receive_DMA(&(uart->handle), rx_fifo->buffer, serial->config.bufsz) != HAL_OK)
|
||||||
|
{
|
||||||
|
/* Transfer error in reception process */
|
||||||
|
RT_ASSERT(0);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* enable interrupt */
|
||||||
|
__HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_IDLE);
|
||||||
|
|
||||||
|
/* enable rx irq */
|
||||||
|
HAL_NVIC_SetPriority(uart->config->dma_irq, 1, 0);
|
||||||
|
HAL_NVIC_EnableIRQ(uart->config->dma_irq);
|
||||||
|
|
||||||
|
HAL_NVIC_SetPriority(uart->config->irq_type, 0, 0);
|
||||||
|
HAL_NVIC_EnableIRQ(uart->config->irq_type);
|
||||||
|
|
||||||
|
LOG_D("%s dma RX instance: %x", uart->config->name, uart->dma.handle.Instance);
|
||||||
|
LOG_D("%s dma config done", uart->config->name);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief UART error callbacks
|
||||||
|
* @param huart: UART handle
|
||||||
|
* @note This example shows a simple way to report transfer error, and you can
|
||||||
|
* add your own implementation.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
|
||||||
|
{
|
||||||
|
RT_ASSERT(huart != NULL);
|
||||||
|
struct stm32_uart *uart = (struct stm32_uart *)huart;
|
||||||
|
LOG_D("%s: %s %d\n", __FUNCTION__, uart->config->name, huart->ErrorCode);
|
||||||
|
UNUSED(uart);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Rx Transfer completed callback
|
||||||
|
* @param huart: UART handle
|
||||||
|
* @note This example shows a simple way to report end of DMA Rx transfer, and
|
||||||
|
* you can add your own implementation.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
|
||||||
|
{
|
||||||
|
struct rt_serial_device *serial;
|
||||||
|
struct stm32_uart *uart;
|
||||||
|
rt_size_t recv_len;
|
||||||
|
rt_base_t level;
|
||||||
|
|
||||||
|
RT_ASSERT(huart != NULL);
|
||||||
|
uart = (struct stm32_uart *)huart;
|
||||||
|
serial = &uart->serial;
|
||||||
|
|
||||||
|
level = rt_hw_interrupt_disable();
|
||||||
|
|
||||||
|
recv_len = serial->config.bufsz - uart->dma.last_index;
|
||||||
|
uart->dma.last_index = 0;
|
||||||
|
|
||||||
|
rt_hw_interrupt_enable(level);
|
||||||
|
if (recv_len)
|
||||||
|
{
|
||||||
|
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif /* BSP_UART_USING_DMA_RX */
|
||||||
|
|
||||||
|
int rt_hw_usart_init(void)
|
||||||
|
{
|
||||||
|
rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct stm32_uart);
|
||||||
|
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
|
||||||
|
|
||||||
|
rt_err_t result = 0;
|
||||||
|
|
||||||
|
for (int i = 0; i < obj_num; i++)
|
||||||
|
{
|
||||||
|
uart_obj[i].config = &uart_config[i];
|
||||||
|
uart_obj[i].serial.ops = &stm32_uart_ops;
|
||||||
|
uart_obj[i].serial.config = config;
|
||||||
|
|
||||||
|
/* Determines whether a serial instance supports DMA */
|
||||||
|
if(uart_obj[i].config->dma.Instance != DMA_NOT_AVAILABLE)
|
||||||
|
{
|
||||||
|
/* register UART device */
|
||||||
|
result = rt_hw_serial_register(&uart_obj[i].serial,uart_obj[i].config->name,
|
||||||
|
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX
|
||||||
|
#if defined(BSP_UART_USING_DMA_RX)
|
||||||
|
| RT_DEVICE_FLAG_DMA_RX
|
||||||
|
#endif
|
||||||
|
,&uart_obj[i]);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* register UART device */
|
||||||
|
result = rt_hw_serial_register(&uart_obj[i].serial,uart_obj[i].config->name,
|
||||||
|
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX
|
||||||
|
,&uart_obj[i]);
|
||||||
|
}
|
||||||
|
RT_ASSERT(result == RT_EOK);
|
||||||
|
}
|
||||||
|
|
||||||
|
return result;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* RT_USING_SERIAL */
|
||||||
|
|
@ -0,0 +1,84 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* Change Logs:
|
||||||
|
* Date Author Notes
|
||||||
|
* 2018.10.30 SummerGift change to new framework
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __DRV_USART_H__
|
||||||
|
#define __DRV_USART_H__
|
||||||
|
|
||||||
|
#include <rtthread.h>
|
||||||
|
#include "rtdevice.h"
|
||||||
|
#include <rthw.h>
|
||||||
|
#include <drv_common.h>
|
||||||
|
|
||||||
|
int rt_hw_usart_init(void);
|
||||||
|
|
||||||
|
#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4)
|
||||||
|
#define DMA_INSTANCE_TYPE DMA_Channel_TypeDef
|
||||||
|
#elif defined(SOC_SERIES_STM32F4)
|
||||||
|
#define DMA_INSTANCE_TYPE DMA_Stream_TypeDef
|
||||||
|
#endif /* defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) */
|
||||||
|
|
||||||
|
/* stm32 config class */
|
||||||
|
struct stm32_uart_config
|
||||||
|
{
|
||||||
|
const char *name;
|
||||||
|
USART_TypeDef *Instance;
|
||||||
|
IRQn_Type irq_type;
|
||||||
|
|
||||||
|
union {
|
||||||
|
DMA_INSTANCE_TYPE *Instance;
|
||||||
|
|
||||||
|
#if defined(SOC_SERIES_STM32F1)
|
||||||
|
/* the DMA config has channel only, such as on STM32F1xx */
|
||||||
|
struct {
|
||||||
|
DMA_INSTANCE_TYPE *Instance;
|
||||||
|
} channel;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(SOC_SERIES_STM32F4)
|
||||||
|
/* the DMA config has stream and channel, such as on STM32F4xx */
|
||||||
|
struct {
|
||||||
|
DMA_INSTANCE_TYPE *Instance;
|
||||||
|
rt_uint32_t channel;
|
||||||
|
} stream_channel;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(SOC_SERIES_STM32L4)
|
||||||
|
/* the DMA config has channel and request, such as on STM32L4xx */
|
||||||
|
struct {
|
||||||
|
DMA_INSTANCE_TYPE *Instance;
|
||||||
|
rt_uint32_t request;
|
||||||
|
} channel_request;
|
||||||
|
#endif
|
||||||
|
} dma;
|
||||||
|
|
||||||
|
rt_uint32_t dma_rcc;
|
||||||
|
IRQn_Type dma_irq;
|
||||||
|
};
|
||||||
|
|
||||||
|
/* stm32 uart dirver class */
|
||||||
|
struct stm32_uart
|
||||||
|
{
|
||||||
|
UART_HandleTypeDef handle;
|
||||||
|
const struct stm32_uart_config *config;
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef BSP_UART_USING_DMA_RX
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
DMA_HandleTypeDef handle;
|
||||||
|
rt_size_t last_index;
|
||||||
|
} dma;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
struct rt_serial_device serial;
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif /* __DRV_USART_H__ */
|
||||||
|
|
@ -0,0 +1,17 @@
|
||||||
|
config SOC_FAMILY_STM32
|
||||||
|
bool
|
||||||
|
|
||||||
|
config SOC_SERIES_STM32F1
|
||||||
|
bool
|
||||||
|
select ARCH_ARM_CORTEX_M3
|
||||||
|
select SOC_FAMILY_STM32
|
||||||
|
|
||||||
|
config SOC_SERIES_STM32F4
|
||||||
|
bool
|
||||||
|
select ARCH_ARM_CORTEX_M4
|
||||||
|
select SOC_FAMILY_STM32
|
||||||
|
|
||||||
|
config SOC_SERIES_STM32L4
|
||||||
|
bool
|
||||||
|
select ARCH_ARM_CORTEX_M4
|
||||||
|
select SOC_FAMILY_STM32
|
||||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,238 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V4.2.0
|
||||||
|
* @date 31-March-2017
|
||||||
|
* @brief CMSIS STM32F1xx Device Peripheral Access Layer Header File.
|
||||||
|
*
|
||||||
|
* The file is the unique include file that the application programmer
|
||||||
|
* is using in the C source code, usually in main.c. This file contains:
|
||||||
|
* - Configuration section that allows to select:
|
||||||
|
* - The STM32F1xx device used in the target application
|
||||||
|
* - To use or not the peripheral’s drivers in application code(i.e.
|
||||||
|
* code will be based on direct access to peripheral’s registers
|
||||||
|
* rather than drivers API), this option is controlled by
|
||||||
|
* "#define USE_HAL_DRIVER"
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup CMSIS
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup stm32f1xx
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __STM32F1XX_H
|
||||||
|
#define __STM32F1XX_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif /* __cplusplus */
|
||||||
|
|
||||||
|
/** @addtogroup Library_configuration_section
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief STM32 Family
|
||||||
|
*/
|
||||||
|
#if !defined (STM32F1)
|
||||||
|
#define STM32F1
|
||||||
|
#endif /* STM32F1 */
|
||||||
|
|
||||||
|
/* Uncomment the line below according to the target STM32L device used in your
|
||||||
|
application
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if !defined (STM32F100xB) && !defined (STM32F100xE) && !defined (STM32F101x6) && \
|
||||||
|
!defined (STM32F101xB) && !defined (STM32F101xE) && !defined (STM32F101xG) && !defined (STM32F102x6) && !defined (STM32F102xB) && !defined (STM32F103x6) && \
|
||||||
|
!defined (STM32F103xB) && !defined (STM32F103xE) && !defined (STM32F103xG) && !defined (STM32F105xC) && !defined (STM32F107xC)
|
||||||
|
/* #define STM32F100xB */ /*!< STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB and STM32F100VB */
|
||||||
|
/* #define STM32F100xE */ /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */
|
||||||
|
/* #define STM32F101x6 */ /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */
|
||||||
|
/* #define STM32F101xB */ /*!< STM32F101C8, STM32F101R8, STM32F101T8, STM32F101V8, STM32F101CB, STM32F101RB, STM32F101TB and STM32F101VB */
|
||||||
|
/* #define STM32F101xE */ /*!< STM32F101RC, STM32F101VC, STM32F101ZC, STM32F101RD, STM32F101VD, STM32F101ZD, STM32F101RE, STM32F101VE and STM32F101ZE */
|
||||||
|
/* #define STM32F101xG */ /*!< STM32F101RF, STM32F101VF, STM32F101ZF, STM32F101RG, STM32F101VG and STM32F101ZG */
|
||||||
|
/* #define STM32F102x6 */ /*!< STM32F102C4, STM32F102R4, STM32F102C6 and STM32F102R6 */
|
||||||
|
/* #define STM32F102xB */ /*!< STM32F102C8, STM32F102R8, STM32F102CB and STM32F102RB */
|
||||||
|
/* #define STM32F103x6 */ /*!< STM32F103C4, STM32F103R4, STM32F103T4, STM32F103C6, STM32F103R6 and STM32F103T6 */
|
||||||
|
/* #define STM32F103xB */ /*!< STM32F103C8, STM32F103R8, STM32F103T8, STM32F103V8, STM32F103CB, STM32F103RB, STM32F103TB and STM32F103VB */
|
||||||
|
/* #define STM32F103xE */ /*!< STM32F103RC, STM32F103VC, STM32F103ZC, STM32F103RD, STM32F103VD, STM32F103ZD, STM32F103RE, STM32F103VE and STM32F103ZE */
|
||||||
|
/* #define STM32F103xG */ /*!< STM32F103RF, STM32F103VF, STM32F103ZF, STM32F103RG, STM32F103VG and STM32F103ZG */
|
||||||
|
/* #define STM32F105xC */ /*!< STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC and STM32F105VC */
|
||||||
|
/* #define STM32F107xC */ /*!< STM32F107RB, STM32F107VB, STM32F107RC and STM32F107VC */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Tip: To avoid modifying this file each time you need to switch between these
|
||||||
|
devices, you can define the device in your toolchain compiler preprocessor.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if !defined (USE_HAL_DRIVER)
|
||||||
|
/**
|
||||||
|
* @brief Comment the line below if you will not use the peripherals drivers.
|
||||||
|
In this case, these drivers will not be included and the application code will
|
||||||
|
be based on direct access to peripherals registers
|
||||||
|
*/
|
||||||
|
/*#define USE_HAL_DRIVER */
|
||||||
|
#endif /* USE_HAL_DRIVER */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief CMSIS Device version number V4.2.0
|
||||||
|
*/
|
||||||
|
#define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */
|
||||||
|
#define __STM32F1_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
|
||||||
|
#define __STM32F1_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
|
||||||
|
#define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||||
|
#define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24)\
|
||||||
|
|(__STM32F1_CMSIS_VERSION_SUB1 << 16)\
|
||||||
|
|(__STM32F1_CMSIS_VERSION_SUB2 << 8 )\
|
||||||
|
|(__STM32F1_CMSIS_VERSION_RC))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup Device_Included
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined(STM32F100xB)
|
||||||
|
#include "stm32f100xb.h"
|
||||||
|
#elif defined(STM32F100xE)
|
||||||
|
#include "stm32f100xe.h"
|
||||||
|
#elif defined(STM32F101x6)
|
||||||
|
#include "stm32f101x6.h"
|
||||||
|
#elif defined(STM32F101xB)
|
||||||
|
#include "stm32f101xb.h"
|
||||||
|
#elif defined(STM32F101xE)
|
||||||
|
#include "stm32f101xe.h"
|
||||||
|
#elif defined(STM32F101xG)
|
||||||
|
#include "stm32f101xg.h"
|
||||||
|
#elif defined(STM32F102x6)
|
||||||
|
#include "stm32f102x6.h"
|
||||||
|
#elif defined(STM32F102xB)
|
||||||
|
#include "stm32f102xb.h"
|
||||||
|
#elif defined(STM32F103x6)
|
||||||
|
#include "stm32f103x6.h"
|
||||||
|
#elif defined(STM32F103xB)
|
||||||
|
#include "stm32f103xb.h"
|
||||||
|
#elif defined(STM32F103xE)
|
||||||
|
#include "stm32f103xe.h"
|
||||||
|
#elif defined(STM32F103xG)
|
||||||
|
#include "stm32f103xg.h"
|
||||||
|
#elif defined(STM32F105xC)
|
||||||
|
#include "stm32f105xc.h"
|
||||||
|
#elif defined(STM32F107xC)
|
||||||
|
#include "stm32f107xc.h"
|
||||||
|
#else
|
||||||
|
#error "Please select first the target STM32F1xx device used in your application (in stm32f1xx.h file)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup Exported_types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
RESET = 0,
|
||||||
|
SET = !RESET
|
||||||
|
} FlagStatus, ITStatus;
|
||||||
|
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
DISABLE = 0,
|
||||||
|
ENABLE = !DISABLE
|
||||||
|
} FunctionalState;
|
||||||
|
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
|
||||||
|
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
ERROR = 0,
|
||||||
|
SUCCESS = !ERROR
|
||||||
|
} ErrorStatus;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Exported_macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
|
||||||
|
|
||||||
|
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
|
||||||
|
|
||||||
|
#define READ_BIT(REG, BIT) ((REG) & (BIT))
|
||||||
|
|
||||||
|
#define CLEAR_REG(REG) ((REG) = (0x0))
|
||||||
|
|
||||||
|
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
|
||||||
|
|
||||||
|
#define READ_REG(REG) ((REG))
|
||||||
|
|
||||||
|
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
|
||||||
|
|
||||||
|
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined (USE_HAL_DRIVER)
|
||||||
|
#include "stm32f1xx_hal.h"
|
||||||
|
#endif /* USE_HAL_DRIVER */
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif /* __cplusplus */
|
||||||
|
|
||||||
|
#endif /* __STM32F1xx_H */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,116 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file system_stm32f10x.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V4.2.0
|
||||||
|
* @date 31-March-2017
|
||||||
|
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup CMSIS
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup stm32f10x_system
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Define to prevent recursive inclusion
|
||||||
|
*/
|
||||||
|
#ifndef __SYSTEM_STM32F10X_H
|
||||||
|
#define __SYSTEM_STM32F10X_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** @addtogroup STM32F10x_System_Includes
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup STM32F10x_System_Exported_types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||||
|
extern const uint8_t AHBPrescTable[16U]; /*!< AHB prescalers table values */
|
||||||
|
extern const uint8_t APBPrescTable[8U]; /*!< APB prescalers table values */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup STM32F10x_System_Exported_Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup STM32F10x_System_Exported_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup STM32F10x_System_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
extern void SystemInit(void);
|
||||||
|
extern void SystemCoreClockUpdate(void);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /*__SYSTEM_STM32F10X_H */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
File diff suppressed because one or more lines are too long
|
|
@ -0,0 +1,332 @@
|
||||||
|
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
|
||||||
|
;* File Name : startup_stm32f100xb.s
|
||||||
|
;* Author : MCD Application Team
|
||||||
|
;* Version : V4.2.0
|
||||||
|
;* Date : 31-March-2017
|
||||||
|
;* Description : STM32F100xB Devices vector table for MDK-ARM toolchain.
|
||||||
|
;* This module performs:
|
||||||
|
;* - Set the initial SP
|
||||||
|
;* - Set the initial PC == Reset_Handler
|
||||||
|
;* - Set the vector table entries with the exceptions ISR address
|
||||||
|
;* - Configure the clock system
|
||||||
|
;* - Branches to __main in the C library (which eventually
|
||||||
|
;* calls main()).
|
||||||
|
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||||
|
;* priority is Privileged, and the Stack is set to Main.
|
||||||
|
;********************************************************************************
|
||||||
|
;*
|
||||||
|
;* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||||
|
;*
|
||||||
|
;* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
;* are permitted provided that the following conditions are met:
|
||||||
|
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
;* this list of conditions and the following disclaimer.
|
||||||
|
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
;* this list of conditions and the following disclaimer in the documentation
|
||||||
|
;* and/or other materials provided with the distribution.
|
||||||
|
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
;* may be used to endorse or promote products derived from this software
|
||||||
|
;* without specific prior written permission.
|
||||||
|
;*
|
||||||
|
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
;
|
||||||
|
;*******************************************************************************
|
||||||
|
|
||||||
|
; Amount of memory (in bytes) allocated for Stack
|
||||||
|
; Tailor this value to your application needs
|
||||||
|
; <h> Stack Configuration
|
||||||
|
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Stack_Size EQU 0x00000400
|
||||||
|
|
||||||
|
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||||
|
Stack_Mem SPACE Stack_Size
|
||||||
|
__initial_sp
|
||||||
|
|
||||||
|
|
||||||
|
; <h> Heap Configuration
|
||||||
|
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Heap_Size EQU 0x00000200
|
||||||
|
|
||||||
|
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||||
|
__heap_base
|
||||||
|
Heap_Mem SPACE Heap_Size
|
||||||
|
__heap_limit
|
||||||
|
|
||||||
|
PRESERVE8
|
||||||
|
THUMB
|
||||||
|
|
||||||
|
|
||||||
|
; Vector Table Mapped to Address 0 at Reset
|
||||||
|
AREA RESET, DATA, READONLY
|
||||||
|
EXPORT __Vectors
|
||||||
|
EXPORT __Vectors_End
|
||||||
|
EXPORT __Vectors_Size
|
||||||
|
|
||||||
|
__Vectors DCD __initial_sp ; Top of Stack
|
||||||
|
DCD Reset_Handler ; Reset Handler
|
||||||
|
DCD NMI_Handler ; NMI Handler
|
||||||
|
DCD HardFault_Handler ; Hard Fault Handler
|
||||||
|
DCD MemManage_Handler ; MPU Fault Handler
|
||||||
|
DCD BusFault_Handler ; Bus Fault Handler
|
||||||
|
DCD UsageFault_Handler ; Usage Fault Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; SVCall Handler
|
||||||
|
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD PendSV_Handler ; PendSV Handler
|
||||||
|
DCD SysTick_Handler ; SysTick Handler
|
||||||
|
|
||||||
|
; External Interrupts
|
||||||
|
DCD WWDG_IRQHandler ; Window Watchdog
|
||||||
|
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||||
|
DCD TAMPER_IRQHandler ; Tamper
|
||||||
|
DCD RTC_IRQHandler ; RTC
|
||||||
|
DCD FLASH_IRQHandler ; Flash
|
||||||
|
DCD RCC_IRQHandler ; RCC
|
||||||
|
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||||
|
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||||
|
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||||
|
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||||
|
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||||
|
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||||
|
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||||
|
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||||
|
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||||
|
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||||
|
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||||
|
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||||
|
DCD ADC1_IRQHandler ; ADC1
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||||
|
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
|
||||||
|
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
|
||||||
|
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
|
||||||
|
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||||
|
DCD TIM2_IRQHandler ; TIM2
|
||||||
|
DCD TIM3_IRQHandler ; TIM3
|
||||||
|
DCD TIM4_IRQHandler ; TIM4
|
||||||
|
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||||
|
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||||
|
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||||
|
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||||
|
DCD SPI1_IRQHandler ; SPI1
|
||||||
|
DCD SPI2_IRQHandler ; SPI2
|
||||||
|
DCD USART1_IRQHandler ; USART1
|
||||||
|
DCD USART2_IRQHandler ; USART2
|
||||||
|
DCD USART3_IRQHandler ; USART3
|
||||||
|
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||||
|
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
|
||||||
|
DCD CEC_IRQHandler ; HDMI-CEC
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
|
||||||
|
DCD TIM7_IRQHandler ; TIM7
|
||||||
|
__Vectors_End
|
||||||
|
|
||||||
|
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||||
|
|
||||||
|
AREA |.text|, CODE, READONLY
|
||||||
|
|
||||||
|
; Reset handler
|
||||||
|
Reset_Handler PROC
|
||||||
|
EXPORT Reset_Handler [WEAK]
|
||||||
|
IMPORT __main
|
||||||
|
IMPORT SystemInit
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__main
|
||||||
|
BX R0
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||||
|
|
||||||
|
NMI_Handler PROC
|
||||||
|
EXPORT NMI_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
HardFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT HardFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
MemManage_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT MemManage_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
BusFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT BusFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
UsageFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT UsageFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SVC_Handler PROC
|
||||||
|
EXPORT SVC_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
DebugMon_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT DebugMon_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
PendSV_Handler PROC
|
||||||
|
EXPORT PendSV_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SysTick_Handler PROC
|
||||||
|
EXPORT SysTick_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
Default_Handler PROC
|
||||||
|
|
||||||
|
EXPORT WWDG_IRQHandler [WEAK]
|
||||||
|
EXPORT PVD_IRQHandler [WEAK]
|
||||||
|
EXPORT TAMPER_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_IRQHandler [WEAK]
|
||||||
|
EXPORT FLASH_IRQHandler [WEAK]
|
||||||
|
EXPORT RCC_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI0_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI1_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI2_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI3_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||||
|
EXPORT ADC1_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM2_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM3_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM4_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI1_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI2_IRQHandler [WEAK]
|
||||||
|
EXPORT USART1_IRQHandler [WEAK]
|
||||||
|
EXPORT USART2_IRQHandler [WEAK]
|
||||||
|
EXPORT USART3_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||||
|
EXPORT CEC_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM6_DAC_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM7_IRQHandler [WEAK]
|
||||||
|
|
||||||
|
WWDG_IRQHandler
|
||||||
|
PVD_IRQHandler
|
||||||
|
TAMPER_IRQHandler
|
||||||
|
RTC_IRQHandler
|
||||||
|
FLASH_IRQHandler
|
||||||
|
RCC_IRQHandler
|
||||||
|
EXTI0_IRQHandler
|
||||||
|
EXTI1_IRQHandler
|
||||||
|
EXTI2_IRQHandler
|
||||||
|
EXTI3_IRQHandler
|
||||||
|
EXTI4_IRQHandler
|
||||||
|
DMA1_Channel1_IRQHandler
|
||||||
|
DMA1_Channel2_IRQHandler
|
||||||
|
DMA1_Channel3_IRQHandler
|
||||||
|
DMA1_Channel4_IRQHandler
|
||||||
|
DMA1_Channel5_IRQHandler
|
||||||
|
DMA1_Channel6_IRQHandler
|
||||||
|
DMA1_Channel7_IRQHandler
|
||||||
|
ADC1_IRQHandler
|
||||||
|
EXTI9_5_IRQHandler
|
||||||
|
TIM1_BRK_TIM15_IRQHandler
|
||||||
|
TIM1_UP_TIM16_IRQHandler
|
||||||
|
TIM1_TRG_COM_TIM17_IRQHandler
|
||||||
|
TIM1_CC_IRQHandler
|
||||||
|
TIM2_IRQHandler
|
||||||
|
TIM3_IRQHandler
|
||||||
|
TIM4_IRQHandler
|
||||||
|
I2C1_EV_IRQHandler
|
||||||
|
I2C1_ER_IRQHandler
|
||||||
|
I2C2_EV_IRQHandler
|
||||||
|
I2C2_ER_IRQHandler
|
||||||
|
SPI1_IRQHandler
|
||||||
|
SPI2_IRQHandler
|
||||||
|
USART1_IRQHandler
|
||||||
|
USART2_IRQHandler
|
||||||
|
USART3_IRQHandler
|
||||||
|
EXTI15_10_IRQHandler
|
||||||
|
RTC_Alarm_IRQHandler
|
||||||
|
CEC_IRQHandler
|
||||||
|
TIM6_DAC_IRQHandler
|
||||||
|
TIM7_IRQHandler
|
||||||
|
B .
|
||||||
|
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
;*******************************************************************************
|
||||||
|
; User Stack and Heap initialization
|
||||||
|
;*******************************************************************************
|
||||||
|
IF :DEF:__MICROLIB
|
||||||
|
|
||||||
|
EXPORT __initial_sp
|
||||||
|
EXPORT __heap_base
|
||||||
|
EXPORT __heap_limit
|
||||||
|
|
||||||
|
ELSE
|
||||||
|
|
||||||
|
IMPORT __use_two_region_memory
|
||||||
|
EXPORT __user_initial_stackheap
|
||||||
|
|
||||||
|
__user_initial_stackheap
|
||||||
|
|
||||||
|
LDR R0, = Heap_Mem
|
||||||
|
LDR R1, =(Stack_Mem + Stack_Size)
|
||||||
|
LDR R2, = (Heap_Mem + Heap_Size)
|
||||||
|
LDR R3, = Stack_Mem
|
||||||
|
BX LR
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
ENDIF
|
||||||
|
|
||||||
|
END
|
||||||
|
|
||||||
|
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||||
|
|
@ -0,0 +1,363 @@
|
||||||
|
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
|
||||||
|
;* File Name : startup_stm32f100xe.s
|
||||||
|
;* Author : MCD Application Team
|
||||||
|
;* Version : V4.2.0
|
||||||
|
;* Date : 31-March-2017
|
||||||
|
;* Description : STM32F100xE Devices vector table for MDK-ARM toolchain.
|
||||||
|
;* This module performs:
|
||||||
|
;* - Set the initial SP
|
||||||
|
;* - Set the initial PC == Reset_Handler
|
||||||
|
;* - Set the vector table entries with the exceptions ISR address
|
||||||
|
;* - Configure the clock system and also configure the external
|
||||||
|
;* SRAM mounted on STM32100E-EVAL board to be used as data
|
||||||
|
;* memory (optional, to be enabled by user)
|
||||||
|
;* - Branches to __main in the C library (which eventually
|
||||||
|
;* calls main()).
|
||||||
|
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||||
|
;* priority is Privileged, and the Stack is set to Main.
|
||||||
|
;********************************************************************************
|
||||||
|
;*
|
||||||
|
;* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||||
|
;*
|
||||||
|
;* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
;* are permitted provided that the following conditions are met:
|
||||||
|
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
;* this list of conditions and the following disclaimer.
|
||||||
|
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
;* this list of conditions and the following disclaimer in the documentation
|
||||||
|
;* and/or other materials provided with the distribution.
|
||||||
|
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
;* may be used to endorse or promote products derived from this software
|
||||||
|
;* without specific prior written permission.
|
||||||
|
;*
|
||||||
|
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
;
|
||||||
|
;*******************************************************************************
|
||||||
|
|
||||||
|
; Amount of memory (in bytes) allocated for Stack
|
||||||
|
; Tailor this value to your application needs
|
||||||
|
; <h> Stack Configuration
|
||||||
|
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Stack_Size EQU 0x00000400
|
||||||
|
|
||||||
|
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||||
|
Stack_Mem SPACE Stack_Size
|
||||||
|
__initial_sp
|
||||||
|
|
||||||
|
|
||||||
|
; <h> Heap Configuration
|
||||||
|
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Heap_Size EQU 0x00000200
|
||||||
|
|
||||||
|
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||||
|
__heap_base
|
||||||
|
Heap_Mem SPACE Heap_Size
|
||||||
|
__heap_limit
|
||||||
|
|
||||||
|
PRESERVE8
|
||||||
|
THUMB
|
||||||
|
|
||||||
|
|
||||||
|
; Vector Table Mapped to Address 0 at Reset
|
||||||
|
AREA RESET, DATA, READONLY
|
||||||
|
EXPORT __Vectors
|
||||||
|
EXPORT __Vectors_End
|
||||||
|
EXPORT __Vectors_Size
|
||||||
|
|
||||||
|
__Vectors DCD __initial_sp ; Top of Stack
|
||||||
|
DCD Reset_Handler ; Reset Handler
|
||||||
|
DCD NMI_Handler ; NMI Handler
|
||||||
|
DCD HardFault_Handler ; Hard Fault Handler
|
||||||
|
DCD MemManage_Handler ; MPU Fault Handler
|
||||||
|
DCD BusFault_Handler ; Bus Fault Handler
|
||||||
|
DCD UsageFault_Handler ; Usage Fault Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; SVCall Handler
|
||||||
|
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD PendSV_Handler ; PendSV Handler
|
||||||
|
DCD SysTick_Handler ; SysTick Handler
|
||||||
|
|
||||||
|
; External Interrupts
|
||||||
|
DCD WWDG_IRQHandler ; Window Watchdog
|
||||||
|
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||||
|
DCD TAMPER_IRQHandler ; Tamper
|
||||||
|
DCD RTC_IRQHandler ; RTC
|
||||||
|
DCD FLASH_IRQHandler ; Flash
|
||||||
|
DCD RCC_IRQHandler ; RCC
|
||||||
|
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||||
|
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||||
|
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||||
|
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||||
|
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||||
|
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||||
|
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||||
|
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||||
|
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||||
|
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||||
|
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||||
|
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||||
|
DCD ADC1_IRQHandler ; ADC1
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||||
|
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
|
||||||
|
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
|
||||||
|
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
|
||||||
|
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||||
|
DCD TIM2_IRQHandler ; TIM2
|
||||||
|
DCD TIM3_IRQHandler ; TIM3
|
||||||
|
DCD TIM4_IRQHandler ; TIM4
|
||||||
|
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||||
|
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||||
|
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||||
|
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||||
|
DCD SPI1_IRQHandler ; SPI1
|
||||||
|
DCD SPI2_IRQHandler ; SPI2
|
||||||
|
DCD USART1_IRQHandler ; USART1
|
||||||
|
DCD USART2_IRQHandler ; USART2
|
||||||
|
DCD USART3_IRQHandler ; USART3
|
||||||
|
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||||
|
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
|
||||||
|
DCD CEC_IRQHandler ; HDMI CEC
|
||||||
|
DCD TIM12_IRQHandler ; TIM12
|
||||||
|
DCD TIM13_IRQHandler ; TIM13
|
||||||
|
DCD TIM14_IRQHandler ; TIM14
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD TIM5_IRQHandler ; TIM5
|
||||||
|
DCD SPI3_IRQHandler ; SPI3
|
||||||
|
DCD UART4_IRQHandler ; UART4
|
||||||
|
DCD UART5_IRQHandler ; UART5
|
||||||
|
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
|
||||||
|
DCD TIM7_IRQHandler ; TIM7
|
||||||
|
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
|
||||||
|
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
|
||||||
|
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
|
||||||
|
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
|
||||||
|
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
|
||||||
|
__Vectors_End
|
||||||
|
|
||||||
|
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||||
|
|
||||||
|
AREA |.text|, CODE, READONLY
|
||||||
|
|
||||||
|
; Reset handler
|
||||||
|
Reset_Handler PROC
|
||||||
|
EXPORT Reset_Handler [WEAK]
|
||||||
|
IMPORT __main
|
||||||
|
IMPORT SystemInit
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__main
|
||||||
|
BX R0
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||||
|
|
||||||
|
NMI_Handler PROC
|
||||||
|
EXPORT NMI_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
HardFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT HardFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
MemManage_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT MemManage_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
BusFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT BusFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
UsageFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT UsageFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SVC_Handler PROC
|
||||||
|
EXPORT SVC_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
DebugMon_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT DebugMon_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
PendSV_Handler PROC
|
||||||
|
EXPORT PendSV_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SysTick_Handler PROC
|
||||||
|
EXPORT SysTick_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
Default_Handler PROC
|
||||||
|
|
||||||
|
EXPORT WWDG_IRQHandler [WEAK]
|
||||||
|
EXPORT PVD_IRQHandler [WEAK]
|
||||||
|
EXPORT TAMPER_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_IRQHandler [WEAK]
|
||||||
|
EXPORT FLASH_IRQHandler [WEAK]
|
||||||
|
EXPORT RCC_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI0_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI1_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI2_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI3_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||||
|
EXPORT ADC1_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM2_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM3_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM4_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI1_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI2_IRQHandler [WEAK]
|
||||||
|
EXPORT USART1_IRQHandler [WEAK]
|
||||||
|
EXPORT USART2_IRQHandler [WEAK]
|
||||||
|
EXPORT USART3_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||||
|
EXPORT CEC_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM12_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM13_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM14_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM5_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI3_IRQHandler [WEAK]
|
||||||
|
EXPORT UART4_IRQHandler [WEAK]
|
||||||
|
EXPORT UART5_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM6_DAC_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM7_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Channel1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Channel2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Channel3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Channel5_IRQHandler [WEAK]
|
||||||
|
|
||||||
|
WWDG_IRQHandler
|
||||||
|
PVD_IRQHandler
|
||||||
|
TAMPER_IRQHandler
|
||||||
|
RTC_IRQHandler
|
||||||
|
FLASH_IRQHandler
|
||||||
|
RCC_IRQHandler
|
||||||
|
EXTI0_IRQHandler
|
||||||
|
EXTI1_IRQHandler
|
||||||
|
EXTI2_IRQHandler
|
||||||
|
EXTI3_IRQHandler
|
||||||
|
EXTI4_IRQHandler
|
||||||
|
DMA1_Channel1_IRQHandler
|
||||||
|
DMA1_Channel2_IRQHandler
|
||||||
|
DMA1_Channel3_IRQHandler
|
||||||
|
DMA1_Channel4_IRQHandler
|
||||||
|
DMA1_Channel5_IRQHandler
|
||||||
|
DMA1_Channel6_IRQHandler
|
||||||
|
DMA1_Channel7_IRQHandler
|
||||||
|
ADC1_IRQHandler
|
||||||
|
EXTI9_5_IRQHandler
|
||||||
|
TIM1_BRK_TIM15_IRQHandler
|
||||||
|
TIM1_UP_TIM16_IRQHandler
|
||||||
|
TIM1_TRG_COM_TIM17_IRQHandler
|
||||||
|
TIM1_CC_IRQHandler
|
||||||
|
TIM2_IRQHandler
|
||||||
|
TIM3_IRQHandler
|
||||||
|
TIM4_IRQHandler
|
||||||
|
I2C1_EV_IRQHandler
|
||||||
|
I2C1_ER_IRQHandler
|
||||||
|
I2C2_EV_IRQHandler
|
||||||
|
I2C2_ER_IRQHandler
|
||||||
|
SPI1_IRQHandler
|
||||||
|
SPI2_IRQHandler
|
||||||
|
USART1_IRQHandler
|
||||||
|
USART2_IRQHandler
|
||||||
|
USART3_IRQHandler
|
||||||
|
EXTI15_10_IRQHandler
|
||||||
|
RTC_Alarm_IRQHandler
|
||||||
|
CEC_IRQHandler
|
||||||
|
TIM12_IRQHandler
|
||||||
|
TIM13_IRQHandler
|
||||||
|
TIM14_IRQHandler
|
||||||
|
TIM5_IRQHandler
|
||||||
|
SPI3_IRQHandler
|
||||||
|
UART4_IRQHandler
|
||||||
|
UART5_IRQHandler
|
||||||
|
TIM6_DAC_IRQHandler
|
||||||
|
TIM7_IRQHandler
|
||||||
|
DMA2_Channel1_IRQHandler
|
||||||
|
DMA2_Channel2_IRQHandler
|
||||||
|
DMA2_Channel3_IRQHandler
|
||||||
|
DMA2_Channel4_5_IRQHandler
|
||||||
|
DMA2_Channel5_IRQHandler
|
||||||
|
B .
|
||||||
|
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
;*******************************************************************************
|
||||||
|
; User Stack and Heap initialization
|
||||||
|
;*******************************************************************************
|
||||||
|
IF :DEF:__MICROLIB
|
||||||
|
|
||||||
|
EXPORT __initial_sp
|
||||||
|
EXPORT __heap_base
|
||||||
|
EXPORT __heap_limit
|
||||||
|
|
||||||
|
ELSE
|
||||||
|
|
||||||
|
IMPORT __use_two_region_memory
|
||||||
|
EXPORT __user_initial_stackheap
|
||||||
|
|
||||||
|
__user_initial_stackheap
|
||||||
|
|
||||||
|
LDR R0, = Heap_Mem
|
||||||
|
LDR R1, =(Stack_Mem + Stack_Size)
|
||||||
|
LDR R2, = (Heap_Mem + Heap_Size)
|
||||||
|
LDR R3, = Stack_Mem
|
||||||
|
BX LR
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
ENDIF
|
||||||
|
|
||||||
|
END
|
||||||
|
|
||||||
|
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||||
|
|
@ -0,0 +1,295 @@
|
||||||
|
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
|
||||||
|
;* File Name : startup_stm32f101x6.s
|
||||||
|
;* Author : MCD Application Team
|
||||||
|
;* Version : V4.2.0
|
||||||
|
;* Date : 31-March-2017
|
||||||
|
;* Description : STM32F101x6 Devices vector table for MDK-ARM toolchain.
|
||||||
|
;* This module performs:
|
||||||
|
;* - Set the initial SP
|
||||||
|
;* - Set the initial PC == Reset_Handler
|
||||||
|
;* - Set the vector table entries with the exceptions ISR address
|
||||||
|
;* - Configure the clock system
|
||||||
|
;* - Branches to __main in the C library (which eventually
|
||||||
|
;* calls main()).
|
||||||
|
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||||
|
;* priority is Privileged, and the Stack is set to Main.
|
||||||
|
;********************************************************************************
|
||||||
|
;*
|
||||||
|
;* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||||
|
;*
|
||||||
|
;* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
;* are permitted provided that the following conditions are met:
|
||||||
|
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
;* this list of conditions and the following disclaimer.
|
||||||
|
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
;* this list of conditions and the following disclaimer in the documentation
|
||||||
|
;* and/or other materials provided with the distribution.
|
||||||
|
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
;* may be used to endorse or promote products derived from this software
|
||||||
|
;* without specific prior written permission.
|
||||||
|
;*
|
||||||
|
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
;
|
||||||
|
;*******************************************************************************
|
||||||
|
|
||||||
|
; Amount of memory (in bytes) allocated for Stack
|
||||||
|
; Tailor this value to your application needs
|
||||||
|
; <h> Stack Configuration
|
||||||
|
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Stack_Size EQU 0x00000400
|
||||||
|
|
||||||
|
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||||
|
Stack_Mem SPACE Stack_Size
|
||||||
|
__initial_sp
|
||||||
|
|
||||||
|
|
||||||
|
; <h> Heap Configuration
|
||||||
|
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Heap_Size EQU 0x00000200
|
||||||
|
|
||||||
|
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||||
|
__heap_base
|
||||||
|
Heap_Mem SPACE Heap_Size
|
||||||
|
__heap_limit
|
||||||
|
|
||||||
|
PRESERVE8
|
||||||
|
THUMB
|
||||||
|
|
||||||
|
|
||||||
|
; Vector Table Mapped to Address 0 at Reset
|
||||||
|
AREA RESET, DATA, READONLY
|
||||||
|
EXPORT __Vectors
|
||||||
|
EXPORT __Vectors_End
|
||||||
|
EXPORT __Vectors_Size
|
||||||
|
|
||||||
|
__Vectors DCD __initial_sp ; Top of Stack
|
||||||
|
DCD Reset_Handler ; Reset Handler
|
||||||
|
DCD NMI_Handler ; NMI Handler
|
||||||
|
DCD HardFault_Handler ; Hard Fault Handler
|
||||||
|
DCD MemManage_Handler ; MPU Fault Handler
|
||||||
|
DCD BusFault_Handler ; Bus Fault Handler
|
||||||
|
DCD UsageFault_Handler ; Usage Fault Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; SVCall Handler
|
||||||
|
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD PendSV_Handler ; PendSV Handler
|
||||||
|
DCD SysTick_Handler ; SysTick Handler
|
||||||
|
|
||||||
|
; External Interrupts
|
||||||
|
DCD WWDG_IRQHandler ; Window Watchdog
|
||||||
|
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||||
|
DCD TAMPER_IRQHandler ; Tamper
|
||||||
|
DCD RTC_IRQHandler ; RTC
|
||||||
|
DCD FLASH_IRQHandler ; Flash
|
||||||
|
DCD RCC_IRQHandler ; RCC
|
||||||
|
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||||
|
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||||
|
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||||
|
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||||
|
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||||
|
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||||
|
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||||
|
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||||
|
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||||
|
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||||
|
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||||
|
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||||
|
DCD ADC1_IRQHandler ; ADC1
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD TIM2_IRQHandler ; TIM2
|
||||||
|
DCD TIM3_IRQHandler ; TIM3
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||||
|
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SPI1_IRQHandler ; SPI1
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD USART1_IRQHandler ; USART1
|
||||||
|
DCD USART2_IRQHandler ; USART2
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||||
|
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
|
||||||
|
__Vectors_End
|
||||||
|
|
||||||
|
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||||
|
|
||||||
|
AREA |.text|, CODE, READONLY
|
||||||
|
|
||||||
|
; Reset handler routine
|
||||||
|
Reset_Handler PROC
|
||||||
|
EXPORT Reset_Handler [WEAK]
|
||||||
|
IMPORT __main
|
||||||
|
IMPORT SystemInit
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__main
|
||||||
|
BX R0
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||||
|
|
||||||
|
NMI_Handler PROC
|
||||||
|
EXPORT NMI_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
HardFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT HardFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
MemManage_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT MemManage_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
BusFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT BusFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
UsageFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT UsageFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SVC_Handler PROC
|
||||||
|
EXPORT SVC_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
DebugMon_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT DebugMon_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
PendSV_Handler PROC
|
||||||
|
EXPORT PendSV_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SysTick_Handler PROC
|
||||||
|
EXPORT SysTick_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
Default_Handler PROC
|
||||||
|
|
||||||
|
EXPORT WWDG_IRQHandler [WEAK]
|
||||||
|
EXPORT PVD_IRQHandler [WEAK]
|
||||||
|
EXPORT TAMPER_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_IRQHandler [WEAK]
|
||||||
|
EXPORT FLASH_IRQHandler [WEAK]
|
||||||
|
EXPORT RCC_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI0_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI1_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI2_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI3_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||||
|
EXPORT ADC1_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM2_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM3_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI1_IRQHandler [WEAK]
|
||||||
|
EXPORT USART1_IRQHandler [WEAK]
|
||||||
|
EXPORT USART2_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||||
|
|
||||||
|
WWDG_IRQHandler
|
||||||
|
PVD_IRQHandler
|
||||||
|
TAMPER_IRQHandler
|
||||||
|
RTC_IRQHandler
|
||||||
|
FLASH_IRQHandler
|
||||||
|
RCC_IRQHandler
|
||||||
|
EXTI0_IRQHandler
|
||||||
|
EXTI1_IRQHandler
|
||||||
|
EXTI2_IRQHandler
|
||||||
|
EXTI3_IRQHandler
|
||||||
|
EXTI4_IRQHandler
|
||||||
|
DMA1_Channel1_IRQHandler
|
||||||
|
DMA1_Channel2_IRQHandler
|
||||||
|
DMA1_Channel3_IRQHandler
|
||||||
|
DMA1_Channel4_IRQHandler
|
||||||
|
DMA1_Channel5_IRQHandler
|
||||||
|
DMA1_Channel6_IRQHandler
|
||||||
|
DMA1_Channel7_IRQHandler
|
||||||
|
ADC1_IRQHandler
|
||||||
|
EXTI9_5_IRQHandler
|
||||||
|
TIM2_IRQHandler
|
||||||
|
TIM3_IRQHandler
|
||||||
|
I2C1_EV_IRQHandler
|
||||||
|
I2C1_ER_IRQHandler
|
||||||
|
SPI1_IRQHandler
|
||||||
|
USART1_IRQHandler
|
||||||
|
USART2_IRQHandler
|
||||||
|
EXTI15_10_IRQHandler
|
||||||
|
RTC_Alarm_IRQHandler
|
||||||
|
|
||||||
|
B .
|
||||||
|
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
;*******************************************************************************
|
||||||
|
; User Stack and Heap initialization
|
||||||
|
;*******************************************************************************
|
||||||
|
IF :DEF:__MICROLIB
|
||||||
|
|
||||||
|
EXPORT __initial_sp
|
||||||
|
EXPORT __heap_base
|
||||||
|
EXPORT __heap_limit
|
||||||
|
|
||||||
|
ELSE
|
||||||
|
|
||||||
|
IMPORT __use_two_region_memory
|
||||||
|
EXPORT __user_initial_stackheap
|
||||||
|
|
||||||
|
__user_initial_stackheap
|
||||||
|
|
||||||
|
LDR R0, = Heap_Mem
|
||||||
|
LDR R1, =(Stack_Mem + Stack_Size)
|
||||||
|
LDR R2, = (Heap_Mem + Heap_Size)
|
||||||
|
LDR R3, = Stack_Mem
|
||||||
|
BX LR
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
ENDIF
|
||||||
|
|
||||||
|
END
|
||||||
|
|
||||||
|
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||||
|
|
@ -0,0 +1,305 @@
|
||||||
|
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
|
||||||
|
;* File Name : startup_stm32f101xb.s
|
||||||
|
;* Author : MCD Application Team
|
||||||
|
;* Version : V4.2.0
|
||||||
|
;* Date : 31-March-2017
|
||||||
|
;* Description : STM32F101xB Devices vector table for MDK-ARM toolchain.
|
||||||
|
;* This module performs:
|
||||||
|
;* - Set the initial SP
|
||||||
|
;* - Set the initial PC == Reset_Handler
|
||||||
|
;* - Set the vector table entries with the exceptions ISR address
|
||||||
|
;* - Configure the clock system
|
||||||
|
;* - Branches to __main in the C library (which eventually
|
||||||
|
;* calls main()).
|
||||||
|
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||||
|
;* priority is Privileged, and the Stack is set to Main.
|
||||||
|
;********************************************************************************
|
||||||
|
;*
|
||||||
|
;* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||||
|
;*
|
||||||
|
;* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
;* are permitted provided that the following conditions are met:
|
||||||
|
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
;* this list of conditions and the following disclaimer.
|
||||||
|
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
;* this list of conditions and the following disclaimer in the documentation
|
||||||
|
;* and/or other materials provided with the distribution.
|
||||||
|
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
;* may be used to endorse or promote products derived from this software
|
||||||
|
;* without specific prior written permission.
|
||||||
|
;*
|
||||||
|
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
;
|
||||||
|
;*******************************************************************************
|
||||||
|
|
||||||
|
; Amount of memory (in bytes) allocated for Stack
|
||||||
|
; Tailor this value to your application needs
|
||||||
|
; <h> Stack Configuration
|
||||||
|
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Stack_Size EQU 0x00000400
|
||||||
|
|
||||||
|
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||||
|
Stack_Mem SPACE Stack_Size
|
||||||
|
__initial_sp
|
||||||
|
|
||||||
|
|
||||||
|
; <h> Heap Configuration
|
||||||
|
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Heap_Size EQU 0x00000200
|
||||||
|
|
||||||
|
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||||
|
__heap_base
|
||||||
|
Heap_Mem SPACE Heap_Size
|
||||||
|
__heap_limit
|
||||||
|
|
||||||
|
PRESERVE8
|
||||||
|
THUMB
|
||||||
|
|
||||||
|
|
||||||
|
; Vector Table Mapped to Address 0 at Reset
|
||||||
|
AREA RESET, DATA, READONLY
|
||||||
|
EXPORT __Vectors
|
||||||
|
EXPORT __Vectors_End
|
||||||
|
EXPORT __Vectors_Size
|
||||||
|
|
||||||
|
__Vectors DCD __initial_sp ; Top of Stack
|
||||||
|
DCD Reset_Handler ; Reset Handler
|
||||||
|
DCD NMI_Handler ; NMI Handler
|
||||||
|
DCD HardFault_Handler ; Hard Fault Handler
|
||||||
|
DCD MemManage_Handler ; MPU Fault Handler
|
||||||
|
DCD BusFault_Handler ; Bus Fault Handler
|
||||||
|
DCD UsageFault_Handler ; Usage Fault Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; SVCall Handler
|
||||||
|
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD PendSV_Handler ; PendSV Handler
|
||||||
|
DCD SysTick_Handler ; SysTick Handler
|
||||||
|
|
||||||
|
; External Interrupts
|
||||||
|
DCD WWDG_IRQHandler ; Window Watchdog
|
||||||
|
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||||
|
DCD TAMPER_IRQHandler ; Tamper
|
||||||
|
DCD RTC_IRQHandler ; RTC
|
||||||
|
DCD FLASH_IRQHandler ; Flash
|
||||||
|
DCD RCC_IRQHandler ; RCC
|
||||||
|
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||||
|
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||||
|
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||||
|
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||||
|
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||||
|
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||||
|
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||||
|
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||||
|
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||||
|
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||||
|
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||||
|
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||||
|
DCD ADC1_IRQHandler ; ADC1
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD TIM2_IRQHandler ; TIM2
|
||||||
|
DCD TIM3_IRQHandler ; TIM3
|
||||||
|
DCD TIM4_IRQHandler ; TIM4
|
||||||
|
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||||
|
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||||
|
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||||
|
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||||
|
DCD SPI1_IRQHandler ; SPI1
|
||||||
|
DCD SPI2_IRQHandler ; SPI2
|
||||||
|
DCD USART1_IRQHandler ; USART1
|
||||||
|
DCD USART2_IRQHandler ; USART2
|
||||||
|
DCD USART3_IRQHandler ; USART3
|
||||||
|
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||||
|
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
|
||||||
|
__Vectors_End
|
||||||
|
|
||||||
|
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||||
|
|
||||||
|
AREA |.text|, CODE, READONLY
|
||||||
|
|
||||||
|
; Reset handler
|
||||||
|
Reset_Handler PROC
|
||||||
|
EXPORT Reset_Handler [WEAK]
|
||||||
|
IMPORT __main
|
||||||
|
IMPORT SystemInit
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__main
|
||||||
|
BX R0
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||||
|
|
||||||
|
NMI_Handler PROC
|
||||||
|
EXPORT NMI_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
HardFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT HardFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
MemManage_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT MemManage_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
BusFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT BusFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
UsageFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT UsageFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SVC_Handler PROC
|
||||||
|
EXPORT SVC_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
DebugMon_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT DebugMon_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
PendSV_Handler PROC
|
||||||
|
EXPORT PendSV_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SysTick_Handler PROC
|
||||||
|
EXPORT SysTick_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
Default_Handler PROC
|
||||||
|
|
||||||
|
EXPORT WWDG_IRQHandler [WEAK]
|
||||||
|
EXPORT PVD_IRQHandler [WEAK]
|
||||||
|
EXPORT TAMPER_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_IRQHandler [WEAK]
|
||||||
|
EXPORT FLASH_IRQHandler [WEAK]
|
||||||
|
EXPORT RCC_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI0_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI1_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI2_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI3_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||||
|
EXPORT ADC1_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM2_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM3_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM4_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI1_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI2_IRQHandler [WEAK]
|
||||||
|
EXPORT USART1_IRQHandler [WEAK]
|
||||||
|
EXPORT USART2_IRQHandler [WEAK]
|
||||||
|
EXPORT USART3_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||||
|
|
||||||
|
WWDG_IRQHandler
|
||||||
|
PVD_IRQHandler
|
||||||
|
TAMPER_IRQHandler
|
||||||
|
RTC_IRQHandler
|
||||||
|
FLASH_IRQHandler
|
||||||
|
RCC_IRQHandler
|
||||||
|
EXTI0_IRQHandler
|
||||||
|
EXTI1_IRQHandler
|
||||||
|
EXTI2_IRQHandler
|
||||||
|
EXTI3_IRQHandler
|
||||||
|
EXTI4_IRQHandler
|
||||||
|
DMA1_Channel1_IRQHandler
|
||||||
|
DMA1_Channel2_IRQHandler
|
||||||
|
DMA1_Channel3_IRQHandler
|
||||||
|
DMA1_Channel4_IRQHandler
|
||||||
|
DMA1_Channel5_IRQHandler
|
||||||
|
DMA1_Channel6_IRQHandler
|
||||||
|
DMA1_Channel7_IRQHandler
|
||||||
|
ADC1_IRQHandler
|
||||||
|
EXTI9_5_IRQHandler
|
||||||
|
TIM2_IRQHandler
|
||||||
|
TIM3_IRQHandler
|
||||||
|
TIM4_IRQHandler
|
||||||
|
I2C1_EV_IRQHandler
|
||||||
|
I2C1_ER_IRQHandler
|
||||||
|
I2C2_EV_IRQHandler
|
||||||
|
I2C2_ER_IRQHandler
|
||||||
|
SPI1_IRQHandler
|
||||||
|
SPI2_IRQHandler
|
||||||
|
USART1_IRQHandler
|
||||||
|
USART2_IRQHandler
|
||||||
|
USART3_IRQHandler
|
||||||
|
EXTI15_10_IRQHandler
|
||||||
|
RTC_Alarm_IRQHandler
|
||||||
|
|
||||||
|
B .
|
||||||
|
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
;*******************************************************************************
|
||||||
|
; User Stack and Heap initialization
|
||||||
|
;*******************************************************************************
|
||||||
|
IF :DEF:__MICROLIB
|
||||||
|
|
||||||
|
EXPORT __initial_sp
|
||||||
|
EXPORT __heap_base
|
||||||
|
EXPORT __heap_limit
|
||||||
|
|
||||||
|
ELSE
|
||||||
|
|
||||||
|
IMPORT __use_two_region_memory
|
||||||
|
EXPORT __user_initial_stackheap
|
||||||
|
|
||||||
|
__user_initial_stackheap
|
||||||
|
|
||||||
|
LDR R0, = Heap_Mem
|
||||||
|
LDR R1, =(Stack_Mem + Stack_Size)
|
||||||
|
LDR R2, = (Heap_Mem + Heap_Size)
|
||||||
|
LDR R3, = Stack_Mem
|
||||||
|
BX LR
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
ENDIF
|
||||||
|
|
||||||
|
END
|
||||||
|
|
||||||
|
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||||
|
|
@ -0,0 +1,343 @@
|
||||||
|
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
|
||||||
|
;* File Name : startup_stm32f101xe.s
|
||||||
|
;* Author : MCD Application Team
|
||||||
|
;* Version : V4.2.0
|
||||||
|
;* Date : 31-March-2017
|
||||||
|
;* Description : STM32F101xE Devices vector table for MDK-ARM toolchain.
|
||||||
|
;* This module performs:
|
||||||
|
;* - Set the initial SP
|
||||||
|
;* - Set the initial PC == Reset_Handler
|
||||||
|
;* - Set the vector table entries with the exceptions ISR address
|
||||||
|
;* - Configure the clock system
|
||||||
|
;* - Branches to __main in the C library (which eventually
|
||||||
|
;* calls main()).
|
||||||
|
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||||
|
;* priority is Privileged, and the Stack is set to Main.
|
||||||
|
;********************************************************************************
|
||||||
|
;*
|
||||||
|
;* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||||
|
;*
|
||||||
|
;* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
;* are permitted provided that the following conditions are met:
|
||||||
|
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
;* this list of conditions and the following disclaimer.
|
||||||
|
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
;* this list of conditions and the following disclaimer in the documentation
|
||||||
|
;* and/or other materials provided with the distribution.
|
||||||
|
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
;* may be used to endorse or promote products derived from this software
|
||||||
|
;* without specific prior written permission.
|
||||||
|
;*
|
||||||
|
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
;
|
||||||
|
;*******************************************************************************
|
||||||
|
|
||||||
|
; Amount of memory (in bytes) allocated for Stack
|
||||||
|
; Tailor this value to your application needs
|
||||||
|
; <h> Stack Configuration
|
||||||
|
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Stack_Size EQU 0x00000400
|
||||||
|
|
||||||
|
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||||
|
Stack_Mem SPACE Stack_Size
|
||||||
|
__initial_sp
|
||||||
|
|
||||||
|
; <h> Heap Configuration
|
||||||
|
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Heap_Size EQU 0x00000200
|
||||||
|
|
||||||
|
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||||
|
__heap_base
|
||||||
|
Heap_Mem SPACE Heap_Size
|
||||||
|
__heap_limit
|
||||||
|
|
||||||
|
PRESERVE8
|
||||||
|
THUMB
|
||||||
|
|
||||||
|
|
||||||
|
; Vector Table Mapped to Address 0 at Reset
|
||||||
|
AREA RESET, DATA, READONLY
|
||||||
|
EXPORT __Vectors
|
||||||
|
EXPORT __Vectors_End
|
||||||
|
EXPORT __Vectors_Size
|
||||||
|
|
||||||
|
__Vectors DCD __initial_sp ; Top of Stack
|
||||||
|
DCD Reset_Handler ; Reset Handler
|
||||||
|
DCD NMI_Handler ; NMI Handler
|
||||||
|
DCD HardFault_Handler ; Hard Fault Handler
|
||||||
|
DCD MemManage_Handler ; MPU Fault Handler
|
||||||
|
DCD BusFault_Handler ; Bus Fault Handler
|
||||||
|
DCD UsageFault_Handler ; Usage Fault Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; SVCall Handler
|
||||||
|
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD PendSV_Handler ; PendSV Handler
|
||||||
|
DCD SysTick_Handler ; SysTick Handler
|
||||||
|
|
||||||
|
; External Interrupts
|
||||||
|
DCD WWDG_IRQHandler ; Window Watchdog
|
||||||
|
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||||
|
DCD TAMPER_IRQHandler ; Tamper
|
||||||
|
DCD RTC_IRQHandler ; RTC
|
||||||
|
DCD FLASH_IRQHandler ; Flash
|
||||||
|
DCD RCC_IRQHandler ; RCC
|
||||||
|
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||||
|
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||||
|
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||||
|
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||||
|
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||||
|
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||||
|
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||||
|
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||||
|
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||||
|
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||||
|
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||||
|
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||||
|
DCD ADC1_IRQHandler ; ADC1
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD TIM2_IRQHandler ; TIM2
|
||||||
|
DCD TIM3_IRQHandler ; TIM3
|
||||||
|
DCD TIM4_IRQHandler ; TIM4
|
||||||
|
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||||
|
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||||
|
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||||
|
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||||
|
DCD SPI1_IRQHandler ; SPI1
|
||||||
|
DCD SPI2_IRQHandler ; SPI2
|
||||||
|
DCD USART1_IRQHandler ; USART1
|
||||||
|
DCD USART2_IRQHandler ; USART2
|
||||||
|
DCD USART3_IRQHandler ; USART3
|
||||||
|
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||||
|
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD FSMC_IRQHandler ; FSMC
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD TIM5_IRQHandler ; TIM5
|
||||||
|
DCD SPI3_IRQHandler ; SPI3
|
||||||
|
DCD UART4_IRQHandler ; UART4
|
||||||
|
DCD UART5_IRQHandler ; UART5
|
||||||
|
DCD TIM6_IRQHandler ; TIM6
|
||||||
|
DCD TIM7_IRQHandler ; TIM7
|
||||||
|
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
|
||||||
|
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
|
||||||
|
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
|
||||||
|
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
|
||||||
|
__Vectors_End
|
||||||
|
|
||||||
|
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||||
|
|
||||||
|
AREA |.text|, CODE, READONLY
|
||||||
|
|
||||||
|
; Reset handler
|
||||||
|
Reset_Handler PROC
|
||||||
|
EXPORT Reset_Handler [WEAK]
|
||||||
|
IMPORT __main
|
||||||
|
IMPORT SystemInit
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__main
|
||||||
|
BX R0
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||||
|
|
||||||
|
NMI_Handler PROC
|
||||||
|
EXPORT NMI_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
HardFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT HardFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
MemManage_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT MemManage_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
BusFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT BusFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
UsageFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT UsageFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SVC_Handler PROC
|
||||||
|
EXPORT SVC_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
DebugMon_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT DebugMon_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
PendSV_Handler PROC
|
||||||
|
EXPORT PendSV_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SysTick_Handler PROC
|
||||||
|
EXPORT SysTick_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
Default_Handler PROC
|
||||||
|
|
||||||
|
EXPORT WWDG_IRQHandler [WEAK]
|
||||||
|
EXPORT PVD_IRQHandler [WEAK]
|
||||||
|
EXPORT TAMPER_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_IRQHandler [WEAK]
|
||||||
|
EXPORT FLASH_IRQHandler [WEAK]
|
||||||
|
EXPORT RCC_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI0_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI1_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI2_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI3_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||||
|
EXPORT ADC1_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM2_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM3_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM4_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI1_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI2_IRQHandler [WEAK]
|
||||||
|
EXPORT USART1_IRQHandler [WEAK]
|
||||||
|
EXPORT USART2_IRQHandler [WEAK]
|
||||||
|
EXPORT USART3_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||||
|
EXPORT FSMC_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM5_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI3_IRQHandler [WEAK]
|
||||||
|
EXPORT UART4_IRQHandler [WEAK]
|
||||||
|
EXPORT UART5_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM6_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM7_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Channel1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Channel2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Channel3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
|
||||||
|
|
||||||
|
WWDG_IRQHandler
|
||||||
|
PVD_IRQHandler
|
||||||
|
TAMPER_IRQHandler
|
||||||
|
RTC_IRQHandler
|
||||||
|
FLASH_IRQHandler
|
||||||
|
RCC_IRQHandler
|
||||||
|
EXTI0_IRQHandler
|
||||||
|
EXTI1_IRQHandler
|
||||||
|
EXTI2_IRQHandler
|
||||||
|
EXTI3_IRQHandler
|
||||||
|
EXTI4_IRQHandler
|
||||||
|
DMA1_Channel1_IRQHandler
|
||||||
|
DMA1_Channel2_IRQHandler
|
||||||
|
DMA1_Channel3_IRQHandler
|
||||||
|
DMA1_Channel4_IRQHandler
|
||||||
|
DMA1_Channel5_IRQHandler
|
||||||
|
DMA1_Channel6_IRQHandler
|
||||||
|
DMA1_Channel7_IRQHandler
|
||||||
|
ADC1_IRQHandler
|
||||||
|
EXTI9_5_IRQHandler
|
||||||
|
TIM2_IRQHandler
|
||||||
|
TIM3_IRQHandler
|
||||||
|
TIM4_IRQHandler
|
||||||
|
I2C1_EV_IRQHandler
|
||||||
|
I2C1_ER_IRQHandler
|
||||||
|
I2C2_EV_IRQHandler
|
||||||
|
I2C2_ER_IRQHandler
|
||||||
|
SPI1_IRQHandler
|
||||||
|
SPI2_IRQHandler
|
||||||
|
USART1_IRQHandler
|
||||||
|
USART2_IRQHandler
|
||||||
|
USART3_IRQHandler
|
||||||
|
EXTI15_10_IRQHandler
|
||||||
|
RTC_Alarm_IRQHandler
|
||||||
|
FSMC_IRQHandler
|
||||||
|
TIM5_IRQHandler
|
||||||
|
SPI3_IRQHandler
|
||||||
|
UART4_IRQHandler
|
||||||
|
UART5_IRQHandler
|
||||||
|
TIM6_IRQHandler
|
||||||
|
TIM7_IRQHandler
|
||||||
|
DMA2_Channel1_IRQHandler
|
||||||
|
DMA2_Channel2_IRQHandler
|
||||||
|
DMA2_Channel3_IRQHandler
|
||||||
|
DMA2_Channel4_5_IRQHandler
|
||||||
|
B .
|
||||||
|
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
;*******************************************************************************
|
||||||
|
; User Stack and Heap initialization
|
||||||
|
;*******************************************************************************
|
||||||
|
IF :DEF:__MICROLIB
|
||||||
|
|
||||||
|
EXPORT __initial_sp
|
||||||
|
EXPORT __heap_base
|
||||||
|
EXPORT __heap_limit
|
||||||
|
|
||||||
|
ELSE
|
||||||
|
|
||||||
|
IMPORT __use_two_region_memory
|
||||||
|
EXPORT __user_initial_stackheap
|
||||||
|
|
||||||
|
__user_initial_stackheap
|
||||||
|
|
||||||
|
LDR R0, = Heap_Mem
|
||||||
|
LDR R1, =(Stack_Mem + Stack_Size)
|
||||||
|
LDR R2, = (Heap_Mem + Heap_Size)
|
||||||
|
LDR R3, = Stack_Mem
|
||||||
|
BX LR
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
ENDIF
|
||||||
|
|
||||||
|
END
|
||||||
|
|
||||||
|
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||||
|
|
@ -0,0 +1,355 @@
|
||||||
|
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
|
||||||
|
;* File Name : startup_stm32f101xg.s
|
||||||
|
;* Author : MCD Application Team
|
||||||
|
;* Version : V4.2.0
|
||||||
|
;* Date : 31-March-2017
|
||||||
|
;* Description : STM32F101xG Devices vector table for MDK-ARM toolchain.
|
||||||
|
;* This module performs:
|
||||||
|
;* - Set the initial SP
|
||||||
|
;* - Set the initial PC == Reset_Handler
|
||||||
|
;* - Set the vector table entries with the exceptions ISR address
|
||||||
|
;* - Configure the clock system
|
||||||
|
;* - Branches to __main in the C library (which eventually
|
||||||
|
;* calls main()).
|
||||||
|
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||||
|
;* priority is Privileged, and the Stack is set to Main.
|
||||||
|
;********************************************************************************
|
||||||
|
;*
|
||||||
|
;* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||||
|
;*
|
||||||
|
;* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
;* are permitted provided that the following conditions are met:
|
||||||
|
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
;* this list of conditions and the following disclaimer.
|
||||||
|
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
;* this list of conditions and the following disclaimer in the documentation
|
||||||
|
;* and/or other materials provided with the distribution.
|
||||||
|
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
;* may be used to endorse or promote products derived from this software
|
||||||
|
;* without specific prior written permission.
|
||||||
|
;*
|
||||||
|
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
;
|
||||||
|
;*******************************************************************************
|
||||||
|
|
||||||
|
; Amount of memory (in bytes) allocated for Stack
|
||||||
|
; Tailor this value to your application needs
|
||||||
|
; <h> Stack Configuration
|
||||||
|
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Stack_Size EQU 0x00000400
|
||||||
|
|
||||||
|
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||||
|
Stack_Mem SPACE Stack_Size
|
||||||
|
__initial_sp
|
||||||
|
|
||||||
|
; <h> Heap Configuration
|
||||||
|
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Heap_Size EQU 0x00000200
|
||||||
|
|
||||||
|
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||||
|
__heap_base
|
||||||
|
Heap_Mem SPACE Heap_Size
|
||||||
|
__heap_limit
|
||||||
|
|
||||||
|
PRESERVE8
|
||||||
|
THUMB
|
||||||
|
|
||||||
|
|
||||||
|
; Vector Table Mapped to Address 0 at Reset
|
||||||
|
AREA RESET, DATA, READONLY
|
||||||
|
EXPORT __Vectors
|
||||||
|
EXPORT __Vectors_End
|
||||||
|
EXPORT __Vectors_Size
|
||||||
|
|
||||||
|
__Vectors DCD __initial_sp ; Top of Stack
|
||||||
|
DCD Reset_Handler ; Reset Handler
|
||||||
|
DCD NMI_Handler ; NMI Handler
|
||||||
|
DCD HardFault_Handler ; Hard Fault Handler
|
||||||
|
DCD MemManage_Handler ; MPU Fault Handler
|
||||||
|
DCD BusFault_Handler ; Bus Fault Handler
|
||||||
|
DCD UsageFault_Handler ; Usage Fault Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; SVCall Handler
|
||||||
|
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD PendSV_Handler ; PendSV Handler
|
||||||
|
DCD SysTick_Handler ; SysTick Handler
|
||||||
|
|
||||||
|
; External Interrupts
|
||||||
|
DCD WWDG_IRQHandler ; Window Watchdog
|
||||||
|
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||||
|
DCD TAMPER_IRQHandler ; Tamper
|
||||||
|
DCD RTC_IRQHandler ; RTC
|
||||||
|
DCD FLASH_IRQHandler ; Flash
|
||||||
|
DCD RCC_IRQHandler ; RCC
|
||||||
|
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||||
|
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||||
|
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||||
|
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||||
|
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||||
|
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||||
|
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||||
|
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||||
|
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||||
|
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||||
|
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||||
|
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||||
|
DCD ADC1_2_IRQHandler ; ADC1_2
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||||
|
DCD TIM9_IRQHandler ; TIM9
|
||||||
|
DCD TIM10_IRQHandler ; TIM10
|
||||||
|
DCD TIM11_IRQHandler ; TIM11
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD TIM2_IRQHandler ; TIM2
|
||||||
|
DCD TIM3_IRQHandler ; TIM3
|
||||||
|
DCD TIM4_IRQHandler ; TIM4
|
||||||
|
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||||
|
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||||
|
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||||
|
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||||
|
DCD SPI1_IRQHandler ; SPI1
|
||||||
|
DCD SPI2_IRQHandler ; SPI2
|
||||||
|
DCD USART1_IRQHandler ; USART1
|
||||||
|
DCD USART2_IRQHandler ; USART2
|
||||||
|
DCD USART3_IRQHandler ; USART3
|
||||||
|
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||||
|
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD TIM12_IRQHandler ; TIM12
|
||||||
|
DCD TIM13_IRQHandler ; TIM13
|
||||||
|
DCD TIM14_IRQHandler ; TIM14
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD FSMC_IRQHandler ; FSMC
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD TIM5_IRQHandler ; TIM5
|
||||||
|
DCD SPI3_IRQHandler ; SPI3
|
||||||
|
DCD UART4_IRQHandler ; UART4
|
||||||
|
DCD UART5_IRQHandler ; UART5
|
||||||
|
DCD TIM6_IRQHandler ; TIM6
|
||||||
|
DCD TIM7_IRQHandler ; TIM7
|
||||||
|
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
|
||||||
|
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
|
||||||
|
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
|
||||||
|
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
|
||||||
|
__Vectors_End
|
||||||
|
|
||||||
|
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||||
|
|
||||||
|
AREA |.text|, CODE, READONLY
|
||||||
|
|
||||||
|
; Reset handler
|
||||||
|
Reset_Handler PROC
|
||||||
|
EXPORT Reset_Handler [WEAK]
|
||||||
|
IMPORT __main
|
||||||
|
IMPORT SystemInit
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__main
|
||||||
|
BX R0
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||||
|
|
||||||
|
NMI_Handler PROC
|
||||||
|
EXPORT NMI_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
HardFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT HardFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
MemManage_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT MemManage_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
BusFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT BusFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
UsageFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT UsageFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SVC_Handler PROC
|
||||||
|
EXPORT SVC_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
DebugMon_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT DebugMon_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
PendSV_Handler PROC
|
||||||
|
EXPORT PendSV_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SysTick_Handler PROC
|
||||||
|
EXPORT SysTick_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
Default_Handler PROC
|
||||||
|
|
||||||
|
EXPORT WWDG_IRQHandler [WEAK]
|
||||||
|
EXPORT PVD_IRQHandler [WEAK]
|
||||||
|
EXPORT TAMPER_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_IRQHandler [WEAK]
|
||||||
|
EXPORT FLASH_IRQHandler [WEAK]
|
||||||
|
EXPORT RCC_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI0_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI1_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI2_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI3_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||||
|
EXPORT ADC1_2_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM9_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM10_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM11_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM2_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM3_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM4_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI1_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI2_IRQHandler [WEAK]
|
||||||
|
EXPORT USART1_IRQHandler [WEAK]
|
||||||
|
EXPORT USART2_IRQHandler [WEAK]
|
||||||
|
EXPORT USART3_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM12_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM13_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM14_IRQHandler [WEAK]
|
||||||
|
EXPORT FSMC_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM5_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI3_IRQHandler [WEAK]
|
||||||
|
EXPORT UART4_IRQHandler [WEAK]
|
||||||
|
EXPORT UART5_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM6_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM7_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Channel1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Channel2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Channel3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
|
||||||
|
|
||||||
|
WWDG_IRQHandler
|
||||||
|
PVD_IRQHandler
|
||||||
|
TAMPER_IRQHandler
|
||||||
|
RTC_IRQHandler
|
||||||
|
FLASH_IRQHandler
|
||||||
|
RCC_IRQHandler
|
||||||
|
EXTI0_IRQHandler
|
||||||
|
EXTI1_IRQHandler
|
||||||
|
EXTI2_IRQHandler
|
||||||
|
EXTI3_IRQHandler
|
||||||
|
EXTI4_IRQHandler
|
||||||
|
DMA1_Channel1_IRQHandler
|
||||||
|
DMA1_Channel2_IRQHandler
|
||||||
|
DMA1_Channel3_IRQHandler
|
||||||
|
DMA1_Channel4_IRQHandler
|
||||||
|
DMA1_Channel5_IRQHandler
|
||||||
|
DMA1_Channel6_IRQHandler
|
||||||
|
DMA1_Channel7_IRQHandler
|
||||||
|
ADC1_2_IRQHandler
|
||||||
|
EXTI9_5_IRQHandler
|
||||||
|
TIM9_IRQHandler
|
||||||
|
TIM10_IRQHandler
|
||||||
|
TIM11_IRQHandler
|
||||||
|
TIM2_IRQHandler
|
||||||
|
TIM3_IRQHandler
|
||||||
|
TIM4_IRQHandler
|
||||||
|
I2C1_EV_IRQHandler
|
||||||
|
I2C1_ER_IRQHandler
|
||||||
|
I2C2_EV_IRQHandler
|
||||||
|
I2C2_ER_IRQHandler
|
||||||
|
SPI1_IRQHandler
|
||||||
|
SPI2_IRQHandler
|
||||||
|
USART1_IRQHandler
|
||||||
|
USART2_IRQHandler
|
||||||
|
USART3_IRQHandler
|
||||||
|
EXTI15_10_IRQHandler
|
||||||
|
RTC_Alarm_IRQHandler
|
||||||
|
TIM12_IRQHandler
|
||||||
|
TIM13_IRQHandler
|
||||||
|
TIM14_IRQHandler
|
||||||
|
FSMC_IRQHandler
|
||||||
|
TIM5_IRQHandler
|
||||||
|
SPI3_IRQHandler
|
||||||
|
UART4_IRQHandler
|
||||||
|
UART5_IRQHandler
|
||||||
|
TIM6_IRQHandler
|
||||||
|
TIM7_IRQHandler
|
||||||
|
DMA2_Channel1_IRQHandler
|
||||||
|
DMA2_Channel2_IRQHandler
|
||||||
|
DMA2_Channel3_IRQHandler
|
||||||
|
DMA2_Channel4_5_IRQHandler
|
||||||
|
B .
|
||||||
|
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
;*******************************************************************************
|
||||||
|
; User Stack and Heap initialization
|
||||||
|
;*******************************************************************************
|
||||||
|
IF :DEF:__MICROLIB
|
||||||
|
|
||||||
|
EXPORT __initial_sp
|
||||||
|
EXPORT __heap_base
|
||||||
|
EXPORT __heap_limit
|
||||||
|
|
||||||
|
ELSE
|
||||||
|
|
||||||
|
IMPORT __use_two_region_memory
|
||||||
|
EXPORT __user_initial_stackheap
|
||||||
|
|
||||||
|
__user_initial_stackheap
|
||||||
|
|
||||||
|
LDR R0, = Heap_Mem
|
||||||
|
LDR R1, =(Stack_Mem + Stack_Size)
|
||||||
|
LDR R2, = (Heap_Mem + Heap_Size)
|
||||||
|
LDR R3, = Stack_Mem
|
||||||
|
BX LR
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
ENDIF
|
||||||
|
|
||||||
|
END
|
||||||
|
|
||||||
|
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||||
|
|
@ -0,0 +1,302 @@
|
||||||
|
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
|
||||||
|
;* File Name : startup_stm32f102x6.s
|
||||||
|
;* Author : MCD Application Team
|
||||||
|
;* Version : V4.2.0
|
||||||
|
;* Date : 31-March-2017
|
||||||
|
;* Description : STM32F102x6 Devices vector table for MDK-ARM toolchain.
|
||||||
|
;* This module performs:
|
||||||
|
;* - Set the initial SP
|
||||||
|
;* - Set the initial PC == Reset_Handler
|
||||||
|
;* - Set the vector table entries with the exceptions ISR address
|
||||||
|
;* - Configure the clock system
|
||||||
|
;* - Branches to __main in the C library (which eventually
|
||||||
|
;* calls main()).
|
||||||
|
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||||
|
;* priority is Privileged, and the Stack is set to Main.
|
||||||
|
;********************************************************************************
|
||||||
|
;*
|
||||||
|
;* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||||
|
;*
|
||||||
|
;* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
;* are permitted provided that the following conditions are met:
|
||||||
|
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
;* this list of conditions and the following disclaimer.
|
||||||
|
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
;* this list of conditions and the following disclaimer in the documentation
|
||||||
|
;* and/or other materials provided with the distribution.
|
||||||
|
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
;* may be used to endorse or promote products derived from this software
|
||||||
|
;* without specific prior written permission.
|
||||||
|
;*
|
||||||
|
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
;
|
||||||
|
;*******************************************************************************
|
||||||
|
|
||||||
|
; Amount of memory (in bytes) allocated for Stack
|
||||||
|
; Tailor this value to your application needs
|
||||||
|
; <h> Stack Configuration
|
||||||
|
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Stack_Size EQU 0x00000400
|
||||||
|
|
||||||
|
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||||
|
Stack_Mem SPACE Stack_Size
|
||||||
|
__initial_sp
|
||||||
|
|
||||||
|
|
||||||
|
; <h> Heap Configuration
|
||||||
|
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Heap_Size EQU 0x00000200
|
||||||
|
|
||||||
|
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||||
|
__heap_base
|
||||||
|
Heap_Mem SPACE Heap_Size
|
||||||
|
__heap_limit
|
||||||
|
|
||||||
|
PRESERVE8
|
||||||
|
THUMB
|
||||||
|
|
||||||
|
|
||||||
|
; Vector Table Mapped to Address 0 at Reset
|
||||||
|
AREA RESET, DATA, READONLY
|
||||||
|
EXPORT __Vectors
|
||||||
|
EXPORT __Vectors_End
|
||||||
|
EXPORT __Vectors_Size
|
||||||
|
|
||||||
|
__Vectors DCD __initial_sp ; Top of Stack
|
||||||
|
DCD Reset_Handler ; Reset Handler
|
||||||
|
DCD NMI_Handler ; NMI Handler
|
||||||
|
DCD HardFault_Handler ; Hard Fault Handler
|
||||||
|
DCD MemManage_Handler ; MPU Fault Handler
|
||||||
|
DCD BusFault_Handler ; Bus Fault Handler
|
||||||
|
DCD UsageFault_Handler ; Usage Fault Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; SVCall Handler
|
||||||
|
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD PendSV_Handler ; PendSV Handler
|
||||||
|
DCD SysTick_Handler ; SysTick Handler
|
||||||
|
|
||||||
|
; External Interrupts
|
||||||
|
DCD WWDG_IRQHandler ; Window Watchdog
|
||||||
|
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||||
|
DCD TAMPER_IRQHandler ; Tamper
|
||||||
|
DCD RTC_IRQHandler ; RTC
|
||||||
|
DCD FLASH_IRQHandler ; Flash
|
||||||
|
DCD RCC_IRQHandler ; RCC
|
||||||
|
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||||
|
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||||
|
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||||
|
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||||
|
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||||
|
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||||
|
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||||
|
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||||
|
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||||
|
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||||
|
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||||
|
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||||
|
DCD ADC1_IRQHandler ; ADC1
|
||||||
|
DCD USB_HP_IRQHandler ; USB High Priority
|
||||||
|
DCD USB_LP_IRQHandler ; USB Low Priority
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD TIM2_IRQHandler ; TIM2
|
||||||
|
DCD TIM3_IRQHandler ; TIM3
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||||
|
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SPI1_IRQHandler ; SPI1
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD USART1_IRQHandler ; USART1
|
||||||
|
DCD USART2_IRQHandler ; USART2
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||||
|
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
|
||||||
|
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
|
||||||
|
__Vectors_End
|
||||||
|
|
||||||
|
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||||
|
|
||||||
|
AREA |.text|, CODE, READONLY
|
||||||
|
|
||||||
|
; Reset handler routine
|
||||||
|
Reset_Handler PROC
|
||||||
|
EXPORT Reset_Handler [WEAK]
|
||||||
|
IMPORT __main
|
||||||
|
IMPORT SystemInit
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__main
|
||||||
|
BX R0
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||||
|
|
||||||
|
NMI_Handler PROC
|
||||||
|
EXPORT NMI_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
HardFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT HardFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
MemManage_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT MemManage_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
BusFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT BusFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
UsageFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT UsageFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SVC_Handler PROC
|
||||||
|
EXPORT SVC_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
DebugMon_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT DebugMon_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
PendSV_Handler PROC
|
||||||
|
EXPORT PendSV_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SysTick_Handler PROC
|
||||||
|
EXPORT SysTick_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
Default_Handler PROC
|
||||||
|
|
||||||
|
EXPORT WWDG_IRQHandler [WEAK]
|
||||||
|
EXPORT PVD_IRQHandler [WEAK]
|
||||||
|
EXPORT TAMPER_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_IRQHandler [WEAK]
|
||||||
|
EXPORT FLASH_IRQHandler [WEAK]
|
||||||
|
EXPORT RCC_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI0_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI1_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI2_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI3_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||||
|
EXPORT ADC1_IRQHandler [WEAK]
|
||||||
|
EXPORT USB_HP_IRQHandler [WEAK]
|
||||||
|
EXPORT USB_LP_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM2_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM3_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI1_IRQHandler [WEAK]
|
||||||
|
EXPORT USART1_IRQHandler [WEAK]
|
||||||
|
EXPORT USART2_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||||
|
EXPORT USBWakeUp_IRQHandler [WEAK]
|
||||||
|
|
||||||
|
WWDG_IRQHandler
|
||||||
|
PVD_IRQHandler
|
||||||
|
TAMPER_IRQHandler
|
||||||
|
RTC_IRQHandler
|
||||||
|
FLASH_IRQHandler
|
||||||
|
RCC_IRQHandler
|
||||||
|
EXTI0_IRQHandler
|
||||||
|
EXTI1_IRQHandler
|
||||||
|
EXTI2_IRQHandler
|
||||||
|
EXTI3_IRQHandler
|
||||||
|
EXTI4_IRQHandler
|
||||||
|
DMA1_Channel1_IRQHandler
|
||||||
|
DMA1_Channel2_IRQHandler
|
||||||
|
DMA1_Channel3_IRQHandler
|
||||||
|
DMA1_Channel4_IRQHandler
|
||||||
|
DMA1_Channel5_IRQHandler
|
||||||
|
DMA1_Channel6_IRQHandler
|
||||||
|
DMA1_Channel7_IRQHandler
|
||||||
|
ADC1_IRQHandler
|
||||||
|
USB_HP_IRQHandler
|
||||||
|
USB_LP_IRQHandler
|
||||||
|
EXTI9_5_IRQHandler
|
||||||
|
TIM2_IRQHandler
|
||||||
|
TIM3_IRQHandler
|
||||||
|
I2C1_EV_IRQHandler
|
||||||
|
I2C1_ER_IRQHandler
|
||||||
|
SPI1_IRQHandler
|
||||||
|
USART1_IRQHandler
|
||||||
|
USART2_IRQHandler
|
||||||
|
EXTI15_10_IRQHandler
|
||||||
|
RTC_Alarm_IRQHandler
|
||||||
|
USBWakeUp_IRQHandler
|
||||||
|
|
||||||
|
B .
|
||||||
|
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
;*******************************************************************************
|
||||||
|
; User Stack and Heap initialization
|
||||||
|
;*******************************************************************************
|
||||||
|
IF :DEF:__MICROLIB
|
||||||
|
|
||||||
|
EXPORT __initial_sp
|
||||||
|
EXPORT __heap_base
|
||||||
|
EXPORT __heap_limit
|
||||||
|
|
||||||
|
ELSE
|
||||||
|
|
||||||
|
IMPORT __use_two_region_memory
|
||||||
|
EXPORT __user_initial_stackheap
|
||||||
|
|
||||||
|
__user_initial_stackheap
|
||||||
|
|
||||||
|
LDR R0, = Heap_Mem
|
||||||
|
LDR R1, =(Stack_Mem + Stack_Size)
|
||||||
|
LDR R2, = (Heap_Mem + Heap_Size)
|
||||||
|
LDR R3, = Stack_Mem
|
||||||
|
BX LR
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
ENDIF
|
||||||
|
|
||||||
|
END
|
||||||
|
|
||||||
|
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||||
|
|
@ -0,0 +1,312 @@
|
||||||
|
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
|
||||||
|
;* File Name : startup_stm32f102xb.s
|
||||||
|
;* Author : MCD Application Team
|
||||||
|
;* Version : V4.2.0
|
||||||
|
;* Date : 31-March-2017
|
||||||
|
;* Description : STM32F102xB Devices vector table for MDK-ARM toolchain.
|
||||||
|
;* This module performs:
|
||||||
|
;* - Set the initial SP
|
||||||
|
;* - Set the initial PC == Reset_Handler
|
||||||
|
;* - Set the vector table entries with the exceptions ISR address
|
||||||
|
;* - Configure the clock system
|
||||||
|
;* - Branches to __main in the C library (which eventually
|
||||||
|
;* calls main()).
|
||||||
|
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||||
|
;* priority is Privileged, and the Stack is set to Main.
|
||||||
|
;********************************************************************************
|
||||||
|
;*
|
||||||
|
;* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||||
|
;*
|
||||||
|
;* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
;* are permitted provided that the following conditions are met:
|
||||||
|
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
;* this list of conditions and the following disclaimer.
|
||||||
|
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
;* this list of conditions and the following disclaimer in the documentation
|
||||||
|
;* and/or other materials provided with the distribution.
|
||||||
|
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
;* may be used to endorse or promote products derived from this software
|
||||||
|
;* without specific prior written permission.
|
||||||
|
;*
|
||||||
|
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
;
|
||||||
|
;*******************************************************************************
|
||||||
|
|
||||||
|
; Amount of memory (in bytes) allocated for Stack
|
||||||
|
; Tailor this value to your application needs
|
||||||
|
; <h> Stack Configuration
|
||||||
|
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Stack_Size EQU 0x00000400
|
||||||
|
|
||||||
|
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||||
|
Stack_Mem SPACE Stack_Size
|
||||||
|
__initial_sp
|
||||||
|
|
||||||
|
|
||||||
|
; <h> Heap Configuration
|
||||||
|
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Heap_Size EQU 0x00000200
|
||||||
|
|
||||||
|
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||||
|
__heap_base
|
||||||
|
Heap_Mem SPACE Heap_Size
|
||||||
|
__heap_limit
|
||||||
|
|
||||||
|
PRESERVE8
|
||||||
|
THUMB
|
||||||
|
|
||||||
|
|
||||||
|
; Vector Table Mapped to Address 0 at Reset
|
||||||
|
AREA RESET, DATA, READONLY
|
||||||
|
EXPORT __Vectors
|
||||||
|
EXPORT __Vectors_End
|
||||||
|
EXPORT __Vectors_Size
|
||||||
|
|
||||||
|
__Vectors DCD __initial_sp ; Top of Stack
|
||||||
|
DCD Reset_Handler ; Reset Handler
|
||||||
|
DCD NMI_Handler ; NMI Handler
|
||||||
|
DCD HardFault_Handler ; Hard Fault Handler
|
||||||
|
DCD MemManage_Handler ; MPU Fault Handler
|
||||||
|
DCD BusFault_Handler ; Bus Fault Handler
|
||||||
|
DCD UsageFault_Handler ; Usage Fault Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; SVCall Handler
|
||||||
|
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD PendSV_Handler ; PendSV Handler
|
||||||
|
DCD SysTick_Handler ; SysTick Handler
|
||||||
|
|
||||||
|
; External Interrupts
|
||||||
|
DCD WWDG_IRQHandler ; Window Watchdog
|
||||||
|
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||||
|
DCD TAMPER_IRQHandler ; Tamper
|
||||||
|
DCD RTC_IRQHandler ; RTC
|
||||||
|
DCD FLASH_IRQHandler ; Flash
|
||||||
|
DCD RCC_IRQHandler ; RCC
|
||||||
|
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||||
|
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||||
|
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||||
|
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||||
|
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||||
|
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||||
|
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||||
|
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||||
|
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||||
|
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||||
|
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||||
|
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||||
|
DCD ADC1_IRQHandler ; ADC1
|
||||||
|
DCD USB_HP_IRQHandler ; USB High Priority
|
||||||
|
DCD USB_LP_IRQHandler ; USB Low Priority
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD TIM2_IRQHandler ; TIM2
|
||||||
|
DCD TIM3_IRQHandler ; TIM3
|
||||||
|
DCD TIM4_IRQHandler ; TIM4
|
||||||
|
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||||
|
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||||
|
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||||
|
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||||
|
DCD SPI1_IRQHandler ; SPI1
|
||||||
|
DCD SPI2_IRQHandler ; SPI2
|
||||||
|
DCD USART1_IRQHandler ; USART1
|
||||||
|
DCD USART2_IRQHandler ; USART2
|
||||||
|
DCD USART3_IRQHandler ; USART3
|
||||||
|
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||||
|
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
|
||||||
|
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
|
||||||
|
__Vectors_End
|
||||||
|
|
||||||
|
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||||
|
|
||||||
|
AREA |.text|, CODE, READONLY
|
||||||
|
|
||||||
|
; Reset handler
|
||||||
|
Reset_Handler PROC
|
||||||
|
EXPORT Reset_Handler [WEAK]
|
||||||
|
IMPORT __main
|
||||||
|
IMPORT SystemInit
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__main
|
||||||
|
BX R0
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||||
|
|
||||||
|
NMI_Handler PROC
|
||||||
|
EXPORT NMI_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
HardFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT HardFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
MemManage_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT MemManage_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
BusFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT BusFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
UsageFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT UsageFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SVC_Handler PROC
|
||||||
|
EXPORT SVC_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
DebugMon_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT DebugMon_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
PendSV_Handler PROC
|
||||||
|
EXPORT PendSV_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SysTick_Handler PROC
|
||||||
|
EXPORT SysTick_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
Default_Handler PROC
|
||||||
|
|
||||||
|
EXPORT WWDG_IRQHandler [WEAK]
|
||||||
|
EXPORT PVD_IRQHandler [WEAK]
|
||||||
|
EXPORT TAMPER_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_IRQHandler [WEAK]
|
||||||
|
EXPORT FLASH_IRQHandler [WEAK]
|
||||||
|
EXPORT RCC_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI0_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI1_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI2_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI3_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||||
|
EXPORT ADC1_IRQHandler [WEAK]
|
||||||
|
EXPORT USB_HP_IRQHandler [WEAK]
|
||||||
|
EXPORT USB_LP_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM2_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM3_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM4_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI1_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI2_IRQHandler [WEAK]
|
||||||
|
EXPORT USART1_IRQHandler [WEAK]
|
||||||
|
EXPORT USART2_IRQHandler [WEAK]
|
||||||
|
EXPORT USART3_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||||
|
EXPORT USBWakeUp_IRQHandler [WEAK]
|
||||||
|
|
||||||
|
WWDG_IRQHandler
|
||||||
|
PVD_IRQHandler
|
||||||
|
TAMPER_IRQHandler
|
||||||
|
RTC_IRQHandler
|
||||||
|
FLASH_IRQHandler
|
||||||
|
RCC_IRQHandler
|
||||||
|
EXTI0_IRQHandler
|
||||||
|
EXTI1_IRQHandler
|
||||||
|
EXTI2_IRQHandler
|
||||||
|
EXTI3_IRQHandler
|
||||||
|
EXTI4_IRQHandler
|
||||||
|
DMA1_Channel1_IRQHandler
|
||||||
|
DMA1_Channel2_IRQHandler
|
||||||
|
DMA1_Channel3_IRQHandler
|
||||||
|
DMA1_Channel4_IRQHandler
|
||||||
|
DMA1_Channel5_IRQHandler
|
||||||
|
DMA1_Channel6_IRQHandler
|
||||||
|
DMA1_Channel7_IRQHandler
|
||||||
|
ADC1_IRQHandler
|
||||||
|
USB_HP_IRQHandler
|
||||||
|
USB_LP_IRQHandler
|
||||||
|
EXTI9_5_IRQHandler
|
||||||
|
TIM2_IRQHandler
|
||||||
|
TIM3_IRQHandler
|
||||||
|
TIM4_IRQHandler
|
||||||
|
I2C1_EV_IRQHandler
|
||||||
|
I2C1_ER_IRQHandler
|
||||||
|
I2C2_EV_IRQHandler
|
||||||
|
I2C2_ER_IRQHandler
|
||||||
|
SPI1_IRQHandler
|
||||||
|
SPI2_IRQHandler
|
||||||
|
USART1_IRQHandler
|
||||||
|
USART2_IRQHandler
|
||||||
|
USART3_IRQHandler
|
||||||
|
EXTI15_10_IRQHandler
|
||||||
|
RTC_Alarm_IRQHandler
|
||||||
|
USBWakeUp_IRQHandler
|
||||||
|
|
||||||
|
B .
|
||||||
|
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
;*******************************************************************************
|
||||||
|
; User Stack and Heap initialization
|
||||||
|
;*******************************************************************************
|
||||||
|
IF :DEF:__MICROLIB
|
||||||
|
|
||||||
|
EXPORT __initial_sp
|
||||||
|
EXPORT __heap_base
|
||||||
|
EXPORT __heap_limit
|
||||||
|
|
||||||
|
ELSE
|
||||||
|
|
||||||
|
IMPORT __use_two_region_memory
|
||||||
|
EXPORT __user_initial_stackheap
|
||||||
|
|
||||||
|
__user_initial_stackheap
|
||||||
|
|
||||||
|
LDR R0, = Heap_Mem
|
||||||
|
LDR R1, =(Stack_Mem + Stack_Size)
|
||||||
|
LDR R2, = (Heap_Mem + Heap_Size)
|
||||||
|
LDR R3, = Stack_Mem
|
||||||
|
BX LR
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
ENDIF
|
||||||
|
|
||||||
|
END
|
||||||
|
|
||||||
|
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||||
|
|
@ -0,0 +1,314 @@
|
||||||
|
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
|
||||||
|
;* File Name : startup_stm32f103x6.s
|
||||||
|
;* Author : MCD Application Team
|
||||||
|
;* Version : V4.2.0
|
||||||
|
;* Date : 31-March-2017
|
||||||
|
;* Description : STM32F103x6 Devices vector table for MDK-ARM toolchain.
|
||||||
|
;* This module performs:
|
||||||
|
;* - Set the initial SP
|
||||||
|
;* - Set the initial PC == Reset_Handler
|
||||||
|
;* - Set the vector table entries with the exceptions ISR address
|
||||||
|
;* - Configure the clock system
|
||||||
|
;* - Branches to __main in the C library (which eventually
|
||||||
|
;* calls main()).
|
||||||
|
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||||
|
;* priority is Privileged, and the Stack is set to Main.
|
||||||
|
;********************************************************************************
|
||||||
|
;*
|
||||||
|
;* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||||
|
;*
|
||||||
|
;* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
;* are permitted provided that the following conditions are met:
|
||||||
|
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
;* this list of conditions and the following disclaimer.
|
||||||
|
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
;* this list of conditions and the following disclaimer in the documentation
|
||||||
|
;* and/or other materials provided with the distribution.
|
||||||
|
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
;* may be used to endorse or promote products derived from this software
|
||||||
|
;* without specific prior written permission.
|
||||||
|
;*
|
||||||
|
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
;
|
||||||
|
;*******************************************************************************
|
||||||
|
|
||||||
|
; Amount of memory (in bytes) allocated for Stack
|
||||||
|
; Tailor this value to your application needs
|
||||||
|
; <h> Stack Configuration
|
||||||
|
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Stack_Size EQU 0x00000400
|
||||||
|
|
||||||
|
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||||
|
Stack_Mem SPACE Stack_Size
|
||||||
|
__initial_sp
|
||||||
|
|
||||||
|
|
||||||
|
; <h> Heap Configuration
|
||||||
|
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Heap_Size EQU 0x00000200
|
||||||
|
|
||||||
|
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||||
|
__heap_base
|
||||||
|
Heap_Mem SPACE Heap_Size
|
||||||
|
__heap_limit
|
||||||
|
|
||||||
|
PRESERVE8
|
||||||
|
THUMB
|
||||||
|
|
||||||
|
|
||||||
|
; Vector Table Mapped to Address 0 at Reset
|
||||||
|
AREA RESET, DATA, READONLY
|
||||||
|
EXPORT __Vectors
|
||||||
|
EXPORT __Vectors_End
|
||||||
|
EXPORT __Vectors_Size
|
||||||
|
|
||||||
|
__Vectors DCD __initial_sp ; Top of Stack
|
||||||
|
DCD Reset_Handler ; Reset Handler
|
||||||
|
DCD NMI_Handler ; NMI Handler
|
||||||
|
DCD HardFault_Handler ; Hard Fault Handler
|
||||||
|
DCD MemManage_Handler ; MPU Fault Handler
|
||||||
|
DCD BusFault_Handler ; Bus Fault Handler
|
||||||
|
DCD UsageFault_Handler ; Usage Fault Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; SVCall Handler
|
||||||
|
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD PendSV_Handler ; PendSV Handler
|
||||||
|
DCD SysTick_Handler ; SysTick Handler
|
||||||
|
|
||||||
|
; External Interrupts
|
||||||
|
DCD WWDG_IRQHandler ; Window Watchdog
|
||||||
|
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||||
|
DCD TAMPER_IRQHandler ; Tamper
|
||||||
|
DCD RTC_IRQHandler ; RTC
|
||||||
|
DCD FLASH_IRQHandler ; Flash
|
||||||
|
DCD RCC_IRQHandler ; RCC
|
||||||
|
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||||
|
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||||
|
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||||
|
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||||
|
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||||
|
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||||
|
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||||
|
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||||
|
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||||
|
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||||
|
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||||
|
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||||
|
DCD ADC1_2_IRQHandler ; ADC1_2
|
||||||
|
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
|
||||||
|
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
|
||||||
|
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
|
||||||
|
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
|
||||||
|
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||||
|
DCD TIM1_BRK_IRQHandler ; TIM1 Break
|
||||||
|
DCD TIM1_UP_IRQHandler ; TIM1 Update
|
||||||
|
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
|
||||||
|
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||||
|
DCD TIM2_IRQHandler ; TIM2
|
||||||
|
DCD TIM3_IRQHandler ; TIM3
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||||
|
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SPI1_IRQHandler ; SPI1
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD USART1_IRQHandler ; USART1
|
||||||
|
DCD USART2_IRQHandler ; USART2
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||||
|
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
|
||||||
|
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
|
||||||
|
__Vectors_End
|
||||||
|
|
||||||
|
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||||
|
|
||||||
|
AREA |.text|, CODE, READONLY
|
||||||
|
|
||||||
|
; Reset handler routine
|
||||||
|
Reset_Handler PROC
|
||||||
|
EXPORT Reset_Handler [WEAK]
|
||||||
|
IMPORT __main
|
||||||
|
IMPORT SystemInit
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__main
|
||||||
|
BX R0
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||||
|
|
||||||
|
NMI_Handler PROC
|
||||||
|
EXPORT NMI_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
HardFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT HardFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
MemManage_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT MemManage_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
BusFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT BusFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
UsageFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT UsageFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SVC_Handler PROC
|
||||||
|
EXPORT SVC_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
DebugMon_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT DebugMon_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
PendSV_Handler PROC
|
||||||
|
EXPORT PendSV_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SysTick_Handler PROC
|
||||||
|
EXPORT SysTick_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
Default_Handler PROC
|
||||||
|
|
||||||
|
EXPORT WWDG_IRQHandler [WEAK]
|
||||||
|
EXPORT PVD_IRQHandler [WEAK]
|
||||||
|
EXPORT TAMPER_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_IRQHandler [WEAK]
|
||||||
|
EXPORT FLASH_IRQHandler [WEAK]
|
||||||
|
EXPORT RCC_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI0_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI1_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI2_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI3_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||||
|
EXPORT ADC1_2_IRQHandler [WEAK]
|
||||||
|
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
|
||||||
|
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN1_RX1_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN1_SCE_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_BRK_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_UP_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM2_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM3_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI1_IRQHandler [WEAK]
|
||||||
|
EXPORT USART1_IRQHandler [WEAK]
|
||||||
|
EXPORT USART2_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||||
|
EXPORT USBWakeUp_IRQHandler [WEAK]
|
||||||
|
|
||||||
|
WWDG_IRQHandler
|
||||||
|
PVD_IRQHandler
|
||||||
|
TAMPER_IRQHandler
|
||||||
|
RTC_IRQHandler
|
||||||
|
FLASH_IRQHandler
|
||||||
|
RCC_IRQHandler
|
||||||
|
EXTI0_IRQHandler
|
||||||
|
EXTI1_IRQHandler
|
||||||
|
EXTI2_IRQHandler
|
||||||
|
EXTI3_IRQHandler
|
||||||
|
EXTI4_IRQHandler
|
||||||
|
DMA1_Channel1_IRQHandler
|
||||||
|
DMA1_Channel2_IRQHandler
|
||||||
|
DMA1_Channel3_IRQHandler
|
||||||
|
DMA1_Channel4_IRQHandler
|
||||||
|
DMA1_Channel5_IRQHandler
|
||||||
|
DMA1_Channel6_IRQHandler
|
||||||
|
DMA1_Channel7_IRQHandler
|
||||||
|
ADC1_2_IRQHandler
|
||||||
|
USB_HP_CAN1_TX_IRQHandler
|
||||||
|
USB_LP_CAN1_RX0_IRQHandler
|
||||||
|
CAN1_RX1_IRQHandler
|
||||||
|
CAN1_SCE_IRQHandler
|
||||||
|
EXTI9_5_IRQHandler
|
||||||
|
TIM1_BRK_IRQHandler
|
||||||
|
TIM1_UP_IRQHandler
|
||||||
|
TIM1_TRG_COM_IRQHandler
|
||||||
|
TIM1_CC_IRQHandler
|
||||||
|
TIM2_IRQHandler
|
||||||
|
TIM3_IRQHandler
|
||||||
|
I2C1_EV_IRQHandler
|
||||||
|
I2C1_ER_IRQHandler
|
||||||
|
SPI1_IRQHandler
|
||||||
|
USART1_IRQHandler
|
||||||
|
USART2_IRQHandler
|
||||||
|
EXTI15_10_IRQHandler
|
||||||
|
RTC_Alarm_IRQHandler
|
||||||
|
USBWakeUp_IRQHandler
|
||||||
|
|
||||||
|
B .
|
||||||
|
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
;*******************************************************************************
|
||||||
|
; User Stack and Heap initialization
|
||||||
|
;*******************************************************************************
|
||||||
|
IF :DEF:__MICROLIB
|
||||||
|
|
||||||
|
EXPORT __initial_sp
|
||||||
|
EXPORT __heap_base
|
||||||
|
EXPORT __heap_limit
|
||||||
|
|
||||||
|
ELSE
|
||||||
|
|
||||||
|
IMPORT __use_two_region_memory
|
||||||
|
EXPORT __user_initial_stackheap
|
||||||
|
|
||||||
|
__user_initial_stackheap
|
||||||
|
|
||||||
|
LDR R0, = Heap_Mem
|
||||||
|
LDR R1, =(Stack_Mem + Stack_Size)
|
||||||
|
LDR R2, = (Heap_Mem + Heap_Size)
|
||||||
|
LDR R3, = Stack_Mem
|
||||||
|
BX LR
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
ENDIF
|
||||||
|
|
||||||
|
END
|
||||||
|
|
||||||
|
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||||
|
|
@ -0,0 +1,324 @@
|
||||||
|
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
|
||||||
|
;* File Name : startup_stm32f103xb.s
|
||||||
|
;* Author : MCD Application Team
|
||||||
|
;* Version : V4.2.0
|
||||||
|
;* Date : 31-March-2017
|
||||||
|
;* Description : STM32F103xB Devices vector table for MDK-ARM toolchain.
|
||||||
|
;* This module performs:
|
||||||
|
;* - Set the initial SP
|
||||||
|
;* - Set the initial PC == Reset_Handler
|
||||||
|
;* - Set the vector table entries with the exceptions ISR address
|
||||||
|
;* - Configure the clock system
|
||||||
|
;* - Branches to __main in the C library (which eventually
|
||||||
|
;* calls main()).
|
||||||
|
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||||
|
;* priority is Privileged, and the Stack is set to Main.
|
||||||
|
;********************************************************************************
|
||||||
|
;*
|
||||||
|
;* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||||
|
;*
|
||||||
|
;* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
;* are permitted provided that the following conditions are met:
|
||||||
|
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
;* this list of conditions and the following disclaimer.
|
||||||
|
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
;* this list of conditions and the following disclaimer in the documentation
|
||||||
|
;* and/or other materials provided with the distribution.
|
||||||
|
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
;* may be used to endorse or promote products derived from this software
|
||||||
|
;* without specific prior written permission.
|
||||||
|
;*
|
||||||
|
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
;
|
||||||
|
;*******************************************************************************
|
||||||
|
|
||||||
|
; Amount of memory (in bytes) allocated for Stack
|
||||||
|
; Tailor this value to your application needs
|
||||||
|
; <h> Stack Configuration
|
||||||
|
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Stack_Size EQU 0x00000400
|
||||||
|
|
||||||
|
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||||
|
Stack_Mem SPACE Stack_Size
|
||||||
|
__initial_sp
|
||||||
|
|
||||||
|
|
||||||
|
; <h> Heap Configuration
|
||||||
|
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Heap_Size EQU 0x00000200
|
||||||
|
|
||||||
|
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||||
|
__heap_base
|
||||||
|
Heap_Mem SPACE Heap_Size
|
||||||
|
__heap_limit
|
||||||
|
|
||||||
|
PRESERVE8
|
||||||
|
THUMB
|
||||||
|
|
||||||
|
|
||||||
|
; Vector Table Mapped to Address 0 at Reset
|
||||||
|
AREA RESET, DATA, READONLY
|
||||||
|
EXPORT __Vectors
|
||||||
|
EXPORT __Vectors_End
|
||||||
|
EXPORT __Vectors_Size
|
||||||
|
|
||||||
|
__Vectors DCD __initial_sp ; Top of Stack
|
||||||
|
DCD Reset_Handler ; Reset Handler
|
||||||
|
DCD NMI_Handler ; NMI Handler
|
||||||
|
DCD HardFault_Handler ; Hard Fault Handler
|
||||||
|
DCD MemManage_Handler ; MPU Fault Handler
|
||||||
|
DCD BusFault_Handler ; Bus Fault Handler
|
||||||
|
DCD UsageFault_Handler ; Usage Fault Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; SVCall Handler
|
||||||
|
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD PendSV_Handler ; PendSV Handler
|
||||||
|
DCD SysTick_Handler ; SysTick Handler
|
||||||
|
|
||||||
|
; External Interrupts
|
||||||
|
DCD WWDG_IRQHandler ; Window Watchdog
|
||||||
|
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||||
|
DCD TAMPER_IRQHandler ; Tamper
|
||||||
|
DCD RTC_IRQHandler ; RTC
|
||||||
|
DCD FLASH_IRQHandler ; Flash
|
||||||
|
DCD RCC_IRQHandler ; RCC
|
||||||
|
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||||
|
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||||
|
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||||
|
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||||
|
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||||
|
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||||
|
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||||
|
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||||
|
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||||
|
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||||
|
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||||
|
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||||
|
DCD ADC1_2_IRQHandler ; ADC1_2
|
||||||
|
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
|
||||||
|
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
|
||||||
|
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
|
||||||
|
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
|
||||||
|
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||||
|
DCD TIM1_BRK_IRQHandler ; TIM1 Break
|
||||||
|
DCD TIM1_UP_IRQHandler ; TIM1 Update
|
||||||
|
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
|
||||||
|
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||||
|
DCD TIM2_IRQHandler ; TIM2
|
||||||
|
DCD TIM3_IRQHandler ; TIM3
|
||||||
|
DCD TIM4_IRQHandler ; TIM4
|
||||||
|
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||||
|
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||||
|
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||||
|
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||||
|
DCD SPI1_IRQHandler ; SPI1
|
||||||
|
DCD SPI2_IRQHandler ; SPI2
|
||||||
|
DCD USART1_IRQHandler ; USART1
|
||||||
|
DCD USART2_IRQHandler ; USART2
|
||||||
|
DCD USART3_IRQHandler ; USART3
|
||||||
|
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||||
|
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
|
||||||
|
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
|
||||||
|
__Vectors_End
|
||||||
|
|
||||||
|
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||||
|
|
||||||
|
AREA |.text|, CODE, READONLY
|
||||||
|
|
||||||
|
; Reset handler
|
||||||
|
Reset_Handler PROC
|
||||||
|
EXPORT Reset_Handler [WEAK]
|
||||||
|
IMPORT __main
|
||||||
|
IMPORT SystemInit
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__main
|
||||||
|
BX R0
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||||
|
|
||||||
|
NMI_Handler PROC
|
||||||
|
EXPORT NMI_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
HardFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT HardFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
MemManage_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT MemManage_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
BusFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT BusFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
UsageFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT UsageFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SVC_Handler PROC
|
||||||
|
EXPORT SVC_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
DebugMon_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT DebugMon_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
PendSV_Handler PROC
|
||||||
|
EXPORT PendSV_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SysTick_Handler PROC
|
||||||
|
EXPORT SysTick_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
Default_Handler PROC
|
||||||
|
|
||||||
|
EXPORT WWDG_IRQHandler [WEAK]
|
||||||
|
EXPORT PVD_IRQHandler [WEAK]
|
||||||
|
EXPORT TAMPER_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_IRQHandler [WEAK]
|
||||||
|
EXPORT FLASH_IRQHandler [WEAK]
|
||||||
|
EXPORT RCC_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI0_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI1_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI2_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI3_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||||
|
EXPORT ADC1_2_IRQHandler [WEAK]
|
||||||
|
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
|
||||||
|
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN1_RX1_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN1_SCE_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_BRK_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_UP_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM2_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM3_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM4_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI1_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI2_IRQHandler [WEAK]
|
||||||
|
EXPORT USART1_IRQHandler [WEAK]
|
||||||
|
EXPORT USART2_IRQHandler [WEAK]
|
||||||
|
EXPORT USART3_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||||
|
EXPORT USBWakeUp_IRQHandler [WEAK]
|
||||||
|
|
||||||
|
WWDG_IRQHandler
|
||||||
|
PVD_IRQHandler
|
||||||
|
TAMPER_IRQHandler
|
||||||
|
RTC_IRQHandler
|
||||||
|
FLASH_IRQHandler
|
||||||
|
RCC_IRQHandler
|
||||||
|
EXTI0_IRQHandler
|
||||||
|
EXTI1_IRQHandler
|
||||||
|
EXTI2_IRQHandler
|
||||||
|
EXTI3_IRQHandler
|
||||||
|
EXTI4_IRQHandler
|
||||||
|
DMA1_Channel1_IRQHandler
|
||||||
|
DMA1_Channel2_IRQHandler
|
||||||
|
DMA1_Channel3_IRQHandler
|
||||||
|
DMA1_Channel4_IRQHandler
|
||||||
|
DMA1_Channel5_IRQHandler
|
||||||
|
DMA1_Channel6_IRQHandler
|
||||||
|
DMA1_Channel7_IRQHandler
|
||||||
|
ADC1_2_IRQHandler
|
||||||
|
USB_HP_CAN1_TX_IRQHandler
|
||||||
|
USB_LP_CAN1_RX0_IRQHandler
|
||||||
|
CAN1_RX1_IRQHandler
|
||||||
|
CAN1_SCE_IRQHandler
|
||||||
|
EXTI9_5_IRQHandler
|
||||||
|
TIM1_BRK_IRQHandler
|
||||||
|
TIM1_UP_IRQHandler
|
||||||
|
TIM1_TRG_COM_IRQHandler
|
||||||
|
TIM1_CC_IRQHandler
|
||||||
|
TIM2_IRQHandler
|
||||||
|
TIM3_IRQHandler
|
||||||
|
TIM4_IRQHandler
|
||||||
|
I2C1_EV_IRQHandler
|
||||||
|
I2C1_ER_IRQHandler
|
||||||
|
I2C2_EV_IRQHandler
|
||||||
|
I2C2_ER_IRQHandler
|
||||||
|
SPI1_IRQHandler
|
||||||
|
SPI2_IRQHandler
|
||||||
|
USART1_IRQHandler
|
||||||
|
USART2_IRQHandler
|
||||||
|
USART3_IRQHandler
|
||||||
|
EXTI15_10_IRQHandler
|
||||||
|
RTC_Alarm_IRQHandler
|
||||||
|
USBWakeUp_IRQHandler
|
||||||
|
|
||||||
|
B .
|
||||||
|
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
;*******************************************************************************
|
||||||
|
; User Stack and Heap initialization
|
||||||
|
;*******************************************************************************
|
||||||
|
IF :DEF:__MICROLIB
|
||||||
|
|
||||||
|
EXPORT __initial_sp
|
||||||
|
EXPORT __heap_base
|
||||||
|
EXPORT __heap_limit
|
||||||
|
|
||||||
|
ELSE
|
||||||
|
|
||||||
|
IMPORT __use_two_region_memory
|
||||||
|
EXPORT __user_initial_stackheap
|
||||||
|
|
||||||
|
__user_initial_stackheap
|
||||||
|
|
||||||
|
LDR R0, = Heap_Mem
|
||||||
|
LDR R1, =(Stack_Mem + Stack_Size)
|
||||||
|
LDR R2, = (Heap_Mem + Heap_Size)
|
||||||
|
LDR R3, = Stack_Mem
|
||||||
|
BX LR
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
ENDIF
|
||||||
|
|
||||||
|
END
|
||||||
|
|
||||||
|
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||||
|
|
@ -0,0 +1,373 @@
|
||||||
|
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
|
||||||
|
;* File Name : startup_stm32f103xe.s
|
||||||
|
;* Author : MCD Application Team
|
||||||
|
;* Version : V4.2.0
|
||||||
|
;* Date : 31-March-2017
|
||||||
|
;* Description : STM32F103xE Devices vector table for MDK-ARM toolchain.
|
||||||
|
;* This module performs:
|
||||||
|
;* - Set the initial SP
|
||||||
|
;* - Set the initial PC == Reset_Handler
|
||||||
|
;* - Set the vector table entries with the exceptions ISR address
|
||||||
|
;* - Configure the clock system
|
||||||
|
;* - Branches to __main in the C library (which eventually
|
||||||
|
;* calls main()).
|
||||||
|
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||||
|
;* priority is Privileged, and the Stack is set to Main.
|
||||||
|
;********************************************************************************
|
||||||
|
;*
|
||||||
|
;* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||||
|
;*
|
||||||
|
;* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
;* are permitted provided that the following conditions are met:
|
||||||
|
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
;* this list of conditions and the following disclaimer.
|
||||||
|
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
;* this list of conditions and the following disclaimer in the documentation
|
||||||
|
;* and/or other materials provided with the distribution.
|
||||||
|
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
;* may be used to endorse or promote products derived from this software
|
||||||
|
;* without specific prior written permission.
|
||||||
|
;*
|
||||||
|
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
;
|
||||||
|
;*******************************************************************************
|
||||||
|
|
||||||
|
; Amount of memory (in bytes) allocated for Stack
|
||||||
|
; Tailor this value to your application needs
|
||||||
|
; <h> Stack Configuration
|
||||||
|
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Stack_Size EQU 0x00000400
|
||||||
|
|
||||||
|
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||||
|
Stack_Mem SPACE Stack_Size
|
||||||
|
__initial_sp
|
||||||
|
|
||||||
|
; <h> Heap Configuration
|
||||||
|
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Heap_Size EQU 0x00000200
|
||||||
|
|
||||||
|
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||||
|
__heap_base
|
||||||
|
Heap_Mem SPACE Heap_Size
|
||||||
|
__heap_limit
|
||||||
|
|
||||||
|
PRESERVE8
|
||||||
|
THUMB
|
||||||
|
|
||||||
|
|
||||||
|
; Vector Table Mapped to Address 0 at Reset
|
||||||
|
AREA RESET, DATA, READONLY
|
||||||
|
EXPORT __Vectors
|
||||||
|
EXPORT __Vectors_End
|
||||||
|
EXPORT __Vectors_Size
|
||||||
|
|
||||||
|
__Vectors DCD __initial_sp ; Top of Stack
|
||||||
|
DCD Reset_Handler ; Reset Handler
|
||||||
|
DCD NMI_Handler ; NMI Handler
|
||||||
|
DCD HardFault_Handler ; Hard Fault Handler
|
||||||
|
DCD MemManage_Handler ; MPU Fault Handler
|
||||||
|
DCD BusFault_Handler ; Bus Fault Handler
|
||||||
|
DCD UsageFault_Handler ; Usage Fault Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; SVCall Handler
|
||||||
|
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD PendSV_Handler ; PendSV Handler
|
||||||
|
DCD SysTick_Handler ; SysTick Handler
|
||||||
|
|
||||||
|
; External Interrupts
|
||||||
|
DCD WWDG_IRQHandler ; Window Watchdog
|
||||||
|
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||||
|
DCD TAMPER_IRQHandler ; Tamper
|
||||||
|
DCD RTC_IRQHandler ; RTC
|
||||||
|
DCD FLASH_IRQHandler ; Flash
|
||||||
|
DCD RCC_IRQHandler ; RCC
|
||||||
|
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||||
|
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||||
|
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||||
|
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||||
|
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||||
|
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||||
|
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||||
|
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||||
|
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||||
|
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||||
|
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||||
|
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||||
|
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
|
||||||
|
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
|
||||||
|
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
|
||||||
|
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
|
||||||
|
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
|
||||||
|
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||||
|
DCD TIM1_BRK_IRQHandler ; TIM1 Break
|
||||||
|
DCD TIM1_UP_IRQHandler ; TIM1 Update
|
||||||
|
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
|
||||||
|
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||||
|
DCD TIM2_IRQHandler ; TIM2
|
||||||
|
DCD TIM3_IRQHandler ; TIM3
|
||||||
|
DCD TIM4_IRQHandler ; TIM4
|
||||||
|
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||||
|
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||||
|
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||||
|
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||||
|
DCD SPI1_IRQHandler ; SPI1
|
||||||
|
DCD SPI2_IRQHandler ; SPI2
|
||||||
|
DCD USART1_IRQHandler ; USART1
|
||||||
|
DCD USART2_IRQHandler ; USART2
|
||||||
|
DCD USART3_IRQHandler ; USART3
|
||||||
|
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||||
|
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
|
||||||
|
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
|
||||||
|
DCD TIM8_BRK_IRQHandler ; TIM8 Break
|
||||||
|
DCD TIM8_UP_IRQHandler ; TIM8 Update
|
||||||
|
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
|
||||||
|
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
|
||||||
|
DCD ADC3_IRQHandler ; ADC3
|
||||||
|
DCD FSMC_IRQHandler ; FSMC
|
||||||
|
DCD SDIO_IRQHandler ; SDIO
|
||||||
|
DCD TIM5_IRQHandler ; TIM5
|
||||||
|
DCD SPI3_IRQHandler ; SPI3
|
||||||
|
DCD UART4_IRQHandler ; UART4
|
||||||
|
DCD UART5_IRQHandler ; UART5
|
||||||
|
DCD TIM6_IRQHandler ; TIM6
|
||||||
|
DCD TIM7_IRQHandler ; TIM7
|
||||||
|
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
|
||||||
|
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
|
||||||
|
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
|
||||||
|
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
|
||||||
|
__Vectors_End
|
||||||
|
|
||||||
|
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||||
|
|
||||||
|
AREA |.text|, CODE, READONLY
|
||||||
|
|
||||||
|
; Reset handler
|
||||||
|
Reset_Handler PROC
|
||||||
|
EXPORT Reset_Handler [WEAK]
|
||||||
|
IMPORT __main
|
||||||
|
IMPORT SystemInit
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__main
|
||||||
|
BX R0
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||||
|
|
||||||
|
NMI_Handler PROC
|
||||||
|
EXPORT NMI_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
HardFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT HardFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
MemManage_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT MemManage_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
BusFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT BusFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
UsageFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT UsageFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SVC_Handler PROC
|
||||||
|
EXPORT SVC_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
DebugMon_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT DebugMon_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
PendSV_Handler PROC
|
||||||
|
EXPORT PendSV_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SysTick_Handler PROC
|
||||||
|
EXPORT SysTick_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
Default_Handler PROC
|
||||||
|
|
||||||
|
EXPORT WWDG_IRQHandler [WEAK]
|
||||||
|
EXPORT PVD_IRQHandler [WEAK]
|
||||||
|
EXPORT TAMPER_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_IRQHandler [WEAK]
|
||||||
|
EXPORT FLASH_IRQHandler [WEAK]
|
||||||
|
EXPORT RCC_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI0_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI1_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI2_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI3_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||||
|
EXPORT ADC1_2_IRQHandler [WEAK]
|
||||||
|
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
|
||||||
|
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN1_RX1_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN1_SCE_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_BRK_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_UP_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM2_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM3_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM4_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI1_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI2_IRQHandler [WEAK]
|
||||||
|
EXPORT USART1_IRQHandler [WEAK]
|
||||||
|
EXPORT USART2_IRQHandler [WEAK]
|
||||||
|
EXPORT USART3_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||||
|
EXPORT USBWakeUp_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM8_BRK_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM8_UP_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM8_CC_IRQHandler [WEAK]
|
||||||
|
EXPORT ADC3_IRQHandler [WEAK]
|
||||||
|
EXPORT FSMC_IRQHandler [WEAK]
|
||||||
|
EXPORT SDIO_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM5_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI3_IRQHandler [WEAK]
|
||||||
|
EXPORT UART4_IRQHandler [WEAK]
|
||||||
|
EXPORT UART5_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM6_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM7_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Channel1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Channel2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Channel3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
|
||||||
|
|
||||||
|
WWDG_IRQHandler
|
||||||
|
PVD_IRQHandler
|
||||||
|
TAMPER_IRQHandler
|
||||||
|
RTC_IRQHandler
|
||||||
|
FLASH_IRQHandler
|
||||||
|
RCC_IRQHandler
|
||||||
|
EXTI0_IRQHandler
|
||||||
|
EXTI1_IRQHandler
|
||||||
|
EXTI2_IRQHandler
|
||||||
|
EXTI3_IRQHandler
|
||||||
|
EXTI4_IRQHandler
|
||||||
|
DMA1_Channel1_IRQHandler
|
||||||
|
DMA1_Channel2_IRQHandler
|
||||||
|
DMA1_Channel3_IRQHandler
|
||||||
|
DMA1_Channel4_IRQHandler
|
||||||
|
DMA1_Channel5_IRQHandler
|
||||||
|
DMA1_Channel6_IRQHandler
|
||||||
|
DMA1_Channel7_IRQHandler
|
||||||
|
ADC1_2_IRQHandler
|
||||||
|
USB_HP_CAN1_TX_IRQHandler
|
||||||
|
USB_LP_CAN1_RX0_IRQHandler
|
||||||
|
CAN1_RX1_IRQHandler
|
||||||
|
CAN1_SCE_IRQHandler
|
||||||
|
EXTI9_5_IRQHandler
|
||||||
|
TIM1_BRK_IRQHandler
|
||||||
|
TIM1_UP_IRQHandler
|
||||||
|
TIM1_TRG_COM_IRQHandler
|
||||||
|
TIM1_CC_IRQHandler
|
||||||
|
TIM2_IRQHandler
|
||||||
|
TIM3_IRQHandler
|
||||||
|
TIM4_IRQHandler
|
||||||
|
I2C1_EV_IRQHandler
|
||||||
|
I2C1_ER_IRQHandler
|
||||||
|
I2C2_EV_IRQHandler
|
||||||
|
I2C2_ER_IRQHandler
|
||||||
|
SPI1_IRQHandler
|
||||||
|
SPI2_IRQHandler
|
||||||
|
USART1_IRQHandler
|
||||||
|
USART2_IRQHandler
|
||||||
|
USART3_IRQHandler
|
||||||
|
EXTI15_10_IRQHandler
|
||||||
|
RTC_Alarm_IRQHandler
|
||||||
|
USBWakeUp_IRQHandler
|
||||||
|
TIM8_BRK_IRQHandler
|
||||||
|
TIM8_UP_IRQHandler
|
||||||
|
TIM8_TRG_COM_IRQHandler
|
||||||
|
TIM8_CC_IRQHandler
|
||||||
|
ADC3_IRQHandler
|
||||||
|
FSMC_IRQHandler
|
||||||
|
SDIO_IRQHandler
|
||||||
|
TIM5_IRQHandler
|
||||||
|
SPI3_IRQHandler
|
||||||
|
UART4_IRQHandler
|
||||||
|
UART5_IRQHandler
|
||||||
|
TIM6_IRQHandler
|
||||||
|
TIM7_IRQHandler
|
||||||
|
DMA2_Channel1_IRQHandler
|
||||||
|
DMA2_Channel2_IRQHandler
|
||||||
|
DMA2_Channel3_IRQHandler
|
||||||
|
DMA2_Channel4_5_IRQHandler
|
||||||
|
B .
|
||||||
|
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
;*******************************************************************************
|
||||||
|
; User Stack and Heap initialization
|
||||||
|
;*******************************************************************************
|
||||||
|
IF :DEF:__MICROLIB
|
||||||
|
|
||||||
|
EXPORT __initial_sp
|
||||||
|
EXPORT __heap_base
|
||||||
|
EXPORT __heap_limit
|
||||||
|
|
||||||
|
ELSE
|
||||||
|
|
||||||
|
IMPORT __use_two_region_memory
|
||||||
|
EXPORT __user_initial_stackheap
|
||||||
|
|
||||||
|
__user_initial_stackheap
|
||||||
|
|
||||||
|
LDR R0, = Heap_Mem
|
||||||
|
LDR R1, =(Stack_Mem + Stack_Size)
|
||||||
|
LDR R2, = (Heap_Mem + Heap_Size)
|
||||||
|
LDR R3, = Stack_Mem
|
||||||
|
BX LR
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
ENDIF
|
||||||
|
|
||||||
|
END
|
||||||
|
|
||||||
|
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||||
|
|
@ -0,0 +1,373 @@
|
||||||
|
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
|
||||||
|
;* File Name : startup_stm32f103xg.s
|
||||||
|
;* Author : MCD Application Team
|
||||||
|
;* Version : V4.2.0
|
||||||
|
;* Date : 31-March-2017
|
||||||
|
;* Description : STM32F103xG Devices vector table for MDK-ARM toolchain.
|
||||||
|
;* This module performs:
|
||||||
|
;* - Set the initial SP
|
||||||
|
;* - Set the initial PC == Reset_Handler
|
||||||
|
;* - Set the vector table entries with the exceptions ISR address
|
||||||
|
;* - Configure the clock system
|
||||||
|
;* - Branches to __main in the C library (which eventually
|
||||||
|
;* calls main()).
|
||||||
|
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||||
|
;* priority is Privileged, and the Stack is set to Main.
|
||||||
|
;********************************************************************************
|
||||||
|
;*
|
||||||
|
;* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||||
|
;*
|
||||||
|
;* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
;* are permitted provided that the following conditions are met:
|
||||||
|
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
;* this list of conditions and the following disclaimer.
|
||||||
|
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
;* this list of conditions and the following disclaimer in the documentation
|
||||||
|
;* and/or other materials provided with the distribution.
|
||||||
|
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
;* may be used to endorse or promote products derived from this software
|
||||||
|
;* without specific prior written permission.
|
||||||
|
;*
|
||||||
|
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
;
|
||||||
|
;*******************************************************************************
|
||||||
|
|
||||||
|
; Amount of memory (in bytes) allocated for Stack
|
||||||
|
; Tailor this value to your application needs
|
||||||
|
; <h> Stack Configuration
|
||||||
|
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Stack_Size EQU 0x00000400
|
||||||
|
|
||||||
|
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||||
|
Stack_Mem SPACE Stack_Size
|
||||||
|
__initial_sp
|
||||||
|
|
||||||
|
; <h> Heap Configuration
|
||||||
|
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Heap_Size EQU 0x00000200
|
||||||
|
|
||||||
|
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||||
|
__heap_base
|
||||||
|
Heap_Mem SPACE Heap_Size
|
||||||
|
__heap_limit
|
||||||
|
|
||||||
|
PRESERVE8
|
||||||
|
THUMB
|
||||||
|
|
||||||
|
|
||||||
|
; Vector Table Mapped to Address 0 at Reset
|
||||||
|
AREA RESET, DATA, READONLY
|
||||||
|
EXPORT __Vectors
|
||||||
|
EXPORT __Vectors_End
|
||||||
|
EXPORT __Vectors_Size
|
||||||
|
|
||||||
|
__Vectors DCD __initial_sp ; Top of Stack
|
||||||
|
DCD Reset_Handler ; Reset Handler
|
||||||
|
DCD NMI_Handler ; NMI Handler
|
||||||
|
DCD HardFault_Handler ; Hard Fault Handler
|
||||||
|
DCD MemManage_Handler ; MPU Fault Handler
|
||||||
|
DCD BusFault_Handler ; Bus Fault Handler
|
||||||
|
DCD UsageFault_Handler ; Usage Fault Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; SVCall Handler
|
||||||
|
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD PendSV_Handler ; PendSV Handler
|
||||||
|
DCD SysTick_Handler ; SysTick Handler
|
||||||
|
|
||||||
|
; External Interrupts
|
||||||
|
DCD WWDG_IRQHandler ; Window Watchdog
|
||||||
|
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||||
|
DCD TAMPER_IRQHandler ; Tamper
|
||||||
|
DCD RTC_IRQHandler ; RTC
|
||||||
|
DCD FLASH_IRQHandler ; Flash
|
||||||
|
DCD RCC_IRQHandler ; RCC
|
||||||
|
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||||
|
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||||
|
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||||
|
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||||
|
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||||
|
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||||
|
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||||
|
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||||
|
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||||
|
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||||
|
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||||
|
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||||
|
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
|
||||||
|
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
|
||||||
|
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
|
||||||
|
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
|
||||||
|
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
|
||||||
|
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||||
|
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
|
||||||
|
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
|
||||||
|
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
|
||||||
|
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||||
|
DCD TIM2_IRQHandler ; TIM2
|
||||||
|
DCD TIM3_IRQHandler ; TIM3
|
||||||
|
DCD TIM4_IRQHandler ; TIM4
|
||||||
|
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||||
|
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||||
|
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||||
|
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||||
|
DCD SPI1_IRQHandler ; SPI1
|
||||||
|
DCD SPI2_IRQHandler ; SPI2
|
||||||
|
DCD USART1_IRQHandler ; USART1
|
||||||
|
DCD USART2_IRQHandler ; USART2
|
||||||
|
DCD USART3_IRQHandler ; USART3
|
||||||
|
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||||
|
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
|
||||||
|
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
|
||||||
|
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
|
||||||
|
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
|
||||||
|
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
|
||||||
|
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
|
||||||
|
DCD ADC3_IRQHandler ; ADC3
|
||||||
|
DCD FSMC_IRQHandler ; FSMC
|
||||||
|
DCD SDIO_IRQHandler ; SDIO
|
||||||
|
DCD TIM5_IRQHandler ; TIM5
|
||||||
|
DCD SPI3_IRQHandler ; SPI3
|
||||||
|
DCD UART4_IRQHandler ; UART4
|
||||||
|
DCD UART5_IRQHandler ; UART5
|
||||||
|
DCD TIM6_IRQHandler ; TIM6
|
||||||
|
DCD TIM7_IRQHandler ; TIM7
|
||||||
|
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
|
||||||
|
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
|
||||||
|
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
|
||||||
|
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
|
||||||
|
__Vectors_End
|
||||||
|
|
||||||
|
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||||
|
|
||||||
|
AREA |.text|, CODE, READONLY
|
||||||
|
|
||||||
|
; Reset handler
|
||||||
|
Reset_Handler PROC
|
||||||
|
EXPORT Reset_Handler [WEAK]
|
||||||
|
IMPORT __main
|
||||||
|
IMPORT SystemInit
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__main
|
||||||
|
BX R0
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||||
|
|
||||||
|
NMI_Handler PROC
|
||||||
|
EXPORT NMI_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
HardFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT HardFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
MemManage_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT MemManage_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
BusFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT BusFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
UsageFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT UsageFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SVC_Handler PROC
|
||||||
|
EXPORT SVC_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
DebugMon_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT DebugMon_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
PendSV_Handler PROC
|
||||||
|
EXPORT PendSV_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SysTick_Handler PROC
|
||||||
|
EXPORT SysTick_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
Default_Handler PROC
|
||||||
|
|
||||||
|
EXPORT WWDG_IRQHandler [WEAK]
|
||||||
|
EXPORT PVD_IRQHandler [WEAK]
|
||||||
|
EXPORT TAMPER_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_IRQHandler [WEAK]
|
||||||
|
EXPORT FLASH_IRQHandler [WEAK]
|
||||||
|
EXPORT RCC_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI0_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI1_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI2_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI3_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||||
|
EXPORT ADC1_2_IRQHandler [WEAK]
|
||||||
|
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
|
||||||
|
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN1_RX1_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN1_SCE_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM2_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM3_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM4_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI1_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI2_IRQHandler [WEAK]
|
||||||
|
EXPORT USART1_IRQHandler [WEAK]
|
||||||
|
EXPORT USART2_IRQHandler [WEAK]
|
||||||
|
EXPORT USART3_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||||
|
EXPORT USBWakeUp_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM8_CC_IRQHandler [WEAK]
|
||||||
|
EXPORT ADC3_IRQHandler [WEAK]
|
||||||
|
EXPORT FSMC_IRQHandler [WEAK]
|
||||||
|
EXPORT SDIO_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM5_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI3_IRQHandler [WEAK]
|
||||||
|
EXPORT UART4_IRQHandler [WEAK]
|
||||||
|
EXPORT UART5_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM6_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM7_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Channel1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Channel2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Channel3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
|
||||||
|
|
||||||
|
WWDG_IRQHandler
|
||||||
|
PVD_IRQHandler
|
||||||
|
TAMPER_IRQHandler
|
||||||
|
RTC_IRQHandler
|
||||||
|
FLASH_IRQHandler
|
||||||
|
RCC_IRQHandler
|
||||||
|
EXTI0_IRQHandler
|
||||||
|
EXTI1_IRQHandler
|
||||||
|
EXTI2_IRQHandler
|
||||||
|
EXTI3_IRQHandler
|
||||||
|
EXTI4_IRQHandler
|
||||||
|
DMA1_Channel1_IRQHandler
|
||||||
|
DMA1_Channel2_IRQHandler
|
||||||
|
DMA1_Channel3_IRQHandler
|
||||||
|
DMA1_Channel4_IRQHandler
|
||||||
|
DMA1_Channel5_IRQHandler
|
||||||
|
DMA1_Channel6_IRQHandler
|
||||||
|
DMA1_Channel7_IRQHandler
|
||||||
|
ADC1_2_IRQHandler
|
||||||
|
USB_HP_CAN1_TX_IRQHandler
|
||||||
|
USB_LP_CAN1_RX0_IRQHandler
|
||||||
|
CAN1_RX1_IRQHandler
|
||||||
|
CAN1_SCE_IRQHandler
|
||||||
|
EXTI9_5_IRQHandler
|
||||||
|
TIM1_BRK_TIM9_IRQHandler
|
||||||
|
TIM1_UP_TIM10_IRQHandler
|
||||||
|
TIM1_TRG_COM_TIM11_IRQHandler
|
||||||
|
TIM1_CC_IRQHandler
|
||||||
|
TIM2_IRQHandler
|
||||||
|
TIM3_IRQHandler
|
||||||
|
TIM4_IRQHandler
|
||||||
|
I2C1_EV_IRQHandler
|
||||||
|
I2C1_ER_IRQHandler
|
||||||
|
I2C2_EV_IRQHandler
|
||||||
|
I2C2_ER_IRQHandler
|
||||||
|
SPI1_IRQHandler
|
||||||
|
SPI2_IRQHandler
|
||||||
|
USART1_IRQHandler
|
||||||
|
USART2_IRQHandler
|
||||||
|
USART3_IRQHandler
|
||||||
|
EXTI15_10_IRQHandler
|
||||||
|
RTC_Alarm_IRQHandler
|
||||||
|
USBWakeUp_IRQHandler
|
||||||
|
TIM8_BRK_TIM12_IRQHandler
|
||||||
|
TIM8_UP_TIM13_IRQHandler
|
||||||
|
TIM8_TRG_COM_TIM14_IRQHandler
|
||||||
|
TIM8_CC_IRQHandler
|
||||||
|
ADC3_IRQHandler
|
||||||
|
FSMC_IRQHandler
|
||||||
|
SDIO_IRQHandler
|
||||||
|
TIM5_IRQHandler
|
||||||
|
SPI3_IRQHandler
|
||||||
|
UART4_IRQHandler
|
||||||
|
UART5_IRQHandler
|
||||||
|
TIM6_IRQHandler
|
||||||
|
TIM7_IRQHandler
|
||||||
|
DMA2_Channel1_IRQHandler
|
||||||
|
DMA2_Channel2_IRQHandler
|
||||||
|
DMA2_Channel3_IRQHandler
|
||||||
|
DMA2_Channel4_5_IRQHandler
|
||||||
|
B .
|
||||||
|
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
;*******************************************************************************
|
||||||
|
; User Stack and Heap initialization
|
||||||
|
;*******************************************************************************
|
||||||
|
IF :DEF:__MICROLIB
|
||||||
|
|
||||||
|
EXPORT __initial_sp
|
||||||
|
EXPORT __heap_base
|
||||||
|
EXPORT __heap_limit
|
||||||
|
|
||||||
|
ELSE
|
||||||
|
|
||||||
|
IMPORT __use_two_region_memory
|
||||||
|
EXPORT __user_initial_stackheap
|
||||||
|
|
||||||
|
__user_initial_stackheap
|
||||||
|
|
||||||
|
LDR R0, = Heap_Mem
|
||||||
|
LDR R1, =(Stack_Mem + Stack_Size)
|
||||||
|
LDR R2, = (Heap_Mem + Heap_Size)
|
||||||
|
LDR R3, = Stack_Mem
|
||||||
|
BX LR
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
ENDIF
|
||||||
|
|
||||||
|
END
|
||||||
|
|
||||||
|
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||||
|
|
@ -0,0 +1,381 @@
|
||||||
|
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
|
||||||
|
;* File Name : startup_stm32f105xc.s
|
||||||
|
;* Author : MCD Application Team
|
||||||
|
;* Version : V4.2.0
|
||||||
|
;* Date : 31-March-2017
|
||||||
|
;* Description : STM32F105xC Devices vector table for MDK-ARM toolchain.
|
||||||
|
;* This module performs:
|
||||||
|
;* - Set the initial SP
|
||||||
|
;* - Set the initial PC == Reset_Handler
|
||||||
|
;* - Set the vector table entries with the exceptions ISR address
|
||||||
|
;* - Configure the clock system
|
||||||
|
;* - Branches to __main in the C library (which eventually
|
||||||
|
;* calls main()).
|
||||||
|
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||||
|
;* priority is Privileged, and the Stack is set to Main.
|
||||||
|
;********************************************************************************
|
||||||
|
;*
|
||||||
|
;* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||||
|
;*
|
||||||
|
;* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
;* are permitted provided that the following conditions are met:
|
||||||
|
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
;* this list of conditions and the following disclaimer.
|
||||||
|
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
;* this list of conditions and the following disclaimer in the documentation
|
||||||
|
;* and/or other materials provided with the distribution.
|
||||||
|
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
;* may be used to endorse or promote products derived from this software
|
||||||
|
;* without specific prior written permission.
|
||||||
|
;*
|
||||||
|
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
;
|
||||||
|
;*******************************************************************************
|
||||||
|
|
||||||
|
; Amount of memory (in bytes) allocated for Stack
|
||||||
|
; Tailor this value to your application needs
|
||||||
|
; <h> Stack Configuration
|
||||||
|
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Stack_Size EQU 0x00000400
|
||||||
|
|
||||||
|
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||||
|
Stack_Mem SPACE Stack_Size
|
||||||
|
__initial_sp
|
||||||
|
|
||||||
|
|
||||||
|
; <h> Heap Configuration
|
||||||
|
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Heap_Size EQU 0x00000200
|
||||||
|
|
||||||
|
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||||
|
__heap_base
|
||||||
|
Heap_Mem SPACE Heap_Size
|
||||||
|
__heap_limit
|
||||||
|
|
||||||
|
PRESERVE8
|
||||||
|
THUMB
|
||||||
|
|
||||||
|
|
||||||
|
; Vector Table Mapped to Address 0 at Reset
|
||||||
|
AREA RESET, DATA, READONLY
|
||||||
|
EXPORT __Vectors
|
||||||
|
EXPORT __Vectors_End
|
||||||
|
EXPORT __Vectors_Size
|
||||||
|
|
||||||
|
__Vectors DCD __initial_sp ; Top of Stack
|
||||||
|
DCD Reset_Handler ; Reset Handler
|
||||||
|
DCD NMI_Handler ; NMI Handler
|
||||||
|
DCD HardFault_Handler ; Hard Fault Handler
|
||||||
|
DCD MemManage_Handler ; MPU Fault Handler
|
||||||
|
DCD BusFault_Handler ; Bus Fault Handler
|
||||||
|
DCD UsageFault_Handler ; Usage Fault Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; SVCall Handler
|
||||||
|
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD PendSV_Handler ; PendSV Handler
|
||||||
|
DCD SysTick_Handler ; SysTick Handler
|
||||||
|
|
||||||
|
; External Interrupts
|
||||||
|
DCD WWDG_IRQHandler ; Window Watchdog
|
||||||
|
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||||
|
DCD TAMPER_IRQHandler ; Tamper
|
||||||
|
DCD RTC_IRQHandler ; RTC
|
||||||
|
DCD FLASH_IRQHandler ; Flash
|
||||||
|
DCD RCC_IRQHandler ; RCC
|
||||||
|
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||||
|
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||||
|
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||||
|
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||||
|
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||||
|
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||||
|
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||||
|
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||||
|
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||||
|
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||||
|
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||||
|
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||||
|
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
|
||||||
|
DCD CAN1_TX_IRQHandler ; CAN1 TX
|
||||||
|
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
|
||||||
|
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
|
||||||
|
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
|
||||||
|
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||||
|
DCD TIM1_BRK_IRQHandler ; TIM1 Break
|
||||||
|
DCD TIM1_UP_IRQHandler ; TIM1 Update
|
||||||
|
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
|
||||||
|
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||||
|
DCD TIM2_IRQHandler ; TIM2
|
||||||
|
DCD TIM3_IRQHandler ; TIM3
|
||||||
|
DCD TIM4_IRQHandler ; TIM4
|
||||||
|
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||||
|
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||||
|
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||||
|
DCD I2C2_ER_IRQHandler ; I2C1 Error
|
||||||
|
DCD SPI1_IRQHandler ; SPI1
|
||||||
|
DCD SPI2_IRQHandler ; SPI2
|
||||||
|
DCD USART1_IRQHandler ; USART1
|
||||||
|
DCD USART2_IRQHandler ; USART2
|
||||||
|
DCD USART3_IRQHandler ; USART3
|
||||||
|
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||||
|
DCD RTC_Alarm_IRQHandler ; RTC alarm through EXTI line
|
||||||
|
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD TIM5_IRQHandler ; TIM5
|
||||||
|
DCD SPI3_IRQHandler ; SPI3
|
||||||
|
DCD UART4_IRQHandler ; UART4
|
||||||
|
DCD UART5_IRQHandler ; UART5
|
||||||
|
DCD TIM6_IRQHandler ; TIM6
|
||||||
|
DCD TIM7_IRQHandler ; TIM7
|
||||||
|
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
|
||||||
|
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
|
||||||
|
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
|
||||||
|
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4
|
||||||
|
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD CAN2_TX_IRQHandler ; CAN2 TX
|
||||||
|
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
|
||||||
|
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
|
||||||
|
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
|
||||||
|
DCD OTG_FS_IRQHandler ; USB OTG FS
|
||||||
|
__Vectors_End
|
||||||
|
|
||||||
|
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||||
|
|
||||||
|
AREA |.text|, CODE, READONLY
|
||||||
|
|
||||||
|
; Reset handler
|
||||||
|
Reset_Handler PROC
|
||||||
|
EXPORT Reset_Handler [WEAK]
|
||||||
|
IMPORT SystemInit
|
||||||
|
IMPORT __main
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__main
|
||||||
|
BX R0
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||||
|
|
||||||
|
NMI_Handler PROC
|
||||||
|
EXPORT NMI_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
HardFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT HardFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
MemManage_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT MemManage_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
BusFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT BusFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
UsageFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT UsageFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SVC_Handler PROC
|
||||||
|
EXPORT SVC_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
DebugMon_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT DebugMon_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
PendSV_Handler PROC
|
||||||
|
EXPORT PendSV_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SysTick_Handler PROC
|
||||||
|
EXPORT SysTick_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
Default_Handler PROC
|
||||||
|
|
||||||
|
EXPORT WWDG_IRQHandler [WEAK]
|
||||||
|
EXPORT PVD_IRQHandler [WEAK]
|
||||||
|
EXPORT TAMPER_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_IRQHandler [WEAK]
|
||||||
|
EXPORT FLASH_IRQHandler [WEAK]
|
||||||
|
EXPORT RCC_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI0_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI1_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI2_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI3_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||||
|
EXPORT ADC1_2_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN1_TX_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN1_RX0_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN1_RX1_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN1_SCE_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_BRK_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_UP_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM2_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM3_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM4_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI1_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI2_IRQHandler [WEAK]
|
||||||
|
EXPORT USART1_IRQHandler [WEAK]
|
||||||
|
EXPORT USART2_IRQHandler [WEAK]
|
||||||
|
EXPORT USART3_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||||
|
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM5_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI3_IRQHandler [WEAK]
|
||||||
|
EXPORT UART4_IRQHandler [WEAK]
|
||||||
|
EXPORT UART5_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM6_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM7_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Channel1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Channel2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Channel3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Channel4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Channel5_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN2_TX_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN2_RX0_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN2_RX1_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN2_SCE_IRQHandler [WEAK]
|
||||||
|
EXPORT OTG_FS_IRQHandler [WEAK]
|
||||||
|
|
||||||
|
WWDG_IRQHandler
|
||||||
|
PVD_IRQHandler
|
||||||
|
TAMPER_IRQHandler
|
||||||
|
RTC_IRQHandler
|
||||||
|
FLASH_IRQHandler
|
||||||
|
RCC_IRQHandler
|
||||||
|
EXTI0_IRQHandler
|
||||||
|
EXTI1_IRQHandler
|
||||||
|
EXTI2_IRQHandler
|
||||||
|
EXTI3_IRQHandler
|
||||||
|
EXTI4_IRQHandler
|
||||||
|
DMA1_Channel1_IRQHandler
|
||||||
|
DMA1_Channel2_IRQHandler
|
||||||
|
DMA1_Channel3_IRQHandler
|
||||||
|
DMA1_Channel4_IRQHandler
|
||||||
|
DMA1_Channel5_IRQHandler
|
||||||
|
DMA1_Channel6_IRQHandler
|
||||||
|
DMA1_Channel7_IRQHandler
|
||||||
|
ADC1_2_IRQHandler
|
||||||
|
CAN1_TX_IRQHandler
|
||||||
|
CAN1_RX0_IRQHandler
|
||||||
|
CAN1_RX1_IRQHandler
|
||||||
|
CAN1_SCE_IRQHandler
|
||||||
|
EXTI9_5_IRQHandler
|
||||||
|
TIM1_BRK_IRQHandler
|
||||||
|
TIM1_UP_IRQHandler
|
||||||
|
TIM1_TRG_COM_IRQHandler
|
||||||
|
TIM1_CC_IRQHandler
|
||||||
|
TIM2_IRQHandler
|
||||||
|
TIM3_IRQHandler
|
||||||
|
TIM4_IRQHandler
|
||||||
|
I2C1_EV_IRQHandler
|
||||||
|
I2C1_ER_IRQHandler
|
||||||
|
I2C2_EV_IRQHandler
|
||||||
|
I2C2_ER_IRQHandler
|
||||||
|
SPI1_IRQHandler
|
||||||
|
SPI2_IRQHandler
|
||||||
|
USART1_IRQHandler
|
||||||
|
USART2_IRQHandler
|
||||||
|
USART3_IRQHandler
|
||||||
|
EXTI15_10_IRQHandler
|
||||||
|
RTC_Alarm_IRQHandler
|
||||||
|
OTG_FS_WKUP_IRQHandler
|
||||||
|
TIM5_IRQHandler
|
||||||
|
SPI3_IRQHandler
|
||||||
|
UART4_IRQHandler
|
||||||
|
UART5_IRQHandler
|
||||||
|
TIM6_IRQHandler
|
||||||
|
TIM7_IRQHandler
|
||||||
|
DMA2_Channel1_IRQHandler
|
||||||
|
DMA2_Channel2_IRQHandler
|
||||||
|
DMA2_Channel3_IRQHandler
|
||||||
|
DMA2_Channel4_IRQHandler
|
||||||
|
DMA2_Channel5_IRQHandler
|
||||||
|
CAN2_TX_IRQHandler
|
||||||
|
CAN2_RX0_IRQHandler
|
||||||
|
CAN2_RX1_IRQHandler
|
||||||
|
CAN2_SCE_IRQHandler
|
||||||
|
OTG_FS_IRQHandler
|
||||||
|
|
||||||
|
B .
|
||||||
|
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
;*******************************************************************************
|
||||||
|
; User Stack and Heap initialization
|
||||||
|
;*******************************************************************************
|
||||||
|
IF :DEF:__MICROLIB
|
||||||
|
|
||||||
|
EXPORT __initial_sp
|
||||||
|
EXPORT __heap_base
|
||||||
|
EXPORT __heap_limit
|
||||||
|
|
||||||
|
ELSE
|
||||||
|
|
||||||
|
IMPORT __use_two_region_memory
|
||||||
|
EXPORT __user_initial_stackheap
|
||||||
|
|
||||||
|
__user_initial_stackheap
|
||||||
|
|
||||||
|
LDR R0, = Heap_Mem
|
||||||
|
LDR R1, =(Stack_Mem + Stack_Size)
|
||||||
|
LDR R2, = (Heap_Mem + Heap_Size)
|
||||||
|
LDR R3, = Stack_Mem
|
||||||
|
BX LR
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
ENDIF
|
||||||
|
|
||||||
|
END
|
||||||
|
|
||||||
|
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||||
|
|
@ -0,0 +1,385 @@
|
||||||
|
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
|
||||||
|
;* File Name : startup_stm32f107xc.s
|
||||||
|
;* Author : MCD Application Team
|
||||||
|
;* Version : V4.2.0
|
||||||
|
;* Date : 31-March-2017
|
||||||
|
;* Description : STM32F107xC Devices vector table for MDK-ARM toolchain.
|
||||||
|
;* This module performs:
|
||||||
|
;* - Set the initial SP
|
||||||
|
;* - Set the initial PC == Reset_Handler
|
||||||
|
;* - Set the vector table entries with the exceptions ISR address
|
||||||
|
;* - Configure the clock system
|
||||||
|
;* - Branches to __main in the C library (which eventually
|
||||||
|
;* calls main()).
|
||||||
|
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||||
|
;* priority is Privileged, and the Stack is set to Main.
|
||||||
|
;********************************************************************************
|
||||||
|
;*
|
||||||
|
;* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||||
|
;*
|
||||||
|
;* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
;* are permitted provided that the following conditions are met:
|
||||||
|
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
;* this list of conditions and the following disclaimer.
|
||||||
|
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
;* this list of conditions and the following disclaimer in the documentation
|
||||||
|
;* and/or other materials provided with the distribution.
|
||||||
|
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
;* may be used to endorse or promote products derived from this software
|
||||||
|
;* without specific prior written permission.
|
||||||
|
;*
|
||||||
|
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
;
|
||||||
|
;*******************************************************************************
|
||||||
|
|
||||||
|
; Amount of memory (in bytes) allocated for Stack
|
||||||
|
; Tailor this value to your application needs
|
||||||
|
; <h> Stack Configuration
|
||||||
|
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Stack_Size EQU 0x00000400
|
||||||
|
|
||||||
|
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||||
|
Stack_Mem SPACE Stack_Size
|
||||||
|
__initial_sp
|
||||||
|
|
||||||
|
|
||||||
|
; <h> Heap Configuration
|
||||||
|
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Heap_Size EQU 0x00000200
|
||||||
|
|
||||||
|
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||||
|
__heap_base
|
||||||
|
Heap_Mem SPACE Heap_Size
|
||||||
|
__heap_limit
|
||||||
|
|
||||||
|
PRESERVE8
|
||||||
|
THUMB
|
||||||
|
|
||||||
|
|
||||||
|
; Vector Table Mapped to Address 0 at Reset
|
||||||
|
AREA RESET, DATA, READONLY
|
||||||
|
EXPORT __Vectors
|
||||||
|
EXPORT __Vectors_End
|
||||||
|
EXPORT __Vectors_Size
|
||||||
|
|
||||||
|
__Vectors DCD __initial_sp ; Top of Stack
|
||||||
|
DCD Reset_Handler ; Reset Handler
|
||||||
|
DCD NMI_Handler ; NMI Handler
|
||||||
|
DCD HardFault_Handler ; Hard Fault Handler
|
||||||
|
DCD MemManage_Handler ; MPU Fault Handler
|
||||||
|
DCD BusFault_Handler ; Bus Fault Handler
|
||||||
|
DCD UsageFault_Handler ; Usage Fault Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; SVCall Handler
|
||||||
|
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD PendSV_Handler ; PendSV Handler
|
||||||
|
DCD SysTick_Handler ; SysTick Handler
|
||||||
|
|
||||||
|
; External Interrupts
|
||||||
|
DCD WWDG_IRQHandler ; Window Watchdog
|
||||||
|
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||||
|
DCD TAMPER_IRQHandler ; Tamper
|
||||||
|
DCD RTC_IRQHandler ; RTC
|
||||||
|
DCD FLASH_IRQHandler ; Flash
|
||||||
|
DCD RCC_IRQHandler ; RCC
|
||||||
|
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||||
|
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||||
|
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||||
|
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||||
|
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||||
|
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||||
|
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||||
|
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||||
|
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||||
|
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||||
|
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||||
|
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||||
|
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
|
||||||
|
DCD CAN1_TX_IRQHandler ; CAN1 TX
|
||||||
|
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
|
||||||
|
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
|
||||||
|
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
|
||||||
|
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||||
|
DCD TIM1_BRK_IRQHandler ; TIM1 Break
|
||||||
|
DCD TIM1_UP_IRQHandler ; TIM1 Update
|
||||||
|
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
|
||||||
|
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||||
|
DCD TIM2_IRQHandler ; TIM2
|
||||||
|
DCD TIM3_IRQHandler ; TIM3
|
||||||
|
DCD TIM4_IRQHandler ; TIM4
|
||||||
|
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||||
|
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||||
|
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||||
|
DCD I2C2_ER_IRQHandler ; I2C1 Error
|
||||||
|
DCD SPI1_IRQHandler ; SPI1
|
||||||
|
DCD SPI2_IRQHandler ; SPI2
|
||||||
|
DCD USART1_IRQHandler ; USART1
|
||||||
|
DCD USART2_IRQHandler ; USART2
|
||||||
|
DCD USART3_IRQHandler ; USART3
|
||||||
|
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||||
|
DCD RTC_Alarm_IRQHandler ; RTC alarm through EXTI line
|
||||||
|
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD TIM5_IRQHandler ; TIM5
|
||||||
|
DCD SPI3_IRQHandler ; SPI3
|
||||||
|
DCD UART4_IRQHandler ; UART4
|
||||||
|
DCD UART5_IRQHandler ; UART5
|
||||||
|
DCD TIM6_IRQHandler ; TIM6
|
||||||
|
DCD TIM7_IRQHandler ; TIM7
|
||||||
|
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
|
||||||
|
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
|
||||||
|
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
|
||||||
|
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4
|
||||||
|
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
|
||||||
|
DCD ETH_IRQHandler ; Ethernet
|
||||||
|
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
|
||||||
|
DCD CAN2_TX_IRQHandler ; CAN2 TX
|
||||||
|
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
|
||||||
|
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
|
||||||
|
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
|
||||||
|
DCD OTG_FS_IRQHandler ; USB OTG FS
|
||||||
|
__Vectors_End
|
||||||
|
|
||||||
|
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||||
|
|
||||||
|
AREA |.text|, CODE, READONLY
|
||||||
|
|
||||||
|
; Reset handler
|
||||||
|
Reset_Handler PROC
|
||||||
|
EXPORT Reset_Handler [WEAK]
|
||||||
|
IMPORT SystemInit
|
||||||
|
IMPORT __main
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__main
|
||||||
|
BX R0
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||||
|
|
||||||
|
NMI_Handler PROC
|
||||||
|
EXPORT NMI_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
HardFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT HardFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
MemManage_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT MemManage_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
BusFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT BusFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
UsageFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT UsageFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SVC_Handler PROC
|
||||||
|
EXPORT SVC_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
DebugMon_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT DebugMon_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
PendSV_Handler PROC
|
||||||
|
EXPORT PendSV_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SysTick_Handler PROC
|
||||||
|
EXPORT SysTick_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
Default_Handler PROC
|
||||||
|
|
||||||
|
EXPORT WWDG_IRQHandler [WEAK]
|
||||||
|
EXPORT PVD_IRQHandler [WEAK]
|
||||||
|
EXPORT TAMPER_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_IRQHandler [WEAK]
|
||||||
|
EXPORT FLASH_IRQHandler [WEAK]
|
||||||
|
EXPORT RCC_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI0_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI1_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI2_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI3_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||||
|
EXPORT ADC1_2_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN1_TX_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN1_RX0_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN1_RX1_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN1_SCE_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_BRK_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_UP_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM2_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM3_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM4_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI1_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI2_IRQHandler [WEAK]
|
||||||
|
EXPORT USART1_IRQHandler [WEAK]
|
||||||
|
EXPORT USART2_IRQHandler [WEAK]
|
||||||
|
EXPORT USART3_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||||
|
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM5_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI3_IRQHandler [WEAK]
|
||||||
|
EXPORT UART4_IRQHandler [WEAK]
|
||||||
|
EXPORT UART5_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM6_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM7_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Channel1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Channel2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Channel3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Channel4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA2_Channel5_IRQHandler [WEAK]
|
||||||
|
EXPORT ETH_IRQHandler [WEAK]
|
||||||
|
EXPORT ETH_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN2_TX_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN2_RX0_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN2_RX1_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN2_SCE_IRQHandler [WEAK]
|
||||||
|
EXPORT OTG_FS_IRQHandler [WEAK]
|
||||||
|
|
||||||
|
WWDG_IRQHandler
|
||||||
|
PVD_IRQHandler
|
||||||
|
TAMPER_IRQHandler
|
||||||
|
RTC_IRQHandler
|
||||||
|
FLASH_IRQHandler
|
||||||
|
RCC_IRQHandler
|
||||||
|
EXTI0_IRQHandler
|
||||||
|
EXTI1_IRQHandler
|
||||||
|
EXTI2_IRQHandler
|
||||||
|
EXTI3_IRQHandler
|
||||||
|
EXTI4_IRQHandler
|
||||||
|
DMA1_Channel1_IRQHandler
|
||||||
|
DMA1_Channel2_IRQHandler
|
||||||
|
DMA1_Channel3_IRQHandler
|
||||||
|
DMA1_Channel4_IRQHandler
|
||||||
|
DMA1_Channel5_IRQHandler
|
||||||
|
DMA1_Channel6_IRQHandler
|
||||||
|
DMA1_Channel7_IRQHandler
|
||||||
|
ADC1_2_IRQHandler
|
||||||
|
CAN1_TX_IRQHandler
|
||||||
|
CAN1_RX0_IRQHandler
|
||||||
|
CAN1_RX1_IRQHandler
|
||||||
|
CAN1_SCE_IRQHandler
|
||||||
|
EXTI9_5_IRQHandler
|
||||||
|
TIM1_BRK_IRQHandler
|
||||||
|
TIM1_UP_IRQHandler
|
||||||
|
TIM1_TRG_COM_IRQHandler
|
||||||
|
TIM1_CC_IRQHandler
|
||||||
|
TIM2_IRQHandler
|
||||||
|
TIM3_IRQHandler
|
||||||
|
TIM4_IRQHandler
|
||||||
|
I2C1_EV_IRQHandler
|
||||||
|
I2C1_ER_IRQHandler
|
||||||
|
I2C2_EV_IRQHandler
|
||||||
|
I2C2_ER_IRQHandler
|
||||||
|
SPI1_IRQHandler
|
||||||
|
SPI2_IRQHandler
|
||||||
|
USART1_IRQHandler
|
||||||
|
USART2_IRQHandler
|
||||||
|
USART3_IRQHandler
|
||||||
|
EXTI15_10_IRQHandler
|
||||||
|
RTC_Alarm_IRQHandler
|
||||||
|
OTG_FS_WKUP_IRQHandler
|
||||||
|
TIM5_IRQHandler
|
||||||
|
SPI3_IRQHandler
|
||||||
|
UART4_IRQHandler
|
||||||
|
UART5_IRQHandler
|
||||||
|
TIM6_IRQHandler
|
||||||
|
TIM7_IRQHandler
|
||||||
|
DMA2_Channel1_IRQHandler
|
||||||
|
DMA2_Channel2_IRQHandler
|
||||||
|
DMA2_Channel3_IRQHandler
|
||||||
|
DMA2_Channel4_IRQHandler
|
||||||
|
DMA2_Channel5_IRQHandler
|
||||||
|
ETH_IRQHandler
|
||||||
|
ETH_WKUP_IRQHandler
|
||||||
|
CAN2_TX_IRQHandler
|
||||||
|
CAN2_RX0_IRQHandler
|
||||||
|
CAN2_RX1_IRQHandler
|
||||||
|
CAN2_SCE_IRQHandler
|
||||||
|
OTG_FS_IRQHandler
|
||||||
|
|
||||||
|
B .
|
||||||
|
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
;*******************************************************************************
|
||||||
|
; User Stack and Heap initialization
|
||||||
|
;*******************************************************************************
|
||||||
|
IF :DEF:__MICROLIB
|
||||||
|
|
||||||
|
EXPORT __initial_sp
|
||||||
|
EXPORT __heap_base
|
||||||
|
EXPORT __heap_limit
|
||||||
|
|
||||||
|
ELSE
|
||||||
|
|
||||||
|
IMPORT __use_two_region_memory
|
||||||
|
EXPORT __user_initial_stackheap
|
||||||
|
|
||||||
|
__user_initial_stackheap
|
||||||
|
|
||||||
|
LDR R0, = Heap_Mem
|
||||||
|
LDR R1, =(Stack_Mem + Stack_Size)
|
||||||
|
LDR R2, = (Heap_Mem + Heap_Size)
|
||||||
|
LDR R3, = Stack_Mem
|
||||||
|
BX LR
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
ENDIF
|
||||||
|
|
||||||
|
END
|
||||||
|
|
||||||
|
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||||
|
|
@ -0,0 +1,166 @@
|
||||||
|
/*
|
||||||
|
*****************************************************************************
|
||||||
|
**
|
||||||
|
** File : STM32F100XB_FLASH.ld
|
||||||
|
**
|
||||||
|
** Abstract : Linker script for STM32F100xB Device with
|
||||||
|
** 128KByte FLASH, 8KByte RAM
|
||||||
|
**
|
||||||
|
** Set heap size, stack size and stack location according
|
||||||
|
** to application requirements.
|
||||||
|
**
|
||||||
|
** Set memory bank area and size if external memory is used.
|
||||||
|
**
|
||||||
|
** Target : STMicroelectronics STM32
|
||||||
|
**
|
||||||
|
** Environment : Atollic TrueSTUDIO(R)
|
||||||
|
**
|
||||||
|
** Distribution: The file is distributed “as is,” without any warranty
|
||||||
|
** of any kind.
|
||||||
|
**
|
||||||
|
** (c)Copyright Atollic AB.
|
||||||
|
** You may use this file as-is or modify it according to the needs of your
|
||||||
|
** project. This file may only be built (assembled or compiled and linked)
|
||||||
|
** using the Atollic TrueSTUDIO(R) product. The use of this file together
|
||||||
|
** with other tools than Atollic TrueSTUDIO(R) is not permitted.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
*/
|
||||||
|
0
|
||||||
|
/* Entry Point */
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
0
|
||||||
|
/* Highest address of the user mode stack */
|
||||||
|
_estack = 0x20001FFF; /* end of RAM */
|
||||||
|
0
|
||||||
|
/* Generate a link error if heap and stack don't fit into RAM */
|
||||||
|
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||||
|
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||||
|
0
|
||||||
|
/* Specify the memory areas */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K
|
||||||
|
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 8K
|
||||||
|
}
|
||||||
|
0
|
||||||
|
/* Define output sections */
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
/* The startup code goes first into FLASH */
|
||||||
|
.isr_vector :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.isr_vector)) /* Startup code */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
/* The program code and other data goes into FLASH */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text) /* .text sections (code) */
|
||||||
|
*(.text*) /* .text* sections (code) */
|
||||||
|
*(.glue_7) /* glue arm to thumb code */
|
||||||
|
*(.glue_7t) /* glue thumb to arm code */
|
||||||
|
*(.eh_frame)
|
||||||
|
0
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
0
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etext = .; /* define a global symbols at end of code */
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
/* Constant data goes into FLASH */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||||
|
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||||
|
.ARM : {
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
/* used by the startup to initialize data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
0
|
||||||
|
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
_sdata = .; /* create a global symbol at data start */
|
||||||
|
*(.data) /* .data sections */
|
||||||
|
*(.data*) /* .data* sections */
|
||||||
|
0
|
||||||
|
. = ALIGN(4);
|
||||||
|
_edata = .; /* define a global symbol at data end */
|
||||||
|
} >RAM AT> FLASH
|
||||||
|
0
|
||||||
|
|
||||||
|
/* Uninitialized data section */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
/* This is used by the startup in order to initialize the .bss secion */
|
||||||
|
_sbss = .; /* define a global symbol at bss start */
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
0
|
||||||
|
. = ALIGN(4);
|
||||||
|
_ebss = .; /* define a global symbol at bss end */
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} >RAM
|
||||||
|
0
|
||||||
|
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||||
|
._user_heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
PROVIDE ( end = . );
|
||||||
|
PROVIDE ( _end = . );
|
||||||
|
. = . + _Min_Heap_Size;
|
||||||
|
. = . + _Min_Stack_Size;
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >RAM
|
||||||
|
0
|
||||||
|
|
||||||
|
0
|
||||||
|
/* Remove information from the standard libraries */
|
||||||
|
/DISCARD/ :
|
||||||
|
{
|
||||||
|
libc.a ( * )
|
||||||
|
libm.a ( * )
|
||||||
|
libgcc.a ( * )
|
||||||
|
}
|
||||||
|
0
|
||||||
|
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,166 @@
|
||||||
|
/*
|
||||||
|
*****************************************************************************
|
||||||
|
**
|
||||||
|
** File : STM32F100XE_FLASH.ld
|
||||||
|
**
|
||||||
|
** Abstract : Linker script for STM32F100xE Device with
|
||||||
|
** 512KByte FLASH, 32KByte RAM
|
||||||
|
**
|
||||||
|
** Set heap size, stack size and stack location according
|
||||||
|
** to application requirements.
|
||||||
|
**
|
||||||
|
** Set memory bank area and size if external memory is used.
|
||||||
|
**
|
||||||
|
** Target : STMicroelectronics STM32
|
||||||
|
**
|
||||||
|
** Environment : Atollic TrueSTUDIO(R)
|
||||||
|
**
|
||||||
|
** Distribution: The file is distributed “as is,” without any warranty
|
||||||
|
** of any kind.
|
||||||
|
**
|
||||||
|
** (c)Copyright Atollic AB.
|
||||||
|
** You may use this file as-is or modify it according to the needs of your
|
||||||
|
** project. This file may only be built (assembled or compiled and linked)
|
||||||
|
** using the Atollic TrueSTUDIO(R) product. The use of this file together
|
||||||
|
** with other tools than Atollic TrueSTUDIO(R) is not permitted.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
*/
|
||||||
|
0
|
||||||
|
/* Entry Point */
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
0
|
||||||
|
/* Highest address of the user mode stack */
|
||||||
|
_estack = 0x20007FFF; /* end of RAM */
|
||||||
|
0
|
||||||
|
/* Generate a link error if heap and stack don't fit into RAM */
|
||||||
|
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||||
|
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||||
|
0
|
||||||
|
/* Specify the memory areas */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K
|
||||||
|
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K
|
||||||
|
}
|
||||||
|
0
|
||||||
|
/* Define output sections */
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
/* The startup code goes first into FLASH */
|
||||||
|
.isr_vector :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.isr_vector)) /* Startup code */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
/* The program code and other data goes into FLASH */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text) /* .text sections (code) */
|
||||||
|
*(.text*) /* .text* sections (code) */
|
||||||
|
*(.glue_7) /* glue arm to thumb code */
|
||||||
|
*(.glue_7t) /* glue thumb to arm code */
|
||||||
|
*(.eh_frame)
|
||||||
|
0
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
0
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etext = .; /* define a global symbols at end of code */
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
/* Constant data goes into FLASH */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||||
|
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||||
|
.ARM : {
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
/* used by the startup to initialize data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
0
|
||||||
|
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
_sdata = .; /* create a global symbol at data start */
|
||||||
|
*(.data) /* .data sections */
|
||||||
|
*(.data*) /* .data* sections */
|
||||||
|
0
|
||||||
|
. = ALIGN(4);
|
||||||
|
_edata = .; /* define a global symbol at data end */
|
||||||
|
} >RAM AT> FLASH
|
||||||
|
0
|
||||||
|
|
||||||
|
/* Uninitialized data section */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
/* This is used by the startup in order to initialize the .bss secion */
|
||||||
|
_sbss = .; /* define a global symbol at bss start */
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
0
|
||||||
|
. = ALIGN(4);
|
||||||
|
_ebss = .; /* define a global symbol at bss end */
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} >RAM
|
||||||
|
0
|
||||||
|
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||||
|
._user_heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
PROVIDE ( end = . );
|
||||||
|
PROVIDE ( _end = . );
|
||||||
|
. = . + _Min_Heap_Size;
|
||||||
|
. = . + _Min_Stack_Size;
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >RAM
|
||||||
|
0
|
||||||
|
|
||||||
|
0
|
||||||
|
/* Remove information from the standard libraries */
|
||||||
|
/DISCARD/ :
|
||||||
|
{
|
||||||
|
libc.a ( * )
|
||||||
|
libm.a ( * )
|
||||||
|
libgcc.a ( * )
|
||||||
|
}
|
||||||
|
0
|
||||||
|
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,166 @@
|
||||||
|
/*
|
||||||
|
*****************************************************************************
|
||||||
|
**
|
||||||
|
** File : STM32F101X6_FLASH.ld
|
||||||
|
**
|
||||||
|
** Abstract : Linker script for STM32F101x6 Device with
|
||||||
|
** 32KByte FLASH, 6KByte RAM
|
||||||
|
**
|
||||||
|
** Set heap size, stack size and stack location according
|
||||||
|
** to application requirements.
|
||||||
|
**
|
||||||
|
** Set memory bank area and size if external memory is used.
|
||||||
|
**
|
||||||
|
** Target : STMicroelectronics STM32
|
||||||
|
**
|
||||||
|
** Environment : Atollic TrueSTUDIO(R)
|
||||||
|
**
|
||||||
|
** Distribution: The file is distributed “as is,” without any warranty
|
||||||
|
** of any kind.
|
||||||
|
**
|
||||||
|
** (c)Copyright Atollic AB.
|
||||||
|
** You may use this file as-is or modify it according to the needs of your
|
||||||
|
** project. This file may only be built (assembled or compiled and linked)
|
||||||
|
** using the Atollic TrueSTUDIO(R) product. The use of this file together
|
||||||
|
** with other tools than Atollic TrueSTUDIO(R) is not permitted.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
*/
|
||||||
|
0
|
||||||
|
/* Entry Point */
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
0
|
||||||
|
/* Highest address of the user mode stack */
|
||||||
|
_estack = 0x200017FF; /* end of RAM */
|
||||||
|
0
|
||||||
|
/* Generate a link error if heap and stack don't fit into RAM */
|
||||||
|
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||||
|
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||||
|
0
|
||||||
|
/* Specify the memory areas */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 32K
|
||||||
|
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 6K
|
||||||
|
}
|
||||||
|
0
|
||||||
|
/* Define output sections */
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
/* The startup code goes first into FLASH */
|
||||||
|
.isr_vector :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.isr_vector)) /* Startup code */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
/* The program code and other data goes into FLASH */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text) /* .text sections (code) */
|
||||||
|
*(.text*) /* .text* sections (code) */
|
||||||
|
*(.glue_7) /* glue arm to thumb code */
|
||||||
|
*(.glue_7t) /* glue thumb to arm code */
|
||||||
|
*(.eh_frame)
|
||||||
|
0
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
0
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etext = .; /* define a global symbols at end of code */
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
/* Constant data goes into FLASH */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||||
|
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||||
|
.ARM : {
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
/* used by the startup to initialize data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
0
|
||||||
|
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
_sdata = .; /* create a global symbol at data start */
|
||||||
|
*(.data) /* .data sections */
|
||||||
|
*(.data*) /* .data* sections */
|
||||||
|
0
|
||||||
|
. = ALIGN(4);
|
||||||
|
_edata = .; /* define a global symbol at data end */
|
||||||
|
} >RAM AT> FLASH
|
||||||
|
0
|
||||||
|
|
||||||
|
/* Uninitialized data section */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
/* This is used by the startup in order to initialize the .bss secion */
|
||||||
|
_sbss = .; /* define a global symbol at bss start */
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
0
|
||||||
|
. = ALIGN(4);
|
||||||
|
_ebss = .; /* define a global symbol at bss end */
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} >RAM
|
||||||
|
0
|
||||||
|
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||||
|
._user_heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
PROVIDE ( end = . );
|
||||||
|
PROVIDE ( _end = . );
|
||||||
|
. = . + _Min_Heap_Size;
|
||||||
|
. = . + _Min_Stack_Size;
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >RAM
|
||||||
|
0
|
||||||
|
|
||||||
|
0
|
||||||
|
/* Remove information from the standard libraries */
|
||||||
|
/DISCARD/ :
|
||||||
|
{
|
||||||
|
libc.a ( * )
|
||||||
|
libm.a ( * )
|
||||||
|
libgcc.a ( * )
|
||||||
|
}
|
||||||
|
0
|
||||||
|
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,166 @@
|
||||||
|
/*
|
||||||
|
*****************************************************************************
|
||||||
|
**
|
||||||
|
** File : STM32F101XB_FLASH.ld
|
||||||
|
**
|
||||||
|
** Abstract : Linker script for STM32F101xB Device with
|
||||||
|
** 128KByte FLASH, 16KByte RAM
|
||||||
|
**
|
||||||
|
** Set heap size, stack size and stack location according
|
||||||
|
** to application requirements.
|
||||||
|
**
|
||||||
|
** Set memory bank area and size if external memory is used.
|
||||||
|
**
|
||||||
|
** Target : STMicroelectronics STM32
|
||||||
|
**
|
||||||
|
** Environment : Atollic TrueSTUDIO(R)
|
||||||
|
**
|
||||||
|
** Distribution: The file is distributed “as is,” without any warranty
|
||||||
|
** of any kind.
|
||||||
|
**
|
||||||
|
** (c)Copyright Atollic AB.
|
||||||
|
** You may use this file as-is or modify it according to the needs of your
|
||||||
|
** project. This file may only be built (assembled or compiled and linked)
|
||||||
|
** using the Atollic TrueSTUDIO(R) product. The use of this file together
|
||||||
|
** with other tools than Atollic TrueSTUDIO(R) is not permitted.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
*/
|
||||||
|
0
|
||||||
|
/* Entry Point */
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
0
|
||||||
|
/* Highest address of the user mode stack */
|
||||||
|
_estack = 0x20003FFF; /* end of RAM */
|
||||||
|
0
|
||||||
|
/* Generate a link error if heap and stack don't fit into RAM */
|
||||||
|
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||||
|
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||||
|
0
|
||||||
|
/* Specify the memory areas */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K
|
||||||
|
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 16K
|
||||||
|
}
|
||||||
|
0
|
||||||
|
/* Define output sections */
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
/* The startup code goes first into FLASH */
|
||||||
|
.isr_vector :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.isr_vector)) /* Startup code */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
/* The program code and other data goes into FLASH */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text) /* .text sections (code) */
|
||||||
|
*(.text*) /* .text* sections (code) */
|
||||||
|
*(.glue_7) /* glue arm to thumb code */
|
||||||
|
*(.glue_7t) /* glue thumb to arm code */
|
||||||
|
*(.eh_frame)
|
||||||
|
0
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
0
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etext = .; /* define a global symbols at end of code */
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
/* Constant data goes into FLASH */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||||
|
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||||
|
.ARM : {
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
/* used by the startup to initialize data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
0
|
||||||
|
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
_sdata = .; /* create a global symbol at data start */
|
||||||
|
*(.data) /* .data sections */
|
||||||
|
*(.data*) /* .data* sections */
|
||||||
|
0
|
||||||
|
. = ALIGN(4);
|
||||||
|
_edata = .; /* define a global symbol at data end */
|
||||||
|
} >RAM AT> FLASH
|
||||||
|
0
|
||||||
|
|
||||||
|
/* Uninitialized data section */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
/* This is used by the startup in order to initialize the .bss secion */
|
||||||
|
_sbss = .; /* define a global symbol at bss start */
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
0
|
||||||
|
. = ALIGN(4);
|
||||||
|
_ebss = .; /* define a global symbol at bss end */
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} >RAM
|
||||||
|
0
|
||||||
|
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||||
|
._user_heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
PROVIDE ( end = . );
|
||||||
|
PROVIDE ( _end = . );
|
||||||
|
. = . + _Min_Heap_Size;
|
||||||
|
. = . + _Min_Stack_Size;
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >RAM
|
||||||
|
0
|
||||||
|
|
||||||
|
0
|
||||||
|
/* Remove information from the standard libraries */
|
||||||
|
/DISCARD/ :
|
||||||
|
{
|
||||||
|
libc.a ( * )
|
||||||
|
libm.a ( * )
|
||||||
|
libgcc.a ( * )
|
||||||
|
}
|
||||||
|
0
|
||||||
|
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,166 @@
|
||||||
|
/*
|
||||||
|
*****************************************************************************
|
||||||
|
**
|
||||||
|
** File : STM32F101XE_FLASH.ld
|
||||||
|
**
|
||||||
|
** Abstract : Linker script for STM32F101xE Device with
|
||||||
|
** 512KByte FLASH, 48KByte RAM
|
||||||
|
**
|
||||||
|
** Set heap size, stack size and stack location according
|
||||||
|
** to application requirements.
|
||||||
|
**
|
||||||
|
** Set memory bank area and size if external memory is used.
|
||||||
|
**
|
||||||
|
** Target : STMicroelectronics STM32
|
||||||
|
**
|
||||||
|
** Environment : Atollic TrueSTUDIO(R)
|
||||||
|
**
|
||||||
|
** Distribution: The file is distributed “as is,” without any warranty
|
||||||
|
** of any kind.
|
||||||
|
**
|
||||||
|
** (c)Copyright Atollic AB.
|
||||||
|
** You may use this file as-is or modify it according to the needs of your
|
||||||
|
** project. This file may only be built (assembled or compiled and linked)
|
||||||
|
** using the Atollic TrueSTUDIO(R) product. The use of this file together
|
||||||
|
** with other tools than Atollic TrueSTUDIO(R) is not permitted.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
*/
|
||||||
|
0
|
||||||
|
/* Entry Point */
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
0
|
||||||
|
/* Highest address of the user mode stack */
|
||||||
|
_estack = 0x2000BFFF; /* end of RAM */
|
||||||
|
0
|
||||||
|
/* Generate a link error if heap and stack don't fit into RAM */
|
||||||
|
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||||
|
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||||
|
0
|
||||||
|
/* Specify the memory areas */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K
|
||||||
|
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 48K
|
||||||
|
}
|
||||||
|
0
|
||||||
|
/* Define output sections */
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
/* The startup code goes first into FLASH */
|
||||||
|
.isr_vector :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.isr_vector)) /* Startup code */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
/* The program code and other data goes into FLASH */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text) /* .text sections (code) */
|
||||||
|
*(.text*) /* .text* sections (code) */
|
||||||
|
*(.glue_7) /* glue arm to thumb code */
|
||||||
|
*(.glue_7t) /* glue thumb to arm code */
|
||||||
|
*(.eh_frame)
|
||||||
|
0
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
0
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etext = .; /* define a global symbols at end of code */
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
/* Constant data goes into FLASH */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||||
|
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||||
|
.ARM : {
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
/* used by the startup to initialize data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
0
|
||||||
|
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
_sdata = .; /* create a global symbol at data start */
|
||||||
|
*(.data) /* .data sections */
|
||||||
|
*(.data*) /* .data* sections */
|
||||||
|
0
|
||||||
|
. = ALIGN(4);
|
||||||
|
_edata = .; /* define a global symbol at data end */
|
||||||
|
} >RAM AT> FLASH
|
||||||
|
0
|
||||||
|
|
||||||
|
/* Uninitialized data section */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
/* This is used by the startup in order to initialize the .bss secion */
|
||||||
|
_sbss = .; /* define a global symbol at bss start */
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
0
|
||||||
|
. = ALIGN(4);
|
||||||
|
_ebss = .; /* define a global symbol at bss end */
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} >RAM
|
||||||
|
0
|
||||||
|
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||||
|
._user_heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
PROVIDE ( end = . );
|
||||||
|
PROVIDE ( _end = . );
|
||||||
|
. = . + _Min_Heap_Size;
|
||||||
|
. = . + _Min_Stack_Size;
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >RAM
|
||||||
|
0
|
||||||
|
|
||||||
|
0
|
||||||
|
/* Remove information from the standard libraries */
|
||||||
|
/DISCARD/ :
|
||||||
|
{
|
||||||
|
libc.a ( * )
|
||||||
|
libm.a ( * )
|
||||||
|
libgcc.a ( * )
|
||||||
|
}
|
||||||
|
0
|
||||||
|
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,166 @@
|
||||||
|
/*
|
||||||
|
*****************************************************************************
|
||||||
|
**
|
||||||
|
** File : STM32F101XG_FLASH.ld
|
||||||
|
**
|
||||||
|
** Abstract : Linker script for STM32F101xG Device with
|
||||||
|
** 1000KByte FLASH, 80KByte RAM
|
||||||
|
**
|
||||||
|
** Set heap size, stack size and stack location according
|
||||||
|
** to application requirements.
|
||||||
|
**
|
||||||
|
** Set memory bank area and size if external memory is used.
|
||||||
|
**
|
||||||
|
** Target : STMicroelectronics STM32
|
||||||
|
**
|
||||||
|
** Environment : Atollic TrueSTUDIO(R)
|
||||||
|
**
|
||||||
|
** Distribution: The file is distributed “as is,” without any warranty
|
||||||
|
** of any kind.
|
||||||
|
**
|
||||||
|
** (c)Copyright Atollic AB.
|
||||||
|
** You may use this file as-is or modify it according to the needs of your
|
||||||
|
** project. This file may only be built (assembled or compiled and linked)
|
||||||
|
** using the Atollic TrueSTUDIO(R) product. The use of this file together
|
||||||
|
** with other tools than Atollic TrueSTUDIO(R) is not permitted.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
*/
|
||||||
|
0
|
||||||
|
/* Entry Point */
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
0
|
||||||
|
/* Highest address of the user mode stack */
|
||||||
|
_estack = 0x20013FFF; /* end of RAM */
|
||||||
|
0
|
||||||
|
/* Generate a link error if heap and stack don't fit into RAM */
|
||||||
|
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||||
|
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||||
|
0
|
||||||
|
/* Specify the memory areas */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1000K
|
||||||
|
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 80K
|
||||||
|
}
|
||||||
|
0
|
||||||
|
/* Define output sections */
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
/* The startup code goes first into FLASH */
|
||||||
|
.isr_vector :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.isr_vector)) /* Startup code */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
/* The program code and other data goes into FLASH */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text) /* .text sections (code) */
|
||||||
|
*(.text*) /* .text* sections (code) */
|
||||||
|
*(.glue_7) /* glue arm to thumb code */
|
||||||
|
*(.glue_7t) /* glue thumb to arm code */
|
||||||
|
*(.eh_frame)
|
||||||
|
0
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
0
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etext = .; /* define a global symbols at end of code */
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
/* Constant data goes into FLASH */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||||
|
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||||
|
.ARM : {
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
/* used by the startup to initialize data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
0
|
||||||
|
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
_sdata = .; /* create a global symbol at data start */
|
||||||
|
*(.data) /* .data sections */
|
||||||
|
*(.data*) /* .data* sections */
|
||||||
|
0
|
||||||
|
. = ALIGN(4);
|
||||||
|
_edata = .; /* define a global symbol at data end */
|
||||||
|
} >RAM AT> FLASH
|
||||||
|
0
|
||||||
|
|
||||||
|
/* Uninitialized data section */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
/* This is used by the startup in order to initialize the .bss secion */
|
||||||
|
_sbss = .; /* define a global symbol at bss start */
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
0
|
||||||
|
. = ALIGN(4);
|
||||||
|
_ebss = .; /* define a global symbol at bss end */
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} >RAM
|
||||||
|
0
|
||||||
|
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||||
|
._user_heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
PROVIDE ( end = . );
|
||||||
|
PROVIDE ( _end = . );
|
||||||
|
. = . + _Min_Heap_Size;
|
||||||
|
. = . + _Min_Stack_Size;
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >RAM
|
||||||
|
0
|
||||||
|
|
||||||
|
0
|
||||||
|
/* Remove information from the standard libraries */
|
||||||
|
/DISCARD/ :
|
||||||
|
{
|
||||||
|
libc.a ( * )
|
||||||
|
libm.a ( * )
|
||||||
|
libgcc.a ( * )
|
||||||
|
}
|
||||||
|
0
|
||||||
|
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,166 @@
|
||||||
|
/*
|
||||||
|
*****************************************************************************
|
||||||
|
**
|
||||||
|
** File : STM32F102X6_FLASH.ld
|
||||||
|
**
|
||||||
|
** Abstract : Linker script for STM32F102x6 Device with
|
||||||
|
** 32KByte FLASH, 6KByte RAM
|
||||||
|
**
|
||||||
|
** Set heap size, stack size and stack location according
|
||||||
|
** to application requirements.
|
||||||
|
**
|
||||||
|
** Set memory bank area and size if external memory is used.
|
||||||
|
**
|
||||||
|
** Target : STMicroelectronics STM32
|
||||||
|
**
|
||||||
|
** Environment : Atollic TrueSTUDIO(R)
|
||||||
|
**
|
||||||
|
** Distribution: The file is distributed “as is,” without any warranty
|
||||||
|
** of any kind.
|
||||||
|
**
|
||||||
|
** (c)Copyright Atollic AB.
|
||||||
|
** You may use this file as-is or modify it according to the needs of your
|
||||||
|
** project. This file may only be built (assembled or compiled and linked)
|
||||||
|
** using the Atollic TrueSTUDIO(R) product. The use of this file together
|
||||||
|
** with other tools than Atollic TrueSTUDIO(R) is not permitted.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
*/
|
||||||
|
0
|
||||||
|
/* Entry Point */
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
0
|
||||||
|
/* Highest address of the user mode stack */
|
||||||
|
_estack = 0x200017FF; /* end of RAM */
|
||||||
|
0
|
||||||
|
/* Generate a link error if heap and stack don't fit into RAM */
|
||||||
|
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||||
|
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||||
|
0
|
||||||
|
/* Specify the memory areas */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 32K
|
||||||
|
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 6K
|
||||||
|
}
|
||||||
|
0
|
||||||
|
/* Define output sections */
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
/* The startup code goes first into FLASH */
|
||||||
|
.isr_vector :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.isr_vector)) /* Startup code */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
/* The program code and other data goes into FLASH */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text) /* .text sections (code) */
|
||||||
|
*(.text*) /* .text* sections (code) */
|
||||||
|
*(.glue_7) /* glue arm to thumb code */
|
||||||
|
*(.glue_7t) /* glue thumb to arm code */
|
||||||
|
*(.eh_frame)
|
||||||
|
0
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
0
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etext = .; /* define a global symbols at end of code */
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
/* Constant data goes into FLASH */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||||
|
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||||
|
.ARM : {
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
/* used by the startup to initialize data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
0
|
||||||
|
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
_sdata = .; /* create a global symbol at data start */
|
||||||
|
*(.data) /* .data sections */
|
||||||
|
*(.data*) /* .data* sections */
|
||||||
|
0
|
||||||
|
. = ALIGN(4);
|
||||||
|
_edata = .; /* define a global symbol at data end */
|
||||||
|
} >RAM AT> FLASH
|
||||||
|
0
|
||||||
|
|
||||||
|
/* Uninitialized data section */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
/* This is used by the startup in order to initialize the .bss secion */
|
||||||
|
_sbss = .; /* define a global symbol at bss start */
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
0
|
||||||
|
. = ALIGN(4);
|
||||||
|
_ebss = .; /* define a global symbol at bss end */
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} >RAM
|
||||||
|
0
|
||||||
|
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||||
|
._user_heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
PROVIDE ( end = . );
|
||||||
|
PROVIDE ( _end = . );
|
||||||
|
. = . + _Min_Heap_Size;
|
||||||
|
. = . + _Min_Stack_Size;
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >RAM
|
||||||
|
0
|
||||||
|
|
||||||
|
0
|
||||||
|
/* Remove information from the standard libraries */
|
||||||
|
/DISCARD/ :
|
||||||
|
{
|
||||||
|
libc.a ( * )
|
||||||
|
libm.a ( * )
|
||||||
|
libgcc.a ( * )
|
||||||
|
}
|
||||||
|
0
|
||||||
|
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,166 @@
|
||||||
|
/*
|
||||||
|
*****************************************************************************
|
||||||
|
**
|
||||||
|
** File : STM32F102XB_FLASH.ld
|
||||||
|
**
|
||||||
|
** Abstract : Linker script for STM32F102xB Device with
|
||||||
|
** 128KByte FLASH, 16KByte RAM
|
||||||
|
**
|
||||||
|
** Set heap size, stack size and stack location according
|
||||||
|
** to application requirements.
|
||||||
|
**
|
||||||
|
** Set memory bank area and size if external memory is used.
|
||||||
|
**
|
||||||
|
** Target : STMicroelectronics STM32
|
||||||
|
**
|
||||||
|
** Environment : Atollic TrueSTUDIO(R)
|
||||||
|
**
|
||||||
|
** Distribution: The file is distributed “as is,” without any warranty
|
||||||
|
** of any kind.
|
||||||
|
**
|
||||||
|
** (c)Copyright Atollic AB.
|
||||||
|
** You may use this file as-is or modify it according to the needs of your
|
||||||
|
** project. This file may only be built (assembled or compiled and linked)
|
||||||
|
** using the Atollic TrueSTUDIO(R) product. The use of this file together
|
||||||
|
** with other tools than Atollic TrueSTUDIO(R) is not permitted.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
*/
|
||||||
|
0
|
||||||
|
/* Entry Point */
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
0
|
||||||
|
/* Highest address of the user mode stack */
|
||||||
|
_estack = 0x20003FFF; /* end of RAM */
|
||||||
|
0
|
||||||
|
/* Generate a link error if heap and stack don't fit into RAM */
|
||||||
|
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||||
|
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||||
|
0
|
||||||
|
/* Specify the memory areas */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K
|
||||||
|
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 16K
|
||||||
|
}
|
||||||
|
0
|
||||||
|
/* Define output sections */
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
/* The startup code goes first into FLASH */
|
||||||
|
.isr_vector :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.isr_vector)) /* Startup code */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
/* The program code and other data goes into FLASH */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text) /* .text sections (code) */
|
||||||
|
*(.text*) /* .text* sections (code) */
|
||||||
|
*(.glue_7) /* glue arm to thumb code */
|
||||||
|
*(.glue_7t) /* glue thumb to arm code */
|
||||||
|
*(.eh_frame)
|
||||||
|
0
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
0
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etext = .; /* define a global symbols at end of code */
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
/* Constant data goes into FLASH */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||||
|
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||||
|
.ARM : {
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
/* used by the startup to initialize data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
0
|
||||||
|
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
_sdata = .; /* create a global symbol at data start */
|
||||||
|
*(.data) /* .data sections */
|
||||||
|
*(.data*) /* .data* sections */
|
||||||
|
0
|
||||||
|
. = ALIGN(4);
|
||||||
|
_edata = .; /* define a global symbol at data end */
|
||||||
|
} >RAM AT> FLASH
|
||||||
|
0
|
||||||
|
|
||||||
|
/* Uninitialized data section */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
/* This is used by the startup in order to initialize the .bss secion */
|
||||||
|
_sbss = .; /* define a global symbol at bss start */
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
0
|
||||||
|
. = ALIGN(4);
|
||||||
|
_ebss = .; /* define a global symbol at bss end */
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} >RAM
|
||||||
|
0
|
||||||
|
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||||
|
._user_heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
PROVIDE ( end = . );
|
||||||
|
PROVIDE ( _end = . );
|
||||||
|
. = . + _Min_Heap_Size;
|
||||||
|
. = . + _Min_Stack_Size;
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >RAM
|
||||||
|
0
|
||||||
|
|
||||||
|
0
|
||||||
|
/* Remove information from the standard libraries */
|
||||||
|
/DISCARD/ :
|
||||||
|
{
|
||||||
|
libc.a ( * )
|
||||||
|
libm.a ( * )
|
||||||
|
libgcc.a ( * )
|
||||||
|
}
|
||||||
|
0
|
||||||
|
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,166 @@
|
||||||
|
/*
|
||||||
|
*****************************************************************************
|
||||||
|
**
|
||||||
|
** File : STM32F103X6_FLASH.ld
|
||||||
|
**
|
||||||
|
** Abstract : Linker script for STM32F103x6 Device with
|
||||||
|
** 32KByte FLASH, 10KByte RAM
|
||||||
|
**
|
||||||
|
** Set heap size, stack size and stack location according
|
||||||
|
** to application requirements.
|
||||||
|
**
|
||||||
|
** Set memory bank area and size if external memory is used.
|
||||||
|
**
|
||||||
|
** Target : STMicroelectronics STM32
|
||||||
|
**
|
||||||
|
** Environment : Atollic TrueSTUDIO(R)
|
||||||
|
**
|
||||||
|
** Distribution: The file is distributed “as is,” without any warranty
|
||||||
|
** of any kind.
|
||||||
|
**
|
||||||
|
** (c)Copyright Atollic AB.
|
||||||
|
** You may use this file as-is or modify it according to the needs of your
|
||||||
|
** project. This file may only be built (assembled or compiled and linked)
|
||||||
|
** using the Atollic TrueSTUDIO(R) product. The use of this file together
|
||||||
|
** with other tools than Atollic TrueSTUDIO(R) is not permitted.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
*/
|
||||||
|
0
|
||||||
|
/* Entry Point */
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
0
|
||||||
|
/* Highest address of the user mode stack */
|
||||||
|
_estack = 0x200027FF; /* end of RAM */
|
||||||
|
0
|
||||||
|
/* Generate a link error if heap and stack don't fit into RAM */
|
||||||
|
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||||
|
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||||
|
0
|
||||||
|
/* Specify the memory areas */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 32K
|
||||||
|
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K
|
||||||
|
}
|
||||||
|
0
|
||||||
|
/* Define output sections */
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
/* The startup code goes first into FLASH */
|
||||||
|
.isr_vector :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.isr_vector)) /* Startup code */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
/* The program code and other data goes into FLASH */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text) /* .text sections (code) */
|
||||||
|
*(.text*) /* .text* sections (code) */
|
||||||
|
*(.glue_7) /* glue arm to thumb code */
|
||||||
|
*(.glue_7t) /* glue thumb to arm code */
|
||||||
|
*(.eh_frame)
|
||||||
|
0
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
0
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etext = .; /* define a global symbols at end of code */
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
/* Constant data goes into FLASH */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||||
|
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||||
|
.ARM : {
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
/* used by the startup to initialize data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
0
|
||||||
|
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
_sdata = .; /* create a global symbol at data start */
|
||||||
|
*(.data) /* .data sections */
|
||||||
|
*(.data*) /* .data* sections */
|
||||||
|
0
|
||||||
|
. = ALIGN(4);
|
||||||
|
_edata = .; /* define a global symbol at data end */
|
||||||
|
} >RAM AT> FLASH
|
||||||
|
0
|
||||||
|
|
||||||
|
/* Uninitialized data section */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
/* This is used by the startup in order to initialize the .bss secion */
|
||||||
|
_sbss = .; /* define a global symbol at bss start */
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
0
|
||||||
|
. = ALIGN(4);
|
||||||
|
_ebss = .; /* define a global symbol at bss end */
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} >RAM
|
||||||
|
0
|
||||||
|
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||||
|
._user_heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
PROVIDE ( end = . );
|
||||||
|
PROVIDE ( _end = . );
|
||||||
|
. = . + _Min_Heap_Size;
|
||||||
|
. = . + _Min_Stack_Size;
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >RAM
|
||||||
|
0
|
||||||
|
|
||||||
|
0
|
||||||
|
/* Remove information from the standard libraries */
|
||||||
|
/DISCARD/ :
|
||||||
|
{
|
||||||
|
libc.a ( * )
|
||||||
|
libm.a ( * )
|
||||||
|
libgcc.a ( * )
|
||||||
|
}
|
||||||
|
0
|
||||||
|
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,166 @@
|
||||||
|
/*
|
||||||
|
*****************************************************************************
|
||||||
|
**
|
||||||
|
** File : STM32F103XB_FLASH.ld
|
||||||
|
**
|
||||||
|
** Abstract : Linker script for STM32F103xB Device with
|
||||||
|
** 128KByte FLASH, 20KByte RAM
|
||||||
|
**
|
||||||
|
** Set heap size, stack size and stack location according
|
||||||
|
** to application requirements.
|
||||||
|
**
|
||||||
|
** Set memory bank area and size if external memory is used.
|
||||||
|
**
|
||||||
|
** Target : STMicroelectronics STM32
|
||||||
|
**
|
||||||
|
** Environment : Atollic TrueSTUDIO(R)
|
||||||
|
**
|
||||||
|
** Distribution: The file is distributed “as is,” without any warranty
|
||||||
|
** of any kind.
|
||||||
|
**
|
||||||
|
** (c)Copyright Atollic AB.
|
||||||
|
** You may use this file as-is or modify it according to the needs of your
|
||||||
|
** project. This file may only be built (assembled or compiled and linked)
|
||||||
|
** using the Atollic TrueSTUDIO(R) product. The use of this file together
|
||||||
|
** with other tools than Atollic TrueSTUDIO(R) is not permitted.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
*/
|
||||||
|
0
|
||||||
|
/* Entry Point */
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
0
|
||||||
|
/* Highest address of the user mode stack */
|
||||||
|
_estack = 0x20004FFF; /* end of RAM */
|
||||||
|
0
|
||||||
|
/* Generate a link error if heap and stack don't fit into RAM */
|
||||||
|
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||||
|
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||||
|
0
|
||||||
|
/* Specify the memory areas */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K
|
||||||
|
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K
|
||||||
|
}
|
||||||
|
0
|
||||||
|
/* Define output sections */
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
/* The startup code goes first into FLASH */
|
||||||
|
.isr_vector :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.isr_vector)) /* Startup code */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
/* The program code and other data goes into FLASH */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text) /* .text sections (code) */
|
||||||
|
*(.text*) /* .text* sections (code) */
|
||||||
|
*(.glue_7) /* glue arm to thumb code */
|
||||||
|
*(.glue_7t) /* glue thumb to arm code */
|
||||||
|
*(.eh_frame)
|
||||||
|
0
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
0
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etext = .; /* define a global symbols at end of code */
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
/* Constant data goes into FLASH */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||||
|
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||||
|
.ARM : {
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
/* used by the startup to initialize data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
0
|
||||||
|
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
_sdata = .; /* create a global symbol at data start */
|
||||||
|
*(.data) /* .data sections */
|
||||||
|
*(.data*) /* .data* sections */
|
||||||
|
0
|
||||||
|
. = ALIGN(4);
|
||||||
|
_edata = .; /* define a global symbol at data end */
|
||||||
|
} >RAM AT> FLASH
|
||||||
|
0
|
||||||
|
|
||||||
|
/* Uninitialized data section */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
/* This is used by the startup in order to initialize the .bss secion */
|
||||||
|
_sbss = .; /* define a global symbol at bss start */
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
0
|
||||||
|
. = ALIGN(4);
|
||||||
|
_ebss = .; /* define a global symbol at bss end */
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} >RAM
|
||||||
|
0
|
||||||
|
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||||
|
._user_heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
PROVIDE ( end = . );
|
||||||
|
PROVIDE ( _end = . );
|
||||||
|
. = . + _Min_Heap_Size;
|
||||||
|
. = . + _Min_Stack_Size;
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >RAM
|
||||||
|
0
|
||||||
|
|
||||||
|
0
|
||||||
|
/* Remove information from the standard libraries */
|
||||||
|
/DISCARD/ :
|
||||||
|
{
|
||||||
|
libc.a ( * )
|
||||||
|
libm.a ( * )
|
||||||
|
libgcc.a ( * )
|
||||||
|
}
|
||||||
|
0
|
||||||
|
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,166 @@
|
||||||
|
/*
|
||||||
|
*****************************************************************************
|
||||||
|
**
|
||||||
|
** File : STM32F103XE_FLASH.ld
|
||||||
|
**
|
||||||
|
** Abstract : Linker script for STM32F103xE Device with
|
||||||
|
** 512KByte FLASH, 64KByte RAM
|
||||||
|
**
|
||||||
|
** Set heap size, stack size and stack location according
|
||||||
|
** to application requirements.
|
||||||
|
**
|
||||||
|
** Set memory bank area and size if external memory is used.
|
||||||
|
**
|
||||||
|
** Target : STMicroelectronics STM32
|
||||||
|
**
|
||||||
|
** Environment : Atollic TrueSTUDIO(R)
|
||||||
|
**
|
||||||
|
** Distribution: The file is distributed “as is,” without any warranty
|
||||||
|
** of any kind.
|
||||||
|
**
|
||||||
|
** (c)Copyright Atollic AB.
|
||||||
|
** You may use this file as-is or modify it according to the needs of your
|
||||||
|
** project. This file may only be built (assembled or compiled and linked)
|
||||||
|
** using the Atollic TrueSTUDIO(R) product. The use of this file together
|
||||||
|
** with other tools than Atollic TrueSTUDIO(R) is not permitted.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
*/
|
||||||
|
0
|
||||||
|
/* Entry Point */
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
0
|
||||||
|
/* Highest address of the user mode stack */
|
||||||
|
_estack = 0x2000FFFF; /* end of RAM */
|
||||||
|
0
|
||||||
|
/* Generate a link error if heap and stack don't fit into RAM */
|
||||||
|
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||||
|
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||||
|
0
|
||||||
|
/* Specify the memory areas */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K
|
||||||
|
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K
|
||||||
|
}
|
||||||
|
0
|
||||||
|
/* Define output sections */
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
/* The startup code goes first into FLASH */
|
||||||
|
.isr_vector :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.isr_vector)) /* Startup code */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
/* The program code and other data goes into FLASH */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text) /* .text sections (code) */
|
||||||
|
*(.text*) /* .text* sections (code) */
|
||||||
|
*(.glue_7) /* glue arm to thumb code */
|
||||||
|
*(.glue_7t) /* glue thumb to arm code */
|
||||||
|
*(.eh_frame)
|
||||||
|
0
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
0
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etext = .; /* define a global symbols at end of code */
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
/* Constant data goes into FLASH */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||||
|
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||||
|
.ARM : {
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
/* used by the startup to initialize data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
0
|
||||||
|
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
_sdata = .; /* create a global symbol at data start */
|
||||||
|
*(.data) /* .data sections */
|
||||||
|
*(.data*) /* .data* sections */
|
||||||
|
0
|
||||||
|
. = ALIGN(4);
|
||||||
|
_edata = .; /* define a global symbol at data end */
|
||||||
|
} >RAM AT> FLASH
|
||||||
|
0
|
||||||
|
|
||||||
|
/* Uninitialized data section */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
/* This is used by the startup in order to initialize the .bss secion */
|
||||||
|
_sbss = .; /* define a global symbol at bss start */
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
0
|
||||||
|
. = ALIGN(4);
|
||||||
|
_ebss = .; /* define a global symbol at bss end */
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} >RAM
|
||||||
|
0
|
||||||
|
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||||
|
._user_heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
PROVIDE ( end = . );
|
||||||
|
PROVIDE ( _end = . );
|
||||||
|
. = . + _Min_Heap_Size;
|
||||||
|
. = . + _Min_Stack_Size;
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >RAM
|
||||||
|
0
|
||||||
|
|
||||||
|
0
|
||||||
|
/* Remove information from the standard libraries */
|
||||||
|
/DISCARD/ :
|
||||||
|
{
|
||||||
|
libc.a ( * )
|
||||||
|
libm.a ( * )
|
||||||
|
libgcc.a ( * )
|
||||||
|
}
|
||||||
|
0
|
||||||
|
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,166 @@
|
||||||
|
/*
|
||||||
|
*****************************************************************************
|
||||||
|
**
|
||||||
|
** File : STM32F103XG_FLASH.ld
|
||||||
|
**
|
||||||
|
** Abstract : Linker script for STM32F103xG Device with
|
||||||
|
** 1000KByte FLASH, 96KByte RAM
|
||||||
|
**
|
||||||
|
** Set heap size, stack size and stack location according
|
||||||
|
** to application requirements.
|
||||||
|
**
|
||||||
|
** Set memory bank area and size if external memory is used.
|
||||||
|
**
|
||||||
|
** Target : STMicroelectronics STM32
|
||||||
|
**
|
||||||
|
** Environment : Atollic TrueSTUDIO(R)
|
||||||
|
**
|
||||||
|
** Distribution: The file is distributed “as is,” without any warranty
|
||||||
|
** of any kind.
|
||||||
|
**
|
||||||
|
** (c)Copyright Atollic AB.
|
||||||
|
** You may use this file as-is or modify it according to the needs of your
|
||||||
|
** project. This file may only be built (assembled or compiled and linked)
|
||||||
|
** using the Atollic TrueSTUDIO(R) product. The use of this file together
|
||||||
|
** with other tools than Atollic TrueSTUDIO(R) is not permitted.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
*/
|
||||||
|
0
|
||||||
|
/* Entry Point */
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
0
|
||||||
|
/* Highest address of the user mode stack */
|
||||||
|
_estack = 0x20017FFF; /* end of RAM */
|
||||||
|
0
|
||||||
|
/* Generate a link error if heap and stack don't fit into RAM */
|
||||||
|
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||||
|
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||||
|
0
|
||||||
|
/* Specify the memory areas */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1000K
|
||||||
|
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 96K
|
||||||
|
}
|
||||||
|
0
|
||||||
|
/* Define output sections */
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
/* The startup code goes first into FLASH */
|
||||||
|
.isr_vector :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.isr_vector)) /* Startup code */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
/* The program code and other data goes into FLASH */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text) /* .text sections (code) */
|
||||||
|
*(.text*) /* .text* sections (code) */
|
||||||
|
*(.glue_7) /* glue arm to thumb code */
|
||||||
|
*(.glue_7t) /* glue thumb to arm code */
|
||||||
|
*(.eh_frame)
|
||||||
|
0
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
0
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etext = .; /* define a global symbols at end of code */
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
/* Constant data goes into FLASH */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||||
|
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||||
|
.ARM : {
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
/* used by the startup to initialize data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
0
|
||||||
|
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
_sdata = .; /* create a global symbol at data start */
|
||||||
|
*(.data) /* .data sections */
|
||||||
|
*(.data*) /* .data* sections */
|
||||||
|
0
|
||||||
|
. = ALIGN(4);
|
||||||
|
_edata = .; /* define a global symbol at data end */
|
||||||
|
} >RAM AT> FLASH
|
||||||
|
0
|
||||||
|
|
||||||
|
/* Uninitialized data section */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
/* This is used by the startup in order to initialize the .bss secion */
|
||||||
|
_sbss = .; /* define a global symbol at bss start */
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
0
|
||||||
|
. = ALIGN(4);
|
||||||
|
_ebss = .; /* define a global symbol at bss end */
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} >RAM
|
||||||
|
0
|
||||||
|
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||||
|
._user_heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
PROVIDE ( end = . );
|
||||||
|
PROVIDE ( _end = . );
|
||||||
|
. = . + _Min_Heap_Size;
|
||||||
|
. = . + _Min_Stack_Size;
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >RAM
|
||||||
|
0
|
||||||
|
|
||||||
|
0
|
||||||
|
/* Remove information from the standard libraries */
|
||||||
|
/DISCARD/ :
|
||||||
|
{
|
||||||
|
libc.a ( * )
|
||||||
|
libm.a ( * )
|
||||||
|
libgcc.a ( * )
|
||||||
|
}
|
||||||
|
0
|
||||||
|
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,166 @@
|
||||||
|
/*
|
||||||
|
*****************************************************************************
|
||||||
|
**
|
||||||
|
** File : STM32F105XC_FLASH.ld
|
||||||
|
**
|
||||||
|
** Abstract : Linker script for STM32F105xC Device with
|
||||||
|
** 256KByte FLASH, 64KByte RAM
|
||||||
|
**
|
||||||
|
** Set heap size, stack size and stack location according
|
||||||
|
** to application requirements.
|
||||||
|
**
|
||||||
|
** Set memory bank area and size if external memory is used.
|
||||||
|
**
|
||||||
|
** Target : STMicroelectronics STM32
|
||||||
|
**
|
||||||
|
** Environment : Atollic TrueSTUDIO(R)
|
||||||
|
**
|
||||||
|
** Distribution: The file is distributed “as is,” without any warranty
|
||||||
|
** of any kind.
|
||||||
|
**
|
||||||
|
** (c)Copyright Atollic AB.
|
||||||
|
** You may use this file as-is or modify it according to the needs of your
|
||||||
|
** project. This file may only be built (assembled or compiled and linked)
|
||||||
|
** using the Atollic TrueSTUDIO(R) product. The use of this file together
|
||||||
|
** with other tools than Atollic TrueSTUDIO(R) is not permitted.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
*/
|
||||||
|
0
|
||||||
|
/* Entry Point */
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
0
|
||||||
|
/* Highest address of the user mode stack */
|
||||||
|
_estack = 0x2000FFFF; /* end of RAM */
|
||||||
|
0
|
||||||
|
/* Generate a link error if heap and stack don't fit into RAM */
|
||||||
|
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||||
|
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||||
|
0
|
||||||
|
/* Specify the memory areas */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256K
|
||||||
|
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K
|
||||||
|
}
|
||||||
|
0
|
||||||
|
/* Define output sections */
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
/* The startup code goes first into FLASH */
|
||||||
|
.isr_vector :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.isr_vector)) /* Startup code */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
/* The program code and other data goes into FLASH */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text) /* .text sections (code) */
|
||||||
|
*(.text*) /* .text* sections (code) */
|
||||||
|
*(.glue_7) /* glue arm to thumb code */
|
||||||
|
*(.glue_7t) /* glue thumb to arm code */
|
||||||
|
*(.eh_frame)
|
||||||
|
0
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
0
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etext = .; /* define a global symbols at end of code */
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
/* Constant data goes into FLASH */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||||
|
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||||
|
.ARM : {
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
/* used by the startup to initialize data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
0
|
||||||
|
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
_sdata = .; /* create a global symbol at data start */
|
||||||
|
*(.data) /* .data sections */
|
||||||
|
*(.data*) /* .data* sections */
|
||||||
|
0
|
||||||
|
. = ALIGN(4);
|
||||||
|
_edata = .; /* define a global symbol at data end */
|
||||||
|
} >RAM AT> FLASH
|
||||||
|
0
|
||||||
|
|
||||||
|
/* Uninitialized data section */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
/* This is used by the startup in order to initialize the .bss secion */
|
||||||
|
_sbss = .; /* define a global symbol at bss start */
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
0
|
||||||
|
. = ALIGN(4);
|
||||||
|
_ebss = .; /* define a global symbol at bss end */
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} >RAM
|
||||||
|
0
|
||||||
|
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||||
|
._user_heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
PROVIDE ( end = . );
|
||||||
|
PROVIDE ( _end = . );
|
||||||
|
. = . + _Min_Heap_Size;
|
||||||
|
. = . + _Min_Stack_Size;
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >RAM
|
||||||
|
0
|
||||||
|
|
||||||
|
0
|
||||||
|
/* Remove information from the standard libraries */
|
||||||
|
/DISCARD/ :
|
||||||
|
{
|
||||||
|
libc.a ( * )
|
||||||
|
libm.a ( * )
|
||||||
|
libgcc.a ( * )
|
||||||
|
}
|
||||||
|
0
|
||||||
|
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,166 @@
|
||||||
|
/*
|
||||||
|
*****************************************************************************
|
||||||
|
**
|
||||||
|
** File : STM32F107XC_FLASH.ld
|
||||||
|
**
|
||||||
|
** Abstract : Linker script for STM32F107xC Device with
|
||||||
|
** 256KByte FLASH, 64KByte RAM
|
||||||
|
**
|
||||||
|
** Set heap size, stack size and stack location according
|
||||||
|
** to application requirements.
|
||||||
|
**
|
||||||
|
** Set memory bank area and size if external memory is used.
|
||||||
|
**
|
||||||
|
** Target : STMicroelectronics STM32
|
||||||
|
**
|
||||||
|
** Environment : Atollic TrueSTUDIO(R)
|
||||||
|
**
|
||||||
|
** Distribution: The file is distributed “as is,” without any warranty
|
||||||
|
** of any kind.
|
||||||
|
**
|
||||||
|
** (c)Copyright Atollic AB.
|
||||||
|
** You may use this file as-is or modify it according to the needs of your
|
||||||
|
** project. This file may only be built (assembled or compiled and linked)
|
||||||
|
** using the Atollic TrueSTUDIO(R) product. The use of this file together
|
||||||
|
** with other tools than Atollic TrueSTUDIO(R) is not permitted.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
*/
|
||||||
|
0
|
||||||
|
/* Entry Point */
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
0
|
||||||
|
/* Highest address of the user mode stack */
|
||||||
|
_estack = 0x2000FFFF; /* end of RAM */
|
||||||
|
0
|
||||||
|
/* Generate a link error if heap and stack don't fit into RAM */
|
||||||
|
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||||
|
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||||
|
0
|
||||||
|
/* Specify the memory areas */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256K
|
||||||
|
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K
|
||||||
|
}
|
||||||
|
0
|
||||||
|
/* Define output sections */
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
/* The startup code goes first into FLASH */
|
||||||
|
.isr_vector :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.isr_vector)) /* Startup code */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
/* The program code and other data goes into FLASH */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text) /* .text sections (code) */
|
||||||
|
*(.text*) /* .text* sections (code) */
|
||||||
|
*(.glue_7) /* glue arm to thumb code */
|
||||||
|
*(.glue_7t) /* glue thumb to arm code */
|
||||||
|
*(.eh_frame)
|
||||||
|
0
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
0
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etext = .; /* define a global symbols at end of code */
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
/* Constant data goes into FLASH */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||||
|
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||||
|
.ARM : {
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
0
|
||||||
|
/* used by the startup to initialize data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
0
|
||||||
|
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
_sdata = .; /* create a global symbol at data start */
|
||||||
|
*(.data) /* .data sections */
|
||||||
|
*(.data*) /* .data* sections */
|
||||||
|
0
|
||||||
|
. = ALIGN(4);
|
||||||
|
_edata = .; /* define a global symbol at data end */
|
||||||
|
} >RAM AT> FLASH
|
||||||
|
0
|
||||||
|
|
||||||
|
/* Uninitialized data section */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
/* This is used by the startup in order to initialize the .bss secion */
|
||||||
|
_sbss = .; /* define a global symbol at bss start */
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
0
|
||||||
|
. = ALIGN(4);
|
||||||
|
_ebss = .; /* define a global symbol at bss end */
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} >RAM
|
||||||
|
0
|
||||||
|
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||||
|
._user_heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
PROVIDE ( end = . );
|
||||||
|
PROVIDE ( _end = . );
|
||||||
|
. = . + _Min_Heap_Size;
|
||||||
|
. = . + _Min_Stack_Size;
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >RAM
|
||||||
|
0
|
||||||
|
|
||||||
|
0
|
||||||
|
/* Remove information from the standard libraries */
|
||||||
|
/DISCARD/ :
|
||||||
|
{
|
||||||
|
libc.a ( * )
|
||||||
|
libm.a ( * )
|
||||||
|
libgcc.a ( * )
|
||||||
|
}
|
||||||
|
0
|
||||||
|
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,422 @@
|
||||||
|
/**
|
||||||
|
*************** (C) COPYRIGHT 2017 STMicroelectronics ************************
|
||||||
|
* @file startup_stm32f100xb.s
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V4.2.0
|
||||||
|
* @date 31-March-2017
|
||||||
|
* @brief STM32F100xB Devices vector table for Atollic toolchain.
|
||||||
|
* This module performs:
|
||||||
|
* - Set the initial SP
|
||||||
|
* - Set the initial PC == Reset_Handler,
|
||||||
|
* - Set the vector table entries with the exceptions ISR address
|
||||||
|
* - Configure the clock system
|
||||||
|
* - Branches to main in the C library (which eventually
|
||||||
|
* calls main()).
|
||||||
|
* After Reset the Cortex-M3 processor is in Thread mode,
|
||||||
|
* priority is Privileged, and the Stack is set to Main.
|
||||||
|
******************************************************************************
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
.syntax unified
|
||||||
|
.cpu cortex-m3
|
||||||
|
.fpu softvfp
|
||||||
|
.thumb
|
||||||
|
|
||||||
|
.global g_pfnVectors
|
||||||
|
.global Default_Handler
|
||||||
|
|
||||||
|
/* start address for the initialization values of the .data section.
|
||||||
|
defined in linker script */
|
||||||
|
.word _sidata
|
||||||
|
/* start address for the .data section. defined in linker script */
|
||||||
|
.word _sdata
|
||||||
|
/* end address for the .data section. defined in linker script */
|
||||||
|
.word _edata
|
||||||
|
/* start address for the .bss section. defined in linker script */
|
||||||
|
.word _sbss
|
||||||
|
/* end address for the .bss section. defined in linker script */
|
||||||
|
.word _ebss
|
||||||
|
|
||||||
|
.equ BootRAM, 0xF108F85F
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor first
|
||||||
|
* starts execution following a reset event. Only the absolutely
|
||||||
|
* necessary set is performed, after which the application
|
||||||
|
* supplied main() routine is called.
|
||||||
|
* @param None
|
||||||
|
* @retval : None
|
||||||
|
*/
|
||||||
|
|
||||||
|
.section .text.Reset_Handler
|
||||||
|
.weak Reset_Handler
|
||||||
|
.type Reset_Handler, %function
|
||||||
|
Reset_Handler:
|
||||||
|
|
||||||
|
/* Copy the data segment initializers from flash to SRAM */
|
||||||
|
movs r1, #0
|
||||||
|
b LoopCopyDataInit
|
||||||
|
|
||||||
|
CopyDataInit:
|
||||||
|
ldr r3, =_sidata
|
||||||
|
ldr r3, [r3, r1]
|
||||||
|
str r3, [r0, r1]
|
||||||
|
adds r1, r1, #4
|
||||||
|
|
||||||
|
LoopCopyDataInit:
|
||||||
|
ldr r0, =_sdata
|
||||||
|
ldr r3, =_edata
|
||||||
|
adds r2, r0, r1
|
||||||
|
cmp r2, r3
|
||||||
|
bcc CopyDataInit
|
||||||
|
ldr r2, =_sbss
|
||||||
|
b LoopFillZerobss
|
||||||
|
/* Zero fill the bss segment. */
|
||||||
|
FillZerobss:
|
||||||
|
movs r3, #0
|
||||||
|
str r3, [r2], #4
|
||||||
|
|
||||||
|
LoopFillZerobss:
|
||||||
|
ldr r3, = _ebss
|
||||||
|
cmp r2, r3
|
||||||
|
bcc FillZerobss
|
||||||
|
|
||||||
|
/* Call the clock system intitialization function.*/
|
||||||
|
bl SystemInit
|
||||||
|
/* Call static constructors */
|
||||||
|
/* bl __libc_init_array */
|
||||||
|
/* Call the application's entry point.*/
|
||||||
|
bl entry
|
||||||
|
bx lr
|
||||||
|
.size Reset_Handler, .-Reset_Handler
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor receives an
|
||||||
|
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||||
|
* the system state for examination by a debugger.
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
* @retval : None
|
||||||
|
*/
|
||||||
|
.section .text.Default_Handler,"ax",%progbits
|
||||||
|
Default_Handler:
|
||||||
|
Infinite_Loop:
|
||||||
|
b Infinite_Loop
|
||||||
|
.size Default_Handler, .-Default_Handler
|
||||||
|
/******************************************************************************
|
||||||
|
*
|
||||||
|
* The minimal vector table for a Cortex M3. Note that the proper constructs
|
||||||
|
* must be placed on this to ensure that it ends up at physical address
|
||||||
|
* 0x0000.0000.
|
||||||
|
*
|
||||||
|
******************************************************************************/
|
||||||
|
.section .isr_vector,"a",%progbits
|
||||||
|
.type g_pfnVectors, %object
|
||||||
|
.size g_pfnVectors, .-g_pfnVectors
|
||||||
|
|
||||||
|
|
||||||
|
g_pfnVectors:
|
||||||
|
.word _estack
|
||||||
|
.word Reset_Handler
|
||||||
|
.word NMI_Handler
|
||||||
|
.word HardFault_Handler
|
||||||
|
.word MemManage_Handler
|
||||||
|
.word BusFault_Handler
|
||||||
|
.word UsageFault_Handler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word SVC_Handler
|
||||||
|
.word DebugMon_Handler
|
||||||
|
.word 0
|
||||||
|
.word PendSV_Handler
|
||||||
|
.word SysTick_Handler
|
||||||
|
.word WWDG_IRQHandler
|
||||||
|
.word PVD_IRQHandler
|
||||||
|
.word TAMPER_IRQHandler
|
||||||
|
.word RTC_IRQHandler
|
||||||
|
.word FLASH_IRQHandler
|
||||||
|
.word RCC_IRQHandler
|
||||||
|
.word EXTI0_IRQHandler
|
||||||
|
.word EXTI1_IRQHandler
|
||||||
|
.word EXTI2_IRQHandler
|
||||||
|
.word EXTI3_IRQHandler
|
||||||
|
.word EXTI4_IRQHandler
|
||||||
|
.word DMA1_Channel1_IRQHandler
|
||||||
|
.word DMA1_Channel2_IRQHandler
|
||||||
|
.word DMA1_Channel3_IRQHandler
|
||||||
|
.word DMA1_Channel4_IRQHandler
|
||||||
|
.word DMA1_Channel5_IRQHandler
|
||||||
|
.word DMA1_Channel6_IRQHandler
|
||||||
|
.word DMA1_Channel7_IRQHandler
|
||||||
|
.word ADC1_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word EXTI9_5_IRQHandler
|
||||||
|
.word TIM1_BRK_TIM15_IRQHandler
|
||||||
|
.word TIM1_UP_TIM16_IRQHandler
|
||||||
|
.word TIM1_TRG_COM_TIM17_IRQHandler
|
||||||
|
.word TIM1_CC_IRQHandler
|
||||||
|
.word TIM2_IRQHandler
|
||||||
|
.word TIM3_IRQHandler
|
||||||
|
.word TIM4_IRQHandler
|
||||||
|
.word I2C1_EV_IRQHandler
|
||||||
|
.word I2C1_ER_IRQHandler
|
||||||
|
.word I2C2_EV_IRQHandler
|
||||||
|
.word I2C2_ER_IRQHandler
|
||||||
|
.word SPI1_IRQHandler
|
||||||
|
.word SPI2_IRQHandler
|
||||||
|
.word USART1_IRQHandler
|
||||||
|
.word USART2_IRQHandler
|
||||||
|
.word USART3_IRQHandler
|
||||||
|
.word EXTI15_10_IRQHandler
|
||||||
|
.word RTC_Alarm_IRQHandler
|
||||||
|
.word CEC_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word TIM6_DAC_IRQHandler
|
||||||
|
.word TIM7_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word BootRAM /* @0x01CC. This is for boot in RAM mode for
|
||||||
|
STM32F10xB Value Line devices. */
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
*
|
||||||
|
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||||
|
* As they are weak aliases, any function with the same name will override
|
||||||
|
* this definition.
|
||||||
|
*
|
||||||
|
*******************************************************************************/
|
||||||
|
|
||||||
|
|
||||||
|
.weak NMI_Handler
|
||||||
|
.thumb_set NMI_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak HardFault_Handler
|
||||||
|
.thumb_set HardFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak MemManage_Handler
|
||||||
|
.thumb_set MemManage_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak BusFault_Handler
|
||||||
|
.thumb_set BusFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak UsageFault_Handler
|
||||||
|
.thumb_set UsageFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SVC_Handler
|
||||||
|
.thumb_set SVC_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak DebugMon_Handler
|
||||||
|
.thumb_set DebugMon_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak PendSV_Handler
|
||||||
|
.thumb_set PendSV_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SysTick_Handler
|
||||||
|
.thumb_set SysTick_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak WWDG_IRQHandler
|
||||||
|
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak PVD_IRQHandler
|
||||||
|
.thumb_set PVD_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TAMPER_IRQHandler
|
||||||
|
.thumb_set TAMPER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_IRQHandler
|
||||||
|
.thumb_set RTC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FLASH_IRQHandler
|
||||||
|
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RCC_IRQHandler
|
||||||
|
.thumb_set RCC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI0_IRQHandler
|
||||||
|
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI1_IRQHandler
|
||||||
|
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI2_IRQHandler
|
||||||
|
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI3_IRQHandler
|
||||||
|
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI4_IRQHandler
|
||||||
|
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel1_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel2_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel3_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel4_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel5_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel6_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel7_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ADC1_IRQHandler
|
||||||
|
.thumb_set ADC1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI9_5_IRQHandler
|
||||||
|
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_BRK_TIM15_IRQHandler
|
||||||
|
.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_UP_TIM16_IRQHandler
|
||||||
|
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_TRG_COM_TIM17_IRQHandler
|
||||||
|
.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_CC_IRQHandler
|
||||||
|
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM2_IRQHandler
|
||||||
|
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM3_IRQHandler
|
||||||
|
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM4_IRQHandler
|
||||||
|
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_EV_IRQHandler
|
||||||
|
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_ER_IRQHandler
|
||||||
|
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_EV_IRQHandler
|
||||||
|
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_ER_IRQHandler
|
||||||
|
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI1_IRQHandler
|
||||||
|
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI1_IRQHandler
|
||||||
|
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART1_IRQHandler
|
||||||
|
.thumb_set USART1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART2_IRQHandler
|
||||||
|
.thumb_set USART2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART3_IRQHandler
|
||||||
|
.thumb_set USART3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI15_10_IRQHandler
|
||||||
|
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_Alarm_IRQHandler
|
||||||
|
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CEC_IRQHandler
|
||||||
|
.thumb_set CEC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM6_DAC_IRQHandler
|
||||||
|
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM7_IRQHandler
|
||||||
|
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
||||||
|
|
@ -0,0 +1,464 @@
|
||||||
|
/**
|
||||||
|
*************** (C) COPYRIGHT 2017 STMicroelectronics ************************
|
||||||
|
* @file startup_stm32f100xe.s
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V4.2.0
|
||||||
|
* @date 31-March-2017
|
||||||
|
* @brief STM32F100xE Devices vector table for Atollic toolchain.
|
||||||
|
* This module performs:
|
||||||
|
* - Set the initial SP
|
||||||
|
* - Set the initial PC == Reset_Handler,
|
||||||
|
* - Set the vector table entries with the exceptions ISR address
|
||||||
|
* - Configure the clock system
|
||||||
|
* - Branches to main in the C library (which eventually
|
||||||
|
* calls main()).
|
||||||
|
* After Reset the Cortex-M3 processor is in Thread mode,
|
||||||
|
* priority is Privileged, and the Stack is set to Main.
|
||||||
|
******************************************************************************
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
.syntax unified
|
||||||
|
.cpu cortex-m3
|
||||||
|
.fpu softvfp
|
||||||
|
.thumb
|
||||||
|
|
||||||
|
.global g_pfnVectors
|
||||||
|
.global Default_Handler
|
||||||
|
|
||||||
|
/* start address for the initialization values of the .data section.
|
||||||
|
defined in linker script */
|
||||||
|
.word _sidata
|
||||||
|
/* start address for the .data section. defined in linker script */
|
||||||
|
.word _sdata
|
||||||
|
/* end address for the .data section. defined in linker script */
|
||||||
|
.word _edata
|
||||||
|
/* start address for the .bss section. defined in linker script */
|
||||||
|
.word _sbss
|
||||||
|
/* end address for the .bss section. defined in linker script */
|
||||||
|
.word _ebss
|
||||||
|
|
||||||
|
.equ BootRAM, 0xF108F85F
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor first
|
||||||
|
* starts execution following a reset event. Only the absolutely
|
||||||
|
* necessary set is performed, after which the application
|
||||||
|
* supplied main() routine is called.
|
||||||
|
* @param None
|
||||||
|
* @retval : None
|
||||||
|
*/
|
||||||
|
|
||||||
|
.section .text.Reset_Handler
|
||||||
|
.weak Reset_Handler
|
||||||
|
.type Reset_Handler, %function
|
||||||
|
Reset_Handler:
|
||||||
|
|
||||||
|
/* Copy the data segment initializers from flash to SRAM */
|
||||||
|
movs r1, #0
|
||||||
|
b LoopCopyDataInit
|
||||||
|
|
||||||
|
CopyDataInit:
|
||||||
|
ldr r3, =_sidata
|
||||||
|
ldr r3, [r3, r1]
|
||||||
|
str r3, [r0, r1]
|
||||||
|
adds r1, r1, #4
|
||||||
|
|
||||||
|
LoopCopyDataInit:
|
||||||
|
ldr r0, =_sdata
|
||||||
|
ldr r3, =_edata
|
||||||
|
adds r2, r0, r1
|
||||||
|
cmp r2, r3
|
||||||
|
bcc CopyDataInit
|
||||||
|
ldr r2, =_sbss
|
||||||
|
b LoopFillZerobss
|
||||||
|
/* Zero fill the bss segment. */
|
||||||
|
FillZerobss:
|
||||||
|
movs r3, #0
|
||||||
|
str r3, [r2], #4
|
||||||
|
|
||||||
|
LoopFillZerobss:
|
||||||
|
ldr r3, = _ebss
|
||||||
|
cmp r2, r3
|
||||||
|
bcc FillZerobss
|
||||||
|
|
||||||
|
/* Call the clock system intitialization function.*/
|
||||||
|
bl SystemInit
|
||||||
|
/* Call static constructors */
|
||||||
|
/* bl __libc_init_array */
|
||||||
|
/* Call the application's entry point.*/
|
||||||
|
bl entry
|
||||||
|
bx lr
|
||||||
|
.size Reset_Handler, .-Reset_Handler
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor receives an
|
||||||
|
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||||
|
* the system state for examination by a debugger.
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
* @retval : None
|
||||||
|
*/
|
||||||
|
.section .text.Default_Handler,"ax",%progbits
|
||||||
|
Default_Handler:
|
||||||
|
Infinite_Loop:
|
||||||
|
b Infinite_Loop
|
||||||
|
.size Default_Handler, .-Default_Handler
|
||||||
|
/******************************************************************************
|
||||||
|
*
|
||||||
|
* The minimal vector table for a Cortex M3. Note that the proper constructs
|
||||||
|
* must be placed on this to ensure that it ends up at physical address
|
||||||
|
* 0x0000.0000.
|
||||||
|
*
|
||||||
|
******************************************************************************/
|
||||||
|
.section .isr_vector,"a",%progbits
|
||||||
|
.type g_pfnVectors, %object
|
||||||
|
.size g_pfnVectors, .-g_pfnVectors
|
||||||
|
|
||||||
|
|
||||||
|
g_pfnVectors:
|
||||||
|
|
||||||
|
.word _estack
|
||||||
|
.word Reset_Handler
|
||||||
|
.word NMI_Handler
|
||||||
|
.word HardFault_Handler
|
||||||
|
.word MemManage_Handler
|
||||||
|
.word BusFault_Handler
|
||||||
|
.word UsageFault_Handler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word SVC_Handler
|
||||||
|
.word DebugMon_Handler
|
||||||
|
.word 0
|
||||||
|
.word PendSV_Handler
|
||||||
|
.word SysTick_Handler
|
||||||
|
.word WWDG_IRQHandler
|
||||||
|
.word PVD_IRQHandler
|
||||||
|
.word TAMPER_IRQHandler
|
||||||
|
.word RTC_IRQHandler
|
||||||
|
.word FLASH_IRQHandler
|
||||||
|
.word RCC_IRQHandler
|
||||||
|
.word EXTI0_IRQHandler
|
||||||
|
.word EXTI1_IRQHandler
|
||||||
|
.word EXTI2_IRQHandler
|
||||||
|
.word EXTI3_IRQHandler
|
||||||
|
.word EXTI4_IRQHandler
|
||||||
|
.word DMA1_Channel1_IRQHandler
|
||||||
|
.word DMA1_Channel2_IRQHandler
|
||||||
|
.word DMA1_Channel3_IRQHandler
|
||||||
|
.word DMA1_Channel4_IRQHandler
|
||||||
|
.word DMA1_Channel5_IRQHandler
|
||||||
|
.word DMA1_Channel6_IRQHandler
|
||||||
|
.word DMA1_Channel7_IRQHandler
|
||||||
|
.word ADC1_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word EXTI9_5_IRQHandler
|
||||||
|
.word TIM1_BRK_TIM15_IRQHandler
|
||||||
|
.word TIM1_UP_TIM16_IRQHandler
|
||||||
|
.word TIM1_TRG_COM_TIM17_IRQHandler
|
||||||
|
.word TIM1_CC_IRQHandler
|
||||||
|
.word TIM2_IRQHandler
|
||||||
|
.word TIM3_IRQHandler
|
||||||
|
.word TIM4_IRQHandler
|
||||||
|
.word I2C1_EV_IRQHandler
|
||||||
|
.word I2C1_ER_IRQHandler
|
||||||
|
.word I2C2_EV_IRQHandler
|
||||||
|
.word I2C2_ER_IRQHandler
|
||||||
|
.word SPI1_IRQHandler
|
||||||
|
.word SPI2_IRQHandler
|
||||||
|
.word USART1_IRQHandler
|
||||||
|
.word USART2_IRQHandler
|
||||||
|
.word USART3_IRQHandler
|
||||||
|
.word EXTI15_10_IRQHandler
|
||||||
|
.word RTC_Alarm_IRQHandler
|
||||||
|
.word CEC_IRQHandler
|
||||||
|
.word TIM12_IRQHandler
|
||||||
|
.word TIM13_IRQHandler
|
||||||
|
.word TIM14_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word TIM5_IRQHandler
|
||||||
|
.word SPI3_IRQHandler
|
||||||
|
.word UART4_IRQHandler
|
||||||
|
.word UART5_IRQHandler
|
||||||
|
.word TIM6_DAC_IRQHandler
|
||||||
|
.word TIM7_IRQHandler
|
||||||
|
.word DMA2_Channel1_IRQHandler
|
||||||
|
.word DMA2_Channel2_IRQHandler
|
||||||
|
.word DMA2_Channel3_IRQHandler
|
||||||
|
.word DMA2_Channel4_5_IRQHandler
|
||||||
|
.word DMA2_Channel5_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word BootRAM /* @0x1E0. This is for boot in RAM mode for
|
||||||
|
STM32F10x High Density Value line devices. */
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
*
|
||||||
|
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||||
|
* As they are weak aliases, any function with the same name will override
|
||||||
|
* this definition.
|
||||||
|
*
|
||||||
|
*******************************************************************************/
|
||||||
|
|
||||||
|
|
||||||
|
.weak NMI_Handler
|
||||||
|
.thumb_set NMI_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak HardFault_Handler
|
||||||
|
.thumb_set HardFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak MemManage_Handler
|
||||||
|
.thumb_set MemManage_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak BusFault_Handler
|
||||||
|
.thumb_set BusFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak UsageFault_Handler
|
||||||
|
.thumb_set UsageFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SVC_Handler
|
||||||
|
.thumb_set SVC_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak DebugMon_Handler
|
||||||
|
.thumb_set DebugMon_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak PendSV_Handler
|
||||||
|
.thumb_set PendSV_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SysTick_Handler
|
||||||
|
.thumb_set SysTick_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak WWDG_IRQHandler
|
||||||
|
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak PVD_IRQHandler
|
||||||
|
.thumb_set PVD_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TAMPER_IRQHandler
|
||||||
|
.thumb_set TAMPER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_IRQHandler
|
||||||
|
.thumb_set RTC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FLASH_IRQHandler
|
||||||
|
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RCC_IRQHandler
|
||||||
|
.thumb_set RCC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI0_IRQHandler
|
||||||
|
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI1_IRQHandler
|
||||||
|
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI2_IRQHandler
|
||||||
|
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI3_IRQHandler
|
||||||
|
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI4_IRQHandler
|
||||||
|
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel1_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel2_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel3_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel4_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel5_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel6_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel7_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ADC1_IRQHandler
|
||||||
|
.thumb_set ADC1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI9_5_IRQHandler
|
||||||
|
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_BRK_TIM15_IRQHandler
|
||||||
|
.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_UP_TIM16_IRQHandler
|
||||||
|
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_TRG_COM_TIM17_IRQHandler
|
||||||
|
.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_CC_IRQHandler
|
||||||
|
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM2_IRQHandler
|
||||||
|
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM3_IRQHandler
|
||||||
|
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM4_IRQHandler
|
||||||
|
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_EV_IRQHandler
|
||||||
|
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_ER_IRQHandler
|
||||||
|
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_EV_IRQHandler
|
||||||
|
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_ER_IRQHandler
|
||||||
|
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI1_IRQHandler
|
||||||
|
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI2_IRQHandler
|
||||||
|
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART1_IRQHandler
|
||||||
|
.thumb_set USART1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART2_IRQHandler
|
||||||
|
.thumb_set USART2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART3_IRQHandler
|
||||||
|
.thumb_set USART3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI15_10_IRQHandler
|
||||||
|
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_Alarm_IRQHandler
|
||||||
|
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CEC_IRQHandler
|
||||||
|
.thumb_set CEC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM12_IRQHandler
|
||||||
|
.thumb_set TIM12_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM13_IRQHandler
|
||||||
|
.thumb_set TIM13_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM14_IRQHandler
|
||||||
|
.thumb_set TIM14_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM5_IRQHandler
|
||||||
|
.thumb_set TIM5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI3_IRQHandler
|
||||||
|
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART4_IRQHandler
|
||||||
|
.thumb_set UART4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART5_IRQHandler
|
||||||
|
.thumb_set UART5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM6_DAC_IRQHandler
|
||||||
|
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM7_IRQHandler
|
||||||
|
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Channel1_IRQHandler
|
||||||
|
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Channel2_IRQHandler
|
||||||
|
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Channel3_IRQHandler
|
||||||
|
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Channel4_5_IRQHandler
|
||||||
|
.thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Channel5_IRQHandler
|
||||||
|
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
||||||
|
|
@ -0,0 +1,337 @@
|
||||||
|
/**
|
||||||
|
*************** (C) COPYRIGHT 2017 STMicroelectronics ************************
|
||||||
|
* @file startup_stm32f101x6.s
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V4.2.0
|
||||||
|
* @date 31-March-2017
|
||||||
|
* @brief STM32F101x6 Devices vector table for Atollic toolchain.
|
||||||
|
* This module performs:
|
||||||
|
* - Set the initial SP
|
||||||
|
* - Set the initial PC == Reset_Handler,
|
||||||
|
* - Set the vector table entries with the exceptions ISR address
|
||||||
|
* - Configure the clock system
|
||||||
|
* - Branches to main in the C library (which eventually
|
||||||
|
* calls main()).
|
||||||
|
* After Reset the Cortex-M3 processor is in Thread mode,
|
||||||
|
* priority is Privileged, and the Stack is set to Main.
|
||||||
|
******************************************************************************
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
.syntax unified
|
||||||
|
.cpu cortex-m3
|
||||||
|
.fpu softvfp
|
||||||
|
.thumb
|
||||||
|
|
||||||
|
.global g_pfnVectors
|
||||||
|
.global Default_Handler
|
||||||
|
|
||||||
|
/* start address for the initialization values of the .data section.
|
||||||
|
defined in linker script */
|
||||||
|
.word _sidata
|
||||||
|
/* start address for the .data section. defined in linker script */
|
||||||
|
.word _sdata
|
||||||
|
/* end address for the .data section. defined in linker script */
|
||||||
|
.word _edata
|
||||||
|
/* start address for the .bss section. defined in linker script */
|
||||||
|
.word _sbss
|
||||||
|
/* end address for the .bss section. defined in linker script */
|
||||||
|
.word _ebss
|
||||||
|
|
||||||
|
.equ BootRAM, 0xF108F85F
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor first
|
||||||
|
* starts execution following a reset event. Only the absolutely
|
||||||
|
* necessary set is performed, after which the application
|
||||||
|
* supplied main() routine is called.
|
||||||
|
* @param None
|
||||||
|
* @retval : None
|
||||||
|
*/
|
||||||
|
|
||||||
|
.section .text.Reset_Handler
|
||||||
|
.weak Reset_Handler
|
||||||
|
.type Reset_Handler, %function
|
||||||
|
Reset_Handler:
|
||||||
|
|
||||||
|
/* Copy the data segment initializers from flash to SRAM */
|
||||||
|
movs r1, #0
|
||||||
|
b LoopCopyDataInit
|
||||||
|
|
||||||
|
CopyDataInit:
|
||||||
|
ldr r3, =_sidata
|
||||||
|
ldr r3, [r3, r1]
|
||||||
|
str r3, [r0, r1]
|
||||||
|
adds r1, r1, #4
|
||||||
|
|
||||||
|
LoopCopyDataInit:
|
||||||
|
ldr r0, =_sdata
|
||||||
|
ldr r3, =_edata
|
||||||
|
adds r2, r0, r1
|
||||||
|
cmp r2, r3
|
||||||
|
bcc CopyDataInit
|
||||||
|
ldr r2, =_sbss
|
||||||
|
b LoopFillZerobss
|
||||||
|
/* Zero fill the bss segment. */
|
||||||
|
FillZerobss:
|
||||||
|
movs r3, #0
|
||||||
|
str r3, [r2], #4
|
||||||
|
|
||||||
|
LoopFillZerobss:
|
||||||
|
ldr r3, = _ebss
|
||||||
|
cmp r2, r3
|
||||||
|
bcc FillZerobss
|
||||||
|
|
||||||
|
/* Call the clock system intitialization function.*/
|
||||||
|
bl SystemInit
|
||||||
|
/* Call static constructors */
|
||||||
|
/* bl __libc_init_array */
|
||||||
|
/* Call the application's entry point.*/
|
||||||
|
bl entry
|
||||||
|
bx lr
|
||||||
|
.size Reset_Handler, .-Reset_Handler
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor receives an
|
||||||
|
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||||
|
* the system state for examination by a debugger.
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
* @retval : None
|
||||||
|
*/
|
||||||
|
.section .text.Default_Handler,"ax",%progbits
|
||||||
|
Default_Handler:
|
||||||
|
Infinite_Loop:
|
||||||
|
b Infinite_Loop
|
||||||
|
.size Default_Handler, .-Default_Handler
|
||||||
|
/******************************************************************************
|
||||||
|
*
|
||||||
|
* The minimal vector table for a Cortex M3. Note that the proper constructs
|
||||||
|
* must be placed on this to ensure that it ends up at physical address
|
||||||
|
* 0x0000.0000.
|
||||||
|
*
|
||||||
|
******************************************************************************/
|
||||||
|
.section .isr_vector,"a",%progbits
|
||||||
|
.type g_pfnVectors, %object
|
||||||
|
.size g_pfnVectors, .-g_pfnVectors
|
||||||
|
|
||||||
|
|
||||||
|
g_pfnVectors:
|
||||||
|
|
||||||
|
|
||||||
|
.word _estack
|
||||||
|
.word Reset_Handler
|
||||||
|
.word NMI_Handler
|
||||||
|
.word HardFault_Handler
|
||||||
|
.word MemManage_Handler
|
||||||
|
.word BusFault_Handler
|
||||||
|
.word UsageFault_Handler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word SVC_Handler
|
||||||
|
.word DebugMon_Handler
|
||||||
|
.word 0
|
||||||
|
.word PendSV_Handler
|
||||||
|
.word SysTick_Handler
|
||||||
|
.word WWDG_IRQHandler
|
||||||
|
.word PVD_IRQHandler
|
||||||
|
.word TAMPER_IRQHandler
|
||||||
|
.word RTC_IRQHandler
|
||||||
|
.word FLASH_IRQHandler
|
||||||
|
.word RCC_IRQHandler
|
||||||
|
.word EXTI0_IRQHandler
|
||||||
|
.word EXTI1_IRQHandler
|
||||||
|
.word EXTI2_IRQHandler
|
||||||
|
.word EXTI3_IRQHandler
|
||||||
|
.word EXTI4_IRQHandler
|
||||||
|
.word DMA1_Channel1_IRQHandler
|
||||||
|
.word DMA1_Channel2_IRQHandler
|
||||||
|
.word DMA1_Channel3_IRQHandler
|
||||||
|
.word DMA1_Channel4_IRQHandler
|
||||||
|
.word DMA1_Channel5_IRQHandler
|
||||||
|
.word DMA1_Channel6_IRQHandler
|
||||||
|
.word DMA1_Channel7_IRQHandler
|
||||||
|
.word ADC1_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word EXTI9_5_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word TIM2_IRQHandler
|
||||||
|
.word TIM3_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word I2C1_EV_IRQHandler
|
||||||
|
.word I2C1_ER_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word SPI1_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word USART1_IRQHandler
|
||||||
|
.word USART2_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word EXTI15_10_IRQHandler
|
||||||
|
.word RTC_Alarm_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word BootRAM /* @0x108. This is for boot in RAM mode for
|
||||||
|
STM32F10x Low Density devices.*/
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
*
|
||||||
|
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||||
|
* As they are weak aliases, any function with the same name will override
|
||||||
|
* this definition.
|
||||||
|
*
|
||||||
|
*******************************************************************************/
|
||||||
|
|
||||||
|
.weak NMI_Handler
|
||||||
|
.thumb_set NMI_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak HardFault_Handler
|
||||||
|
.thumb_set HardFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak MemManage_Handler
|
||||||
|
.thumb_set MemManage_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak BusFault_Handler
|
||||||
|
.thumb_set BusFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak UsageFault_Handler
|
||||||
|
.thumb_set UsageFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SVC_Handler
|
||||||
|
.thumb_set SVC_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak DebugMon_Handler
|
||||||
|
.thumb_set DebugMon_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak PendSV_Handler
|
||||||
|
.thumb_set PendSV_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SysTick_Handler
|
||||||
|
.thumb_set SysTick_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak WWDG_IRQHandler
|
||||||
|
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak PVD_IRQHandler
|
||||||
|
.thumb_set PVD_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TAMPER_IRQHandler
|
||||||
|
.thumb_set TAMPER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_IRQHandler
|
||||||
|
.thumb_set RTC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FLASH_IRQHandler
|
||||||
|
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RCC_IRQHandler
|
||||||
|
.thumb_set RCC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI0_IRQHandler
|
||||||
|
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI1_IRQHandler
|
||||||
|
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI2_IRQHandler
|
||||||
|
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI3_IRQHandler
|
||||||
|
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI4_IRQHandler
|
||||||
|
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel1_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel2_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel3_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel4_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel5_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel6_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel7_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ADC1_IRQHandler
|
||||||
|
.thumb_set ADC1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI9_5_IRQHandler
|
||||||
|
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM2_IRQHandler
|
||||||
|
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM3_IRQHandler
|
||||||
|
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_EV_IRQHandler
|
||||||
|
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_ER_IRQHandler
|
||||||
|
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI1_IRQHandler
|
||||||
|
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART1_IRQHandler
|
||||||
|
.thumb_set USART1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART2_IRQHandler
|
||||||
|
.thumb_set USART2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI15_10_IRQHandler
|
||||||
|
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_Alarm_IRQHandler
|
||||||
|
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,353 @@
|
||||||
|
/**
|
||||||
|
*************** (C) COPYRIGHT 2017 STMicroelectronics ************************
|
||||||
|
* @file startup_stm32f101xb.s
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V4.2.0
|
||||||
|
* @date 31-March-2017
|
||||||
|
* @brief STM32F101xB Devices vector table for Atollic toolchain.
|
||||||
|
* This module performs:
|
||||||
|
* - Set the initial SP
|
||||||
|
* - Set the initial PC == Reset_Handler,
|
||||||
|
* - Set the vector table entries with the exceptions ISR address
|
||||||
|
* - Configure the clock system
|
||||||
|
* - Branches to main in the C library (which eventually
|
||||||
|
* calls main()).
|
||||||
|
* After Reset the Cortex-M3 processor is in Thread mode,
|
||||||
|
* priority is Privileged, and the Stack is set to Main.
|
||||||
|
******************************************************************************
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
.syntax unified
|
||||||
|
.cpu cortex-m3
|
||||||
|
.fpu softvfp
|
||||||
|
.thumb
|
||||||
|
|
||||||
|
.global g_pfnVectors
|
||||||
|
.global Default_Handler
|
||||||
|
|
||||||
|
/* start address for the initialization values of the .data section.
|
||||||
|
defined in linker script */
|
||||||
|
.word _sidata
|
||||||
|
/* start address for the .data section. defined in linker script */
|
||||||
|
.word _sdata
|
||||||
|
/* end address for the .data section. defined in linker script */
|
||||||
|
.word _edata
|
||||||
|
/* start address for the .bss section. defined in linker script */
|
||||||
|
.word _sbss
|
||||||
|
/* end address for the .bss section. defined in linker script */
|
||||||
|
.word _ebss
|
||||||
|
|
||||||
|
.equ BootRAM, 0xF108F85F
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor first
|
||||||
|
* starts execution following a reset event. Only the absolutely
|
||||||
|
* necessary set is performed, after which the application
|
||||||
|
* supplied main() routine is called.
|
||||||
|
* @param None
|
||||||
|
* @retval : None
|
||||||
|
*/
|
||||||
|
|
||||||
|
.section .text.Reset_Handler
|
||||||
|
.weak Reset_Handler
|
||||||
|
.type Reset_Handler, %function
|
||||||
|
Reset_Handler:
|
||||||
|
|
||||||
|
/* Copy the data segment initializers from flash to SRAM */
|
||||||
|
movs r1, #0
|
||||||
|
b LoopCopyDataInit
|
||||||
|
|
||||||
|
CopyDataInit:
|
||||||
|
ldr r3, =_sidata
|
||||||
|
ldr r3, [r3, r1]
|
||||||
|
str r3, [r0, r1]
|
||||||
|
adds r1, r1, #4
|
||||||
|
|
||||||
|
LoopCopyDataInit:
|
||||||
|
ldr r0, =_sdata
|
||||||
|
ldr r3, =_edata
|
||||||
|
adds r2, r0, r1
|
||||||
|
cmp r2, r3
|
||||||
|
bcc CopyDataInit
|
||||||
|
ldr r2, =_sbss
|
||||||
|
b LoopFillZerobss
|
||||||
|
/* Zero fill the bss segment. */
|
||||||
|
FillZerobss:
|
||||||
|
movs r3, #0
|
||||||
|
str r3, [r2], #4
|
||||||
|
|
||||||
|
LoopFillZerobss:
|
||||||
|
ldr r3, = _ebss
|
||||||
|
cmp r2, r3
|
||||||
|
bcc FillZerobss
|
||||||
|
|
||||||
|
/* Call the clock system intitialization function.*/
|
||||||
|
bl SystemInit
|
||||||
|
/* Call static constructors */
|
||||||
|
/* bl __libc_init_array */
|
||||||
|
/* Call the application's entry point.*/
|
||||||
|
bl entry
|
||||||
|
bx lr
|
||||||
|
.size Reset_Handler, .-Reset_Handler
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor receives an
|
||||||
|
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||||
|
* the system state for examination by a debugger.
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
* @retval : None
|
||||||
|
*/
|
||||||
|
.section .text.Default_Handler,"ax",%progbits
|
||||||
|
Default_Handler:
|
||||||
|
Infinite_Loop:
|
||||||
|
b Infinite_Loop
|
||||||
|
.size Default_Handler, .-Default_Handler
|
||||||
|
/******************************************************************************
|
||||||
|
*
|
||||||
|
* The minimal vector table for a Cortex M3. Note that the proper constructs
|
||||||
|
* must be placed on this to ensure that it ends up at physical address
|
||||||
|
* 0x0000.0000.
|
||||||
|
*
|
||||||
|
******************************************************************************/
|
||||||
|
.section .isr_vector,"a",%progbits
|
||||||
|
.type g_pfnVectors, %object
|
||||||
|
.size g_pfnVectors, .-g_pfnVectors
|
||||||
|
|
||||||
|
|
||||||
|
g_pfnVectors:
|
||||||
|
|
||||||
|
.word _estack
|
||||||
|
.word Reset_Handler
|
||||||
|
.word NMI_Handler
|
||||||
|
.word HardFault_Handler
|
||||||
|
.word MemManage_Handler
|
||||||
|
.word BusFault_Handler
|
||||||
|
.word UsageFault_Handler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word SVC_Handler
|
||||||
|
.word DebugMon_Handler
|
||||||
|
.word 0
|
||||||
|
.word PendSV_Handler
|
||||||
|
.word SysTick_Handler
|
||||||
|
.word WWDG_IRQHandler
|
||||||
|
.word PVD_IRQHandler
|
||||||
|
.word TAMPER_IRQHandler
|
||||||
|
.word RTC_IRQHandler
|
||||||
|
.word FLASH_IRQHandler
|
||||||
|
.word RCC_IRQHandler
|
||||||
|
.word EXTI0_IRQHandler
|
||||||
|
.word EXTI1_IRQHandler
|
||||||
|
.word EXTI2_IRQHandler
|
||||||
|
.word EXTI3_IRQHandler
|
||||||
|
.word EXTI4_IRQHandler
|
||||||
|
.word DMA1_Channel1_IRQHandler
|
||||||
|
.word DMA1_Channel2_IRQHandler
|
||||||
|
.word DMA1_Channel3_IRQHandler
|
||||||
|
.word DMA1_Channel4_IRQHandler
|
||||||
|
.word DMA1_Channel5_IRQHandler
|
||||||
|
.word DMA1_Channel6_IRQHandler
|
||||||
|
.word DMA1_Channel7_IRQHandler
|
||||||
|
.word ADC1_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word EXTI9_5_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word TIM2_IRQHandler
|
||||||
|
.word TIM3_IRQHandler
|
||||||
|
.word TIM4_IRQHandler
|
||||||
|
.word I2C1_EV_IRQHandler
|
||||||
|
.word I2C1_ER_IRQHandler
|
||||||
|
.word I2C2_EV_IRQHandler
|
||||||
|
.word I2C2_ER_IRQHandler
|
||||||
|
.word SPI1_IRQHandler
|
||||||
|
.word SPI2_IRQHandler
|
||||||
|
.word USART1_IRQHandler
|
||||||
|
.word USART2_IRQHandler
|
||||||
|
.word USART3_IRQHandler
|
||||||
|
.word EXTI15_10_IRQHandler
|
||||||
|
.word RTC_Alarm_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word BootRAM /* @0x108. This is for boot in RAM mode for
|
||||||
|
STM32F10x Medium Density devices. */
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
*
|
||||||
|
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||||
|
* As they are weak aliases, any function with the same name will override
|
||||||
|
* this definition.
|
||||||
|
*
|
||||||
|
*******************************************************************************/
|
||||||
|
|
||||||
|
.weak NMI_Handler
|
||||||
|
.thumb_set NMI_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak HardFault_Handler
|
||||||
|
.thumb_set HardFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak MemManage_Handler
|
||||||
|
.thumb_set MemManage_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak BusFault_Handler
|
||||||
|
.thumb_set BusFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak UsageFault_Handler
|
||||||
|
.thumb_set UsageFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SVC_Handler
|
||||||
|
.thumb_set SVC_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak DebugMon_Handler
|
||||||
|
.thumb_set DebugMon_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak PendSV_Handler
|
||||||
|
.thumb_set PendSV_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SysTick_Handler
|
||||||
|
.thumb_set SysTick_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak WWDG_IRQHandler
|
||||||
|
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak PVD_IRQHandler
|
||||||
|
.thumb_set PVD_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TAMPER_IRQHandler
|
||||||
|
.thumb_set TAMPER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_IRQHandler
|
||||||
|
.thumb_set RTC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FLASH_IRQHandler
|
||||||
|
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RCC_IRQHandler
|
||||||
|
.thumb_set RCC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI0_IRQHandler
|
||||||
|
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI1_IRQHandler
|
||||||
|
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI2_IRQHandler
|
||||||
|
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI3_IRQHandler
|
||||||
|
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI4_IRQHandler
|
||||||
|
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel1_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel2_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel3_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel4_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel5_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel6_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel7_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ADC1_IRQHandler
|
||||||
|
.thumb_set ADC1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI9_5_IRQHandler
|
||||||
|
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM2_IRQHandler
|
||||||
|
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM3_IRQHandler
|
||||||
|
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM4_IRQHandler
|
||||||
|
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_EV_IRQHandler
|
||||||
|
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_ER_IRQHandler
|
||||||
|
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_EV_IRQHandler
|
||||||
|
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_ER_IRQHandler
|
||||||
|
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI1_IRQHandler
|
||||||
|
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI2_IRQHandler
|
||||||
|
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART1_IRQHandler
|
||||||
|
.thumb_set USART1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART2_IRQHandler
|
||||||
|
.thumb_set USART2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART3_IRQHandler
|
||||||
|
.thumb_set USART3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI15_10_IRQHandler
|
||||||
|
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_Alarm_IRQHandler
|
||||||
|
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
||||||
|
|
@ -0,0 +1,438 @@
|
||||||
|
/**
|
||||||
|
*************** (C) COPYRIGHT 2017 STMicroelectronics ************************
|
||||||
|
* @file startup_stm32f101xe.s
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V4.2.0
|
||||||
|
* @date 31-March-2017
|
||||||
|
* @brief STM32F101xE Value Line Devices vector table for Atollic toolchain.
|
||||||
|
* This module performs:
|
||||||
|
* - Set the initial SP
|
||||||
|
* - Set the initial PC == Reset_Handler,
|
||||||
|
* - Set the vector table entries with the exceptions ISR address
|
||||||
|
* - Configure the clock system
|
||||||
|
* - Branches to main in the C library (which eventually
|
||||||
|
* calls main()).
|
||||||
|
* After Reset the Cortex-M3 processor is in Thread mode,
|
||||||
|
* priority is Privileged, and the Stack is set to Main.
|
||||||
|
******************************************************************************
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
.syntax unified
|
||||||
|
.cpu cortex-m3
|
||||||
|
.fpu softvfp
|
||||||
|
.thumb
|
||||||
|
|
||||||
|
.global g_pfnVectors
|
||||||
|
.global Default_Handler
|
||||||
|
|
||||||
|
/* start address for the initialization values of the .data section.
|
||||||
|
defined in linker script */
|
||||||
|
.word _sidata
|
||||||
|
/* start address for the .data section. defined in linker script */
|
||||||
|
.word _sdata
|
||||||
|
/* end address for the .data section. defined in linker script */
|
||||||
|
.word _edata
|
||||||
|
/* start address for the .bss section. defined in linker script */
|
||||||
|
.word _sbss
|
||||||
|
/* end address for the .bss section. defined in linker script */
|
||||||
|
.word _ebss
|
||||||
|
|
||||||
|
.equ BootRAM, 0xF1E0F85F
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor first
|
||||||
|
* starts execution following a reset event. Only the absolutely
|
||||||
|
* necessary set is performed, after which the application
|
||||||
|
* supplied main() routine is called.
|
||||||
|
* @param None
|
||||||
|
* @retval : None
|
||||||
|
*/
|
||||||
|
|
||||||
|
.section .text.Reset_Handler
|
||||||
|
.weak Reset_Handler
|
||||||
|
.type Reset_Handler, %function
|
||||||
|
Reset_Handler:
|
||||||
|
|
||||||
|
/* Copy the data segment initializers from flash to SRAM */
|
||||||
|
movs r1, #0
|
||||||
|
b LoopCopyDataInit
|
||||||
|
|
||||||
|
CopyDataInit:
|
||||||
|
ldr r3, =_sidata
|
||||||
|
ldr r3, [r3, r1]
|
||||||
|
str r3, [r0, r1]
|
||||||
|
adds r1, r1, #4
|
||||||
|
|
||||||
|
LoopCopyDataInit:
|
||||||
|
ldr r0, =_sdata
|
||||||
|
ldr r3, =_edata
|
||||||
|
adds r2, r0, r1
|
||||||
|
cmp r2, r3
|
||||||
|
bcc CopyDataInit
|
||||||
|
ldr r2, =_sbss
|
||||||
|
b LoopFillZerobss
|
||||||
|
/* Zero fill the bss segment. */
|
||||||
|
FillZerobss:
|
||||||
|
movs r3, #0
|
||||||
|
str r3, [r2], #4
|
||||||
|
|
||||||
|
LoopFillZerobss:
|
||||||
|
ldr r3, = _ebss
|
||||||
|
cmp r2, r3
|
||||||
|
bcc FillZerobss
|
||||||
|
|
||||||
|
/* Call the clock system intitialization function.*/
|
||||||
|
bl SystemInit
|
||||||
|
/* Call static constructors */
|
||||||
|
/* bl __libc_init_array */
|
||||||
|
/* Call the application's entry point.*/
|
||||||
|
bl entry
|
||||||
|
bx lr
|
||||||
|
.size Reset_Handler, .-Reset_Handler
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor receives an
|
||||||
|
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||||
|
* the system state for examination by a debugger.
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
* @retval : None
|
||||||
|
*/
|
||||||
|
.section .text.Default_Handler,"ax",%progbits
|
||||||
|
Default_Handler:
|
||||||
|
Infinite_Loop:
|
||||||
|
b Infinite_Loop
|
||||||
|
.size Default_Handler, .-Default_Handler
|
||||||
|
/******************************************************************************
|
||||||
|
*
|
||||||
|
* The minimal vector table for a Cortex M3. Note that the proper constructs
|
||||||
|
* must be placed on this to ensure that it ends up at physical address
|
||||||
|
* 0x0000.0000.
|
||||||
|
*
|
||||||
|
******************************************************************************/
|
||||||
|
.section .isr_vector,"a",%progbits
|
||||||
|
.type g_pfnVectors, %object
|
||||||
|
.size g_pfnVectors, .-g_pfnVectors
|
||||||
|
|
||||||
|
|
||||||
|
g_pfnVectors:
|
||||||
|
|
||||||
|
.word _estack
|
||||||
|
.word Reset_Handler
|
||||||
|
.word NMI_Handler
|
||||||
|
.word HardFault_Handler
|
||||||
|
.word MemManage_Handler
|
||||||
|
.word BusFault_Handler
|
||||||
|
.word UsageFault_Handler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word SVC_Handler
|
||||||
|
.word DebugMon_Handler
|
||||||
|
.word 0
|
||||||
|
.word PendSV_Handler
|
||||||
|
.word SysTick_Handler
|
||||||
|
.word WWDG_IRQHandler
|
||||||
|
.word PVD_IRQHandler
|
||||||
|
.word TAMPER_IRQHandler
|
||||||
|
.word RTC_IRQHandler
|
||||||
|
.word FLASH_IRQHandler
|
||||||
|
.word RCC_IRQHandler
|
||||||
|
.word EXTI0_IRQHandler
|
||||||
|
.word EXTI1_IRQHandler
|
||||||
|
.word EXTI2_IRQHandler
|
||||||
|
.word EXTI3_IRQHandler
|
||||||
|
.word EXTI4_IRQHandler
|
||||||
|
.word DMA1_Channel1_IRQHandler
|
||||||
|
.word DMA1_Channel2_IRQHandler
|
||||||
|
.word DMA1_Channel3_IRQHandler
|
||||||
|
.word DMA1_Channel4_IRQHandler
|
||||||
|
.word DMA1_Channel5_IRQHandler
|
||||||
|
.word DMA1_Channel6_IRQHandler
|
||||||
|
.word DMA1_Channel7_IRQHandler
|
||||||
|
.word ADC1_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word EXTI9_5_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word TIM2_IRQHandler
|
||||||
|
.word TIM3_IRQHandler
|
||||||
|
.word TIM4_IRQHandler
|
||||||
|
.word I2C1_EV_IRQHandler
|
||||||
|
.word I2C1_ER_IRQHandler
|
||||||
|
.word I2C2_EV_IRQHandler
|
||||||
|
.word I2C2_ER_IRQHandler
|
||||||
|
.word SPI1_IRQHandler
|
||||||
|
.word SPI2_IRQHandler
|
||||||
|
.word USART1_IRQHandler
|
||||||
|
.word USART2_IRQHandler
|
||||||
|
.word USART3_IRQHandler
|
||||||
|
.word EXTI15_10_IRQHandler
|
||||||
|
.word RTC_Alarm_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word FSMC_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word TIM5_IRQHandler
|
||||||
|
.word SPI3_IRQHandler
|
||||||
|
.word UART4_IRQHandler
|
||||||
|
.word UART5_IRQHandler
|
||||||
|
.word TIM6_IRQHandler
|
||||||
|
.word TIM7_IRQHandler
|
||||||
|
.word DMA2_Channel1_IRQHandler
|
||||||
|
.word DMA2_Channel2_IRQHandler
|
||||||
|
.word DMA2_Channel3_IRQHandler
|
||||||
|
.word DMA2_Channel4_5_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word BootRAM /* @0x1E0. This is for boot in RAM mode for
|
||||||
|
STM32F10x High Density devices. */
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
*
|
||||||
|
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||||
|
* As they are weak aliases, any function with the same name will override
|
||||||
|
* this definition.
|
||||||
|
*
|
||||||
|
*******************************************************************************/
|
||||||
|
|
||||||
|
.weak NMI_Handler
|
||||||
|
.thumb_set NMI_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak HardFault_Handler
|
||||||
|
.thumb_set HardFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak MemManage_Handler
|
||||||
|
.thumb_set MemManage_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak BusFault_Handler
|
||||||
|
.thumb_set BusFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak UsageFault_Handler
|
||||||
|
.thumb_set UsageFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SVC_Handler
|
||||||
|
.thumb_set SVC_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak DebugMon_Handler
|
||||||
|
.thumb_set DebugMon_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak PendSV_Handler
|
||||||
|
.thumb_set PendSV_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SysTick_Handler
|
||||||
|
.thumb_set SysTick_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak WWDG_IRQHandler
|
||||||
|
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak PVD_IRQHandler
|
||||||
|
.thumb_set PVD_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TAMPER_IRQHandler
|
||||||
|
.thumb_set TAMPER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_IRQHandler
|
||||||
|
.thumb_set RTC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FLASH_IRQHandler
|
||||||
|
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RCC_IRQHandler
|
||||||
|
.thumb_set RCC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI0_IRQHandler
|
||||||
|
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI1_IRQHandler
|
||||||
|
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI2_IRQHandler
|
||||||
|
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI3_IRQHandler
|
||||||
|
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI4_IRQHandler
|
||||||
|
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel1_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel2_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel3_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel4_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel5_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel6_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel7_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ADC1_IRQHandler
|
||||||
|
.thumb_set ADC1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI9_5_IRQHandler
|
||||||
|
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM2_IRQHandler
|
||||||
|
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM3_IRQHandler
|
||||||
|
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM4_IRQHandler
|
||||||
|
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_EV_IRQHandler
|
||||||
|
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_ER_IRQHandler
|
||||||
|
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_EV_IRQHandler
|
||||||
|
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_ER_IRQHandler
|
||||||
|
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI1_IRQHandler
|
||||||
|
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI2_IRQHandler
|
||||||
|
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART1_IRQHandler
|
||||||
|
.thumb_set USART1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART2_IRQHandler
|
||||||
|
.thumb_set USART2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART3_IRQHandler
|
||||||
|
.thumb_set USART3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI15_10_IRQHandler
|
||||||
|
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_Alarm_IRQHandler
|
||||||
|
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FSMC_IRQHandler
|
||||||
|
.thumb_set FSMC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM5_IRQHandler
|
||||||
|
.thumb_set TIM5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI3_IRQHandler
|
||||||
|
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART4_IRQHandler
|
||||||
|
.thumb_set UART4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART5_IRQHandler
|
||||||
|
.thumb_set UART5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM6_IRQHandler
|
||||||
|
.thumb_set TIM6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM7_IRQHandler
|
||||||
|
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Channel1_IRQHandler
|
||||||
|
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Channel2_IRQHandler
|
||||||
|
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Channel3_IRQHandler
|
||||||
|
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Channel4_5_IRQHandler
|
||||||
|
.thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,454 @@
|
||||||
|
/**
|
||||||
|
*************** (C) COPYRIGHT 2017 STMicroelectronics ************************
|
||||||
|
* @file startup_stm32f101xg.s
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V4.2.0
|
||||||
|
* @date 31-March-2017
|
||||||
|
* @brief STM32F101xG Devices vector table for Atollic toolchain.
|
||||||
|
* This module performs:
|
||||||
|
* - Set the initial SP
|
||||||
|
* - Set the initial PC == Reset_Handler,
|
||||||
|
* - Set the vector table entries with the exceptions ISR address
|
||||||
|
* - Configure the clock system
|
||||||
|
* - Branches to main in the C library (which eventually
|
||||||
|
* calls main()).
|
||||||
|
* After Reset the Cortex-M3 processor is in Thread mode,
|
||||||
|
* priority is Privileged, and the Stack is set to Main.
|
||||||
|
******************************************************************************
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
.syntax unified
|
||||||
|
.cpu cortex-m3
|
||||||
|
.fpu softvfp
|
||||||
|
.thumb
|
||||||
|
|
||||||
|
.global g_pfnVectors
|
||||||
|
.global Default_Handler
|
||||||
|
|
||||||
|
/* start address for the initialization values of the .data section.
|
||||||
|
defined in linker script */
|
||||||
|
.word _sidata
|
||||||
|
/* start address for the .data section. defined in linker script */
|
||||||
|
.word _sdata
|
||||||
|
/* end address for the .data section. defined in linker script */
|
||||||
|
.word _edata
|
||||||
|
/* start address for the .bss section. defined in linker script */
|
||||||
|
.word _sbss
|
||||||
|
/* end address for the .bss section. defined in linker script */
|
||||||
|
.word _ebss
|
||||||
|
|
||||||
|
.equ BootRAM, 0xF1E0F85F
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor first
|
||||||
|
* starts execution following a reset event. Only the absolutely
|
||||||
|
* necessary set is performed, after which the application
|
||||||
|
* supplied main() routine is called.
|
||||||
|
* @param None
|
||||||
|
* @retval : None
|
||||||
|
*/
|
||||||
|
|
||||||
|
.section .text.Reset_Handler
|
||||||
|
.weak Reset_Handler
|
||||||
|
.type Reset_Handler, %function
|
||||||
|
Reset_Handler:
|
||||||
|
|
||||||
|
/* Copy the data segment initializers from flash to SRAM */
|
||||||
|
movs r1, #0
|
||||||
|
b LoopCopyDataInit
|
||||||
|
|
||||||
|
CopyDataInit:
|
||||||
|
ldr r3, =_sidata
|
||||||
|
ldr r3, [r3, r1]
|
||||||
|
str r3, [r0, r1]
|
||||||
|
adds r1, r1, #4
|
||||||
|
|
||||||
|
LoopCopyDataInit:
|
||||||
|
ldr r0, =_sdata
|
||||||
|
ldr r3, =_edata
|
||||||
|
adds r2, r0, r1
|
||||||
|
cmp r2, r3
|
||||||
|
bcc CopyDataInit
|
||||||
|
ldr r2, =_sbss
|
||||||
|
b LoopFillZerobss
|
||||||
|
/* Zero fill the bss segment. */
|
||||||
|
FillZerobss:
|
||||||
|
movs r3, #0
|
||||||
|
str r3, [r2], #4
|
||||||
|
|
||||||
|
LoopFillZerobss:
|
||||||
|
ldr r3, = _ebss
|
||||||
|
cmp r2, r3
|
||||||
|
bcc FillZerobss
|
||||||
|
|
||||||
|
/* Call the clock system intitialization function.*/
|
||||||
|
bl SystemInit
|
||||||
|
/* Call static constructors */
|
||||||
|
/* bl __libc_init_array */
|
||||||
|
/* Call the application's entry point.*/
|
||||||
|
bl entry
|
||||||
|
bx lr
|
||||||
|
.size Reset_Handler, .-Reset_Handler
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor receives an
|
||||||
|
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||||
|
* the system state for examination by a debugger.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
.section .text.Default_Handler,"ax",%progbits
|
||||||
|
Default_Handler:
|
||||||
|
Infinite_Loop:
|
||||||
|
b Infinite_Loop
|
||||||
|
.size Default_Handler, .-Default_Handler
|
||||||
|
/******************************************************************************
|
||||||
|
*
|
||||||
|
* The minimal vector table for a Cortex M3. Note that the proper constructs
|
||||||
|
* must be placed on this to ensure that it ends up at physical address
|
||||||
|
* 0x0000.0000.
|
||||||
|
*
|
||||||
|
******************************************************************************/
|
||||||
|
.section .isr_vector,"a",%progbits
|
||||||
|
.type g_pfnVectors, %object
|
||||||
|
.size g_pfnVectors, .-g_pfnVectors
|
||||||
|
|
||||||
|
|
||||||
|
g_pfnVectors:
|
||||||
|
|
||||||
|
.word _estack
|
||||||
|
.word Reset_Handler
|
||||||
|
.word NMI_Handler
|
||||||
|
.word HardFault_Handler
|
||||||
|
.word MemManage_Handler
|
||||||
|
.word BusFault_Handler
|
||||||
|
.word UsageFault_Handler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word SVC_Handler
|
||||||
|
.word DebugMon_Handler
|
||||||
|
.word 0
|
||||||
|
.word PendSV_Handler
|
||||||
|
.word SysTick_Handler
|
||||||
|
.word WWDG_IRQHandler
|
||||||
|
.word PVD_IRQHandler
|
||||||
|
.word TAMPER_IRQHandler
|
||||||
|
.word RTC_IRQHandler
|
||||||
|
.word FLASH_IRQHandler
|
||||||
|
.word RCC_IRQHandler
|
||||||
|
.word EXTI0_IRQHandler
|
||||||
|
.word EXTI1_IRQHandler
|
||||||
|
.word EXTI2_IRQHandler
|
||||||
|
.word EXTI3_IRQHandler
|
||||||
|
.word EXTI4_IRQHandler
|
||||||
|
.word DMA1_Channel1_IRQHandler
|
||||||
|
.word DMA1_Channel2_IRQHandler
|
||||||
|
.word DMA1_Channel3_IRQHandler
|
||||||
|
.word DMA1_Channel4_IRQHandler
|
||||||
|
.word DMA1_Channel5_IRQHandler
|
||||||
|
.word DMA1_Channel6_IRQHandler
|
||||||
|
.word DMA1_Channel7_IRQHandler
|
||||||
|
.word ADC1_2_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word EXTI9_5_IRQHandler
|
||||||
|
.word TIM9_IRQHandler
|
||||||
|
.word TIM10_IRQHandler
|
||||||
|
.word TIM11_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word TIM2_IRQHandler
|
||||||
|
.word TIM3_IRQHandler
|
||||||
|
.word TIM4_IRQHandler
|
||||||
|
.word I2C1_EV_IRQHandler
|
||||||
|
.word I2C1_ER_IRQHandler
|
||||||
|
.word I2C2_EV_IRQHandler
|
||||||
|
.word I2C2_ER_IRQHandler
|
||||||
|
.word SPI1_IRQHandler
|
||||||
|
.word SPI2_IRQHandler
|
||||||
|
.word USART1_IRQHandler
|
||||||
|
.word USART2_IRQHandler
|
||||||
|
.word USART3_IRQHandler
|
||||||
|
.word EXTI15_10_IRQHandler
|
||||||
|
.word RTC_Alarm_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word TIM12_IRQHandler
|
||||||
|
.word TIM13_IRQHandler
|
||||||
|
.word TIM14_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word FSMC_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word TIM5_IRQHandler
|
||||||
|
.word SPI3_IRQHandler
|
||||||
|
.word UART4_IRQHandler
|
||||||
|
.word UART5_IRQHandler
|
||||||
|
.word TIM6_IRQHandler
|
||||||
|
.word TIM7_IRQHandler
|
||||||
|
.word DMA2_Channel1_IRQHandler
|
||||||
|
.word DMA2_Channel2_IRQHandler
|
||||||
|
.word DMA2_Channel3_IRQHandler
|
||||||
|
.word DMA2_Channel4_5_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word BootRAM /* @0x1E0. This is for boot in RAM mode for
|
||||||
|
STM32F10x XL-Density devices. */
|
||||||
|
/*******************************************************************************
|
||||||
|
*
|
||||||
|
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||||
|
* As they are weak aliases, any function with the same name will override
|
||||||
|
* this definition.
|
||||||
|
*
|
||||||
|
*******************************************************************************/
|
||||||
|
|
||||||
|
.weak NMI_Handler
|
||||||
|
.thumb_set NMI_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak HardFault_Handler
|
||||||
|
.thumb_set HardFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak MemManage_Handler
|
||||||
|
.thumb_set MemManage_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak BusFault_Handler
|
||||||
|
.thumb_set BusFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak UsageFault_Handler
|
||||||
|
.thumb_set UsageFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SVC_Handler
|
||||||
|
.thumb_set SVC_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak DebugMon_Handler
|
||||||
|
.thumb_set DebugMon_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak PendSV_Handler
|
||||||
|
.thumb_set PendSV_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SysTick_Handler
|
||||||
|
.thumb_set SysTick_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak WWDG_IRQHandler
|
||||||
|
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak PVD_IRQHandler
|
||||||
|
.thumb_set PVD_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TAMPER_IRQHandler
|
||||||
|
.thumb_set TAMPER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_IRQHandler
|
||||||
|
.thumb_set RTC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FLASH_IRQHandler
|
||||||
|
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RCC_IRQHandler
|
||||||
|
.thumb_set RCC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI0_IRQHandler
|
||||||
|
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI1_IRQHandler
|
||||||
|
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI2_IRQHandler
|
||||||
|
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI3_IRQHandler
|
||||||
|
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI4_IRQHandler
|
||||||
|
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel1_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel2_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel3_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel4_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel5_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel6_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel7_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ADC1_2_IRQHandler
|
||||||
|
.thumb_set ADC1_2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI9_5_IRQHandler
|
||||||
|
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM9_IRQHandler
|
||||||
|
.thumb_set TIM9_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM10_IRQHandler
|
||||||
|
.thumb_set TIM10_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM11_IRQHandler
|
||||||
|
.thumb_set TIM11_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM2_IRQHandler
|
||||||
|
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM3_IRQHandler
|
||||||
|
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM4_IRQHandler
|
||||||
|
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_EV_IRQHandler
|
||||||
|
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_ER_IRQHandler
|
||||||
|
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_EV_IRQHandler
|
||||||
|
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_ER_IRQHandler
|
||||||
|
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI1_IRQHandler
|
||||||
|
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI2_IRQHandler
|
||||||
|
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART1_IRQHandler
|
||||||
|
.thumb_set USART1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART2_IRQHandler
|
||||||
|
.thumb_set USART2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART3_IRQHandler
|
||||||
|
.thumb_set USART3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI15_10_IRQHandler
|
||||||
|
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_Alarm_IRQHandler
|
||||||
|
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM12_IRQHandler
|
||||||
|
.thumb_set TIM12_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM13_IRQHandler
|
||||||
|
.thumb_set TIM13_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM14_IRQHandler
|
||||||
|
.thumb_set TIM14_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FSMC_IRQHandler
|
||||||
|
.thumb_set FSMC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM5_IRQHandler
|
||||||
|
.thumb_set TIM5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI3_IRQHandler
|
||||||
|
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART4_IRQHandler
|
||||||
|
.thumb_set UART4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART5_IRQHandler
|
||||||
|
.thumb_set UART5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM6_IRQHandler
|
||||||
|
.thumb_set TIM6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM7_IRQHandler
|
||||||
|
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Channel1_IRQHandler
|
||||||
|
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Channel2_IRQHandler
|
||||||
|
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Channel3_IRQHandler
|
||||||
|
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Channel4_5_IRQHandler
|
||||||
|
.thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,345 @@
|
||||||
|
/**
|
||||||
|
*************** (C) COPYRIGHT 2017 STMicroelectronics ************************
|
||||||
|
* @file startup_stm32f102x6.s
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V4.2.0
|
||||||
|
* @date 31-March-2017
|
||||||
|
* @brief STM32F102x6 Devices vector table for Atollic toolchain.
|
||||||
|
* This module performs:
|
||||||
|
* - Set the initial SP
|
||||||
|
* - Set the initial PC == Reset_Handler,
|
||||||
|
* - Set the vector table entries with the exceptions ISR address
|
||||||
|
* - Configure the clock system
|
||||||
|
* - Branches to main in the C library (which eventually
|
||||||
|
* calls main()).
|
||||||
|
* After Reset the Cortex-M3 processor is in Thread mode,
|
||||||
|
* priority is Privileged, and the Stack is set to Main.
|
||||||
|
******************************************************************************
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
.syntax unified
|
||||||
|
.cpu cortex-m3
|
||||||
|
.fpu softvfp
|
||||||
|
.thumb
|
||||||
|
|
||||||
|
.global g_pfnVectors
|
||||||
|
.global Default_Handler
|
||||||
|
|
||||||
|
/* start address for the initialization values of the .data section.
|
||||||
|
defined in linker script */
|
||||||
|
.word _sidata
|
||||||
|
/* start address for the .data section. defined in linker script */
|
||||||
|
.word _sdata
|
||||||
|
/* end address for the .data section. defined in linker script */
|
||||||
|
.word _edata
|
||||||
|
/* start address for the .bss section. defined in linker script */
|
||||||
|
.word _sbss
|
||||||
|
/* end address for the .bss section. defined in linker script */
|
||||||
|
.word _ebss
|
||||||
|
|
||||||
|
.equ BootRAM, 0xF108F85F
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor first
|
||||||
|
* starts execution following a reset event. Only the absolutely
|
||||||
|
* necessary set is performed, after which the application
|
||||||
|
* supplied main() routine is called.
|
||||||
|
* @param None
|
||||||
|
* @retval : None
|
||||||
|
*/
|
||||||
|
|
||||||
|
.section .text.Reset_Handler
|
||||||
|
.weak Reset_Handler
|
||||||
|
.type Reset_Handler, %function
|
||||||
|
Reset_Handler:
|
||||||
|
|
||||||
|
/* Copy the data segment initializers from flash to SRAM */
|
||||||
|
movs r1, #0
|
||||||
|
b LoopCopyDataInit
|
||||||
|
|
||||||
|
CopyDataInit:
|
||||||
|
ldr r3, =_sidata
|
||||||
|
ldr r3, [r3, r1]
|
||||||
|
str r3, [r0, r1]
|
||||||
|
adds r1, r1, #4
|
||||||
|
|
||||||
|
LoopCopyDataInit:
|
||||||
|
ldr r0, =_sdata
|
||||||
|
ldr r3, =_edata
|
||||||
|
adds r2, r0, r1
|
||||||
|
cmp r2, r3
|
||||||
|
bcc CopyDataInit
|
||||||
|
ldr r2, =_sbss
|
||||||
|
b LoopFillZerobss
|
||||||
|
/* Zero fill the bss segment. */
|
||||||
|
FillZerobss:
|
||||||
|
movs r3, #0
|
||||||
|
str r3, [r2], #4
|
||||||
|
|
||||||
|
LoopFillZerobss:
|
||||||
|
ldr r3, = _ebss
|
||||||
|
cmp r2, r3
|
||||||
|
bcc FillZerobss
|
||||||
|
|
||||||
|
/* Call the clock system intitialization function.*/
|
||||||
|
bl SystemInit
|
||||||
|
/* Call static constructors */
|
||||||
|
/* bl __libc_init_array */
|
||||||
|
/* Call the application's entry point.*/
|
||||||
|
bl entry
|
||||||
|
bx lr
|
||||||
|
.size Reset_Handler, .-Reset_Handler
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor receives an
|
||||||
|
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||||
|
* the system state for examination by a debugger.
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
* @retval : None
|
||||||
|
*/
|
||||||
|
.section .text.Default_Handler,"ax",%progbits
|
||||||
|
Default_Handler:
|
||||||
|
Infinite_Loop:
|
||||||
|
b Infinite_Loop
|
||||||
|
.size Default_Handler, .-Default_Handler
|
||||||
|
/******************************************************************************
|
||||||
|
*
|
||||||
|
* The minimal vector table for a Cortex M3. Note that the proper constructs
|
||||||
|
* must be placed on this to ensure that it ends up at physical address
|
||||||
|
* 0x0000.0000.
|
||||||
|
*
|
||||||
|
******************************************************************************/
|
||||||
|
.section .isr_vector,"a",%progbits
|
||||||
|
.type g_pfnVectors, %object
|
||||||
|
.size g_pfnVectors, .-g_pfnVectors
|
||||||
|
|
||||||
|
|
||||||
|
g_pfnVectors:
|
||||||
|
|
||||||
|
.word _estack
|
||||||
|
.word Reset_Handler
|
||||||
|
.word NMI_Handler
|
||||||
|
.word HardFault_Handler
|
||||||
|
.word MemManage_Handler
|
||||||
|
.word BusFault_Handler
|
||||||
|
.word UsageFault_Handler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word SVC_Handler
|
||||||
|
.word DebugMon_Handler
|
||||||
|
.word 0
|
||||||
|
.word PendSV_Handler
|
||||||
|
.word SysTick_Handler
|
||||||
|
.word WWDG_IRQHandler
|
||||||
|
.word PVD_IRQHandler
|
||||||
|
.word TAMPER_IRQHandler
|
||||||
|
.word RTC_IRQHandler
|
||||||
|
.word FLASH_IRQHandler
|
||||||
|
.word RCC_IRQHandler
|
||||||
|
.word EXTI0_IRQHandler
|
||||||
|
.word EXTI1_IRQHandler
|
||||||
|
.word EXTI2_IRQHandler
|
||||||
|
.word EXTI3_IRQHandler
|
||||||
|
.word EXTI4_IRQHandler
|
||||||
|
.word DMA1_Channel1_IRQHandler
|
||||||
|
.word DMA1_Channel2_IRQHandler
|
||||||
|
.word DMA1_Channel3_IRQHandler
|
||||||
|
.word DMA1_Channel4_IRQHandler
|
||||||
|
.word DMA1_Channel5_IRQHandler
|
||||||
|
.word DMA1_Channel6_IRQHandler
|
||||||
|
.word DMA1_Channel7_IRQHandler
|
||||||
|
.word ADC1_IRQHandler
|
||||||
|
.word USB_HP_IRQHandler
|
||||||
|
.word USB_LP_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word EXTI9_5_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word TIM2_IRQHandler
|
||||||
|
.word TIM3_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word I2C1_EV_IRQHandler
|
||||||
|
.word I2C1_ER_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word SPI1_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word USART1_IRQHandler
|
||||||
|
.word USART2_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word EXTI15_10_IRQHandler
|
||||||
|
.word RTC_Alarm_IRQHandler
|
||||||
|
.word USBWakeUp_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word BootRAM /* @0x108. This is for boot in RAM mode for
|
||||||
|
STM32F10x Low Density devices.*/
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
*
|
||||||
|
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||||
|
* As they are weak aliases, any function with the same name will override
|
||||||
|
* this definition.
|
||||||
|
*
|
||||||
|
*******************************************************************************/
|
||||||
|
|
||||||
|
.weak NMI_Handler
|
||||||
|
.thumb_set NMI_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak HardFault_Handler
|
||||||
|
.thumb_set HardFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak MemManage_Handler
|
||||||
|
.thumb_set MemManage_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak BusFault_Handler
|
||||||
|
.thumb_set BusFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak UsageFault_Handler
|
||||||
|
.thumb_set UsageFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SVC_Handler
|
||||||
|
.thumb_set SVC_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak DebugMon_Handler
|
||||||
|
.thumb_set DebugMon_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak PendSV_Handler
|
||||||
|
.thumb_set PendSV_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SysTick_Handler
|
||||||
|
.thumb_set SysTick_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak WWDG_IRQHandler
|
||||||
|
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak PVD_IRQHandler
|
||||||
|
.thumb_set PVD_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TAMPER_IRQHandler
|
||||||
|
.thumb_set TAMPER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_IRQHandler
|
||||||
|
.thumb_set RTC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FLASH_IRQHandler
|
||||||
|
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RCC_IRQHandler
|
||||||
|
.thumb_set RCC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI0_IRQHandler
|
||||||
|
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI1_IRQHandler
|
||||||
|
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI2_IRQHandler
|
||||||
|
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI3_IRQHandler
|
||||||
|
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI4_IRQHandler
|
||||||
|
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel1_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel2_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel3_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel4_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel5_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel6_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel7_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ADC1_IRQHandler
|
||||||
|
.thumb_set ADC1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USB_HP_IRQHandler
|
||||||
|
.thumb_set USB_HP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USB_LP_IRQHandler
|
||||||
|
.thumb_set USB_LP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI9_5_IRQHandler
|
||||||
|
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM2_IRQHandler
|
||||||
|
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM3_IRQHandler
|
||||||
|
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_EV_IRQHandler
|
||||||
|
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_ER_IRQHandler
|
||||||
|
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI1_IRQHandler
|
||||||
|
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART1_IRQHandler
|
||||||
|
.thumb_set USART1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART2_IRQHandler
|
||||||
|
.thumb_set USART2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI15_10_IRQHandler
|
||||||
|
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_Alarm_IRQHandler
|
||||||
|
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USBWakeUp_IRQHandler
|
||||||
|
.thumb_set USBWakeUp_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,361 @@
|
||||||
|
/**
|
||||||
|
*************** (C) COPYRIGHT 2017 STMicroelectronics ************************
|
||||||
|
* @file startup_stm32f102xb.s
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V4.2.0
|
||||||
|
* @date 31-March-2017
|
||||||
|
* @brief STM32F102xB Value Line Devices vector table for Atollic toolchain.
|
||||||
|
* This module performs:
|
||||||
|
* - Set the initial SP
|
||||||
|
* - Set the initial PC == Reset_Handler,
|
||||||
|
* - Set the vector table entries with the exceptions ISR address
|
||||||
|
* - Configure the clock system
|
||||||
|
* - Branches to main in the C library (which eventually
|
||||||
|
* calls main()).
|
||||||
|
* After Reset the Cortex-M3 processor is in Thread mode,
|
||||||
|
* priority is Privileged, and the Stack is set to Main.
|
||||||
|
******************************************************************************
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
.syntax unified
|
||||||
|
.cpu cortex-m3
|
||||||
|
.fpu softvfp
|
||||||
|
.thumb
|
||||||
|
|
||||||
|
.global g_pfnVectors
|
||||||
|
.global Default_Handler
|
||||||
|
|
||||||
|
/* start address for the initialization values of the .data section.
|
||||||
|
defined in linker script */
|
||||||
|
.word _sidata
|
||||||
|
/* start address for the .data section. defined in linker script */
|
||||||
|
.word _sdata
|
||||||
|
/* end address for the .data section. defined in linker script */
|
||||||
|
.word _edata
|
||||||
|
/* start address for the .bss section. defined in linker script */
|
||||||
|
.word _sbss
|
||||||
|
/* end address for the .bss section. defined in linker script */
|
||||||
|
.word _ebss
|
||||||
|
|
||||||
|
.equ BootRAM, 0xF108F85F
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor first
|
||||||
|
* starts execution following a reset event. Only the absolutely
|
||||||
|
* necessary set is performed, after which the application
|
||||||
|
* supplied main() routine is called.
|
||||||
|
* @param None
|
||||||
|
* @retval : None
|
||||||
|
*/
|
||||||
|
|
||||||
|
.section .text.Reset_Handler
|
||||||
|
.weak Reset_Handler
|
||||||
|
.type Reset_Handler, %function
|
||||||
|
Reset_Handler:
|
||||||
|
|
||||||
|
/* Copy the data segment initializers from flash to SRAM */
|
||||||
|
movs r1, #0
|
||||||
|
b LoopCopyDataInit
|
||||||
|
|
||||||
|
CopyDataInit:
|
||||||
|
ldr r3, =_sidata
|
||||||
|
ldr r3, [r3, r1]
|
||||||
|
str r3, [r0, r1]
|
||||||
|
adds r1, r1, #4
|
||||||
|
|
||||||
|
LoopCopyDataInit:
|
||||||
|
ldr r0, =_sdata
|
||||||
|
ldr r3, =_edata
|
||||||
|
adds r2, r0, r1
|
||||||
|
cmp r2, r3
|
||||||
|
bcc CopyDataInit
|
||||||
|
ldr r2, =_sbss
|
||||||
|
b LoopFillZerobss
|
||||||
|
/* Zero fill the bss segment. */
|
||||||
|
FillZerobss:
|
||||||
|
movs r3, #0
|
||||||
|
str r3, [r2], #4
|
||||||
|
|
||||||
|
LoopFillZerobss:
|
||||||
|
ldr r3, = _ebss
|
||||||
|
cmp r2, r3
|
||||||
|
bcc FillZerobss
|
||||||
|
|
||||||
|
/* Call the clock system intitialization function.*/
|
||||||
|
bl SystemInit
|
||||||
|
/* Call static constructors */
|
||||||
|
/* bl __libc_init_array */
|
||||||
|
/* Call the application's entry point.*/
|
||||||
|
bl entry
|
||||||
|
bx lr
|
||||||
|
.size Reset_Handler, .-Reset_Handler
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor receives an
|
||||||
|
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||||
|
* the system state for examination by a debugger.
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
* @retval : None
|
||||||
|
*/
|
||||||
|
.section .text.Default_Handler,"ax",%progbits
|
||||||
|
Default_Handler:
|
||||||
|
Infinite_Loop:
|
||||||
|
b Infinite_Loop
|
||||||
|
.size Default_Handler, .-Default_Handler
|
||||||
|
/******************************************************************************
|
||||||
|
*
|
||||||
|
* The minimal vector table for a Cortex M3. Note that the proper constructs
|
||||||
|
* must be placed on this to ensure that it ends up at physical address
|
||||||
|
* 0x0000.0000.
|
||||||
|
*
|
||||||
|
******************************************************************************/
|
||||||
|
.section .isr_vector,"a",%progbits
|
||||||
|
.type g_pfnVectors, %object
|
||||||
|
.size g_pfnVectors, .-g_pfnVectors
|
||||||
|
|
||||||
|
|
||||||
|
g_pfnVectors:
|
||||||
|
|
||||||
|
.word _estack
|
||||||
|
.word Reset_Handler
|
||||||
|
.word NMI_Handler
|
||||||
|
.word HardFault_Handler
|
||||||
|
.word MemManage_Handler
|
||||||
|
.word BusFault_Handler
|
||||||
|
.word UsageFault_Handler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word SVC_Handler
|
||||||
|
.word DebugMon_Handler
|
||||||
|
.word 0
|
||||||
|
.word PendSV_Handler
|
||||||
|
.word SysTick_Handler
|
||||||
|
.word WWDG_IRQHandler
|
||||||
|
.word PVD_IRQHandler
|
||||||
|
.word TAMPER_IRQHandler
|
||||||
|
.word RTC_IRQHandler
|
||||||
|
.word FLASH_IRQHandler
|
||||||
|
.word RCC_IRQHandler
|
||||||
|
.word EXTI0_IRQHandler
|
||||||
|
.word EXTI1_IRQHandler
|
||||||
|
.word EXTI2_IRQHandler
|
||||||
|
.word EXTI3_IRQHandler
|
||||||
|
.word EXTI4_IRQHandler
|
||||||
|
.word DMA1_Channel1_IRQHandler
|
||||||
|
.word DMA1_Channel2_IRQHandler
|
||||||
|
.word DMA1_Channel3_IRQHandler
|
||||||
|
.word DMA1_Channel4_IRQHandler
|
||||||
|
.word DMA1_Channel5_IRQHandler
|
||||||
|
.word DMA1_Channel6_IRQHandler
|
||||||
|
.word DMA1_Channel7_IRQHandler
|
||||||
|
.word ADC1_IRQHandler
|
||||||
|
.word USB_HP_IRQHandler
|
||||||
|
.word USB_LP_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word EXTI9_5_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word TIM2_IRQHandler
|
||||||
|
.word TIM3_IRQHandler
|
||||||
|
.word TIM4_IRQHandler
|
||||||
|
.word I2C1_EV_IRQHandler
|
||||||
|
.word I2C1_ER_IRQHandler
|
||||||
|
.word I2C2_EV_IRQHandler
|
||||||
|
.word I2C2_ER_IRQHandler
|
||||||
|
.word SPI1_IRQHandler
|
||||||
|
.word SPI2_IRQHandler
|
||||||
|
.word USART1_IRQHandler
|
||||||
|
.word USART2_IRQHandler
|
||||||
|
.word USART3_IRQHandler
|
||||||
|
.word EXTI15_10_IRQHandler
|
||||||
|
.word RTC_Alarm_IRQHandler
|
||||||
|
.word USBWakeUp_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word BootRAM /* @0x108. This is for boot in RAM mode for
|
||||||
|
STM32F10x Medium Density devices. */
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
*
|
||||||
|
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||||
|
* As they are weak aliases, any function with the same name will override
|
||||||
|
* this definition.
|
||||||
|
*
|
||||||
|
*******************************************************************************/
|
||||||
|
|
||||||
|
.weak NMI_Handler
|
||||||
|
.thumb_set NMI_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak HardFault_Handler
|
||||||
|
.thumb_set HardFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak MemManage_Handler
|
||||||
|
.thumb_set MemManage_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak BusFault_Handler
|
||||||
|
.thumb_set BusFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak UsageFault_Handler
|
||||||
|
.thumb_set UsageFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SVC_Handler
|
||||||
|
.thumb_set SVC_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak DebugMon_Handler
|
||||||
|
.thumb_set DebugMon_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak PendSV_Handler
|
||||||
|
.thumb_set PendSV_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SysTick_Handler
|
||||||
|
.thumb_set SysTick_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak WWDG_IRQHandler
|
||||||
|
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak PVD_IRQHandler
|
||||||
|
.thumb_set PVD_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TAMPER_IRQHandler
|
||||||
|
.thumb_set TAMPER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_IRQHandler
|
||||||
|
.thumb_set RTC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FLASH_IRQHandler
|
||||||
|
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RCC_IRQHandler
|
||||||
|
.thumb_set RCC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI0_IRQHandler
|
||||||
|
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI1_IRQHandler
|
||||||
|
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI2_IRQHandler
|
||||||
|
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI3_IRQHandler
|
||||||
|
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI4_IRQHandler
|
||||||
|
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel1_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel2_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel3_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel4_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel5_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel6_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel7_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ADC1_IRQHandler
|
||||||
|
.thumb_set ADC1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USB_HP_IRQHandler
|
||||||
|
.thumb_set USB_HP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USB_LP_IRQHandler
|
||||||
|
.thumb_set USB_LP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI9_5_IRQHandler
|
||||||
|
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM2_IRQHandler
|
||||||
|
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM3_IRQHandler
|
||||||
|
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM4_IRQHandler
|
||||||
|
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_EV_IRQHandler
|
||||||
|
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_ER_IRQHandler
|
||||||
|
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_EV_IRQHandler
|
||||||
|
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_ER_IRQHandler
|
||||||
|
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI1_IRQHandler
|
||||||
|
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI2_IRQHandler
|
||||||
|
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART1_IRQHandler
|
||||||
|
.thumb_set USART1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART2_IRQHandler
|
||||||
|
.thumb_set USART2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART3_IRQHandler
|
||||||
|
.thumb_set USART3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI15_10_IRQHandler
|
||||||
|
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_Alarm_IRQHandler
|
||||||
|
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USBWakeUp_IRQHandler
|
||||||
|
.thumb_set USBWakeUp_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
||||||
|
|
@ -0,0 +1,363 @@
|
||||||
|
/**
|
||||||
|
*************** (C) COPYRIGHT 2017 STMicroelectronics ************************
|
||||||
|
* @file startup_stm32f103x6.s
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V4.2.0
|
||||||
|
* @date 31-March-2017
|
||||||
|
* @brief STM32F103x6 Devices vector table for Atollic toolchain.
|
||||||
|
* This module performs:
|
||||||
|
* - Set the initial SP
|
||||||
|
* - Set the initial PC == Reset_Handler,
|
||||||
|
* - Set the vector table entries with the exceptions ISR address
|
||||||
|
* - Configure the clock system
|
||||||
|
* - Branches to main in the C library (which eventually
|
||||||
|
* calls main()).
|
||||||
|
* After Reset the Cortex-M3 processor is in Thread mode,
|
||||||
|
* priority is Privileged, and the Stack is set to Main.
|
||||||
|
******************************************************************************
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
.syntax unified
|
||||||
|
.cpu cortex-m3
|
||||||
|
.fpu softvfp
|
||||||
|
.thumb
|
||||||
|
|
||||||
|
.global g_pfnVectors
|
||||||
|
.global Default_Handler
|
||||||
|
|
||||||
|
/* start address for the initialization values of the .data section.
|
||||||
|
defined in linker script */
|
||||||
|
.word _sidata
|
||||||
|
/* start address for the .data section. defined in linker script */
|
||||||
|
.word _sdata
|
||||||
|
/* end address for the .data section. defined in linker script */
|
||||||
|
.word _edata
|
||||||
|
/* start address for the .bss section. defined in linker script */
|
||||||
|
.word _sbss
|
||||||
|
/* end address for the .bss section. defined in linker script */
|
||||||
|
.word _ebss
|
||||||
|
|
||||||
|
.equ BootRAM, 0xF108F85F
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor first
|
||||||
|
* starts execution following a reset event. Only the absolutely
|
||||||
|
* necessary set is performed, after which the application
|
||||||
|
* supplied main() routine is called.
|
||||||
|
* @param None
|
||||||
|
* @retval : None
|
||||||
|
*/
|
||||||
|
|
||||||
|
.section .text.Reset_Handler
|
||||||
|
.weak Reset_Handler
|
||||||
|
.type Reset_Handler, %function
|
||||||
|
Reset_Handler:
|
||||||
|
|
||||||
|
/* Copy the data segment initializers from flash to SRAM */
|
||||||
|
movs r1, #0
|
||||||
|
b LoopCopyDataInit
|
||||||
|
|
||||||
|
CopyDataInit:
|
||||||
|
ldr r3, =_sidata
|
||||||
|
ldr r3, [r3, r1]
|
||||||
|
str r3, [r0, r1]
|
||||||
|
adds r1, r1, #4
|
||||||
|
|
||||||
|
LoopCopyDataInit:
|
||||||
|
ldr r0, =_sdata
|
||||||
|
ldr r3, =_edata
|
||||||
|
adds r2, r0, r1
|
||||||
|
cmp r2, r3
|
||||||
|
bcc CopyDataInit
|
||||||
|
ldr r2, =_sbss
|
||||||
|
b LoopFillZerobss
|
||||||
|
/* Zero fill the bss segment. */
|
||||||
|
FillZerobss:
|
||||||
|
movs r3, #0
|
||||||
|
str r3, [r2], #4
|
||||||
|
|
||||||
|
LoopFillZerobss:
|
||||||
|
ldr r3, = _ebss
|
||||||
|
cmp r2, r3
|
||||||
|
bcc FillZerobss
|
||||||
|
|
||||||
|
/* Call the clock system intitialization function.*/
|
||||||
|
bl SystemInit
|
||||||
|
/* Call static constructors */
|
||||||
|
/* bl __libc_init_array */
|
||||||
|
/* Call the application's entry point.*/
|
||||||
|
bl entry
|
||||||
|
bx lr
|
||||||
|
.size Reset_Handler, .-Reset_Handler
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor receives an
|
||||||
|
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||||
|
* the system state for examination by a debugger.
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
* @retval : None
|
||||||
|
*/
|
||||||
|
.section .text.Default_Handler,"ax",%progbits
|
||||||
|
Default_Handler:
|
||||||
|
Infinite_Loop:
|
||||||
|
b Infinite_Loop
|
||||||
|
.size Default_Handler, .-Default_Handler
|
||||||
|
/******************************************************************************
|
||||||
|
*
|
||||||
|
* The minimal vector table for a Cortex M3. Note that the proper constructs
|
||||||
|
* must be placed on this to ensure that it ends up at physical address
|
||||||
|
* 0x0000.0000.
|
||||||
|
*
|
||||||
|
******************************************************************************/
|
||||||
|
.section .isr_vector,"a",%progbits
|
||||||
|
.type g_pfnVectors, %object
|
||||||
|
.size g_pfnVectors, .-g_pfnVectors
|
||||||
|
|
||||||
|
|
||||||
|
g_pfnVectors:
|
||||||
|
|
||||||
|
.word _estack
|
||||||
|
.word Reset_Handler
|
||||||
|
.word NMI_Handler
|
||||||
|
.word HardFault_Handler
|
||||||
|
.word MemManage_Handler
|
||||||
|
.word BusFault_Handler
|
||||||
|
.word UsageFault_Handler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word SVC_Handler
|
||||||
|
.word DebugMon_Handler
|
||||||
|
.word 0
|
||||||
|
.word PendSV_Handler
|
||||||
|
.word SysTick_Handler
|
||||||
|
.word WWDG_IRQHandler
|
||||||
|
.word PVD_IRQHandler
|
||||||
|
.word TAMPER_IRQHandler
|
||||||
|
.word RTC_IRQHandler
|
||||||
|
.word FLASH_IRQHandler
|
||||||
|
.word RCC_IRQHandler
|
||||||
|
.word EXTI0_IRQHandler
|
||||||
|
.word EXTI1_IRQHandler
|
||||||
|
.word EXTI2_IRQHandler
|
||||||
|
.word EXTI3_IRQHandler
|
||||||
|
.word EXTI4_IRQHandler
|
||||||
|
.word DMA1_Channel1_IRQHandler
|
||||||
|
.word DMA1_Channel2_IRQHandler
|
||||||
|
.word DMA1_Channel3_IRQHandler
|
||||||
|
.word DMA1_Channel4_IRQHandler
|
||||||
|
.word DMA1_Channel5_IRQHandler
|
||||||
|
.word DMA1_Channel6_IRQHandler
|
||||||
|
.word DMA1_Channel7_IRQHandler
|
||||||
|
.word ADC1_2_IRQHandler
|
||||||
|
.word USB_HP_CAN1_TX_IRQHandler
|
||||||
|
.word USB_LP_CAN1_RX0_IRQHandler
|
||||||
|
.word CAN1_RX1_IRQHandler
|
||||||
|
.word CAN1_SCE_IRQHandler
|
||||||
|
.word EXTI9_5_IRQHandler
|
||||||
|
.word TIM1_BRK_IRQHandler
|
||||||
|
.word TIM1_UP_IRQHandler
|
||||||
|
.word TIM1_TRG_COM_IRQHandler
|
||||||
|
.word TIM1_CC_IRQHandler
|
||||||
|
.word TIM2_IRQHandler
|
||||||
|
.word TIM3_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word I2C1_EV_IRQHandler
|
||||||
|
.word I2C1_ER_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word SPI1_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word USART1_IRQHandler
|
||||||
|
.word USART2_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word EXTI15_10_IRQHandler
|
||||||
|
.word RTC_Alarm_IRQHandler
|
||||||
|
.word USBWakeUp_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word BootRAM /* @0x108. This is for boot in RAM mode for
|
||||||
|
STM32F10x Low Density devices.*/
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
*
|
||||||
|
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||||
|
* As they are weak aliases, any function with the same name will override
|
||||||
|
* this definition.
|
||||||
|
*
|
||||||
|
*******************************************************************************/
|
||||||
|
|
||||||
|
.weak NMI_Handler
|
||||||
|
.thumb_set NMI_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak HardFault_Handler
|
||||||
|
.thumb_set HardFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak MemManage_Handler
|
||||||
|
.thumb_set MemManage_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak BusFault_Handler
|
||||||
|
.thumb_set BusFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak UsageFault_Handler
|
||||||
|
.thumb_set UsageFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SVC_Handler
|
||||||
|
.thumb_set SVC_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak DebugMon_Handler
|
||||||
|
.thumb_set DebugMon_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak PendSV_Handler
|
||||||
|
.thumb_set PendSV_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SysTick_Handler
|
||||||
|
.thumb_set SysTick_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak WWDG_IRQHandler
|
||||||
|
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak PVD_IRQHandler
|
||||||
|
.thumb_set PVD_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TAMPER_IRQHandler
|
||||||
|
.thumb_set TAMPER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_IRQHandler
|
||||||
|
.thumb_set RTC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FLASH_IRQHandler
|
||||||
|
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RCC_IRQHandler
|
||||||
|
.thumb_set RCC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI0_IRQHandler
|
||||||
|
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI1_IRQHandler
|
||||||
|
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI2_IRQHandler
|
||||||
|
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI3_IRQHandler
|
||||||
|
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI4_IRQHandler
|
||||||
|
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel1_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel2_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel3_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel4_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel5_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel6_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel7_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ADC1_2_IRQHandler
|
||||||
|
.thumb_set ADC1_2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USB_HP_CAN1_TX_IRQHandler
|
||||||
|
.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USB_LP_CAN1_RX0_IRQHandler
|
||||||
|
.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN1_RX1_IRQHandler
|
||||||
|
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN1_SCE_IRQHandler
|
||||||
|
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI9_5_IRQHandler
|
||||||
|
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_BRK_IRQHandler
|
||||||
|
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_UP_IRQHandler
|
||||||
|
.thumb_set TIM1_UP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_TRG_COM_IRQHandler
|
||||||
|
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_CC_IRQHandler
|
||||||
|
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM2_IRQHandler
|
||||||
|
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM3_IRQHandler
|
||||||
|
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_EV_IRQHandler
|
||||||
|
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_ER_IRQHandler
|
||||||
|
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI1_IRQHandler
|
||||||
|
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART1_IRQHandler
|
||||||
|
.thumb_set USART1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART2_IRQHandler
|
||||||
|
.thumb_set USART2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI15_10_IRQHandler
|
||||||
|
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_Alarm_IRQHandler
|
||||||
|
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USBWakeUp_IRQHandler
|
||||||
|
.thumb_set USBWakeUp_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,379 @@
|
||||||
|
/**
|
||||||
|
*************** (C) COPYRIGHT 2017 STMicroelectronics ************************
|
||||||
|
* @file startup_stm32f103xb.s
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V4.2.0
|
||||||
|
* @date 31-March-2017
|
||||||
|
* @brief STM32F103xB Devices vector table for Atollic toolchain.
|
||||||
|
* This module performs:
|
||||||
|
* - Set the initial SP
|
||||||
|
* - Set the initial PC == Reset_Handler,
|
||||||
|
* - Set the vector table entries with the exceptions ISR address
|
||||||
|
* - Configure the clock system
|
||||||
|
* - Branches to main in the C library (which eventually
|
||||||
|
* calls main()).
|
||||||
|
* After Reset the Cortex-M3 processor is in Thread mode,
|
||||||
|
* priority is Privileged, and the Stack is set to Main.
|
||||||
|
******************************************************************************
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
.syntax unified
|
||||||
|
.cpu cortex-m3
|
||||||
|
.fpu softvfp
|
||||||
|
.thumb
|
||||||
|
|
||||||
|
.global g_pfnVectors
|
||||||
|
.global Default_Handler
|
||||||
|
|
||||||
|
/* start address for the initialization values of the .data section.
|
||||||
|
defined in linker script */
|
||||||
|
.word _sidata
|
||||||
|
/* start address for the .data section. defined in linker script */
|
||||||
|
.word _sdata
|
||||||
|
/* end address for the .data section. defined in linker script */
|
||||||
|
.word _edata
|
||||||
|
/* start address for the .bss section. defined in linker script */
|
||||||
|
.word _sbss
|
||||||
|
/* end address for the .bss section. defined in linker script */
|
||||||
|
.word _ebss
|
||||||
|
|
||||||
|
.equ BootRAM, 0xF108F85F
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor first
|
||||||
|
* starts execution following a reset event. Only the absolutely
|
||||||
|
* necessary set is performed, after which the application
|
||||||
|
* supplied main() routine is called.
|
||||||
|
* @param None
|
||||||
|
* @retval : None
|
||||||
|
*/
|
||||||
|
|
||||||
|
.section .text.Reset_Handler
|
||||||
|
.weak Reset_Handler
|
||||||
|
.type Reset_Handler, %function
|
||||||
|
Reset_Handler:
|
||||||
|
|
||||||
|
/* Copy the data segment initializers from flash to SRAM */
|
||||||
|
movs r1, #0
|
||||||
|
b LoopCopyDataInit
|
||||||
|
|
||||||
|
CopyDataInit:
|
||||||
|
ldr r3, =_sidata
|
||||||
|
ldr r3, [r3, r1]
|
||||||
|
str r3, [r0, r1]
|
||||||
|
adds r1, r1, #4
|
||||||
|
|
||||||
|
LoopCopyDataInit:
|
||||||
|
ldr r0, =_sdata
|
||||||
|
ldr r3, =_edata
|
||||||
|
adds r2, r0, r1
|
||||||
|
cmp r2, r3
|
||||||
|
bcc CopyDataInit
|
||||||
|
ldr r2, =_sbss
|
||||||
|
b LoopFillZerobss
|
||||||
|
/* Zero fill the bss segment. */
|
||||||
|
FillZerobss:
|
||||||
|
movs r3, #0
|
||||||
|
str r3, [r2], #4
|
||||||
|
|
||||||
|
LoopFillZerobss:
|
||||||
|
ldr r3, = _ebss
|
||||||
|
cmp r2, r3
|
||||||
|
bcc FillZerobss
|
||||||
|
|
||||||
|
/* Call the clock system intitialization function.*/
|
||||||
|
bl SystemInit
|
||||||
|
/* Call static constructors */
|
||||||
|
/* bl __libc_init_array */
|
||||||
|
/* Call the application's entry point.*/
|
||||||
|
bl entry
|
||||||
|
bx lr
|
||||||
|
.size Reset_Handler, .-Reset_Handler
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor receives an
|
||||||
|
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||||
|
* the system state for examination by a debugger.
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
* @retval : None
|
||||||
|
*/
|
||||||
|
.section .text.Default_Handler,"ax",%progbits
|
||||||
|
Default_Handler:
|
||||||
|
Infinite_Loop:
|
||||||
|
b Infinite_Loop
|
||||||
|
.size Default_Handler, .-Default_Handler
|
||||||
|
/******************************************************************************
|
||||||
|
*
|
||||||
|
* The minimal vector table for a Cortex M3. Note that the proper constructs
|
||||||
|
* must be placed on this to ensure that it ends up at physical address
|
||||||
|
* 0x0000.0000.
|
||||||
|
*
|
||||||
|
******************************************************************************/
|
||||||
|
.section .isr_vector,"a",%progbits
|
||||||
|
.type g_pfnVectors, %object
|
||||||
|
.size g_pfnVectors, .-g_pfnVectors
|
||||||
|
|
||||||
|
|
||||||
|
g_pfnVectors:
|
||||||
|
|
||||||
|
.word _estack
|
||||||
|
.word Reset_Handler
|
||||||
|
.word NMI_Handler
|
||||||
|
.word HardFault_Handler
|
||||||
|
.word MemManage_Handler
|
||||||
|
.word BusFault_Handler
|
||||||
|
.word UsageFault_Handler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word SVC_Handler
|
||||||
|
.word DebugMon_Handler
|
||||||
|
.word 0
|
||||||
|
.word PendSV_Handler
|
||||||
|
.word SysTick_Handler
|
||||||
|
.word WWDG_IRQHandler
|
||||||
|
.word PVD_IRQHandler
|
||||||
|
.word TAMPER_IRQHandler
|
||||||
|
.word RTC_IRQHandler
|
||||||
|
.word FLASH_IRQHandler
|
||||||
|
.word RCC_IRQHandler
|
||||||
|
.word EXTI0_IRQHandler
|
||||||
|
.word EXTI1_IRQHandler
|
||||||
|
.word EXTI2_IRQHandler
|
||||||
|
.word EXTI3_IRQHandler
|
||||||
|
.word EXTI4_IRQHandler
|
||||||
|
.word DMA1_Channel1_IRQHandler
|
||||||
|
.word DMA1_Channel2_IRQHandler
|
||||||
|
.word DMA1_Channel3_IRQHandler
|
||||||
|
.word DMA1_Channel4_IRQHandler
|
||||||
|
.word DMA1_Channel5_IRQHandler
|
||||||
|
.word DMA1_Channel6_IRQHandler
|
||||||
|
.word DMA1_Channel7_IRQHandler
|
||||||
|
.word ADC1_2_IRQHandler
|
||||||
|
.word USB_HP_CAN1_TX_IRQHandler
|
||||||
|
.word USB_LP_CAN1_RX0_IRQHandler
|
||||||
|
.word CAN1_RX1_IRQHandler
|
||||||
|
.word CAN1_SCE_IRQHandler
|
||||||
|
.word EXTI9_5_IRQHandler
|
||||||
|
.word TIM1_BRK_IRQHandler
|
||||||
|
.word TIM1_UP_IRQHandler
|
||||||
|
.word TIM1_TRG_COM_IRQHandler
|
||||||
|
.word TIM1_CC_IRQHandler
|
||||||
|
.word TIM2_IRQHandler
|
||||||
|
.word TIM3_IRQHandler
|
||||||
|
.word TIM4_IRQHandler
|
||||||
|
.word I2C1_EV_IRQHandler
|
||||||
|
.word I2C1_ER_IRQHandler
|
||||||
|
.word I2C2_EV_IRQHandler
|
||||||
|
.word I2C2_ER_IRQHandler
|
||||||
|
.word SPI1_IRQHandler
|
||||||
|
.word SPI2_IRQHandler
|
||||||
|
.word USART1_IRQHandler
|
||||||
|
.word USART2_IRQHandler
|
||||||
|
.word USART3_IRQHandler
|
||||||
|
.word EXTI15_10_IRQHandler
|
||||||
|
.word RTC_Alarm_IRQHandler
|
||||||
|
.word USBWakeUp_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word BootRAM /* @0x108. This is for boot in RAM mode for
|
||||||
|
STM32F10x Medium Density devices. */
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
*
|
||||||
|
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||||
|
* As they are weak aliases, any function with the same name will override
|
||||||
|
* this definition.
|
||||||
|
*
|
||||||
|
*******************************************************************************/
|
||||||
|
|
||||||
|
.weak NMI_Handler
|
||||||
|
.thumb_set NMI_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak HardFault_Handler
|
||||||
|
.thumb_set HardFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak MemManage_Handler
|
||||||
|
.thumb_set MemManage_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak BusFault_Handler
|
||||||
|
.thumb_set BusFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak UsageFault_Handler
|
||||||
|
.thumb_set UsageFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SVC_Handler
|
||||||
|
.thumb_set SVC_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak DebugMon_Handler
|
||||||
|
.thumb_set DebugMon_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak PendSV_Handler
|
||||||
|
.thumb_set PendSV_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SysTick_Handler
|
||||||
|
.thumb_set SysTick_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak WWDG_IRQHandler
|
||||||
|
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak PVD_IRQHandler
|
||||||
|
.thumb_set PVD_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TAMPER_IRQHandler
|
||||||
|
.thumb_set TAMPER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_IRQHandler
|
||||||
|
.thumb_set RTC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FLASH_IRQHandler
|
||||||
|
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RCC_IRQHandler
|
||||||
|
.thumb_set RCC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI0_IRQHandler
|
||||||
|
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI1_IRQHandler
|
||||||
|
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI2_IRQHandler
|
||||||
|
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI3_IRQHandler
|
||||||
|
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI4_IRQHandler
|
||||||
|
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel1_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel2_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel3_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel4_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel5_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel6_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel7_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ADC1_2_IRQHandler
|
||||||
|
.thumb_set ADC1_2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USB_HP_CAN1_TX_IRQHandler
|
||||||
|
.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USB_LP_CAN1_RX0_IRQHandler
|
||||||
|
.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN1_RX1_IRQHandler
|
||||||
|
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN1_SCE_IRQHandler
|
||||||
|
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI9_5_IRQHandler
|
||||||
|
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_BRK_IRQHandler
|
||||||
|
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_UP_IRQHandler
|
||||||
|
.thumb_set TIM1_UP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_TRG_COM_IRQHandler
|
||||||
|
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_CC_IRQHandler
|
||||||
|
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM2_IRQHandler
|
||||||
|
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM3_IRQHandler
|
||||||
|
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM4_IRQHandler
|
||||||
|
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_EV_IRQHandler
|
||||||
|
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_ER_IRQHandler
|
||||||
|
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_EV_IRQHandler
|
||||||
|
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_ER_IRQHandler
|
||||||
|
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI1_IRQHandler
|
||||||
|
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI2_IRQHandler
|
||||||
|
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART1_IRQHandler
|
||||||
|
.thumb_set USART1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART2_IRQHandler
|
||||||
|
.thumb_set USART2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART3_IRQHandler
|
||||||
|
.thumb_set USART3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI15_10_IRQHandler
|
||||||
|
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_Alarm_IRQHandler
|
||||||
|
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USBWakeUp_IRQHandler
|
||||||
|
.thumb_set USBWakeUp_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
||||||
|
|
@ -0,0 +1,485 @@
|
||||||
|
/**
|
||||||
|
*************** (C) COPYRIGHT 2017 STMicroelectronics ************************
|
||||||
|
* @file startup_stm32f103xe.s
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V4.2.0
|
||||||
|
* @date 31-March-2017
|
||||||
|
* @brief STM32F103xE Devices vector table for Atollic toolchain.
|
||||||
|
* This module performs:
|
||||||
|
* - Set the initial SP
|
||||||
|
* - Set the initial PC == Reset_Handler,
|
||||||
|
* - Set the vector table entries with the exceptions ISR address
|
||||||
|
* - Configure the clock system
|
||||||
|
* - Configure external SRAM mounted on STM3210E-EVAL board
|
||||||
|
* to be used as data memory (optional, to be enabled by user)
|
||||||
|
* - Branches to main in the C library (which eventually
|
||||||
|
* calls main()).
|
||||||
|
* After Reset the Cortex-M3 processor is in Thread mode,
|
||||||
|
* priority is Privileged, and the Stack is set to Main.
|
||||||
|
******************************************************************************
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
.syntax unified
|
||||||
|
.cpu cortex-m3
|
||||||
|
.fpu softvfp
|
||||||
|
.thumb
|
||||||
|
|
||||||
|
.global g_pfnVectors
|
||||||
|
.global Default_Handler
|
||||||
|
|
||||||
|
/* start address for the initialization values of the .data section.
|
||||||
|
defined in linker script */
|
||||||
|
.word _sidata
|
||||||
|
/* start address for the .data section. defined in linker script */
|
||||||
|
.word _sdata
|
||||||
|
/* end address for the .data section. defined in linker script */
|
||||||
|
.word _edata
|
||||||
|
/* start address for the .bss section. defined in linker script */
|
||||||
|
.word _sbss
|
||||||
|
/* end address for the .bss section. defined in linker script */
|
||||||
|
.word _ebss
|
||||||
|
|
||||||
|
.equ BootRAM, 0xF1E0F85F
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor first
|
||||||
|
* starts execution following a reset event. Only the absolutely
|
||||||
|
* necessary set is performed, after which the application
|
||||||
|
* supplied main() routine is called.
|
||||||
|
* @param None
|
||||||
|
* @retval : None
|
||||||
|
*/
|
||||||
|
|
||||||
|
.section .text.Reset_Handler
|
||||||
|
.weak Reset_Handler
|
||||||
|
.type Reset_Handler, %function
|
||||||
|
Reset_Handler:
|
||||||
|
|
||||||
|
/* Copy the data segment initializers from flash to SRAM */
|
||||||
|
movs r1, #0
|
||||||
|
b LoopCopyDataInit
|
||||||
|
|
||||||
|
CopyDataInit:
|
||||||
|
ldr r3, =_sidata
|
||||||
|
ldr r3, [r3, r1]
|
||||||
|
str r3, [r0, r1]
|
||||||
|
adds r1, r1, #4
|
||||||
|
|
||||||
|
LoopCopyDataInit:
|
||||||
|
ldr r0, =_sdata
|
||||||
|
ldr r3, =_edata
|
||||||
|
adds r2, r0, r1
|
||||||
|
cmp r2, r3
|
||||||
|
bcc CopyDataInit
|
||||||
|
ldr r2, =_sbss
|
||||||
|
b LoopFillZerobss
|
||||||
|
/* Zero fill the bss segment. */
|
||||||
|
FillZerobss:
|
||||||
|
movs r3, #0
|
||||||
|
str r3, [r2], #4
|
||||||
|
|
||||||
|
LoopFillZerobss:
|
||||||
|
ldr r3, = _ebss
|
||||||
|
cmp r2, r3
|
||||||
|
bcc FillZerobss
|
||||||
|
|
||||||
|
/* Call the clock system intitialization function.*/
|
||||||
|
bl SystemInit
|
||||||
|
/* Call static constructors */
|
||||||
|
/* bl __libc_init_array */
|
||||||
|
/* Call the application's entry point.*/
|
||||||
|
bl entry
|
||||||
|
bx lr
|
||||||
|
.size Reset_Handler, .-Reset_Handler
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor receives an
|
||||||
|
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||||
|
* the system state for examination by a debugger.
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
* @retval : None
|
||||||
|
*/
|
||||||
|
.section .text.Default_Handler,"ax",%progbits
|
||||||
|
Default_Handler:
|
||||||
|
Infinite_Loop:
|
||||||
|
b Infinite_Loop
|
||||||
|
.size Default_Handler, .-Default_Handler
|
||||||
|
/******************************************************************************
|
||||||
|
*
|
||||||
|
* The minimal vector table for a Cortex M3. Note that the proper constructs
|
||||||
|
* must be placed on this to ensure that it ends up at physical address
|
||||||
|
* 0x0000.0000.
|
||||||
|
*
|
||||||
|
******************************************************************************/
|
||||||
|
.section .isr_vector,"a",%progbits
|
||||||
|
.type g_pfnVectors, %object
|
||||||
|
.size g_pfnVectors, .-g_pfnVectors
|
||||||
|
|
||||||
|
|
||||||
|
g_pfnVectors:
|
||||||
|
|
||||||
|
.word _estack
|
||||||
|
.word Reset_Handler
|
||||||
|
.word NMI_Handler
|
||||||
|
.word HardFault_Handler
|
||||||
|
.word MemManage_Handler
|
||||||
|
.word BusFault_Handler
|
||||||
|
.word UsageFault_Handler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word SVC_Handler
|
||||||
|
.word DebugMon_Handler
|
||||||
|
.word 0
|
||||||
|
.word PendSV_Handler
|
||||||
|
.word SysTick_Handler
|
||||||
|
.word WWDG_IRQHandler
|
||||||
|
.word PVD_IRQHandler
|
||||||
|
.word TAMPER_IRQHandler
|
||||||
|
.word RTC_IRQHandler
|
||||||
|
.word FLASH_IRQHandler
|
||||||
|
.word RCC_IRQHandler
|
||||||
|
.word EXTI0_IRQHandler
|
||||||
|
.word EXTI1_IRQHandler
|
||||||
|
.word EXTI2_IRQHandler
|
||||||
|
.word EXTI3_IRQHandler
|
||||||
|
.word EXTI4_IRQHandler
|
||||||
|
.word DMA1_Channel1_IRQHandler
|
||||||
|
.word DMA1_Channel2_IRQHandler
|
||||||
|
.word DMA1_Channel3_IRQHandler
|
||||||
|
.word DMA1_Channel4_IRQHandler
|
||||||
|
.word DMA1_Channel5_IRQHandler
|
||||||
|
.word DMA1_Channel6_IRQHandler
|
||||||
|
.word DMA1_Channel7_IRQHandler
|
||||||
|
.word ADC1_2_IRQHandler
|
||||||
|
.word USB_HP_CAN1_TX_IRQHandler
|
||||||
|
.word USB_LP_CAN1_RX0_IRQHandler
|
||||||
|
.word CAN1_RX1_IRQHandler
|
||||||
|
.word CAN1_SCE_IRQHandler
|
||||||
|
.word EXTI9_5_IRQHandler
|
||||||
|
.word TIM1_BRK_IRQHandler
|
||||||
|
.word TIM1_UP_IRQHandler
|
||||||
|
.word TIM1_TRG_COM_IRQHandler
|
||||||
|
.word TIM1_CC_IRQHandler
|
||||||
|
.word TIM2_IRQHandler
|
||||||
|
.word TIM3_IRQHandler
|
||||||
|
.word TIM4_IRQHandler
|
||||||
|
.word I2C1_EV_IRQHandler
|
||||||
|
.word I2C1_ER_IRQHandler
|
||||||
|
.word I2C2_EV_IRQHandler
|
||||||
|
.word I2C2_ER_IRQHandler
|
||||||
|
.word SPI1_IRQHandler
|
||||||
|
.word SPI2_IRQHandler
|
||||||
|
.word USART1_IRQHandler
|
||||||
|
.word USART2_IRQHandler
|
||||||
|
.word USART3_IRQHandler
|
||||||
|
.word EXTI15_10_IRQHandler
|
||||||
|
.word RTC_Alarm_IRQHandler
|
||||||
|
.word USBWakeUp_IRQHandler
|
||||||
|
.word TIM8_BRK_IRQHandler
|
||||||
|
.word TIM8_UP_IRQHandler
|
||||||
|
.word TIM8_TRG_COM_IRQHandler
|
||||||
|
.word TIM8_CC_IRQHandler
|
||||||
|
.word ADC3_IRQHandler
|
||||||
|
.word FSMC_IRQHandler
|
||||||
|
.word SDIO_IRQHandler
|
||||||
|
.word TIM5_IRQHandler
|
||||||
|
.word SPI3_IRQHandler
|
||||||
|
.word UART4_IRQHandler
|
||||||
|
.word UART5_IRQHandler
|
||||||
|
.word TIM6_IRQHandler
|
||||||
|
.word TIM7_IRQHandler
|
||||||
|
.word DMA2_Channel1_IRQHandler
|
||||||
|
.word DMA2_Channel2_IRQHandler
|
||||||
|
.word DMA2_Channel3_IRQHandler
|
||||||
|
.word DMA2_Channel4_5_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word BootRAM /* @0x1E0. This is for boot in RAM mode for
|
||||||
|
STM32F10x High Density devices. */
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
*
|
||||||
|
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||||
|
* As they are weak aliases, any function with the same name will override
|
||||||
|
* this definition.
|
||||||
|
*
|
||||||
|
*******************************************************************************/
|
||||||
|
|
||||||
|
.weak NMI_Handler
|
||||||
|
.thumb_set NMI_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak HardFault_Handler
|
||||||
|
.thumb_set HardFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak MemManage_Handler
|
||||||
|
.thumb_set MemManage_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak BusFault_Handler
|
||||||
|
.thumb_set BusFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak UsageFault_Handler
|
||||||
|
.thumb_set UsageFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SVC_Handler
|
||||||
|
.thumb_set SVC_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak DebugMon_Handler
|
||||||
|
.thumb_set DebugMon_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak PendSV_Handler
|
||||||
|
.thumb_set PendSV_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SysTick_Handler
|
||||||
|
.thumb_set SysTick_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak WWDG_IRQHandler
|
||||||
|
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak PVD_IRQHandler
|
||||||
|
.thumb_set PVD_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TAMPER_IRQHandler
|
||||||
|
.thumb_set TAMPER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_IRQHandler
|
||||||
|
.thumb_set RTC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FLASH_IRQHandler
|
||||||
|
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RCC_IRQHandler
|
||||||
|
.thumb_set RCC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI0_IRQHandler
|
||||||
|
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI1_IRQHandler
|
||||||
|
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI2_IRQHandler
|
||||||
|
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI3_IRQHandler
|
||||||
|
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI4_IRQHandler
|
||||||
|
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel1_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel2_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel3_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel4_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel5_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel6_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel7_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ADC1_2_IRQHandler
|
||||||
|
.thumb_set ADC1_2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USB_HP_CAN1_TX_IRQHandler
|
||||||
|
.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USB_LP_CAN1_RX0_IRQHandler
|
||||||
|
.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN1_RX1_IRQHandler
|
||||||
|
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN1_SCE_IRQHandler
|
||||||
|
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI9_5_IRQHandler
|
||||||
|
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_BRK_IRQHandler
|
||||||
|
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_UP_IRQHandler
|
||||||
|
.thumb_set TIM1_UP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_TRG_COM_IRQHandler
|
||||||
|
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_CC_IRQHandler
|
||||||
|
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM2_IRQHandler
|
||||||
|
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM3_IRQHandler
|
||||||
|
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM4_IRQHandler
|
||||||
|
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_EV_IRQHandler
|
||||||
|
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_ER_IRQHandler
|
||||||
|
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_EV_IRQHandler
|
||||||
|
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_ER_IRQHandler
|
||||||
|
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI1_IRQHandler
|
||||||
|
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI2_IRQHandler
|
||||||
|
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART1_IRQHandler
|
||||||
|
.thumb_set USART1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART2_IRQHandler
|
||||||
|
.thumb_set USART2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART3_IRQHandler
|
||||||
|
.thumb_set USART3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI15_10_IRQHandler
|
||||||
|
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_Alarm_IRQHandler
|
||||||
|
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USBWakeUp_IRQHandler
|
||||||
|
.thumb_set USBWakeUp_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM8_BRK_IRQHandler
|
||||||
|
.thumb_set TIM8_BRK_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM8_UP_IRQHandler
|
||||||
|
.thumb_set TIM8_UP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM8_TRG_COM_IRQHandler
|
||||||
|
.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM8_CC_IRQHandler
|
||||||
|
.thumb_set TIM8_CC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ADC3_IRQHandler
|
||||||
|
.thumb_set ADC3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FSMC_IRQHandler
|
||||||
|
.thumb_set FSMC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SDIO_IRQHandler
|
||||||
|
.thumb_set SDIO_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM5_IRQHandler
|
||||||
|
.thumb_set TIM5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI3_IRQHandler
|
||||||
|
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART4_IRQHandler
|
||||||
|
.thumb_set UART4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART5_IRQHandler
|
||||||
|
.thumb_set UART5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM6_IRQHandler
|
||||||
|
.thumb_set TIM6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM7_IRQHandler
|
||||||
|
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Channel1_IRQHandler
|
||||||
|
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Channel2_IRQHandler
|
||||||
|
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Channel3_IRQHandler
|
||||||
|
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Channel4_5_IRQHandler
|
||||||
|
.thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,482 @@
|
||||||
|
/**
|
||||||
|
*************** (C) COPYRIGHT 2017 STMicroelectronics ************************
|
||||||
|
* @file startup_stm32f103xb.s
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V4.2.0
|
||||||
|
* @date 31-March-2017
|
||||||
|
* @brief STM32F103xB Devices vector table for Atollic toolchain.
|
||||||
|
* This module performs:
|
||||||
|
* - Set the initial SP
|
||||||
|
* - Set the initial PC == Reset_Handler,
|
||||||
|
* - Set the vector table entries with the exceptions ISR address
|
||||||
|
* - Configure the clock system
|
||||||
|
* - Branches to main in the C library (which eventually
|
||||||
|
* calls main()).
|
||||||
|
* After Reset the Cortex-M3 processor is in Thread mode,
|
||||||
|
* priority is Privileged, and the Stack is set to Main.
|
||||||
|
******************************************************************************
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
.syntax unified
|
||||||
|
.cpu cortex-m3
|
||||||
|
.fpu softvfp
|
||||||
|
.thumb
|
||||||
|
|
||||||
|
.global g_pfnVectors
|
||||||
|
.global Default_Handler
|
||||||
|
|
||||||
|
/* start address for the initialization values of the .data section.
|
||||||
|
defined in linker script */
|
||||||
|
.word _sidata
|
||||||
|
/* start address for the .data section. defined in linker script */
|
||||||
|
.word _sdata
|
||||||
|
/* end address for the .data section. defined in linker script */
|
||||||
|
.word _edata
|
||||||
|
/* start address for the .bss section. defined in linker script */
|
||||||
|
.word _sbss
|
||||||
|
/* end address for the .bss section. defined in linker script */
|
||||||
|
.word _ebss
|
||||||
|
|
||||||
|
.equ BootRAM, 0xF1E0F85F
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor first
|
||||||
|
* starts execution following a reset event. Only the absolutely
|
||||||
|
* necessary set is performed, after which the application
|
||||||
|
* supplied main() routine is called.
|
||||||
|
* @param None
|
||||||
|
* @retval : None
|
||||||
|
*/
|
||||||
|
|
||||||
|
.section .text.Reset_Handler
|
||||||
|
.weak Reset_Handler
|
||||||
|
.type Reset_Handler, %function
|
||||||
|
Reset_Handler:
|
||||||
|
|
||||||
|
/* Copy the data segment initializers from flash to SRAM */
|
||||||
|
movs r1, #0
|
||||||
|
b LoopCopyDataInit
|
||||||
|
|
||||||
|
CopyDataInit:
|
||||||
|
ldr r3, =_sidata
|
||||||
|
ldr r3, [r3, r1]
|
||||||
|
str r3, [r0, r1]
|
||||||
|
adds r1, r1, #4
|
||||||
|
|
||||||
|
LoopCopyDataInit:
|
||||||
|
ldr r0, =_sdata
|
||||||
|
ldr r3, =_edata
|
||||||
|
adds r2, r0, r1
|
||||||
|
cmp r2, r3
|
||||||
|
bcc CopyDataInit
|
||||||
|
ldr r2, =_sbss
|
||||||
|
b LoopFillZerobss
|
||||||
|
|
||||||
|
/* Zero fill the bss segment. */
|
||||||
|
FillZerobss:
|
||||||
|
movs r3, #0
|
||||||
|
str r3, [r2], #4
|
||||||
|
|
||||||
|
LoopFillZerobss:
|
||||||
|
ldr r3, = _ebss
|
||||||
|
cmp r2, r3
|
||||||
|
bcc FillZerobss
|
||||||
|
|
||||||
|
/* Call the clock system intitialization function.*/
|
||||||
|
bl SystemInit
|
||||||
|
/* Call static constructors */
|
||||||
|
/* bl __libc_init_array */
|
||||||
|
/* Call the application's entry point.*/
|
||||||
|
bl entry
|
||||||
|
bx lr
|
||||||
|
.size Reset_Handler, .-Reset_Handler
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor receives an
|
||||||
|
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||||
|
* the system state for examination by a debugger.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
.section .text.Default_Handler,"ax",%progbits
|
||||||
|
Default_Handler:
|
||||||
|
Infinite_Loop:
|
||||||
|
b Infinite_Loop
|
||||||
|
.size Default_Handler, .-Default_Handler
|
||||||
|
/******************************************************************************
|
||||||
|
*
|
||||||
|
* The minimal vector table for a Cortex M3. Note that the proper constructs
|
||||||
|
* must be placed on this to ensure that it ends up at physical address
|
||||||
|
* 0x0000.0000.
|
||||||
|
*
|
||||||
|
*******************************************************************************/
|
||||||
|
.section .isr_vector,"a",%progbits
|
||||||
|
.type g_pfnVectors, %object
|
||||||
|
.size g_pfnVectors, .-g_pfnVectors
|
||||||
|
|
||||||
|
|
||||||
|
g_pfnVectors:
|
||||||
|
|
||||||
|
.word _estack
|
||||||
|
.word Reset_Handler
|
||||||
|
.word NMI_Handler
|
||||||
|
.word HardFault_Handler
|
||||||
|
.word MemManage_Handler
|
||||||
|
.word BusFault_Handler
|
||||||
|
.word UsageFault_Handler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word SVC_Handler
|
||||||
|
.word DebugMon_Handler
|
||||||
|
.word 0
|
||||||
|
.word PendSV_Handler
|
||||||
|
.word SysTick_Handler
|
||||||
|
.word WWDG_IRQHandler
|
||||||
|
.word PVD_IRQHandler
|
||||||
|
.word TAMPER_IRQHandler
|
||||||
|
.word RTC_IRQHandler
|
||||||
|
.word FLASH_IRQHandler
|
||||||
|
.word RCC_IRQHandler
|
||||||
|
.word EXTI0_IRQHandler
|
||||||
|
.word EXTI1_IRQHandler
|
||||||
|
.word EXTI2_IRQHandler
|
||||||
|
.word EXTI3_IRQHandler
|
||||||
|
.word EXTI4_IRQHandler
|
||||||
|
.word DMA1_Channel1_IRQHandler
|
||||||
|
.word DMA1_Channel2_IRQHandler
|
||||||
|
.word DMA1_Channel3_IRQHandler
|
||||||
|
.word DMA1_Channel4_IRQHandler
|
||||||
|
.word DMA1_Channel5_IRQHandler
|
||||||
|
.word DMA1_Channel6_IRQHandler
|
||||||
|
.word DMA1_Channel7_IRQHandler
|
||||||
|
.word ADC1_2_IRQHandler
|
||||||
|
.word USB_HP_CAN1_TX_IRQHandler
|
||||||
|
.word USB_LP_CAN1_RX0_IRQHandler
|
||||||
|
.word CAN1_RX1_IRQHandler
|
||||||
|
.word CAN1_SCE_IRQHandler
|
||||||
|
.word EXTI9_5_IRQHandler
|
||||||
|
.word TIM1_BRK_TIM9_IRQHandler
|
||||||
|
.word TIM1_UP_TIM10_IRQHandler
|
||||||
|
.word TIM1_TRG_COM_TIM11_IRQHandler
|
||||||
|
.word TIM1_CC_IRQHandler
|
||||||
|
.word TIM2_IRQHandler
|
||||||
|
.word TIM3_IRQHandler
|
||||||
|
.word TIM4_IRQHandler
|
||||||
|
.word I2C1_EV_IRQHandler
|
||||||
|
.word I2C1_ER_IRQHandler
|
||||||
|
.word I2C2_EV_IRQHandler
|
||||||
|
.word I2C2_ER_IRQHandler
|
||||||
|
.word SPI1_IRQHandler
|
||||||
|
.word SPI2_IRQHandler
|
||||||
|
.word USART1_IRQHandler
|
||||||
|
.word USART2_IRQHandler
|
||||||
|
.word USART3_IRQHandler
|
||||||
|
.word EXTI15_10_IRQHandler
|
||||||
|
.word RTC_Alarm_IRQHandler
|
||||||
|
.word USBWakeUp_IRQHandler
|
||||||
|
.word TIM8_BRK_TIM12_IRQHandler
|
||||||
|
.word TIM8_UP_TIM13_IRQHandler
|
||||||
|
.word TIM8_TRG_COM_TIM14_IRQHandler
|
||||||
|
.word TIM8_CC_IRQHandler
|
||||||
|
.word ADC3_IRQHandler
|
||||||
|
.word FSMC_IRQHandler
|
||||||
|
.word SDIO_IRQHandler
|
||||||
|
.word TIM5_IRQHandler
|
||||||
|
.word SPI3_IRQHandler
|
||||||
|
.word UART4_IRQHandler
|
||||||
|
.word UART5_IRQHandler
|
||||||
|
.word TIM6_IRQHandler
|
||||||
|
.word TIM7_IRQHandler
|
||||||
|
.word DMA2_Channel1_IRQHandler
|
||||||
|
.word DMA2_Channel2_IRQHandler
|
||||||
|
.word DMA2_Channel3_IRQHandler
|
||||||
|
.word DMA2_Channel4_5_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word BootRAM /* @0x1E0. This is for boot in RAM mode for
|
||||||
|
STM32F10x XL-Density devices. */
|
||||||
|
/*******************************************************************************
|
||||||
|
*
|
||||||
|
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||||
|
* As they are weak aliases, any function with the same name will override
|
||||||
|
* this definition.
|
||||||
|
*
|
||||||
|
*******************************************************************************/
|
||||||
|
|
||||||
|
.weak NMI_Handler
|
||||||
|
.thumb_set NMI_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak HardFault_Handler
|
||||||
|
.thumb_set HardFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak MemManage_Handler
|
||||||
|
.thumb_set MemManage_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak BusFault_Handler
|
||||||
|
.thumb_set BusFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak UsageFault_Handler
|
||||||
|
.thumb_set UsageFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SVC_Handler
|
||||||
|
.thumb_set SVC_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak DebugMon_Handler
|
||||||
|
.thumb_set DebugMon_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak PendSV_Handler
|
||||||
|
.thumb_set PendSV_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SysTick_Handler
|
||||||
|
.thumb_set SysTick_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak WWDG_IRQHandler
|
||||||
|
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak PVD_IRQHandler
|
||||||
|
.thumb_set PVD_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TAMPER_IRQHandler
|
||||||
|
.thumb_set TAMPER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_IRQHandler
|
||||||
|
.thumb_set RTC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FLASH_IRQHandler
|
||||||
|
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RCC_IRQHandler
|
||||||
|
.thumb_set RCC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI0_IRQHandler
|
||||||
|
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI1_IRQHandler
|
||||||
|
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI2_IRQHandler
|
||||||
|
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI3_IRQHandler
|
||||||
|
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI4_IRQHandler
|
||||||
|
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel1_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel2_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel3_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel4_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel5_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel6_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel7_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ADC1_2_IRQHandler
|
||||||
|
.thumb_set ADC1_2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USB_HP_CAN1_TX_IRQHandler
|
||||||
|
.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USB_LP_CAN1_RX0_IRQHandler
|
||||||
|
.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN1_RX1_IRQHandler
|
||||||
|
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN1_SCE_IRQHandler
|
||||||
|
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI9_5_IRQHandler
|
||||||
|
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_BRK_TIM9_IRQHandler
|
||||||
|
.thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_UP_TIM10_IRQHandler
|
||||||
|
.thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_TRG_COM_TIM11_IRQHandler
|
||||||
|
.thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_CC_IRQHandler
|
||||||
|
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM2_IRQHandler
|
||||||
|
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM3_IRQHandler
|
||||||
|
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM4_IRQHandler
|
||||||
|
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_EV_IRQHandler
|
||||||
|
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_ER_IRQHandler
|
||||||
|
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_EV_IRQHandler
|
||||||
|
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_ER_IRQHandler
|
||||||
|
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI1_IRQHandler
|
||||||
|
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI2_IRQHandler
|
||||||
|
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART1_IRQHandler
|
||||||
|
.thumb_set USART1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART2_IRQHandler
|
||||||
|
.thumb_set USART2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART3_IRQHandler
|
||||||
|
.thumb_set USART3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI15_10_IRQHandler
|
||||||
|
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_Alarm_IRQHandler
|
||||||
|
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USBWakeUp_IRQHandler
|
||||||
|
.thumb_set USBWakeUp_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM8_BRK_TIM12_IRQHandler
|
||||||
|
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM8_UP_TIM13_IRQHandler
|
||||||
|
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM8_TRG_COM_TIM14_IRQHandler
|
||||||
|
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM8_CC_IRQHandler
|
||||||
|
.thumb_set TIM8_CC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ADC3_IRQHandler
|
||||||
|
.thumb_set ADC3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FSMC_IRQHandler
|
||||||
|
.thumb_set FSMC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SDIO_IRQHandler
|
||||||
|
.thumb_set SDIO_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM5_IRQHandler
|
||||||
|
.thumb_set TIM5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI3_IRQHandler
|
||||||
|
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART4_IRQHandler
|
||||||
|
.thumb_set UART4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART5_IRQHandler
|
||||||
|
.thumb_set UART5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM6_IRQHandler
|
||||||
|
.thumb_set TIM6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM7_IRQHandler
|
||||||
|
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Channel1_IRQHandler
|
||||||
|
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Channel2_IRQHandler
|
||||||
|
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Channel3_IRQHandler
|
||||||
|
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Channel4_5_IRQHandler
|
||||||
|
.thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,476 @@
|
||||||
|
/**
|
||||||
|
*************** (C) COPYRIGHT 2017 STMicroelectronics ************************
|
||||||
|
* @file startup_stm32f105xc.s
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V4.2.0
|
||||||
|
* @date 31-March-2017
|
||||||
|
* @brief STM32F105xC Devices vector table for Atollic toolchain.
|
||||||
|
* This module performs:
|
||||||
|
* - Set the initial SP
|
||||||
|
* - Set the initial PC == Reset_Handler,
|
||||||
|
* - Set the vector table entries with the exceptions ISR address
|
||||||
|
* - Configure the clock system
|
||||||
|
* - Branches to main in the C library (which eventually
|
||||||
|
* calls main()).
|
||||||
|
* After Reset the Cortex-M3 processor is in Thread mode,
|
||||||
|
* priority is Privileged, and the Stack is set to Main.
|
||||||
|
******************************************************************************
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
.syntax unified
|
||||||
|
.cpu cortex-m3
|
||||||
|
.fpu softvfp
|
||||||
|
.thumb
|
||||||
|
|
||||||
|
.global g_pfnVectors
|
||||||
|
.global Default_Handler
|
||||||
|
|
||||||
|
/* start address for the initialization values of the .data section.
|
||||||
|
defined in linker script */
|
||||||
|
.word _sidata
|
||||||
|
/* start address for the .data section. defined in linker script */
|
||||||
|
.word _sdata
|
||||||
|
/* end address for the .data section. defined in linker script */
|
||||||
|
.word _edata
|
||||||
|
/* start address for the .bss section. defined in linker script */
|
||||||
|
.word _sbss
|
||||||
|
/* end address for the .bss section. defined in linker script */
|
||||||
|
.word _ebss
|
||||||
|
|
||||||
|
.equ BootRAM, 0xF1E0F85F
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor first
|
||||||
|
* starts execution following a reset event. Only the absolutely
|
||||||
|
* necessary set is performed, after which the application
|
||||||
|
* supplied main() routine is called.
|
||||||
|
* @param None
|
||||||
|
* @retval : None
|
||||||
|
*/
|
||||||
|
|
||||||
|
.section .text.Reset_Handler
|
||||||
|
.weak Reset_Handler
|
||||||
|
.type Reset_Handler, %function
|
||||||
|
Reset_Handler:
|
||||||
|
|
||||||
|
/* Copy the data segment initializers from flash to SRAM */
|
||||||
|
movs r1, #0
|
||||||
|
b LoopCopyDataInit
|
||||||
|
|
||||||
|
CopyDataInit:
|
||||||
|
ldr r3, =_sidata
|
||||||
|
ldr r3, [r3, r1]
|
||||||
|
str r3, [r0, r1]
|
||||||
|
adds r1, r1, #4
|
||||||
|
|
||||||
|
LoopCopyDataInit:
|
||||||
|
ldr r0, =_sdata
|
||||||
|
ldr r3, =_edata
|
||||||
|
adds r2, r0, r1
|
||||||
|
cmp r2, r3
|
||||||
|
bcc CopyDataInit
|
||||||
|
ldr r2, =_sbss
|
||||||
|
b LoopFillZerobss
|
||||||
|
|
||||||
|
/* Zero fill the bss segment. */
|
||||||
|
FillZerobss:
|
||||||
|
movs r3, #0
|
||||||
|
str r3, [r2], #4
|
||||||
|
|
||||||
|
LoopFillZerobss:
|
||||||
|
ldr r3, = _ebss
|
||||||
|
cmp r2, r3
|
||||||
|
bcc FillZerobss
|
||||||
|
/* Call the clock system intitialization function.*/
|
||||||
|
bl SystemInit
|
||||||
|
/* Call the application's entry point.*/
|
||||||
|
bl entry
|
||||||
|
bx lr
|
||||||
|
.size Reset_Handler, .-Reset_Handler
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor receives an
|
||||||
|
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||||
|
* the system state for examination by a debugger.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
.section .text.Default_Handler,"ax",%progbits
|
||||||
|
Default_Handler:
|
||||||
|
Infinite_Loop:
|
||||||
|
b Infinite_Loop
|
||||||
|
.size Default_Handler, .-Default_Handler
|
||||||
|
/******************************************************************************
|
||||||
|
*
|
||||||
|
* The minimal vector table for a Cortex M3. Note that the proper constructs
|
||||||
|
* must be placed on this to ensure that it ends up at physical address
|
||||||
|
* 0x0000.0000.
|
||||||
|
*
|
||||||
|
******************************************************************************/
|
||||||
|
.section .isr_vector,"a",%progbits
|
||||||
|
.type g_pfnVectors, %object
|
||||||
|
.size g_pfnVectors, .-g_pfnVectors
|
||||||
|
|
||||||
|
|
||||||
|
g_pfnVectors:
|
||||||
|
|
||||||
|
.word _estack
|
||||||
|
.word Reset_Handler
|
||||||
|
.word NMI_Handler
|
||||||
|
.word HardFault_Handler
|
||||||
|
.word MemManage_Handler
|
||||||
|
.word BusFault_Handler
|
||||||
|
.word UsageFault_Handler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word SVC_Handler
|
||||||
|
.word DebugMon_Handler
|
||||||
|
.word 0
|
||||||
|
.word PendSV_Handler
|
||||||
|
.word SysTick_Handler
|
||||||
|
.word WWDG_IRQHandler
|
||||||
|
.word PVD_IRQHandler
|
||||||
|
.word TAMPER_IRQHandler
|
||||||
|
.word RTC_IRQHandler
|
||||||
|
.word FLASH_IRQHandler
|
||||||
|
.word RCC_IRQHandler
|
||||||
|
.word EXTI0_IRQHandler
|
||||||
|
.word EXTI1_IRQHandler
|
||||||
|
.word EXTI2_IRQHandler
|
||||||
|
.word EXTI3_IRQHandler
|
||||||
|
.word EXTI4_IRQHandler
|
||||||
|
.word DMA1_Channel1_IRQHandler
|
||||||
|
.word DMA1_Channel2_IRQHandler
|
||||||
|
.word DMA1_Channel3_IRQHandler
|
||||||
|
.word DMA1_Channel4_IRQHandler
|
||||||
|
.word DMA1_Channel5_IRQHandler
|
||||||
|
.word DMA1_Channel6_IRQHandler
|
||||||
|
.word DMA1_Channel7_IRQHandler
|
||||||
|
.word ADC1_2_IRQHandler
|
||||||
|
.word CAN1_TX_IRQHandler
|
||||||
|
.word CAN1_RX0_IRQHandler
|
||||||
|
.word CAN1_RX1_IRQHandler
|
||||||
|
.word CAN1_SCE_IRQHandler
|
||||||
|
.word EXTI9_5_IRQHandler
|
||||||
|
.word TIM1_BRK_IRQHandler
|
||||||
|
.word TIM1_UP_IRQHandler
|
||||||
|
.word TIM1_TRG_COM_IRQHandler
|
||||||
|
.word TIM1_CC_IRQHandler
|
||||||
|
.word TIM2_IRQHandler
|
||||||
|
.word TIM3_IRQHandler
|
||||||
|
.word TIM4_IRQHandler
|
||||||
|
.word I2C1_EV_IRQHandler
|
||||||
|
.word I2C1_ER_IRQHandler
|
||||||
|
.word I2C2_EV_IRQHandler
|
||||||
|
.word I2C2_ER_IRQHandler
|
||||||
|
.word SPI1_IRQHandler
|
||||||
|
.word SPI2_IRQHandler
|
||||||
|
.word USART1_IRQHandler
|
||||||
|
.word USART2_IRQHandler
|
||||||
|
.word USART3_IRQHandler
|
||||||
|
.word EXTI15_10_IRQHandler
|
||||||
|
.word RTC_Alarm_IRQHandler
|
||||||
|
.word OTG_FS_WKUP_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word TIM5_IRQHandler
|
||||||
|
.word SPI3_IRQHandler
|
||||||
|
.word UART4_IRQHandler
|
||||||
|
.word UART5_IRQHandler
|
||||||
|
.word TIM6_IRQHandler
|
||||||
|
.word TIM7_IRQHandler
|
||||||
|
.word DMA2_Channel1_IRQHandler
|
||||||
|
.word DMA2_Channel2_IRQHandler
|
||||||
|
.word DMA2_Channel3_IRQHandler
|
||||||
|
.word DMA2_Channel4_IRQHandler
|
||||||
|
.word DMA2_Channel5_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word CAN2_TX_IRQHandler
|
||||||
|
.word CAN2_RX0_IRQHandler
|
||||||
|
.word CAN2_RX1_IRQHandler
|
||||||
|
.word CAN2_SCE_IRQHandler
|
||||||
|
.word OTG_FS_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word BootRAM /* @0x1E0. This is for boot in RAM mode for
|
||||||
|
STM32F10x Connectivity line Devices. */
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
*
|
||||||
|
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||||
|
* As they are weak aliases, any function with the same name will override
|
||||||
|
* this definition.
|
||||||
|
*
|
||||||
|
*******************************************************************************/
|
||||||
|
.weak NMI_Handler
|
||||||
|
.thumb_set NMI_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak HardFault_Handler
|
||||||
|
.thumb_set HardFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak MemManage_Handler
|
||||||
|
.thumb_set MemManage_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak BusFault_Handler
|
||||||
|
.thumb_set BusFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak UsageFault_Handler
|
||||||
|
.thumb_set UsageFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SVC_Handler
|
||||||
|
.thumb_set SVC_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak DebugMon_Handler
|
||||||
|
.thumb_set DebugMon_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak PendSV_Handler
|
||||||
|
.thumb_set PendSV_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SysTick_Handler
|
||||||
|
.thumb_set SysTick_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak WWDG_IRQHandler
|
||||||
|
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak PVD_IRQHandler
|
||||||
|
.thumb_set PVD_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TAMPER_IRQHandler
|
||||||
|
.thumb_set TAMPER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_IRQHandler
|
||||||
|
.thumb_set RTC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FLASH_IRQHandler
|
||||||
|
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RCC_IRQHandler
|
||||||
|
.thumb_set RCC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI0_IRQHandler
|
||||||
|
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI1_IRQHandler
|
||||||
|
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI2_IRQHandler
|
||||||
|
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI3_IRQHandler
|
||||||
|
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI4_IRQHandler
|
||||||
|
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel1_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel2_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel3_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel4_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel5_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel6_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel7_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ADC1_2_IRQHandler
|
||||||
|
.thumb_set ADC1_2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN1_TX_IRQHandler
|
||||||
|
.thumb_set CAN1_TX_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN1_RX0_IRQHandler
|
||||||
|
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN1_RX1_IRQHandler
|
||||||
|
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN1_SCE_IRQHandler
|
||||||
|
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI9_5_IRQHandler
|
||||||
|
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_BRK_IRQHandler
|
||||||
|
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_UP_IRQHandler
|
||||||
|
.thumb_set TIM1_UP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_TRG_COM_IRQHandler
|
||||||
|
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_CC_IRQHandler
|
||||||
|
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM2_IRQHandler
|
||||||
|
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM3_IRQHandler
|
||||||
|
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM4_IRQHandler
|
||||||
|
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_EV_IRQHandler
|
||||||
|
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_ER_IRQHandler
|
||||||
|
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_EV_IRQHandler
|
||||||
|
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_ER_IRQHandler
|
||||||
|
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI1_IRQHandler
|
||||||
|
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI2_IRQHandler
|
||||||
|
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART1_IRQHandler
|
||||||
|
.thumb_set USART1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART2_IRQHandler
|
||||||
|
.thumb_set USART2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART3_IRQHandler
|
||||||
|
.thumb_set USART3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI15_10_IRQHandler
|
||||||
|
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_Alarm_IRQHandler
|
||||||
|
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_FS_WKUP_IRQHandler
|
||||||
|
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM5_IRQHandler
|
||||||
|
.thumb_set TIM5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI3_IRQHandler
|
||||||
|
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART4_IRQHandler
|
||||||
|
.thumb_set UART4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART5_IRQHandler
|
||||||
|
.thumb_set UART5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM6_IRQHandler
|
||||||
|
.thumb_set TIM6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM7_IRQHandler
|
||||||
|
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Channel1_IRQHandler
|
||||||
|
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Channel2_IRQHandler
|
||||||
|
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Channel3_IRQHandler
|
||||||
|
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Channel4_IRQHandler
|
||||||
|
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Channel5_IRQHandler
|
||||||
|
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN2_TX_IRQHandler
|
||||||
|
.thumb_set CAN2_TX_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN2_RX0_IRQHandler
|
||||||
|
.thumb_set CAN2_RX0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN2_RX1_IRQHandler
|
||||||
|
.thumb_set CAN2_RX1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN2_SCE_IRQHandler
|
||||||
|
.thumb_set CAN2_SCE_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_FS_IRQHandler
|
||||||
|
.thumb_set OTG_FS_IRQHandler ,Default_Handler
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,487 @@
|
||||||
|
/**
|
||||||
|
*************** (C) COPYRIGHT 2017 STMicroelectronics ************************
|
||||||
|
* @file startup_stm32f107xc.s
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V4.2.0
|
||||||
|
* @date 31-March-2017
|
||||||
|
* @brief STM32F107xC Devices vector table for Atollic toolchain.
|
||||||
|
* This module performs:
|
||||||
|
* - Set the initial SP
|
||||||
|
* - Set the initial PC == Reset_Handler,
|
||||||
|
* - Set the vector table entries with the exceptions ISR address
|
||||||
|
* - Configure the clock system
|
||||||
|
* - Branches to main in the C library (which eventually
|
||||||
|
* calls main()).
|
||||||
|
* After Reset the Cortex-M3 processor is in Thread mode,
|
||||||
|
* priority is Privileged, and the Stack is set to Main.
|
||||||
|
******************************************************************************
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
.syntax unified
|
||||||
|
.cpu cortex-m3
|
||||||
|
.fpu softvfp
|
||||||
|
.thumb
|
||||||
|
|
||||||
|
.global g_pfnVectors
|
||||||
|
.global Default_Handler
|
||||||
|
|
||||||
|
/* start address for the initialization values of the .data section.
|
||||||
|
defined in linker script */
|
||||||
|
.word _sidata
|
||||||
|
/* start address for the .data section. defined in linker script */
|
||||||
|
.word _sdata
|
||||||
|
/* end address for the .data section. defined in linker script */
|
||||||
|
.word _edata
|
||||||
|
/* start address for the .bss section. defined in linker script */
|
||||||
|
.word _sbss
|
||||||
|
/* end address for the .bss section. defined in linker script */
|
||||||
|
.word _ebss
|
||||||
|
|
||||||
|
.equ BootRAM, 0xF1E0F85F
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor first
|
||||||
|
* starts execution following a reset event. Only the absolutely
|
||||||
|
* necessary set is performed, after which the application
|
||||||
|
* supplied main() routine is called.
|
||||||
|
* @param None
|
||||||
|
* @retval : None
|
||||||
|
*/
|
||||||
|
|
||||||
|
.section .text.Reset_Handler
|
||||||
|
.weak Reset_Handler
|
||||||
|
.type Reset_Handler, %function
|
||||||
|
Reset_Handler:
|
||||||
|
|
||||||
|
/* Copy the data segment initializers from flash to SRAM */
|
||||||
|
movs r1, #0
|
||||||
|
b LoopCopyDataInit
|
||||||
|
|
||||||
|
CopyDataInit:
|
||||||
|
ldr r3, =_sidata
|
||||||
|
ldr r3, [r3, r1]
|
||||||
|
str r3, [r0, r1]
|
||||||
|
adds r1, r1, #4
|
||||||
|
|
||||||
|
LoopCopyDataInit:
|
||||||
|
ldr r0, =_sdata
|
||||||
|
ldr r3, =_edata
|
||||||
|
adds r2, r0, r1
|
||||||
|
cmp r2, r3
|
||||||
|
bcc CopyDataInit
|
||||||
|
ldr r2, =_sbss
|
||||||
|
b LoopFillZerobss
|
||||||
|
|
||||||
|
/* Zero fill the bss segment. */
|
||||||
|
FillZerobss:
|
||||||
|
movs r3, #0
|
||||||
|
str r3, [r2], #4
|
||||||
|
|
||||||
|
LoopFillZerobss:
|
||||||
|
ldr r3, = _ebss
|
||||||
|
cmp r2, r3
|
||||||
|
bcc FillZerobss
|
||||||
|
|
||||||
|
/* Call the clock system intitialization function.*/
|
||||||
|
bl SystemInit
|
||||||
|
/* Call static constructors */
|
||||||
|
/* bl __libc_init_array */
|
||||||
|
/* Call the application's entry point.*/
|
||||||
|
bl entry
|
||||||
|
bx lr
|
||||||
|
.size Reset_Handler, .-Reset_Handler
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor receives an
|
||||||
|
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||||
|
* the system state for examination by a debugger.
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
* @retval : None
|
||||||
|
*/
|
||||||
|
.section .text.Default_Handler,"ax",%progbits
|
||||||
|
Default_Handler:
|
||||||
|
Infinite_Loop:
|
||||||
|
b Infinite_Loop
|
||||||
|
.size Default_Handler, .-Default_Handler
|
||||||
|
|
||||||
|
/******************************************************************************
|
||||||
|
*
|
||||||
|
* The minimal vector table for a Cortex M3. Note that the proper constructs
|
||||||
|
* must be placed on this to ensure that it ends up at physical address
|
||||||
|
* 0x0000.0000.
|
||||||
|
*
|
||||||
|
******************************************************************************/
|
||||||
|
.section .isr_vector,"a",%progbits
|
||||||
|
.type g_pfnVectors, %object
|
||||||
|
.size g_pfnVectors, .-g_pfnVectors
|
||||||
|
|
||||||
|
|
||||||
|
g_pfnVectors:
|
||||||
|
|
||||||
|
.word _estack
|
||||||
|
.word Reset_Handler
|
||||||
|
.word NMI_Handler
|
||||||
|
.word HardFault_Handler
|
||||||
|
.word MemManage_Handler
|
||||||
|
.word BusFault_Handler
|
||||||
|
.word UsageFault_Handler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word SVC_Handler
|
||||||
|
.word DebugMon_Handler
|
||||||
|
.word 0
|
||||||
|
.word PendSV_Handler
|
||||||
|
.word SysTick_Handler
|
||||||
|
.word WWDG_IRQHandler
|
||||||
|
.word PVD_IRQHandler
|
||||||
|
.word TAMPER_IRQHandler
|
||||||
|
.word RTC_IRQHandler
|
||||||
|
.word FLASH_IRQHandler
|
||||||
|
.word RCC_IRQHandler
|
||||||
|
.word EXTI0_IRQHandler
|
||||||
|
.word EXTI1_IRQHandler
|
||||||
|
.word EXTI2_IRQHandler
|
||||||
|
.word EXTI3_IRQHandler
|
||||||
|
.word EXTI4_IRQHandler
|
||||||
|
.word DMA1_Channel1_IRQHandler
|
||||||
|
.word DMA1_Channel2_IRQHandler
|
||||||
|
.word DMA1_Channel3_IRQHandler
|
||||||
|
.word DMA1_Channel4_IRQHandler
|
||||||
|
.word DMA1_Channel5_IRQHandler
|
||||||
|
.word DMA1_Channel6_IRQHandler
|
||||||
|
.word DMA1_Channel7_IRQHandler
|
||||||
|
.word ADC1_2_IRQHandler
|
||||||
|
.word CAN1_TX_IRQHandler
|
||||||
|
.word CAN1_RX0_IRQHandler
|
||||||
|
.word CAN1_RX1_IRQHandler
|
||||||
|
.word CAN1_SCE_IRQHandler
|
||||||
|
.word EXTI9_5_IRQHandler
|
||||||
|
.word TIM1_BRK_IRQHandler
|
||||||
|
.word TIM1_UP_IRQHandler
|
||||||
|
.word TIM1_TRG_COM_IRQHandler
|
||||||
|
.word TIM1_CC_IRQHandler
|
||||||
|
.word TIM2_IRQHandler
|
||||||
|
.word TIM3_IRQHandler
|
||||||
|
.word TIM4_IRQHandler
|
||||||
|
.word I2C1_EV_IRQHandler
|
||||||
|
.word I2C1_ER_IRQHandler
|
||||||
|
.word I2C2_EV_IRQHandler
|
||||||
|
.word I2C2_ER_IRQHandler
|
||||||
|
.word SPI1_IRQHandler
|
||||||
|
.word SPI2_IRQHandler
|
||||||
|
.word USART1_IRQHandler
|
||||||
|
.word USART2_IRQHandler
|
||||||
|
.word USART3_IRQHandler
|
||||||
|
.word EXTI15_10_IRQHandler
|
||||||
|
.word RTC_Alarm_IRQHandler
|
||||||
|
.word OTG_FS_WKUP_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word TIM5_IRQHandler
|
||||||
|
.word SPI3_IRQHandler
|
||||||
|
.word UART4_IRQHandler
|
||||||
|
.word UART5_IRQHandler
|
||||||
|
.word TIM6_IRQHandler
|
||||||
|
.word TIM7_IRQHandler
|
||||||
|
.word DMA2_Channel1_IRQHandler
|
||||||
|
.word DMA2_Channel2_IRQHandler
|
||||||
|
.word DMA2_Channel3_IRQHandler
|
||||||
|
.word DMA2_Channel4_IRQHandler
|
||||||
|
.word DMA2_Channel5_IRQHandler
|
||||||
|
.word ETH_IRQHandler
|
||||||
|
.word ETH_WKUP_IRQHandler
|
||||||
|
.word CAN2_TX_IRQHandler
|
||||||
|
.word CAN2_RX0_IRQHandler
|
||||||
|
.word CAN2_RX1_IRQHandler
|
||||||
|
.word CAN2_SCE_IRQHandler
|
||||||
|
.word OTG_FS_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word BootRAM /* @0x1E0. This is for boot in RAM mode for
|
||||||
|
STM32F10x Connectivity line Devices. */
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
*
|
||||||
|
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||||
|
* As they are weak aliases, any function with the same name will override
|
||||||
|
* this definition.
|
||||||
|
*
|
||||||
|
*******************************************************************************/
|
||||||
|
.weak NMI_Handler
|
||||||
|
.thumb_set NMI_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak HardFault_Handler
|
||||||
|
.thumb_set HardFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak MemManage_Handler
|
||||||
|
.thumb_set MemManage_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak BusFault_Handler
|
||||||
|
.thumb_set BusFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak UsageFault_Handler
|
||||||
|
.thumb_set UsageFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SVC_Handler
|
||||||
|
.thumb_set SVC_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak DebugMon_Handler
|
||||||
|
.thumb_set DebugMon_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak PendSV_Handler
|
||||||
|
.thumb_set PendSV_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SysTick_Handler
|
||||||
|
.thumb_set SysTick_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak WWDG_IRQHandler
|
||||||
|
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak PVD_IRQHandler
|
||||||
|
.thumb_set PVD_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TAMPER_IRQHandler
|
||||||
|
.thumb_set TAMPER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_IRQHandler
|
||||||
|
.thumb_set RTC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FLASH_IRQHandler
|
||||||
|
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RCC_IRQHandler
|
||||||
|
.thumb_set RCC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI0_IRQHandler
|
||||||
|
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI1_IRQHandler
|
||||||
|
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI2_IRQHandler
|
||||||
|
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI3_IRQHandler
|
||||||
|
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI4_IRQHandler
|
||||||
|
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel1_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel2_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel3_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel4_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel5_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel6_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel7_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ADC1_2_IRQHandler
|
||||||
|
.thumb_set ADC1_2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN1_TX_IRQHandler
|
||||||
|
.thumb_set CAN1_TX_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN1_RX0_IRQHandler
|
||||||
|
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN1_RX1_IRQHandler
|
||||||
|
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN1_SCE_IRQHandler
|
||||||
|
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI9_5_IRQHandler
|
||||||
|
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_BRK_IRQHandler
|
||||||
|
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_UP_IRQHandler
|
||||||
|
.thumb_set TIM1_UP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_TRG_COM_IRQHandler
|
||||||
|
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_CC_IRQHandler
|
||||||
|
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM2_IRQHandler
|
||||||
|
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM3_IRQHandler
|
||||||
|
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM4_IRQHandler
|
||||||
|
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_EV_IRQHandler
|
||||||
|
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_ER_IRQHandler
|
||||||
|
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_EV_IRQHandler
|
||||||
|
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_ER_IRQHandler
|
||||||
|
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI1_IRQHandler
|
||||||
|
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI2_IRQHandler
|
||||||
|
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART1_IRQHandler
|
||||||
|
.thumb_set USART1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART2_IRQHandler
|
||||||
|
.thumb_set USART2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART3_IRQHandler
|
||||||
|
.thumb_set USART3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI15_10_IRQHandler
|
||||||
|
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_Alarm_IRQHandler
|
||||||
|
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_FS_WKUP_IRQHandler
|
||||||
|
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM5_IRQHandler
|
||||||
|
.thumb_set TIM5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI3_IRQHandler
|
||||||
|
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART4_IRQHandler
|
||||||
|
.thumb_set UART4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART5_IRQHandler
|
||||||
|
.thumb_set UART5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM6_IRQHandler
|
||||||
|
.thumb_set TIM6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM7_IRQHandler
|
||||||
|
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Channel1_IRQHandler
|
||||||
|
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Channel2_IRQHandler
|
||||||
|
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Channel3_IRQHandler
|
||||||
|
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Channel4_IRQHandler
|
||||||
|
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Channel5_IRQHandler
|
||||||
|
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ETH_IRQHandler
|
||||||
|
.thumb_set ETH_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ETH_WKUP_IRQHandler
|
||||||
|
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN2_TX_IRQHandler
|
||||||
|
.thumb_set CAN2_TX_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN2_RX0_IRQHandler
|
||||||
|
.thumb_set CAN2_RX0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN2_RX1_IRQHandler
|
||||||
|
.thumb_set CAN2_RX1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN2_SCE_IRQHandler
|
||||||
|
.thumb_set CAN2_SCE_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_FS_IRQHandler
|
||||||
|
.thumb_set OTG_FS_IRQHandler ,Default_Handler
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,31 @@
|
||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
|
|
@ -0,0 +1,31 @@
|
||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x20000000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x20000000 ;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x200013FF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
|
|
@ -0,0 +1,31 @@
|
||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
|
|
@ -0,0 +1,31 @@
|
||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x20000000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x20000000 ;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x200013FF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
|
|
@ -0,0 +1,31 @@
|
||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x08007FFF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x200017FF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
|
|
@ -0,0 +1,31 @@
|
||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x20000000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x20000000 ;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x200013FF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x200017FF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
|
|
@ -0,0 +1,31 @@
|
||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
|
|
@ -0,0 +1,31 @@
|
||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x20000000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x20000000 ;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x200013FF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
|
|
@ -0,0 +1,31 @@
|
||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x2000BFFF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
|
|
@ -0,0 +1,31 @@
|
||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x20000000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x20000000 ;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x200013FF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x2000BFFF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
|
|
@ -0,0 +1,31 @@
|
||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x20013FFF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
|
|
@ -0,0 +1,31 @@
|
||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x20000000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x20000000 ;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x200013FF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x20013FFF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
|
|
@ -0,0 +1,31 @@
|
||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x08007FFF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x200017FF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
|
|
@ -0,0 +1,31 @@
|
||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x20000000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x20000000 ;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x200013FF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x200017FF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
|
|
@ -0,0 +1,31 @@
|
||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
|
|
@ -0,0 +1,31 @@
|
||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x20000000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x20000000 ;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x200013FF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue