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更正stm32/stm32f103-100ask-mini和pro的默认下载器为st-link，添加基于mm32f3270系列由百问网自主设计的火龙果开发板的bsp

This commit is contained in:
slhuan 2022-08-31 15:14:16 +08:00 committed by guo
parent cbbea1a0f5
commit 75133af2e7
133 changed files with 78635 additions and 13 deletions
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1
.github/workflows/action.yml vendored
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@ -86,6 +86,7 @@ jobs:
- {RTT_BSP: "fujitsu/mb9x/mb9bf618s", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "fujitsu/mb9x/mb9bf568r", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "mini2440", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "mm32/mm32f3270-100ask-pitaya", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "nrf5x/nrf51822", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "nrf5x/nrf52832", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "nrf5x/nrf52833", RTT_TOOL_CHAIN: "sourcery-arm"}

10
bsp/mm32/README.md Normal file
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# MM32 BSP 说明
MM32 系列 BSP 目前支持情况如下表所示：
| **BSP 文件夹名称** | **开发板名称** |
|:------------------------- |:-------------------------- |
| **F3270 系列** | |
| [mm32f3270-100ask-pitaya](mm32f3270-100ask-pitaya) | 百问网MM32F3273G8P火龙果开发板 |
可以通过阅读相应 BSP 下的 README 来快速上手。

25
bsp/mm32/libraries/HAL_Drivers/Kconfig Normal file
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if BSP_USING_USBD
config BSP_USBD_TYPE_FS
bool
# "USB Full Speed (FS) Core"
config BSP_USBD_TYPE_HS
bool
# "USB High Speed (HS) Core"
config BSP_USBD_SPEED_HS
bool
# "USB High Speed (HS) Mode"
config BSP_USBD_SPEED_HSINFS
bool
# "USB High Speed (HS) Core in FS mode"
config BSP_USBD_PHY_EMBEDDED
bool
# "Using Embedded phy interface"
config BSP_USBD_PHY_UTMI
bool
# "UTMI: USB 2.0 Transceiver Macrocell Interace"
config BSP_USBD_PHY_ULPI
bool
# "ULPI: UTMI+ Low Pin Interface"
endif

24
bsp/mm32/libraries/HAL_Drivers/SConscript Normal file
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Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
# add the general drivers.
src = Split("""
""")
if GetDepend(['RT_USING_PIN']):
src += ['drv_gpio.c']
if GetDepend(['RT_USING_SERIAL']):
src += ['drv_uart.c']
src += ['drv_common.c']
path = [cwd]
path += [cwd + '/config']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
Return('group')

206
bsp/mm32/libraries/HAL_Drivers/config/mm32f3277g8p/dma_config.h Normal file
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/**
* @file dma_config.h
* @author 100ask development team
* @brief
* @version 0.1
* @date 2022-06-16
*
* @copyright Copyright (c) 2022 Chongqing 100ASK Technology Co., LTD
*
*/
#ifndef __DMA_CONFIG_H__
#define __DMA_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
/* DMA1 channel1 */
#if defined(BSP_ADC1_USING_DMA) && !defined(ADC1_DMA_INSTANCE)
#define ADC1_DMA_INSTANCE DMA1
#define ADC1_DMA_REQ DMA_REQ_DMA1_ADC1
#define ADC1_DMA_IRQ DMA1_CH1_IRQn
#define ADC1_DMA_IRQHandler DMA1_Channel1_IRQHandler
#define ADC1_DMA_RCC RCC_AHB1_PERIPH_DMA1
#elif defined(BSP_UART6_RX_USING_DMA) && !defined(UART6_RX_DMA_INSTANCE)
#define UART6_DMA_INSTANCE DMA1
#define UART6_RX_DMA_REQ DMA_REQ_DMA1_UART6_RX
#define UART6_RX_DMA_IRQ DMA1_CH1_IRQn
#define UART6_DMA_RX_IRQHandler DMA1_Channel1_IRQHandler
#define UART6_RX_DMA_RCC RCC_AHB1_PERIPH_DMA1
#endif
/* DMA1 channel2 */
#if defined(BSP_ADC2_USING_DMA) && !defined(ADC2_DMA_INSTANCE)
#define ADC2_DMA_INSTANCE DMA1
#define ADC2_DMA_REQ DMA_REQ_DMA1_ADC2
#define ADC2_DMA_IRQ DMA1_CH2_IRQn
#define ADC2_DMA_IRQHandler DMA1_Channel2_IRQHandler
#define ADC2_DMA_RCC RCC_AHB1_PERIPH_DMA1
#elif defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
#define SPI1_RX_DMA_INSTANCE DMA1
#define SPI1_RX_DMA_REQ DMA_REQ_DMA1_SPI1_RX
#define SPI1_RX_DMA_IRQ DMA1_CH2_IRQn
#define SPI1_DMA_RX_IRQHandler DMA1_Channel2_IRQHandler
#define SPI1_RX_DMA_RCC RCC_AHB1_PERIPH_DMA1
#elif defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA_INSTANCE)
#define UART3_TX_DMA_INSTANCE DMA1
#define UART3_TX_DMA_REQ DMA_REQ_DMA1_UART3_TX
#define UART3_TX_DMA_IRQ DMA1_CH2_IRQn
#define UART3_DMA_TX_IRQHandler DMA1_Channel2_IRQHandler
#define UART3_TX_DMA_RCC RCC_AHB1_PERIPH_DMA1
#endif
/* DMA1 channel3 */
#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
#define SPI1_TX_DMA_INSTANCE DMA1
#define SPI1_TX_DMA_REQ DMA_REQ_DMA1_SPI1_TX
#define SPI1_TX_DMA_IRQ DMA1_CH3_IRQn
#define SPI1_DMA_TX_IRQHandler DMA1_Channel3_IRQHandler
#define SPI1_TX_DMA_RCC RCC_AHB1_PERIPH_DMA1
#elif defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
#define UART3_RX_DMA_INSTANCE DMA1
#define UART3_RX_DMA_REQ DMA_REQ_DMA1_UART3_RX
#define UART3_RX_DMA_IRQ DMA1_CH3_IRQn
#define UART3_DMA_RX_IRQHandler DMA1_Channel3_IRQHandler
#define UART3_RX_DMA_RCC RCC_AHB1_PERIPH_DMA1
#endif
/* DMA1 channel4 */
#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
#define SPI2_RX_DMA_INSTANCE DMA1
#define SPI2_RX_DMA_REQ DMA_REQ_DMA1_SPI2_RX
#define SPI2_RX_DMA_IRQ DMA1_CH4_IRQn
#define SPI2_DMA_RX_IRQHandler DMA1_Channel4_IRQHandler
#define SPI2_RX_DMA_RCC RCC_AHB1_PERIPH_DMA1
#elif defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
#define UART1_TX_DMA_INSTANCE DMA1
#define UART1_TX_DMA_REQ DMA_REQ_DMA1_UART1_TX
#define UART1_TX_DMA_IRQ DMA1_CH4_IRQn
#define UART1_DMA_TX_IRQHandler DMA1_Channel4_IRQHandler
#define UART1_TX_DMA_RCC RCC_AHB1_PERIPH_DMA1
#endif
/* DMA1 channel5 */
#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
#define SPI2_TX_DMA_INSTANCE DMA1
#define SPI2_TX_DMA_REQ DMA_REQ_DMA1_SPI2_TX
#define SPI2_TX_DMA_IRQ DMA1_CH5_IRQn
#define SPI2_DMA_TX_IRQHandler DMA1_Channel5_IRQHandler
#define SPI2_TX_DMA_RCC RCC_AHB1_PERIPH_DMA1
#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
#define UART1_RX_DMA_INSTANCE DMA1
#define UART1_RX_DMA_REQ DMA_REQ_DMA1_UART1_RX
#define UART1_RX_DMA_IRQ DMA1_CH5_IRQn
#define UART1_DMA_RX_IRQHandler DMA1_Channel5_IRQHandler
#define UART1_RX_DMA_RCC RCC_AHB1_PERIPH_DMA1
#endif
/* DMA1 channel6 */
#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
#define UART6_RX_DMA_INSTANCE DMA1
#define UART6_RX_DMA_REQ DMA_REQ_DMA1_UART6_RX
#define UART6_RX_DMA_IRQ DMA1_CH6_IRQn
#define UART6_DMA_RX_IRQHandler DMA1_Channel6_IRQHandler
#define UART6_RX_DMA_RCC RCC_AHB1_PERIPH_DMA1
#endif
/* DMA1 channel7 */
#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
#define UART2_TX_DMA_INSTANCE DMA1
#define UART2_TX_DMA_REQ DMA_REQ_DMA1_UART2_TX
#define UART2_TX_DMA_IRQ DMA1_CH7_IRQn
#define UART2_DMA_TX_IRQHandler DMA1_Channel7_IRQHandler
#define UART2_TX_DMA_RCC RCC_AHB1_PERIPH_DMA1
#endif
/* DMA2 channel1 */
#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
#define SPI3_RX_DMA_INSTANCE DMA2
#define SPI3_RX_DMA_REQ DMA_REQ_DMA2_SPI3_RX
#define SPI3_RX_DMA_IRQ DMA2_CH1_IRQn
#define SPI3_DMA_RX_IRQHandler DMA2_Channel1_IRQHandler
#define SPI3_RX_DMA_RCC RCC_AHB1_PERIPH_DMA2
#elif defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE)
#define UART5_RX_DMA_INSTANCE DMA2
#define UART5_RX_DMA_REQ DMA_REQ_DMA2_UART5_RX
#define UART5_RX_DMA_IRQ DMA2_CH1_IRQn
#define UART5_DMA_RX_IRQHandler DMA2_Channel1_IRQHandler
#define UART5_RX_DMA_RCC RCC_AHB1_PERIPH_DMA2
#elif defined(BSP_UART7_RX_USING_DMA) && !defined(UART7_RX_DMA_INSTANCE)
#define UART7_RX_DMA_INSTANCE DMA2
#define UART7_RX_DMA_REQ DMA_REQ_DMA2_UART7_RX
#define UART7_RX_DMA_IRQ DMA2_CH1_IRQn
#define UART7_DMA_RX_IRQHandler DMA2_Channel1_IRQHandler
#define UART7_RX_DMA_RCC RCC_AHB1_PERIPH_DMA2
#endif
/* DMA2 channel2 */
#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
#define SPI3_TX_DMA_INSTANCE DMA2
#define SPI3_TX_DMA_REQ DMA_REQ_DMA2_SPI3_TX
#define SPI3_TX_DMA_IRQ DMA2_CH2_IRQn
#define SPI3_DMA_TX_IRQHandler DMA2_Channel2_IRQHandler
#define SPI3_TX_DMA_RCC RCC_AHB1_PERIPH_DMA2
#elif defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE)
#define UART5_TX_DMA_INSTANCE DMA2
#define UART5_TX_DMA_REQ DMA_REQ_DMA2_UART5_TX
#define UART5_TX_DMA_IRQ DMA2_CH2_IRQn
#define UART5_DMA_TX_IRQHandler DMA2_Channel2_IRQHandler
#define UART5_TX_DMA_RCC RCC_AHB1_PERIPH_DMA2
#elif defined(BSP_UART7_TX_USING_DMA) && !defined(UART7_TX_DMA_INSTANCE)
#define UART7_TX_DMA_INSTANCE DMA2
#define UART7_TX_DMA_REQ DMA_REQ_DMA2_UART7_TX
#define UART7_TX_DMA_IRQ DMA2_CH2_IRQn
#define UART7_DMA_TX_IRQHandler DMA2_Channel2_IRQHandler
#define UART7_TX_DMA_RCC RCC_AHB1_PERIPH_DMA2
#endif
/* DMA2 channel3 */
#if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
#define UART4_RX_DMA_INSTANCE DMA2
#define UART4_RX_DMA_REQ DMA_REQ_DMA2_UART4_RX
#define UART4_RX_DMA_IRQ DMA2_CH3_IRQn
#define UART4_DMA_RX_IRQHandler DMA2_Channel3_IRQHandler
#define UART4_RX_DMA_RCC RCC_AHB1_PERIPH_DMA2
#elif defined(BSP_UART8_RX_USING_DMA) && !defined(UART8_RX_DMA_INSTANCE)
#define UART8_RX_DMA_INSTANCE DMA2
#define UART8_RX_DMA_REQ DMA_REQ_DMA2_UART8_RX
#define UART8_RX_DMA_IRQ DMA2_CH3_IRQn
#define UART8_DMA_RX_IRQHandler DMA2_Channel3_IRQHandler
#define UART8_RX_DMA_RCC RCC_AHB1_PERIPH_DMA2
#endif
/* DMA2 channel4 */
#if defined(BSP_UART6_TX_USING_DMA) && !defined(UART6_TX_DMA_INSTANCE)
#define UART6_TX_DMA_INSTANCE DMA2
#define UART6_TX_DMA_REQ DMA_REQ_DMA2_UART6_TX
#define UART6_TX_DMA_IRQ DMA2_CH4_IRQn
#define UART6_DMA_TX_IRQHandler DMA2_Channel4_IRQHandler
#define UART6_TX_DMA_RCC RCC_AHB1_PERIPH_DMA2
#endif
/* DMA2 channel5 */
#if defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE)
#define UART4_TX_DMA_INSTANCE DMA2
#define UART4_TX_DMA_REQ DMA_REQ_DMA2_UART4_TX
#define UART4_TX_DMA_IRQ DMA2_CH5_IRQn
#define UART4_DMA_TX_IRQHandler DMA2_Channel5_IRQHandler
#define UART4_TX_DMA_RCC RCC_AHB1_PERIPH_DMA2
#elif defined(BSP_UART8_TX_USING_DMA) && !defined(UART8_TX_DMA_INSTANCE)
#define UART8_TX_DMA_INSTANCE DMA2
#define UART8_TX_DMA_REQ DMA_REQ_DMA2_UART8_TX
#define UART8_TX_DMA_IRQ DMA2_CH5_IRQn
#define UART8_DMA_TX_IRQHandler DMA2_Channel5_IRQHandler
#define UART8_TX_DMA_RCC RCC_AHB1_PERIPH_DMA2
#endif
#ifdef __cplusplus
}
#endif
#endif /* __DMA_CONFIG_H__ */

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bsp/mm32/libraries/HAL_Drivers/config/mm32f3277g8p/spi_config.h Normal file
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/**
* @file spi_config.h
* @author 100ask development team
* @brief
* @version 0.1
* @date 2022-06-16
*
* @copyright Copyright (c) 2022 Chongqing 100ASK Technology Co., LTD
*
*/
#ifndef __SPI_CONFIG_H__
#define __SPI_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_SPI1
#ifndef SPI1_BUS_CONFIG
#define SPI1_BUS_CONFIG \
{ \
.Instance = SPI1, \
.bus_name = "spi1", \
}
#endif /* SPI1_BUS_CONFIG */
#endif /* BSP_USING_SPI1 */
#ifdef BSP_SPI1_TX_USING_DMA
#ifndef SPI1_TX_DMA_CONFIG
#define SPI1_TX_DMA_CONFIG \
{ \
.dma_port = SPI1_TX_DMA_PORT, \
.dma_rcc = SPI1_TX_DMA_RCC, \
.Instance = SPI1_TX_DMA_INSTANCE, \
.dma_irq = SPI1_TX_DMA_IRQ, \
}
#endif /* SPI1_TX_DMA_CONFIG */
#endif /* BSP_SPI1_TX_USING_DMA */
#ifdef BSP_SPI1_RX_USING_DMA
#ifndef SPI1_RX_DMA_CONFIG
#define SPI1_RX_DMA_CONFIG \
{ \
.dma_rcc = SPI1_RX_DMA_RCC, \
.Instance = SPI1_RX_DMA_INSTANCE, \
.dma_irq = SPI1_RX_DMA_IRQ, \
}
#endif /* SPI1_RX_DMA_CONFIG */
#endif /* BSP_SPI1_RX_USING_DMA */
#ifdef BSP_USING_SPI2
#ifndef SPI2_BUS_CONFIG
#define SPI2_BUS_CONFIG \
{ \
.Instance = SPI2, \
.bus_name = "spi2", \
}
#endif /* SPI2_BUS_CONFIG */
#endif /* BSP_USING_SPI2 */
#ifdef BSP_SPI2_TX_USING_DMA
#ifndef SPI2_TX_DMA_CONFIG
#define SPI2_TX_DMA_CONFIG \
{ \
.dma_rcc = SPI2_TX_DMA_RCC, \
.Instance = SPI2_TX_DMA_INSTANCE, \
.dma_irq = SPI2_TX_DMA_IRQ, \
}
#endif /* SPI2_TX_DMA_CONFIG */
#endif /* BSP_SPI2_TX_USING_DMA */
#ifdef BSP_SPI2_RX_USING_DMA
#ifndef SPI2_RX_DMA_CONFIG
#define SPI2_RX_DMA_CONFIG \
{ \
.dma_rcc = SPI2_RX_DMA_RCC, \
.Instance = SPI2_RX_DMA_INSTANCE, \
.dma_irq = SPI2_RX_DMA_IRQ, \
}
#endif /* SPI2_RX_DMA_CONFIG */
#endif /* BSP_SPI2_RX_USING_DMA */
#ifdef BSP_USING_SPI3
#ifndef SPI3_BUS_CONFIG
#define SPI3_BUS_CONFIG \
{ \
.Instance = SPI3, \
.bus_name = "spi3", \
}
#endif /* SPI3_BUS_CONFIG */
#endif /* BSP_USING_SPI3 */
#ifdef BSP_SPI3_TX_USING_DMA
#ifndef SPI3_TX_DMA_CONFIG
#define SPI3_TX_DMA_CONFIG \
{ \
.dma_rcc = SPI3_TX_DMA_RCC, \
.Instance = SPI3_TX_DMA_INSTANCE, \
.dma_irq = SPI3_TX_DMA_IRQ, \
}
#endif /* SPI3_TX_DMA_CONFIG */
#endif /* BSP_SPI3_TX_USING_DMA */
#ifdef BSP_SPI3_RX_USING_DMA
#ifndef SPI3_RX_DMA_CONFIG
#define SPI3_RX_DMA_CONFIG \
{ \
.dma_rcc = SPI3_RX_DMA_RCC, \
.Instance = SPI3_RX_DMA_INSTANCE, \
.dma_irq = SPI3_RX_DMA_IRQ, \
}
#endif /* SPI3_RX_DMA_CONFIG */
#endif /* BSP_SPI3_RX_USING_DMA */
#ifdef __cplusplus
}
#endif
#endif /*__SPI_CONFIG_H__ */

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bsp/mm32/libraries/HAL_Drivers/config/mm32f3277g8p/uart_config.h Normal file
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/*
* Copyright (c) 2020-2022, CQ 100ask Development Team
*
* Change Logs:
* Date Author Notes
* 2022-05-29 Alen first version
*/
#ifndef __UART_CONFIG_H__
#define __UART_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined(BSP_USING_UART1)
#ifndef UART1_CONFIG
#define UART1_CONFIG \
{ \
.name = "uart1", \
.Instance = UART1, \
.irq_type = UART1_IRQn, \
}
#endif /* UART1_CONFIG */
#endif /* BSP_USING_UART1 */
#if defined(BSP_USING_UART2)
#ifndef UART2_CONFIG
#define UART2_CONFIG \
{ \
.name = "uart2", \
.Instance = UART2, \
.irq_type = UART2_IRQn, \
}
#endif /* UART2_CONFIG */
#endif /* BSP_USING_UART2 */
#if defined(BSP_USING_UART3)
#ifndef UART3_CONFIG
#define UART3_CONFIG \
{ \
.name = "uart3", \
.Instance = UART3, \
.irq_type = UART3_IRQn, \
}
#endif /* UART3_CONFIG */
#endif /* BSP_USING_UART3 */
#if defined(BSP_USING_UART4)
#ifndef UART4_CONFIG
#define UART4_CONFIG \
{ \
.name = "uart4", \
.Instance = UART4, \
.irq_type = UART4_IRQn, \
}
#endif /* UART4_CONFIG */
#endif /* BSP_USING_UART4 */
#if defined(BSP_USING_UART5)
#ifndef UART5_CONFIG
#define UART5_CONFIG \
{ \
.name = "uart5", \
.Instance = UART5, \
.irq_type = UART5_IRQn, \
}
#endif /* UART5_CONFIG */
#endif /* BSP_USING_UART5 */
#if defined(BSP_USING_UART6)
#ifndef UART6_CONFIG
#define UART6_CONFIG \
{ \
.name = "uart6", \
.Instance = UART6, \
.irq_type = UART6_IRQn, \
}
#endif /* UART5_CONFIG */
#endif /* BSP_USING_UART5 */
#if defined(BSP_USING_UART7)
#ifndef UART7_CONFIG
#define UART7_CONFIG \
{ \
.name = "uart7", \
.Instance = UART7, \
.irq_type = UART7_IRQn, \
}
#endif /* UART5_CONFIG */
#endif /* BSP_USING_UART5 */
#if defined(BSP_USING_UART8)
#ifndef UART8_CONFIG
#define UART8_CONFIG \
{ \
.name = "uart8", \
.Instance = UART8, \
.irq_type = UART8_IRQn, \
}
#endif /* UART5_CONFIG */
#endif /* BSP_USING_UART5 */
#ifdef __cplusplus
}
#endif
#endif

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bsp/mm32/libraries/HAL_Drivers/drv_common.c Normal file
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/*
* Copyright (c) 2020-2022, CQ 100ask Development Team
*
* Change Logs:
* Date Author Notes
* 2022-05-29 Alen first version
*/
#include "drv_common.h"
#define DBG_TAG "drv_common"
#define DBG_LVL DBG_INFO
#include <rtdbg.h>
#ifdef RT_USING_FINSH
#include <finsh.h>
static void reboot(uint8_t argc, char **argv)
{
rt_hw_cpu_reset();
}
MSH_CMD_EXPORT(reboot, Reboot System);
#endif /* RT_USING_FINSH */
volatile uint32_t uwTick;
static uint32_t _systick_ms = 1;
void HAL_IncTick(void);
/* SysTick configuration */
void rt_hw_systick_init(void)
{
uint32_t prioritygroup = 0x00U;
uint32_t SystemCoreClock = HAL_GetSysClockFreq();
/* Configure the SysTick to have interrupt in 1ms time basis*/
if(SysTick_Config(SystemCoreClock/1000) > 0)
{
return;
}
/* Configure the SysTick IRQ priority */
prioritygroup = NVIC_GetPriorityGrouping();
NVIC_SetPriority(SysTick_IRQn, NVIC_EncodePriority(prioritygroup, 15, 0));
_systick_ms = 1000u / RT_TICK_PER_SECOND;
if(_systick_ms == 0)
_systick_ms = 1;
}
/**
* This is the timer interrupt service routine.
*
*/
void SysTick_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
if(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)
HAL_IncTick();
rt_tick_increase();
/* leave interrupt */
rt_interrupt_leave();
}
void HAL_IncTick(void)
{
uwTick += _systick_ms;
}
/**
* @brief This function is executed in case of error occurrence.
* @param None
* @retval None
*/
void _Error_Handler(char *s, int num)
{
/* USER CODE BEGIN Error_Handler */
/* User can add his own implementation to report the HAL error return state */
LOG_E("Error_Handler at file:%s num:%d", s, num);
while (1)
{
}
/* USER CODE END Error_Handler */
}
/**
* This function will delay for some us.
*
* @param us the delay time of us
*/
void rt_hw_us_delay(rt_uint32_t us)
{
rt_uint32_t ticks;
rt_uint32_t told, tnow, tcnt = 0;
rt_uint32_t reload = SysTick->LOAD;
ticks = us * reload / (1000000 / RT_TICK_PER_SECOND);
told = SysTick->VAL;
while (1)
{
tnow = SysTick->VAL;
if (tnow != told)
{
if (tnow < told)
{
tcnt += told - tnow;
}
else
{
tcnt += reload - tnow + told;
}
told = tnow;
if (tcnt >= ticks)
{
break;
}
}
}
}
/**
* This function will initial STM32 board.
*/
RT_WEAK void rt_hw_board_init()
{
#ifdef BSP_SCB_ENABLE_I_CACHE
/* Enable I-Cache---------------------------------------------------------*/
SCB_EnableICache();
#endif
#ifdef BSP_SCB_ENABLE_D_CACHE
/* Enable D-Cache---------------------------------------------------------*/
SCB_EnableDCache();
#endif
/* System clock initialization */
SystemClock_Config();
rt_hw_systick_init();
/* Heap initialization */
#if defined(RT_USING_HEAP)
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
#endif
/* Pin driver initialization is open by default */
#ifdef RT_USING_PIN
rt_hw_pin_init();
#endif
/* USART driver initialization is open by default */
#ifdef RT_USING_SERIAL
rt_hw_uart_init();
#endif
/* Set the shell console output device */
#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
/* Board underlying hardware initialization */
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
}

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/*
* Copyright (c) 2020-2022, CQ 100ask Development Team
*
* Change Logs:
* Date Author Notes
* 2022-05-29 Alen first version
*/
#ifndef __DRV_COMMON_H__
#define __DRV_COMMON_H__
#include <rtthread.h>
#include <rthw.h>
#include <board.h>
#include <hal_common.h>
#include <hal_dma.h>
#include <hal_rcc.h>
#ifdef RT_USING_PIN
#include <hal_exti.h>
#include <hal_syscfg.h>
#include <hal_gpio.h>
#endif
#ifdef RT_USING_SERIAL
#include <hal_uart.h>
#endif
#ifdef RT_USING_SPI
#include <hal_spi.h>
#endif
#ifdef RT_USING_DEVICE
#include <rtdevice.h>
#endif
#ifdef __cplusplus
extern "C" {
#endif
void _Error_Handler(char *s, int num);
#ifndef Error_Handler
#define Error_Handler() _Error_Handler(__FILE__, __LINE__)
#endif
#define DMA_NOT_AVAILABLE ((DMA_INSTANCE_TYPE *)0xFFFFFFFFU)
#ifdef __cplusplus
}
#endif
#endif

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/*
* Copyright (c) 2020-2022, CQ 100ask Development Team
*
* Change Logs:
* Date Author Notes
* 2022-05-29 Alen first version
*/
#ifndef __DRV_CONFIG_H__
#define __DRV_CONFIG_H__
#include <board.h>
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined(SOC_SERIES_MM32F3277)
#include "mm32f3277g8p/dma_config.h"
#include "mm32f3277g8p/uart_config.h"
#include "mm32f3277g8p/spi_config.h"
#endif
#ifdef __cplusplus
}
#endif
#endif

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/**
* @file drv_dma.h
* @author 100ask development team
* @brief
* @version 0.1
* @date 2022-06-16
*
* @copyright Copyright (c) 2022 Chongqing 100ASK Technology Co., LTD
*
*/
#ifndef __DRV_DMA_H_
#define __DRV_DMA_H_
#include <rtthread.h>
#include "drv_common.h"
#ifdef __cplusplus
extern "C" {
#endif
struct dma_config {
DMA_Type *dma_port;
rt_uint32_t dma_req;
IRQn_Type dma_irq;
rt_uint32_t dma_rcc;
};
#ifdef __cplusplus
}
#endif
#endif /*__DRV_DMA_H_ */

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/*
* Copyright (c) 2020-2022, CQ 100ask Development Team
*
* Change Logs:
* Date Author Notes
* 2022-05-29 Alen first version
*/
#include "drv_gpio.h"
#ifdef RT_USING_PIN
#define PIN_NUM(port, no) (((((port) & 0xFu) << 4) | ((no) & 0xFu)))
#define PIN_PORT(pin) ((uint8_t)(((pin) >> 4) & 0xFu))
#define PIN_NO(pin) ((uint8_t)((pin) & 0xFu))
#define PIN_STPORT(pin) ((GPIO_Type *)(GPIOA_BASE + (0x400u * PIN_PORT(pin))))
#define PIN_STPIN(pin) ((uint16_t)(1u << PIN_NO(pin)))
#if defined(GPIOF)
#define __MM32_PORT_MAX 6u
#elif defined(GPIOE)
#define __MM32_PORT_MAX 5u
#elif defined(GPIOD)
#define __MM32_PORT_MAX 4u
#elif defined(GPIOC)
#define __MM32_PORT_MAX 3u
#elif defined(GPIOB)
#define __MM32_PORT_MAX 2u
#elif defined(GPIOA)
#define __MM32_PORT_MAX 1u
#else
#define __MM32_PORT_MAX 0u
#error Unsupported MM32 GPIO peripheral.
#endif
#define PIN_STPORT_MAX __MM32_PORT_MAX
#define GET_EXTI_PORT(PORT)
static const struct pin_irq_map pin_irq_map[] =
{
{GPIO_PIN_0, EXTI0_IRQn, EXTI_LINE_0, SYSCFG_EXTILine_0},
{GPIO_PIN_1, EXTI1_IRQn, EXTI_LINE_1, SYSCFG_EXTILine_1},
{GPIO_PIN_2, EXTI2_IRQn, EXTI_LINE_2, SYSCFG_EXTILine_2},
{GPIO_PIN_3, EXTI3_IRQn, EXTI_LINE_3, SYSCFG_EXTILine_3},
{GPIO_PIN_4, EXTI4_IRQn, EXTI_LINE_4, SYSCFG_EXTILine_4},
{GPIO_PIN_5, EXTI9_5_IRQn, EXTI_LINE_5,SYSCFG_EXTILine_5},
{GPIO_PIN_6, EXTI9_5_IRQn, EXTI_LINE_6, SYSCFG_EXTILine_6},
{GPIO_PIN_7, EXTI9_5_IRQn, EXTI_LINE_7, SYSCFG_EXTILine_7},
{GPIO_PIN_8, EXTI9_5_IRQn, EXTI_LINE_8, SYSCFG_EXTILine_8},
{GPIO_PIN_9, EXTI9_5_IRQn, EXTI_LINE_9, SYSCFG_EXTILine_9},
{GPIO_PIN_10, EXTI15_10_IRQn, EXTI_LINE_10, SYSCFG_EXTILine_10},
{GPIO_PIN_11, EXTI15_10_IRQn, EXTI_LINE_11, SYSCFG_EXTILine_11},
{GPIO_PIN_12, EXTI15_10_IRQn, EXTI_LINE_12, SYSCFG_EXTILine_12},
{GPIO_PIN_13, EXTI15_10_IRQn, EXTI_LINE_13, SYSCFG_EXTILine_13},
{GPIO_PIN_14, EXTI15_10_IRQn, EXTI_LINE_14, SYSCFG_EXTILine_14},
{GPIO_PIN_15, EXTI15_10_IRQn, EXTI_LINE_15, SYSCFG_EXTILine_15},
};
static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
{
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
};
static uint32_t pin_irq_enable_mask = 0;
#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
static rt_base_t mm32_pin_get(const char *name)
{
rt_base_t pin = 0;
int hw_port_num, hw_pin_num = 0;
int i, name_len;
name_len = rt_strlen(name);
if ((name_len < 4) || (name_len >= 6))
{
return -RT_EINVAL;
}
if ((name[0] != 'P') || (name[2] != '.'))
{
return -RT_EINVAL;
}
if ((name[1] >= 'A') && (name[1] <= 'F'))
{
hw_port_num = (int)(name[1] - 'A');
}
else
{
return -RT_EINVAL;
}
for (i = 3; i < name_len; i++)
{
hw_pin_num *= 10;
hw_pin_num += name[i] - '0';
}
pin = PIN_NUM(hw_port_num, hw_pin_num);
return pin;
}
static void mm32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
{
GPIO_Type *gpio_port;
uint16_t gpio_pin;
if (PIN_PORT(pin) < PIN_STPORT_MAX)
{
gpio_port = PIN_STPORT(pin);
gpio_pin = PIN_STPIN(pin);
GPIO_WriteBit(gpio_port, gpio_pin, (rt_uint16_t)value);
}
}
static int mm32_pin_read(rt_device_t dev, rt_base_t pin)
{
GPIO_Type *gpio_port;
uint16_t gpio_pin;
int value = PIN_LOW;
if (PIN_PORT(pin) < PIN_STPORT_MAX)
{
gpio_port = PIN_STPORT(pin);
gpio_pin = PIN_STPIN(pin);
value = GPIO_ReadInDataBit(gpio_port, gpio_pin);
}
return value;
}
static void mm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
{
GPIO_Init_Type GPIO_InitStruct;
if (PIN_PORT(pin) >= PIN_STPORT_MAX)
{
return;
}
/* Configure GPIO_InitStructure */
GPIO_InitStruct.Pins = PIN_STPIN(pin);
GPIO_InitStruct.PinMode = GPIO_PinMode_Out_PushPull;
GPIO_InitStruct.Speed = GPIO_Speed_50MHz;
if (mode == PIN_MODE_OUTPUT)
{
/* output setting */
GPIO_InitStruct.PinMode = GPIO_PinMode_Out_PushPull;
}
else if (mode == PIN_MODE_INPUT)
{
/* input setting: not pull. */
GPIO_InitStruct.PinMode = GPIO_PinMode_In_Floating;
}
else if (mode == PIN_MODE_INPUT_PULLUP)
{
/* input setting: pull up. */
GPIO_InitStruct.PinMode = GPIO_PinMode_In_PullUp;
}
else if (mode == PIN_MODE_INPUT_PULLDOWN)
{
/* input setting: pull down. */
GPIO_InitStruct.PinMode = GPIO_PinMode_In_PullDown;
}
else if (mode == PIN_MODE_OUTPUT_OD)
{
/* output setting: od. */
GPIO_InitStruct.PinMode = GPIO_PinMode_Out_OpenDrain;
}
GPIO_Init(PIN_STPORT(pin), &GPIO_InitStruct);
}
rt_inline rt_int32_t bit2bitno(rt_uint32_t bit)
{
rt_uint8_t i;
for (i = 0; i < 32; i++)
{
if ((0x01 << i) == bit)
{
return i;
}
}
return -1;
}
rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
{
rt_int32_t mapindex = bit2bitno(pinbit);
if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map))
{
return RT_NULL;
}
return &pin_irq_map[mapindex];
};
static rt_err_t mm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
rt_uint32_t mode, void (*hdr)(void *args), void *args)
{
rt_base_t level;
rt_int32_t irqindex = -1;
if (PIN_PORT(pin) >= PIN_STPORT_MAX)
{
return -RT_ENOSYS;
}
irqindex = bit2bitno(PIN_STPIN(pin));
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
{
return RT_ENOSYS;
}
level = rt_hw_interrupt_disable();
if (pin_irq_hdr_tab[irqindex].pin == pin &&
pin_irq_hdr_tab[irqindex].hdr == hdr &&
pin_irq_hdr_tab[irqindex].mode == mode &&
pin_irq_hdr_tab[irqindex].args == args)
{
rt_hw_interrupt_enable(level);
return RT_EOK;
}
if (pin_irq_hdr_tab[irqindex].pin != -1)
{
rt_hw_interrupt_enable(level);
return RT_EBUSY;
}
pin_irq_hdr_tab[irqindex].pin = pin;
pin_irq_hdr_tab[irqindex].hdr = hdr;
pin_irq_hdr_tab[irqindex].mode = mode;
pin_irq_hdr_tab[irqindex].args = args;
rt_hw_interrupt_enable(level);
return RT_EOK;
}
static rt_err_t mm32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
{
rt_base_t level;
rt_int32_t irqindex = -1;
if (PIN_PORT(pin) >= PIN_STPORT_MAX)
{
return -RT_ENOSYS;
}
irqindex = bit2bitno(PIN_STPIN(pin));
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
{
return RT_ENOSYS;
}
level = rt_hw_interrupt_disable();
if (pin_irq_hdr_tab[irqindex].pin == -1)
{
rt_hw_interrupt_enable(level);
return RT_EOK;
}
pin_irq_hdr_tab[irqindex].pin = -1;
pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
pin_irq_hdr_tab[irqindex].mode = 0;
pin_irq_hdr_tab[irqindex].args = RT_NULL;
rt_hw_interrupt_enable(level);
return RT_EOK;
}
static rt_err_t mm32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
rt_uint32_t enabled)
{
const struct pin_irq_map *irqmap;
rt_base_t level;
rt_int32_t irqindex = -1;
GPIO_Init_Type GPIO_InitStruct;
if (PIN_PORT(pin) >= PIN_STPORT_MAX)
{
return -RT_ENOSYS;
}
if (enabled == PIN_IRQ_ENABLE)
{
irqindex = bit2bitno(PIN_STPIN(pin));
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
{
return RT_ENOSYS;
}
level = rt_hw_interrupt_disable();
if (pin_irq_hdr_tab[irqindex].pin == -1)
{
rt_hw_interrupt_enable(level);
return RT_ENOSYS;
}
irqmap = &pin_irq_map[irqindex];
/* Configure GPIO_InitStructure */
GPIO_InitStruct.Pins = PIN_STPIN(pin);
GPIO_InitStruct.Speed = GPIO_Speed_50MHz;
GPIO_InitStruct.PinMode = GPIO_PinMode_In_PullUp;
GPIO_Init(PIN_STPORT(pin), &GPIO_InitStruct);
SYSCFG_SetExtIntMux(SYSCFG_EXTIPort_GPIOA + (0 == (rt_uint32_t)PIN_PORT(pin)?0: PIN_PORT(pin)/GPIOB_BASE), irqmap->syscfg_extiline);
switch (pin_irq_hdr_tab[irqindex].mode)
{
case PIN_IRQ_MODE_RISING:
EXTI_SetTriggerIn(EXTI, irqmap->extiline, EXTI_TriggerIn_RisingEdge);
break;
case PIN_IRQ_MODE_FALLING:
EXTI_SetTriggerIn(EXTI, irqmap->extiline, EXTI_TriggerIn_FallingEdge);
break;
case PIN_IRQ_MODE_RISING_FALLING:
EXTI_SetTriggerIn(EXTI, irqmap->extiline, EXTI_TriggerIn_BothEdges);
break;
}
EXTI_EnableLineInterrupt(EXTI, irqmap->extiline, true);
NVIC_SetPriority(irqmap->irqno, NVIC_EncodePriority(4, 5, 0));
NVIC_EnableIRQ(irqmap->irqno);
pin_irq_enable_mask |= irqmap->pinbit;
rt_hw_interrupt_enable(level);
}
else if (enabled == PIN_IRQ_DISABLE)
{
irqmap = get_pin_irq_map(PIN_STPIN(pin));
if (irqmap == RT_NULL)
{
return RT_ENOSYS;
}
level = rt_hw_interrupt_disable();
pin_irq_enable_mask &= ~irqmap->pinbit;
if ((irqmap->pinbit >= GPIO_PIN_5) && (irqmap->pinbit <= GPIO_PIN_9))
{
if (!(pin_irq_enable_mask & (GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9)))
{
NVIC_DisableIRQ(irqmap->irqno);
}
}
else if ((irqmap->pinbit >= GPIO_PIN_10) && (irqmap->pinbit <= GPIO_PIN_15))
{
if (!(pin_irq_enable_mask & (GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15)))
{
NVIC_DisableIRQ(irqmap->irqno);
}
}
else
{
NVIC_DisableIRQ(irqmap->irqno);
}
rt_hw_interrupt_enable(level);
}
else
{
return -RT_ENOSYS;
}
return RT_EOK;
}
const static struct rt_pin_ops _mm32_pin_ops =
{
mm32_pin_mode,
mm32_pin_write,
mm32_pin_read,
mm32_pin_attach_irq,
mm32_pin_dettach_irq,
mm32_pin_irq_enable,
mm32_pin_get,
};
rt_inline void pin_irq_hdr(int irqno)
{
if (pin_irq_hdr_tab[irqno].hdr)
{
pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
}
}
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
{
pin_irq_hdr(bit2bitno(GPIO_Pin));
}
#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
{
/* EXTI line interrupt detected */
if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u)
{
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
HAL_GPIO_EXTI_Callback(GPIO_Pin);
}
}
void EXTI0_IRQHandler(void)
{
rt_interrupt_enter();
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_0);
rt_interrupt_leave();
}
void EXTI1_IRQHandler(void)
{
rt_interrupt_enter();
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_1);
rt_interrupt_leave();
}
void EXTI2_IRQHandler(void)
{
rt_interrupt_enter();
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_2);
rt_interrupt_leave();
}
void EXTI3_IRQHandler(void)
{
rt_interrupt_enter();
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_3);
rt_interrupt_leave();
}
void EXTI4_IRQHandler(void)
{
rt_interrupt_enter();
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_4);
rt_interrupt_leave();
}
void EXTI9_5_IRQHandler(void)
{
rt_interrupt_enter();
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_5);
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_6);
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_7);
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_8);
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_9);
rt_interrupt_leave();
}
void EXTI15_10_IRQHandler(void)
{
rt_interrupt_enter();
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_10);
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_11);
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_12);
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_13);
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_14);
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_15);
rt_interrupt_leave();
}
int rt_hw_pin_init(void)
{
#if defined(RCC_AHB1_PERIPH_GPIOA)
RCC_EnableAHB1Periphs(RCC_AHB1_PERIPH_GPIOA, true);
#endif
#if defined(RCC_AHB1_PERIPH_GPIOB)
RCC_EnableAHB1Periphs(RCC_AHB1_PERIPH_GPIOB, true);
#endif
#if defined(RCC_AHB1_PERIPH_GPIOC)
RCC_EnableAHB1Periphs(RCC_AHB1_PERIPH_GPIOC, true);
#endif
#if defined(RCC_AHB1_PERIPH_GPIOD)
RCC_EnableAHB1Periphs(RCC_AHB1_PERIPH_GPIOD, true);
#endif
#if defined(RCC_AHB1_PERIPH_GPIOE)
RCC_EnableAHB1Periphs(RCC_AHB1_PERIPH_GPIOE, true);
#endif
#if defined(RCC_AHB1_PERIPH_GPIOF)
RCC_EnableAHB1Periphs(RCC_AHB1_PERIPH_GPIOF, true);
#endif
#if defined(RCC_APB2_PERIPH_SYSCFG)
RCC_EnableAPB2Periphs(RCC_APB2_PERIPH_SYSCFG, true);
#endif
return rt_device_pin_register("pin", &_mm32_pin_ops, RT_NULL);
}
#endif /* RT_USING_PIN */

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/*
* Copyright (c) 2020-2022, CQ 100ask Development Team
*
* Change Logs:
* Date Author Notes
* 2022-05-29 Alen first version
*/
#ifndef __DRV_GPIO_H__
#define __DRV_GPIO_H__
#include <drv_common.h>
#ifdef __cplusplus
extern "C" {
#endif
#define __MM32_PORT(port) GPIO##port##_BASE
#define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__MM32_PORT(PORTx) - (rt_base_t)GPIOA_BASE)/(0x0400UL) )) + PIN)
struct pin_irq_map
{
rt_uint16_t pinbit;
IRQn_Type irqno;
rt_uint32_t extiline;
SYSCFG_EXTILine_Type syscfg_extiline;
};
int rt_hw_pin_init(void);
#ifdef __cplusplus
}
#endif
#endif /* __DRV_GPIO_H__ */

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/**
* @file drv_spi.c
* @author 100ask development team
* @brief
* @version 0.1
* @date 2022-06-16
*
* @copyright Copyright (c) 2022 Chongqing 100ASK Technology Co., LTD
*
*/
#include <rtthread.h>
#include <rtdevice.h>
#define RT_USING_SPI
#define BSP_USING_SPI1
#define BSP_SPI1_TX_USING_DMA
#define BSP_SPI1_RX_USING_DMA
#ifdef RT_USING_SPI
#if defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2) || defined(BSP_USING_SPI3)
#include "drv_spi.h"
#include "drv_config.h"
#include <string.h>
//#define DRV_DEBUG
#define LOG_TAG "drv.spi"
#include <drv_log.h>
enum
{
#ifdef BSP_USING_SPI1
SPI1_INDEX,
#endif
#ifdef BSP_USING_SPI2
SPI2_INDEX,
#endif
#ifdef BSP_USING_SPI3
SPI3_INDEX,
#endif
};
static struct mm32_spi_config spi_config[] =
{
#ifdef BSP_USING_SPI1
SPI1_BUS_CONFIG,
#endif
#ifdef BSP_USING_SPI2
SPI2_BUS_CONFIG,
#endif
#ifdef BSP_USING_SPI3
SPI3_BUS_CONFIG,
#endif
};
static struct mm32_spi spi_bus_obj[sizeof(spi_config) / sizeof(spi_config[0])] = {0};
static rt_err_t mm32_spi_init(struct mm32_spi *spi_drv, struct rt_spi_configuration *cfg)
{
RT_ASSERT(spi_drv != RT_NULL);
RT_ASSERT(cfg != RT_NULL);
SPI_Master_Init_Type *spi_handle = &spi_drv->handle;
spi_handle->ClockFreqHz = Drv_Get_APB1_Clock();
if (cfg->data_width == 8)
{
spi_handle->DataWidth = SPI_DataWidth_8b;
}
else if (cfg->data_width == 16)
{
spi_handle->DataWidth = SPI_DataWidth_8b;
}
else
{
return RT_EIO;
}
if (cfg->mode & RT_SPI_CPOL)
{
spi_handle->PolarityPhase = SPI_PolarityPhase_Alt0;
}
else
{
spi_handle->PolarityPhase = SPI_PolarityPhase_Alt1;
}
if (cfg->mode & RT_SPI_NO_CS)
{
spi_handle->AutoCS = RT_FALSE;
}
else
{
spi_handle->AutoCS = RT_TRUE;
}
uint32_t SPI_APB_CLOCK;
SPI_APB_CLOCK = Drv_Get_APB1_Clock();
if (cfg->max_hz >= SPI_APB_CLOCK / 2)
{
spi_handle->BaudRate= (SPI_APB_CLOCK>>1);
}
else
{
spi_handle->BaudRate = cfg->max_hz;
}
LOG_D("sys freq: %d, pclk2 freq: %d, SPI limiting freq: %d, BaudRatePrescaler: %d",
HAL_RCC_GetSysClockFreq(),
SPI_APB_CLOCK,
cfg->max_hz,
spi_handle->BaudRate);
if (cfg->mode & RT_SPI_MSB)
{
spi_handle->LSB = RT_FALSE;
}
else
{
spi_handle->LSB = RT_TRUE;
}
spi_handle->XferMode = SPI_XferMode_TxRx;
extern void SPI_MspInit(SPI_Type *mspi, , uint8_t autocs);
SPI_MspInit(spi_drv->config->Instance, cfg->mode & RT_SPI_NO_CS);
SPI_InitMaster(spi_drv->config->Instance, spi_handle);
/* DMA configuration */
extern int DMA_MspInit(DMA_Channel_Init_Type handle, \
DMA_Type *dma, \
uint32_t req, \
IRQn_Type irqn, \
rt_uint32_t rcc, \
uint8_t *buf, \
uint16_t buf_len);
if (spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG)
{
int ret = DMA_MspInit(spi_drv->dma.handle_rx, \
spi_drv->config->dma_rx->Instance, \
spi_drv->config->dma_rx->dma_req, \
spi_drv->config->dma_rx->dma_irq, \
spi_drv->config->dma_rx->dma_rcc, \
spi_drv->dma.rx_buf_len, \
spi_drv->dma.rx_buf);
if(ret == -1)
{
LOG_D("%s init DMA failed.\r\n", spi_drv->config->bus_name);
return RT_ERROR;
}
SPI_EnableDMA(spi_drv->config->dma_rx->Instance, RT_TRUE);
}
if (spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG)
{
int ret = DMA_MspInit(spi_drv->dma.handle_tx, \
spi_drv->config->dma_tx->Instance, \
spi_drv->config->dma_tx->dma_req, \
spi_drv->config->dma_tx->dma_irq, \
spi_drv->config->dma_tx->dma_rcc,
spi_drv->dma.tx_buf_len, \
spi_drv->dma.tx_buf);
if(ret == -1)
{
LOG_D("%s init DMA failed.\r\n", spi_drv->config->bus_name);
return RT_ERROR;
}
SPI_EnableDMA(spi_drv->config->dma_tx->Instance, RT_TRUE);
}
SPI_Enable(spi_drv->config->Instance, RT_TRUE);
LOG_D("%s init done", spi_drv->config->bus_name);
return RT_EOK;
}
static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
{
HAL_StatusTypeDef state;
rt_size_t message_length, already_send_length;
rt_uint16_t send_length;
rt_uint8_t *recv_buf;
const rt_uint8_t *send_buf;
RT_ASSERT(device != RT_NULL);
RT_ASSERT(device->bus != RT_NULL);
RT_ASSERT(device->bus->parent.user_data != RT_NULL);
RT_ASSERT(message != RT_NULL);
struct mm32_spi *spi_drv = rt_container_of(device->bus, struct mm32_spi, spi_bus);
SPI_Master_Init_Type *spi_handle = &spi_drv->handle;
struct mm32_hw_spi_cs *cs = device->parent.user_data;
if (message->cs_take)
{
GPIO_WriteBit(cs->GPIOx, cs->GPIO_Pin, 0);
}
LOG_D("%s transfer prepare and start", spi_drv->config->bus_name);
LOG_D("%s sendbuf: %X, recvbuf: %X, length: %d",
spi_drv->config->bus_name,
(uint32_t)message->send_buf,
(uint32_t)message->recv_buf, message->length);
message_length = message->length;
recv_buf = message->recv_buf;
send_buf = message->send_buf;
while (message_length)
{
/* the HAL library use uint16 to save the data length */
if (message_length > 65535)
{
send_length = 65535;
message_length = message_length - 65535;
}
else
{
send_length = message_length;
message_length = 0;
}
/* calculate the start address */
already_send_length = message->length - send_length - message_length;
send_buf = (rt_uint8_t *)message->send_buf + already_send_length;
recv_buf = (rt_uint8_t *)message->recv_buf + already_send_length;
/* start once data exchange in DMA mode */
if (message->send_buf && message->recv_buf)
{
if ((spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG) && (spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG))
{
state = HAL_SPI_TransmitReceive_DMA(spi_handle, (uint8_t *)send_buf, (uint8_t *)recv_buf, send_length);
}
else
{
state = HAL_SPI_TransmitReceive(spi_handle, (uint8_t *)send_buf, (uint8_t *)recv_buf, send_length, 1000);
}
}
else if (message->send_buf)
{
if (spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG)
{
state = HAL_SPI_Transmit_DMA(spi_handle, (uint8_t *)send_buf, send_length);
}
else
{
state = HAL_SPI_Transmit(spi_handle, (uint8_t *)send_buf, send_length, 1000);
}
}
else
{
memset((uint8_t *)recv_buf, 0xff, send_length);
if (spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG)
{
state = HAL_SPI_Receive_DMA(spi_handle, (uint8_t *)recv_buf, send_length);
}
else
{
state = HAL_SPI_Receive(spi_handle, (uint8_t *)recv_buf, send_length, 1000);
}
}
if (state != HAL_OK)
{
LOG_I("spi transfer error : %d", state);
message->length = 0;
spi_handle->State = HAL_SPI_STATE_READY;
}
else
{
LOG_D("%s transfer done", spi_drv->config->bus_name);
}
/* For simplicity reasons, this example is just waiting till the end of the
transfer, but application may perform other tasks while transfer operation
is ongoing. */
while (HAL_SPI_GetState(spi_handle) != HAL_SPI_STATE_READY);
}
if (message->cs_release)
{
HAL_GPIO_WritePin(cs->GPIOx, cs->GPIO_Pin, GPIO_PIN_SET);
}
return message->length;
}
static rt_err_t spi_configure(struct rt_spi_device *device,
struct rt_spi_configuration *configuration)
{
RT_ASSERT(device != RT_NULL);
RT_ASSERT(configuration != RT_NULL);
struct mm32_spi *spi_drv = rt_container_of(device->bus, struct mm32_spi, spi_bus);
spi_drv->cfg = configuration;
return mm32_spi_init(spi_drv, configuration);
}
static const struct rt_spi_ops stm_spi_ops =
{
.configure = spi_configure,
.xfer = spixfer,
};
static int rt_hw_spi_bus_init(void)
{
rt_err_t result;
for (int i = 0; i < sizeof(spi_config) / sizeof(spi_config[0]); i++)
{
spi_bus_obj[i].config = &spi_config[i];
spi_bus_obj[i].spi_bus.parent.user_data = &spi_config[i];
spi_bus_obj[i].handle.Instance = spi_config[i].Instance;
if (spi_bus_obj[i].spi_dma_flag & SPI_USING_RX_DMA_FLAG)
{
/* Configure the DMA handler for Transmission process */
spi_bus_obj[i].dma.handle_rx.Instance = spi_config[i].dma_rx->Instance;
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
spi_bus_obj[i].dma.handle_rx.Init.Channel = spi_config[i].dma_rx->channel;
#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0)
spi_bus_obj[i].dma.handle_rx.Init.Request = spi_config[i].dma_rx->request;
#endif
spi_bus_obj[i].dma.handle_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
spi_bus_obj[i].dma.handle_rx.Init.PeriphInc = DMA_PINC_DISABLE;
spi_bus_obj[i].dma.handle_rx.Init.MemInc = DMA_MINC_ENABLE;
spi_bus_obj[i].dma.handle_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
spi_bus_obj[i].dma.handle_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
spi_bus_obj[i].dma.handle_rx.Init.Mode = DMA_NORMAL;
spi_bus_obj[i].dma.handle_rx.Init.Priority = DMA_PRIORITY_HIGH;
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
spi_bus_obj[i].dma.handle_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
spi_bus_obj[i].dma.handle_rx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
spi_bus_obj[i].dma.handle_rx.Init.MemBurst = DMA_MBURST_INC4;
spi_bus_obj[i].dma.handle_rx.Init.PeriphBurst = DMA_PBURST_INC4;
#endif
{
rt_uint32_t tmpreg = 0x00U;
#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32F0)
/* enable DMA clock && Delay after an RCC peripheral clock enabling*/
SET_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc);
tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc);
#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
SET_BIT(RCC->AHB1ENR, spi_config[i].dma_rx->dma_rcc);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->AHB1ENR, spi_config[i].dma_rx->dma_rcc);
#endif
UNUSED(tmpreg); /* To avoid compiler warnings */
}
}
if (spi_bus_obj[i].spi_dma_flag & SPI_USING_TX_DMA_FLAG)
{
/* Configure the DMA handler for Transmission process */
spi_bus_obj[i].dma.handle_tx.Instance = spi_config[i].dma_tx->Instance;
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
spi_bus_obj[i].dma.handle_tx.Init.Channel = spi_config[i].dma_tx->channel;
#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0)
spi_bus_obj[i].dma.handle_tx.Init.Request = spi_config[i].dma_tx->request;
#endif
spi_bus_obj[i].dma.handle_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
spi_bus_obj[i].dma.handle_tx.Init.PeriphInc = DMA_PINC_DISABLE;
spi_bus_obj[i].dma.handle_tx.Init.MemInc = DMA_MINC_ENABLE;
spi_bus_obj[i].dma.handle_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
spi_bus_obj[i].dma.handle_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
spi_bus_obj[i].dma.handle_tx.Init.Mode = DMA_NORMAL;
spi_bus_obj[i].dma.handle_tx.Init.Priority = DMA_PRIORITY_LOW;
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
spi_bus_obj[i].dma.handle_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
spi_bus_obj[i].dma.handle_tx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
spi_bus_obj[i].dma.handle_tx.Init.MemBurst = DMA_MBURST_INC4;
spi_bus_obj[i].dma.handle_tx.Init.PeriphBurst = DMA_PBURST_INC4;
#endif
{
rt_uint32_t tmpreg = 0x00U;
#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32F0)
/* enable DMA clock && Delay after an RCC peripheral clock enabling*/
SET_BIT(RCC->AHBENR, spi_config[i].dma_tx->dma_rcc);
tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_tx->dma_rcc);
#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
SET_BIT(RCC->AHB1ENR, spi_config[i].dma_tx->dma_rcc);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->AHB1ENR, spi_config[i].dma_tx->dma_rcc);
#endif
UNUSED(tmpreg); /* To avoid compiler warnings */
}
}
result = rt_spi_bus_register(&spi_bus_obj[i].spi_bus, spi_config[i].bus_name, &stm_spi_ops);
RT_ASSERT(result == RT_EOK);
LOG_D("%s bus init done", spi_config[i].bus_name);
}
return result;
}
/**
* Attach the spi device to SPI bus, this function must be used after initialization.
*/
rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, GPIO_TypeDef *cs_gpiox, uint16_t cs_gpio_pin)
{
RT_ASSERT(bus_name != RT_NULL);
RT_ASSERT(device_name != RT_NULL);
rt_err_t result;
struct rt_spi_device *spi_device;
struct mm32_hw_spi_cs *cs_pin;
/* initialize the cs pin && select the slave*/
GPIO_InitTypeDef GPIO_Initure;
GPIO_Initure.Pin = cs_gpio_pin;
GPIO_Initure.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_Initure.Pull = GPIO_PULLUP;
GPIO_Initure.Speed = GPIO_SPEED_FREQ_HIGH;
HAL_GPIO_Init(cs_gpiox, &GPIO_Initure);
HAL_GPIO_WritePin(cs_gpiox, cs_gpio_pin, GPIO_PIN_SET);
/* attach the device to spi bus*/
spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
RT_ASSERT(spi_device != RT_NULL);
cs_pin = (struct mm32_hw_spi_cs *)rt_malloc(sizeof(struct mm32_hw_spi_cs));
RT_ASSERT(cs_pin != RT_NULL);
cs_pin->GPIOx = cs_gpiox;
cs_pin->GPIO_Pin = cs_gpio_pin;
result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin);
if (result != RT_EOK)
{
LOG_E("%s attach to %s faild, %d\n", device_name, bus_name, result);
}
RT_ASSERT(result == RT_EOK);
LOG_D("%s attach to %s done", device_name, bus_name);
return result;
}
#if defined(BSP_SPI1_TX_USING_DMA) || defined(BSP_SPI1_RX_USING_DMA)
void SPI1_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
HAL_SPI_IRQHandler(&spi_bus_obj[SPI1_INDEX].handle);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#if defined(BSP_USING_SPI1) && defined(BSP_SPI1_RX_USING_DMA)
/**
* @brief This function handles DMA Rx interrupt request.
* @param None
* @retval None
*/
void SPI1_DMA_RX_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
HAL_DMA_IRQHandler(&spi_bus_obj[SPI1_INDEX].dma.handle_rx);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#if defined(BSP_USING_SPI1) && defined(BSP_SPI1_TX_USING_DMA)
/**
* @brief This function handles DMA Tx interrupt request.
* @param None
* @retval None
*/
void SPI1_DMA_TX_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
HAL_DMA_IRQHandler(&spi_bus_obj[SPI1_INDEX].dma.handle_tx);
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* defined(BSP_USING_SPI1) && defined(BSP_SPI_USING_DMA) */
#if defined(BSP_SPI2_TX_USING_DMA) || defined(BSP_SPI2_RX_USING_DMA)
void SPI2_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
HAL_SPI_IRQHandler(&spi_bus_obj[SPI2_INDEX].handle);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#if defined(BSP_USING_SPI2) && defined(BSP_SPI2_RX_USING_DMA)
/**
* @brief This function handles DMA Rx interrupt request.
* @param None
* @retval None
*/
void SPI2_DMA_RX_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
HAL_DMA_IRQHandler(&spi_bus_obj[SPI2_INDEX].dma.handle_rx);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#if defined(BSP_USING_SPI2) && defined(BSP_SPI2_TX_USING_DMA)
/**
* @brief This function handles DMA Tx interrupt request.
* @param None
* @retval None
*/
void SPI2_DMA_TX_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
HAL_DMA_IRQHandler(&spi_bus_obj[SPI2_INDEX].dma.handle_tx);
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* defined(BSP_USING_SPI2) && defined(BSP_SPI_USING_DMA) */
#if defined(BSP_SPI3_TX_USING_DMA) || defined(BSP_SPI3_RX_USING_DMA)
void SPI3_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
HAL_SPI_IRQHandler(&spi_bus_obj[SPI3_INDEX].handle);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#if defined(BSP_USING_SPI3) && defined(BSP_SPI3_RX_USING_DMA)
/**
* @brief This function handles DMA Rx interrupt request.
* @param None
* @retval None
*/
void SPI3_DMA_RX_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
HAL_DMA_IRQHandler(&spi_bus_obj[SPI3_INDEX].dma.handle_rx);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#if defined(BSP_USING_SPI3) && defined(BSP_SPI3_TX_USING_DMA)
/**
* @brief This function handles DMA Tx interrupt request.
* @param None
* @retval None
*/
void SPI3_DMA_TX_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
HAL_DMA_IRQHandler(&spi_bus_obj[SPI3_INDEX].dma.handle_tx);
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* defined(BSP_USING_SPI3) && defined(BSP_SPI_USING_DMA) */
#if defined(BSP_SPI4_TX_USING_DMA) || defined(BSP_SPI4_RX_USING_DMA)
void SPI4_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
HAL_SPI_IRQHandler(&spi_bus_obj[SPI4_INDEX].handle);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#if defined(BSP_USING_SPI4) && defined(BSP_SPI4_RX_USING_DMA)
/**
* @brief This function handles DMA Rx interrupt request.
* @param None
* @retval None
*/
void SPI4_DMA_RX_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
HAL_DMA_IRQHandler(&spi_bus_obj[SPI4_INDEX].dma.handle_rx);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#if defined(BSP_USING_SPI4) && defined(BSP_SPI4_TX_USING_DMA)
/**
* @brief This function handles DMA Tx interrupt request.
* @param None
* @retval None
*/
void SPI4_DMA_TX_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
HAL_DMA_IRQHandler(&spi_bus_obj[SPI4_INDEX].dma.handle_tx);
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* defined(BSP_USING_SPI4) && defined(BSP_SPI_USING_DMA) */
#if defined(BSP_SPI5_TX_USING_DMA) || defined(BSP_SPI5_RX_USING_DMA)
void SPI5_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
HAL_SPI_IRQHandler(&spi_bus_obj[SPI5_INDEX].handle);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#if defined(BSP_USING_SPI5) && defined(BSP_SPI5_RX_USING_DMA)
/**
* @brief This function handles DMA Rx interrupt request.
* @param None
* @retval None
*/
void SPI5_DMA_RX_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
HAL_DMA_IRQHandler(&spi_bus_obj[SPI5_INDEX].dma.handle_rx);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#if defined(BSP_USING_SPI5) && defined(BSP_SPI5_TX_USING_DMA)
/**
* @brief This function handles DMA Tx interrupt request.
* @param None
* @retval None
*/
void SPI5_DMA_TX_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
HAL_DMA_IRQHandler(&spi_bus_obj[SPI5_INDEX].dma.handle_tx);
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* defined(BSP_USING_SPI5) && defined(BSP_SPI_USING_DMA) */
#if defined(BSP_USING_SPI6) && defined(BSP_SPI6_RX_USING_DMA)
/**
* @brief This function handles DMA Rx interrupt request.
* @param None
* @retval None
*/
void SPI6_DMA_RX_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
HAL_DMA_IRQHandler(&spi_bus_obj[SPI6_INDEX].dma.handle_rx);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#if defined(BSP_USING_SPI6) && defined(BSP_SPI6_TX_USING_DMA)
/**
* @brief This function handles DMA Tx interrupt request.
* @param None
* @retval None
*/
void SPI6_DMA_TX_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
HAL_DMA_IRQHandler(&spi_bus_obj[SPI6_INDEX].dma.handle_tx);
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* defined(BSP_USING_SPI6) && defined(BSP_SPI_USING_DMA) */
static void mm32_get_dma_info(void)
{
#ifdef BSP_SPI1_RX_USING_DMA
spi_bus_obj[SPI1_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG;
static struct dma_config spi1_dma_rx = SPI1_RX_DMA_CONFIG;
spi_config[SPI1_INDEX].dma_rx = &spi1_dma_rx;
#endif
#ifdef BSP_SPI1_TX_USING_DMA
spi_bus_obj[SPI1_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG;
static struct dma_config spi1_dma_tx = SPI1_TX_DMA_CONFIG;
spi_config[SPI1_INDEX].dma_tx = &spi1_dma_tx;
#endif
#ifdef BSP_SPI2_RX_USING_DMA
spi_bus_obj[SPI2_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG;
static struct dma_config spi2_dma_rx = SPI2_RX_DMA_CONFIG;
spi_config[SPI2_INDEX].dma_rx = &spi2_dma_rx;
#endif
#ifdef BSP_SPI2_TX_USING_DMA
spi_bus_obj[SPI2_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG;
static struct dma_config spi2_dma_tx = SPI2_TX_DMA_CONFIG;
spi_config[SPI2_INDEX].dma_tx = &spi2_dma_tx;
#endif
#ifdef BSP_SPI3_RX_USING_DMA
spi_bus_obj[SPI3_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG;
static struct dma_config spi3_dma_rx = SPI3_RX_DMA_CONFIG;
spi_config[SPI3_INDEX].dma_rx = &spi3_dma_rx;
#endif
#ifdef BSP_SPI3_TX_USING_DMA
spi_bus_obj[SPI3_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG;
static struct dma_config spi3_dma_tx = SPI3_TX_DMA_CONFIG;
spi_config[SPI3_INDEX].dma_tx = &spi3_dma_tx;
#endif
#ifdef BSP_SPI4_RX_USING_DMA
spi_bus_obj[SPI4_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG;
static struct dma_config spi4_dma_rx = SPI4_RX_DMA_CONFIG;
spi_config[SPI4_INDEX].dma_rx = &spi4_dma_rx;
#endif
#ifdef BSP_SPI4_TX_USING_DMA
spi_bus_obj[SPI4_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG;
static struct dma_config spi4_dma_tx = SPI4_TX_DMA_CONFIG;
spi_config[SPI4_INDEX].dma_tx = &spi4_dma_tx;
#endif
#ifdef BSP_SPI5_RX_USING_DMA
spi_bus_obj[SPI5_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG;
static struct dma_config spi5_dma_rx = SPI5_RX_DMA_CONFIG;
spi_config[SPI5_INDEX].dma_rx = &spi5_dma_rx;
#endif
#ifdef BSP_SPI5_TX_USING_DMA
spi_bus_obj[SPI5_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG;
static struct dma_config spi5_dma_tx = SPI5_TX_DMA_CONFIG;
spi_config[SPI5_INDEX].dma_tx = &spi5_dma_tx;
#endif
#ifdef BSP_SPI6_RX_USING_DMA
spi_bus_obj[SPI6_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG;
static struct dma_config spi6_dma_rx = SPI6_RX_DMA_CONFIG;
spi_config[SPI6_INDEX].dma_rx = &spi6_dma_rx;
#endif
#ifdef BSP_SPI6_TX_USING_DMA
spi_bus_obj[SPI6_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG;
static struct dma_config spi6_dma_tx = SPI6_TX_DMA_CONFIG;
spi_config[SPI6_INDEX].dma_tx = &spi6_dma_tx;
#endif
}
#if defined(SOC_SERIES_STM32F0)
void SPI1_DMA_RX_TX_IRQHandler(void)
{
#if defined(BSP_USING_SPI1) && defined(BSP_SPI1_TX_USING_DMA)
SPI1_DMA_TX_IRQHandler();
#endif
#if defined(BSP_USING_SPI1) && defined(BSP_SPI1_RX_USING_DMA)
SPI1_DMA_RX_IRQHandler();
#endif
}
void SPI2_DMA_RX_TX_IRQHandler(void)
{
#if defined(BSP_USING_SPI2) && defined(BSP_SPI2_TX_USING_DMA)
SPI2_DMA_TX_IRQHandler();
#endif
#if defined(BSP_USING_SPI2) && defined(BSP_SPI2_RX_USING_DMA)
SPI2_DMA_RX_IRQHandler();
#endif
}
#endif /* SOC_SERIES_STM32F0 */
int rt_hw_spi_init(void)
{
mm32_get_dma_info();
return rt_hw_spi_bus_init();
}
INIT_BOARD_EXPORT(rt_hw_spi_init);
#endif /* BSP_USING_SPI1 || BSP_USING_SPI2 || BSP_USING_SPI3 */
#endif /* RT_USING_SPI */

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/**
* @file drv_spi.h
* @author 100ask development team
* @brief
* @version 0.1
* @date 2022-06-16
*
* @copyright Copyright (c) 2022 Chongqing 100ASK Technology Co., LTD
*
*/
#ifndef __DRV_SPI_H_
#define __DRV_SPI_H_
#include <rtthread.h>
#include "rtdevice.h"
#include <rthw.h>
#include "drv_common.h"
#include "drv_dma.h"
rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, GPIO_TypeDef* cs_gpiox, uint16_t cs_gpio_pin);
struct mm32_hw_spi_cs
{
GPIO_Type* GPIOx;
uint16_t GPIO_Pin;
};
struct mm32_spi_config
{
SPI_Type *Instance;
char *bus_name;
struct dma_config *dma_rx, *dma_tx;
};
struct stm32_spi_device
{
rt_uint32_t pin;
char *bus_name;
char *device_name;
};
#define SPI_USING_RX_DMA_FLAG (1<<0)
#define SPI_USING_TX_DMA_FLAG (1<<1)
/* stm32 spi dirver class */
struct mm32_spi
{
SPI_Master_Init_Type handle;
struct mm32_spi_config *config;
struct rt_spi_configuration *cfg;
struct
{
rt_uint16_t rx_buf_len;
rt_uint8_t *rx_buf;
DMA_Channel_Init_Type handle_rx;
rt_uint16_t tx_buf_len;
rt_uint8_t *tx_buf;
DMA_Channel_Init_Type handle_tx;
} dma;
rt_uint8_t spi_dma_flag;
struct rt_spi_bus spi_bus;
};
#endif /* __DRV_SPI_H_ */

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/*
* Copyright (c) 2020-2022, CQ 100ask Development Team
*
* Change Logs:
* Date Author Notes
* 2022-05-29 Alen first version
*/
#include "board.h"
#include "drv_uart.h"
#include "drv_config.h"
#ifdef RT_USING_SERIAL
//#define DRV_DEBUG
#define LOG_TAG "drv.usart"
#if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3) && \
!defined(BSP_USING_UART4) && !defined(BSP_USING_UART5) && !defined(BSP_USING_UART6) && \
!defined(BSP_USING_UART7) && !defined(BSP_USING_UART8)
#error "Please define at least one BSP_USING_UARTx"
/* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
#endif
#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->CSR & (__FLAG__)) == (__FLAG__))
#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->CSR = ~(__FLAG__))
#define __HAL_UART_GET_INT_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->ISR & (__FLAG__)) == (__FLAG__))
#define __HAL_UART_CLEAR_INT_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->ICR &= (__FLAG__))
enum
{
#ifdef BSP_USING_UART1
UART1_INDEX,
#endif
#ifdef BSP_USING_UART2
UART2_INDEX,
#endif
#ifdef BSP_USING_UART3
UART3_INDEX,
#endif
#ifdef BSP_USING_UART4
UART4_INDEX,
#endif
#ifdef BSP_USING_UART5
UART5_INDEX,
#endif
#ifdef BSP_USING_UART6
UART6_INDEX,
#endif
#ifdef BSP_USING_UART7
UART7_INDEX,
#endif
#ifdef BSP_USING_UART8
UART8_INDEX,
#endif
#ifdef BSP_USING_LPUART1
LPUART1_INDEX,
#endif
};
static struct mm32_uart_config uart_config[] =
{
#ifdef BSP_USING_UART1
UART1_CONFIG,
#endif
#ifdef BSP_USING_UART2
UART2_CONFIG,
#endif
#ifdef BSP_USING_UART3
UART3_CONFIG,
#endif
#ifdef BSP_USING_UART4
UART4_CONFIG,
#endif
#ifdef BSP_USING_UART5
UART5_CONFIG,
#endif
#ifdef BSP_USING_UART6
UART6_CONFIG,
#endif
#ifdef BSP_USING_UART7
UART7_CONFIG,
#endif
#ifdef BSP_USING_UART8
UART8_CONFIG,
#endif
#ifdef BSP_USING_LPUART1
LPUART1_CONFIG,
#endif
};
static struct mm32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0};
static rt_err_t mm32_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
{
struct mm32_uart *uart;
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(cfg != RT_NULL);
uart = rt_container_of(serial, struct mm32_uart, serial);
uart->handle.ClockFreqHz = HAL_Get_APB2_Clock();
uart->handle.BaudRate = cfg->baud_rate;
uart->handle.XferMode = UART_XferMode_RxTx;
switch (cfg->flowcontrol)
{
case RT_SERIAL_FLOWCONTROL_NONE:
uart->handle.HwFlowControl = UART_HwFlowControl_None;
break;
case RT_SERIAL_FLOWCONTROL_CTSRTS:
uart->handle.HwFlowControl = UART_HwFlowControl_RTS_CTS;
break;
default:
uart->handle.HwFlowControl = UART_HwFlowControl_None;
break;
}
switch (cfg->data_bits)
{
case DATA_BITS_5:
uart->handle.WordLength = UART_WordLength_5b;
break;
case DATA_BITS_6:
uart->handle.WordLength = UART_WordLength_6b;
break;
case DATA_BITS_7:
uart->handle.WordLength = UART_WordLength_7b;
break;
case DATA_BITS_8:
uart->handle.WordLength = UART_WordLength_8b;
break;
default:
uart->handle.WordLength = UART_WordLength_8b;
break;
}
switch (cfg->stop_bits)
{
case STOP_BITS_1:
uart->handle.StopBits = UART_StopBits_1;
break;
case STOP_BITS_2:
uart->handle.StopBits = UART_StopBits_2;
break;
default:
uart->handle.StopBits = UART_StopBits_1;
break;
}
switch (cfg->parity)
{
case PARITY_NONE:
uart->handle.Parity = UART_Parity_None;
break;
case PARITY_ODD:
uart->handle.Parity = UART_Parity_Odd;
break;
case PARITY_EVEN:
uart->handle.Parity = UART_Parity_Even;
break;
default:
uart->handle.Parity = UART_Parity_None;
break;
}
#ifdef RT_SERIAL_USING_DMA
if (!(serial->parent.open_flag & RT_DEVICE_OFLAG_OPEN)) {
uart->dma_rx.last_index = 0;
}
#endif
extern void UART_MspInit(UART_Type *muart);
UART_MspInit(uart->config->Instance);
UART_Init(uart->config->Instance, &uart->handle);
UART_Enable(uart->config->Instance, true);
return RT_EOK;
}
static rt_err_t mm32_control(struct rt_serial_device *serial, int cmd, void *arg)
{
struct mm32_uart *uart;
rt_uint32_t prioritygroup = 0x00U;
#ifdef RT_SERIAL_USING_DMA
rt_ubase_t ctrl_arg = (rt_ubase_t)arg;
#endif
RT_ASSERT(serial != RT_NULL);
uart = rt_container_of(serial, struct mm32_uart, serial);
switch (cmd)
{
/* disable interrupt */
case RT_DEVICE_CTRL_CLR_INT:
/* disable rx irq */
NVIC_DisableIRQ(uart->config->irq_type);
#ifdef RT_SERIAL_USING_DMA
/* disable DMA */
if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX)
{
}
else if(ctrl_arg == RT_DEVICE_FLAG_DMA_TX)
{
}
#endif
break;
/* enable interrupt */
case RT_DEVICE_CTRL_SET_INT:
/* enable rx irq */
UART_EnableInterrupts(uart->config->Instance, UART_INT_RX_DONE, true);
prioritygroup = NVIC_GetPriorityGrouping();
NVIC_SetPriority(SysTick_IRQn, NVIC_EncodePriority(prioritygroup, 1, 0));
NVIC_EnableIRQ(uart->config->irq_type);
break;
#ifdef RT_SERIAL_USING_DMA
case RT_DEVICE_CTRL_CONFIG:
break;
#endif
case RT_DEVICE_CTRL_CLOSE:
break;
}
return RT_EOK;
}
rt_uint32_t mm32_uart_get_mask(rt_uint32_t word_length, rt_uint32_t parity)
{
rt_uint32_t mask;
if (word_length == UART_WordLength_8b)
{
if (parity == UART_Parity_None)
{
mask = 0x00FFU ;
}
else
{
mask = 0x007FU ;
}
}
#ifdef UART_WORDLENGTH_7B
else if (word_length == UART_WordLength_7b)
{
if (parity == UART_Parity_None)
{
mask = 0x007FU ;
}
else
{
mask = 0x003FU ;
}
}
else
{
mask = 0x0000U;
}
#endif
return mask;
}
static int mm32_putc(struct rt_serial_device *serial, char c)
{
struct mm32_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = rt_container_of(serial, struct mm32_uart, serial);
uart->config->Instance->TDR = c;
while ( 0u == (UART_STATUS_TX_EMPTY & UART_GetStatus(uart->config->Instance)) )
{}
return 1;
}
static int mm32_getc(struct rt_serial_device *serial)
{
int ch;
struct mm32_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = rt_container_of(serial, struct mm32_uart, serial);
ch = -1;
if ((UART_STATUS_RX_DONE & UART_GetStatus(uart->config->Instance)) != 0)
{
ch = uart->config->Instance->RDR & mm32_uart_get_mask(uart->handle.WordLength, uart->handle.Parity);
}
return ch;
}
/**
* Uart common interrupt process. This need add to uart ISR.
*
* @param serial serial device
*/
static void uart_isr(struct rt_serial_device *serial)
{
struct mm32_uart *uart;
#ifdef RT_SERIAL_USING_DMA
rt_size_t recv_total_index, recv_len;
rt_base_t level;
#endif
RT_ASSERT(serial != RT_NULL);
uart = rt_container_of(serial, struct mm32_uart, serial);
/* UART in mode Receiver -------------------------------------------------*/
if ( (0u != __HAL_UART_GET_INT_FLAG(uart->config->Instance, UART_INT_RX_DONE))
&& (0u != __HAL_UART_GET_FLAG(uart->config->Instance, UART_STATUS_RX_DONE)) )
{
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
}
#ifdef RT_SERIAL_USING_DMA
#endif
else
{
if (__HAL_UART_GET_FLAG(uart->config->Instance, UART_STATUS_RX_DONE) != 0)
{
__HAL_UART_CLEAR_FLAG(uart->config->Instance, UART_STATUS_RX_DONE);
}
if (__HAL_UART_GET_FLAG(uart->config->Instance, UART_STATUS_TX_DONE) != 0)
{
__HAL_UART_CLEAR_FLAG(uart->config->Instance, UART_STATUS_TX_DONE);
}
if (__HAL_UART_GET_FLAG(uart->config->Instance, UART_STATUS_TX_FULL) != 0)
{
__HAL_UART_CLEAR_FLAG(uart->config->Instance, UART_STATUS_TX_FULL);
}
if (__HAL_UART_GET_FLAG(uart->config->Instance, UART_STATUS_TX_EMPTY) != 0)
{
__HAL_UART_CLEAR_FLAG(uart->config->Instance, UART_STATUS_TX_EMPTY);
}
if (__HAL_UART_GET_INT_FLAG(uart->config->Instance, UART_INT_RX_DONE) != 0)
{
__HAL_UART_CLEAR_INT_FLAG(uart->config->Instance, UART_INT_RX_DONE);
}
if (__HAL_UART_GET_INT_FLAG(uart->config->Instance, UART_INT_TX_DONE) != 0)
{
__HAL_UART_CLEAR_INT_FLAG(uart->config->Instance, UART_INT_TX_DONE);
}
if (__HAL_UART_GET_INT_FLAG(uart->config->Instance, UART_INT_TX_EMPTY) != 0)
{
__HAL_UART_CLEAR_INT_FLAG(uart->config->Instance, UART_INT_TX_EMPTY);
}
}
}
#if defined(BSP_USING_UART1)
void UART1_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
uart_isr(&(uart_obj[UART1_INDEX].serial));
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#if defined(BSP_USING_UART2)
void UART2_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
uart_isr(&(uart_obj[UART2_INDEX].serial));
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#if defined(BSP_USING_UART3)
void UART3_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
uart_isr(&(uart_obj[UART3_INDEX].serial));
/* leave interrupt */
rt_interrupt_leave();
}
#endif
static const struct rt_uart_ops mm32_uart_ops =
{
.configure = mm32_configure,
.control = mm32_control,
.putc = mm32_putc,
.getc = mm32_getc,
.dma_transmit = RT_NULL
};
int rt_hw_uart_init(void)
{
rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct mm32_uart);
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
rt_err_t result = 0;
for (int i = 0; i < obj_num; i++)
{
/* init UART object */
uart_obj[i].config = &uart_config[i];
uart_obj[i].serial.ops = &mm32_uart_ops;
uart_obj[i].serial.config = config;
/* register UART device */
result = rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name,
RT_DEVICE_FLAG_RDWR
| RT_DEVICE_FLAG_INT_RX
| RT_DEVICE_FLAG_INT_TX
| uart_obj[i].uart_dma_flag
, NULL);
RT_ASSERT(result == RT_EOK);
}
return result;
}
#endif /* RT_USING_SERIAL */

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/*
* Copyright (c) 2020-2022, CQ 100ask Development Team
*
* Change Logs:
* Date Author Notes
* 2022-05-29 Alen first version
*/
#ifndef __DRV_USART_H__
#define __DRV_USART_H__
#include <rtthread.h>
#include "rtdevice.h"
#include <rthw.h>
#include <drv_common.h>
int rt_hw_uart_init(void);
#define DMA_INSTANCE_TYPE MA_Channel_TypeDef
#define UART_INSTANCE_CLEAR_FUNCTION __HAL_UART_CLEAR_FLAG
/* stm32 config class */
struct mm32_uart_config
{
const char *name;
UART_Type *Instance;
IRQn_Type irq_type;
struct dma_config *dma_rx;
struct dma_config *dma_tx;
};
/* stm32 uart dirver class */
struct mm32_uart
{
UART_Init_Type handle;
struct mm32_uart_config *config;
#ifdef RT_SERIAL_USING_DMA
struct
{
DMA_Type handle;
rt_size_t last_index;
} dma_rx;
#endif
rt_uint16_t uart_dma_flag;
struct rt_serial_device serial;
};
#endif /* __DRV_USART_H__ */

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config SOC_FAMILY_MM32
bool
config SOC_SERIES_MM32F3277
bool
select ARCH_ARM_CORTEX_M3
select SOC_FAMILY_MM32

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bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Device/MM32/MM32F3277/Include/hal_device_registers.h Normal file
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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_DEVICE_REGISTER_H__
#define __HAL_DEVICE_REGISTER_H__
//#include "./mm32f327x/mm32_device.h"
#include "mm32f3277g.h"
#include "mm32f3277g_features.h"
#include "system_mm32f3277g.h"
#endif /* __HAL_DEVICE_REGISTER_H__ */

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bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Device/MM32/MM32F3277/Include/system_mm32f3277g.h Normal file
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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __SYSTEM_MM32F327X_H__
#define __SYSTEM_MM32F327X_H__
void SystemInit(void);
#endif /* __SYSTEM_MM32F327X_H__ */

16
bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Device/MM32/MM32F3277/Source/Templates/arm/linker/mm32f3277g_flash.sct Normal file
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; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x08000000 0x00080000 { ; load region size_region
ER_IROM1 0x08000000 0x00080000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_IRAM1 0x20000000 0x00020000 { ; RW data
.ANY (+RW +ZI)
}
}

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; ////////////////////////////////////////////////////////////////////////////////
; /// @file startup_mm32f327x_keil.s
; /// @author AE TEAM
; /// @brief THIS FILE PROVIDES ALL THE Device Startup File of MM32 Cortex-M
; /// Core Device for ARM KEIL toolchain.
; ////////////////////////////////////////////////////////////////////////////////
; /// @attention
; ///
; /// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
; /// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
; /// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
; /// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
; /// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
; /// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
; ///
; /// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
; //////////////////////////////////////////////////////////////////////////////
;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
__vector_table_0x1c
DCD 0 ; -9 Reserved
DCD 0 ; -8 Reserved
DCD 0 ; -7 Reserved
DCD 0 ; -6 Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; -3 Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler ; External Interrupts
DCD WWDG_IRQHandler ; 0 Window Watchdog
DCD PVD_IRQHandler ; 1 PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; 2 Tamper
DCD RTC_IRQHandler ; 3 RTC
DCD FLASH_IRQHandler ; 4 Flash
DCD RCC_CRS_IRQHandler ; 5 RCC
DCD EXTI0_IRQHandler ; 6 EXTI Line 0
DCD EXTI1_IRQHandler ; 7 EXTI Line 1
DCD EXTI2_IRQHandler ; 8 EXTI Line 2
DCD EXTI3_IRQHandler ; 9 EXTI Line 3
DCD EXTI4_IRQHandler ; 10 EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; 11 DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; 12 DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; 13 DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; 14 DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; 15 DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; 16 DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; 17 DMA1 Channel 7
DCD ADC1_2_IRQHandler ; 18 ADC1 and ADC2
DCD FlashCache_IRQHandler ; 19 FlashCache outage
DCD 0 ; 20 Reserved
DCD CAN1_RX_IRQHandler ; 21 CAN1_RX
DCD 0 ; 22 Reserved
DCD EXTI9_5_IRQHandler ; 23 EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; 24 TIM1 Break
DCD TIM1_UP_IRQHandler ; 25 TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; 26 TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; 27 TIM1 Capture Compare
DCD TIM2_IRQHandler ; 28 TIM2
DCD TIM3_IRQHandler ; 29 TIM3
DCD TIM4_IRQHandler ; 30 TIM4
DCD I2C1_IRQHandler ; 31 I2C1 Event
DCD 0 ; 32 Reserved
DCD I2C2_IRQHandler ; 33 I2C2 Event
DCD 0 ; 34 Reserved
DCD SPI1_IRQHandler ; 35 SPI1
DCD SPI2_IRQHandler ; 36 SPI2
DCD UART1_IRQHandler ; 37 UART1
DCD UART2_IRQHandler ; 38 UART2
DCD UART3_IRQHandler ; 39 UART3
DCD EXTI15_10_IRQHandler ; 40 EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; 41 RTC Alarm through EXTI Line 17
DCD OTG_FS_WKUP_IRQHandler ; 42 USB OTG FS Wakeup through EXTI line
DCD TIM8_BRK_IRQHandler ; 43 TIM8 Break
DCD TIM8_UP_IRQHandler ; 44 TIM8 Update
DCD TIM8_TRG_COM_IRQHandler ; 45 TIM8 Trigger and Commutation
DCD TIM8_CC_IRQHandler ; 46 TIM8 Capture Compare
DCD ADC3_IRQHandler ; 47 ADC3
DCD 0 ; 48 Reserved
DCD SDIO_IRQHandler ; 49 SDIO
DCD TIM5_IRQHandler ; 50 TIM5
DCD SPI3_IRQHandler ; 51 SPI3
DCD UART4_IRQHandler ; 52 UART4
DCD UART5_IRQHandler ; 53 UART5
DCD TIM6_IRQHandler ; 54 TIM6
DCD TIM7_IRQHandler ; 55 TIM7
DCD DMA2_Channel1_IRQHandler ; 56 DMA2 Channel 1
DCD DMA2_Channel2_IRQHandler ; 57 DMA2 Channel 2
DCD DMA2_Channel3_IRQHandler ; 58 DMA2 Channel 3
DCD DMA2_Channel4_IRQHandler ; 59 DMA2 Channel 4
DCD DMA2_Channel5_IRQHandler ; 60 DMA2 Channel 5
DCD ETH_IRQHandler ; 61 Ethernet
DCD 0 ; 62 Reserved
DCD 0 ; 63 Reserved
DCD COMP1_2_IRQHandler ; 64 COMP1,COMP2
DCD 0 ; 65 Reserved
DCD 0 ; 66 Reserved
DCD OTG_FS_IRQHandler ; 67 USB OTG_FullSpeed
DCD 0 ; 68 Reserved
DCD 0 ; 69 Reserved
DCD 0 ; 70 Reserved
DCD UART6_IRQHandler ; 71 UART6
DCD 0 ; 72 Reserved
DCD 0 ; 73 Reserved
DCD 0 ; 74 Reserved
DCD 0 ; 75 Reserved
DCD 0 ; 76 Reserved
DCD 0 ; 77 Reserved
DCD 0 ; 78 Reserved
DCD 0 ; 79 Reserved
DCD 0 ; 80 Reserved
DCD 0 ; 81 Reserved
DCD UART7_IRQHandler ; 82 UART7
DCD UART8_IRQHandler ; 83 UART8
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_CRS_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT FlashCache_IRQHandler [WEAK]
EXPORT CAN1_RX_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT I2C2_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM8_BRK_IRQHandler [WEAK]
EXPORT TIM8_UP_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT COMP1_2_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT UART6_IRQHandler [WEAK]
EXPORT UART7_IRQHandler [WEAK]
EXPORT UART8_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_CRS_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
FlashCache_IRQHandler
CAN1_RX_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_IRQHandler
I2C2_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM8_BRK_IRQHandler
TIM8_UP_IRQHandler
TIM8_TRG_COM_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
ETH_IRQHandler
COMP1_2_IRQHandler
OTG_FS_IRQHandler
UART6_IRQHandler
UART7_IRQHandler
UART8_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END

208
bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Device/MM32/MM32F3277/Source/Templates/gcc/linker/mm32f3277g_flash.ld Normal file
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/*
** ###################################################################
** Processors: MM32F3277G
**
** Compiler: GNU C Compiler
** Build: b211202
**
** Abstract:
** Linker file for the GNU C Compiler
**
** Copyright 2021 MindMotion Microelectronics Co., Ltd.
**
** SPDX-License-Identifier: BSD-3-Clause
**
**
** ###################################################################
*/
/* Entry Point */
ENTRY(Reset_Handler)
HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
/* Specify the memory areas */
MEMORY
{
m_interrupts (RX) : ORIGIN = 0x08000000, LENGTH = 0x00000400
m_text (RX) : ORIGIN = 0x08000400, LENGTH = 0x0007FC00 /* 512KB. */
m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 /* 128KB. */
}
/* Define output sections */
SECTIONS
{
/* The startup code goes first into internal flash */
.interrupts :
{
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
} > m_interrupts
/* The program code and other data goes into internal flash */
.text :
{
. = ALIGN(4);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
*(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
} > m_text
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > m_text
.ARM :
{
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} > m_text
.ctors :
{
__CTOR_LIST__ = .;
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
/* We don't want to include the .ctor section from
from the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__CTOR_END__ = .;
} > m_text
.dtors :
{
__DTOR_LIST__ = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
__DTOR_END__ = .;
} > m_text
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} > m_text
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} > m_text
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
} > m_text
__etext = .; /* define a global symbol at end of code */
__DATA_ROM = .; /* Symbol is used by startup for data initialization */
.data : AT(__DATA_ROM)
{
. = ALIGN(4);
__DATA_RAM = .;
__data_start__ = .; /* create a global symbol at data start */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
KEEP(*(.jcr*))
. = ALIGN(4);
__data_end__ = .; /* define a global symbol at data end */
} > m_data
__NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__);
.ncache.init : AT(__NDATA_ROM)
{
__noncachedata_start__ = .; /* create a global symbol at ncache data start */
*(NonCacheable.init)
. = ALIGN(4);
__noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
} > m_data
. = __noncachedata_init_end__;
.ncache :
{
*(NonCacheable)
. = ALIGN(4);
__noncachedata_end__ = .; /* define a global symbol at ncache data end */
} > m_data
__DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__);
text_end = ORIGIN(m_text) + LENGTH(m_text);
ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
/* Uninitialized data section */
.bss :
{
/* This is used by the startup in order to initialize the .bss section */
. = ALIGN(4);
__START_BSS = .;
__bss_start__ = .;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
__END_BSS = .;
} > m_data
.heap :
{
. = ALIGN(8);
__end__ = .;
PROVIDE(end = .);
__HeapBase = .;
. += HEAP_SIZE;
__HeapLimit = .;
__heap_limit = .; /* Add for _sbrk */
} > m_data
.stack :
{
. = ALIGN(8);
. += STACK_SIZE;
} > m_data
/* Initializes stack on the end of block */
__StackTop = ORIGIN(m_data) + LENGTH(m_data);
__StackLimit = __StackTop - STACK_SIZE;
PROVIDE(__stack = __StackTop);
.ARM.attributes 0 : { *(.ARM.attributes) }
ASSERT(__StackLimit >= __HeapLimit, "region m_data_2 overflowed with stack and heap")
}

399
bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Device/MM32/MM32F3277/Source/Templates/gcc/startup_mm32f3270.s Normal file
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/* ------------------------------------------------------------------------- */
/* @file: startup_MM32F3270.s */
/* @purpose: CMSIS Cortex-M3 Core Device Startup File */
/* */
/* @version: 1.0 */
/* @date: 2021-7-21 */
/* @build: b210721 */
/* ------------------------------------------------------------------------- */
/* */
/* Copyright 2021 MindMotion */
/* All rights reserved. */
/* */
/* SPDX-License-Identifier: BSD-3-Clause */
/*****************************************************************************/
/* Version: GCC for ARM Embedded Processors */
/*****************************************************************************/
.syntax unified
.arch armv7-m
.section .isr_vector, "a"
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler*/
.long HardFault_Handler /* Hard Fault Handler*/
.long MemManage_Handler /* MPU Fault Handler*/
.long BusFault_Handler /* Bus Fault Handler*/
.long UsageFault_Handler /* Usage Fault Handler*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long SVC_Handler /* SVCall Handler*/
.long DebugMon_Handler /* Debug Monitor Handler*/
.long 0 /* Reserved*/
.long PendSV_Handler /* PendSV Handler*/
.long SysTick_Handler /* SysTick Handler*/
.long WWDG_IRQHandler /* 0 Window Watchdog */
.long PVD_IRQHandler /* 1 PVD through EXTI Line detect */
.long TAMPER_IRQHandler /* 2 Tamper */
.long RTC_IRQHandler /* 3 RTC */
.long FLASH_IRQHandler /* 4 Flash */
.long RCC_CRS_IRQHandler /* 5 RCC */
.long EXTI0_IRQHandler /* 6 EXTI Line 0 */
.long EXTI1_IRQHandler /* 7 EXTI Line 1 */
.long EXTI2_IRQHandler /* 8 EXTI Line 2 */
.long EXTI3_IRQHandler /* 9 EXTI Line 3 */
.long EXTI4_IRQHandler /* 10 EXTI Line 4 */
.long DMA1_Channel1_IRQHandler /* 11 DMA1 Channel 1 */
.long DMA1_Channel2_IRQHandler /* 12 DMA1 Channel 2 */
.long DMA1_Channel3_IRQHandler /* 13 DMA1 Channel 3 */
.long DMA1_Channel4_IRQHandler /* 14 DMA1 Channel 4 */
.long DMA1_Channel5_IRQHandler /* 15 DMA1 Channel 5 */
.long DMA1_Channel6_IRQHandler /* 16 DMA1 Channel 6 */
.long DMA1_Channel7_IRQHandler /* 17 DMA1 Channel 7 */
.long ADC1_2_IRQHandler /* 18 ADC1 and ADC2 */
.long FlashCache_IRQHandler /* 19 FlashCache outage */
.long 0 /* 20 Reserved */
.long CAN1_RX_IRQHandler /* 21 CAN1_RX */
.long 0 /* 22 Reserved */
.long EXTI9_5_IRQHandler /* 23 EXTI Line 9..5 */
.long TIM1_BRK_IRQHandler /* 24 TIM1 Break */
.long TIM1_UP_IRQHandler /* 25 TIM1 Update */
.long TIM1_TRG_COM_IRQHandler /* 26 TIM1 Trigger and Commutation */
.long TIM1_CC_IRQHandler /* 27 TIM1 Capture Compare */
.long TIM2_IRQHandler /* 28 TIM2 */
.long TIM3_IRQHandler /* 29 TIM3 */
.long TIM4_IRQHandler /* 30 TIM4 */
.long I2C1_IRQHandler /* 31 I2C1 Event */
.long 0 /* 32 Reserved */
.long I2C2_IRQHandler /* 33 I2C2 Event */
.long 0 /* 34 Reserved */
.long SPI1_IRQHandler /* 35 SPI1 */
.long SPI2_IRQHandler /* 36 SPI2 */
.long UART1_IRQHandler /* 37 UART1 */
.long UART2_IRQHandler /* 38 UART2 */
.long UART3_IRQHandler /* 39 UART3 */
.long EXTI15_10_IRQHandler /* 40 EXTI Line 15..10 */
.long RTCAlarm_IRQHandler /* 41 RTC Alarm through EXTI Line 17 */
.long OTG_FS_WKUP_IRQHandler /* 42 USB OTG FS Wakeup through EXTI line */
.long TIM8_BRK_IRQHandler /* 43 TIM8 Break */
.long TIM8_UP_IRQHandler /* 44 TIM8 Update */
.long TIM8_TRG_COM_IRQHandler /* 45 TIM8 Trigger and Commutation */
.long TIM8_CC_IRQHandler /* 46 TIM8 Capture Compare */
.long ADC3_IRQHandler /* 47 ADC3 */
.long 0 /* 48 Reserved */
.long SDIO_IRQHandler /* 49 SDIO */
.long TIM5_IRQHandler /* 50 TIM5 */
.long SPI3_IRQHandler /* 51 SPI3 */
.long UART4_IRQHandler /* 52 UART4 */
.long UART5_IRQHandler /* 53 UART5 */
.long TIM6_IRQHandler /* 54 TIM6 */
.long TIM7_IRQHandler /* 55 TIM7 */
.long DMA2_Channel1_IRQHandler /* 56 DMA2 Channel 1 */
.long DMA2_Channel2_IRQHandler /* 57 DMA2 Channel 2 */
.long DMA2_Channel3_IRQHandler /* 58 DMA2 Channel 3 */
.long DMA2_Channel4_IRQHandler /* 59 DMA2 Channel 4 */
.long DMA2_Channel5_IRQHandler /* 60 DMA2 Channel 5 */
.long ETH_IRQHandler /* 61 Ethernet */
.long 0 /* 62 Reserved */
.long 0 /* 63 Reserved */
.long COMP1_2_IRQHandler /* 64 COMP1,COMP2 */
.long 0 /* 65 Reserved */
.long 0 /* 66 Reserved */
.long OTG_FS_IRQHandler /* 67 USB OTG_FullSpeed */
.long 0 /* 68 Reserved */
.long 0 /* 69 Reserved */
.long 0 /* 70 Reserved */
.long UART6_IRQHandler /* 71 UART6 */
.long 0 /* 72 Reserved */
.long 0 /* 73 Reserved */
.long 0 /* 74 Reserved */
.long 0 /* 75 Reserved */
.long 0 /* 76 Reserved */
.long 0 /* 77 Reserved */
.long 0 /* 78 Reserved */
.long 0 /* 79 Reserved */
.long 0 /* 80 Reserved */
.long 0 /* 81 Reserved */
.long UART7_IRQHandler /* 82 UART7 */
.long UART8_IRQHandler /* 83 UART8 */
.long DefaultISR /* 254*/
.size __isr_vector, . - __isr_vector
.text
.thumb
/* Reset Handler */
.thumb_func
.align 2
.globl Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
cpsid i /* Mask interrupts */
.equ VTOR, 0xE000ED08
ldr r0, =VTOR
ldr r1, =__isr_vector
str r1, [r0]
ldr r2, [r1]
msr msp, r2
#ifndef __NO_SYSTEM_INIT
ldr r0,=SystemInit
blx r0
#endif
/* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* __etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* __noncachedata_start__/__noncachedata_end__ : none cachable region
* copied to. Both must be aligned to 4 bytes boundary. */
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
#ifdef __PERFORMANCE_IMPLEMENTATION
/* Here are two copies of loop implementations. First one favors performance
* and the second one favors code size. Default uses the second one.
* Define macro "__PERFORMANCE_IMPLEMENTATION" in project to use the first one */
subs r3, r2
ble .LC1
.LC0:
subs r3, #4
ldr r0, [r1, r3]
str r0, [r2, r3]
bgt .LC0
.LC1:
#else /* code size implemenation */
.LC0:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .LC0
#endif
#ifdef __STARTUP_INITIALIZE_NONCACHEDATA
ldr r2, =__noncachedata_start__
ldr r3, =__noncachedata_init_end__
#ifdef __PERFORMANCE_IMPLEMENTATION
/* Here are two copies of loop implementations. First one favors performance
* and the second one favors code size. Default uses the second one.
* Define macro "__PERFORMANCE_IMPLEMENTATION" in project to use the first one */
subs r3, r2
ble .LC3
.LC2:
subs r3, #4
ldr r0, [r1, r3]
str r0, [r2, r3]
bgt .LC2
.LC3:
#else /* code size implemenation */
.LC2:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .LC2
#endif
/* zero inited ncache section initialization */
ldr r3, =__noncachedata_end__
movs r0,0
.LC4:
cmp r2,r3
itt lt
strlt r0,[r2],#4
blt .LC4
#endif /* __STARTUP_INITIALIZE_NONCACHEDATA */
#ifdef __STARTUP_CLEAR_BSS
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* Loop to zero out BSS section, which uses following symbols
* in linker script:
* __bss_start__: start of BSS section. Must align to 4
* __bss_end__: end of BSS section. Must align to 4
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
.LC5:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt .LC5
#endif /* __STARTUP_CLEAR_BSS */
cpsie i /* Unmask interrupts */
#ifndef __START
#define __START _start
#endif
#ifndef __ATOLLIC__
ldr r0,=__START
blx r0
#else
ldr r0,=__libc_init_array
blx r0
ldr r0,=main
bx r0
#endif
.pool
.size Reset_Handler, . - Reset_Handler
# DefaultISR
.align 1
.thumb_func
.weak DefaultISR
.type DefaultISR, %function
DefaultISR:
b DefaultISR
.size DefaultISR, . - DefaultISR
# NMI_Handler
.align 1
.thumb_func
.weak NMI_Handler
.type NMI_Handler, %function
NMI_Handler:
ldr r0,=NMI_Handler
bx r0
.size NMI_Handler, . - NMI_Handler
# HardFault_Handler
.align 1
.thumb_func
.weak HardFault_Handler
.type HardFault_Handler, %function
HardFault_Handler:
ldr r0,=HardFault_Handler
bx r0
.size HardFault_Handler, . - HardFault_Handler
# MemManage_Handler
# BusFault_Handler
# UsageFault_Handler
# DebugMon_Handler
# SVC_Handler
.align 1
.thumb_func
.weak SVC_Handler
.type SVC_Handler, %function
SVC_Handler:
ldr r0,=SVC_Handler
bx r0
.size SVC_Handler, . - SVC_Handler
# PendSV_Handler
.align 1
.thumb_func
.weak PendSV_Handler
.type PendSV_Handler, %function
PendSV_Handler:
ldr r0,=PendSV_Handler
bx r0
.size PendSV_Handler, . - PendSV_Handler
# SysTick_Handler
.align 1
.thumb_func
.weak SysTick_Handler
.type SysTick_Handler, %function
SysTick_Handler:
ldr r0,=SysTick_Handler
bx r0
.size SysTick_Handler, . - SysTick_Handler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, DefaultISR
.endm
/* Exception Handlers */
def_irq_handler MemManage_Handler
def_irq_handler BusFault_Handler
def_irq_handler UsageFault_Handler
def_irq_handler DebugMon_Handler
def_irq_handler WWDG_IRQHandler /* 0 Window Watchdog */
def_irq_handler PVD_IRQHandler /* 1 PVD through EXTI Line detect */
def_irq_handler TAMPER_IRQHandler /* 2 Tamper */
def_irq_handler RTC_IRQHandler /* 3 RTC */
def_irq_handler FLASH_IRQHandler /* 4 Flash */
def_irq_handler RCC_CRS_IRQHandler /* 5 RCC */
def_irq_handler EXTI0_IRQHandler /* 6 EXTI Line 0 */
def_irq_handler EXTI1_IRQHandler /* 7 EXTI Line 1 */
def_irq_handler EXTI2_IRQHandler /* 8 EXTI Line 2 */
def_irq_handler EXTI3_IRQHandler /* 9 EXTI Line 3 */
def_irq_handler EXTI4_IRQHandler /* 10 EXTI Line 4 */
def_irq_handler DMA1_Channel1_IRQHandler /* 11 DMA1 Channel 1 */
def_irq_handler DMA1_Channel2_IRQHandler /* 12 DMA1 Channel 2 */
def_irq_handler DMA1_Channel3_IRQHandler /* 13 DMA1 Channel 3 */
def_irq_handler DMA1_Channel4_IRQHandler /* 14 DMA1 Channel 4 */
def_irq_handler DMA1_Channel5_IRQHandler /* 15 DMA1 Channel 5 */
def_irq_handler DMA1_Channel6_IRQHandler /* 16 DMA1 Channel 6 */
def_irq_handler DMA1_Channel7_IRQHandler /* 17 DMA1 Channel 7 */
def_irq_handler ADC1_2_IRQHandler /* 18 ADC1 and ADC2 */
def_irq_handler FlashCache_IRQHandler /* 19 FlashCache outage */
def_irq_handler CAN1_RX_IRQHandler /* 21 CAN1_RX */
def_irq_handler EXTI9_5_IRQHandler /* 23 EXTI Line 9..5 */
def_irq_handler TIM1_BRK_IRQHandler /* 24 TIM1 Break */
def_irq_handler TIM1_UP_IRQHandler /* 25 TIM1 Update */
def_irq_handler TIM1_TRG_COM_IRQHandler /* 26 TIM1 Trigger and Commutation */
def_irq_handler TIM1_CC_IRQHandler /* 27 TIM1 Capture Compare */
def_irq_handler TIM2_IRQHandler /* 28 TIM2 */
def_irq_handler TIM3_IRQHandler /* 29 TIM3 */
def_irq_handler TIM4_IRQHandler /* 30 TIM4 */
def_irq_handler I2C1_IRQHandler /* 31 I2C1 Event */
def_irq_handler I2C2_IRQHandler /* 33 I2C2 Event */
def_irq_handler SPI1_IRQHandler /* 35 SPI1 */
def_irq_handler SPI2_IRQHandler /* 36 SPI2 */
def_irq_handler UART1_IRQHandler /* 37 UART1 */
def_irq_handler UART2_IRQHandler /* 38 UART2 */
def_irq_handler UART3_IRQHandler /* 39 UART3 */
def_irq_handler EXTI15_10_IRQHandler /* 40 EXTI Line 15..10 */
def_irq_handler RTCAlarm_IRQHandler /* 41 RTC Alarm through EXTI Line 17 */
def_irq_handler OTG_FS_WKUP_IRQHandler /* 42 USB OTG FS Wakeup through EXTI line */
def_irq_handler TIM8_BRK_IRQHandler /* 43 TIM8 Break */
def_irq_handler TIM8_UP_IRQHandler /* 44 TIM8 Update */
def_irq_handler TIM8_TRG_COM_IRQHandler /* 45 TIM8 Trigger and Commutation */
def_irq_handler TIM8_CC_IRQHandler /* 46 TIM8 Capture Compare */
def_irq_handler ADC3_IRQHandler /* 47 ADC3 */
def_irq_handler SDIO_IRQHandler /* 49 SDIO */
def_irq_handler TIM5_IRQHandler /* 50 TIM5 */
def_irq_handler SPI3_IRQHandler /* 51 SPI3 */
def_irq_handler UART4_IRQHandler /* 52 UART4 */
def_irq_handler UART5_IRQHandler /* 53 UART5 */
def_irq_handler TIM6_IRQHandler /* 54 TIM6 */
def_irq_handler TIM7_IRQHandler /* 55 TIM7 */
def_irq_handler DMA2_Channel1_IRQHandler /* 56 DMA2 Channel 1 */
def_irq_handler DMA2_Channel2_IRQHandler /* 57 DMA2 Channel 2 */
def_irq_handler DMA2_Channel3_IRQHandler /* 58 DMA2 Channel 3 */
def_irq_handler DMA2_Channel4_IRQHandler /* 59 DMA2 Channel 4 */
def_irq_handler DMA2_Channel5_IRQHandler /* 60 DMA2 Channel 5 */
def_irq_handler ETH_IRQHandler /* 61 Ethernet */
def_irq_handler COMP1_2_IRQHandler /* 64 COMP1,COMP2 */
def_irq_handler OTG_FS_IRQHandler /* 67 USB OTG_FullSpeed */
def_irq_handler UART6_IRQHandler /* 71 UART6 */
def_irq_handler UART7_IRQHandler /* 82 UART7 */
def_irq_handler UART8_IRQHandler /* 83 UART8 */
.end

30
bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Device/MM32/MM32F3277/Source/Templates/iar/linker/mm32f3273g.icf Normal file
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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x800;
define symbol __ICFEDIT_size_heap__ = 0x800;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };

306
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/* ------------------------------------------------------------------------- */
/* @file: startup_MM32F3273.s */
/* @purpose: CMSIS Cortex-M0 Core Device Startup File */
/* */
/* @version: 1.0 */
/* @date: 2021-07-21 */
/* @build: b210721 */
/* ------------------------------------------------------------------------- */
/* */
/* Copyright 2021 MindMotion */
/* All rights reserved. */
/* */
/* SPDX-License-Identifier: BSD-3-Clause */
/*****************************************************************************/
/* Version: ICC for ARM Embedded Processors */
/*****************************************************************************/
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
PUBLIC __vector_table_0x1c
PUBLIC __Vectors
PUBLIC __Vectors_End
PUBLIC __Vectors_Size
DATA
__vector_table
DCD sfe(CSTACK) ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
__vector_table_0x1c
DCD 0 ; -9 Reserved
DCD 0 ; -8 Reserved
DCD 0 ; -7 Reserved
DCD 0 ; -6 Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; -3 Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler ; External Interrupts
DCD WWDG_IRQHandler ; 0 Window Watchdog
DCD PVD_IRQHandler ; 1 PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; 2 Tamper
DCD RTC_IRQHandler ; 3 RTC
DCD FLASH_IRQHandler ; 4 Flash
DCD RCC_CRS_IRQHandler ; 5 RCC
DCD EXTI0_IRQHandler ; 6 EXTI Line 0
DCD EXTI1_IRQHandler ; 7 EXTI Line 1
DCD EXTI2_IRQHandler ; 8 EXTI Line 2
DCD EXTI3_IRQHandler ; 9 EXTI Line 3
DCD EXTI4_IRQHandler ; 10 EXTI Line 4
DCD DMA1_CH1_IRQHandler ; 11 DMA1 Channel 1
DCD DMA1_CH2_IRQHandler ; 12 DMA1 Channel 2
DCD DMA1_CH3_IRQHandler ; 13 DMA1 Channel 3
DCD DMA1_CH4_IRQHandler ; 14 DMA1 Channel 4
DCD DMA1_CH5_IRQHandler ; 15 DMA1 Channel 5
DCD DMA1_CH6_IRQHandler ; 16 DMA1 Channel 6
DCD DMA1_CH7_IRQHandler ; 17 DMA1 Channel 7
DCD ADC1_2_IRQHandler ; 18 ADC1 and ADC2
DCD FlashCache_IRQHandler ; 19 FlashCache outage
DCD 0 ; 20 Reserved
DCD CAN1_RX_IRQHandler ; 21 CAN1_RX
DCD 0 ; 22 Reserved
DCD EXTI9_5_IRQHandler ; 23 EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; 24 TIM1 Break
DCD TIM1_UP_IRQHandler ; 25 TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; 26 TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; 27 TIM1 Capture Compare
DCD TIM2_IRQHandler ; 28 TIM2
DCD TIM3_IRQHandler ; 29 TIM3
DCD TIM4_IRQHandler ; 30 TIM4
DCD I2C1_IRQHandler ; 31 I2C1 Event
DCD 0 ; 32 Reserved
DCD I2C2_IRQHandler ; 33 I2C2 Event
DCD 0 ; 34 Reserved
DCD SPI1_IRQHandler ; 35 SPI1
DCD SPI2_IRQHandler ; 36 SPI2
DCD UART1_IRQHandler ; 37 UART1
DCD UART2_IRQHandler ; 38 UART2
DCD UART3_IRQHandler ; 39 UART3
DCD EXTI15_10_IRQHandler ; 40 EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; 41 RTC Alarm through EXTI Line 17
DCD OTG_FS_WKUP_IRQHandler ; 42 USB OTG FS Wakeup through EXTI line
DCD TIM8_BRK_IRQHandler ; 43 TIM8 Break
DCD TIM8_UP_IRQHandler ; 44 TIM8 Update
DCD TIM8_TRG_COM_IRQHandler ; 45 TIM8 Trigger and Commutation
DCD TIM8_CC_IRQHandler ; 46 TIM8 Capture Compare
DCD ADC3_IRQHandler ; 47 ADC3
DCD 0 ; 48 Reserved
DCD SDIO_IRQHandler ; 49 SDIO
DCD TIM5_IRQHandler ; 50 TIM5
DCD SPI3_IRQHandler ; 51 SPI3
DCD UART4_IRQHandler ; 52 UART4
DCD UART5_IRQHandler ; 53 UART5
DCD TIM6_IRQHandler ; 54 TIM6
DCD TIM7_IRQHandler ; 55 TIM7
DCD DMA2_CH1_IRQHandler ; 56 DMA2 Channel 1
DCD DMA2_CH2_IRQHandler ; 57 DMA2 Channel 2
DCD DMA2_CH3_IRQHandler ; 58 DMA2 Channel 3
DCD DMA2_CH4_IRQHandler ; 59 DMA2 Channel 4
DCD DMA2_CH5_IRQHandler ; 60 DMA2 Channel 5
DCD 0 ; 61 Reserved
DCD 0 ; 62 Reserved
DCD 0 ; 63 Reserved
DCD COMP1_2_IRQHandler ; 64 COMP1,COMP2
DCD 0 ; 65 Reserved
DCD 0 ; 66 Reserved
DCD OTG_FS_IRQHandler ; 67 USB OTG_FullSpeed
DCD 0 ; 68 Reserved
DCD 0 ; 69 Reserved
DCD 0 ; 70 Reserved
DCD UART6_IRQHandler ; 71 UART6
DCD 0 ; 72 Reserved
DCD 0 ; 73 Reserved
DCD 0 ; 74 Reserved
DCD 0 ; 75 Reserved
DCD 0 ; 76 Reserved
DCD 0 ; 77 Reserved
DCD 0 ; 78 Reserved
DCD 0 ; 79 Reserved
DCD 0 ; 80 Reserved
DCD 0 ; 81 Reserved
DCD UART7_IRQHandler ; 82 UART7
DCD UART8_IRQHandler ; 83 UART8
__Vectors_End
__Vectors EQU __vector_table
__Vectors_Size EQU __Vectors_End - __Vectors
THUMB
; Reset Handler
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
PUBWEAK HardFault_Handler
PUBWEAK MemManage_Handler
PUBWEAK BusFault_Handler
PUBWEAK UsageFault_Handler
PUBWEAK SVC_Handler
PUBWEAK DebugMon_Handler
PUBWEAK PendSV_Handler
PUBWEAK SysTick_Handler
PUBWEAK WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
PUBWEAK TAMPER_IRQHandler
PUBWEAK RTC_IRQHandler
PUBWEAK FLASH_IRQHandler
PUBWEAK RCC_CRS_IRQHandler
PUBWEAK EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
PUBWEAK DMA1_CH1_IRQHandler
PUBWEAK DMA1_CH2_IRQHandler
PUBWEAK DMA1_CH3_IRQHandler
PUBWEAK DMA1_CH4_IRQHandler
PUBWEAK DMA1_CH5_IRQHandler
PUBWEAK DMA1_CH6_IRQHandler
PUBWEAK DMA1_CH7_IRQHandler
PUBWEAK ADC1_2_IRQHandler
PUBWEAK FlashCache_IRQHandler
PUBWEAK CAN1_RX_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
PUBWEAK I2C1_IRQHandler
PUBWEAK I2C2_IRQHandler
PUBWEAK SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
PUBWEAK UART1_IRQHandler
PUBWEAK UART2_IRQHandler
PUBWEAK UART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
PUBWEAK RTCAlarm_IRQHandler
PUBWEAK OTG_FS_WKUP_IRQHandler
PUBWEAK TIM8_BRK_IRQHandler
PUBWEAK TIM8_UP_IRQHandler
PUBWEAK TIM8_TRG_COM_IRQHandler
PUBWEAK TIM8_CC_IRQHandler
PUBWEAK ADC3_IRQHandler
PUBWEAK SDIO_IRQHandler
PUBWEAK TIM5_IRQHandler
PUBWEAK SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
PUBWEAK UART5_IRQHandler
PUBWEAK TIM6_IRQHandler
PUBWEAK TIM7_IRQHandler
PUBWEAK DMA2_CH1_IRQHandler
PUBWEAK DMA2_CH2_IRQHandler
PUBWEAK DMA2_CH3_IRQHandler
PUBWEAK DMA2_CH4_IRQHandler
PUBWEAK DMA2_CH5_IRQHandler
PUBWEAK COMP1_2_IRQHandler
PUBWEAK OTG_FS_IRQHandler
PUBWEAK UART6_IRQHandler
PUBWEAK UART7_IRQHandler
PUBWEAK UART8_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
HardFault_Handler
MemManage_Handler
BusFault_Handler
UsageFault_Handler
SVC_Handler
DebugMon_Handler
PendSV_Handler
SysTick_Handler
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_CRS_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_CH1_IRQHandler
DMA1_CH2_IRQHandler
DMA1_CH3_IRQHandler
DMA1_CH4_IRQHandler
DMA1_CH5_IRQHandler
DMA1_CH6_IRQHandler
DMA1_CH7_IRQHandler
ADC1_2_IRQHandler
FlashCache_IRQHandler
CAN1_RX_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_IRQHandler
I2C2_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM8_BRK_IRQHandler
TIM8_UP_IRQHandler
TIM8_TRG_COM_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_CH1_IRQHandler
DMA2_CH2_IRQHandler
DMA2_CH3_IRQHandler
DMA2_CH4_IRQHandler
DMA2_CH5_IRQHandler
COMP1_2_IRQHandler
OTG_FS_IRQHandler
UART6_IRQHandler
UART7_IRQHandler
UART8_IRQHandler
Default_Handler
B .
END

16
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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "hal_device_registers.h"
void SystemInit(void)
{
}
/* EOF. */

378
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/* ----------------------------------------------------------------------
* Project: CMSIS DSP Library
* Title: arm_common_tables.h
* Description: Extern declaration for common tables
*
* $Date: 27. January 2017
* $Revision: V.1.5.1
*
* Target Processor: Cortex-M cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _ARM_COMMON_TABLES_H
#define _ARM_COMMON_TABLES_H
#include "arm_math.h"
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREV_1024)
extern const uint16_t armBitRevTable[1024];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_16)
extern const float32_t twiddleCoef_16[32];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_32)
extern const float32_t twiddleCoef_32[64];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_64)
extern const float32_t twiddleCoef_64[128];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_128)
extern const float32_t twiddleCoef_128[256];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_256)
extern const float32_t twiddleCoef_256[512];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_512)
extern const float32_t twiddleCoef_512[1024];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_1024)
extern const float32_t twiddleCoef_1024[2048];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048)
extern const float32_t twiddleCoef_2048[4096];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096)
extern const float32_t twiddleCoef_4096[8192];
#define twiddleCoef twiddleCoef_4096
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_16)
extern const q31_t twiddleCoef_16_q31[24];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_32)
extern const q31_t twiddleCoef_32_q31[48];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_64)
extern const q31_t twiddleCoef_64_q31[96];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_128)
extern const q31_t twiddleCoef_128_q31[192];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_256)
extern const q31_t twiddleCoef_256_q31[384];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_512)
extern const q31_t twiddleCoef_512_q31[768];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_1024)
extern const q31_t twiddleCoef_1024_q31[1536];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_2048)
extern const q31_t twiddleCoef_2048_q31[3072];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096)
extern const q31_t twiddleCoef_4096_q31[6144];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_16)
extern const q15_t twiddleCoef_16_q15[24];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_32)
extern const q15_t twiddleCoef_32_q15[48];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_64)
extern const q15_t twiddleCoef_64_q15[96];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_128)
extern const q15_t twiddleCoef_128_q15[192];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_256)
extern const q15_t twiddleCoef_256_q15[384];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_512)
extern const q15_t twiddleCoef_512_q15[768];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_1024)
extern const q15_t twiddleCoef_1024_q15[1536];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_2048)
extern const q15_t twiddleCoef_2048_q15[3072];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096)
extern const q15_t twiddleCoef_4096_q15[6144];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_32)
extern const float32_t twiddleCoef_rfft_32[32];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_64)
extern const float32_t twiddleCoef_rfft_64[64];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_128)
extern const float32_t twiddleCoef_rfft_128[128];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_256)
extern const float32_t twiddleCoef_rfft_256[256];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_512)
extern const float32_t twiddleCoef_rfft_512[512];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_1024)
extern const float32_t twiddleCoef_rfft_1024[1024];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_2048)
extern const float32_t twiddleCoef_rfft_2048[2048];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_4096)
extern const float32_t twiddleCoef_rfft_4096[4096];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
/* floating-point bit reversal tables */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_16)
#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_32)
#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_64)
#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_128)
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_256)
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_512)
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_1024)
#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_2048)
#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_4096)
#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
/* fixed-point bit reversal tables */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_16)
#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)
extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_32)
#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_64)
#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_128)
#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_256)
#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_512)
#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)
extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_1024)
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_2048)
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_4096)
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_F32)
extern const float32_t realCoefA[8192];
extern const float32_t realCoefB[8192];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q31)
extern const q31_t realCoefAQ31[8192];
extern const q31_t realCoefBQ31[8192];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q15)
extern const q15_t realCoefAQ15[8192];
extern const q15_t realCoefBQ15[8192];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_128)
extern const float32_t Weights_128[256];
extern const float32_t cos_factors_128[128];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_512)
extern const float32_t Weights_512[1024];
extern const float32_t cos_factors_512[512];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_2048)
extern const float32_t Weights_2048[4096];
extern const float32_t cos_factors_2048[2048];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_8192)
extern const float32_t Weights_8192[16384];
extern const float32_t cos_factors_8192[8192];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_128)
extern const q15_t WeightsQ15_128[256];
extern const q15_t cos_factorsQ15_128[128];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_512)
extern const q15_t WeightsQ15_512[1024];
extern const q15_t cos_factorsQ15_512[512];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_2048)
extern const q15_t WeightsQ15_2048[4096];
extern const q15_t cos_factorsQ15_2048[2048];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_8192)
extern const q15_t WeightsQ15_8192[16384];
extern const q15_t cos_factorsQ15_8192[8192];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_128)
extern const q31_t WeightsQ31_128[256];
extern const q31_t cos_factorsQ31_128[128];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_512)
extern const q31_t WeightsQ31_512[1024];
extern const q31_t cos_factorsQ31_512[512];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_2048)
extern const q31_t WeightsQ31_2048[4096];
extern const q31_t cos_factorsQ31_2048[2048];
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_8192)
extern const q31_t WeightsQ31_8192[16384];
extern const q31_t cos_factorsQ31_8192[8192];
#endif
#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_ALLOW_TABLES)
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q15)
extern const q15_t armRecipTableQ15[64];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q31)
extern const q31_t armRecipTableQ31[64];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
/* Tables for Fast Math Sine and Cosine */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_F32)
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q31)
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q15)
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_TABLES) */
#endif /* ARM_COMMON_TABLES_H */

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/* ----------------------------------------------------------------------
* Project: CMSIS DSP Library
* Title: arm_const_structs.h
* Description: Constant structs that are initialized for user convenience.
* For example, some can be given as arguments to the arm_cfft_f32() function.
*
* $Date: 27. January 2017
* $Revision: V.1.5.1
*
* Target Processor: Cortex-M cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _ARM_CONST_STRUCTS_H
#define _ARM_CONST_STRUCTS_H
#include "arm_math.h"
#include "arm_common_tables.h"
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
#endif

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/**************************************************************************//**
* @file cmsis_armcc.h
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
* @version V5.1.0
* @date 08. May 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_ARMCC_H
#define __CMSIS_ARMCC_H
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
#endif
/* CMSIS compiler control architecture macros */
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
#define __ARM_ARCH_6M__ 1
#endif
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
#define __ARM_ARCH_7M__ 1
#endif
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
#define __ARM_ARCH_7EM__ 1
#endif
/* __ARM_ARCH_8M_BASE__ not applicable */
/* __ARM_ARCH_8M_MAIN__ not applicable */
/* CMSIS compiler control DSP macros */
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __ARM_FEATURE_DSP 1
#endif
/* CMSIS compiler specific defines */
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE __inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static __inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE static __forceinline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __declspec(noreturn)
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT __packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION __packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __COMPILER_BARRIER
#define __COMPILER_BARRIER() __memory_changed()
#endif
/* ######################### Startup and Lowlevel Init ######################## */
#ifndef __PROGRAM_START
#define __PROGRAM_START __main
#endif
#ifndef __INITIAL_SP
#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
#endif
#ifndef __STACK_LIMIT
#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
#endif
#ifndef __VECTOR_TABLE
#define __VECTOR_TABLE __Vectors
#endif
#ifndef __VECTOR_TABLE_ATTRIBUTE
#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET")))
#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/**
\brief Enable IRQ Interrupts
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __enable_irq(); */
/**
\brief Disable IRQ Interrupts
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __disable_irq(); */
/**
\brief Get Control Register
\details Returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/**
\brief Set Control Register
\details Writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/**
\brief Get IPSR Register
\details Returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/**
\brief Get APSR Register
\details Returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/**
\brief Get xPSR Register
\details Returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/**
\brief Get Process Stack Pointer
\details Returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/**
\brief Set Process Stack Pointer
\details Assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/**
\brief Get Main Stack Pointer
\details Returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/**
\brief Set Main Stack Pointer
\details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/**
\brief Get Priority Mask
\details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/**
\brief Set Priority Mask
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief Enable FIQ
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/**
\brief Disable FIQ
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/**
\brief Get Base Priority
\details Returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/**
\brief Set Base Priority
\details Assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xFFU);
}
/**
\brief Set Base Priority with condition
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
{
register uint32_t __regBasePriMax __ASM("basepri_max");
__regBasePriMax = (basePri & 0xFFU);
}
/**
\brief Get Fault Mask
\details Returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/**
\brief Set Fault Mask
\details Assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1U);
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0U);
#endif
}
/**
\brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#else
(void)fpscr;
#endif
}
/*@} end of CMSIS_Core_RegAccFunctions */
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
#define __WFI __wfi
/**
\brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/**
\brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
#define __ISB() do {\
__schedule_barrier();\
__isb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() do {\
__schedule_barrier();\
__dsb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() do {\
__schedule_barrier();\
__dmb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#endif
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] op1 Value to rotate
\param [in] op2 Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/**
\brief Breakpoint
\details Causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __RBIT __rbit
#else
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value != 0U; value >>= 1U)
{
result <<= 1U;
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
return result;
}
#endif
/**
\brief Count leading zeros
\details Counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief LDR Exclusive (8 bit)
\details Executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
#else
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
#else
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
#else
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXB(value, ptr) __strex(value, ptr)
#else
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXH(value, ptr) __strex(value, ptr)
#else
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXW(value, ptr) __strex(value, ptr)
#else
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/**
\brief Rotate Right with Extend (32 bit)
\details Moves each bit of a bitstring right by one bit.
The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
{
rrx r0, r0
bx lr
}
#endif
/**
\brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
/**
\brief LDRT Unprivileged (16 bit)
\details Executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
/**
\brief LDRT Unprivileged (32 bit)
\details Executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
/**
\brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRBT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRHT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRT(value, ptr) __strt(value, ptr)
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32U) ) >> 32U))
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CMSIS_ARMCC_H */

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/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.1.0
* @date 09. October 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* Arm Compiler 6.6 LTM (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
#include "cmsis_armclang_ltm.h"
/*
* Arm Compiler above 6.10.1 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h>
/*
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */

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/**************************************************************************//**
* @file cmsis_iccarm.h
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
* @version V5.1.0
* @date 08. May 2019
******************************************************************************/
//------------------------------------------------------------------------------
//
// Copyright (c) 2017-2019 IAR Systems
// Copyright (c) 2017-2019 Arm Limited. All rights reserved.
//
// Licensed under the Apache License, Version 2.0 (the "License")
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
//------------------------------------------------------------------------------
#ifndef __CMSIS_ICCARM_H__
#define __CMSIS_ICCARM_H__
#ifndef __ICCARM__
#error This file should only be compiled by ICCARM
#endif
#pragma system_include
#define __IAR_FT _Pragma("inline=forced") __intrinsic
#if (__VER__ >= 8000000)
#define __ICCARM_V8 1
#else
#define __ICCARM_V8 0
#endif
#ifndef __ALIGNED
#if __ICCARM_V8
#define __ALIGNED(x) __attribute__((aligned(x)))
#elif (__VER__ >= 7080000)
/* Needs IAR language extensions */
#define __ALIGNED(x) __attribute__((aligned(x)))
#else
#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#endif
/* Define compiler macros for CPU architecture, used in CMSIS 5.
*/
#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
/* Macros already defined */
#else
#if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
#if __ARM_ARCH == 6
#define __ARM_ARCH_6M__ 1
#elif __ARM_ARCH == 7
#if __ARM_FEATURE_DSP
#define __ARM_ARCH_7EM__ 1
#else
#define __ARM_ARCH_7M__ 1
#endif
#endif /* __ARM_ARCH */
#endif /* __ARM_ARCH_PROFILE == 'M' */
#endif
/* Alternativ core deduction for older ICCARM's */
#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
!defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
#if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
#define __ARM_ARCH_6M__ 1
#elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
#define __ARM_ARCH_7M__ 1
#elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
#define __ARM_ARCH_7EM__ 1
#elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#else
#error "Unknown target."
#endif
#endif
#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
#define __IAR_M0_FAMILY 1
#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
#define __IAR_M0_FAMILY 1
#else
#define __IAR_M0_FAMILY 0
#endif
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __COMPILER_BARRIER
#define __COMPILER_BARRIER() __ASM volatile("":::"memory")
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __NO_RETURN
#if __ICCARM_V8
#define __NO_RETURN __attribute__((__noreturn__))
#else
#define __NO_RETURN _Pragma("object_attribute=__noreturn")
#endif
#endif
#ifndef __PACKED
#if __ICCARM_V8
#define __PACKED __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED __packed
#endif
#endif
#ifndef __PACKED_STRUCT
#if __ICCARM_V8
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_STRUCT __packed struct
#endif
#endif
#ifndef __PACKED_UNION
#if __ICCARM_V8
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_UNION __packed union
#endif
#endif
#ifndef __RESTRICT
#if __ICCARM_V8
#define __RESTRICT __restrict
#else
/* Needs IAR language extensions */
#define __RESTRICT restrict
#endif
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __FORCEINLINE
#define __FORCEINLINE _Pragma("inline=forced")
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
#endif
#ifndef __UNALIGNED_UINT16_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
{
return *(__packed uint16_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
{
*(__packed uint16_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
{
return *(__packed uint32_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
{
*(__packed uint32_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#pragma language=save
#pragma language=extended
__packed struct __iar_u32 { uint32_t v; };
#pragma language=restore
#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
#endif
#ifndef __USED
#if __ICCARM_V8
#define __USED __attribute__((used))
#else
#define __USED _Pragma("__root")
#endif
#endif
#ifndef __WEAK
#if __ICCARM_V8
#define __WEAK __attribute__((weak))
#else
#define __WEAK _Pragma("__weak")
#endif
#endif
#ifndef __PROGRAM_START
#define __PROGRAM_START __iar_program_start
#endif
#ifndef __INITIAL_SP
#define __INITIAL_SP CSTACK$$Limit
#endif
#ifndef __STACK_LIMIT
#define __STACK_LIMIT CSTACK$$Base
#endif
#ifndef __VECTOR_TABLE
#define __VECTOR_TABLE __vector_table
#endif
#ifndef __VECTOR_TABLE_ATTRIBUTE
#define __VECTOR_TABLE_ATTRIBUTE @".intvec"
#endif
#ifndef __ICCARM_INTRINSICS_VERSION__
#define __ICCARM_INTRINSICS_VERSION__ 0
#endif
#if __ICCARM_INTRINSICS_VERSION__ == 2
#if defined(__CLZ)
#undef __CLZ
#endif
#if defined(__REVSH)
#undef __REVSH
#endif
#if defined(__RBIT)
#undef __RBIT
#endif
#if defined(__SSAT)
#undef __SSAT
#endif
#if defined(__USAT)
#undef __USAT
#endif
#include "iccarm_builtin.h"
#define __disable_fault_irq __iar_builtin_disable_fiq
#define __disable_irq __iar_builtin_disable_interrupt
#define __enable_fault_irq __iar_builtin_enable_fiq
#define __enable_irq __iar_builtin_enable_interrupt
#define __arm_rsr __iar_builtin_rsr
#define __arm_wsr __iar_builtin_wsr
#define __get_APSR() (__arm_rsr("APSR"))
#define __get_BASEPRI() (__arm_rsr("BASEPRI"))
#define __get_CONTROL() (__arm_rsr("CONTROL"))
#define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
#define __get_FPSCR() (__arm_rsr("FPSCR"))
#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
#else
#define __get_FPSCR() ( 0 )
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#define __get_IPSR() (__arm_rsr("IPSR"))
#define __get_MSP() (__arm_rsr("MSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __get_MSPLIM() (0U)
#else
#define __get_MSPLIM() (__arm_rsr("MSPLIM"))
#endif
#define __get_PRIMASK() (__arm_rsr("PRIMASK"))
#define __get_PSP() (__arm_rsr("PSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __get_PSPLIM() (0U)
#else
#define __get_PSPLIM() (__arm_rsr("PSPLIM"))
#endif
#define __get_xPSR() (__arm_rsr("xPSR"))
#define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
#define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
#define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __set_MSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
#endif
#define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
#define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __set_PSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
#endif
#define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
#define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
#define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
#define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
#define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
#define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
#define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
#define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
#define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
#define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
#define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
#define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
#define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __TZ_get_PSPLIM_NS() (0U)
#define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
#else
#define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
#define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
#endif
#define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
#define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
#define __NOP __iar_builtin_no_operation
#define __CLZ __iar_builtin_CLZ
#define __CLREX __iar_builtin_CLREX
#define __DMB __iar_builtin_DMB
#define __DSB __iar_builtin_DSB
#define __ISB __iar_builtin_ISB
#define __LDREXB __iar_builtin_LDREXB
#define __LDREXH __iar_builtin_LDREXH
#define __LDREXW __iar_builtin_LDREX
#define __RBIT __iar_builtin_RBIT
#define __REV __iar_builtin_REV
#define __REV16 __iar_builtin_REV16
__IAR_FT int16_t __REVSH(int16_t val)
{
return (int16_t) __iar_builtin_REVSH(val);
}
#define __ROR __iar_builtin_ROR
#define __RRX __iar_builtin_RRX
#define __SEV __iar_builtin_SEV
#if !__IAR_M0_FAMILY
#define __SSAT __iar_builtin_SSAT
#endif
#define __STREXB __iar_builtin_STREXB
#define __STREXH __iar_builtin_STREXH
#define __STREXW __iar_builtin_STREX
#if !__IAR_M0_FAMILY
#define __USAT __iar_builtin_USAT
#endif
#define __WFE __iar_builtin_WFE
#define __WFI __iar_builtin_WFI
#if __ARM_MEDIA__
#define __SADD8 __iar_builtin_SADD8
#define __QADD8 __iar_builtin_QADD8
#define __SHADD8 __iar_builtin_SHADD8
#define __UADD8 __iar_builtin_UADD8
#define __UQADD8 __iar_builtin_UQADD8
#define __UHADD8 __iar_builtin_UHADD8
#define __SSUB8 __iar_builtin_SSUB8
#define __QSUB8 __iar_builtin_QSUB8
#define __SHSUB8 __iar_builtin_SHSUB8
#define __USUB8 __iar_builtin_USUB8
#define __UQSUB8 __iar_builtin_UQSUB8
#define __UHSUB8 __iar_builtin_UHSUB8
#define __SADD16 __iar_builtin_SADD16
#define __QADD16 __iar_builtin_QADD16
#define __SHADD16 __iar_builtin_SHADD16
#define __UADD16 __iar_builtin_UADD16
#define __UQADD16 __iar_builtin_UQADD16
#define __UHADD16 __iar_builtin_UHADD16
#define __SSUB16 __iar_builtin_SSUB16
#define __QSUB16 __iar_builtin_QSUB16
#define __SHSUB16 __iar_builtin_SHSUB16
#define __USUB16 __iar_builtin_USUB16
#define __UQSUB16 __iar_builtin_UQSUB16
#define __UHSUB16 __iar_builtin_UHSUB16
#define __SASX __iar_builtin_SASX
#define __QASX __iar_builtin_QASX
#define __SHASX __iar_builtin_SHASX
#define __UASX __iar_builtin_UASX
#define __UQASX __iar_builtin_UQASX
#define __UHASX __iar_builtin_UHASX
#define __SSAX __iar_builtin_SSAX
#define __QSAX __iar_builtin_QSAX
#define __SHSAX __iar_builtin_SHSAX
#define __USAX __iar_builtin_USAX
#define __UQSAX __iar_builtin_UQSAX
#define __UHSAX __iar_builtin_UHSAX
#define __USAD8 __iar_builtin_USAD8
#define __USADA8 __iar_builtin_USADA8
#define __SSAT16 __iar_builtin_SSAT16
#define __USAT16 __iar_builtin_USAT16
#define __UXTB16 __iar_builtin_UXTB16
#define __UXTAB16 __iar_builtin_UXTAB16
#define __SXTB16 __iar_builtin_SXTB16
#define __SXTAB16 __iar_builtin_SXTAB16
#define __SMUAD __iar_builtin_SMUAD
#define __SMUADX __iar_builtin_SMUADX
#define __SMMLA __iar_builtin_SMMLA
#define __SMLAD __iar_builtin_SMLAD
#define __SMLADX __iar_builtin_SMLADX
#define __SMLALD __iar_builtin_SMLALD
#define __SMLALDX __iar_builtin_SMLALDX
#define __SMUSD __iar_builtin_SMUSD
#define __SMUSDX __iar_builtin_SMUSDX
#define __SMLSD __iar_builtin_SMLSD
#define __SMLSDX __iar_builtin_SMLSDX
#define __SMLSLD __iar_builtin_SMLSLD
#define __SMLSLDX __iar_builtin_SMLSLDX
#define __SEL __iar_builtin_SEL
#define __QADD __iar_builtin_QADD
#define __QSUB __iar_builtin_QSUB
#define __PKHBT __iar_builtin_PKHBT
#define __PKHTB __iar_builtin_PKHTB
#endif
#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#define __CLZ __cmsis_iar_clz_not_active
#define __SSAT __cmsis_iar_ssat_not_active
#define __USAT __cmsis_iar_usat_not_active
#define __RBIT __cmsis_iar_rbit_not_active
#define __get_APSR __cmsis_iar_get_APSR_not_active
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
#define __set_FPSCR __cmsis_iar_set_FPSR_not_active
#endif
#ifdef __INTRINSICS_INCLUDED
#error intrinsics.h is already included previously!
#endif
#include <intrinsics.h>
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#undef __CLZ
#undef __SSAT
#undef __USAT
#undef __RBIT
#undef __get_APSR
__STATIC_INLINE uint8_t __CLZ(uint32_t data)
{
if (data == 0U) { return 32U; }
uint32_t count = 0U;
uint32_t mask = 0x80000000U;
while ((data & mask) == 0U)
{
count += 1U;
mask = mask >> 1U;
}
return count;
}
__STATIC_INLINE uint32_t __RBIT(uint32_t v)
{
uint8_t sc = 31U;
uint32_t r = v;
for (v >>= 1U; v; v >>= 1U)
{
r <<= 1U;
r |= v & 1U;
sc--;
}
return (r << sc);
}
__STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t res;
__asm("MRS %0,APSR" : "=r" (res));
return res;
}
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#undef __get_FPSCR
#undef __set_FPSCR
#define __get_FPSCR() (0)
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#pragma diag_suppress=Pe940
#pragma diag_suppress=Pe177
#define __enable_irq __enable_interrupt
#define __disable_irq __disable_interrupt
#define __NOP __no_operation
#define __get_xPSR __get_PSR
#if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
{
return __LDREX((unsigned long *)ptr);
}
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
{
return __STREX(value, (unsigned long *)ptr);
}
#endif
/* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
#if (__CORTEX_M >= 0x03)
__IAR_FT uint32_t __RRX(uint32_t value)
{
uint32_t result;
__ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
return(result);
}
__IAR_FT void __set_BASEPRI_MAX(uint32_t value)
{
__asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
}
#define __enable_fault_irq __enable_fiq
#define __disable_fault_irq __disable_fiq
#endif /* (__CORTEX_M >= 0x03) */
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
}
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint32_t __get_MSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,MSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_MSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR MSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __get_PSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_PSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
{
__asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PSP_NS(uint32_t value)
{
__asm volatile("MSR PSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_MSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSP_NS(uint32_t value)
{
__asm volatile("MSR MSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_SP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,SP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_SP_NS(uint32_t value)
{
__asm volatile("MSR SP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
{
__asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
{
__asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
{
__asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
#endif
return res;
}
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
{
__asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
#if __IAR_M0_FAMILY
__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif
#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
{
uint32_t res;
__ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
{
uint32_t res;
__ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
{
uint32_t res;
__ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return res;
}
__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
{
__ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
{
__ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
{
__ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
{
__ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
{
__ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
{
__ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#undef __IAR_FT
#undef __IAR_M0_FAMILY
#undef __ICCARM_V8
#pragma diag_default=Pe940
#pragma diag_default=Pe177
#endif /* __CMSIS_ICCARM_H__ */

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/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.3
* @date 24. June 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif

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/**************************************************************************//**
* @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version V5.0.6
* @date 13. March 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM0_H_GENERIC
#define __CORE_CM0_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M0
@{
*/
#include "cmsis_version.h"
/* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
__CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (0U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_FP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0_H_DEPENDANT
#define __CORE_CM0_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0_REV
#define __CM0_REV 0x0000U
#warning "__CM0_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M0 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RESERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__COMPILER_BARRIER();
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__COMPILER_BARRIER();
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
Address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t vectors = 0x0U;
(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
/* ARM Application Note 321 states that the M0 does not require the architectural barrier */
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t vectors = 0x0U;
return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

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/**************************************************************************//**
* @file core_cm1.h
* @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File
* @version V1.0.1
* @date 12. November 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM1_H_GENERIC
#define __CORE_CM1_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M1
@{
*/
#include "cmsis_version.h"
/* CMSIS CM1 definitions */
#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
__CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (1U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_FP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM1_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM1_H_DEPENDANT
#define __CORE_CM1_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM1_REV
#define __CM1_REV 0x0100U
#warning "__CM1_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M1 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
\brief Type definitions for the System Control and ID Register not in the SCB
@{
*/
/**
\brief Structure type to access the System Control and ID Register not in the SCB.
*/
typedef struct
{
uint32_t RESERVED0[2U];
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
} SCnSCB_Type;
/* Auxiliary Control Register Definitions */
#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
/*@} end of group CMSIS_SCnotSCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M1 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__COMPILER_BARRIER();
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__COMPILER_BARRIER();
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
Address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)0x0U;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
/* ARM Application Note 321 states that the M1 does not require the architectural barrier */
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)0x0U;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM1_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

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/**************************************************************************//**
* @file cmsis_xcc.h
* @brief CMSIS DSP Core Peripheral Access Layer Header File
* @version V1.0
* @date 20. January 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CORE_DSP_H_GENERIC
#define __CORE_DSP_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
#define __STATIC_INLINE static inline
#define __BKPT(value) do {} while(0)
#define __NOP() do {} while(0)
#define NVIC_SetPriorityGrouping(value) do {} while(0)
#define NVIC_GetPriorityGrouping() do {} while(0)
#define NVIC_EnableIRQ(value) do {} while(0)
#define NVIC_GetEnableIRQ(value) do {} while(0)
#define NVIC_DisableIRQ(value) do {} while(0)
#define NVIC_GetPendingIRQ(value) do {} while(0)
#define NVIC_SetPendingIRQ(value) do {} while(0)
#define NVIC_ClearPendingIRQ(value) do {} while(0)
#define NVIC_GetActive(value) do {} while(0)
#ifdef __cplusplus
}
#endif
#endif /* __CORE_DSP_H_GENERIC */

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/******************************************************************************
* @file mpu_armv7.h
* @brief CMSIS MPU API for Armv7-M MPU
* @version V5.1.0
* @date 08. March 2019
******************************************************************************/
/*
* Copyright (c) 2017-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV7_H
#define ARM_MPU_ARMV7_H
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
/** MPU Region Base Address Register Value
*
* \param Region The region to be configured, number 0 to 15.
* \param BaseAddress The base address for the region.
*/
#define ARM_MPU_RBAR(Region, BaseAddress) \
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
((Region) & MPU_RBAR_REGION_Msk) | \
(MPU_RBAR_VALID_Msk))
/**
* MPU Memory Access Attributes
*
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
*/
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
(((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
(((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
(((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
(((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
(((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
(((MPU_RASR_ENABLE_Msk))))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
/**
* MPU Memory Access Attribute for strongly ordered memory.
* - TEX: 000b
* - Shareable
* - Non-cacheable
* - Non-bufferable
*/
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
/**
* MPU Memory Access Attribute for device memory.
* - TEX: 000b (if shareable) or 010b (if non-shareable)
* - Shareable or non-shareable
* - Non-cacheable
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
*
* \param IsShareable Configures the device memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
/**
* MPU Memory Access Attribute for normal memory.
* - TEX: 1BBb (reflecting outer cacheability rules)
* - Shareable or non-shareable
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
*
* \param OuterCp Configures the outer cache policy.
* \param InnerCp Configures the inner cache policy.
* \param IsShareable Configures the memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
/**
* MPU Memory Access Attribute non-cacheable policy.
*/
#define ARM_MPU_CACHEP_NOCACHE 0U
/**
* MPU Memory Access Attribute write-back, write and read allocate policy.
*/
#define ARM_MPU_CACHEP_WB_WRA 1U
/**
* MPU Memory Access Attribute write-through, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WT_NWA 2U
/**
* MPU Memory Access Attribute write-back, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WB_NWA 3U
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; //!< The region base address register value (RBAR)
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
MPU->RNR = rnr;
MPU->RASR = 0U;
}
/** Configure an MPU region.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
{
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
{
MPU->RNR = rnr;
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
while (cnt > MPU_TYPE_RALIASES) {
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
table += MPU_TYPE_RALIASES;
cnt -= MPU_TYPE_RALIASES;
}
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
}
#endif

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/******************************************************************************
* @file mpu_armv8.h
* @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
* @version V5.1.0
* @date 08. March 2019
******************************************************************************/
/*
* Copyright (c) 2017-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV8_H
#define ARM_MPU_ARMV8_H
/** \brief Attribute for device memory (outer only) */
#define ARM_MPU_ATTR_DEVICE ( 0U )
/** \brief Attribute for non-cacheable, normal memory */
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
/** \brief Attribute for normal memory (outer and inner)
* \param NT Non-Transient: Set to 1 for non-transient data.
* \param WB Write-Back: Set to 1 to use write-back update policy.
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
*/
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
(((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
/** \brief Memory Attribute
* \param O Outer memory attributes
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
*/
#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
/** \brief Normal memory non-shareable */
#define ARM_MPU_SH_NON (0U)
/** \brief Normal memory outer shareable */
#define ARM_MPU_SH_OUTER (2U)
/** \brief Normal memory inner shareable */
#define ARM_MPU_SH_INNER (3U)
/** \brief Memory access permissions
* \param RO Read-Only: Set to 1 for read-only memory.
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
*/
#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
/** \brief Region Base Address Register value
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
* \param SH Defines the Shareability domain for this memory region.
* \param RO Read-Only: Set to 1 for a read-only memory region.
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
*/
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
((BASE & MPU_RBAR_BASE_Msk) | \
((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
/** \brief Region Limit Address Register value
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
* \param IDX The attribute index to be associated with this memory region.
*/
#define ARM_MPU_RLAR(LIMIT, IDX) \
((LIMIT & MPU_RLAR_LIMIT_Msk) | \
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
(MPU_RLAR_EN_Msk))
#if defined(MPU_RLAR_PXN_Pos)
/** \brief Region Limit Address Register with PXN value
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
* \param IDX The attribute index to be associated with this memory region.
*/
#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
((LIMIT & MPU_RLAR_LIMIT_Msk) | \
((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
(MPU_RLAR_EN_Msk))
#endif
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; /*!< Region Base Address Register value */
uint32_t RLAR; /*!< Region Limit Address Register value */
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
#ifdef MPU_NS
/** Enable the Non-secure MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
{
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the Non-secure MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
#endif
/** Set the memory attribute encoding to the given MPU.
* \param mpu Pointer to the MPU to be configured.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
{
const uint8_t reg = idx / 4U;
const uint32_t pos = ((idx % 4U) * 8U);
const uint32_t mask = 0xFFU << pos;
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
return; // invalid index
}
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
}
/** Set the memory attribute encoding.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
}
#ifdef MPU_NS
/** Set the memory attribute encoding to the Non-secure MPU.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
}
#endif
/** Clear and disable the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
{
mpu->RNR = rnr;
mpu->RLAR = 0U;
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU, rnr);
}
#ifdef MPU_NS
/** Clear and disable the given Non-secure MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
}
#endif
/** Configure the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
mpu->RNR = rnr;
mpu->RBAR = rbar;
mpu->RLAR = rlar;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
}
#ifdef MPU_NS
/** Configure the given Non-secure MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
}
#endif
/** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table to the given MPU.
* \param mpu Pointer to the MPU registers to be used.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
if (cnt == 1U) {
mpu->RNR = rnr;
ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
} else {
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
table += c;
cnt -= c;
rnrOffset = 0U;
rnrBase += MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
}
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
}
}
/** Load the given number of MPU regions from a table.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
}
#ifdef MPU_NS
/** Load the given number of MPU regions from a table to the Non-secure MPU.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
}
#endif
#endif

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/******************************************************************************
* @file tz_context.h
* @brief Context Management for Armv8-M TrustZone
* @version V1.0.1
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef TZ_CONTEXT_H
#define TZ_CONTEXT_H
#include <stdint.h>
#ifndef TZ_MODULEID_T
#define TZ_MODULEID_T
/// \details Data type that identifies secure software modules called by a process.
typedef uint32_t TZ_ModuleId_t;
#endif
/// \details TZ Memory ID identifies an allocated memory slot.
typedef uint32_t TZ_MemoryId_t;
/// Initialize secure context memory system
/// \return execution status (1: success, 0: error)
uint32_t TZ_InitContextSystem_S (void);
/// Allocate context memory for calling secure software modules in TrustZone
/// \param[in] module identifies software modules called from non-secure mode
/// \return value != 0 id TrustZone memory slot identifier
/// \return value 0 no memory available or internal error
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
/// Load secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
/// Store secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
#endif // TZ_CONTEXT_H

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_ADC_H__
#define __HAL_ADC_H__
#include "hal_common.h"
/*!
* @addtogroup ADC
* @{
*/
/*!
* @brief ADC driver version number.
*/
#define ADC_DRIVER_VERSION 0u /*!< adc_0. */
/*!
* @addtogroup ADC_STATUS
* Define ADC status.
* @{
*/
#define ADC_STATUS_CONV_SLOT_DONE (1u << 0u) /*!< Status flag when ADC slot conversion done. */
#define ADC_STATUS_CONV_SAMPLE_DONE (1u << 1u) /*!< Status flag when ADC sample done. */
#define ADC_STATUS_CONV_SEQ_DONE (1u << 2u) /*!< Status flag when ADC sequence conversion done. */
#define ADC_STATUS_COMPARE_DONE (1u << 3u) /*!< Status flag when ADC compare done. */
/*!
* @}
*/
/*!
* @addtogroup ADC_INT
* ADC interrupt define.
* @{
*/
#define ADC_INT_CONV_SLOT_DONE (1u << 0u) /*!< Interrupt enable when when ADC slot conversion done. */
#define ADC_INT_CONV_SAMPLE_DONE (1u << 1u) /*!< Interrupt enable when when ADC sample done. */
#define ADC_INT_CONV_SEQ_DONE (1u << 2u) /*!< Interrupt enable when when ADC sequence conversion done. */
#define ADC_INT_COMPARE_DONE (1u << 3u) /*!< Interrupt enable when when ADC compare done. */
/*!
* @}
*/
/*!
* @addtogroup ADC_RESULT_FLAGS
* Define ADC Convert result flags.
* @{
*/
#define ADC_CONV_RESULT_FLAG_OVERRUN (1u << 0u) /*!< Result flag when adc conversion result is overrun. */
#define ADC_CONV_RESULT_FLAG_VALID (1u << 1u) /*!< Result flag when adc conversion result valid. */
/*!
* @}
*/
/*!
* @brief ADC Resolution type.
*
* Select ADC conversion valid data bit.
*/
typedef enum
{
ADC_Resolution_12b = 0u, /*!< Resolution select 12 bit. */
ADC_Resolution_11b = 1u, /*!< Resolution select 11 bit. */
ADC_Resolution_10b = 2u, /*!< Resolution select 10 bit. */
ADC_Resolution_9b = 3u, /*!< Resolution select 9 bit. */
ADC_Resolution_8b = 4u, /*!< Resolution select 8 bit. */
} ADC_Resolution_Type;
/*!
* @brief ADC Prescaler type.
*
* Select the prescaler of the bus as the adc clock.
*/
typedef enum
{
ADC_ClockDiv_2 = 0u, /*!< ADC clock divided by 2. */
ADC_ClockDiv_3 = 1u, /*!< ADC clock divided by 3. */
ADC_ClockDiv_4 = 2u, /*!< ADC clock divided by 4. */
ADC_ClockDiv_5 = 3u, /*!< ADC clock divided by 5. */
ADC_ClockDiv_6 = 4u, /*!< ADC clock divided by 6. */
ADC_ClockDiv_7 = 5u, /*!< ADC clock divided by 7. */
ADC_ClockDiv_8 = 6u, /*!< ADC clock divided by 8. */
ADC_ClockDiv_9 = 7u, /*!< ADC clock divided by 9. */
ADC_ClockDiv_10 = 8u, /*!< ADC clock divided by 10. */
ADC_ClockDiv_11 = 9u, /*!< ADC clock divided by 11. */
ADC_ClockDiv_12 = 10u, /*!< ADC clock divided by 12. */
ADC_ClockDiv_13 = 11u, /*!< ADC clock divided by 13. */
ADC_ClockDiv_14 = 12u, /*!< ADC clock divided by 14. */
ADC_ClockDiv_15 = 13u, /*!< ADC clock divided by 15. */
ADC_ClockDiv_16 = 14u, /*!< ADC clock divided by 16. */
ADC_ClockDiv_17 = 15u, /*!< ADC clock divided by 17. */
} ADC_ClockDiv_Type;
/*!
* @brief ADC HwTrgEdge type.
*
* Use hardware trigger in ADC, select the trigger edge to trigger adc.
*/
typedef enum
{
ADC_HwTrgEdge_Both = 0u, /*!< Both edge trigger. */
ADC_HwTrgEdge_Falling = 1u, /*!< Falling edge trigger. */
ADC_HwTrgEdge_Rising = 2u, /*!< Rising edge trigger. */
ADC_HwTrgEdge_Disabled = 3u, /*!< Edge trigger is disabled. */
} ADC_HwTrgEdge_Type;
/*!
* @brief ADC HwTrgDelayCycle type.
*
* After the hardware trigger signal is generated, delay N PCLK2 clock cycles before starting the first sample.
*/
typedef enum
{
ADC_HwTrgDelayCycle_0 = 0u, /*!< Delay 0 cycle. */
ADC_HwTrgDelayCycle_4 = 1u, /*!< Delay 4 cycle. */
ADC_HwTrgDelayCycle_16 = 2u, /*!< Delay 16 cycle. */
ADC_HwTrgDelayCycle_32 = 3u, /*!< Delay 32 cycle. */
ADC_HwTrgDelayCycle_64 = 4u, /*!< Delay 64 cycle. */
ADC_HwTrgDelayCycle_128 = 5u, /*!< Delay 128 cycle. */
ADC_HwTrgDelayCycle_256 = 6u, /*!< Delay 256 cycle. */
ADC_HwTrgDelayCycle_512 = 7u, /*!< Delay 512 cycle. */
} ADC_HwTrgDelayCycle_Type;
/*!
* @brief ADC Align type.
*
* Choose to store the converted data as left-aligned or right-aligned.
*/
typedef enum
{
ADC_Align_Right = 0u, /*!< Data right align. */
ADC_Align_Left = 1u, /*!< Data left align. */
} ADC_Align_Type;
/*!
* @brief ADC RegularSeqDirection type.
*
* In single-cycle scan or continuous scan mode, set the order of scan channels.
*/
typedef enum
{
ADC_RegSeqDirection_LowFirst = 0u, /*!< ADC scan direction from low channel to high channel. */
ADC_RegSeqDirection_HighFirst = 1u, /*!< ADC scan direction from high channel to low channel. */
} ADC_RegSeqDirection_Type;
/*!
* @brief ADC ConvMode type.
*
* Select the adc channel or sequence convert mode.
*/
typedef enum
{
ADC_ConvMode_SingleSlot = 0u, /*!< Run the conversion by channel. */
ADC_ConvMode_Seq = 1u, /*!< Run the conversion by sequence. */
ADC_ConvMode_SeqContinues = 2u, /*!< Run the conversion by sequence again and again. */
} ADC_ConvMode_Type;
/*!
* @brief ADC HwTrgSel type.
*
* Select ADC hardware trigger source.
*/
typedef enum
{
ADC_HwTrgSource_Alt0 = 0u, /*!< source 0 as an external trigger source for ADC . */
ADC_HwTrgSource_Alt1 = 1u, /*!< source 1 as an external trigger source for ADC . */
ADC_HwTrgSource_Alt2 = 2u, /*!< source 2 as an external trigger source for ADC . */
ADC_HwTrgSource_Alt3 = 3u, /*!< source 3 as an external trigger source for ADC . */
ADC_HwTrgSource_Alt4 = 4u, /*!< source 4 as an external trigger source for ADC . */
ADC_HwTrgSource_Alt5 = 5u, /*!< source 5 as an external trigger source for ADC . */
ADC_HwTrgSource_Alt6 = 6u, /*!< source 6 as an external trigger source for ADC . */
ADC_HwTrgSource_Alt7 = 7u, /*!< source 7 as an external trigger source for ADC . */
ADC_HwTrgSource_Alt8 = 8u, /*!< source 8 as an external trigger source for ADC . */
ADC_HwTrgSource_Alt9 = 9u, /*!< source 9 as an external trigger source for ADC . */
ADC_HwTrgSource_Alt10 = 10u, /*!< source 10 as an external trigger source for ADC . */
ADC_HwTrgSource_Alt11 = 11u, /*!< source 11 as an external trigger source for ADC . */
ADC_HwTrgSource_Alt12 = 12u, /*!< source 12 as an external trigger source for ADC . */
ADC_HwTrgSource_Alt13 = 13u, /*!< source 13 as an external trigger source for ADC . */
ADC_HwTrgSource_Alt14 = 14u, /*!< source 14 as an external trigger source for ADC . */
ADC_HwTrgSource_Alt15 = 15u, /*!< source 15 as an external trigger source for ADC . */
ADC_HwTrgSource_Alt16 = 16u, /*!< source 16 as an external trigger source for ADC . */
ADC_HwTrgSource_Alt17 = 17u, /*!< source 17 as an external trigger source for ADC . */
ADC_HwTrgSource_Alt18 = 18u, /*!< source 18 as an external trigger source for ADC . */
ADC_HwTrgSource_Alt19 = 19u, /*!< source 19 as an external trigger source for ADC . */
ADC_HwTrgSource_Alt20 = 20u, /*!< source 20 as an external trigger source for ADC . */
ADC_HwTrgSource_Alt21 = 21u, /*!< source 21 as an external trigger source for ADC . */
ADC_HwTrgSource_Alt22 = 22u, /*!< source 22 as an external trigger source for ADC . */
ADC_HwTrgSource_Alt23 = 23u, /*!< source 23 as an external trigger source for ADC . */
ADC_HwTrgSource_Alt24 = 24u, /*!< source 24 as an external trigger source for ADC . */
ADC_HwTrgSource_Alt25 = 25u, /*!< source 25 as an external trigger source for ADC . */
ADC_HwTrgSource_Alt26 = 26u, /*!< source 26 as an external trigger source for ADC . */
ADC_HwTrgSource_Alt27 = 27u, /*!< source 27 as an external trigger source for ADC . */
ADC_HwTrgSource_Alt28 = 28u, /*!< source 28 as an external trigger source for ADC . */
ADC_HwTrgSource_Alt29 = 29u, /*!< source 29 as an external trigger source for ADC . */
ADC_HwTrgSource_Alt30 = 30u, /*!< source 30 as an external trigger source for ADC . */
ADC_HwTrgSource_Alt31 = 31u, /*!< source 31 as an external trigger source for ADC . */
} ADC_HwTrgSource_Type;
/*!
* @brief ADC SampleTime type.
*
* Select channel sample time.
*/
typedef enum
{
ADC_SampleTime_Alt0 = 0u, /*!< Channel sample time mode 0 . */
ADC_SampleTime_Alt1 = 1u, /*!< Channel sample time mode 1 . */
ADC_SampleTime_Alt2 = 2u, /*!< Channel sample time mode 2 . */
ADC_SampleTime_Alt3 = 3u, /*!< Channel sample time mode 3 . */
ADC_SampleTime_Alt4 = 4u, /*!< Channel sample time mode 4 . */
ADC_SampleTime_Alt5 = 5u, /*!< Channel sample time mode 5 . */
ADC_SampleTime_Alt6 = 6u, /*!< Channel sample time mode 6 . */
ADC_SampleTime_Alt7 = 7u, /*!< Channel sample time mode 7 . */
ADC_SampleTime_Alt8 = 8u, /*!< Channel sample time mode 8 . */
ADC_SampleTime_Alt9 = 9u, /*!< Channel sample time mode 9 . */
ADC_SampleTime_Alt10 = 10u, /*!< Channel sample time mode 10. */
ADC_SampleTime_Alt11 = 11u, /*!< Channel sample time mode 11. */
ADC_SampleTime_Alt12 = 12u, /*!< Channel sample time mode 12. */
ADC_SampleTime_Alt13 = 13u, /*!< Channel sample time mode 13. */
ADC_SampleTime_Alt14 = 14u, /*!< Channel sample time mode 14. */
ADC_SampleTime_Alt15 = 15u, /*!< Channel sample time mode 15. */
} ADC_SampleTime_Type;
/*!
* @brief This type of structure instance is used to keep the settings
* when calling the @ref ADC_Init() to initialize the ADC module.
*/
typedef struct
{
ADC_Resolution_Type Resolution; /*!< Specify the available bits for the conversion result data. */
ADC_ClockDiv_Type ClockDiv; /*!< Specify the adc clock divison. */
ADC_Align_Type Align; /*!< Specify the data alignment. */
ADC_ConvMode_Type ConvMode; /*!< Specify the adc conversion mode. */
} ADC_Init_Type;
/*!
* @brief This type of structure instance is used to keep the settings
* when calling the @ref ADC_EnableHwTrigger() to initialize the ADC hardware trigger module.
*/
typedef struct
{
ADC_HwTrgSource_Type Source; /*!< Select the ADC hardware trigger source. */
ADC_HwTrgEdge_Type Edge; /*!< Select the trigger edge. */
ADC_HwTrgDelayCycle_Type DelayCycle; /*!< Select the hardware trigger shift sample. */
} ADC_HwTrgConf_Type;
/*!
* @brief This type of structure instance is used to keep the settings
* when calling the @ref ADC_EnableRegSeq() to initialize the ADC regular sequence module.
*/
typedef struct
{
uint32_t SeqSlots; /*!< Select the slots length. */
ADC_RegSeqDirection_Type SeqDirection; /*!< Select the regular sequence sacn direction. */
} ADC_RegSeqConf_Type;
/*!
* @brief This type of structure instance is used to keep the settings
* when calling the @ref ADC_EnableAnySeq() to initialize the ADC Any sequence mode.
*/
typedef struct
{
uint32_t SeqLen; /*!< Select the slots length. */
uint32_t * SeqChannels; /*!< Select the channel, channel can be disorder. */
} ADC_AnySeqConf_Type;
/*!
* @brief This type of structure instance is used to keep the settings
* when calling the @ref ADC_EnableHwCompare() to enable the ADC windows compare mode.
*/
typedef struct
{
uint32_t ChnNum; /*!< Select the channel number binding to the compare. */
uint32_t HighLimit; /*!< The comparator high limit. */
uint32_t LowLimit; /*!< The comparator low limit. */
} ADC_HwCompConf_Type;
/*!
* @brief Initialize the ADC module.
*
* @param ADCx ADC instance.
* @param init Pointer to the initialization structure. See to @ref ADC_Init_Type.
* @return None.
*/
void ADC_Init(ADC_Type * ADCx, ADC_Init_Type * init);
/*!
* @brief Enable the ADC module.
*
* The ADC module should be enabled before conversion data.
*
* @param ADCx ADC instance.
* @param enable 'true' to enable the module, 'false' to disable the module.
* @return None.
*/
void ADC_Enable(ADC_Type * ADCx, bool enable);
/*!
* @brief Enable Temperature sensor from the ADC module.
*
* The module should be enabled when Using the built-in temperature sensor to
* detect temperature changes inside the device.
*
* @param ADCx ADC instance.
* @param enable 'true' to enable the module, 'false' to disable the module.
* @return None.
*/
void ADC_EnableTempSensor(ADC_Type * ADCx, bool enable);
/*!
* @brief Enable Voltage sensor from the ADC module.
*
* The module should be enabled when using internal reference voltage .
*
* @param ADCx ADC instance.
* @param enable 'true' to enable the module, 'false' to disable the module.
* @return None.
*/
void ADC_EnableVoltSensor(ADC_Type * ADCx, bool enable);
/*!
* @brief Enable the DMA from the ADC module.
*
* @param ADCx ADC instance.
* @param enable 'true' to enable the DMA, 'false' to disable the DMA.
* @return None.
*/
void ADC_EnableDMA(ADC_Type * ADCx, bool enable);
/*!
* @brief Enable interrupts of the ADC module.
*
* @param ADCx ADC instance.
* @param interrupts Interrupt code masks.
* @param enable 'true' to enable the indicated interrupts, 'false' to disable the indicated interrupts.
* @return None.
*/
void ADC_EnableInterrupts(ADC_Type * ADCx, uint32_t interrupts, bool enable);
/*!
* @brief Get the current status flags of the ADC module.
*
* @param ADCx ADC instance.
* @return Status flags.
*/
uint32_t ADC_GetStatus(ADC_Type * ADCx);
/*!
* @brief Clear the status flags of the ADC module.
*
* @param ADCx ADC instance.
* @param flags The mask codes of the indicated interrupt flags to be cleared.
* @return None.
*/
void ADC_ClearStatus(ADC_Type * ADCx, uint32_t flags);
/*!
* @brief Get the channel convert data from the ADC module.
*
* @param ADCx ADC instance.
* @param channel The convert channel.
* @param flags The ADC convert result flags. See to @ref ADC_RESULT_FLAGS.
* @return The data value.
*/
uint32_t ADC_GetConvResult(ADC_Type * ADCx, uint32_t * channel, uint32_t * flags);
/*!
* @brief Get the indication channel current data from the ADC module.
*
* @param ADCx ADC instance.
* @param channel the adc channel.
* @param flags The ADC convert result flags. See to @ref ADC_RESULT_FLAGS.
* @return The data value.
*/
uint32_t ADC_GetChnConvResult(ADC_Type * ADCx, uint32_t channel, uint32_t * flags);
/*!
* @brief Configuration channel sample time of the ADC module.
*
* @param ADCx ADC instance.
* @param channel the adc convert channel.
* @param sampletime the adc channel sample time
* @return None.
*/
void ADC_SetChnSampleTime(ADC_Type * ADCx, uint32_t channel, ADC_SampleTime_Type sampletime);
/*!
* @brief Enable regular sequence from the ADC module.
*
* The ADC module should be enabled before regular sequence function.
* it also have interrupt.
*
* @param ADCx ADC instance.
* @param conf Pointer to the initialization structure. See to @ref ADC_RegSeqConf_Type.
* @return None.
*/
void ADC_EnableRegSeq(ADC_Type * ADCx, ADC_RegSeqConf_Type * conf);
/*!
* @brief Enable hardware trigger from the ADC module.
*
* The ADC module should be enabled before using hardware trrigger function.
* it also have interrupt.
*
* @param ADCx ADC instance.
* @param conf Select the hardware trigger source. See to @ref ADC_HwTrgConf_Type.
* @return None.
*/
void ADC_EnableHwTrigger(ADC_Type * ADCx, ADC_HwTrgConf_Type * conf);
/*!
* @brief Enable Any sequence from the ADC module.
*
* The ADC module should be enabled before Any sequence function.
* it also have interrupt.
*
* @param ADCx ADC instance.
* @param conf Pointer to the initialization structure. See to @ref ADC_AnySeqConf_Type.
* @return None.
*/
void ADC_EnableAnySeq(ADC_Type * ADCx, ADC_AnySeqConf_Type * conf);
/*!
* @brief Enable window comparison from the ADC module.
*
* The ADC module should be enabled before using analog watchdog function.
* it also have interrupt.
*
* @param ADCx ADC instance.
* @param conf Pointer to the initialization structure. See to @ref ADC_HwCompareConf_Type.
* @return None.
*/
void ADC_EnableHwComp(ADC_Type * ADCx, ADC_HwCompConf_Type * conf);
/*!
* @brief Do soft trigger.
*
* @param ADCx ADC instance.
* @param enable 'true' to enable the ADC start convert, 'false' to disable.
* @return None.
*/
void ADC_DoSwTrigger(ADC_Type * ADCx, bool enable);
/*!
*@}
*/
#endif /*__HAL_ADC_H__. */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_COMMON_H__
#define __HAL_COMMON_H__
#include <stdint.h>
#include <stdbool.h>
#include <string.h>
#include "hal_device_registers.h"
#endif /* __HAL_COMMON_H__ */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_COMP_H__
#define __HAL_COMP_H__
#include "hal_common.h"
/*!
* @addtogroup COMP
* @{
*/
/*!
* @brief COMP driver version number.
*/
#define COMP_DRIVER_VERSION 0u /*!< COMP_0. */
/*!
* @brief COMP number.
*/
#define COMP_CHANNEL_NUM 2
/*!
* @brief COMP output filter type.
*
* If the compare result keeps n APB Clocks unchanged, the output is valid.
*/
typedef enum
{
COMP_OutFilter_1 = 0, /*!< 1 PCLK filter. */
COMP_OutFilter_2 = 1, /*!< 2 PCLK filter. */
COMP_OutFilter_4 = 2, /*!< 4 PCLK filter. */
COMP_OutFilter_8 = 3, /*!< 8 PCLK filter. */
COMP_OutFilter_16 = 4, /*!< 16 PCLK filter. */
COMP_OutFilter_32 = 5, /*!< 32 PCLK filter. */
COMP_OutFilter_64 = 6, /*!< 64 PCLK filter. */
COMP_OutFilter_128 = 7, /*!< 128 PCLK filter. */
} COMP_OutFilter_Type;
/*!
* @brief COMP hysteresis type.
*
* If V(InvInput) > V(PosInput), the compare result is high, if V(InvInput) < (V(PosInput) - hysteresis), the compare result is low.
*/
typedef enum
{
COMP_Hysteresis_Alt0 = 0, /*!< Hysteresis Alt 0. */
COMP_Hysteresis_Alt1 = 1, /*!< Hysteresis Alt 1. */
COMP_Hysteresis_Alt2 = 2, /*!< Hysteresis Alt 2. */
COMP_Hysteresis_Alt3 = 3, /*!< Hysteresis Alt 3. */
} COMP_Hysteresis_Type;
/*!
* @brief COMP output mux type.
*/
typedef enum
{
COMP_OutMux_None = 0, /*!< Not output to other peripheral input. */
COMP_OutMux_Alt0 = 2, /*!< Output Mux 0. */
COMP_OutMux_Alt1 = 4, /*!< Output Mux 1. */
COMP_OutMux_Alt2 = 6, /*!< Output Mux 2. */
COMP_OutMux_Alt3 = 7, /*!< Output Mux 3. */
COMP_OutMux_Alt4 = 8, /*!< Output Mux 4. */
COMP_OutMux_Alt5 = 9, /*!< Output Mux 5. */
COMP_OutMux_Alt6 = 10, /*!< Output Mux 6. */
COMP_OutMux_Alt7 = 11, /*!< Output Mux 7. */
} COMP_OutMux_Type;
/*!
* @brief COMP input Mux type.
*/
typedef enum
{
COMP_InMux_Alt0 = 0, /*!< Input Mux 0. */
COMP_InMux_Alt1 = 1, /*!< Input Mux 1. */
COMP_InMux_Alt2 = 2, /*!< Input Mux 2. */
COMP_InMux_Alt3 = 3, /*!< Input Mux 3. */
COMP_InMux_Alt4 = 4, /*!< Input Mux 4. */
} COMP_InMux_Type;
/*!
* @brief COMP speed type.
*/
typedef enum
{
COMP_Speed_High = 0, /*!< High speed, high power. */
COMP_Speed_Middle = 1, /*!< Middle speed, middle power. */
COMP_Speed_Low = 2, /*!< Low speed, low power. */
COMP_Speed_DeepLow = 3, /*!< Deep low speed, deep low power. */
} COMP_Speed_Type;
/*!
* @brief COMP external reference voltage source type.
*/
typedef enum
{
COMP_ExtVrefSource_VREFINT = 0, /*!< Internal reference voltage. */
COMP_ExtVrefSource_VDDA = 1, /*!< VDDA voltage. */
} COMP_ExtVrefSource_Type;
/*!
* @brief COMP external reference voltage type.
*/
typedef enum
{
COMP_ExtVrefVolt_Alt0 = 0, /*!< External reference voltage Alt 0. */
COMP_ExtVrefVolt_Alt1 = 1, /*!< External reference voltage Alt 1. */
COMP_ExtVrefVolt_Alt2 = 2, /*!< External reference voltage Alt 2. */
COMP_ExtVrefVolt_Alt3 = 3, /*!< External reference voltage Alt 3. */
COMP_ExtVrefVolt_Alt4 = 4, /*!< External reference voltage Alt 4. */
COMP_ExtVrefVolt_Alt5 = 5, /*!< External reference voltage Alt 5. */
COMP_ExtVrefVolt_Alt6 = 6, /*!< External reference voltage Alt 6. */
COMP_ExtVrefVolt_Alt7 = 7, /*!< External reference voltage Alt 7. */
COMP_ExtVrefVolt_Alt8 = 8, /*!< External reference voltage Alt 8. */
COMP_ExtVrefVolt_Alt9 = 9, /*!< External reference voltage Alt 9. */
COMP_ExtVrefVolt_Alt10 = 10, /*!< External reference voltage Alt 10. */
COMP_ExtVrefVolt_Alt11 = 11, /*!< External reference voltage Alt 11. */
COMP_ExtVrefVolt_Alt12 = 12, /*!< External reference voltage Alt 12. */
COMP_ExtVrefVolt_Alt13 = 13, /*!< External reference voltage Alt 13. */
COMP_ExtVrefVolt_Alt14 = 14, /*!< External reference voltage Alt 14. */
COMP_ExtVrefVolt_Alt15 = 15, /*!< External reference voltage Alt 15. */
} COMP_ExtVrefVolt_Type;
/*!
* @brief COMP round robin period type.
*
* wait n APB clock to compare next channel.
*/
typedef enum
{
COMP_RoundRobinPeriod_1 = 0, /*!< Wait 1 PCLK2 to compare next channel. */
COMP_RoundRobinPeriod_2 = 1, /*!< Wait 2 PCLK2 to compare next channel. */
COMP_RoundRobinPeriod_4 = 2, /*!< Wait 4 PCLK2 to compare next channel. */
COMP_RoundRobinPeriod_8 = 3, /*!< Wait 8 PCLK2 to compare next channel. */
COMP_RoundRobinPeriod_16 = 4, /*!< Wait 16 PCLK2 to compare next channel. */
COMP_RoundRobinPeriod_32 = 5, /*!< Wait 32 PCLK2 to compare next channel. */
COMP_RoundRobinPeriod_64 = 6, /*!< Wait 64 PCLK2 to compare next channel. */
COMP_RoundRobinPeriod_128 = 7, /*!< Wait 128 PCLK2 to compare next channel. */
} COMP_RoundRobinPeriod_Type;
/*!
* @brief COMP round robin channel Type.
*/
typedef enum
{
COMP_RoundRobinChnGroup_Alt0 = 0, /*!< Compare the positive input 1 & 2. */
COMP_RoundRobinChnGroup_Alt1 = 1, /*!< Compare the positive input 1, 2 & 3. */
} COMP_RoundRobinChnGroup_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref COMP_Init() to initialize the COMP module.
*/
typedef struct
{
COMP_OutFilter_Type OutFilter; /*!< Specify the output filter. */
COMP_Hysteresis_Type Hysteresis; /*!< Specify the hysteresis. */
bool OutInvert; /*!< Specify the output invert. */
COMP_OutMux_Type OutMux; /*!< Specify the output. */
COMP_InMux_Type PosInMux; /*!< Specify the positive input. */
COMP_InMux_Type InvInMux; /*!< Specify the nagetive input. */
COMP_Speed_Type Speed; /*!< Specify the compare speed. */
} COMP_Init_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref COMP_EnableExtVrefConf() to enable the COMP ext vref.
*/
typedef struct
{
COMP_ExtVrefSource_Type VrefSource; /*!< Specify the Vref source. */
COMP_ExtVrefVolt_Type Volt; /*!< Specify the Vref voltage. */
} COMP_ExtVrefConf_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref COMP_EnableRoundRobinConf() to enable the COMP round robin.
*/
typedef struct
{
COMP_RoundRobinPeriod_Type Period; /*!< Specify the round robin period. */
bool InvInFix; /*!< Specify the nagetive input fix. */
COMP_RoundRobinChnGroup_Type ChnGroup; /*!< Specify the round robin channel. */
} COMP_RoundRobinConf_Type;
/*!
* @brief Initialize the COMP module.
*
* @param COMPx COMP instance.
* @param channel COMP channel.
* @param init Pointer to the initialization structure. See to @ref COMP_Init_Type.
* @return None.
*/
void COMP_Init(COMP_Type * COMPx, uint32_t channel, COMP_Init_Type * init);
/*!
* @brief Enable the COMP module.
*
* @param COMPx COMP instance.
* @param channel COMP channel.
* @param enable 'true' to enable the module, 'false' to disable the module.
* @return None.
*/
void COMP_Enable(COMP_Type * COMPx, uint32_t channel, bool enable);
/*!
* @brief Keep the COMP settings not changed.
*
* @param COMPx COMP instance.
* @param channel COMP channel.
* @return None.
*/
void COMP_Lock(COMP_Type * COMPx, uint32_t channel);
/*!
* @brief Get comp output status.
*
* @param COMPx COMP instance.
* @param channel COMP channel.
* @return output status.
*/
bool COMP_GetOutputStatus(COMP_Type * COMPx, uint32_t channel);
/*!
* @brief Enable the COMP ext Vref.
*
* @param COMPx COMP instance.
* @param init Pointer to the initialization structure. See to @ref COMP_ExtVrefConf_Type, if null, disable ext Vref.
* @return None.
*/
void COMP_EnableExtVrefConf(COMP_Type * COMPx, COMP_ExtVrefConf_Type * conf);
/*!
* @brief Enable polling function.
*
* Enable round robin function, the comp channel can get positive input 1, 2 & 3 status.
*
* @param COMPx COMP instance.
* @param channel COMP channel.
* @param init Pointer to the initialization structure. See to @ref COMP_RoundRobinConf_Type, if null, disable round robin.
* @return None.
*/
void COMP_EnableRoundRobinConf(COMP_Type * COMPx, uint32_t channel, COMP_RoundRobinConf_Type * conf);
/*!
* @brief Get round robin output status.
*
* @param COMPx COMP instance.
* @param channel COMP channel.
* @param pos_in Positive input Mux.
* @return Status of comp channel output level.
*/
bool COMP_GetRoundRobinOutStatus(COMP_Type * COMPx, uint32_t channel, COMP_InMux_Type pos_in);
/*!
*@}
*/
#endif /* __HAL_COMP_H__ */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_DAC_H__
#define __HAL_DAC_H__
#include "hal_common.h"
/*!
* @addtogroup DAC
* @{
*/
/*!
* @brief DAC driver version number.
*/
#define DAC_DRIVER_VERSION 0u /*!< dac_0. */
/*!
* @addtogroup DAC_CHANNEL_SELECTION
* @{
*/
#define DAC_CHN_NUM (2u) /*!< The total number of DAC channel. */
#define DAC_CHN_1 (0u) /*!< The selection of DAC Channel 1. */
#define DAC_CHN_2 (1u) /*!< The selection of DAC Channel 2. */
/*!
*@}
*/
/*!
* @brief DAC align type.
*/
typedef enum
{
DAC_Align_8b_Dual = 0u, /*!< The selection of dual channel data alignment of 8b right. */
DAC_Align_8b_Right = 1u, /*!< The selection of single channel data alignment of 8b right. */
DAC_Align_12b_Left = 2u, /*!< The selection of single channel data alignment of 12b left. */
DAC_Align_12b_Right = 3u, /*!< The selection of single channel data alignment of 12b right. */
DAC_Align_12b_Dual_Left = 4u, /*!< The selection of dual channel data alignment of 12b left. */
DAC_Align_12b_Dual_Right = 5u, /*!< The selection of dual channel data alignment of 12b right. */
} DAC_Align_Type;
/*!
* @brief DAC trigger source selection.
*/
typedef enum
{
DAC_TrgSource_Alt0 = 0u, /*!< The selection of the documented trigger of value 0. */
DAC_TrgSource_Alt1 = 1u, /*!< The selection of the documented trigger of value 1. */
DAC_TrgSource_Alt2 = 2u, /*!< The selection of the documented trigger of value 2. */
DAC_TrgSource_Alt3 = 3u, /*!< The selection of the documented trigger of value 3. */
DAC_TrgSource_Alt4 = 4u, /*!< The selection of the documented trigger of value 4. */
DAC_TrgSource_Alt5 = 5u, /*!< The selection of the documented trigger of value 5. */
DAC_TrgSource_Alt6 = 6u, /*!< The selection of the documented trigger of value 6. */
DAC_TrgSource_Alt7 = 7u, /*!< The selection of the documented software trigger. */
DAC_TrgSource_None = 16u, /*!< No trigger to be used. */
} DAC_TrgSource_Type;
/*!
* @brief DAC LFSR unmask bit selector type for adding noise wave.
*/
typedef enum
{
DAC_AddNoise_LFSRUnMask_0 = 0u, /*!< Unmask DAC channel LFSR bit0. */
DAC_AddNoise_LFSRUnMask_1 = 1u, /*!< Unmask DAC channel LFSR bit[1:0]. */
DAC_AddNoise_LFSRUnMask_2 = 2u, /*!< Unmask DAC channel LFSR bit[2:0]. */
DAC_AddNoise_LFSRUnMask_3 = 3u, /*!< Unmask DAC channel LFSR bit[3:0]. */
DAC_AddNoise_LFSRUnMask_4 = 4u, /*!< Unmask DAC channel LFSR bit[4:0]. */
DAC_AddNoise_LFSRUnMask_5 = 5u, /*!< Unmask DAC channel LFSR bit[5:0]. */
DAC_AddNoise_LFSRUnMask_6 = 6u, /*!< Unmask DAC channel LFSR bit[6:0]. */
DAC_AddNoise_LFSRUnMask_7 = 7u, /*!< Unmask DAC channel LFSR bit[7:0]. */
DAC_AddNoise_LFSRUnMask_8 = 8u, /*!< Unmask DAC channel LFSR bit[8:0]. */
DAC_AddNoise_LFSRUnMask_9 = 9u, /*!< Unmask DAC channel LFSR bit[9:0]. */
DAC_AddNoise_LFSRUnMask_10 = 10u, /*!< Unmask DAC channel LFSR bit[10:0]. */
DAC_AddNoise_LFSRUnMask_11 = 11u, /*!< Unmask DAC channel LFSR bit[11:0]. */
} DAC_AddNoise_Type;
/*!
* @brief DAC triangle amplitude selector type for adding triangle wave.
*/
typedef enum
{
DAC_AddTriangle_LFSRAmplitude_1 = 0u, /*!< Max triangle amplitude of 1. */
DAC_AddTriangle_LFSRAmplitude_3 = 1u, /*!< Max triangle amplitude of 3. */
DAC_AddTriangle_LFSRAmplitude_7 = 2u, /*!< Max triangle amplitude of 7. */
DAC_AddTriangle_LFSRAmplitude_15 = 3u, /*!< Max triangle amplitude of 15. */
DAC_AddTriangle_LFSRAmplitude_31 = 4u, /*!< Max triangle amplitude of 31. */
DAC_AddTriangle_LFSRAmplitude_63 = 5u, /*!< Max triangle amplitude of 63. */
DAC_AddTriangle_LFSRAmplitude_127 = 6u, /*!< Max triangle amplitude of 127. */
DAC_AddTriangle_LFSRAmplitude_255 = 7u, /*!< Max triangle amplitude of 255. */
DAC_AddTriangle_LFSRAmplitude_511 = 8u, /*!< Max triangle amplitude of 511. */
DAC_AddTriangle_LFSRAmplitude_1023 = 9u, /*!< Max triangle amplitude of 1023. */
DAC_AddTriangle_LFSRAmplitude_2047 = 10u, /*!< Max triangle amplitude of 2047. */
DAC_AddTriangle_LFSRAmplitude_4095 = 11u, /*!< Max triangle amplitude of 4095. */
} DAC_AddTriangle_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref DAC_EnableAddNoise() to initialize the DAC noise wave generation.
*/
typedef struct
{
DAC_AddNoise_Type AddNoise; /*!< Specify the noise wave pattern. */
} DAC_AddNoise_Init_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref DAC_EnableAddTriangle() to initialize the DAC triangle wave generation.
*/
typedef struct
{
DAC_AddTriangle_Type AddTriangle; /*!< Specify the triangle wave pattern. */
} DAC_AddTriangle_Init_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref DAC_Init() to initialize the DAC module.
*/
typedef struct
{
DAC_TrgSource_Type TrgSource; /*!< Specify whether to use the trigger and the trigger type. */
bool EnableOutBuf; /*!< Specify whether output buffer is enabled. */
} DAC_Init_Type;
/*!
* @brief Initialize the DAC module.
*
* @param DACx DAC instance.
* @param channel Indicated DAC channel. See to @ref DAC_CHANNEL_SELECTION.
* @param init Pointer to the initialization structure. See to @ref DAC_Init_Type.
* @return None.
*/
void DAC_Init(DAC_Type * DACx, uint32_t channel, DAC_Init_Type * init);
/*!
* @brief Enable the DAC module.
*
* The DAC module should be enabled before outputting voltage.
*
* @param DACx DAC instance.
* @param channel Indicated DAC channel. See to @ref DAC_CHANNEL_SELECTION.
* @param enable 'true' to enable the module, 'false' to disable the module.
* @return None.
*/
void DAC_Enable(DAC_Type * DACx, uint32_t channel, bool enable);
/*!
* @brief Get the echo data from the output of the indicated DAC channel.
*
* The value in DAC_DORx register takes effect on the actual output of DAC.
*
* @param DACx DAC instance.
* @param channel Indicated DAC channel. See to @ref DAC_CHANNEL_SELECTION.
* @return The indicated DAC channel data output value.
*/
uint32_t DAC_GetData(DAC_Type * DACx, uint32_t channel);
/*!
* @brief Put the value into the indicated channel of the DAC module with the alignment.
*
* The value in DAC_DORx register takes effect on the actual output of DAC.
*
* @param DACx DAC instance.
* @param channel Indicated DAC channel. See to @ref DAC_CHANNEL_SELECTION.
* @param value Data value to be put in indicated DAC channel for conversion.
* @param align Alignment the value expected to be put into the conversion. See to @ref DAC_Align_Type.
* @return The current converted value of the indicated DAC channel.
*/
uint32_t DAC_PutData(DAC_Type * DACx, uint32_t channel, uint32_t value, DAC_Align_Type align);
/*!
* @brief Enable the feature of generating noise wave from the DAC module.
*
* If enable additional noise wave, the output value will depend on the the unmask LFSR bit and input of the indicated channel.
*
* @param DACx DAC instance.
* @param channel Indicated DAC channel. See to @ref DAC_CHANNEL_SELECTION.
* @param init Pointer to the initialization structure. See to @ref DAC_AddNoise_Init_Type. If null, disable the wave generation.
* @return None.
*/
void DAC_EnableAddNoise(DAC_Type * DACx, uint32_t channel, DAC_AddNoise_Init_Type * init);
/*!
* @brief Enable the feature of generating triangle wave from the DAC module.
*
* Defaultedly, DAC does not generate any wave.
* If enable additional triangle wave, the output value will depend on the the indicated amplitude and input of the indicated channel.
*
* @param DACx DAC instance.
* @param channel Indicated DAC channel. See to @ref DAC_CHANNEL_SELECTION.
* @param init Pointer to the initialization structure. See to @ref DAC_AddTriangle_Init_Type. If null, disable the wave generation.
* @return None.
*/
void DAC_EnableAddTriangle(DAC_Type * DACx, uint32_t channel, DAC_AddTriangle_Init_Type * init);
/*!
* @brief Enable the DMA trigger from the DAC module.
*
* The DMA trigger events are the same as the intertupts.
*
* @param DACx DAC instance.
* @param channel Indicated DAC channel. See to @ref DAC_CHANNEL_SELECTION.
* @param enable 'true' to enable the DMA trigger, 'false' to disable the DMA trigger.
* @return None.
*/
void DAC_EnableDMA(DAC_Type * DACx, uint32_t channel, bool enable);
/*!
* @brief Do trigger the indicated DAC channel with software trigger.
*
* @param DACx DAC instance.
* @param channel Indicated DAC channel. See to @ref DAC_CHANNEL_SELECTION.
* @return None.
*/
void DAC_DoSwTrigger(DAC_Type * DACx, uint32_t channel);
/*!
* @brief Do trigger the dual DAC channels with software trigger simultaneously.
*
* @param DACx DAC instance.
* @return None.
*/
void DAC_DoDualChannelSwTrigger(DAC_Type * DACx);
/*!
* @brief Get the indicated register address of the DAC module.
*
* @param DACx DAC instance.
* @param channel Indicated DAC channel. See to @ref DAC_CHANNEL_SELECTION.
* @param align Alignment that the data expects to br transferred. See to @ref DAC_Align_Type.
* @return The value of the address for indicated align type of the DAC channel.
*/
uint32_t DAC_GetDataRegAddr(DAC_Type * DACx, uint32_t channel, DAC_Align_Type align);
/*!
* @brief Put 8-bit value into the indicated channel of the DAC module.
*
* The low 8-bit of the setting value here will be output with 4-bit left shift.
* If the value is 0x1f, the output will be 0x1f0.
*
* @param DACx DAC instance.
* @param channel Indicated DAC channel. See to @ref DAC_CHANNEL_SELECTION.
* @param value Data value to be put in indicated DAC channel for conversion.
* @return None.
*/
void DAC_PutData8bRightAlign(DAC_Type * DACx, uint32_t channel, uint32_t value);
/*!
* @brief Put the 12-bit value into indicated channel of the DAC module.
*
* The low 12-bit of the setting value here will be output after 4-bit right shift.
* If the value is 0x1ff, the output will be 0x1f.
*
* @param DACx DAC instance.
* @param channel Indicated DAC channel. See to @ref DAC_CHANNEL_SELECTION.
* @param value Data value to be put in indicated DAC channel for conversion.
* @return None.
*/
void DAC_PutData12bLeftAlign(DAC_Type * DACx, uint32_t channel, uint32_t value);
/*!
* @brief Put the current data into indicated channel of the DAC module.
*
* The low 12-bit of the setting value here will output with the original value.
*
* @param DACx DAC instance.
* @param channel Indicated DAC channel. See to @ref DAC_CHANNEL_SELECTION.
* @param value Data value to be put in indicated DAC channel for conversion.
* @return None.
*/
void DAC_PutData12bRightAlign(DAC_Type * DACx, uint32_t channel, uint32_t value);
/*!
* @brief Respectively put the value into the dual channels of the DAC module 8b right aligned.
*
* Simultaneously output the low 8-bit of the low 16-bit and high 16-bit of the 32-bit value seperately with a 4-bit left shift.
* If value is 0x011f01ff, the output of each channel will be 0xff0 ( channel 1 ) and 0x1f0 ( channel 2 ).
*
* @param DACx DAC instance.
* @param value Data value to be put in DAC channel 1 and DAC channel 2 for conversion.
* @return None.
*/
void DAC_PutDualChannelData8bRightAlign(DAC_Type * DACx, uint32_t value);
/*!
* @brief Put the data into the dual channel of the DAC module 12b left aligned.
*
* Simultaneously output the high 12-bit of the low 16-bit and high 16-bit of the 32-bit value seperately after 4-bit right shift.
* If value is 0x011f01ff, the output of each channel will be 0x01f ( channel 1 ) and 0x011 ( channel 2 ).
*
* @param DACx DAC instance.
* @param value Data value to be put in DAC channel 1 and DAC channel 2 for conversion.
* @return None.
*/
void DAC_PutDualChannelData12bLeftAlign(DAC_Type * DACx, uint32_t value);
/*!
* @brief Put the data into the dual channel of the DAC module 12b right aligned.
*
* Simultaneously output the low 12-bit of the low 16-bit and high 16-bit of the 32-bit value seperately.
*
* @param DACx DAC instance.
* @param value Data value to be put in DAC channel 1 and DAC channel 2 for conversion.
* @return None.
*/
void DAC_PutDualChannelData12bRightAlign(DAC_Type * DACx, uint32_t value);
/*!
* @brief Get the 8-bit data register address of the DAC module.
*
* @param DACx DAC instance.
* @param channel Indicated DAC channel. See to @ref DAC_CHANNEL_SELECTION.
* @return The value of the address for DAC module's 8-bit data register .
*/
uint32_t DAC_GetData8bRegAddr(DAC_Type * DACx, uint32_t channel);
/*!
* @brief Get the 12-bit left-aligned data register address of the DAC module.
*
* @param DACx DAC instance.
* @param channel Indicated DAC channel. See to @ref DAC_CHANNEL_SELECTION.
* @return The value of the address for DAC module's 12-bit left-aligned data register .
*/
uint32_t DAC_GetData12bLeftRegAddr(DAC_Type * DACx, uint32_t channel);
/*!
* @brief Get the 12-bit right-aligned data register address of the DAC module.
*
* @param DACx DAC instance.
* @param channel Indicated DAC channel. See to @ref DAC_CHANNEL_SELECTION.
* @return The value of the address for DAC module's 12-bit right-aligned data register .
*/
uint32_t DAC_GetData12bRightRegAddr(DAC_Type * DACx, uint32_t channel);
/*!
* @brief Get the dual channel 8-bit data register address of the DAC module.
*
* @param DACx DAC instance.
* @return The value of the address for DAC module's dual channel 8-bit data register .
*/
uint32_t DAC_GetDualChannelData8bRegAddr(DAC_Type * DACx);
/*!
* @brief Get the dual channel 12-bit left-aligned data register address of the DAC module.
*
* @param DACx DAC instance.
* @return The value of the address for DAC module's 12-bit dual channel left-aligned data register .
*/
uint32_t DAC_GetDualChannelData12bLeftRegAddr(DAC_Type * DACx);
/*!
* @brief Get the dual channel 12-bit right-aligned data register address of the DAC module.
*
* @param DACx DAC instance.
* @return The value of the address for DAC module's 12-bit dual channel right-aligned data register .
*/
uint32_t DAC_GetDualChannelData12bRightRegAddr(DAC_Type * DACx);
/*!
*@}
*/
#endif /* __HAL_DAC_H__ */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_DMA_H__
#define __HAL_DMA_H__
#include "hal_common.h"
/*!
* @addtogroup DMA
* @{
*/
/*!
* @addtogroup DMA_CHANNEL_INT
* @{
*/
#define DMA_CHN_INT_XFER_GLOBAL (0x1u << 0u) /*!< DMA global interrupt channel. */
#define DMA_CHN_INT_XFER_DONE (0x1u << 1u) /*!< DMA end of transfer interrupt channel. */
#define DMA_CHN_INT_XFER_HALF_DONE (0x1u << 2u) /*!< DMA half transfer interrupt channel. */
#define DMA_CHN_INT_XFER_ERR (0x1u << 3u) /*!< DMA transfer error interrupt channel. */
/*!
* @}
*/
/*!
* @brief Define the enum type of DMA_XferMode_Type.
*/
typedef enum
{
DMA_XferMode_PeriphToMemory = 0u, /*!< memory to memory mode, from periph addr to memory addr. */
DMA_XferMode_MemoryToPeriph = 1u, /*!< memory to memory mode, from periph addr to memory addr. */
DMA_XferMode_PeriphToMemoryBurst = 2u, /*!< memory to memory mode, from periph addr to memory addr. */
DMA_XferMode_MemoryToPeriphBurst = 3u, /*!< memory to memory mode, from memory addr to periph addr. */
} DMA_XferMode_Type;
/*!
* @brief Define the enum type of DMA_ReloadMode_Type.
*/
typedef enum
{
DMA_ReloadMode_OneTime = 0u, /*!< the count is exhausted after the xfer is done. */
DMA_ReloadMode_AutoReload = 1u, /*!< auto reload the count for the new xfer. */
DMA_ReloadMode_AutoReloadContinuous = 2u, /*!< auto reload the count for the next xfer, and always run. */
} DMA_ReloadMode_Type;
/*!
* @brief Incremental mode of peripherals and memories.
*/
typedef enum
{
DMA_AddrIncMode_StayAfterXfer = 0u, /*!< Peripheral access address accumulation. */
DMA_AddrIncMode_IncAfterXfer = 1u, /*!< Memory access address accumulation. */
} DMA_AddrIncMode_Type;
/*!
* @brief Define the enum type of DMA xfer width type.
*/
typedef enum
{
DMA_XferWidth_8b = 0u, /*!< Xfer width 8 bits. */
DMA_XferWidth_16b = 1u, /*!< Xfer width 16 bits. */
DMA_XferWidth_32b = 2u, /*!< Xfer width 32 bits. */
} DMA_XferWidth_Type;
/*!
* @brief Configure DMA Priority.
*/
typedef enum
{
DMA_Priority_Low = 0u, /*!< Low Priority. */
DMA_Priority_Middle = 1u, /*!< Middle Priority. */
DMA_Priority_High = 2u, /*!< High Priority. */
DMA_Priority_Highest = 3u, /*!< Highest Priority. */
} DMA_Priority_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref DMA_InitChannel() to initialize the DMA module.
*/
typedef struct
{
DMA_XferMode_Type XferMode; /*!< Specify whether the Receive or Transmit mode is enabled or not. */
DMA_ReloadMode_Type ReloadMode; /*!< Specify whether to automatically reload the next transfer count when the count is exhausted. */
DMA_AddrIncMode_Type PeriphAddrIncMode; /*!< Specify peripheral Address Inc Mode. */
DMA_AddrIncMode_Type MemAddrIncMode; /*!< Specify Memory Address Inc Mode. */
DMA_XferWidth_Type XferWidth; /*!< Specify the transmission data width. */
DMA_Priority_Type Priority; /*!< Specify priority mode. */
uint32_t XferCount; /*!< Specify CircularMode's count. */
uint32_t MemAddr; /*!< Specify Memory Address. */
uint32_t PeriphAddr; /*!< Specify Periph Address. */
} DMA_Channel_Init_Type;
/*!
* @brief Initialize the DMA module.
*
* @param DMAx DMA instance.
* @param channel Channel corresponding to DMA controller.
* @param init Pointer to the initialization structure. See to @ref DMA_Channel_Init_Type.
* @return None.
*/
uint32_t DMA_InitChannel(DMA_Type * DMAx, uint32_t channel, DMA_Channel_Init_Type * init);
/*!
* @brief enable the DMA channel interrupts of the DMA module.
*
* @param DMAx DMA instance.
* @param channel Channel corresponding to DMA controller.
* @param interrupts Interrupt code masks. See to @ref DMA_CHANNEL_INT.
* @param enable 'true' to enable the DMA channel interrupts, 'false' to disable the DMA channel interrupts.
* @return None.
*/
void DMA_EnableChannelInterrupts(DMA_Type * DMAx, uint32_t channel, uint32_t interrupts, bool enable);
/*!
* @brief Get the channel interrupts status flags of the DMA module.
*
* @param DMAx DMA instance.
* @param channel Channel corresponding to DMA controller in DMA. See to @ref DMA_CHANNEL_INT.
* @return Interrupt status flags.
*/
uint32_t DMA_GetChannelInterruptStatus(DMA_Type * DMAx, uint32_t channel);
/*!
* @brief Clear the channel interrupts status flags of the DMA module.
*
* @param DMAx DMA instance.
* @param channel Channel corresponding to DMA controller. See to @ref DMA_CHANNEL_INT.
* @param interrupts Interrupt code masks.
* @return None.
*/
void DMA_ClearChannelInterruptStatus(DMA_Type * DMAx, uint32_t channel, uint32_t interrupts);
/*!
* @brief Enable the channel of the DMA module.
*
* @param DMAx DMA instance.
* @param channel Channel corresponding to DMA controller. See to @ref DMA_CHANNEL_INT.
* @param enable 'true' to enable the DMA controller sends a reply signal to the peripheral, 'false' to disable the DMA controller sends a reply signal to the peripheral.
* @return None.
*/
void DMA_EnableChannel(DMA_Type * DMAx, uint32_t channel, bool enable);
/*!
*@}
*/
#endif /* __HAL_DMA_H__ */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_DMA_REQUESET_H__
#define __HAL_DMA_REQUESET_H__
#if 0
#define DMA_REQ_GET_DMA_INSTANCE(code) (uint32_t)((code) >> 8u)
#define DMA_REQ_GET_DMA_CHANNEL(code) (uint32_t)((code) & 0xFF)
#define DMA_REQ_DMA_INSTANCE(dmax) (uint32_t)((dmax) << 8u)
#define DMA_REQ_DMA_CHANNEL(channel) (uint32_t)((channel) & 0xFF)
#define DMA_REQ_DMA1_ADC1 0u
#define DMA_REQ_DMA1_UART6_RX 0u
#define DMA_REQ_DMA1_TIM2_CC3 0u
#define DMA_REQ_DMA1_TIM4_CC1 0u
#define DMA_REQ_DMA1_ADC2 1u
#define DMA_REQ_DMA1_SPI1_RX 1u
#define DMA_REQ_DMA1_UART3_TX 1u
#define DMA_REQ_DMA1_TIM1_CC1 1u
#define DMA_REQ_DMA1_TIM2_UP 1u
#define DMA_REQ_DMA1_TIM3_CC3 1u
#define DMA_REQ_DMA1_SPI1_TX 2u
#define DMA_REQ_DMA1_UART3_RX 2u
#define DMA_REQ_DMA1_TIM1_CC2 2u
#define DMA_REQ_DMA1_TIM3_CC4 2u
#define DMA_REQ_DMA1_TIM2_UP 2u
#define DMA_REQ_DMA1_SPI2_RX 3u
#define DMA_REQ_DMA1_UART1_TX 3u
#define DMA_REQ_DMA1_I2C2_TX 3u
#define DMA_REQ_DMA1_TIM1_CC4 3u
#define DMA_REQ_DMA1_TIM1_TRIG 3u
#define DMA_REQ_DMA1_TIM1_COM 3u
#define DMA_REQ_DMA1_TIM4_CC2 3u
#define DMA_REQ_DMA1_SPI2_TX 4u
#define DMA_REQ_DMA1_UART1_RX 4u
#define DMA_REQ_DMA1_I2C2_RX 4u
#define DMA_REQ_DMA1_TIM1_UP 4u
#define DMA_REQ_DMA1_TIM2_CC1 4u
#define DMA_REQ_DMA1_TIM4_CC3 4u
#define DMA_REQ_DMA1_UART2_RX 5u
#define DMA_REQ_DMA1_I2C1_TX 5u
#define DMA_REQ_DMA1_TIM1_CC3 5u
#define DMA_REQ_DMA1_TIM3_CC1 5u
#define DMA_REQ_DMA1_TIM3_TRIG 5u
#define DMA_REQ_DMA1_UART2_TX 6u
#define DMA_REQ_DMA1_I2C1_RX 6u
#define DMA_REQ_DMA1_TIM2_CC2 6u
#define DMA_REQ_DMA1_TIM2_CC4 6u
#define DMA_REQ_DMA1_TIM4_UP 6u
#define DMA_REQ_DMA2_SPI3_RX 0u
#define DMA_REQ_DMA2_UART5_RX 0u
#define DMA_REQ_DMA2_UART7_RX 0u
#define DMA_REQ_DMA2_TIM5_CC4 0u
#define DMA_REQ_DMA2_TIM5_TRIG 0u
#define DMA_REQ_DMA2_TIM8_CC3 0u
#define DMA_REQ_DMA2_TIM8_UP 0u
#define DMA_REQ_DMA2_SPI3_TX 1u
#define DMA_REQ_DMA2_UART5_TX 1u
#define DMA_REQ_DMA2_UART7_TX 1u
#define DMA_REQ_DMA2_TIM5_CC3 1u
#define DMA_REQ_DMA2_TIM5_UP 1u
#define DMA_REQ_DMA2_TIM8_CC4 1u
#define DMA_REQ_DMA2_TIM8_TRIG 1u
#define DMA_REQ_DMA2_TIM8_COM 1u
#define DMA_REQ_DMA2_UART4_RX 2u
#define DMA_REQ_DMA2_UART8_RX 2u
#define DMA_REQ_DMA2_TIM6_UP 2u
#define DMA_REQ_DMA2_DAC_CH1 2u
#define DMA_REQ_DMA2_TIM8_CC1 2u
#define DMA_REQ_DMA2_UART6_TX 3u
#define DMA_REQ_DMA2_SDIO 3u
#define DMA_REQ_DMA2_TIM5_CC2 3u
#define DMA_REQ_DMA2_TIM6_UP 3u
#define DMA_REQ_DMA2_DAC_CH2 3u
#define DMA_REQ_DMA2_ADC3 4u
#define DMA_REQ_DMA2_UART4_TX 4u
#define DMA_REQ_DMA2_UART8_TX 4u
#define DMA_REQ_DMA2_TIM5_CC1 4u
#define DMA_REQ_DMA2_TIM8_CC2 4u
#endif
/* ADC. */
#define DMA_REQ_DMA1_ADC1 0u
#define DMA_REQ_DMA1_ADC2 1u
#define DMA_REQ_DMA2_ADC3 4u
/* DAC. */
#define DMA_REQ_DMA2_DAC_CH1 2u
#define DMA_REQ_DMA2_DAC_CH2 3u
/* UART. */
#define DMA_REQ_DMA1_UART1_TX 3u
#define DMA_REQ_DMA1_UART1_RX 4u
#define DMA_REQ_DMA1_UART2_RX 5u
#define DMA_REQ_DMA1_UART2_TX 6u
#define DMA_REQ_DMA1_UART3_RX 2u
#define DMA_REQ_DMA1_UART3_TX 1u
#define DMA_REQ_DMA2_UART4_RX 2u
#define DMA_REQ_DMA2_UART4_TX 4u
#define DMA_REQ_DMA2_UART5_RX 0u
#define DMA_REQ_DMA2_UART5_TX 1u
#define DMA_REQ_DMA1_UART6_RX 0u
#define DMA_REQ_DMA2_UART6_TX 3u
#define DMA_REQ_DMA2_UART7_RX 0u
#define DMA_REQ_DMA2_UART7_TX 1u
#define DMA_REQ_DMA2_UART8_RX 2u
#define DMA_REQ_DMA2_UART8_TX 4u
/* SPI. */
#define DMA_REQ_DMA1_SPI1_RX 1u
#define DMA_REQ_DMA1_SPI1_TX 2u
#define DMA_REQ_DMA1_SPI2_RX 3u
#define DMA_REQ_DMA1_SPI2_TX 4u
#define DMA_REQ_DMA2_SPI3_RX 0u
#define DMA_REQ_DMA2_SPI3_TX 1u
/* I2C. */
#define DMA_REQ_DMA1_I2C1_RX 6u
#define DMA_REQ_DMA1_I2C1_TX 5u
#define DMA_REQ_DMA1_I2C2_RX 4u
#define DMA_REQ_DMA1_I2C2_TX 3u
/* TIM1. */
#define DMA_REQ_DMA1_TIM1_CC1 1u
#define DMA_REQ_DMA1_TIM1_CC2 2u
#define DMA_REQ_DMA1_TIM1_CC3 5u
#define DMA_REQ_DMA1_TIM1_CC4 3u
#define DMA_REQ_DMA1_TIM1_TRIG 3u
#define DMA_REQ_DMA1_TIM1_COM 3u
#define DMA_REQ_DMA1_TIM1_UP 4u
/* TIM2. */
#define DMA_REQ_DMA1_TIM2_CC1 4u
#define DMA_REQ_DMA1_TIM2_CC2 6u
#define DMA_REQ_DMA1_TIM2_CC3 0u
#define DMA_REQ_DMA1_TIM2_CC4 6u
#define DMA_REQ_DMA1_TIM2_UP 1u
/* TIM3. */
#define DMA_REQ_DMA1_TIM3_CC1 5u
#define DMA_REQ_DMA1_TIM3_CC3 1u
#define DMA_REQ_DMA1_TIM3_CC4 2u
#define DMA_REQ_DMA1_TIM3_UP 2u
#define DMA_REQ_DMA1_TIM3_TRIG 5u
/* TIM4. */
#define DMA_REQ_DMA1_TIM4_CC1 0u
#define DMA_REQ_DMA1_TIM4_CC2 3u
#define DMA_REQ_DMA1_TIM4_CC3 4u
#define DMA_REQ_DMA1_TIM4_UP 6u
/* TIM5. */
#define DMA_REQ_DMA2_TIM5_CC1 4u
#define DMA_REQ_DMA2_TIM5_CC2 3u
#define DMA_REQ_DMA2_TIM5_CC3 1u
#define DMA_REQ_DMA2_TIM5_CC4 0u
#define DMA_REQ_DMA2_TIM5_TRIG 0u
#define DMA_REQ_DMA2_TIM5_UP 1u
/* TIM6. */
#define DMA_REQ_DMA2_TIM6_UP 2u
/* TIM7. */
#define DMA_REQ_DMA2_TIM7_UP 3u /* DMA_REQ_DMA2_TIM7_UP */
/* TIM8. */
#define DMA_REQ_DMA2_TIM8_CC1 2u
#define DMA_REQ_DMA2_TIM8_CC2 4u
#define DMA_REQ_DMA2_TIM8_CC3 0u
#define DMA_REQ_DMA2_TIM8_CC4 1u
#define DMA_REQ_DMA2_TIM8_UP 0u
#define DMA_REQ_DMA2_TIM8_COM 1u
#define DMA_REQ_DMA2_TIM8_TRIG 1u
/* SDIO. */
#define DMA_REQ_DMA2_SDIO 3u
#endif /* __HAL_DMA_REQUESET_H__ */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_EXTI_H__
#define __HAL_EXTI_H__
#include "hal_common.h"
/*!
* @addtogroup EXTI
* @{
*/
/*!
* @brief EXTI driver version number.
*/
#define EXTI_DRIVER_VERSION 0u /*!< exti_0. */
/*!
* @addtogroup EXTI_LINE
* @{
*/
#define EXTI_LINE_0 (1u << 0u) /*!<External Interrupt Line 0 switcher. */
#define EXTI_LINE_1 (1u << 1u) /*!<External Interrupt Line 1 switcher. */
#define EXTI_LINE_2 (1u << 2u) /*!<External Interrupt Line 2 switcher. */
#define EXTI_LINE_3 (1u << 3u) /*!<External Interrupt Line 3 switcher. */
#define EXTI_LINE_4 (1u << 4u) /*!<External Interrupt Line 4 switcher. */
#define EXTI_LINE_5 (1u << 5u) /*!<External Interrupt Line 5 switcher. */
#define EXTI_LINE_6 (1u << 6u) /*!<External Interrupt Line 6 switcher. */
#define EXTI_LINE_7 (1u << 7u) /*!<External Interrupt Line 7 switcher. */
#define EXTI_LINE_8 (1u << 8u) /*!<External Interrupt Line 8 switcher. */
#define EXTI_LINE_9 (1u << 9u) /*!<External Interrupt Line 9 switcher. */
#define EXTI_LINE_10 (1u << 10u) /*!<External Interrupt Line 10 switcher. */
#define EXTI_LINE_11 (1u << 11u) /*!<External Interrupt Line 11 switcher. */
#define EXTI_LINE_12 (1u << 12u) /*!<External Interrupt Line 12 switcher. */
#define EXTI_LINE_13 (1u << 13u) /*!<External Interrupt Line 13 switcher. */
#define EXTI_LINE_14 (1u << 14u) /*!<External Interrupt Line 14 switcher. */
#define EXTI_LINE_15 (1u << 15u) /*!<External Interrupt Line 15 switcher. */
#define EXTI_LINE_16 (1u << 16u) /*!<External Interrupt Line 16 switcher. */
#define EXTI_LINE_17 (1u << 17u) /*!<External Interrupt Line 17 switcher. */
#define EXTI_LINE_18 (1u << 18u) /*!<External Interrupt Line 18 switcher. */
#define EXTI_LINE_19 (1u << 19u) /*!<External Interrupt Line 19 switcher. */
#define EXTI_LINE_20 (1u << 20u) /*!<External Interrupt Line 20 switcher. */
#define EXTI_LINE_21 (1u << 21u) /*!<External Interrupt Line 21 switcher. */
#define EXTI_LINE_22 (1u << 22u) /*!<External Interrupt Line 22 switcher. */
#define EXTI_LINE_23 (1u << 23u) /*!<External Interrupt Line 23 switcher. */
#define EXTI_LINE_24 (1u << 24u) /*!<External Interrupt Line 24 switcher. */
/*!
* @}
*/
/*!
* @brief EXTI trigger input detection edge alt.
*/
typedef enum
{
EXTI_TriggerIn_Disable = 0u, /*!< Disable the trigger input interrupt. */
EXTI_TriggerIn_RisingEdge = 1u, /*!< Trigger input rising edge interrupt.*/
EXTI_TriggerIn_FallingEdge = 2u, /*!< Trigger input falling edge interrupt.*/
EXTI_TriggerIn_BothEdges = 3u, /*!< Both trigger input rising and falling edge interrupt.*/
} EXTI_TriggerIn_Type;
/*!
* @brief Enable the external interrupt line's interrupts.
*
* @param EXTIx EXTI instance.
* @param lines External interrupt lines. See to @ref EXTI_LINE.
* @param enable 'true' to unmask the external interrupt lines' interrupt, 'false' to mask the external interrupt lines' interrupt.
* @return None.
*/
void EXTI_EnableLineInterrupt(EXTI_Type * EXTIx, uint32_t lines, bool enable);
/*!
* @brief Enable the external interrupt line's events.
*
* @param EXTIx EXTI instance.
* @param lines External interrupt lines. See to @ref EXTI_LINE.
* @param enable 'true' to unmask the external interrupt lines' event, 'false' to disable the external interrupt lines' event.
* @return None.
*/
void EXTI_EnableLineEvent(EXTI_Type * EXTIx, uint32_t lines, bool enable);
/*!
* @brief Set the line input for triggering interrupts.
*
* @param EXTIx EXTI instance.
* @param lines External interrupt lines. See to @ref EXTI_LINE.
* @param trgin The active signal for triggering interrupts. See to @ref EXTI_TriggerIn_Type;
* @return None.
*/
void EXTI_SetTriggerIn(EXTI_Type * EXTIx, uint32_t lines, EXTI_TriggerIn_Type trgin);
/*!
* @brief Do software trigger to trigger interrupts of the indicated lines.
*
* @param EXTIx EXTI instance.
* @param lines External interrupt lines. See to @ref EXTI_LINE.
* @return None.
*/
void EXTI_DoSwTrigger(EXTI_Type * EXTIx, uint32_t lines);
/*!
* @brief Get the interrupt status of the indicated EXTI module.
*
* @param EXTIx EXTI instance.
* @return Line status flags. See to @ref EXTI_LINE.
*/
uint32_t EXTI_GetLineStatus(EXTI_Type * EXTIx);
/*!
* @brief Clear the interrupt status of the indicated EXTI module.
*
* @param EXTIx EXTI instance.
* @param lines Interrupt status flags. See to @ref EXTI_LINE.
* @return None.
*/
void EXTI_ClearLineStatus(EXTI_Type * EXTIx, uint32_t lines);
/*!
* @}
*/
#endif /* __HAL_EXTI_H__ */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_FSMC_H__
#define __HAL_FSMC_H__
#include "hal_common.h"
/*
* There are still some configurations in SYSCFG_CFGR1:
* - switch between 8080 mode and NOR FLASH mode.
* - disable the reuse of data pins as address pins.
* - enable the fsmc sync.
*/
/*!
* @addtogroup FSMC
* @{
*/
/*!
* @brief FSMC driver version number.
*/
#define FSMC_DRIVER_VERSION 0u /*!< fsmc_0. */
/*!
* @brief FSMC memory type.
*/
typedef enum
{
FSMC_MemType_SRAM = 1u, /*!< Mem type: SRAM. */
FSMC_MemType_NorFlash = 2u, /*!< Mem type: NorFlash. */
FSMC_MemType_PSRAM = 3u, /*!< Mem type: PSRAM. */
} FSMC_MemType_Type;
/*!
* @brief FSMC memory size type.
*/
typedef enum
{
FSMC_MemSize_NoDevice = 0u, /*!< Mem Size type: NoDevice. */
FSMC_MemSize_64KB = 1u, /*!< Mem Size type: 64KB. */
FSMC_MemSize_128KB = 2u, /*!< Mem Size type: 128KB. */
FSMC_MemSize_256KB = 3u, /*!< Mem Size type: 256KB. */
FSMC_MemSize_512KB = 4u, /*!< Mem Size type: 512KB. */
FSMC_MemSize_1MB = 5u, /*!< Mem Size type: 1MB. */
FSMC_MemSize_2MB = 6u, /*!< Mem Size type: 2MB. */
FSMC_MemSize_4MB = 7u, /*!< Mem Size type: 4MB. */
FSMC_MemSize_8MB = 8u, /*!< Mem Size type: 8MB. */
FSMC_MemSize_16MB = 9u, /*!< Mem Size type: 16MB. */
FSMC_MemSize_32MB = 10u, /*!< Mem Size type: 32MB. */
FSMC_MemSize_64MB = 11u, /*!< Mem Size type: 64MB. */
FSMC_MemSize_128MB = 12u, /*!< Mem Size type: 128MB. */
FSMC_MemSize_256MB = 13u, /*!< Mem Size type: 256MB. */
FSMC_MemSize_512MB = 14u, /*!< Mem Size type: 512MB. */
FSMC_MemSize_1GB = 15u, /*!< Mem Size type: 1GB. */
FSMC_MemSize_2GB = 16u, /*!< Mem Size type: 2GB. */
FSMC_MemSize_4GB = 17u, /*!< Mem Size type: 4GB. */
} FSMC_MemSize_Type;
/*!
* @brief FSMC ready signal type.
*/
typedef enum
{
FSMC_ReadySignal_Internal = 0u, /*!< The ready signal is inside the FSMC, do not need the external ready signal. */
FSMC_ReadySignal_External = 1u, /*!< The ready signal is from external device. */
} FSMC_ReadySignal_Type;
/*!
* @brief FSMC bus width type.
*/
typedef enum
{
FSMC_BusWidth_8b = 4u, /*!< Bus width: 8bit. */
FSMC_BusWidth_16b = 0u, /*!< Bus width: 16bit. */
FSMC_BusWidth_32b = 1u, /*!< Bus width: 32bit. */
} FSMC_BusWidth_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref FSMC_Init() to initialize the FSMC module.
*/
typedef struct
{
FSMC_MemType_Type MemType; /*!< Specify the memory type. */
FSMC_MemSize_Type MemSize; /*!< Specify the memory size. */
} FSMC_Init_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref FSMC_SetConf() to initialize the FSMC config.
*/
typedef struct
{
uint32_t ReadPeriod; /*!< the cycles for 'reading data', NOE available period. */
uint32_t AddrSetTime; /*!< the cycles for 'setup' when writing. */
uint32_t WriteHoldTime; /*!< the cycles between the master write action and slave capture done. */
uint32_t WritePeriod; /*!< the cycles for 'keep data' in writing operation, NWE available period. */
FSMC_ReadySignal_Type ReadySignal; /*!< select if capture the external ready signal. */
uint32_t SMReadPipe; /*!< the cycles between the read action and release the bus.*/
FSMC_BusWidth_Type BusWidth; /*!< Specify the bus width. */
} FSMC_Conf_Type;
/*!
* @brief Initialize the FSMC module.
*
* @param FSMCx FSMC instance.
* @param init Pointer to the initialization structure. See to @ref FSMC_Init_Type.
* @return None.
*/
void FSMC_Init(FSMC_Type * FSMCx, FSMC_Init_Type * init);
/*!
* @brief Set the FSMC config.
*
* @param FSMCx FSMC instance.
* @param index Config index.
* @param conf Pointer to the config structure. See to @ref FSMC_Conf_Type.
* @return None.
*/
void FSMC_SetConf(FSMC_Type * FSMCx, uint32_t index, FSMC_Conf_Type * conf);
/*!
* @brief Enable the FSMC config.
*
* Only last enabled config is available.
*
* @param FSMCx FSMC instance.
* @param index Config index.
* @return None.
*/
void FSMC_EnableConf(FSMC_Type * FSMCx, uint32_t index);
/*!
* @brief Get the Xfer data reg addr.
*
* @param FSMCx FSMC instance.
* @param bankn FSMC bank number.
* @param offset offset of data in FSMC bank.
* @return The addr value of Xfer data reg.
*/
uint32_t FSMC_GetXferDataRegAddr(FSMC_Type *FSMCx, uint32_t bankn, uint32_t offset);
/*!
* @brief Put the 32bit data by FSMC module.
*
* @param FSMCx FSMC instance.
* @param bankn FSMC bank number.
* @param offset offset of data in FSMC bank.
* @param data Data value to be send through the transmiter.
* @return None.
*/
void FSMC_PutData32(FSMC_Type * FSMCx, uint32_t bankn, uint32_t offset, uint32_t data);
/*!
* @brief Get the 32bit data by FSMC module.
*
* @param FSMCx FSMC instance.
* @param bankn FSMC bank number.
* @param offset offset of data in FSMC bank.
* @return The data value received from FSMC.
*/
uint32_t FSMC_GetData32(FSMC_Type * FSMCx, uint32_t bankn, uint32_t offset);
/*!
* @brief Put the 16bit data by FSMC module.
*
* @param FSMCx FSMC instance.
* @param bankn FSMC bank number.
* @param offset offset of data in FSMC bank.
* @param data Data value to be send through the transmiter.
* @return None.
*/
void FSMC_PutData16(FSMC_Type * FSMCx, uint32_t bankn, uint32_t offset, uint16_t data);
/*!
* @brief Get the 16bit data by FSMC module.
*
* @param FSMCx FSMC instance.
* @param bankn FSMC bank number.
* @param offset offset of data in FSMC bank.
* @return The data value received from FSMC.
*/
uint16_t FSMC_GetData16(FSMC_Type * FSMCx, uint32_t bankn, uint32_t offset);
/*!
* @brief Put the 8bit data by FSMC module.
*
* @param FSMCx FSMC instance.
* @param bankn FSMC bank number.
* @param offset offset of data in FSMC bank.
* @param data Data value to be send through the transmiter.
* @return None.
*/
void FSMC_PutData8(FSMC_Type * FSMCx, uint32_t bankn, uint32_t offset, uint8_t data);
/*!
* @brief Get the 8bit data by FSMC module.
*
* @param FSMCx FSMC instance.
* @param bankn FSMC bank number.
* @param offset offset of data in FSMC bank.
* @return The data value received from FSMC.
*/
uint8_t FSMC_GetData8(FSMC_Type * FSMCx, uint32_t bankn, uint32_t offset);
/*!
*@}
*/
#endif /* __HAL_FSMC_H__ */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_GPIO_H__
#define __HAL_GPIO_H__
#include "hal_common.h"
/*!
* @addtogroup GPIO
* @{
*/
/*!
* @addtogroup GPIO_PIN
* @brief GPIO pin mask codes.
* @{
*/
#define GPIO_PIN_0 (0x0001u) /*!< Pin 0 selected. */
#define GPIO_PIN_1 (0x0002u) /*!< Pin 1 selected. */
#define GPIO_PIN_2 (0x0004u) /*!< Pin 2 selected. */
#define GPIO_PIN_3 (0x0008u) /*!< Pin 3 selected. */
#define GPIO_PIN_4 (0x0010u) /*!< Pin 4 selected. */
#define GPIO_PIN_5 (0x0020u) /*!< Pin 5 selected. */
#define GPIO_PIN_6 (0x0040u) /*!< Pin 6 selected. */
#define GPIO_PIN_7 (0x0080u) /*!< Pin 7 selected. */
#define GPIO_PIN_8 (0x0100u) /*!< Pin 8 selected. */
#define GPIO_PIN_9 (0x0200u) /*!< Pin 9 selected. */
#define GPIO_PIN_10 (0x0400u) /*!< Pin 10 selected. */
#define GPIO_PIN_11 (0x0800u) /*!< Pin 11 selected. */
#define GPIO_PIN_12 (0x1000u) /*!< Pin 12 selected. */
#define GPIO_PIN_13 (0x2000u) /*!< Pin 13 selected. */
#define GPIO_PIN_14 (0x4000u) /*!< Pin 14 selected. */
#define GPIO_PIN_15 (0x8000u) /*!< Pin 15 selected. */
#define GPIO_PINS_ALL (0xFFFFu) /*!< All pins selected. */
/*!
* @}
*/
/*!
* @addtogroup GPIO_AF
* @brief GPIO pin alternative function.
* @{
*/
#define GPIO_AF_0 (0x00u) /*!< Alternative function 0. */
#define GPIO_AF_1 (0x01u) /*!< Alternative function 1. */
#define GPIO_AF_2 (0x02u) /*!< Alternative function 2. */
#define GPIO_AF_3 (0x03u) /*!< Alternative function 3. */
#define GPIO_AF_4 (0x04u) /*!< Alternative function 4. */
#define GPIO_AF_5 (0x05u) /*!< Alternative function 5. */
#define GPIO_AF_6 (0x06u) /*!< Alternative function 6. */
#define GPIO_AF_7 (0x07u) /*!< Alternative function 7. */
#define GPIO_AF_8 (0x08u) /*!< Alternative function 8. */
#define GPIO_AF_9 (0x09u) /*!< Alternative function 9. */
#define GPIO_AF_10 (0x0Au) /*!< Alternative function 10. */
#define GPIO_AF_11 (0x0Bu) /*!< Alternative function 11. */
#define GPIO_AF_12 (0x0Cu) /*!< Alternative function 12. */
#define GPIO_AF_13 (0x0Du) /*!< Alternative function 13. */
#define GPIO_AF_14 (0x0Eu) /*!< Alternative function 14. */
#define GPIO_AF_15 (0x0Fu) /*!< Alternative function 15. */
/*!
* @}
*/
/*!
* @brief GPIO maximum speed type.
*/
typedef enum
{
GPIO_Speed_50MHz = 1u, /*!< Maximum speed is 50MHz. */
GPIO_Speed_20MHz = 2u, /*!< Maximum speed is 20MHz. */
GPIO_Speed_10MHz = 3u, /*!< Maximum speed is 10MHz. */
} GPIO_Speed_Type;
/*!
* @brief Port input / output mode.
*/
typedef enum
{
GPIO_PinMode_In_Analog = 0x00u, /*!< Analog input. */
GPIO_PinMode_In_Floating = 0x04u, /*!< Floating input. */
GPIO_PinMode_In_PullDown = 0x28u, /*!< Pull down input. */
GPIO_PinMode_In_PullUp = 0x48u, /*!< Pull up input. */
GPIO_PinMode_Out_OpenDrain = 0x14u, /*!< Universal open drain output. */
GPIO_PinMode_Out_PushPull = 0x10u, /*!< Universal push-pull output. */
GPIO_PinMode_AF_OpenDrain = 0x1Cu, /*!< Multiplex open drain output. */
GPIO_PinMode_AF_PushPull = 0x18u, /*!< Multiplexed push-pull output. */
} GPIO_PinMode_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref GPIO_Init() to initialize the GPIO module.
*/
typedef struct
{
uint16_t Pins; /*!< GPIO operating pins. */
GPIO_Speed_Type Speed; /*!< GPIO pin speed mode. */
GPIO_PinMode_Type PinMode; /*!< GPIO pin input / output functional mode. */
} GPIO_Init_Type;
/*!
* @brief Initialize the GPIO module.
*
* @param GPIOx GPIO instance.
* @param init Pointer to the initialization structure. See to @ref GPIO_Init_Type.
* @return None.
*/
void GPIO_Init(GPIO_Type * GPIOx, GPIO_Init_Type * init);
/*!
* @brief Set the specified data port bit.
*
* @param GPIOx GPIO instance.
* @param pins GPIO operating pins. See to @ref GPIO_PIN.
* @return None.
*/
void GPIO_SetBits(GPIO_Type * GPIOx, uint16_t pins);
/*!
* @brief Clear the specified data port bit.
*
* @param GPIOx GPIO instance.
* @param pins GPIO operating pins. See to @ref GPIO_PIN.
* @return None.
*/
void GPIO_ClearBits(GPIO_Type * GPIOx, uint16_t pins);
/*!
* @brief Writes 0 or 1 to the specified bit.
*
* @param GPIOx GPIO instance.
* @param pins GPIO operating pins. See to @ref GPIO_PIN.
* @param val Decide whether to set or clear.
* @return None.
*/
void GPIO_WriteBit(GPIO_Type * GPIOx, uint16_t pins, uint16_t val);
/*!
* @brief Write 0 or 1 for multiple I/O ports.
*
* @param GPIOx GPIO instance.
* @param val Decide whether to set or clear.
* @return None.
*/
void GPIO_WriteBits(GPIO_Type * GPIOx, uint16_t val);
/*!
* @brief Keep the set I/O configuration can not be changed.
*
* @param GPIOx GPIO instance.
* @param pins GPIO operating pins. See to @ref GPIO_PIN.
* @param enable_lock enable 'true' to enable the lock, 'false' to disable the lock.
* @return None.
*/
void GPIO_PinLock(GPIO_Type * GPIOx, uint16_t pins, bool enable_lock);
/*!
* @brief Lock the corresponding bit of the select port configuration register.
*
* @param GPIOx GPIO instance.
* @param pins GPIO operating pins. See to @ref GPIO_PIN.
* @return None.
*/
void GPIO_PinLockConf(GPIO_Type * GPIOx, uint16_t pins);
/*!
* @brief Read the value once entered before by the specified pin.
*
* @param GPIOx GPIO instance.
* @param pins GPIO operating pins. See to @ref GPIO_PIN.
* @return Status of a pin's logic level, 0 for low level or 1 for high level.
*/
bool GPIO_ReadInDataBit(GPIO_Type * GPIOx, uint16_t pins);
/*!
* @brief Read the value previously output by the specified pin.
*
* @param GPIOx GPIO instance.
* @param pins GPIO operating pins. See to @ref GPIO_PIN.
* @return Status of a pin's logic level, 0 for low level or 1 for high level.
*/
bool GPIO_ReadOutDataBit(GPIO_Type * GPIOx, uint16_t pins);
/*!
* @brief Read the specified GPIO port input.
*
* @param GPIOx GPIO instance.
* @return A hexadecimal number.
*/
uint16_t GPIO_ReadInData(GPIO_Type * GPIOx);
/*!
* @brief Read the specified GPIO port output.
*
* @param GPIOx GPIO instance.
* @return A hexadecimal number.
*/
uint16_t GPIO_ReadOutData(GPIO_Type * GPIOx);
/*!
* @brief Pin alternate function configuration of GPIO.
*
* @param GPIOx GPIO instance.
* @param pins GPIO operating pins. See to @ref GPIO_PIN.
* @param alternate_function Reuse the unified I/O port, but the function is different.
* @return None.
*/
void GPIO_PinAFConf(GPIO_Type* GPIOx, uint16_t pins, uint8_t alternate_function);
/*!
* @}
*/
#endif /* __HAL_GPIO_H__ */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_I2C_H__
#define __HAL_I2C_H__
#include "hal_common.h"
/*!
* @addtogroup I2C
* @{
*/
/*!
* @addtogroup I2C_INT
* @{
*/
#define I2C_INT_RX_UNDER I2C_RAWISR_RXUNDER_MASK /*!< Assert when attempting to read the RX fifo, even it is empty. */
#define I2C_INT_RX_NOTEMPTY I2C_RAWISR_RXFULL_MASK /*!< Assert when the data in RX fifo is available. */
#define I2C_INT_TX_EMPTY I2C_RAWISR_TXEMPTY_MASK /*!< When working as master, this bit asserts if the data count is under or equal to the tx threshold. */
#define I2C_INT_TX_ABORT I2C_RAWISR_TXABRT_MASK /*!< Assert when transmit abort. */
#define I2C_INT_ACTIVE I2C_RAWISR_ACTIV_MASK /*!< Assert when the i2c bus is active, while the clocks are transfered. */
#define I2C_INT_STOP I2C_RAWISR_STOP_MASK /*!< Assert when detecting a STOP on the i2c bus, no mater working as master or slave. */
#define I2C_INT_START I2C_RAWISR_START_MASK /*!< Assert when detecting a START on the i2c bus, no matter working as master or slave. */
/*!
* @}
*/
/*!
* @addtogroup I2C_STATUS
* @{
*/
#define I2C_STATUS_ACTIVE I2C_SR_ACTIV_MASK /*!< I2C bus is active. */
#define I2C_STATUS_TX_EMPTY I2C_SR_TFE_MASK /*!< I2C tx fifo is empty. */
#define I2C_STATUS_RX_NOTEMPTY I2C_SR_RFNE_MASK /*!< I2C rx fifo is not empty. */
/*!
* @}
*/
/*!
* @brief I2C baudrate type.
*/
typedef enum
{
I2C_BaudRate_50K = 50000u, /*!< Specify operate at the speed of 50K. */
I2C_BaudRate_100K = 100000u, /*!< Specify operate at the speed of 100K. */
} I2C_BaudRate_Type;
/*!
* @brief I2C transmission direction type.
*/
typedef enum
{
I2C_Direction_Tx = 0u, /*!< Specify I2C transmission direction as tx. */
I2C_Direction_Rx = 1u, /*!< Specify I2C transmission direction as rx. */
} I2C_Direction_Type;
/*!
* @brief Define the callback function called when the I2C master transfer is abort.
*/
typedef void (*I2C_Callback_1_Type)(void *param);
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref I2C_MasterXfer() to transfer the I2C address and data.
*/
typedef struct
{
uint16_t TargetAddr; /*!< Specify I2C target device address. */
I2C_Direction_Type Direction; /*!< specify transmission direction. */
uint8_t *TxBuf; /*!< Specify the tx buffer array. */
uint32_t TxIdx; /*!< Specify the number of data currently sent. */
uint8_t TxLen; /*!< Specify the tx data len. */
uint8_t *RxBuf; /*!< Specify the rx buffer array. */
uint32_t RxIdx; /*!< Specify the number of data currently receive. */
uint8_t RxLen; /*!< Specify the rx data len. */
uint32_t WaitTimes; /*!< Specify the time limit for wait to the flag to be generated. If the required flag is not generated after this time, considered as timeout. */
I2C_Callback_1_Type DoneCallback; /*!< Callback function, called when the i2c transmit is done. */
I2C_Callback_1_Type AbortCallback; /*!< Callback function, called when the i2c transmit is abort. */
} I2C_MasterXfer_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref I2C_InitMaster() to initialize the I2C master module.
*/
typedef struct
{
uint32_t ClockFreqHz; /*!< Specify bus clock frequency. */
I2C_BaudRate_Type BaudRate; /*!< Specify the I2C communication baud rate. */
} I2C_Master_Init_Type;
/*!
* @brief Initialize the I2C master module.
*
* @param I2Cx I2C instance.
* @param init Pointer to the master initialization structure. See to @ref I2C_Master_Init_Type.
* @return The initialize succeed return true, the misconfiguration of speed or baud rate return false.
*/
bool I2C_InitMaster(I2C_Type * I2Cx, I2C_Master_Init_Type * init);
/*!
* @brief Enabel the I2C module.
*
* @param I2Cx I2C instance.
* @param enable 'true' to enable the module, 'false' to disable the module.
* @return None.
*/
void I2C_Enable(I2C_Type *I2Cx, bool enable);
/*!
* @brief Set the I2C target device address that matches the slave device.
*
* @param I2Cx I2C instance.
* @param addr I2C target device address.
* @return None.
*/
void I2C_SetTargetAddr(I2C_Type * I2Cx, uint8_t addr);
/*!
* @brief Get I2C target device address.
*
* @param I2Cx I2C instance.
* @return I2C target device addr.
*/
uint16_t I2C_GetTargetAddr(I2C_Type * I2Cx);
/*!
* @brief Put the data into transmiter buffer of the I2C module.
*
* @param I2Cx I2C instance.
* @param val Data value to be send through the transmiter.
* @return None.
*/
void I2C_PutData(I2C_Type * I2Cx, uint8_t val);
/*!
* @brief Control read-write bit to prepare for data acquisition.
*
* @param I2Cx I2C instance.
* @return None.
*/
void I2C_PrepareToGetData(I2C_Type * I2Cx);
/*!
* @brief Get the data from receiver buffer of the I2C module.
*
* @param I2Cx I2C instance.
* @return Data received by I2C bus.
*/
uint8_t I2C_GetData(I2C_Type * I2Cx);
/*!
* @brief Get the current status flags of the I2C module.
*
* @param I2Cx I2C instance.
* @return Status flags. See to @ref I2C_STATUS.
*/
uint32_t I2C_GetStatus(I2C_Type * I2Cx);
/*!
* @brief Prepare for the stop, when transfer finish.
*
* @param I2Cx I2C instance.
* @return None.
*/
void I2C_Stop(I2C_Type * I2Cx);
/*!
* @brief Enable interrupts of I2C module.
*
* @param I2Cx I2C instance.
* @param interrupts Interrupt code masks. See to @ref I2C_INT.
* @param enable 'true' to enable the indicated interrupts, 'false' to disable the indicated interrupts.
* @return None.
*/
void I2C_EnableInterrupts(I2C_Type * I2Cx, uint32_t interrupts, bool enable);
/*!
* @brief Read the current enabled interrupts the I2C module.
*
* @param I2Cx I2C instance.
* @return The mask codes enabled interrupts. See to @ref I2C_INT.
*/
uint32_t I2C_GetEnabledInterrupts(I2C_Type * I2Cx);
/*!
* @brief Get the I2C interrupt status flags of the I2C module.
*
* @param I2Cx I2C instance.
* @return Interrupt status flags. See to @ref I2C_INT.
*/
uint32_t I2C_GetInterruptStatus(I2C_Type * I2Cx);
/*!
* @brief Clear the I2C interrupt status flags of the I2C module.
*
* @param I2Cx I2C instance.
* @param interrupts The mask codes of the indicated interrupt flags to be cleared.
* @return None.
*/
void I2C_ClearInterruptStatus(I2C_Type * I2Cx, uint32_t interrupts);
/*!
* @brief I2C master interrupt transfer of the I2C module.
*
* @param I2Cx I2C instance.
* @param xfer Pointer to the I2C master transimt structure. See to @ref I2C_MasterXfer_Type.
* @return None.
*/
void I2C_MasterXfer(I2C_Type * I2Cx, I2C_MasterXfer_Type * xfer);
/*!
* @brief I2C master transfer interrupt handler.
*
* @param I2Cx I2C instance.
* @param xfer Pointer to the I2C master transimt structure. See to @ref I2C_MasterXfer_Type.
* @param interrupts Interrupt status flags. See to @ref I2C_INT.
* @return None.
*/
void I2C_MasterXferHandler(I2C_Type * I2Cx, I2C_MasterXfer_Type * xfer, uint32_t interrupts);
/*!
* @brief I2C master write polling.
*
* @param I2Cx I2C instance.
* @param xfer Pointer to the I2C master transimt structure. See to @ref I2C_MasterXfer_Type.
* @return 'true' to I2C write polling succeed, 'false' to I2C write polling failed.
*/
bool I2C_MasterWriteBlocking(I2C_Type * I2Cx, I2C_MasterXfer_Type * xfer);
/*!
* @brief I2C master read polling.
*
* @param I2Cx I2C instance.
* @param xfer Pointer to the I2C master transimt structure. See to @ref I2C_MasterXfer_Type.
* @return 'true' to I2C read polling succeed, 'false' to I2C read polling failed.
*/
bool I2C_MasterReadBlocking(I2C_Type * I2Cx, I2C_MasterXfer_Type * xfer);
/*!
*@}
*/
#endif /* __HAL_I2C_H__ */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_IWDG_H__
#define __HAL_IWDG_H__
#include "hal_common.h"
/*!
* @addtogroup IWDG
* @{
*/
/*!
* @brief IWDG driver version number.
*/
#define IWDG_DRIVER_VERSION 0u /*!< IWDG_0. */
/*!
* @brief IWDG key values
*/
#define IWDG_KEY_ENABLE 0xCCCC /*!< IWDG Peripheral Enable . */
#define IWDG_KEY_RELOAD 0xAAAA /*!< IWDG Reload Counter Enable. */
#define IWDG_KEY_UNLOCK 0x5555 /*!< IWDG KR Write Access Enable*/
/*!
* @addtogroup IWDG_STATUS
* @{
*/
#define IWDG_STATUS_RELOAD_UPDATE IWDG_SR_RVU_MASK /*!< Status flag when IWDG counter reload value update, can not be cleared. */
#define IWDG_STATUS_PRESCALER_UPDATE IWDG_SR_PVU_MASK /*!< Status flag when IWDG prescaler value update, can not be cleared. */
#define IWDG_STATUS_ALMOST_TIMEOUT IWDG_SR_IVU_MASK /*!< Status flag when IWDG almost timeout. */
/*!
* @}
*/
/*!
* @addtogroup IWDG_INT
* @{
*/
#define IWDG_INT_ALMOST_TIMEOUT IWDG_CR_IRQSEL_MASK /*!< IWDG Interrupt: Select IWDG interrupt method */
/*!
* @}
*/
/*!
* @brief IWDG prescaler type.
*
* Select the prescaler of time base as the IWDG counter clock.
*/
typedef enum
{
IWDG_Prescaler_4 = 0u, /*!< IWDG prescaler 4. */
IWDG_Prescaler_8 = 1u, /*!< IWDG prescaler 8. */
IWDG_Prescaler_16 = 2u, /*!< IWDG prescaler 16. */
IWDG_Prescaler_32 = 3u, /*!< IWDG prescaler 32. */
IWDG_Prescaler_64 = 4u, /*!< IWDG prescaler 64. */
IWDG_Prescaler_128 = 5u, /*!< IWDG prescaler 128. */
IWDG_Prescaler_256 = 6u, /*!< IWDG prescaler 256. */
} IWDG_Prescaler_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref IWDG_Init() to initialize the IWDG module.
*/
typedef struct
{
IWDG_Prescaler_Type Prescaler; /*!< Specify the IWDG counter time base division value. */
uint32_t Relaod; /*!< Specify the IWDG counter reload value. */
} IWDG_Init_Type;
/*!
* @brief Initialize the IWDG module.
*
* @param IWDGx IWDG instance.
* @param init Pointer to the initialization structure. See to @ref IWDG_Init_Type.
* @return None.
*/
void IWDG_Init(IWDG_Type * IWDGx, IWDG_Init_Type * init);
/*!
* @brief Start the IWDG counter.
*
* Once IWDG counter is started, it cannot be stopped unless reset MCU.
*
* @param IWDGx IWDG instance.
* @return None.
*/
void IWDG_Start(IWDG_Type * IWDGx);
/*!
* @brief Get the current status flags of the IWDG module.
*
* @param IWDGx IWDG instance.
* @return Status flags. See to @ref IWDG_STATUS.
*/
uint32_t IWDG_GetStatus(IWDG_Type * IWDGx);
/*!
* @brief Clear the status flags of the IWDG module.
*
* @param IWDGx IWDG instance.
* @param status Status flags. See to @ref IWDG_STATUS.
* @return None.
*/
void IWDG_ClearStatus(IWDG_Type * IWDGx, uint32_t status);
/*!
* @brief Do reload IWDG counter (i.e. "feed dog").
*
* @param IWDGx IWDG instance.
* @return None.
*/
void IWDG_DoReload(IWDG_Type * IWDGx);
/*!
* @brief Enable interrupts of the IWDG module.
*
* @param IWDGx IWDG instance.
* @param interrupts Interrupt code masks. See to @ref IWDG_INT.
* @param enable 'true' to enable the indicated interrupts, 'false' has no effect.
* @return None.
*/
void IWDG_EnableInterrupts(IWDG_Type * IWDGx, uint32_t interrupts, bool enable);
/*!
*@}
*/
#endif /* __HAL_IWDG_H__ */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_RCC_H__
#define __HAL_RCC_H__
#include "hal_common.h"
/*!
* @addtogroup RCC
* @{
*/
/*!
* @addtogroup RCC_AHB1_PERIPH
* @{
*/
#define RCC_AHB1_PERIPH_GPIOA (1u << 0u) /*!< AHB1 peripheral GPIOA clock 0 bit. */
#define RCC_AHB1_PERIPH_GPIOB (1u << 1u) /*!< AHB1 peripheral GPIOB clock 1 bit. */
#define RCC_AHB1_PERIPH_GPIOC (1u << 2u) /*!< AHB1 peripheral GPIOC clock 2 bit. */
#define RCC_AHB1_PERIPH_GPIOD (1u << 3u) /*!< AHB1 peripheral GPIOD clock 3 bit. */
#define RCC_AHB1_PERIPH_GPIOE (1u << 4u) /*!< AHB1 peripheral GPIOE clock 4 bit. */
#define RCC_AHB1_PERIPH_GPIOF (1u << 5u) /*!< AHB1 peripheral GPIOF clock 5 bit. */
#define RCC_AHB1_PERIPH_GPIOG (1u << 6u) /*!< AHB1 peripheral GPIOG clock 6 bit. */
#define RCC_AHB1_PERIPH_GPIOH (1u << 7u) /*!< AHB1 peripheral GPIOH clock 7 bit. */
#define RCC_AHB1_PERIPH_SDIO (1u << 10u) /*!< AHB1 peripheral SDIO clock 10 bit. */
#define RCC_AHB1_PERIPH_CRC (1u << 12u) /*!< AHB1 peripheral CRC clock 12 bit. */
#define RCC_AHB1_PERIPH_FLASH (1u << 13u) /*!< AHB1 peripheral FLASH clock 13 bit. */
#define RCC_AHB1_PERIPH_SRAM (1u << 14u) /*!< AHB1 peripheral SRAM clock 14 bit. */
#define RCC_AHB1_PERIPH_DMA1 (1u << 21u) /*!< AHB1 peripheral DMA1 clock 21 bit. */
#define RCC_AHB1_PERIPH_DMA2 (1u << 22u) /*!< AHB1 peripheral DMA2 clock 22 bit. */
#define RCC_AHB1_PERIPH_ETHMAC (1u << 25u) /*!< AHB1 peripheral ETHMAC clock 25 bit. */
/*!
* @}
*/
/*!
* @addtogroup RCC_AHB2_PERIPH
* @{
*/
#define RCC_AHB2_PERIPH_USBOTGFS (1u << 7u) /*!< AHB2 peripheral USBOTGFS clock 7 bit. */
/*!
* @}
*/
/*!
* @addtogroup RCC_AHB3_PERIPH
* @{
*/
#define RCC_AHB3_PERIPH_FSMC (1u << 0u) /*!< AHB3 Periph FSMC clock 0 bit. */
/*!
* @}
*/
/*!
* @addtogroup RCC_APB1_PERIPH
* @{
*/
#define RCC_APB1_PERIPH_TIM2 (1u << 0u) /*!< APB1 peripheral TIM2 clock 0 bit. */
#define RCC_APB1_PERIPH_TIM3 (1u << 1u) /*!< APB1 peripheral TIM3 clock 1 bit. */
#define RCC_APB1_PERIPH_TIM4 (1u << 2u) /*!< APB1 peripheral TIM4 clock 2 bit. */
#define RCC_APB1_PERIPH_TIM5 (1u << 3u) /*!< APB1 peripheral TIM5 clock 3 bit. */
#define RCC_APB1_PERIPH_TIM6 (1u << 4u) /*!< APB1 peripheral TIM6 clock 4 bit. */
#define RCC_APB1_PERIPH_TIM7 (1u << 5u) /*!< APB1 peripheral TIM7 clock 5 bit. */
#define RCC_APB1_PERIPH_WWDG (1u << 11u) /*!< APB1 peripheral WWDG clock 11 bit. */
#define RCC_APB1_PERIPH_SPI2 (1u << 14u) /*!< APB1 peripheral SPI2 clock 14 bit. */
#define RCC_APB1_PERIPH_SPI3 (1u << 15u) /*!< APB1 peripheral SPI3 clock 15 bit. */
#define RCC_APB1_PERIPH_UART2 (1u << 17u) /*!< APB1 peripheral UART2 clock 17 bit. */
#define RCC_APB1_PERIPH_UART3 (1u << 18u) /*!< APB1 peripheral UART3 clock 18 bit. */
#define RCC_APB1_PERIPH_UART4 (1u << 19u) /*!< APB1 peripheral UART4 clock 19 bit. */
#define RCC_APB1_PERIPH_UART5 (1u << 20u) /*!< APB1 peripheral UART5 clock 20 bit. */
#define RCC_APB1_PERIPH_I2C1 (1u << 21u) /*!< APB1 peripheral I2C1 clock 21 bit. */
#define RCC_APB1_PERIPH_I2C2 (1u << 22u) /*!< APB1 peripheral I2C2 clock 22 bit. */
#define RCC_APB1_PERIPH_CRS (1u << 24u) /*!< APB1 peripheral CRS clock 24 bit. */
#define RCC_APB1_PERIPH_CAN (1u << 25u) /*!< APB1 peripheral CAN clock 25 bit. */
#define RCC_APB1_PERIPH_BKP (1u << 27u) /*!< APB1 peripheral BKP clock 27 bit. */
#define RCC_APB1_PERIPH_PWR (1u << 28u) /*!< APB1 peripheral PWR clock 28 bit. */
#define RCC_APB1_PERIPH_DAC (1u << 29u) /*!< APB1 peripheral DAC clock 29 bit. */
#define RCC_APB1_PERIPH_UART7 (1u << 30u) /*!< APB1 peripheral UART7 clock 30 bit. */
#define RCC_APB1_PERIPH_UART8 (1u << 31u) /*!< APB1 peripheral UART8 clock 31 bit. */
/*!
* @}
*/
/*!
* @addtogroup RCC_APB2_PERIPH
* @{
*/
#define RCC_APB2_PERIPH_TIM1 (1u << 0u) /*!< APB2 peripheral TIM1 clock 0 bit. */
#define RCC_APB2_PERIPH_TIM8 (1u << 1u) /*!< APB2 peripheral TIM8 clock 1 bit. */
#define RCC_APB2_PERIPH_UART1 (1u << 4u) /*!< APB2 peripheral UART1 clock 4 bit. */
#define RCC_APB2_PERIPH_UART6 (1u << 5u) /*!< APB2 peripheral UART6 clock 5 bit. */
#define RCC_APB2_PERIPH_ADC1 (1u << 8u) /*!< APB2 peripheral ADC1 clock 8 bit. */
#define RCC_APB2_PERIPH_ADC2 (1u << 9u) /*!< APB2 peripheral ADC2 clock 9 bit. */
#define RCC_APB2_PERIPH_ADC3 (1u << 10u) /*!< APB2 peripheral ADC3 clock 10 bit. */
#define RCC_APB2_PERIPH_SPI1 (1u << 12u) /*!< APB2 peripheral SPI1 clock 12 bit. */
#define RCC_APB2_PERIPH_SYSCFG (1u << 14u) /*!< APB2 peripheral SYSCFG clock 14 bit. */
#define RCC_APB2_PERIPH_COMP (1u << 15u) /*!< APB2 peripheral COMP clock 15 bit. */
/*!
* @}
*/
/*!
* @brief Define the clock source for MCO output.
*/
typedef enum
{
RCC_MCO_NoClock = 0u, /*!< MCO NoClock 0 bits. */
RCC_MCO_LSI = 2u, /*!< MCO LSI 2 bits. */
RCC_MCO_LSE = 3u, /*!< MCO LSE 3 bits. */
RCC_MCO_SYSCLK = 4u, /*!< MCO SYSCLK 4 bits. */
RCC_MCO_HSI = 5u, /*!< MCO HSI 5 bits. */
RCC_MCO_HSE = 6u, /*!< MCO HSE 6 bits. */
RCC_MCO_PLLCLK_Div2 = 7u, /*!< MCO PLLCLK divided by 2 7 bits. */
} RCC_MCO_Type;
/*!
* @brief Enable the RCC AHB1 periphs clock module.
*
* @param ahb1_periphs AHB1 Peripheral instance.
* @param enable 'true' to enable the AHB1Periphs, 'false' to disable the AHB1Periphs.
* @return None.
*/
void RCC_EnableAHB1Periphs(uint32_t ahb1_periphs, bool enable);
/*!
* @brief Reset the RCC AHB1 periphs clock module.
*
* @param ahb1_periphs AHB1 Peripheral instance.
* @return None.
*/
void RCC_ResetAHB1Periphs(uint32_t ahb1_periphs);
/*!
* @brief Enable the RCC AHB2 periphs clock module.
*
* @param ahb2_periphs AHB2 Peripheral instance.
* @param enable 'true' to enable the AHB2Periphs, 'false' to disable the AHB2Periphs.
* @return None.
*/
void RCC_EnableAHB2Periphs(uint32_t ahb2_periphs, bool enable);
/*!
* @brief Reset the RCC AHB2 periphs clock module.
*
* @param ahb2_periphs AHB2 Peripheral instance.
* @return None.
*/
void RCC_ResetAHB2Periphs(uint32_t ahb2_periphs);
/*!
* @brief Enable the RCC AHB3 periphs clock module.
*
* @param ahb3_periphs AHB3 Peripheral instance.
* @param enable 'true' to enable the AHB3Periphs, 'false' to disable the AHB3Periphs.
* @return None.
*/
void RCC_EnableAHB3Periphs(uint32_t ahb3_periphs, bool enable);
/*!
* @brief Reset the RCC AHB3 periphs clock module.
*
* @param ahb3_periphs AHB3 Peripheral instance.
* @return None.
*/
void RCC_ResetAHB3Periphs(uint32_t ahb3_periphs);
/*!
* @brief Enable the RCC APB1 periphs clock module.
*
* @param apb1_periphs APB1 Peripheral instance.
* @param enable 'true' to enable the APB1Periphs, 'false' to disable the APB1Periphs.
* @return None.
*/
void RCC_EnableAPB1Periphs(uint32_t apb1_periphs, bool enable);
/*!
* @brief Reset the RCC APB1 periphs clock module.
*
* @param apb1_periphs APB1 Peripheral instance.
* @return None.
*/
void RCC_ResetAPB1Periphs(uint32_t apb1_periphs);
/*!
* @brief Enable the RCC APB2 periphs clock module.
*
* @param apb2_periphs APB1 Peripheral instance.
* @param enable 'true' to enable the APB2Periphs, 'false' to disable the APB2Periphs.
* @return None.
*/
void RCC_EnableAPB2Periphs(uint32_t apb2_periphs, bool enable);
/*!
* @brief Reset the RCC APB2 periphs clock module.
*
* @param apb2_periphs APB2 Peripheral instance.
* @return None.
*/
void RCC_ResetAPB2Periphs(uint32_t apb2_periphs);
/*!
* @brief MCO Configuration clock source.
*
* @param source The clock source for MCO Configuration.
* @return None.
*/
void RCC_MCOConf(RCC_MCO_Type source);
/*!
*@}
*/
#endif /* __HAL_RCC_H__ */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_RTC_H__
#define __HAL_RTC_H__
#include "hal_common.h"
#include "hal_rcc.h"
/*!
* @addtogroup RTC
* @{
*/
/*!
* @addtogroup RTC_STATUS
* @{
*/
#define RTC_STATUS_OPERATION RTC_CRL_RTOFF_MASK /*!< Status flag when write operation of RTC register is completed. */
#define RTC_STATUS_SYNC RTC_CRL_RSF_MASK /*!< Status flag when registers synchronized. */
#define RTC_STATUS_CLKRDY RCC_BDCR_LSERDY_MASK /*!< Status flag when the clock of LSE is ready. */
/*!
* @}
*/
/*!
* @addtogroup RTC_INT
* @{
*/
#define RTC_INT_SEC RTC_CRL_SECF_MASK /*!< Interrupt enable when seconds interrupt generation or overflow of prescaler. After the flag is generated, RTC counter + 1. */
#define RTC_INT_ALARM RTC_CRL_ALRF_MASK /*!< Interrupt enable when the alarm interrupt is generated, in other words, the value of the alarm counter is the same as the RTC counter. */
#define RTC_INT_OVERFLOW RTC_CRL_OWF_MASK /*!< Interrupt enable when overflow interrupt generaton or programmable counter overflow. */
/*!
* @}
*/
/*!
* @brief Define the callback function called when the RTC interrupt is done.
*/
typedef void (*RTC_Callback_1_Type)(void *param);
/*!
* @brief This type of structure instance is used to set and get time when set time and get current time.
*/
typedef struct
{
uint8_t Secs; /*!< Specify the clock seconds. */
uint8_t Mins; /*!< Specify the clock minutes. */
uint8_t Hours; /*!< Specify the clock hours. */
uint8_t Days; /*!< Specify the clock days. */
uint8_t Months; /*!< Specify the clock months. */
uint16_t Years; /*!< Specify the clock years. */
uint16_t HYears; /*!< Specify term of highest years. */
uint16_t LYears; /*!< Specify term of lowest years. */
uint32_t Div; /*!< Specify the number of prescaler. */
} RTC_Init_Type;
typedef struct
{
uint32_t WaitTime; /*!< Specify the time limit for wait to the flag to be generated. If the required flag is not generated after this time, considered as timeout. */
uint32_t AlarmTime; /*!< Specify the number of seconds that alarm clock will respond. */
RTC_Callback_1_Type SecDoneCallback; /*!< Callback function, called when the rtc seconds interrupt is done. */
RTC_Callback_1_Type AlarmDoneCallback; /*!< Callback function, called when the rtc alarm interrupt is done. */
} RTC_Time_Type;
/*!
* @brief Initialize the RTC module.
*
* Open access to BKP, enable clock source and RTC.
* RTC starts counting after initialization.
*
* @return None.
*/
void RTC_Init(void);
/*!
* @brief Enable the BKP access module.
*
* @param enable 'true' to enable the access to RTC and BKP, 'false' to disable the access to RTC and BKP.
* @return None.
*/
void RTC_EnableAccess(bool enable);
/*!
* @brief Enable reset of the RTC module.
*
* The register of BKP is reset by the backup domain and is not reset during power reset or system reset.
*
* @param enable 'true' to enable the BKP reset, 'false' to disable the BKP reset.
* @return None.
*/
void RTC_EnableReset(bool enable);
/*!
* @brief Enable the RTC moudle.
*
* @param enable 'true' to enable the module, 'false' to disable the module.
* @return None.
*/
void RTC_Enable(bool enable);
/*!
* @brief Get the current status flags of the RTC module.
*
* @return Status flags. See to @ref RTC_STATUS.
*/
uint32_t RTC_GetStatus(void);
/*!
* @brief Clear the status flags of the RTC module.
*
* @param status The mask code of the indicated flags to be clear. See to @ref RTC_STATUS.
* @return None.
*/
void RTC_ClearStatus(uint32_t status);
/*!
* @brief Get the current clock source status flags of RTC module.
*
* @return Status flags. See to @ref RTC_STATUS.
*/
uint32_t RTC_GetClockStatus(void);
/*!
* @brief Enable the configration of the RTC module.
*
* @param enable 'true' to enable the configration module, 'false' to disable the configration module.
* @return None.
*/
void RTC_EnableConf(bool enable);
/*!
* @brief Put the data into prescaler register of the RTC module.
*
* @param div Data value to be send into the prescaler register.
* @return None.
*/
void RTC_PutPrescalerData(uint32_t div);
/*!
* @brief Put the data into counter register of the RTC module.
*
* @param cnt Data value to be send into the counter register.
* @return None.
*/
void RTC_PutCounterData(uint32_t cnt);
/*!
* @brief Put the data into alarm register of the RTC module.
*
* @param alarm Data value to be send into the alarm register.
* @return None.
*/
void RTC_PutAlarmData(uint32_t alarm);
/*!
* @brief Get the data from counter register of the RTC module.
*
* @return The data value from counter.
*/
uint32_t RTC_GetCounterData(void);
/*!
* @brief Get the data from alarm register of the RTC module.
*
* @return The data value from alarm register.
*/
uint32_t RTC_GetAlarmData(void);
/*!
* @brief Enabel interrupt of the RTC module.
*
* @param interrupts Interrupt code masks. See to @ref RTC_INT.
* @param enable 'true' to enable the indicated interrupts, 'false' to disable the indicated interrupts.
* @return None.
*/
void RTC_EnableInterrupts(uint32_t interrupts, bool enable);
/*!
* @brief Get the interrupts status flags of the RTC module.
*
* @return Interrupt status flags. See to @ref RTC_INT.
*/
uint32_t RTC_GetInterruptStatus(void);
/*!
* @brief Clear the interrupts status flags of the RTC module.
*
* @param interrupts The mask codes of the indicated interrupt flags to be cleared. See to @ref RTC_INT.
* @return None.
*/
void RTC_ClearInterruptStatus(uint32_t interrupts);
/*!
* @brief Read the current enabled interrupts the RTC module.
*
* @return The mask codes enabled interrupts. See to @ref RTC_INT.
*/
uint32_t RTC_GetEnabledInterrupts(void);
/*!
* @brief Setup the initialization time of the RTC module.
*
* @param init Pointer to the initialization structure. See to @ref RTC_Init_Type.
* @param time Pointer to the time structure. See to @ref RTC_Time_Type.
* @return 'true' to set time succeess, 'false' to set time failed.
*/
bool RTC_SetTimeBlocking(RTC_Init_Type * init, RTC_Time_Type * time);
/*!
* @brief Calculate and get current time.
*
* @param init Pointer to the initialization structure. See to @ref RTC_Init_Type.
* @param time Pointer to the time structure. See to @ref RTC_Time_Type.
* @return None.
*/
void RTC_CalcTimeBlocking(RTC_Init_Type * init, RTC_Time_Type * time);
/*!
* @brief Set alarm time of the RTC module.
*
* @param time Pointer to the time structure. See to @ref RTC_Time_Type.
* @return 'true' to set alarm time succeess, 'false' to set alarm time failed.
*/
bool RTC_SetAlarmBlocking(RTC_Time_Type * time);
/*!
* @brief RTC interrupt handler.
*
* @param init Pointer to the RTC current time. See to @ref RTC_Init_Type.
* @param time Pointer to the RTC interrupt done and interrupt count. See to @ref RTC_Time_Type.
* @param interrupts Interrupt status flags. See to @ref RTC_INT.
* @return None.
*/
void RTC_TimeHandler(RTC_Init_Type * init, RTC_Time_Type * time, uint32_t interrupts);
/*!
*@}
*/
#endif /* __HAL_RTC_H__ */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_SDIO_H__
#define __HAL_SDIO_H__
#include "hal_common.h"
/*!
* @addtogroup SDIO
* @{
*/
/*!
* @brief SDIO driver version number.
*/
#define SDIO_DRIVER_VERSION 0u /*!< sdio_0. */
/*!
* @brief Card command return type .
*/
typedef enum
{
SDIO_RespType_R1, /*!< 32 bit + 8 bit CRC. */
SDIO_RespType_R2, /*!< 128 bit + 8 bit CRC, for CID and CSD. */
SDIO_RespType_R3, /*!< 32 bit + 8 bit CRC, for OCR. */
SDIO_RespType_R6, /*!< 32 bit + 8 bit CRC, for RCA. */
SDIO_RespType_R7, /*!< 32 bit + 8 bit CRC, for card interface condition. */
} SDIO_RespType_Type;
/*!
* @brief SDIO data bus width.
*/
typedef enum
{
SDIO_DataBusWidth_1b = 0u, /*!< 1-bit data bus. */
SDIO_DataBusWidth_4b = 1u, /*!< 4-bit data bus. */
} SDIO_DataBusWidth_Type;
/*!
* @brief SDIO base clock source.
*/
typedef enum
{
SDIO_BaseClkSrc_1MHz = 0u, /*!< Select 1MHz clock as the clock source of SDIO module. */
SDIO_BaseClkSrc_BusClk = 1u, /*!< Select bus clock as the clock source of SDIO module. */
} SDIO_BaseClkSrc_Type;
/*!
* @brief The divider from base clock to port clk line speed.
*/
typedef enum
{
SDIO_ClkLineSpeedDiv_Div2 = 0u, /*!< SDIO clk command line clock freq's divider as 2. */
SDIO_ClkLineSpeedDiv_Div4 = 1u, /*!< SDIO clk command line clock freq's divider as 4. */
SDIO_ClkLineSpeedDiv_Div6 = 2u, /*!< SDIO clk command line clock freq's divider as 6. */
SDIO_ClkLineSpeedDiv_Div8 = 3u, /*!< SDIO clk command line clock freq's divider as 8. */
SDIO_ClkLineSpeedDiv_Div10 = 4u, /*!< SDIO clk command line clock freq's divider as 10. */
SDIO_ClkLineSpeedDiv_Div12 = 5u, /*!< SDIO clk command line clock freq's divider as 12. */
SDIO_ClkLineSpeedDiv_Div14 = 6u, /*!< SDIO clk command line clock freq's divider as 14. */
SDIO_ClkLineSpeedDiv_Div16 = 7u, /*!< SDIO clk command line clock freq's divider as 16. */
} SDIO_ClkLineSpeedDiv_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref SDIO_Init() to initialize the SDIO module.
*/
typedef struct
{
uint32_t BusClkHz; /*!< SDIO module clock freq. */
SDIO_BaseClkSrc_Type BaseClkSrc; /*!< Select the SDIO base clock source. */
SDIO_ClkLineSpeedDiv_Type ClkLineSpeedDiv; /*!< Select the divider from base clock to port clk line speed. */
} SDIO_Init_Type;
/*!
* @addtogroup SDIO_STATUS
* @{
*/
#define SDIO_STATUS_CMD_DONE (1u << 0u) /*!< Status flag when SDIO sent a command to bus. */
#define SDIO_STATUS_DAT_DONE (1u << 1u) /*!< Status flag when SDIO sent a word of data to bus. */
#define SDIO_STATUS_DAT_CRC_ERR (1u << 2u) /*!< Status flag when SDIO found a data crc error. */
#define SDIO_STATUS_CMD_CRC_ERR (1u << 3u) /*!< Status flag when SDIO found a command crc error. */
#define SDIO_STATUS_DAT_MULTI_BLOCKS_DONE (1u << 4u) /*!< Status flag when SDIO sent multiple blocks of data. */
#define SDIO_STATUS_DAT_MULTI_BLOCKS_TIMEOUT (1u << 5u) /*!< Status flag when SDIO found a timeout of sending multiple blocks of data. */
#define SDIO_STATUS_CMD_NCR_TIMEOUT (1u << 6u) /*!< Status flag when SDIO found a command ncr timeout issue. */
#define SDIO_STATUS_CRC_CRC_ERR (1u << 7u) /*!< Status flag when SDIO found a crc issue. */
#define SDIO_STATUS_DAT0_BUSY (1u << 8u) /*!< Status flag when SDIO checked the data0 line is busy. */
#define SDIO_STATUS_DAT_BUF_FULL (1u << 9u) /*!< Status flag when SDIO fifo buffer is full. */
#define SDIO_STATUS_DAT_BUF_EMPTY (1u << 10u) /*!< Status flag when SDIO fifo buffer is empty. */
/*!
* @}
*/
/*!
* @addtogroup SDIO_INT
* @{
*/
#define SDIO_INT_CMD_DONE (1u << 0u) /*!< Interrupt enable when SDIO sent a command to bus. */
#define SDIO_INT_DAT_DONE (1u << 1u) /*!< Interrupt enable when SDIO sent a word of data to bus. */
#define SDIO_INT_DAT_CRC_ERR (1u << 2u) /*!< Interrupt enable when SDIO found a data crc error. */
#define SDIO_INT_CMD_CRC_ERR (1u << 3u) /*!< Interrupt enable when SDIO found a command crc error. */
#define SDIO_INT_DAT_MULTI_BLOCKS_DONE (1u << 4u) /*!< Interrupt enable when SDIO sent multiple blocks of data. */
#define SDIO_INT_DAT_MULTI_BLOCKS_TIMEOUT (1u << 5u) /*!< Interrupt enable when SDIO found a timeout of sending multiple blocks of data. */
#define SDIO_INT_CMD_NCR_TIMEOUT (1u << 6u) /*!< Interrupt enable when SDIO found a command ncr timeout issue. */
#define SDIO_INT_CRC_CRC_ERR (1u << 7u) /*!< Interrupt enable when SDIO found a crc issue. */
#define SDIO_INT_DAT0_BUSY (1u << 8u) /*!< Interrupt enable when SDIO checked the data0 line is busy. */
/*!
* @}
*/
/*!
* @addtogroup SDIO_CMD_FLAG
* @{
*/
#define SDIO_CMD_FLAG_READ_BLOCK (1u << 0u) /*!< SDIO command flag of reading block. */
#define SDIO_CMD_FLAG_WRITE_BLOCK (1u << 1u) /*!< SDIO command flag of writing block. */
#define SDIO_CMD_FLAG_READ_CID_CSD (1u << 2u) /*!< SDIO command flag of reading CID and CSD. */
#define SDIO_CMD_FLAG_WRITE_BLOCKS (1u << 5u) /*!< SDIO command flag of writing multiple blocks. */
#define SDIO_CMD_FLAG_READ_BLOCKS (1u << 6u) /*!< SDIO command flag of reading multiple blocks. */
#define SDIO_CMD_FLAG_ENABLE_DATA_XFER (1u << 7u) /*!< SDIO command flag of starting the data transfer. */
/*!
* @}
*/
/*!
* @brief Initialize the SDIO module.
*
* @param SDIOx SDIO instance.
* @param init Pointer to the initialization structure. See to @ref SDIO_Init_Type.
* @return None.
*/
void SDIO_Init(SDIO_Type * SDIOx, SDIO_Init_Type * init);
/*!
* @brief Enable the SDIO module.
*
* @param SDIOx SDIO instance.
* @param enable 'true' to enable the module, 'false' to disable the module.
* @return None.
*/
void SDIO_Enable(SDIO_Type * SDIOx, bool enable);
/*!
* @brief Setup the data bus width of the SDIO module.
*
* @param SDIOx SDIO instance.
* @param width SDIO data bus width. See to @ref SDIO_DataBusWidth_Type.
* @return None.
*/
void SDIO_SetDataBusWidth(SDIO_Type *SDIOx, SDIO_DataBusWidth_Type width);
/*!
* @brief Get the status of the SDIO module.
*
* @param SDIOx SDIO instance.
* @return SDIO module status, see to @ref SDIO_STATUS.
*/
uint32_t SDIO_GetStatus(SDIO_Type * SDIOx);
/*!
* @brief Clear the status of the SDIO module.
*
* @param SDIOx SDIO instance.
* @param flags Indicate the flags to be cleared. See to @ref SDIO_STATUS.
* @return SDIO module status, see to @ref SDIO_STATUS.
*/
void SDIO_ClearStatus(SDIO_Type * SDIOx, uint32_t flags);
/*!
* @brief Enable interrupts of the SDIO module.
*
* @param SDIOx SDIO instance.
* @param interrupts Interrupt code masks. See to @ref SDIO_INT.
* @param enable 'true' to enable the indicated interrupts, 'false' to disable the indicated interrupts.
* @return None.
*/
void SDIO_EnableInterrupts(SDIO_Type * SDIOx, uint32_t interrupts, bool enable);
/*!
* @brief Execute the SD command through the SDIO module.
*
* @param SDIOx SDIO instance.
* @param cmd_index SD command index number.
* @param param SD commamd parameter.
* @param cmd_flags SD command option flags. See to @ref SDIO_CMD_FLAG.
* @return None.
*/
void SDIO_ExecuteCmd(SDIO_Type * SDIOx, uint8_t cmd_index, uint32_t param, uint32_t cmd_flags);
/*!
* @brief Send data when executing the SD command through the SDIO module.
*
* @param SDIOx SDIO instance.
* @param cmd_flags SD command option flags. See to @ref SDIO_CMD_FLAG.
* @return None.
*/
void SDIO_ExecuteData(SDIO_Type * SDIOx, uint32_t cmd_flags);
/*!
* @brief Receive the return type at the end of executing SD command.
*
* @param SDIOx SDIO instance.
* @param resp_type SD command return type. See to @ref SDIO_RespType_Type.
* @param resp Pointer to a buffer, which would be used to keep the return value.
* @return None.
*/
void SDIO_RequestResp(SDIO_Type * SDIOx, SDIO_RespType_Type resp_type, uint32_t *resp);
/*!
* @brief Put data into the FIFO inside the SDIO module.
*
* @param SDIOx SDIO instance.
* @param dat Data word to be put into the FIFO.
* @return None.
*/
void SDIO_PutFifoData(SDIO_Type * SDIOx, uint32_t dat);
/*!
* @brief Get data from the FIFO inside the SDIO module.
*
* @param SDIOx SDIO instance.
* @return Data word from the FIFO.
*/
uint32_t SDIO_GetFifoData(SDIO_Type * SDIOx);
/*!
* @brief Clear all data of the FIFO inside the SDIO module.
*
* @param SDIOx SDIO instance.
* @return None.
*/
void SDIO_ClearFifoData(SDIO_Type * SDIOx);
/*!
* @brief Setup the data direction of data transfer.
*
* @param SDIOx SDIO instance.
* @param write 'true' to setup as write, 'false' to setup as read.
* @return None.
*/
void SDIO_SwitchFifoWrite(SDIO_Type * SDIOx, bool write);
/*!
* @brief Setup the watermark of the FIFO inside the SDIO module.
*
* @param SDIOx SDIO instance.
* @param word_cnt Indicated the watermark value.
* @return None.
*/
void SDIO_SetFifoWatermark(SDIO_Type * SDIOx, uint32_t word_cnt);
/*!
* @brief Enable the DMA of SDIO module
*
* @param SDIOx SDIO instance.
* @param enable 'true' to enable the DMA, while 'false' to disable.
* @return None.
*/
void SDIO_EnableFifoDMA(SDIO_Type * SDIOx, bool enable);
/*!
* @brief Setup count number for the read multiple block operation.
*
* @param SDIOx SDIO instance.
* @param blk_cnt Indicated the count number of blocks.
* @return None.
*/
void SDIO_SetMultiBlockCount(SDIO_Type * SDIOx, uint32_t blk_cnt);
/*!
* @brief Enable the wait operation when reading the FIFO.
*
* @param SDIOx SDIO instance.
* @param enable 'true' to enable the wait operation, 'false' to disable this function.
* @return None.
*/
void SDIO_EnableFifoReadWait(SDIO_Type * SDIOx, bool enable);
/*!
* @}
*/
#endif /* __HAL_SDIO_H__ */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_SPI_H__
#define __HAL_SPI_H__
#include "hal_common.h"
/*!
* @addtogroup SPI
* @{
*/
/*!
* @addtogroup SPI_STATUS
* @{
*/
#define SPI_STATUS_TXEMPTY SPI_I2S_CSTAT_TXEPT_MASK /*!< Status flag when SPI transmiter buffer is empty. */
#define SPI_STATUS_RXDONE SPI_I2S_CSTAT_RXAVL_MASK /*!< Status flag when SPI receiving buffer is with available data. */
#define SPI_STATUS_TXFULL SPI_I2S_CSTAT_TXFULL_MASK /*!< Status flag when SPI transmiter buffer is full. */
/*!
* @}
*/
/*!
* @addtogroup SPI_INT
* @{
*/
#define SPI_INT_TXEMPTY SPI_I2S_INTEN_TXIEN_MASK /*!< Interrupt enable when SPI transmiter buffer is empty. */
#define SPI_INT_RXDONE SPI_I2S_INTEN_RXIEN_MASK /*!< Interrupt enable when UART receiving buffer is with available data. */
/*!
* @}
*/
/*!
* @brief SPI Polarity Phase type.
*/
typedef enum
{
SPI_PolarityPhase_Alt0 = 0u, /*!< CPOL = 0, CPHA = 0, Clock line is low when idle. Tx data line is high when idle. Data valid when at rising edge */
SPI_PolarityPhase_Alt1 = 1u, /*!< CPOL = 0, CPHA = 1, Clock line is low when idle. Tx data line is high when idle. Data valid when at falling edge */
SPI_PolarityPhase_Alt2 = 2u, /*!< CPOL = 1, CPHA = 0, Clock line is high when idle. Tx data line is high when idle. Data valid when at falling edge */
SPI_PolarityPhase_Alt3 = 3u, /*!< CPOL = 1, CPHA = 1, Clock line is high when idle. Tx data line is high when idle. Data valid when at rising edge */
} SPI_PolarityPhase_Type;
/*!
* @brief SPI data width type.
*/
typedef enum
{
SPI_DataWidth_0b = 0u, /*!< Data Width 0 bits. */
SPI_DataWidth_1b = 1u, /*!< Data Width 1 bits. */
SPI_DataWidth_2b = 2u, /*!< Data Width 2 bits. */
SPI_DataWidth_3b = 3u, /*!< Data Width 3 bits. */
SPI_DataWidth_4b = 4u, /*!< Data Width 4 bits. */
SPI_DataWidth_5b = 5u, /*!< Data Width 5 bits. */
SPI_DataWidth_6b = 6u, /*!< Data Width 6 bits. */
SPI_DataWidth_7b = 7u, /*!< Data Width 7 bits. */
SPI_DataWidth_8b = 8u, /*!< Data Width 8 bits. */
SPI_DataWidth_9b = 9u, /*!< Data Width 9 bits. */
SPI_DataWidth_10b = 10u, /*!< Data Width 10 bits. */
SPI_DataWidth_11b = 11u, /*!< Data Width 11 bits. */
SPI_DataWidth_12b = 12u, /*!< Data Width 12 bits. */
SPI_DataWidth_13b = 13u, /*!< Data Width 13 bits. */
SPI_DataWidth_14b = 14u, /*!< Data Width 14 bits. */
SPI_DataWidth_15b = 15u, /*!< Data Width 15 bits. */
SPI_DataWidth_16b = 16u, /*!< Data Width 16 bits. */
SPI_DataWidth_17b = 17u, /*!< Data Width 17 bits. */
SPI_DataWidth_18b = 18u, /*!< Data Width 18 bits. */
SPI_DataWidth_19b = 19u, /*!< Data Width 19 bits. */
SPI_DataWidth_20b = 20u, /*!< Data Width 20 bits. */
SPI_DataWidth_21b = 21u, /*!< Data Width 21 bits. */
SPI_DataWidth_22b = 22u, /*!< Data Width 22 bits. */
SPI_DataWidth_23b = 23u, /*!< Data Width 23 bits. */
SPI_DataWidth_24b = 24u, /*!< Data Width 24 bits. */
SPI_DataWidth_25b = 25u, /*!< Data Width 25 bits. */
SPI_DataWidth_26b = 26u, /*!< Data Width 26 bits. */
SPI_DataWidth_27b = 27u, /*!< Data Width 27 bits. */
SPI_DataWidth_28b = 28u, /*!< Data Width 28 bits. */
SPI_DataWidth_29b = 29u, /*!< Data Width 29 bits. */
SPI_DataWidth_30b = 30u, /*!< Data Width 30 bits. */
SPI_DataWidth_31b = 31u, /*!< Data Width 31 bits. */
SPI_DataWidth_32b = 32u, /*!< Data Width 32 bits. */
} SPI_DataWidth_Type;
/*!
* @brief SPI xfer mode type.
*/
typedef enum
{
SPI_XferMode_Disabled = 0u, /*!< Disable both Tx and Rx. */
SPI_XferMode_RxOnly = 1u, /*!< Enable Rx only. */
SPI_XferMode_TxRx = 2u, /*!< Enable both Tx and Rx. */
} SPI_XferMode_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref SPI_InitMaster() to initialize the SPI module.
*/
typedef struct
{
uint32_t ClockFreqHz; /*!< Bus Clock Freq. */
uint32_t BaudRate; /*!< This member configures the UART communication baud rate. */
SPI_PolarityPhase_Type PolarityPhase; /*!< Specifies different communication modes. */
SPI_DataWidth_Type DataWidth; /*!< Specifies the number of bits of data to be transmitted. */
SPI_XferMode_Type XferMode; /*!< Specifies whether the Receive or Transmit mode is enable or not. */
bool AutoCS; /*!< Specifies whether the chip selection signal is controlled by SPI or not. */
bool LSB; /*!< Specifies whether the current state is Thumb or ARM mode. */
} SPI_Master_Init_Type;
/*!
* @brief Initialize the SPI Master module.
*
* @param SPIx SPI instance.
* @param init Pointer to the initialization structure. See to @ref SPI_Master_Init_Type.
* @return None.
*/
void SPI_InitMaster(SPI_Type * SPIx, SPI_Master_Init_Type * init);
/*!
* @brief Enable the SPI module.
*
* The SPI module should be enabled before sending or receiving data.
*
* @param SPIx SPI instance.
* @param enable 'true' to enable the module, 'false' to disable the module.
* @return None.
*/
void SPI_Enable(SPI_Type * SPIx, bool enable);
/*!
* @brief Get the current status flags of the SPI module.
*
* @param SPIx SPI instance.
* @return Status flags. See to @ref SPI_STATUS.
*/
uint32_t SPI_GetStatus(SPI_Type * SPIx);
/*!
* @brief Enable interrupts of the SPI module.
*
* @param SPIx SPI instance.
* @param interrupts Interrupt code masks. See to @ref SPI_INT.
* @param enable 'true' to enable the indicated interrupts, 'false' to disable the indicated interrupts.
* @return None.
*/
void SPI_EnableInterrupts(SPI_Type * SPIx, uint32_t interrupts, bool enable);
/*!
* @brief Get the interrupts status flags of the SPI module.
*
* @param SPIx SPI instance.
* @return Interrupt status flags. See to @ref SPI_INT.
*/
uint32_t SPI_GetInterruptStatus(SPI_Type * SPIx);
/*!
* @brief Clear the interrupts status flags of the SPI module.
*
* @param SPIx SPI instance.
* @param interrupts The mask codes of the indicated interrupt flags to be cleared.
* @return Interrupt status flags. See to @ref SPI_INT.
*/
void SPI_ClearInterruptStatus(SPI_Type * SPIx, uint32_t interrupts);
/*!
* @brief Put the data into transmiter buffer of the SPI module.
*
* @param SPIx SPI instance.
* @param dat Data value to be send through the transmiter.
* @return None.
*/
void SPI_PutData(SPI_Type * SPIx, uint32_t dat);
/*!
* @brief Get the data from receiver buffer of the SPI module.
*
* @param SPIx SPI instance.
* @return The data value received from the receiver.
* @return None.
*/
uint32_t SPI_GetData(SPI_Type * SPIx);
/*!
* @brief Enable the DMA trigger from the SPI module.
*
* The DMA trigger events are the same as the intertupts.
*
* @param SPIx SPI instance.
* @param enable 'true' to enable the DMA trigger, 'false' to disable the DMA trigger.
* @return None.
*/
void SPI_EnableDMA(SPI_Type * SPIx, bool enable);
/*!
* @brief Read the current enabled interrupts the SPI module.
*
* @param SPIx SPI instance.
* @return The mask codes enabled interrupts. See to ref@ SPI_INT
*/
uint32_t SPI_GetEnabledInterrupts(SPI_Type * SPIx);
/*!
* @brief Get the hardware Rx data buffer's address the SPI module.
*
* The return value of the address is most used with DMA module.
*
* @param SPIx SPI instance.
* @return The value of the address for SPI module's hardware Rx data buffer.
*/
uint32_t SPI_GetRxDataRegAddr(SPI_Type * SPIx);
/*!
* @brief Get the hardware Tx data buffer's address the SPI module.
*
* The return value of the address is most used with DMA module.
*
* @param SPIx SPI instance.
* @return The value of the address for SPI module's hardware Tx data buffer.
*/
uint32_t SPI_GetTxDataRegAddr(SPI_Type * SPIx);
/*!
* @brief Enable the SPI CS module.
*
* @param SPIx SPI instance.
* @param cs_mask Code mask of whether the chip selection signal is controlled by SPI
* @return None.
*/
void SPI_EnableCS(SPI_Type * SPIx, uint32_t cs_mask);
/*!
*@}
*/
#endif /* __HAL_SPI_H__ */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_SYSCFG_H__
#define __HAL_SYSCFG_H__
#include "hal_common.h"
/*!
* @addtogroup SYSCFG
* @{
*/
/*!
* @brief Boot memory mapping mode.
*/
typedef enum
{
SYSCFG_BootMemMode_Flash = 0u, /*!< SYSCFG Boot Memory Flash mode. */
SYSCFG_BootMemMode_ROM = 1u, /*!< SYSCFG Boot Memory ROM mode. */
SYSCFG_BootMemMode_SRAM = 3u, /*!< SYSCFG Boot Memory SRAM mode. */
} SYSCFG_BootMemMode_Type;
/*!
* @brief Set FSMC compatible mode.
*/
typedef enum
{
SYSCFG_FSMCMode_NorFlash = 0u, /*!< SYSCFG FSMC compatible with Nor Flash. */
SYSCFG_FSMCMode_8080 = 1u, /*!< SYSCFG FSMC compatible with 8080 protocal. */
} SYSCFG_FSMCMode_Type;
/*!
* @brief FSMC pin usage.
* FSMC pins can be used as data use only or mixed as data use and address use.
*/
typedef enum
{
SYSCFG_FSMCPinUseMode_DataAndAddrMixed = 0u, /*!< FSMC pins can be used mixedly. */
SYSCFG_FSMCPinUseMode_DataOnly = 1u, /*!< FSMC pins can be used for data only. */
} SYSCFG_FSMCPinUseMode_Type;
/*!
* @brief External interrupt port.
*/
typedef enum
{
SYSCFG_EXTIPort_GPIOA = (0x00U), /*!< SYSCFG External Interrupt GPIOA. */
SYSCFG_EXTIPort_GPIOB = (0x01U), /*!< SYSCFG External Interrupt GPIOB. */
SYSCFG_EXTIPort_GPIOC = (0x02U), /*!< SYSCFG External Interrupt GPIOC. */
SYSCFG_EXTIPort_GPIOD = (0x03U), /*!< SYSCFG External Interrupt GPIOD. */
SYSCFG_EXTIPort_GPIOE = (0x04U), /*!< SYSCFG External Interrupt GPIOE. */
SYSCFG_EXTIPort_GPIOF = (0x05U), /*!< SYSCFG External Interrupt GPIOF. */
} SYSCFG_EXTIPort_Type;
/*!
* @brief External interrupt line.
*/
typedef enum
{
SYSCFG_EXTILine_0 = (0x00U), /*!< Pin 0 selected. */
SYSCFG_EXTILine_1 = (0x01U), /*!< Pin 1 selected. */
SYSCFG_EXTILine_2 = (0x02U), /*!< Pin 2 selected. */
SYSCFG_EXTILine_3 = (0x03U), /*!< Pin 3 selected. */
SYSCFG_EXTILine_4 = (0x04U), /*!< Pin 4 selected. */
SYSCFG_EXTILine_5 = (0x05U), /*!< Pin 5 selected. */
SYSCFG_EXTILine_6 = (0x06U), /*!< Pin 6 selected. */
SYSCFG_EXTILine_7 = (0x07U), /*!< Pin 7 selected. */
SYSCFG_EXTILine_8 = (0x08U), /*!< Pin 8 selected. */
SYSCFG_EXTILine_9 = (0x09U), /*!< Pin 9 selected. */
SYSCFG_EXTILine_10 = (0x0AU), /*!< Pin 10 selected. */
SYSCFG_EXTILine_11 = (0x0BU), /*!< Pin 11 selected. */
SYSCFG_EXTILine_12 = (0x0CU), /*!< Pin 12 selected. */
SYSCFG_EXTILine_13 = (0x0DU), /*!< Pin 13 selected. */
SYSCFG_EXTILine_14 = (0x0EU), /*!< Pin 14 selected. */
SYSCFG_EXTILine_15 = (0x0FU), /*!< Pin 15 selected. */
} SYSCFG_EXTILine_Type;
/*!
* @brief I2C port mode.
*/
typedef enum
{
SYSCFG_I2CPortMode_OpenDrain = 0u, /*!< I2C output open-drain mode. */
SYSCFG_I2CPortMode_PushPull = 1u, /*!< I2C output push-pull mode. */
} SYSCFG_I2CPortMode_Type;
/*!
* @brief Ethernet port mode.
*/
typedef enum
{
SYSCFG_ENETPortMode_MII = 0u, /*!< Ethernet connect on MMI port. */
SYSCFG_ENETPortMode_RMII = 1u, /*!< Ethernet connect on RMMI port. */
} SYSCFG_ENETPortMode_Type;
/*!
* @brief Ethernet speed mode.
*/
typedef enum
{
SYSCFG_ENETSpeedMode_10Mb = 0u, /*!< Ethernet speed mode of 10 Mbps. */
SYSCFG_ENETSpeedMode_100Mb = 1u, /*!< Ethernet speed mode of 100 Mbps. */
} SYSCFG_ENETSpeedMode_Type;
/*!
* @brief PVD threshold.
*/
typedef enum
{
SYSCFG_PVDThold_1v8 = 0u, /*!< PVD threshold of 1.8 v.*/
SYSCFG_PVDThold_2v1 = 1u, /*!< PVD threshold of 2.1 v.*/
SYSCFG_PVDThold_2v4 = 2u, /*!< PVD threshold of 2.4 v.*/
SYSCFG_PVDThold_2v7 = 3u, /*!< PVD threshold of 2.7 v.*/
SYSCFG_PVDThold_3v0 = 4u, /*!< PVD threshold of 3.0 v.*/
SYSCFG_PVDThold_3v3 = 5u, /*!< PVD threshold of 3.3 v.*/
SYSCFG_PVDThold_3v6 = 6u, /*!< PVD threshold of 3.6 v.*/
SYSCFG_PVDThold_3v9 = 7u, /*!< PVD threshold of 3.9 v.*/
SYSCFG_PVDThold_4v2 = 8u, /*!< PVD threshold of 4.2 v.*/
SYSCFG_PVDThold_4v5 = 9u, /*!< PVD threshold of 4.5 v.*/
SYSCFG_PVDThold_4v8 = 10u, /*!< PVD threshold of 4.8 v.*/
} SYSCFG_PVDThold_Type;
/*!
* @brief PVD output state.
*/
typedef enum
{
SYSCFG_PVDOut_Low = 0u, /*!< PVD output low.*/
SYSCFG_PVDOut_High = 1u, /*!< PVD output high.*/
} SYSCFG_PVDOut_Type;
/*!
* @brief VDT threshold alt.
*/
typedef enum
{
SYSCFG_VDTThold_1v2 = 0u, /*!< VDT threshold of 1.2 v.*/
SYSCFG_VDTThold_1v1 = 1u, /*!< VDT threshold of 1.1 v.*/
SYSCFG_VDTThold_1v0 = 2u, /*!< VDT threshold of 1.0 v.*/
SYSCFG_VDTThold_0v9 = 3u, /*!< VDT threshold of 0.9 v.*/
} SYSCFG_VDTThold_Type;
/*!
* @brief VDT output state.
*/
typedef enum
{
SYSCFG_VDTOut_Low = 0u, /*!< VDT output low.*/
SYSCFG_VDTOut_High = 1u, /*!< VDT output high.*/
} SYSCFG_VDTOut_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref SYSCFG_EnablePVD().
*/
typedef struct
{
SYSCFG_PVDThold_Type Thold; /* Set the threshold of the PVD. */
SYSCFG_PVDOut_Type Output; /* Set the output of the PVD. */
} SYSCFG_PVDConf_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref SYSCFG_EnableVDT().
*/
typedef struct
{
SYSCFG_VDTThold_Type Thold; /* Set the threshold of the VDT. */
SYSCFG_VDTOut_Type Output; /* Set the output of the VDT. */
} SYSCFG_VDTConf_Type;
/*!
* @brief Set boot memory mode.
*
* @param mode The memory mode. See to @ref SYSCFG_BootMemMode_Type.
* @return None.
*/
void SYSCFG_SetBootMemMode(SYSCFG_BootMemMode_Type mode);
/*!
* @brief Set FSMC pin usage mode.
*
* @param mode FMSC pin use mode to be set. See to @ref SYSCFG_FSMCPinUseMode_Type.
* @return None.
*/
void SYSCFG_SetFSMCPinUseMode(SYSCFG_FSMCPinUseMode_Type mode);
/*!
* @brief Set the FMSC compatible mode.
*
* @param mode The compatible mode to be set for FMSC. See to @ref SYSCFG_FSMCMode_Type.
* @return None.
*/
void SYSCFG_SetFSMCMode(SYSCFG_FSMCMode_Type mode);
/*!
* @brief Set the external interrupt mux.
*
* @param port external interrupt port. See to @ref SYSCFG_EXTIPort_Type.
* @param line external interrupt line. See to @ref SYSCFG_EXTILine_Type.
* @return None.
*/
void SYSCFG_SetExtIntMux(SYSCFG_EXTIPort_Type port, SYSCFG_EXTILine_Type line);
/*!
* @brief Set the I2C port 0 mode.
*
* @param mode The I2C output state to be set. See to @ref SYSCFG_I2CPortMode_Type.
* @return None.
*/
void SYSCFG_SetI2C0PortMode(SYSCFG_I2CPortMode_Type mode);
/*!
* @brief Set the I2C port 1 mode.
*
* @param mode The I2C output state to be set. See to @ref SYSCFG_I2CPortMode_Type.
* @return None.
*/
void SYSCFG_SetI2C1PortMode(SYSCFG_I2CPortMode_Type mode);
/*!
* @brief Set the Ethernet port mode.
*
* @param mode The Ethernet port mode. See to @ref SYSCFG_ENETPortMode_Type.
* @return None.
*/
void SYSCFG_SetENETPortMode(SYSCFG_ENETPortMode_Type mode);
/*!
* @brief Set the Ethernet speed mode.
*
* @param mode The Ethernet speed mode. See to @ref SYSCFG_ENETSpeedMode_Type.
* @return None.
*/
void SYSCFG_SetENETSpeedMode(SYSCFG_ENETSpeedMode_Type mode);
/*!
* @brief Enable the PVD.
*
* @param conf Pointer to the PDV configuration structure. See to @ref SYSCFG_PVDConf_Type.
* @return None.
*/
void SYSCFG_EnablePVD(SYSCFG_PVDConf_Type * conf);
/*!
* @brief Enable the VDT.
*
* @param conf Pointer to the VDT configuration structure. See to @ref SYSCFG_VDTConf_Type.
* @return None.
*/
void SYSCFG_EnableVDT(SYSCFG_VDTConf_Type * conf);
/*!
* @brief Enable ADC checking VBat_Div3.
*
* @param enable 'true' to enable ADC checking, 'false' to disable ADC checking.
* @return None.
*/
void SYSCFG_EnableADCCheckVBatDiv3(bool enable);
/*!
* @brief Set the VOS delay time.
*
* @param time VOS delay time.
* @return None.
*/
void SYSCFG_SetVOSDelayValue(uint32_t val);
/*!
* @}
*/
#endif /* __HAL_SYSCFG_H__ */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_TIM_16B_H__
#define __HAL_TIM_16B_H__
#include "hal_common.h"
/*!
* @addtogroup TIM_16B
* @{
*/
/*!
* @brief TIM_16B driver version number.
*/
#define TIM_16B_DRIVER_VERSION 0u /*!< TIM_16B_0. */
/*!
* @addtogroup TIM_16B_CHANNEL_SELECTION
* @{
*/
#define TIM_16B_CHN_NUM (4u) /*!< The total number of TIM_16B channel. */
#define TIM_16B_CHN_1 (0u) /*!< The selection of TIM_16B Channel 1. */
#define TIM_16B_CHN_2 (1u) /*!< The selection of TIM_16B Channel 2. */
#define TIM_16B_CHN_3 (2u) /*!< The selection of TIM_16B Channel 3. */
#define TIM_16B_CHN_4 (3u) /*!< The selection of TIM_16B Channel 4. */
/*!
*@}
*/
/*!
* @addtogroup TIM_16B_INT
* @brief Enable interrupt.
* @{
*/
#define TIM_16B_INT_UPDATE_PERIOD (1u << 0u) /*!< Timer update period interrupt switchers. */
#define TIM_16B_INT_CHN1_EVENT (1u << 1u) /*!< Channel 1 event for output compare or input capture interrupt switchers. */
#define TIM_16B_INT_CHN2_EVENT (1u << 2u) /*!< Channel 2 event for output compare or input capture interrupt switchers. */
#define TIM_16B_INT_CHN3_EVENT (1u << 3u) /*!< Channel 3 event for output compare or input capture interrupt switchers. */
#define TIM_16B_INT_CHN4_EVENT (1u << 4u) /*!< Channel 4 event for output compare or input capture interrupt switchers. */
#define TIM_16B_INT_TRGOUT_EVENT (1u << 6u) /*!< Trigger out event interrupt switchers. */
/*!
* @}
*/
/*!
* @addtogroup TIM_16B_DMA
* @brief Enable DMA.
* @{
*/
#define TIM_16B_DMA_UPDATE_PERIOD (1u << 8u) /*!< Timer update period DMA switchers. */
#define TIM_16B_DMA_CHN1_EVENT (1u << 9u) /*!< Channel 1 event for output compare or input capture DMA switchers. */
#define TIM_16B_DMA_CHN2_EVENT (1u << 10u) /*!< Channel 2 event for output compare or input capture DMA switchers. */
#define TIM_16B_DMA_CHN3_EVENT (1u << 11u) /*!< Channel 3 event for output compare or input capture DMA switchers. */
#define TIM_16B_DMA_CHN4_EVENT (1u << 12u) /*!< Channel 4 event for output compare or input capture DMA switchers. */
#define TIM_16B_DMA_TRGOUT_EVENT (1u << 14u) /*!< Trigger out event DMA switchers. */
/*!
* @}
*/
/*!
* @addtogroup TIM_16B_INT_STATUS
* @brief Check interrupt status.
* @{
*/
#define TIM_16B_STATUS_UPDATE_PERIOD (1u << 0u) /*!< Timer update period interrupt flag. */
#define TIM_16B_STATUS_CHN1_EVENT (1u << 1u) /*!< Channel 1 event for output compare or input capture interrupt flag. */
#define TIM_16B_STATUS_CHN2_EVENT (1u << 2u) /*!< Channel 2 event for output compare or input capture interrupt flag. */
#define TIM_16B_STATUS_CHN3_EVENT (1u << 3u) /*!< Channel 3 event for output compare or input capture interrupt flag. */
#define TIM_16B_STATUS_CHN4_EVENT (1u << 4u) /*!< Channel 4 event for output compare or input capture interrupt flag. */
#define TIM_16B_STATUS_TRGOUT_EVENT (1u << 6u) /*!< Trigger out event interrupt flag. */
#define TIM_16B_STATUS_CHN1_OVER_EVENT (1u << 9u) /*!< Channel 1 event for output overcompare or input overcapture interrupt flag. */
#define TIM_16B_STATUS_CHN2_OVER_EVENT (1u << 10u) /*!< Channel 2 event for output overcompare or input overcapture interrupt flag. */
#define TIM_16B_STATUS_CHN3_OVER_EVENT (1u << 11u) /*!< Channel 3 event for output overcompare or input overcapture interrupt flag. */
#define TIM_16B_STATUS_CHN4_OVER_EVENT (1u << 12u) /*!< Channel 4 event for output overcompare or input overcapture interrupt flag. */
/*!
* @}
*/
/*!
* @addtogroup TIM_16B_SWTRG
* @brief Events to be triggered by software.
* @{
*/
#define TIM_16B_SWTRG_UPDATE_PERIOD (1u << 0u) /*!< Timer update period software trigger. */
#define TIM_16B_SWTRG_CHN1_EVENT (1u << 1u) /*!< Channel 1 event for output compare or input capture software trigger. */
#define TIM_16B_SWTRG_CHN2_EVENT (1u << 2u) /*!< Channel 2 event for output compare or input capture software trigger. */
#define TIM_16B_SWTRG_CHN3_EVENT (1u << 3u) /*!< Channel 3 event for output compare or input capture software trigger. */
#define TIM_16B_SWTRG_CHN4_EVENT (1u << 4u) /*!< Channel 4 event for output compare or input capture software trigger. */
#define TIM_16B_SWTRG_COM_EVENT (1u << 5u) /*!< COM event software trigger. */
#define TIM_16B_SWTRG_TRGOUT_EVENT (1u << 6u) /*!< Trigger out event software trigger. */
/*!
* @}
*/
/*!
* @brief Counter period working mode.
*/
typedef enum
{
TIM_16B_PeriodMode_Continuous = 0u, /*!< Counter works circularly once started. */
TIM_16B_PeriodMode_OneTimeRun = 1u, /*!< Counter only works one time once started. */
} TIM_16B_PeriodMode_Type;
/*!
* @brief Counter count direction.
*/
typedef enum
{
TIM_16B_CountMode_Increasing = 0u, /*!< Counter counts incrementally from 0 to period and generates an update. */
TIM_16B_CountMode_Decreasing = 1u, /*!< Counter counts decrementally from period to 0 and generates an update. */
TIM_16B_CountMode_CenterAligned1 = 2u, /*!< Counter counts center-aligned from 0 to period - 1 then from period to 0 and generates an update. */
TIM_16B_CountMode_CenterAligned2 = 3u, /*!< Counter counts center-aligned from 0 to period - 1 and generates an update then from period to 0. */
TIM_16B_CountMode_CenterAligned3 = 4u, /*!< Counter counts center-aligned from 0 to period - 1 and generates an update then from period to 0 and generates another update. */
} TIM_16B_CountMode_Type;
/*!
* @brief TIM output compare reference polairty event.
*/
typedef enum
{
TIM_16B_OutputCompareRefOut_None = 0u, /*!< Reference will not be changed. */
TIM_16B_OutputCompareRefOut_HighOnMatch = 1u, /*!< Reference will be high when counter value equals channel value. */
TIM_16B_OutputCompareRefOut_LowOnMatch = 2u, /*!< Reference will be low when counter value equals channel value. */
TIM_16B_OutputCompareRefOut_ToggleOnMatch = 3u, /*!< Reference will toggle. */
TIM_16B_OutputCompareRefOut_LowAlways = 4u, /*!< Reference will always be low. */
TIM_16B_OutputCompareRefOut_HighAlways = 5u, /*!< Reference will always be high. */
TIM_16B_OutputCompareRefOut_FallingEdgeOnMatch = 6u, /*!< PWM mode 1. */
TIM_16B_OutputCompareRefOut_RisingEdgeOnMatch = 7u, /*!< PWM mode 2. */
} TIM_16B_OutputCompareRefOut_Type;
/*!
* @brief TIM input capture active edge selection and output compare active polarity selection.
*
* | conf | TIM_16B_PinPolarity_Rising | TIM_16B_PinPolarity_Falling |
* | -------------- | -------------------------- | --------------------------- |
* | input capture | detects rising edge | detects falling edge |
* | output compare | high polarity is active | low polarity is active |
* | encoder mode | input remains | input reverses |
*
*/
typedef enum
{
TIM_16B_PinPolarity_Disable = 0u, /*!< Disable channel. */
TIM_16B_PinPolarity_Rising = 1u, /*!< See the table above. */
TIM_16B_PinPolarity_Falling = 2u, /*!< See the table above. */
TIM_16B_PinPolarity_RisingOrFalling = 3u, /*!< For input capture, detect both the rising and falling edge. */
}TIM_16B_PinPolarity_Type;
/*!
* @brief TIM Input active times to evoke capture.
*/
typedef enum
{
TIM_16B_InputCaptureInDiv_OnEveryCapture = 0u, /*!< Every input call capture. */
TIM_16B_InputCaptureInDiv_OnEach2Capture = 1u, /*!< Every two input call capture. */
TIM_16B_InputCaptureInDiv_OnEach4Capture = 2u, /*!< Every four input call capture. */
TIM_16B_InputCaptureInDiv_OnEach8Capture = 3u, /*!< Every eight input call capture. */
} TIM_16B_InputCaptureInDiv_Type;
/*!
* @brief TIM Input sampling filter.
*/
typedef enum
{
TIM_16B_InputCaptureInFilter_Alt0 = 0u, /*!< Filter swicther 0. */
TIM_16B_InputCaptureInFilter_Alt1 = 1u, /*!< Filter swicther 1. */
TIM_16B_InputCaptureInFilter_Alt2 = 2u, /*!< Filter swicther 2. */
TIM_16B_InputCaptureInFilter_Alt3 = 3u, /*!< Filter swicther 3. */
TIM_16B_InputCaptureInFilter_Alt4 = 4u, /*!< Filter swicther 4. */
TIM_16B_InputCaptureInFilter_Alt5 = 5u, /*!< Filter swicther 5. */
TIM_16B_InputCaptureInFilter_Alt6 = 6u, /*!< Filter swicther 6. */
TIM_16B_InputCaptureInFilter_Alt7 = 7u, /*!< Filter swicther 7. */
TIM_16B_InputCaptureInFilter_Alt8 = 8u, /*!< Filter swicther 8. */
TIM_16B_InputCaptureInFilter_Alt9 = 9u, /*!< Filter swicther 9. */
TIM_16B_InputCaptureInFilter_Alt10 = 10u, /*!< Filter swicther 10. */
TIM_16B_InputCaptureInFilter_Alt11 = 11u, /*!< Filter swicther 11. */
TIM_16B_InputCaptureInFilter_Alt12 = 12u, /*!< Filter swicther 12. */
TIM_16B_InputCaptureInFilter_Alt13 = 13u, /*!< Filter swicther 13. */
TIM_16B_InputCaptureInFilter_Alt14 = 14u, /*!< Filter swicther 14. */
TIM_16B_InputCaptureInFilter_Alt15 = 15u, /*!< Filter swicther 15. */
} TIM_16B_InputCaptureInFilter_Type;
/*!
* @brief TIM channel IO mode.
*/
typedef enum
{
TIM_16B_ChannelIOMode_Out = 0u, /*!< Channel output. */
TIM_16B_ChannelIOMode_In = 1u, /*!< Channel input, capture signal from direct channel. */
TIM_16B_ChannelIOMode_Alt2 = 2u, /*!< Channel input, capture signal from indirect channel. */
TIM_16B_ChannelIOMode_Alt3 = 3u, /*!< Channel input, capture signal from trc. */
} TIM_16B_ChannelIOMode_Type;
/*!
* @brief TIM external trigger input active edge selection.
*/
typedef enum
{
TIM_16B_ExtTriggerPinPolarity_Disable = 0u, /*!< Disable external trigger input. */
TIM_16B_ExtTriggerPinPolarity_Rising = 1u, /*!< Detect the rising edge from external trigger. */
TIM_16B_ExtTriggerPinPolarity_Falling = 2u, /*!< Detect the falling edge from external trigger. */
}TIM_16B_ExtTriggerPinPolarity_Type;
/*!
* @brief TIM external trigger active input times to drive counter.
*/
typedef enum
{
TIM_16B_ExtTriggerInDiv_OnEveryCapture = 0u, /*!< Every input call capture. */
TIM_16B_ExtTriggerInDiv_OnEach2Capture = 1u, /*!< Every two input call capture. */
TIM_16B_ExtTriggerInDiv_OnEach4Capture = 2u, /*!< Every four input call capture. */
TIM_16B_ExtTriggerInDiv_OnEach8Capture = 3u, /*!< Every eight input call capture. */
} TIM_16B_ExtTriggerInDiv_Type;
/*!
* @brief TIM external trigger sampling filter.
*/
typedef enum
{
TIM_16B_ExtTriggerInFilter_Alt0 = 0u, /*!< Filter swicther 0. */
TIM_16B_ExtTriggerInFilter_Alt1 = 1u, /*!< Filter swicther 1. */
TIM_16B_ExtTriggerInFilter_Alt2 = 2u, /*!< Filter swicther 2. */
TIM_16B_ExtTriggerInFilter_Alt3 = 3u, /*!< Filter swicther 3. */
TIM_16B_ExtTriggerInFilter_Alt4 = 4u, /*!< Filter swicther 4. */
TIM_16B_ExtTriggerInFilter_Alt5 = 5u, /*!< Filter swicther 5. */
TIM_16B_ExtTriggerInFilter_Alt6 = 6u, /*!< Filter swicther 6. */
TIM_16B_ExtTriggerInFilter_Alt7 = 7u, /*!< Filter swicther 7. */
TIM_16B_ExtTriggerInFilter_Alt8 = 8u, /*!< Filter swicther 8. */
TIM_16B_ExtTriggerInFilter_Alt9 = 9u, /*!< Filter swicther 9. */
TIM_16B_ExtTriggerInFilter_Alt10 = 10u, /*!< Filter swicther 10. */
TIM_16B_ExtTriggerInFilter_Alt11 = 11u, /*!< Filter swicther 11. */
TIM_16B_ExtTriggerInFilter_Alt12 = 12u, /*!< Filter swicther 12. */
TIM_16B_ExtTriggerInFilter_Alt13 = 13u, /*!< Filter swicther 13. */
TIM_16B_ExtTriggerInFilter_Alt14 = 14u, /*!< Filter swicther 14. */
TIM_16B_ExtTriggerInFilter_Alt15 = 15u, /*!< Filter swicther 15. */
} TIM_16B_ExtTriggerInFilter_Type;
/*!
* @brief TIM Dead area time step length.
*/
typedef enum
{
TIM_16B_DeadAreaStep_Alt0 = 0u, /*!< Dead area step = clock source step. */
TIM_16B_DeadAreaStep_Alt1 = 1u, /*!< Dead area step = 2 * clock source step. */
TIM_16B_DeadAreaStep_Alt2 = 2u, /*!< Dead area step = 4 * clock source step. */
} TIM_16B_DeadAreaStep_Type;
/*!
* @brief TIM master mode output signal source.
*/
typedef enum
{
TIM_16B_MasterOut_Alt0 = 0u, /*!< Software update period trigger signal works as master output. */
TIM_16B_MasterOut_Alt1 = 1u, /*!< Counter enable signal works as master output. */
TIM_16B_MasterOut_Alt2 = 2u, /*!< Update period event works as master output. */
TIM_16B_MasterOut_Alt3 = 3u, /*!< Channel capture or compare event works as master output. */
TIM_16B_MasterOut_Alt4 = 4u, /*!< Reference signal of channel 1 works as master output. */
TIM_16B_MasterOut_Alt5 = 5u, /*!< Reference signal of channel 2 works as master output. */
TIM_16B_MasterOut_Alt6 = 6u, /*!< Reference signal of channel 3 works as master output. */
TIM_16B_MasterOut_Alt7 = 7u, /*!< Reference signal of channel 4 works as master output. */
} TIM_16B_MasterOut_Type;
/*!
* @brief TIM slave mode input object source.
*/
typedef enum
{
TIM_16B_SlaveIn_Alt0 = 0u, /*!< Internal trigger 0. */
TIM_16B_SlaveIn_Alt1 = 1u, /*!< Internal trigger 1. */
TIM_16B_SlaveIn_Alt2 = 2u, /*!< Internal trigger 2.*/
TIM_16B_SlaveIn_Alt3 = 3u, /*!< Internal trigger 3. */
TIM_16B_SlaveIn_Alt4 = 4u, /*!< Edge detector of timer input channel 1. */
TIM_16B_SlaveIn_Alt5 = 5u, /*!< Timer input channel 1. */
TIM_16B_SlaveIn_Alt6 = 6u, /*!< Timer input channel 2. */
TIM_16B_SlaveIn_Alt7 = 7u, /*!< External trigger input. */
} TIM_16B_SlaveIn_Type;
/*!
* @brief TIM slave mode counter response.
*/
typedef enum
{
TIM_16B_SlaveResp_Disable = 0u, /*!< Disable the slave mode. */
TIM_16B_SlaveResp_Alt1 = 1u, /*!< Counting in encoder mode 1. */
TIM_16B_SlaveResp_Alt2 = 2u, /*!< Counting in encoder mode 2.*/
TIM_16B_SlaveResp_Alt3 = 3u, /*!< Counting in encoder mode 3. */
TIM_16B_SlaveResp_Alt4 = 4u, /*!< Reset counter. */
TIM_16B_SlaveResp_Alt5 = 5u, /*!< Counter treat the signal as a gate. */
TIM_16B_SlaveResp_Alt6 = 6u, /*!< Start the counter. */
TIM_16B_SlaveResp_Alt7 = 7u, /*!< Counter counts on rising edges. */
} TIM_16B_SlaveResp_Type;
/*!
* @brief TIM DMA Burst transfer base address.
*/
typedef enum
{
TIM_16B_DMABurstBaseAddr_Alt0 = 0u, /*!< Start from CR1 register. */
TIM_16B_DMABurstBaseAddr_Alt1 = 1u, /*!< Start from CR2 register. */
TIM_16B_DMABurstBaseAddr_Alt2 = 2u, /*!< Start from SMCR register. */
TIM_16B_DMABurstBaseAddr_Alt3 = 3u, /*!< Start from DIER register. */
TIM_16B_DMABurstBaseAddr_Alt4 = 4u, /*!< Start from SR register. */
TIM_16B_DMABurstBaseAddr_Alt5 = 5u, /*!< Start from EGR register. */
TIM_16B_DMABurstBaseAddr_Alt6 = 6u, /*!< Start from CCMR1 register. */
TIM_16B_DMABurstBaseAddr_Alt7 = 7u, /*!< Start from CCMR2 register. */
TIM_16B_DMABurstBaseAddr_Alt8 = 8u, /*!< Start from CCER register. */
TIM_16B_DMABurstBaseAddr_Alt9 = 9u, /*!< Start from CNT register. */
TIM_16B_DMABurstBaseAddr_Alt10 = 10u, /*!< Start from PSC register. */
TIM_16B_DMABurstBaseAddr_Alt11 = 11u, /*!< Start from ARR register. */
TIM_16B_DMABurstBaseAddr_Alt12 = 12u, /*!< Start from CCR1 register. */
TIM_16B_DMABurstBaseAddr_Alt13 = 13u, /*!< Start from CCR2 register. */
TIM_16B_DMABurstBaseAddr_Alt14 = 14u, /*!< Start from CCR3 register. */
TIM_16B_DMABurstBaseAddr_Alt15 = 15u, /*!< Start from CCR4 register. */
} TIM_16B_DMABurstBaseAddr_Type;
/*!
* @brief TIM DMA Burst transfer length.
*/
typedef enum
{
TIM_16B_DMABurstBaseLen_Alt0 = 0u, /*!< Sequentially visit 1 register from base register */
TIM_16B_DMABurstBaseLen_Alt1 = 1u, /*!< Sequentially visit 2 registers from base register */
TIM_16B_DMABurstBaseLen_Alt2 = 2u, /*!< Sequentially visit 3 registers from base register */
TIM_16B_DMABurstBaseLen_Alt3 = 3u, /*!< Sequentially visit 4 registers from base register */
TIM_16B_DMABurstBaseLen_Alt4 = 4u, /*!< Sequentially visit 5 registers from base register */
TIM_16B_DMABurstBaseLen_Alt5 = 5u, /*!< Sequentially visit 6 registers from base register */
TIM_16B_DMABurstBaseLen_Alt6 = 6u, /*!< Sequentially visit 7 registers from base register */
TIM_16B_DMABurstBaseLen_Alt7 = 7u, /*!< Sequentially visit 8 registers from base register */
TIM_16B_DMABurstBaseLen_Alt8 = 8u, /*!< Sequentially visit 9 registers from base register */
TIM_16B_DMABurstBaseLen_Alt9 = 9u, /*!< Sequentially visit 10 registers from base register */
TIM_16B_DMABurstBaseLen_Alt10 = 10u, /*!< Sequentially visit 11 registers from base register */
TIM_16B_DMABurstBaseLen_Alt11 = 11u, /*!< Sequentially visit 12 registers from base register */
TIM_16B_DMABurstBaseLen_Alt12 = 12u, /*!< Sequentially visit 13 registers from base register */
TIM_16B_DMABurstBaseLen_Alt13 = 13u, /*!< Sequentially visit 14 registers from base register */
TIM_16B_DMABurstBaseLen_Alt14 = 14u, /*!< Sequentially visit 15 registers from base register */
TIM_16B_DMABurstBaseLen_Alt15 = 15u, /*!< Sequentially visit 16 registers from base register */
TIM_16B_DMABurstBaseLen_Alt16 = 16u, /*!< Sequentially visit 17 registers from base register */
TIM_16B_DMABurstBaseLen_Alt17 = 17u, /*!< Sequentially visit 18 registers from base register */
} TIM_16B_DMABurstBaseLen_Type;
/*!
* @brief TIM encoder direction.
*/
typedef enum
{
TIM_16B_EncoderDirection_Forward = 0u, /*!< Encoder rotates in forward direction. */
TIM_16B_EncoderDirection_Backward = 1u, /*!< Encoder rotates in backward direction. */
} TIM_16B_EncoderDirection_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref TIM_16B_Init() to initialize the TIM module time base unit.
*/
typedef struct
{
uint32_t ClockFreqHz; /*!< Frequence of clock source for counter. */
uint32_t StepFreqHz; /*!< Step length value. Counter freq = ClockSourceFreqHz / (ClockSourceDiv+1). */
uint32_t Period; /*!< Counter counting period length, from 0 to Period. */
bool EnablePreloadPeriod; /*!< Enable the preload of period value. If enable, it will be updated in next period, otherwise immediately. */
TIM_16B_PeriodMode_Type PeriodMode; /*!< Counter working period times. */
TIM_16B_CountMode_Type CountMode; /*!< Counter count direction. */
} TIM_16B_Init_Type;
/*!
* @brief This type of structure instance is used to setup the output compare feature when calling the @ref TIM_16B_EnableOutputCompare() to enable the TIM module output compare channel.
*/
typedef struct
{
uint16_t ChannelValue; /*!< Value to be compared with counter. */
bool EnableFastOutput; /*!< Enable fast response to the trigger input event. */
bool EnablePreLoadChannelValue; /*!< Enable the preload of channel value. If enable, it will be updated in next period, otherwise immediately. */
TIM_16B_OutputCompareRefOut_Type RefOutMode; /*!< The reference output when counter matching the channel value. */
bool ClearRefOutOnExtTrigger; /*!< External trigger high will clear the reference. */
TIM_16B_PinPolarity_Type PinPolarity; /*!< Setup the output pin's polarity. */
} TIM_16B_OutputCompareConf_Type;
/*!
* @brief This type of structure instance is used to setup the input capture feature when calling the @ref TIM_16B_EnableInputCapture() to enable the TIM module input capture channel.
*/
typedef struct
{
TIM_16B_InputCaptureInDiv_Type InDiv; /*!< The division of filtered input. */
TIM_16B_InputCaptureInFilter_Type InFilter; /*!< The filter sampling time for initial input. */
TIM_16B_PinPolarity_Type PinPolarity; /*!< Setup the output pin's polarity. */
} TIM_16B_InputCaptureConf_Type;
/*!
* @brief This type of structure instance is used to setup the dead time feature when calling the @ref TIM_16B_EnableDeadArea() to enable the TIM module dead time area set.
*/
typedef struct
{
TIM_16B_DeadAreaStep_Type StepFreqHz; /*!< Dead time area step set. */
} TIM_16B_DeadAreaConf_Type;
/*!
* @brief This type of structure instance is used to setup the master mode configuration when calling the @ref TIM_16B_EnableMasterMode().
*/
typedef struct
{
TIM_16B_MasterOut_Type Out; /*!< Master mode output selection. */
bool EnableSync; /*!< Enable sychronize with slave timers. */
} TIM_16B_MasterModeConf_Type;
/*!
* @brief This type of structure instance is used to setup the slave mode configuration when calling the @ref TIM_16B_EnableSlaveMode().
*/
typedef struct
{
TIM_16B_SlaveIn_Type In; /*!< Input trigger selection for slave timer. */
TIM_16B_SlaveResp_Type Resp; /*!< Slave timer counter response for its input trigger. */
} TIM_16B_SlaveModeConf_Type;
/*!
* @brief This type of structure instance is used to setup the external trigger input configuration when calling the @ref TIM_16B_EnableExtTriggerIn().
*/
typedef struct
{
TIM_16B_ExtTriggerInDiv_Type InDiv; /*!< The division of filtered input. */
TIM_16B_ExtTriggerInFilter_Type InFilter; /*!< The filter sampling time for initial input. */
TIM_16B_ExtTriggerPinPolarity_Type PinPolarity; /*!< Setup the output pin's polarity. */
} TIM_16B_ExtTriggerInConf_Type;
/*!
* @brief This type of structure instance is used to setup the dma burst configuration when calling the @ref TIM_16B_EnableDMABurst().
*/
typedef struct
{
TIM_16B_DMABurstBaseAddr_Type BaseAddr; /*!< The base address to start transfer. */
TIM_16B_DMABurstBaseLen_Type Length; /*!< Length of sequential registers DMA burst visits. */
} TIM_16B_DMABurstConf_Type;
/*!
* @brief Set the timer's step for indicated TIM module.
*
* @param TIMx TIM_16B instance.
* @param init Pointer to the initialization structure. See to @ref TIM_16B_Init_Type.
* @return val 'true' to set the timer's step successfully, 'false' to fail because the invalid StepFreqHz.
*/
bool TIM_16B_Init(TIM_16B_Type * TIMx, TIM_16B_Init_Type * init);
/*!
* @brief Start counting.
*
* @param TIMx TIM_16B instance.
* @return None.
*/
void TIM_16B_Start(TIM_16B_Type * TIMx);
/*!
* @brief Stop counting immediately.
*
* @param TIMx TIM_16B instance.
* @return None.
*/
void TIM_16B_Stop(TIM_16B_Type * TIMx);
/*!
* @brief Get the indicated TIMx Counter value.
*
* @param TIMx TIM_16B_Type instance.
* @return The current value of the counter register.
*/
uint32_t TIM_16B_GetCounterValue(TIM_16B_Type * TIMx);
/*!
* @brief Clear the indicated TIMx Counter.
*
* @param TIMx TIM_16B_Type instance.
* @return None.
*/
void TIM_16B_ClearCounterValue(TIM_16B_Type * TIMx);
/*!
* @brief Enable the TIM_16B interrupts.
*
* @param TIMx TIM_16B_Type instance.
* @param interrupts Interrupts to be enabled.See to @ref TIM_16B_INT.
* @param enable 'true' to enable the indicated interrupts or DMAs, 'false' to disable the indicated interrupts or DMAs.
* @return None.
*/
void TIM_16B_EnableInterrupts(TIM_16B_Type * TIMx, uint32_t interrupts, bool enable);
/*!
* @brief Enable the TIM_16B DMAs.
*
* @param TIMx TIM_16B_Type instance.
* @param dmas DMA masks to be enabled. See to @ref TIM_16B_DMA.
* @param enable 'true' to enable the indicated interrupts or DMAs, 'false' to disable the indicated interrupts or DMAs.
* @return None.
*/
void TIM_16B_EnableDMA(TIM_16B_Type * TIMx, uint32_t dmas, bool enable);
/*!
* @brief Software trigger events to call interrupts or DMAs.
*
* Can simultaneously trigger multiple events.
*
* @param TIMx TIM_16B instance. See to @ref TIM_16B_SWTRG.
* @param swtrgs Trigger the events to generate interrupts.
*/
void TIM_16B_DoSwTrigger(TIM_16B_Type * TIMx, uint32_t swtrgs);
/*!
* @brief Get the status of the indicated timer.
*
* @param TIMx TIM_16B_Type instance.
* @return Interrupt status flags. See to @ref TIM_16B_INT_STATUS.
*/
uint32_t TIM_16B_GetInterruptStatus(TIM_16B_Type * TIMx);
/*!
* @brief Clear the status of indicated interrupt.
*
* @param TIMx TIM_16B_Type instance.
* @param status The required clear flag type. See to @ref TIM_16B_INT_STATUS.
* @return None.
*/
void TIM_16B_ClearInterruptStatus(TIM_16B_Type * TIMx, uint32_t status);
/*!
* @brief Enable the output compare feature of indicated timer channel.
*
* If need to change the IO mode of the working channel, channel must be disabled first, then modify.
*
* @param TIMx TIM_16B_Type instance.
* @param channel Output channel instance. See to @ref TIM_16B_CHANNEL_SELECTION.
* @param conf Pointer to the configuration structure. See to @ref TIM_16B_OutputCompareConf_Type.
* @return None.
*/
void TIM_16B_EnableOutputCompare(TIM_16B_Type * TIMx, uint32_t channel, TIM_16B_OutputCompareConf_Type * conf);
/*!
* @brief Enable the input capture feature of indicated timer channel.
*
* If need to change the IO mode of the working channel, channel must be disabled first, then modify.
*
* @param TIMx TIM_16B_Type instance.
* @param channel Input channel instance. See to @ref TIM_16B_CHANNEL_SELECTION.
* @param conf Pointer to the configuration structure. See to @ref TIM_16B_InputCaptureConf_Type.
* @return None.
*/
void TIM_16B_EnableInputCapture(TIM_16B_Type * TIMx, uint32_t channel, TIM_16B_InputCaptureConf_Type * conf);
/*!
* @brief Get the value of the indicated timer channel.
*
* When capture event happens, counter value will be kept in its indicated channel.
*
* @param TIMx TIM_16B_Type instance.
* @param channel Channel instance to get the value. See to @ref TIM_16B_CHANNEL_SELECTION.
* @return Value of the indiacted timer channel.
*/
uint16_t TIM_16B_GetChannelValue(TIM_16B_Type * TIMx, uint32_t channel);
/*!
* @brief Put the value into the indicated timer channel.
*
* When in output compare, channel value would be the compared with counter value.
*
* @param TIMx TIM_16B_Type instance.
* @param channel Channel instance to put the value. See to @ref TIM_16B_CHANNEL_SELECTION.
* @param value The value to be set in the indicated timer channel.
* @return None.
*/
void TIM_16B_PutChannelValue(TIM_16B_Type * TIMx, uint32_t channel, uint16_t value);
/*!
* @brief Enable the dead area of the indicated timer.
*
* @param TIMx TIM_16B_Type instance.
* @param conf Pointer to the configuration structure. See to @ref TIM_16B_DeadAreaConf_Type.
* @return None.
*/
void TIM_16B_EnableDeadArea(TIM_16B_Type * TIMx, TIM_16B_DeadAreaConf_Type * conf);
/*!
* @brief Enable the master mode of the indicated timer.
*
* Master mode transfer the timer signal to other timers.
*
* @param TIMx TIM_16B_Type instance.
* @param conf Pointer to the configuration structure. See to @ref TIM_16B_MasterModeConf_Type.
* @return None.
*/
void TIM_16B_EnableMasterMode(TIM_16B_Type * TIMx, TIM_16B_MasterModeConf_Type * conf);
/*!
* @brief Enable the slave mode of the indicated timer.
*
* Slave mode can control the working state of counter.
*
* @param TIMx TIM_16B_Type instance.
* @param conf Pointer to the configuration structure. See to @ref TIM_16B_SlaveModeConf_Type.
* @return None.
*/
void TIM_16B_EnableSlaveMode(TIM_16B_Type * TIMx, TIM_16B_SlaveModeConf_Type * conf);
/*!
* @brief Enable the external trigger input of the indicated counter.
*
* External trigger signal will trigger counter do addition.
* Its div and filter along with the counter StepFreqHz will affect.
*
* @param TIMx TIM_16B_Type instance.
* @param conf Pointer to the configuration structure. See to @ref TIM_16B_ExtTriggerInConf_Type.
* @return None.
*/
void TIM_16B_EnableExtTriggerIn(TIM_16B_Type * TIMx, TIM_16B_ExtTriggerInConf_Type * conf);
/*!
* @brief Enable the dma burst transfer of the indicated timer.
*
* @param TIMx TIM_16B_Type instance.
* @param conf Pointer to the configuration structure. See to @ref TIM_16B_DMABurstConf_Type.
* @return Address of DMA Burst transfer base register address.
*/
uint32_t TIM_16B_EnableDMABurst(TIM_16B_Type * TIMx, TIM_16B_DMABurstConf_Type * conf);
/*!
* @brief Get the encoder rotating direction and the counted encoder pulse times.
*
* @param TIMx TIM_16B_Type instance.
* @param value The counter value for pulse times.
* @return Encoder rotating direction. See to @ref TIM_16B_EncoderDirection_Type.
*/
TIM_16B_EncoderDirection_Type TIM_16B_GetEncoder(TIM_16B_Type * TIMx, uint32_t * value);
/*!
*@}
*/
#endif /* __HAL_TIM_16B_H__ */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_TIM_32B_H__
#define __HAL_TIM_32B_H__
#include "hal_common.h"
/*!
* @addtogroup TIM_32B
* @{
*/
/*!
* @brief TIM_32B driver version number.
*/
#define TIM_32B_DRIVER_VERSION 0u /*!< TIM_32B_0. */
/*!
* @addtogroup TIM_32B_CHANNEL_SELECTION
* @{
*/
#define TIM_32B_CHN_NUM (4u) /*!< The total number of TIM_32B channel. */
#define TIM_32B_CHN_1 (0u) /*!< The selection of TIM_32B Channel 1. */
#define TIM_32B_CHN_2 (1u) /*!< The selection of TIM_32B Channel 2. */
#define TIM_32B_CHN_3 (2u) /*!< The selection of TIM_32B Channel 3. */
#define TIM_32B_CHN_4 (3u) /*!< The selection of TIM_32B Channel 4. */
/*!
*@}
*/
/*!
* @addtogroup TIM_32B_INT
* @brief Enable interrupt.
* @{
*/
#define TIM_32B_INT_UPDATE_PERIOD (1u << 0u) /*!< Timer update period interrupt switchers. */
#define TIM_32B_INT_CHN1_EVENT (1u << 1u) /*!< Channel 1 event for output compare or input capture interrupt switchers. */
#define TIM_32B_INT_CHN2_EVENT (1u << 2u) /*!< Channel 2 event for output compare or input capture interrupt switchers. */
#define TIM_32B_INT_CHN3_EVENT (1u << 3u) /*!< Channel 3 event for output compare or input capture interrupt switchers. */
#define TIM_32B_INT_CHN4_EVENT (1u << 4u) /*!< Channel 4 event for output compare or input capture interrupt switchers. */
#define TIM_32B_INT_TRGOUT_EVENT (1u << 6u) /*!< Trigger out event interrupt switchers. */
/*!
* @}
*/
/*!
* @addtogroup TIM_32B_DMA
* @brief Enable DMA.
* @{
*/
#define TIM_32B_DMA_UPDATE_PERIOD (1u << 8u) /*!< Timer update period DMA switchers. */
#define TIM_32B_DMA_CHN1_EVENT (1u << 9u) /*!< Channel 1 event for output compare or input capture DMA switchers. */
#define TIM_32B_DMA_CHN2_EVENT (1u << 10u) /*!< Channel 2 event for output compare or input capture DMA switchers. */
#define TIM_32B_DMA_CHN3_EVENT (1u << 11u) /*!< Channel 3 event for output compare or input capture DMA switchers. */
#define TIM_32B_DMA_CHN4_EVENT (1u << 12u) /*!< Channel 4 event for output compare or input capture DMA switchers. */
#define TIM_32B_DMA_TRGOUT_EVENT (1u << 14u) /*!< Trigger out event DMA switchers. */
/*!
* @}
*/
/*!
* @addtogroup TIM_32B_INT_STATUS
* @brief Check interrupt status.
* @{
*/
#define TIM_32B_STATUS_UPDATE_PERIOD (1u << 0u) /*!< Timer update period interrupt flag. */
#define TIM_32B_STATUS_CHN1_EVENT (1u << 1u) /*!< Channel 1 event for output compare or input capture interrupt flag. */
#define TIM_32B_STATUS_CHN2_EVENT (1u << 2u) /*!< Channel 2 event for output compare or input capture interrupt flag. */
#define TIM_32B_STATUS_CHN3_EVENT (1u << 3u) /*!< Channel 3 event for output compare or input capture interrupt flag. */
#define TIM_32B_STATUS_CHN4_EVENT (1u << 4u) /*!< Channel 4 event for output compare or input capture interrupt flag. */
#define TIM_32B_STATUS_TRGOUT_EVENT (1u << 6u) /*!< Trigger out event interrupt flag. */
#define TIM_32B_STATUS_CHN1_OVER_EVENT (1u << 9u) /*!< Channel 1 event for output overcompare or input overcapture interrupt flag. */
#define TIM_32B_STATUS_CHN2_OVER_EVENT (1u << 10u) /*!< Channel 2 event for output overcompare or input overcapture interrupt flag. */
#define TIM_32B_STATUS_CHN3_OVER_EVENT (1u << 11u) /*!< Channel 3 event for output overcompare or input overcapture interrupt flag. */
#define TIM_32B_STATUS_CHN4_OVER_EVENT (1u << 12u) /*!< Channel 4 event for output overcompare or input overcapture interrupt flag. */
/*!
* @}
*/
/*!
* @addtogroup TIM_32B_SWTRG
* @brief Events to be triggered by software.
* @{
*/
#define TIM_32B_SWTRG_UPDATE_PERIOD (1u << 0u) /*!< Timer update period software trigger. */
#define TIM_32B_SWTRG_CHN1_EVENT (1u << 1u) /*!< Channel 1 event for output compare or input capture software trigger. */
#define TIM_32B_SWTRG_CHN2_EVENT (1u << 2u) /*!< Channel 2 event for output compare or input capture software trigger. */
#define TIM_32B_SWTRG_CHN3_EVENT (1u << 3u) /*!< Channel 3 event for output compare or input capture software trigger. */
#define TIM_32B_SWTRG_CHN4_EVENT (1u << 4u) /*!< Channel 4 event for output compare or input capture software trigger. */
#define TIM_32B_SWTRG_COM_EVENT (1u << 5u) /*!< COM event software trigger. */
#define TIM_32B_SWTRG_TRGOUT_EVENT (1u << 6u) /*!< Trigger out event software trigger. */
/*!
* @}
*/
/*!
* @brief Counter period working mode.
*/
typedef enum
{
TIM_32B_PeriodMode_Continuous = 0u, /*!< Counter works circularly once started. */
TIM_32B_PeriodMode_OneTimeRun = 1u, /*!< Counter only works one time once started. */
} TIM_32B_PeriodMode_Type;
/*!
* @brief Counter count direction.
*/
typedef enum
{
TIM_32B_CountMode_Increasing = 0u, /*!< Counter counts incrementally from 0 to period and generates an update. */
TIM_32B_CountMode_Decreasing = 1u, /*!< Counter counts decrementally from period to 0 and generates an update. */
TIM_32B_CountMode_CenterAligned1 = 2u, /*!< Counter counts center-aligned from 0 to period - 1 then from period to 0 and generates an update. */
TIM_32B_CountMode_CenterAligned2 = 3u, /*!< Counter counts center-aligned from 0 to period - 1 and generates an update then from period to 0. */
TIM_32B_CountMode_CenterAligned3 = 4u, /*!< Counter counts center-aligned from 0 to period - 1 and generates an update then from period to 0 and generates another update. */
} TIM_32B_CountMode_Type;
/*!
* @brief TIM output compare reference polairty event.
*/
typedef enum
{
TIM_32B_OutputCompareRefOut_None = 0u, /*!< Reference will not be changed. */
TIM_32B_OutputCompareRefOut_HighOnMatch = 1u, /*!< Reference will be high when counter value equals channel value. */
TIM_32B_OutputCompareRefOut_LowOnMatch = 2u, /*!< Reference will be low when counter value equals channel value. */
TIM_32B_OutputCompareRefOut_ToggleOnMatch = 3u, /*!< Reference will toggle. */
TIM_32B_OutputCompareRefOut_LowAlways = 4u, /*!< Reference will always be low. */
TIM_32B_OutputCompareRefOut_HighAlways = 5u, /*!< Reference will always be high. */
TIM_32B_OutputCompareRefOut_FallingEdgeOnMatch = 6u, /*!< PWM mode 1. */
TIM_32B_OutputCompareRefOut_RisingEdgeOnMatch = 7u, /*!< PWM mode 2. */
} TIM_32B_OutputCompareRefOut_Type;
/*!
* @brief TIM input capture active edge selection and output compare active polarity selection.
* | conf | TIM_32B_PinPolarity_Rising | TIM_32B_PinPolarity_Falling |
* | -------------- | -------------------------- | --------------------------- |
* | input capture | detects rising edge | detects falling edge |
* | output compare | high polarity is active | low polarity is active |
* | encoder mode | input remains | input reverses |
*/
typedef enum
{
TIM_32B_PinPolarity_Disable = 0u, /*!< Disable channel. */
TIM_32B_PinPolarity_Rising = 1u, /*!< See the table above. */
TIM_32B_PinPolarity_Falling = 2u, /*!< See the table above. */
TIM_32B_PinPolarity_RisingOrFalling = 3u, /*!< For input capture, detect both the rising and falling edge. */
}TIM_32B_PinPolarity_Type;
/*!
* @brief TIM Input active times to evoke capture.
*/
typedef enum
{
TIM_32B_InputCaptureInDiv_OnEveryCapture = 0u, /*!< Every input call capture. */
TIM_32B_InputCaptureInDiv_OnEach2Capture = 1u, /*!< Every two input call capture. */
TIM_32B_InputCaptureInDiv_OnEach4Capture = 2u, /*!< Every four input call capture. */
TIM_32B_InputCaptureInDiv_OnEach8Capture = 3u, /*!< Every eight input call capture. */
} TIM_32B_InputCaptureInDiv_Type;
/*!
* @brief TIM Input sampling filter.
*/
typedef enum
{
TIM_32B_InputCaptureInFilter_Alt0 = 0u, /*!< Filter swicther 0. */
TIM_32B_InputCaptureInFilter_Alt1 = 1u, /*!< Filter swicther 1. */
TIM_32B_InputCaptureInFilter_Alt2 = 2u, /*!< Filter swicther 2. */
TIM_32B_InputCaptureInFilter_Alt3 = 3u, /*!< Filter swicther 3. */
TIM_32B_InputCaptureInFilter_Alt4 = 4u, /*!< Filter swicther 4. */
TIM_32B_InputCaptureInFilter_Alt5 = 5u, /*!< Filter swicther 5. */
TIM_32B_InputCaptureInFilter_Alt6 = 6u, /*!< Filter swicther 6. */
TIM_32B_InputCaptureInFilter_Alt7 = 7u, /*!< Filter swicther 7. */
TIM_32B_InputCaptureInFilter_Alt8 = 8u, /*!< Filter swicther 8. */
TIM_32B_InputCaptureInFilter_Alt9 = 9u, /*!< Filter swicther 9. */
TIM_32B_InputCaptureInFilter_Alt10 = 10u, /*!< Filter swicther 10. */
TIM_32B_InputCaptureInFilter_Alt11 = 11u, /*!< Filter swicther 11. */
TIM_32B_InputCaptureInFilter_Alt12 = 12u, /*!< Filter swicther 12. */
TIM_32B_InputCaptureInFilter_Alt13 = 13u, /*!< Filter swicther 13. */
TIM_32B_InputCaptureInFilter_Alt14 = 14u, /*!< Filter swicther 14. */
TIM_32B_InputCaptureInFilter_Alt15 = 15u, /*!< Filter swicther 15. */
} TIM_32B_InputCaptureInFilter_Type;
/*!
* @brief TIM channel IO mode.
*/
typedef enum
{
TIM_32B_ChannelIOMode_Out = 0u, /*!< Channel output. */
TIM_32B_ChannelIOMode_In = 1u, /*!< Channel input, capture signal from direct channel. */
TIM_32B_ChannelIOMode_Alt2 = 2u, /*!< Channel input, capture signal from indirect channel. */
TIM_32B_ChannelIOMode_Alt3 = 3u, /*!< Channel input, capture signal from trc. */
} TIM_32B_ChannelIOMode_Type;
/*!
* @brief TIM external trigger input active edge selection.
*/
typedef enum
{
TIM_32B_ExtTriggerPinPolarity_Disable = 0u, /*!< Disable external trigger input. */
TIM_32B_ExtTriggerPinPolarity_Rising = 1u, /*!< Detect the rising edge from external trigger. */
TIM_32B_ExtTriggerPinPolarity_Falling = 2u, /*!< Detect the falling edge from external trigger. */
}TIM_32B_ExtTriggerPinPolarity_Type;
/*!
* @brief TIM external trigger active input times to drive counter.
*/
typedef enum
{
TIM_32B_ExtTriggerInDiv_OnEveryCapture = 0u, /*!< Every input call capture. */
TIM_32B_ExtTriggerInDiv_OnEach2Capture = 1u, /*!< Every two input call capture. */
TIM_32B_ExtTriggerInDiv_OnEach4Capture = 2u, /*!< Every four input call capture. */
TIM_32B_ExtTriggerInDiv_OnEach8Capture = 3u, /*!< Every eight input call capture. */
} TIM_32B_ExtTriggerInDiv_Type;
/*!
* @brief TIM external trigger sampling filter.
*/
typedef enum
{
TIM_32B_ExtTriggerInFilter_Alt0 = 0u, /*!< Filter swicther 0. */
TIM_32B_ExtTriggerInFilter_Alt1 = 1u, /*!< Filter swicther 1. */
TIM_32B_ExtTriggerInFilter_Alt2 = 2u, /*!< Filter swicther 2. */
TIM_32B_ExtTriggerInFilter_Alt3 = 3u, /*!< Filter swicther 3. */
TIM_32B_ExtTriggerInFilter_Alt4 = 4u, /*!< Filter swicther 4. */
TIM_32B_ExtTriggerInFilter_Alt5 = 5u, /*!< Filter swicther 5. */
TIM_32B_ExtTriggerInFilter_Alt6 = 6u, /*!< Filter swicther 6. */
TIM_32B_ExtTriggerInFilter_Alt7 = 7u, /*!< Filter swicther 7. */
TIM_32B_ExtTriggerInFilter_Alt8 = 8u, /*!< Filter swicther 8. */
TIM_32B_ExtTriggerInFilter_Alt9 = 9u, /*!< Filter swicther 9. */
TIM_32B_ExtTriggerInFilter_Alt10 = 10u, /*!< Filter swicther 10. */
TIM_32B_ExtTriggerInFilter_Alt11 = 11u, /*!< Filter swicther 11. */
TIM_32B_ExtTriggerInFilter_Alt12 = 12u, /*!< Filter swicther 12. */
TIM_32B_ExtTriggerInFilter_Alt13 = 13u, /*!< Filter swicther 13. */
TIM_32B_ExtTriggerInFilter_Alt14 = 14u, /*!< Filter swicther 14. */
TIM_32B_ExtTriggerInFilter_Alt15 = 15u, /*!< Filter swicther 15. */
} TIM_32B_ExtTriggerInFilter_Type;
/*!
* @brief TIM Dead area time step length.
*/
typedef enum
{
TIM_32B_DeadAreaStep_Alt0 = 0u, /*!< Dead area step = clock source step. */
TIM_32B_DeadAreaStep_Alt1 = 1u, /*!< Dead area step = 2 * clock source step. */
TIM_32B_DeadAreaStep_Alt2 = 2u, /*!< Dead area step = 4 * clock source step. */
} TIM_32B_DeadAreaStep_Type;
/*!
* @brief TIM master mode output signal source.
*/
typedef enum
{
TIM_32B_MasterOut_Alt0 = 0u, /*!< Software update period trigger signal works as master output. */
TIM_32B_MasterOut_Alt1 = 1u, /*!< Counter enable signal works as master output. */
TIM_32B_MasterOut_Alt2 = 2u, /*!< Update period event works as master output. */
TIM_32B_MasterOut_Alt3 = 3u, /*!< Channel capture or compare event works as master output. */
TIM_32B_MasterOut_Alt4 = 4u, /*!< Reference signal of channel 1 works as master output. */
TIM_32B_MasterOut_Alt5 = 5u, /*!< Reference signal of channel 2 works as master output. */
TIM_32B_MasterOut_Alt6 = 6u, /*!< Reference signal of channel 3 works as master output. */
TIM_32B_MasterOut_Alt7 = 7u, /*!< Reference signal of channel 4 works as master output. */
} TIM_32B_MasterOut_Type;
/*!
* @brief TIM slave mode input object source.
*/
typedef enum
{
TIM_32B_SlaveIn_Alt0 = 0u, /*!< Internal trigger 0. */
TIM_32B_SlaveIn_Alt1 = 1u, /*!< Internal trigger 1. */
TIM_32B_SlaveIn_Alt2 = 2u, /*!< Internal trigger 2.*/
TIM_32B_SlaveIn_Alt3 = 3u, /*!< Internal trigger 3. */
TIM_32B_SlaveIn_Alt4 = 4u, /*!< Edge detector of timer input channel 1. */
TIM_32B_SlaveIn_Alt5 = 5u, /*!< Timer input channel 1. */
TIM_32B_SlaveIn_Alt6 = 6u, /*!< Timer input channel 2. */
TIM_32B_SlaveIn_Alt7 = 7u, /*!< External trigger input. */
} TIM_32B_SlaveIn_Type;
/*!
* @brief TIM slave mode counter response.
*/
typedef enum
{
TIM_32B_SlaveResp_Disable = 0u, /*!< Disable the slave mode. */
TIM_32B_SlaveResp_Alt1 = 1u, /*!< Counting in encoder mode 1. */
TIM_32B_SlaveResp_Alt2 = 2u, /*!< Counting in encoder mode 2.*/
TIM_32B_SlaveResp_Alt3 = 3u, /*!< Counting in encoder mode 3. */
TIM_32B_SlaveResp_Alt4 = 4u, /*!< Reset counter. */
TIM_32B_SlaveResp_Alt5 = 5u, /*!< Counter treat the signal as a gate. */
TIM_32B_SlaveResp_Alt6 = 6u, /*!< Start the counter. */
TIM_32B_SlaveResp_Alt7 = 7u, /*!< Counter counts on rising edges. */
} TIM_32B_SlaveResp_Type;
/*!
* @brief TIM DMA Burst transfer base address.
*/
typedef enum
{
TIM_32B_DMABurstBaseAddr_Alt0 = 0u, /*!< Start from CR1 register. */
TIM_32B_DMABurstBaseAddr_Alt1 = 1u, /*!< Start from CR2 register. */
TIM_32B_DMABurstBaseAddr_Alt2 = 2u, /*!< Start from SMCR register. */
TIM_32B_DMABurstBaseAddr_Alt3 = 3u, /*!< Start from DIER register. */
TIM_32B_DMABurstBaseAddr_Alt4 = 4u, /*!< Start from SR register. */
TIM_32B_DMABurstBaseAddr_Alt5 = 5u, /*!< Start from EGR register. */
TIM_32B_DMABurstBaseAddr_Alt6 = 6u, /*!< Start from CCMR1 register. */
TIM_32B_DMABurstBaseAddr_Alt7 = 7u, /*!< Start from CCMR2 register. */
TIM_32B_DMABurstBaseAddr_Alt8 = 8u, /*!< Start from CCER register. */
TIM_32B_DMABurstBaseAddr_Alt9 = 9u, /*!< Start from CNT register. */
TIM_32B_DMABurstBaseAddr_Alt10 = 10u, /*!< Start from PSC register. */
TIM_32B_DMABurstBaseAddr_Alt11 = 11u, /*!< Start from ARR register. */
TIM_32B_DMABurstBaseAddr_Alt12 = 12u, /*!< Start from CCR1 register. */
TIM_32B_DMABurstBaseAddr_Alt13 = 13u, /*!< Start from CCR2 register. */
TIM_32B_DMABurstBaseAddr_Alt14 = 14u, /*!< Start from CCR3 register. */
TIM_32B_DMABurstBaseAddr_Alt15 = 15u, /*!< Start from CCR4 register. */
} TIM_32B_DMABurstBaseAddr_Type;
/*!
* @brief TIM DMA Burst transfer length.
*/
typedef enum
{
TIM_32B_DMABurstBaseLen_Alt0 = 0u, /*!< Sequentially visit 1 register from base register */
TIM_32B_DMABurstBaseLen_Alt1 = 1u, /*!< Sequentially visit 2 registers from base register */
TIM_32B_DMABurstBaseLen_Alt2 = 2u, /*!< Sequentially visit 3 registers from base register */
TIM_32B_DMABurstBaseLen_Alt3 = 3u, /*!< Sequentially visit 4 registers from base register */
TIM_32B_DMABurstBaseLen_Alt4 = 4u, /*!< Sequentially visit 5 registers from base register */
TIM_32B_DMABurstBaseLen_Alt5 = 5u, /*!< Sequentially visit 6 registers from base register */
TIM_32B_DMABurstBaseLen_Alt6 = 6u, /*!< Sequentially visit 7 registers from base register */
TIM_32B_DMABurstBaseLen_Alt7 = 7u, /*!< Sequentially visit 8 registers from base register */
TIM_32B_DMABurstBaseLen_Alt8 = 8u, /*!< Sequentially visit 9 registers from base register */
TIM_32B_DMABurstBaseLen_Alt9 = 9u, /*!< Sequentially visit 10 registers from base register */
TIM_32B_DMABurstBaseLen_Alt10 = 10u, /*!< Sequentially visit 11 registers from base register */
TIM_32B_DMABurstBaseLen_Alt11 = 11u, /*!< Sequentially visit 12 registers from base register */
TIM_32B_DMABurstBaseLen_Alt12 = 12u, /*!< Sequentially visit 13 registers from base register */
TIM_32B_DMABurstBaseLen_Alt13 = 13u, /*!< Sequentially visit 14 registers from base register */
TIM_32B_DMABurstBaseLen_Alt14 = 14u, /*!< Sequentially visit 15 registers from base register */
TIM_32B_DMABurstBaseLen_Alt15 = 15u, /*!< Sequentially visit 16 registers from base register */
TIM_32B_DMABurstBaseLen_Alt16 = 16u, /*!< Sequentially visit 17 registers from base register */
TIM_32B_DMABurstBaseLen_Alt17 = 17u, /*!< Sequentially visit 18 registers from base register */
} TIM_32B_DMABurstBaseLen_Type;
/*!
* @brief TIM encoder direction.
*/
typedef enum
{
TIM_32B_EncoderDirection_Forward = 0u, /*!< Encoder rotates in forward direction. */
TIM_32B_EncoderDirection_Backward = 1u, /*!< Encoder rotates in backward direction. */
} TIM_32B_EncoderDirection_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref TIM_32B_Init() to initialize the TIM module time base unit.
*/
typedef struct
{
uint32_t ClockFreqHz; /*!< Frequence of clock source for counter. */
uint32_t StepFreqHz; /*!< Step length value. Counter freq = ClockSourceFreqHz / (ClockSourceDiv+1). */
uint32_t Period; /*!< Counter counting period length, from 0 to Period. */
bool EnablePreloadPeriod; /*!< Enable the preload of period value. If enable, it will be updated in next period, otherwise immediately. */
TIM_32B_PeriodMode_Type PeriodMode; /*!< Counter working period times. */
TIM_32B_CountMode_Type CountMode; /*!< Counter count direction. */
} TIM_32B_Init_Type;
/*!
* @brief This type of structure instance is used to setup the output compare feature when calling the @ref TIM_32B_EnableOutputCompare() to enable the TIM module output compare channel.
*/
typedef struct
{
uint32_t ChannelValue; /*!< Value to be compared with counter. */
bool EnableFastOutput; /*!< Enable fast response to the trigger input event. */
bool EnablePreLoadChannelValue; /*!< Enable the preload of channel value. If enable, it will be updated in next period, otherwise immediately. */
TIM_32B_OutputCompareRefOut_Type RefOutMode; /*!< The reference output when counter matching the channel value. */
bool ClearRefOutOnExtTrigger; /*!< External trigger high will clear the reference. */
TIM_32B_PinPolarity_Type PinPolarity; /*!< Setup the output pin's polarity. */
} TIM_32B_OutputCompareConf_Type;
/*!
* @brief This type of structure instance is used to setup the input capture feature when calling the @ref TIM_32B_EnableInputCapture() to enable the TIM module input capture channel.
*/
typedef struct
{
TIM_32B_InputCaptureInDiv_Type InDiv; /*!< The division of filtered input. */
TIM_32B_InputCaptureInFilter_Type InFilter; /*!< The filter sampling time for initial input. */
TIM_32B_PinPolarity_Type PinPolarity; /*!< Setup the output pin's polarity. */
} TIM_32B_InputCaptureConf_Type;
/*!
* @brief This type of structure instance is used to setup the dead time feature when calling the @ref TIM_32B_EnableDeadArea() to enable the TIM module dead time area set.
*/
typedef struct
{
TIM_32B_DeadAreaStep_Type StepFreqHz; /*!< Dead time area step set. */
} TIM_32B_DeadAreaConf_Type;
/*!
* @brief This type of structure instance is used to setup the master mode configuration when calling the @ref TIM_32B_EnableMasterMode().
*/
typedef struct
{
TIM_32B_MasterOut_Type Out; /*!< Master mode output selection. */
bool EnableSync; /*!< Enable sychronize with slave timers. */
} TIM_32B_MasterModeConf_Type;
/*!
* @brief This type of structure instance is used to setup the slave mode configuration when calling the @ref TIM_32B_EnableSlaveMode().
*/
typedef struct
{
TIM_32B_SlaveIn_Type In; /*!< Input trigger selection for slave timer. */
TIM_32B_SlaveResp_Type Resp; /*!< Slave timer counter response for its input trigger. */
} TIM_32B_SlaveModeConf_Type;
/*!
* @brief This type of structure instance is used to setup the external trigger input configuration when calling the @ref TIM_32B_EnableExtTriggerIn().
*/
typedef struct
{
TIM_32B_ExtTriggerInDiv_Type InDiv; /*!< The division of filtered input. */
TIM_32B_ExtTriggerInFilter_Type InFilter; /*!< The filter sampling time for initial input. */
TIM_32B_ExtTriggerPinPolarity_Type PinPolarity; /*!< Setup the output pin's polarity. */
} TIM_32B_ExtTriggerInConf_Type;
/*!
* @brief This type of structure instance is used to setup the dma burst configuration when calling the @ref TIM_32B_EnableDMABurst().
*/
typedef struct
{
TIM_32B_DMABurstBaseAddr_Type BaseAddr; /*!< The base address to start transfer. */
TIM_32B_DMABurstBaseLen_Type Length; /*!< Length of sequential registers DMA burst visits. */
} TIM_32B_DMABurstConf_Type;
/*!
* @brief Set the timer's step for indicated TIM module.
*
* @param TIMx TIM_32B instance.
* @param init Pointer to the initialization structure. See to @ref TIM_32B_Init_Type.
* @return val 'true' to set the timer's step successfully, 'false' to fail because the invalid StepFreqHz.
*/
bool TIM_32B_Init(TIM_32B_Type * TIMx, TIM_32B_Init_Type * init);
/*!
* @brief Start counting.
*
* @param TIMx TIM_32B instance.
* @return None.
*/
void TIM_32B_Start(TIM_32B_Type * TIMx);
/*!
* @brief Stop counting immediately.
*
* @param TIMx TIM_32B instance.
* @return None.
*/
void TIM_32B_Stop(TIM_32B_Type * TIMx);
/*!
* @brief Get the indicated TIMx Counter value.
*
* @param TIMx TIM_32B_Type instance.
* @return The current value of the counter register.
*/
uint32_t TIM_32B_GetCounterValue(TIM_32B_Type * TIMx);
/*!
* @brief Clear the indicated TIMx Counter.
*
* @param TIMx TIM_32B_Type instance.
* @return None.
*/
void TIM_32B_ClearCounterValue(TIM_32B_Type * TIMx);
/*!
* @brief Enable the TIM_32B interrupts.
*
* @param TIMx TIM_32B_Type instance.
* @param interrupts Interrupts to be enabled.See to @ref TIM_32B_INT.
* @param enable 'true' to enable the indicated interrupts or DMAs, 'false' to disable the indicated interrupts or DMAs.
* @return None.
*/
void TIM_32B_EnableInterrupts(TIM_32B_Type * TIMx, uint32_t interrupts, bool enable);
/*!
* @brief Enable the TIM_32B DMAs.
*
* @param TIMx TIM_32B_Type instance.
* @param dmas DMA masks to be enabled. See to @ref TIM_32B_DMA.
* @param enable 'true' to enable the indicated interrupts or DMAs, 'false' to disable the indicated interrupts or DMAs.
* @return None.
*/
void TIM_32B_EnableDMA(TIM_32B_Type * TIMx, uint32_t dmas, bool enable);
/*!
* @brief Software trigger events to call interrupts or DMAs.
*
* Can simultaneously trigger multiple events.
*
* @param TIMx TIM_32B instance. See to @ref TIM_32B_SWTRG.
* @param swtrgs Trigger the events to generate interrupts.
*/
void TIM_32B_DoSwTrigger(TIM_32B_Type * TIMx, uint32_t swtrgs);
/*!
* @brief Get the status of the indicated timer.
*
* @param TIMx TIM_32B_Type instance.
* @return Interrupt status flags. See to @ref TIM_32B_INT_STATUS.
*/
uint32_t TIM_32B_GetInterruptStatus(TIM_32B_Type * TIMx);
/*!
* @brief Clear the status of indicated interrupt.
*
* @param TIMx TIM_32B_Type instance.
* @param status The required clear flag type. See to @ref TIM_32B_INT_STATUS.
* @return None.
*/
void TIM_32B_ClearInterruptStatus(TIM_32B_Type * TIMx, uint32_t status);
/*!
* @brief Enable the output compare feature of indicated timer channel.
*
* If need to change the IO mode of the working channel, channel must be disabled first, then modify.
*
* @param TIMx TIM_32B_Type instance.
* @param channel Output channel instance. See to @ref TIM_32B_CHANNEL_SELECTION.
* @param conf Pointer to the configuration structure. See to @ref TIM_32B_OutputCompareConf_Type.
* @return None.
*/
void TIM_32B_EnableOutputCompare(TIM_32B_Type * TIMx, uint32_t channel, TIM_32B_OutputCompareConf_Type * conf);
/*!
* @brief Enable the input capture feature of indicated timer channel.
*
* If need to change the IO mode of the working channel, channel must be disabled first, then modify.
*
* @param TIMx TIM_32B_Type instance.
* @param channel Input channel instance. See to @ref TIM_32B_CHANNEL_SELECTION.
* @param conf Pointer to the configuration structure. See to @ref TIM_32B_InputCaptureConf_Type.
* @return None.
*/
void TIM_32B_EnableInputCapture(TIM_32B_Type * TIMx, uint32_t channel, TIM_32B_InputCaptureConf_Type * conf);
/*!
* @brief Get the value of the indicated timer channel.
*
* When capture event happens, counter value will be kept in its indicated channel.
*
* @param TIMx TIM_32B_Type instance.
* @param channel Channel instance to get the value. See to @ref TIM_32B_CHANNEL_SELECTION.
* @return Value of the indiacted timer channel.
*/
uint32_t TIM_32B_GetChannelValue(TIM_32B_Type * TIMx, uint32_t channel);
/*!
* @brief Put the value into the indicated timer channel.
*
* When in output compare, channel value would be the compared with counter value.
*
* @param TIMx TIM_32B_Type instance.
* @param channel Channel instance to put the value. See to @ref TIM_32B_CHANNEL_SELECTION.
* @param value The value to be set in the indicated timer channel.
* @return None.
*/
void TIM_32B_PutChannelValue(TIM_32B_Type * TIMx, uint32_t channel, uint32_t value);
/*!
* @brief Enable the dead area of the indicated timer.
*
* @param TIMx TIM_32B_Type instance.
* @param conf Pointer to the configuration structure. See to @ref TIM_32B_DeadAreaConf_Type.
* @return None.
*/
void TIM_32B_EnableDeadArea(TIM_32B_Type * TIMx, TIM_32B_DeadAreaConf_Type * conf);
/*!
* @brief Enable the master mode of the indicated timer.
*
* Master mode transfer the timer signal to other timers.
*
* @param TIMx TIM_32B_Type instance.
* @param conf Pointer to the configuration structure. See to @ref TIM_32B_MasterModeConf_Type.
* @return None.
*/
void TIM_32B_EnableMasterMode(TIM_32B_Type * TIMx, TIM_32B_MasterModeConf_Type * conf);
/*!
* @brief Enable the slave mode of the indicated timer.
*
* Slave mode can control the working state of counter.
*
* @param TIMx TIM_32B_Type instance.
* @param conf Pointer to the configuration structure. See to @ref TIM_32B_SlaveModeConf_Type.
* @return None.
*/
void TIM_32B_EnableSlaveMode(TIM_32B_Type * TIMx, TIM_32B_SlaveModeConf_Type * conf);
/*!
* @brief Enable the external trigger input of the indicated counter.
*
* External trigger signal will trigger counter do addition.
* Its div and filter along with the counter StepFreqHz will affect.
*
* @param TIMx TIM_32B_Type instance.
* @param conf Pointer to the configuration structure. See to @ref TIM_32B_ExtTriggerInConf_Type.
* @return None.
*/
void TIM_32B_EnableExtTriggerIn(TIM_32B_Type * TIMx, TIM_32B_ExtTriggerInConf_Type * conf);
/*!
* @brief Enable the dma burst transfer of the indicated timer.
*
* @param TIMx TIM_32B_Type instance.
* @param conf Pointer to the configuration structure. See to @ref TIM_32B_DMABurstConf_Type.
* @return Address of DMA Burst transfer base register address.
*/
uint32_t TIM_32B_EnableDMABurst(TIM_32B_Type * TIMx, TIM_32B_DMABurstConf_Type * conf);
/*!
* @brief Get the encoder rotating direction and the counted encoder pulse times.
*
* @param TIMx TIM_32B_Type instance.
* @param value The counter value for pulse times.
* @return Encoder rotating direction. See to @ref TIM_32B_EncoderDirection_Type.
*/
TIM_32B_EncoderDirection_Type TIM_32B_GetEncoder(TIM_32B_Type * TIMx, uint32_t * value);
/*!
*@}
*/
#endif /* __HAL_TIM_32B_H__ */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_TIM_ADV_H__
#define __HAL_TIM_ADV_H__
#include "hal_common.h"
/*!
* @addtogroup TIM_ADV
* @{
*/
/*!
* @brief TIM_ADV driver version number.
*/
#define TIM_ADV_DRIVER_VERSION 0u /*!< TIM_ADV_0. */
/*!
* @addtogroup TIM_ADV_CHANNEL_SELECTION
* @{
*/
#define TIM_ADV_CHN_NUM (5u) /*!< The total number of TIM_ADV channel. */
#define TIM_ADV_CHN_1 (0u) /*!< The selection of TIM_ADV Channel 1. */
#define TIM_ADV_CHN_2 (1u) /*!< The selection of TIM_ADV Channel 2. */
#define TIM_ADV_CHN_3 (2u) /*!< The selection of TIM_ADV Channel 3. */
#define TIM_ADV_CHN_4 (3u) /*!< The selection of TIM_ADV Channel 4. */
#define TIM_ADV_CHN_5 (4u) /*!< The selection of TIM_ADV Channel 5. */
/*!
*@}
*/
/*!
* @addtogroup TIM_ADV_INT
* @brief Enable interrupt.
* @{
*/
#define TIM_ADV_INT_UPDATE_PERIOD (1u << 0u) /*!< Timer update period interrupt switchers. */
#define TIM_ADV_INT_CHN1_EVENT (1u << 1u) /*!< Channel 1 event for output compare or input capture interrupt switchers. */
#define TIM_ADV_INT_CHN2_EVENT (1u << 2u) /*!< Channel 2 event for output compare or input capture interrupt switchers. */
#define TIM_ADV_INT_CHN3_EVENT (1u << 3u) /*!< Channel 3 event for output compare or input capture interrupt switchers. */
#define TIM_ADV_INT_CHN4_EVENT (1u << 4u) /*!< Channel 4 event for output compare or input capture interrupt switchers. */
#define TIM_ADV_INT_COM_EVENT (1u << 5u) /*!< Channel complementary pwm commutation interrupt switchers. */
#define TIM_ADV_INT_TRGOUT_EVENT (1u << 6u) /*!< Trigger out event interrupt switchers. */
#define TIM_ADV_INT_BREAK_EVENT (1u << 7u) /*!< Break event interrupt switchers. */
#define TIM_ADV_INT_CH5_EVENT (1u << 16u) /*!< Channel 5 event for output compare or input capture interrupt switchers. */
/*!
* @}
*/
/*!
* @addtogroup TIM_ADV_DMA
* @brief Enable DMA.
* @{
*/
#define TIM_ADV_DMA_UPDATE_PERIOD (1u << 8u) /*!< Timer update period DMA switchers. */
#define TIM_ADV_DMA_CHN1_EVENT (1u << 9u) /*!< Channel 1 event for output compare or input capture DMA switchers. */
#define TIM_ADV_DMA_CHN2_EVENT (1u << 10u) /*!< Channel 2 event for output compare or input capture DMA switchers. */
#define TIM_ADV_DMA_CHN3_EVENT (1u << 11u) /*!< Channel 3 event for output compare or input capture DMA switchers. */
#define TIM_ADV_DMA_CHN4_EVENT (1u << 12u) /*!< Channel 4 event for output compare or input capture DMA switchers. */
#define TIM_ADV_DMA_COM_EVENT (1u << 13u) /*!< Channel complementary pwm commutation interrupt switchers. */
#define TIM_ADV_DMA_TRGOUT_EVENT (1u << 14u) /*!< Trigger out event DMA switchers. */
/*!
* @}
*/
/*!
* @addtogroup TIM_ADV_INT_STATUS
* @brief Check interrupt status.
* @{
*/
#define TIM_ADV_STATUS_UPDATE_PERIOD (1u << 0u) /*!< Timer update period interrupt flag. */
#define TIM_ADV_STATUS_CHN1_EVENT (1u << 1u) /*!< Channel 1 event for output compare or input capture interrupt flag. */
#define TIM_ADV_STATUS_CHN2_EVENT (1u << 2u) /*!< Channel 2 event for output compare or input capture interrupt flag. */
#define TIM_ADV_STATUS_CHN3_EVENT (1u << 3u) /*!< Channel 3 event for output compare or input capture interrupt flag. */
#define TIM_ADV_STATUS_CHN4_EVENT (1u << 4u) /*!< Channel 4 event for output compare or input capture interrupt flag. */
#define TIM_ADV_STATUS_COM_EVENT (1u << 5u) /*!< Channel complementary pwm commutation interrupt flag. */
#define TIM_ADV_STATUS_TRGOUT_EVENT (1u << 6u) /*!< Trigger out event interrupt flag. */
#define TIM_ADV_STATUS_BREAK_EVENT (1u << 7u) /*!< Break event interrupt flag. */
#define TIM_ADV_STATUS_CHN1_OVER_EVENT (1u << 9u) /*!< Channel 1 event for output overcompare or input overcapture interrupt flag. */
#define TIM_ADV_STATUS_CHN2_OVER_EVENT (1u << 10u) /*!< Channel 2 event for output overcompare or input overcapture interrupt flag. */
#define TIM_ADV_STATUS_CHN3_OVER_EVENT (1u << 11u) /*!< Channel 3 event for output overcompare or input overcapture interrupt flag. */
#define TIM_ADV_STATUS_CHN4_OVER_EVENT (1u << 12u) /*!< Channel 4 event for output overcompare or input overcapture interrupt flag. */
#define TIM_ADV_STATUS_CHN5_EVENT (1u << 16u) /*!< Channel 5 event for output compare or input capture interrupt flag. */
/*!
* @}
*/
/*!
* @addtogroup TIM_ADV_SWTRG
* @brief Events to be triggered by software.
* @{
*/
#define TIM_ADV_SWTRG_UPDATE_PERIOD (1u << 0u) /*!< Timer update period software trigger. */
#define TIM_ADV_SWTRG_CHN1_EVENT (1u << 1u) /*!< Channel 1 event for output compare or input capture software trigger. */
#define TIM_ADV_SWTRG_CHN2_EVENT (1u << 2u) /*!< Channel 2 event for output compare or input capture software trigger. */
#define TIM_ADV_SWTRG_CHN3_EVENT (1u << 3u) /*!< Channel 3 event for output compare or input capture software trigger. */
#define TIM_ADV_SWTRG_CHN4_EVENT (1u << 4u) /*!< Channel 4 event for output compare or input capture software trigger. */
#define TIM_ADV_SWTRG_COM_EVENT (1u << 5u) /*!< Channel complementary pwm commutation software trigger. */
#define TIM_ADV_SWTRG_TRGOUT_EVENT (1u << 6u) /*!< Trigger out event software trigger. */
#define TIM_ADV_SWTRG_BREAK_EVENT (1u << 7u) /*!< Break event software trigger. */
#define TIM_ADV_SWTRG_CHN5_EVENT (1u << 16u) /*!< Channel 5 event for output compare or input capture software trigger. */
/*!
* @}
*/
/*!
* @brief Counter period working mode.
*/
typedef enum
{
TIM_ADV_PeriodMode_Continuous = 0u, /*!< Counter works circularly once started. */
TIM_ADV_PeriodMode_OneTimeRun = 1u, /*!< Counter only works one time once started. */
} TIM_ADV_PeriodMode_Type;
/*!
* @brief Counter count direction.
*/
typedef enum
{
TIM_ADV_CountMode_Increasing = 0u, /*!< Counter counts incrementally from 0 to period and generates an update. */
TIM_ADV_CountMode_Decreasing = 1u, /*!< Counter counts decrementally from period to 0 and generates an update. */
TIM_ADV_CountMode_CenterAligned1 = 2u, /*!< Counter counts center-aligned from 0 to period - 1 then from period to 0 and generates an update. */
TIM_ADV_CountMode_CenterAligned2 = 3u, /*!< Counter counts center-aligned from 0 to period - 1 and generates an update then from period to 0. */
TIM_ADV_CountMode_CenterAligned3 = 4u, /*!< Counter counts center-aligned from 0 to period - 1 and generates an update then from period to 0 and generates another update. */
} TIM_ADV_CountMode_Type;
/*!
* @brief TIM output compare reference polairty event.
*/
typedef enum
{
TIM_ADV_OutputCompareRefOut_None = 0u, /*!< Reference will not be changed. */
TIM_ADV_OutputCompareRefOut_HighOnMatch = 1u, /*!< Reference will be high when counter value equals channel value. */
TIM_ADV_OutputCompareRefOut_LowOnMatch = 2u, /*!< Reference will be low when counter value equals channel value. */
TIM_ADV_OutputCompareRefOut_ToggleOnMatch = 3u, /*!< Reference will toggle. */
TIM_ADV_OutputCompareRefOut_LowAlways = 4u, /*!< Reference will always be low. */
TIM_ADV_OutputCompareRefOut_HighAlways = 5u, /*!< Reference will always be high. */
TIM_ADV_OutputCompareRefOut_FallingEdgeOnMatch = 6u, /*!< PWM mode 1. */
TIM_ADV_OutputCompareRefOut_RisingEdgeOnMatch = 7u, /*!< PWM mode 2. */
} TIM_ADV_OutputCompareRefOut_Type;
/*!
* @brief TIM input capture active edge selection and output compare active polarity selection.
* | conf | TIM_ADV_PinPolarity_Rising | TIM_ADV_PinPolarity_Falling |
* | ----------------------- | -------------------------- | --------------------------- |
* | input capture | detects rising edge | detects falling edge |
* | output compare | high polarity is active | low polarity is active |
* | encoder mode | input remains | input reverses |
* | output under idle state | output high polarity | output low polarity |
*/
typedef enum
{
TIM_ADV_PinPolarity_Disable = 0u, /*!< Disable channel. */
TIM_ADV_PinPolarity_Rising = 1u, /*!< See the table above. */
TIM_ADV_PinPolarity_Falling = 2u, /*!< See the table above.*/
TIM_ADV_PinPolarity_RisingOrFalling = 3u, /*!< For input capture, detect both the rising and falling edge. */
}TIM_ADV_PinPolarity_Type;
/*!
* @brief TIM Input active times to evoke capture.
*/
typedef enum
{
TIM_ADV_InputCaptureInDiv_OnEveryCapture = 0u, /*!< Every input call capture. */
TIM_ADV_InputCaptureInDiv_OnEach2Capture = 1u, /*!< Every two input call capture. */
TIM_ADV_InputCaptureInDiv_OnEach4Capture = 2u, /*!< Every four input call capture. */
TIM_ADV_InputCaptureInDiv_OnEach8Capture = 3u, /*!< Every eight input call capture. */
} TIM_ADV_InputCaptureInDiv_Type;
/*!
* @brief TIM Input sampling filter.
*/
typedef enum
{
TIM_ADV_InputCaptureInFilter_Alt0 = 0u, /*!< Filter swicther 0. */
TIM_ADV_InputCaptureInFilter_Alt1 = 1u, /*!< Filter swicther 1. */
TIM_ADV_InputCaptureInFilter_Alt2 = 2u, /*!< Filter swicther 2. */
TIM_ADV_InputCaptureInFilter_Alt3 = 3u, /*!< Filter swicther 3. */
TIM_ADV_InputCaptureInFilter_Alt4 = 4u, /*!< Filter swicther 4. */
TIM_ADV_InputCaptureInFilter_Alt5 = 5u, /*!< Filter swicther 5. */
TIM_ADV_InputCaptureInFilter_Alt6 = 6u, /*!< Filter swicther 6. */
TIM_ADV_InputCaptureInFilter_Alt7 = 7u, /*!< Filter swicther 7. */
TIM_ADV_InputCaptureInFilter_Alt8 = 8u, /*!< Filter swicther 8. */
TIM_ADV_InputCaptureInFilter_Alt9 = 9u, /*!< Filter swicther 9. */
TIM_ADV_InputCaptureInFilter_Alt10 = 10u, /*!< Filter swicther 10. */
TIM_ADV_InputCaptureInFilter_Alt11 = 11u, /*!< Filter swicther 11. */
TIM_ADV_InputCaptureInFilter_Alt12 = 12u, /*!< Filter swicther 12. */
TIM_ADV_InputCaptureInFilter_Alt13 = 13u, /*!< Filter swicther 13. */
TIM_ADV_InputCaptureInFilter_Alt14 = 14u, /*!< Filter swicther 14. */
TIM_ADV_InputCaptureInFilter_Alt15 = 15u, /*!< Filter swicther 15. */
} TIM_ADV_InputCaptureInFilter_Type;
/*!
* @brief TIM channel IO mode.
*/
typedef enum
{
TIM_ADV_ChannelIOMode_Out = 0u, /*!< Channel output. */
TIM_ADV_ChannelIOMode_In = 1u, /*!< Channel input, capture signal from direct channel. */
TIM_ADV_ChannelIOMode_Alt2 = 2u, /*!< Channel input, capture signal from indirect channel. */
TIM_ADV_ChannelIOMode_Alt3 = 3u, /*!< Channel input, capture signal from trc. */
} TIM_ADV_ChannelIOMode_Type;
/*!
* @brief TIM external trigger input active edge selection.
*/
typedef enum
{
TIM_ADV_ExtTriggerPinPolarity_Disable = 0u, /*!< Disable external trigger input. */
TIM_ADV_ExtTriggerPinPolarity_Rising = 1u, /*!< Detect the rising edge from external trigger. */
TIM_ADV_ExtTriggerPinPolarity_Falling = 2u, /*!< Detect the falling edge from external trigger. */
}TIM_ADV_ExtTriggerPinPolarity_Type;
/*!
* @brief TIM external trigger active input times to drive counter.
*/
typedef enum
{
TIM_ADV_ExtTriggerInDiv_OnEveryCapture = 0u, /*!< Every input call capture. */
TIM_ADV_ExtTriggerInDiv_OnEach2Capture = 1u, /*!< Every two input call capture. */
TIM_ADV_ExtTriggerInDiv_OnEach4Capture = 2u, /*!< Every four input call capture. */
TIM_ADV_ExtTriggerInDiv_OnEach8Capture = 3u, /*!< Every eight input call capture. */
} TIM_ADV_ExtTriggerInDiv_Type;
/*!
* @brief TIM external trigger sampling filter.
*/
typedef enum
{
TIM_ADV_ExtTriggerInFilter_Alt0 = 0u, /*!< Filter swicther 0. */
TIM_ADV_ExtTriggerInFilter_Alt1 = 1u, /*!< Filter swicther 1. */
TIM_ADV_ExtTriggerInFilter_Alt2 = 2u, /*!< Filter swicther 2. */
TIM_ADV_ExtTriggerInFilter_Alt3 = 3u, /*!< Filter swicther 3. */
TIM_ADV_ExtTriggerInFilter_Alt4 = 4u, /*!< Filter swicther 4. */
TIM_ADV_ExtTriggerInFilter_Alt5 = 5u, /*!< Filter swicther 5. */
TIM_ADV_ExtTriggerInFilter_Alt6 = 6u, /*!< Filter swicther 6. */
TIM_ADV_ExtTriggerInFilter_Alt7 = 7u, /*!< Filter swicther 7. */
TIM_ADV_ExtTriggerInFilter_Alt8 = 8u, /*!< Filter swicther 8. */
TIM_ADV_ExtTriggerInFilter_Alt9 = 9u, /*!< Filter swicther 9. */
TIM_ADV_ExtTriggerInFilter_Alt10 = 10u, /*!< Filter swicther 10. */
TIM_ADV_ExtTriggerInFilter_Alt11 = 11u, /*!< Filter swicther 11. */
TIM_ADV_ExtTriggerInFilter_Alt12 = 12u, /*!< Filter swicther 12. */
TIM_ADV_ExtTriggerInFilter_Alt13 = 13u, /*!< Filter swicther 13. */
TIM_ADV_ExtTriggerInFilter_Alt14 = 14u, /*!< Filter swicther 14. */
TIM_ADV_ExtTriggerInFilter_Alt15 = 15u, /*!< Filter swicther 15. */
} TIM_ADV_ExtTriggerInFilter_Type;
/*!
* @brief TIM Dead area time step length.
*/
typedef enum
{
TIM_ADV_DeadAreaStep_Alt0 = 0u, /*!< Dead area step = clock source step. */
TIM_ADV_DeadAreaStep_Alt1 = 1u, /*!< Dead area step = 2 * clock source step. */
TIM_ADV_DeadAreaStep_Alt2 = 2u, /*!< Dead area step = 4 * clock source step. */
} TIM_ADV_DeadAreaStep_Type;
/*!
* @brief TIM master mode output signal source.
*/
typedef enum
{
TIM_ADV_MasterOut_Alt0 = 0u, /*!< Software update period trigger signal works as master output. */
TIM_ADV_MasterOut_Alt1 = 1u, /*!< Counter enable signal works as master output. */
TIM_ADV_MasterOut_Alt2 = 2u, /*!< Update period event works as master output. */
TIM_ADV_MasterOut_Alt3 = 3u, /*!< Channel capture or compare event works as master output. */
TIM_ADV_MasterOut_Alt4 = 4u, /*!< Reference signal of channel 1 works as master output. */
TIM_ADV_MasterOut_Alt5 = 5u, /*!< Reference signal of channel 2 works as master output. */
TIM_ADV_MasterOut_Alt6 = 6u, /*!< Reference signal of channel 3 works as master output. */
TIM_ADV_MasterOut_Alt7 = 7u, /*!< Reference signal of channel 4 works as master output. */
} TIM_ADV_MasterOut_Type;
/*!
* @brief TIM slave mode input object source.
*/
typedef enum
{
TIM_ADV_SlaveIn_Alt0 = 0u, /*!< Internal trigger 0. */
TIM_ADV_SlaveIn_Alt1 = 1u, /*!< Internal trigger 1. */
TIM_ADV_SlaveIn_Alt2 = 2u, /*!< Internal trigger 2.*/
TIM_ADV_SlaveIn_Alt3 = 3u, /*!< Internal trigger 3. */
TIM_ADV_SlaveIn_Alt4 = 4u, /*!< Edge detector of timer input channel 1. */
TIM_ADV_SlaveIn_Alt5 = 5u, /*!< Timer input channel 1. */
TIM_ADV_SlaveIn_Alt6 = 6u, /*!< Timer input channel 2. */
TIM_ADV_SlaveIn_Alt7 = 7u, /*!< External trigger input. */
} TIM_ADV_SlaveIn_Type;
/*!
* @brief TIM slave mode counter response.
*/
typedef enum
{
TIM_ADV_SlaveResp_Disable = 0u, /*!< Disable the slave mode. */
TIM_ADV_SlaveResp_Alt1 = 1u, /*!< Counting in encoder mode 1. */
TIM_ADV_SlaveResp_Alt2 = 2u, /*!< Counting in encoder mode 2.*/
TIM_ADV_SlaveResp_Alt3 = 3u, /*!< Counting in encoder mode 3. */
TIM_ADV_SlaveResp_Alt4 = 4u, /*!< Reset counter. */
TIM_ADV_SlaveResp_Alt5 = 5u, /*!< Counter treat the signal as a gate. */
TIM_ADV_SlaveResp_Alt6 = 6u, /*!< Start the counter. */
TIM_ADV_SlaveResp_Alt7 = 7u, /*!< Counter counts on rising edges. */
} TIM_ADV_SlaveResp_Type;
/*!
* @brief TIM DMA Burst transfer base address.
*/
typedef enum
{
TIM_ADV_DMABurstBaseAddr_Alt0 = 0u, /*!< Start from CR1 register. */
TIM_ADV_DMABurstBaseAddr_Alt1 = 1u, /*!< Start from CR2 register. */
TIM_ADV_DMABurstBaseAddr_Alt2 = 2u, /*!< Start from SMCR register. */
TIM_ADV_DMABurstBaseAddr_Alt3 = 3u, /*!< Start from DIER register. */
TIM_ADV_DMABurstBaseAddr_Alt4 = 4u, /*!< Start from SR register. */
TIM_ADV_DMABurstBaseAddr_Alt5 = 5u, /*!< Start from EGR register. */
TIM_ADV_DMABurstBaseAddr_Alt6 = 6u, /*!< Start from CCMR1 register. */
TIM_ADV_DMABurstBaseAddr_Alt7 = 7u, /*!< Start from CCMR2 register. */
TIM_ADV_DMABurstBaseAddr_Alt8 = 8u, /*!< Start from CCER register. */
TIM_ADV_DMABurstBaseAddr_Alt9 = 9u, /*!< Start from CNT register. */
TIM_ADV_DMABurstBaseAddr_Alt10 = 10u, /*!< Start from PSC register. */
TIM_ADV_DMABurstBaseAddr_Alt11 = 11u, /*!< Start from ARR register. */
TIM_ADV_DMABurstBaseAddr_Alt12 = 12u, /*!< Start from CCR1 register. */
TIM_ADV_DMABurstBaseAddr_Alt13 = 13u, /*!< Start from CCR2 register. */
TIM_ADV_DMABurstBaseAddr_Alt14 = 14u, /*!< Start from CCR3 register. */
TIM_ADV_DMABurstBaseAddr_Alt15 = 15u, /*!< Start from CCR4 register. */
} TIM_ADV_DMABurstBaseAddr_Type;
/*!
* @brief TIM DMA Burst transfer length.
*/
typedef enum
{
TIM_ADV_DMABurstBaseLen_Alt0 = 0u, /*!< Sequentially visit 1 register from base register */
TIM_ADV_DMABurstBaseLen_Alt1 = 1u, /*!< Sequentially visit 2 registers from base register */
TIM_ADV_DMABurstBaseLen_Alt2 = 2u, /*!< Sequentially visit 3 registers from base register */
TIM_ADV_DMABurstBaseLen_Alt3 = 3u, /*!< Sequentially visit 4 registers from base register */
TIM_ADV_DMABurstBaseLen_Alt4 = 4u, /*!< Sequentially visit 5 registers from base register */
TIM_ADV_DMABurstBaseLen_Alt5 = 5u, /*!< Sequentially visit 6 registers from base register */
TIM_ADV_DMABurstBaseLen_Alt6 = 6u, /*!< Sequentially visit 7 registers from base register */
TIM_ADV_DMABurstBaseLen_Alt7 = 7u, /*!< Sequentially visit 8 registers from base register */
TIM_ADV_DMABurstBaseLen_Alt8 = 8u, /*!< Sequentially visit 9 registers from base register */
TIM_ADV_DMABurstBaseLen_Alt9 = 9u, /*!< Sequentially visit 10 registers from base register */
TIM_ADV_DMABurstBaseLen_Alt10 = 10u, /*!< Sequentially visit 11 registers from base register */
TIM_ADV_DMABurstBaseLen_Alt11 = 11u, /*!< Sequentially visit 12 registers from base register */
TIM_ADV_DMABurstBaseLen_Alt12 = 12u, /*!< Sequentially visit 13 registers from base register */
TIM_ADV_DMABurstBaseLen_Alt13 = 13u, /*!< Sequentially visit 14 registers from base register */
TIM_ADV_DMABurstBaseLen_Alt14 = 14u, /*!< Sequentially visit 15 registers from base register */
TIM_ADV_DMABurstBaseLen_Alt15 = 15u, /*!< Sequentially visit 16 registers from base register */
TIM_ADV_DMABurstBaseLen_Alt16 = 16u, /*!< Sequentially visit 17 registers from base register */
TIM_ADV_DMABurstBaseLen_Alt17 = 17u, /*!< Sequentially visit 18 registers from base register */
} TIM_ADV_DMABurstBaseLen_Type;
/*!
* @brief TIM encoder direction.
*/
typedef enum
{
TIM_ADV_EncoderDirection_Forward = 0u, /*!< Encoder rotates in forward direction. */
TIM_ADV_EncoderDirection_Backward = 1u, /*!< Encoder rotates in backward direction. */
} TIM_ADV_EncoderDirection_Type;
/*!
* @brief TIM lock level.
*/
typedef enum
{
TIM_ADV_LockLevel_Disable = 0u, /*!< Unlock. */
TIM_ADV_LockLevel_Alt0 = 1u, /*!< Lock level 1. */
TIM_ADV_LockLevel_Alt1 = 2u, /*!< Lock level 2. */
TIM_ADV_LockLevel_Alt2 = 3u, /*!< Lock level 3. */
} TIM_ADV_LockLevel_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref TIM_ADV_Init() to initialize the TIM module time base unit.
*/
typedef struct
{
uint32_t ClockFreqHz; /*!< Frequence of clock source for counter. */
uint32_t StepFreqHz; /*!< Step length value. Counter freq = ClockSourceFreqHz / (ClockSourceDiv+1). */
uint32_t Period; /*!< Counter counting period length, from 0 to Period. */
bool EnablePreloadPeriod; /*!< Enable the preload of period value. If enable, it will be updated in next period, otherwise immediately. */
TIM_ADV_PeriodMode_Type PeriodMode; /*!< Counter working period times. */
TIM_ADV_CountMode_Type CountMode; /*!< Counter count direction. */
} TIM_ADV_Init_Type;
/*!
* @brief This type of structure instance is used to setup the output compare feature when calling the @ref TIM_ADV_EnableOutputCompare() to enable the TIM module output compare channel.
*/
typedef struct
{
uint16_t ChannelValue; /*!< Value to be compared with counter. */
bool EnableFastOutput; /*!< Enable fast response to the trigger input event. */
bool EnablePreLoadChannelValue; /*!< Enable the preload of channel value. If enable, it will be updated in next period, otherwise immediately. */
TIM_ADV_OutputCompareRefOut_Type RefOutMode; /*!< The reference output when counter matching the channel value. */
bool ClearRefOutOnExtTrigger; /*!< External trigger high will clear the reference. */
TIM_ADV_PinPolarity_Type PinPolarity; /*!< Setup the output pin's polarity. */
TIM_ADV_PinPolarity_Type COMPPinPolarity; /*!< Set the complementary channel output. */
} TIM_ADV_OutputCompareConf_Type;
/*!
* @brief This type of structure instance is used to setup the input capture feature when calling the @ref TIM_ADV_EnableInputCapture() to enable the TIM module input capture channel.
*/
typedef struct
{
TIM_ADV_InputCaptureInDiv_Type InDiv; /*!< The division of filtered input. */
TIM_ADV_InputCaptureInFilter_Type InFilter; /*!< The filter sampling time for initial input. */
TIM_ADV_PinPolarity_Type PinPolarity; /*!< Setup the output pin's polarity. */
} TIM_ADV_InputCaptureConf_Type;
/*!
* @brief This type of structure instance is used to setup the dead time feature when calling the @ref TIM_ADV_EnableDeadArea() to enable the TIM module dead time area set.
* | DeadAreaCoef | Real Dead Area Time |
* | ------------ | --------------------------------------------------- |
* | 0xxxxxxx | DeadAreaCoef * DeadAreaStep |
* | 10xxxxxx | ( 64 + DeadAreaCoef[5:0] ) * ( 2 * DeadAreaStep ) |
* | 110xxxxx | ( 32 + DeadAreaCoef[4:0] ) * ( 8 * DeadAreaStep ） |
* | 111xxxxx | ( 32 + DeadAreaCoef[4:0] ) * ( 16 * DeadAreaStep ) |
*/
typedef struct
{
TIM_ADV_DeadAreaStep_Type StepFreqHz; /*!< Dead time area step set. */
uint8_t DeadAreaCoef; /*!< The coefficient with bias to multiply with StepFreqHz to get the final dead area time. */
} TIM_ADV_DeadAreaConf_Type;
/*!
* @brief This type of structure instance is used to setup the master mode configuration when calling the @ref TIM_ADV_EnableMasterMode().
*/
typedef struct
{
TIM_ADV_MasterOut_Type Out; /*!< Master mode output selection. */
bool EnableSync; /*!< Enable sychronize with slave timers. */
} TIM_ADV_MasterModeConf_Type;
/*!
* @brief This type of structure instance is used to setup the slave mode configuration when calling the @ref TIM_ADV_EnableSlaveMode().
*/
typedef struct
{
TIM_ADV_SlaveIn_Type In; /*!< Input trigger selection for slave timer. */
TIM_ADV_SlaveResp_Type Resp; /*!< Slave timer counter response for its input trigger. */
} TIM_ADV_SlaveModeConf_Type;
/*!
* @brief This type of structure instance is used to setup the external trigger input configuration when calling the @ref TIM_ADV_EnableExtTriggerIn().
*/
typedef struct
{
TIM_ADV_ExtTriggerInDiv_Type InDiv; /*!< The division of filtered input. */
TIM_ADV_ExtTriggerInFilter_Type InFilter; /*!< The filter sampling time for initial input. */
TIM_ADV_ExtTriggerPinPolarity_Type PinPolarity; /*!< Setup the output pin's polarity. */
} TIM_ADV_ExtTriggerInConf_Type;
/*!
* @brief This type of structure instance is used to setup the dma burst configuration when calling the @ref TIM_ADV_EnableDMABurst().
*/
typedef struct
{
TIM_ADV_DMABurstBaseAddr_Type BaseAddr; /*!< The base address to start transfer. */
TIM_ADV_DMABurstBaseLen_Type Length; /*!< Length of sequential registers DMA burst visits. */
} TIM_ADV_DMABurstConf_Type;
/*!
* @brief This type of structure instance is used to setup the idle state output when calling the @ref TIM_ADV_EnableIdleOut().
*/
typedef struct
{
TIM_ADV_PinPolarity_Type PinPolarity; /*!< The output state of channel under idle mode. */
TIM_ADV_PinPolarity_Type COMPPinPolarity; /*!< The output state of complementary channel under idle mode. */
} TIM_ADV_IdleOut_Type;
/*!
* @brief This type of structure instance is used to setup the break in configuration when calling the @ref TIM_ADV_EnableBreakIn().
*/
typedef struct
{
TIM_ADV_PinPolarity_Type PinPolarity; /*!< The active edge of the break in signal. */
bool AutoSwitchOutput; /*!< If input signal is inactive, switch the output compare at next update. */
bool DirectIdleOutput; /*!< If enable, output the set idle state directly. */
} TIM_ADV_BreakIn_Type;
/*!
* @brief Set the timer's step for indicated TIM module.
*
* @param TIMx TIM_ADV instance.
* @param init Pointer to the initialization structure. See to @ref TIM_ADV_Init_Type.
* @return val 'true' to set the timer's step successfully, 'false' to fail because the invalid StepFreqHz.
*/
bool TIM_ADV_Init(TIM_ADV_Type * TIMx, TIM_ADV_Init_Type * init);
/*!
* @brief Start counting.
*
* @param TIMx TIM_ADV instance.
* @return None.
*/
void TIM_ADV_Start(TIM_ADV_Type * TIMx);
/*!
* @brief Stop counting immediately.
*
* @param TIMx TIM_ADV instance.
* @return None.
*/
void TIM_ADV_Stop(TIM_ADV_Type * TIMx);
/*!
* @brief Get the indicated TIMx Counter value.
*
* @param TIMx TIM_ADV_Type instance.
* @return The current value of the counter register.
*/
uint32_t TIM_ADV_GetCounterValue(TIM_ADV_Type * TIMx);
/*!
* @brief Clear the indicated TIMx Counter.
*
* @param TIMx TIM_ADV_Type instance.
* @return None.
*/
void TIM_ADV_ClearCounterValue(TIM_ADV_Type * TIMx);
/*!
* @brief Enable the TIM_ADV interrupts.
*
* @param TIMx TIM_ADV_Type instance.
* @param interrupts Interrupts to be enabled.See to @ref TIM_ADV_INT.
* @param enable 'true' to enable the indicated interrupts or DMAs, 'false' to disable the indicated interrupts or DMAs.
* @return None.
*/
void TIM_ADV_EnableInterrupts(TIM_ADV_Type * TIMx, uint32_t interrupts, bool enable);
/*!
* @brief Enable the TIM_ADV DMAs.
*
* @param TIMx TIM_ADV_Type instance.
* @param dmas DMA masks to be enabled. See to @ref TIM_ADV_DMA.
* @param enable 'true' to enable the indicated interrupts or DMAs, 'false' to disable the indicated interrupts or DMAs.
* @return None.
*/
void TIM_ADV_EnableDMA(TIM_ADV_Type * TIMx, uint32_t dmas, bool enable);
/*!
* @brief Software trigger events to call interrupts or DMAs.
*
* Can simultaneously trigger multiple events.
*
* @param TIMx TIM_ADV instance. See to @ref TIM_ADV_SWTRG.
* @param swtrgs Trigger the events to generate interrupts.
*/
void TIM_ADV_DoSwTrigger(TIM_ADV_Type * TIMx, uint32_t swtrgs);
/*!
* @brief Get the status of the indicated timer.
*
* @param TIMx TIM_ADV_Type instance.
* @return Interrupt status flags. See to @ref TIM_ADV_INT_STATUS.
*/
uint32_t TIM_ADV_GetInterruptStatus(TIM_ADV_Type * TIMx);
/*!
* @brief Clear the status of indicated interrupt.
*
* @param TIMx TIM_ADV_Type instance.
* @param status The required clear flag type. See to @ref TIM_ADV_INT_STATUS.
* @return None.
*/
void TIM_ADV_ClearInterruptStatus(TIM_ADV_Type * TIMx, uint32_t status);
/*!
* @brief Set up the output compare feature of indicated timer channel.
*
* If need to change the IO mode of the working channel, channel must be disabled first, then modify.
*
* @param TIMx TIM_ADV_Type instance.
* @param channel Output channel instance. See to @ref TIM_ADV_CHANNEL_SELECTION.
* @param conf Pointer to the configuration structure. See to @ref TIM_ADV_OutputCompareConf_Type.
* @return None.
*/
void TIM_ADV_EnableOutputCompare(TIM_ADV_Type * TIMx, uint32_t channel, TIM_ADV_OutputCompareConf_Type * conf);
/*!
* @brief Enable the TIM_ADV channel output for pulse generation.
*
* @param TIMx TIM_ADV_Type instance.
* @param enable 'true' to enable the channel output, 'false' to disable the channel output.
* @return None.
*/
void TIM_ADV_EnableOutputCompareSwitch(TIM_ADV_Type * TIMx, bool enable);
/*!
* @brief Enable the input capture feature of indicated timer channel.
*
* If need to change the IO mode of the working channel, channel must be disabled first, then modify.
*
* @param TIMx TIM_ADV_Type instance.
* @param channel Input channel instance. See to @ref TIM_ADV_CHANNEL_SELECTION.
* @param conf Pointer to the configuration structure. See to @ref TIM_ADV_InputCaptureConf_Type.
* @return None.
*/
void TIM_ADV_EnableInputCapture(TIM_ADV_Type * TIMx, uint32_t channel, TIM_ADV_InputCaptureConf_Type * conf);
/*!
* @brief Get the value of the indicated timer channel.
*
* When capture event happens, counter value will be kept in its indicated channel.
*
* @param TIMx TIM_ADV_Type instance.
* @param channel Channel instance to get the value. See to @ref TIM_ADV_CHANNEL_SELECTION.
* @return Value of the indiacted timer channel.
*/
uint16_t TIM_ADV_GetChannelValue(TIM_ADV_Type * TIMx, uint32_t channel);
/*!
* @brief Put the value into the indicated timer channel.
*
* When in output compare, channel value would be the compared with counter value.
*
* @param TIMx TIM_ADV_Type instance.
* @param channel Channel instance to put the value. See to @ref TIM_ADV_CHANNEL_SELECTION.
* @param value The value to be set in the indicated timer channel.
* @return None.
*/
void TIM_ADV_PutChannelValue(TIM_ADV_Type * TIMx, uint32_t channel, uint16_t value);
/*!
* @brief Enable the dead area of the indicated timer.
*
* @param TIMx TIM_ADV_Type instance.
* @param conf Pointer to the configuration structure. See to @ref TIM_ADV_DeadAreaConf_Type.
* @return None.
*/
void TIM_ADV_EnableDeadArea(TIM_ADV_Type * TIMx, TIM_ADV_DeadAreaConf_Type * conf);
/*!
* @brief Enable the master mode of the indicated timer.
*
* Master mode transfer the timer signal to other timers.
*
* @param TIMx TIM_ADV_Type instance.
* @param conf Pointer to the configuration structure. See to @ref TIM_ADV_MasterModeConf_Type.
* @return None.
*/
void TIM_ADV_EnableMasterMode(TIM_ADV_Type * TIMx, TIM_ADV_MasterModeConf_Type * conf);
/*!
* @brief Enable the slave mode of the indicated timer.
*
* Slave mode can control the working state of counter.
*
* @param TIMx TIM_ADV_Type instance.
* @param conf Pointer to the configuration structure. See to @ref TIM_ADV_SlaveModeConf_Type.
* @return None.
*/
void TIM_ADV_EnableSlaveMode(TIM_ADV_Type * TIMx, TIM_ADV_SlaveModeConf_Type * conf);
/*!
* @brief Enable the external trigger input of the indicated counter.
*
* External trigger signal will trigger counter do addition.
* Its div and filter along with the counter StepFreqHz will affect.
*
* @param TIMx TIM_ADV_Type instance.
* @param conf Pointer to the configuration structure. See to @ref TIM_ADV_ExtTriggerInConf_Type.
* @return None.
*/
void TIM_ADV_EnableExtTriggerIn(TIM_ADV_Type * TIMx, TIM_ADV_ExtTriggerInConf_Type * conf);
/*!
* @brief Enable the dma burst transfer of the indicated timer.
*
* @param TIMx TIM_ADV_Type instance.
* @param conf Pointer to the configuration structure. See to @ref TIM_ADV_DMABurstConf_Type.
* @return Address of DMA Burst transfer base register address.
*/
uint32_t TIM_ADV_EnableDMABurst(TIM_ADV_Type * TIMx, TIM_ADV_DMABurstConf_Type * conf);
/*!
* @brief Get the encoder rotating direction and the counted encoder pulse times.
*
* @param TIMx TIM_ADV_Type instance.
* @param value The counter value for pulse times.
* @return Encoder rotating direction. See to @ref TIM_ADV_EncoderDirection_Type.
*/
TIM_ADV_EncoderDirection_Type TIM_ADV_GetEncoder(TIM_ADV_Type * TIMx, uint32_t * value);
/*!
* @brief Set the indicated TIMx repetition counter value.
*
* @param TIMx TIM_ADV_Type instance.
* @param value The repetition value to be set.
* @return The current value of the counter register.
*/
void TIM_ADV_SetRepCounter(TIM_ADV_Type * TIMx, uint8_t value);
/*!
* @brief Get the indicated TIMx Counter value.
*
* Real repetition's times number, meaning left repetition period times to run.
*
* @param TIMx TIM_ADV_Type instance.
* @return The current value of the counter register.
*/
uint8_t TIM_ADV_GetRepCounterValue(TIM_ADV_Type * TIMx);
/*!
* @brief Set the channel idle state output when switch off the output compare.
*
* @param TIMx TIM_ADV_Type instance.
* @param channel Channel instance to set the idle state output. See to @ref TIM_ADV_CHANNEL_SELECTION.
* @param conf Pointer to the configuration structure. See to @ref TIM_ADV_IdleOut_Type.
* @return None.
*/
void TIM_ADV_EnableIdleOut(TIM_ADV_Type * TIMx, uint32_t channel, TIM_ADV_IdleOut_Type * conf);
/*!
* @brief Set the lock level for protecting the timer config setting.
*
* @param TIMx TIM_ADV_Type instance.
* @param lock Lock level to be set for protecting Timer set. See to @ref TIM_ADV_LockLevel_Type.
* @return None.
*/
void TIM_ADV_EnableLock(TIM_ADV_Type * TIMx, TIM_ADV_LockLevel_Type lock);
/*!
* @brief Set the break input of the timer.
*
* @param TIMx TIM_ADV_Type instance.
* @param conf Pointer to the configuration structure. See to @ref TIM_ADV_BreakIn_Type.
* @return None.
*/
void TIM_ADV_EnableBreakIn(TIM_ADV_Type * TIMx, TIM_ADV_BreakIn_Type * conf);
/*!
* @brief Set the PWM shift of the indicated channel.
*
* @param TIMx TIM_ADV_Type instance.
* @param channel Channel instance to set the pwm shift. See to @ref TIM_ADV_CHANNEL_SELECTION.
* @param value The counter time when need pwm output shift. If val equals the channel value, disable the shift.
* @return None.
*/
void TIM_ADV_EnablePWMShift(TIM_ADV_Type * TIMx, uint32_t channel, uint16_t value);
/*!
*@}
*/
#endif /* __HAL_TIM_ADV_H__ */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_TIM_BASIC_H__
#define __HAL_TIM_BASIC_H__
#include "hal_common.h"
/*!
* @addtogroup TIM_BASIC
* @{
*/
/*!
* @brief TIM_BASIC driver version number.
*/
#define TIM_BASIC_DRIVER_VERSION 0u /*!< TIM_BASIC_0. */
/*!
* @addtogroup TIM_BASIC_INT
* @brief Enable interrupt.
* @{
*/
#define TIM_BASIC_INT_UPDATE_PERIOD (1u << 0u) /*!< Timer update period interrupt switchers. */
/*!
* @}
*/
/*!
* @addtogroup TIM_BASIC_DMA
* @brief Enable DMA.
* @{
*/
#define TIM_BASIC_DMA_UPDATE_PERIOD (1u << 8u) /*!< Timer update period interrupt switchers. */
/*!
* @}
*/
/*!
* @addtogroup TIM_BASIC_INT_STATUS
* @brief Check interrupt status.
* @{
*/
#define TIM_BASIC_STATUS_UPDATE_PERIOD (1u << 0u) /*!< Timer update period interrupt flag. */
/*!
* @}
*/
/*!
* @addtogroup TIM_BASIC_SWTRG
* @brief Events to be triggered by software.
* @{
*/
#define TIM_BASIC_SWTRG_UPDATE_PERIOD (1u << 0u) /*!< Timer update period trigger. */
/*!
* @}
*/
/*!
* @brief Counter period working mode.
*/
typedef enum
{
TIM_BASIC_PeriodMode_Continuous = 0u, /*!< The counter would count from zero to indicated period value then generate an update circularly. */
TIM_BASIC_PeriodMode_OneTimeRun = 1u, /*!< The counter would count from zero to indicated period value then generate an update then stop. */
} TIM_BASIC_PeriodMode_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref TIM_BASIC_Init() to initialize the TIM module time base unit.
*/
typedef struct
{
uint32_t ClockFreqHz; /*!< Frequence of clock source for counter. */
uint32_t StepFreqHz; /*!< Step length value. Counter's StepFreqHz = ClockSourceFreqHz / (ClockSourceDiv+1). */
uint32_t Period; /*!< Counter counting period length, from 0 to Period. */
bool EnablePreloadPeriod; /*!< Enable the preload of period value. If enable, it will be updated in next period, otherwise immediately. */
TIM_BASIC_PeriodMode_Type PeriodMode; /*!< Counting working mode. */
} TIM_BASIC_Init_Type;
/*!
* @brief Set the timer's step for indicated TIM module.
*
* @param TIMx TIM_BASIC instance.
* @param init Pointer to the initialization structure. See to @ref TIM_BASIC_Init_Type.
* @return 'true' to set the timer's step successfully, 'false' to fail because the invalid StepFreqHz.
*/
bool TIM_BASIC_Init(TIM_BASIC_Type * TIMx, TIM_BASIC_Init_Type * init);
/*!
* @brief Start counting.
*
* @param TIMx TIM_BASIC instance.
* @return None.
*/
void TIM_BASIC_Start(TIM_BASIC_Type * TIMx);
/*!
* @brief Stop counting immediately.
*
* @param TIMx TIM_BASIC instance.
* @return None.
*/
void TIM_BASIC_Stop(TIM_BASIC_Type * TIMx);
/*!
* @brief Get the indicated TIMx Counter value.
*
* @param TIMx TIM_BASIC_Type instance.
* @return The current value of the counter register.
*/
uint32_t TIM_BASIC_GetCounterValue(TIM_BASIC_Type * TIMx);
/*!
* @brief Enable the TIM_BASIC interrupts.
*
* @param TIMx TIM_BASIC_Type instance.
* @param interrupts Interrupts to be enabled.See to @ref TIM_BASIC_INT.
* @param enable 'true' to enable the indicated interrupts or DMAs, 'false' to disable the indicated interrupts or DMAs.
* @return None.
*/
void TIM_BASIC_EnableInterrupts(TIM_BASIC_Type *TIMx, uint32_t interrupts, bool enable);
/*!
* @brief Enable the TIM_BASIC DMAs.
*
* @param TIMx TIM_BASIC_Type instance.
* @param dmas DMA masks to be enabled. See to @ref TIM_BASIC_DMA.
* @param enable 'true' to enable the indicated interrupts or DMAs, 'false' to disable the indicated interrupts or DMAs.
* @return None.
*/
void TIM_BASIC_EnableDMA(TIM_BASIC_Type *TIMx, uint32_t dmas, bool enable);
/*!
* @brief Software trigger events to call interrupts or DMAs.
*
* Can simultaneously trigger multiple events.
*
* @param TIMx TIM_BASIC instance. See to @ref TIM_BASIC_SWTRG.
* @param swtrgs Trigger the events to generate interrupts.
*/
void TIM_BASIC_DoSwTrigger(TIM_BASIC_Type *TIMx, uint32_t swtrgs);
/*!
* @brief Get the status of the indicated timer.
*
* @param TIMx TIM_BASIC_Type instance.
* @return Interrupt status flags. See to @ref TIM_BASIC_INT_STATUS.
*/
uint32_t TIM_BASIC_GetInterruptStatus(TIM_BASIC_Type * TIMx);
/*!
* @brief Clear the status of indicated interrupt.
*
* @param TIMx TIM_BASIC_Type instance.
* @param status The required clear flag type. See to @ref TIM_BASIC_INT_STATUS.
* @return None.
*/
void TIM_BASIC_ClearInterruptStatus(TIM_BASIC_Type *TIMx, uint32_t status);
/*!
*@}
*/
#endif /* __HAL_TIM_BASIC_H__ */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_UART_H__
#define __HAL_UART_H__
#include "hal_common.h"
/*!
* @addtogroup UART
* @{
*/
/*!
* @brief UART driver version number.
*/
#define UART_DRIVER_VERSION 0u /*!< uart_0. */
/*!
* @addtogroup UART_STATUS
* @{
*/
#define UART_STATUS_TX_DONE UART_CSR_TXC_MASK /*!< Status flag when UART transmiter shifter is empty after the transfer is done. */
#define UART_STATUS_RX_DONE UART_CSR_RXAVL_MASK /*!< Status flag when UART receiving buffer is with available data. */
#define UART_STATUS_TX_FULL UART_CSR_TXFULL_MASK /*!< Status flag when UART transmiter buffer is full. */
#define UART_STATUS_TX_EMPTY UART_CSR_TXEPT_MASK /*!< Status flag when UART transmiter buffer is empty. */
/*!
* @}
*/
/*!
* @addtogroup UART_INT
* @{
*/
#define UART_INT_TX_EMPTY UART_ISR_TXINTF_MASK /*!< Interrupt enable when UART transmiter buffer is empty. */
#define UART_INT_RX_DONE UART_ISR_RXINTF_MASK /*!< Interrupt enable when UART receiving buffer is with available data. */
#define UART_INT_TX_DONE UART_ISR_TXCINTF_MASK /*!< Interrupt enable when UART transmiter shifter is empty. */
/*!
* @}
*/
/*!
* @brief UART word length type.
*/
typedef enum
{
UART_WordLength_5b = 0u, /*!< Word length 5 bits. */
UART_WordLength_6b = 1u, /*!< Word length 6 bits. */
UART_WordLength_7b = 2u, /*!< Word length 7 bits. */
UART_WordLength_8b = 3u, /*!< Word length 8 bits. */
} UART_WordLength_Type;
/*!
* @brief UART stop bits type.
*/
typedef enum
{
UART_StopBits_1 = 0u, /*!< 1 stop bits. */
UART_StopBits_2 = 1u, /*!< 2 stop bits. */
UART_StopBits_0_5 = 2u, /*!< 0.5 stop bits. */
UART_StopBits_1_5 = 3u, /*!< 1.5 stop bits. */
} UART_StopBits_Type;
/*!
* @brief UART parity type.
*/
typedef enum
{
UART_Parity_None = 0u, /*!< No parity. */
UART_Parity_Even = 1u, /*!< Even parity. */
UART_Parity_Odd = 2u, /*!< Odd parity. */
} UART_Parity_Type;
/*!
* @brief UART hardware flow control type.
*/
typedef enum
{
UART_HwFlowControl_None = 0u, /*!< No hardware flow control. */
UART_HwFlowControl_RTS_CTS = 1u, /*!< Enable RTS and CTS hardware flow control.*/
} UART_HwFlowControl_Type;
/*!
* @brief UART xfer mode type.
*/
typedef enum
{
UART_XferMode_None = 0u, /*!< Disable both Tx and Rx. */
UART_XferMode_RxOnly = 1u, /*!< Enable Rx only. */
UART_XferMode_TxOnly = 2u, /*!< Enable Tx only. */
UART_XferMode_RxTx = 3u, /*!< Enable both Rx and Tx. */
} UART_XferMode_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref UART_Init() to initialize the UART module.
*/
typedef struct
{
uint32_t ClockFreqHz; /*!< Bus Clock Freq. */
uint32_t BaudRate; /*!< Specify the UART communication baud rate. */
UART_WordLength_Type WordLength; /*!< Specify the number of data bits transmitted or received in a frame. */
UART_StopBits_Type StopBits; /*!< Specify the number of stop bits transmitted. */
UART_Parity_Type Parity; /*!< Specify the parity mode. */
UART_XferMode_Type XferMode; /*!< Specify whether the Receive or Transmit mode is enabled or not. */
UART_HwFlowControl_Type HwFlowControl; /*!< Specify whether the hardware flow control mode is enabled or not. */
} UART_Init_Type;
/*!
* @brief Initialize the UART module.
*
* @param UARTx UART instance.
* @param init Pointer to the initialization structure. See to @ref UART_Init_Type.
* @return None.
*/
void UART_Init(UART_Type * UARTx, UART_Init_Type * init);
/*!
* @brief Enable the UART module.
*
* The UART module should be enabled before sending or receiving data.
*
* @param UARTx UART instance.
* @param enable 'true' to enable the module, 'false' to disable the module.
* @return None.
*/
void UART_Enable(UART_Type * UARTx, bool enable);
/*!
* @brief Get the current status flags of the UART module.
*
* @param UARTx UART instance.
* @return Status flags. See to @ref UART_STATUS.
*/
uint32_t UART_GetStatus(UART_Type * UARTx);
/*!
* @brief Enable interrupts of the UART module.
*
* @param UARTx UART instance.
* @param interrupts Interrupt code masks. See to @ref UART_INT.
* @param enable 'true' to enable the indicated interrupts, 'false' to disable the indicated interrupts.
* @return None.
*/
void UART_EnableInterrupts(UART_Type * UARTx, uint32_t interrupts, bool enable);
/*!
* @brief Get the interrupts status flags of the UART module.
*
* @param UARTx UART instance.
* @return Interrupt status flags. See to @ref UART_INT.
*/
uint32_t UART_GetInterruptStatus(UART_Type * UARTx);
/*!
* @brief Clear the interrupts status flags of the UART module.
*
* @param UARTx UART instance.
* @param interrupts The mask codes of the indicated interrupt flags to be cleared.
* @return Interrupt status flags. See to @ref UART_INT.
*/
void UART_ClearInterruptStatus(UART_Type * UARTx, uint32_t interrupts);
/*!
* @brief Put the data into transmiter buffer of the UART module.
*
* @param UARTx UART instance.
* @param value Data value to be send through the transmiter.
* @return None.
*/
void UART_PutData(UART_Type * UARTx, uint8_t value);
/*!
* @brief Get the data from receiver buffer of the UART module.
*
* @param UARTx UART instance.
* @return The data value received from the receiver.
* @return None.
*/
uint8_t UART_GetData(UART_Type * UARTx);
/*!
* @brief Enable the DMA trigger from the UART module.
*
* The DMA trigger events are the same as the intertupts.
*
* @param UARTx UART instance.
* @param enable 'true' to enable the DMA trigger, 'false' to disable the DMA trigger.
* @return None.
*/
void UART_EnableDMA(UART_Type * UARTx, bool enable);
/*!
* @brief Read the current enabled interrupts the UART module.
*
* @param UARTx UART instance.
* @return The mask codes enabled interrupts. See to @ref UART_INT
*/
uint32_t UART_GetEnabledInterrupts(UART_Type * UARTx);
/*!
* @brief Get the hardware Rx data buffer's address the UART module.
*
* The return value of the address is most used with DMA module.
*
* @param UARTx UART instance.
* @return The value of the address for UART module's hardware Rx data buffer.
*/
uint32_t UART_GetRxDataRegAddr(UART_Type * UARTx);
/*!
* @brief Get the hardware Tx data buffer's address the UART module.
*
* The return value of the address is most used with DMA module.
*
* @param UARTx UART instance.
* @return The value of the address for UART module's hardware Tx data buffer.
*/
uint32_t UART_GetTxDataRegAddr(UART_Type * UARTx);
/*!
*@}
*/
#endif /* __HAL_UART_H__ */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_USB_H__
#define __HAL_USB_H__
#include "hal_common.h"
#include "hal_usb_bdt.h"
/*!
* @addtogroup USB
* @{
*/
/*!
* @brief USB driver version number.
*/
#define USB_DRIVER_VERSION 0u /*!< USB_0. */
/*!
* @addtogroup USB_INT
* @brief USB_INT mask codes
* @{
*/
#define USB_INT_RESET USB_INTSTAT_USBRST_MASK /*!< USB Interrupt: USB bus reset. */
#define USB_INT_ERROR USB_INTSTAT_ERROR_MASK /*!< USB Interrupt: Error happend. */
#define USB_INT_SOFTOK USB_INTSTAT_SOFTOK_MASK /*!< USB Interrupt: Recv a SOF_Tok. */
#define USB_INT_TOKENDONE USB_INTSTAT_TOKDNE_MASK /*!< USB Interrupt: Token done. */
#define USB_INT_SLEEP USB_INTSTAT_SLEEP_MASK /*!< USB Interrupt: Sleep. */
#define USB_INT_RESUME USB_INTSTAT_RESUME_MASK /*!< USB Interrupt: Resume. */
#define USB_INT_ATTACH USB_INTSTAT_ATTACH_MASK /*!< USB Interrupt: Attach. */
#define USB_INT_STALL USB_INTSTAT_STALL_MASK /*!< USB Interrupt: Stall. */
/*!
* @}
*/
/*!
* @addtogroup USB_INT_ERR
* @brief USB_INT_ERR mask codes
* @{
*/
#define USB_INT_ERR_PID USB_ERRSTAT_PIDERR_MASK /*!< USB Error: PID check error. */
#define USB_INT_ERR_CRC5 USB_ERRSTAT_CRC5EOF_MASK /*!< USB Error: CRC5 check failed. */
#define USB_INT_ERR_EOF USB_ERRSTAT_CRC5EOF_MASK /*!< USB Error: EOF Error. */
#define USB_INT_ERR_CRC16 USB_ERRSTAT_CRC16_MASK /*!< USB Error: CRC16 check failed. */
#define USB_INT_ERR_DFN8 USB_ERRSTAT_DFN8_MASK /*!< USB Error: Data not 8bit. */
#define USB_INT_ERR_BTO USB_ERRSTAT_BTOERR_MASK /*!< USB Error: BTO error. */
#define USB_INT_ERR_DMA USB_ERRSTAT_DMAERR_MASK /*!< USB Error: DMA error. */
#define USB_INT_ERR_BTS USB_ERRSTAT_BTSERR_MASK /*!< USB Error: Bit stuff error. */
/*!
* @}
*/
/*!
* @addtogroup USB_EP
* @brief USB_EP mask codes
* @{
*/
#define USB_EP_0 (1u << 0u ) /*!< EndPoint 0. */
#define USB_EP_1 (1u << 1u ) /*!< EndPoint 1. */
#define USB_EP_2 (1u << 2u ) /*!< EndPoint 2. */
#define USB_EP_3 (1u << 3u ) /*!< EndPoint 3. */
#define USB_EP_4 (1u << 4u ) /*!< EndPoint 4. */
#define USB_EP_5 (1u << 5u ) /*!< EndPoint 5. */
#define USB_EP_6 (1u << 6u ) /*!< EndPoint 6. */
#define USB_EP_7 (1u << 7u ) /*!< EndPoint 7. */
#define USB_EP_8 (1u << 8u ) /*!< EndPoint 8. */
#define USB_EP_9 (1u << 9u ) /*!< EndPoint 9. */
#define USB_EP_10 (1u << 10u) /*!< EndPoint 10. */
#define USB_EP_11 (1u << 11u) /*!< EndPoint 11. */
#define USB_EP_12 (1u << 12u) /*!< EndPoint 12. */
#define USB_EP_13 (1u << 13u) /*!< EndPoint 13. */
#define USB_EP_14 (1u << 14u) /*!< EndPoint 14. */
#define USB_EP_15 (1u << 15u) /*!< EndPoint 15. */
/*!
* @}
*/
/*!
* @brief USB TokenPid type.
*/
typedef enum
{
USB_TokenPid_OUT = 0x1u, /*!< USB Token Pid: OUT. */
USB_TokenPid_IN = 0x9u, /*!< USB Token Pid: IN. */
USB_TokenPid_SETUP = 0xDu, /*!< USB Token Pid: SETUP. */
} USB_TokenPid_Type;
/*!
* @brief USB Direction type.
*/
typedef enum
{
USB_Direction_OUT = 0x0u, /*!< USB Direstion: IN. */
USB_Direction_IN = 0x1u, /*!< USB Direstion: OUT. */
USB_Direction_NULL, /*!< USB Direstion: NULL. */
} USB_Direction_Type;
/*!
* @brief USB BufDesp OddEven type.
*/
typedef enum
{
USB_BufDesp_OddEven_Even = 0x0u, /*!< Buffer Descriptor OddEven: Even. */
USB_BufDesp_OddEven_Odd = 0x1u, /*!< Buffer Descriptor OddEven: Odd. */
} USB_BufDesp_OddEven_Type;
/*!
* @brief USB EndPoint Mode.
*/
typedef enum
{
USB_EndPointMode_Control = 1u, /*!< USB EndPoint Mode: Control xfer. */
USB_EndPointMode_Bulk = 2u, /*!< USB EndPoint Mode: Bulk xfer. */
USB_EndPointMode_Interrupt = 3u, /*!< USB EndPoint Mode: Interrupt xfer. */
USB_EndPointMode_Isochronous = 4u, /*!< USB EndPoint Mode: isoch xfer. */
USB_EndPointMode_NULL, /*!< USB EndPoint Mode: NULL. */
} USB_EndPointMode_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref USB_InitDevice() to initialize the USB module.
*/
typedef struct
{
uint32_t BufDespTable_Addr; /*!< BufDespTable addr. */
} USB_Device_Init_Type;
/*!
* @brief Initialize the USB module.
*
* @param USBx USB instance.
* @param init Pointer to the initialization structure. See to @ref USB_Device_Init_Type.
* @return None.
*/
void USB_InitDevice(USB_Type * USBx, USB_Device_Init_Type * init);
/*!
* @brief Enable interrupts of the USB module.
*
* @param USBx USB instance.
* @param interrupts Interrupt code masks. See to @ref USB_INT.
* @param enable 'true' to enable the indicated interrupts, 'false' to disable the indicated interrupts.
* @return None.
*/
void USB_EnableInterrupts(USB_Type * USBx, uint32_t interrupts, bool enable);
/*!
* @brief Get the enabled interrupts status flags of the USB module.
*
* @param USBx USB instance.
* @return Interrupt status flags. See to @ref USB_INT.
*/
uint32_t USB_GetEnabledInterrupts(USB_Type * USBx);
/*!
* @brief Get the interrupts status flags of the USB module.
*
* @param USBx USB instance.
* @return Interrupt status flags. See to @ref USB_INT.
*/
uint32_t USB_GetInterruptStatus(USB_Type * USBx);
/*!
* @brief Clear the interrupts status flags of the USB module.
* @param USBx USB instance.
* @param interrupts Interrupt status flags. See to @ref USB_INT.
* @return None.
*/
void USB_ClearInterruptStatus(USB_Type * USBx, uint32_t interrupts);
/*!
* @brief Enable error interrupts of the USB module.
*
* @param USBx USB instance.
* @param interrupts Error Interrupt code masks. See to @ref USB_INT_ERR.
* @param enable 'true' to enable the indicated interrupts, 'false' to disable the indicated interrupts.
* @return None.
*/
void USB_EnableErrInterrupts(USB_Type * USBx, uint32_t interrupts, bool enable);
/*!
* @brief Get the enabled error interrupts status flags of the USB module.
*
* @param USBx USB instance.
* @return Interrupt status flags. See to @ref USB_INT_ERR.
*/
uint32_t USB_GetEnabledErrInterrupts(USB_Type * USBx);
/*!
* @brief Get the error interrupts status flags of the USB module.
*
* @param USBx USB instance.
* @return Interrupt status flags. See to @ref USB_INT_ERR.
*/
uint32_t USB_GetErrInterruptStatus(USB_Type * USBx);
/*!
* @brief Clear the error interrupts status flags of the USB module.
* @param USBx USB instance.
* @param interrupts Interrupt status flags. See to @ref USB_INT_ERR.
* @return None.
*/
void USB_ClearErrInterruptStatus(USB_Type * USBx, uint32_t interrupts);
/*!
* @brief Enable USB.
*
* @param USBx USB instance.
* @param enable 'true' to enable the module, 'false' to disable the module.
* @return None.
*/
void USB_Enable(USB_Type * USBx, bool enable);
/*!
* @brief Enable USB BufDesp ODD_EVEN Reset, and make only even BufDesp can be used.
*
* @param USBx USB instance.
* @param enable 'true' to enable the feature, 'false' to disable the feature.
* @return None.
*/
void USB_EnableOddEvenReset(USB_Type * USBx, bool enable);
/*!
* @brief Enable USB Resume signal.
*
* @param USBx USB instance.
* @param enable 'true' to enable the resume signal, 'false' to disable the resume signal.
* @return None.
*/
void USB_EnableResumeSignal(USB_Type * USBx, bool enable);
/*!
* @brief Enable USB Suspend.
*
* @param USBx USB instance.
* @param enable 'true' to enable suspend, 'false' to disable suspend.
* @return None.
*/
void USB_EnableSuspend(USB_Type * USBx, bool enable);
/*!
* @brief Set Device address. This address is distribute by host.
*
* @param USBx USB instance.
* @param addr The Device address.
* @return None.
*/
void USB_SetDeviceAddr(USB_Type * USBx, uint8_t addr);
/*!
* @brief Get Device address.
*
* @param USBx USB instance.
* @return The Device address.
*/
uint8_t USB_GetDeviceAddr(USB_Type * USBx);
/*!
* @brief Get buffer descriptor table address.
*
* @param USBx USB instance.
* @return The BufDespTable address.
*/
uint32_t USB_GetBufDespTableAddr(USB_Type * USBx);
/*!
* @brief Get the USB Frame Number.
*
* @param USBx USB instance.
* @return The USB Frame Number.
*/
uint32_t USB_GetFrameNumber(USB_Type * USBx);
/*!
* @brief Get BufDesp after USB_INT_TOKENDONE interrupt happened and before clear USB_INT_TOKENDONE interrupt status.
*
* @param USBx USB instance.
* @return BufDesp address.
*/
USB_BufDesp_Type * USB_GetBufDesp(USB_Type * USBx);
/*!
* @brief Get Token Pid from BufDesp before the BufDesp Reset.
*
* @param bd BufDesp addr.
* @return Token Pid.
*/
USB_TokenPid_Type USB_BufDesp_GetTokenPid(USB_BufDesp_Type * bd);
/*!
* @brief Get packet addr from BufDesp before the BufDesp Reset.
*
* @param bd BufDesp addr.
* @return Packet addrress.
*/
uint32_t USB_BufDesp_GetPacketAddr(USB_BufDesp_Type * bd);
/*!
* @brief Get packet size from BufDesp before the BufDesp Reset.
*
* @param bd BufDesp addr.
* @return Packet size.
*/
uint32_t USB_BufDesp_GetPacketSize(USB_BufDesp_Type * bd);
/*!
* @brief Reset BufDesp.
*
* @param bd BufDesp addr.
* @return None.
*/
void USB_BufDesp_Reset(USB_BufDesp_Type * bd);
/*!
* @brief Get EndPoint index after USB_INT_TOKENDONE interrupt happened and before clear USB_INT_TOKENDONE interrupt status.
*
* @param USBx USB instance.
* @return EndPoint index.
*/
uint32_t USB_GetEndPointIndex(USB_Type * USBx);
/*!
* @brief Get Xfer Direction after USB_INT_TOKENDONE interrupt happened and before clear USB_INT_TOKENDONE interrupt status.
*
* @param USBx USB instance.
* @return Xfer Direction, See to @ref USB_Direction_Type.
*/
USB_Direction_Type USB_GetXferDirection(USB_Type * USBx);
/*!
* @brief Get BufDesp OddEven after USB_INT_TOKENDONE interrupt happened and before clear USB_INT_TOKENDONE interrupt status.
*
* @param USBx USB instance.
* @return BufDesp OddEven.
*/
USB_BufDesp_OddEven_Type USB_GetBufDespOddEven(USB_Type * USBx);
/*!
* @brief Enable the end point.
*
* @param USBx USB instance.
* @param index endpoint index.
* @param mode End point mode, See to @ref USB_EndPointMode_Type.
* @param enable 'true' to enable the EndPoint, 'false' to disable the EndPoint.
* @return None.
*/
void USB_EnableEndPoint(USB_Type * USBx, uint32_t index, USB_EndPointMode_Type mode, bool enable);
/*!
* @brief Stall EndPoint n.
*
* @param USBx USB instance.
* @param ep_mask EndPoint mask, see to @ref USB_EP mask codes.
* @param enable 'true' to enable the EndPoint stall, 'false' to disable the EndPoint stall.
* @return None.
*/
void USB_EnableEndPointStall(USB_Type * USBx, uint32_t ep_mask, bool enable);
/*!
* @brief Get Enabled EndPoint stall status.
*
* @param USBx USB instance.
* @return stall status, see to @ref USB_EP mask codes.
*/
uint32_t USB_GetEnabledEndPointStall(USB_Type * USBx);
/*!
* @brief Xfer data by usb.
*
* @param bd BufDesp.
* @param data_n DATAn packet, n equal 0 or 1.
* @param data the address of data.
* @param len Data length.
* @return 'true': BufDesp can be xfer data, 'false': BufDesp is busy.
*/
bool USB_BufDesp_Xfer(USB_BufDesp_Type * bd, uint32_t data_n, uint8_t * data, uint32_t len);
/*!
* @brief Check whether BufDesp is busy.
*
* @param bd BufDesp addr.
* @return 'true': BufDesp is busy, 'false': BufDesp is not busy.
*/
bool USB_BufDesp_IsBusy(USB_BufDesp_Type * bd);
/*!
*@}
*/
#endif /* __HAL_USB_H__ */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_USB_BDT_H__
#define __HAL_USB_BDT_H__
#include "hal_common.h"
/*!
* @addtogroup USB
* @{
*/
/*!
* @brief USB BufDesp EndPoint number.
*/
#define USB_BDT_EP_NUM 16u /*!< USB BufDesp EndPoint num. */
/*!
* @brief USB BufDesp EndPoint direction number.
*/
#define USB_BDT_DIRECTION_NUM 2u /*!< USB BufDesp EndPoint direction num. */
/*!
* @brief USB BufDesp EndPoint buffer number.
*/
#define USB_BDT_BUF_NUM 2u /*!< USB BufDesp EndPoint buffer num. */
/*!
* @brief This type of structure instance is used to implement the buffer descriptor for USB.
*/
typedef struct
{
union
{
uint32_t HEAD; /*!< Head. */
struct
{
uint32_t RESEVED0 :2; /*!< RESEVED. */
uint32_t BDT_STALL :1; /*!< Stall. */
uint32_t DTS :1; /*!< Data shift sync. */
uint32_t NINC :1; /*!< DMA addr cannot increasing. */
uint32_t KEEP :1; /*!< Keep BD held by USB. */
uint32_t DATA :1; /*!< DATA0 or DATA1. */
uint32_t OWN :1; /*!< Owner, 0 is CPU, 1 is USB. */
uint32_t RESEVED1 :8; /*!< RESEVED. */
uint32_t BC :10; /*!< Packet size. */
uint32_t RESEVED2 :6; /*!< RESEVED. */
};
struct
{
uint32_t RESEVED3 :2; /*!< RESEVED. */
uint32_t TOK_PID :4; /*!< Token pid. */
uint32_t RESEVED4 :26; /*!< RESEVED. */
};
};
uint32_t ADDR; /*!< Buffer addr. */
} USB_BufDesp_Type;
/*!
* @brief This type of structure instance is used to implement the buffer descriptor table for USB.
*/
typedef union
{
USB_BufDesp_Type Table[USB_BDT_EP_NUM][ USB_BDT_DIRECTION_NUM][ USB_BDT_BUF_NUM]; /*!< [EndPoint] [Direction] [Odd_Even]. */
USB_BufDesp_Type Index[USB_BDT_EP_NUM * USB_BDT_DIRECTION_NUM * USB_BDT_BUF_NUM]; /*!< Index. */
} USB_BufDespTable_Type;
/*!
* @}
*/
#endif /* __HAL_USB_BDT_H__ */

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/* hal_wwdg.h */
#ifndef __HAL_WWDG_H__
#define __HAL_WWDG_H__
/*!
* @addtogroup WWDG
* @{
*/
#include "hal_common.h"
/*!
* @brief WWDG driver version number.
*/
#define WWDG_DRIVER_VERSION 0u /*!< WWDG_0. */
/*!
* @brief The lower limit value of WWDG counter.
*/
#define WWDG_LOWER_LIMIT 0x40u /*!< If WWDG counter Below this value, WWDG will generate a reset request. */
/*!
* @addtogroup WWDG_INT
* @brief WWDG_STATUS mask codes
* @{
*/
#define WWDG_INT_ALMOST_TIMEOUT WWDG_CFGR_EWI_MASK /*!< WWDG interrupt: Almost timeout. */
/*!
* @}
*/
/*!
* @addtogroup WWDG_STATUS
* @brief WWDG_STATUS mask codes
* @{
*/
#define WWDG_STATUS_ALMOST_TIMEOUT WWDG_SR_EWIF_MASK /*!< WWDG status: Almost timeout. */
/*!
* @}
*/
/*!
* @brief WWDG prescaler type.
*
* Select the prescaler of WWDG counter clock.
*/
typedef enum
{
WWDG_Prescaler_1 = 0u, /*!< WWDG Prescaler 1. */
WWDG_Prescaler_2 = 1u, /*!< WWDG Prescaler 2. */
WWDG_Prescaler_4 = 2u, /*!< WWDG Prescaler 4. */
WWDG_Prescaler_8 = 3u, /*!< WWDG Prescaler 8. */
} WWDG_Prescaler_Type;
/*!
* @brief This type of structure instance is used to keep the settings when calling the @ref WWDG_Init() to initialize the USB module.
*/
typedef struct
{
WWDG_Prescaler_Type Prescaler; /*!< Specify the WWDG counter prescaler. */
uint32_t UpperLimit; /*!< Specify the upperLimit, WWDG will generate a reset request if reload WWDG counter before the counter value greater than UpperLimit. */
} WWDG_Init_Type;
/*!
* @brief Initialize the WWDG module.
*
* @param WWDGx WWDG instance.
* @param init Pointer to the initialization structure. See to @ref WWDG_Init_Type.
* @return None.
*/
void WWDG_Init(WWDG_Type * WWDGx, WWDG_Init_Type * init);
/*!
* @brief Start counting.
*
* If the counter is started, it cannot be stoped unless reset MCU.
*
* @param WWDGx WWDG instance.
* @return None.
*/
void WWDG_Start(WWDG_Type * WWDGx);
/*!
* @brief Reolad WWDG counter (Feed dog).
*
* Reload WWDG counter to ensure that the counter value greater than WWDG_LOWER_LIMIT_VALUE and prevent generate a reset request.
*
* @param WWDGx WWDG instance.
* @param value The value of reload WWDG counter, the value ranges from 0x40 to 0x7f.
* @return None.
*/
void WWDG_Reload(WWDG_Type * WWDGx, uint32_t value);
/*!
* @brief Enable interrupts of the WWDG module.
*
* @param WWDGx WWDG instance.
* @param interrupts Interrupt code masks. See to @ref WWDG_INT.
* @param enable 'true' to enable the indicated interrupts, 'false' has no effect.
* @return None.
*/
void WWDG_EnableInterrupts(WWDG_Type * WWDGx, uint32_t interrupts, bool enable);
/*!
* @brief Get the status flags of the WWDG module.
*
* @param WWDGx WWDG instance.
* @return status flags. See to @ref WWDG_STATUS.
*/
uint32_t WWDG_GetStatus(WWDG_Type * WWDGx);
/*!
* @brief Clear the status flags of the WWDG module.
*
* @param WWDGx WWDG instance.
* @param status status flags. See to @ref WWDG_STATUS.
* @return None.
*/
void WWDG_ClearStatus(WWDG_Type * WWDGx, uint32_t status);
/*!
*@}
*/
#endif /* __HAL_WWDG_H__. */
/* EOF. */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "hal_adc.h"
void ADC_Init(ADC_Type * ADCx, ADC_Init_Type * init)
{
uint32_t cfg;
if (!init)
{
return;
}
cfg = ADCx->ADCFG & ~( ADC_ADCFG_ADCPREH_MASK
| ADC_ADCFG_ADCPREL_MASK
| ADC_ADCFG_RSLTCTL_MASK
| ADC_ADCR_ALIGN_MASK )
;
/* Prescaler & Resolution. */
cfg |= ADC_ADCFG_ADCPREL(init->ClockDiv)
| ADC_ADCFG_ADCPREH((init->ClockDiv)>>1)
| ADC_ADCFG_RSLTCTL(init->Resolution)
;
ADCx->ADCFG = cfg;
/* ADC conversion mode and conversion data result align. */
ADCx->ADCR = (ADCx->ADCR & ~( ADC_ADCR_ADMD_MASK | ADC_ADCR_ALIGN_MASK) )
| ADC_ADCR_ADMD(init->ConvMode)
| ADC_ADCR_ALIGN(init->Align)
;
}
void ADC_Enable(ADC_Type * ADCx, bool enable)
{
if (enable)
{
ADCx->ADCFG |= ADC_ADCFG_ADEN_MASK;
}
else
{
ADCx->ADCFG &= ~ADC_ADCFG_ADEN_MASK;
}
}
void ADC_EnableTempSensor(ADC_Type * ADCx, bool enable)
{
if (enable)
{
ADCx->ADCFG |= ADC_ADCFG_TSEN_MASK;
}
else
{
ADCx->ADCFG &= ~ADC_ADCFG_TSEN_MASK;
}
}
/* Use VBG 1.2V as default voltage sensor. */
void ADC_EnableVoltSensor(ADC_Type * ADCx, bool enable)
{
if (enable)
{
ADCx ->ADCFG |= ADC_ADCFG_VSEN_MASK;
}
else
{
ADCx->ADCFG &= ~ADC_ADCFG_VSEN_MASK;
}
}
void ADC_EnableDMA(ADC_Type * ADCx, bool enable)
{
if (enable)
{
ADCx->ADCR |= ADC_ADCR_DMAEN_MASK;
}
else
{
ADCx->ADCR &= ~ADC_ADCR_DMAEN_MASK;
}
}
void ADC_EnableInterrupts(ADC_Type * ADCx, uint32_t interrupts, bool enable)
{
if (enable)
{
if ( 0u != (ADC_STATUS_CONV_SLOT_DONE & interrupts) )
{
ADCx->ADCR |= ADC_ADCR_EOCIE_MASK;
}
if ( 0u != (ADC_STATUS_CONV_SAMPLE_DONE & interrupts) )
{
ADCx->ADCR |= ADC_ADCR_EOSMPIE_MASK;
}
if ( 0u != (ADC_STATUS_CONV_SEQ_DONE & interrupts) )
{
ADCx->ADCR |= ADC_ADCR_ADIE_MASK;
}
if ( 0u != (ADC_STATUS_COMPARE_DONE & interrupts) )
{
ADCx->ADCR |= ADC_ADCR_ADWIE_MASK;
}
}
else
{
if ( 0u != (ADC_STATUS_CONV_SLOT_DONE & interrupts) )
{
ADCx->ADCR &= ~ADC_ADCR_EOCIE_MASK;
}
if ( 0u != (ADC_STATUS_CONV_SAMPLE_DONE & interrupts) )
{
ADCx->ADCR &= ~ADC_ADCR_EOSMPIE_MASK;
}
if ( 0u != (ADC_STATUS_CONV_SEQ_DONE & interrupts) )
{
ADCx->ADCR &= ~ADC_ADCR_ADIE_MASK;
}
if ( 0u != (ADC_STATUS_COMPARE_DONE & interrupts) )
{
ADCx->ADCR &= ~ADC_ADCR_ADWIE_MASK;
}
}
}
uint32_t ADC_GetStatus(ADC_Type * ADCx)
{
uint32_t flags = 0u;
if ( 0u != (ADC_ADSTAEXT_EOCIF_MASK & ADCx->ADSTAEXT) )
{
flags |= ADC_STATUS_CONV_SLOT_DONE;
}
if ( 0u != (ADC_ADSTAEXT_EOSMPIF_MASK & ADCx->ADSTAEXT) )
{
flags |= ADC_STATUS_CONV_SAMPLE_DONE;
}
if ( 0u != (ADC_ADSTA_ADIF_MASK & ADCx->ADSTA) )
{
flags |= ADC_STATUS_CONV_SEQ_DONE;
}
if ( 0u != (ADC_ADSTA_ADWIF_MASK & ADCx->ADSTA) )
{
flags |= ADC_STATUS_COMPARE_DONE;
}
return flags;
}
void ADC_ClearStatus(ADC_Type * ADCx, uint32_t flags)
{
if ( 0u != (ADC_STATUS_CONV_SLOT_DONE & flags) )
{
ADCx->ADSTAEXT = ADC_ADSTAEXT_EOCIF_MASK;
}
if ( 0u != (ADC_STATUS_CONV_SAMPLE_DONE & flags) )
{
ADCx->ADSTAEXT = ADC_ADSTAEXT_EOSMPIF_MASK;
}
if ( 0u != (ADC_STATUS_CONV_SEQ_DONE & flags) )
{
ADCx->ADSTA = ADC_ADSTA_ADIF_MASK;
}
if ( 0u != (ADC_STATUS_COMPARE_DONE & flags) )
{
ADCx->ADSTA = ADC_ADSTA_ADWIF_MASK;
}
}
uint32_t ADC_GetConvResult(ADC_Type * ADCx, uint32_t * channel, uint32_t * flags)
{
uint32_t tmp32 = ADCx->ADDATA;
*channel = (tmp32 & ADC_ADDATA_CHANNELSEL_MASK) >> ADC_ADDATA_CHANNELSEL_SHIFT;
if (flags)
{
*flags = (tmp32 & (ADC_ADDATA_OVERRUN_MASK | ADC_ADDATA_VALID_MASK) ) >> ADC_ADDATA_OVERRUN_SHIFT;
}
return (tmp32 & ADC_ADDATA_DATA_MASK ) >> ADC_ADDATA_DATA_SHIFT;
}
uint32_t ADC_GetChnConvResult(ADC_Type * ADCx, uint32_t channel, uint32_t * flags)
{
uint32_t tmp32 = ADCx ->ADDR[channel];
if (flags)
{
*flags = (tmp32 & (ADC_ADDR_OVERRUN_MASK | ADC_ADDR_VALID_MASK) ) >> ADC_ADDR_OVERRUN_SHIFT;
}
return (tmp32 & ADC_ADDR_DATA_MASK ) >> ADC_ADDR_DATA_SHIFT;
}
void ADC_SetChnSampleTime(ADC_Type * ADCx, uint32_t channel, ADC_SampleTime_Type sample_time)
{
if (channel < 8u)
{
ADCx->SMPR1 = (ADCx->SMPR1 & ~(0xF << (4u * channel))) | (sample_time << (4u * channel));
}
else
{
channel-= 8u;
ADCx->SMPR2 = (ADCx->SMPR2 & ~(0xF << (4u * channel))) | (sample_time << (4u * channel));
}
}
void ADC_EnableHwTrigger(ADC_Type * ADCx, ADC_HwTrgConf_Type * conf)
{
if ( !conf )
{
ADCx->ADCR &= ~ADC_ADCR_TRGEN_MASK;
return;
}
/* Enable the hardware trigger. */
ADCx->ADCR = ( ADCx->ADCR & ~(ADC_ADCR_TRGSELL_MASK | ADC_ADCR_TRGSELH_MASK | ADC_ADCR_TRGSHIFT_MASK | ADC_ADCR_TRGEDGE_MASK) )
| ADC_ADCR_TRGEN_MASK
| ADC_ADCR_TRGSELL(conf->Source & 0x7)
| ADC_ADCR_TRGSELH(conf->Source >> 3u)
| ADC_ADCR_TRGSHIFT(conf->DelayCycle)
| ADC_ADCR_TRGEDGE(conf->Edge)
;
}
void ADC_EnableRegSeq(ADC_Type * ADCx, ADC_RegSeqConf_Type * conf)
{
if (!conf)
{
return;
}
ADCx->ANYCR &= ~ADC_ANYCR_CHANYMDEN_MASK;
/* enable regular channels. */
ADCx->ADCHS = conf->SeqSlots;
ADCx->ADCR = (ADCx->ADCR & ~ADC_ADCR_SCANDIR_MASK)
| ADC_ADCR_SCANDIR(conf->SeqDirection)
;
}
void ADC_EnableAnySeq(ADC_Type * ADCx, ADC_AnySeqConf_Type * conf)
{
if (!conf)
{
ADCx->ANYCR &= ~ADC_ANYCR_CHANYMDEN_MASK;
return;
}
if (conf->SeqLen > 16u)
{
return; /* the available range of seq length is within 16u. */
}
/* enable any channel sequence mode. */
ADCx->ANYCR |= ADC_ANYCR_CHANYMDEN_MASK;
/* select the any slots number. */
ADCx->ANYCFG = ADC_ANYCFG_CHANYNUM(conf->SeqLen - 1u);
/* fill the channels into each slot of ANY sequence. */
uint32_t offset;
for (uint32_t i = 0u; i < conf->SeqLen; i++)
{
if (i < 8u)
{
offset = i;
ADCx->CHANY0 = (ADCx->CHANY0 & ~(0xF << (4u * offset))) | (conf->SeqChannels[i] << (4u * offset));
}
else if (i < 16)
{
offset = i - 8u;
ADCx->CHANY1 = (ADCx->CHANY1 & ~(0xF << (4u * offset))) | (conf->SeqChannels[i] << (4u * offset));
}
}
}
void ADC_DoSwTrigger(ADC_Type * ADCx, bool enable)
{
if (enable)
{
ADCx->ADCR |= ADC_ADCR_ADST_MASK;
}
else
{
ADCx->ADCR &= ~ADC_ADCR_ADST_MASK;
}
}
void ADC_EnableHwComp(ADC_Type * ADCx, ADC_HwCompConf_Type * conf)
{
if ( !conf )
{
/* disable the hardware compare feature for both regular & any seq. */
ADCx->ADCFG &= ~ADC_ADCFG_ADWEN_MASK;
return;
}
/* enable the hardware compare feature. */
ADCx->ADCFG |= ADC_ADCFG_ADWEN_MASK;
/* setup the channel in monitor. */
ADCx->ADCR = (ADCx->ADCR & ~ADC_ADCR_CMPCH_MASK) | ADC_ADCR_CMPCH(conf->ChnNum);
/* setup the compare boundary. */
ADCx->ADCMPR = ADC_ADCMPR_CMPLDATA(conf->LowLimit)
| ADC_ADCMPR_CMPHDATA(conf->HighLimit)
;
}
/* EOF. */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "hal_comp.h"
void COMP_Init(COMP_Type * COMPx, uint32_t channel, COMP_Init_Type * init)
{
if ( channel < COMP_CHANNEL_NUM )
{
COMPx->CSR[channel] = COMP_CSR_OFLT(init->OutFilter)
| COMP_CSR_HYST(init->Hysteresis)
| COMP_CSR_POL(init->OutInvert)
| COMP_CSR_OUTSEL(init->OutMux)
| COMP_CSR_INPSEL(init->PosInMux)
| COMP_CSR_INMSEL(init->InvInMux)
| COMP_CSR_MODE(init->Speed)
;
}
}
void COMP_Enable(COMP_Type * COMPx, uint32_t channel, bool enable)
{
if ( channel < COMP_CHANNEL_NUM )
{
if ( true == enable )
{
COMPx->CSR[channel] |= COMP_CSR_EN_MASK;
}
else
{
COMPx->CSR[channel] &= ~COMP_CSR_EN_MASK;
}
}
}
void COMP_Lock(COMP_Type * COMPx, uint32_t channel)
{
if ( channel < COMP_CHANNEL_NUM )
{
COMPx->CSR[channel] |= COMP_CSR_LOCK_MASK;
}
}
bool COMP_GetOutputStatus(COMP_Type * COMPx, uint32_t channel)
{
if ( channel < COMP_CHANNEL_NUM )
{
if ( 0u != ( COMP_CSR_OUT_MASK & COMPx->CSR[channel] ) )
{
return true;
}
else
{
return false; /* normal input voltage lower than inverting input. */
}
}
else
{
return false;
}
}
void COMP_EnableExtVrefConf(COMP_Type * COMPx, COMP_ExtVrefConf_Type * conf)
{
if ( NULL == conf ) /* disable the ext vref. */
{
COMPx->CRV &= ~COMP_CRV_CRVEN_MASK;
}
else /* init & enable ext vref. */
{
COMPx->CRV = COMP_CRV_CRVSRC (conf->VrefSource)
| COMP_CRV_CRVSEL (conf->Volt)
| COMP_CRV_CRVEN_MASK
;
}
}
void COMP_EnableRoundRobinConf(COMP_Type * COMPx, uint32_t channel, COMP_RoundRobinConf_Type * conf)
{
if ( channel < COMP_CHANNEL_NUM )
{
if ( NULL == conf )
{
COMPx->POLL[channel] &= ~COMP_POLL_POLLEN_MASK;
}
else
{
COMPx->POLL[channel] = COMP_POLL_PERIOD(conf->Period)
| COMP_POLL_FIXN(conf->InvInFix)
| COMP_POLL_POLLCH(conf->ChnGroup)
| COMP_POLL_POLLEN_MASK;
;
}
}
}
bool COMP_GetRoundRobinOutStatus(COMP_Type * COMPx, uint32_t channel, COMP_InMux_Type pos_in)
{
if ( channel < COMP_CHANNEL_NUM )
{
uint32_t flag = COMP_POLL_POUT(1 << ( (uint32_t)pos_in - 1 ) );
if ( 0 != (COMPx->POLL[channel] & flag ) )
{
return true;
}
else
{
return false;
}
}
else
{
return false;
}
}
/* EOF. */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "hal_dac.h"
void DAC_Init(DAC_Type * DACx, uint32_t channel, DAC_Init_Type * init)
{
uint32_t cr = 0u;
cr = DACx->CR & ~(( DAC_CR_BOFF1_MASK
| DAC_CR_TEN1_MASK
| DAC_CR_TSEL1_MASK
) << (channel<<4u)); /* Calculate the shift and clear the indicated bit. */
/* Enable Output Buffer. */
if (init->EnableOutBuf == false)
{
cr |= (DAC_CR_BOFF1_MASK << (channel<<4u));
}
/* Trigger Source. */
if (init->TrgSource < DAC_TrgSource_None)
{
cr |= ((DAC_CR_TEN1_MASK | DAC_CR_TSEL1(init->TrgSource)) << (channel<<4u));
}
DAC->CR = cr;
}
void DAC_Enable(DAC_Type * DACx, uint32_t channel, bool enable)
{
if (enable)
{
DACx->CR |= (DAC_CR_EN1_MASK << (channel << 4u));
}
else
{
DACx->CR &= ~(DAC_CR_EN1_MASK << (channel << 4u));
}
}
uint32_t DAC_GetData(DAC_Type * DACx, uint32_t channel)
{
uint32_t ret = 0u;
if(channel == DAC_CHN_1)
{
ret = (DACx->DOR1 & DAC_DOR1_DACC1DOR_MASK);
}
else if (channel == DAC_CHN_2)
{
ret = (DACx->DOR2 & DAC_DOR2_DACC2DOR_MASK);
}
return ret;
}
uint32_t DAC_PutData(DAC_Type * DACx, uint32_t channel, uint32_t value, DAC_Align_Type align)
{
uint32_t ret = 0u;
switch (align)
{
case DAC_Align_8b_Dual:
{
DAC_PutDualChannelData8bRightAlign(DACx, value);
ret = DAC_GetData(DACx, DAC_CHN_1) | ( DAC_GetData(DACx, DAC_CHN_2) << 16u);
break;
}
case DAC_Align_8b_Right:
{
DAC_PutData8bRightAlign(DACx, channel, value);
ret = DAC_GetData(DACx, channel);
break;
}
case DAC_Align_12b_Left:
{
DAC_PutData12bLeftAlign(DACx, channel, value);
ret = DAC_GetData(DACx, channel);
break;
}
case DAC_Align_12b_Right:
{
DAC_PutData12bRightAlign(DACx, channel, value);
ret = DAC_GetData(DACx, channel);
break;
}
case DAC_Align_12b_Dual_Left:
{
DAC_PutDualChannelData12bLeftAlign(DACx, value);
ret = DAC_GetData(DACx, DAC_CHN_1)
| ( DAC_GetData(DACx, DAC_CHN_2) << 16u);
break;
}
case DAC_Align_12b_Dual_Right:
{
DAC_PutDualChannelData12bRightAlign(DACx, value);
ret = DAC_GetData(DACx, DAC_CHN_1)
| ( DAC_GetData(DACx, DAC_CHN_2) << 16u);
break;
}
default:
break;
}
return ret;
}
void DAC_EnableAddNoise(DAC_Type * DACx, uint32_t channel, DAC_AddNoise_Init_Type * init)
{
if (init == NULL)
{
DAC->CR &= ~(DAC_CR_WAVE1_MASK << (channel << 4u));
}
else
{
DAC->CR |= (( DAC_CR_WAVE1(1u) /* Noise wave need to set WAVEx = 01. */
| DAC_CR_MAMP1(init->AddNoise)
) << (channel << 4u));
}
}
void DAC_EnableAddTriangle(DAC_Type * DACx, uint32_t channel, DAC_AddTriangle_Init_Type * init)
{
if (init == NULL)
{
DAC->CR &= ~(DAC_CR_WAVE1_MASK << (channel << 4u));
}
else
{
DAC->CR |= (( DAC_CR_WAVE1(2u) /* Noise wave need to set WAVEx = 1x. */
| DAC_CR_MAMP1(init->AddTriangle)
) << (channel << 4u));
}
}
void DAC_EnableDMA(DAC_Type * DACx, uint32_t channel, bool enable)
{
if (enable)
{
DACx->CR |= (DAC_CR_DMAEN1_MASK << (channel<<4u));
}
else
{
DACx->CR &= ~(DAC_CR_DMAEN1_MASK << (channel<<4u));
}
}
void DAC_DoSwTrigger(DAC_Type * DACx, uint32_t channel)
{
DACx->SWTRIGR |= (DAC_SWTRIGR_SWTRIG1_MASK << channel);
}
void DAC_DoDualChannelSwTrigger(DAC_Type * DACx)
{
DACx->SWTRIGR |= DAC_SWTRIGR_SWTRIG1_MASK
| DAC_SWTRIGR_SWTRIG2_MASK
;
}
uint32_t DAC_GetDataRegAddr(DAC_Type * DACx, uint32_t channel, DAC_Align_Type align)
{
uint32_t ret = 0u;
switch (align)
{
case DAC_Align_8b_Dual:
{
ret = DAC_GetDualChannelData8bRegAddr(DACx);
break;
}
case DAC_Align_8b_Right:
{
ret = DAC_GetData8bRegAddr(DACx, channel);
break;
}
case DAC_Align_12b_Left:
{
ret = DAC_GetData12bLeftRegAddr(DACx, channel);
break;
}
case DAC_Align_12b_Right:
{
ret = DAC_GetData12bRightRegAddr(DACx, channel);
break;
}
case DAC_Align_12b_Dual_Left:
{
ret = DAC_GetDualChannelData12bLeftRegAddr(DACx);
break;
}
case DAC_Align_12b_Dual_Right:
{
ret = DAC_GetDualChannelData12bRightRegAddr(DACx);
break;
}
default:
break;
}
return ret;
}
/* input value bit[7:0]. 12b output: xxxxxxxx0000. */
void DAC_PutData8bRightAlign(DAC_Type * DACx, uint32_t channel, uint32_t value)
{
if (channel == DAC_CHN_1)
{
DACx->DHR8R1 = value;
}
else if (channel == DAC_CHN_2)
{
DACx->DHR8R2 = value;
}
}
/* input value bit[15:4]. 12b output: xxxxxxxxxxxx. */
void DAC_PutData12bLeftAlign(DAC_Type * DACx, uint32_t channel, uint32_t value)
{
if (channel == DAC_CHN_1)
{
DACx->DHR12L1 = value;
}
else if (channel == DAC_CHN_2)
{
DACx->DHR12L2 = value;
}
}
/* input value bit[11:0], 12b output: xxxxxxxxxxxx. */
void DAC_PutData12bRightAlign(DAC_Type * DACx, uint32_t channel, uint32_t value)
{
if (channel == DAC_CHN_1)
{
DACx->DHR12R1 = value;
}
else if (channel == DAC_CHN_2)
{
DACx->DHR12R2 = value;
}
}
/* bit[15:8] for channel 2, bit[7:0] for channel 1. */
void DAC_PutDualChannelData8bRightAlign(DAC_Type * DACx, uint32_t value)
{
DACx->DHR8RD = value;
}
/* bit[31:16] for channel 2, bit[15:0] for channel 1. */
void DAC_PutDualChannelData12bLeftAlign(DAC_Type * DACx, uint32_t value)
{
DACx->DHR12LD = value;
}
/* bit[31:16] for channel 2, bit[15:0] for channel 1. */
void DAC_PutDualChannelData12bRightAlign(DAC_Type * DACx, uint32_t value)
{
DACx->DHR12RD = value;
}
uint32_t DAC_GetData8bRegAddr(DAC_Type * DACx, uint32_t channel)
{
uint32_t ret = 0u;
if (channel == DAC_CHN_1)
{
ret = (uint32_t)(&(DACx->DHR8R1));
}
else if (channel == DAC_CHN_2)
{
ret = (uint32_t)(&(DACx->DHR8R2));
}
return ret;
}
uint32_t DAC_GetData12bLeftRegAddr(DAC_Type * DACx, uint32_t channel)
{
uint32_t ret = 0u;
if (channel == DAC_CHN_1)
{
ret = (uint32_t)(&(DACx->DHR12L1));
}
else if (channel == DAC_CHN_2)
{
ret = (uint32_t)(&(DACx->DHR12L2));
}
return ret;
}
uint32_t DAC_GetData12bRightRegAddr(DAC_Type * DACx, uint32_t channel)
{
uint32_t ret = 0;
if (channel == DAC_CHN_1)
{
ret = (uint32_t)(&(DACx->DHR12R1));
}
else if (channel == DAC_CHN_2)
{
ret = (uint32_t)(&(DACx->DHR12R2));
}
return ret;
}
uint32_t DAC_GetDualChannelData8bRegAddr(DAC_Type * DACx)
{
return (uint32_t)(&(DACx->DHR8RD));
}
uint32_t DAC_GetDualChannelData12bLeftRegAddr(DAC_Type * DACx)
{
return (uint32_t)(&(DACx->DHR12LD));
}
uint32_t DAC_GetDualChannelData12bRightRegAddr(DAC_Type * DACx)
{
return (uint32_t)(&(DACx->DHR12RD));
}
/* EOF. */

86
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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "hal_dma.h"
/* clear all the interrupt enables and disable the dma channel. */
uint32_t DMA_InitChannel(DMA_Type * DMAx, uint32_t channel, DMA_Channel_Init_Type * init)
{
uint32_t ccr = 0u;
if ( (init->XferMode == DMA_XferMode_MemoryToPeriph)
|| (init->XferMode == DMA_XferMode_MemoryToPeriphBurst) )
{
ccr |= DMA_CCR_DIR_MASK;
}
if ( (init->XferMode == DMA_XferMode_PeriphToMemoryBurst)
|| (init->XferMode == DMA_XferMode_MemoryToPeriphBurst) )
{
ccr |= DMA_CCR_MEM2MEM_MASK;
}
if (init->ReloadMode == DMA_ReloadMode_AutoReload)
{
ccr |= DMA_CCR_ARE_MASK;
}
else if (init->ReloadMode == DMA_ReloadMode_AutoReloadContinuous)
{
ccr |= (DMA_CCR_ARE_MASK | DMA_CCR_CIRC_MASK);
}
ccr |= DMA_CCR_PINC(init->PeriphAddrIncMode)
| DMA_CCR_MINC(init->MemAddrIncMode)
| DMA_CCR_PSIZE(init->XferWidth)
| DMA_CCR_MSIZE(init->XferWidth)
| DMA_CCR_PL(init->Priority)
;
DMAx->CH[channel].CCR = ccr;
DMAx->CH[channel].CNDTR = init->XferCount;
DMAx->CH[channel].CPAR = init->PeriphAddr;
DMAx->CH[channel].CMAR = init->MemAddr;
return 0u;
}
void DMA_EnableChannelInterrupts(DMA_Type * DMAx, uint32_t channel, uint32_t interrupts, bool enable)
{
if (enable)
{
DMAx->CH[channel].CCR |= (interrupts & 0xEu);
}
else
{
DMAx->CH[channel].CCR &= ~(interrupts & 0xEu);
}
}
uint32_t DMA_GetChannelInterruptStatus(DMA_Type * DMAx, uint32_t channel)
{
return (DMAx->ISR >> (channel * 4u)) & 0xFu;
}
void DMA_ClearChannelInterruptStatus(DMA_Type * DMAx, uint32_t channel, uint32_t interrupts)
{
DMAx->IFCR = ( (interrupts & 0xFu) << (channel * 4u) );
}
void DMA_EnableChannel(DMA_Type * DMAx, uint32_t channel, bool enable)
{
if (enable)
{
DMAx->CH[channel].CCR |= DMA_CCR_EN_MASK;
}
else
{
DMAx->CH[channel].CCR &= ~DMA_CCR_EN_MASK;
}
}
/* EOF. */

74
bsp/mm32/libraries/MM32F3270_HAL/MM32F3270_HAL_Driver/Src/hal_exti.c Normal file
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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "hal_exti.h"
void EXTI_EnableLineInterrupt(EXTI_Type * EXTIx, uint32_t lines, bool enable)
{
if (enable)
{
EXTIx->IMR |= lines;
}
else
{
EXTIx->IMR &= ~ lines;
}
}
void EXTI_EnableLineEvent(EXTI_Type * EXTIx, uint32_t lines, bool enable)
{
if (enable)
{
EXTIx->EMR |= lines;
}
else
{
EXTIx->EMR &= ~ lines;
}
}
void EXTI_SetTriggerIn(EXTI_Type * EXTIx, uint32_t lines, EXTI_TriggerIn_Type trgin)
{
switch (trgin)
{
case EXTI_TriggerIn_Disable:
EXTIx->RTSR &= ~ lines;
EXTIx->FTSR &= ~ lines;
break;
case EXTI_TriggerIn_RisingEdge:
EXTI->RTSR |= lines;
EXTIx->FTSR &= ~ lines;
break;
case EXTI_TriggerIn_FallingEdge:
EXTI->RTSR &= ~ lines;
EXTI->FTSR |= lines;
break;
case EXTI_TriggerIn_BothEdges:
EXTI->RTSR |= lines;
EXTI->FTSR |= lines;
break;
default:
break;
}
}
void EXTI_DoSwTrigger(EXTI_Type * EXTIx, uint32_t lines)
{
EXTIx->SWIER = lines;
}
uint32_t EXTI_GetLineStatus(EXTI_Type * EXTIx)
{
return EXTIx->PR;
}
void EXTI_ClearLineStatus(EXTI_Type * EXTIx, uint32_t lines)
{
EXTIx->PR |= lines;
}
/* EOF. */

115
bsp/mm32/libraries/MM32F3270_HAL/MM32F3270_HAL_Driver/Src/hal_fsmc.c Normal file
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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "hal_fsmc.h"
const uint32_t FSMC_BankBases[] =
{
FSMC_BANK0_BASE,
FSMC_BANK1_BASE,
FSMC_BANK2_BASE,
FSMC_BANK3_BASE
};
void FSMC_Init(FSMC_Type * FSMCx, FSMC_Init_Type * init)
{
FSMCx->SMSKR0 = ( (FSMCx->SMSKR0 & ~(FSMC_SMSKR0_MEMSIZE_MASK | FSMC_SMSKR0_MEMTYPE_MASK) )
| FSMC_SMSKR0_MEMSIZE(init->MemSize)
| FSMC_SMSKR0_MEMTYPE(init->MemType) )
;
}
void FSMC_SetConf(FSMC_Type * FSMCx, uint32_t index, FSMC_Conf_Type * init)
{
if (index >= FSMC_SMTMGR_REG_NUM)
{
return;
}
FSMCx->SMTMGRSET[index] = FSMC_SMTMGRSET_TRC(init->ReadPeriod)
| FSMC_SMTMGRSET_TAS(init->AddrSetTime)
| FSMC_SMTMGRSET_TWR(init->WriteHoldTime)
| FSMC_SMTMGRSET_TWP(init->WritePeriod)
| FSMC_SMTMGRSET_READYMODE(init->ReadySignal)
| FSMC_SMTMGRSET_SMREADPIPE(init->SMReadPipe)
;
switch (index)
{
case 0u:
FSMCx->SMCTLR = ( (FSMCx->SMCTLR & ~FSMC_SMCTLR_SMDATAWIDTHSET0_MASK)
| FSMC_SMCTLR_SMDATAWIDTHSET0(init->BusWidth) )
;
break;
case 1u:
FSMCx->SMCTLR = ( (FSMCx->SMCTLR & ~FSMC_SMCTLR_SMDATAWIDTHSET1_MASK)
| FSMC_SMCTLR_SMDATAWIDTHSET1(init->BusWidth) )
;
break;
case 2u:
FSMCx->SMCTLR = ( (FSMCx->SMCTLR & ~FSMC_SMCTLR_SMDATAWIDTHSET2_MASK)
| FSMC_SMCTLR_SMDATAWIDTHSET2(init->BusWidth) )
;
break;
default:
break;
}
}
/* only last enabled bankn is available. */
void FSMC_EnableConf(FSMC_Type * FSMCx, uint32_t index)
{
if (index >= FSMC_SMTMGR_REG_NUM)
{
return;
}
FSMCx->SMSKR0 = ( (FSMCx->SMSKR0 & ~FSMC_SMSKR0_REGSELECT_MASK)
| FSMC_SMSKR0_REGSELECT(index) )
;
}
void FSMC_PutData32(FSMC_Type * FSMCx, uint32_t bankn, uint32_t offset, uint32_t data)
{
(void)FSMCx;
*( (uint32_t *)(FSMC_BankBases[bankn] + offset) ) = data;
}
uint32_t FSMC_GetData32(FSMC_Type * FSMCx, uint32_t bankn, uint32_t offset)
{
(void)FSMCx;
return (*( (uint32_t *)(FSMC_BankBases[bankn] + offset) ) );
}
uint32_t FSMC_GetXferDataRegAddr(FSMC_Type *FSMCx, uint32_t bankn, uint32_t offset)
{
(void)FSMCx;
return (FSMC_BankBases[bankn] + offset);
}
void FSMC_PutData16(FSMC_Type * FSMCx, uint32_t bankn, uint32_t offset, uint16_t data)
{
(void)FSMCx;
*( (uint16_t *)(FSMC_BankBases[bankn] + offset) ) = data;
}
uint16_t FSMC_GetData16(FSMC_Type * FSMCx, uint32_t bankn, uint32_t offset)
{
(void)FSMCx;
return (*( (uint16_t *)(FSMC_BankBases[bankn] + offset) ) );
}
void FSMC_PutData8(FSMC_Type * FSMCx, uint32_t bankn, uint32_t offset, uint8_t data)
{
(void)FSMCx;
*( (uint8_t *)(FSMC_BankBases[bankn] + offset) ) = data;
}
uint8_t FSMC_GetData8(FSMC_Type * FSMCx, uint32_t bankn, uint32_t offset)
{
(void)FSMCx;
return (*( (uint8_t *)(FSMC_BankBases[bankn] + offset) ) );
}
/* EOF. */

149
bsp/mm32/libraries/MM32F3270_HAL/MM32F3270_HAL_Driver/Src/hal_gpio.c Normal file
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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "hal_gpio.h"
void GPIO_Init(GPIO_Type * GPIOx, GPIO_Init_Type * init)
{
uint8_t idx;
uint8_t i;
uint32_t pin;
__IO uint32_t * addr;
/* 1x. */
uint32_t dat = init->PinMode & 0xFu;
if (init->PinMode & 0x10u)
{
dat |= init->Speed;
}
/* 0x. */
addr = &(GPIOx->CRL);
for (i = 0u; i < 8u; i++)
{
idx = i * 4u;
if ( (init->Pins) & (1u << i) )
{
*addr = ( *addr & ~(0xFu << idx) ) | (dat << idx);
}
}
addr = &(GPIOx->CRH);
pin = init->Pins >> 8u;
for (i = 0u; i < 8u; i++)
{
idx = i * 4u;
if ( pin & (1u << i) )
{
*addr = ( *addr & ~(0xFu << idx) ) | (dat << idx);
}
}
/* 2x,4x. */
if (init->PinMode == GPIO_PinMode_In_PullDown)
{
GPIOx->BRR |= init->Pins;
}
else if (init->PinMode == GPIO_PinMode_In_PullUp)
{
GPIOx->BSRR |= init->Pins;
}
}
bool GPIO_ReadInDataBit(GPIO_Type * GPIOx, uint16_t pin)
{
return (GPIOx->IDR & pin);
}
uint16_t GPIO_ReadInData(GPIO_Type * GPIOx)
{
return (uint16_t)(GPIOx->IDR);
}
bool GPIO_ReadOutDataBit(GPIO_Type * GPIOx, uint16_t pins)
{
return (GPIOx->ODR & pins);
}
uint16_t GPIO_ReadOutData(GPIO_Type * GPIOx)
{
return (uint16_t)GPIOx->ODR;
}
void GPIO_SetBits(GPIO_Type * GPIOx, uint16_t pins)
{
GPIOx->BSRR = pins;
}
void GPIO_ClearBits(GPIO_Type * GPIOx, uint16_t pins)
{
GPIOx->BRR = pins;
}
void GPIO_WriteBit(GPIO_Type * GPIOx, uint16_t pins, uint16_t val)
{
(val != 0u) ? (GPIOx->BSRR = pins) : (GPIOx->BRR = pins);
}
void GPIO_WriteBits(GPIO_Type * GPIOx, uint16_t val)
{
GPIOx->ODR = val;
}
void GPIO_PinLock(GPIO_Type * GPIOx, uint16_t pins, bool enable_lock)
{
(enable_lock) ? (GPIOx->LCKR |= pins) : (GPIOx->LCKR &= ~pins);
}
void GPIO_PinLockConf(GPIO_Type * GPIOx, uint16_t pins)
{
GPIOx->LCKR = GPIO_LCKR_LCKK_MASK | GPIO_LCKR_LCK(pins);
GPIOx->LCKR = pins;
GPIOx->LCKR = GPIO_LCKR_LCKK_MASK | GPIO_LCKR_LCK(pins);
GPIOx->LCKR;
GPIOx->LCKR;
}
void GPIO_PinAFConf(GPIO_Type * GPIOx, uint16_t pins, uint8_t af)
{
uint32_t shift = 0u;
uint32_t idx = 0u;
uint32_t val = GPIOx->AFRL;
while (idx < 8u)
{
if ( ( (1u << idx) & pins) != 0u )
{
shift = idx * 4u;
val &= ~(0xFu << shift);
val |= (uint32_t)af << shift;
}
idx++;
}
GPIOx->AFRL = val;
val = GPIOx->AFRH;
while (idx < 16u)
{
if ( ( (1u << idx) & pins) != 0u )
{
shift = (idx - 8u) * 4u;
val &= ~(0xFu << shift);
val |= (uint32_t)af << shift;
}
idx++;
}
GPIOx->AFRH = val;
}
void GPIO_PortAFConfig(GPIO_Type * GPIOx, uint32_t af_high, uint32_t af_low)
{
GPIOx->AFRL = af_low;
GPIOx->AFRH = af_high;
}
/* EOF. */

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bsp/mm32/libraries/MM32F3270_HAL/MM32F3270_HAL_Driver/Src/hal_i2c.c Normal file
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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "hal_i2c.h"
/* Configure I2C speed to ordinary speed. */
static bool I2C_CalcBandrate(I2C_Type * I2Cx, uint32_t clk, uint32_t bandrate)
{
/*
* SCLH = (xSHR + 12) * I2C_CLK + tSYNC1;
* SCLL = (xSLR + 1) * I2C_CLK + tSYNC2;
* tSYNC1 & tSYNC2 equal 0 ~ 1 clk.
*/
if ( (clk / 24u) < bandrate ) /* the system clock cannot meet the baud rate requirement. */
{
return false;
}
else
{
uint32_t tmp = clk / bandrate;
I2Cx->SSHR = tmp / 2u - 12u; /* Configure high level count in normal speed. */
I2Cx->SSLR = tmp / 2u - 1u; /* Configure low level count in normal speed. */
I2Cx->FSHR = tmp / 2u - 14u; /* Configure high level count in fast speed. */
I2Cx->FSLR = tmp / 2u - 3u; /* Configure low level count in fast speed. */
return true;
}
}
/* Initialize I2C, Initialization failure return false, Initialization success return true. */
bool I2C_InitMaster(I2C_Type * I2Cx, I2C_Master_Init_Type * init)
{
I2Cx->ENR &= ~I2C_ENR_ENABLE_MASK; /* Disable I2C. */
if ( !I2C_CalcBandrate(I2Cx, init->ClockFreqHz, init->BaudRate) ) /* The system clock cannot meet the baud rate requirement. */
{
return false;
}
I2Cx->CR = I2C_CR_SPEED(1u);
/* Setup I2C. */
I2Cx->CR &= ~I2C_CR_MASTER10_MASK; /* Address format. */
I2Cx->CR |= I2C_CR_RESTART_MASK /* Generate restart signal. */
| I2C_CR_DISSLAVE_MASK /* Disable slave module. */
| I2C_CR_REPEN_MASK /* Enable sending restart condition. */
| I2C_CR_EMPINT_MASK /* Control tx_empty interrupt generation. */
| I2C_CR_MASTER_MASK; /* Enable master module. */
I2Cx->IMR = 0u; /* Close all interrupts. */
I2Cx->RXTLR = 0u; /* Configure the sending receive value. */
I2Cx->TXTLR = 0u; /* Configure the sending threshold value. */
return true; /* Initialize I2C succeeded, return true. */
}
/* Enable I2C. */
void I2C_Enable(I2C_Type * I2Cx, bool enable)
{
if (enable)
{
I2Cx->ENR |= I2C_ENR_ENABLE_MASK;
}
else
{
I2Cx->ENR &= ~I2C_ENR_ENABLE_MASK;
}
}
/* Configuration the target device address. */
void I2C_SetTargetAddr(I2C_Type * I2Cx, uint8_t addr)
{
I2Cx->TAR = I2C_TAR_ADDR(addr);
}
/* Get I2C target device address. */
uint16_t I2C_GetTargetAddr(I2C_Type * I2Cx)
{
return (I2Cx->TAR & I2C_TAR_ADDR_MASK);
}
/* Put data to target device. */
void I2C_PutData(I2C_Type * I2Cx, uint8_t val)
{
I2Cx->DR = I2C_DR_DAT(val);
}
/* Control read-write bit to prepare to read data. */
void I2C_PrepareToGetData(I2C_Type * I2Cx)
{
I2Cx->DR = I2C_DR_CMD_MASK;
}
/* Get the data received by target device. */
uint8_t I2C_GetData(I2C_Type * I2Cx)
{
return ( (uint8_t)I2Cx->DR );
}
/* Get the current status flags of the I2C module. */
uint32_t I2C_GetStatus(I2C_Type * I2Cx)
{
return I2Cx->SR;
}
/* Prepare for the stop, when transfer finish. */
void I2C_Stop(I2C_Type * I2Cx)
{
I2Cx->ENR |= I2C_ENR_ABORT_MASK; /* Prepare for the stop. */
I2Cx->TXABRT; /* Read register to release tx fifo. */
}
/* Enable I2C interrupt. */
void I2C_EnableInterrupts(I2C_Type * I2Cx, uint32_t interrupts, bool enable)
{
if (enable)
{
I2Cx->IMR |= interrupts;
}
else
{
I2Cx->IMR &= ~interrupts;
}
}
/* Get the current enabled interrupts the I2C module. */
uint32_t I2C_GetEnabledInterrupts(I2C_Type * I2Cx)
{
return I2Cx->IMR;
}
/* Get the I2C interrupt status flags of the I2C module. */
uint32_t I2C_GetInterruptStatus(I2C_Type * I2Cx)
{
return (I2Cx->RAWISR & I2Cx->IMR); /* To ensure that the acquired interrupt is an enabled interrupt. */
}
/* Clear I2C interrupt status. */
void I2C_ClearInterruptStatus(I2C_Type * I2Cx, uint32_t interrupts)
{
if ( (I2C_INT_RX_UNDER & interrupts) != 0u ) /* Clear receive buffer under status. */
{
I2Cx->RXUNDER;
}
if ( (I2C_INT_TX_ABORT & interrupts) != 0u ) /* Clear I2C transmit abort status. */
{
I2Cx->TXABRT;
}
if ( (I2C_INT_ACTIVE & interrupts) != 0u ) /* Clear I2C interface activation status. */
{
I2Cx->ACTIV;
}
if ( (I2C_INT_STOP & interrupts) != 0u ) /* Clear I2C stop condition detection status. */
{
I2Cx->STOP;
}
if ( (I2C_INT_START & interrupts) != 0u ) /* Clear I2C start condition detection status. */
{
I2Cx->START;
}
}
/* Performs polling tx. */
bool I2C_MasterWriteBlocking(I2C_Type * I2Cx, I2C_MasterXfer_Type * xfer)
{
/* Put register address. */
I2C_PutData(I2Cx, xfer->TxBuf[0u]);
uint32_t waittime1 = xfer->WaitTimes;
/* Wait to tx fifo empty. */
while ( (0u == (I2C_GetStatus(I2Cx) & I2C_STATUS_TX_EMPTY) ) && (0u != waittime1) )
{
waittime1--;
}
if (0u == waittime1) /* I2C write register address timeout. */
{
return false;
}
uint32_t waittime2 = xfer->WaitTimes;
/* Write data to target device. */
for (uint32_t i = 1u; i < xfer->TxLen; i++)
{
I2C_PutData(I2Cx, xfer->TxBuf[i]);
while ( ( 0u == (I2C_GetStatus(I2Cx) & I2C_STATUS_TX_EMPTY) ) && (0u != waittime2) ) /* Wait to tx fifo empty. */
{
waittime2--;
}
if (0u == waittime2) /* I2C write timeout. */
{
return false;
}
}
I2C_Stop(I2Cx); /* Prepare to stop send data. */
uint32_t waittime3 = xfer->WaitTimes;
/* Wait to I2C not active, which means stop is taking effect. */
while ( (I2C_GetStatus(I2Cx) & I2C_STATUS_ACTIVE) && (0u != waittime3) )
{
waittime3--;
}
if (0u == waittime3) /* The wait operation is timeout. */
{
return false;
}
/* Clear fifo and flags. */
I2C1->ICR;
I2C1->TXABRT;
return true;
}
/* Performs polling rx. */
bool I2C_MasterReadBlocking(I2C_Type * I2Cx, I2C_MasterXfer_Type * xfer)
{
I2C_PutData(I2Cx, xfer->TxBuf[0u]); /* Put device register address. */
uint32_t waittime1 = xfer->WaitTimes;
while ( ( 0u == (I2C_GetStatus(I2Cx) & I2C_STATUS_TX_EMPTY) ) && (0u != waittime1) ) /* Wait to tx fifo empty. */
{
waittime1--;
}
if (0u == waittime1)
{
return false;
}
/* read data from target device. */
for (uint32_t i = 0u; i < xfer->RxLen; i++)
{
I2C_PrepareToGetData(I2Cx); /* Swich read-write bit, prepare to get data. */
while ( 0u == (I2C_GetStatus(I2Cx) & I2C_STATUS_RX_NOTEMPTY) ) /* Wait to rx fifo not empty. */
{
if ( 0u == (I2C_GetStatus(I2Cx) & I2C_STATUS_ACTIVE) ) /* Receive is active. */
{
return false;
}
}
xfer->RxBuf[i] = I2C_GetData(I2Cx);
}
I2C_Stop(I2Cx); /* Prepare to stop I2C. */
uint32_t waittime2 = xfer->WaitTimes;
while ( (I2C_GetStatus(I2Cx) & I2C_STATUS_ACTIVE) && (0u != waittime2) ) /* Wait I2C not active, which means stop being effective. */
{
waittime2--;
}
if (0u == waittime2)
{
return false;
}
/* Clear fifo and flags. */
I2C1->ICR;
I2C1->TXABRT;
return true;
}
/* I2C master interrupt transfer of the I2C module. */
void I2C_MasterXfer(I2C_Type * I2Cx, I2C_MasterXfer_Type * xfer)
{
I2C_PutData(I2Cx, (uint8_t)xfer->TxBuf[0u]); /* Put target register address. */
I2C_EnableInterrupts(I2Cx, I2C_INT_TX_EMPTY | I2C_INT_TX_ABORT | I2C_INT_STOP, true); /* Enable tx required interrupt. */
xfer->TxIdx = 1u; /* One data has been sent. */
xfer->RxIdx = 0u;
xfer->TxLen--;
}
/* I2C Master handler. */
void I2C_MasterXferHandler(I2C_Type * I2Cx, I2C_MasterXfer_Type * xfer, uint32_t interrupts)
{
if ( 0u != (interrupts & I2C_INT_TX_ABORT) ) /* Early termination of program. */
{
I2C_EnableInterrupts(I2Cx, I2C_INT_TX_EMPTY | I2C_INT_TX_ABORT | I2C_INT_STOP, false); /* Clear the interrupt used for tx. */
if (NULL != xfer->AbortCallback)
{
xfer->AbortCallback(xfer); /* Use abort call back. */
}
}
else if ( 0u != (interrupts & I2C_INT_TX_EMPTY) ) /* Tx fifo is empty, can send data. */
{
if (I2C_Direction_Rx == xfer->Direction) /* The current operation is receive, the register address has been sent. */
{
I2C_EnableInterrupts(I2Cx, I2C_INT_TX_EMPTY | I2C_INT_TX_ABORT, false); /* Clear tx interrupt. */
I2C_EnableInterrupts(I2Cx, I2C_INT_RX_NOTEMPTY, true); /* Enable receive required interrupt. */
if (0u != xfer->RxLen) /* The data to be received is not 0. */
{
I2C_PrepareToGetData(I2Cx); /* Prepare to get data. */
xfer->RxLen--;
}
else
{
I2C_Stop(I2Cx); /* No more transmition, prepare to stop. */
}
}
else
{
if (0u == xfer->TxLen) /* Tx finish. */
{
I2C_EnableInterrupts(I2Cx, I2C_INT_TX_EMPTY | I2C_INT_TX_ABORT, false); /* Clear Tx interrupt. */
I2C_Stop(I2Cx); /* Prepare to stop. */
}
else
{
xfer->TxLen--;
I2C_PutData(I2Cx, xfer->TxBuf[xfer->TxIdx++]); /* Tx is not over, continue to put data. */
}
}
}
else if ( 0u != (interrupts & I2C_INT_RX_NOTEMPTY) ) /* Receive interrupt. */
{
if (0u == xfer->RxLen) /* Receive finish. */
{
xfer->RxBuf[xfer->RxIdx++] = I2C_GetData(I2Cx); /* Get last data from I2C bus. */
I2C_EnableInterrupts(I2Cx, I2C_INT_RX_NOTEMPTY, false); /* Clear receive interrupt. */
I2C_Stop(I2Cx); /* Prepare to stop. */
}
else
{
xfer->RxLen--; /* Current count length count -1. */
xfer->RxBuf[xfer->RxIdx++] = I2C_GetData(I2Cx); /* Receive is not over, continue to get data. */
I2C_PrepareToGetData(I2Cx); /* Prepare to get data. */
}
}
else if ( 0u != (interrupts & I2C_INT_STOP) ) /* Xfer stop. */
{
I2C_EnableInterrupts(I2Cx, I2C_INT_STOP, false); /* Clear stop interrupt. */
if ( (0u != xfer->TxLen) || (0u != xfer->RxLen) ) /* The transmission was not completed but terminated. */
{
if (NULL != xfer->AbortCallback)
{
xfer->AbortCallback(xfer); /* Early termination of program, abort callback. */
I2C1->ICR;
I2C1->TXABRT; /* Clear FIFO. */
}
}
else
{
if (NULL != xfer->DoneCallback)
{
xfer->DoneCallback(xfer); /* Transmission finish and stop, xfer done callback. */
I2C1->ICR;
I2C1->TXABRT; /* Clear FIFO. */
}
}
}
}
/* EOF. */

59
bsp/mm32/libraries/MM32F3270_HAL/MM32F3270_HAL_Driver/Src/hal_iwdg.c Normal file
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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "hal_iwdg.h"
void IWDG_Init(IWDG_Type * IWDGx, IWDG_Init_Type * init)
{
if ( NULL != init )
{
IWDGx->KR = IWDG_KEY_UNLOCK;
IWDGx->PR = init->Prescaler;
IWDGx->KR = IWDG_KEY_UNLOCK;
IWDGx->RLR = init->Relaod;
IWDG_DoReload(IWDGx);
}
}
void IWDG_Start(IWDG_Type * IWDGx)
{
IWDGx->KR = IWDG_KEY_ENABLE;
}
uint32_t IWDG_GetStatus(IWDG_Type * IWDGx)
{
return IWDGx->SR;
}
void IWDG_DoReload(IWDG_Type * IWDGx)
{
IWDGx->KR = IWDG_KEY_RELOAD;
}
void IWDG_EnableInterrupts(IWDG_Type * IWDGx, uint32_t interrupts, bool enable)
{
if( (true == enable ) && (IWDG_INT_ALMOST_TIMEOUT == interrupts) )
{
IWDGx->CR |= IWDG_CR_IRQSEL_MASK;
}
else
{
/* if IWDG_EnableInterrupts interrupt was enabled, only MCU reset can close it. */
}
}
void IWDG_ClearStatus(IWDG_Type * IWDGx, uint32_t status)
{
if( 0u != ( status & IWDG_CR_IRQCLR_MASK ) )
{
IWDGx->CR |= IWDG_CR_IRQCLR_MASK;
}
}
/* EOF. */

72
bsp/mm32/libraries/MM32F3270_HAL/MM32F3270_HAL_Driver/Src/hal_rcc.c Normal file
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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "hal_common.h"
#include "hal_rcc.h"
void RCC_EnableAHB1Periphs(uint32_t ahb1_periphs, bool enable)
{
(enable) ? (RCC->AHB1ENR |= ahb1_periphs) : (RCC->AHB1ENR &= ~ahb1_periphs);
}
void RCC_EnableAHB2Periphs(uint32_t ahb2_periphs, bool enable)
{
(enable) ? (RCC->AHB2ENR |= ahb2_periphs) : (RCC->AHB2ENR &= ~ahb2_periphs);
}
void RCC_EnableAHB3Periphs(uint32_t ahb3_periphs, bool enable)
{
(enable) ? (RCC->AHB3ENR |= ahb3_periphs) : (RCC->AHB3ENR &= ~ahb3_periphs);
}
void RCC_EnableAPB1Periphs(uint32_t apb1_periphs, bool enable)
{
(enable) ? (RCC->APB1ENR |= apb1_periphs) : (RCC->APB1ENR &= ~apb1_periphs);
}
void RCC_EnableAPB2Periphs(uint32_t apb2_periphs, bool enable)
{
(enable) ? (RCC->APB2ENR |= apb2_periphs) : (RCC->APB2ENR &= ~apb2_periphs);
}
void RCC_ResetAHB1Periphs(uint32_t ahb1_periphs)
{
RCC->AHB1RSTR |= ahb1_periphs;
RCC->AHB1RSTR &= ~ahb1_periphs;
}
void RCC_ResetAHB2Periphs(uint32_t ahb2_periphs)
{
RCC->AHB2RSTR |= ahb2_periphs;
RCC->AHB2RSTR &= ~ahb2_periphs;
}
void RCC_ResetAHB3Periphs(uint32_t ahb3_periphs)
{
RCC->AHB3RSTR |= ahb3_periphs;
RCC->AHB3RSTR &= ~ahb3_periphs;
}
void RCC_ResetAPB1Periphs(uint32_t apb1_periphs)
{
RCC->APB1RSTR |= apb1_periphs;
RCC->APB1RSTR &= ~apb1_periphs;
}
void RCC_ResetAPB2Periphs(uint32_t apb2_periphs)
{
RCC->APB2RSTR |= apb2_periphs;
RCC->APB2RSTR &= ~apb2_periphs;
}
void RCC_MCOConf(RCC_MCO_Type source)
{
RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_MCO_MASK) | RCC_CFGR_MCO(source);
}
/* EOF. */

372
bsp/mm32/libraries/MM32F3270_HAL/MM32F3270_HAL_Driver/Src/hal_rtc.c Normal file
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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "hal_rtc.h"
/* Initialize RTC. */
void RTC_Init(void)
{
/* Open access rights. */
RCC->BDCR |= RCC_BDCR_DBP_MASK;
/* Reset BKP. */
RCC->BDCR |= RCC_BDCR_BDRST_MASK;
RCC->BDCR &= ~RCC_BDCR_BDRST_MASK;
/* Enable clock source. */
RCC->BDCR |= RCC_BDCR_RTCSEL(1u);
RCC->BDCR &= ~RCC_BDCR_LSEON_MASK;
RCC->BDCR |= RCC_BDCR_LSEON_MASK;
/* Clear register synchronization status. */
RTC->CRL &= ~RTC_CRL_RSF_MASK;
}
/* Enable or disable access to RTC and backing registers. */
void RTC_EnableAccess(bool enable)
{
if (enable)
{
RCC->BDCR |= RCC_BDCR_DBP_MASK;
}
else
{
RCC->BDCR &= ~RCC_BDCR_DBP_MASK;
}
}
/* Enable backup domain software reset, the register of BKP is reset by the backup domain, not reset during power reset and system reset. */
void RTC_EnableReset(bool enable)
{
if (enable)
{
RCC->BDCR |= RCC_BDCR_BDRST_MASK;
}
else
{
RCC->BDCR &= ~RCC_BDCR_BDRST_MASK;
}
}
/* Get the current status flags of the RTC module. */
uint32_t RTC_GetStatus(void)
{
return RTC->CRL;
}
/* Clear the status flag of the RTC module. */
void RTC_ClearStatus(uint32_t status)
{
RTC->CRL &= ~status;
}
/* Get RTC clock source status. */
uint32_t RTC_GetClockStatus(void)
{
return RCC->BDCR;
}
/* Enable RTC clock. */
void RTC_Enable(bool enable)
{
if (enable)
{
RCC->BDCR |= RCC_BDCR_RTCEN_MASK;
}
else
{
RCC->BDCR &= ~RCC_BDCR_RTCEN_MASK;
}
}
/* Enable or disable the configuration mode, enable to enter configuration mode, this is a precondition for registers to write data. */
void RTC_EnableConf(bool enable)
{
if (enable)
{
RTC->CRL |= RTC_CRL_CNF_MASK;
}
else
{
RTC->CRL &= ~RTC_CRL_CNF_MASK;
}
}
/* Setup prescaler register, open configration module before put data into RTC register. */
void RTC_PutPrescalerData(uint32_t div)
{
RTC->CRL |= RTC_CRL_CNF_MASK; /* Enable the configuration mode. */
RTC->PRLH = div >> 16u; /* Setup the upper 16-bit value of prescaler. */
RTC->PRLL = div; /* Setup the lower 16-bit value of prescaler. */
RTC->CRL &= ~RTC_CRL_CNF_MASK; /* Disable the configuration mode. */
}
/* Setup counter register, open configration module before put data into RTC register. */
void RTC_PutCounterData(uint32_t cnt)
{
RTC->CRL |= RTC_CRL_CNF_MASK; /* Enable the configuration mode. */
RTC->CNTH = cnt >> 16u; /* Setup the upper 16-bit value of counter. */
RTC->CNTL = cnt; /* Setup the lower 16-bit value of counter. */
RTC->CRL &= ~RTC_CRL_CNF_MASK; /* Disable the configuration mode. */
}
/* Setup alarm register, open configration module before put data into RTC register. */
void RTC_PutAlarmData(uint32_t alarm)
{
RTC->CRL |= RTC_CRL_CNF_MASK; /* Enable the configuration mode. */
RTC->ALRH = alarm >> 16u; /* Setup the upper 16-bit value of alarm counter. */
RTC->ALRL = alarm; /* Setup the lower 16-bit value of alarm counter. */
RTC->CRL &= ~RTC_CRL_CNF_MASK; /* Disable the configuration mode. */
}
/* Get the data from counter of I2C module. */
uint32_t RTC_GetCounterData(void)
{
return ( (RTC->CNTH << 16u) | RTC->CNTL );
}
/* Get alarm count value which is used to alarm interrupt. */
uint32_t RTC_GetAlarmData(void)
{
return ( (RTC->ALRH << 16u) | RTC->ALRL);
}
/* Enable RTC interrupt of RTC module. */
void RTC_EnableInterrupts(uint32_t interrupts, bool enable)
{
if (enable)
{
RTC->CRH |= interrupts;
}
else
{
RTC->CRH &= ~interrupts;
}
}
/* Get the interrupts status flags of the RTC module. */
uint32_t RTC_GetInterruptStatus(void)
{
return RTC->CRL;
}
/* Clear the status of RTC interrupt. */
void RTC_ClearInterruptStatus(uint32_t interrupts)
{
RTC->CRL &= ~interrupts;
}
/* Get RTC interrupt enable status. */
uint32_t RTC_GetEnabledInterrupts(void)
{
return RTC->CRH;
}
/* Judging whether the current year is a leap year, an ordinary leap year or a century leap year. */
bool RTC_JudgeLeapYear(uint16_t years)
{
if (years % 4u == 0u)
{
if (years % 100u == 0u)
{
if (years % 400u == 0u)
{
return true; /* Century leap year. */
}
else
{
return false;
}
}
else
{
return true; /* Ordinary leap year. */
}
}
else
{
return false;
}
}
/* Month correction table, used for calculation of month. */
const uint8_t month_table[12u] = {31u, 28u, 31u, 30u, 31u, 30u, 31u, 31u, 30u, 31u, 30u, 31u};
/* Setup initialization time. */
bool RTC_SetTimeBlocking(RTC_Init_Type * init, RTC_Time_Type * time)
{
RTC_PutPrescalerData(init->Div); /* Setup prescaler. */
while ( (0u == (RTC_GetStatus() & RTC_STATUS_OPERATION) ) && (0u != (time->WaitTime--) ) ) /* Wait for write operation finish, only after the end of the previous write operation can new write be performed. */
{
}
/* Calculate the total number of seconds of the current configuration time. */
uint32_t seccnt = 0u;
if ( (init->Years < init->LYears) || (init->Years > init->HYears) ) /* Exceeding the specified year. */
{
return false;
}
/* Calculate the number of seconds from the lowest years to the current setup years. */
for (uint16_t years = init->LYears; years < init->Years; years++)
{
if ( RTC_JudgeLeapYear(years) )
{
seccnt += 31622400u; /* The number of seconds in leap year is 31622400. */
}
else
{
seccnt += 31536000u; /* The number of seconds in normal year is 31622400. */
}
}
/* Add up the seconds of the previous month. */
init->Months -= 1u; /* The month count starts from 0 instead of 1, so current months - 1. */
for (uint16_t months = 0u; months < init->Months; months++)
{
seccnt += (uint32_t)month_table[months] * 86400u; /* Calculate the number of seconds of months, the total number of seconds in a day is 86400. */
if ( ( RTC_JudgeLeapYear(init->Years) ) && (months == 1u) ) /* The time is in a leap year and february, add the number of seconds in one day. */
{
seccnt += 86400u; /* The number of seconds in day is 86400. */
}
}
/* Add up the seconds of the previous date. */
seccnt += (uint32_t)(init->Days - 1u) * 86400u; /* The day set for initialization is less than 24 hours, which needs to be subtracted by one day. */
seccnt += (uint32_t)(init->Hours) * 3600u; /* There are 3600 seconds in a hour. */
seccnt += (uint32_t)(init->Mins) * 60u; /* There are 60 seconds in a minute. */
seccnt += (init->Secs);
while ( (0u == (RTC_GetStatus() & RTC_STATUS_OPERATION)) && (0u != (time->WaitTime--) ) ) /* Wait for write operation finish, only after the end of the previous write operation can new write be performed. */
{
}
/* Configrate counter value. */
RTC_PutCounterData(seccnt); /* Put data into counter. */
while ( ( 0u == (RTC_GetStatus() & RTC_STATUS_OPERATION) ) && (0u != (time->WaitTime--) ) ) /* Wait for write operation finish. */
{
}
if (0u == time->WaitTime) /* Timeout. */
{
return false;
}
return true;
}
/* Calculate and get current time. */
void RTC_CalcTimeBlocking(RTC_Init_Type * init, RTC_Time_Type * time)
{
while ( 0u == (RTC_GetStatus() & RTC_STATUS_SYNC) && (0u != time->WaitTime) ) /* Wait for register synchronization, only register synchronization can read RTC register. */
{
time->WaitTime--;
}
uint32_t count = RTC_GetCounterData(); /* Get current seconds count. */
/* Calculated in days. */
uint16_t years = init->LYears;
uint32_t days = count / 86400u;
for (; days >= 365u; days -= 365u)
{
if ( RTC_JudgeLeapYear(years) ) /* Determine whether it is a leap year. */
{
if (days >= 366u)
{
days -= 1u;
}
else
{
break;
}
}
years++;
}
init->Years = years; /* Get current years. */
uint16_t months = 0u;
for (; days >= 28u; days -= 28u)
{
if ( ( true == RTC_JudgeLeapYear(init->Years) ) && (months == 1u) ) /* The time is February of leap year. */
{
if (days >= 29u)
{
days -= 1u;
}
else
{
break;
}
}
else
{
if (days >= month_table[months]) /* Reach the maximum number of days in the current month. */
{
days = days - month_table[months] + 28u;
}
else
{
break;
}
}
months++;
}
init->Months = months + 1u; /* Get current months. */
init->Days = days + 1u; /* Get current days. */
init->Hours = ( count % 86400u) / 3600u; /* Get current hours. */
init->Mins = ((count % 86400u) % 3600u) / 60u; /* Get current minutes. */
init->Secs = ((count % 86400u) % 3600u) % 60u; /* Get current seconds. */
}
/* Setup the alarm response time. */
bool RTC_SetAlarmBlocking(RTC_Time_Type * time)
{
RTC_EnableInterrupts(RTC_INT_ALARM, true); /* Enable alarm interrupt. */
while ( 0u == (RTC_GetStatus() & RTC_STATUS_SYNC) && (0u != time->WaitTime) ) /* Wait for register synchronization, only register synchronization can read RTC register. */
{
time->WaitTime--;
}
uint32_t value = RTC_GetCounterData(); /* Get the current total number of seconds. */
RTC_PutAlarmData(value + time->AlarmTime); /* Set alarm respond time. */
while ( 0u == (RTC_GetStatus() & RTC_STATUS_OPERATION) && (0u != time->WaitTime) ) /* Wait for write operation finish. */
{
time->WaitTime--;
}
if (0u == time->WaitTime)
{
return false;
}
return true;
}
/* RTC interrupt request handler. */
void RTC_TimeHandler(RTC_Init_Type * init, RTC_Time_Type * time, uint32_t interrupts)
{
/* Seconds interrupt. */
if ( ( 0u == (interrupts & RTC_INT_ALARM) ) && ( 1u == (interrupts & RTC_INT_SEC) ) )
{
RTC_CalcTimeBlocking(init, time); /* Get current time. */
if (time->SecDoneCallback)
{
(*(time->SecDoneCallback))((void *)time); /* Callback when seconds interrupt done. */
}
}
/* Alarm interrupt. */
if (0u != (interrupts & RTC_INT_ALARM) ) /* When the alarm count value is the same as the current count value, the alarm clock interrupt is generated. */
{
RTC_CalcTimeBlocking(init, time); /* Get current time. */
RTC_ClearInterruptStatus(RTC_INT_ALARM); /* Clear alarm interrupt status flag. */
if (time->AlarmDoneCallback)
{
(*(time->AlarmDoneCallback))((void *)time); /* Callback when alarm interrupt done. */
}
}
RTC_ClearInterruptStatus(RTC_INT_SEC | RTC_INT_OVERFLOW); /* Clear seconds interrupt status flag and overflow status flag. */
}
/* EOF. */

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bsp/mm32/libraries/MM32F3270_HAL/MM32F3270_HAL_Driver/Src/hal_sdio.c Normal file
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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "hal_sdio.h"
static void SDIO_SetPeriphClockBaseClock(SDIO_Type * SDIOx, uint32_t busclk_hz, uint32_t periph_1mhz);
void SDIO_Init(SDIO_Type * SDIOx, SDIO_Init_Type * init)
{
SDIO_Enable(SDIOx, true);
SDIOx->MMCCTRL = SDIO_MMCCTRL_OPMSEL(1) /* SD mode as default. */
| SDIO_MMCCTRL_SELSM(1) /* hardware auto mode. */
| SDIO_MMCCTRL_OUTM(0) /* open drain io mode. */
| SDIO_MMCCTRL_CLKSP(init->ClkLineSpeedDiv)
| SDIO_MMCCTRL_SELPTSM(init->BaseClkSrc)
| SDIO_MMCCTRL_DATWT(0) /* use 1b data width as default. */
| SDIO_MMCCTRL_MDEN(0) /* SD card as default. */
| SDIO_MMCCTRL_INTEN(0) /* unlock the interrupt switchers. */
| SDIO_MMCCTRL_RDWTEN(0) /* disable the read wait signal. */
;
SDIOx->MMCCTRL |= SDIO_MMCCTRL_SELSM_MASK;
if (init->BaseClkSrc == SDIO_BaseClkSrc_1MHz)
{
SDIO_SetPeriphClockBaseClock(SDIOx, init->BusClkHz, 1000000u);
}
SDIO_SetDataBusWidth(SDIOx, SDIO_DataBusWidth_1b);
SDIOx->MMCCRCCTL = 0u; /* disable all the crc feature. */
SDIOx->MMCIOMBCTL = 0u;
SDIOx->MMCCRCCTL = SDIO_MMCCRCCTL_CMDCRCEN_MASK | SDIO_MMCCRCCTL_DATCRCEN_MASK;
}
void SDIO_Enable(SDIO_Type * SDIOx, bool enable)
{
if (enable)
{
SDIOx->MMCCARDSEL |= SDIO_MMCCARDSEL_CTREN_MASK /* enable the card controller. */
| SDIO_MMCCARDSEL_ENPCLK_MASK /* enable the card clk. */
;
}
else
{
SDIOx->MMCCARDSEL &= ~(SDIO_MMCCARDSEL_CTREN_MASK | SDIO_MMCCARDSEL_ENPCLK_MASK);
}
}
static void SDIO_SetPeriphClockBaseClock(SDIO_Type * SDIOx, uint32_t busclk_hz, uint32_t periph_1mhz)
{
uint32_t div = busclk_hz / periph_1mhz / 2 - 1u;
SDIOx->MMCCARDSEL = (SDIOx->MMCCARDSEL & ~SDIO_MMCCARDSEL_TSCALE_MASK) | SDIO_MMCCARDSEL_TSCALE(div);
}
void SDIO_SetDataBusWidth(SDIO_Type *SDIOx, SDIO_DataBusWidth_Type width)
{
if (width == SDIO_DataBusWidth_1b)
{
SDIOx->MMCCTRL &= ~SDIO_MMCCTRL_DATWT_MASK;
}
else if (width == SDIO_DataBusWidth_4b)
{
SDIOx->MMCCTRL |= SDIO_MMCCTRL_DATWT_MASK;
}
}
/* return "SDIO_FLAG_XXXX." */
uint32_t SDIO_GetStatus(SDIO_Type * SDIOx)
{
uint32_t flags = SDIOx->CLRMMCINT;
/* add the flags for data fifo. */
if (SDIOx->BUFCTL & SDIO_BUFCTL_DBF_MASK)
{
flags |= SDIO_STATUS_DAT_BUF_FULL;
}
if (SDIOx->BUFCTL & SDIO_BUFCTL_DBE_MASK)
{
flags |= SDIO_STATUS_DAT_BUF_EMPTY;
}
return flags;
}
/* parameter flgas, refre to "SDIO_FLAG_XXXX." */
void SDIO_ClearStatus(SDIO_Type * SDIOx, uint32_t flags)
{
SDIOx->CLRMMCINT = (SDIO_STATUS_DAT0_BUSY - 1u) & flags;
/* SDIO_STATUS_DAT_BUF_FULL and SDIO_STATUS_DAT_BUF_EMPYT would be cleared by hardware automatically. */
}
/* parameter interrupts, refre to "SDIO_INT_XXXX." */
void SDIO_EnableInterrupts(SDIO_Type * SDIOx, uint32_t interrupts, bool enable)
{
if (enable)
{
SDIOx->MMCINTMASK |= interrupts;
}
else
{
SDIOx->MMCINTMASK &= ~interrupts;
}
}
void SDIO_EnableFifoDMA(SDIO_Type * SDIOx, bool enable)
{
uint32_t bufctl = SDIOx->BUFCTL & ~(SDIO_BUFCTL_DRM_MASK | SDIO_BUFCTL_DMAHEN_MASK);
if (enable)
{
SDIOx->BUFCTL = bufctl | SDIO_BUFCTL_DMAHEN_MASK ;
}
else
{
SDIOx->BUFCTL = SDIOx->BUFCTL | SDIO_BUFCTL_DRM_MASK;
}
}
/* parameter flgas, refre to "SDIO_CMD_FLAG_XXXX." */
void SDIO_ExecuteCmd(SDIO_Type * SDIOx, uint8_t cmd_index, uint32_t param, uint32_t flags)
{
/* setup parameter. */
SDIOx->CMDBUF[4] = 0x40 | cmd_index;
SDIOx->CMDBUF[3] = ((param & 0xff000000) >> 24);
SDIOx->CMDBUF[2] = ((param & 0xff0000 ) >> 16);
SDIOx->CMDBUF[1] = ((param & 0xff00 ) >> 8);
SDIOx->CMDBUF[0] = ( param & 0xff );
/* prepare the command. */
uint32_t cmd_io = SDIO_MMCIO_AUTOTR_MASK;
uint32_t cmd_io_ext = SDIOx->MMCIOMBCTL
& ~( SDIO_MMCIOMBCTL_SPMBDTR_MASK
| SDIO_MMCIOMBCTL_SMBDTD_MASK
| SDIO_MMCIOMBCTL_PAUTOTR_MASK );
if (0u != (flags & (SDIO_CMD_FLAG_READ_BLOCKS | SDIO_CMD_FLAG_READ_BLOCKS) ) )
{
if (0u != (flags & SDIO_CMD_FLAG_READ_BLOCKS))
{
cmd_io_ext |= SDIO_MMCIOMBCTL_SMBDTD_MASK;
}
/* write MMCIO and MMCIOMBCTL to execute the cmd. */
SDIOx->MMCIO = 0u;
SDIOx->MMCIOMBCTL = cmd_io_ext | SDIO_MMCIOMBCTL_SPMBDTR_MASK;
}
else
{
if (0u != (flags & SDIO_CMD_FLAG_READ_BLOCK) )
{
cmd_io |= SDIO_MMCIO_TRANSFDIR_MASK;
}
if (0u != (flags & SDIO_CMD_FLAG_READ_CID_CSD) )
{
cmd_io |= SDIO_MMCIO_CIDCSDRD_MASK;
}
//if (0u != (flags & SDIO_CMD_FLAG_FOLLOWED_DATA_BLOCK) )
//{
// cmd_io |= SDIO_MMCIO_CMDCH_MASK;
//}
//if (0u != (flags & SDIO_CMD_FLAG_STOP_TRAN) )
//{
// cmd_io |= SDIO_MMCIO_CMDAF_MASK;
//}
if (0u != (flags & SDIO_CMD_FLAG_ENABLE_DATA_XFER) )
{
cmd_io |= SDIO_MMCIO_AUTODATTR_MASK;
}
SDIOx->MMCIOMBCTL = cmd_io_ext;
SDIOx->MMCIO = cmd_io;
}
/* pending for the xfer done. */
while ( 0u == (SDIO_STATUS_CMD_DONE & SDIO_GetStatus(SDIOx)) )
{}
SDIO_ClearStatus(SDIOx, SDIO_STATUS_CMD_DONE);
}
void SDIO_ExecuteData(SDIO_Type * SDIOx, uint32_t cmd_flags)
{
uint32_t cmd_io_ext = SDIOx->MMCIOMBCTL
& ~( SDIO_MMCIOMBCTL_SPMBDTR_MASK
| SDIO_MMCIOMBCTL_SMBDTD_MASK
| SDIO_MMCIOMBCTL_PAUTOTR_MASK );
uint32_t cmd_io = 0u;
if (0u != (cmd_flags & SDIO_CMD_FLAG_WRITE_BLOCK) )
{
//SDIOx->MMCIO = SDIO_MMCIO_AUTODATTR_MASK;
cmd_io |= SDIO_MMCIO_AUTODATTR_MASK;
}
if (0u != (cmd_flags & SDIO_CMD_FLAG_READ_BLOCK) )
{
//SDIOx->MMCIO = SDIO_MMCIO_AUTODATTR_MASK | SDIO_MMCIO_TRANSFDIR_MASK;
cmd_io |= SDIO_MMCIO_AUTODATTR_MASK | SDIO_MMCIO_TRANSFDIR_MASK;
}
if (0u != (cmd_flags & SDIO_CMD_FLAG_WRITE_BLOCKS) )
{
cmd_io_ext |= SDIO_MMCIOMBCTL_SPMBDTR_MASK;
//SDIOx->MMCIOMBCTL = cmd_io_ext;
}
else if (0u != (cmd_flags & SDIO_CMD_FLAG_READ_BLOCKS) )
{
//SDIOx->MMCIO = SDIO_MMCIO_RESPCMDSEL_MASK | SDIO_MMCIO_AUTOTR_MASK;
//SDIOx->MMCIOMBCTL = cmd_io_ext | SDIO_MMCIOMBCTL_SPMBDTR_MASK | SDIO_MMCIOMBCTL_SMBDTD_MASK;
cmd_io_ext |= SDIO_MMCIOMBCTL_SPMBDTR_MASK | SDIO_MMCIOMBCTL_SMBDTD_MASK;
}
SDIOx->MMCIO = cmd_io;
SDIOx->MMCIOMBCTL = cmd_io_ext;
}
void SDIO_RequestResp(SDIO_Type * SDIOx, SDIO_RespType_Type type, uint32_t *resp)
{
uint32_t cmd_io = SDIO_MMCIO_AUTOTR_MASK | SDIO_MMCIO_RESPCMDSEL_MASK;
if (type == SDIO_RespType_R2)
{
cmd_io |= SDIO_MMCIO_CIDCSDRD_MASK;
}
SDIOx->MMCIO = cmd_io;
/* pending for the xfer done. */
while ( 0u == (SDIO_STATUS_CMD_DONE & SDIO_GetStatus(SDIOx)) )
{}
SDIO_ClearStatus(SDIOx, SDIO_STATUS_CMD_DONE | SDIO_STATUS_CMD_CRC_ERR);
*resp = (SDIOx->CMDBUF[3] << 24)
| (SDIOx->CMDBUF[2] << 16)
| (SDIOx->CMDBUF[1] << 8 )
| (SDIOx->CMDBUF[0]);
if (type == SDIO_RespType_R2)
{
resp++;
*resp = (SDIOx->CMDBUF[7] << 24)
| (SDIOx->CMDBUF[6] << 16)
| (SDIOx->CMDBUF[5] << 8 )
| (SDIOx->CMDBUF[4]);
resp++;
*resp = (SDIOx->CMDBUF[11] << 24)
| (SDIOx->CMDBUF[10] << 16)
| (SDIOx->CMDBUF[9 ] << 8 )
| (SDIOx->CMDBUF[8 ]);
resp++;
*resp = (SDIOx->CMDBUF[15] << 24)
| (SDIOx->CMDBUF[14] << 16)
| (SDIOx->CMDBUF[13] << 8 )
| (SDIOx->CMDBUF[12]);
}
}
void SDIO_PutFifoData(SDIO_Type * SDIOx, uint32_t dat)
{
SDIOx->DATABUF[0] = dat;
}
uint32_t SDIO_GetFifoData(SDIO_Type * SDIOx)
{
return SDIOx->DATABUF[0];
}
/* SDIO_BUFCTL_DBFEN bit would be cleared automatically by hardware. */
void SDIO_ClearFifoData(SDIO_Type * SDIOx)
{
SDIOx->BUFCTL |= SDIO_BUFCTL_DBFEN_MASK;
}
/* the direction of fifo operation is read. need to switch to write before any write operation,
* and back to read mannually before the read operation. */
void SDIO_SwitchFifoWrite(SDIO_Type * SDIOx, bool write)
{
if (write)
{
SDIOx->BUFCTL |= SDIO_BUFCTL_SBAD_MASK;
}
else
{
SDIOx->BUFCTL &= ~SDIO_BUFCTL_SBAD_MASK;
}
}
/* word_cnt is for 32-bit type. */
void SDIO_SetFifoWatermark(SDIO_Type * SDIOx, uint32_t word_cnt)
{
SDIOx->BUFCTL = (SDIOx->BUFCTL & ~SDIO_BUFCTL_DBML_MASK) | SDIO_BUFCTL_DBML(word_cnt);
}
void SDIO_SetMultiBlockCount(SDIO_Type * SDIOx, uint32_t blk_cnt)
{
SDIOx->MMCBLOCKCNT = blk_cnt;
}
void SDIO_EnableFifoReadWait(SDIO_Type * SDIOx, bool enable)
{
if (enable)
{
SDIOx->MMCCTRL |= SDIO_MMCCTRL_RDWTEN_MASK;
}
else
{
SDIOx->MMCCTRL &= ~SDIO_MMCCTRL_RDWTEN_MASK;
}
}
/* EOF. */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "hal_spi.h"
void SPI_SetBaudrate(SPI_Type * SPIx, uint32_t src_clk, uint32_t baudrate)
{
uint32_t div = src_clk / baudrate;
if (div < 2u)
{
/* div = 0, 1 is not allowed. */
div = 2u;
}
SPIx->SPBRG = div;
if (div <= 4)
{
/* to support high speed mode. */
SPIx->CCTL |= (SPI_I2S_CCTL_TXEDGE_MASK | SPI_I2S_CCTL_RXEDGE_MASK);
}
else
{
SPIx->CCTL &= ~(SPI_I2S_CCTL_TXEDGE_MASK | SPI_I2S_CCTL_RXEDGE_MASK);
}
}
/* SPI peripheral is disabled just after the initialization.
* user needs to call SPI_Enable() before using the module.
*/
void SPI_InitMaster(SPI_Type * SPIx, SPI_Master_Init_Type * init)
{
/* Master. */
SPIx->GCTL = SPI_I2S_GCTL_MODE_MASK; /* master mode, disable spi, and reset the other bits in CCTL. */
/* XferMode. */
switch (init->XferMode)
{
case SPI_XferMode_RxOnly:
SPIx->GCTL |= SPI_I2S_GCTL_RXEN_MASK;
break;
case SPI_XferMode_TxRx:
SPIx->GCTL |= (SPI_I2S_GCTL_RXEN_MASK | SPI_I2S_GCTL_TXEN_MASK);
break;
default:
break;
}
/* AutoCS. */
if (init->AutoCS)
{
SPIx->GCTL |= SPI_I2S_GCTL_NSS_MASK;
}
else
{
SPIx->GCTL &= ~SPI_I2S_GCTL_NSS_MASK;
}
/* Interrupts. Always enable the global interrupt. The specific events are controlled by each bits in INTEN register. */
SPIx->GCTL |= SPI_I2S_GCTL_INTEN_MASK;
/* BaudRate. */
SPI_SetBaudrate(SPIx, init->ClockFreqHz, init->BaudRate);
/* DataWidth. */
if (init->DataWidth == SPI_DataWidth_8b)
{
SPIx->GCTL &= ~SPI_I2S_GCTL_DW832_MASK;
}
else
{
SPIx->GCTL |= SPI_I2S_GCTL_DW832_MASK;
SPIx->EXTCTL = SPI_I2S_EXTCTL_EXTLEN(init->DataWidth);
}
/* CPOL & CPHA. */
SPIx->CCTL = (SPIx->CCTL & ~(SPI_I2S_CCTL_CPHA_MASK | SPI_I2S_CCTL_CPOL_MASK))
| ( (SPI_I2S_CCTL_CPHA_MASK | SPI_I2S_CCTL_CPOL_MASK) & ((init->PolarityPhase) << SPI_I2S_CCTL_CPHA_SHIFT) );
/* MSB. */
if (init->LSB)
{
SPIx->CCTL |= SPI_I2S_CCTL_LSBFE_MASK;
}
else
{
SPIx->CCTL &= ~SPI_I2S_CCTL_LSBFE_MASK;
}
}
void SPI_Enable(SPI_Type * SPIx, bool enable)
{
if (enable)
{
SPIx->GCTL |= SPI_I2S_GCTL_SPIEN_MASK;
}
else
{
SPIx->GCTL &= ~SPI_I2S_GCTL_SPIEN_MASK;
}
}
uint32_t SPI_GetStatus(SPI_Type * SPIx)
{
return SPIx->CSTAT;
}
void SPI_EnableInterrupts(SPI_Type * SPIx, uint32_t interrupts, bool enable)
{
if (enable)
{
SPIx->INTEN |= interrupts;
}
else
{
SPIx->INTEN &= ~interrupts;
}
}
uint32_t SPI_GetInterruptStatus(SPI_Type * SPIx)
{
return SPIx->INTSTAT;
}
void SPI_ClearInterruptStatus(SPI_Type * SPIx, uint32_t interrupts)
{
SPIx->INTCLR = interrupts;
}
void SPI_PutData(SPI_Type * SPIx, uint32_t dat)
{
SPIx->TXREG = dat;
}
uint32_t SPI_GetData(SPI_Type * SPIx)
{
return SPIx->RXREG;
}
void SPI_EnableDMA(SPI_Type * SPIx, bool enable)
{
if (enable)
{
SPIx->GCTL |= SPI_I2S_GCTL_DMAMODE_MASK;
}
else
{
SPIx->GCTL &= ~SPI_I2S_GCTL_DMAMODE_MASK;
}
}
uint32_t SPI_GetEnabledInterrupts(SPI_Type * SPIx)
{
return SPIx->INTEN;
}
uint32_t SPI_GetRxDataRegAddr(SPI_Type * SPIx)
{
return (uint32_t)(&(SPIx->RXREG));
}
uint32_t SPI_GetTxDataRegAddr(SPI_Type * SPIx)
{
return (uint32_t)(&(SPIx->TXREG));
}
void SPI_EnableCS(SPI_Type * SPIx, uint32_t cs_mask)
{
SPIx->NSSR = ~(cs_mask);
}
/* EOF. */

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bsp/mm32/libraries/MM32F3270_HAL/MM32F3270_HAL_Driver/Src/hal_syscfg.c Normal file
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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "hal_syscfg.h"
#define SYSCFG_EXTICR_MASK(x) ( (0x0Fu) << ( ( (uint32_t)(x) & 0x3u ) << 2u ) ) /* mask bit for clear exti line. */
#define SYSCFG_EXTICR(x, y) ( (uint32_t)( (uint32_t)(x) << ( ( (uint32_t)(y) & 0x3u ) << 2u ) ) ) /* set the data for indicated exti port and line. */
void SYSCFG_SetBootMemMode(SYSCFG_BootMemMode_Type mode)
{
SYSCFG->CFGR = ( SYSCFG->CFGR & ~ SYSCFG_CFGR_MEMMODE_MASK )
| SYSCFG_CFGR_MEMMODE(mode);
}
void SYSCFG_SetFSMCPinUseMode(SYSCFG_FSMCPinUseMode_Type mode)
{
SYSCFG->CFGR = ( SYSCFG->CFGR & ~ SYSCFG_CFGR_FCODATAEN_MASK )
| SYSCFG_CFGR_FCODATAEN(mode);
}
void SYSCFG_SetFSMCMode(SYSCFG_FSMCMode_Type mode)
{
SYSCFG->CFGR = ( SYSCFG->CFGR & ~ SYSCFG_CFGR_MODESEL_MASK )
| SYSCFG_CFGR_MODESEL(mode);
}
void SYSCFG_SetExtIntMux(SYSCFG_EXTIPort_Type port, SYSCFG_EXTILine_Type line)
{
if ( line < SYSCFG_EXTILine_4)
{
SYSCFG->EXTICR1 = ( SYSCFG->EXTICR1 & ~ SYSCFG_EXTICR_MASK(line) )
| ( SYSCFG_EXTICR(port, line) );
}
else if ( line < SYSCFG_EXTILine_8 )
{
SYSCFG->EXTICR2 = ( SYSCFG->EXTICR1 & ~ SYSCFG_EXTICR_MASK(line) )
| ( SYSCFG_EXTICR(port, line) );
}
else if ( line < SYSCFG_EXTILine_12 )
{
SYSCFG->EXTICR3 = ( SYSCFG->EXTICR1 & ~ SYSCFG_EXTICR_MASK(line) )
| ( SYSCFG_EXTICR(port, line) );
}
else
{
SYSCFG->EXTICR4 = ( SYSCFG->EXTICR1 & ~ SYSCFG_EXTICR_MASK(line) )
| ( SYSCFG_EXTICR(port, line) );
}
}
void SYSCFG_SetI2C0PortMode(SYSCFG_I2CPortMode_Type mode)
{
SYSCFG->CFGR2 = ( SYSCFG->CFGR2 & ~ SYSCFG_CFGR2_I2C1MODESEL_MASK )
| SYSCFG_CFGR2_I2C1MODESEL(mode);
}
void SYSCFG_SetI2C1PortMode(SYSCFG_I2CPortMode_Type mode)
{
SYSCFG->CFGR2 = ( SYSCFG->CFGR2 & ~ SYSCFG_CFGR2_I2C2MODESEL_MASK )
| SYSCFG_CFGR2_I2C2MODESEL(mode);
}
void SYSCFG_SetENETPortMode(SYSCFG_ENETPortMode_Type mode)
{
SYSCFG->CFGR2 = ( SYSCFG->CFGR2 & ~ SYSCFG_CFGR2_MIIRMIISEL_MASK )
| SYSCFG_CFGR2_MIIRMIISEL(mode);
}
void SYSCFG_SetENETSpeedMode(SYSCFG_ENETSpeedMode_Type mode)
{
SYSCFG->CFGR2 = ( SYSCFG->CFGR2 & ~ SYSCFG_CFGR2_MACSPDSEL_MASK )
| SYSCFG_CFGR2_MACSPDSEL(mode);
}
void SYSCFG_EnablePVD(SYSCFG_PVDConf_Type * conf)
{
if (conf == NULL)
{
SYSCFG->PDETCSR &= ~ SYSCFG_PDETCSR_PVDE_MASK;
}
else
{
SYSCFG->PDETCSR = ( ( SYSCFG->PDETCSR & ~ ( SYSCFG_PDETCSR_PVDE_MASK
| SYSCFG_PDETCSR_PLS_MASK
| SYSCFG_PDETCSR_PVDO_MASK
) )
| SYSCFG_PDETCSR_PLS(conf->Thold)
| SYSCFG_PDETCSR_PVDO(conf->Output)
| SYSCFG_PDETCSR_PVDE_MASK
);
}
}
void SYSCFG_EnableVDT(SYSCFG_VDTConf_Type * conf)
{
if (conf == NULL)
{
SYSCFG->PDETCSR &= ~ SYSCFG_PDETCSR_VDTE_MASK;
}
else
{
SYSCFG->PDETCSR = ( ( SYSCFG->PDETCSR & ~ ( SYSCFG_PDETCSR_VDTE_MASK
| SYSCFG_PDETCSR_VDTLS_MASK
| SYSCFG_PDETCSR_VDTO_MASK
) )
| SYSCFG_PDETCSR_VDTLS(conf->Thold)
| SYSCFG_PDETCSR_VDTO(conf->Output)
| SYSCFG_PDETCSR_VDTE_MASK
);
}
}
void SYSCFG_EnableADCCheckVBatDiv3(bool enable)
{
if (enable)
{
SYSCFG->PDETCSR |= SYSCFG_PDETCSR_VBATDIV3EN_MASK;
}
else
{
SYSCFG->PDETCSR &= ~ SYSCFG_PDETCSR_VBATDIV3EN_MASK;
}
}
void SYSCFG_SetVOSDelayValue(uint32_t val)
{
SYSCFG->VOSDLY = val;
}
/* EOF. */

302
bsp/mm32/libraries/MM32F3270_HAL/MM32F3270_HAL_Driver/Src/hal_tim_16b.c Normal file
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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "hal_tim_16b.h"
bool TIM_16B_Init(TIM_16B_Type * TIMx, TIM_16B_Init_Type * init)
{
uint32_t cr1 = TIMx->CR1 &~ ( TIM_16B_CR1_OPM_MASK
| TIM_16B_CR1_APRE_MASK
| TIM_16B_CR1_CMS_MASK
| TIM_16B_CR1_DIR_MASK
);
cr1 |= TIM_16B_CR1_OPM(init->PeriodMode);
cr1 |= ((init->EnablePreloadPeriod) ? TIM_16B_CR1_APRE_MASK: 0u);
switch ( init->CountMode )
{
case TIM_16B_CountMode_Increasing:
break;
case TIM_16B_CountMode_Decreasing:
cr1 |= TIM_16B_CR1_DIR_MASK;
break;
case TIM_16B_CountMode_CenterAligned1:
cr1 |= TIM_16B_CR1_CMS(1u);
break;
case TIM_16B_CountMode_CenterAligned2:
cr1 |= TIM_16B_CR1_CMS(2u);
break;
case TIM_16B_CountMode_CenterAligned3:
cr1 |= TIM_16B_CR1_CMS(3u);
break;
default:
break;
}
TIMx->CR1 = cr1;
/* Check the vadility of StepFreqHz. */
if ( (init->StepFreqHz == 0u) || (init->StepFreqHz > init->ClockFreqHz) )
{
return false;
}
/* Calculate the prescaler. */
TIMx->PSC = init->ClockFreqHz / init->StepFreqHz - 1u;
TIMx->ARR = init->Period;
return true;
}
void TIM_16B_Start(TIM_16B_Type * TIMx)
{
TIMx->CR1 |= TIM_16B_CR1_CEN_MASK;
}
void TIM_16B_Stop(TIM_16B_Type * TIMx)
{
TIMx->CR1 &= ~TIM_16B_CR1_CEN_MASK;
}
uint32_t TIM_16B_GetCounterValue(TIM_16B_Type * TIMx)
{
return TIMx->CNT;
}
void TIM_16B_ClearCounterValue(TIM_16B_Type * TIMx)
{
TIMx->CNT = 0u;
}
void TIM_16B_EnableInterrupts(TIM_16B_Type * TIMx, uint32_t interrupts, bool enable)
{
if (enable)
{
TIMx->DIER |= interrupts;
}
else
{
TIMx->DIER &= ~interrupts;
}
}
void TIM_16B_EnableDMA(TIM_16B_Type * TIMx, uint32_t dmas, bool enable)
{
if (enable)
{
TIMx->DIER |= dmas;
}
else
{
TIMx->DIER &= ~dmas;
}
}
void TIM_16B_DoSwTrigger(TIM_16B_Type * TIMx, uint32_t swtrgs)
{
TIMx->EGR = swtrgs;
}
uint32_t TIM_16B_GetInterruptStatus(TIM_16B_Type * TIMx)
{
return TIMx->SR;
}
void TIM_16B_ClearInterruptStatus(TIM_16B_Type * TIMx, uint32_t status)
{
TIMx->SR &= ~status;
}
/*******************************/
static void _TIM_16B_WriteChannelCtrlReg(TIM_16B_Type * TIMx, uint32_t channel, uint32_t regval)
{
switch (channel)
{
case TIM_16B_CHN_1:
TIMx->CCMR1 = (TIMx->CCMR1 & ~(0xFF)) | (regval & 0xFF);
break;
case TIM_16B_CHN_2:
TIMx->CCMR1 = (TIMx->CCMR1 & ~(0xFF00)) | ((regval & 0xFF) << 8u);
break;
case TIM_16B_CHN_3:
TIMx->CCMR2 = (TIMx->CCMR2 & ~(0xFF)) | (regval & 0xFF);
break;
case TIM_16B_CHN_4:
TIMx->CCMR2 = (TIMx->CCMR2 & ~(0xFF00)) | ((regval & 0xFF) << 8u);
break;
default:
break;
}
}
void TIM_16B_EnableOutputCompare(TIM_16B_Type * TIMx, uint32_t channel, TIM_16B_OutputCompareConf_Type * conf)
{
uint32_t regval = TIM_16B_CCMR1_CC1S(TIM_16B_ChannelIOMode_Out) /* output compare mode. */
| ( (conf->EnableFastOutput) ? TIM_16B_CCMR1_OC1FE_MASK : 0u ) /* fast output. */
| ( (conf->EnablePreLoadChannelValue) ? TIM_16B_CCMR1_OC1PE_MASK : 0u) /* preload of channel value. */
| TIM_16B_CCMR1_OC1M(conf->RefOutMode) /* output compare comparison mode. */
| ( (conf->ClearRefOutOnExtTrigger) ? TIM_16B_CCMR1_OC1CE_MASK : 0u) /* external trigger clear ref. */
;
_TIM_16B_WriteChannelCtrlReg(TIMx, channel, regval);
TIM_16B_PutChannelValue(TIMx, channel, conf->ChannelValue);
switch (conf->PinPolarity)
{
case TIM_16B_PinPolarity_Disable:
TIMx->CCER &= ~( TIM_16B_CCER_CC1E_MASK << (channel<<2u) );
break;
case TIM_16B_PinPolarity_Rising:
TIMx->CCER = ( TIMx->CCER & ~(0xF << (channel<<2u)) )
| (( TIM_16B_CCER_CC1E_MASK /* Enable the pin output / input. */
) << (channel<<2u));
break;
case TIM_16B_PinPolarity_Falling:
TIMx->CCER = ( TIMx->CCER & ~(0xF << (channel<<2u)) )
| (( TIM_16B_CCER_CC1E_MASK /* Enable the pin output / input. */
| TIM_16B_CCER_CC1P_MASK /* Set output active polarity. */
| ~TIM_16B_CCER_CC1NP_MASK
) << (channel<<2u));
break;
default:
break;
}
}
void TIM_16B_EnableInputCapture(TIM_16B_Type * TIMx, uint32_t channel, TIM_16B_InputCaptureConf_Type * conf)
{
uint32_t regval = TIM_16B_CCMR1_CC1S(TIM_16B_ChannelIOMode_In) /* input capture mode. */
| TIM_16B_CCMR1_IC1PSC(conf->InDiv)
| TIM_16B_CCMR1_IC1F(conf->InFilter)
;
_TIM_16B_WriteChannelCtrlReg(TIMx, channel, regval);
switch (conf->PinPolarity)
{
case TIM_16B_PinPolarity_Disable:
TIMx->CCER &= ~(TIM_16B_CCER_CC1E_MASK << (channel<<2u));
break;
case TIM_16B_PinPolarity_Rising:
TIMx->CCER = (TIMx->CCER & ~(0xF << (channel<<2u)) )
| (( TIM_16B_CCER_CC1E_MASK /* Enable the pin output / input */
) << (channel<<2u) );
break;
case TIM_16B_PinPolarity_Falling:
TIMx->CCER = ( TIMx->CCER & ~(0xF << (channel<<2u)) )
| (( TIM_16B_CCER_CC1E_MASK /* Enable the pin output / input */
| TIM_16B_CCER_CC1P_MASK /* Set active input edge. */
) << (channel<<2u) );
break;
case TIM_16B_PinPolarity_RisingOrFalling:
TIMx->CCER = ( TIMx->CCER & ~(0xF << (channel<<2u)) )
| (( TIM_16B_CCER_CC1E_MASK /* Enable the pin output / input */
| TIM_16B_CCER_CC1P_MASK /* Set active input edge. */
| TIM_16B_CCER_CC1NP_MASK
) << (channel<<2u) );
break;
default:
break;
}
}
uint16_t TIM_16B_GetChannelValue(TIM_16B_Type * TIMx, uint32_t channel)
{
return TIMx->CCR[channel];
}
void TIM_16B_PutChannelValue(TIM_16B_Type * TIMx, uint32_t channel, uint16_t value)
{
TIMx->CCR[channel] = value;
}
void TIM_16B_EnableDeadArea(TIM_16B_Type * TIMx, TIM_16B_DeadAreaConf_Type * conf)
{
TIMx->CR1 = ( TIMx->CR1 &~ TIM_16B_CR1_CKD_MASK )
| ( TIM_16B_CR1_CKD(conf->StepFreqHz) ); /* set the frequncy ratio. */
}
void TIM_16B_EnableMasterMode(TIM_16B_Type * TIMx, TIM_16B_MasterModeConf_Type * conf)
{
TIMx->CR2 = ( TIMx->CR2 &~ TIM_16B_CR2_MMS_MASK )
| ( TIM_16B_CR2_MMS(conf->Out) ); /* Set master mode output. */
uint32_t smcr = TIMx->SMCR &~ TIM_16B_SMCR_MSM_MASK;
if (conf->EnableSync) /* synchronize with slave timers. */
{
smcr |= TIM_16B_SMCR_MSM_MASK;
}
TIMx->SMCR = smcr;
}
void TIM_16B_EnableSlaveMode(TIM_16B_Type * TIMx, TIM_16B_SlaveModeConf_Type * conf)
{
if ( conf->Resp != TIM_16B_SlaveResp_Disable )
{
TIMx->SMCR = ( TIMx->SMCR &~ ( TIM_16B_SMCR_TS_MASK
| TIM_16B_SMCR_SMS_MASK
) )
| TIM_16B_SMCR_TS(conf->In) /* set input trigger source. */
| TIM_16B_SMCR_SMS(conf->Resp); /* set response to the source */
}
else
{
TIMx->SMCR &= ~ TIM_16B_SMCR_SMS_MASK;
}
}
void TIM_16B_EnableExtTriggerIn(TIM_16B_Type * TIMx, TIM_16B_ExtTriggerInConf_Type * conf)
{
uint32_t smcr = TIMx->SMCR &~ ( TIM_16B_SMCR_ETPS_MASK
| TIM_16B_SMCR_ETF_MASK
| TIM_16B_SMCR_ECE_MASK
| TIM_16B_SMCR_ETP_MASK
);
switch (conf->PinPolarity)
{
case TIM_16B_PinPolarity_Disable:
break;
case TIM_16B_PinPolarity_Rising:
smcr |= TIM_16B_SMCR_ECE_MASK; /* enable external trigger input. */
break;
case TIM_16B_PinPolarity_Falling:
smcr |= TIM_16B_SMCR_ETP_MASK; /* falling edge active. */
smcr |= TIM_16B_SMCR_ECE_MASK; /* enable external trigger input. */
break;
default:
break;
}
smcr |= TIM_16B_SMCR_ETPS( conf->InDiv ); /* division to the input external trigger. */
smcr |= TIM_16B_SMCR_ETF( conf->InFilter ); /* set filter. */
TIMx->SMCR = smcr;
}
uint32_t TIM_16B_EnableDMABurst(TIM_16B_Type * TIMx, TIM_16B_DMABurstConf_Type * conf)
{
TIMx->DCR = TIM_16B_DCR_DBA(conf->BaseAddr) | TIM_16B_DCR_DBL(conf->Length);
return (uint32_t)(&(TIMx->DMAR));
}
TIM_16B_EncoderDirection_Type TIM_16B_GetEncoder(TIM_16B_Type * TIMx, uint32_t * value)
{
if (value)
{
* value = TIM_16B_GetCounterValue(TIMx);
}
if ( (TIMx->CR1 & TIM_16B_CR1_DIR_MASK) != 0u )
{
return TIM_16B_EncoderDirection_Backward;
}
else
{
return TIM_16B_EncoderDirection_Forward;
}
}
/* EOF. */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "hal_tim_32b.h"
bool TIM_32B_Init(TIM_32B_Type * TIMx, TIM_32B_Init_Type * init)
{
uint32_t cr1 = TIMx->CR1 &~ ( TIM_32B_CR1_OPM_MASK
| TIM_32B_CR1_APRE_MASK
| TIM_32B_CR1_CMS_MASK
| TIM_32B_CR1_DIR_MASK
);
cr1 |= TIM_32B_CR1_OPM(init->PeriodMode);
cr1 |= ((init->EnablePreloadPeriod) ? TIM_32B_CR1_APRE_MASK: 0u);
switch ( init->CountMode )
{
case TIM_32B_CountMode_Increasing:
break;
case TIM_32B_CountMode_Decreasing:
cr1 |= TIM_32B_CR1_DIR_MASK;
break;
case TIM_32B_CountMode_CenterAligned1:
cr1 |= TIM_32B_CR1_CMS(1u);
break;
case TIM_32B_CountMode_CenterAligned2:
cr1 |= TIM_32B_CR1_CMS(2u);
break;
case TIM_32B_CountMode_CenterAligned3:
cr1 |= TIM_32B_CR1_CMS(3u);
break;
default:
break;
}
TIMx->CR1 = cr1;
/* Check the vadility of StepFreqHz. */
if ( (init->StepFreqHz == 0u) || (init->StepFreqHz > init->ClockFreqHz) )
{
return false;
}
/* Calculate the prescaler. */
TIMx->PSC = init->ClockFreqHz / init->StepFreqHz - 1u;
TIMx->ARR = init->Period;
return true;
}
void TIM_32B_Start(TIM_32B_Type * TIMx)
{
TIMx->CR1 |= TIM_32B_CR1_CEN_MASK;
}
void TIM_32B_Stop(TIM_32B_Type * TIMx)
{
TIMx->CR1 &= ~TIM_32B_CR1_CEN_MASK;
}
uint32_t TIM_32B_GetCounterValue(TIM_32B_Type * TIMx)
{
return TIMx->CNT;
}
void TIM_32B_ClearCounterValue(TIM_32B_Type * TIMx)
{
TIMx->CNT = 0u;
}
void TIM_32B_EnableInterrupts(TIM_32B_Type * TIMx, uint32_t interrupts, bool enable)
{
if (enable)
{
TIMx->DIER |= interrupts;
}
else
{
TIMx->DIER &= ~interrupts;
}
}
void TIM_32B_EnableDMA(TIM_32B_Type * TIMx, uint32_t dmas, bool enable)
{
if (enable)
{
TIMx->DIER |= dmas;
}
else
{
TIMx->DIER &= ~dmas;
}
}
void TIM_32B_DoSwTrigger(TIM_32B_Type * TIMx, uint32_t swtrgs)
{
TIMx->EGR = swtrgs;
}
uint32_t TIM_32B_GetInterruptStatus(TIM_32B_Type * TIMx)
{
return TIMx->SR;
}
void TIM_32B_ClearInterruptStatus(TIM_32B_Type * TIMx, uint32_t status)
{
TIMx->SR &= ~status;
}
/*******************************/
static void _TIM_32B_WriteChannelCtrlReg(TIM_32B_Type * TIMx, uint32_t channel, uint32_t regval)
{
switch (channel)
{
case TIM_32B_CHN_1:
TIMx->CCMR1 = (TIMx->CCMR1 & ~(0xFF)) | (regval & 0xFF);
break;
case TIM_32B_CHN_2:
TIMx->CCMR1 = (TIMx->CCMR1 & ~(0xFF00)) | ((regval & 0xFF) << 8u);
break;
case TIM_32B_CHN_3:
TIMx->CCMR2 = (TIMx->CCMR2 & ~(0xFF)) | (regval & 0xFF);
break;
case TIM_32B_CHN_4:
TIMx->CCMR2 = (TIMx->CCMR2 & ~(0xFF00)) | ((regval & 0xFF) << 8u);
break;
default:
break;
}
}
void TIM_32B_EnableOutputCompare(TIM_32B_Type * TIMx, uint32_t channel, TIM_32B_OutputCompareConf_Type * conf)
{
uint32_t regval = TIM_32B_CCMR1_CC1S(TIM_32B_ChannelIOMode_Out) /* output compare mode. */
| ( (conf->EnableFastOutput) ? TIM_32B_CCMR1_OC1FE_MASK : 0u ) /* fast output. */
| ( (conf->EnablePreLoadChannelValue) ? TIM_32B_CCMR1_OC1PE_MASK : 0u) /* preload of channel value. */
| TIM_32B_CCMR1_OC1M(conf->RefOutMode) /* output compare comparison mode. */
| ( (conf->ClearRefOutOnExtTrigger) ? TIM_32B_CCMR1_OC1CE_MASK : 0u) /* external trigger clear ref. */
;
_TIM_32B_WriteChannelCtrlReg(TIMx, channel, regval);
TIM_32B_PutChannelValue(TIMx, channel, conf->ChannelValue);
switch (conf->PinPolarity)
{
case TIM_32B_PinPolarity_Disable:
TIMx->CCER &= ~( TIM_32B_CCER_CC1E_MASK << (channel<<2u) );
break;
case TIM_32B_PinPolarity_Rising:
TIMx->CCER = ( TIMx->CCER & ~(0xF << (channel<<2u)) )
| (( TIM_32B_CCER_CC1E_MASK /* Enable the pin output / input. */
) << (channel<<2u));
break;
case TIM_32B_PinPolarity_Falling:
TIMx->CCER = ( TIMx->CCER & ~(0xF << (channel<<2u)) )
| (( TIM_32B_CCER_CC1E_MASK /* Enable the pin output / input. */
| TIM_32B_CCER_CC1P_MASK /* Set output active polarity. */
| ~TIM_32B_CCER_CC1NP_MASK
) << (channel<<2u));
break;
default:
break;
}
}
void TIM_32B_EnableInputCapture(TIM_32B_Type * TIMx, uint32_t channel, TIM_32B_InputCaptureConf_Type * conf)
{
uint32_t regval = TIM_32B_CCMR1_CC1S(TIM_32B_ChannelIOMode_In) /* input capture mode. */
| TIM_32B_CCMR1_IC1PSC(conf->InDiv)
| TIM_32B_CCMR1_IC1F(conf->InFilter)
;
_TIM_32B_WriteChannelCtrlReg(TIMx, channel, regval);
switch (conf->PinPolarity)
{
case TIM_32B_PinPolarity_Disable:
TIMx->CCER &= ~(TIM_32B_CCER_CC1E_MASK << (channel<<2u));
break;
case TIM_32B_PinPolarity_Rising:
TIMx->CCER = (TIMx->CCER & ~(0xF << (channel<<2u)) )
| (( TIM_32B_CCER_CC1E_MASK /* Enable the pin output / input */
) << (channel<<2u) );
break;
case TIM_32B_PinPolarity_Falling:
TIMx->CCER = ( TIMx->CCER & ~(0xF << (channel<<2u)) )
| (( TIM_32B_CCER_CC1E_MASK /* Enable the pin output / input */
| TIM_32B_CCER_CC1P_MASK /* Set active input edge. */
) << (channel<<2u) );
break;
case TIM_32B_PinPolarity_RisingOrFalling:
TIMx->CCER = ( TIMx->CCER & ~(0xF << (channel<<2u)) )
| (( TIM_32B_CCER_CC1E_MASK /* Enable the pin output / input */
| TIM_32B_CCER_CC1P_MASK /* Set active input edge. */
| TIM_32B_CCER_CC1NP_MASK
) << (channel<<2u) );
break;
default:
break;
}
}
uint32_t TIM_32B_GetChannelValue(TIM_32B_Type * TIMx, uint32_t channel)
{
return TIMx->CCR[channel];
}
void TIM_32B_PutChannelValue(TIM_32B_Type * TIMx, uint32_t channel, uint32_t value)
{
TIMx->CCR[channel] = value;
}
void TIM_32B_EnableDeadArea(TIM_32B_Type * TIMx, TIM_32B_DeadAreaConf_Type * conf)
{
TIMx->CR1 = ( TIMx->CR1 &~ TIM_32B_CR1_CKD_MASK )
| ( TIM_32B_CR1_CKD(conf->StepFreqHz) ); /* set the frequncy ratio. */
}
void TIM_32B_EnableMasterMode(TIM_32B_Type * TIMx, TIM_32B_MasterModeConf_Type * conf)
{
TIMx->CR2 = ( TIMx->CR2 &~ TIM_32B_CR2_MMS_MASK )
| ( TIM_32B_CR2_MMS(conf->Out) ); /* Set master mode output. */
uint32_t smcr = TIMx->SMCR &~ TIM_32B_SMCR_MSM_MASK;
if (conf->EnableSync) /* synchronize with slave timers. */
{
smcr |= TIM_32B_SMCR_MSM_MASK;
}
TIMx->SMCR = smcr;
}
void TIM_32B_EnableSlaveMode(TIM_32B_Type * TIMx, TIM_32B_SlaveModeConf_Type * conf)
{
if ( conf->Resp != TIM_32B_SlaveResp_Disable )
{
TIMx->SMCR = ( TIMx->SMCR &~ ( TIM_32B_SMCR_TS_MASK
| TIM_32B_SMCR_SMS_MASK
) )
| TIM_32B_SMCR_TS(conf->In) /* set input trigger source. */
| TIM_32B_SMCR_SMS(conf->Resp); /* set response to the source */
}
else
{
TIMx->SMCR &= ~ TIM_32B_SMCR_SMS_MASK;
}
}
void TIM_32B_EnableExtTriggerIn(TIM_32B_Type * TIMx, TIM_32B_ExtTriggerInConf_Type * conf)
{
uint32_t smcr = TIMx->SMCR &~ ( TIM_32B_SMCR_ETPS_MASK
| TIM_32B_SMCR_ETF_MASK
| TIM_32B_SMCR_ECE_MASK
| TIM_32B_SMCR_ETP_MASK
);
switch (conf->PinPolarity)
{
case TIM_32B_PinPolarity_Disable:
break;
case TIM_32B_PinPolarity_Rising:
smcr |= TIM_32B_SMCR_ECE_MASK; /* enable external trigger input. */
break;
case TIM_32B_PinPolarity_Falling:
smcr |= TIM_32B_SMCR_ETP_MASK; /* falling edge active. */
smcr |= TIM_32B_SMCR_ECE_MASK; /* enable external trigger input. */
break;
default:
break;
}
smcr |= TIM_32B_SMCR_ETPS( conf->InDiv ); /* division to the input external trigger. */
smcr |= TIM_32B_SMCR_ETF( conf->InFilter ); /* set filter. */
TIMx->SMCR = smcr;
}
uint32_t TIM_32B_EnableDMABurst(TIM_32B_Type * TIMx, TIM_32B_DMABurstConf_Type * conf)
{
TIMx->DCR = TIM_32B_DCR_DBA(conf->BaseAddr) | TIM_32B_DCR_DBL(conf->Length);
return (uint32_t)(&(TIMx->DMAR));
}
TIM_32B_EncoderDirection_Type TIM_32B_GetEncoder(TIM_32B_Type * TIMx, uint32_t * value)
{
if (value)
{
* value = TIM_32B_GetCounterValue(TIMx);
}
if ( (TIMx->CR1 & TIM_32B_CR1_DIR_MASK) != 0u )
{
return TIM_32B_EncoderDirection_Backward;
}
else
{
return TIM_32B_EncoderDirection_Forward;
}
}
/* EOF. */

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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "hal_tim_adv.h"
bool TIM_ADV_Init(TIM_ADV_Type * TIMx, TIM_ADV_Init_Type * init)
{
uint32_t cr1 = TIMx->CR1 &~ ( TIM_ADV_CR1_OPM_MASK
| TIM_ADV_CR1_APRE_MASK
| TIM_ADV_CR1_CMS_MASK
| TIM_ADV_CR1_DIR_MASK
);
cr1 |= TIM_ADV_CR1_OPM(init->PeriodMode);
cr1 |= ((init->EnablePreloadPeriod) ? TIM_ADV_CR1_APRE_MASK: 0u);
switch ( init->CountMode )
{
case TIM_ADV_CountMode_Increasing:
break;
case TIM_ADV_CountMode_Decreasing:
cr1 |= TIM_ADV_CR1_DIR_MASK;
break;
case TIM_ADV_CountMode_CenterAligned1:
cr1 |= TIM_ADV_CR1_CMS(1u);
break;
case TIM_ADV_CountMode_CenterAligned2:
cr1 |= TIM_ADV_CR1_CMS(2u);
break;
case TIM_ADV_CountMode_CenterAligned3:
cr1 |= TIM_ADV_CR1_CMS(3u);
break;
default:
break;
}
TIMx->CR1 = cr1;
/* Check the vadility of StepFreqHz. */
if ( (init->StepFreqHz == 0u) || (init->StepFreqHz > init->ClockFreqHz) )
{
return false;
}
/* Calculate the prescaler. */
TIMx->PSC = init->ClockFreqHz / init->StepFreqHz - 1u;
TIMx->ARR = init->Period;
return true;
}
void TIM_ADV_Start(TIM_ADV_Type * TIMx)
{
TIMx->CR1 |= TIM_ADV_CR1_CEN_MASK;
}
void TIM_ADV_Stop(TIM_ADV_Type * TIMx)
{
TIMx->CR1 &= ~TIM_ADV_CR1_CEN_MASK;
}
uint32_t TIM_ADV_GetCounterValue(TIM_ADV_Type * TIMx)
{
return TIMx->CNT;
}
void TIM_ADV_ClearCounterValue(TIM_ADV_Type * TIMx)
{
TIMx->CNT = 0u;
}
void TIM_ADV_EnableInterrupts(TIM_ADV_Type * TIMx, uint32_t interrupts, bool enable)
{
if (enable)
{
TIMx->DIER |= interrupts;
}
else
{
TIMx->DIER &= ~interrupts;
}
}
void TIM_ADV_EnableDMA(TIM_ADV_Type * TIMx, uint32_t dmas, bool enable)
{
if (enable)
{
TIMx->DIER |= dmas;
}
else
{
TIMx->DIER &= ~dmas;
}
}
void TIM_ADV_DoSwTrigger(TIM_ADV_Type * TIMx, uint32_t swtrgs)
{
TIMx->EGR = swtrgs;
}
uint32_t TIM_ADV_GetInterruptStatus(TIM_ADV_Type * TIMx)
{
return TIMx->SR;
}
void TIM_ADV_ClearInterruptStatus(TIM_ADV_Type * TIMx, uint32_t status)
{
TIMx->SR &= ~status;
}
/*******************************/
static void _TIM_ADV_WriteChannelCtrlReg(TIM_ADV_Type * TIMx, uint32_t channel, uint32_t regval)
{
switch (channel)
{
case TIM_ADV_CHN_1:
TIMx->CCMR1 = (TIMx->CCMR1 & ~(0xFF)) | (regval & 0xFF);
break;
case TIM_ADV_CHN_2:
TIMx->CCMR1 = (TIMx->CCMR1 & ~(0xFF00)) | ((regval & 0xFF) << 8u);
break;
case TIM_ADV_CHN_3:
TIMx->CCMR2 = (TIMx->CCMR2 & ~(0xFF)) | (regval & 0xFF);
break;
case TIM_ADV_CHN_4:
TIMx->CCMR2 = (TIMx->CCMR2 & ~(0xFF00)) | ((regval & 0xFF) << 8u);
break;
default:
break;
}
}
static void _TIM_ADV_EnableChannel5OutputCompare(TIM_ADV_Type * TIMx, TIM_ADV_OutputCompareConf_Type * conf)
{
TIMx->CCMR3 = ( TIMx->CCMR3 & ~(0xFF) )
| ( (conf->EnableFastOutput) ? TIM_ADV_CCMR3_OC5FE_MASK : 0u )
| ( (conf->EnablePreLoadChannelValue) ? TIM_ADV_CCMR3_OC5PE_MASK : 0u )
| TIM_ADV_CCMR3_OC5M(conf->RefOutMode);
TIM_ADV_PutChannelValue(TIMx, TIM_ADV_CHN_5, conf->ChannelValue);
}
void TIM_ADV_EnableOutputCompare(TIM_ADV_Type * TIMx, uint32_t channel, TIM_ADV_OutputCompareConf_Type * conf)
{
if ( channel == TIM_ADV_CHN_5)
{
_TIM_ADV_EnableChannel5OutputCompare(TIMx, conf);
}
else
{
uint32_t regval = TIM_ADV_CCMR1_CC1S(TIM_ADV_ChannelIOMode_Out) /* output compare mode. */
| ( (conf->EnableFastOutput) ? TIM_ADV_CCMR1_OC1FE_MASK : 0u ) /* fast output. */
| ( (conf->EnablePreLoadChannelValue) ? TIM_ADV_CCMR1_OC1PE_MASK : 0u) /* preload of channel value. */
| TIM_ADV_CCMR1_OC1M(conf->RefOutMode) /* output compare comparison mode. */
| ( (conf->ClearRefOutOnExtTrigger) ? TIM_ADV_CCMR1_OC1CE_MASK : 0u) /* external trigger clear ref. */
;
_TIM_ADV_WriteChannelCtrlReg(TIMx, channel, regval);
TIM_ADV_PutChannelValue(TIMx, channel, conf->ChannelValue);
switch (conf->PinPolarity)
{
case TIM_ADV_PinPolarity_Disable:
TIMx->CCER &= ~( ( TIM_ADV_CCER_CC1E_MASK
| TIM_ADV_CCER_CC1NE_MASK
) << (channel<<2u) ); /* Disable both channel. */
break;
case TIM_ADV_PinPolarity_Rising:
TIMx->CCER = ( ( TIMx->CCER & ~(0xF << (channel<<2u)) )
| ( ( TIM_ADV_CCER_CC1E_MASK ) /* Enable the pin output / input. */
| ( ( conf->COMPPinPolarity == TIM_ADV_PinPolarity_Falling) ? TIM_ADV_CCER_CC1NP_MASK : 0u )
| ( ( conf->COMPPinPolarity != TIM_ADV_PinPolarity_Disable) ? TIM_ADV_CCER_CC1NE_MASK : 0u )
) << (channel<<2u));
break;
case TIM_ADV_PinPolarity_Falling:
TIMx->CCER = ( TIMx->CCER & ~(0xF << (channel<<2u)) )
| (( TIM_ADV_CCER_CC1E_MASK /* Enable the pin output / input. */
| TIM_ADV_CCER_CC1P_MASK /* Set output active polarity. */
| ( ( conf->COMPPinPolarity == TIM_ADV_PinPolarity_Falling) ? TIM_ADV_CCER_CC1NP_MASK : 0u )
| ( ( conf->COMPPinPolarity != TIM_ADV_PinPolarity_Disable) ? TIM_ADV_CCER_CC1NE_MASK : 0u )
) << (channel<<2u));
break;
default:
break;
}
}
}
void TIM_ADV_EnableOutputCompareSwitch(TIM_ADV_Type * TIMx, bool enable)
{
if (enable)
{
TIMx->BDTR |= TIM_ADV_BDTR_MOE_MASK;
}
else
{
TIMx->BDTR &= ~ TIM_ADV_BDTR_MOE_MASK;
}
}
void TIM_ADV_EnableInputCapture(TIM_ADV_Type * TIMx, uint32_t channel, TIM_ADV_InputCaptureConf_Type * conf)
{
uint32_t regval = TIM_ADV_CCMR1_CC1S(TIM_ADV_ChannelIOMode_In) /* input capture mode. */
| TIM_ADV_CCMR1_IC1PSC(conf->InDiv)
| TIM_ADV_CCMR1_IC1F(conf->InFilter)
;
_TIM_ADV_WriteChannelCtrlReg(TIMx, channel, regval);
switch (conf->PinPolarity)
{
case TIM_ADV_PinPolarity_Disable:
TIMx->CCER &= ~(TIM_ADV_CCER_CC1E_MASK << (channel<<2u));
break;
case TIM_ADV_PinPolarity_Rising:
TIMx->CCER = (TIMx->CCER & ~(0xF << (channel<<2u)) )
| (( TIM_ADV_CCER_CC1E_MASK /* Enable the pin output / input */
) << (channel<<2u) );
break;
case TIM_ADV_PinPolarity_Falling:
TIMx->CCER = ( TIMx->CCER & ~(0xF << (channel<<2u)) )
| (( TIM_ADV_CCER_CC1E_MASK /* Enable the pin output / input */
| TIM_ADV_CCER_CC1P_MASK /* Set active input edge. */
) << (channel<<2u) );
break;
case TIM_ADV_PinPolarity_RisingOrFalling:
TIMx->CCER = ( TIMx->CCER & ~(0xF << (channel<<2u)) )
| (( TIM_ADV_CCER_CC1E_MASK /* Enable the pin output / input */
| TIM_ADV_CCER_CC1P_MASK /* Set active input edge. */
| TIM_ADV_CCER_CC1NP_MASK
) << (channel<<2u) );
break;
default:
break;
}
}
uint16_t TIM_ADV_GetChannelValue(TIM_ADV_Type * TIMx, uint32_t channel)
{
return TIMx->CCR[channel];
}
void TIM_ADV_PutChannelValue(TIM_ADV_Type * TIMx, uint32_t channel, uint16_t value)
{
if ( channel == TIM_ADV_CHN_5 )
{
TIMx->CCR5 = value;
}
else
{
TIMx->CCR[channel] = value;
}
}
void TIM_ADV_EnableDeadArea(TIM_ADV_Type * TIMx, TIM_ADV_DeadAreaConf_Type * conf)
{
TIMx->CR1 = ( TIMx->CR1 &~ TIM_ADV_CR1_CKD_MASK )
| ( TIM_ADV_CR1_CKD(conf->StepFreqHz) ); /* set the frequncy ratio. */
TIMx->BDTR = ( TIMx->BDTR &~ TIM_ADV_BDTR_DTG_MASK )
| ( TIM_ADV_BDTR_DTG(conf->DeadAreaCoef) ); /* set the coefficient. */
}
void TIM_ADV_EnableMasterMode(TIM_ADV_Type * TIMx, TIM_ADV_MasterModeConf_Type * conf)
{
TIMx->CR2 = ( TIMx->CR2 &~ TIM_ADV_CR2_MMS_MASK )
| ( TIM_ADV_CR2_MMS(conf->Out) ); /* Set master mode output. */
uint32_t smcr = TIMx->SMCR &~ TIM_ADV_SMCR_MSM_MASK;
if (conf->EnableSync) /* synchronize with slave timers. */
{
smcr |= TIM_ADV_SMCR_MSM_MASK;
}
TIMx->SMCR = smcr;
}
void TIM_ADV_EnableSlaveMode(TIM_ADV_Type * TIMx, TIM_ADV_SlaveModeConf_Type * conf)
{
if ( conf->Resp != TIM_ADV_SlaveResp_Disable )
{
TIMx->SMCR = ( TIMx->SMCR &~ ( TIM_ADV_SMCR_TS_MASK
| TIM_ADV_SMCR_SMS_MASK
) )
| TIM_ADV_SMCR_TS(conf->In) /* set input trigger source. */
| TIM_ADV_SMCR_SMS(conf->Resp); /* set response to the source */
}
else
{
TIMx->SMCR &= ~ TIM_ADV_SMCR_SMS_MASK;
}
}
void TIM_ADV_EnableExtTriggerIn(TIM_ADV_Type * TIMx, TIM_ADV_ExtTriggerInConf_Type * conf)
{
uint32_t smcr = TIMx->SMCR &~ ( TIM_ADV_SMCR_ETPS_MASK
| TIM_ADV_SMCR_ETF_MASK
| TIM_ADV_SMCR_ECE_MASK
| TIM_ADV_SMCR_ETP_MASK
);
switch (conf->PinPolarity)
{
case TIM_ADV_PinPolarity_Disable:
break;
case TIM_ADV_PinPolarity_Rising:
smcr |= TIM_ADV_SMCR_ECE_MASK; /* enable external trigger input. */
break;
case TIM_ADV_PinPolarity_Falling:
smcr |= TIM_ADV_SMCR_ETP_MASK; /* falling edge active. */
smcr |= TIM_ADV_SMCR_ECE_MASK; /* enable external trigger input. */
break;
default:
break;
}
smcr |= TIM_ADV_SMCR_ETPS( conf->InDiv ); /* division to the input external trigger. */
smcr |= TIM_ADV_SMCR_ETF( conf->InFilter ); /* set filter. */
TIMx->SMCR = smcr;
}
uint32_t TIM_ADV_EnableDMABurst(TIM_ADV_Type * TIMx, TIM_ADV_DMABurstConf_Type * conf)
{
TIMx->DCR = TIM_ADV_DCR_DBA(conf->BaseAddr) | TIM_ADV_DCR_DBL(conf->Length);
return (uint32_t)(&(TIMx->DMAR));
}
TIM_ADV_EncoderDirection_Type TIM_ADV_GetEncoder(TIM_ADV_Type * TIMx, uint32_t * value)
{
if (value)
{
* value = TIM_ADV_GetCounterValue(TIMx);
}
if ( (TIMx->CR1 & TIM_ADV_CR1_DIR_MASK) != 0u )
{
return TIM_ADV_EncoderDirection_Backward;
}
else
{
return TIM_ADV_EncoderDirection_Forward;
}
}
void TIM_ADV_SetRepCounter(TIM_ADV_Type * TIMx, uint8_t value)
{
TIMx->RCR = TIM_ADV_RCR_REP(value);
}
uint8_t TIM_ADV_GetRepCounterValue(TIM_ADV_Type * TIMx)
{
return TIMx->RCR >> TIM_ADV_RCR_REPCNT_SHIFT;
}
void TIM_ADV_EnableIdleOut(TIM_ADV_Type * TIMx, uint32_t channel, TIM_ADV_IdleOut_Type * conf)
{
uint32_t cr2 = TIMx->CR2 & ~ ( ( TIM_ADV_CR2_OIS1_MASK
| TIM_ADV_CR2_OIS1N_MASK
) << ( channel << 1u )
);
if ( conf->PinPolarity == TIM_ADV_PinPolarity_Rising )
{
cr2 |= ( TIM_ADV_CR2_OIS1_MASK << ( channel << 1u ) );
}
if ( conf->COMPPinPolarity == TIM_ADV_PinPolarity_Rising )
{
cr2 |= ( TIM_ADV_CR2_OIS1N_MASK << ( channel << 1u ) );
}
TIMx->CR2 = cr2;
}
void TIM_ADV_EnableLock(TIM_ADV_Type * TIMx, TIM_ADV_LockLevel_Type lock)
{
TIMx->BDTR = ( TIMx->BDTR & ~ TIM_ADV_BDTR_LOCK_MASK )
| TIM_ADV_BDTR_LOCK(lock);
}
void TIM_ADV_EnableBreakIn(TIM_ADV_Type * TIMx, TIM_ADV_BreakIn_Type * conf)
{
uint32_t bdtr = TIMx->BDTR &~ ( TIM_ADV_BDTR_BKE_MASK
| TIM_ADV_BDTR_BKP_MASK
| TIM_ADV_BDTR_AOE_MASK
| TIM_ADV_BDTR_DOE_MASK
);
switch (conf->PinPolarity)
{
case TIM_ADV_PinPolarity_Disable:
break;
case TIM_ADV_PinPolarity_Rising:
bdtr |= ( TIM_ADV_BDTR_BKE_MASK
| TIM_ADV_BDTR_BKP_MASK
| ( conf->AutoSwitchOutput ? TIM_ADV_BDTR_AOE_MASK : 0u )
| ( conf->DirectIdleOutput ? TIM_ADV_BDTR_DOE_MASK : 0u )
);
break;
case TIM_ADV_PinPolarity_Falling:
bdtr |= ( TIM_ADV_BDTR_BKE_MASK
| ( conf->AutoSwitchOutput ? TIM_ADV_BDTR_AOE_MASK : 0u )
| ( conf->DirectIdleOutput ? TIM_ADV_BDTR_DOE_MASK : 0u )
);
break;
default:
break;
}
}
void TIM_ADV_EnablePWMShift(TIM_ADV_Type * TIMx, uint32_t channel, uint16_t value)
{
if ( value == TIM_ADV_GetChannelValue(TIMx, channel) )
{
TIMx->PDER &= ~( TIM_ADV_PDER_CCR1SHIFTEN_MASK << channel );
}
else
{
TIMx->PDER |= ( TIM_ADV_PDER_CCR1SHIFTEN_MASK << channel );
TIMx->CCRFALL[channel] = value;
}
}
/* EOF. */

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bsp/mm32/libraries/MM32F3270_HAL/MM32F3270_HAL_Driver/Src/hal_tim_basic.c Normal file
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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "hal_tim_basic.h"
bool TIM_BASIC_Init(TIM_BASIC_Type * TIMx, TIM_BASIC_Init_Type * init)
{
TIMx->CR1 = (TIMx->CR1 & ~(TIM_BASIC_CR1_OPM_MASK | TIM_BASIC_CR1_APRE_MASK) )
| TIM_BASIC_CR1_OPM(init->PeriodMode)
| ((init->EnablePreloadPeriod) ? TIM_BASIC_CR1_APRE_MASK: 0u)
;
/* Check StepFreqHz validity. */
if ( (init->StepFreqHz == 0u) || (init->StepFreqHz > init->ClockFreqHz) )
{
return false;
}
/* Calculate prescaler of the timer.*/
TIMx->PSC = init->ClockFreqHz / init->StepFreqHz - 1u;
/* Set the period length. */
TIMx->ARR = init->Period;
return true;
}
void TIM_BASIC_Start(TIM_BASIC_Type * TIMx)
{
TIMx->CR1 |= TIM_BASIC_CR1_CEN_MASK;
}
void TIM_BASIC_Stop(TIM_BASIC_Type * TIMx)
{
TIMx->CR1 &= ~TIM_BASIC_CR1_CEN_MASK;
}
uint32_t TIM_BASIC_GetCounterValue(TIM_BASIC_Type * TIMx)
{
return TIMx->CNT;
}
void TIM_BASIC_EnableInterrupts(TIM_BASIC_Type *TIMx, uint32_t interrupts, bool enable)
{
if (enable)
{
TIMx->DIER |= interrupts;
}
else
{
TIMx->DIER &= ~interrupts;
}
}
void TIM_BASIC_EnableDMA(TIM_BASIC_Type *TIMx, uint32_t dmas, bool enable)
{
if (enable)
{
TIMx->DIER |= dmas;
}
else
{
TIMx->DIER &= ~dmas;
}
}
void TIM_BASIC_DoSwTrigger(TIM_BASIC_Type *TIMx, uint32_t swtrgs)
{
TIMx->EGR = swtrgs;
}
uint32_t TIM_BASIC_GetInterruptStatus(TIM_BASIC_Type * TIMx)
{
return TIMx->SR;
}
void TIM_BASIC_ClearInterruptStatus(TIM_BASIC_Type *TIMx, uint32_t status)
{
TIMx->SR &= ~status;
}
/* EOF. */

130
bsp/mm32/libraries/MM32F3270_HAL/MM32F3270_HAL_Driver/Src/hal_uart.c Normal file
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/*
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "hal_uart.h"
void UART_Init(UART_Type * UARTx, UART_Init_Type * init)
{
uint32_t ccr = UARTx->CCR & ~( UART_CCR_PEN_MASK
| UART_CCR_PSEL_MASK
| UART_CCR_SPB0_MASK
| UART_CCR_CHAR_MASK
| UART_CCR_SPB1_MASK
);
/* WordLength. */
ccr |= UART_CCR_CHAR(init->WordLength);
/* StopBits. */
if ( (init->StopBits == UART_StopBits_2) || (init->StopBits == UART_StopBits_1_5) )
{
ccr |= UART_CCR_SPB0_MASK;
}
if ( (init->StopBits == UART_StopBits_0_5) || (init->StopBits == UART_StopBits_1_5) )
{
ccr |= UART_CCR_SPB1_MASK;
}
/* Parity. */
if (init->Parity == UART_Parity_Even)
{
ccr |= UART_CCR_PEN_MASK;
}
if (init->Parity == UART_Parity_Odd)
{
ccr |= UART_CCR_PEN_MASK | UART_CCR_PSEL_MASK;
}
UARTx->CCR = ccr;
/* XferMode. */
uint32_t gcr = UARTx->GCR & ~( UART_GCR_RXEN_MASK
| UART_GCR_TXEN_MASK
| UART_GCR_AUTOFLOWEN_MASK
);
gcr |= ((uint32_t)(init->XferMode) << UART_GCR_RXEN_SHIFT);
if (init->HwFlowControl == UART_HwFlowControl_RTS_CTS)
{
gcr |= UART_GCR_AUTOFLOWEN_MASK;
}
UARTx->GCR = gcr;
/* Setup the baudrate. */
UARTx->BRR = (init->ClockFreqHz / init->BaudRate) / 16u;
UARTx->FRA = (init->ClockFreqHz / init->BaudRate) % 16u;
}
void UART_Enable(UART_Type * UARTx, bool enable)
{
if (enable)
{
UARTx->GCR |= UART_GCR_UARTEN_MASK;
}
else
{
UARTx->GCR &= ~UART_GCR_UARTEN_MASK;
}
}
void UART_EnableInterrupts(UART_Type * UARTx, uint32_t interrupts, bool enable)
{
(enable) ? (UARTx->IER |= interrupts) : (UARTx->IER &= ~interrupts);
}
uint32_t UART_GetEnabledInterrupts(UART_Type * UARTx)
{
return UARTx->IER;
}
void UART_EnableDMA(UART_Type * UARTx, bool enable)
{
if (enable)
{
UARTx->GCR |= UART_GCR_DMAMODE_MASK;
}
else
{
UARTx->GCR &= ~UART_GCR_DMAMODE_MASK;
}
}
void UART_PutData(UART_Type * UARTx, uint8_t value)
{
UARTx->TDR = value;
}
uint8_t UART_GetData(UART_Type * UARTx)
{
return (uint8_t)(UARTx->RDR & 0xFFU);
}
/* return flags */
uint32_t UART_GetStatus(UART_Type * UARTx)
{
return UARTx->CSR;
}
/* return flags. */
uint32_t UART_GetInterruptStatus(UART_Type * UARTx)
{
return UARTx->ISR;
}
void UART_ClearInterruptStatus(UART_Type * UARTx, uint32_t interrupts)
{
UARTx->ICR = interrupts;
}
uint32_t UART_GetRxDataRegAddr(UART_Type * UARTx)
{
return (uint32_t)(&(UARTx->RDR));
}
uint32_t UART_GetTxDataRegAddr(UART_Type * UARTx)
{
return (uint32_t)(&(UARTx->TDR));
}
/* EOF. */

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