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[libcpu][renesas]add cortex-m85 && ek-ra8m1 adapt

This commit is contained in:
Rbb666 2023-10-17 17:20:54 +08:00 committed by guo
parent 7066761510
commit 7ace7d0a78
162 changed files with 113163 additions and 110 deletions
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1
.github/workflows/action.yml vendored
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@ -197,6 +197,7 @@ jobs:
- "renesas/ra6m3-hmi-board"
- "renesas/ra4m2-eco"
- "renesas/ra2l1-cpk"
- "renesas/ra8m1-ek"
- RTT_BSP: "gd32_n32_apm32"
RTT_TOOL_CHAIN: "sourcery-arm"
SUB_RTT_BSP:

2
bsp/renesas/README.md
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@ -15,6 +15,8 @@ RA 系列 BSP 目前支持情况如下表所示：
| [ra4m2-eco](ra4m2-eco) | Renesas 官方 RA-Eco-RA4M2 开发板 |
| **RA2 系列** | |
| [ra2l1-cpk](ra2l1-cpk) | Renesas 官方 CPK-RA2L1 开发板 |
| **RA8 系列** | |
| [ra8m1-ek](ra8m1-ek) | Renesas 官方 EK-RA8M1 开发板 |
可以通过阅读相应 BSP 下的 README 来快速上手，如果想要使用 BSP 更多功能可参考 docs 文件夹下提供的说明文档，如下表所示：

5
bsp/renesas/libraries/HAL_Drivers/config/drv_config.h
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@ -124,6 +124,11 @@ extern "C"
#endif
#endif /* SOC_SERIES_R7FA4M2 */
#ifdef SOC_SERIES_R7FA8M85
#include "ra8/uart_config.h"
#endif /* SOC_SERIES_R7FA8M85 */
#ifdef __cplusplus
}
#endif

136
bsp/renesas/libraries/HAL_Drivers/config/ra8/uart_config.h Normal file
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@ -0,0 +1,136 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-07-29 KyleChan first version
*/
#ifndef __UART_CONFIG_H__
#define __UART_CONFIG_H__
#include <rtthread.h>
#include "hal_data.h"
#ifdef __cplusplus
extern "C" {
#endif
#if defined(BSP_USING_UART0)
#ifndef UART0_CONFIG
#define UART0_CONFIG \
{ \
.name = "uart0", \
.p_api_ctrl = &g_uart0_ctrl, \
.p_cfg = &g_uart0_cfg, \
}
#endif /* UART0_CONFIG */
#endif /* BSP_USING_UART0 */
#if defined(BSP_USING_UART1)
#ifndef UART1_CONFIG
#define UART1_CONFIG \
{ \
.name = "uart1", \
.p_api_ctrl = &g_uart1_ctrl, \
.p_cfg = &g_uart1_cfg, \
}
#endif /* UART1_CONFIG */
#endif /* BSP_USING_UART1 */
#if defined(BSP_USING_UART2)
#ifndef UART2_CONFIG
#define UART2_CONFIG \
{ \
.name = "uart2", \
.p_api_ctrl = &g_uart2_ctrl, \
.p_cfg = &g_uart2_cfg, \
}
#endif /* UART2_CONFIG */
#endif /* BSP_USING_UART2 */
#if defined(BSP_USING_UART3)
#ifndef UART3_CONFIG
#define UART3_CONFIG \
{ \
.name = "uart3", \
.p_api_ctrl = &g_uart3_ctrl, \
.p_cfg = &g_uart3_cfg, \
}
#endif /* UART3_CONFIG */
#endif /* BSP_USING_UART3 */
#if defined(BSP_USING_UART4)
#ifndef UART4_CONFIG
#define UART4_CONFIG \
{ \
.name = "uart4", \
.p_api_ctrl = &g_uart4_ctrl, \
.p_cfg = &g_uart4_cfg, \
}
#endif /* UART4_CONFIG */
#endif /* BSP_USING_UART4 */
#if defined(BSP_USING_UART5)
#ifndef UART5_CONFIG
#define UART5_CONFIG \
{ \
.name = "uart5", \
.p_api_ctrl = &g_uart5_ctrl, \
.p_cfg = &g_uart5_cfg, \
}
#endif /* UART5_CONFIG */
#endif /* BSP_USING_UART5 */
#if defined(BSP_USING_UART6)
#ifndef UART6_CONFIG
#define UART6_CONFIG \
{ \
.name = "uart6", \
.p_api_ctrl = &g_uart6_ctrl, \
.p_cfg = &g_uart6_cfg, \
}
#endif /* UART6_CONFIG */
#endif /* BSP_USING_UART6 */
#if defined(BSP_USING_UART7)
#ifndef UART7_CONFIG
#define UART7_CONFIG \
{ \
.name = "uart7", \
.p_api_ctrl = &g_uart7_ctrl, \
.p_cfg = &g_uart7_cfg, \
}
#endif /* UART7_CONFIG */
#endif /* BSP_USING_UART7 */
#if defined(BSP_USING_UART8)
#ifndef UART8_CONFIG
#define UART8_CONFIG \
{ \
.name = "uart8", \
.p_api_ctrl = &g_uart8_ctrl, \
.p_cfg = &g_uart8_cfg, \
}
#endif /* UART8_CONFIG */
#endif /* BSP_USING_UART8 */
#if defined(BSP_USING_UART9)
#ifndef UART9_CONFIG
#define UART9_CONFIG \
{ \
.name = "uart9", \
.p_api_ctrl = &g_uart9_ctrl, \
.p_cfg = &g_uart9_cfg, \
}
#endif /* UART9_CONFIG */
#endif /* BSP_USING_UART9 */
#ifdef __cplusplus
}
#endif
#endif

1
bsp/renesas/libraries/HAL_Drivers/drv_common.c
View File

@ -111,7 +111,6 @@ void rt_hw_us_delay(rt_uint32_t us)
*/
rt_weak void rt_hw_board_init()
{
rt_hw_systick_init();
/* Heap initialization */

237
bsp/renesas/libraries/HAL_Drivers/drv_sci.c
View File

@ -65,39 +65,50 @@ struct ra_sci_param
const void *ops;
};
rt_weak const struct rt_i2c_bus_device_ops sci_ops_i2c;
rt_weak const struct rt_spi_ops sci_ops_spi;
rt_weak const struct rt_uart_ops sci_ops_uart;
#ifdef RT_USING_I2C
rt_weak const struct rt_i2c_bus_device_ops sci_ops_i2c;
#endif
#ifdef RT_USING_SPI
rt_weak const struct rt_spi_ops sci_ops_spi;
#endif
#ifdef RT_USING_UART
rt_weak const struct rt_uart_ops sci_ops_uart;
#endif
struct ra_sci_object
{
union
{
#ifdef RT_USING_SPI
struct
{
struct rt_spi_bus sbus;
struct rt_spi_configuration *spi_cfg;
};
#endif
#ifdef RT_USING_I2C
struct
{
struct rt_i2c_bus_device ibus;
};
#endif
#ifdef RT_USING_UART
struct
{
struct rt_serial_device ubus;
};
#endif
};
const struct ra_sci_param *param;
struct rt_event event;
};
#ifndef BIT
#define BIT(idx) (1ul << (idx))
#define BIT(idx) (1ul << (idx))
#endif
#ifndef BITS
#define BITS(b,e) ((((uint32_t)-1)<<(b))&(((uint32_t)-1)>>(31-(e))))
#define BITS(b,e) ((((uint32_t)-1)<<(b))&(((uint32_t)-1)>>(31-(e))))
#endif
#define _TO_STR(_a) #_a
@ -218,11 +229,11 @@ static struct ra_sci_object sci_obj[RA_SCI_INDEX_MAX] = {0};
rt_used static rt_err_t ra_wait_complete(struct ra_sci_object *obj)
{
rt_uint32_t event = 0;
if(RT_EOK != rt_event_recv(&obj->event, RA_SCI_EVENT_ALL, RT_EVENT_FLAG_OR|RT_EVENT_FLAG_CLEAR, (rt_int32_t)rt_tick_from_millisecond(400), &event))
if (RT_EOK != rt_event_recv(&obj->event, RA_SCI_EVENT_ALL, RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, (rt_int32_t)rt_tick_from_millisecond(400), &event))
{
return -RT_ETIMEOUT;
}
if((event & (RA_SCI_EVENT_ABORTED|RA_SCI_EVENT_ERROR)) == 0)
if ((event & (RA_SCI_EVENT_ABORTED | RA_SCI_EVENT_ERROR)) == 0)
{
return RT_EOK;
}
@ -238,42 +249,42 @@ rt_used static rt_err_t ra_wait_complete(struct ra_sci_object *obj)
const static int uart_buff_size[][2] =
{
#ifdef BSP_USING_SCI0_UART
{BSP_SCI0_UART_RX_BUFSIZE,BSP_SCI0_UART_TX_BUFSIZE},
{BSP_SCI0_UART_RX_BUFSIZE, BSP_SCI0_UART_TX_BUFSIZE},
#endif
#ifdef BSP_USING_SCI1_UART
{BSP_SCI1_UART_RX_BUFSIZE,BSP_SCI1_UART_TX_BUFSIZE},
{BSP_SCI1_UART_RX_BUFSIZE, BSP_SCI1_UART_TX_BUFSIZE},
#endif
#ifdef BSP_USING_SCI2_UART
{BSP_SCI2_UART_RX_BUFSIZE,BSP_SCI2_UART_TX_BUFSIZE},
{BSP_SCI2_UART_RX_BUFSIZE, BSP_SCI2_UART_TX_BUFSIZE},
#endif
#ifdef BSP_USING_SCI3_UART
{BSP_SCI3_UART_RX_BUFSIZE,BSP_SCI3_UART_TX_BUFSIZE},
{BSP_SCI3_UART_RX_BUFSIZE, BSP_SCI3_UART_TX_BUFSIZE},
#endif
#ifdef BSP_USING_SCI4_UART
{BSP_SCI4_UART_RX_BUFSIZE,BSP_SCI4_UART_TX_BUFSIZE},
{BSP_SCI4_UART_RX_BUFSIZE, BSP_SCI4_UART_TX_BUFSIZE},
#endif
#ifdef BSP_USING_SCI5_UART
{BSP_SCI5_UART_RX_BUFSIZE,BSP_SCI5_UART_TX_BUFSIZE},
{BSP_SCI5_UART_RX_BUFSIZE, BSP_SCI5_UART_TX_BUFSIZE},
#endif
#ifdef BSP_USING_SCI6_UART
{BSP_SCI6_UART_RX_BUFSIZE,BSP_SCI6_UART_TX_BUFSIZE},
{BSP_SCI6_UART_RX_BUFSIZE, BSP_SCI6_UART_TX_BUFSIZE},
#endif
#ifdef BSP_USING_SCI7_UART
{BSP_SCI7_UART_RX_BUFSIZE,BSP_SCI7_UART_TX_BUFSIZE},
{BSP_SCI7_UART_RX_BUFSIZE, BSP_SCI7_UART_TX_BUFSIZE},
#endif
#ifdef BSP_USING_SCI8_UART
{BSP_SCI8_UART_RX_BUFSIZE,BSP_SCI8_UART_TX_BUFSIZE},
{BSP_SCI8_UART_RX_BUFSIZE, BSP_SCI8_UART_TX_BUFSIZE},
#endif
#ifdef BSP_USING_SCI9_UART
{BSP_SCI9_UART_RX_BUFSIZE,BSP_SCI9_UART_TX_BUFSIZE},
{BSP_SCI9_UART_RX_BUFSIZE, BSP_SCI9_UART_TX_BUFSIZE},
#endif
{0,0},
{0, 0},
};
void sci_uart_irq_callback(uart_callback_args_t *p_args)
{
rt_interrupt_enter();
if(NULL != p_args)
if (NULL != p_args)
{
struct ra_sci_object *obj = (struct ra_sci_object *)p_args->p_context;
RT_ASSERT(obj != RT_NULL);
@ -306,13 +317,13 @@ static rt_err_t ra_uart_configure(struct rt_serial_device *serial, struct serial
param = obj->param;
RT_ASSERT(param != RT_NULL);
err = R_SCI_UART_Open((uart_ctrl_t * const)param->sci_ctrl, (uart_cfg_t * const)param->sci_cfg);
err = R_SCI_UART_Open((uart_ctrl_t *const)param->sci_ctrl, (uart_cfg_t *const)param->sci_cfg);
if (FSP_SUCCESS != err)
{
return -RT_ERROR;
}
err = R_SCI_UART_CallbackSet((uart_ctrl_t * const)param->sci_ctrl, sci_uart_irq_callback, obj, NULL);
err = R_SCI_UART_CallbackSet((uart_ctrl_t *const)param->sci_ctrl, sci_uart_irq_callback, obj, NULL);
if (FSP_SUCCESS != err)
{
//LOG_W("R_SCI_UART_CallbackSet API failed,%d", err);
@ -350,9 +361,9 @@ static int ra_uart_getc(struct rt_serial_device *serial)
}
static rt_ssize_t ra_uart_transmit(struct rt_serial_device *serial,
rt_uint8_t *buf,
rt_size_t size,
rt_uint32_t tx_flag)
rt_uint8_t *buf,
rt_size_t size,
rt_uint32_t tx_flag)
{
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(buf != RT_NULL);
@ -392,15 +403,15 @@ void sci_i2c_irq_callback(i2c_master_callback_args_t *p_args)
struct ra_sci_object *obj = (struct ra_sci_object *)p_args->p_context;
uint32_t event = 0;
RT_ASSERT(obj != RT_NULL);
switch(p_args->event)
switch (p_args->event)
{
case I2C_MASTER_EVENT_ABORTED:
case I2C_MASTER_EVENT_ABORTED:
event |= RA_SCI_EVENT_ABORTED;
break;
case I2C_MASTER_EVENT_RX_COMPLETE:
case I2C_MASTER_EVENT_RX_COMPLETE:
event |= RA_SCI_EVENT_RX_COMPLETE;
break;
case I2C_MASTER_EVENT_TX_COMPLETE:
case I2C_MASTER_EVENT_TX_COMPLETE:
event |= RA_SCI_EVENT_TX_COMPLETE;
break;
}
@ -412,8 +423,8 @@ void sci_i2c_irq_callback(i2c_master_callback_args_t *p_args)
}
static rt_ssize_t ra_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
struct rt_i2c_msg msgs[],
rt_uint32_t num)
struct rt_i2c_msg msgs[],
rt_uint32_t num)
{
rt_size_t i;
RT_ASSERT(bus != RT_NULL);
@ -438,27 +449,43 @@ static rt_ssize_t ra_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
{
//LOG_E("10Bit not support");
//break;
#ifdef SOC_SERIES_R7FA8M85
R_SCI_B_I2C_SlaveAddressSet(master_ctrl, msg->addr, I2C_MASTER_ADDR_MODE_10BIT);
#else
R_SCI_I2C_SlaveAddressSet(master_ctrl, msg->addr, I2C_MASTER_ADDR_MODE_10BIT);
#endif
}
else
{
//master_ctrl->slave = msg->addr;
#ifdef SOC_SERIES_R7FA8M85
R_SCI_B_I2C_SlaveAddressSet(master_ctrl, msg->addr, I2C_MASTER_ADDR_MODE_7BIT);
#else
R_SCI_I2C_SlaveAddressSet(master_ctrl, msg->addr, I2C_MASTER_ADDR_MODE_7BIT);
#endif
}
if (msg->flags & RT_I2C_RD)
{
#ifdef SOC_SERIES_R7FA8M85
err = R_SCI_B_I2C_Read(master_ctrl, msg->buf, msg->len, restart);
#else
err = R_SCI_I2C_Read(master_ctrl, msg->buf, msg->len, restart);
#endif
}
else
{
#ifdef SOC_SERIES_R7FA8M85
err = R_SCI_B_I2C_Write(master_ctrl, msg->buf, msg->len, restart);
#else
err = R_SCI_I2C_Write(master_ctrl, msg->buf, msg->len, restart);
#endif
}
if (FSP_SUCCESS == err)
{
/* handle error */
err = ra_wait_complete(obj);
if(RT_EOK != err)
if (RT_EOK != err)
{
//LOG_E("POWER_CTL reg I2C write failed,%d,%d", err, i);
break;
@ -481,10 +508,6 @@ const struct rt_i2c_bus_device_ops sci_ops_i2c =
.slave_xfer = RT_NULL,
.i2c_bus_control = RT_NULL
};
#else
void sci_i2c_irq_callback(i2c_master_callback_args_t *p_args)
{
}
#endif
/**
* @}
@ -504,20 +527,20 @@ void sci_spi_irq_callback(spi_callback_args_t *p_args)
/* capture callback event for validating the i2c transfer event*/
struct ra_sci_object *obj = (struct ra_sci_object *)p_args->p_context;
uint32_t event = 0;
switch(p_args->event)
switch (p_args->event)
{
case SPI_EVENT_ERR_MODE_FAULT :
case SPI_EVENT_ERR_READ_OVERFLOW:
case SPI_EVENT_ERR_PARITY :
case SPI_EVENT_ERR_OVERRUN :
case SPI_EVENT_ERR_FRAMING :
case SPI_EVENT_ERR_MODE_UNDERRUN:
case SPI_EVENT_ERR_MODE_FAULT :
case SPI_EVENT_ERR_READ_OVERFLOW:
case SPI_EVENT_ERR_PARITY :
case SPI_EVENT_ERR_OVERRUN :
case SPI_EVENT_ERR_FRAMING :
case SPI_EVENT_ERR_MODE_UNDERRUN:
event |= RA_SCI_EVENT_ERROR;
break;
case SPI_EVENT_TRANSFER_ABORTED :
case SPI_EVENT_TRANSFER_ABORTED :
event |= RA_SCI_EVENT_ABORTED;
break;
case SPI_EVENT_TRANSFER_COMPLETE:
case SPI_EVENT_TRANSFER_COMPLETE:
event |= RA_SCI_EVENT_TX_COMPLETE;
break;
}
@ -531,11 +554,11 @@ void sci_spi_irq_callback(spi_callback_args_t *p_args)
static spi_bit_width_t ra_width_shift(rt_uint8_t data_width)
{
spi_bit_width_t bit_width = SPI_BIT_WIDTH_8_BITS;
if(data_width == 1)
if (data_width == 1)
bit_width = SPI_BIT_WIDTH_8_BITS;
else if(data_width == 2)
else if (data_width == 2)
bit_width = SPI_BIT_WIDTH_16_BITS;
else if(data_width == 4)
else if (data_width == 4)
bit_width = SPI_BIT_WIDTH_32_BITS;
return bit_width;
@ -636,7 +659,8 @@ static rt_err_t ra_hw_spi_configure(struct rt_spi_device *device,
/**< init */
err = R_SCI_SPI_Open((spi_ctrl_t *)param->sci_ctrl, cfg);
/* handle error */
if(err == FSP_ERR_IN_USE) {
if (err == FSP_ERR_IN_USE)
{
R_SCI_SPI_Close((spi_ctrl_t *)param->sci_ctrl);
err = R_SCI_SPI_Open((spi_ctrl_t *)param->sci_ctrl, cfg);
}
@ -703,10 +727,6 @@ const struct rt_spi_ops sci_ops_spi =
.configure = ra_hw_spi_configure,
.xfer = ra_spixfer,
};
#else
void sci_spi_irq_callback(spi_callback_args_t *p_args)
{
}
#endif
/**
* @}
@ -714,15 +734,14 @@ void sci_spi_irq_callback(spi_callback_args_t *p_args)
static int ra_hw_sci_init(void)
{
int bufsz_idx = 0;
for (rt_uint8_t idx = 0; idx < RA_SCI_INDEX_MAX; idx++)
{
struct ra_sci_object *obj = &sci_obj[idx];
const struct ra_sci_param *param = &sci_param[idx];
obj->param = param;
rt_err_t err;
#ifdef BSP_USING_SCIn_SPI
if((uint32_t)param->ops == (uint32_t)&sci_ops_spi)
#ifdef BSP_USING_SCIn_SPI
if ((uint32_t)param->ops == (uint32_t)&sci_ops_spi)
{
/**< register spi bus */
err = rt_spi_bus_register(&obj->sbus, param->bus_name, param->ops);
@ -733,56 +752,64 @@ static int ra_hw_sci_init(void)
}
}
else
#endif
#ifdef BSP_USING_SCIn_I2C
if((uint32_t)param->ops == (uint32_t)&sci_ops_i2c)
{
obj->ibus.ops = param->ops;
obj->ibus.priv = 0;
/* opening IIC master module */
err = R_SCI_I2C_Open((i2c_master_ctrl_t *)param->sci_ctrl, param->sci_cfg);
if(err != FSP_SUCCESS)
#endif
#ifdef BSP_USING_SCIn_I2C
if ((uint32_t)param->ops == (uint32_t)&sci_ops_i2c)
{
LOG_E("R_IIC_MASTER_Open API failed,%d", err);
continue;
}
err = R_SCI_I2C_CallbackSet((i2c_master_ctrl_t *)param->sci_ctrl, sci_i2c_irq_callback, obj, NULL);
/* handle error */
if (FSP_SUCCESS != err)
{
LOG_E("R_SCI_I2C_CallbackSet API failed,%d", err);
continue;
}
obj->ibus.ops = param->ops;
obj->ibus.priv = 0;
/* opening IIC master module */
#ifdef SOC_SERIES_R7FA8M85
err = R_SCI_B_I2C_Open((i2c_master_ctrl_t *)param->sci_ctrl, param->sci_cfg);
#else
err = R_SCI_I2C_Open((i2c_master_ctrl_t *)param->sci_ctrl, param->sci_cfg);
#endif
if (err != FSP_SUCCESS)
{
LOG_E("R_IIC_MASTER_Open API failed,%d", err);
continue;
}
#ifdef SOC_SERIES_R7FA8M85
err = R_SCI_B_I2C_CallbackSet((i2c_master_ctrl_t *)param->sci_ctrl, sci_i2c_irq_callback, obj, NULL);
#else
err = R_SCI_I2C_CallbackSet((i2c_master_ctrl_t *)param->sci_ctrl, sci_i2c_irq_callback, obj, NULL);
#endif
/* handle error */
if (FSP_SUCCESS != err)
{
LOG_E("R_SCI_I2C_CallbackSet API failed,%d", err);
continue;
}
err = rt_i2c_bus_device_register(&obj->ibus, param->bus_name);
if (RT_EOK != err)
{
LOG_E("i2c bus %s register failed,%d", param->bus_name, err);
continue;
err = rt_i2c_bus_device_register(&obj->ibus, param->bus_name);
if (RT_EOK != err)
{
LOG_E("i2c bus %s register failed,%d", param->bus_name, err);
continue;
}
}
}
else
#endif
#ifdef BSP_USING_SCIn_UART
if((uint32_t)param->ops == (uint32_t)&sci_ops_uart)
{
if(rt_device_find(param->bus_name) != RT_NULL)
{
continue;
}
struct rt_serial_device *serial = &obj->ubus;
obj->ubus.ops = param->ops;
serial->config.rx_bufsz = uart_buff_size[bufsz_idx][0];
serial->config.tx_bufsz = uart_buff_size[bufsz_idx][1];
bufsz_idx ++;
err = rt_hw_serial_register(serial, param->bus_name, RT_DEVICE_FLAG_RDWR, RT_NULL);
if (RT_EOK != err)
{
LOG_E("uart %s register failed,%d", param->bus_name, err);
continue;
}
}
#endif
else
#endif
#ifdef BSP_USING_SCIn_UART
if ((uint32_t)param->ops == (uint32_t)&sci_ops_uart)
{
if (rt_device_find(param->bus_name) != RT_NULL)
{
continue;
}
struct rt_serial_device *serial = &obj->ubus;
obj->ubus.ops = param->ops;
serial->config.rx_bufsz = uart_buff_size[bufsz_idx][0];
serial->config.tx_bufsz = uart_buff_size[bufsz_idx][1];
bufsz_idx ++;
err = rt_hw_serial_register(serial, param->bus_name, RT_DEVICE_FLAG_RDWR, RT_NULL);
if (RT_EOK != err)
{
LOG_E("uart %s register failed,%d", param->bus_name, err);
continue;
}
}
#endif
{
}
if (RT_EOK != rt_event_init(&obj->event, param->bus_name, RT_IPC_FLAG_PRIO))
@ -806,9 +833,9 @@ rt_weak int rt_hw_usart_init(void)
const struct ra_sci_param *param = &sci_param[idx];
obj->param = param;
rt_err_t err;
if((uint32_t)param->ops == (uint32_t)&sci_ops_uart)
if ((uint32_t)param->ops == (uint32_t)&sci_ops_uart)
{
if(rt_device_find(param->bus_name) != RT_NULL)
if (rt_device_find(param->bus_name) != RT_NULL)
{
continue;
}

23
bsp/renesas/libraries/HAL_Drivers/drv_usart_v2.c
View File

@ -1,11 +1,12 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-07-29 KyleChan first version
* 2023-10-17 Rbb666 add ra8 adapt
*/
#include <drv_usart_v2.h>
@ -209,7 +210,11 @@ static rt_err_t ra_uart_configure(struct rt_serial_device *serial, struct serial
uart = rt_container_of(serial, struct ra_uart, serial);
RT_ASSERT(uart != RT_NULL);
#ifdef SOC_SERIES_R7FA8M85
err = R_SCI_B_UART_Open(uart->config->p_api_ctrl, uart->config->p_cfg);
#else
err = R_SCI_UART_Open(uart->config->p_api_ctrl, uart->config->p_cfg);
#endif
if (FSP_SUCCESS != err)
{
return -RT_ERROR;
@ -231,10 +236,19 @@ static int ra_uart_putc(struct rt_serial_device *serial, char c)
uart = rt_container_of(serial, struct ra_uart, serial);
RT_ASSERT(uart != RT_NULL);
#ifdef SOC_SERIES_R7FA8M85
sci_b_uart_instance_ctrl_t *p_ctrl = (sci_b_uart_instance_ctrl_t *)uart->config->p_api_ctrl;
#else
sci_uart_instance_ctrl_t *p_ctrl = (sci_uart_instance_ctrl_t *)uart->config->p_api_ctrl;
#endif
p_ctrl->p_reg->TDR = c;
#ifdef SOC_SERIES_R7FA8M85
while ((p_ctrl->p_reg->CSR_b.TEND) == 0);
#else
while ((p_ctrl->p_reg->SSR_b.TEND) == 0);
#endif
return RT_EOK;
}
@ -245,15 +259,16 @@ static int ra_uart_getc(struct rt_serial_device *serial)
}
static rt_ssize_t ra_uart_transmit(struct rt_serial_device *serial,
rt_uint8_t *buf,
rt_size_t size,
rt_uint32_t tx_flag)
rt_uint8_t *buf,
rt_size_t size,
rt_uint32_t tx_flag)
{
struct ra_uart *uart;
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(buf != RT_NULL);
uart = rt_container_of(serial, struct ra_uart, serial);
RT_ASSERT(uart != RT_NULL);
ra_uart_control(serial, RT_DEVICE_CTRL_SET_INT, (void *)tx_flag);

6
bsp/renesas/libraries/Kconfig
View File

@ -32,3 +32,9 @@ config SOC_SERIES_R7FA4M2
select ARCH_ARM_CORTEX_M4
select SOC_FAMILY_RENESAS
default n
config SOC_SERIES_R7FA8M85
bool
select ARCH_ARM_CORTEX_M85
select SOC_FAMILY_RENESAS
default n

1051
bsp/renesas/ra8m1-ek/.config Normal file
View File

File diff suppressed because it is too large Load Diff

222
bsp/renesas/ra8m1-ek/.cproject Normal file
View File

@ -0,0 +1,222 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings">
<cconfiguration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.553091094">
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.553091094" moduleId="org.eclipse.cdt.core.settings" name="Debug">
<externalSettings/>
<extensions>
<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
</extensions>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration artifactExtension="elf" artifactName="rtthread" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="${cross_rm} -rf" description="" id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.553091094" name="Debug" parent="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug">
<folderInfo id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.553091094." name="/" resourcePath="">
<toolChain id="ilg.gnuarmeclipse.managedbuild.cross.toolchain.elf.debug.1201710416" name="ARM Cross GCC" superClass="ilg.gnuarmeclipse.managedbuild.cross.toolchain.elf.debug">
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createflash.251260409" name="Create flash image" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createflash" useByScannerDiscovery="false" value="true" valueType="boolean"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createlisting.1365878149" name="Create extended listing" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createlisting" useByScannerDiscovery="false"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize.709136944" name="Print size" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize" useByScannerDiscovery="false" value="true" valueType="boolean"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.1986446770" name="Optimization Level" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level" useByScannerDiscovery="true" value="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.none" valueType="enumerated"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.messagelength.1312975261" name="Message length (-fmessage-length=0)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.messagelength" useByScannerDiscovery="true" value="false" valueType="boolean"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.signedchar.1538128212" name="'char' is signed (-fsigned-char)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.signedchar" useByScannerDiscovery="true" value="false" valueType="boolean"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.functionsections.2136804218" name="Function sections (-ffunction-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.functionsections" useByScannerDiscovery="true" value="true" valueType="boolean"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.datasections.244767666" name="Data sections (-fdata-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.datasections" useByScannerDiscovery="true" value="true" valueType="boolean"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level.1055848773" name="Debug level" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level" useByScannerDiscovery="true" value="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level.default" valueType="enumerated"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format.501941135" name="Debug format" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format" useByScannerDiscovery="true" value="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format.dwarf2" valueType="enumerated"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.toolchain.name.1696308067" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.toolchain.name" useByScannerDiscovery="false" value="GNU Tools for ARM Embedded Processors" valueType="string"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.architecture.1558403188" name="Architecture" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.architecture" useByScannerDiscovery="false" value="ilg.gnuarmeclipse.managedbuild.cross.option.architecture.arm" valueType="enumerated"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.family.749415257" name="ARM family" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.family" useByScannerDiscovery="false" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.mcpu.cortex-m4" valueType="enumerated"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.instructionset.2114153533" name="Instruction set" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.instructionset" useByScannerDiscovery="false" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.instructionset.thumb" valueType="enumerated"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.prefix.1600865811" name="Prefix" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.prefix" useByScannerDiscovery="false" value="arm-none-eabi-" valueType="string"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.c.1109963929" name="C compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.c" useByScannerDiscovery="false" value="gcc" valueType="string"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.cpp.1040883831" name="C++ compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.cpp" useByScannerDiscovery="false" value="g++" valueType="string"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.ar.1678200391" name="Archiver" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.ar" useByScannerDiscovery="false" value="ar" valueType="string"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.objcopy.1171840296" name="Hex/Bin converter" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.objcopy" useByScannerDiscovery="false" value="objcopy" valueType="string"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.objdump.342604837" name="Listing generator" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.objdump" useByScannerDiscovery="false" value="objdump" valueType="string"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.size.898269225" name="Size command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.size" useByScannerDiscovery="false" value="size" valueType="string"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.make.2016398076" name="Build command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.make" useByScannerDiscovery="false" value="make" valueType="string"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.rm.1606171496" name="Remove command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.rm" useByScannerDiscovery="false" value="rm" valueType="string"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.toolchain.id.540792084" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.toolchain.id" useByScannerDiscovery="false" value="1287942917" valueType="string"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.architecture.430121817" name="Architecture" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.architecture" useByScannerDiscovery="false" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.arch.none" valueType="enumerated"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi.966735324" name="Float ABI" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi" useByScannerDiscovery="true" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi.hard" valueType="enumerated"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.allwarn.1381561249" name="Enable all common warnings (-Wall)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.allwarn" useByScannerDiscovery="true" value="true" valueType="boolean"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.target.other.2041717463" name="Other target flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.target.other" useByScannerDiscovery="true" value="" valueType="string"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.unit.1463655269" name="FPU Type" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.unit" useByScannerDiscovery="true" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.unit.fpv4spd16" valueType="enumerated"/>
<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="ilg.gnuarmeclipse.managedbuild.cross.targetPlatform.1798638225" isAbstract="false" osList="all" superClass="ilg.gnuarmeclipse.managedbuild.cross.targetPlatform"/>
<builder buildPath="${workspace_loc:/${ProjName}/Debug" cleanBuildTarget="clean2" id="ilg.gnuarmeclipse.managedbuild.cross.builder.1736709688" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="ilg.gnuarmeclipse.managedbuild.cross.builder"/>
<tool commandLinePattern="${COMMAND} ${cross_toolchain_flags} ${FLAGS} -c ${OUTPUT_FLAG} ${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.1810966071" name="GNU ARM Cross Assembler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler">
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.usepreprocessor.1072524326" name="Use preprocessor" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.usepreprocessor" useByScannerDiscovery="false" value="true" valueType="boolean"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.include.paths.161242639" name="Include paths (-I)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.include.paths" useByScannerDiscovery="true"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.defs.1521934876" name="Defined symbols (-D)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.defs" useByScannerDiscovery="true"/>
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.flags.1325367962" name="Assembler flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.flags" useByScannerDiscovery="false" valueType="stringList">
<listOptionValue builtIn="false" value="-mimplicit-it=thumb"/>
</option>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.other.647856572" name="Other assembler flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.other" useByScannerDiscovery="false" value="" valueType="string"/>
<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.input.1843333483" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.input"/>
</tool>
<tool commandLinePattern="${COMMAND} ${cross_toolchain_flags} ${FLAGS} -c ${OUTPUT_FLAG} ${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.1570350559" name="GNU ARM Cross C Compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler">
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.paths.634882052" name="Include paths (-I)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.paths" useByScannerDiscovery="true" valueType="includePath">
<listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//.}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//board/ports/wifi}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//board/ports}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//board}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//libraries/HAL_Drivers/config}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//libraries/HAL_Drivers}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//ra/arm/CMSIS_5/CMSIS/Core/Include}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//ra/fsp/inc/api}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//ra/fsp/inc/instances}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//ra/fsp/inc}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//ra/tes/dave2d/inc}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//ra_cfg/fsp_cfg/bsp}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//ra_cfg/fsp_cfg}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//ra_gen}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/components/drivers/include}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/components/finsh}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/components/libc/compilers/common/include}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/components/libc/compilers/newlib}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/components/libc/posix/io/poll}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/components/libc/posix/io/stdio}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/components/libc/posix/ipc}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/include}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/libcpu/arm/common}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/libcpu/arm/cortex-m4}&quot;"/>
</option>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.defs.100549972" name="Defined symbols (-D)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.defs" useByScannerDiscovery="true"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.other.2133065240" name="Other compiler flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.other" useByScannerDiscovery="true" value="" valueType="string"/>
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.files.714348818" name="Include files (-include)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.files" useByScannerDiscovery="true" valueType="includeFiles">
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/rtconfig_preinc.h}&quot;"/>
</option>
<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input.992053063" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input"/>
</tool>
<tool commandLinePattern="${COMMAND} ${cross_toolchain_flags} ${FLAGS} ${OUTPUT_FLAG} ${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.linker.869072473" name="Cross ARM C Linker" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.linker">
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.gcsections.1167322178" name="Remove unused sections (-Xlinker --gc-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.gcsections" useByScannerDiscovery="false" value="true" valueType="boolean"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.nostart.351692886" name="Do not use standard start files (-nostartfiles)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.nostart" useByScannerDiscovery="false" value="false" valueType="boolean"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.nostdlibs.1009243715" name="No startup or default libs (-nostdlib)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.nostdlibs" useByScannerDiscovery="false" value="false" valueType="boolean"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.nodeflibs.2016026082" name="Do not use default libraries (-nodefaultlibs)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.nodeflibs" useByScannerDiscovery="false" value="false" valueType="boolean"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.usenewlibnano.923990336" name="Use newlib-nano (--specs=nano.specs)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.usenewlibnano" useByScannerDiscovery="false" value="false" valueType="boolean"/>
<option defaultValue="true" id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.shared.548869459" name="Shared (-shared)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.shared" useByScannerDiscovery="false" valueType="boolean"/>
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.scriptfile.1818777301" name="Script files (-T)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.scriptfile" useByScannerDiscovery="false" valueType="stringList">
<listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//script/fsp.ld}&quot;"/>
</option>
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.libs.1135656995" name="Libraries (-l)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.libs" useByScannerDiscovery="false" valueType="libs">
<listOptionValue builtIn="false" value="c "/>
<listOptionValue builtIn="false" value="m "/>
</option>
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.paths.36884122" name="Library search path (-L)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.paths" useByScannerDiscovery="false" valueType="libPaths">
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/script}&quot;"/>
</option>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.other.396049466" name="Other linker flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.other" useByScannerDiscovery="false" value="" valueType="string"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.cref.1645737861" name="Cross reference (-Xlinker --cref)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.cref" useByScannerDiscovery="false" value="true" valueType="boolean"/>
<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.linker.input.334732222" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.linker.input">
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
</inputType>
</tool>
<tool commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG} ${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.1601059928" name="GNU ARM Cross C++ Linker" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker">
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.gcsections.437759352" name="Remove unused sections (-Xlinker --gc-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.gcsections" useByScannerDiscovery="false" value="true" valueType="boolean"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.scriptfile.1101974459" name="Script files (-T)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.scriptfile" useByScannerDiscovery="false"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.cref.2007675975" name="Cross reference (-Xlinker --cref)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.cref" useByScannerDiscovery="false" value="true" valueType="boolean"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.usenewlibnano.2105838438" name="Use newlib-nano (--specs=nano.specs)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.usenewlibnano" useByScannerDiscovery="false" value="true" valueType="boolean"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.libs.934137837" name="Libraries (-l)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.libs" useByScannerDiscovery="false"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.nostart.2118356996" name="Do not use standard start files (-nostartfiles)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.nostart" useByScannerDiscovery="false" value="false" valueType="boolean"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.nodeflibs.1427884346" name="Do not use default libraries (-nodefaultlibs)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.nodeflibs" useByScannerDiscovery="false" value="false" valueType="boolean"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.nostdlibs.1433863653" name="No startup or default libs (-nostdlib)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.nostdlibs" useByScannerDiscovery="false" value="false" valueType="boolean"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.printgcsections.1387745410" name="Print removed sections (-Xlinker --print-gc-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.printgcsections" useByScannerDiscovery="false" value="false" valueType="boolean"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.strip.1230158061" name="Omit all symbol information (-s)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.strip" useByScannerDiscovery="false" value="false" valueType="boolean"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.printmap.1307581821" name="Print link map (-Xlinker --print-map)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.printmap" useByScannerDiscovery="false" value="false" valueType="boolean"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.useprintffloat.960778920" name="Use float with nano printf (-u _printf_float)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.useprintffloat" useByScannerDiscovery="false" value="false" valueType="boolean"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.usescanffloat.637205035" name="Use float with nano scanf (-u _scanf_float)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.usescanffloat" useByScannerDiscovery="false" value="false" valueType="boolean"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.usenewlibnosys.1948314201" name="Do not use syscalls (--specs=nosys.specs)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.usenewlibnosys" useByScannerDiscovery="false" value="false" valueType="boolean"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.verbose.273162112" name="Verbose (-v)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.verbose" useByScannerDiscovery="false" value="false" valueType="boolean"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.paths.1399535143" name="Library search path (-L)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.paths" useByScannerDiscovery="false"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.other.882307902" name="Other linker flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.other" useByScannerDiscovery="false" value="-mcpu=cortex-m4 -mthumb -mfpu=fpv5-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -L script/" valueType="string"/>
<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.input.262373798" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.input">
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
</inputType>
</tool>
<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.archiver.506412204" name="GNU ARM Cross Archiver" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.archiver"/>
<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.createflash.1461589245" name="GNU ARM Cross Create Flash Image" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.createflash">
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice.1937707052" name="Output file format (-O)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice" useByScannerDiscovery="false" value="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice.ihex" valueType="enumerated"/>
</tool>
<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.createlisting.82359725" name="GNU ARM Cross Create Listing" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.createlisting">
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.source.601724476" name="Display source (--source|-S)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.source" value="true" valueType="boolean"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.allheaders.692505279" name="Display all headers (--all-headers|-x)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.allheaders" value="true" valueType="boolean"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.demangle.97345172" name="Demangle names (--demangle|-C)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.demangle" value="true" valueType="boolean"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.linenumbers.1342893377" name="Display line numbers (--line-numbers|-l)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.linenumbers" value="true" valueType="boolean"/>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.wide.1533725981" name="Wide lines (--wide|-w)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.wide" value="true" valueType="boolean"/>
</tool>
<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.printsize.1073550295" name="GNU ARM Cross Print Size" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.printsize">
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.printsize.format.946451386" name="Size format" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.printsize.format" useByScannerDiscovery="false"/>
</tool>
<tool commandLinePattern="${COMMAND} ${FLAGS} -c ${OUTPUT_FLAG} ${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.1302177015" name="GNU ARM Cross C++ Compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler">
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.defs.704468062" name="Defined symbols (-D)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.defs" useByScannerDiscovery="true"/>
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.paths.302877723" name="Include paths (-I)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.paths" useByScannerDiscovery="true" valueType="includePath">
<listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//.}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//board/ports/wifi}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//board/ports}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//board}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//libraries/HAL_Drivers/config}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//libraries/HAL_Drivers}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//ra/arm/CMSIS_5/CMSIS/Core/Include}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//ra/fsp/inc/api}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//ra/fsp/inc/instances}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//ra/fsp/inc}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//ra/tes/dave2d/inc}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//ra_cfg/fsp_cfg/bsp}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//ra_cfg/fsp_cfg}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//ra_gen}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/components/drivers/include}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/components/finsh}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/components/libc/compilers/common/include}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/components/libc/compilers/newlib}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/components/libc/posix/io/poll}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/components/libc/posix/io/stdio}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/components/libc/posix/ipc}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/include}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/libcpu/arm/common}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/libcpu/arm/cortex-m4}&quot;"/>
</option>
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.files.343249373" name="Include files (-include)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.files" useByScannerDiscovery="true" valueType="includeFiles">
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/rtconfig_preinc.h}&quot;"/>
</option>
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.other.465079095" name="Other compiler flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.other" useByScannerDiscovery="true" value="" valueType="string"/>
<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input.45918001" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input"/>
</tool>
</toolChain>
</folderInfo>
<sourceEntries>
<entry excluding="//board/lvgl|//board/ports|//libraries/HAL_Drivers/drv_adc.c|//libraries/HAL_Drivers/drv_can.c|//libraries/HAL_Drivers/drv_dac.c|//libraries/HAL_Drivers/drv_eth.c|//libraries/HAL_Drivers/drv_flash.c|//libraries/HAL_Drivers/drv_i2c.c|//libraries/HAL_Drivers/drv_lcd.c|//libraries/HAL_Drivers/drv_pwm.c|//libraries/HAL_Drivers/drv_rtc.c|//libraries/HAL_Drivers/drv_sci_spi.c|//libraries/HAL_Drivers/drv_sdhi.c|//libraries/HAL_Drivers/drv_soft_i2c.c|//libraries/HAL_Drivers/drv_spi.c|//libraries/HAL_Drivers/drv_wdt.c|//ra/board|//ra/fsp/src/r_ether_phy/targets|//rt-thread/components/dfs|//rt-thread/components/drivers/audio|//rt-thread/components/drivers/can|//rt-thread/components/drivers/cputime|//rt-thread/components/drivers/fdt|//rt-thread/components/drivers/hwcrypto|//rt-thread/components/drivers/hwtimer|//rt-thread/components/drivers/i2c|//rt-thread/components/drivers/misc/adc.c|//rt-thread/components/drivers/misc/dac.c|//rt-thread/components/drivers/misc/pulse_encoder.c|//rt-thread/components/drivers/misc/rt_dev_bus.c|//rt-thread/components/drivers/misc/rt_drv_pwm.c|//rt-thread/components/drivers/misc/rt_inputcapture.c|//rt-thread/components/drivers/misc/rt_null.c|//rt-thread/components/drivers/misc/rt_random.c|//rt-thread/components/drivers/misc/rt_zero.c|//rt-thread/components/drivers/mtd|//rt-thread/components/drivers/phy|//rt-thread/components/drivers/pm|//rt-thread/components/drivers/rtc|//rt-thread/components/drivers/sdio|//rt-thread/components/drivers/sensor|//rt-thread/components/drivers/serial/serial.c|//rt-thread/components/drivers/spi|//rt-thread/components/drivers/touch|//rt-thread/components/drivers/tty|//rt-thread/components/drivers/usb|//rt-thread/components/drivers/virtio|//rt-thread/components/drivers/watchdog|//rt-thread/components/drivers/wlan|//rt-thread/components/fal|//rt-thread/components/finsh/msh_file.c|//rt-thread/components/legacy|//rt-thread/components/libc/compilers/armlibc|//rt-thread/components/libc/compilers/dlib|//rt-thread/components/libc/compilers/musl|//rt-thread/components/libc/cplusplus|//rt-thread/components/libc/posix|//rt-thread/components/lwp|//rt-thread/components/mm|//rt-thread/components/net|//rt-thread/components/utilities|//rt-thread/components/vbus|//rt-thread/components/vmm|//rt-thread/examples|//rt-thread/libcpu/aarch64|//rt-thread/libcpu/arc|//rt-thread/libcpu/arm/AT91SAM7S|//rt-thread/libcpu/arm/AT91SAM7X|//rt-thread/libcpu/arm/am335x|//rt-thread/libcpu/arm/arm926|//rt-thread/libcpu/arm/armv6|//rt-thread/libcpu/arm/common/divsi3.S|//rt-thread/libcpu/arm/cortex-a|//rt-thread/libcpu/arm/cortex-m0|//rt-thread/libcpu/arm/cortex-m23|//rt-thread/libcpu/arm/cortex-m3|//rt-thread/libcpu/arm/cortex-m33|//rt-thread/libcpu/arm/cortex-m4/context_iar.S|//rt-thread/libcpu/arm/cortex-m4/context_rvds.S|//rt-thread/libcpu/arm/cortex-m7|//rt-thread/libcpu/arm/cortex-r4|//rt-thread/libcpu/arm/dm36x|//rt-thread/libcpu/arm/lpc214x|//rt-thread/libcpu/arm/lpc24xx|//rt-thread/libcpu/arm/realview-a8-vmm|//rt-thread/libcpu/arm/s3c24x0|//rt-thread/libcpu/arm/s3c44b0|//rt-thread/libcpu/arm/sep4020|//rt-thread/libcpu/arm/zynqmp-r5|//rt-thread/libcpu/avr32|//rt-thread/libcpu/blackfin|//rt-thread/libcpu/c-sky|//rt-thread/libcpu/ia32|//rt-thread/libcpu/m16c|//rt-thread/libcpu/mips|//rt-thread/libcpu/nios|//rt-thread/libcpu/ppc|//rt-thread/libcpu/risc-v|//rt-thread/libcpu/rx|//rt-thread/libcpu/sim|//rt-thread/libcpu/sparc-v8|//rt-thread/libcpu/ti-dsp|//rt-thread/libcpu/unicore32|//rt-thread/libcpu/v850|//rt-thread/libcpu/xilinx|//rt-thread/src/cpu.c|//rt-thread/src/driver.c|//rt-thread/src/memheap.c|//rt-thread/src/mempool.c|//rt-thread/src/scheduler_mp.c|//rt-thread/src/signal.c|//rt-thread/src/slab.c|//rt-thread/tools" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
</sourceEntries>
</configuration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
<storageModule moduleId="ilg.gnumcueclipse.managedbuild.packs"/>
</cconfiguration>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<project id="qemu-vexpress-a9.ilg.gnuarmeclipse.managedbuild.cross.target.elf.860020518" name="Executable" projectType="ilg.gnuarmeclipse.managedbuild.cross.target.elf"/>
</storageModule>
<storageModule moduleId="scannerConfiguration">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
<scannerConfigBuildInfo instanceId="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.553091094;ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.553091094.;ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.1570350559;ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input.992053063">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
</scannerConfigBuildInfo>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
<storageModule moduleId="refreshScope" versionNumber="2">
<configuration configurationName="Debug">
<resource resourceType="PROJECT" workspacePath="/111"/>
</configuration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings">
<doc-comment-owner id="org.eclipse.cdt.ui.doxygen">
<path value=""/>
</doc-comment-owner>
</storageModule>
</cproject>

5
bsp/renesas/ra8m1-ek/.gitignore vendored Normal file
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@ -0,0 +1,5 @@
/RTE
/Listings
/Objects
ra_cfg.txt

9
bsp/renesas/ra8m1-ek/.ignore_format.yml Normal file
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@ -0,0 +1,9 @@
# files format check exclude path, please follow the instructions below to modify;
# If you need to exclude an entire folder, add the folder path in dir_path;
# If you need to exclude a file, add the path to the file in file_path.
dir_path:
- ra
- ra_gen
- ra_cfg
- RTE

28
bsp/renesas/ra8m1-ek/.project Normal file
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@ -0,0 +1,28 @@
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>ra6m3-temp</name>
<comment />
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<triggers>clean,full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
<triggers>full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.rt-thread.studio.rttnature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
</natures>
<linkedResources />
</projectDescription>

86
bsp/renesas/ra8m1-ek/.secure_azone Normal file
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@ -0,0 +1,86 @@
<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
<azone>
<rzone name="R7FA8M1AHECBD.rzone"/>
<partition>
<peripheral name="PORT0" group="PORT">
<slot name="P000" secure="true"/>
<slot name="P002" secure="true"/>
<slot name="P003" secure="true"/>
<slot name="P004" secure="true"/>
<slot name="P005" secure="true"/>
<slot name="P007" secure="true"/>
<slot name="P008" secure="true"/>
<slot name="P009" secure="true"/>
<slot name="P014" secure="true"/>
<slot name="P015" secure="true"/>
</peripheral>
<peripheral name="PORT1" group="PORT">
<slot name="P100" secure="true"/>
<slot name="P101" secure="true"/>
<slot name="P102" secure="true"/>
<slot name="P103" secure="true"/>
<slot name="P104" secure="true"/>
<slot name="P105" secure="true"/>
<slot name="P106" secure="true"/>
<slot name="P107" secure="true"/>
<slot name="P112" secure="true"/>
<slot name="P114" secure="true"/>
</peripheral>
<peripheral name="PORT2" group="PORT">
<slot name="P208" secure="true"/>
<slot name="P209" secure="true"/>
<slot name="P210" secure="true"/>
<slot name="P211" secure="true"/>
</peripheral>
<peripheral name="PORT3" group="PORT">
<slot name="P300" secure="true"/>
<slot name="P301" secure="true"/>
<slot name="P302" secure="true"/>
<slot name="P303" secure="true"/>
<slot name="P304" secure="true"/>
<slot name="P305" secure="true"/>
<slot name="P306" secure="true"/>
<slot name="P307" secure="true"/>
<slot name="P308" secure="true"/>
</peripheral>
<peripheral name="PORT4" group="PORT">
<slot name="P407" secure="true"/>
<slot name="P408" secure="true"/>
<slot name="P409" secure="true"/>
<slot name="P410" secure="true"/>
<slot name="P411" secure="true"/>
<slot name="P412" secure="true"/>
<slot name="P413" secure="true"/>
<slot name="P414" secure="true"/>
</peripheral>
<peripheral name="PORT5" group="PORT">
<slot name="P500" secure="true"/>
<slot name="P501" secure="true"/>
<slot name="P511" secure="true"/>
<slot name="P512" secure="true"/>
</peripheral>
<peripheral name="PORT6" group="PORT">
<slot name="P600" secure="true"/>
</peripheral>
<peripheral name="PORT8" group="PORT">
<slot name="P800" secure="true"/>
<slot name="P801" secure="true"/>
<slot name="P802" secure="true"/>
<slot name="P803" secure="true"/>
<slot name="P804" secure="true"/>
<slot name="P808" secure="true"/>
<slot name="P809" secure="true"/>
<slot name="P814" secure="true"/>
<slot name="P815" secure="true"/>
</peripheral>
<peripheral name="PORTB" group="PORT">
<slot name="PB01" secure="true"/>
</peripheral>
<peripheral name="ICU">
<slot name="IRQ0" secure="true"/>
<slot name="IRQ1" secure="true"/>
<slot name="IRQ2" secure="true"/>
<slot name="IRQ3" secure="true"/>
</peripheral>
</partition>
</azone>

159
bsp/renesas/ra8m1-ek/.secure_xml Normal file
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@ -0,0 +1,159 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<raConfiguration version="8">
<generalSettings>
<option key="#Board#" value="board.ra8m1ek"/>
<option key="CPU" value="RA8M1"/>
<option key="Core" value="CM85"/>
<option key="#TargetName#" value="R7FA8M1AHECBD"/>
<option key="#TargetARCHITECTURE#" value="cortex-m85"/>
<option key="#DeviceCommand#" value="R7FA8M1AH"/>
<option key="#RTOS#" value="_none"/>
<option key="#pinconfiguration#" value="R7FA8M1AHECBD.pincfg"/>
<option key="#FSPVersion#" value="5.0.0"/>
<option key="#ConfigurationFragments#" value="Renesas##BSP##Board##ra8m1_ek##"/>
<option key="#SELECTED_TOOLCHAIN#" value="com.arm.toolchain"/>
</generalSettings>
<raBspConfiguration/>
<raClockConfiguration>
<node id="board.clock.xtal.freq" mul="20000000" option="_edit"/>
<node id="board.clock.hoco.freq" option="board.clock.hoco.freq.48m"/>
<node id="board.clock.loco.freq" option="board.clock.loco.freq.32768"/>
<node id="board.clock.moco.freq" option="board.clock.moco.freq.8m"/>
<node id="board.clock.subclk.freq" option="board.clock.subclk.freq.32768"/>
<node id="board.clock.pll.source" option="board.clock.pll.source.xtal"/>
<node id="board.clock.pll.div" option="board.clock.pll.div.1"/>
<node id="board.clock.pll.mul" option="board.clock.pll.mul.48_00"/>
<node id="board.clock.pll.display" option="board.clock.pll.display.value"/>
<node id="board.clock.pll1p.div" option="board.clock.pll1p.div.2"/>
<node id="board.clock.pll1p.display" option="board.clock.pll1p.display.value"/>
<node id="board.clock.pll1q.div" option="board.clock.pll1q.div.2"/>
<node id="board.clock.pll1q.display" option="board.clock.pll1q.display.value"/>
<node id="board.clock.pll1r.div" option="board.clock.pll1r.div.2"/>
<node id="board.clock.pll1r.display" option="board.clock.pll1r.display.value"/>
<node id="board.clock.pll2.source" option="board.clock.pll2.source.disabled"/>
<node id="board.clock.pll2.div" option="board.clock.pll2.div.1"/>
<node id="board.clock.pll2.mul" option="board.clock.pll2.mul.48_00"/>
<node id="board.clock.pll2.display" option="board.clock.pll2.display.value"/>
<node id="board.clock.pll2p.div" option="board.clock.pll2p.div.2"/>
<node id="board.clock.pll2p.display" option="board.clock.pll2p.display.value"/>
<node id="board.clock.pll2q.div" option="board.clock.pll2q.div.2"/>
<node id="board.clock.pll2q.display" option="board.clock.pll2q.display.value"/>
<node id="board.clock.pll2r.div" option="board.clock.pll2r.div.2"/>
<node id="board.clock.pll2r.display" option="board.clock.pll2r.display.value"/>
<node id="board.clock.clock.source" option="board.clock.clock.source.pll1p"/>
<node id="board.clock.clkout.source" option="board.clock.clkout.source.disabled"/>
<node id="board.clock.sciclk.source" option="board.clock.sciclk.source.pll1p"/>
<node id="board.clock.spiclk.source" option="board.clock.spiclk.source.disabled"/>
<node id="board.clock.canfdclk.source" option="board.clock.canfdclk.source.disabled"/>
<node id="board.clock.i3cclk.source" option="board.clock.i3cclk.source.disabled"/>
<node id="board.clock.uck.source" option="board.clock.uck.source.disabled"/>
<node id="board.clock.u60ck.source" option="board.clock.u60ck.source.disabled"/>
<node id="board.clock.octaspiclk.source" option="board.clock.octaspiclk.source.disabled"/>
<node id="board.clock.cpuclk.div" option="board.clock.cpuclk.div.1"/>
<node id="board.clock.iclk.div" option="board.clock.iclk.div.2"/>
<node id="board.clock.pclka.div" option="board.clock.pclka.div.4"/>
<node id="board.clock.pclkb.div" option="board.clock.pclkb.div.8"/>
<node id="board.clock.pclkc.div" option="board.clock.pclkc.div.8"/>
<node id="board.clock.pclkd.div" option="board.clock.pclkd.div.4"/>
<node id="board.clock.pclke.div" option="board.clock.pclke.div.2"/>
<node id="board.clock.sdclkout.enable" option="board.clock.sdclkout.enable.enabled"/>
<node id="board.clock.bclk.div" option="board.clock.bclk.div.4"/>
<node id="board.clock.bclkout.div" option="board.clock.bclkout.div.2"/>
<node id="board.clock.fclk.div" option="board.clock.fclk.div.8"/>
<node id="board.clock.clkout.div" option="board.clock.clkout.div.1"/>
<node id="board.clock.sciclk.div" option="board.clock.sciclk.div.4"/>
<node id="board.clock.spiclk.div" option="board.clock.spiclk.div.4"/>
<node id="board.clock.canfdclk.div" option="board.clock.canfdclk.div.8"/>
<node id="board.clock.i3cclk.div" option="board.clock.i3cclk.div.3"/>
<node id="board.clock.uck.div" option="board.clock.uck.div.5"/>
<node id="board.clock.u60ck.div" option="board.clock.u60ck.div.5"/>
<node id="board.clock.octaspiclk.div" option="board.clock.octaspiclk.div.4"/>
<node id="board.clock.cpuclk.display" option="board.clock.cpuclk.display.value"/>
<node id="board.clock.iclk.display" option="board.clock.iclk.display.value"/>
<node id="board.clock.pclka.display" option="board.clock.pclka.display.value"/>
<node id="board.clock.pclkb.display" option="board.clock.pclkb.display.value"/>
<node id="board.clock.pclkc.display" option="board.clock.pclkc.display.value"/>
<node id="board.clock.pclkd.display" option="board.clock.pclkd.display.value"/>
<node id="board.clock.pclke.display" option="board.clock.pclke.display.value"/>
<node id="board.clock.sdclkout.display" option="board.clock.sdclkout.display.value"/>
<node id="board.clock.bclk.display" option="board.clock.bclk.display.value"/>
<node id="board.clock.bclkout.display" option="board.clock.bclkout.display.value"/>
<node id="board.clock.fclk.display" option="board.clock.fclk.display.value"/>
<node id="board.clock.clkout.display" option="board.clock.clkout.display.value"/>
<node id="board.clock.sciclk.display" option="board.clock.sciclk.display.value"/>
<node id="board.clock.spiclk.display" option="board.clock.spiclk.display.value"/>
<node id="board.clock.canfdclk.display" option="board.clock.canfdclk.display.value"/>
<node id="board.clock.i3cclk.display" option="board.clock.i3cclk.display.value"/>
<node id="board.clock.uck.display" option="board.clock.uck.display.value"/>
<node id="board.clock.u60ck.display" option="board.clock.u60ck.display.value"/>
<node id="board.clock.octaspiclk.display" option="board.clock.octaspiclk.display.value"/>
</raClockConfiguration>
<raPinConfiguration>
<pincfg active="true" name="" symbol="">
<configSetting altId="adc0.an000.p004" configurationId="adc0.an000"/>
<configSetting altId="adc0.an001.p005" configurationId="adc0.an001"/>
<configSetting altId="adc0.an004.p007" configurationId="adc0.an004"/>
<configSetting altId="adc0.an007.p014" configurationId="adc0.an007"/>
<configSetting altId="adc1.an102.p002" configurationId="adc1.an102"/>
<configSetting altId="adc1.an104.p003" configurationId="adc1.an104"/>
<configSetting altId="adc1.an105.p015" configurationId="adc1.an105"/>
<configSetting altId="adc1.an106.p011" configurationId="adc1.an106"/>
<configSetting altId="ether_rmii.et0_linksta.p114" configurationId="ether_rmii.et0_linksta"/>
<configSetting altId="ether_rmii.et0_mdc.p308" configurationId="ether_rmii.et0_mdc"/>
<configSetting altId="ether_rmii.et0_mdio.p307" configurationId="ether_rmii.et0_mdio"/>
<configSetting altId="ether_rmii.ref50ck0.p303" configurationId="ether_rmii.ref50ck0"/>
<configSetting altId="ether_rmii.rmii0_crs_dv.p112" configurationId="ether_rmii.rmii0_crs_dv"/>
<configSetting altId="ether_rmii.rmii0_rx_er.p300" configurationId="ether_rmii.rmii0_rx_er"/>
<configSetting altId="ether_rmii.rmii0_rxd0.p302" configurationId="ether_rmii.rmii0_rxd0"/>
<configSetting altId="ether_rmii.rmii0_rxd1.p301" configurationId="ether_rmii.rmii0_rxd1"/>
<configSetting altId="ether_rmii.rmii0_txd0.p304" configurationId="ether_rmii.rmii0_txd0"/>
<configSetting altId="ether_rmii.rmii0_txd1.p305" configurationId="ether_rmii.rmii0_txd1"/>
<configSetting altId="ether_rmii.rmii0_txd_en.p306" configurationId="ether_rmii.rmii0_txd_en"/>
<configSetting altId="iic1.scl1.p512" configurationId="iic1.scl1"/>
<configSetting altId="iic1.sda1.p511" configurationId="iic1.sda1"/>
<configSetting altId="irq12.irq12_dash_ds.p008" configurationId="irq12.irq12_dash_ds"/>
<configSetting altId="irq13.irq13_dash_ds.p009" configurationId="irq13.irq13_dash_ds"/>
<configSetting altId="jtag_fslash_swd.tck.p211" configurationId="jtag_fslash_swd.tck"/>
<configSetting altId="jtag_fslash_swd.tdi.p208" configurationId="jtag_fslash_swd.tdi"/>
<configSetting altId="jtag_fslash_swd.tdo.p209" configurationId="jtag_fslash_swd.tdo"/>
<configSetting altId="jtag_fslash_swd.tms.p210" configurationId="jtag_fslash_swd.tms"/>
<configSetting altId="ospi.om_cs1.p104" configurationId="ospi.om_cs1"/>
<configSetting altId="ospi.om_dqs.p801" configurationId="ospi.om_dqs"/>
<configSetting altId="ospi.om_ecsint1.p105" configurationId="ospi.om_ecsint1"/>
<configSetting altId="ospi.om_reset.p106" configurationId="ospi.om_reset"/>
<configSetting altId="ospi.om_sclk.p808" configurationId="ospi.om_sclk"/>
<configSetting altId="ospi.om_sio0.p100" configurationId="ospi.om_sio0"/>
<configSetting altId="ospi.om_sio1.p803" configurationId="ospi.om_sio1"/>
<configSetting altId="ospi.om_sio2.p103" configurationId="ospi.om_sio2"/>
<configSetting altId="ospi.om_sio3.p101" configurationId="ospi.om_sio3"/>
<configSetting altId="ospi.om_sio4.p102" configurationId="ospi.om_sio4"/>
<configSetting altId="ospi.om_sio5.p800" configurationId="ospi.om_sio5"/>
<configSetting altId="ospi.om_sio6.p802" configurationId="ospi.om_sio6"/>
<configSetting altId="ospi.om_sio7.p804" configurationId="ospi.om_sio7"/>
<configSetting altId="p000.input" configurationId="p000"/>
<configSetting altId="p107.output.low" configurationId="p107"/>
<configSetting altId="p414.output.low" configurationId="p414"/>
<configSetting altId="p600.output.low" configurationId="p600"/>
<configSetting altId="p809.output.low" configurationId="p809"/>
<configSetting altId="pa06.input" configurationId="pa06"/>
<configSetting altId="sci2.cts_rts2.pa05" configurationId="sci2.cts_rts2"/>
<configSetting altId="sci2.rxd2.pa02" configurationId="sci2.rxd2"/>
<configSetting altId="sci2.sck2.pa04" configurationId="sci2.sck2"/>
<configSetting altId="sci2.txd2.pa03" configurationId="sci2.txd2"/>
<configSetting altId="sci9.rxd9.pa15" configurationId="sci9.rxd9" isUsedByDriver="true"/>
<configSetting altId="sci9.txd9.pa14" configurationId="sci9.txd9" isUsedByDriver="true"/>
<configSetting altId="spi1.miso1.p410" configurationId="spi1.miso1"/>
<configSetting altId="spi1.mosi1.p411" configurationId="spi1.mosi1"/>
<configSetting altId="spi1.rspck1.p412" configurationId="spi1.rspck1"/>
<configSetting altId="spi1.sslb0.p413" configurationId="spi1.sslb0"/>
<configSetting altId="usbfs.usb_dm.p815" configurationId="usbfs.usb_dm"/>
<configSetting altId="usbfs.usb_dp.p814" configurationId="usbfs.usb_dp"/>
<configSetting altId="usbfs.usb_ovrcura.p501" configurationId="usbfs.usb_ovrcura"/>
<configSetting altId="usbfs.usb_vbus.p407" configurationId="usbfs.usb_vbus"/>
<configSetting altId="usbfs.usb_vbusen.p500" configurationId="usbfs.usb_vbusen"/>
<configSetting altId="usbhs.usbhs_ovrcura.p409" configurationId="usbhs.usbhs_ovrcura"/>
<configSetting altId="usbhs.usbhs_vbus.pb01" configurationId="usbhs.usbhs_vbus"/>
<configSetting altId="usbhs.usbhs_vbusen.p408" configurationId="usbhs.usbhs_vbusen"/>
</pincfg>
</raPinConfiguration>
</raConfiguration>

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bsp/renesas/ra8m1-ek/.settings/.rtmenus Normal file
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Binary file not shown.

14
bsp/renesas/ra8m1-ek/.settings/language.settings.xml Normal file
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@ -0,0 +1,14 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project>
<configuration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.553091094" name="Debug">
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-1208902908258079360" id="ilg.gnuarmeclipse.managedbuild.cross.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT ARM Cross GCC Built-in Compiler Settings " parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
<language-scope id="org.eclipse.cdt.core.gcc"/>
<language-scope id="org.eclipse.cdt.core.g++"/>
</provider>
</extension>
</configuration>
</project>

3
bsp/renesas/ra8m1-ek/.settings/org.eclipse.core.runtime.prefs Normal file
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@ -0,0 +1,3 @@
content-types/enabled=true
content-types/org.eclipse.cdt.core.asmSource/file-extensions=s
eclipse.preferences.version=1

19
bsp/renesas/ra8m1-ek/.settings/projcfg.ini Normal file
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@ -0,0 +1,19 @@
#RT-Thread Studio Project Configuration
#Tue Jan 10 14:37:39 CST 2023
cfg_version=v3.0
board_name=ra6m3-ek
example_name=
hardware_adapter=J-Link
board_base_nano_proj=false
project_type=rt-thread
chip_name=R7FA6M3AH\n
selected_rtt_version=latest
bsp_version=
os_branch=master
project_base_rtt_bsp=true
output_project_path=E\:softwareRT-ThreadStudioworkspace\ra6m3-temp
is_base_example_project=false
is_use_scons_build=true
project_name=ra6m3-temp
os_version=latest
bsp_path=

90
bsp/renesas/ra8m1-ek/.settings/ra6m3-temp.JLink.Debug.rttlaunch Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.jlink.launchConfigurationType">
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.adapterName" value="J-Link"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.binFileStartAddress" value=""/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doConnectToRunning" value="false"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doContinue" value="true"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doDebugInRam" value="false"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doFirstReset" value="true"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerAllocateConsole" value="true"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerAllocateSemihostingConsole" value="true"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerInitRegs" value="true"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerLocalOnly" value="true"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerSilent" value="false"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerVerifyDownload" value="true"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doSecondReset" value="true"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doStartGdbServer" value="true"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableFlashBreakpoints" value="true"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableSemihosting" value="true"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableSemihostingIoclientGdbClient" value="false"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableSemihostingIoclientTelnet" value="true"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableSwo" value="false"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.eraseEndAddress" value=""/>
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.eraseMode" value="0"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.eraseStartAddress" value=""/>
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.firstResetSpeed" value="1000"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.firstResetType" value=""/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.flashDeviceName" value="R7FA6M3AH&#10;"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.flashDownloadHex" value="true"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.forceQuitGdbServer" value="false"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbClientOtherCommands" value="set mem inaccessible-by-default off"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbClientOtherOptions" value=""/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerConnection" value="usb"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerConnectionAddress" value=""/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDebugInterface" value="swd"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDeviceEndianness" value="little"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDeviceName" value="R7FA6M3AH"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDeviceSpeed" value="100000"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerExecutable" value="${debugger_install_path}/${jlink_debugger_relative_path}\JLinkGDBServerCL.exe"/>
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerGdbPortNumber" value="2331"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerLog" value=""/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerOther" value="-singlerun"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerRunAfterStopDebug" value="true"/>
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerSwoPortNumber" value="2332"/>
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerTelnetPortNumber" value="2333"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.interfaceSpeed" value="auto"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.jlinkExecutable" value="${debugger_install_path}/${jlink_debugger_relative_path}\JLink.exe"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.otherInitCommands" value=""/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.otherRunCommands" value=""/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.runAfterDownload" value="true"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.secondResetType" value=""/>
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetCpuFreq" value="0"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetPortMask" value="0x1"/>
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetSwoFreq" value="0"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU J-Link"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="2331"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${rtt_gnu_gcc}/arm-none-eabi-gdb.exe"/>
<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="0"/>
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/rtthread.elf"/>
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="ra6m3-temp"/>
<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
<listEntry value="/ra6m3-temp"/>
</listAttribute>
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
<listEntry value="4"/>
</listAttribute>
<stringAttribute key="org.eclipse.debug.core.source_locator_id" value="org.eclipse.cdt.debug.core.sourceLocator"/>
<stringAttribute key="org.eclipse.debug.core.source_locator_memento" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;sourceLookupDirector&gt;&#13;&#10;&lt;sourceContainers duplicates=&quot;false&quot;&gt;&#13;&#10;&lt;container memento=&quot;&amp;lt;?xml version=&amp;quot;1.0&amp;quot; encoding=&amp;quot;UTF-8&amp;quot; standalone=&amp;quot;no&amp;quot;?&amp;gt;&amp;#13;&amp;#10;&amp;lt;default/&amp;gt;&amp;#13;&amp;#10;&quot; typeId=&quot;org.eclipse.debug.core.containerType.default&quot;/&gt;&#13;&#10;&lt;/sourceContainers&gt;&#13;&#10;&lt;/sourceLookupDirector&gt;&#13;&#10;"/>
<stringAttribute key="org.eclipse.debug.ui.ATTR_CONSOLE_ENCODING" value="GBK"/>
</launchConfiguration>

21
bsp/renesas/ra8m1-ek/.settings/standalone.prefs Normal file
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@ -0,0 +1,21 @@
#Mon Oct 30 16:09:15 CST 2023
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_b_uart\#\#\#\#5.0.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#5.0.0/all=1896254027,ra/fsp/inc/api/r_ioport_api.h|3058606325,ra/fsp/inc/instances/r_ioport.h|3002446768,ra/fsp/src/r_ioport/r_ioport.c
com.renesas.cdt.ddsc.content/com.renesas.cdt.ddsc.content.defaultlinkerscript=script/fsp.scat
com.renesas.cdt.ddsc.contentgen.options/options/suppresswarningspaths=ra/arm
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra8m1\#\#device\#\#R7FA8M1AHECBD\#\#5.0.0/libraries=
com.renesas.cdt.ddsc.settingseditor/com.renesas.cdt.ddsc.settingseditor.active_page=ELCConfigurator
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra8m1\#\#device\#\#\#\#5.0.0/all=3557931260,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA8M1AH.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#5.0.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra8m1\#\#fsp\#\#\#\#5.0.0/all=4143092756,script/fsp.scat|346195372,script/ac6/fsp_keep.via|934437302,ra/fsp/inc/fsp_features.h|3058606325,ra/fsp/inc/instances/r_ioport.h|1171232788,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|543620856,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|1277668127,ra/fsp/src/bsp/mcu/ra8m1/bsp_mcu_info.h|3527988232,ra/fsp/src/bsp/mcu/ra8m1/bsp_override.h|1726006039,ra/fsp/src/bsp/mcu/ra8m1/bsp_elc.h|2183999466,ra/fsp/src/bsp/mcu/ra8m1/bsp_feature.h|1884526901,ra/fsp/src/bsp/mcu/all/bsp_register_protection.h|1437525339,ra/fsp/src/bsp/mcu/all/bsp_register_protection.c|248082807,ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h|3324174567,ra/fsp/src/bsp/mcu/all/bsp_exceptions.h|2550773705,ra/fsp/src/bsp/mcu/all/bsp_tfu.h|271204625,ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h|1668386995,ra/fsp/src/bsp/mcu/all/bsp_security.h|690210506,ra/fsp/src/bsp/mcu/all/bsp_irq.h|2942105346,ra/fsp/src/bsp/mcu/all/bsp_irq.c|296810838,ra/fsp/src/bsp/mcu/all/bsp_guard.c|1246740431,ra/fsp/src/bsp/mcu/all/bsp_delay.h|1331691689,ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c|3569788004,ra/fsp/src/bsp/mcu/all/bsp_io.h|3610800851,ra/fsp/src/bsp/mcu/all/bsp_guard.h|2964028862,ra/fsp/src/bsp/mcu/all/bsp_common.h|3881030941,ra/fsp/src/bsp/mcu/all/bsp_clocks.h|3171976222,ra/fsp/src/bsp/mcu/all/bsp_security.c|429234293,ra/fsp/src/bsp/mcu/all/bsp_common.c|1872304413,ra/fsp/src/bsp/mcu/all/bsp_clocks.c|4092753007,ra/fsp/src/bsp/mcu/all/bsp_delay.c|2702335218,ra/fsp/src/bsp/mcu/all/bsp_group_irq.c|3085135894,ra/fsp/src/bsp/mcu/all/bsp_group_irq.h|2365965045,ra/fsp/src/bsp/mcu/all/bsp_sbrk.c|1835725510,ra/fsp/src/bsp/mcu/all/bsp_io.c|2551036977,ra/fsp/src/bsp/mcu/all/bsp_module_stop.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra8m1\#\#fsp\#\#\#\#5.0.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.9.0+renesas.0.fsp.5.0.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.9.0+renesas.0.fsp.5.0.0/all=1441545198,ra/arm/CMSIS_5/LICENSE.txt|304461792,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h|1480183821,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h|3898569239,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h|2327633156,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h|1608305587,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm85.h|2701379970,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h|3778515955,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h|965562395,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h|3007265674,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h|1577199483,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h|2635219934,ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h|1438162915,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h|4290386133,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h|3358993753,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h|1017116116,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h|1745843273,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h|364344841,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h|4084823319,ra/arm/CMSIS_5/CMSIS/Core/Include/pac_armv81.h|302860276,ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h|3163610011,ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h|4147548732,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h|1564341101,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h|1290634672,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h|1494441116,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h|1372010515,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h|1924015782,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h|2851112248,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h|3911746910,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h|2675617387,ra/arm/CMSIS_5/CMSIS/Core/Include/core_starmc1.h|1044777225,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_b_uart\#\#\#\#5.0.0/all=3115705082,ra/fsp/inc/api/r_transfer_api.h|1476071459,ra/fsp/inc/api/r_uart_api.h|419014891,ra/fsp/inc/instances/r_sci_b_uart.h|3063216256,ra/fsp/src/r_sci_b_uart/r_sci_b_uart.c
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#5.0.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra8m1\#\#device\#\#R7FA8M1AHECBD\#\#5.0.0/all=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#5.0.0/all=107063585,ra/fsp/inc/fsp_version.h|2560512765,ra/fsp/inc/api/bsp_api.h|1896254027,ra/fsp/inc/api/r_ioport_api.h|1037141086,ra/fsp/inc/api/fsp_common_api.h|4290340792,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|3566655744,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#ra8m1_ek\#\#\#\#5.0.0/all=2370294288,ra/board/ra8m1_ek/board_init.h|3816945414,ra/board/ra8m1_ek/board_init.c|3071464958,ra/board/ra8m1_ek/board_leds.h|3090459819,ra/board/ra8m1_ek/board_leds.c|106221315,ra/board/ra8m1_ek/board.h|1919213143,ra/board/ra8m1_ek/board_ethernet_phy.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#ra8m1_ek\#\#\#\#5.0.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra8m1\#\#device\#\#\#\#5.0.0/libraries=
com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.uart_on_sci_b_uart.1514241209=false

29
bsp/renesas/ra8m1-ek/Kconfig Normal file
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@ -0,0 +1,29 @@
mainmenu "RT-Thread Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config RTT_DIR
string
option env="RTT_ROOT"
default "../../.."
# you can change the RTT_ROOT default "../.." to your rtthread_root,
# example : default "F:/git_repositories/rt-thread"
config PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
config ENV_DIR
string
option env="ENV_ROOT"
default "/"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
source "../libraries/Kconfig"
source "$BSP_DIR/board/Kconfig"

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# 瑞萨 EK-RA8M1 开发板 BSP 说明
中文|[English](README_EN.md)
## 简介
本文档为 EK-RA8M1 开发板提供的 BSP (板级支持包) 说明。通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。
主要内容如下：
- 开发板介绍
- BSP 快速上手指南
## 开发板介绍
基于瑞萨 RA8M1 MCU 开发的 EK-RA8M1 评估板，通过灵活配置软件包和 IDE，可帮助用户对 RA8 MCU 群组的特性轻松进行评估，并对嵌入系统应用程序进行开发。
开发板正面外观如下图：
![](docs/picture/front.png)
该开发板常用 **板载资源** 如下：
- MCU：R7FA8M1AH，480MHz，**Arm®Cortex®-M85** 内核，2MB 代码闪存, 1MB SRAM
- Jlink OB
- OSPI FLASH（64MX8）
- USB-Host
- USB-Device
- CANFD
- 以太网接口
- 2个PMOD+Arduino+micro BUS接口
- 3个用户LED
- 3个按键：2个用户按键，1个复位按键
**更多详细资料及工具**
## 外设支持
本 BSP 目前对外设的支持情况如下：
| **片上外设** | **支持情况** | **备注** |
| :----------------: | :----------------: | :------------- |
| UART | 支持 | UART9 为默认日志输出端口 |
| GPIO | 支持 | |
* 注意：仓库刚拉下来是最小系统，若需添加/使能其他外设需参考：[外设驱动使用教程 (rt-thread.org)](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/tutorial/make-bsp/renesas-ra/RA系列BSP外设驱动使用教程)
## 使用说明
使用说明分为如下两个章节：
- 快速上手
本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
- 进阶使用
本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
### 支持的编译平台
* armclang（AC6 V6.19）
* LLVM（V16/17）[ARM-software/LLVM-embedded-toolchain-for-Arm (github.com)](https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm/releases/tag/release-17.0.1)
### 快速上手
#### 1、使用 MDK 编译：
本 BSP 目前提供 MDK5 工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
**编译下载**
- 编译：双击 project.uvprojx 文件，打开 MDK5 工程，编译程序。
- 下载：点击 MDK 的 Debug 按钮进行下载调试
#### 2、使用 LLVM 编译
使用 env 工具打开当前 bsp，设定要使用的工具链和对应的路径。
```shell
set RTT_CC=llvm-arm
set RTT_EXEC_PATH=D:\Progrem\LLVMEmbeddedToolchainForArm-17.0.1-Windows-x86_64\bin
```
然后运行 scons 命令，执行编译
```shell
scons
```
**查看运行结果**
下载程序成功之后，系统会自动运行并打印系统信息。
连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息。输入 help 命令可查看系统中支持的命令。
```bash
initialize rti_board_start:0 done
\ | /
- RT - Thread Operating System
/ | \ 5.1.0 build Oct 30 2023 16:14:05
2006 - 2022 Copyright by RT-Thread team
do components initialization.
initialize rti_board_end:0 done
initialize finsh_system_init:0 done
Hello RT-Thread!
msh >
```
**应用入口函数**
应用层的入口函数在 **bsp\renesas\ra8m1-ek\src\hal_entry.c** 中 的 `void hal_entry(void)` 。用户编写的源文件可直接放在 src 目录下。
```c
void hal_entry(void)
{
rt_kprintf("\nHello RT-Thread!\n");
while (1)
{
rt_pin_write(LED3_PIN, PIN_HIGH);
rt_thread_mdelay(500);
rt_pin_write(LED3_PIN, PIN_LOW);
rt_thread_mdelay(500);
}
}
```
### 进阶使用
**资料及文档**
- [开发板官网主页]([EK-RA8M1 - RA8M1 MCU 群组评估套件 | Renesas](https://www.renesas.cn/cn/zh/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra8m1-evaluation-kit-ra8m1-mcu-group))
- [开发板用户手册](https://www.renesas.cn/cn/zh/document/mat/ek-ra8m1-users-manual?r=25448206)
- [瑞萨RA MCU 基础知识](https://www2.renesas.cn/cn/zh/document/gde/1520091)
**ENV 配置**
- 如何使用 ENV 工具：[RT-Thread env 工具用户手册](https://www.rt-thread.org/document/site/#/development-tools/env/env)
此 BSP 默认只开启了 UART9 的功能，如果需使用更多高级功能例如组件、软件包等，需要利用 ENV 工具进行配置。
步骤如下：
1. 在 bsp 下打开 env 工具。
2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
3. 输入`pkgs --update`命令更新软件包。
4. 输入`scons --target=mdk5` 命令重新生成工程。
## 联系人信息
在使用过程中若您有任何的想法和建议，建议您通过以下方式来联系到我们 [RT-Thread 社区论坛](https://club.rt-thread.org/)
## 贡献代码
如果您对 EK-RA8M1 感兴趣，并且有一些好玩的项目愿意与大家分享的话欢迎给我们贡献代码，您可以参考 [如何向 RT-Thread 代码贡献](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/development-guide/github/github)。

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# EK-RA8M1 BSP Instruction
中文|[English](README.md)
## Introduction
Prepare for an exhilarating journey into the realm of the EK-RA8M1 development board! This guide is your treasure map, leading you to a trove of knowledge about the Board Support Package (BSP). The Quick Start section is your launchpad, propelling developers into action with the BSP, and getting RT-Thread operational on the development board faster than a speeding bullet.
Here’s a sneak peek of the adventure that awaits:
• A captivating exploration of the development board
• A practical and user-friendly BSP Quick Start Guide
## Hardware
The EK-RA8M1 evaluation board, developed based on the Renesas RA8M1 MCU, is a handy tool that allows users to easily evaluate the features of the RA8 MCU group. With flexible software package and IDE configurations, it’s a breeze to develop embedded system applications.
Here’s a sneak peek of what the front of the development board looks like:
![](docs/picture/front.png)
The board comes with some commonly used **on-board resources**. Let’s dive in and explore!
- MCU: R7FA8M1AH, 480MHz, **Arm®Cortex®-M85**, 2MB Flash, 1MB SRAM
- Jlink OB
- OSPI FLASH（64MX8）
- USB-Host
- USB-Device
- CANFD
- ethernet
- 2个PMOD+Arduino+micro BUS interface
- 3 user LED
- 3 button: 2 user button, 1 reset button
**More Details**
### Peripheral Condition
Each peripheral supporting condition for this BSP is as follows:
| **On-chip Peripheral Drivers** | **Support** | **Remark** |
| :----------------: | :----------------: | :------------- |
| UART | Support | UART9 is the default log output port. |
| GPIO | Support | |
## Instructions for Use
The instructions for use are divided into the following two sections:
• Quick Start
This section is a user guide for newcomers to RT-Thread. By following simple steps, you can run the RT-Thread operating system on this development board and see the experimental results.
• Advanced Use
This section is for developers who want to enable more development board resources on the RT-Thread operating system. By using the ENV tool to configure the BSP, you can enable more on-board resources and achieve more advanced functions.
### Quick Start
This BSP currently only provides an MDK5 project. The following tutorial takes the MDK5 development environment as an example to introduce how to run the system.
**Compile and Download**
• Compile: Double-click the **project.uvprojx** file to open the MDK5 project and compile the program.
• Download: Click the Debug button in MDK to download and debug
**Running results**
After the program is downloaded successfully, the system will automatically run and print system information.
Connect the corresponding serial port of the development board to the PC, open the corresponding serial port (115200-8-1-N) in the terminal tool, reset the device, and you can see RT-Thread’s output information. Enter the help command can view the commands supported by the system.
```bash
initialize rti_board_start:0 done
\ | /
- RT - Thread Operating System
/ | \ 5.1.0 build Oct 30 2023 16:14:05
2006 - 2022 Copyright by RT-Thread team
do components initialization.
initialize rti_board_end:0 done
initialize finsh_system_init:0 done
Hello RT-Thread!
msh >
```
**Entry function**
The entry function of the application layer is in **bsp\renesas\ra8m1-ek\src\hal_entry.c** in `void hal_entry(void)`. Source files that you created can be placed directly in the src directory.
```c
void hal_entry(void)
{
rt_kprintf("\nHello RT-Thread!\n");
while (1)
{
rt_pin_write(LED3_PIN, PIN_HIGH);
rt_thread_mdelay(500);
rt_pin_write(LED3_PIN, PIN_LOW);
rt_thread_mdelay(500);
}
}
```
### Advanced Features
**Resources & Documents**
- [Development Board Overview](https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra8m1-480-mhz-arm-cortex-m85-based-microcontroller-helium-and-trustzone)
- [User Guide](https://www.renesas.cn/cn/zh/document/mat/ek-ra8m1-users-manual1)
- [RA MCU](https://www.renesas.com/us/en/document/gde/1520091)
**ENV Configuration**
• How to use the ENV tool: [RT-Thread env tool user manual](https://www.rt-thread.io/document/site/programming-manual/env/env/).
This BSP only enables the function of UART9 by default. If you're looking for more advanced functions such as components and software packages, ENV tool for configuration is available.
The steps are as follows:
1. Open the env tool under bsp.
2. Enter the `menuconfig` command to configure the project, and save and exit after configuration.
3. Enter the `pkgs --update` command to update the software package.
4. Enter the `scons --target=mdk5` command to regenerate the project.
## Contribute the Code
If you’re interested in the EK-RA8M1 and have some cool projects you’d like to share with everyone, we’d love for you to contribute your code! You can check out [how to contribute to RT-Thread’s code](https://www.rt-thread.io/contribution.html). Let’s make something awesome together!

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# for module compiling
import os
Import('RTT_ROOT')
Import('rtconfig')
from building import *
from gcc import *
cwd = GetCurrentDir()
src = []
CPPPATH = []
list = os.listdir(cwd)
if rtconfig.PLATFORM in ['iccarm']:
print("\nThe current project does not support IAR build\n")
Return('group')
elif rtconfig.PLATFORM in GetGCCLikePLATFORM():
if GetOption('target') != 'mdk5':
CPPPATH = [cwd]
src = Glob('./src/*.c')
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
group = group + SConscript(os.path.join(d, 'SConscript'))
Return('group')

55
bsp/renesas/ra8m1-ek/SConstruct Normal file
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@ -0,0 +1,55 @@
import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
try:
from building import *
except:
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
print(RTT_ROOT)
exit(-1)
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
if rtconfig.PLATFORM in ['iccarm']:
env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
env.Replace(ARFLAGS = [''])
env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map')
Export('RTT_ROOT')
Export('rtconfig')
SDK_ROOT = os.path.abspath('./')
if os.path.exists(SDK_ROOT + '/libraries'):
libraries_path_prefix = SDK_ROOT + '/libraries'
else:
libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
SDK_LIB = libraries_path_prefix
Export('SDK_LIB')
rtconfig.BSP_LIBRARY_TYPE = None
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
# include drivers
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript')))
# make a building
DoBuilding(TARGET, objs)

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menu "Hardware Drivers Config"
config SOC_R7FA8M1AH
bool
select SOC_SERIES_R7FA8M85
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
default y
menu "Onboard Peripheral Drivers"
endmenu
menu "On-chip Peripheral Drivers"
source "../libraries/HAL_Drivers/Kconfig"
menuconfig BSP_USING_UART
bool "Enable UART"
default y
select RT_USING_SERIAL
select RT_USING_SERIAL_V2
if BSP_USING_UART
menuconfig BSP_USING_UART3
bool "Enable UART3"
default n
if BSP_USING_UART3
config BSP_UART3_RX_USING_DMA
bool "Enable UART3 RX DMA"
depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA
default n
config BSP_UART3_TX_USING_DMA
bool "Enable UART3 TX DMA"
depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA
default n
config BSP_UART3_RX_BUFSIZE
int "Set UART3 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_UART3_TX_BUFSIZE
int "Set UART3 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
menuconfig BSP_USING_UART9
bool "Enable UART9"
default n
if BSP_USING_UART9
config BSP_UART9_RX_USING_DMA
bool "Enable UART9 RX DMA"
depends on BSP_USING_UART9 && RT_SERIAL_USING_DMA
default n
config BSP_UART9_TX_USING_DMA
bool "Enable UART9 TX DMA"
depends on BSP_USING_UART9 && RT_SERIAL_USING_DMA
default n
config BSP_UART9_RX_BUFSIZE
int "Set UART9 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_UART9_TX_BUFSIZE
int "Set UART9 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
endif
menuconfig BSP_USING_SCI_SPI
bool "Enable SCI SPI BUS"
default n
select RT_USING_SPI
if BSP_USING_SCI_SPI
config BSP_USING_SCI_SPI0
bool "Enable SCI SPI0 BUS"
default n
config BSP_USING_SCI_SPI1
bool "Enable SCI SPI1 BUS"
default n
config BSP_USING_SCI_SPI2
bool "Enable SCI SPI2 BUS"
default n
config BSP_USING_SCI_SPI3
bool "Enable SCI SPI3 BUS"
default n
config BSP_USING_SCI_SPI6
bool "Enable SCI SPI6 BUS"
default n
endif
menuconfig BSP_USING_SCI
bool "Enable SCI Controller"
default n
config BSP_USING_SCIn_SPI
bool
default n
depends on BSP_USING_SCI
select RT_USING_SPI
config BSP_USING_SCIn_I2C
bool
default n
depends on BSP_USING_SCI
select RT_USING_I2C
config BSP_USING_SCIn_UART
bool
default n
depends on BSP_USING_SCI
select RT_USING_SERIAL
select RT_USING_SERIAL_V2
if BSP_USING_SCI
config BSP_USING_SCI0
bool "Enable SCI0"
default n
if BSP_USING_SCI0
choice
prompt "choice sci mode"
default BSP_USING_SCI0_SPI
config BSP_USING_SCI0_SPI
select BSP_USING_SCIn_SPI
bool "SPI mode"
config BSP_USING_SCI0_I2C
select BSP_USING_SCIn_I2C
bool "I2C mode"
config BSP_USING_SCI0_UART
select BSP_USING_SCIn_UART
bool "UART mode"
endchoice
if BSP_USING_SCI0_UART
config BSP_SCI0_UART_RX_BUFSIZE
int "Set UART0 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_SCI0_UART_TX_BUFSIZE
int "Set UART0 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
endif
config BSP_USING_SCI1
bool "Enable SCI1"
default n
if BSP_USING_SCI1
choice
prompt "choice sci mode"
default BSP_USING_SCI1_SPI
config BSP_USING_SCI1_SPI
select BSP_USING_SCIn_SPI
bool "SPI mode"
config BSP_USING_SCI1_I2C
select BSP_USING_SCIn_I2C
bool "I2C mode"
config BSP_USING_SCI1_UART
select BSP_USING_SCIn_UART
bool "UART mode"
endchoice
if BSP_USING_SCI1_UART
config BSP_SCI1_UART_RX_BUFSIZE
int "Set UART1 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_SCI1_UART_TX_BUFSIZE
int "Set UART1 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
endif
config BSP_USING_SCI2
bool "Enable SCI2"
default n
if BSP_USING_SCI2
choice
prompt "choice sci mode"
default BSP_USING_SCI2_SPI
config BSP_USING_SCI2_SPI
select BSP_USING_SCIn_SPI
bool "SPI mode"
config BSP_USING_SCI2_I2C
select BSP_USING_SCIn_I2C
bool "I2C mode"
config BSP_USING_SCI2_UART
select BSP_USING_SCIn_UART
bool "UART mode"
endchoice
if BSP_USING_SCI2_UART
config BSP_SCI2_UART_RX_BUFSIZE
int "Set UART2 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_SCI2_UART_TX_BUFSIZE
int "Set UART2 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
endif
config BSP_USING_SCI3
bool "Enable SCI3"
default n
if BSP_USING_SCI3
choice
prompt "choice sci mode"
default BSP_USING_SCI3_SPI
config BSP_USING_SCI3_SPI
select BSP_USING_SCIn_SPI
bool "SPI mode"
config BSP_USING_SCI3_I2C
select BSP_USING_SCIn_I2C
bool "I2C mode"
config BSP_USING_SCI3_UART
select BSP_USING_SCIn_UART
bool "UART mode"
endchoice
if BSP_USING_SCI3_UART
config BSP_SCI3_UART_RX_BUFSIZE
int "Set UART3 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_SCI3_UART_TX_BUFSIZE
int "Set UART3 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
endif
config BSP_USING_SCI4
bool "Enable SCI4"
default n
if BSP_USING_SCI4
choice
prompt "choice sci mode"
default BSP_USING_SCI4_SPI
config BSP_USING_SCI4_SPI
select BSP_USING_SCIn_SPI
bool "SPI mode"
config BSP_USING_SCI4_I2C
select BSP_USING_SCIn_I2C
bool "I2C mode"
config BSP_USING_SCI4_UART
select BSP_USING_SCIn_UART
bool "UART mode"
endchoice
if BSP_USING_SCI4_UART
config BSP_SCI4_UART_RX_BUFSIZE
int "Set UART4 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_SCI4_UART_TX_BUFSIZE
int "Set UART4 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
endif
config BSP_USING_SCI5
bool "Enable SCI5"
default n
if BSP_USING_SCI5
choice
prompt "choice sci mode"
default BSP_USING_SCI5_SPI
config BSP_USING_SCI5_SPI
select BSP_USING_SCIn_SPI
bool "SPI mode"
config BSP_USING_SCI5_I2C
select BSP_USING_SCIn_I2C
bool "I2C mode"
config BSP_USING_SCI5_UART
select BSP_USING_SCIn_UART
bool "UART mode"
endchoice
if BSP_USING_SCI5_UART
config BSP_SCI5_UART_RX_BUFSIZE
int "Set UART5 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_SCI5_UART_TX_BUFSIZE
int "Set UART5 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
endif
config BSP_USING_SCI6
bool "Enable SCI6"
default n
if BSP_USING_SCI6
choice
prompt "choice sci mode"
default BSP_USING_SCI6_SPI
config BSP_USING_SCI6_SPI
select BSP_USING_SCIn_SPI
bool "SPI mode"
config BSP_USING_SCI6_I2C
select BSP_USING_SCIn_I2C
bool "I2C mode"
config BSP_USING_SCI6_UART
select BSP_USING_SCIn_UART
bool "UART mode"
endchoice
if BSP_USING_SCI6_UART
config BSP_SCI6_UART_RX_BUFSIZE
int "Set UART6 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_SCI6_UART_TX_BUFSIZE
int "Set UART6 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
endif
config BSP_USING_SCI7
bool "Enable SCI7"
default n
if BSP_USING_SCI7
choice
prompt "choice sci mode"
default BSP_USING_SCI7_SPI
config BSP_USING_SCI7_SPI
select BSP_USING_SCIn_SPI
bool "SPI mode"
config BSP_USING_SCI7_I2C
select BSP_USING_SCIn_I2C
bool "I2C mode"
config BSP_USING_SCI7_UART
select BSP_USING_SCIn_UART
bool "UART mode"
endchoice
if BSP_USING_SCI7_UART
config BSP_SCI7_UART_RX_BUFSIZE
int "Set UART7 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_SCI7_UART_TX_BUFSIZE
int "Set UART7 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
endif
config BSP_USING_SCI8
bool "Enable SCI8"
default n
if BSP_USING_SCI8
choice
prompt "choice sci mode"
default BSP_USING_SCI8_SPI
config BSP_USING_SCI8_SPI
select BSP_USING_SCIn_SPI
bool "SPI mode"
config BSP_USING_SCI8_I2C
select BSP_USING_SCIn_I2C
bool "I2C mode"
config BSP_USING_SCI8_UART
select BSP_USING_SCIn_UART
bool "UART mode"
endchoice
if BSP_USING_SCI8_UART
config BSP_SCI8_UART_RX_BUFSIZE
int "Set UART8 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_SCI8_UART_TX_BUFSIZE
int "Set UART8 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
endif
config BSP_USING_SCI9
bool "Enable SCI9"
default n
if BSP_USING_SCI9
choice
prompt "choice sci mode"
default BSP_USING_SCI9_SPI
config BSP_USING_SCI9_SPI
select BSP_USING_SCIn_SPI
bool "SPI mode"
config BSP_USING_SCI9_I2C
select BSP_USING_SCIn_I2C
bool "I2C mode"
config BSP_USING_SCI9_UART
select BSP_USING_SCIn_UART
bool "UART mode"
endchoice
if BSP_USING_SCI9_UART
config BSP_SCI9_UART_RX_BUFSIZE
int "Set UART9 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_SCI9_UART_TX_BUFSIZE
int "Set UART9 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
endif
endif
menuconfig BSP_USING_SPI
bool "Enable SPI BUS"
default n
select RT_USING_SPI
if BSP_USING_SPI
config BSP_USING_SPI0
bool "Enable SPI0 BUS"
default n
config BSP_USING_SPI1
bool "Enable SPI1 BUS"
default n
endif
menuconfig BSP_USING_I2C
bool "Enable I2C BUS"
default n
select RT_USING_I2C
select RT_USING_I2C_BITOPS
select RT_USING_PIN
if BSP_USING_I2C
config BSP_USING_HW_I2C
bool "Enable Hardware I2C BUS"
default n
if BSP_USING_HW_I2C
config BSP_USING_HW_I2C1
bool "Enable Hardware I2C1 BUS"
default n
endif
endif
menuconfig BSP_USING_FS
bool "Enable filesystem"
default n
if BSP_USING_FS
config BSP_USING_SPICARD_FS
bool "Enable SPI FLASH filesystem"
select BSP_USING_SPI
select BSP_USING_SCI_SPI6
select RT_USING_SPI_MSD
select RT_USING_DFS_ELMFAT
default n
endif
menuconfig BSP_USING_PWM
bool "Enable PWM"
default n
select RT_USING_PWM
if BSP_USING_PWM
config BSP_USING_PWM12
bool "Enable GPT12 (16-Bits) output PWM"
default n
endif
endmenu
endmenu

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import os
from building import *
objs = []
cwd = GetCurrentDir()
list = os.listdir(cwd)
CPPPATH = [cwd]
src = Glob('*.c')
if GetDepend(['BSP_USING_FS']):
src += Glob('ports/mnt.c')
objs = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
for item in list:
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
objs = objs + SConscript(os.path.join(item, 'SConscript'))
Return('objs')

38
bsp/renesas/ra8m1-ek/board/board.h Normal file
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-10-10 Sherman first version
*/
#ifndef __BOARD_H__
#define __BOARD_H__
#ifdef __cplusplus
extern "C" {
#endif
#define RA_SRAM_SIZE 896 /* The SRAM size of the chip needs to be modified */
#define RA_SRAM_END (0x22000000 + RA_SRAM_SIZE * 1024)
#ifdef __ARMCC_VERSION
extern int Image$$RAM_END$$ZI$$Base;
#define HEAP_BEGIN ((void *)&Image$$RAM_END$$ZI$$Base)
#elif __ICCARM__
#pragma section="CSTACK"
#define HEAP_BEGIN (__segment_end("CSTACK"))
#else
extern int __RAM_segment_used_end__;
#define HEAP_BEGIN (&__RAM_segment_used_end__)
#endif
#define HEAP_END RA_SRAM_END
#ifdef __cplusplus
}
#endif
#endif

16
bsp/renesas/ra8m1-ek/board/lvgl/SConscript Normal file
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from building import *
import os
cwd = GetCurrentDir()
group = []
src = Glob('*.c')
CPPPATH = [cwd]
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
group = group + SConscript(os.path.join(d, 'SConscript'))
group = group + DefineGroup('LVGL-port', src, depend = ['BSP_USING_LVGL'], CPPPATH = CPPPATH)
Return('group')

17
bsp/renesas/ra8m1-ek/board/lvgl/demo/SConscript Normal file
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from building import *
import os
cwd = GetCurrentDir()
group = []
src = Glob('*.c')
CPPPATH = [cwd]
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
group = group + SConscript(os.path.join(d, 'SConscript'))
group = group + DefineGroup('LVGL-demo', src, depend = ['BSP_USING_LVGL', 'BSP_USING_LVGL_DEMO'], CPPPATH = CPPPATH)
Return('group')

18
bsp/renesas/ra8m1-ek/board/lvgl/demo/lv_demo.c Normal file
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-10-17 Meco Man First version
* 2022-05-10 Meco Man improve rt-thread initialization process
*/
#include "rtconfig.h"
void lv_user_gui_init(void)
{
/* display demo; you may replace with your LVGL application at here */
extern void lv_demo_music(void);
lv_demo_music();
}

66
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-02-22 Rbb666 First version
*/
#ifndef LV_CONF_H
#define LV_CONF_H
#include <rtconfig.h>
/* Enable additional color format support */
#define DLG_LVGL_CF 1
/* Enable sub byte color formats to be swapped. If disabled, which is recommended for
* performance, bitmaps need to be in correct order */
#define DLG_LVGL_CF_SUB_BYTE_SWAP 0
#define DLG_LVGL_USE_GPU_RA6M3 0
#define LV_USE_PERF_MONITOR 1
#define LV_COLOR_DEPTH 16
#ifdef PKG_USING_ILI9341
#define LV_HOR_RES_MAX 240
#define LV_VER_RES_MAX 320
#define LV_COLOR_16_SWAP 1
#define LV_DPI_DEF 99
#else
#define LV_HOR_RES_MAX 480
#define LV_VER_RES_MAX 272
#define LV_DPI_DEF 89
#endif
#ifdef BSP_USING_LVGL_VIDEO_DEMO
#define LV_USE_FILE_EXPLORER 1
#if LV_USE_FILE_EXPLORER
/*Maximum length of path*/
#define LV_FILE_EXPLORER_PATH_MAX_LEN (128)
/*Quick access bar, 1:use, 0:not use*/
/*Requires: lv_list*/
#define LV_FILE_EXPLORER_QUICK_ACCESS 0
#endif
#define LV_USE_FS_STDIO 1
#if LV_USE_FS_STDIO
#define LV_FS_STDIO_LETTER '/' /*Set an upper cased letter on which the drive will accessible (e.g. 'A')*/
#define LV_FS_STDIO_PATH "/" /*Set the working directory. File/directory paths will be appended to it.*/
#define LV_FS_STDIO_CACHE_SIZE 0 /*>0 to cache this number of bytes in lv_fs_read()*/
#endif
#endif
#ifdef PKG_USING_LV_MUSIC_DEMO
/* music player demo */
#define LV_USE_DEMO_RTT_MUSIC 1
#define LV_DEMO_RTT_MUSIC_AUTO_PLAY 1
#define LV_FONT_MONTSERRAT_12 1
#define LV_FONT_MONTSERRAT_16 1
#define LV_COLOR_SCREEN_TRANSP 0
#endif /* PKG_USING_LV_MUSIC_DEMO */
#endif

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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-11-24 Rbb666 The first version
*/
#include <lvgl.h>
#include "hal_data.h"
#if DLG_LVGL_USE_GPU_RA6M3
#include "drv_g2d.h"
#endif
#ifdef PKG_USING_ILI9341
#include "lcd_ili9341.h"
#else
#include "lcd_port.h"
#endif
#define COLOR_BUFFER (LV_HOR_RES_MAX * LV_VER_RES_MAX / 4)
/*A static or global variable to store the buffers*/
static lv_disp_draw_buf_t disp_buf;
/*Descriptor of a display driver*/
static lv_disp_drv_t disp_drv;
static struct rt_device_graphic_info info;
/*Static or global buffer(s). The second buffer is optional*/
// 0x1FFE0000 0x20040000
lv_color_t buf_1[COLOR_BUFFER];
#if !DLG_LVGL_USE_GPU_RA6M3
static void color_to16_maybe(lv_color16_t *dst, lv_color_t *src)
{
#if (LV_COLOR_DEPTH == 16)
dst->full = src->full;
#else
dst->ch.blue = src->ch.blue;
dst->ch.green = src->ch.green;
dst->ch.red = src->ch.red;
#endif
}
#endif
void _ra_port_display_callback(display_callback_args_t *p_args)
{
/* TFT-Callback */
}
static void disp_flush(lv_disp_drv_t *disp_drv, const lv_area_t *area, lv_color_t *color_p)
{
#ifdef PKG_USING_ILI9341
lcd_fill_array_spi(area->x1, area->y1, area->x2, area->y2, color_p);
#elif DLG_LVGL_USE_GPU_RA6M3
lv_port_gpu_blit(area->x1, area->y1, color_p, area);
#else
int x1, x2, y1, y2;
x1 = area->x1;
x2 = area->x2;
y1 = area->y1;
y2 = area->y2;
/*Return if the area is out the screen*/
if (x2 < 0)
return;
if (y2 < 0)
return;
if (x1 > info.width - 1)
return;
if (y1 > info.height - 1)
return;
/*Truncate the area to the screen*/
int32_t act_x1 = x1 < 0 ? 0 : x1;
int32_t act_y1 = y1 < 0 ? 0 : y1;
int32_t act_x2 = x2 > info.width - 1 ? info.width - 1 : x2;
int32_t act_y2 = y2 > info.height - 1 ? info.height - 1 : y2;
uint32_t x;
uint32_t y;
long int location = 0;
/* color_p is a buffer pointer; the buffer is provided by LVGL */
lv_color16_t *fbp16 = (lv_color16_t *)info.framebuffer;
for (y = act_y1; y <= act_y2; y++)
{
for (x = act_x1; x <= act_x2; x++)
{
location = (x) + (y) * info.width;
color_to16_maybe(&fbp16[location], color_p);
color_p++;
}
color_p += x2 - act_x2;
}
#endif
lv_disp_flush_ready(disp_drv);
}
void lv_port_disp_init(void)
{
#ifdef PKG_USING_ILI9341
spi_lcd_init(20);
#else
static rt_device_t device;
/* LCD Device Init */
device = rt_device_find("lcd");
RT_ASSERT(device != RT_NULL);
if (rt_device_open(device, RT_DEVICE_OFLAG_RDWR) == RT_EOK)
{
rt_device_control(device, RTGRAPHIC_CTRL_GET_INFO, &info);
}
RT_ASSERT(info.bits_per_pixel == 8 || info.bits_per_pixel == 16 ||
info.bits_per_pixel == 24 || info.bits_per_pixel == 32);
#endif
/*Initialize `disp_buf` with the buffer(s). With only one buffer use NULL instead buf_2 */
lv_disp_draw_buf_init(&disp_buf, buf_1, NULL, COLOR_BUFFER);
lv_disp_drv_init(&disp_drv); /*Basic initialization*/
/*Set the resolution of the display*/
disp_drv.hor_res = LV_HOR_RES_MAX;
disp_drv.ver_res = LV_VER_RES_MAX;
/*Set a display buffer*/
disp_drv.draw_buf = &disp_buf;
/*Used to copy the buffer's content to the display*/
disp_drv.flush_cb = disp_flush;
#if DLG_LVGL_USE_GPU_RA6M3
/* Initialize GPU module */
G2d_Drv_HWInit();
#endif /* LV_PORT_DISP_GPU_EN */
/*Finally register the driver*/
lv_disp_drv_register(&disp_drv);
}

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bsp/renesas/ra8m1-ek/board/lvgl/lv_port_indev.c Normal file
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-03-09 Rbb666 The first version
*/
#include <lvgl.h>
#include <rtdevice.h>
#include "gt911.h"
#define DBG_TAG "lv_port_indev"
#define DBG_LVL DBG_LOG
#include <rtdbg.h>
#include "hal_data.h"
#define GT911_IRQ_PIN BSP_IO_PORT_00_PIN_04
#define GT911_RST_PIN BSP_IO_PORT_08_PIN_01
static rt_device_t touch_dev;
static lv_indev_t *touch_indev;
struct rt_touch_data *read_data;
volatile static rt_uint8_t touch_detect_flag = 0;
static void touchpad_read(lv_indev_drv_t *indev, lv_indev_data_t *data)
{
if (touch_detect_flag != 1)
return;
rt_device_read(touch_dev, 0, read_data, 1);
if (read_data->event == RT_TOUCH_EVENT_NONE)
return;
data->point.x = read_data->x_coordinate;
data->point.y = read_data->y_coordinate;
if (read_data->event == RT_TOUCH_EVENT_DOWN)
data->state = LV_INDEV_STATE_PR;
if (read_data->event == RT_TOUCH_EVENT_MOVE)
data->state = LV_INDEV_STATE_PR;
if (read_data->event == RT_TOUCH_EVENT_UP)
data->state = LV_INDEV_STATE_REL;
touch_detect_flag = 0;
rt_device_control(touch_dev, RT_TOUCH_CTRL_ENABLE_INT, RT_NULL);
}
static rt_err_t rx_callback(rt_device_t dev, rt_size_t size)
{
touch_detect_flag = 1;
rt_device_control(dev, RT_TOUCH_CTRL_DISABLE_INT, RT_NULL);
return 0;
}
rt_err_t gt911_probe(rt_uint16_t x, rt_uint16_t y)
{
void *id;
touch_dev = rt_device_find("gt911");
if (touch_dev == RT_NULL)
{
rt_kprintf("can't find device gt911\n");
return -1;
}
if (rt_device_open(touch_dev, RT_DEVICE_FLAG_INT_RX) != RT_EOK)
{
rt_kprintf("open device failed!");
return -1;
}
id = rt_malloc(sizeof(rt_uint8_t) * 8);
rt_device_control(touch_dev, RT_TOUCH_CTRL_GET_ID, id);
rt_uint8_t *read_id = (rt_uint8_t *)id;
rt_kprintf("id = GT%d%d%d \n", read_id[0] - '0', read_id[1] - '0', read_id[2] - '0');
rt_device_control(touch_dev, RT_TOUCH_CTRL_SET_X_RANGE, &x); /* if possible you can set your x y coordinate*/
rt_device_control(touch_dev, RT_TOUCH_CTRL_SET_Y_RANGE, &y);
rt_device_control(touch_dev, RT_TOUCH_CTRL_GET_INFO, id);
rt_kprintf("range_x = %d \n", (*(struct rt_touch_info *)id).range_x);
rt_kprintf("range_y = %d \n", (*(struct rt_touch_info *)id).range_y);
rt_kprintf("point_num = %d \n", (*(struct rt_touch_info *)id).point_num);
rt_free(id);
rt_device_set_rx_indicate(touch_dev, rx_callback);
read_data = (struct rt_touch_data *)rt_calloc(1, sizeof(struct rt_touch_data));
if (!read_data)
{
return -RT_ENOMEM;
}
return RT_EOK;
}
#define RST_PIN "p801"
#define INT_PIN "p004"
rt_err_t rt_hw_gt911_register(void)
{
struct rt_touch_config cfg;
rt_base_t int_pin = rt_pin_get(INT_PIN);
rt_base_t rst_pin = rt_pin_get(RST_PIN);
cfg.dev_name = "i2c1";
cfg.irq_pin.pin = int_pin;
cfg.irq_pin.mode = PIN_MODE_INPUT_PULLDOWN;
cfg.user_data = &rst_pin;
rt_hw_gt911_init("gt911", &cfg);
gt911_probe(480, 272);
return RT_EOK;
}
void lv_port_indev_init(void)
{
static lv_indev_drv_t indev_drv; /* Descriptor of a input device driver */
lv_indev_drv_init(&indev_drv); /* Basic initialization */
indev_drv.type = LV_INDEV_TYPE_POINTER; /* Touch pad is a pointer-like device */
indev_drv.read_cb = touchpad_read; /* Set your driver function */
/* Register the driver in LVGL and save the created input device object */
touch_indev = lv_indev_drv_register(&indev_drv);
/* Register touch device */
rt_err_t res = rt_hw_gt911_register();
RT_ASSERT(res == RT_EOK);
}

16
bsp/renesas/ra8m1-ek/board/ports/SConscript Normal file
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import os
from building import *
src = []
objs = []
cwd = GetCurrentDir()
CPPPATH = [cwd]
objs = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
list = os.listdir(cwd)
for item in list:
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
objs = objs + SConscript(os.path.join(item, 'SConscript'))
Return('objs')

82
bsp/renesas/ra8m1-ek/board/ports/gpio_cfg.h Normal file
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-01-19 Sherman first version
*/
/* Number of IRQ channels on the device */
#define RA_IRQ_MAX 16
/* PIN to IRQx table */
#define PIN2IRQX_TABLE(pin) \
{ \
switch (pin) \
{ \
case BSP_IO_PORT_04_PIN_00: \
case BSP_IO_PORT_02_PIN_06: \
case BSP_IO_PORT_01_PIN_05: \
return 0; \
case BSP_IO_PORT_02_PIN_05: \
case BSP_IO_PORT_01_PIN_01: \
case BSP_IO_PORT_01_PIN_04: \
return 1; \
case BSP_IO_PORT_02_PIN_03: \
case BSP_IO_PORT_01_PIN_00: \
case BSP_IO_PORT_02_PIN_13: \
return 2; \
case BSP_IO_PORT_02_PIN_02: \
case BSP_IO_PORT_01_PIN_10: \
case BSP_IO_PORT_02_PIN_12: \
return 3; \
case BSP_IO_PORT_04_PIN_02: \
case BSP_IO_PORT_01_PIN_11: \
case BSP_IO_PORT_04_PIN_11: \
return 4; \
case BSP_IO_PORT_04_PIN_01: \
case BSP_IO_PORT_03_PIN_02: \
case BSP_IO_PORT_04_PIN_10: \
return 5; \
case BSP_IO_PORT_03_PIN_01: \
case BSP_IO_PORT_00_PIN_00: \
case BSP_IO_PORT_04_PIN_09: \
return 6; \
case BSP_IO_PORT_00_PIN_01: \
case BSP_IO_PORT_04_PIN_08: \
return 7; \
case BSP_IO_PORT_00_PIN_02: \
case BSP_IO_PORT_03_PIN_05: \
case BSP_IO_PORT_04_PIN_15: \
return 8; \
case BSP_IO_PORT_00_PIN_04: \
case BSP_IO_PORT_03_PIN_04: \
case BSP_IO_PORT_04_PIN_14: \
return 9; \
case BSP_IO_PORT_00_PIN_05: \
case BSP_IO_PORT_07_PIN_09: \
return 10; \
case BSP_IO_PORT_05_PIN_01: \
case BSP_IO_PORT_00_PIN_06: \
case BSP_IO_PORT_07_PIN_08: \
return 11; \
case BSP_IO_PORT_05_PIN_02: \
case BSP_IO_PORT_00_PIN_08: \
return 12; \
case BSP_IO_PORT_00_PIN_15: \
case BSP_IO_PORT_00_PIN_09: \
return 13; \
case BSP_IO_PORT_04_PIN_03: \
case BSP_IO_PORT_05_PIN_12: \
case BSP_IO_PORT_05_PIN_05: \
return 14; \
case BSP_IO_PORT_04_PIN_04: \
case BSP_IO_PORT_05_PIN_11: \
case BSP_IO_PORT_05_PIN_06: \
return 15; \
default : \
return -1; \
} \
}

130
bsp/renesas/ra8m1-ek/board/ports/mnt.c Normal file
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#include <rtthread.h>
#include "hal_data.h"
#ifdef BSP_USING_FS
#include <dfs_fs.h>
#define DBG_TAG "app.filesystem"
#define DBG_LVL DBG_INFO
#include <rtdbg.h>
#ifdef BSP_USING_SDCARD_FS
#include <drv_sdhi.h>
/* SD Card hot plug detection pin */
#define SD_CHECK_PIN "p405"
static rt_base_t sd_check_pin = 0;
static void _sdcard_mount(void)
{
rt_device_t device;
device = rt_device_find("sd");
rt_kprintf("rt_device_find %x \r\n", device);
if (device == NULL)
{
mmcsd_wait_cd_changed(0);
sdcard_change();
mmcsd_wait_cd_changed(RT_WAITING_FOREVER);
device = rt_device_find("sd");
}
if (device != RT_NULL)
{
if (dfs_mount("sd", "/", "elm", 0, 0) == RT_EOK)
{
LOG_I("sd card mount to '/'");
}
else
{
LOG_W("sd card mount to '/' failed!");
}
}
}
static void _sdcard_unmount(void)
{
rt_thread_mdelay(200);
dfs_unmount("/sdcard");
LOG_I("Unmount \"/sdcard\"");
mmcsd_wait_cd_changed(0);
sdcard_change();
mmcsd_wait_cd_changed(RT_WAITING_FOREVER);
}
static void sd_auto_mount(void *parameter)
{
rt_uint8_t re_sd_check_pin = 1;
rt_thread_mdelay(20);
if (!rt_pin_read(sd_check_pin))
{
_sdcard_mount();
}
while (1)
{
rt_thread_mdelay(200);
if (re_sd_check_pin && (re_sd_check_pin = rt_pin_read(sd_check_pin)) == 0)
{
_sdcard_mount();
}
if (!re_sd_check_pin && (re_sd_check_pin = rt_pin_read(sd_check_pin)) != 0)
{
_sdcard_unmount();
}
}
}
static void sd_mount(void)
{
rt_thread_t tid;
sd_check_pin = rt_pin_get(SD_CHECK_PIN);
rt_pin_mode(sd_check_pin, PIN_MODE_INPUT_PULLUP);
tid = rt_thread_create("sd_mount", sd_auto_mount, RT_NULL,
2048, RT_THREAD_PRIORITY_MAX - 2, 20);
if (tid != RT_NULL)
{
rt_thread_startup(tid);
}
else
{
LOG_E("create sd_mount thread err!");
return;
}
}
#else
#include <spi_msd.h>
#include "drv_sci_spi.h"
int sd_mount(void)
{
uint32_t cs_pin = BSP_IO_PORT_06_PIN_11;
rt_hw_sci_spi_device_attach("scpi7", "scpi70", cs_pin);
msd_init("sd0", "scpi70");
if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
{
LOG_I("Mount \"/dev/sd0\" on \"/\"\n");
}
else
{
LOG_W("sd card mount to '/' failed!");
}
return 0;
}
#endif /* BSP_USING_SDCARD_FS */
int mount_init(void)
{
sd_mount();
return RT_EOK;
}
INIT_ENV_EXPORT(mount_init);
#endif

20
bsp/renesas/ra8m1-ek/board/ra8_it.c Normal file
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#include <rtthread.h>
#include "hal_data.h"
#ifdef BSP_USING_SCI_SPI
rt_weak void sci_spi3_callback(spi_callback_args_t *p_args)
{
}
rt_weak void sci_spi4_callback(spi_callback_args_t *p_args)
{
}
rt_weak void sci_spi6_callback(spi_callback_args_t *p_args)
{
}
rt_weak void sci_spi7_callback(spi_callback_args_t *p_args)
{
}
#endif

161
bsp/renesas/ra8m1-ek/buildinfo.gpdsc Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<package xmlns:xs="http://www.w3.org/2001/XMLSchema-instance">
<vendor>Renesas</vendor>
<name>Project Content</name>
<description>Project content managed by the Renesas Smart Configurator</description>
<url/>
<releases>
<release version="1.0.0"/>
</releases>
<generators>
<generator id="Renesas RA Smart Configurator">
<project_files>
<file category="include" name="src/"/>
<file category="source" name="src/hal_entry.c"/>
</project_files>
</generator>
</generators>
<components generator="Renesas RA Smart Configurator">
<component Cclass="Flex Software" Cgroup="Components" Csub="ra">
<files>
<file category="include" name="ra/arm/CMSIS_5/CMSIS/Core/Include/"/>
<file category="include" name="ra/fsp/inc/"/>
<file category="include" name="ra/fsp/inc/api/"/>
<file category="include" name="ra/fsp/inc/instances/"/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm85.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_starmc1.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/pac_armv81.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h" path=""/>
<file category="other" name="ra/arm/CMSIS_5/LICENSE.txt"/>
<file category="header" name="ra/board/ra8m1_ek/board.h" path=""/>
<file category="header" name="ra/board/ra8m1_ek/board_ethernet_phy.h" path=""/>
<file category="source" name="ra/board/ra8m1_ek/board_init.c"/>
<file category="header" name="ra/board/ra8m1_ek/board_init.h" path=""/>
<file category="source" name="ra/board/ra8m1_ek/board_leds.c"/>
<file category="header" name="ra/board/ra8m1_ek/board_leds.h" path=""/>
<file category="header" name="ra/fsp/inc/api/bsp_api.h" path=""/>
<file category="header" name="ra/fsp/inc/api/fsp_common_api.h" path=""/>
<file category="header" name="ra/fsp/inc/api/r_ioport_api.h" path=""/>
<file category="header" name="ra/fsp/inc/api/r_transfer_api.h" path=""/>
<file category="header" name="ra/fsp/inc/api/r_uart_api.h" path=""/>
<file category="header" name="ra/fsp/inc/fsp_features.h" path=""/>
<file category="header" name="ra/fsp/inc/fsp_version.h" path=""/>
<file category="header" name="ra/fsp/inc/instances/r_ioport.h" path=""/>
<file category="header" name="ra/fsp/inc/instances/r_sci_b_uart.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA8M1AH.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c"/>
<file category="other" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.o"/>
<file category="source" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_clocks.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_clocks.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_clocks.o"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_common.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_common.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_common.o"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_delay.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_delay.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_delay.o"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_exceptions.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_group_irq.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_group_irq.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_group_irq.o"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_guard.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_guard.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_guard.o"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_io.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_io.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_io.o"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_irq.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_irq.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_irq.o"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_module_stop.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_register_protection.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_register_protection.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_register_protection.o"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c"/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_rom_registers.o"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_sbrk.c"/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_sbrk.o"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_security.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_security.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_security.o"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_tfu.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/mcu/ra8m1/bsp_elc.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/mcu/ra8m1/bsp_feature.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/mcu/ra8m1/bsp_mcu_info.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/mcu/ra8m1/bsp_override.h" path=""/>
<file category="source" name="ra/fsp/src/r_ioport/r_ioport.c"/>
<file category="other" name="ra/fsp/src/r_ioport/r_ioport.o"/>
<file category="source" name="ra/fsp/src/r_sci_b_uart/r_sci_b_uart.c"/>
<file category="other" name="ra/fsp/src/r_sci_b_uart/r_sci_b_uart.o"/>
<file category="other" name="ra/SConscript"/>
</files>
</component>
<component Cclass="Flex Software" Cgroup="Build Configuration">
<files>
<file category="include" name="ra_cfg/fsp_cfg/"/>
<file category="include" name="ra_cfg/fsp_cfg/bsp/"/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/board_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/r_ioport_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/r_sci_b_uart_cfg.h" path=""/>
<file category="other" name="ra_cfg/SConscript"/>
</files>
</component>
<component Cclass="Flex Software" Cgroup="Generated Data">
<files>
<file category="include" name="ra_gen/"/>
<file category="header" name="ra_gen/bsp_clock_cfg.h" path=""/>
<file category="source" name="ra_gen/common_data.c"/>
<file category="header" name="ra_gen/common_data.h" path=""/>
<file category="source" name="ra_gen/hal_data.c"/>
<file category="header" name="ra_gen/hal_data.h" path=""/>
<file category="source" name="ra_gen/main.c"/>
<file category="source" name="ra_gen/pin_data.c"/>
<file category="other" name="ra_gen/SConscript"/>
<file category="source" name="ra_gen/vector_data.c"/>
<file category="header" name="ra_gen/vector_data.h" path=""/>
</files>
</component>
<component Cclass="Flex Software" Cgroup="Linker Script">
<files>
<file category="linkerScript" name="script/fsp.scat"/>
<file category="other" name="script/ac6/fsp_keep.via"/>
</files>
</component>
</components>
</package>

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bsp/renesas/ra8m1-ek/configuration.xml Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<raConfiguration version="8">
<generalSettings>
<option key="#Board#" value="board.ra8m1ek"/>
<option key="CPU" value="RA8M1"/>
<option key="Core" value="CM85"/>
<option key="#TargetName#" value="R7FA8M1AHECBD"/>
<option key="#TargetARCHITECTURE#" value="cortex-m85"/>
<option key="#DeviceCommand#" value="R7FA8M1AH"/>
<option key="#RTOS#" value="_none"/>
<option key="#pinconfiguration#" value="R7FA8M1AHECBD.pincfg"/>
<option key="#FSPVersion#" value="5.0.0"/>
<option key="#ConfigurationFragments#" value="Renesas##BSP##Board##ra8m1_ek##"/>
<option key="#SELECTED_TOOLCHAIN#" value="com.arm.toolchain"/>
</generalSettings>
<raBspConfiguration>
<config id="config.bsp.ra8m1.R7FA8M1AHECBD">
<property id="config.bsp.part_number" value="config.bsp.part_number.value"/>
<property id="config.bsp.rom_size_bytes" value="config.bsp.rom_size_bytes.value"/>
<property id="config.bsp.rom_size_bytes_hidden" value="2064384"/>
<property id="config.bsp.ram_size_bytes" value="config.bsp.ram_size_bytes.value"/>
<property id="config.bsp.data_flash_size_bytes" value="config.bsp.data_flash_size_bytes.value"/>
<property id="config.bsp.package_style" value="config.bsp.package_style.value"/>
<property id="config.bsp.package_pins" value="config.bsp.package_pins.value"/>
<property id="config.bsp.irq_count_hidden" value="96"/>
</config>
<config id="config.bsp.ra8m1">
<property id="config.bsp.series" value="config.bsp.series.value"/>
</config>
<config id="config.bsp.ra8m1.fsp">
<property id="config.bsp.fsp.tz.exception_response" value="config.bsp.fsp.tz.exception_response.nmi"/>
<property id="config.bsp.fsp.tz.cmsis.bfhfnmins" value="config.bsp.fsp.tz.cmsis.bfhfnmins.secure"/>
<property id="config.bsp.fsp.tz.cmsis.sysresetreqs" value="config.bsp.fsp.tz.cmsis.sysresetreqs.secure_only"/>
<property id="config.bsp.fsp.tz.cmsis.s_priority_boost" value="config.bsp.fsp.tz.cmsis.s_priority_boost.disabled"/>
<property id="config.bsp.fsp.tz.rstsar" value="config.bsp.fsp.tz.rstsar.both"/>
<property id="config.bsp.fsp.tz.bbfsar" value="config.bsp.fsp.tz.bbfsar.both"/>
<property id="config.bsp.fsp.tz.sramsar.sramsa0" value="config.bsp.fsp.tz.sramsar.sramsa0.both"/>
<property id="config.bsp.fsp.tz.sramsar.sramsa1" value="config.bsp.fsp.tz.sramsar.sramsa1.both"/>
<property id="config.bsp.fsp.tz.sramsar.stbramsa" value="config.bsp.fsp.tz.sramsar.stbramsa.both"/>
<property id="config.bsp.fsp.tz.bussara" value="config.bsp.fsp.tz.bussara.both"/>
<property id="config.bsp.fsp.tz.bussarb" value="config.bsp.fsp.tz.bussarb.both"/>
<property id="config.bsp.fsp.tz.bussarc" value="config.bsp.fsp.tz.bussarc.both"/>
<property id="config.bsp.fsp.tz.banksel_sel" value="config.bsp.fsp.tz.banksel_sel.both"/>
<property id="config.bsp.fsp.tz.uninitialized_ns_application_fallback" value="config.bsp.fsp.tz.uninitialized_ns_application_fallback.enabled"/>
<property id="config.bsp.fsp.OFS0.iwdt_start_mode" value="config.bsp.fsp.OFS0.iwdt_start_mode.disabled"/>
<property id="config.bsp.fsp.OFS0.iwdt_timeout" value="config.bsp.fsp.OFS0.iwdt_timeout.2048"/>
<property id="config.bsp.fsp.OFS0.iwdt_divisor" value="config.bsp.fsp.OFS0.iwdt_divisor.128"/>
<property id="config.bsp.fsp.OFS0.iwdt_window_end" value="config.bsp.fsp.OFS0.iwdt_window_end.0"/>
<property id="config.bsp.fsp.OFS0.iwdt_window_start" value="config.bsp.fsp.OFS0.iwdt_window_start.100"/>
<property id="config.bsp.fsp.OFS0.iwdt_reset_interrupt" value="config.bsp.fsp.OFS0.iwdt_reset_interrupt.Reset"/>
<property id="config.bsp.fsp.OFS0.iwdt_stop_control" value="config.bsp.fsp.OFS0.iwdt_stop_control.stops"/>
<property id="config.bsp.fsp.OFS0.wdt_start_mode" value="config.bsp.fsp.OFS0.wdt_start_mode.register"/>
<property id="config.bsp.fsp.OFS0.wdt_timeout" value="config.bsp.fsp.OFS0.wdt_timeout.16384"/>
<property id="config.bsp.fsp.OFS0.wdt_divisor" value="config.bsp.fsp.OFS0.wdt_divisor.128"/>
<property id="config.bsp.fsp.OFS0.wdt_window_end" value="config.bsp.fsp.OFS0.wdt_window_end.0"/>
<property id="config.bsp.fsp.OFS0.wdt_window_start" value="config.bsp.fsp.OFS0.wdt_window_start.100"/>
<property id="config.bsp.fsp.OFS0.wdt_reset_interrupt" value="config.bsp.fsp.OFS0.wdt_reset_interrupt.Reset"/>
<property id="config.bsp.fsp.OFS0.wdt_stop_control" value="config.bsp.fsp.OFS0.wdt_stop_control.stops"/>
<property id="config.bsp.fsp.OFS1_SEL.voltage_detection0_level" value="config.bsp.fsp.OFS1_SEL.voltage_detection0_level.secure"/>
<property id="config.bsp.fsp.OFS1_SEL.voltage_detection0.start" value="config.bsp.fsp.OFS1_SEL.voltage_detection0.start.secure"/>
<property id="config.bsp.fsp.OFS1_SEL.voltage_detection0.low_power_consumption" value="config.bsp.fsp.OFS1_SEL.voltage_detection0.low_power_consumption.secure"/>
<property id="config.bsp.fsp.OFS1_SEL.swdbg" value="config.bsp.fsp.OFS1_SEL.swdbg.secure"/>
<property id="config.bsp.fsp.OFS1_SEL.initeccen" value="config.bsp.fsp.OFS1_SEL.initeccen.secure"/>
<property id="config.bsp.fsp.OFS1.voltage_detection0.start" value="config.bsp.fsp.OFS1.voltage_detection0.start.disabled"/>
<property id="config.bsp.fsp.OFS1.voltage_detection0_level" value="config.bsp.fsp.OFS1.voltage_detection0_level.160"/>
<property id="config.bsp.fsp.OFS1.voltage_detection0.low_power_consumption" value="config.bsp.fsp.OFS1.voltage_detection0.low_power_consumption.disabled"/>
<property id="config.bsp.fsp.OFS1.hoco_osc" value="config.bsp.fsp.OFS1.hoco_osc.disabled"/>
<property id="config.bsp.fsp.OFS1.swdbg" value="config.bsp.fsp.OFS1.swdbg.disabled"/>
<property id="config.bsp.fsp.OFS1.initeccen" value="config.bsp.fsp.OFS1.initeccen.enabled"/>
<property id="config.bsp.fsp.OFS2.dcdc" value="config.bsp.fsp.OFS2.dcdc.enabled"/>
<property id="config.bsp.fsp.BPS.BPS0" value=""/>
<property id="config.bsp.fsp.BPS.BPS1" value=""/>
<property id="config.bsp.fsp.BPS.BPS2" value=""/>
<property id="config.bsp.fsp.BPS.BPS3" value=""/>
<property id="config.bsp.fsp.PBPS.PBPS0" value=""/>
<property id="config.bsp.fsp.PBPS.PBPS1" value=""/>
<property id="config.bsp.fsp.PBPS.PBPS2" value=""/>
<property id="config.bsp.fsp.PBPS.PBPS3" value=""/>
<property id="config.bsp.fsp.dual_bank" value="config.bsp.fsp.dual_bank.disabled"/>
<property id="config.bsp.fsp.FSBLCTRL0.FSBLEN" value="config.bsp.fsp.FSBLCTRL0.FSBLEN.disabled"/>
<property id="config.bsp.fsp.FSBLCTRL0.FSBLSKIPSW" value="config.bsp.fsp.FSBLCTRL0.FSBLSKIPSW.disabled"/>
<property id="config.bsp.fsp.FSBLCTRL0.FSBLSKIPDS" value="config.bsp.fsp.FSBLCTRL0.FSBLSKIPDS.disabled"/>
<property id="config.bsp.fsp.FSBLCTRL0.FSBLCLK" value="config.bsp.fsp.FSBLCTRL0.FSBLCLK.240"/>
<property id="config.bsp.fsp.FSBLCTRL1.FSBLEXMD" value="config.bsp.fsp.FSBLCTRL1.FSBLEXMD.secure_report"/>
<property id="config.bsp.fsp.FSBLCTRL2.PORTPN" value="config.bsp.fsp.FSBLCTRL2.PORTPN.15"/>
<property id="config.bsp.fsp.FSBLCTRL2.PORTGN" value="config.bsp.fsp.FSBLCTRL2.PORTGN.reserved"/>
<property id="config.bsp.fsp.SACC0" value="0xFFFFFFFF"/>
<property id="config.bsp.fsp.SACC1" value="0xFFFFFFFF"/>
<property id="config.bsp.fsp.SAMR" value="0xFFFFFFFF"/>
<property id="config.bsp.fsp.hoco_fll" value="config.bsp.fsp.hoco_fll.disabled"/>
<property id="config.bsp.fsp.clock_settling_delay" value="config.bsp.fsp.clock_settling_delay.enabled"/>
<property id="config.bsp.fsp.sleep_mode_delays" value="config.bsp.fsp.sleep_mode_delays.enabled"/>
<property id="config.bsp.fsp.rtos_sleep_delay" value="config.bsp.fsp.rtos_sleep_delay.enabled"/>
<property id="config.bsp.fsp.mstp_change_delays" value="config.bsp.fsp.mstp_change_delays.enabled"/>
<property id="config.bsp.fsp.settling_delay_us" value="150"/>
<property id="config.bsp.common.main_osc_wait" value="config.bsp.common.main_osc_wait.wait_8163"/>
<property id="config.bsp.fsp.mcu.adc.max_freq_hz" value="60000000"/>
<property id="config.bsp.fsp.mcu.sci_b_uart.max_baud" value="20000000"/>
<property id="config.bsp.fsp.mcu.sci_b_uart.ctspen_channels" value="0x021F"/>
<property id="config.bsp.fsp.mcu.adc.sample_and_hold" value="0"/>
<property id="config.bsp.fsp.mcu.sci_spi.max_bitrate" value="30000000"/>
<property id="config.bsp.fsp.mcu.spi.max_bitrate" value="60000000"/>
<property id="config.bsp.fsp.mcu.iic_master.rate.rate_fastplus" value="1"/>
<property id="config.bsp.fsp.mcu.iic_master.fastplus_channels" value="0x3"/>
<property id="config.bsp.fsp.mcu.iic_slave.rate.rate_fastplus" value="1"/>
<property id="config.bsp.fsp.mcu.iic_slave.fastplus_channels" value="0x3"/>
<property id="config.bsp.fsp.mcu.gpt.pin_count_source_channels" value="0xFF0F"/>
<property id="config.bsp.fsp.mcu.canfd.num_channels" value="2"/>
<property id="config.bsp.fsp.mcu.canfd.rx_fifos" value="2"/>
<property id="config.bsp.fsp.mcu.canfd.buffer_ram" value="1216"/>
<property id="config.bsp.fsp.mcu.canfd.afl_rules" value="32"/>
<property id="config.bsp.fsp.mcu.canfd.afl_rules_each_chnl" value="16"/>
<property id="config.bsp.fsp.mcu.canfd.max_data_rate_hz" value="8"/>
<property id="config.bsp.fsp.mcu.adc_dmac.samples_per_channel" value="32767"/>
<property id="config.bsp.fsp.dcache" value="config.bsp.fsp.dcache.disabled"/>
</config>
<config id="config.bsp.ra">
<property id="config.bsp.common.main" value="0x400"/>
<property id="config.bsp.common.heap" value="0"/>
<property id="config.bsp.common.vcc" value="3300"/>
<property id="config.bsp.common.checking" value="config.bsp.common.checking.disabled"/>
<property id="config.bsp.common.assert" value="config.bsp.common.assert.none"/>
<property id="config.bsp.common.error_log" value="config.bsp.common.error_log.none"/>
<property id="config.bsp.common.soft_reset" value="config.bsp.common.soft_reset.disabled"/>
<property id="config.bsp.common.main_osc_populated" value="config.bsp.common.main_osc_populated.enabled"/>
<property id="config.bsp.common.pfs_protect" value="config.bsp.common.pfs_protect.enabled"/>
<property id="config.bsp.common.c_runtime_init" value="config.bsp.common.c_runtime_init.enabled"/>
<property id="config.bsp.common.early_init" value="config.bsp.common.early_init.disabled"/>
<property id="config.bsp.common.main_osc_clock_source" value="config.bsp.common.main_osc_clock_source.crystal"/>
<property id="config.bsp.common.subclock_populated" value="config.bsp.common.subclock_populated.enabled"/>
<property id="config.bsp.common.subclock_drive" value="config.bsp.common.subclock_drive.standard"/>
<property id="config.bsp.common.subclock_stabilization_ms" value="1000"/>
</config>
</raBspConfiguration>
<raClockConfiguration>
<node id="board.clock.xtal.freq" mul="20000000" option="_edit"/>
<node id="board.clock.hoco.freq" option="board.clock.hoco.freq.48m"/>
<node id="board.clock.loco.freq" option="board.clock.loco.freq.32768"/>
<node id="board.clock.moco.freq" option="board.clock.moco.freq.8m"/>
<node id="board.clock.subclk.freq" option="board.clock.subclk.freq.32768"/>
<node id="board.clock.pll.source" option="board.clock.pll.source.xtal"/>
<node id="board.clock.pll.div" option="board.clock.pll.div.1"/>
<node id="board.clock.pll.mul" option="board.clock.pll.mul.48_00"/>
<node id="board.clock.pll.display" option="board.clock.pll.display.value"/>
<node id="board.clock.pll1p.div" option="board.clock.pll1p.div.2"/>
<node id="board.clock.pll1p.display" option="board.clock.pll1p.display.value"/>
<node id="board.clock.pll1q.div" option="board.clock.pll1q.div.2"/>
<node id="board.clock.pll1q.display" option="board.clock.pll1q.display.value"/>
<node id="board.clock.pll1r.div" option="board.clock.pll1r.div.2"/>
<node id="board.clock.pll1r.display" option="board.clock.pll1r.display.value"/>
<node id="board.clock.pll2.source" option="board.clock.pll2.source.disabled"/>
<node id="board.clock.pll2.div" option="board.clock.pll2.div.1"/>
<node id="board.clock.pll2.mul" option="board.clock.pll2.mul.48_00"/>
<node id="board.clock.pll2.display" option="board.clock.pll2.display.value"/>
<node id="board.clock.pll2p.div" option="board.clock.pll2p.div.2"/>
<node id="board.clock.pll2p.display" option="board.clock.pll2p.display.value"/>
<node id="board.clock.pll2q.div" option="board.clock.pll2q.div.2"/>
<node id="board.clock.pll2q.display" option="board.clock.pll2q.display.value"/>
<node id="board.clock.pll2r.div" option="board.clock.pll2r.div.2"/>
<node id="board.clock.pll2r.display" option="board.clock.pll2r.display.value"/>
<node id="board.clock.clock.source" option="board.clock.clock.source.pll1p"/>
<node id="board.clock.clkout.source" option="board.clock.clkout.source.disabled"/>
<node id="board.clock.sciclk.source" option="board.clock.sciclk.source.pll1p"/>
<node id="board.clock.spiclk.source" option="board.clock.spiclk.source.disabled"/>
<node id="board.clock.canfdclk.source" option="board.clock.canfdclk.source.disabled"/>
<node id="board.clock.i3cclk.source" option="board.clock.i3cclk.source.disabled"/>
<node id="board.clock.uck.source" option="board.clock.uck.source.disabled"/>
<node id="board.clock.u60ck.source" option="board.clock.u60ck.source.disabled"/>
<node id="board.clock.octaspiclk.source" option="board.clock.octaspiclk.source.disabled"/>
<node id="board.clock.cpuclk.div" option="board.clock.cpuclk.div.1"/>
<node id="board.clock.iclk.div" option="board.clock.iclk.div.2"/>
<node id="board.clock.pclka.div" option="board.clock.pclka.div.4"/>
<node id="board.clock.pclkb.div" option="board.clock.pclkb.div.8"/>
<node id="board.clock.pclkc.div" option="board.clock.pclkc.div.8"/>
<node id="board.clock.pclkd.div" option="board.clock.pclkd.div.4"/>
<node id="board.clock.pclke.div" option="board.clock.pclke.div.2"/>
<node id="board.clock.sdclkout.enable" option="board.clock.sdclkout.enable.enabled"/>
<node id="board.clock.bclk.div" option="board.clock.bclk.div.4"/>
<node id="board.clock.bclkout.div" option="board.clock.bclkout.div.2"/>
<node id="board.clock.fclk.div" option="board.clock.fclk.div.8"/>
<node id="board.clock.clkout.div" option="board.clock.clkout.div.1"/>
<node id="board.clock.sciclk.div" option="board.clock.sciclk.div.4"/>
<node id="board.clock.spiclk.div" option="board.clock.spiclk.div.4"/>
<node id="board.clock.canfdclk.div" option="board.clock.canfdclk.div.8"/>
<node id="board.clock.i3cclk.div" option="board.clock.i3cclk.div.3"/>
<node id="board.clock.uck.div" option="board.clock.uck.div.5"/>
<node id="board.clock.u60ck.div" option="board.clock.u60ck.div.5"/>
<node id="board.clock.octaspiclk.div" option="board.clock.octaspiclk.div.4"/>
<node id="board.clock.cpuclk.display" option="board.clock.cpuclk.display.value"/>
<node id="board.clock.iclk.display" option="board.clock.iclk.display.value"/>
<node id="board.clock.pclka.display" option="board.clock.pclka.display.value"/>
<node id="board.clock.pclkb.display" option="board.clock.pclkb.display.value"/>
<node id="board.clock.pclkc.display" option="board.clock.pclkc.display.value"/>
<node id="board.clock.pclkd.display" option="board.clock.pclkd.display.value"/>
<node id="board.clock.pclke.display" option="board.clock.pclke.display.value"/>
<node id="board.clock.sdclkout.display" option="board.clock.sdclkout.display.value"/>
<node id="board.clock.bclk.display" option="board.clock.bclk.display.value"/>
<node id="board.clock.bclkout.display" option="board.clock.bclkout.display.value"/>
<node id="board.clock.fclk.display" option="board.clock.fclk.display.value"/>
<node id="board.clock.clkout.display" option="board.clock.clkout.display.value"/>
<node id="board.clock.sciclk.display" option="board.clock.sciclk.display.value"/>
<node id="board.clock.spiclk.display" option="board.clock.spiclk.display.value"/>
<node id="board.clock.canfdclk.display" option="board.clock.canfdclk.display.value"/>
<node id="board.clock.i3cclk.display" option="board.clock.i3cclk.display.value"/>
<node id="board.clock.uck.display" option="board.clock.uck.display.value"/>
<node id="board.clock.u60ck.display" option="board.clock.u60ck.display.value"/>
<node id="board.clock.octaspiclk.display" option="board.clock.octaspiclk.display.value"/>
</raClockConfiguration>
<raComponentSelection>
<component apiversion="" class="BSP" condition="" group="ra8m1" subgroup="device" variant="R7FA8M1AHECBD" vendor="Renesas" version="5.0.0">
<description>Board support package for R7FA8M1AHECBD</description>
<originalPack>Renesas.RA_mcu_ra8m1.5.0.0.pack</originalPack>
</component>
<component apiversion="" class="BSP" condition="" group="ra8m1" subgroup="device" variant="" vendor="Renesas" version="5.0.0">
<description>Board support package for RA8M1</description>
<originalPack>Renesas.RA_mcu_ra8m1.5.0.0.pack</originalPack>
</component>
<component apiversion="" class="BSP" condition="" group="ra8m1" subgroup="fsp" variant="" vendor="Renesas" version="5.0.0">
<description>Board support package for RA8M1 - FSP Data</description>
<originalPack>Renesas.RA_mcu_ra8m1.5.0.0.pack</originalPack>
</component>
<component apiversion="" class="Common" condition="" group="all" subgroup="fsp_common" variant="" vendor="Renesas" version="5.0.0">
<description>Board Support Package Common Files</description>
<originalPack>Renesas.RA.5.0.0.pack</originalPack>
</component>
<component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_ioport" variant="" vendor="Renesas" version="5.0.0">
<description>I/O Port</description>
<originalPack>Renesas.RA.5.0.0.pack</originalPack>
</component>
<component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_sci_b_uart" variant="" vendor="Renesas" version="5.0.0">
<description>SCI UART</description>
<originalPack>Renesas.RA.5.0.0.pack</originalPack>
</component>
<component apiversion="" class="CMSIS" condition="" group="CMSIS5" subgroup="CoreM" variant="" vendor="Arm" version="5.9.0+renesas.0.fsp.5.0.0">
<description>Arm CMSIS Version 5 - Core (M)</description>
<originalPack>Arm.CMSIS5.5.9.0+renesas.0.fsp.5.0.0.pack</originalPack>
</component>
<component apiversion="" class="BSP" condition="" group="Board" subgroup="ra8m1_ek" variant="" vendor="Renesas" version="5.0.0">
<description>RA8M1-EK Board Support Files</description>
<originalPack>Renesas.RA_board_ra8m1_ek.5.0.0.pack</originalPack>
</component>
</raComponentSelection>
<raElcConfiguration/>
<raIcuConfiguration/>
<raModuleConfiguration>
<module id="module.driver.ioport_on_ioport.0">
<property id="module.driver.ioport.name" value="g_ioport"/>
<property id="module.driver.ioport.elc_trigger_ioport1" value="_disabled"/>
<property id="module.driver.ioport.elc_trigger_ioport2" value="_disabled"/>
<property id="module.driver.ioport.elc_trigger_ioport3" value="_disabled"/>
<property id="module.driver.ioport.elc_trigger_ioport4" value="_disabled"/>
<property id="module.driver.ioport.pincfg" value="g_bsp_pin_cfg"/>
</module>
<module id="module.driver.uart_on_sci_b_uart.1514241209">
<property id="module.driver.uart.name" value="g_uart9"/>
<property id="module.driver.uart.channel" value="9"/>
<property id="module.driver.uart.data_bits" value="module.driver.uart.data_bits.data_bits_8"/>
<property id="module.driver.uart.parity" value="module.driver.uart.parity.parity_off"/>
<property id="module.driver.uart.stop_bits" value="module.driver.uart.stop_bits.stop_bits_1"/>
<property id="module.driver.uart.baud" value="115200"/>
<property id="module.driver.uart.baudrate_modulation" value="module.driver.uart.baudrate_modulation.disabled"/>
<property id="module.driver.uart.baudrate_max_err" value="5"/>
<property id="module.driver.uart.flow_control" value="module.driver.uart.flow_control.rts"/>
<property id="module.driver.uart.pin_control_port" value="module.driver.uart.pin_control_port.PORT_DISABLE"/>
<property id="module.driver.uart.pin_control_pin" value="module.driver.uart.pin_control_pin.PIN_DISABLE"/>
<property id="module.driver.uart.clk_src" value="module.driver.uart.clk_src.int_clk"/>
<property id="module.driver.uart.rx_edge_start" value="module.driver.uart.rx_edge_start.falling_edge"/>
<property id="module.driver.uart.noisecancel_en" value="module.driver.uart.noisecancel_en.disabled"/>
<property id="module.driver.uart.rx_fifo_trigger" value="module.driver.uart.rx_fifo_trigger.max"/>
<property id="module.driver.uart.rs485.de_enable" value="module.driver.uart.rs485.de_enable.disabled"/>
<property id="module.driver.uart.rs485.de_polarity" value="module.driver.uart.rs485.de_polarity.high"/>
<property id="module.driver.uart.rs485.de_assertion_time" value="1"/>
<property id="module.driver.uart.rs485.de_negation_time" value="1"/>
<property id="module.driver.uart.callback" value="user_uart9_callback"/>
<property id="module.driver.uart.rxi_ipl" value="board.icu.common.irq.priority12"/>
<property id="module.driver.uart.txi_ipl" value="board.icu.common.irq.priority12"/>
<property id="module.driver.uart.tei_ipl" value="board.icu.common.irq.priority12"/>
<property id="module.driver.uart.eri_ipl" value="board.icu.common.irq.priority12"/>
</module>
<context id="_hal.0">
<stack module="module.driver.ioport_on_ioport.0"/>
<stack module="module.driver.uart_on_sci_b_uart.1514241209"/>
</context>
<config id="config.driver.ioport">
<property id="config.driver.ioport.checking" value="config.driver.ioport.checking.system"/>
</config>
<config id="config.driver.sci_b_uart">
<property id="config.driver.sci_b_uart.param_checking_enable" value="config.driver.sci_b_uart.param_checking_enable.bsp"/>
<property id="config.driver.sci_b_uart.fifo_support" value="config.driver.sci_b_uart.fifo_support.enabled"/>
<property id="config.driver.sci_b_uart.dtc_support" value="config.driver.sci_b_uart.dtc_support.disabled"/>
<property id="config.driver.sci_b_uart.flow_control" value="config.driver.sci_b_uart.flow_control.disabled"/>
</config>
</raModuleConfiguration>
<raPinConfiguration>
<symbolicName propertyId="p000.symbolic_name" value="ENET_RMII_INT"/>
<symbolicName propertyId="p001.symbolic_name" value="ARDUINO_A3"/>
<symbolicName propertyId="p002.symbolic_name" value="GROVE2_AN102"/>
<symbolicName propertyId="p003.symbolic_name" value="ARDUINO_A1"/>
<symbolicName propertyId="p004.symbolic_name" value="ARDUINO_A0_MIKROBUS_AN000"/>
<symbolicName propertyId="p005.symbolic_name" value="GROVE2_AN001"/>
<symbolicName propertyId="p006.symbolic_name" value="PMOD1_IRQ11"/>
<symbolicName propertyId="p007.symbolic_name" value="ARDUINO_A004"/>
<symbolicName propertyId="p008.symbolic_name" value="USER_S2"/>
<symbolicName propertyId="p009.symbolic_name" value="USER_S1"/>
<symbolicName propertyId="p010.symbolic_name" value="MIKROBUS_IRQ14"/>
<symbolicName propertyId="p014.symbolic_name" value="ARDUINO_A4"/>
<symbolicName propertyId="p015.symbolic_name" value="ARDUINO_A5"/>
<symbolicName propertyId="p100.symbolic_name" value="OSPI_DQ0"/>
<symbolicName propertyId="p101.symbolic_name" value="OSPI_DQ3"/>
<symbolicName propertyId="p102.symbolic_name" value="OSPI_DQ4"/>
<symbolicName propertyId="p103.symbolic_name" value="OSPI_DQ2"/>
<symbolicName propertyId="p104.symbolic_name" value="OSPI_CS"/>
<symbolicName propertyId="p105.symbolic_name" value="OSPI_INT"/>
<symbolicName propertyId="p106.symbolic_name" value="OSPI_RESET"/>
<symbolicName propertyId="p107.symbolic_name" value="LED3"/>
<symbolicName propertyId="p112.symbolic_name" value="ETH_A_RMII_RMII_RXDV"/>
<symbolicName propertyId="p114.symbolic_name" value="ETH_A_LINKSTA"/>
<symbolicName propertyId="p115.symbolic_name" value="MPLX_CTRL"/>
<symbolicName propertyId="p200.symbolic_name" value="NMI"/>
<symbolicName propertyId="p201.symbolic_name" value="MD"/>
<symbolicName propertyId="p207.symbolic_name" value="CAN_STB"/>
<symbolicName propertyId="p208.symbolic_name" value="TDI"/>
<symbolicName propertyId="p209.symbolic_name" value="TDO"/>
<symbolicName propertyId="p210.symbolic_name" value="SWDIO"/>
<symbolicName propertyId="p211.symbolic_name" value="SWCLK"/>
<symbolicName propertyId="p212.symbolic_name" value="EXTAL"/>
<symbolicName propertyId="p213.symbolic_name" value="XTAL"/>
<symbolicName propertyId="p300.symbolic_name" value="ETH_A_RXER"/>
<symbolicName propertyId="p301.symbolic_name" value="ETH_A_RXD1"/>
<symbolicName propertyId="p302.symbolic_name" value="ETH_A_RXD0"/>
<symbolicName propertyId="p303.symbolic_name" value="ETH_A_REFCLK"/>
<symbolicName propertyId="p304.symbolic_name" value="ETH_A_TXD0"/>
<symbolicName propertyId="p305.symbolic_name" value="ETH_A_TXD1"/>
<symbolicName propertyId="p306.symbolic_name" value="ETH_A_TXEN"/>
<symbolicName propertyId="p307.symbolic_name" value="ETH_A_MDIO"/>
<symbolicName propertyId="p308.symbolic_name" value="ETH_A_MDC"/>
<symbolicName propertyId="p309.symbolic_name" value="ARDUINO_D0_MIKROBUS_RXD3"/>
<symbolicName propertyId="p310.symbolic_name" value="ARDUINO_D1_MIKROBUS_TXD3"/>
<symbolicName propertyId="p311.symbolic_name" value="CAN_RXD"/>
<symbolicName propertyId="p312.symbolic_name" value="CAN_TXD"/>
<symbolicName propertyId="p400.symbolic_name" value="I3C_SCL0_ARDUINO_MIKROBUS_PMOD1_3_qwiic"/>
<symbolicName propertyId="p401.symbolic_name" value="I3C_SDA0_ARDUINO_MIKROBUS_PMOD1_4_qwiic"/>
<symbolicName propertyId="p402.symbolic_name" value="ETH_B_MDIO"/>
<symbolicName propertyId="p403.symbolic_name" value="ETH_B_LINKSTA"/>
<symbolicName propertyId="p404.symbolic_name" value="ETH_B_RST_N"/>
<symbolicName propertyId="p405.symbolic_name" value="ETH_B_TXEN"/>
<symbolicName propertyId="p406.symbolic_name" value="ETH_B_TXD1"/>
<symbolicName propertyId="p407.symbolic_name" value="USBFS_VBUS"/>
<symbolicName propertyId="p408.symbolic_name" value="USBHS_VBUSEN"/>
<symbolicName propertyId="p409.symbolic_name" value="USBHS_OVRCURA"/>
<symbolicName propertyId="p410.symbolic_name" value="MISOB_B_ARDUINO_MIKROBUS"/>
<symbolicName propertyId="p411.symbolic_name" value="MOSIB_B_ARDUINO_MIKROBUS"/>
<symbolicName propertyId="p412.symbolic_name" value="RSPCKB_B_ARDUINO_MIKROBUS"/>
<symbolicName propertyId="p413.symbolic_name" value="SSLB0_B_ARDUINO_D10_MIKROBUS"/>
<symbolicName propertyId="p414.symbolic_name" value="LED2"/>
<symbolicName propertyId="p500.symbolic_name" value="USBFS_VBUS_EN"/>
<symbolicName propertyId="p501.symbolic_name" value="USBFS_OVERCURA"/>
<symbolicName propertyId="p502.symbolic_name" value="MIKROBUS_RESET"/>
<symbolicName propertyId="p508.symbolic_name" value="PMOD2_7_IRQ1"/>
<symbolicName propertyId="p511.symbolic_name" value="GROVE2_IIC_SDA1"/>
<symbolicName propertyId="p512.symbolic_name" value="GROVE2_IIC_SCL1"/>
<symbolicName propertyId="p600.symbolic_name" value="LED1"/>
<symbolicName propertyId="p601.symbolic_name" value="ARDUINO_D5"/>
<symbolicName propertyId="p602.symbolic_name" value="ARDUINO_D6"/>
<symbolicName propertyId="p603.symbolic_name" value="ARDUINO_D9"/>
<symbolicName propertyId="p609.symbolic_name" value="PMOD1_3_MISO0_RXD0_SCL0"/>
<symbolicName propertyId="p610.symbolic_name" value="PMOD1_2_MOSI0_TXD0"/>
<symbolicName propertyId="p611.symbolic_name" value="PMOD1_4_SCK0"/>
<symbolicName propertyId="p612.symbolic_name" value="PMOD1_1_SSL0_CTS_RTS"/>
<symbolicName propertyId="p613.symbolic_name" value="PMOD1_1_CTS0"/>
<symbolicName propertyId="p614.symbolic_name" value="PMOD1_9_GPIO"/>
<symbolicName propertyId="p615.symbolic_name" value="PMOD1_10_GPIO"/>
<symbolicName propertyId="p700.symbolic_name" value="ETH_B_TXD0"/>
<symbolicName propertyId="p701.symbolic_name" value="ETH_B_REFCLK"/>
<symbolicName propertyId="p702.symbolic_name" value="ETH_B_RXD0"/>
<symbolicName propertyId="p703.symbolic_name" value="ETH_B_RXD1"/>
<symbolicName propertyId="p704.symbolic_name" value="ETH_B_RXER"/>
<symbolicName propertyId="p705.symbolic_name" value="ETH_B_RMII_RXDV"/>
<symbolicName propertyId="p711.symbolic_name" value="I3C_SDA0_PULLUP"/>
<symbolicName propertyId="p800.symbolic_name" value="OSPI_DQ5"/>
<symbolicName propertyId="p801.symbolic_name" value="OSPI_DS"/>
<symbolicName propertyId="p802.symbolic_name" value="OSPI_DQ6"/>
<symbolicName propertyId="p803.symbolic_name" value="OSPI_DQ1"/>
<symbolicName propertyId="p804.symbolic_name" value="OSPI_DQ7"/>
<symbolicName propertyId="p808.symbolic_name" value="OSPI_CK"/>
<symbolicName propertyId="p809.symbolic_name" value="PMOD2_8_RESET"/>
<symbolicName propertyId="p810.symbolic_name" value="PMOD2_9_GPIO"/>
<symbolicName propertyId="p811.symbolic_name" value="PMOD2_10_GPIO"/>
<symbolicName propertyId="p812.symbolic_name" value="ARDUINO_RESET"/>
<symbolicName propertyId="p814.symbolic_name" value="USBFS_P"/>
<symbolicName propertyId="p815.symbolic_name" value="USBFS_N"/>
<symbolicName propertyId="p905.symbolic_name" value="ARDUINO_D4"/>
<symbolicName propertyId="p906.symbolic_name" value="ARDUINO_D2"/>
<symbolicName propertyId="p907.symbolic_name" value="ARDUINO_D3_MIKROBUS_GTIOC13A"/>
<symbolicName propertyId="p908.symbolic_name" value="ARDUINO_D7"/>
<symbolicName propertyId="p909.symbolic_name" value="ARDUINO_D8"/>
<symbolicName propertyId="pa02.symbolic_name" value="PMOD2_3_MISO2_RXD2"/>
<symbolicName propertyId="pa03.symbolic_name" value="PMOD2_2_MOSI2_TXD2"/>
<symbolicName propertyId="pa04.symbolic_name" value="PMOD2_4_SCK2"/>
<symbolicName propertyId="pa05.symbolic_name" value="PMOD2_1_CTS_RTS_SSL2"/>
<symbolicName propertyId="pa06.symbolic_name" value="PMOD2_1_CTS2"/>
<symbolicName propertyId="pa08.symbolic_name" value="PMOD1_8_RESET"/>
<symbolicName propertyId="pa14.symbolic_name" value="JLOB_COMS_TX"/>
<symbolicName propertyId="pa15.symbolic_name" value="JLOB_COMS_RX"/>
<symbolicName propertyId="pb00.symbolic_name" value="I3C_SCL0_PULLUP"/>
<symbolicName propertyId="pb01.symbolic_name" value="USBHS_VBUS"/>
<pincfg active="true" name="RA8M1 EK" selected="true" symbol="g_bsp_pin_cfg">
<configSetting altId="adc0.an000.p004" configurationId="adc0.an000"/>
<configSetting altId="adc0.an001.p005" configurationId="adc0.an001"/>
<configSetting altId="adc0.an004.p007" configurationId="adc0.an004"/>
<configSetting altId="adc0.an007.p014" configurationId="adc0.an007"/>
<configSetting altId="adc0.mode.custom.free" configurationId="adc0.mode"/>
<configSetting altId="adc1.an102.p002" configurationId="adc1.an102"/>
<configSetting altId="adc1.an104.p003" configurationId="adc1.an104"/>
<configSetting altId="adc1.an105.p015" configurationId="adc1.an105"/>
<configSetting altId="adc1.an106.p011" configurationId="adc1.an106"/>
<configSetting altId="adc1.mode.custom.free" configurationId="adc1.mode"/>
<configSetting altId="ether_rmii.et0_linksta.p114" configurationId="ether_rmii.et0_linksta"/>
<configSetting altId="ether_rmii.et0_mdc.p308" configurationId="ether_rmii.et0_mdc"/>
<configSetting altId="ether_rmii.et0_mdio.p307" configurationId="ether_rmii.et0_mdio"/>
<configSetting altId="ether_rmii.mode.rmii.a" configurationId="ether_rmii.mode"/>
<configSetting altId="ether_rmii.pairing.a" configurationId="ether_rmii.pairing"/>
<configSetting altId="ether_rmii.ref50ck0.p303" configurationId="ether_rmii.ref50ck0"/>
<configSetting altId="ether_rmii.rmii0_crs_dv.p112" configurationId="ether_rmii.rmii0_crs_dv"/>
<configSetting altId="ether_rmii.rmii0_rx_er.p300" configurationId="ether_rmii.rmii0_rx_er"/>
<configSetting altId="ether_rmii.rmii0_rxd0.p302" configurationId="ether_rmii.rmii0_rxd0"/>
<configSetting altId="ether_rmii.rmii0_rxd1.p301" configurationId="ether_rmii.rmii0_rxd1"/>
<configSetting altId="ether_rmii.rmii0_txd0.p304" configurationId="ether_rmii.rmii0_txd0"/>
<configSetting altId="ether_rmii.rmii0_txd1.p305" configurationId="ether_rmii.rmii0_txd1"/>
<configSetting altId="ether_rmii.rmii0_txd_en.p306" configurationId="ether_rmii.rmii0_txd_en"/>
<configSetting altId="iic1.mode.enabled.a" configurationId="iic1.mode"/>
<configSetting altId="iic1.scl1.p512" configurationId="iic1.scl1"/>
<configSetting altId="iic1.sda1.p511" configurationId="iic1.sda1"/>
<configSetting altId="irq12.irq12_dash_ds.p008" configurationId="irq12.irq12_dash_ds"/>
<configSetting altId="irq12.mode.custom.free" configurationId="irq12.mode"/>
<configSetting altId="irq13.irq13_dash_ds.p009" configurationId="irq13.irq13_dash_ds"/>
<configSetting altId="irq13.mode.custom.free" configurationId="irq13.mode"/>
<configSetting altId="irq9.mode.custom.free" configurationId="irq9.mode"/>
<configSetting altId="jtag_fslash_swd.mode.jtag.free" configurationId="jtag_fslash_swd.mode"/>
<configSetting altId="jtag_fslash_swd.tck.p211" configurationId="jtag_fslash_swd.tck"/>
<configSetting altId="jtag_fslash_swd.tdi.p208" configurationId="jtag_fslash_swd.tdi"/>
<configSetting altId="jtag_fslash_swd.tdo.p209" configurationId="jtag_fslash_swd.tdo"/>
<configSetting altId="jtag_fslash_swd.tms.p210" configurationId="jtag_fslash_swd.tms"/>
<configSetting altId="ospi.mode.custom.free" configurationId="ospi.mode"/>
<configSetting altId="ospi.om_cs1.p104" configurationId="ospi.om_cs1"/>
<configSetting altId="ospi.om_dqs.p801" configurationId="ospi.om_dqs"/>
<configSetting altId="ospi.om_ecsint1.p105" configurationId="ospi.om_ecsint1"/>
<configSetting altId="ospi.om_reset.p106" configurationId="ospi.om_reset"/>
<configSetting altId="ospi.om_sclk.p808" configurationId="ospi.om_sclk"/>
<configSetting altId="ospi.om_sio0.p100" configurationId="ospi.om_sio0"/>
<configSetting altId="ospi.om_sio1.p803" configurationId="ospi.om_sio1"/>
<configSetting altId="ospi.om_sio2.p103" configurationId="ospi.om_sio2"/>
<configSetting altId="ospi.om_sio3.p101" configurationId="ospi.om_sio3"/>
<configSetting altId="ospi.om_sio4.p102" configurationId="ospi.om_sio4"/>
<configSetting altId="ospi.om_sio5.p800" configurationId="ospi.om_sio5"/>
<configSetting altId="ospi.om_sio6.p802" configurationId="ospi.om_sio6"/>
<configSetting altId="ospi.om_sio7.p804" configurationId="ospi.om_sio7"/>
<configSetting altId="p000.input" configurationId="p000"/>
<configSetting altId="p000.gpio_mode.gpio_mode_in" configurationId="p000.gpio_mode"/>
<configSetting altId="p002.adc1.an102" configurationId="p002"/>
<configSetting altId="p002.gpio_mode.gpio_mode_an" configurationId="p002.gpio_mode"/>
<configSetting altId="p003.adc1.an104" configurationId="p003"/>
<configSetting altId="p003.gpio_mode.gpio_mode_an" configurationId="p003.gpio_mode"/>
<configSetting altId="p004.adc0.an000" configurationId="p004"/>
<configSetting altId="p004.gpio_mode.gpio_mode_an" configurationId="p004.gpio_mode"/>
<configSetting altId="p005.adc0.an001" configurationId="p005"/>
<configSetting altId="p005.gpio_mode.gpio_mode_an" configurationId="p005.gpio_mode"/>
<configSetting altId="p007.adc0.an004" configurationId="p007"/>
<configSetting altId="p007.gpio_mode.gpio_mode_an" configurationId="p007.gpio_mode"/>
<configSetting altId="p008.irq12.irq12_dash_ds" configurationId="p008"/>
<configSetting altId="p008.gpio_irq.gpio_irq_enabled" configurationId="p008.gpio_irq"/>
<configSetting altId="p008.gpio_mode.gpio_mode_irq" configurationId="p008.gpio_mode"/>
<configSetting altId="p009.irq13.irq13_dash_ds" configurationId="p009"/>
<configSetting altId="p009.gpio_irq.gpio_irq_enabled" configurationId="p009.gpio_irq"/>
<configSetting altId="p009.gpio_mode.gpio_mode_irq" configurationId="p009.gpio_mode"/>
<configSetting altId="p011.adc1.an106" configurationId="p011"/>
<configSetting altId="p011.gpio_mode.gpio_mode_an" configurationId="p011.gpio_mode"/>
<configSetting altId="p014.adc0.an007" configurationId="p014"/>
<configSetting altId="p014.gpio_mode.gpio_mode_an" configurationId="p014.gpio_mode"/>
<configSetting altId="p015.adc1.an105" configurationId="p015"/>
<configSetting altId="p015.gpio_mode.gpio_mode_an" configurationId="p015.gpio_mode"/>
<configSetting altId="p100.ospi.om_sio0" configurationId="p100"/>
<configSetting altId="p100.gpio_mode.gpio_mode_peripheral" configurationId="p100.gpio_mode"/>
<configSetting altId="p101.ospi.om_sio3" configurationId="p101"/>
<configSetting altId="p101.gpio_mode.gpio_mode_peripheral" configurationId="p101.gpio_mode"/>
<configSetting altId="p102.ospi.om_sio4" configurationId="p102"/>
<configSetting altId="p102.gpio_mode.gpio_mode_peripheral" configurationId="p102.gpio_mode"/>
<configSetting altId="p103.ospi.om_sio2" configurationId="p103"/>
<configSetting altId="p103.gpio_mode.gpio_mode_peripheral" configurationId="p103.gpio_mode"/>
<configSetting altId="p104.ospi.om_cs1" configurationId="p104"/>
<configSetting altId="p104.gpio_mode.gpio_mode_peripheral" configurationId="p104.gpio_mode"/>
<configSetting altId="p105.ospi.om_ecsint1" configurationId="p105"/>
<configSetting altId="p105.gpio_mode.gpio_mode_peripheral" configurationId="p105.gpio_mode"/>
<configSetting altId="p106.ospi.om_reset" configurationId="p106"/>
<configSetting altId="p106.gpio_mode.gpio_mode_peripheral" configurationId="p106.gpio_mode"/>
<configSetting altId="p107.output.low" configurationId="p107"/>
<configSetting altId="p107.gpio_mode.gpio_mode_out.low" configurationId="p107.gpio_mode"/>
<configSetting altId="p112.ether_rmii.rmii0_crs_dv" configurationId="p112"/>
<configSetting altId="p112.gpio_mode.gpio_mode_peripheral" configurationId="p112.gpio_mode"/>
<configSetting altId="p114.ether_rmii.et0_linksta" configurationId="p114"/>
<configSetting altId="p114.gpio_mode.gpio_mode_peripheral" configurationId="p114.gpio_mode"/>
<configSetting altId="p208.jtag_fslash_swd.tdi" configurationId="p208"/>
<configSetting altId="p208.gpio_mode.gpio_mode_peripheral" configurationId="p208.gpio_mode"/>
<configSetting altId="p209.jtag_fslash_swd.tdo" configurationId="p209"/>
<configSetting altId="p209.gpio_mode.gpio_mode_peripheral" configurationId="p209.gpio_mode"/>
<configSetting altId="p210.jtag_fslash_swd.tms" configurationId="p210"/>
<configSetting altId="p210.gpio_mode.gpio_mode_peripheral" configurationId="p210.gpio_mode"/>
<configSetting altId="p211.jtag_fslash_swd.tck" configurationId="p211"/>
<configSetting altId="p211.gpio_mode.gpio_mode_peripheral" configurationId="p211.gpio_mode"/>
<configSetting altId="p300.ether_rmii.rmii0_rx_er" configurationId="p300"/>
<configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/>
<configSetting altId="p301.ether_rmii.rmii0_rxd1" configurationId="p301"/>
<configSetting altId="p301.gpio_mode.gpio_mode_peripheral" configurationId="p301.gpio_mode"/>
<configSetting altId="p302.ether_rmii.rmii0_rxd0" configurationId="p302"/>
<configSetting altId="p302.gpio_mode.gpio_mode_peripheral" configurationId="p302.gpio_mode"/>
<configSetting altId="p303.ether_rmii.ref50ck0" configurationId="p303"/>
<configSetting altId="p303.gpio_mode.gpio_mode_peripheral" configurationId="p303.gpio_mode"/>
<configSetting altId="p304.ether_rmii.rmii0_txd0" configurationId="p304"/>
<configSetting altId="p304.gpio_mode.gpio_mode_peripheral" configurationId="p304.gpio_mode"/>
<configSetting altId="p305.ether_rmii.rmii0_txd1" configurationId="p305"/>
<configSetting altId="p305.gpio_mode.gpio_mode_peripheral" configurationId="p305.gpio_mode"/>
<configSetting altId="p306.ether_rmii.rmii0_txd_en" configurationId="p306"/>
<configSetting altId="p306.gpio_mode.gpio_mode_peripheral" configurationId="p306.gpio_mode"/>
<configSetting altId="p307.ether_rmii.et0_mdio" configurationId="p307"/>
<configSetting altId="p307.gpio_mode.gpio_mode_peripheral" configurationId="p307.gpio_mode"/>
<configSetting altId="p308.ether_rmii.et0_mdc" configurationId="p308"/>
<configSetting altId="p308.gpio_mode.gpio_mode_peripheral" configurationId="p308.gpio_mode"/>
<configSetting altId="p407.usbfs.usb_vbus" configurationId="p407"/>
<configSetting altId="p407.gpio_mode.gpio_mode_peripheral" configurationId="p407.gpio_mode"/>
<configSetting altId="p408.usbhs.usbhs_vbusen" configurationId="p408"/>
<configSetting altId="p408.gpio_mode.gpio_mode_peripheral" configurationId="p408.gpio_mode"/>
<configSetting altId="p409.usbhs.usbhs_ovrcura" configurationId="p409"/>
<configSetting altId="p409.gpio_mode.gpio_mode_peripheral" configurationId="p409.gpio_mode"/>
<configSetting altId="p410.spi1.miso1" configurationId="p410"/>
<configSetting altId="p410.gpio_speed.gpio_speed_m" configurationId="p410.gpio_drivecapacity"/>
<configSetting altId="p410.gpio_mode.gpio_mode_peripheral" configurationId="p410.gpio_mode"/>
<configSetting altId="p411.spi1.mosi1" configurationId="p411"/>
<configSetting altId="p411.gpio_speed.gpio_speed_m" configurationId="p411.gpio_drivecapacity"/>
<configSetting altId="p411.gpio_mode.gpio_mode_peripheral" configurationId="p411.gpio_mode"/>
<configSetting altId="p412.spi1.rspck1" configurationId="p412"/>
<configSetting altId="p412.gpio_mode.gpio_mode_peripheral" configurationId="p412.gpio_mode"/>
<configSetting altId="p413.spi1.sslb0" configurationId="p413"/>
<configSetting altId="p413.gpio_speed.gpio_speed_m" configurationId="p413.gpio_drivecapacity"/>
<configSetting altId="p413.gpio_mode.gpio_mode_peripheral" configurationId="p413.gpio_mode"/>
<configSetting altId="p414.output.low" configurationId="p414"/>
<configSetting altId="p414.gpio_mode.gpio_mode_out.low" configurationId="p414.gpio_mode"/>
<configSetting altId="p500.usbfs.usb_vbusen" configurationId="p500"/>
<configSetting altId="p500.gpio_mode.gpio_mode_peripheral" configurationId="p500.gpio_mode"/>
<configSetting altId="p501.usbfs.usb_ovrcura" configurationId="p501"/>
<configSetting altId="p501.gpio_mode.gpio_mode_peripheral" configurationId="p501.gpio_mode"/>
<configSetting altId="p511.iic1.sda1" configurationId="p511"/>
<configSetting altId="p511.gpio_speed.gpio_speed_m" configurationId="p511.gpio_drivecapacity"/>
<configSetting altId="p511.gpio_mode.gpio_mode_peripheral" configurationId="p511.gpio_mode"/>
<configSetting altId="p512.iic1.scl1" configurationId="p512"/>
<configSetting altId="p512.gpio_speed.gpio_speed_m" configurationId="p512.gpio_drivecapacity"/>
<configSetting altId="p512.gpio_mode.gpio_mode_peripheral" configurationId="p512.gpio_mode"/>
<configSetting altId="p600.output.low" configurationId="p600"/>
<configSetting altId="p600.gpio_mode.gpio_mode_out.low" configurationId="p600.gpio_mode"/>
<configSetting altId="p800.ospi.om_sio5" configurationId="p800"/>
<configSetting altId="p800.gpio_mode.gpio_mode_peripheral" configurationId="p800.gpio_mode"/>
<configSetting altId="p801.ospi.om_dqs" configurationId="p801"/>
<configSetting altId="p801.gpio_mode.gpio_mode_peripheral" configurationId="p801.gpio_mode"/>
<configSetting altId="p802.ospi.om_sio6" configurationId="p802"/>
<configSetting altId="p802.gpio_mode.gpio_mode_peripheral" configurationId="p802.gpio_mode"/>
<configSetting altId="p803.ospi.om_sio1" configurationId="p803"/>
<configSetting altId="p803.gpio_mode.gpio_mode_peripheral" configurationId="p803.gpio_mode"/>
<configSetting altId="p804.ospi.om_sio7" configurationId="p804"/>
<configSetting altId="p804.gpio_mode.gpio_mode_peripheral" configurationId="p804.gpio_mode"/>
<configSetting altId="p808.ospi.om_sclk" configurationId="p808"/>
<configSetting altId="p808.gpio_mode.gpio_mode_peripheral" configurationId="p808.gpio_mode"/>
<configSetting altId="p809.output.low" configurationId="p809"/>
<configSetting altId="p809.gpio_mode.gpio_mode_out.low" configurationId="p809.gpio_mode"/>
<configSetting altId="p814.usbfs.usb_dp" configurationId="p814"/>
<configSetting altId="p814.gpio_mode.gpio_mode_peripheral" configurationId="p814.gpio_mode"/>
<configSetting altId="p815.usbfs.usb_dm" configurationId="p815"/>
<configSetting altId="p815.gpio_mode.gpio_mode_peripheral" configurationId="p815.gpio_mode"/>
<configSetting altId="pa02.sci2.rxd2" configurationId="pa02"/>
<configSetting altId="pa02.gpio_mode.gpio_mode_peripheral" configurationId="pa02.gpio_mode"/>
<configSetting altId="pa03.sci2.txd2" configurationId="pa03"/>
<configSetting altId="pa03.gpio_mode.gpio_mode_peripheral" configurationId="pa03.gpio_mode"/>
<configSetting altId="pa04.sci2.sck2" configurationId="pa04"/>
<configSetting altId="pa04.gpio_mode.gpio_mode_peripheral" configurationId="pa04.gpio_mode"/>
<configSetting altId="pa05.sci2.cts_rts2" configurationId="pa05"/>
<configSetting altId="pa05.gpio_mode.gpio_mode_peripheral" configurationId="pa05.gpio_mode"/>
<configSetting altId="pa06.input" configurationId="pa06"/>
<configSetting altId="pa06.gpio_mode.gpio_mode_in" configurationId="pa06.gpio_mode"/>
<configSetting altId="pa14.sci9.txd9" configurationId="pa14"/>
<configSetting altId="pa14.gpio_speed.gpio_speed_h" configurationId="pa14.gpio_drivecapacity"/>
<configSetting altId="pa14.gpio_mode.gpio_mode_peripheral" configurationId="pa14.gpio_mode"/>
<configSetting altId="pa15.sci9.rxd9" configurationId="pa15"/>
<configSetting altId="pa15.gpio_speed.gpio_speed_h" configurationId="pa15.gpio_drivecapacity"/>
<configSetting altId="pa15.gpio_mode.gpio_mode_peripheral" configurationId="pa15.gpio_mode"/>
<configSetting altId="pb01.usbhs.usbhs_vbus" configurationId="pb01"/>
<configSetting altId="pb01.gpio_speed.gpio_speed_h" configurationId="pb01.gpio_drivecapacity"/>
<configSetting altId="pb01.gpio_mode.gpio_mode_peripheral" configurationId="pb01.gpio_mode"/>
<configSetting altId="sci0.mode.custom.free" configurationId="sci0.mode"/>
<configSetting altId="sci1.mode.custom.free" configurationId="sci1.mode"/>
<configSetting altId="sci2.cts_rts2.pa05" configurationId="sci2.cts_rts2"/>
<configSetting altId="sci2.mode.custom.free" configurationId="sci2.mode"/>
<configSetting altId="sci2.rxd2.pa02" configurationId="sci2.rxd2"/>
<configSetting altId="sci2.sck2.pa04" configurationId="sci2.sck2"/>
<configSetting altId="sci2.txd2.pa03" configurationId="sci2.txd2"/>
<configSetting altId="sci4.mode.custom.free" configurationId="sci4.mode"/>
<configSetting altId="sci9.mode.custom.free" configurationId="sci9.mode"/>
<configSetting altId="sci9.rxd9.pa15" configurationId="sci9.rxd9"/>
<configSetting altId="sci9.txd9.pa14" configurationId="sci9.txd9"/>
<configSetting altId="spi1.miso1.p410" configurationId="spi1.miso1"/>
<configSetting altId="spi1.mode.custom.free" configurationId="spi1.mode"/>
<configSetting altId="spi1.mosi1.p411" configurationId="spi1.mosi1"/>
<configSetting altId="spi1.rspck1.p412" configurationId="spi1.rspck1"/>
<configSetting altId="spi1.sslb0.p413" configurationId="spi1.sslb0"/>
<configSetting altId="system.mode.custom.free" configurationId="system.mode"/>
<configSetting altId="usbfs.mode.custom.free" configurationId="usbfs.mode"/>
<configSetting altId="usbfs.usb_dm.p815" configurationId="usbfs.usb_dm"/>
<configSetting altId="usbfs.usb_dp.p814" configurationId="usbfs.usb_dp"/>
<configSetting altId="usbfs.usb_ovrcura.p501" configurationId="usbfs.usb_ovrcura"/>
<configSetting altId="usbfs.usb_vbus.p407" configurationId="usbfs.usb_vbus"/>
<configSetting altId="usbfs.usb_vbusen.p500" configurationId="usbfs.usb_vbusen"/>
<configSetting altId="usbhs.mode.custom.free" configurationId="usbhs.mode"/>
<configSetting altId="usbhs.usbhs_ovrcura.p409" configurationId="usbhs.usbhs_ovrcura"/>
<configSetting altId="usbhs.usbhs_vbus.pb01" configurationId="usbhs.usbhs_vbus"/>
<configSetting altId="usbhs.usbhs_vbusen.p408" configurationId="usbhs.usbhs_vbusen"/>
</pincfg>
<pincfg active="false" name="R7FA8M1AHECBD.pincfg" selected="false" symbol="">
<configSetting altId="jtag_fslash_swd.mode.jtag.free" configurationId="jtag_fslash_swd.mode"/>
<configSetting altId="jtag_fslash_swd.tck.p211" configurationId="jtag_fslash_swd.tck"/>
<configSetting altId="jtag_fslash_swd.tdi.p208" configurationId="jtag_fslash_swd.tdi"/>
<configSetting altId="jtag_fslash_swd.tdo.p209" configurationId="jtag_fslash_swd.tdo"/>
<configSetting altId="jtag_fslash_swd.tms.p210" configurationId="jtag_fslash_swd.tms"/>
<configSetting altId="p208.jtag_fslash_swd.tdi" configurationId="p208"/>
<configSetting altId="p208.gpio_mode.gpio_mode_peripheral" configurationId="p208.gpio_mode"/>
<configSetting altId="p209.jtag_fslash_swd.tdo" configurationId="p209"/>
<configSetting altId="p209.gpio_mode.gpio_mode_peripheral" configurationId="p209.gpio_mode"/>
<configSetting altId="p210.jtag_fslash_swd.tms" configurationId="p210"/>
<configSetting altId="p210.gpio_mode.gpio_mode_peripheral" configurationId="p210.gpio_mode"/>
<configSetting altId="p211.jtag_fslash_swd.tck" configurationId="p211"/>
<configSetting altId="p211.gpio_mode.gpio_mode_peripheral" configurationId="p211.gpio_mode"/>
</pincfg>
</raPinConfiguration>
</raConfiguration>

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bsp/renesas/ra8m1-ek/docs/picture/front.png Normal file
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752
bsp/renesas/ra8m1-ek/project.uvoptx Normal file
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@ -0,0 +1,752 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>Target 1</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>1</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\Listings\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>255</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>1</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>4</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon>Segger\JL2CM3.dll</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2V8M</Key>
<Name>UL2V8M(-S0 -C0 -P0 ) -FN3 -FC2000 -FD22000000 -FF0RA8D1_2M -FF1RA8D1_DATA_C2M -FF2RA8D1_CCONF -FL01F8000 -FL13000 -FL2200 -FS02000000 -FS127000000 -FS2300A100 -FP0($$Device:R7FA8D1BH$Flash\RA8D1_2M.FLM) -FP1($$Device:R7FA8D1BH$Flash\RA8D1_DATA_C2M.FLM) -FP2($$Device:R7FA8D1BH$Flash\RA8D1_CCONF.FLM)</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>1</periodic>
<aLwin>0</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>0</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>0</bLintAuto>
<bAutoGenD>0</bAutoGenD>
<LntExFlags>0</LntExFlags>
<pMisraName></pMisraName>
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
<Group>
<GroupName>Compiler</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>1</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\components\libc\compilers\armlibc\syscall_mem.c</PathWithFileName>
<FilenameWithoutPath>syscall_mem.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>2</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\components\libc\compilers\armlibc\syscalls.c</PathWithFileName>
<FilenameWithoutPath>syscalls.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>3</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\components\libc\compilers\common\cctype.c</PathWithFileName>
<FilenameWithoutPath>cctype.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>4</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\components\libc\compilers\common\cstdlib.c</PathWithFileName>
<FilenameWithoutPath>cstdlib.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>5</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\components\libc\compilers\common\cstring.c</PathWithFileName>
<FilenameWithoutPath>cstring.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>6</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\components\libc\compilers\common\ctime.c</PathWithFileName>
<FilenameWithoutPath>ctime.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>7</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\components\libc\compilers\common\cunistd.c</PathWithFileName>
<FilenameWithoutPath>cunistd.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>8</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\components\libc\compilers\common\cwchar.c</PathWithFileName>
<FilenameWithoutPath>cwchar.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>CPU</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>9</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\libcpu\arm\common\atomic_arm.c</PathWithFileName>
<FilenameWithoutPath>atomic_arm.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>10</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\libcpu\arm\common\div0.c</PathWithFileName>
<FilenameWithoutPath>div0.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>11</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\libcpu\arm\common\showmem.c</PathWithFileName>
<FilenameWithoutPath>showmem.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>12</FileNumber>
<FileType>2</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\libcpu\arm\cortex-m85\context_gcc.S</PathWithFileName>
<FilenameWithoutPath>context_gcc.S</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>13</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\libcpu\arm\cortex-m85\cpuport.c</PathWithFileName>
<FilenameWithoutPath>cpuport.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>DeviceDrivers</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>14</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\components\drivers\core\device.c</PathWithFileName>
<FilenameWithoutPath>device.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>15</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\components\drivers\ipc\completion.c</PathWithFileName>
<FilenameWithoutPath>completion.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>16</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\components\drivers\ipc\dataqueue.c</PathWithFileName>
<FilenameWithoutPath>dataqueue.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>17</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\components\drivers\ipc\pipe.c</PathWithFileName>
<FilenameWithoutPath>pipe.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>18</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\components\drivers\ipc\ringblk_buf.c</PathWithFileName>
<FilenameWithoutPath>ringblk_buf.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>19</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\components\drivers\ipc\ringbuffer.c</PathWithFileName>
<FilenameWithoutPath>ringbuffer.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>20</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\components\drivers\ipc\waitqueue.c</PathWithFileName>
<FilenameWithoutPath>waitqueue.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>21</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\components\drivers\ipc\workqueue.c</PathWithFileName>
<FilenameWithoutPath>workqueue.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>22</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\components\drivers\misc\pin.c</PathWithFileName>
<FilenameWithoutPath>pin.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>23</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\components\drivers\serial\serial_v2.c</PathWithFileName>
<FilenameWithoutPath>serial_v2.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>Drivers</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>4</GroupNumber>
<FileNumber>24</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>board\ra8_it.c</PathWithFileName>
<FilenameWithoutPath>ra8_it.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>4</GroupNumber>
<FileNumber>25</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\libraries\HAL_Drivers\drv_common.c</PathWithFileName>
<FilenameWithoutPath>drv_common.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>4</GroupNumber>
<FileNumber>26</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\libraries\HAL_Drivers\drv_gpio.c</PathWithFileName>
<FilenameWithoutPath>drv_gpio.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>4</GroupNumber>
<FileNumber>27</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\libraries\HAL_Drivers\drv_usart_v2.c</PathWithFileName>
<FilenameWithoutPath>drv_usart_v2.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>Finsh</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>28</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\components\finsh\shell.c</PathWithFileName>
<FilenameWithoutPath>shell.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>29</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\components\finsh\msh.c</PathWithFileName>
<FilenameWithoutPath>msh.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>30</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\components\finsh\msh_parse.c</PathWithFileName>
<FilenameWithoutPath>msh_parse.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>31</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\components\finsh\cmd.c</PathWithFileName>
<FilenameWithoutPath>cmd.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>Kernel</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>32</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\src\clock.c</PathWithFileName>
<FilenameWithoutPath>clock.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>33</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\src\components.c</PathWithFileName>
<FilenameWithoutPath>components.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>34</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\src\idle.c</PathWithFileName>
<FilenameWithoutPath>idle.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>35</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\src\ipc.c</PathWithFileName>
<FilenameWithoutPath>ipc.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>36</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\src\irq.c</PathWithFileName>
<FilenameWithoutPath>irq.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>37</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\src\kservice.c</PathWithFileName>
<FilenameWithoutPath>kservice.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>38</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\src\mem.c</PathWithFileName>
<FilenameWithoutPath>mem.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>39</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\src\object.c</PathWithFileName>
<FilenameWithoutPath>object.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>40</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\src\scheduler_up.c</PathWithFileName>
<FilenameWithoutPath>scheduler_up.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>41</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\src\thread.c</PathWithFileName>
<FilenameWithoutPath>thread.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>42</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\src\timer.c</PathWithFileName>
<FilenameWithoutPath>timer.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>:Renesas RA Smart Configurator:Common Sources</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>7</GroupNumber>
<FileNumber>43</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\src\hal_entry.c</PathWithFileName>
<FilenameWithoutPath>hal_entry.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>::Flex Software</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>1</RteFlg>
</Group>
</ProjectOpt>

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bsp/renesas/ra8m1-ek/project.uvprojx Normal file
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@ -0,0 +1,670 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
<SchemaVersion>2.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>Target 1</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>6190000::V6.19::ARMCLANG</pCCUsed>
<uAC6>1</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>R7FA8M1AH</Device>
<Vendor>Renesas</Vendor>
<PackID>Renesas.RA_DFP.5.0.0</PackID>
<PackURL>https://www2.renesas.eu/Keil_MDK_Packs/</PackURL>
<Cpu>CPUTYPE("Cortex-M85") DSP TZ MVE(FP) FPU3(DFPU) PACBTI CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll></FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile></RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>$$Device:R7FA8M1AH$SVD\R7FA8M1AH.svd</SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath></RegisterFilePath>
<DBRegisterFilePath></DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\Objects\</OutputDirectory>
<OutputName>ra8m1</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>1</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
<ListingPath>.\Listings\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
<nStopU2X>0</nStopU2X>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopB1X>0</nStopB1X>
<nStopB2X>0</nStopB2X>
</BeforeMake>
<AfterMake>
<RunUserProg1>1</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name>cmd /c "start "Renesas" /w cmd /c ""$Slauncher\rasc_launcher.bat" "$Prasc_version.txt" -nosplash --launcher.suppressErrors --gensmartbundle --compiler ARMv6 "$Pconfiguration.xml" "$L%L" 2&gt; "%%TEMP%%\rasc_stderr.out"""</UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopA1X>2</nStopA1X>
<nStopA2X>0</nStopA2X>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<DllOption>
<SimDllName>SARMV8M.DLL</SimDllName>
<SimDllArguments> -MPU</SimDllArguments>
<SimDlgDll>DCM.DLL</SimDlgDll>
<SimDlgDllArguments>-pCM4</SimDlgDllArguments>
<TargetDllName>SARMV8M.DLL</TargetDllName>
<TargetDllArguments> -MPU</TargetDllArguments>
<TargetDlgDll>TCM.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM85</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>0</UseTargetDll>
<UseExternalTool>1</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>-1</DriverSelection>
</Flash1>
<bUseTDR>1</bUseTDR>
<Flash2></Flash2>
<Flash3>"" ()</Flash3>
<Flash4></Flash4>
<pFcarmOut></pFcarmOut>
<pFcarmGrp></pFcarmGrp>
<pFcArmRoot></pFcArmRoot>
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>1</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
<AdsLven>1</AdsLven>
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M85"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>0</hadIROM>
<hadIRAM>0</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>3</RvdsVP>
<RvdsMve>2</RvdsMve>
<RvdsCdeCp>0</RvdsCdeCp>
<nBranchProt>0</nBranchProt>
<hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>0</StupSel>
<useUlib>1</useUlib>
<EndSel>0</EndSel>
<uLtcg>0</uLtcg>
<nSecure>0</nSecure>
<RoSelD>0</RoSelD>
<RwSelD>0</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>0</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>0</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>0</Im1Chk>
<Im2Chk>0</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</IRAM>
<IROM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</IROM>
<XRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>6</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>0</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>0</uC99>
<uGnu>0</uGnu>
<useXO>0</useXO>
<v6Lang>3</v6Lang>
<v6LangP>3</v6LangP>
<vShortEn>0</vShortEn>
<vShortWch>0</vShortWch>
<v6Lto>0</v6Lto>
<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls>-Wno-license-management -Wuninitialized -Wall -Wmissing-declarations -Wpointer-arith -Waggregate-return -Wfloat-equal</MiscControls>
<Define>RT_USING_LIBC, RT_USING_ARMLIBC, __STDC_LIMIT_MACROS, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND</Define>
<Undefine></Undefine>
<IncludePath>board\ports;..\..\..\components\finsh;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\include;..\..\..\components\libc\posix\io\eventfd;..\libraries\HAL_Drivers\config;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m85;..\..\..\components\libc\posix\io\epoll;..\libraries\HAL_Drivers;..\..\..\components\libc\posix\ipc;..\..\..\components\drivers\include;..\..\..\components\libc\compilers\common\extension;board;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\compilers\common\include;.</IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<ClangAsOpt>2</ClangAsOpt>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>0</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>0</RepFail>
<useFile>0</useFile>
<TextAddressRange></TextAddressRange>
<DataAddressRange></DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile>.\script\fsp.scat</ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings>6319,6314</DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>Compiler</GroupName>
<Files>
<File>
<FileName>syscall_mem.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\libc\compilers\armlibc\syscall_mem.c</FilePath>
</File>
<File>
<FileName>syscalls.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\libc\compilers\armlibc\syscalls.c</FilePath>
</File>
<File>
<FileName>cctype.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\libc\compilers\common\cctype.c</FilePath>
</File>
<File>
<FileName>cstdlib.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\libc\compilers\common\cstdlib.c</FilePath>
</File>
<File>
<FileName>cstring.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\libc\compilers\common\cstring.c</FilePath>
</File>
<File>
<FileName>ctime.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\libc\compilers\common\ctime.c</FilePath>
</File>
<File>
<FileName>cunistd.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\libc\compilers\common\cunistd.c</FilePath>
</File>
<File>
<FileName>cwchar.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\libc\compilers\common\cwchar.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>CPU</GroupName>
<Files>
<File>
<FileName>atomic_arm.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\libcpu\arm\common\atomic_arm.c</FilePath>
</File>
<File>
<FileName>div0.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\libcpu\arm\common\div0.c</FilePath>
</File>
<File>
<FileName>showmem.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\libcpu\arm\common\showmem.c</FilePath>
</File>
<File>
<FileName>context_gcc.S</FileName>
<FileType>2</FileType>
<FilePath>..\..\..\libcpu\arm\cortex-m85\context_gcc.S</FilePath>
</File>
<File>
<FileName>cpuport.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\libcpu\arm\cortex-m85\cpuport.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>DeviceDrivers</GroupName>
<Files>
<File>
<FileName>device.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\core\device.c</FilePath>
</File>
<File>
<FileName>completion.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\ipc\completion.c</FilePath>
</File>
<File>
<FileName>dataqueue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\ipc\dataqueue.c</FilePath>
</File>
<File>
<FileName>pipe.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\ipc\pipe.c</FilePath>
</File>
<File>
<FileName>ringblk_buf.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\ipc\ringblk_buf.c</FilePath>
</File>
<File>
<FileName>ringbuffer.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\ipc\ringbuffer.c</FilePath>
</File>
<File>
<FileName>waitqueue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\ipc\waitqueue.c</FilePath>
</File>
<File>
<FileName>workqueue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\ipc\workqueue.c</FilePath>
</File>
<File>
<FileName>pin.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\misc\pin.c</FilePath>
</File>
<File>
<FileName>serial_v2.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\serial\serial_v2.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Drivers</GroupName>
<Files>
<File>
<FileName>ra8_it.c</FileName>
<FileType>1</FileType>
<FilePath>board\ra8_it.c</FilePath>
</File>
<File>
<FileName>drv_common.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\HAL_Drivers\drv_common.c</FilePath>
</File>
<File>
<FileName>drv_gpio.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\HAL_Drivers\drv_gpio.c</FilePath>
</File>
<File>
<FileName>drv_usart_v2.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\HAL_Drivers\drv_usart_v2.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Finsh</GroupName>
<Files>
<File>
<FileName>shell.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\shell.c</FilePath>
</File>
<File>
<FileName>msh.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\msh.c</FilePath>
</File>
<File>
<FileName>msh_parse.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\msh_parse.c</FilePath>
</File>
<File>
<FileName>cmd.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\cmd.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Kernel</GroupName>
<Files>
<File>
<FileName>clock.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\clock.c</FilePath>
</File>
<File>
<FileName>components.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\components.c</FilePath>
</File>
<File>
<FileName>idle.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\idle.c</FilePath>
</File>
<File>
<FileName>ipc.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\ipc.c</FilePath>
</File>
<File>
<FileName>irq.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\irq.c</FilePath>
</File>
<File>
<FileName>kservice.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\kservice.c</FilePath>
</File>
<File>
<FileName>mem.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\mem.c</FilePath>
</File>
<File>
<FileName>object.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\object.c</FilePath>
</File>
<File>
<FileName>scheduler_up.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\scheduler_up.c</FilePath>
</File>
<File>
<FileName>thread.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\thread.c</FilePath>
</File>
<File>
<FileName>timer.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\timer.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>:Renesas RA Smart Configurator:Common Sources</GroupName>
<Files>
<File>
<FileName>hal_entry.c</FileName>
<FileType>1</FileType>
<FilePath>.\src\hal_entry.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>::Flex Software</GroupName>
</Group>
</Groups>
</Target>
</Targets>
<RTE>
<gpdscs>
<gpdsc name="buildinfo.gpdsc">
<targetInfos>
<targetInfo name="Target 1"/>
</targetInfos>
</gpdsc>
</gpdscs>
<apis/>
<components>
<component Cclass="Flex Software" Cgroup="RA Configuration" Cvendor="Renesas" Cversion="1.0.0" condition="RA Device" generator="Renesas RA Smart Configurator">
<package name="RA_DFP" schemaVersion="1.7.2" url="https://www2.renesas.eu/Keil_MDK_Packs/" vendor="Renesas" version="5.0.0"/>
<targetInfos>
<targetInfo name="Target 1"/>
</targetInfos>
</component>
</components>
<files/>
</RTE>
<LayerInfo>
<Layers>
<Layer>
<LayName>project</LayName>
<LayPrjMark>1</LayPrjMark>
</Layer>
</Layers>
</LayerInfo>
</Project>

26
bsp/renesas/ra8m1-ek/ra/SConscript Normal file
View File

@ -0,0 +1,26 @@
Import('RTT_ROOT')
Import('rtconfig')
from building import *
from gcc import *
cwd = GetCurrentDir()
src = []
group = []
CPPPATH = []
if rtconfig.PLATFORM in ['iccarm']:
print("\nThe current project does not support IAR build\n")
Return('group')
elif rtconfig.PLATFORM in GetGCCLikePLATFORM():
if GetOption('target') != 'mdk5':
src += Glob(cwd + '/fsp/src/bsp/mcu/all/*.c')
src += [cwd + '/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c']
src += [cwd + '/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c']
src += Glob(cwd + '/fsp/src/r_*/*.c')
CPPPATH = [ cwd + '/arm/CMSIS_5/CMSIS/Core/Include',
cwd + '/fsp/inc',
cwd + '/fsp/inc/api',
cwd + '/fsp/inc/instances',]
group = DefineGroup('ra', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

411
bsp/renesas/ra8m1-ek/ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h Normal file
View File

@ -0,0 +1,411 @@
/******************************************************************************
* @file cachel1_armv7.h
* @brief CMSIS Level 1 Cache API for Armv7-M and later
* @version V1.0.1
* @date 19. April 2021
******************************************************************************/
/*
* Copyright (c) 2020-2021 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_CACHEL1_ARMV7_H
#define ARM_CACHEL1_ARMV7_H
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_CacheFunctions Cache Functions
\brief Functions that configure Instruction and Data cache.
@{
*/
/* Cache Size ID Register Macros */
#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
#ifndef __SCB_DCACHE_LINE_SIZE
#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
#endif
#ifndef __SCB_ICACHE_LINE_SIZE
#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
#endif
/**
\brief Enable I-Cache
\details Turns on I-Cache
*/
__STATIC_FORCEINLINE void SCB_EnableICache (void)
{
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */
__DSB();
__ISB();
SCB->ICIALLU = 0UL; /* invalidate I-Cache */
__DSB();
__ISB();
SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
__DSB();
__ISB();
#endif
}
/**
\brief Disable I-Cache
\details Turns off I-Cache
*/
__STATIC_FORCEINLINE void SCB_DisableICache (void)
{
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
__DSB();
__ISB();
SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
SCB->ICIALLU = 0UL; /* invalidate I-Cache */
__DSB();
__ISB();
#endif
}
/**
\brief Invalidate I-Cache
\details Invalidates I-Cache
*/
__STATIC_FORCEINLINE void SCB_InvalidateICache (void)
{
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
__DSB();
__ISB();
SCB->ICIALLU = 0UL;
__DSB();
__ISB();
#endif
}
/**
\brief I-Cache Invalidate by address
\details Invalidates I-Cache for the given address.
I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
I-Cache memory blocks which are part of given address + given size are invalidated.
\param[in] addr address
\param[in] isize size of memory block (in number of bytes)
*/
__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize)
{
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
if ( isize > 0 ) {
int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;
__DSB();
do {
SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
op_addr += __SCB_ICACHE_LINE_SIZE;
op_size -= __SCB_ICACHE_LINE_SIZE;
} while ( op_size > 0 );
__DSB();
__ISB();
}
#endif
}
/**
\brief Enable D-Cache
\details Turns on D-Cache
*/
__STATIC_FORCEINLINE void SCB_EnableDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */
SCB->CSSELR = 0U; /* select Level 1 data cache */
__DSB();
ccsidr = SCB->CCSIDR;
/* invalidate D-Cache */
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do {
SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
#if defined ( __CC_ARM )
__schedule_barrier();
#endif
} while (ways-- != 0U);
} while(sets-- != 0U);
__DSB();
SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
__DSB();
__ISB();
#endif
}
/**
\brief Disable D-Cache
\details Turns off D-Cache
*/
__STATIC_FORCEINLINE void SCB_DisableDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
SCB->CSSELR = 0U; /* select Level 1 data cache */
__DSB();
SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
__DSB();
ccsidr = SCB->CCSIDR;
/* clean & invalidate D-Cache */
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do {
SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
#if defined ( __CC_ARM )
__schedule_barrier();
#endif
} while (ways-- != 0U);
} while(sets-- != 0U);
__DSB();
__ISB();
#endif
}
/**
\brief Invalidate D-Cache
\details Invalidates D-Cache
*/
__STATIC_FORCEINLINE void SCB_InvalidateDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
SCB->CSSELR = 0U; /* select Level 1 data cache */
__DSB();
ccsidr = SCB->CCSIDR;
/* invalidate D-Cache */
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do {
SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
#if defined ( __CC_ARM )
__schedule_barrier();
#endif
} while (ways-- != 0U);
} while(sets-- != 0U);
__DSB();
__ISB();
#endif
}
/**
\brief Clean D-Cache
\details Cleans D-Cache
*/
__STATIC_FORCEINLINE void SCB_CleanDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
SCB->CSSELR = 0U; /* select Level 1 data cache */
__DSB();
ccsidr = SCB->CCSIDR;
/* clean D-Cache */
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do {
SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
#if defined ( __CC_ARM )
__schedule_barrier();
#endif
} while (ways-- != 0U);
} while(sets-- != 0U);
__DSB();
__ISB();
#endif
}
/**
\brief Clean & Invalidate D-Cache
\details Cleans and Invalidates D-Cache
*/
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
SCB->CSSELR = 0U; /* select Level 1 data cache */
__DSB();
ccsidr = SCB->CCSIDR;
/* clean & invalidate D-Cache */
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do {
SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
#if defined ( __CC_ARM )
__schedule_barrier();
#endif
} while (ways-- != 0U);
} while(sets-- != 0U);
__DSB();
__ISB();
#endif
}
/**
\brief D-Cache Invalidate by address
\details Invalidates D-Cache for the given address.
D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
D-Cache memory blocks which are part of given address + given size are invalidated.
\param[in] addr address
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
if ( dsize > 0 ) {
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
__DSB();
do {
SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
op_addr += __SCB_DCACHE_LINE_SIZE;
op_size -= __SCB_DCACHE_LINE_SIZE;
} while ( op_size > 0 );
__DSB();
__ISB();
}
#endif
}
/**
\brief D-Cache Clean by address
\details Cleans D-Cache for the given address
D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity.
D-Cache memory blocks which are part of given address + given size are cleaned.
\param[in] addr address
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
if ( dsize > 0 ) {
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
__DSB();
do {
SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
op_addr += __SCB_DCACHE_LINE_SIZE;
op_size -= __SCB_DCACHE_LINE_SIZE;
} while ( op_size > 0 );
__DSB();
__ISB();
}
#endif
}
/**
\brief D-Cache Clean and Invalidate by address
\details Cleans and invalidates D_Cache for the given address
D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity.
D-Cache memory blocks which are part of given address + given size are cleaned and invalidated.
\param[in] addr address (aligned to 32-byte boundary)
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
if ( dsize > 0 ) {
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
__DSB();
do {
SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
op_addr += __SCB_DCACHE_LINE_SIZE;
op_size -= __SCB_DCACHE_LINE_SIZE;
} while ( op_size > 0 );
__DSB();
__ISB();
}
#endif
}
/*@} end of CMSIS_Core_CacheFunctions */
#endif /* ARM_CACHEL1_ARMV7_H */

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/**************************************************************************//**
* @file cmsis_armcc.h
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
* @version V5.3.2
* @date 27. May 2021
******************************************************************************/
/*
* Copyright (c) 2009-2021 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_ARMCC_H
#define __CMSIS_ARMCC_H
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
#endif
/* CMSIS compiler control architecture macros */
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
#define __ARM_ARCH_6M__ 1
#endif
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
#define __ARM_ARCH_7M__ 1
#endif
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
#define __ARM_ARCH_7EM__ 1
#endif
/* __ARM_ARCH_8M_BASE__ not applicable */
/* __ARM_ARCH_8M_MAIN__ not applicable */
/* __ARM_ARCH_8_1M_MAIN__ not applicable */
/* CMSIS compiler control DSP macros */
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __ARM_FEATURE_DSP 1
#endif
/* CMSIS compiler specific defines */
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE __inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static __inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE static __forceinline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __declspec(noreturn)
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT __packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION __packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __COMPILER_BARRIER
#define __COMPILER_BARRIER() __memory_changed()
#endif
/* ######################### Startup and Lowlevel Init ######################## */
#ifndef __PROGRAM_START
#define __PROGRAM_START __main
#endif
#ifndef __INITIAL_SP
#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
#endif
#ifndef __STACK_LIMIT
#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
#endif
#ifndef __VECTOR_TABLE
#define __VECTOR_TABLE __Vectors
#endif
#ifndef __VECTOR_TABLE_ATTRIBUTE
#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET")))
#endif
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
#define __WFI __wfi
/**
\brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/**
\brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
#define __ISB() __isb(0xF)
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() __dsb(0xF)
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() __dmb(0xF)
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#endif
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] op1 Value to rotate
\param [in] op2 Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/**
\brief Breakpoint
\details Causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __RBIT __rbit
#else
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value != 0U; value >>= 1U)
{
result <<= 1U;
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
return result;
}
#endif
/**
\brief Count leading zeros
\details Counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief LDR Exclusive (8 bit)
\details Executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
#else
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
#else
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
#else
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXB(value, ptr) __strex(value, ptr)
#else
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXH(value, ptr) __strex(value, ptr)
#else
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXW(value, ptr) __strex(value, ptr)
#else
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/**
\brief Rotate Right with Extend (32 bit)
\details Moves each bit of a bitstring right by one bit.
The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
{
rrx r0, r0
bx lr
}
#endif
/**
\brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
/**
\brief LDRT Unprivileged (16 bit)
\details Executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
/**
\brief LDRT Unprivileged (32 bit)
\details Executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
/**
\brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRBT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRHT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRT(value, ptr) __strt(value, ptr)
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/**
\brief Enable IRQ Interrupts
\details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
Can only be executed in Privileged modes.
*/
/* intrinsic void __enable_irq(); */
/**
\brief Disable IRQ Interrupts
\details Disables IRQ interrupts by setting special-purpose register PRIMASK.
Can only be executed in Privileged modes.
*/
/* intrinsic void __disable_irq(); */
/**
\brief Get Control Register
\details Returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/**
\brief Set Control Register
\details Writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
__ISB();
}
/**
\brief Get IPSR Register
\details Returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/**
\brief Get APSR Register
\details Returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/**
\brief Get xPSR Register
\details Returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/**
\brief Get Process Stack Pointer
\details Returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/**
\brief Set Process Stack Pointer
\details Assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/**
\brief Get Main Stack Pointer
\details Returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/**
\brief Set Main Stack Pointer
\details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/**
\brief Get Priority Mask
\details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/**
\brief Set Priority Mask
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief Enable FIQ
\details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/**
\brief Disable FIQ
\details Disables FIQ interrupts by setting special-purpose register FAULTMASK.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/**
\brief Get Base Priority
\details Returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/**
\brief Set Base Priority
\details Assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xFFU);
}
/**
\brief Set Base Priority with condition
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
{
register uint32_t __regBasePriMax __ASM("basepri_max");
__regBasePriMax = (basePri & 0xFFU);
}
/**
\brief Get Fault Mask
\details Returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/**
\brief Set Fault Mask
\details Assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1U);
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0U);
#endif
}
/**
\brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#else
(void)fpscr;
#endif
}
/*@} end of CMSIS_Core_RegAccFunctions */
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32U) ) >> 32U))
#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CMSIS_ARMCC_H */

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/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.1.0
* @date 09. October 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* Arm Compiler 6.6 LTM (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
#include "cmsis_armclang_ltm.h"
/*
* Arm Compiler above 6.10.1 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h>
/*
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */

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/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.5
* @date 02. February 2022
******************************************************************************/
/*
* Copyright (c) 2009-2022 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 6U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif

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/**************************************************************************//**
* @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version V5.0.8
* @date 21. August 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM0_H_GENERIC
#define __CORE_CM0_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M0
@{
*/
#include "cmsis_version.h"
/* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
__CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (0U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_FP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0_H_DEPENDANT
#define __CORE_CM0_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0_REV
#define __CM0_REV 0x0000U
#warning "__CM0_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M0 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RESERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__COMPILER_BARRIER();
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__COMPILER_BARRIER();
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
Address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
*(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */
/* ARM Application Note 321 states that the M0 does not require the architectural barrier */
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

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/**************************************************************************//**
* @file core_cm1.h
* @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File
* @version V1.0.1
* @date 12. November 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM1_H_GENERIC
#define __CORE_CM1_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M1
@{
*/
#include "cmsis_version.h"
/* CMSIS CM1 definitions */
#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
__CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (1U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_FP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM1_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM1_H_DEPENDANT
#define __CORE_CM1_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM1_REV
#define __CM1_REV 0x0100U
#warning "__CM1_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M1 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
\brief Type definitions for the System Control and ID Register not in the SCB
@{
*/
/**
\brief Structure type to access the System Control and ID Register not in the SCB.
*/
typedef struct
{
uint32_t RESERVED0[2U];
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
} SCnSCB_Type;
/* Auxiliary Control Register Definitions */
#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
/*@} end of group CMSIS_SCnotSCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M1 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__COMPILER_BARRIER();
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__COMPILER_BARRIER();
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
Address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)0x0U;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
/* ARM Application Note 321 states that the M1 does not require the architectural barrier */
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)0x0U;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM1_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

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/******************************************************************************
* @file mpu_armv7.h
* @brief CMSIS MPU API for Armv7-M MPU
* @version V5.1.2
* @date 25. May 2020
******************************************************************************/
/*
* Copyright (c) 2017-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV7_H
#define ARM_MPU_ARMV7_H
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
/** MPU Region Base Address Register Value
*
* \param Region The region to be configured, number 0 to 15.
* \param BaseAddress The base address for the region.
*/
#define ARM_MPU_RBAR(Region, BaseAddress) \
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
((Region) & MPU_RBAR_REGION_Msk) | \
(MPU_RBAR_VALID_Msk))
/**
* MPU Memory Access Attributes
*
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
*/
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
(((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
(((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
(((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
(((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
(((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
(((MPU_RASR_ENABLE_Msk))))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
/**
* MPU Memory Access Attribute for strongly ordered memory.
* - TEX: 000b
* - Shareable
* - Non-cacheable
* - Non-bufferable
*/
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
/**
* MPU Memory Access Attribute for device memory.
* - TEX: 000b (if shareable) or 010b (if non-shareable)
* - Shareable or non-shareable
* - Non-cacheable
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
*
* \param IsShareable Configures the device memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
/**
* MPU Memory Access Attribute for normal memory.
* - TEX: 1BBb (reflecting outer cacheability rules)
* - Shareable or non-shareable
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
*
* \param OuterCp Configures the outer cache policy.
* \param InnerCp Configures the inner cache policy.
* \param IsShareable Configures the memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))
/**
* MPU Memory Access Attribute non-cacheable policy.
*/
#define ARM_MPU_CACHEP_NOCACHE 0U
/**
* MPU Memory Access Attribute write-back, write and read allocate policy.
*/
#define ARM_MPU_CACHEP_WB_WRA 1U
/**
* MPU Memory Access Attribute write-through, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WT_NWA 2U
/**
* MPU Memory Access Attribute write-back, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WB_NWA 3U
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; //!< The region base address register value (RBAR)
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
__DMB();
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
__DSB();
__ISB();
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
MPU->RNR = rnr;
MPU->RASR = 0U;
}
/** Configure an MPU region.
* \param rbar Value for RBAR register.
* \param rasr Value for RASR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
{
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rasr Value for RASR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
{
MPU->RNR = rnr;
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load().
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
while (cnt > MPU_TYPE_RALIASES) {
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
table += MPU_TYPE_RALIASES;
cnt -= MPU_TYPE_RALIASES;
}
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
}
#endif

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/******************************************************************************
* @file mpu_armv8.h
* @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
* @version V5.1.3
* @date 03. February 2021
******************************************************************************/
/*
* Copyright (c) 2017-2021 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV8_H
#define ARM_MPU_ARMV8_H
/** \brief Attribute for device memory (outer only) */
#define ARM_MPU_ATTR_DEVICE ( 0U )
/** \brief Attribute for non-cacheable, normal memory */
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
/** \brief Attribute for normal memory (outer and inner)
* \param NT Non-Transient: Set to 1 for non-transient data.
* \param WB Write-Back: Set to 1 to use write-back update policy.
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
*/
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U))
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
/** \brief Memory Attribute
* \param O Outer memory attributes
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
*/
#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U)))
/** \brief Normal memory non-shareable */
#define ARM_MPU_SH_NON (0U)
/** \brief Normal memory outer shareable */
#define ARM_MPU_SH_OUTER (2U)
/** \brief Normal memory inner shareable */
#define ARM_MPU_SH_INNER (3U)
/** \brief Memory access permissions
* \param RO Read-Only: Set to 1 for read-only memory.
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
*/
#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U))
/** \brief Region Base Address Register value
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
* \param SH Defines the Shareability domain for this memory region.
* \param RO Read-Only: Set to 1 for a read-only memory region.
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
*/
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
(((BASE) & MPU_RBAR_BASE_Msk) | \
(((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
(((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
/** \brief Region Limit Address Register value
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
* \param IDX The attribute index to be associated with this memory region.
*/
#define ARM_MPU_RLAR(LIMIT, IDX) \
(((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
(((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
(MPU_RLAR_EN_Msk))
#if defined(MPU_RLAR_PXN_Pos)
/** \brief Region Limit Address Register with PXN value
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
* \param IDX The attribute index to be associated with this memory region.
*/
#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
(((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
(((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
(((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
(MPU_RLAR_EN_Msk))
#endif
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; /*!< Region Base Address Register value */
uint32_t RLAR; /*!< Region Limit Address Register value */
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
__DMB();
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
__DSB();
__ISB();
}
#ifdef MPU_NS
/** Enable the Non-secure MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
{
__DMB();
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the Non-secure MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
__DSB();
__ISB();
}
#endif
/** Set the memory attribute encoding to the given MPU.
* \param mpu Pointer to the MPU to be configured.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
{
const uint8_t reg = idx / 4U;
const uint32_t pos = ((idx % 4U) * 8U);
const uint32_t mask = 0xFFU << pos;
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
return; // invalid index
}
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
}
/** Set the memory attribute encoding.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
}
#ifdef MPU_NS
/** Set the memory attribute encoding to the Non-secure MPU.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
}
#endif
/** Clear and disable the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
{
mpu->RNR = rnr;
mpu->RLAR = 0U;
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU, rnr);
}
#ifdef MPU_NS
/** Clear and disable the given Non-secure MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
}
#endif
/** Configure the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
mpu->RNR = rnr;
mpu->RBAR = rbar;
mpu->RLAR = rlar;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
}
#ifdef MPU_NS
/** Configure the given Non-secure MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
}
#endif
/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx()
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table to the given MPU.
* \param mpu Pointer to the MPU registers to be used.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
if (cnt == 1U) {
mpu->RNR = rnr;
ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
} else {
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
table += c;
cnt -= c;
rnrOffset = 0U;
rnrBase += MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
}
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
}
}
/** Load the given number of MPU regions from a table.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
}
#ifdef MPU_NS
/** Load the given number of MPU regions from a table to the Non-secure MPU.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
}
#endif
#endif

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/******************************************************************************
* @file pac_armv81.h
* @brief CMSIS PAC key functions for Armv8.1-M PAC extension
* @version V1.0.0
* @date 23. March 2022
******************************************************************************/
/*
* Copyright (c) 2022 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef PAC_ARMV81_H
#define PAC_ARMV81_H
/* ################### PAC Key functions ########################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_PacKeyFunctions PAC Key functions
\brief Functions that access the PAC keys.
@{
*/
#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1))
/**
\brief read the PAC key used for privileged mode
\details Reads the PAC key stored in the PAC_KEY_P registers.
\param [out] pPacKey 128bit PAC key
*/
__STATIC_FORCEINLINE void __get_PAC_KEY_P (uint32_t* pPacKey) {
__ASM volatile (
"mrs r1, pac_key_p_0\n"
"str r1,[%0,#0]\n"
"mrs r1, pac_key_p_1\n"
"str r1,[%0,#4]\n"
"mrs r1, pac_key_p_2\n"
"str r1,[%0,#8]\n"
"mrs r1, pac_key_p_3\n"
"str r1,[%0,#12]\n"
: : "r" (pPacKey) : "memory", "r1"
);
}
/**
\brief write the PAC key used for privileged mode
\details writes the given PAC key to the PAC_KEY_P registers.
\param [in] pPacKey 128bit PAC key
*/
__STATIC_FORCEINLINE void __set_PAC_KEY_P (uint32_t* pPacKey) {
__ASM volatile (
"ldr r1,[%0,#0]\n"
"msr pac_key_p_0, r1\n"
"ldr r1,[%0,#4]\n"
"msr pac_key_p_1, r1\n"
"ldr r1,[%0,#8]\n"
"msr pac_key_p_2, r1\n"
"ldr r1,[%0,#12]\n"
"msr pac_key_p_3, r1\n"
: : "r" (pPacKey) : "memory", "r1"
);
}
/**
\brief read the PAC key used for unprivileged mode
\details Reads the PAC key stored in the PAC_KEY_U registers.
\param [out] pPacKey 128bit PAC key
*/
__STATIC_FORCEINLINE void __get_PAC_KEY_U (uint32_t* pPacKey) {
__ASM volatile (
"mrs r1, pac_key_u_0\n"
"str r1,[%0,#0]\n"
"mrs r1, pac_key_u_1\n"
"str r1,[%0,#4]\n"
"mrs r1, pac_key_u_2\n"
"str r1,[%0,#8]\n"
"mrs r1, pac_key_u_3\n"
"str r1,[%0,#12]\n"
: : "r" (pPacKey) : "memory", "r1"
);
}
/**
\brief write the PAC key used for unprivileged mode
\details writes the given PAC key to the PAC_KEY_U registers.
\param [in] pPacKey 128bit PAC key
*/
__STATIC_FORCEINLINE void __set_PAC_KEY_U (uint32_t* pPacKey) {
__ASM volatile (
"ldr r1,[%0,#0]\n"
"msr pac_key_u_0, r1\n"
"ldr r1,[%0,#4]\n"
"msr pac_key_u_1, r1\n"
"ldr r1,[%0,#8]\n"
"msr pac_key_u_2, r1\n"
"ldr r1,[%0,#12]\n"
"msr pac_key_u_3, r1\n"
: : "r" (pPacKey) : "memory", "r1"
);
}
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief read the PAC key used for privileged mode (non-secure)
\details Reads the PAC key stored in the non-secure PAC_KEY_P registers when in secure mode.
\param [out] pPacKey 128bit PAC key
*/
__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_P_NS (uint32_t* pPacKey) {
__ASM volatile (
"mrs r1, pac_key_p_0_ns\n"
"str r1,[%0,#0]\n"
"mrs r1, pac_key_p_1_ns\n"
"str r1,[%0,#4]\n"
"mrs r1, pac_key_p_2_ns\n"
"str r1,[%0,#8]\n"
"mrs r1, pac_key_p_3_ns\n"
"str r1,[%0,#12]\n"
: : "r" (pPacKey) : "memory", "r1"
);
}
/**
\brief write the PAC key used for privileged mode (non-secure)
\details writes the given PAC key to the non-secure PAC_KEY_P registers when in secure mode.
\param [in] pPacKey 128bit PAC key
*/
__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_P_NS (uint32_t* pPacKey) {
__ASM volatile (
"ldr r1,[%0,#0]\n"
"msr pac_key_p_0_ns, r1\n"
"ldr r1,[%0,#4]\n"
"msr pac_key_p_1_ns, r1\n"
"ldr r1,[%0,#8]\n"
"msr pac_key_p_2_ns, r1\n"
"ldr r1,[%0,#12]\n"
"msr pac_key_p_3_ns, r1\n"
: : "r" (pPacKey) : "memory", "r1"
);
}
/**
\brief read the PAC key used for unprivileged mode (non-secure)
\details Reads the PAC key stored in the non-secure PAC_KEY_U registers when in secure mode.
\param [out] pPacKey 128bit PAC key
*/
__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_U_NS (uint32_t* pPacKey) {
__ASM volatile (
"mrs r1, pac_key_u_0_ns\n"
"str r1,[%0,#0]\n"
"mrs r1, pac_key_u_1_ns\n"
"str r1,[%0,#4]\n"
"mrs r1, pac_key_u_2_ns\n"
"str r1,[%0,#8]\n"
"mrs r1, pac_key_u_3_ns\n"
"str r1,[%0,#12]\n"
: : "r" (pPacKey) : "memory", "r1"
);
}
/**
\brief write the PAC key used for unprivileged mode (non-secure)
\details writes the given PAC key to the non-secure PAC_KEY_U registers when in secure mode.
\param [in] pPacKey 128bit PAC key
*/
__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_U_NS (uint32_t* pPacKey) {
__ASM volatile (
"ldr r1,[%0,#0]\n"
"msr pac_key_u_0_ns, r1\n"
"ldr r1,[%0,#4]\n"
"msr pac_key_u_1_ns, r1\n"
"ldr r1,[%0,#8]\n"
"msr pac_key_u_2_ns, r1\n"
"ldr r1,[%0,#12]\n"
"msr pac_key_u_3_ns, r1\n"
: : "r" (pPacKey) : "memory", "r1"
);
}
#endif /* (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) */
#endif /* (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) */
/*@} end of CMSIS_Core_PacKeyFunctions */
#endif /* PAC_ARMV81_H */

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/******************************************************************************
* @file pmu_armv8.h
* @brief CMSIS PMU API for Armv8.1-M PMU
* @version V1.0.1
* @date 15. April 2020
******************************************************************************/
/*
* Copyright (c) 2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_PMU_ARMV8_H
#define ARM_PMU_ARMV8_H
/**
* \brief PMU Events
* \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events.
* */
#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */
#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */
#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */
#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */
#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */
#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */
#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */
#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */
#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */
#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */
#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */
#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */
#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */
#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */
#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */
#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */
#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */
#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */
#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */
#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */
#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */
#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */
#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */
#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */
#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */
#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */
#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */
#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */
#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */
#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */
#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */
#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */
#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */
#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */
#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */
#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */
#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */
#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */
#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */
#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */
#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */
#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */
#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */
#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */
#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */
#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */
#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */
#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */
#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */
#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */
#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */
#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */
#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */
#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */
#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */
#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */
#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */
#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */
#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */
#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */
#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */
#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */
#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */
#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */
#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */
#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */
#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */
#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */
#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */
#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */
#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */
#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */
#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */
#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */
#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */
#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */
#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */
#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */
#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */
#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */
#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */
#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */
#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */
#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */
#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */
#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */
#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */
#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */
#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */
#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */
#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */
#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */
#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */
#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */
#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */
#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */
#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */
#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */
#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */
#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */
#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */
#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */
#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */
#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */
#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */
#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */
#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */
#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */
#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */
#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */
#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */
#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */
#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */
#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */
#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */
#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */
#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */
#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */
#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */
#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */
#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */
#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */
#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */
#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */
#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */
#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */
#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */
#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */
#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */
#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */
#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */
/** \brief PMU Functions */
__STATIC_INLINE void ARM_PMU_Enable(void);
__STATIC_INLINE void ARM_PMU_Disable(void);
__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type);
__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void);
__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void);
__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask);
__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask);
__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void);
__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num);
__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void);
__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask);
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask);
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask);
__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask);
/**
\brief Enable the PMU
*/
__STATIC_INLINE void ARM_PMU_Enable(void)
{
PMU->CTRL |= PMU_CTRL_ENABLE_Msk;
}
/**
\brief Disable the PMU
*/
__STATIC_INLINE void ARM_PMU_Disable(void)
{
PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk;
}
/**
\brief Set event to count for PMU eventer counter
\param [in] num Event counter (0-30) to configure
\param [in] type Event to count
*/
__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type)
{
PMU->EVTYPER[num] = type;
}
/**
\brief Reset cycle counter
*/
__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void)
{
PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk;
}
/**
\brief Reset all event counters
*/
__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void)
{
PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk;
}
/**
\brief Enable counters
\param [in] mask Counters to enable
\note Enables one or more of the following:
- event counters (0-30)
- cycle counter
*/
__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask)
{
PMU->CNTENSET = mask;
}
/**
\brief Disable counters
\param [in] mask Counters to enable
\note Disables one or more of the following:
- event counters (0-30)
- cycle counter
*/
__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask)
{
PMU->CNTENCLR = mask;
}
/**
\brief Read cycle counter
\return Cycle count
*/
__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void)
{
return PMU->CCNTR;
}
/**
\brief Read event counter
\param [in] num Event counter (0-30) to read
\return Event count
*/
__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num)
{
return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num];
}
/**
\brief Read counter overflow status
\return Counter overflow status bits for the following:
- event counters (0-30)
- cycle counter
*/
__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void)
{
return PMU->OVSSET;
}
/**
\brief Clear counter overflow status
\param [in] mask Counter overflow status bits to clear
\note Clears overflow status bits for one or more of the following:
- event counters (0-30)
- cycle counter
*/
__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask)
{
PMU->OVSCLR = mask;
}
/**
\brief Enable counter overflow interrupt request
\param [in] mask Counter overflow interrupt request bits to set
\note Sets overflow interrupt request bits for one or more of the following:
- event counters (0-30)
- cycle counter
*/
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask)
{
PMU->INTENSET = mask;
}
/**
\brief Disable counter overflow interrupt request
\param [in] mask Counter overflow interrupt request bits to clear
\note Clears overflow interrupt request bits for one or more of the following:
- event counters (0-30)
- cycle counter
*/
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask)
{
PMU->INTENCLR = mask;
}
/**
\brief Software increment event counter
\param [in] mask Counters to increment
\note Software increment bits for one or more event counters (0-30)
*/
__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask)
{
PMU->SWINC = mask;
}
#endif

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/******************************************************************************
* @file tz_context.h
* @brief Context Management for Armv8-M TrustZone
* @version V1.0.1
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef TZ_CONTEXT_H
#define TZ_CONTEXT_H
#include <stdint.h>
#ifndef TZ_MODULEID_T
#define TZ_MODULEID_T
/// \details Data type that identifies secure software modules called by a process.
typedef uint32_t TZ_ModuleId_t;
#endif
/// \details TZ Memory ID identifies an allocated memory slot.
typedef uint32_t TZ_MemoryId_t;
/// Initialize secure context memory system
/// \return execution status (1: success, 0: error)
uint32_t TZ_InitContextSystem_S (void);
/// Allocate context memory for calling secure software modules in TrustZone
/// \param[in] module identifies software modules called from non-secure mode
/// \return value != 0 id TrustZone memory slot identifier
/// \return value 0 no memory available or internal error
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
/// Load secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
/// Store secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
#endif // TZ_CONTEXT_H

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Apache License
Version 2.0, January 2004
http://www.apache.org/licenses/
TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
1. Definitions.
"License" shall mean the terms and conditions for use, reproduction,
and distribution as defined by Sections 1 through 9 of this document.
"Licensor" shall mean the copyright owner or entity authorized by
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/***********************************************************************************************************************
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @ingroup BOARDS
* @defgroup BOARD_RA8M1_EK for the RA8M1-EK board
* @brief BSP for the RA8M1-EK Board
*
* The RA8M1_EK is a development kit for the Renesas R7FA8M1AHDCBD microcontroller in a BGA224 package.
*
* @{
**********************************************************************************************************************/
#ifndef BOARD_H
#define BOARD_H
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
/* BSP Board Specific Includes. */
#include "board_init.h"
#include "board_leds.h"
#include "board_ethernet_phy.h"
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#define BOARD_RA8M1_EK
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
/** @} (end defgroup BOARD_RA8M1_EK) */
#endif

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/***********************************************************************************************************************
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @ingroup BOARD_RA8M1_EK
* @defgroup BOARD_RA8M1_EK_ETHERNET_PHY Board Ethernet Phy
* @brief Ethernet Phy information for this board.
*
* This is code specific to the RA8M1_EK board.
*
* @{
**********************************************************************************************************************/
#ifndef BSP_ETHERNET_PHY_H
#define BSP_ETHERNET_PHY_H
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#define ETHER_PHY_CFG_TARGET_ICS1894_ENABLE (1)
#define ETHER_PHY_LSI_TYPE_KIT_COMPONENT ETHER_PHY_LSI_TYPE_ICS1894
#define BOARD_PHY_REF_CLK (1)
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Public Functions
**********************************************************************************************************************/
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif
/** @} (end defgroup BOARD_RA8M1_EK_ETHERNET_PHY) */

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/***********************************************************************************************************************
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @addtogroup BOARD_RA8M1_EK
*
* @{
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
#include "bsp_api.h"
#if defined(BOARD_RA8M1_EK)
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
/***********************************************************************************************************************
* Private global variables and functions
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @brief Performs any initialization specific to this BSP.
*
* @param[in] p_args Pointer to arguments of the user's choice.
**********************************************************************************************************************/
void bsp_init (void * p_args)
{
FSP_PARAMETER_NOT_USED(p_args);
}
#endif
/** @} (end addtogroup BOARD_RA8M1_EK) */

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/***********************************************************************************************************************
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @addtogroup BOARD_RA8M1_EK
* @brief Board specific code for the RA8M1-EK Board
*
* This include file is specific to the RA8M1-EK board.
*
* @{
**********************************************************************************************************************/
#ifndef BOARD_INIT_H
#define BOARD_INIT_H
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
void bsp_init(void * p_args);
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif
/** @} (end addtogroup BOARD_RA8M1_EK) */

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/***********************************************************************************************************************
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @addtogroup BOARD_RA8M1_EK_LEDS
*
* @{
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
#include "bsp_api.h"
#if defined(BOARD_RA8M1_EK)
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Private global variables and functions
**********************************************************************************************************************/
/** Array of LED IOPORT pins. */
static const uint16_t g_bsp_prv_leds[] =
{
(uint16_t) BSP_IO_PORT_06_PIN_00, ///< LED1
(uint16_t) BSP_IO_PORT_04_PIN_14, ///< LED2
(uint16_t) BSP_IO_PORT_01_PIN_07, ///< LED3
};
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
/** Structure with LED information for this board. */
const bsp_leds_t g_bsp_leds =
{
.led_count = (uint16_t) ((sizeof(g_bsp_prv_leds) / sizeof(g_bsp_prv_leds[0]))),
.p_leds = &g_bsp_prv_leds[0]
};
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
#endif
/** @} (end addtogroup BOARD_RA8M1_EK_LEDS) */

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/***********************************************************************************************************************
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @ingroup BOARD_RA8M1_EK
* @defgroup BOARD_RA8M1_EK_LEDS Board LEDs
* @brief LED information for this board.
*
* This is code specific to the EK board. It includes info on the number of LEDs and which pins are they
* are on.
*
* @{
**********************************************************************************************************************/
#ifndef BOARD_LEDS_H
#define BOARD_LEDS_H
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** Information on how many LEDs and what pins they are on. */
typedef struct st_bsp_leds
{
uint16_t led_count; ///< The number of LEDs on this board
uint16_t const * p_leds; ///< Pointer to an array of IOPORT pins for controlling LEDs
} bsp_leds_t;
/** Available user-controllable LEDs on this board. These enums can be can be used to index into the array of LED pins
* found in the bsp_leds_t structure. */
typedef enum e_bsp_led
{
BSP_LED_LED1, ///< LED1
BSP_LED_LED2, ///< LED2
BSP_LED_LED3, ///< LED3
} bsp_led_t;
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Public Functions
**********************************************************************************************************************/
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif
/** @} (end defgroup BOARD_RA8M1_EK_LEDS) */

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/***********************************************************************************************************************
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef BSP_API_H
#define BSP_API_H
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
/* FSP Common Includes. */
#include "fsp_common_api.h"
/* Gets MCU configuration information. */
#include "bsp_cfg.h"
#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
/* Store warning settings for 'conversion' and 'sign-conversion' to as specified on command line. */
#pragma GCC diagnostic push
/* CMSIS-CORE currently generates 2 warnings when compiling with GCC. One in core_cmInstr.h and one in core_cm4_simd.h.
* We are not modifying these files so we will ignore these warnings temporarily. */
#pragma GCC diagnostic ignored "-Wconversion"
#pragma GCC diagnostic ignored "-Wsign-conversion"
#endif
/* Vector information for this project. This is generated by the tooling. */
#include "../../src/bsp/mcu/all/bsp_exceptions.h"
#include "vector_data.h"
/* CMSIS-CORE Renesas Device Files. Must come after bsp_feature.h, which is included in bsp_cfg.h. */
#include "../../src/bsp/cmsis/Device/RENESAS/Include/renesas.h"
#include "../../src/bsp/cmsis/Device/RENESAS/Include/system.h"
#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
/* Restore warning settings for 'conversion' and 'sign-conversion' to as specified on command line. */
#pragma GCC diagnostic pop
#endif
#if defined(BSP_API_OVERRIDE)
#include BSP_API_OVERRIDE
#else
/* BSP Common Includes. */
#include "../../src/bsp/mcu/all/bsp_common.h"
/* BSP MCU Specific Includes. */
#include "../../src/bsp/mcu/all/bsp_register_protection.h"
#include "../../src/bsp/mcu/all/bsp_irq.h"
#include "../../src/bsp/mcu/all/bsp_io.h"
#include "../../src/bsp/mcu/all/bsp_group_irq.h"
#include "../../src/bsp/mcu/all/bsp_clocks.h"
#include "../../src/bsp/mcu/all/bsp_module_stop.h"
#include "../../src/bsp/mcu/all/bsp_security.h"
/* Factory MCU information. */
#include "../../inc/fsp_features.h"
/* BSP Common Includes (Other than bsp_common.h) */
#include "../../src/bsp/mcu/all/bsp_delay.h"
#include "../../src/bsp/mcu/all/bsp_mcu_api.h"
#endif
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
**********************************************************************************************************************/
fsp_err_t R_FSP_VersionGet(fsp_pack_version_t * const p_version);
/** @} (end addtogroup BSP_MCU) */
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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/***********************************************************************************************************************
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef FSP_COMMON_API_H
#define FSP_COMMON_API_H
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
#include <assert.h>
#include <stdint.h>
/* Includes FSP version macros. */
#include "fsp_version.h"
/*******************************************************************************************************************//**
* @ingroup RENESAS_COMMON
* @defgroup RENESAS_ERROR_CODES Common Error Codes
* All FSP modules share these common error codes.
* @{
**********************************************************************************************************************/
/**********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/** This macro is used to suppress compiler messages about a parameter not being used in a function. The nice thing
* about using this implementation is that it does not take any extra RAM or ROM. */
#define FSP_PARAMETER_NOT_USED(p) (void) ((p))
/** Determine if a C++ compiler is being used.
* If so, ensure that standard C is used to process the API information. */
#if defined(__cplusplus)
#define FSP_CPP_HEADER extern "C" {
#define FSP_CPP_FOOTER }
#else
#define FSP_CPP_HEADER
#define FSP_CPP_FOOTER
#endif
/** FSP Header and Footer definitions */
#define FSP_HEADER FSP_CPP_HEADER
#define FSP_FOOTER FSP_CPP_FOOTER
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/** Macro to be used when argument to function is ignored since function call is NSC and the parameter is statically
* defined on the Secure side. */
#define FSP_SECURE_ARGUMENT (NULL)
/**********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** Common error codes */
typedef enum e_fsp_err
{
FSP_SUCCESS = 0,
FSP_ERR_ASSERTION = 1, ///< A critical assertion has failed
FSP_ERR_INVALID_POINTER = 2, ///< Pointer points to invalid memory location
FSP_ERR_INVALID_ARGUMENT = 3, ///< Invalid input parameter
FSP_ERR_INVALID_CHANNEL = 4, ///< Selected channel does not exist
FSP_ERR_INVALID_MODE = 5, ///< Unsupported or incorrect mode
FSP_ERR_UNSUPPORTED = 6, ///< Selected mode not supported by this API
FSP_ERR_NOT_OPEN = 7, ///< Requested channel is not configured or API not open
FSP_ERR_IN_USE = 8, ///< Channel/peripheral is running/busy
FSP_ERR_OUT_OF_MEMORY = 9, ///< Allocate more memory in the driver's cfg.h
FSP_ERR_HW_LOCKED = 10, ///< Hardware is locked
FSP_ERR_IRQ_BSP_DISABLED = 11, ///< IRQ not enabled in BSP
FSP_ERR_OVERFLOW = 12, ///< Hardware overflow
FSP_ERR_UNDERFLOW = 13, ///< Hardware underflow
FSP_ERR_ALREADY_OPEN = 14, ///< Requested channel is already open in a different configuration
FSP_ERR_APPROXIMATION = 15, ///< Could not set value to exact result
FSP_ERR_CLAMPED = 16, ///< Value had to be limited for some reason
FSP_ERR_INVALID_RATE = 17, ///< Selected rate could not be met
FSP_ERR_ABORTED = 18, ///< An operation was aborted
FSP_ERR_NOT_ENABLED = 19, ///< Requested operation is not enabled
FSP_ERR_TIMEOUT = 20, ///< Timeout error
FSP_ERR_INVALID_BLOCKS = 21, ///< Invalid number of blocks supplied
FSP_ERR_INVALID_ADDRESS = 22, ///< Invalid address supplied
FSP_ERR_INVALID_SIZE = 23, ///< Invalid size/length supplied for operation
FSP_ERR_WRITE_FAILED = 24, ///< Write operation failed
FSP_ERR_ERASE_FAILED = 25, ///< Erase operation failed
FSP_ERR_INVALID_CALL = 26, ///< Invalid function call is made
FSP_ERR_INVALID_HW_CONDITION = 27, ///< Detected hardware is in invalid condition
FSP_ERR_INVALID_FACTORY_FLASH = 28, ///< Factory flash is not available on this MCU
FSP_ERR_INVALID_STATE = 30, ///< API or command not valid in the current state
FSP_ERR_NOT_ERASED = 31, ///< Erase verification failed
FSP_ERR_SECTOR_RELEASE_FAILED = 32, ///< Sector release failed
FSP_ERR_NOT_INITIALIZED = 33, ///< Required initialization not complete
FSP_ERR_NOT_FOUND = 34, ///< The requested item could not be found
FSP_ERR_NO_CALLBACK_MEMORY = 35, ///< Non-secure callback memory not provided for non-secure callback
FSP_ERR_BUFFER_EMPTY = 36, ///< No data available in buffer
FSP_ERR_INVALID_DATA = 37, ///< Accuracy of data is not guaranteed
/* Start of RTOS only error codes */
FSP_ERR_INTERNAL = 100, ///< Internal error
FSP_ERR_WAIT_ABORTED = 101, ///< Wait aborted
/* Start of UART specific */
FSP_ERR_FRAMING = 200, ///< Framing error occurs
FSP_ERR_BREAK_DETECT = 201, ///< Break signal detects
FSP_ERR_PARITY = 202, ///< Parity error occurs
FSP_ERR_RXBUF_OVERFLOW = 203, ///< Receive queue overflow
FSP_ERR_QUEUE_UNAVAILABLE = 204, ///< Can't open s/w queue
FSP_ERR_INSUFFICIENT_SPACE = 205, ///< Not enough space in transmission circular buffer
FSP_ERR_INSUFFICIENT_DATA = 206, ///< Not enough data in receive circular buffer
/* Start of SPI specific */
FSP_ERR_TRANSFER_ABORTED = 300, ///< The data transfer was aborted.
FSP_ERR_MODE_FAULT = 301, ///< Mode fault error.
FSP_ERR_READ_OVERFLOW = 302, ///< Read overflow.
FSP_ERR_SPI_PARITY = 303, ///< Parity error.
FSP_ERR_OVERRUN = 304, ///< Overrun error.
/* Start of CGC Specific */
FSP_ERR_CLOCK_INACTIVE = 400, ///< Inactive clock specified as system clock.
FSP_ERR_CLOCK_ACTIVE = 401, ///< Active clock source cannot be modified without stopping first.
FSP_ERR_NOT_STABILIZED = 403, ///< Clock has not stabilized after its been turned on/off
FSP_ERR_PLL_SRC_INACTIVE = 404, ///< PLL initialization attempted when PLL source is turned off
FSP_ERR_OSC_STOP_DET_ENABLED = 405, ///< Illegal attempt to stop LOCO when Oscillation stop is enabled
FSP_ERR_OSC_STOP_DETECTED = 406, ///< The Oscillation stop detection status flag is set
FSP_ERR_OSC_STOP_CLOCK_ACTIVE = 407, ///< Attempt to clear Oscillation Stop Detect Status with PLL/MAIN_OSC active
FSP_ERR_CLKOUT_EXCEEDED = 408, ///< Output on target output clock pin exceeds maximum supported limit
FSP_ERR_USB_MODULE_ENABLED = 409, ///< USB clock configure request with USB Module enabled
FSP_ERR_HARDWARE_TIMEOUT = 410, ///< A register read or write timed out
FSP_ERR_LOW_VOLTAGE_MODE = 411, ///< Invalid clock setting attempted in low voltage mode
/* Start of FLASH Specific */
FSP_ERR_PE_FAILURE = 500, ///< Unable to enter Programming mode.
FSP_ERR_CMD_LOCKED = 501, ///< Peripheral in command locked state
FSP_ERR_FCLK = 502, ///< FCLK must be >= 4 MHz
FSP_ERR_INVALID_LINKED_ADDRESS = 503, ///< Function or data are linked at an invalid region of memory
FSP_ERR_BLANK_CHECK_FAILED = 504, ///< Blank check operation failed
/* Start of CAC Specific */
FSP_ERR_INVALID_CAC_REF_CLOCK = 600, ///< Measured clock rate < reference clock rate
/* Start of IIRFA Specific */
FSP_ERR_INVALID_RESULT = 700, ///< The result of one or more calculations was +/- infinity.
/* Start of GLCD Specific */
FSP_ERR_CLOCK_GENERATION = 1000, ///< Clock cannot be specified as system clock
FSP_ERR_INVALID_TIMING_SETTING = 1001, ///< Invalid timing parameter
FSP_ERR_INVALID_LAYER_SETTING = 1002, ///< Invalid layer parameter
FSP_ERR_INVALID_ALIGNMENT = 1003, ///< Invalid memory alignment found
FSP_ERR_INVALID_GAMMA_SETTING = 1004, ///< Invalid gamma correction parameter
FSP_ERR_INVALID_LAYER_FORMAT = 1005, ///< Invalid color format in layer
FSP_ERR_INVALID_UPDATE_TIMING = 1006, ///< Invalid timing for register update
FSP_ERR_INVALID_CLUT_ACCESS = 1007, ///< Invalid access to CLUT entry
FSP_ERR_INVALID_FADE_SETTING = 1008, ///< Invalid fade-in/fade-out setting
FSP_ERR_INVALID_BRIGHTNESS_SETTING = 1009, ///< Invalid gamma correction parameter
/* Start of JPEG Specific */
FSP_ERR_JPEG_ERR = 1100, ///< JPEG error
FSP_ERR_JPEG_SOI_NOT_DETECTED = 1101, ///< SOI not detected until EOI detected.
FSP_ERR_JPEG_SOF1_TO_SOFF_DETECTED = 1102, ///< SOF1 to SOFF detected.
FSP_ERR_JPEG_UNSUPPORTED_PIXEL_FORMAT = 1103, ///< Unprovided pixel format detected.
FSP_ERR_JPEG_SOF_ACCURACY_ERROR = 1104, ///< SOF accuracy error: other than 8 detected.
FSP_ERR_JPEG_DQT_ACCURACY_ERROR = 1105, ///< DQT accuracy error: other than 0 detected.
FSP_ERR_JPEG_COMPONENT_ERROR1 = 1106, ///< Component error 1: the number of SOF0 header components detected is other than 1, 3, or 4.
FSP_ERR_JPEG_COMPONENT_ERROR2 = 1107, ///< Component error 2: the number of components differs between SOF0 header and SOS.
FSP_ERR_JPEG_SOF0_DQT_DHT_NOT_DETECTED = 1108, ///< SOF0, DQT, and DHT not detected when SOS detected.
FSP_ERR_JPEG_SOS_NOT_DETECTED = 1109, ///< SOS not detected: SOS not detected until EOI detected.
FSP_ERR_JPEG_EOI_NOT_DETECTED = 1110, ///< EOI not detected (default)
FSP_ERR_JPEG_RESTART_INTERVAL_DATA_NUMBER_ERROR = 1111, ///< Restart interval data number error detected.
FSP_ERR_JPEG_IMAGE_SIZE_ERROR = 1112, ///< Image size error detected.
FSP_ERR_JPEG_LAST_MCU_DATA_NUMBER_ERROR = 1113, ///< Last MCU data number error detected.
FSP_ERR_JPEG_BLOCK_DATA_NUMBER_ERROR = 1114, ///< Block data number error detected.
FSP_ERR_JPEG_BUFFERSIZE_NOT_ENOUGH = 1115, ///< User provided buffer size not enough
FSP_ERR_JPEG_UNSUPPORTED_IMAGE_SIZE = 1116, ///< JPEG Image size is not aligned with MCU
/* Start of touch panel framework specific */
FSP_ERR_CALIBRATE_FAILED = 1200, ///< Calibration failed
/* Start of IIRFA specific */
FSP_ERR_IIRFA_ECC_1BIT = 1300, ///< 1-bit ECC error detected
FSP_ERR_IIRFA_ECC_2BIT = 1301, ///< 2-bit ECC error detected
/* Start of IP specific */
FSP_ERR_IP_HARDWARE_NOT_PRESENT = 1400, ///< Requested IP does not exist on this device
FSP_ERR_IP_UNIT_NOT_PRESENT = 1401, ///< Requested unit does not exist on this device
FSP_ERR_IP_CHANNEL_NOT_PRESENT = 1402, ///< Requested channel does not exist on this device
/* Start of USB specific */
FSP_ERR_USB_FAILED = 1500,
FSP_ERR_USB_BUSY = 1501,
FSP_ERR_USB_SIZE_SHORT = 1502,
FSP_ERR_USB_SIZE_OVER = 1503,
FSP_ERR_USB_NOT_OPEN = 1504,
FSP_ERR_USB_NOT_SUSPEND = 1505,
FSP_ERR_USB_PARAMETER = 1506,
/* Start of Message framework specific */
FSP_ERR_NO_MORE_BUFFER = 2000, ///< No more buffer found in the memory block pool
FSP_ERR_ILLEGAL_BUFFER_ADDRESS = 2001, ///< Buffer address is out of block memory pool
FSP_ERR_INVALID_WORKBUFFER_SIZE = 2002, ///< Work buffer size is invalid
FSP_ERR_INVALID_MSG_BUFFER_SIZE = 2003, ///< Message buffer size is invalid
FSP_ERR_TOO_MANY_BUFFERS = 2004, ///< Number of buffer is too many
FSP_ERR_NO_SUBSCRIBER_FOUND = 2005, ///< No message subscriber found
FSP_ERR_MESSAGE_QUEUE_EMPTY = 2006, ///< No message found in the message queue
FSP_ERR_MESSAGE_QUEUE_FULL = 2007, ///< No room for new message in the message queue
FSP_ERR_ILLEGAL_SUBSCRIBER_LISTS = 2008, ///< Message subscriber lists is illegal
FSP_ERR_BUFFER_RELEASED = 2009, ///< Buffer has been released
/* Start of 2DG Driver specific */
FSP_ERR_D2D_ERROR_INIT = 3000, ///< D/AVE 2D has an error in the initialization
FSP_ERR_D2D_ERROR_DEINIT = 3001, ///< D/AVE 2D has an error in the initialization
FSP_ERR_D2D_ERROR_RENDERING = 3002, ///< D/AVE 2D has an error in the rendering
FSP_ERR_D2D_ERROR_SIZE = 3003, ///< D/AVE 2D has an error in the rendering
/* Start of ETHER Driver specific */
FSP_ERR_ETHER_ERROR_NO_DATA = 4000, ///< No Data in Receive buffer.
FSP_ERR_ETHER_ERROR_LINK = 4001, ///< ETHERC/EDMAC has an error in the Auto-negotiation
FSP_ERR_ETHER_ERROR_MAGIC_PACKET_MODE = 4002, ///< As a Magic Packet is being detected, and transmission/reception is not enabled
FSP_ERR_ETHER_ERROR_TRANSMIT_BUFFER_FULL = 4003, ///< Transmit buffer is not empty
FSP_ERR_ETHER_ERROR_FILTERING = 4004, ///< Detect multicast frame when multicast frame filtering enable
FSP_ERR_ETHER_ERROR_PHY_COMMUNICATION = 4005, ///< ETHERC/EDMAC has an error in the phy communication
FSP_ERR_ETHER_RECEIVE_BUFFER_ACTIVE = 4006, ///< Receive buffer is active.
/* Start of ETHER_PHY Driver specific */
FSP_ERR_ETHER_PHY_ERROR_LINK = 5000, ///< PHY is not link up.
FSP_ERR_ETHER_PHY_NOT_READY = 5001, ///< PHY has an error in the Auto-negotiation
/* Start of BYTEQ library specific */
FSP_ERR_QUEUE_FULL = 10000, ///< Queue is full, cannot queue another data
FSP_ERR_QUEUE_EMPTY = 10001, ///< Queue is empty, no data to dequeue
/* Start of CTSU Driver specific */
FSP_ERR_CTSU_SCANNING = 6000, ///< Scanning.
FSP_ERR_CTSU_NOT_GET_DATA = 6001, ///< Not processed previous scan data.
FSP_ERR_CTSU_INCOMPLETE_TUNING = 6002, ///< Incomplete initial offset tuning.
FSP_ERR_CTSU_DIAG_NOT_YET = 6003, ///< Diagnosis of data collected no yet.
FSP_ERR_CTSU_DIAG_LDO_OVER_VOLTAGE = 6004, ///< Diagnosis of LDO over voltage failed.
FSP_ERR_CTSU_DIAG_CCO_HIGH = 6005, ///< Diagnosis of CCO into 19.2uA failed.
FSP_ERR_CTSU_DIAG_CCO_LOW = 6006, ///< Diagnosis of CCO into 2.4uA failed.
FSP_ERR_CTSU_DIAG_SSCG = 6007, ///< Diagnosis of SSCG frequency failed.
FSP_ERR_CTSU_DIAG_DAC = 6008, ///< Diagnosis of non-touch count value failed.
FSP_ERR_CTSU_DIAG_OUTPUT_VOLTAGE = 6009, ///< Diagnosis of LDO output voltage failed.
FSP_ERR_CTSU_DIAG_OVER_VOLTAGE = 6010, ///< Diagnosis of over voltage detection circuit failed.
FSP_ERR_CTSU_DIAG_OVER_CURRENT = 6011, ///< Diagnosis of over current detection circuit failed.
FSP_ERR_CTSU_DIAG_LOAD_RESISTANCE = 6012, ///< Diagnosis of LDO internal resistance value failed.
FSP_ERR_CTSU_DIAG_CURRENT_SOURCE = 6013, ///< Diagnosis of Current source value failed.
FSP_ERR_CTSU_DIAG_SENSCLK_GAIN = 6014, ///< Diagnosis of SENSCLK frequency gain failed.
FSP_ERR_CTSU_DIAG_SUCLK_GAIN = 6015, ///< Diagnosis of SUCLK frequency gain failed.
FSP_ERR_CTSU_DIAG_CLOCK_RECOVERY = 6016, ///< Diagnosis of SUCLK clock recovery function failed.
FSP_ERR_CTSU_DIAG_CFC_GAIN = 6017, ///< Diagnosis of CFC oscillator gain failed.
/* Start of SDMMC specific */
FSP_ERR_CARD_INIT_FAILED = 40000, ///< SD card or eMMC device failed to initialize.
FSP_ERR_CARD_NOT_INSERTED = 40001, ///< SD card not installed.
FSP_ERR_DEVICE_BUSY = 40002, ///< Device is holding DAT0 low or another operation is ongoing.
FSP_ERR_CARD_NOT_INITIALIZED = 40004, ///< SD card was removed.
FSP_ERR_CARD_WRITE_PROTECTED = 40005, ///< Media is write protected.
FSP_ERR_TRANSFER_BUSY = 40006, ///< Transfer in progress.
FSP_ERR_RESPONSE = 40007, ///< Card did not respond or responded with an error.
/* Start of FX_IO specific */
FSP_ERR_MEDIA_FORMAT_FAILED = 50000, ///< Media format failed.
FSP_ERR_MEDIA_OPEN_FAILED = 50001, ///< Media open failed.
/* Start of CAN specific */
FSP_ERR_CAN_DATA_UNAVAILABLE = 60000, ///< No data available.
FSP_ERR_CAN_MODE_SWITCH_FAILED = 60001, ///< Switching operation modes failed.
FSP_ERR_CAN_INIT_FAILED = 60002, ///< Hardware initialization failed.
FSP_ERR_CAN_TRANSMIT_NOT_READY = 60003, ///< Transmit in progress.
FSP_ERR_CAN_RECEIVE_MAILBOX = 60004, ///< Mailbox is setup as a receive mailbox.
FSP_ERR_CAN_TRANSMIT_MAILBOX = 60005, ///< Mailbox is setup as a transmit mailbox.
FSP_ERR_CAN_MESSAGE_LOST = 60006, ///< Receive message has been overwritten or overrun.
FSP_ERR_CAN_TRANSMIT_FIFO_FULL = 60007, ///< Transmit FIFO is full.
/* Start of SF_WIFI Specific */
FSP_ERR_WIFI_CONFIG_FAILED = 70000, ///< WiFi module Configuration failed.
FSP_ERR_WIFI_INIT_FAILED = 70001, ///< WiFi module initialization failed.
FSP_ERR_WIFI_TRANSMIT_FAILED = 70002, ///< Transmission failed
FSP_ERR_WIFI_INVALID_MODE = 70003, ///< API called when provisioned in client mode
FSP_ERR_WIFI_FAILED = 70004, ///< WiFi Failed.
FSP_ERR_WIFI_SCAN_COMPLETE = 70005, ///< Wifi scan has completed.
FSP_ERR_WIFI_AP_NOT_CONNECTED = 70006, ///< WiFi module is not connected to access point
FSP_ERR_WIFI_UNKNOWN_AT_CMD = 70007, ///< DA16200 Unknown AT command Error
FSP_ERR_WIFI_INSUF_PARAM = 70008, ///< DA16200 Insufficient parameter
FSP_ERR_WIFI_TOO_MANY_PARAMS = 70009, ///< DA16200 Too many parameters
FSP_ERR_WIFI_INV_PARAM_VAL = 70010, ///< DA16200 Wrong parameter value
FSP_ERR_WIFI_NO_RESULT = 70011, ///< DA16200 No result
FSP_ERR_WIFI_RSP_BUF_OVFLW = 70012, ///< DA16200 Response buffer overflow
FSP_ERR_WIFI_FUNC_NOT_CONFIG = 70013, ///< DA16200 Function is not configured
FSP_ERR_WIFI_NVRAM_WR_FAIL = 70014, ///< DA16200 NVRAM write failure
FSP_ERR_WIFI_RET_MEM_WR_FAIL = 70015, ///< DA16200 Retention memory write failure
FSP_ERR_WIFI_UNKNOWN_ERR = 70016, ///< DA16200 unknown error
/* Start of SF_CELLULAR Specific */
FSP_ERR_CELLULAR_CONFIG_FAILED = 80000, ///< Cellular module Configuration failed.
FSP_ERR_CELLULAR_INIT_FAILED = 80001, ///< Cellular module initialization failed.
FSP_ERR_CELLULAR_TRANSMIT_FAILED = 80002, ///< Transmission failed
FSP_ERR_CELLULAR_FW_UPTODATE = 80003, ///< Firmware is uptodate
FSP_ERR_CELLULAR_FW_UPGRADE_FAILED = 80004, ///< Firmware upgrade failed
FSP_ERR_CELLULAR_FAILED = 80005, ///< Cellular Failed.
FSP_ERR_CELLULAR_INVALID_STATE = 80006, ///< API Called in invalid state.
FSP_ERR_CELLULAR_REGISTRATION_FAILED = 80007, ///< Cellular Network registration failed
/* Start of SF_BLE specific */
FSP_ERR_BLE_FAILED = 90001, ///< BLE operation failed
FSP_ERR_BLE_INIT_FAILED = 90002, ///< BLE device initialization failed
FSP_ERR_BLE_CONFIG_FAILED = 90003, ///< BLE device configuration failed
FSP_ERR_BLE_PRF_ALREADY_ENABLED = 90004, ///< BLE device Profile already enabled
FSP_ERR_BLE_PRF_NOT_ENABLED = 90005, ///< BLE device not enabled
/* Start of SF_BLE_ABS specific */
FSP_ERR_BLE_ABS_INVALID_OPERATION = 91001, ///< Invalid operation is executed.
FSP_ERR_BLE_ABS_NOT_FOUND = 91002, ///< Valid data or free space is not found.
/* Start of Crypto specific (0x10000) @note Refer to sf_cryoto_err.h for Crypto error code. */
FSP_ERR_CRYPTO_CONTINUE = 0x10000, ///< Continue executing function
FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT = 0x10001, ///< Hardware resource busy
FSP_ERR_CRYPTO_SCE_FAIL = 0x10002, ///< Internal I/O buffer is not empty
FSP_ERR_CRYPTO_SCE_HRK_INVALID_INDEX = 0x10003, ///< Invalid index
FSP_ERR_CRYPTO_SCE_RETRY = 0x10004, ///< Retry
FSP_ERR_CRYPTO_SCE_VERIFY_FAIL = 0x10005, ///< Verify is failed
FSP_ERR_CRYPTO_SCE_ALREADY_OPEN = 0x10006, ///< HW SCE module is already opened
FSP_ERR_CRYPTO_NOT_OPEN = 0x10007, ///< Hardware module is not initialized
FSP_ERR_CRYPTO_UNKNOWN = 0x10008, ///< Some unknown error occurred
FSP_ERR_CRYPTO_NULL_POINTER = 0x10009, ///< Null pointer input as a parameter
FSP_ERR_CRYPTO_NOT_IMPLEMENTED = 0x1000a, ///< Algorithm/size not implemented
FSP_ERR_CRYPTO_RNG_INVALID_PARAM = 0x1000b, ///< An invalid parameter is specified
FSP_ERR_CRYPTO_RNG_FATAL_ERROR = 0x1000c, ///< A fatal error occurred
FSP_ERR_CRYPTO_INVALID_SIZE = 0x1000d, ///< Size specified is invalid
FSP_ERR_CRYPTO_INVALID_STATE = 0x1000e, ///< Function used in an valid state
FSP_ERR_CRYPTO_ALREADY_OPEN = 0x1000f, ///< control block is already opened
FSP_ERR_CRYPTO_INSTALL_KEY_FAILED = 0x10010, ///< Specified input key is invalid.
FSP_ERR_CRYPTO_AUTHENTICATION_FAILED = 0x10011, ///< Authentication failed
FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL = 0x10012, ///< Failure to Init Cipher
FSP_ERR_CRYPTO_SCE_AUTHENTICATION = 0x10013, ///< Authentication failed
FSP_ERR_CRYPTO_SCE_PARAMETER = 0x10014, ///< Input date is illegal.
FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION = 0x10015, ///< An invalid function call occurred.
/* Start of SF_CRYPTO specific */
FSP_ERR_CRYPTO_COMMON_NOT_OPENED = 0x20000, ///< Crypto Framework Common is not opened
FSP_ERR_CRYPTO_HAL_ERROR = 0x20001, ///< Cryoto HAL module returned an error
FSP_ERR_CRYPTO_KEY_BUF_NOT_ENOUGH = 0x20002, ///< Key buffer size is not enough to generate a key
FSP_ERR_CRYPTO_BUF_OVERFLOW = 0x20003, ///< Attempt to write data larger than what the buffer can hold
FSP_ERR_CRYPTO_INVALID_OPERATION_MODE = 0x20004, ///< Invalid operation mode.
FSP_ERR_MESSAGE_TOO_LONG = 0x20005, ///< Message for RSA encryption is too long.
FSP_ERR_RSA_DECRYPTION_ERROR = 0x20006, ///< RSA Decryption error.
/** @note SF_CRYPTO APIs may return an error code starting from 0x10000 which is of Crypto module.
* Refer to sf_cryoto_err.h for Crypto error codes.
*/
/* Start of Sensor specific */
FSP_ERR_SENSOR_INVALID_DATA = 0x30000, ///< Data is invalid.
FSP_ERR_SENSOR_IN_STABILIZATION = 0x30001, ///< Sensor is stabilizing.
FSP_ERR_SENSOR_MEASUREMENT_NOT_FINISHED = 0x30002, ///< Measurement is not finished.
/* Start of COMMS specific */
FSP_ERR_COMMS_BUS_NOT_OPEN = 0x40000, ///< Bus is not open.
} fsp_err_t;
/** @} */
/***********************************************************************************************************************
* Function prototypes
**********************************************************************************************************************/
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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/***********************************************************************************************************************
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @ingroup RENESAS_INTERFACES
* @defgroup IOPORT_API I/O Port Interface
* @brief Interface for accessing I/O ports and configuring I/O functionality.
*
* @section IOPORT_API_SUMMARY Summary
* The IOPort shared interface provides the ability to access the IOPorts of a device at both bit and port level.
* Port and pin direction can be changed.
*
*
* @{
**********************************************************************************************************************/
#ifndef R_IOPORT_API_H
#define R_IOPORT_API_H
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
/* Common error codes and definitions. */
#include "bsp_api.h"
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/**********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/**********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
#ifndef BSP_OVERRIDE_IOPORT_SIZE_T
/** IO port type used with ports */
typedef uint16_t ioport_size_t; ///< IO port size
#endif
/** Pin identifier and pin configuration value */
typedef struct st_ioport_pin_cfg
{
uint32_t pin_cfg; ///< Pin configuration - Use ioport_cfg_options_t parameters to configure
bsp_io_port_pin_t pin; ///< Pin identifier
} ioport_pin_cfg_t;
/** Multiple pin configuration data for loading into registers by R_IOPORT_Open() */
typedef struct st_ioport_cfg
{
uint16_t number_of_pins; ///< Number of pins for which there is configuration data
ioport_pin_cfg_t const * p_pin_cfg_data; ///< Pin configuration data
const void * p_extend; ///< Pointer to hardware extend configuration
} ioport_cfg_t;
/** IOPORT control block. Allocate an instance specific control block to pass into the IOPORT API calls.
*/
typedef void ioport_ctrl_t;
/** IOPort driver structure. IOPort functions implemented at the HAL layer will follow this API. */
typedef struct st_ioport_api
{
/** Initialize internal driver data and initial pin configurations. Called during startup. Do
* not call this API during runtime. Use @ref ioport_api_t::pinsCfg for runtime reconfiguration of
* multiple pins.
*
* @param[in] p_ctrl Pointer to control structure. Must be declared by user. Elements set here.
* @param[in] p_cfg Pointer to pin configuration data array.
*/
fsp_err_t (* open)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg);
/** Close the API.
*
* @param[in] p_ctrl Pointer to control structure.
**/
fsp_err_t (* close)(ioport_ctrl_t * const p_ctrl);
/** Configure multiple pins.
*
* @param[in] p_ctrl Pointer to control structure.
* @param[in] p_cfg Pointer to pin configuration data array.
*/
fsp_err_t (* pinsCfg)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg);
/** Configure settings for an individual pin.
*
* @param[in] p_ctrl Pointer to control structure.
* @param[in] pin Pin to be read.
* @param[in] cfg Configuration options for the pin.
*/
fsp_err_t (* pinCfg)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg);
/** Read the event input data of the specified pin and return the level.
*
* @param[in] p_ctrl Pointer to control structure.
* @param[in] pin Pin to be read.
* @param[in] p_pin_event Pointer to return the event data.
*/
fsp_err_t (* pinEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event);
/** Write pin event data.
*
* @param[in] p_ctrl Pointer to control structure.
* @param[in] pin Pin event data is to be written to.
* @param[in] pin_value Level to be written to pin output event.
*/
fsp_err_t (* pinEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value);
/** Read level of a pin.
*
* @param[in] p_ctrl Pointer to control structure.
* @param[in] pin Pin to be read.
* @param[in] p_pin_value Pointer to return the pin level.
*/
fsp_err_t (* pinRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value);
/** Write specified level to a pin.
*
* @param[in] p_ctrl Pointer to control structure.
* @param[in] pin Pin to be written to.
* @param[in] level State to be written to the pin.
*/
fsp_err_t (* pinWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level);
/** Set the direction of one or more pins on a port.
*
* @param[in] p_ctrl Pointer to control structure.
* @param[in] port Port being configured.
* @param[in] direction_values Value controlling direction of pins on port.
* @param[in] mask Mask controlling which pins on the port are to be configured.
*/
fsp_err_t (* portDirectionSet)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t direction_values,
ioport_size_t mask);
/** Read captured event data for a port.
*
* @param[in] p_ctrl Pointer to control structure.
* @param[in] port Port to be read.
* @param[in] p_event_data Pointer to return the event data.
*/
fsp_err_t (* portEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_event_data);
/** Write event output data for a port.
*
* @param[in] p_ctrl Pointer to control structure.
* @param[in] port Port event data will be written to.
* @param[in] event_data Data to be written as event data to specified port.
* @param[in] mask_value Each bit set to 1 in the mask corresponds to that bit's value in event data.
* being written to port.
*/
fsp_err_t (* portEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t event_data,
ioport_size_t mask_value);
/** Read states of pins on the specified port.
*
* @param[in] p_ctrl Pointer to control structure.
* @param[in] port Port to be read.
* @param[in] p_port_value Pointer to return the port value.
*/
fsp_err_t (* portRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value);
/** Write to multiple pins on a port.
*
* @param[in] p_ctrl Pointer to control structure.
* @param[in] port Port to be written to.
* @param[in] value Value to be written to the port.
* @param[in] mask Mask controlling which pins on the port are written to.
*/
fsp_err_t (* portWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask);
} ioport_api_t;
/** This structure encompasses everything that is needed to use an instance of this interface. */
typedef struct st_ioport_instance
{
ioport_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance
ioport_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance
ioport_api_t const * p_api; ///< Pointer to the API structure for this instance
} ioport_instance_t;
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif
/*******************************************************************************************************************//**
* @} (end defgroup IOPORT_API)
**********************************************************************************************************************/

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/***********************************************************************************************************************
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @ingroup RENESAS_INTERFACES
* @defgroup TRANSFER_API Transfer Interface
*
* @brief Interface for data transfer functions.
*
* @section TRANSFER_API_SUMMARY Summary
* The transfer interface supports background data transfer (no CPU intervention).
*
*
* @{
**********************************************************************************************************************/
#ifndef R_TRANSFER_API_H
#define R_TRANSFER_API_H
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
/* Common error codes and definitions. */
#include "bsp_api.h"
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/**********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#define TRANSFER_SETTINGS_MODE_BITS (30U)
#define TRANSFER_SETTINGS_SIZE_BITS (28U)
#define TRANSFER_SETTINGS_SRC_ADDR_BITS (26U)
#define TRANSFER_SETTINGS_CHAIN_MODE_BITS (22U)
#define TRANSFER_SETTINGS_IRQ_BITS (21U)
#define TRANSFER_SETTINGS_REPEAT_AREA_BITS (20U)
#define TRANSFER_SETTINGS_DEST_ADDR_BITS (18U)
/**********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** Transfer control block. Allocate an instance specific control block to pass into the transfer API calls.
*/
typedef void transfer_ctrl_t;
#ifndef BSP_OVERRIDE_TRANSFER_MODE_T
/** Transfer mode describes what will happen when a transfer request occurs. */
typedef enum e_transfer_mode
{
/** In normal mode, each transfer request causes a transfer of @ref transfer_size_t from the source pointer to
* the destination pointer. The transfer length is decremented and the source and address pointers are
* updated according to @ref transfer_addr_mode_t. After the transfer length reaches 0, transfer requests
* will not cause any further transfers. */
TRANSFER_MODE_NORMAL = 0,
/** Repeat mode is like normal mode, except that when the transfer length reaches 0, the pointer to the
* repeat area and the transfer length will be reset to their initial values. If DMAC is used, the
* transfer repeats only transfer_info_t::num_blocks times. After the transfer repeats
* transfer_info_t::num_blocks times, transfer requests will not cause any further transfers. If DTC is
* used, the transfer repeats continuously (no limit to the number of repeat transfers). */
TRANSFER_MODE_REPEAT = 1,
/** In block mode, each transfer request causes transfer_info_t::length transfers of @ref transfer_size_t.
* After each individual transfer, the source and destination pointers are updated according to
* @ref transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is
* decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any
* further transfers. */
TRANSFER_MODE_BLOCK = 2,
/** In addition to block mode features, repeat-block mode supports a ring buffer of blocks and offsets
* within a block (to split blocks into arrays of their first data, second data, etc.) */
TRANSFER_MODE_REPEAT_BLOCK = 3
} transfer_mode_t;
#endif
#ifndef BSP_OVERRIDE_TRANSFER_SIZE_T
/** Transfer size specifies the size of each individual transfer.
* Total transfer length = transfer_size_t * transfer_length_t
*/
typedef enum e_transfer_size
{
TRANSFER_SIZE_1_BYTE = 0, ///< Each transfer transfers a 8-bit value
TRANSFER_SIZE_2_BYTE = 1, ///< Each transfer transfers a 16-bit value
TRANSFER_SIZE_4_BYTE = 2 ///< Each transfer transfers a 32-bit value
} transfer_size_t;
#endif
#ifndef BSP_OVERRIDE_TRANSFER_ADDR_MODE_T
/** Address mode specifies whether to modify (increment or decrement) pointer after each transfer. */
typedef enum e_transfer_addr_mode
{
/** Address pointer remains fixed after each transfer. */
TRANSFER_ADDR_MODE_FIXED = 0,
/** Offset is added to the address pointer after each transfer. */
TRANSFER_ADDR_MODE_OFFSET = 1,
/** Address pointer is incremented by associated @ref transfer_size_t after each transfer. */
TRANSFER_ADDR_MODE_INCREMENTED = 2,
/** Address pointer is decremented by associated @ref transfer_size_t after each transfer. */
TRANSFER_ADDR_MODE_DECREMENTED = 3
} transfer_addr_mode_t;
#endif
#ifndef BSP_OVERRIDE_TRANSFER_REPEAT_AREA_T
/** Repeat area options (source or destination). In @ref TRANSFER_MODE_REPEAT, the selected pointer returns to its
* original value after transfer_info_t::length transfers. In @ref TRANSFER_MODE_BLOCK and @ref TRANSFER_MODE_REPEAT_BLOCK,
* the selected pointer returns to its original value after each transfer. */
typedef enum e_transfer_repeat_area
{
/** Destination area repeated in @ref TRANSFER_MODE_REPEAT or @ref TRANSFER_MODE_BLOCK or @ref TRANSFER_MODE_REPEAT_BLOCK. */
TRANSFER_REPEAT_AREA_DESTINATION = 0,
/** Source area repeated in @ref TRANSFER_MODE_REPEAT or @ref TRANSFER_MODE_BLOCK or @ref TRANSFER_MODE_REPEAT_BLOCK. */
TRANSFER_REPEAT_AREA_SOURCE = 1
} transfer_repeat_area_t;
#endif
#ifndef BSP_OVERRIDE_TRANSFER_CHAIN_MODE_T
/** Chain transfer mode options.
* @note Only applies for DTC. */
typedef enum e_transfer_chain_mode
{
/** Chain mode not used. */
TRANSFER_CHAIN_MODE_DISABLED = 0,
/** Switch to next transfer after a single transfer from this @ref transfer_info_t. */
TRANSFER_CHAIN_MODE_EACH = 2,
/** Complete the entire transfer defined in this @ref transfer_info_t before chaining to next transfer. */
TRANSFER_CHAIN_MODE_END = 3
} transfer_chain_mode_t;
#endif
#ifndef BSP_OVERRIDE_TRANSFER_IRQ_T
/** Interrupt options. */
typedef enum e_transfer_irq
{
/** Interrupt occurs only after last transfer. If this transfer is chained to a subsequent transfer,
* the interrupt will occur only after subsequent chained transfer(s) are complete.
* @warning DTC triggers the interrupt of the activation source. Choosing TRANSFER_IRQ_END with DTC will
* prevent activation source interrupts until the transfer is complete. */
TRANSFER_IRQ_END = 0,
/** Interrupt occurs after each transfer.
* @note Not available in all HAL drivers. See HAL driver for details. */
TRANSFER_IRQ_EACH = 1
} transfer_irq_t;
#endif
/** Driver specific information. */
typedef struct st_transfer_properties
{
uint32_t block_count_max; ///< Maximum number of blocks
uint32_t block_count_remaining; ///< Number of blocks remaining
uint32_t transfer_length_max; ///< Maximum number of transfers
uint32_t transfer_length_remaining; ///< Number of transfers remaining
} transfer_properties_t;
#ifndef BSP_OVERRIDE_TRANSFER_INFO_T
/** This structure specifies the properties of the transfer.
* @warning When using DTC, this structure corresponds to the descriptor block registers required by the DTC.
* The following components may be modified by the driver: p_src, p_dest, num_blocks, and length.
* @warning When using DTC, do NOT reuse this structure to configure multiple transfers. Each transfer must
* have a unique transfer_info_t.
* @warning When using DTC, this structure must not be allocated in a temporary location. Any instance of this
* structure must remain in scope until the transfer it is used for is closed.
* @note When using DTC, consider placing instances of this structure in a protected section of memory. */
typedef struct st_transfer_info
{
union
{
struct
{
uint32_t : 16;
uint32_t : 2;
/** Select what happens to destination pointer after each transfer. */
transfer_addr_mode_t dest_addr_mode : 2;
/** Select to repeat source or destination area, unused in @ref TRANSFER_MODE_NORMAL. */
transfer_repeat_area_t repeat_area : 1;
/** Select if interrupts should occur after each individual transfer or after the completion of all planned
* transfers. */
transfer_irq_t irq : 1;
/** Select when the chain transfer ends. */
transfer_chain_mode_t chain_mode : 2;
uint32_t : 2;
/** Select what happens to source pointer after each transfer. */
transfer_addr_mode_t src_addr_mode : 2;
/** Select number of bytes to transfer at once. @see transfer_info_t::length. */
transfer_size_t size : 2;
/** Select mode from @ref transfer_mode_t. */
transfer_mode_t mode : 2;
} transfer_settings_word_b;
uint32_t transfer_settings_word;
};
void const * volatile p_src; ///< Source pointer
void * volatile p_dest; ///< Destination pointer
/** Number of blocks to transfer when using @ref TRANSFER_MODE_BLOCK (both DTC an DMAC) or
* @ref TRANSFER_MODE_REPEAT (DMAC only) or
* @ref TRANSFER_MODE_REPEAT_BLOCK (DMAC only), unused in other modes. */
volatile uint16_t num_blocks;
/** Length of each transfer. Range limited for @ref TRANSFER_MODE_BLOCK, @ref TRANSFER_MODE_REPEAT,
* and @ref TRANSFER_MODE_REPEAT_BLOCK
* see HAL driver for details. */
volatile uint16_t length;
} transfer_info_t;
#endif
/** Driver configuration set in @ref transfer_api_t::open. All elements except p_extend are required and must be
* initialized. */
typedef struct st_transfer_cfg
{
/** Pointer to transfer configuration options. If using chain transfer (DTC only), this can be a pointer to
* an array of chained transfers that will be completed in order. */
transfer_info_t * p_info;
void const * p_extend; ///< Extension parameter for hardware specific settings.
} transfer_cfg_t;
/** Select whether to start single or repeated transfer with software start. */
typedef enum e_transfer_start_mode
{
TRANSFER_START_MODE_SINGLE = 0, ///< Software start triggers single transfer.
TRANSFER_START_MODE_REPEAT = 1 ///< Software start transfer continues until transfer is complete.
} transfer_start_mode_t;
/** Transfer functions implemented at the HAL layer will follow this API. */
typedef struct st_transfer_api
{
/** Initial configuration.
*
* @param[in,out] p_ctrl Pointer to control block. Must be declared by user. Elements set here.
* @param[in] p_cfg Pointer to configuration structure. All elements of this structure
* must be set by user.
*/
fsp_err_t (* open)(transfer_ctrl_t * const p_ctrl, transfer_cfg_t const * const p_cfg);
/** Reconfigure the transfer.
* Enable the transfer if p_info is valid.
*
* @param[in,out] p_ctrl Pointer to control block. Must be declared by user. Elements set here.
* @param[in] p_info Pointer to a new transfer info structure.
*/
fsp_err_t (* reconfigure)(transfer_ctrl_t * const p_ctrl, transfer_info_t * p_info);
/** Reset source address pointer, destination address pointer, and/or length, keeping all other settings the same.
* Enable the transfer if p_src, p_dest, and length are valid.
*
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
* @param[in] p_src Pointer to source. Set to NULL if source pointer should not change.
* @param[in] p_dest Pointer to destination. Set to NULL if destination pointer should not change.
* @param[in] num_transfers Transfer length in normal mode or number of blocks in block mode. In DMAC only,
* resets number of repeats (initially stored in transfer_info_t::num_blocks) in
* repeat mode. Not used in repeat mode for DTC.
*/
fsp_err_t (* reset)(transfer_ctrl_t * const p_ctrl, void const * p_src, void * p_dest,
uint16_t const num_transfers);
/** Enable transfer. Transfers occur after the activation source event (or when
* @ref transfer_api_t::softwareStart is called if no peripheral event is chosen as activation source).
*
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
*/
fsp_err_t (* enable)(transfer_ctrl_t * const p_ctrl);
/** Disable transfer. Transfers do not occur after the activation source event (or when
* @ref transfer_api_t::softwareStart is called if no peripheral event is chosen as the DMAC activation source).
* @note If a transfer is in progress, it will be completed. Subsequent transfer requests do not cause a
* transfer.
*
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
*/
fsp_err_t (* disable)(transfer_ctrl_t * const p_ctrl);
/** Start transfer in software.
* @warning Only works if no peripheral event is chosen as the DMAC activation source.
* @note Not supported for DTC.
*
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
* @param[in] mode Select mode from @ref transfer_start_mode_t.
*/
fsp_err_t (* softwareStart)(transfer_ctrl_t * const p_ctrl, transfer_start_mode_t mode);
/** Stop transfer in software. The transfer will stop after completion of the current transfer.
* @note Not supported for DTC.
* @note Only applies for transfers started with TRANSFER_START_MODE_REPEAT.
* @warning Only works if no peripheral event is chosen as the DMAC activation source.
*
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
*/
fsp_err_t (* softwareStop)(transfer_ctrl_t * const p_ctrl);
/** Provides information about this transfer.
*
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
* @param[out] p_properties Driver specific information.
*/
fsp_err_t (* infoGet)(transfer_ctrl_t * const p_ctrl, transfer_properties_t * const p_properties);
/** Releases hardware lock. This allows a transfer to be reconfigured using @ref transfer_api_t::open.
*
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
*/
fsp_err_t (* close)(transfer_ctrl_t * const p_ctrl);
/** To update next transfer information without interruption during transfer.
* Allow further transfer continuation.
*
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
* @param[in] p_src Pointer to source. Set to NULL if source pointer should not change.
* @param[in] p_dest Pointer to destination. Set to NULL if destination pointer should not change.
* @param[in] num_transfers Transfer length in normal mode or block mode.
*/
fsp_err_t (* reload)(transfer_ctrl_t * const p_ctrl, void const * p_src, void * p_dest,
uint32_t const num_transfers);
} transfer_api_t;
/** This structure encompasses everything that is needed to use an instance of this interface. */
typedef struct st_transfer_instance
{
transfer_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance
transfer_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance
transfer_api_t const * p_api; ///< Pointer to the API structure for this instance
} transfer_instance_t;
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif
/*******************************************************************************************************************//**
* @} (end defgroup TRANSFER_API)
**********************************************************************************************************************/

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/***********************************************************************************************************************
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @ingroup RENESAS_INTERFACES
* @defgroup UART_API UART Interface
* @brief Interface for UART communications.
*
* @section UART_INTERFACE_SUMMARY Summary
* The UART interface provides common APIs for UART HAL drivers. The UART interface supports the following features:
* - Full-duplex UART communication
* - Interrupt driven transmit/receive processing
* - Callback function with returned event code
* - Runtime baud-rate change
* - Hardware resource locking during a transaction
* - CTS/RTS hardware flow control support (with an associated IOPORT pin)
*
*
* @{
**********************************************************************************************************************/
#ifndef R_UART_API_H
#define R_UART_API_H
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
/* Includes board and MCU related header files. */
#include "bsp_api.h"
#include "r_transfer_api.h"
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/**********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/**********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** UART Event codes */
#ifndef BSP_OVERRIDE_UART_EVENT_T
typedef enum e_sf_event
{
UART_EVENT_RX_COMPLETE = (1UL << 0), ///< Receive complete event
UART_EVENT_TX_COMPLETE = (1UL << 1), ///< Transmit complete event
UART_EVENT_RX_CHAR = (1UL << 2), ///< Character received
UART_EVENT_ERR_PARITY = (1UL << 3), ///< Parity error event
UART_EVENT_ERR_FRAMING = (1UL << 4), ///< Mode fault error event
UART_EVENT_ERR_OVERFLOW = (1UL << 5), ///< FIFO Overflow error event
UART_EVENT_BREAK_DETECT = (1UL << 6), ///< Break detect error event
UART_EVENT_TX_DATA_EMPTY = (1UL << 7), ///< Last byte is transmitting, ready for more data
} uart_event_t;
#endif
#ifndef BSP_OVERRIDE_UART_DATA_BITS_T
/** UART Data bit length definition */
typedef enum e_uart_data_bits
{
UART_DATA_BITS_9 = 0U, ///< Data bits 9-bit
UART_DATA_BITS_8 = 2U, ///< Data bits 8-bit
UART_DATA_BITS_7 = 3U, ///< Data bits 7-bit
} uart_data_bits_t;
#endif
#ifndef BSP_OVERRIDE_UART_PARITY_T
/** UART Parity definition */
typedef enum e_uart_parity
{
UART_PARITY_OFF = 0U, ///< No parity
UART_PARITY_EVEN = 2U, ///< Even parity
UART_PARITY_ODD = 3U, ///< Odd parity
} uart_parity_t;
#endif
/** UART Stop bits definition */
typedef enum e_uart_stop_bits
{
UART_STOP_BITS_1 = 0U, ///< Stop bit 1-bit
UART_STOP_BITS_2 = 1U, ///< Stop bits 2-bit
} uart_stop_bits_t;
/** UART transaction definition */
typedef enum e_uart_dir
{
UART_DIR_RX_TX = 3U, ///< Both RX and TX
UART_DIR_RX = 1U, ///< Only RX
UART_DIR_TX = 2U, ///< Only TX
} uart_dir_t;
/** UART driver specific information */
typedef struct st_uart_info
{
/** Maximum bytes that can be written at this time. Only applies if uart_cfg_t::p_transfer_tx is not NULL. */
uint32_t write_bytes_max;
/** Maximum bytes that are available to read at one time. Only applies if uart_cfg_t::p_transfer_rx is not NULL. */
uint32_t read_bytes_max;
} uart_info_t;
/** UART Callback parameter definition */
typedef struct st_uart_callback_arg
{
uint32_t channel; ///< Device channel number
uart_event_t event; ///< Event code
/** Contains the next character received for the events UART_EVENT_RX_CHAR, UART_EVENT_ERR_PARITY,
* UART_EVENT_ERR_FRAMING, or UART_EVENT_ERR_OVERFLOW. Otherwise unused. */
uint32_t data;
void const * p_context; ///< Context provided to user during callback
} uart_callback_args_t;
/** UART Configuration */
typedef struct st_uart_cfg
{
/* UART generic configuration */
uint8_t channel; ///< Select a channel corresponding to the channel number of the hardware.
uart_data_bits_t data_bits; ///< Data bit length (8 or 7 or 9)
uart_parity_t parity; ///< Parity type (none or odd or even)
uart_stop_bits_t stop_bits; ///< Stop bit length (1 or 2)
uint8_t rxi_ipl; ///< Receive interrupt priority
IRQn_Type rxi_irq; ///< Receive interrupt IRQ number
uint8_t txi_ipl; ///< Transmit interrupt priority
IRQn_Type txi_irq; ///< Transmit interrupt IRQ number
uint8_t tei_ipl; ///< Transmit end interrupt priority
IRQn_Type tei_irq; ///< Transmit end interrupt IRQ number
uint8_t eri_ipl; ///< Error interrupt priority
IRQn_Type eri_irq; ///< Error interrupt IRQ number
/** Optional transfer instance used to receive multiple bytes without interrupts. Set to NULL if unused.
* If NULL, the number of bytes allowed in the read API is limited to one byte at a time. */
transfer_instance_t const * p_transfer_rx;
/** Optional transfer instance used to send multiple bytes without interrupts. Set to NULL if unused.
* If NULL, the number of bytes allowed in the write APIs is limited to one byte at a time. */
transfer_instance_t const * p_transfer_tx;
/* Configuration for UART Event processing */
void (* p_callback)(uart_callback_args_t * p_args); ///< Pointer to callback function
void const * p_context; ///< User defined context passed into callback function
/* Pointer to UART peripheral specific configuration */
void const * p_extend; ///< UART hardware dependent configuration
} uart_cfg_t;
/** UART control block. Allocate an instance specific control block to pass into the UART API calls.
*/
typedef void uart_ctrl_t;
/** Shared Interface definition for UART */
typedef struct st_uart_api
{
/** Open UART device.
*
* @param[in,out] p_ctrl Pointer to the UART control block. Must be declared by user. Value set here.
* @param[in] uart_cfg_t Pointer to UART configuration structure. All elements of this structure must be set by
* user.
*/
fsp_err_t (* open)(uart_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg);
/** Read from UART device. The read buffer is used until the read is complete. When a transfer is complete, the
* callback is called with event UART_EVENT_RX_COMPLETE. Bytes received outside an active transfer are received in
* the callback function with event UART_EVENT_RX_CHAR.
* The maximum transfer size is reported by infoGet().
*
* @param[in] p_ctrl Pointer to the UART control block for the channel.
* @param[in] p_dest Destination address to read data from.
* @param[in] bytes Read data length.
*/
fsp_err_t (* read)(uart_ctrl_t * const p_ctrl, uint8_t * const p_dest, uint32_t const bytes);
/** Write to UART device. The write buffer is used until write is complete. Do not overwrite write buffer
* contents until the write is finished. When the write is complete (all bytes are fully transmitted on the wire),
* the callback called with event UART_EVENT_TX_COMPLETE.
* The maximum transfer size is reported by infoGet().
*
* @param[in] p_ctrl Pointer to the UART control block.
* @param[in] p_src Source address to write data to.
* @param[in] bytes Write data length.
*/
fsp_err_t (* write)(uart_ctrl_t * const p_ctrl, uint8_t const * const p_src, uint32_t const bytes);
/** Change baud rate.
* @warning Calling this API aborts any in-progress transmission and disables reception until the new baud
* settings have been applied.
*
*
* @param[in] p_ctrl Pointer to the UART control block.
* @param[in] p_baudrate_info Pointer to module specific information for configuring baud rate.
*/
fsp_err_t (* baudSet)(uart_ctrl_t * const p_ctrl, void const * const p_baudrate_info);
/** Get the driver specific information.
*
* @param[in] p_ctrl Pointer to the UART control block.
* @param[in] baudrate Baud rate in bps.
*/
fsp_err_t (* infoGet)(uart_ctrl_t * const p_ctrl, uart_info_t * const p_info);
/**
* Abort ongoing transfer.
*
* @param[in] p_ctrl Pointer to the UART control block.
* @param[in] communication_to_abort Type of abort request.
*/
fsp_err_t (* communicationAbort)(uart_ctrl_t * const p_ctrl, uart_dir_t communication_to_abort);
/**
* Specify callback function and optional context pointer and working memory pointer.
*
* @param[in] p_ctrl Pointer to the UART control block.
* @param[in] p_callback Callback function
* @param[in] p_context Pointer to send to callback function
* @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated.
* Callback arguments allocated here are only valid during the callback.
*/
fsp_err_t (* callbackSet)(uart_ctrl_t * const p_ctrl, void (* p_callback)(uart_callback_args_t *),
void const * const p_context, uart_callback_args_t * const p_callback_memory);
/** Close UART device.
*
* @param[in] p_ctrl Pointer to the UART control block.
*/
fsp_err_t (* close)(uart_ctrl_t * const p_ctrl);
/** Stop ongoing read and return the number of bytes remaining in the read.
*
* @param[in] p_ctrl Pointer to the UART control block.
* @param[in,out] remaining_bytes Pointer to location to store remaining bytes for read.
*/
fsp_err_t (* readStop)(uart_ctrl_t * const p_ctrl, uint32_t * remaining_bytes);
} uart_api_t;
/** This structure encompasses everything that is needed to use an instance of this interface. */
typedef struct st_uart_instance
{
uart_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance
uart_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance
uart_api_t const * p_api; ///< Pointer to the API structure for this instance
} uart_instance_t;
/** @} (end defgroup UART_API) */
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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/***********************************************************************************************************************
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef FSP_FEATURES_H
#define FSP_FEATURES_H
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
/* C99 includes. */
#include <stdint.h>
#include <stddef.h>
#include <stdbool.h>
#include <assert.h>
/* Different compiler support. */
#include "fsp_common_api.h"
#include "../../fsp/src/bsp/mcu/all/bsp_compiler_support.h"
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
**********************************************************************************************************************/
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** Available modules. */
typedef enum e_fsp_ip
{
FSP_IP_CFLASH = 0, ///< Code Flash
FSP_IP_DFLASH = 1, ///< Data Flash
FSP_IP_RAM = 2, ///< RAM
FSP_IP_LVD = 3, ///< Low Voltage Detection
FSP_IP_CGC = 3, ///< Clock Generation Circuit
FSP_IP_LPM = 3, ///< Low Power Modes
FSP_IP_FCU = 4, ///< Flash Control Unit
FSP_IP_ICU = 6, ///< Interrupt Control Unit
FSP_IP_DMAC = 7, ///< DMA Controller
FSP_IP_DTC = 8, ///< Data Transfer Controller
FSP_IP_IOPORT = 9, ///< I/O Ports
FSP_IP_PFS = 10, ///< Pin Function Select
FSP_IP_ELC = 11, ///< Event Link Controller
FSP_IP_MPU = 13, ///< Memory Protection Unit
FSP_IP_MSTP = 14, ///< Module Stop
FSP_IP_MMF = 15, ///< Memory Mirror Function
FSP_IP_KEY = 16, ///< Key Interrupt Function
FSP_IP_CAC = 17, ///< Clock Frequency Accuracy Measurement Circuit
FSP_IP_DOC = 18, ///< Data Operation Circuit
FSP_IP_CRC = 19, ///< Cyclic Redundancy Check Calculator
FSP_IP_SCI = 20, ///< Serial Communications Interface
FSP_IP_IIC = 21, ///< I2C Bus Interface
FSP_IP_SPI = 22, ///< Serial Peripheral Interface
FSP_IP_CTSU = 23, ///< Capacitive Touch Sensing Unit
FSP_IP_SCE = 24, ///< Secure Cryptographic Engine
FSP_IP_SLCDC = 25, ///< Segment LCD Controller
FSP_IP_AES = 26, ///< Advanced Encryption Standard
FSP_IP_TRNG = 27, ///< True Random Number Generator
FSP_IP_FCACHE = 30, ///< Flash Cache
FSP_IP_SRAM = 31, ///< SRAM
FSP_IP_ADC = 32, ///< A/D Converter
FSP_IP_DAC = 33, ///< 12-Bit D/A Converter
FSP_IP_TSN = 34, ///< Temperature Sensor
FSP_IP_DAAD = 35, ///< D/A A/D Synchronous Unit
FSP_IP_ACMPHS = 36, ///< High Speed Analog Comparator
FSP_IP_ACMPLP = 37, ///< Low Power Analog Comparator
FSP_IP_OPAMP = 38, ///< Operational Amplifier
FSP_IP_SDADC = 39, ///< Sigma Delta A/D Converter
FSP_IP_RTC = 40, ///< Real Time Clock
FSP_IP_WDT = 41, ///< Watch Dog Timer
FSP_IP_IWDT = 42, ///< Independent Watch Dog Timer
FSP_IP_GPT = 43, ///< General PWM Timer
FSP_IP_POEG = 44, ///< Port Output Enable for GPT
FSP_IP_OPS = 45, ///< Output Phase Switch
FSP_IP_AGT = 47, ///< Asynchronous General-Purpose Timer
FSP_IP_CAN = 48, ///< Controller Area Network
FSP_IP_IRDA = 49, ///< Infrared Data Association
FSP_IP_QSPI = 50, ///< Quad Serial Peripheral Interface
FSP_IP_USBFS = 51, ///< USB Full Speed
FSP_IP_SDHI = 52, ///< SD/MMC Host Interface
FSP_IP_SRC = 53, ///< Sampling Rate Converter
FSP_IP_SSI = 54, ///< Serial Sound Interface
FSP_IP_DALI = 55, ///< Digital Addressable Lighting Interface
FSP_IP_ETHER = 64, ///< Ethernet MAC Controller
FSP_IP_EDMAC = 64, ///< Ethernet DMA Controller
FSP_IP_EPTPC = 65, ///< Ethernet PTP Controller
FSP_IP_PDC = 66, ///< Parallel Data Capture Unit
FSP_IP_GLCDC = 67, ///< Graphics LCD Controller
FSP_IP_DRW = 68, ///< 2D Drawing Engine
FSP_IP_JPEG = 69, ///< JPEG
FSP_IP_DAC8 = 70, ///< 8-Bit D/A Converter
FSP_IP_USBHS = 71, ///< USB High Speed
FSP_IP_OSPI = 72, ///< Octa Serial Peripheral Interface
FSP_IP_CEC = 73, ///< HDMI CEC
FSP_IP_TFU = 74, ///< Trigonometric Function Unit
FSP_IP_IIRFA = 75, ///< IIR Filter Accelerator
FSP_IP_CANFD = 76, ///< CAN-FD
FSP_IP_ULPT = 77, ///< Ultra Low Power Timer ULPT
} fsp_ip_t;
/** Signals that can be mapped to an interrupt. */
typedef enum e_fsp_signal
{
FSP_SIGNAL_ADC_COMPARE_MATCH = 0, ///< ADC COMPARE MATCH
FSP_SIGNAL_ADC_COMPARE_MISMATCH, ///< ADC COMPARE MISMATCH
FSP_SIGNAL_ADC_SCAN_END, ///< ADC SCAN END
FSP_SIGNAL_ADC_SCAN_END_B, ///< ADC SCAN END B
FSP_SIGNAL_ADC_WINDOW_A, ///< ADC WINDOW A
FSP_SIGNAL_ADC_WINDOW_B, ///< ADC WINDOW B
FSP_SIGNAL_AES_RDREQ = 0, ///< AES RDREQ
FSP_SIGNAL_AES_WRREQ, ///< AES WRREQ
FSP_SIGNAL_AGT_COMPARE_A = 0, ///< AGT COMPARE A
FSP_SIGNAL_AGT_COMPARE_B, ///< AGT COMPARE B
FSP_SIGNAL_AGT_INT, ///< AGT INT
FSP_SIGNAL_CAC_FREQUENCY_ERROR = 0, ///< CAC FREQUENCY ERROR
FSP_SIGNAL_CAC_MEASUREMENT_END, ///< CAC MEASUREMENT END
FSP_SIGNAL_CAC_OVERFLOW, ///< CAC OVERFLOW
FSP_SIGNAL_CAN_ERROR = 0, ///< CAN ERROR
FSP_SIGNAL_CAN_FIFO_RX, ///< CAN FIFO RX
FSP_SIGNAL_CAN_FIFO_TX, ///< CAN FIFO TX
FSP_SIGNAL_CAN_MAILBOX_RX, ///< CAN MAILBOX RX
FSP_SIGNAL_CAN_MAILBOX_TX, ///< CAN MAILBOX TX
FSP_SIGNAL_CGC_MOSC_STOP = 0, ///< CGC MOSC STOP
FSP_SIGNAL_LPM_SNOOZE_REQUEST, ///< LPM SNOOZE REQUEST
FSP_SIGNAL_LVD_LVD1, ///< LVD LVD1
FSP_SIGNAL_LVD_LVD2, ///< LVD LVD2
FSP_SIGNAL_VBATT_LVD, ///< VBATT LVD
FSP_SIGNAL_LVD_VBATT = FSP_SIGNAL_VBATT_LVD, ///< LVD VBATT
FSP_SIGNAL_ACMPHS_INT = 0, ///< ACMPHS INT
FSP_SIGNAL_ACMPLP_INT = 0, ///< ACMPLP INT
FSP_SIGNAL_CTSU_END = 0, ///< CTSU END
FSP_SIGNAL_CTSU_READ, ///< CTSU READ
FSP_SIGNAL_CTSU_WRITE, ///< CTSU WRITE
FSP_SIGNAL_DALI_DEI = 0, ///< DALI DEI
FSP_SIGNAL_DALI_CLI, ///< DALI CLI
FSP_SIGNAL_DALI_SDI, ///< DALI SDI
FSP_SIGNAL_DALI_BPI, ///< DALI BPI
FSP_SIGNAL_DALI_FEI, ///< DALI FEI
FSP_SIGNAL_DALI_SDI_OR_BPI, ///< DALI SDI OR BPI
FSP_SIGNAL_DMAC_INT = 0, ///< DMAC INT
FSP_SIGNAL_DOC_INT = 0, ///< DOC INT
FSP_SIGNAL_DRW_INT = 0, ///< DRW INT
FSP_SIGNAL_DTC_COMPLETE = 0, ///< DTC COMPLETE
FSP_SIGNAL_DTC_END, ///< DTC END
FSP_SIGNAL_EDMAC_EINT = 0, ///< EDMAC EINT
FSP_SIGNAL_ELC_SOFTWARE_EVENT_0 = 0, ///< ELC SOFTWARE EVENT 0
FSP_SIGNAL_ELC_SOFTWARE_EVENT_1, ///< ELC SOFTWARE EVENT 1
FSP_SIGNAL_EPTPC_IPLS = 0, ///< EPTPC IPLS
FSP_SIGNAL_EPTPC_MINT, ///< EPTPC MINT
FSP_SIGNAL_EPTPC_PINT, ///< EPTPC PINT
FSP_SIGNAL_EPTPC_TIMER0_FALL, ///< EPTPC TIMER0 FALL
FSP_SIGNAL_EPTPC_TIMER0_RISE, ///< EPTPC TIMER0 RISE
FSP_SIGNAL_EPTPC_TIMER1_FALL, ///< EPTPC TIMER1 FALL
FSP_SIGNAL_EPTPC_TIMER1_RISE, ///< EPTPC TIMER1 RISE
FSP_SIGNAL_EPTPC_TIMER2_FALL, ///< EPTPC TIMER2 FALL
FSP_SIGNAL_EPTPC_TIMER2_RISE, ///< EPTPC TIMER2 RISE
FSP_SIGNAL_EPTPC_TIMER3_FALL, ///< EPTPC TIMER3 FALL
FSP_SIGNAL_EPTPC_TIMER3_RISE, ///< EPTPC TIMER3 RISE
FSP_SIGNAL_EPTPC_TIMER4_FALL, ///< EPTPC TIMER4 FALL
FSP_SIGNAL_EPTPC_TIMER4_RISE, ///< EPTPC TIMER4 RISE
FSP_SIGNAL_EPTPC_TIMER5_FALL, ///< EPTPC TIMER5 FALL
FSP_SIGNAL_EPTPC_TIMER5_RISE, ///< EPTPC TIMER5 RISE
FSP_SIGNAL_FCU_FIFERR = 0, ///< FCU FIFERR
FSP_SIGNAL_FCU_FRDYI, ///< FCU FRDYI
FSP_SIGNAL_GLCDC_LINE_DETECT = 0, ///< GLCDC LINE DETECT
FSP_SIGNAL_GLCDC_UNDERFLOW_1, ///< GLCDC UNDERFLOW 1
FSP_SIGNAL_GLCDC_UNDERFLOW_2, ///< GLCDC UNDERFLOW 2
FSP_SIGNAL_GPT_CAPTURE_COMPARE_A = 0, ///< GPT CAPTURE COMPARE A
FSP_SIGNAL_GPT_CAPTURE_COMPARE_B, ///< GPT CAPTURE COMPARE B
FSP_SIGNAL_GPT_COMPARE_C, ///< GPT COMPARE C
FSP_SIGNAL_GPT_COMPARE_D, ///< GPT COMPARE D
FSP_SIGNAL_GPT_COMPARE_E, ///< GPT COMPARE E
FSP_SIGNAL_GPT_COMPARE_F, ///< GPT COMPARE F
FSP_SIGNAL_GPT_COUNTER_OVERFLOW, ///< GPT COUNTER OVERFLOW
FSP_SIGNAL_GPT_COUNTER_UNDERFLOW, ///< GPT COUNTER UNDERFLOW
FSP_SIGNAL_GPT_AD_TRIG_A, ///< GPT AD TRIG A
FSP_SIGNAL_GPT_AD_TRIG_B, ///< GPT AD TRIG B
FSP_SIGNAL_OPS_UVW_EDGE, ///< OPS UVW EDGE
FSP_SIGNAL_ICU_IRQ0 = 0, ///< ICU IRQ0
FSP_SIGNAL_ICU_IRQ1, ///< ICU IRQ1
FSP_SIGNAL_ICU_IRQ2, ///< ICU IRQ2
FSP_SIGNAL_ICU_IRQ3, ///< ICU IRQ3
FSP_SIGNAL_ICU_IRQ4, ///< ICU IRQ4
FSP_SIGNAL_ICU_IRQ5, ///< ICU IRQ5
FSP_SIGNAL_ICU_IRQ6, ///< ICU IRQ6
FSP_SIGNAL_ICU_IRQ7, ///< ICU IRQ7
FSP_SIGNAL_ICU_IRQ8, ///< ICU IRQ8
FSP_SIGNAL_ICU_IRQ9, ///< ICU IRQ9
FSP_SIGNAL_ICU_IRQ10, ///< ICU IRQ10
FSP_SIGNAL_ICU_IRQ11, ///< ICU IRQ11
FSP_SIGNAL_ICU_IRQ12, ///< ICU IRQ12
FSP_SIGNAL_ICU_IRQ13, ///< ICU IRQ13
FSP_SIGNAL_ICU_IRQ14, ///< ICU IRQ14
FSP_SIGNAL_ICU_IRQ15, ///< ICU IRQ15
FSP_SIGNAL_ICU_SNOOZE_CANCEL, ///< ICU SNOOZE CANCEL
FSP_SIGNAL_IIC_ERI = 0, ///< IIC ERI
FSP_SIGNAL_IIC_RXI, ///< IIC RXI
FSP_SIGNAL_IIC_TEI, ///< IIC TEI
FSP_SIGNAL_IIC_TXI, ///< IIC TXI
FSP_SIGNAL_IIC_WUI, ///< IIC WUI
FSP_SIGNAL_IOPORT_EVENT_1 = 0, ///< IOPORT EVENT 1
FSP_SIGNAL_IOPORT_EVENT_2, ///< IOPORT EVENT 2
FSP_SIGNAL_IOPORT_EVENT_3, ///< IOPORT EVENT 3
FSP_SIGNAL_IOPORT_EVENT_4, ///< IOPORT EVENT 4
FSP_SIGNAL_IOPORT_EVENT_B = 0, ///< IOPORT EVENT B
FSP_SIGNAL_IOPORT_EVENT_C, ///< IOPORT EVENT C
FSP_SIGNAL_IOPORT_EVENT_D, ///< IOPORT EVENT D
FSP_SIGNAL_IOPORT_EVENT_E, ///< IOPORT EVENT E
FSP_SIGNAL_IWDT_UNDERFLOW = 0, ///< IWDT UNDERFLOW
FSP_SIGNAL_JPEG_JDTI = 0, ///< JPEG JDTI
FSP_SIGNAL_JPEG_JEDI, ///< JPEG JEDI
FSP_SIGNAL_KEY_INT = 0, ///< KEY INT
FSP_SIGNAL_PDC_FRAME_END = 0, ///< PDC FRAME END
FSP_SIGNAL_PDC_INT, ///< PDC INT
FSP_SIGNAL_PDC_RECEIVE_DATA_READY, ///< PDC RECEIVE DATA READY
FSP_SIGNAL_POEG_EVENT = 0, ///< POEG EVENT
FSP_SIGNAL_QSPI_INT = 0, ///< QSPI INT
FSP_SIGNAL_RTC_ALARM = 0, ///< RTC ALARM
FSP_SIGNAL_RTC_PERIOD, ///< RTC PERIOD
FSP_SIGNAL_RTC_CARRY, ///< RTC CARRY
FSP_SIGNAL_SCE_INTEGRATE_RDRDY = 0, ///< SCE INTEGRATE RDRDY
FSP_SIGNAL_SCE_INTEGRATE_WRRDY, ///< SCE INTEGRATE WRRDY
FSP_SIGNAL_SCE_LONG_PLG, ///< SCE LONG PLG
FSP_SIGNAL_SCE_PROC_BUSY, ///< SCE PROC BUSY
FSP_SIGNAL_SCE_RDRDY_0, ///< SCE RDRDY 0
FSP_SIGNAL_SCE_RDRDY_1, ///< SCE RDRDY 1
FSP_SIGNAL_SCE_ROMOK, ///< SCE ROMOK
FSP_SIGNAL_SCE_TEST_BUSY, ///< SCE TEST BUSY
FSP_SIGNAL_SCE_WRRDY_0, ///< SCE WRRDY 0
FSP_SIGNAL_SCE_WRRDY_1, ///< SCE WRRDY 1
FSP_SIGNAL_SCE_WRRDY_4, ///< SCE WRRDY 4
FSP_SIGNAL_SCI_AM = 0, ///< SCI AM
FSP_SIGNAL_SCI_ERI, ///< SCI ERI
FSP_SIGNAL_SCI_RXI, ///< SCI RXI
FSP_SIGNAL_SCI_RXI_OR_ERI, ///< SCI RXI OR ERI
FSP_SIGNAL_SCI_TEI, ///< SCI TEI
FSP_SIGNAL_SCI_TXI, ///< SCI TXI
FSP_SIGNAL_SDADC_ADI = 0, ///< SDADC ADI
FSP_SIGNAL_SDADC_SCANEND, ///< SDADC SCANEND
FSP_SIGNAL_SDADC_CALIEND, ///< SDADC CALIEND
FSP_SIGNAL_SDHIMMC_ACCS = 0, ///< SDHIMMC ACCS
FSP_SIGNAL_SDHIMMC_CARD, ///< SDHIMMC CARD
FSP_SIGNAL_SDHIMMC_DMA_REQ, ///< SDHIMMC DMA REQ
FSP_SIGNAL_SDHIMMC_SDIO, ///< SDHIMMC SDIO
FSP_SIGNAL_SPI_ERI = 0, ///< SPI ERI
FSP_SIGNAL_SPI_IDLE, ///< SPI IDLE
FSP_SIGNAL_SPI_RXI, ///< SPI RXI
FSP_SIGNAL_SPI_TEI, ///< SPI TEI
FSP_SIGNAL_SPI_TXI, ///< SPI TXI
FSP_SIGNAL_SRC_CONVERSION_END = 0, ///< SRC CONVERSION END
FSP_SIGNAL_SRC_INPUT_FIFO_EMPTY, ///< SRC INPUT FIFO EMPTY
FSP_SIGNAL_SRC_OUTPUT_FIFO_FULL, ///< SRC OUTPUT FIFO FULL
FSP_SIGNAL_SRC_OUTPUT_FIFO_OVERFLOW, ///< SRC OUTPUT FIFO OVERFLOW
FSP_SIGNAL_SRC_OUTPUT_FIFO_UNDERFLOW, ///< SRC OUTPUT FIFO UNDERFLOW
FSP_SIGNAL_SSI_INT = 0, ///< SSI INT
FSP_SIGNAL_SSI_RXI, ///< SSI RXI
FSP_SIGNAL_SSI_TXI, ///< SSI TXI
FSP_SIGNAL_SSI_TXI_RXI, ///< SSI TXI RXI
FSP_SIGNAL_TRNG_RDREQ = 0, ///< TRNG RDREQ
FSP_SIGNAL_USB_FIFO_0 = 0, ///< USB FIFO 0
FSP_SIGNAL_USB_FIFO_1, ///< USB FIFO 1
FSP_SIGNAL_USB_INT, ///< USB INT
FSP_SIGNAL_USB_RESUME, ///< USB RESUME
FSP_SIGNAL_USB_USB_INT_RESUME, ///< USB USB INT RESUME
FSP_SIGNAL_WDT_UNDERFLOW = 0, ///< WDT UNDERFLOW
FSP_SIGNAL_ULPT_COMPARE_A = 0, ///< ULPT COMPARE A
FSP_SIGNAL_ULPT_COMPARE_B, ///< ULPT COMPARE B
FSP_SIGNAL_ULPT_INT, ///< ULPT INT
} fsp_signal_t;
typedef void (* fsp_vector_t)(void);
/** @} (end addtogroup BSP_MCU) */
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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/***********************************************************************************************************************
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef FSP_VERSION_H
#define FSP_VERSION_H
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
/* Includes board and MCU related header files. */
#include "bsp_api.h"
/*******************************************************************************************************************//**
* @addtogroup RENESAS_COMMON
* @{
**********************************************************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/**********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/** FSP pack major version. */
#define FSP_VERSION_MAJOR (5U)
/** FSP pack minor version. */
#define FSP_VERSION_MINOR (0U)
/** FSP pack patch version. */
#define FSP_VERSION_PATCH (0U)
/** FSP pack version build number (currently unused). */
#define FSP_VERSION_BUILD (0U)
/** Public FSP version name. */
#define FSP_VERSION_STRING ("5.0.0")
/** Unique FSP version ID. */
#define FSP_VERSION_BUILD_STRING ("Built with Renesas Advanced Flexible Software Package version 5.0.0")
/**********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** FSP Pack version structure */
typedef union st_fsp_pack_version
{
/** Version id */
uint32_t version_id;
/**
* Code version parameters, little endian order.
*/
struct version_id_b_s
{
uint8_t build; ///< Build version of FSP Pack
uint8_t patch; ///< Patch version of FSP Pack
uint8_t minor; ///< Minor version of FSP Pack
uint8_t major; ///< Major version of FSP Pack
} version_id_b;
} fsp_pack_version_t;
/** @} */
#ifdef __cplusplus
}
#endif
#endif

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/***********************************************************************************************************************
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @addtogroup IOPORT
* @{
**********************************************************************************************************************/
#ifndef R_IOPORT_H
#define R_IOPORT_H
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
#include "bsp_api.h"
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
#include "r_ioport_api.h"
#if __has_include("r_ioport_cfg.h")
#include "r_ioport_cfg.h"
#endif
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/* Private definition to set enumeration values. */
#define IOPORT_PRV_PFS_PSEL_OFFSET (24)
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** IOPORT private control block. DO NOT MODIFY. Initialization occurs when R_IOPORT_Open() is called. */
typedef struct st_ioport_instance_ctrl
{
uint32_t open;
void const * p_context;
} ioport_instance_ctrl_t;
/* This typedef is here temporarily. See SWFLEX-144 for details. */
/** Superset list of all possible IO port pins. */
typedef enum e_ioport_port_pin_t
{
IOPORT_PORT_00_PIN_00 = 0x0000, ///< IO port 0 pin 0
IOPORT_PORT_00_PIN_01 = 0x0001, ///< IO port 0 pin 1
IOPORT_PORT_00_PIN_02 = 0x0002, ///< IO port 0 pin 2
IOPORT_PORT_00_PIN_03 = 0x0003, ///< IO port 0 pin 3
IOPORT_PORT_00_PIN_04 = 0x0004, ///< IO port 0 pin 4
IOPORT_PORT_00_PIN_05 = 0x0005, ///< IO port 0 pin 5
IOPORT_PORT_00_PIN_06 = 0x0006, ///< IO port 0 pin 6
IOPORT_PORT_00_PIN_07 = 0x0007, ///< IO port 0 pin 7
IOPORT_PORT_00_PIN_08 = 0x0008, ///< IO port 0 pin 8
IOPORT_PORT_00_PIN_09 = 0x0009, ///< IO port 0 pin 9
IOPORT_PORT_00_PIN_10 = 0x000A, ///< IO port 0 pin 10
IOPORT_PORT_00_PIN_11 = 0x000B, ///< IO port 0 pin 11
IOPORT_PORT_00_PIN_12 = 0x000C, ///< IO port 0 pin 12
IOPORT_PORT_00_PIN_13 = 0x000D, ///< IO port 0 pin 13
IOPORT_PORT_00_PIN_14 = 0x000E, ///< IO port 0 pin 14
IOPORT_PORT_00_PIN_15 = 0x000F, ///< IO port 0 pin 15
IOPORT_PORT_01_PIN_00 = 0x0100, ///< IO port 1 pin 0
IOPORT_PORT_01_PIN_01 = 0x0101, ///< IO port 1 pin 1
IOPORT_PORT_01_PIN_02 = 0x0102, ///< IO port 1 pin 2
IOPORT_PORT_01_PIN_03 = 0x0103, ///< IO port 1 pin 3
IOPORT_PORT_01_PIN_04 = 0x0104, ///< IO port 1 pin 4
IOPORT_PORT_01_PIN_05 = 0x0105, ///< IO port 1 pin 5
IOPORT_PORT_01_PIN_06 = 0x0106, ///< IO port 1 pin 6
IOPORT_PORT_01_PIN_07 = 0x0107, ///< IO port 1 pin 7
IOPORT_PORT_01_PIN_08 = 0x0108, ///< IO port 1 pin 8
IOPORT_PORT_01_PIN_09 = 0x0109, ///< IO port 1 pin 9
IOPORT_PORT_01_PIN_10 = 0x010A, ///< IO port 1 pin 10
IOPORT_PORT_01_PIN_11 = 0x010B, ///< IO port 1 pin 11
IOPORT_PORT_01_PIN_12 = 0x010C, ///< IO port 1 pin 12
IOPORT_PORT_01_PIN_13 = 0x010D, ///< IO port 1 pin 13
IOPORT_PORT_01_PIN_14 = 0x010E, ///< IO port 1 pin 14
IOPORT_PORT_01_PIN_15 = 0x010F, ///< IO port 1 pin 15
IOPORT_PORT_02_PIN_00 = 0x0200, ///< IO port 2 pin 0
IOPORT_PORT_02_PIN_01 = 0x0201, ///< IO port 2 pin 1
IOPORT_PORT_02_PIN_02 = 0x0202, ///< IO port 2 pin 2
IOPORT_PORT_02_PIN_03 = 0x0203, ///< IO port 2 pin 3
IOPORT_PORT_02_PIN_04 = 0x0204, ///< IO port 2 pin 4
IOPORT_PORT_02_PIN_05 = 0x0205, ///< IO port 2 pin 5
IOPORT_PORT_02_PIN_06 = 0x0206, ///< IO port 2 pin 6
IOPORT_PORT_02_PIN_07 = 0x0207, ///< IO port 2 pin 7
IOPORT_PORT_02_PIN_08 = 0x0208, ///< IO port 2 pin 8
IOPORT_PORT_02_PIN_09 = 0x0209, ///< IO port 2 pin 9
IOPORT_PORT_02_PIN_10 = 0x020A, ///< IO port 2 pin 10
IOPORT_PORT_02_PIN_11 = 0x020B, ///< IO port 2 pin 11
IOPORT_PORT_02_PIN_12 = 0x020C, ///< IO port 2 pin 12
IOPORT_PORT_02_PIN_13 = 0x020D, ///< IO port 2 pin 13
IOPORT_PORT_02_PIN_14 = 0x020E, ///< IO port 2 pin 14
IOPORT_PORT_02_PIN_15 = 0x020F, ///< IO port 2 pin 15
IOPORT_PORT_03_PIN_00 = 0x0300, ///< IO port 3 pin 0
IOPORT_PORT_03_PIN_01 = 0x0301, ///< IO port 3 pin 1
IOPORT_PORT_03_PIN_02 = 0x0302, ///< IO port 3 pin 2
IOPORT_PORT_03_PIN_03 = 0x0303, ///< IO port 3 pin 3
IOPORT_PORT_03_PIN_04 = 0x0304, ///< IO port 3 pin 4
IOPORT_PORT_03_PIN_05 = 0x0305, ///< IO port 3 pin 5
IOPORT_PORT_03_PIN_06 = 0x0306, ///< IO port 3 pin 6
IOPORT_PORT_03_PIN_07 = 0x0307, ///< IO port 3 pin 7
IOPORT_PORT_03_PIN_08 = 0x0308, ///< IO port 3 pin 8
IOPORT_PORT_03_PIN_09 = 0x0309, ///< IO port 3 pin 9
IOPORT_PORT_03_PIN_10 = 0x030A, ///< IO port 3 pin 10
IOPORT_PORT_03_PIN_11 = 0x030B, ///< IO port 3 pin 11
IOPORT_PORT_03_PIN_12 = 0x030C, ///< IO port 3 pin 12
IOPORT_PORT_03_PIN_13 = 0x030D, ///< IO port 3 pin 13
IOPORT_PORT_03_PIN_14 = 0x030E, ///< IO port 3 pin 14
IOPORT_PORT_03_PIN_15 = 0x030F, ///< IO port 3 pin 15
IOPORT_PORT_04_PIN_00 = 0x0400, ///< IO port 4 pin 0
IOPORT_PORT_04_PIN_01 = 0x0401, ///< IO port 4 pin 1
IOPORT_PORT_04_PIN_02 = 0x0402, ///< IO port 4 pin 2
IOPORT_PORT_04_PIN_03 = 0x0403, ///< IO port 4 pin 3
IOPORT_PORT_04_PIN_04 = 0x0404, ///< IO port 4 pin 4
IOPORT_PORT_04_PIN_05 = 0x0405, ///< IO port 4 pin 5
IOPORT_PORT_04_PIN_06 = 0x0406, ///< IO port 4 pin 6
IOPORT_PORT_04_PIN_07 = 0x0407, ///< IO port 4 pin 7
IOPORT_PORT_04_PIN_08 = 0x0408, ///< IO port 4 pin 8
IOPORT_PORT_04_PIN_09 = 0x0409, ///< IO port 4 pin 9
IOPORT_PORT_04_PIN_10 = 0x040A, ///< IO port 4 pin 10
IOPORT_PORT_04_PIN_11 = 0x040B, ///< IO port 4 pin 11
IOPORT_PORT_04_PIN_12 = 0x040C, ///< IO port 4 pin 12
IOPORT_PORT_04_PIN_13 = 0x040D, ///< IO port 4 pin 13
IOPORT_PORT_04_PIN_14 = 0x040E, ///< IO port 4 pin 14
IOPORT_PORT_04_PIN_15 = 0x040F, ///< IO port 4 pin 15
IOPORT_PORT_05_PIN_00 = 0x0500, ///< IO port 5 pin 0
IOPORT_PORT_05_PIN_01 = 0x0501, ///< IO port 5 pin 1
IOPORT_PORT_05_PIN_02 = 0x0502, ///< IO port 5 pin 2
IOPORT_PORT_05_PIN_03 = 0x0503, ///< IO port 5 pin 3
IOPORT_PORT_05_PIN_04 = 0x0504, ///< IO port 5 pin 4
IOPORT_PORT_05_PIN_05 = 0x0505, ///< IO port 5 pin 5
IOPORT_PORT_05_PIN_06 = 0x0506, ///< IO port 5 pin 6
IOPORT_PORT_05_PIN_07 = 0x0507, ///< IO port 5 pin 7
IOPORT_PORT_05_PIN_08 = 0x0508, ///< IO port 5 pin 8
IOPORT_PORT_05_PIN_09 = 0x0509, ///< IO port 5 pin 9
IOPORT_PORT_05_PIN_10 = 0x050A, ///< IO port 5 pin 10
IOPORT_PORT_05_PIN_11 = 0x050B, ///< IO port 5 pin 11
IOPORT_PORT_05_PIN_12 = 0x050C, ///< IO port 5 pin 12
IOPORT_PORT_05_PIN_13 = 0x050D, ///< IO port 5 pin 13
IOPORT_PORT_05_PIN_14 = 0x050E, ///< IO port 5 pin 14
IOPORT_PORT_05_PIN_15 = 0x050F, ///< IO port 5 pin 15
IOPORT_PORT_06_PIN_00 = 0x0600, ///< IO port 6 pin 0
IOPORT_PORT_06_PIN_01 = 0x0601, ///< IO port 6 pin 1
IOPORT_PORT_06_PIN_02 = 0x0602, ///< IO port 6 pin 2
IOPORT_PORT_06_PIN_03 = 0x0603, ///< IO port 6 pin 3
IOPORT_PORT_06_PIN_04 = 0x0604, ///< IO port 6 pin 4
IOPORT_PORT_06_PIN_05 = 0x0605, ///< IO port 6 pin 5
IOPORT_PORT_06_PIN_06 = 0x0606, ///< IO port 6 pin 6
IOPORT_PORT_06_PIN_07 = 0x0607, ///< IO port 6 pin 7
IOPORT_PORT_06_PIN_08 = 0x0608, ///< IO port 6 pin 8
IOPORT_PORT_06_PIN_09 = 0x0609, ///< IO port 6 pin 9
IOPORT_PORT_06_PIN_10 = 0x060A, ///< IO port 6 pin 10
IOPORT_PORT_06_PIN_11 = 0x060B, ///< IO port 6 pin 11
IOPORT_PORT_06_PIN_12 = 0x060C, ///< IO port 6 pin 12
IOPORT_PORT_06_PIN_13 = 0x060D, ///< IO port 6 pin 13
IOPORT_PORT_06_PIN_14 = 0x060E, ///< IO port 6 pin 14
IOPORT_PORT_06_PIN_15 = 0x060F, ///< IO port 6 pin 15
IOPORT_PORT_07_PIN_00 = 0x0700, ///< IO port 7 pin 0
IOPORT_PORT_07_PIN_01 = 0x0701, ///< IO port 7 pin 1
IOPORT_PORT_07_PIN_02 = 0x0702, ///< IO port 7 pin 2
IOPORT_PORT_07_PIN_03 = 0x0703, ///< IO port 7 pin 3
IOPORT_PORT_07_PIN_04 = 0x0704, ///< IO port 7 pin 4
IOPORT_PORT_07_PIN_05 = 0x0705, ///< IO port 7 pin 5
IOPORT_PORT_07_PIN_06 = 0x0706, ///< IO port 7 pin 6
IOPORT_PORT_07_PIN_07 = 0x0707, ///< IO port 7 pin 7
IOPORT_PORT_07_PIN_08 = 0x0708, ///< IO port 7 pin 8
IOPORT_PORT_07_PIN_09 = 0x0709, ///< IO port 7 pin 9
IOPORT_PORT_07_PIN_10 = 0x070A, ///< IO port 7 pin 10
IOPORT_PORT_07_PIN_11 = 0x070B, ///< IO port 7 pin 11
IOPORT_PORT_07_PIN_12 = 0x070C, ///< IO port 7 pin 12
IOPORT_PORT_07_PIN_13 = 0x070D, ///< IO port 7 pin 13
IOPORT_PORT_07_PIN_14 = 0x070E, ///< IO port 7 pin 14
IOPORT_PORT_07_PIN_15 = 0x070F, ///< IO port 7 pin 15
IOPORT_PORT_08_PIN_00 = 0x0800, ///< IO port 8 pin 0
IOPORT_PORT_08_PIN_01 = 0x0801, ///< IO port 8 pin 1
IOPORT_PORT_08_PIN_02 = 0x0802, ///< IO port 8 pin 2
IOPORT_PORT_08_PIN_03 = 0x0803, ///< IO port 8 pin 3
IOPORT_PORT_08_PIN_04 = 0x0804, ///< IO port 8 pin 4
IOPORT_PORT_08_PIN_05 = 0x0805, ///< IO port 8 pin 5
IOPORT_PORT_08_PIN_06 = 0x0806, ///< IO port 8 pin 6
IOPORT_PORT_08_PIN_07 = 0x0807, ///< IO port 8 pin 7
IOPORT_PORT_08_PIN_08 = 0x0808, ///< IO port 8 pin 8
IOPORT_PORT_08_PIN_09 = 0x0809, ///< IO port 8 pin 9
IOPORT_PORT_08_PIN_10 = 0x080A, ///< IO port 8 pin 10
IOPORT_PORT_08_PIN_11 = 0x080B, ///< IO port 8 pin 11
IOPORT_PORT_08_PIN_12 = 0x080C, ///< IO port 8 pin 12
IOPORT_PORT_08_PIN_13 = 0x080D, ///< IO port 8 pin 13
IOPORT_PORT_08_PIN_14 = 0x080E, ///< IO port 8 pin 14
IOPORT_PORT_08_PIN_15 = 0x080F, ///< IO port 8 pin 15
IOPORT_PORT_09_PIN_00 = 0x0900, ///< IO port 9 pin 0
IOPORT_PORT_09_PIN_01 = 0x0901, ///< IO port 9 pin 1
IOPORT_PORT_09_PIN_02 = 0x0902, ///< IO port 9 pin 2
IOPORT_PORT_09_PIN_03 = 0x0903, ///< IO port 9 pin 3
IOPORT_PORT_09_PIN_04 = 0x0904, ///< IO port 9 pin 4
IOPORT_PORT_09_PIN_05 = 0x0905, ///< IO port 9 pin 5
IOPORT_PORT_09_PIN_06 = 0x0906, ///< IO port 9 pin 6
IOPORT_PORT_09_PIN_07 = 0x0907, ///< IO port 9 pin 7
IOPORT_PORT_09_PIN_08 = 0x0908, ///< IO port 9 pin 8
IOPORT_PORT_09_PIN_09 = 0x0909, ///< IO port 9 pin 9
IOPORT_PORT_09_PIN_10 = 0x090A, ///< IO port 9 pin 10
IOPORT_PORT_09_PIN_11 = 0x090B, ///< IO port 9 pin 11
IOPORT_PORT_09_PIN_12 = 0x090C, ///< IO port 9 pin 12
IOPORT_PORT_09_PIN_13 = 0x090D, ///< IO port 9 pin 13
IOPORT_PORT_09_PIN_14 = 0x090E, ///< IO port 9 pin 14
IOPORT_PORT_09_PIN_15 = 0x090F, ///< IO port 9 pin 15
IOPORT_PORT_10_PIN_00 = 0x0A00, ///< IO port 10 pin 0
IOPORT_PORT_10_PIN_01 = 0x0A01, ///< IO port 10 pin 1
IOPORT_PORT_10_PIN_02 = 0x0A02, ///< IO port 10 pin 2
IOPORT_PORT_10_PIN_03 = 0x0A03, ///< IO port 10 pin 3
IOPORT_PORT_10_PIN_04 = 0x0A04, ///< IO port 10 pin 4
IOPORT_PORT_10_PIN_05 = 0x0A05, ///< IO port 10 pin 5
IOPORT_PORT_10_PIN_06 = 0x0A06, ///< IO port 10 pin 6
IOPORT_PORT_10_PIN_07 = 0x0A07, ///< IO port 10 pin 7
IOPORT_PORT_10_PIN_08 = 0x0A08, ///< IO port 10 pin 8
IOPORT_PORT_10_PIN_09 = 0x0A09, ///< IO port 10 pin 9
IOPORT_PORT_10_PIN_10 = 0x0A0A, ///< IO port 10 pin 10
IOPORT_PORT_10_PIN_11 = 0x0A0B, ///< IO port 10 pin 11
IOPORT_PORT_10_PIN_12 = 0x0A0C, ///< IO port 10 pin 12
IOPORT_PORT_10_PIN_13 = 0x0A0D, ///< IO port 10 pin 13
IOPORT_PORT_10_PIN_14 = 0x0A0E, ///< IO port 10 pin 14
IOPORT_PORT_10_PIN_15 = 0x0A0F, ///< IO port 10 pin 15
IOPORT_PORT_11_PIN_00 = 0x0B00, ///< IO port 11 pin 0
IOPORT_PORT_11_PIN_01 = 0x0B01, ///< IO port 11 pin 1
IOPORT_PORT_11_PIN_02 = 0x0B02, ///< IO port 11 pin 2
IOPORT_PORT_11_PIN_03 = 0x0B03, ///< IO port 11 pin 3
IOPORT_PORT_11_PIN_04 = 0x0B04, ///< IO port 11 pin 4
IOPORT_PORT_11_PIN_05 = 0x0B05, ///< IO port 11 pin 5
IOPORT_PORT_11_PIN_06 = 0x0B06, ///< IO port 11 pin 6
IOPORT_PORT_11_PIN_07 = 0x0B07, ///< IO port 11 pin 7
IOPORT_PORT_11_PIN_08 = 0x0B08, ///< IO port 11 pin 8
IOPORT_PORT_11_PIN_09 = 0x0B09, ///< IO port 11 pin 9
IOPORT_PORT_11_PIN_10 = 0x0B0A, ///< IO port 11 pin 10
IOPORT_PORT_11_PIN_11 = 0x0B0B, ///< IO port 11 pin 11
IOPORT_PORT_11_PIN_12 = 0x0B0C, ///< IO port 11 pin 12
IOPORT_PORT_11_PIN_13 = 0x0B0D, ///< IO port 11 pin 13
IOPORT_PORT_11_PIN_14 = 0x0B0E, ///< IO port 11 pin 14
IOPORT_PORT_11_PIN_15 = 0x0B0F, ///< IO port 11 pin 15
IOPORT_PORT_12_PIN_00 = 0x0C00, ///< IO port 12 pin 0
IOPORT_PORT_12_PIN_01 = 0x0C01, ///< IO port 12 pin 1
IOPORT_PORT_12_PIN_02 = 0x0C02, ///< IO port 12 pin 2
IOPORT_PORT_12_PIN_03 = 0x0C03, ///< IO port 12 pin 3
IOPORT_PORT_12_PIN_04 = 0x0C04, ///< IO port 12 pin 4
IOPORT_PORT_12_PIN_05 = 0x0C05, ///< IO port 12 pin 5
IOPORT_PORT_12_PIN_06 = 0x0C06, ///< IO port 12 pin 6
IOPORT_PORT_12_PIN_07 = 0x0C07, ///< IO port 12 pin 7
IOPORT_PORT_12_PIN_08 = 0x0C08, ///< IO port 12 pin 8
IOPORT_PORT_12_PIN_09 = 0x0C09, ///< IO port 12 pin 9
IOPORT_PORT_12_PIN_10 = 0x0C0A, ///< IO port 12 pin 10
IOPORT_PORT_12_PIN_11 = 0x0C0B, ///< IO port 12 pin 11
IOPORT_PORT_12_PIN_12 = 0x0C0C, ///< IO port 12 pin 12
IOPORT_PORT_12_PIN_13 = 0x0C0D, ///< IO port 12 pin 13
IOPORT_PORT_12_PIN_14 = 0x0C0E, ///< IO port 12 pin 14
IOPORT_PORT_12_PIN_15 = 0x0C0F, ///< IO port 12 pin 15
IOPORT_PORT_13_PIN_00 = 0x0D00, ///< IO port 13 pin 0
IOPORT_PORT_13_PIN_01 = 0x0D01, ///< IO port 13 pin 1
IOPORT_PORT_13_PIN_02 = 0x0D02, ///< IO port 13 pin 2
IOPORT_PORT_13_PIN_03 = 0x0D03, ///< IO port 13 pin 3
IOPORT_PORT_13_PIN_04 = 0x0D04, ///< IO port 13 pin 4
IOPORT_PORT_13_PIN_05 = 0x0D05, ///< IO port 13 pin 5
IOPORT_PORT_13_PIN_06 = 0x0D06, ///< IO port 13 pin 6
IOPORT_PORT_13_PIN_07 = 0x0D07, ///< IO port 13 pin 7
IOPORT_PORT_13_PIN_08 = 0x0D08, ///< IO port 13 pin 8
IOPORT_PORT_13_PIN_09 = 0x0D09, ///< IO port 13 pin 9
IOPORT_PORT_13_PIN_10 = 0x0D0A, ///< IO port 13 pin 10
IOPORT_PORT_13_PIN_11 = 0x0D0B, ///< IO port 13 pin 11
IOPORT_PORT_13_PIN_12 = 0x0D0C, ///< IO port 13 pin 12
IOPORT_PORT_13_PIN_13 = 0x0D0D, ///< IO port 13 pin 13
IOPORT_PORT_13_PIN_14 = 0x0D0E, ///< IO port 13 pin 14
IOPORT_PORT_13_PIN_15 = 0x0D0F, ///< IO port 13 pin 15
IOPORT_PORT_14_PIN_00 = 0x0E00, ///< IO port 14 pin 0
IOPORT_PORT_14_PIN_01 = 0x0E01, ///< IO port 14 pin 1
IOPORT_PORT_14_PIN_02 = 0x0E02, ///< IO port 14 pin 2
IOPORT_PORT_14_PIN_03 = 0x0E03, ///< IO port 14 pin 3
IOPORT_PORT_14_PIN_04 = 0x0E04, ///< IO port 14 pin 4
IOPORT_PORT_14_PIN_05 = 0x0E05, ///< IO port 14 pin 5
IOPORT_PORT_14_PIN_06 = 0x0E06, ///< IO port 14 pin 6
IOPORT_PORT_14_PIN_07 = 0x0E07, ///< IO port 14 pin 7
IOPORT_PORT_14_PIN_08 = 0x0E08, ///< IO port 14 pin 8
IOPORT_PORT_14_PIN_09 = 0x0E09, ///< IO port 14 pin 9
IOPORT_PORT_14_PIN_10 = 0x0E0A, ///< IO port 14 pin 10
IOPORT_PORT_14_PIN_11 = 0x0E0B, ///< IO port 14 pin 11
IOPORT_PORT_14_PIN_12 = 0x0E0C, ///< IO port 14 pin 12
IOPORT_PORT_14_PIN_13 = 0x0E0D, ///< IO port 14 pin 13
IOPORT_PORT_14_PIN_14 = 0x0E0E, ///< IO port 14 pin 14
IOPORT_PORT_14_PIN_15 = 0x0E0F, ///< IO port 14 pin 15
} ioport_port_pin_t;
/** Superset of all peripheral functions. */
typedef enum e_ioport_peripheral
{
/** Pin will functions as an IO pin */
IOPORT_PERIPHERAL_IO = 0x00,
/** Pin will function as a DEBUG pin */
IOPORT_PERIPHERAL_DEBUG = (0x00UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as an AGT peripheral pin */
IOPORT_PERIPHERAL_AGT = (0x01UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as an AGT peripheral pin */
IOPORT_PERIPHERAL_AGTW = (0x01UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as an AGT peripheral pin */
IOPORT_PERIPHERAL_AGT1 = (0x18UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a GPT peripheral pin */
IOPORT_PERIPHERAL_GPT0 = (0x02UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a GPT peripheral pin */
IOPORT_PERIPHERAL_GPT1 = (0x03UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as an SCI peripheral pin */
IOPORT_PERIPHERAL_SCI0_2_4_6_8 = (0x04UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as an SCI peripheral pin */
IOPORT_PERIPHERAL_SCI1_3_5_7_9 = (0x05UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a SPI peripheral pin */
IOPORT_PERIPHERAL_SPI = (0x06UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a IIC peripheral pin */
IOPORT_PERIPHERAL_IIC = (0x07UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a KEY peripheral pin */
IOPORT_PERIPHERAL_KEY = (0x08UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a clock/comparator/RTC peripheral pin */
IOPORT_PERIPHERAL_CLKOUT_COMP_RTC = (0x09UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a CAC/ADC peripheral pin */
IOPORT_PERIPHERAL_CAC_AD = (0x0AUL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a BUS peripheral pin */
IOPORT_PERIPHERAL_BUS = (0x0BUL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a CTSU peripheral pin */
IOPORT_PERIPHERAL_CTSU = (0x0CUL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a CMPHS peripheral pin */
IOPORT_PERIPHERAL_ACMPHS = (0x0CUL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a segment LCD peripheral pin */
IOPORT_PERIPHERAL_LCDC = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET),
#if BSP_FEATURE_SCI_UART_DE_IS_INVERTED
/** Pin will function as an SCI peripheral DEn pin */
IOPORT_PERIPHERAL_DE_SCI1_3_5_7_9 = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as an SCI DEn peripheral pin */
IOPORT_PERIPHERAL_DE_SCI0_2_4_6_8 = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET),
#else
/** Pin will function as an SCI peripheral DEn pin */
IOPORT_PERIPHERAL_DE_SCI0_2_4_6_8 = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as an SCI DEn peripheral pin */
IOPORT_PERIPHERAL_DE_SCI1_3_5_7_9 = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET),
#endif
/** Pin will function as a DALI peripheral pin */
IOPORT_PERIPHERAL_DALI = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a CEU peripheral pin */
IOPORT_PERIPHERAL_CEU = (0x0FUL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a CAN peripheral pin */
IOPORT_PERIPHERAL_CAN = (0x10UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a QSPI peripheral pin */
IOPORT_PERIPHERAL_QSPI = (0x11UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as an SSI peripheral pin */
IOPORT_PERIPHERAL_SSI = (0x12UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a USB full speed peripheral pin */
IOPORT_PERIPHERAL_USB_FS = (0x13UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a USB high speed peripheral pin */
IOPORT_PERIPHERAL_USB_HS = (0x14UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a GPT peripheral pin */
IOPORT_PERIPHERAL_GPT2 = (0x14UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as an SD/MMC peripheral pin */
IOPORT_PERIPHERAL_SDHI_MMC = (0x15UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a GPT peripheral pin */
IOPORT_PERIPHERAL_GPT3 = (0x15UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as an Ethernet MMI peripheral pin */
IOPORT_PERIPHERAL_ETHER_MII = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a GPT peripheral pin */
IOPORT_PERIPHERAL_GPT4 = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as an Ethernet RMMI peripheral pin */
IOPORT_PERIPHERAL_ETHER_RMII = (0x17UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a PDC peripheral pin */
IOPORT_PERIPHERAL_PDC = (0x18UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a graphics LCD peripheral pin */
IOPORT_PERIPHERAL_LCD_GRAPHICS = (0x19UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a CAC peripheral pin */
IOPORT_PERIPHERAL_CAC = (0x19UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a debug trace peripheral pin */
IOPORT_PERIPHERAL_TRACE = (0x1AUL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a OSPI peripheral pin */
IOPORT_PERIPHERAL_OSPI = (0x1CUL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a CEC peripheral pin */
IOPORT_PERIPHERAL_CEC = (0x1DUL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a PGAOUT peripheral pin */
IOPORT_PERIPHERAL_PGAOUT0 = (0x1DUL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a PGAOUT peripheral pin */
IOPORT_PERIPHERAL_PGAOUT1 = (0x1EUL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a ULPT peripheral pin */
IOPORT_PERIPHERAL_ULPT = (0x1EUL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a MIPI DSI peripheral pin */
IOPORT_PERIPHERAL_MIPI = (0x1FUL << IOPORT_PRV_PFS_PSEL_OFFSET),
} ioport_peripheral_t;
/** Options to configure pin functions */
typedef enum e_ioport_cfg_options
{
IOPORT_CFG_PORT_DIRECTION_INPUT = 0x00000000, ///< Sets the pin direction to input (default)
IOPORT_CFG_PORT_DIRECTION_OUTPUT = 0x00000004, ///< Sets the pin direction to output
IOPORT_CFG_PORT_OUTPUT_LOW = 0x00000000, ///< Sets the pin level to low
IOPORT_CFG_PORT_OUTPUT_HIGH = 0x00000001, ///< Sets the pin level to high
IOPORT_CFG_PULLUP_ENABLE = 0x00000010, ///< Enables the pin's internal pull-up
IOPORT_CFG_PIM_TTL = 0x00000020, ///< Enables the pin's input mode
IOPORT_CFG_NMOS_ENABLE = 0x00000040, ///< Enables the pin's NMOS open-drain output
IOPORT_CFG_PMOS_ENABLE = 0x00000080, ///< Enables the pin's PMOS open-drain ouput
IOPORT_CFG_DRIVE_MID = 0x00000400, ///< Sets pin drive output to medium
IOPORT_CFG_DRIVE_HS_HIGH = 0x00000800, ///< Sets pin drive output to high along with supporting high speed
IOPORT_CFG_DRIVE_MID_IIC = 0x00000C00, ///< Sets pin to drive output needed for IIC on a 20mA port
IOPORT_CFG_DRIVE_HIGH = 0x00000C00, ///< Sets pin drive output to high
IOPORT_CFG_EVENT_RISING_EDGE = 0x00001000, ///< Sets pin event trigger to rising edge
IOPORT_CFG_EVENT_FALLING_EDGE = 0x00002000, ///< Sets pin event trigger to falling edge
IOPORT_CFG_EVENT_BOTH_EDGES = 0x00003000, ///< Sets pin event trigger to both edges
IOPORT_CFG_IRQ_ENABLE = 0x00004000, ///< Sets pin as an IRQ pin
IOPORT_CFG_ANALOG_ENABLE = 0x00008000, ///< Enables pin to operate as an analog pin
IOPORT_CFG_PERIPHERAL_PIN = 0x00010000 ///< Enables pin to operate as a peripheral pin
} ioport_cfg_options_t;
/**********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/** @cond INC_HEADER_DEFS_SEC */
/** Filled in Interface API structure for this Instance. */
extern const ioport_api_t g_ioport_on_ioport;
/** @endcond */
/***********************************************************************************************************************
* Public APIs
**********************************************************************************************************************/
fsp_err_t R_IOPORT_Open(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg);
fsp_err_t R_IOPORT_Close(ioport_ctrl_t * const p_ctrl);
fsp_err_t R_IOPORT_PinsCfg(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg);
fsp_err_t R_IOPORT_PinCfg(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg);
fsp_err_t R_IOPORT_PinEventInputRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event);
fsp_err_t R_IOPORT_PinEventOutputWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value);
fsp_err_t R_IOPORT_PinRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value);
fsp_err_t R_IOPORT_PinWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level);
fsp_err_t R_IOPORT_PortDirectionSet(ioport_ctrl_t * const p_ctrl,
bsp_io_port_t port,
ioport_size_t direction_values,
ioport_size_t mask);
fsp_err_t R_IOPORT_PortEventInputRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * event_data);
fsp_err_t R_IOPORT_PortEventOutputWrite(ioport_ctrl_t * const p_ctrl,
bsp_io_port_t port,
ioport_size_t event_data,
ioport_size_t mask_value);
fsp_err_t R_IOPORT_PortRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value);
fsp_err_t R_IOPORT_PortWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask);
/*******************************************************************************************************************//**
* @} (end defgroup IOPORT)
**********************************************************************************************************************/
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif // R_IOPORT_H

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/***********************************************************************************************************************
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef R_SCI_B_UART_H
#define R_SCI_B_UART_H
/*******************************************************************************************************************//**
* @addtogroup SCI_B_UART
* @{
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
#include "bsp_api.h"
#include "r_uart_api.h"
#include "r_sci_b_uart_cfg.h"
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/**********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** Enumeration for SCI clock source */
typedef enum e_sci_b_clk_src
{
SCI_B_UART_CLOCK_INT, ///< Use internal clock for baud generation
SCI_B_UART_CLOCK_INT_WITH_BAUDRATE_OUTPUT, ///< Use internal clock for baud generation and output on SCK
SCI_B_UART_CLOCK_EXT8X, ///< Use external clock 8x baud rate
SCI_B_UART_CLOCK_EXT16X ///< Use external clock 16x baud rate
} sci_b_clk_src_t;
/** UART flow control mode definition */
typedef enum e_sci_b_uart_flow_control
{
SCI_B_UART_FLOW_CONTROL_RTS = 0U, ///< Use CTSn_RTSn pin for RTS
SCI_B_UART_FLOW_CONTROL_CTS = 1U, ///< Use CTSn_RTSn pin for CTS
SCI_B_UART_FLOW_CONTROL_HARDWARE_CTSRTS = 3U, ///< Use CTSn pin for CTS, CTSn_RTSn pin for RTS
SCI_B_UART_FLOW_CONTROL_CTSRTS = 5U, ///< Use SCI pin for CTS, external pin for RTS
} sci_b_uart_flow_control_t;
/** UART instance control block. */
typedef struct st_sci_b_uart_instance_ctrl
{
/* Parameters to control UART peripheral device */
uint8_t fifo_depth; // FIFO depth of the UART channel
uint8_t rx_transfer_in_progress; // Set to 1 if a receive transfer is in progress, 0 otherwise
uint8_t data_bytes : 2; // 1 byte for 7 or 8 bit data, 2 bytes for 9 bit data
uint8_t bitrate_modulation : 1; // 1 if bit rate modulation is enabled, 0 otherwise
uint32_t open; // Used to determine if the channel is configured
bsp_io_port_pin_t flow_pin;
/* Source buffer pointer used to fill hardware FIFO from transmit ISR. */
uint8_t const * p_tx_src;
/* Size of source buffer pointer used to fill hardware FIFO from transmit ISR. */
uint32_t tx_src_bytes;
/* Destination buffer pointer used for receiving data. */
uint8_t const * p_rx_dest;
/* Size of destination buffer pointer used for receiving data. */
uint32_t rx_dest_bytes;
/* Pointer to the configuration block. */
uart_cfg_t const * p_cfg;
/* Base register for this channel */
R_SCI_B0_Type * p_reg;
void (* p_callback)(uart_callback_args_t *); // Pointer to callback that is called when a uart_event_t occurs.
uart_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory.
/* Pointer to context to be passed into callback function */
void const * p_context;
} sci_b_uart_instance_ctrl_t;
/** Receive FIFO trigger configuration. */
typedef enum e_sci_b_uart_rx_fifo_trigger
{
SCI_B_UART_RX_FIFO_TRIGGER_1 = 0x1, ///< Callback after each byte is received without buffering
SCI_B_UART_RX_FIFO_TRIGGER_MAX = 0xF, ///< Callback when FIFO is full or after 15 bit times with no data (fewer interrupts)
} sci_b_uart_rx_fifo_trigger_t;
/** Asynchronous Start Bit Edge Detection configuration. */
typedef enum e_sci_b_uart_start_bit_detect
{
SCI_B_UART_START_BIT_LOW_LEVEL = 0x0, ///< Detect low level on RXDn pin as start bit
SCI_B_UART_START_BIT_FALLING_EDGE = 0x1, ///< Detect falling level on RXDn pin as start bit
} sci_b_uart_start_bit_detect_t;
/** Noise cancellation configuration. */
typedef enum e_sci_b_uart_noise_cancellation
{
SCI_B_UART_NOISE_CANCELLATION_DISABLE = 0x0, ///< Disable noise cancellation
SCI_B_UART_NOISE_CANCELLATION_ENABLE = 0x1, ///< Enable noise cancellation
} sci_b_uart_noise_cancellation_t;
/** RS-485 Enable/Disable. */
typedef enum e_sci_b_uart_rs485_enable
{
SCI_B_UART_RS485_DISABLE = 0, ///< RS-485 disabled.
SCI_B_UART_RS485_ENABLE = 1, ///< RS-485 enabled.
} sci_b_uart_rs485_enable_t;
/** The polarity of the RS-485 DE signal. */
typedef enum e_sci_b_uart_rs485_de_polarity
{
SCI_B_UART_RS485_DE_POLARITY_HIGH = 0, ///< The DE signal is high when a write transfer is in progress.
SCI_B_UART_RS485_DE_POLARITY_LOW = 1, ///< The DE signal is low when a write transfer is in progress.
} sci_b_uart_rs485_de_polarity_t;
/** Register settings to acheive a desired baud rate and modulation duty. */
typedef struct st_sci_b_baud_setting_t
{
union
{
uint32_t baudrate_bits;
struct
{
uint32_t : 3;
uint32_t : 1;
uint32_t bgdm : 1; ///< Baud Rate Generator Double-Speed Mode Select
uint32_t abcs : 1; ///< Asynchronous Mode Base Clock Select
uint32_t abcse : 1; ///< Asynchronous Mode Extended Base Clock Select 1
uint32_t : 1;
uint32_t brr : 8; ///< Bit Rate Register setting
uint32_t brme : 1; ///< Bit Rate Modulation Enable
uint32_t : 3;
uint32_t cks : 2; ///< CKS value to get divisor (CKS = N)
uint32_t : 2;
uint32_t mddr : 8; ///< Modulation Duty Register setting
} baudrate_bits_b;
};
} sci_b_baud_setting_t;
/** Configuration settings for controlling the DE signal for RS-485. */
typedef struct st_sci_b_uart_rs485_setting
{
sci_b_uart_rs485_enable_t enable; ///< Enable the DE signal.
sci_b_uart_rs485_de_polarity_t polarity; ///< DE signal polarity.
uint8_t assertion_time : 5; ///< Time in baseclock units after assertion of the DE signal and before the start of the write transfer.
uint8_t negation_time : 5; ///< Time in baseclock units after the end of a write transfer and before the DE signal is negated.
} sci_b_uart_rs485_setting_t;
/** UART on SCI device Configuration */
typedef struct st_sci_b_uart_extended_cfg
{
sci_b_clk_src_t clock; ///< The source clock for the baud-rate generator. If internal optionally output baud rate on SCK
sci_b_uart_start_bit_detect_t rx_edge_start; ///< Start reception on falling edge
sci_b_uart_noise_cancellation_t noise_cancel; ///< Noise cancellation setting
sci_b_baud_setting_t * p_baud_setting; ///< Register settings for a desired baud rate.
sci_b_uart_rx_fifo_trigger_t rx_fifo_trigger; ///< Receive FIFO trigger level, unused if channel has no FIFO or if DTC is used.
bsp_io_port_pin_t flow_control_pin; ///< UART Driver Enable pin
sci_b_uart_flow_control_t flow_control; ///< CTS/RTS function of the SSn pin
sci_b_uart_rs485_setting_t rs485_setting; ///< RS-485 settings.
} sci_b_uart_extended_cfg_t;
/**********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/** @cond INC_HEADER_DEFS_SEC */
/** Filled in Interface API structure for this Instance. */
extern const uart_api_t g_uart_on_sci_b;
/** @endcond */
fsp_err_t R_SCI_B_UART_Open(uart_ctrl_t * const p_api_ctrl, uart_cfg_t const * const p_cfg);
fsp_err_t R_SCI_B_UART_Read(uart_ctrl_t * const p_api_ctrl, uint8_t * const p_dest, uint32_t const bytes);
fsp_err_t R_SCI_B_UART_Write(uart_ctrl_t * const p_api_ctrl, uint8_t const * const p_src, uint32_t const bytes);
fsp_err_t R_SCI_B_UART_BaudSet(uart_ctrl_t * const p_api_ctrl, void const * const p_baud_setting);
fsp_err_t R_SCI_B_UART_InfoGet(uart_ctrl_t * const p_api_ctrl, uart_info_t * const p_info);
fsp_err_t R_SCI_B_UART_Close(uart_ctrl_t * const p_api_ctrl);
fsp_err_t R_SCI_B_UART_Abort(uart_ctrl_t * const p_api_ctrl, uart_dir_t communication_to_abort);
fsp_err_t R_SCI_B_UART_BaudCalculate(uint32_t baudrate,
bool bitrate_modulation,
uint32_t baud_rate_error_x_1000,
sci_b_baud_setting_t * const p_baud_setting);
fsp_err_t R_SCI_B_UART_CallbackSet(uart_ctrl_t * const p_api_ctrl,
void ( * p_callback)(uart_callback_args_t *),
void const * const p_context,
uart_callback_args_t * const p_callback_memory);
fsp_err_t R_SCI_B_UART_ReadStop(uart_ctrl_t * const p_api_ctrl, uint32_t * remaining_bytes);
/*******************************************************************************************************************//**
* @} (end addtogroup SCI_B_UART)
**********************************************************************************************************************/
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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/***********************************************************************************************************************
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/* Ensure Renesas MCU variation definitions are included to ensure MCU
* specific register variations are handled correctly. */
#ifndef BSP_FEATURE_H
#error "INTERNAL ERROR: bsp_feature.h must be included before renesas.h."
#endif
/** @addtogroup Renesas
* @{
*/
/** @addtogroup RA
* @{
*/
#ifndef RA_H
#define RA_H
#ifdef __cplusplus
extern "C" {
#endif
/* Workaround for LLVM. __ARM_ARCH_8_1M_MAIN__ is defined for CM85 parts. But CMSIS_5 does not support this */
#if defined(__llvm__) && !defined(__CLANG_TIDY__) && defined(__ARM_ARCH_8_1M_MAIN__)
#undef __ARM_ARCH_8_1M_MAIN__
#define __ARM_ARCH_8M_MAIN__ 1
#endif
#include "cmsis_compiler.h"
/* Workaround for compilers that are not defining __ARM_ARCH_8_1M_MAIN__ for CM85 parts. */
#if BSP_CFG_MCU_PART_SERIES == 8
#undef __ARM_ARCH_8M_MAIN__
#define __ARM_ARCH_8_1M_MAIN__ 1
#endif
/** @addtogroup Configuration_of_CMSIS
* @{
*/
/* =========================================================================================================================== */
/* ================ Interrupt Number Definition ================ */
/* =========================================================================================================================== */
/* IRQn_Type is provided in bsp_exceptions.h. Vectors generated by the FSP Configuration tool are in vector_data.h */
/** @} */ /* End of group Configuration_of_CMSIS */
/* =========================================================================================================================== */
/* ================ Processor and Core Peripheral Section ================ */
/* =========================================================================================================================== */
#if BSP_MCU_GROUP_RA2A1
#include "R7FA2A1AB.h"
#elif BSP_MCU_GROUP_RA2E1
#include "R7FA2E1A9.h"
#elif BSP_MCU_GROUP_RA2E2
#include "R7FA2E2A7.h"
#elif BSP_MCU_GROUP_RA2E3
#include "R7FA2E307.h"
#elif BSP_MCU_GROUP_RA2L1
#include "R7FA2L1AB.h"
#elif BSP_MCU_GROUP_RA4E1
#include "R7FA4E10D.h"
#elif BSP_MCU_GROUP_RA4E2
#include "R7FA4E2B9.h"
#elif BSP_MCU_GROUP_RA4M1
#include "R7FA4M1AB.h"
#elif BSP_MCU_GROUP_RA4M2
#include "R7FA4M2AD.h"
#elif BSP_MCU_GROUP_RA4M3
#include "R7FA4M3AF.h"
#elif BSP_MCU_GROUP_RA4T1
#include "R7FA4T1BB.h"
#elif BSP_MCU_GROUP_RA4W1
#include "R7FA4W1AD.h"
#elif BSP_MCU_GROUP_RA6E1
#include "R7FA6E10F.h"
#elif BSP_MCU_GROUP_RA6E2
#include "R7FA6E2BB.h"
#elif BSP_MCU_GROUP_RA6M1
#include "R7FA6M1AD.h"
#elif BSP_MCU_GROUP_RA6M2
#include "R7FA6M2AF.h"
#elif BSP_MCU_GROUP_RA6M3
#include "R7FA6M3AH.h"
#elif BSP_MCU_GROUP_RA6M4
#include "R7FA6M4AF.h"
#elif BSP_MCU_GROUP_RA6M5
#include "R7FA6M5BH.h"
#elif BSP_MCU_GROUP_RA6T1
#include "R7FA6T1AD.h"
#elif BSP_MCU_GROUP_RA6T2
#include "R7FA6T2BD.h"
#elif BSP_MCU_GROUP_RA6T3
#include "R7FA6T3BB.h"
#elif BSP_MCU_GROUP_RA8M1
#include "R7FA8M1AH.h"
#else
#if __has_include("renesas_internal.h")
#include "renesas_internal.h"
#else
#warning "Unsupported MCU"
#endif
#endif
#if __ARM_ARCH_7EM__
#define RENESAS_CORTEX_M4
#elif __ARM_ARCH_6M__
#define RENESAS_CORTEX_M0PLUS
#elif __ARM_ARCH_8M_BASE__
#define RENESAS_CORTEX_M23
#elif __ARM_ARCH_8M_MAIN__
#define RENESAS_CORTEX_M33
#elif __ARM_ARCH_8_1M_MAIN__
#define RENESAS_CORTEX_M85
#else
#warning Unsupported Architecture
#endif
#ifdef __cplusplus
}
#endif
#endif /* RA_H */
/** @} */ /* End of group RA */
/** @} */ /* End of group Renesas */

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/***********************************************************************************************************************
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef SYSTEM_RENESAS_ARM_H
#define SYSTEM_RENESAS_ARM_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /** System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit(void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate(void);
#ifdef __cplusplus
}
#endif
#endif

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/***********************************************************************************************************************
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
#include "bsp_api.h"
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#if BSP_TZ_SECURE_BUILD
#define BSP_TZ_STACK_SEAL_SIZE (8U)
#else
#define BSP_TZ_STACK_SEAL_SIZE (0U)
#endif
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/* Defines function pointers to be used with vector table. */
typedef void (* exc_ptr_t)(void);
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
/***********************************************************************************************************************
* Private global variables and functions
**********************************************************************************************************************/
void Reset_Handler(void);
void Default_Handler(void);
int32_t main(void);
/*******************************************************************************************************************//**
* MCU starts executing here out of reset. Main stack pointer is set up already.
**********************************************************************************************************************/
void Reset_Handler (void)
{
/* Initialize system using BSP. */
SystemInit();
/* Call user application. */
#ifdef __ARMCC_VERSION
main();
#elif defined(__GNUC__)
extern int entry(void);
entry();
#endif
while (1)
{
/* Infinite Loop. */
}
}
/*******************************************************************************************************************//**
* Default exception handler.
**********************************************************************************************************************/
void Default_Handler (void)
{
/** A error has occurred. The user will need to investigate the cause. Common problems are stack corruption
* or use of an invalid pointer. Use the Fault Status window in e2 studio or manually check the fault status
* registers for more information.
*/
BSP_CFG_HANDLE_UNRECOVERABLE_ERROR(0);
}
/* Main stack */
static uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT)
BSP_PLACE_IN_SECTION(BSP_SECTION_STACK);
/* Heap */
#if (BSP_CFG_HEAP_BYTES > 0)
BSP_DONT_REMOVE static uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) \
BSP_PLACE_IN_SECTION(BSP_SECTION_HEAP);
#endif
/* All system exceptions in the vector table are weak references to Default_Handler. If the user wishes to handle
* these exceptions in their code they should define their own function with the same name.
*/
#if defined(__ICCARM__)
#define WEAK_REF_ATTRIBUTE
#pragma weak HardFault_Handler = Default_Handler
#pragma weak MemManage_Handler = Default_Handler
#pragma weak BusFault_Handler = Default_Handler
#pragma weak UsageFault_Handler = Default_Handler
#pragma weak SecureFault_Handler = Default_Handler
#pragma weak SVC_Handler = Default_Handler
#pragma weak DebugMon_Handler = Default_Handler
#pragma weak PendSV_Handler = Default_Handler
#pragma weak SysTick_Handler = Default_Handler
#elif defined(__GNUC__)
#define WEAK_REF_ATTRIBUTE __attribute__((weak, alias("Default_Handler")))
#endif
void NMI_Handler(void); // NMI has many sources and is handled by BSP
void HardFault_Handler(void) WEAK_REF_ATTRIBUTE;
void MemManage_Handler(void) WEAK_REF_ATTRIBUTE;
void BusFault_Handler(void) WEAK_REF_ATTRIBUTE;
void UsageFault_Handler(void) WEAK_REF_ATTRIBUTE;
void SecureFault_Handler(void) WEAK_REF_ATTRIBUTE;
void SVC_Handler(void) WEAK_REF_ATTRIBUTE;
void DebugMon_Handler(void) WEAK_REF_ATTRIBUTE;
void PendSV_Handler(void) WEAK_REF_ATTRIBUTE;
void SysTick_Handler(void) WEAK_REF_ATTRIBUTE;
/* Vector table. */
BSP_DONT_REMOVE const exc_ptr_t __Vectors[BSP_CORTEX_VECTOR_TABLE_ENTRIES] BSP_PLACE_IN_SECTION(
BSP_SECTION_FIXED_VECTORS) =
{
(exc_ptr_t) (&g_main_stack[0] + BSP_CFG_STACK_MAIN_BYTES), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* NMI Handler */
HardFault_Handler, /* Hard Fault Handler */
MemManage_Handler, /* MPU Fault Handler */
BusFault_Handler, /* Bus Fault Handler */
UsageFault_Handler, /* Usage Fault Handler */
SecureFault_Handler, /* Secure Fault Handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* SVCall Handler */
DebugMon_Handler, /* Debug Monitor Handler */
0, /* Reserved */
PendSV_Handler, /* PendSV Handler */
SysTick_Handler, /* SysTick Handler */
};
/** @} (end addtogroup BSP_MCU) */

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/***********************************************************************************************************************
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
#include <string.h>
#if defined(__GNUC__) && defined(__llvm__) && !defined(__ARMCC_VERSION) && !defined(__CLANG_TIDY__)
#include <picotls.h>
#endif
#include "bsp_api.h"
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/* Mask to select CP bits( 0xF00000 ) */
#define CP_MASK (0xFU << 20)
/* Startup value for CCR to enable instruction cache, branch prediction and LOB extension */
#define CCR_CACHE_ENABLE (0x000E0201)
/* Value to write to OAD register of MPU stack monitor to enable NMI when a stack overflow is detected. */
#define BSP_STACK_POINTER_MONITOR_NMI_ON_DETECTION (0xA500U)
/* Key code for writing PRCR register. */
#define BSP_PRV_PRCR_KEY (0xA500U)
#define BSP_PRV_PRCR_PRC1_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x2U)
#define BSP_PRV_PRCR_LOCK ((BSP_PRV_PRCR_KEY) | 0x0U)
#define BSP_PRV_STACK_LIMIT ((uint32_t) __Vectors[0] - BSP_CFG_STACK_MAIN_BYTES)
#define BSP_PRV_STACK_TOP ((uint32_t) __Vectors[0])
#define BSP_TZ_STACK_SEAL_VALUE (0xFEF5EDA5)
#define ARMV8_MPU_REGION_MIN_SIZE (32U)
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
/** System Clock Frequency (Core Clock) */
uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
#if defined(__ARMCC_VERSION)
extern uint32_t Image$$BSS$$ZI$$Base;
extern uint32_t Image$$BSS$$ZI$$Length;
extern uint32_t Load$$DATA$$Base;
extern uint32_t Image$$DATA$$Base;
extern uint32_t Image$$DATA$$Length;
extern uint32_t Image$$STACK$$ZI$$Base;
extern uint32_t Image$$STACK$$ZI$$Length;
#if BSP_FEATURE_BSP_HAS_ITCM
extern uint32_t Load$$ITCM_DATA$$Base;
extern uint32_t Load$$ITCM_PAD$$Limit;
extern uint32_t Image$$ITCM_DATA$$Base;
#endif
#if BSP_FEATURE_BSP_HAS_DTCM
extern uint32_t Load$$DTCM_DATA$$Base;
extern uint32_t Load$$DTCM_PAD$$Limit;
extern uint32_t Image$$DTCM_DATA$$Base;
extern uint32_t Image$$DTCM_BSS$$Base;
extern uint32_t Image$$DTCM_BSS_PAD$$ZI$$Limit;
#endif
#if BSP_CFG_DCACHE_ENABLED
extern uint32_t Image$$NOCACHE$$ZI$$Base;
extern uint32_t Image$$NOCACHE_PAD$$ZI$$Limit;
extern uint32_t Image$$NOCACHE_SDRAM$$ZI$$Base;
extern uint32_t Image$$NOCACHE_SDRAM_PAD$$ZI$$Limit;
#endif
#elif defined(__GNUC__)
/* Generated by linker. */
extern uint32_t __etext;
extern uint32_t __data_start__;
extern uint32_t __data_end__;
extern uint32_t __bss_start__;
extern uint32_t __bss_end__;
extern uint32_t __StackLimit;
extern uint32_t __StackTop;
/* Nested in __GNUC__ because LLVM generates both __GNUC__ and __llvm__*/
#if defined(__llvm__) && !defined(__CLANG_TIDY__)
extern uint32_t __tls_base;
#endif
#if BSP_FEATURE_BSP_HAS_ITCM
extern uint32_t __itcm_data_init_start;
extern uint32_t __itcm_data_init_end;
extern uint32_t __itcm_data_start;
#endif
#if BSP_FEATURE_BSP_HAS_DTCM
extern uint32_t __dtcm_data_init_start;
extern uint32_t __dtcm_data_init_end;
extern uint32_t __dtcm_data_start;
extern uint32_t __dtcm_bss_start;
extern uint32_t __dtcm_bss_end;
#endif
#if BSP_CFG_DCACHE_ENABLED
extern uint32_t __nocache_start;
extern uint32_t __nocache_end;
extern uint32_t __nocache_sdram_start;
extern uint32_t __nocache_sdram_end;
#endif
#elif defined(__ICCARM__)
#pragma section=".bss"
#pragma section=".data"
#pragma section=".data_init"
#pragma section=".stack"
#if BSP_FEATURE_BSP_HAS_ITCM
extern uint32_t ITCM_DATA_INIT$$Base;
extern uint32_t ITCM_DATA_INIT$$Limit;
extern uint32_t ITCM_DATA$$Base;
#endif
#if BSP_FEATURE_BSP_HAS_DTCM
extern uint32_t DTCM_DATA_INIT$$Base;
extern uint32_t DTCM_DATA_INIT$$Limit;
extern uint32_t DTCM_DATA$$Base;
extern uint32_t DTCM_BSS$$Base;
extern uint32_t DTCM_BSS$$Limit;
#endif
#if BSP_CFG_DCACHE_ENABLED
extern uint32_t NOCACHE$$Base;
extern uint32_t NOCACHE$$Limit;
extern uint32_t NOCACHE_SDRAM$$Base;
extern uint32_t NOCACHE_SDRAM$$Limit;
#endif
#endif
/* Initialize static constructors */
#if defined(__ARMCC_VERSION)
extern void (* Image$$INIT_ARRAY$$Base[])(void);
extern void (* Image$$INIT_ARRAY$$Limit[])(void);
#elif defined(__GNUC__)
extern void (* __init_array_start[])(void);
extern void (* __init_array_end[])(void);
#elif defined(__ICCARM__)
extern void __call_ctors(void const *, void const *);
#pragma section = "SHT$$PREINIT_ARRAY" const
#pragma section = "SHT$$INIT_ARRAY" const
#endif
extern void * __Vectors[];
extern void R_BSP_SecurityInit(void);
/***********************************************************************************************************************
* Private global variables and functions
**********************************************************************************************************************/
#if BSP_FEATURE_BSP_RESET_TRNG
static void bsp_reset_trng_circuit(void);
#endif
#if defined(__ICCARM__)
void R_BSP_WarmStart(bsp_warm_start_event_t event);
#pragma weak R_BSP_WarmStart
#elif defined(__GNUC__) || defined(__ARMCC_VERSION)
void R_BSP_WarmStart(bsp_warm_start_event_t event) __attribute__((weak));
#endif
#if BSP_CFG_EARLY_INIT
static void bsp_init_uninitialized_vars(void);
#endif
#if BSP_CFG_C_RUNTIME_INIT
#if BSP_FEATURE_BSP_HAS_ITCM || BSP_FEATURE_BSP_HAS_DTCM
static void memcpy_64(uint64_t * destination, const uint64_t * source, size_t count);
#endif
#if BSP_FEATURE_BSP_HAS_DTCM
static void memset_64(uint64_t * destination, const uint64_t value, size_t count);
#endif
#endif
#if BSP_CFG_C_RUNTIME_INIT
#if BSP_FEATURE_BSP_HAS_ITCM
static void bsp_init_itcm(void);
#endif
#if BSP_FEATURE_BSP_HAS_DTCM
static void bsp_init_dtcm(void);
#endif
#endif
#if BSP_CFG_DCACHE_ENABLED
static void bsp_init_mpu(void);
#endif
/*******************************************************************************************************************//**
* Initialize the MCU and the runtime environment.
**********************************************************************************************************************/
void SystemInit (void)
{
#if defined(RENESAS_CORTEX_M85)
/* Enable the instruction cache, branch prediction, and the branch cache (required for Low Overhead Branch (LOB) extension).
* See sections 6.5, 6.6, and 6.7 in the Arm Cortex-M85 Processor Technical Reference Manual (Document ID: 101924_0002_05_en, Issue: 05)
* See section D1.2.9 in the Armv8-M Architecture Reference Manual (Document number: DDI0553B.w, Document version: ID07072023) */
SCB->CCR = (uint32_t) CCR_CACHE_ENABLE;
__DSB();
__ISB();
#endif
#if __FPU_USED
/* Enable the FPU only when it is used.
* Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C) */
/* Set bits 20-23 (CP10 and CP11) to enable FPU. */
SCB->CPACR = (uint32_t) CP_MASK;
#endif
#if BSP_TZ_SECURE_BUILD
/* Seal the main stack for secure projects. Reference:
* https://developer.arm.com/documentation/100720/0300
* https://developer.arm.com/support/arm-security-updates/armv8-m-stack-sealing */
uint32_t * p_main_stack_top = (uint32_t *) __Vectors[0];
*p_main_stack_top = BSP_TZ_STACK_SEAL_VALUE;
#endif
#if !BSP_TZ_NONSECURE_BUILD
#if BSP_FEATURE_BSP_SECURITY_PREINIT
R_BSP_SecurityPreinit();
#endif
/* VTOR is in undefined state out of RESET:
* https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-control-block/system-control-block-registers-summary?lang=en.
* Set the Secure/Non-Secure VTOR to the vector table address based on the build. This is skipped for non-secure
* projects because SCB_NS->VTOR is set by the secure project before the non-secure project runs. */
SCB->VTOR = (uint32_t) &__Vectors;
#endif
#if !BSP_TZ_CFG_SKIP_INIT
#if BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP
/* Unlock VBTCR1 register. */
R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_PRC1_UNLOCK;
/* The VBTCR1.BPWSWSTP must be set after reset on MCUs that have VBTCR1.BPWSWSTP. Reference section 11.2.1
* "VBATT Control Register 1 (VBTCR1)" and Figure 11.2 "Setting flow of the VBTCR1.BPWSWSTP bit" in the RA4M1 manual
* R01UM0007EU0110. This must be done before bsp_clock_init because LOCOCR, LOCOUTCR, SOSCCR, and SOMCR cannot
* be accessed until VBTSR.VBTRVLD is set. */
R_SYSTEM->VBTCR1 = 1U;
FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->VBTSR_b.VBTRVLD, 1U);
/* Lock VBTCR1 register. */
R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK;
#endif
#endif
#if BSP_FEATURE_TFU_SUPPORTED
R_BSP_MODULE_START(FSP_IP_TFU, 0U);
#endif
#if BSP_CFG_EARLY_INIT
/* Initialize uninitialized BSP variables early for use in R_BSP_WarmStart. */
bsp_init_uninitialized_vars();
#endif
/* Call pre clock initialization hook. */
R_BSP_WarmStart(BSP_WARM_START_RESET);
#if BSP_TZ_CFG_SKIP_INIT
/* Initialize clock variables to be used with R_BSP_SoftwareDelay. */
bsp_clock_freq_var_init();
#else
/* Configure system clocks. */
bsp_clock_init();
#if BSP_FEATURE_BSP_RESET_TRNG
/* To prevent an undesired current draw, this MCU requires a reset
* of the TRNG circuit after the clocks are initialized */
bsp_reset_trng_circuit();
#endif
#endif
/* Call post clock initialization hook. */
R_BSP_WarmStart(BSP_WARM_START_POST_CLOCK);
#if BSP_FEATURE_BSP_HAS_SP_MON
/* Disable MSP monitoring */
R_MPU_SPMON->SP[0].CTL = 0;
/* Setup NMI interrupt */
R_MPU_SPMON->SP[0].OAD = BSP_STACK_POINTER_MONITOR_NMI_ON_DETECTION;
/* Setup start address */
R_MPU_SPMON->SP[0].SA = BSP_PRV_STACK_LIMIT;
/* Setup end address */
R_MPU_SPMON->SP[0].EA = BSP_PRV_STACK_TOP;
/* Set SPEEN bit to enable NMI on stack monitor exception. NMIER bits cannot be cleared after reset, so no need
* to read-modify-write. */
R_ICU->NMIER = R_ICU_NMIER_SPEEN_Msk;
/* Enable MSP monitoring */
R_MPU_SPMON->SP[0].CTL = 1U;
#endif
#if BSP_FEATURE_TZ_HAS_TRUSTZONE
__set_MSPLIM(BSP_PRV_STACK_LIMIT);
#endif
#if BSP_CFG_C_RUNTIME_INIT
/* Initialize C runtime environment. */
/* Zero out BSS */
#if defined(__ARMCC_VERSION)
memset((uint8_t *) &Image$$BSS$$ZI$$Base, 0U, (uint32_t) &Image$$BSS$$ZI$$Length);
#elif defined(__GNUC__)
memset(&__bss_start__, 0U, ((uint32_t) &__bss_end__ - (uint32_t) &__bss_start__));
#elif defined(__ICCARM__)
memset((uint32_t *) __section_begin(".bss"), 0U, (uint32_t) __section_size(".bss"));
#endif
/* Copy initialized RAM data from ROM to RAM. */
#if defined(__ARMCC_VERSION)
memcpy((uint8_t *) &Image$$DATA$$Base, (uint8_t *) &Load$$DATA$$Base, (uint32_t) &Image$$DATA$$Length);
#elif defined(__GNUC__)
memcpy(&__data_start__, &__etext, ((uint32_t) &__data_end__ - (uint32_t) &__data_start__));
#elif defined(__ICCARM__)
memcpy((uint32_t *) __section_begin(".data"), (uint32_t *) __section_begin(".data_init"),
(uint32_t) __section_size(".data"));
/* Copy functions to be executed from RAM. */
#pragma section=".code_in_ram"
#pragma section=".code_in_ram_init"
memcpy((uint32_t *) __section_begin(".code_in_ram"),
(uint32_t *) __section_begin(".code_in_ram_init"),
(uint32_t) __section_size(".code_in_ram"));
/* Copy main thread TLS to RAM. */
#pragma section="__DLIB_PERTHREAD_init"
#pragma section="__DLIB_PERTHREAD"
memcpy((uint32_t *) __section_begin("__DLIB_PERTHREAD"), (uint32_t *) __section_begin("__DLIB_PERTHREAD_init"),
(uint32_t) __section_size("__DLIB_PERTHREAD_init"));
#endif
/* Initialize TCM memory. */
#if BSP_FEATURE_BSP_HAS_ITCM
bsp_init_itcm();
#endif
#if BSP_FEATURE_BSP_HAS_DTCM
bsp_init_dtcm();
#endif
#if defined(RENESAS_CORTEX_M85)
/* Invalidate I-Cache after initializing the .code_in_ram section. */
SCB_InvalidateICache();
#endif
#if defined(__GNUC__) && defined(__llvm__) && !defined(__CLANG_TIDY__) && !(defined __ARMCC_VERSION)
/* Initialize TLS memory. */
_init_tls(&__tls_base);
_set_tls(&__tls_base);
#endif
/* Initialize static constructors */
#if defined(__ARMCC_VERSION)
int32_t count = Image$$INIT_ARRAY$$Limit - Image$$INIT_ARRAY$$Base;
for (int32_t i = 0; i < count; i++)
{
void (* p_init_func)(void) =
(void (*)(void))((uint32_t) &Image$$INIT_ARRAY$$Base + (uint32_t) Image$$INIT_ARRAY$$Base[i]);
p_init_func();
}
#elif defined(__GNUC__)
int32_t count = __init_array_end - __init_array_start;
for (int32_t i = 0; i < count; i++)
{
__init_array_start[i]();
}
#elif defined(__ICCARM__)
void const * pibase = __section_begin("SHT$$PREINIT_ARRAY");
void const * ilimit = __section_end("SHT$$INIT_ARRAY");
__call_ctors(pibase, ilimit);
#endif
#endif // BSP_CFG_C_RUNTIME_INIT
#if BSP_FEATURE_BSP_POST_CRUNTIME_INIT
R_BSP_PostCRuntimeInit();
#endif
/* Initialize SystemCoreClock variable. */
SystemCoreClockUpdate();
#if BSP_FEATURE_RTC_IS_AVAILABLE || BSP_FEATURE_RTC_HAS_TCEN || BSP_FEATURE_SYSC_HAS_VBTICTLR
/* For TZ project, it should be called by the secure application, whether RTC module is to be configured as secure or not. */
#if !BSP_TZ_NONSECURE_BUILD && !BSP_CFG_BOOT_IMAGE
/* Perform RTC reset sequence to avoid unintended operation. */
R_BSP_Init_RTC();
#endif
#endif
#if !BSP_CFG_PFS_PROTECT && defined(R_PMISC)
#if BSP_TZ_SECURE_BUILD || (BSP_FEATURE_TZ_VERSION == 2 && FSP_PRIV_TZ_USE_SECURE_REGS)
R_PMISC->PWPRS = 0; ///< Clear BOWI bit - writing to PFSWE bit enabled
R_PMISC->PWPRS = 1U << BSP_IO_PWPR_PFSWE_OFFSET; ///< Set PFSWE bit - writing to PFS register enabled
#else
R_PMISC->PWPR = 0; ///< Clear BOWI bit - writing to PFSWE bit enabled
R_PMISC->PWPR = 1U << BSP_IO_PWPR_PFSWE_OFFSET; ///< Set PFSWE bit - writing to PFS register enabled
#endif
#endif
#if FSP_PRIV_TZ_USE_SECURE_REGS
/* Ensure that the PMSAR registers are set to their default value. */
R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR);
for (uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++)
{
#if BSP_FEATURE_TZ_VERSION == 2
R_PMISC->PMSAR[i].PMSAR = 0U;
#else
R_PMISC->PMSAR[i].PMSAR = UINT16_MAX;
#endif
}
R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR);
#endif
#if BSP_TZ_SECURE_BUILD
/* Initialize security features. */
R_BSP_SecurityInit();
#endif
#if BSP_CFG_DCACHE_ENABLED
bsp_init_mpu();
SCB_EnableDCache();
#endif
#if BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN
if ((((0 == R_SYSTEM->PGCSAR) && FSP_PRIV_TZ_USE_SECURE_REGS) ||
((1 == R_SYSTEM->PGCSAR) && BSP_TZ_NONSECURE_BUILD)) && (0 != R_SYSTEM->PDCTRGD))
{
/* Turn on graphics power domain.
* This requires MOCO to be enabled, but MOCO is always enabled after bsp_clock_init(). */
R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT);
FSP_HARDWARE_REGISTER_WAIT((R_SYSTEM->PDCTRGD & (R_SYSTEM_PDCTRGD_PDCSF_Msk | R_SYSTEM_PDCTRGD_PDPGSF_Msk)),
R_SYSTEM_PDCTRGD_PDPGSF_Msk);
R_SYSTEM->PDCTRGD = 0;
FSP_HARDWARE_REGISTER_WAIT((R_SYSTEM->PDCTRGD & (R_SYSTEM_PDCTRGD_PDCSF_Msk | R_SYSTEM_PDCTRGD_PDPGSF_Msk)), 0);
R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT);
}
#endif
/* Call Post C runtime initialization hook. */
R_BSP_WarmStart(BSP_WARM_START_POST_C);
/* Initialize ELC events that will be used to trigger NVIC interrupts. */
bsp_irq_cfg();
/* Call any BSP specific code. No arguments are needed so NULL is sent. */
bsp_init(NULL);
}
/*******************************************************************************************************************//**
* This function is called at various points during the startup process.
* This function is declared as a weak symbol higher up in this file because it is meant to be overridden by a user
* implemented version. One of the main uses for this function is to call functional safety code during the startup
* process. To use this function just copy this function into your own code and modify it to meet your needs.
*
* @param[in] event Where the code currently is in the start up process
**********************************************************************************************************************/
void R_BSP_WarmStart (bsp_warm_start_event_t event)
{
if (BSP_WARM_START_RESET == event)
{
/* C runtime environment has not been setup so you cannot use globals. System clocks are not setup. */
}
if (BSP_WARM_START_POST_CLOCK == event)
{
/* C runtime environment has not been setup so you cannot use globals. Clocks have been initialized. */
}
else if (BSP_WARM_START_POST_C == event)
{
/* C runtime environment, system clocks, and pins are all setup. */
}
else
{
/* Do nothing */
}
}
/*******************************************************************************************************************//**
* Disable TRNG circuit to prevent unnecessary current draw which may otherwise occur when the Crypto module
* is not in use.
**********************************************************************************************************************/
#if BSP_FEATURE_BSP_RESET_TRNG
static void bsp_reset_trng_circuit (void)
{
volatile uint8_t read_port = 0U;
FSP_PARAMETER_NOT_USED(read_port); /// Prevent compiler 'unused' warning
/* Release register protection for low power modes (per RA2A1 User's Manual (R01UH0888EJ0100) Figure 11.13 "Example
* of initial setting flow for an unused circuit") */
R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT);
/* Enable TRNG function (disable stop function) */
#if BSP_FEATURE_BSP_HAS_SCE_ON_RA2
R_BSP_MODULE_START(FSP_IP_TRNG, 0); ///< TRNG Module Stop needs to be started/stopped for RA2 series.
#elif BSP_FEATURE_BSP_HAS_SCE5
R_BSP_MODULE_START(FSP_IP_SCE, 0); ///< TRNG Module Stop needs to be started/stopped for RA4 series.
#else
#error "BSP_FEATURE_BSP_RESET_TRNG is defined but not handled."
#endif
/* Wait for at least 3 PCLKB cycles */
read_port = R_PFS->PORT[0].PIN[0].PmnPFS_b.PODR;
read_port = R_PFS->PORT[0].PIN[0].PmnPFS_b.PODR;
read_port = R_PFS->PORT[0].PIN[0].PmnPFS_b.PODR;
/* Disable TRNG function */
#if BSP_FEATURE_BSP_HAS_SCE_ON_RA2
R_BSP_MODULE_STOP(FSP_IP_TRNG, 0); ///< TRNG Module Stop needs to be started/stopped for RA2 series.
#elif BSP_FEATURE_BSP_HAS_SCE5
R_BSP_MODULE_STOP(FSP_IP_SCE, 0); ///< TRNG Module Stop needs to be started/stopped for RA4 series.
#else
#error "BSP_FEATURE_BSP_RESET_TRNG is defined but not handled."
#endif
/* Reapply register protection for low power modes (per RA2A1 User's Manual (R01UH0888EJ0100) Figure 11.13 "Example
* of initial setting flow for an unused circuit") */
R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT);
}
#endif
#if BSP_CFG_EARLY_INIT
/*******************************************************************************************************************//**
* Initialize BSP variables not handled by C runtime startup.
**********************************************************************************************************************/
static void bsp_init_uninitialized_vars (void)
{
g_protect_pfswe_counter = 0;
extern volatile uint16_t g_protect_counters[];
for (uint32_t i = 0; i < 4; i++)
{
g_protect_counters[i] = 0;
}
extern bsp_grp_irq_cb_t g_bsp_group_irq_sources[];
for (uint32_t i = 0; i < 16; i++)
{
g_bsp_group_irq_sources[i] = 0;
}
#if BSP_CFG_EARLY_INIT
/* Set SystemCoreClock to MOCO */
SystemCoreClock = BSP_MOCO_HZ;
#endif
}
#endif
#if BSP_CFG_C_RUNTIME_INIT
#if (BSP_FEATURE_BSP_HAS_ITCM || BSP_FEATURE_BSP_HAS_DTCM)
/*******************************************************************************************************************//**
* 64-bit memory copy for Armv8.1-M using low overhead loop instructions.
*
* @param[in] destination copy destination start address, word aligned
* @param[in] source copy source start address, word aligned
* @param[in] count number of doublewords to copy
**********************************************************************************************************************/
static void memcpy_64 (uint64_t * destination, const uint64_t * source, size_t count)
{
uint64_t temp;
__asm volatile (
"wls lr, %[count], memcpy_64_loop_end_%=\n"
#if (defined(__ARMCC_VERSION) || defined(__GNUC__))
/* Align the branch target to a 64-bit boundary, a CM85 specific optimization. */
/* IAR does not support alignment control within inline assembly. */
".balign 8\n"
#endif
"memcpy_64_loop_start_%=:\n"
"ldrd %Q[temp], %R[temp], [%[source]], #+8\n"
"strd %Q[temp], %R[temp], [%[destination]], #+8\n"
"le lr, memcpy_64_loop_start_%=\n"
"memcpy_64_loop_end_%=:"
:[destination] "+&r" (destination), [source] "+&r" (source), [temp] "=r" (temp)
:[count] "r" (count)
: "lr", "memory"
);
/* Suppress IAR warning: "Error[Pe550]: variable "temp" was set but never used" */
/* "temp" triggers this warning when it lacks an early-clobber modifier, which was removed to allow register reuse with "count". */
(void) temp;
}
#endif
#if BSP_FEATURE_BSP_HAS_DTCM
/*******************************************************************************************************************//**
* 64-bit memory set for Armv8.1-M using low overhead loop instructions.
*
* @param[in] destination set destination start address, word aligned
* @param[in] value value to set
* @param[in] count number of doublewords to set
**********************************************************************************************************************/
static void memset_64 (uint64_t * destination, const uint64_t value, size_t count)
{
__asm volatile (
"wls lr, %[count], memset_64_loop_end_%=\n"
#if (defined(__ARMCC_VERSION) || defined(__GNUC__))
/* Align the branch target to a 64-bit boundary, a CM85 specific optimization. */
/* IAR does not support alignment control within inline assembly. */
".balign 8\n"
#endif
"memset_64_loop_start_%=:\n"
"strd %Q[value], %R[value], [%[destination]], #+8\n"
"le lr, memset_64_loop_start_%=\n"
"memset_64_loop_end_%=:"
:[destination] "+&r" (destination)
:[count] "r" (count), [value] "r" (value)
: "lr", "memory"
);
}
#endif
#endif
#if BSP_CFG_C_RUNTIME_INIT
#if BSP_FEATURE_BSP_HAS_ITCM
/*******************************************************************************************************************//**
* Initialize ITCM RAM from ROM image.
**********************************************************************************************************************/
static void bsp_init_itcm (void)
{
uint64_t * itcm_destination;
const uint64_t * itcm_source;
size_t count;
#if defined(__ARMCC_VERSION)
itcm_destination = (uint64_t *) &Image$$ITCM_DATA$$Base;
itcm_source = (uint64_t *) &Load$$ITCM_DATA$$Base;
count = ((uint32_t) &Load$$ITCM_PAD$$Limit - (uint32_t) &Load$$ITCM_DATA$$Base) / sizeof(uint64_t);
#elif defined(__GNUC__)
itcm_destination = (uint64_t *) &__itcm_data_start;
itcm_source = (uint64_t *) &__itcm_data_init_start;
count = ((uint32_t) &__itcm_data_init_end - (uint32_t) &__itcm_data_init_start) / sizeof(uint64_t);
#elif defined(__ICCARM__)
itcm_destination = (uint64_t *) &ITCM_DATA$$Base;
itcm_source = (uint64_t *) &ITCM_DATA_INIT$$Base;
count = ((uint32_t) &ITCM_DATA_INIT$$Limit - (uint32_t) &ITCM_DATA_INIT$$Base) / sizeof(uint64_t);
#endif
memcpy_64(itcm_destination, itcm_source, count);
}
#endif
#if BSP_FEATURE_BSP_HAS_DTCM
/*******************************************************************************************************************//**
* Initialize DTCM RAM from ROM image and zero initialize DTCM RAM BSS section.
**********************************************************************************************************************/
static void bsp_init_dtcm (void)
{
uint64_t * dtcm_destination;
const uint64_t * dtcm_source;
size_t count;
uint64_t * dtcm_zero_destination;
size_t count_zero;
#if defined(__ARMCC_VERSION)
dtcm_destination = (uint64_t *) &Image$$DTCM_DATA$$Base;
dtcm_source = (uint64_t *) &Load$$DTCM_DATA$$Base;
count = ((uint32_t) &Load$$DTCM_PAD$$Limit - (uint32_t) &Load$$DTCM_DATA$$Base) / sizeof(uint64_t);
dtcm_zero_destination = (uint64_t *) &Image$$DTCM_BSS$$Base;
count_zero = ((uint32_t) &Image$$DTCM_BSS_PAD$$ZI$$Limit - (uint32_t) &Image$$DTCM_BSS$$Base) /
sizeof(uint64_t);
#elif defined(__GNUC__)
dtcm_destination = (uint64_t *) &__dtcm_data_start;
dtcm_source = (uint64_t *) &__dtcm_data_init_start;
count = ((uint32_t) &__dtcm_data_init_end - (uint32_t) &__dtcm_data_init_start) / sizeof(uint64_t);
dtcm_zero_destination = (uint64_t *) &__dtcm_bss_start;
count_zero = ((uint32_t) &__dtcm_bss_end - (uint32_t) &__dtcm_bss_start) / sizeof(uint64_t);
#elif defined(__ICCARM__)
dtcm_destination = (uint64_t *) &DTCM_DATA$$Base;
dtcm_source = (uint64_t *) &DTCM_DATA_INIT$$Base;
count = ((uint32_t) &DTCM_DATA_INIT$$Limit - (uint32_t) &DTCM_DATA_INIT$$Base) / sizeof(uint64_t);
dtcm_zero_destination = (uint64_t *) &DTCM_BSS$$Base;
count_zero = ((uint32_t) &DTCM_BSS$$Limit - (uint32_t) &DTCM_BSS$$Base) / sizeof(uint64_t);
#endif
memcpy_64(dtcm_destination, dtcm_source, count);
memset_64(dtcm_zero_destination, 0, count_zero);
}
#endif
#endif
#if BSP_CFG_DCACHE_ENABLED
/*******************************************************************************************************************//**
* Initialize MPU for Armv8-M devices.
**********************************************************************************************************************/
static void bsp_init_mpu (void)
{
uint32_t nocache_start;
uint32_t nocache_end;
uint32_t nocache_sdram_start;
uint32_t nocache_sdram_end;
#if defined(__ARMCC_VERSION)
nocache_start = (uint32_t) &Image$$NOCACHE$$ZI$$Base;
nocache_end = (uint32_t) &Image$$NOCACHE_PAD$$ZI$$Limit;
nocache_sdram_start = (uint32_t) &Image$$NOCACHE_SDRAM$$ZI$$Base;
nocache_sdram_end = (uint32_t) &Image$$NOCACHE_SDRAM_PAD$$ZI$$Limit;
#elif defined(__GNUC__)
nocache_start = (uint32_t) &__nocache_start;
nocache_end = (uint32_t) &__nocache_end;
nocache_sdram_start = (uint32_t) &__nocache_sdram_start;
nocache_sdram_end = (uint32_t) &__nocache_sdram_end;
#elif defined(__ICCARM__)
nocache_start = (uint32_t) &NOCACHE$$Base;
nocache_end = (uint32_t) &NOCACHE$$Limit;
nocache_sdram_start = (uint32_t) &NOCACHE_SDRAM$$Base;
nocache_sdram_end = (uint32_t) &NOCACHE_SDRAM$$Limit;
#endif
/* Maximum of eight attributes. */
const uint8_t bsp_mpu_mair_attributes[] =
{
/* Normal, Non-cacheable */
ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE)
};
/* Maximum of eight regions. */
/* A region start address and end address must each be aligned to 32 bytes. A region must be a minimum of 32 bytes to be valid. */
/* A region end address is inclusive. */
const ARM_MPU_Region_t bsp_mpu_regions[] =
{
/* No-Cache Section */
{
.RBAR = ARM_MPU_RBAR(nocache_start, ARM_MPU_SH_NON, 0U, 0U, 1U),
.RLAR = ARM_MPU_RLAR((nocache_end - ARMV8_MPU_REGION_MIN_SIZE), 0U)
},
/* SDRAM No-Cache Section */
{
.RBAR = ARM_MPU_RBAR(nocache_sdram_start, ARM_MPU_SH_NON, 0U, 0U, 1U),
.RLAR = ARM_MPU_RLAR((nocache_sdram_end - ARMV8_MPU_REGION_MIN_SIZE), 0U)
}
};
/* Initialize MPU_MAIR0 and MPU_MAIR1 from attributes table. */
uint8_t num_attr = (sizeof(bsp_mpu_mair_attributes) / sizeof(bsp_mpu_mair_attributes[0]));
for (uint8_t i = 0; i < num_attr; i++)
{
ARM_MPU_SetMemAttr(i, bsp_mpu_mair_attributes[i]);
}
/* Initialize MPU from configuration table. */
uint8_t num_regions = (sizeof(bsp_mpu_regions) / sizeof(bsp_mpu_regions[0]));
for (uint8_t i = 0; i < num_regions; i++)
{
uint32_t rbar = bsp_mpu_regions[i].RBAR;
uint32_t rlar = bsp_mpu_regions[i].RLAR;
/* Only configure regions of non-zero size. */
if ((((rlar & MPU_RLAR_LIMIT_Msk) >> MPU_RLAR_LIMIT_Pos) + ARMV8_MPU_REGION_MIN_SIZE) >
((rbar & MPU_RBAR_BASE_Msk) >> MPU_RBAR_BASE_Pos))
{
ARM_MPU_SetRegion(i, rbar, rlar);
}
}
/*
* SHCSR.MEMFAULTENA is set inside ARM_MPU_Enable().
* Leave SHPR1.PRI_4 at reset value of zero.
* Leave MPU_CTRL.HFNMIENA at reset value of zero.
* Provide MPU_CTRL_PRIVDEFENA_Msk to ARM_MPU_Enable() to set MPU_CTRL.PRIVDEFENA.
*/
ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
}
#endif
/** @} (end addtogroup BSP_MCU) */

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/***********************************************************************************************************************
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/***********************************************************************************************************************
*
* Includes
**********************************************************************************************************************/
#include "bsp_api.h"
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#if defined(__ICCARM__)
#define WEAK_ERROR_ATTRIBUTE
#define WEAK_INIT_ATTRIBUTE
#pragma weak fsp_error_log = fsp_error_log_internal
#pragma weak bsp_init = bsp_init_internal
#elif defined(__GNUC__)
#define WEAK_ERROR_ATTRIBUTE __attribute__((weak, alias("fsp_error_log_internal")))
#define WEAK_INIT_ATTRIBUTE __attribute__((weak, alias("bsp_init_internal")))
#endif
#define FSP_SECTION_VERSION ".version"
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Private function prototypes
**********************************************************************************************************************/
/** Prototype of initialization function called before main. This prototype sets the weak association of this
* function to an internal example implementation. If this function is defined in the application code, the
* application code version is used. */
void bsp_init(void * p_args) WEAK_INIT_ATTRIBUTE;
void bsp_init_internal(void * p_args); /// Default initialization function
#if ((1 == BSP_CFG_ERROR_LOG) || (1 == BSP_CFG_ASSERT))
/** Prototype of function called before errors are returned in FSP code if BSP_CFG_ERROR_LOG is set to 1. This
* prototype sets the weak association of this function to an internal example implementation. */
void fsp_error_log(fsp_err_t err, const char * file, int32_t line) WEAK_ERROR_ATTRIBUTE;
void fsp_error_log_internal(fsp_err_t err, const char * file, int32_t line); /// Default error logger function
#endif
#if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_SECURE_BUILD == 1
static bool bsp_valid_register_check(uint32_t register_address,
uint32_t const * const p_register_table,
uint32_t register_table_length);
#endif
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
/* FSP pack version structure. */
static BSP_DONT_REMOVE const fsp_pack_version_t g_fsp_version BSP_PLACE_IN_SECTION (FSP_SECTION_VERSION) =
{
.version_id_b =
{
.minor = FSP_VERSION_MINOR,
.major = FSP_VERSION_MAJOR,
.build = FSP_VERSION_BUILD,
.patch = FSP_VERSION_PATCH
}
};
/* Public FSP version name. */
static BSP_DONT_REMOVE const uint8_t g_fsp_version_string[] BSP_PLACE_IN_SECTION(FSP_SECTION_VERSION) =
FSP_VERSION_STRING;
/* Unique FSP version ID. */
static BSP_DONT_REMOVE const uint8_t g_fsp_version_build_string[] BSP_PLACE_IN_SECTION(FSP_SECTION_VERSION) =
FSP_VERSION_BUILD_STRING;
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
**********************************************************************************************************************/
/***********************************************************************************************************************
* Private global variables and functions
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* Get the FSP version based on compile time macros.
*
* @param[out] p_version Memory address to return version information to.
*
* @retval FSP_SUCCESS Version information stored.
* @retval FSP_ERR_ASSERTION The parameter p_version is NULL.
**********************************************************************************************************************/
fsp_err_t R_FSP_VersionGet (fsp_pack_version_t * const p_version)
{
#if BSP_CFG_PARAM_CHECKING_ENABLE
/** Verify parameters are valid */
FSP_ASSERT(NULL != p_version);
#endif
*p_version = g_fsp_version;
return FSP_SUCCESS;
}
#if ((1 == BSP_CFG_ERROR_LOG) || (1 == BSP_CFG_ASSERT))
/*******************************************************************************************************************//**
* Default error logger function, used only if fsp_error_log is not defined in the user application.
*
* @param[in] err The error code encountered.
* @param[in] file The file name in which the error code was encountered.
* @param[in] line The line number at which the error code was encountered.
**********************************************************************************************************************/
void fsp_error_log_internal (fsp_err_t err, const char * file, int32_t line)
{
/** Do nothing. Do not generate any 'unused' warnings. */
FSP_PARAMETER_NOT_USED(err);
FSP_PARAMETER_NOT_USED(file);
FSP_PARAMETER_NOT_USED(line);
}
#endif
#if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_SECURE_BUILD == 1
/*******************************************************************************************************************//**
* Read a secure 8-bit STYPE3 register in the non-secure state.
*
* @param[in] p_reg The address of the secure register.
*
* @return Value read from the register.
**********************************************************************************************************************/
BSP_CMSE_NONSECURE_ENTRY uint8_t R_BSP_NSC_STYPE3_RegU8Read (uint8_t volatile const * p_reg)
{
uint8_t volatile * p_reg_s = (uint8_t volatile *) ((uint32_t) p_reg & ~BSP_FEATURE_TZ_NS_OFFSET);
/* Table of secure registers that may be read from the non-secure application. */
static const uint32_t valid_addresses[] =
{
(uint32_t) &R_SYSTEM->SCKDIVCR2,
(uint32_t) &R_SYSTEM->SCKSCR,
(uint32_t) &R_SYSTEM->SPICKDIVCR,
(uint32_t) &R_SYSTEM->SPICKCR,
(uint32_t) &R_SYSTEM->SCICKDIVCR,
(uint32_t) &R_SYSTEM->SCICKCR,
(uint32_t) &R_SYSTEM->CANFDCKCR,
(uint32_t) &R_SYSTEM->PLLCR,
(uint32_t) &R_SYSTEM->PLL2CR,
(uint32_t) &R_SYSTEM->MOCOCR,
(uint32_t) &R_SYSTEM->OPCCR,
};
if (bsp_valid_register_check((uint32_t) p_reg_s, valid_addresses,
sizeof(valid_addresses) / sizeof(valid_addresses[0])))
{
return *p_reg_s;
}
/* Generate a trustzone access violation by accessing the non-secure aliased address. */
return *((uint8_t volatile *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET));
}
/*******************************************************************************************************************//**
* Read a secure 16-bit STYPE3 register in the non-secure state.
*
* @param[in] p_reg The address of the secure register.
*
* @return Value read from the register.
**********************************************************************************************************************/
BSP_CMSE_NONSECURE_ENTRY uint16_t R_BSP_NSC_STYPE3_RegU16Read (uint16_t volatile const * p_reg)
{
uint16_t volatile * p_reg_s = (uint16_t volatile *) ((uint32_t) p_reg & ~BSP_FEATURE_TZ_NS_OFFSET);
/* Table of secure registers that may be read from the non-secure application. */
static const uint32_t valid_addresses[] =
{
(uint32_t) &R_DTC->DTCSTS,
};
if (bsp_valid_register_check((uint32_t) p_reg_s, valid_addresses,
sizeof(valid_addresses) / sizeof(valid_addresses[0])))
{
return *p_reg_s;
}
/* Generate a trustzone access violation by accessing the non-secure aliased address. */
return *((uint16_t volatile *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET));
}
/*******************************************************************************************************************//**
* Read a secure 32-bit STYPE3 register in the non-secure state.
*
* @param[in] p_reg The address of the secure register.
*
* @return Value read from the register.
**********************************************************************************************************************/
BSP_CMSE_NONSECURE_ENTRY uint32_t R_BSP_NSC_STYPE3_RegU32Read (uint32_t volatile const * p_reg)
{
uint32_t volatile * p_reg_s = (uint32_t volatile *) ((uint32_t) p_reg & ~BSP_FEATURE_TZ_NS_OFFSET);
/* Table of secure registers that may be read from the non-secure application. */
static const uint32_t valid_addresses[] =
{
(uint32_t) &R_SYSTEM->SCKDIVCR,
};
if (bsp_valid_register_check((uint32_t) p_reg_s, valid_addresses,
sizeof(valid_addresses) / sizeof(valid_addresses[0])))
{
return *p_reg_s;
}
/* Generate a trustzone access violation by accessing the non-secure aliased address. */
return *((uint32_t volatile *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET));
}
#endif
/** @} (end addtogroup BSP_MCU) */
/*******************************************************************************************************************//**
* Default initialization function, used only if bsp_init is not defined in the user application.
**********************************************************************************************************************/
void bsp_init_internal (void * p_args)
{
/* Do nothing. */
FSP_PARAMETER_NOT_USED(p_args);
}
#if defined(__ARMCC_VERSION)
/*******************************************************************************************************************//**
* Default implementation of assert for AC6.
**********************************************************************************************************************/
__attribute__((weak, noreturn))
void __aeabi_assert (const char * expr, const char * file, int line)
{
FSP_PARAMETER_NOT_USED(expr);
FSP_PARAMETER_NOT_USED(file);
FSP_PARAMETER_NOT_USED(line);
__BKPT(0);
while (1)
{
/* Do nothing. */
}
}
#elif defined(__GNUC__)
/* The default assert implementation for GCC brings in printing/formatting code. FSP overrides the default assert
* behavior to reduce code size. */
#if !BSP_CFG_USE_STANDARD_ASSERT
/*******************************************************************************************************************//**
* Default implementation of assert for GCC.
**********************************************************************************************************************/
BSP_WEAK_REFERENCE void __assert_func (const char * file, int line, const char * func, const char * expr)
{
FSP_PARAMETER_NOT_USED(file);
FSP_PARAMETER_NOT_USED(line);
FSP_PARAMETER_NOT_USED(func);
FSP_PARAMETER_NOT_USED(expr);
__BKPT(0);
while (1)
{
/* Do nothing. */
}
}
#endif
#endif
#if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_SECURE_BUILD == 1
/*******************************************************************************************************************//**
* Check if a register address should be accessible by the non-secure application.
**********************************************************************************************************************/
static bool bsp_valid_register_check (uint32_t register_address,
uint32_t const * const p_register_table,
uint32_t register_table_length)
{
bool valid = false;
/* Check if the given address is valid. */
for (uint32_t i = 0; i < register_table_length; i++)
{
if (p_register_table[i] == register_address)
{
valid = true;
break;
}
}
return valid;
}
#endif

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/***********************************************************************************************************************
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef BSP_COMMON_H
#define BSP_COMMON_H
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
/* C99 includes. */
#include <stdint.h>
#include <stddef.h>
#include <stdbool.h>
#include <assert.h>
#include <string.h>
/* Different compiler support. */
#include "../../inc/api/fsp_common_api.h"
#include "bsp_compiler_support.h"
/* BSP TFU Includes. */
#include "../../src/bsp/mcu/all/bsp_tfu.h"
#include "bsp_cfg.h"
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
**********************************************************************************************************************/
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/** Used to signify that an ELC event is not able to be used as an interrupt. */
#define BSP_IRQ_DISABLED (0xFFU)
/* Version of this module's code and API. */
#if 1 == BSP_CFG_RTOS /* ThreadX */
#include "tx_user.h"
#if defined(TX_ENABLE_EVENT_TRACE) || defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY)
#include "tx_api.h"
#define FSP_CONTEXT_SAVE tx_isr_start((uint32_t) R_FSP_CurrentIrqGet());
#define FSP_CONTEXT_RESTORE tx_isr_end((uint32_t) R_FSP_CurrentIrqGet());
#else
#define FSP_CONTEXT_SAVE
#define FSP_CONTEXT_RESTORE
#endif
#else
#define FSP_CONTEXT_SAVE
#define FSP_CONTEXT_RESTORE
#endif
/** Macro that can be defined in order to enable logging in FSP modules. */
#ifndef FSP_LOG_PRINT
#define FSP_LOG_PRINT(X)
#endif
/** Macro to log and return error without an assertion. */
#ifndef FSP_RETURN
#define FSP_RETURN(err) FSP_ERROR_LOG((err)); \
return err;
#endif
/** This function is called before returning an error code. To stop on a runtime error, define fsp_error_log in
* user code and do required debugging (breakpoints, stack dump, etc) in this function.*/
#if (1 == BSP_CFG_ERROR_LOG)
#ifndef FSP_ERROR_LOG
#define FSP_ERROR_LOG(err) \
fsp_error_log((err), __FILE__, __LINE__);
#endif
#else
#define FSP_ERROR_LOG(err)
#endif
/** Default assertion calls ::FSP_ERROR_RETURN if condition "a" is false. Used to identify incorrect use of API's in FSP
* functions. */
#if (3 == BSP_CFG_ASSERT)
#define FSP_ASSERT(a)
#elif (2 == BSP_CFG_ASSERT)
#define FSP_ASSERT(a) {assert(a);}
#else
#define FSP_ASSERT(a) FSP_ERROR_RETURN((a), FSP_ERR_ASSERTION)
#endif // ifndef FSP_ASSERT
/** All FSP error codes are returned using this macro. Calls ::FSP_ERROR_LOG function if condition "a" is false. Used
* to identify runtime errors in FSP functions. */
#define FSP_ERROR_RETURN(a, err) \
{ \
if ((a)) \
{ \
(void) 0; /* Do nothing */ \
} \
else \
{ \
FSP_ERROR_LOG(err); \
return err; \
} \
}
/* Function-like macro used to wait for a condition to be met, most often used to wait for hardware register updates.
* This macro can be redefined to add a timeout if necessary. */
#ifndef FSP_HARDWARE_REGISTER_WAIT
#define FSP_HARDWARE_REGISTER_WAIT(reg, required_value) while (reg != required_value) { /* Wait. */}
#endif
#ifndef FSP_REGISTER_READ
/* Read a register and discard the result. */
#define FSP_REGISTER_READ(A) __ASM volatile ("" : : "r" (A));
#endif
/****************************************************************
*
* This check is performed to select suitable ASM API with respect to core
*
* The macros __CORE__ , __ARM7EM__ and __ARM_ARCH_8M_BASE__ are undefined for GCC, but defined(__IAR_SYSTEMS_ICC__) is false for GCC, so
* the left half of the || expression evaluates to false for GCC regardless of the values of these macros. */
#if (defined(__IAR_SYSTEMS_ICC__) && ((__CORE__ == __ARM7EM__) || (__CORE__ == __ARM_ARCH_8M_BASE__))) || \
defined(__ARM_ARCH_7EM__) // CM4
#ifndef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION
#define BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION (0U)
#endif
#else // CM23
#ifdef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION
#undef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION
#endif
#define BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION (0U)
#endif
/* This macro defines a variable for saving previous mask value */
#ifndef FSP_CRITICAL_SECTION_DEFINE
#define FSP_CRITICAL_SECTION_DEFINE uint32_t old_mask_level = 0U
#endif
/* These macros abstract methods to save and restore the interrupt state for different architectures. */
#if (0 == BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION)
#define FSP_CRITICAL_SECTION_GET_CURRENT_STATE __get_PRIMASK
#define FSP_CRITICAL_SECTION_SET_STATE __set_PRIMASK
#define FSP_CRITICAL_SECTION_IRQ_MASK_SET (1U)
#else
#define FSP_CRITICAL_SECTION_GET_CURRENT_STATE __get_BASEPRI
#define FSP_CRITICAL_SECTION_SET_STATE __set_BASEPRI
#define FSP_CRITICAL_SECTION_IRQ_MASK_SET ((uint8_t) (BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION << \
(8U - __NVIC_PRIO_BITS)))
#endif
/** This macro temporarily saves the current interrupt state and disables interrupts. */
#ifndef FSP_CRITICAL_SECTION_ENTER
#define FSP_CRITICAL_SECTION_ENTER \
old_mask_level = FSP_CRITICAL_SECTION_GET_CURRENT_STATE(); \
FSP_CRITICAL_SECTION_SET_STATE(FSP_CRITICAL_SECTION_IRQ_MASK_SET)
#endif
/** This macro restores the previously saved interrupt state, reenabling interrupts. */
#ifndef FSP_CRITICAL_SECTION_EXIT
#define FSP_CRITICAL_SECTION_EXIT FSP_CRITICAL_SECTION_SET_STATE(old_mask_level)
#endif
/* Number of Cortex processor exceptions, used as an offset from XPSR value for the IRQn_Type macro. */
#define FSP_PRIV_CORTEX_PROCESSOR_EXCEPTIONS (16U)
/** Used to signify that the requested IRQ vector is not defined in this system. */
#define FSP_INVALID_VECTOR ((IRQn_Type) - 33)
/* Private definition used in bsp_clocks and R_FSP_SystemClockHzGet. Each bitfield in SCKDIVCR is up to 4 bits wide. */
#if (BSP_CFG_MCU_PART_SERIES == 8)
#define FSP_PRV_SCKDIVCR_DIV_MASK (0xFU)
#else
#define FSP_PRV_SCKDIVCR_DIV_MASK (0x7U)
#endif
/* Use the secure registers for secure projects and flat projects. */
#if !BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_HAS_TRUSTZONE
#define FSP_PRIV_TZ_USE_SECURE_REGS (1)
#else
#define FSP_PRIV_TZ_USE_SECURE_REGS (0)
#endif
/* Put certain BSP variables in uninitialized RAM when initializing BSP early. */
#if BSP_CFG_EARLY_INIT
#define BSP_SECTION_EARLY_INIT BSP_PLACE_IN_SECTION(BSP_SECTION_NOINIT)
#else
#define BSP_SECTION_EARLY_INIT
#endif
#if (BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD) && BSP_FEATURE_TZ_VERSION == 2
BSP_CMSE_NONSECURE_ENTRY uint8_t R_BSP_NSC_STYPE3_RegU8Read(uint8_t volatile const * p_reg);
BSP_CMSE_NONSECURE_ENTRY uint16_t R_BSP_NSC_STYPE3_RegU16Read(uint16_t volatile const * p_reg);
BSP_CMSE_NONSECURE_ENTRY uint32_t R_BSP_NSC_STYPE3_RegU32Read(uint32_t volatile const * p_reg);
#endif
#if BSP_FEATURE_TZ_HAS_TRUSTZONE && BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_VERSION == 2
/*
* If the STYPE3 register's security attribution is set to secure, the non-secure application must read the register
* from the secure application using the provided non-secure callable functions.
*/
#define FSP_STYPE3_REG8_READ(X, S) (!(S) ? X : (R_BSP_NSC_STYPE3_RegU8Read((uint8_t const volatile *) &X)))
#define FSP_STYPE3_REG16_READ(X, S) (!(S) ? X : (R_BSP_NSC_STYPE3_RegU16Read((uint16_t const volatile *) &X)))
#define FSP_STYPE3_REG32_READ(X, S) (!(S) ? X : (R_BSP_NSC_STYPE3_RegU32Read((uint32_t const volatile *) &X)))
#elif BSP_FEATURE_TZ_HAS_TRUSTZONE && BSP_TZ_SECURE_BUILD && BSP_FEATURE_TZ_VERSION == 2
/*******************************************************************************************************************//**
* Read a non-secure 8-bit STYPE3 register in the secure state.
*
* @param[in] p_reg The address of the non-secure register.
*
* @return Value read from the register.
**********************************************************************************************************************/
__STATIC_INLINE uint8_t R_BSP_S_STYPE3_RegU8Read (uint8_t volatile const * p_reg)
{
p_reg = (uint8_t volatile const *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET);
return *p_reg;
}
/*******************************************************************************************************************//**
* Read a non-secure 16-bit STYPE3 register in the secure state.
*
* @param[in] p_reg The address of the non-secure register.
*
* @return Value read from the register.
**********************************************************************************************************************/
__STATIC_INLINE uint16_t R_BSP_S_STYPE3_RegU16Read (uint16_t volatile const * p_reg)
{
p_reg = (uint16_t volatile const *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET);
return *p_reg;
}
/*******************************************************************************************************************//**
* Read a non-secure 32-bit STYPE3 register in the secure state.
*
* @param[in] p_reg The address of the non-secure register.
*
* @return Value read from the register.
**********************************************************************************************************************/
__STATIC_INLINE uint32_t R_BSP_S_STYPE3_RegU32Read (uint32_t volatile const * p_reg)
{
p_reg = (uint32_t volatile const *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET);
return *p_reg;
}
/*
* If the STYPE3 register's security attribution is set to non-secure, the secure application must read the register
* using the non-secure aliased address.
*/
#define FSP_STYPE3_REG8_READ(X, S) ((S) ? (X) : R_BSP_S_STYPE3_RegU8Read((uint8_t const volatile *) &X))
#define FSP_STYPE3_REG16_READ(X, S) ((S) ? (X) : R_BSP_S_STYPE3_RegU16Read((uint16_t const volatile *) &X))
#define FSP_STYPE3_REG32_READ(X, S) ((S) ? (X) : R_BSP_S_STYPE3_RegU32Read((uint32_t const volatile *) &X))
#else
#define FSP_STYPE3_REG8_READ(X, S) (X)
#define FSP_STYPE3_REG16_READ(X, S) (X)
#define FSP_STYPE3_REG32_READ(X, S) (X)
#endif
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** Different warm start entry locations in the BSP. */
typedef enum e_bsp_warm_start_event
{
BSP_WARM_START_RESET = 0, ///< Called almost immediately after reset. No C runtime environment, clocks, or IRQs.
BSP_WARM_START_POST_CLOCK, ///< Called after clock initialization. No C runtime environment or IRQs.
BSP_WARM_START_POST_C ///< Called after clocks and C runtime environment have been set up
} bsp_warm_start_event_t;
/* Private enum used in R_FSP_SystemClockHzGet. Maps clock name to base bit in SCKDIVCR. */
typedef enum e_fsp_priv_clock
{
FSP_PRIV_CLOCK_PCLKD = 0,
FSP_PRIV_CLOCK_PCLKC = 4,
FSP_PRIV_CLOCK_PCLKB = 8,
FSP_PRIV_CLOCK_PCLKA = 12,
FSP_PRIV_CLOCK_BCLK = 16,
FSP_PRIV_CLOCK_PCLKE = 20,
FSP_PRIV_CLOCK_ICLK = 24,
FSP_PRIV_CLOCK_FCLK = 28,
FSP_PRIV_CLOCK_CPUCLK = 32,
} fsp_priv_clock_t;
/* Private enum used in R_FSP_SciSpiClockHzGe. Maps clock name to base bit in SCISPICKCR. */
typedef enum e_fsp_priv_source_clock
{
FSP_PRIV_CLOCK_HOCO = 0, ///< The high speed on chip oscillator
FSP_PRIV_CLOCK_MOCO = 1, ///< The middle speed on chip oscillator
FSP_PRIV_CLOCK_LOCO = 2, ///< The low speed on chip oscillator
FSP_PRIV_CLOCK_MAIN_OSC = 3, ///< The main oscillator
FSP_PRIV_CLOCK_SUBCLOCK = 4, ///< The subclock oscillator
FSP_PRIV_CLOCK_PLL = 5, ///< The PLL oscillator
FSP_PRIV_CLOCK_PLL2 = 6, ///< The PLL2 oscillator
} fsp_priv_source_clock_t;
typedef struct st_bsp_unique_id
{
union
{
uint32_t unique_id_words[4];
uint8_t unique_id_bytes[16];
};
} bsp_unique_id_t;
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
uint32_t R_BSP_SourceClockHzGet(fsp_priv_source_clock_t clock);
/***********************************************************************************************************************
* Global variables (defined in other files)
**********************************************************************************************************************/
/***********************************************************************************************************************
* Inline Functions
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* Return active interrupt vector number value
*
* @return Active interrupt vector number value
**********************************************************************************************************************/
__STATIC_INLINE IRQn_Type R_FSP_CurrentIrqGet (void)
{
xPSR_Type xpsr_value;
xpsr_value.w = __get_xPSR();
return (IRQn_Type) (xpsr_value.b.ISR - FSP_PRIV_CORTEX_PROCESSOR_EXCEPTIONS);
}
/*******************************************************************************************************************//**
* Gets the frequency of a system clock.
*
* @return Frequency of requested clock in Hertz.
**********************************************************************************************************************/
__STATIC_INLINE uint32_t R_FSP_SystemClockHzGet (fsp_priv_clock_t clock)
{
uint32_t sckdivcr = FSP_STYPE3_REG32_READ(R_SYSTEM->SCKDIVCR, BSP_CFG_CLOCKS_SECURE);
uint32_t clock_div = (sckdivcr >> clock) & FSP_PRV_SCKDIVCR_DIV_MASK;
#if BSP_FEATURE_CGC_HAS_CPUCLK
if (FSP_PRIV_CLOCK_CPUCLK == clock)
{
return SystemCoreClock;
}
/* Get CPUCLK divisor */
uint32_t cpuclk_div = FSP_STYPE3_REG8_READ(R_SYSTEM->SCKDIVCR2, BSP_CFG_CLOCKS_SECURE) & FSP_PRV_SCKDIVCR_DIV_MASK;
/* Determine if either divisor is a multiple of 3 */
if ((cpuclk_div | clock_div) & 8U)
{
/* Convert divisor settings to their actual values */
cpuclk_div = (cpuclk_div & 8U) ? (3U << (cpuclk_div & 7U)) : (1U << cpuclk_div);
clock_div = (clock_div & 8U) ? (3U << (clock_div & 7U)) : (1U << clock_div);
/* Calculate clock with multiplication and division instead of shifting */
return (SystemCoreClock * cpuclk_div) / clock_div;
}
else
{
return (SystemCoreClock << cpuclk_div) >> clock_div;
}
#else
uint32_t iclk_div = (sckdivcr >> FSP_PRIV_CLOCK_ICLK) & FSP_PRV_SCKDIVCR_DIV_MASK;
return (SystemCoreClock << iclk_div) >> clock_div;
#endif
}
/*******************************************************************************************************************//**
* Converts a clock's CKDIVCR register value to a clock divider (Eg: SPICKDIVCR).
*
* @return Clock Divider
**********************************************************************************************************************/
__STATIC_INLINE uint32_t R_FSP_ClockDividerGet (uint32_t ckdivcr)
{
if (2U >= ckdivcr)
{
/* clock_div:
* - Clock Divided by 1: 0
* - Clock Divided by 2: 1
* - Clock Divided by 4: 2
*/
return 1U << ckdivcr;
}
else if (3U == ckdivcr)
{
/* Clock Divided by 6 */
return 6U;
}
else if (4U == ckdivcr)
{
/* Clock Divided by 8 */
return 8U;
}
else if (5U == ckdivcr)
{
/* Clock Divided by 3 */
return 3U;
}
/* Clock Divided by 5 */
return 5U;
}
#if BSP_FEATURE_BSP_HAS_SCISPI_CLOCK
/*******************************************************************************************************************//**
* Gets the frequency of a SCI/SPI clock.
*
* @return Frequency of requested clock in Hertz.
**********************************************************************************************************************/
__STATIC_INLINE uint32_t R_FSP_SciSpiClockHzGet (void)
{
uint32_t scispidivcr = R_SYSTEM->SCISPICKDIVCR;
uint32_t clock_div = R_FSP_ClockDividerGet(scispidivcr & FSP_PRV_SCKDIVCR_DIV_MASK);
fsp_priv_source_clock_t scispicksel = (fsp_priv_source_clock_t) R_SYSTEM->SCISPICKCR_b.SCISPICKSEL;
return R_BSP_SourceClockHzGet(scispicksel) / clock_div;
}
#endif
#if BSP_FEATURE_BSP_HAS_SPI_CLOCK
/*******************************************************************************************************************//**
* Gets the frequency of a SPI clock.
*
* @return Frequency of requested clock in Hertz.
**********************************************************************************************************************/
__STATIC_INLINE uint32_t R_FSP_SpiClockHzGet (void)
{
uint32_t spidivcr = FSP_STYPE3_REG8_READ(R_SYSTEM->SPICKDIVCR, BSP_CFG_CLOCKS_SECURE);
uint32_t clock_div = R_FSP_ClockDividerGet(spidivcr & FSP_PRV_SCKDIVCR_DIV_MASK);
fsp_priv_source_clock_t spicksel =
(fsp_priv_source_clock_t) ((FSP_STYPE3_REG8_READ(R_SYSTEM->SPICKCR,
BSP_CFG_CLOCKS_SECURE) & R_SYSTEM_SPICKCR_CKSEL_Msk) >>
R_SYSTEM_SPICKCR_CKSEL_Pos);
return R_BSP_SourceClockHzGet(spicksel) / clock_div;
}
#endif
#if BSP_FEATURE_BSP_HAS_SCI_CLOCK
/*******************************************************************************************************************//**
* Gets the frequency of a SCI clock.
*
* @return Frequency of requested clock in Hertz.
**********************************************************************************************************************/
__STATIC_INLINE uint32_t R_FSP_SciClockHzGet (void)
{
uint32_t scidivcr = FSP_STYPE3_REG8_READ(R_SYSTEM->SCICKDIVCR, BSP_CFG_CLOCKS_SECURE);
uint32_t clock_div = R_FSP_ClockDividerGet(scidivcr & FSP_PRV_SCKDIVCR_DIV_MASK);
fsp_priv_source_clock_t scicksel =
(fsp_priv_source_clock_t) (FSP_STYPE3_REG8_READ(R_SYSTEM->SCICKCR,
BSP_CFG_CLOCKS_SECURE) & R_SYSTEM_SCICKCR_SCICKSEL_Msk >>
R_SYSTEM_SCICKCR_SCICKSEL_Pos);
return R_BSP_SourceClockHzGet(scicksel) / clock_div;
}
#endif
/*******************************************************************************************************************//**
* Get unique ID for this device.
*
* @return A pointer to the unique identifier structure
**********************************************************************************************************************/
__STATIC_INLINE bsp_unique_id_t const * R_BSP_UniqueIdGet (void)
{
return (bsp_unique_id_t *) BSP_FEATURE_BSP_UNIQUE_ID_POINTER;
}
/*******************************************************************************************************************//**
* Disables the flash cache.
**********************************************************************************************************************/
__STATIC_INLINE void R_BSP_FlashCacheDisable (void)
{
#if BSP_FEATURE_BSP_FLASH_CACHE
R_FCACHE->FCACHEE = 0U;
#endif
#if BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE
/* Disable the C-Cache. */
R_CACHE->CCACTL = 0U;
#endif
}
/*******************************************************************************************************************//**
* Enables the flash cache.
**********************************************************************************************************************/
__STATIC_INLINE void R_BSP_FlashCacheEnable (void)
{
#if BSP_FEATURE_BSP_FLASH_CACHE
/* Invalidate the flash cache and wait until it is invalidated. (See section 55.3.2.2 "Operation" of the Flash Cache
* in the RA6M3 manual R01UH0878EJ0100). */
R_FCACHE->FCACHEIV = 1U;
FSP_HARDWARE_REGISTER_WAIT(R_FCACHE->FCACHEIV, 0U);
/* Enable flash cache. */
R_FCACHE->FCACHEE = 1U;
#endif
#if BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE
/* Configure the C-Cache line size. */
R_CACHE->CCALCF = BSP_CFG_C_CACHE_LINE_SIZE;
/* Enable the C-Cache. */
R_CACHE->CCACTL = 1U;
#endif
}
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
#if ((1 == BSP_CFG_ERROR_LOG) || (1 == BSP_CFG_ASSERT))
/** Prototype of default function called before errors are returned in FSP code if BSP_CFG_LOG_ERRORS is set to 1. */
void fsp_error_log(fsp_err_t err, const char * file, int32_t line);
#endif
/** In the event of an unrecoverable error the BSP will by default call the __BKPT() intrinsic function which will
* alert the user of the error. The user can override this default behavior by defining their own
* BSP_CFG_HANDLE_UNRECOVERABLE_ERROR macro.
*/
#if !defined(BSP_CFG_HANDLE_UNRECOVERABLE_ERROR)
#define BSP_CFG_HANDLE_UNRECOVERABLE_ERROR(x) __BKPT((x))
#endif
/** @} (end addtogroup BSP_MCU) */
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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