mirror of https://github.com/RT-Thread/rt-thread
[hc32] Add the ev_hc32f4a8_lqfp176 board and modify some bsp drivers. (#10233)
* [hc32] Add the ev_hc32f4a8_lqfp176 board and modify some bsp drivers.
This commit is contained in:
Jamie
GitHub
parent
396eaa32f6
commit
928e47395d
|
|
@ -53,6 +53,7 @@
|
|||
"at32/at32m412-start",
|
||||
"at32/at32m416-start",
|
||||
"hc32/ev_hc32f4a0_lqfp176",
|
||||
"hc32/ev_hc32f4a8_lqfp176",
|
||||
"hc32/ev_hc32f448_lqfp80",
|
||||
"hc32/ev_hc32f460_lqfp100_v2",
|
||||
"hc32/ev_hc32f472_lqfp100",
|
||||
|
|
|
|||
|
|
@ -20,8 +20,8 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#define HC32_FLASH_SIZE_GRANULARITY (8 * 1024)
|
||||
#define HC32_FLASH_ERASE_GRANULARITY (8 * 1024)
|
||||
#define HC32_FLASH_WRITE_GRANULARITY (4)
|
||||
#define HC32_FLASH_SIZE (256 * 1024)
|
||||
#define HC32_FLASH_START_ADDRESS (0)
|
||||
#define HC32_FLASH_END_ADDRESS (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE)
|
||||
|
|
|
|||
|
|
@ -157,7 +157,7 @@ void CanPhyEnable(void)
|
|||
TCA9539_ConfigPin(CAN2_STB_PORT, CAN2_STB_PIN, TCA9539_DIR_OUT);
|
||||
#endif
|
||||
}
|
||||
rt_err_t rt_hw_board_can_init(CM_MCAN_TypeDef *MCANx)
|
||||
rt_err_t rt_hw_board_mcan_init(CM_MCAN_TypeDef *MCANx)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
|
||||
|
|
|
|||
|
|
@ -9,8 +9,8 @@
|
|||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __CAN_CONFIG_H__
|
||||
#define __CAN_CONFIG_H__
|
||||
#ifndef __MCAN_CONFIG_H__
|
||||
#define __MCAN_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "irq_config.h"
|
||||
|
|
@ -21,16 +21,6 @@ extern "C" {
|
|||
|
||||
/***********************************************************************************************/
|
||||
/***********************************************************************************************/
|
||||
// The arguments of RT command RT_CAN_CMD_SET_CANFD
|
||||
#define MCAN_FD_CLASSICAL 0 /* CAN classical */
|
||||
#define MCAN_FD_ISO_FD_NO_BRS 1 /* ISO CAN FD without BRS */
|
||||
#define MCAN_FD_ISO_FD_BRS 2 /* ISO CAN FD with BRS */
|
||||
#define MCAN_FD_NON_ISO_FD_NO_BRS 3 /* non-ISO CAN FD without BRS */
|
||||
#define MCAN_FD_NON_ISO_FD_BRS 4 /* non-ISO CAN FD with BRS */
|
||||
|
||||
#define MCAN_FD_ARG_MIN MCAN_FD_ISO_FD_NO_BRS
|
||||
#define MCAN_FD_ARG_MAX MCAN_FD_NON_ISO_FD_BRS
|
||||
|
||||
/* The default configuration for MCANs. Users can modify the configurations based on the application.
|
||||
For the message RAM:
|
||||
1. MCAN1 and MCAN2 share 2048 bytes message RAM
|
||||
|
|
@ -59,7 +49,7 @@ extern "C" {
|
|||
#endif
|
||||
|
||||
#ifdef BSP_USING_MCAN1
|
||||
#define MCAN1_NAME ("can1")
|
||||
#define MCAN1_NAME ("mcan1")
|
||||
#define MCAN1_WORK_MODE (RT_CAN_MODE_NORMAL)
|
||||
#define MCAN1_TX_PRIV_MODE RT_CAN_MODE_NOPRIV /* RT_CAN_MODE_NOPRIV: Tx FIFO mode; RT_CAN_MODE_PRIV: Tx priority mode */
|
||||
|
||||
|
|
@ -77,7 +67,7 @@ extern "C" {
|
|||
#endif /* BSP_USING_MCAN1 */
|
||||
|
||||
#ifdef BSP_USING_MCAN2
|
||||
#define MCAN2_NAME ("can2")
|
||||
#define MCAN2_NAME ("mcan2")
|
||||
#define MCAN2_WORK_MODE (RT_CAN_MODE_NORMAL)
|
||||
#define MCAN2_TX_PRIV_MODE RT_CAN_MODE_NOPRIV /* RT_CAN_MODE_NOPRIV: Tx FIFO mode; RT_CAN_MODE_PRIV: Tx priority mode */
|
||||
|
||||
|
|
@ -234,9 +224,9 @@ extern "C" {
|
|||
#define MCAN_FD_CFG_1M_5M \
|
||||
{ \
|
||||
.u32NominalPrescaler = 1, \
|
||||
.u32NominalTimeSeg1 = 64, \
|
||||
.u32NominalTimeSeg2 = 16, \
|
||||
.u32NominalSyncJumpWidth = 16, \
|
||||
.u32NominalTimeSeg1 = 32, \
|
||||
.u32NominalTimeSeg2 = 8, \
|
||||
.u32NominalSyncJumpWidth = 8, \
|
||||
.u32DataPrescaler = 1, \
|
||||
.u32DataTimeSeg1 = 6, \
|
||||
.u32DataTimeSeg2 = 2, \
|
||||
|
|
@ -249,9 +239,9 @@ extern "C" {
|
|||
#define MCAN_FD_CFG_1M_8M \
|
||||
{ \
|
||||
.u32NominalPrescaler = 1, \
|
||||
.u32NominalTimeSeg1 = 64, \
|
||||
.u32NominalTimeSeg2 = 16, \
|
||||
.u32NominalSyncJumpWidth = 16, \
|
||||
.u32NominalTimeSeg1 = 32, \
|
||||
.u32NominalTimeSeg2 = 8, \
|
||||
.u32NominalSyncJumpWidth = 8, \
|
||||
.u32DataPrescaler = 1, \
|
||||
.u32DataTimeSeg1 = 4, \
|
||||
.u32DataTimeSeg2 = 1, \
|
||||
|
|
@ -344,12 +334,12 @@ extern "C" {
|
|||
|
||||
#ifdef RT_CAN_USING_CANFD
|
||||
#define MCAN1_BAUD_RATE_CFG MCAN_FD_CFG_1M_4M
|
||||
#define MCAN1_NOMINAL_BAUD_RATE MCANFD_NOMINAL_BAUD_1M
|
||||
#define MCAN1_DATA_BAUD_RATE MCANFD_DATA_BAUD_4M
|
||||
#define MCAN1_NOMINAL_BAUD_RATE CANFD_DATA_BAUD_1M
|
||||
#define MCAN1_DATA_BAUD_RATE CANFD_DATA_BAUD_4M
|
||||
|
||||
#define MCAN2_BAUD_RATE_CFG MCAN_FD_CFG_1M_4M
|
||||
#define MCAN2_NOMINAL_BAUD_RATE MCANFD_NOMINAL_BAUD_1M
|
||||
#define MCAN2_DATA_BAUD_RATE MCANFD_DATA_BAUD_4M
|
||||
#define MCAN2_NOMINAL_BAUD_RATE CANFD_DATA_BAUD_1M
|
||||
#define MCAN2_DATA_BAUD_RATE CANFD_DATA_BAUD_4M
|
||||
|
||||
#else
|
||||
#define MCAN1_BAUD_RATE_CFG MCAN_CC_CFG_1M
|
||||
|
|
@ -369,6 +359,6 @@ extern "C" {
|
|||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CAN_CONFIG_H__ */
|
||||
#endif /* __MCAN_CONFIG_H__ */
|
||||
|
||||
|
||||
|
|
@ -195,181 +195,6 @@ extern "C" {
|
|||
#endif /* SPI3_RX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI3_RX_USING_DMA */
|
||||
|
||||
#ifdef BSP_USING_SPI4
|
||||
#ifndef SPI4_BUS_CONFIG
|
||||
#define SPI4_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = CM_SPI4, \
|
||||
.bus_name = "spi4", \
|
||||
.clock = FCG1_PERIPH_SPI4, \
|
||||
.timeout = 5000UL, \
|
||||
.err_irq.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_SPI4_ERR_IRQ_NUM, \
|
||||
.irq_prio = BSP_SPI4_ERR_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_SPI4_SPEI, \
|
||||
}, \
|
||||
}
|
||||
#endif /* SPI4_BUS_CONFIG */
|
||||
#endif /* BSP_USING_SPI4 */
|
||||
|
||||
#ifdef BSP_SPI4_TX_USING_DMA
|
||||
#ifndef SPI4_TX_DMA_CONFIG
|
||||
#define SPI4_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI4_TX_DMA_INSTANCE, \
|
||||
.channel = SPI4_TX_DMA_CHANNEL, \
|
||||
.clock = SPI4_TX_DMA_CLOCK, \
|
||||
.trigger_select = SPI4_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SPI4_SPTI, \
|
||||
.flag = SPI4_TX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = SPI4_TX_DMA_IRQn, \
|
||||
.irq_prio = SPI4_TX_DMA_INT_PRIO, \
|
||||
.int_src = SPI4_TX_DMA_INT_SRC, \
|
||||
} \
|
||||
}
|
||||
#endif /* SPI4_TX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI4_TX_USING_DMA */
|
||||
|
||||
#ifdef BSP_SPI4_RX_USING_DMA
|
||||
#ifndef SPI4_RX_DMA_CONFIG
|
||||
#define SPI4_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI4_RX_DMA_INSTANCE, \
|
||||
.channel = SPI4_RX_DMA_CHANNEL, \
|
||||
.clock = SPI4_RX_DMA_CLOCK, \
|
||||
.trigger_select = SPI4_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SPI4_SPRI, \
|
||||
.flag = SPI4_RX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = SPI4_RX_DMA_IRQn, \
|
||||
.irq_prio = SPI4_RX_DMA_INT_PRIO, \
|
||||
.int_src = SPI4_RX_DMA_INT_SRC, \
|
||||
} \
|
||||
}
|
||||
#endif /* SPI4_RX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI4_RX_USING_DMA */
|
||||
|
||||
#ifdef BSP_USING_SPI5
|
||||
#ifndef SPI5_BUS_CONFIG
|
||||
#define SPI5_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = CM_SPI5, \
|
||||
.bus_name = "spi5", \
|
||||
.clock = FCG1_PERIPH_SPI5, \
|
||||
.timeout = 5000UL, \
|
||||
.err_irq.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_SPI5_ERR_IRQ_NUM, \
|
||||
.irq_prio = BSP_SPI5_ERR_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_SPI5_SPEI, \
|
||||
}, \
|
||||
}
|
||||
#endif /* SPI5_BUS_CONFIG */
|
||||
#endif /* BSP_USING_SPI5 */
|
||||
|
||||
#ifdef BSP_SPI5_TX_USING_DMA
|
||||
#ifndef SPI5_TX_DMA_CONFIG
|
||||
#define SPI5_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI5_TX_DMA_INSTANCE, \
|
||||
.channel = SPI5_TX_DMA_CHANNEL, \
|
||||
.clock = SPI5_TX_DMA_CLOCK, \
|
||||
.trigger_select = SPI5_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SPI5_SPTI, \
|
||||
.flag = SPI5_TX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = SPI5_TX_DMA_IRQn, \
|
||||
.irq_prio = SPI5_TX_DMA_INT_PRIO, \
|
||||
.int_src = SPI5_TX_DMA_INT_SRC, \
|
||||
} \
|
||||
}
|
||||
#endif /* SPI5_TX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI5_TX_USING_DMA */
|
||||
|
||||
#ifdef BSP_SPI5_RX_USING_DMA
|
||||
#ifndef SPI5_RX_DMA_CONFIG
|
||||
#define SPI5_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI5_RX_DMA_INSTANCE, \
|
||||
.channel = SPI5_RX_DMA_CHANNEL, \
|
||||
.clock = SPI5_RX_DMA_CLOCK, \
|
||||
.trigger_select = SPI5_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SPI5_SPRI, \
|
||||
.flag = SPI5_RX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = SPI5_RX_DMA_IRQn, \
|
||||
.irq_prio = SPI5_RX_DMA_INT_PRIO, \
|
||||
.int_src = SPI5_RX_DMA_INT_SRC, \
|
||||
} \
|
||||
}
|
||||
#endif /* SPI5_RX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI5_RX_USING_DMA */
|
||||
|
||||
#ifdef BSP_USING_SPI6
|
||||
#ifndef SPI6_BUS_CONFIG
|
||||
#define SPI6_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = CM_SPI6, \
|
||||
.bus_name = "spi6", \
|
||||
.clock = FCG1_PERIPH_SPI6, \
|
||||
.timeout = 5000UL, \
|
||||
.err_irq.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_SPI6_ERR_IRQ_NUM, \
|
||||
.irq_prio = BSP_SPI6_ERR_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_SPI6_SPEI, \
|
||||
}, \
|
||||
}
|
||||
#endif /* SPI6_BUS_CONFIG */
|
||||
#endif /* BSP_USING_SPI6 */
|
||||
|
||||
#ifdef BSP_SPI6_TX_USING_DMA
|
||||
#ifndef SPI6_TX_DMA_CONFIG
|
||||
#define SPI6_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI6_TX_DMA_INSTANCE, \
|
||||
.channel = SPI6_TX_DMA_CHANNEL, \
|
||||
.clock = SPI6_TX_DMA_CLOCK, \
|
||||
.trigger_select = SPI6_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SPI6_SPTI, \
|
||||
.flag = SPI6_TX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = SPI6_TX_DMA_IRQn, \
|
||||
.irq_prio = SPI6_TX_DMA_INT_PRIO, \
|
||||
.int_src = SPI6_TX_DMA_INT_SRC, \
|
||||
} \
|
||||
}
|
||||
#endif /* SPI6_TX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI6_TX_USING_DMA */
|
||||
|
||||
#ifdef BSP_SPI6_RX_USING_DMA
|
||||
#ifndef SPI6_RX_DMA_CONFIG
|
||||
#define SPI6_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI6_RX_DMA_INSTANCE, \
|
||||
.channel = SPI6_RX_DMA_CHANNEL, \
|
||||
.clock = SPI6_RX_DMA_CLOCK, \
|
||||
.trigger_select = SPI6_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SPI6_SPRI, \
|
||||
.flag = SPI6_RX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = SPI6_RX_DMA_IRQn, \
|
||||
.irq_prio = SPI6_RX_DMA_INT_PRIO, \
|
||||
.int_src = SPI6_RX_DMA_INT_SRC, \
|
||||
} \
|
||||
}
|
||||
#endif /* SPI6_RX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI6_RX_USING_DMA */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@ extern "C" {
|
|||
#include "adc_config.h"
|
||||
#include "dac_config.h"
|
||||
#include "gpio_config.h"
|
||||
#include "can_config.h"
|
||||
#include "mcan_config.h"
|
||||
#include "pm_config.h"
|
||||
#include "i2c_config.h"
|
||||
#include "qspi_config.h"
|
||||
|
|
|
|||
|
|
@ -20,7 +20,8 @@ extern "C" {
|
|||
#endif
|
||||
|
||||
|
||||
#define HC32_FLASH_SIZE_GRANULARITY (8 * 1024)
|
||||
#define HC32_FLASH_ERASE_GRANULARITY (8 * 1024)
|
||||
#define HC32_FLASH_WRITE_GRANULARITY (4)
|
||||
#define HC32_FLASH_SIZE (512 * 1024)
|
||||
#define HC32_FLASH_START_ADDRESS (0)
|
||||
#define HC32_FLASH_END_ADDRESS (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE)
|
||||
|
|
|
|||
|
|
@ -21,7 +21,8 @@ extern "C" {
|
|||
#endif
|
||||
|
||||
|
||||
#define HC32_FLASH_SIZE_GRANULARITY (8 * 1024)
|
||||
#define HC32_FLASH_ERASE_GRANULARITY (8 * 1024)
|
||||
#define HC32_FLASH_WRITE_GRANULARITY (4)
|
||||
#define HC32_FLASH_SIZE (512 * 1024)
|
||||
#define HC32_FLASH_START_ADDRESS (0)
|
||||
#define HC32_FLASH_END_ADDRESS (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE)
|
||||
|
|
|
|||
|
|
@ -20,9 +20,6 @@ extern "C" {
|
|||
|
||||
#ifdef BSP_USING_CAN1
|
||||
#define CAN1_CLOCK_SEL (CAN_CLOCK_SRC_40M)
|
||||
#ifdef RT_CAN_USING_CANFD
|
||||
#define CAN1_CANFD_MODE (CAN_FD_MD_ISO)
|
||||
#endif
|
||||
#define CAN1_NAME ("can1")
|
||||
#ifndef CAN1_INIT_PARAMS
|
||||
#define CAN1_INIT_PARAMS \
|
||||
|
|
@ -35,9 +32,6 @@ extern "C" {
|
|||
|
||||
#ifdef BSP_USING_CAN2
|
||||
#define CAN2_CLOCK_SEL (CAN_CLOCK_SRC_40M)
|
||||
#ifdef RT_CAN_USING_CANFD
|
||||
#define CAN2_CANFD_MODE (CAN_FD_MD_ISO)
|
||||
#endif
|
||||
#define CAN2_NAME ("can2")
|
||||
#ifndef CAN2_INIT_PARAMS
|
||||
#define CAN2_INIT_PARAMS \
|
||||
|
|
@ -50,9 +44,6 @@ extern "C" {
|
|||
|
||||
#ifdef BSP_USING_CAN3
|
||||
#define CAN3_CLOCK_SEL (CAN_CLOCK_SRC_40M)
|
||||
#ifdef RT_CAN_USING_CANFD
|
||||
#define CAN3_CANFD_MODE (CAN_FD_MD_ISO)
|
||||
#endif
|
||||
#define CAN3_NAME ("can3")
|
||||
#ifndef CAN3_INIT_PARAMS
|
||||
#define CAN3_INIT_PARAMS \
|
||||
|
|
|
|||
|
|
@ -253,123 +253,6 @@ extern "C" {
|
|||
#endif /* SPI4_RX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI4_RX_USING_DMA */
|
||||
|
||||
#ifdef BSP_USING_SPI5
|
||||
#ifndef SPI5_BUS_CONFIG
|
||||
#define SPI5_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = CM_SPI5, \
|
||||
.bus_name = "spi5", \
|
||||
.clock = FCG1_PERIPH_SPI5, \
|
||||
.timeout = 5000UL, \
|
||||
.err_irq.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_SPI5_ERR_IRQ_NUM, \
|
||||
.irq_prio = BSP_SPI5_ERR_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_SPI5_SPEI, \
|
||||
}, \
|
||||
}
|
||||
#endif /* SPI5_BUS_CONFIG */
|
||||
#endif /* BSP_USING_SPI5 */
|
||||
|
||||
#ifdef BSP_SPI5_TX_USING_DMA
|
||||
#ifndef SPI5_TX_DMA_CONFIG
|
||||
#define SPI5_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI5_TX_DMA_INSTANCE, \
|
||||
.channel = SPI5_TX_DMA_CHANNEL, \
|
||||
.clock = SPI5_TX_DMA_CLOCK, \
|
||||
.trigger_select = SPI5_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SPI5_SPTI, \
|
||||
.flag = SPI5_TX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = SPI5_TX_DMA_IRQn, \
|
||||
.irq_prio = SPI5_TX_DMA_INT_PRIO, \
|
||||
.int_src = SPI5_TX_DMA_INT_SRC, \
|
||||
} \
|
||||
}
|
||||
#endif /* SPI5_TX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI5_TX_USING_DMA */
|
||||
|
||||
#ifdef BSP_SPI5_RX_USING_DMA
|
||||
#ifndef SPI5_RX_DMA_CONFIG
|
||||
#define SPI5_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI5_RX_DMA_INSTANCE, \
|
||||
.channel = SPI5_RX_DMA_CHANNEL, \
|
||||
.clock = SPI5_RX_DMA_CLOCK, \
|
||||
.trigger_select = SPI5_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SPI5_SPRI, \
|
||||
.flag = SPI5_RX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = SPI5_RX_DMA_IRQn, \
|
||||
.irq_prio = SPI5_RX_DMA_INT_PRIO, \
|
||||
.int_src = SPI5_RX_DMA_INT_SRC, \
|
||||
} \
|
||||
}
|
||||
#endif /* SPI5_RX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI5_RX_USING_DMA */
|
||||
|
||||
#ifdef BSP_USING_SPI6
|
||||
#ifndef SPI6_BUS_CONFIG
|
||||
#define SPI6_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = CM_SPI6, \
|
||||
.bus_name = "spi6", \
|
||||
.clock = FCG1_PERIPH_SPI6, \
|
||||
.timeout = 5000UL, \
|
||||
.err_irq.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_SPI6_ERR_IRQ_NUM, \
|
||||
.irq_prio = BSP_SPI6_ERR_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_SPI6_SPEI, \
|
||||
}, \
|
||||
}
|
||||
#endif /* SPI6_BUS_CONFIG */
|
||||
#endif /* BSP_USING_SPI6 */
|
||||
|
||||
#ifdef BSP_SPI6_TX_USING_DMA
|
||||
#ifndef SPI6_TX_DMA_CONFIG
|
||||
#define SPI6_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI6_TX_DMA_INSTANCE, \
|
||||
.channel = SPI6_TX_DMA_CHANNEL, \
|
||||
.clock = SPI6_TX_DMA_CLOCK, \
|
||||
.trigger_select = SPI6_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SPI6_SPTI, \
|
||||
.flag = SPI6_TX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = SPI6_TX_DMA_IRQn, \
|
||||
.irq_prio = SPI6_TX_DMA_INT_PRIO, \
|
||||
.int_src = SPI6_TX_DMA_INT_SRC, \
|
||||
} \
|
||||
}
|
||||
#endif /* SPI6_TX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI6_TX_USING_DMA */
|
||||
|
||||
#ifdef BSP_SPI6_RX_USING_DMA
|
||||
#ifndef SPI6_RX_DMA_CONFIG
|
||||
#define SPI6_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI6_RX_DMA_INSTANCE, \
|
||||
.channel = SPI6_RX_DMA_CHANNEL, \
|
||||
.clock = SPI6_RX_DMA_CLOCK, \
|
||||
.trigger_select = SPI6_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SPI6_SPRI, \
|
||||
.flag = SPI6_RX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = SPI6_RX_DMA_IRQn, \
|
||||
.irq_prio = SPI6_RX_DMA_INT_PRIO, \
|
||||
.int_src = SPI6_RX_DMA_INT_SRC, \
|
||||
} \
|
||||
}
|
||||
#endif /* SPI6_RX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI6_RX_USING_DMA */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -20,7 +20,8 @@ extern "C" {
|
|||
#endif
|
||||
|
||||
|
||||
#define HC32_FLASH_SIZE_GRANULARITY (8 * 1024)
|
||||
#define HC32_FLASH_ERASE_GRANULARITY (8 * 1024)
|
||||
#define HC32_FLASH_WRITE_GRANULARITY (4)
|
||||
#define HC32_FLASH_SIZE (2 * 1024 * 1024)
|
||||
#define HC32_FLASH_START_ADDRESS (0)
|
||||
#define HC32_FLASH_END_ADDRESS (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE)
|
||||
|
|
|
|||
|
|
@ -20,9 +20,6 @@ extern "C" {
|
|||
|
||||
#ifdef BSP_USING_CAN1
|
||||
#define CAN1_CLOCK_SEL (CAN_CLOCK_SRC_40M)
|
||||
#ifdef RT_CAN_USING_CANFD
|
||||
#define CAN1_CANFD_MODE (CAN_FD_MD_ISO)
|
||||
#endif
|
||||
#define CAN1_NAME ("can1")
|
||||
#ifndef CAN1_INIT_PARAMS
|
||||
#define CAN1_INIT_PARAMS \
|
||||
|
|
@ -35,9 +32,6 @@ extern "C" {
|
|||
|
||||
#ifdef BSP_USING_CAN2
|
||||
#define CAN2_CLOCK_SEL (CAN_CLOCK_SRC_40M)
|
||||
#ifdef RT_CAN_USING_CANFD
|
||||
#define CAN2_CANFD_MODE (CAN_FD_MD_ISO)
|
||||
#endif
|
||||
#define CAN2_NAME ("can2")
|
||||
#ifndef CAN2_INIT_PARAMS
|
||||
#define CAN2_INIT_PARAMS \
|
||||
|
|
|
|||
|
|
@ -258,6 +258,30 @@ extern "C" {
|
|||
#define I2C4_RX_DMA_INT_SRC INT_SRC_DMA1_TC7
|
||||
#endif
|
||||
|
||||
/* DMA1 ch8 */
|
||||
#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
|
||||
#define SPI5_TX_DMA_INSTANCE CM_DMA1
|
||||
#define SPI5_TX_DMA_CHANNEL DMA_CH8
|
||||
#define SPI5_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define SPI5_TX_DMA_TRIG_SELECT AOS_DMA1_8
|
||||
#define SPI5_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH8
|
||||
#define SPI5_TX_DMA_IRQn BSP_DMA1_CH8_IRQ_NUM
|
||||
#define SPI5_TX_DMA_INT_PRIO BSP_DMA1_CH8_IRQ_PRIO
|
||||
#define SPI5_TX_DMA_INT_SRC INT_SRC_DMA1_TC8
|
||||
#endif
|
||||
|
||||
/* DMA1 ch9 */
|
||||
#if defined(BSP_SPI6_TX_USING_DMA) && !defined(SPI6_TX_DMA_INSTANCE)
|
||||
#define SPI6_TX_DMA_INSTANCE CM_DMA1
|
||||
#define SPI6_TX_DMA_CHANNEL DMA_CH9
|
||||
#define SPI6_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define SPI6_TX_DMA_TRIG_SELECT AOS_DMA1_9
|
||||
#define SPI6_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH9
|
||||
#define SPI6_TX_DMA_IRQn BSP_DMA1_CH9_IRQ_NUM
|
||||
#define SPI6_TX_DMA_INT_PRIO BSP_DMA1_CH9_IRQ_PRIO
|
||||
#define SPI6_TX_DMA_INT_SRC INT_SRC_DMA1_TC9
|
||||
#endif
|
||||
|
||||
/* DMA2 ch0 */
|
||||
#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
|
||||
#define UART1_RX_DMA_INSTANCE CM_DMA2
|
||||
|
|
|
|||
|
|
@ -74,6 +74,12 @@ extern "C" {
|
|||
/* DMA1 ch7 */
|
||||
#define BSP_DMA1_CH7_IRQ_NUM INT019_IRQn
|
||||
#define BSP_DMA1_CH7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
/* DMA1 ch8 */
|
||||
#define BSP_DMA1_CH8_IRQ_NUM INT020_IRQn
|
||||
#define BSP_DMA1_CH8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
/* DMA1 ch9 */
|
||||
#define BSP_DMA1_CH9_IRQ_NUM INT021_IRQn
|
||||
#define BSP_DMA1_CH9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
|
||||
/* DMA2 ch0 */
|
||||
#define BSP_DMA2_CH0_IRQ_NUM INT044_IRQn
|
||||
|
|
@ -235,6 +241,16 @@ extern "C" {
|
|||
#define BSP_SPI4_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_SPI5)
|
||||
#define BSP_SPI5_ERR_IRQ_NUM INT098_IRQn
|
||||
#define BSP_SPI5_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_SPI6)
|
||||
#define BSP_SPI6_ERR_IRQ_NUM INT099_IRQn
|
||||
#define BSP_SPI6_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_UART8)
|
||||
#define BSP_UART8_RXERR_IRQ_NUM INT017_IRQn
|
||||
#define BSP_UART8_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
|
|
@ -0,0 +1,42 @@
|
|||
*.pyc
|
||||
*.map
|
||||
*.dblite
|
||||
*.elf
|
||||
*.bin
|
||||
*.hex
|
||||
*.axf
|
||||
*.exe
|
||||
*.pdb
|
||||
*.idb
|
||||
*.ilk
|
||||
*.old
|
||||
build
|
||||
Debug
|
||||
documentation/html
|
||||
packages/
|
||||
*~
|
||||
*.o
|
||||
*.obj
|
||||
*.out
|
||||
*.bak
|
||||
*.dep
|
||||
*.lib
|
||||
*.i
|
||||
*.d
|
||||
.DS_Stor*
|
||||
.config 3
|
||||
.config 4
|
||||
.config 5
|
||||
Midea-X1
|
||||
*.uimg
|
||||
GPATH
|
||||
GRTAGS
|
||||
GTAGS
|
||||
.vscode
|
||||
JLinkLog.txt
|
||||
JLinkSettings.ini
|
||||
DebugConfig/
|
||||
RTE/
|
||||
settings/
|
||||
*.uvguix*
|
||||
cconfig.h
|
||||
|
|
@ -0,0 +1,78 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<projectDescription>
|
||||
<name>project</name>
|
||||
<comment />
|
||||
<projects>
|
||||
</projects>
|
||||
<buildSpec>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
|
||||
<triggers>clean,full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
|
||||
<triggers>full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
</buildSpec>
|
||||
<natures>
|
||||
<nature>org.eclipse.cdt.core.cnature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
|
||||
</natures>
|
||||
<linkedResources>
|
||||
<link>
|
||||
<name>rt-thread</name>
|
||||
<type>2</type>
|
||||
<locationURI>virtual:/virtual</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>rt-thread/bsp</name>
|
||||
<type>2</type>
|
||||
<locationURI>virtual:/virtual</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>rt-thread/components</name>
|
||||
<type>2</type>
|
||||
<locationURI>$%7BPARENT-3-PROJECT_LOC%7D/components</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>rt-thread/include</name>
|
||||
<type>2</type>
|
||||
<locationURI>$%7BPARENT-3-PROJECT_LOC%7D/include</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>rt-thread/libcpu</name>
|
||||
<type>2</type>
|
||||
<locationURI>$%7BPARENT-3-PROJECT_LOC%7D/libcpu</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>rt-thread/src</name>
|
||||
<type>2</type>
|
||||
<locationURI>$%7BPARENT-3-PROJECT_LOC%7D/src</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>rt-thread/bsp/hc32</name>
|
||||
<type>2</type>
|
||||
<locationURI>virtual:/virtual</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>rt-thread/bsp/hc32/libraries</name>
|
||||
<type>2</type>
|
||||
<locationURI>$%7BPARENT-1-PROJECT_LOC%7D/libraries</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>rt-thread/bsp/hc32/platform</name>
|
||||
<type>2</type>
|
||||
<locationURI>PARENT-1-PROJECT_LOC/platform</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>rt-thread/bsp/hc32/tests</name>
|
||||
<type>2</type>
|
||||
<locationURI>PARENT-1-PROJECT_LOC/tests</locationURI>
|
||||
</link>
|
||||
</linkedResources>
|
||||
</projectDescription>
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
mainmenu "RT-Thread Configuration"
|
||||
|
||||
BSP_DIR := .
|
||||
|
||||
RTT_DIR := ../../..
|
||||
|
||||
PKGS_DIR := packages
|
||||
|
||||
source "$(RTT_DIR)/Kconfig"
|
||||
osource "$PKGS_DIR/Kconfig"
|
||||
rsource "../libraries/Kconfig"
|
||||
rsource "board/Kconfig"
|
||||
|
|
@ -0,0 +1,113 @@
|
|||
# XHSC EV_F4A8_LQ176 开发板 BSP 说明
|
||||
|
||||
## 简介
|
||||
|
||||
本文档为小华半导体为 EV_F4A8_LQ176 开发板提供的 BSP (板级支持包) 说明。
|
||||
|
||||
主要内容如下：
|
||||
|
||||
- 开发板资源介绍
|
||||
- BSP 快速上手
|
||||
- 进阶使用方法
|
||||
|
||||
通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
|
||||
|
||||
## 开发板介绍
|
||||
|
||||
EV_F4A8_LQ176 是 XHSC 官方推出的开发板，搭载 HC32F4A8SITB 芯片，基于 ARM Cortex-M4 内核，最高主频 240 MHz，具有丰富的板载资源，可以充分发挥 HC32F4A8SITB 的芯片性能。
|
||||
|
||||
开发板外观如下图所示：
|
||||
|
||||
|
||||
|
||||
EV_F4A8_LQ176 开发板常用 **板载资源** 如下：
|
||||
|
||||
- MCU：HC32F4A8SITB，主频240MHz，2048KB FLASH，512KB RAM
|
||||
- 外部RAM：IS62WV51216(SRAM, 1MB) W9825G6KH(SDRAM, 8MB)
|
||||
- 外部FLASH: MT29F2G08AB(Nand, 256MB) W25Q64(SPI NOR, 8MB)
|
||||
- 常用外设
|
||||
- LED：3 个， user LED(LED0,LED1,LED2)。
|
||||
- 按键：6个，矩阵键盘(K1~K4)、WAKEUP(K5)、RESET(K0)。
|
||||
- 常用接口：USB转串口、SD卡接口、以太网接口、LCD接口、USB HS、USB FS、USB 3300、DVP接口、3.5mm耳机接口、Line in接口、喇叭接口
|
||||
- 调试接口：板载DAP调试器、标准JTAG/SWD。
|
||||
|
||||
开发板更多详细信息请参考小华半导体半导体[EV_F4A8_LQ176](https://www.xhsc.com.cn)
|
||||
|
||||
## 外设支持
|
||||
|
||||
本 BSP 目前对外设的支持情况如下：
|
||||
|
||||
| **板载外设** | **支持情况** | **备注** |
|
||||
| :------------ | :-----------: | :-----------------------------------: |
|
||||
| USB 转串口 | 支持 | 使用 UART1 |
|
||||
| LED | 支持 | LED |
|
||||
| SDRAM | 支持 | IS42S16400J |
|
||||
|
||||
| **片上外设** | **支持情况** | **备注** |
|
||||
| :------------ | :-----------: | :-----------------------------------: |
|
||||
| CAN | 支持 | |
|
||||
| GPIO | 支持 | PA0, PA1... PI13 ---> PIN: 0, 1...141 |
|
||||
| WDT | 支持 | |
|
||||
| SPI | 支持 | SPI1~6 |
|
||||
| SDIO | 支持 | |
|
||||
| UART V1 & V2 | 支持 | UART1~10 |
|
||||
|
||||
## 使用说明
|
||||
|
||||
使用说明分为如下两个章节：
|
||||
|
||||
- 快速上手
|
||||
|
||||
本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
|
||||
|
||||
- 进阶使用
|
||||
|
||||
本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
|
||||
|
||||
|
||||
### 快速上手
|
||||
|
||||
本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
|
||||
|
||||
#### 硬件连接
|
||||
|
||||
使用Type-A to MircoUSB线连接开发板和PC供电。
|
||||
|
||||
#### 编译下载
|
||||
|
||||
双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
|
||||
|
||||
> 工程默认配置使用板载 DAP 下载程序，点击下载按钮即可下载程序到开发板。
|
||||
|
||||
#### 运行结果
|
||||
|
||||
下载程序成功之后，系统会自动运行，观察开发板上LED的运行效果，绿色LED11会周期性闪烁。
|
||||
|
||||
USB虚拟COM端口默认连接串口1，在终端工具里打开相应的串口，复位设备后，可以看到 RT-Thread 的输出信息:
|
||||
|
||||
```
|
||||
\ | /
|
||||
- RT - Thread Operating System
|
||||
/ | \ 4.1.0 build Apr 24 2022 13:32:39
|
||||
2006 - 2022 Copyright by RT-Thread team
|
||||
msh >
|
||||
```
|
||||
|
||||
### 进阶使用
|
||||
|
||||
此 BSP 默认只开启了 GPIO 和 串口 1 的功能，更多高级功能需要利用 env 工具对 BSP 进行配置，步骤如下：
|
||||
|
||||
1. 在 bsp 下打开 env 工具。
|
||||
|
||||
2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
|
||||
|
||||
3. 输入`pkgs --update`命令更新软件包。
|
||||
|
||||
4. 输入`scons --target=mdk5/iar` 命令重新生成工程。
|
||||
|
||||
|
||||
## 联系人信息
|
||||
|
||||
维护人:
|
||||
|
||||
- [小华半导体MCU](https://www.xhsc.com.cn)，邮箱：<xhsc_ae_cd_ap@xhsc.com.cn>
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
# for module compiling
|
||||
import os
|
||||
Import('RTT_ROOT')
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
objs = []
|
||||
list = os.listdir(cwd)
|
||||
|
||||
for d in list:
|
||||
path = os.path.join(cwd, d)
|
||||
if os.path.isfile(os.path.join(path, 'SConscript')):
|
||||
objs = objs + SConscript(os.path.join(d, 'SConscript'))
|
||||
|
||||
def find_keyword_replace(file_path, keyword, replace, split_num, split_char):
|
||||
with open(file_path, 'r', encoding='utf-8') as file:
|
||||
lines = file.readlines()
|
||||
|
||||
for i, line in enumerate(lines):
|
||||
if keyword in line:
|
||||
parts = line.split(split_char)
|
||||
parts[split_num] = replace
|
||||
new_line = split_char.join(parts)
|
||||
lines[i] = new_line
|
||||
|
||||
with open(file_path, 'w', encoding='utf-8') as file:
|
||||
file.writelines(lines)
|
||||
|
||||
Import('PACKAGES_PATH')
|
||||
replace = PACKAGES_PATH.split("\\")[-1]
|
||||
|
||||
if rtconfig.PLATFORM in ['gcc']:
|
||||
file_path = os.path.join(cwd, 'jlink', 'ev_hc32f4a8_lqfp176 Debug.launch')
|
||||
svd_keyword = 'HC32F4A8.svd'
|
||||
split_num = 3
|
||||
elif rtconfig.PLATFORM in ['armcc', 'armclang']:
|
||||
file_path = os.path.join(cwd, 'template.uvprojx')
|
||||
svd_keyword = 'HC32F4A8.SFR'
|
||||
split_num = 2
|
||||
elif rtconfig.PLATFORM in ['iccarm']:
|
||||
file_path = os.path.join(cwd, 'project.ewd')
|
||||
svd_keyword = 'HC32F4A8.svd'
|
||||
split_num = 3
|
||||
board_keyword = 'FlashHC32F4A8xI.board'
|
||||
find_keyword_replace(file_path, board_keyword, replace, split_num, '/')
|
||||
|
||||
find_keyword_replace(file_path, svd_keyword, replace, split_num, '/')
|
||||
|
||||
Return('objs')
|
||||
|
|
@ -0,0 +1,65 @@
|
|||
import os
|
||||
import sys
|
||||
import rtconfig
|
||||
|
||||
if os.getenv('RTT_ROOT'):
|
||||
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||
else:
|
||||
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
|
||||
|
||||
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
|
||||
try:
|
||||
from building import *
|
||||
except:
|
||||
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
|
||||
print(RTT_ROOT)
|
||||
exit(-1)
|
||||
|
||||
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
|
||||
|
||||
DefaultEnvironment(tools=[])
|
||||
env = Environment(tools = ['mingw'],
|
||||
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
|
||||
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
|
||||
AR = rtconfig.AR, ARFLAGS = '-rc',
|
||||
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
|
||||
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
|
||||
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
|
||||
|
||||
if rtconfig.PLATFORM in ['iccarm']:
|
||||
env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
|
||||
env.Replace(ARFLAGS = [''])
|
||||
env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map')
|
||||
|
||||
Export('RTT_ROOT')
|
||||
Export('rtconfig')
|
||||
|
||||
SDK_ROOT = os.path.abspath('./')
|
||||
|
||||
if os.path.exists(SDK_ROOT + '/libraries'):
|
||||
libraries_path_prefix = SDK_ROOT + '/libraries'
|
||||
else:
|
||||
libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
|
||||
|
||||
SDK_LIB = libraries_path_prefix
|
||||
Export('SDK_LIB')
|
||||
|
||||
# prepare building environment
|
||||
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
|
||||
|
||||
hc32_library = 'hc32f4a8_ddl'
|
||||
rtconfig.BSP_LIBRARY_TYPE = hc32_library
|
||||
|
||||
# include drivers
|
||||
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'hc32_drivers', 'SConscript')))
|
||||
|
||||
# include platform
|
||||
platform_path_prefix = os.path.dirname(SDK_ROOT) + '/platform'
|
||||
objs.extend(SConscript(os.path.join(platform_path_prefix, 'SConscript')))
|
||||
|
||||
# include tests
|
||||
test_path_prefix = os.path.dirname(SDK_ROOT) + '/tests'
|
||||
objs.extend(SConscript(os.path.join(test_path_prefix, 'SConscript')))
|
||||
|
||||
# make a building
|
||||
DoBuilding(TARGET, objs)
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
from building import *
|
||||
import os
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = Glob('*.c')
|
||||
CPPPATH = [cwd]
|
||||
|
||||
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
list = os.listdir(cwd)
|
||||
for item in list:
|
||||
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
|
||||
group = group + SConscript(os.path.join(item, 'SConscript'))
|
||||
|
||||
Return('group')
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include <board.h>
|
||||
|
||||
/* defined the LED_GREEN pin: PC9 */
|
||||
#define LED_GREEN_PIN GET_PIN(C, 9)
|
||||
|
||||
|
||||
int main(void)
|
||||
{
|
||||
/* set LED_GREEN_PIN pin mode to output */
|
||||
rt_pin_mode(LED_GREEN_PIN, PIN_MODE_OUTPUT);
|
||||
|
||||
while (1)
|
||||
{
|
||||
rt_pin_write(LED_GREEN_PIN, PIN_HIGH);
|
||||
rt_thread_mdelay(500);
|
||||
rt_pin_write(LED_GREEN_PIN, PIN_LOW);
|
||||
rt_thread_mdelay(500);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,98 @@
|
|||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2023-10-27 CDT first version
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include <board.h>
|
||||
|
||||
#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
|
||||
|
||||
#define XTAL32_FCM_THREAD_STACK_SIZE (1024)
|
||||
|
||||
/**
|
||||
* @brief This thread is used to monitor whether XTAL32 is stable.
|
||||
* This thread only runs once after the system starts.
|
||||
* When stability is detected or 2s times out, the thread will end.
|
||||
* (When a timeout occurs it will be prompted via rt_kprintf)
|
||||
*/
|
||||
void xtal32_fcm_thread_entry(void *parameter)
|
||||
{
|
||||
stc_fcm_init_t stcFcmInit;
|
||||
uint32_t u32TimeOut = 0UL;
|
||||
uint32_t u32Time = 200UL; /* 200*10ms = 2s */
|
||||
|
||||
/* FCM config */
|
||||
FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, ENABLE);
|
||||
(void)FCM_StructInit(&stcFcmInit);
|
||||
stcFcmInit.u32RefClock = FCM_REF_CLK_MRC;
|
||||
stcFcmInit.u32RefClockDiv = FCM_REF_CLK_DIV8192; /* ~1ms cycle */
|
||||
stcFcmInit.u32RefClockEdge = FCM_REF_CLK_RISING;
|
||||
stcFcmInit.u32TargetClock = FCM_TARGET_CLK_XTAL32;
|
||||
stcFcmInit.u32TargetClockDiv = FCM_TARGET_CLK_DIV1;
|
||||
stcFcmInit.u16LowerLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL);
|
||||
stcFcmInit.u16UpperLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL);
|
||||
(void)FCM_Init(&stcFcmInit);
|
||||
/* Enable FCM, to ensure xtal32 stable */
|
||||
FCM_Cmd(ENABLE);
|
||||
|
||||
while (1)
|
||||
{
|
||||
if (SET == FCM_GetStatus(FCM_FLAG_END))
|
||||
{
|
||||
FCM_ClearStatus(FCM_FLAG_END);
|
||||
if ((SET == FCM_GetStatus(FCM_FLAG_ERR)) || (SET == FCM_GetStatus(FCM_FLAG_OVF)))
|
||||
{
|
||||
FCM_ClearStatus(FCM_FLAG_ERR | FCM_FLAG_OVF);
|
||||
}
|
||||
else
|
||||
{
|
||||
(void)FCM_DeInit();
|
||||
FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE);
|
||||
/* XTAL32 stabled */
|
||||
break;
|
||||
}
|
||||
}
|
||||
u32TimeOut++;
|
||||
if (u32TimeOut > u32Time)
|
||||
{
|
||||
(void)FCM_DeInit();
|
||||
FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE);
|
||||
rt_kprintf("Error: XTAL32 still unstable, timeout.\n");
|
||||
break;
|
||||
}
|
||||
rt_thread_mdelay(10);
|
||||
}
|
||||
}
|
||||
|
||||
int xtal32_fcm_thread_create(void)
|
||||
{
|
||||
rt_thread_t tid;
|
||||
|
||||
tid = rt_thread_create("xtal32_fcm", xtal32_fcm_thread_entry, RT_NULL,
|
||||
XTAL32_FCM_THREAD_STACK_SIZE, RT_THREAD_PRIORITY_MAX - 2, 10);
|
||||
if (tid != RT_NULL)
|
||||
{
|
||||
rt_thread_startup(tid);
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_kprintf("create xtal32_fcm thread err!");
|
||||
}
|
||||
return RT_EOK;
|
||||
}
|
||||
INIT_APP_EXPORT(xtal32_fcm_thread_create);
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,21 @@
|
|||
import os
|
||||
import rtconfig
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
# add general drivers
|
||||
src = Split('''
|
||||
board.c
|
||||
board_config.c
|
||||
''')
|
||||
|
||||
path = [cwd]
|
||||
path += [cwd + '/ports']
|
||||
path += [cwd + '/config']
|
||||
path += [cwd + '/config/usb_config']
|
||||
|
||||
CPPDEFINES = ['HC32F4A8', '__DEBUG']
|
||||
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
|
||||
|
||||
Return('group')
|
||||
|
|
@ -0,0 +1,149 @@
|
|||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
* 2024-06-11 CDT remove CLK_Delay for usb, as it is already included in ddl API
|
||||
*/
|
||||
|
||||
#include "board.h"
|
||||
#include "board_config.h"
|
||||
|
||||
/* unlock/lock peripheral */
|
||||
#define EXAMPLE_PERIPH_WE (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \
|
||||
LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM | LL_PERIPH_LVD)
|
||||
#define EXAMPLE_PERIPH_WP (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM)
|
||||
|
||||
/** System Base Configuration
|
||||
*/
|
||||
void SystemBase_Config(void)
|
||||
{
|
||||
#if defined(BSP_USING_ON_CHIP_FLASH_ICODE_CACHE)
|
||||
EFM_ICacheCmd(ENABLE);
|
||||
#endif
|
||||
#if defined(BSP_USING_ON_CHIP_FLASH_DCODE_CACHE)
|
||||
EFM_DCacheCmd(ENABLE);
|
||||
#endif
|
||||
#if defined(BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH)
|
||||
EFM_PrefetchCmd(ENABLE);
|
||||
#endif
|
||||
/* Reset the VBAT area */
|
||||
PWC_VBAT_Reset();
|
||||
}
|
||||
|
||||
/** System Clock Configuration
|
||||
*/
|
||||
void SystemClock_Config(void)
|
||||
{
|
||||
stc_clock_xtal_init_t stcXtalInit;
|
||||
stc_clock_pll_init_t stcPLLHInit;
|
||||
#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH)
|
||||
stc_clock_pllx_init_t stcPLLAInit;
|
||||
#endif
|
||||
#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
|
||||
stc_clock_xtal32_init_t stcXtal32Init;
|
||||
#endif
|
||||
|
||||
/* PCLK0, HCLK Max 240MHz */
|
||||
/* PCLK1, PCLK4 Max 120MHz */
|
||||
/* PCLK2, PCLK3 Max 60MHz */
|
||||
/* EX BUS Max 120MHz */
|
||||
CLK_SetClockDiv(CLK_BUS_CLK_ALL, \
|
||||
(CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | CLK_PCLK2_DIV4 | \
|
||||
CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2 | CLK_EXCLK_DIV4 | \
|
||||
CLK_HCLK_DIV1));
|
||||
|
||||
GPIO_AnalogCmd(XTAL_PORT, XTAL_IN_PIN | XTAL_OUT_PIN, ENABLE);
|
||||
(void)CLK_XtalStructInit(&stcXtalInit);
|
||||
/* Config Xtal and enable Xtal */
|
||||
stcXtalInit.u8Mode = CLK_XTAL_MD_OSC;
|
||||
stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW;
|
||||
stcXtalInit.u8State = CLK_XTAL_ON;
|
||||
stcXtalInit.u8StableTime = CLK_XTAL_STB_2MS;
|
||||
(void)CLK_XtalInit(&stcXtalInit);
|
||||
|
||||
(void)CLK_PLLStructInit(&stcPLLHInit);
|
||||
/* VCO = (8/1)*120 = 960MHz*/
|
||||
stcPLLHInit.u8PLLState = CLK_PLL_ON;
|
||||
stcPLLHInit.PLLCFGR = 0UL;
|
||||
stcPLLHInit.PLLCFGR_f.PLLM = 1UL - 1UL;
|
||||
stcPLLHInit.PLLCFGR_f.PLLN = 120UL - 1UL;
|
||||
stcPLLHInit.PLLCFGR_f.PLLP = 4UL - 1UL;
|
||||
stcPLLHInit.PLLCFGR_f.PLLQ = 4UL - 1UL;
|
||||
stcPLLHInit.PLLCFGR_f.PLLR = 4UL - 1UL;
|
||||
stcPLLHInit.PLLCFGR_f.PLLSRC = CLK_PLL_SRC_XTAL;
|
||||
(void)CLK_PLLInit(&stcPLLHInit);
|
||||
|
||||
/* Highspeed SRAM set to 0 Read/Write wait cycle */
|
||||
SRAM_SetWaitCycle(SRAM_SRAMH, SRAM_WAIT_CYCLE0, SRAM_WAIT_CYCLE0);
|
||||
/* SRAM1_2_3_4_backup set to 1 Read/Write wait cycle */
|
||||
SRAM_SetWaitCycle((SRAM_SRAM123 | SRAM_SRAM4 | SRAM_SRAMB), SRAM_WAIT_CYCLE1, SRAM_WAIT_CYCLE1);
|
||||
/* 0-wait @ 40MHz */
|
||||
(void)EFM_SetWaitCycle(EFM_WAIT_CYCLE5);
|
||||
/* 4 cycles for 200 ~ 250MHz */
|
||||
GPIO_SetReadWaitCycle(GPIO_RD_WAIT4);
|
||||
CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL);
|
||||
|
||||
#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH)
|
||||
/* PLLX for USB */
|
||||
(void)CLK_PLLxStructInit(&stcPLLAInit);
|
||||
/* VCO = (8/2)*120 = 480MHz*/
|
||||
stcPLLAInit.u8PLLState = CLK_PLL_ON;
|
||||
stcPLLAInit.PLLCFGR = 0UL;
|
||||
stcPLLAInit.PLLCFGR_f.PLLM = 2UL - 1UL;
|
||||
stcPLLAInit.PLLCFGR_f.PLLN = 120UL - 1UL;
|
||||
stcPLLAInit.PLLCFGR_f.PLLP = 10UL - 1UL;
|
||||
stcPLLAInit.PLLCFGR_f.PLLQ = 4UL - 1UL;
|
||||
stcPLLAInit.PLLCFGR_f.PLLR = 4UL - 1UL;
|
||||
(void)CLK_PLLxInit(&stcPLLAInit);
|
||||
#endif
|
||||
|
||||
#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
|
||||
/* Xtal32 config */
|
||||
GPIO_AnalogCmd(XTAL32_PORT, XTAL32_IN_PIN | XTAL32_OUT_PIN, ENABLE);
|
||||
(void)CLK_Xtal32StructInit(&stcXtal32Init);
|
||||
stcXtal32Init.u8State = CLK_XTAL32_ON;
|
||||
stcXtal32Init.u8Drv = CLK_XTAL32_DRV_HIGH;
|
||||
stcXtal32Init.u8Filter = CLK_XTAL32_FILTER_RUN_MD;
|
||||
(void)CLK_Xtal32Init(&stcXtal32Init);
|
||||
#endif
|
||||
}
|
||||
|
||||
/** Peripheral Clock Configuration
|
||||
*/
|
||||
void PeripheralClock_Config(void)
|
||||
{
|
||||
#if defined(BSP_USING_CAN1)
|
||||
CLK_SetCANClockSrc(CLK_CAN1, CLK_CANCLK_SYSCLK_DIV6);
|
||||
#endif
|
||||
#if defined(BSP_USING_CAN2)
|
||||
CLK_SetCANClockSrc(CLK_CAN2, CLK_CANCLK_SYSCLK_DIV6);
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_MCAN1)
|
||||
CLK_SetCANClockSrc(CLK_MCAN1, CLK_CANCLK_SYSCLK_DIV6);
|
||||
#endif
|
||||
#if defined(BSP_USING_MCAN2)
|
||||
CLK_SetCANClockSrc(CLK_MCAN2, CLK_CANCLK_SYSCLK_DIV6);
|
||||
#endif
|
||||
|
||||
#if defined(RT_USING_ADC)
|
||||
CLK_SetPeriClockSrc(CLK_PERIPHCLK_PCLK);
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH)
|
||||
CLK_SetUSBClockSrc(CLK_USBCLK_PLLXP);
|
||||
#endif
|
||||
}
|
||||
|
||||
/** Peripheral Registers Unlock
|
||||
*/
|
||||
void PeripheralRegister_Unlock(void)
|
||||
{
|
||||
LL_PERIPH_WE(EXAMPLE_PERIPH_WE);
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __BOARD_H__
|
||||
#define __BOARD_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "hc32_ll.h"
|
||||
#include "drv_gpio.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#define HC32_FLASH_ERASE_GRANULARITY (8 * 1024)
|
||||
#define HC32_FLASH_WRITE_GRANULARITY (16)
|
||||
#define HC32_FLASH_SIZE (2 * 1024 * 1024)
|
||||
#define HC32_FLASH_START_ADDRESS (0)
|
||||
#define HC32_FLASH_END_ADDRESS (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE)
|
||||
|
||||
#define HC32_SRAM_SIZE (512)
|
||||
#define HC32_SRAM_END (0x1FFE0000 + HC32_SRAM_SIZE * 1024)
|
||||
|
||||
#ifdef __ARMCC_VERSION
|
||||
extern int Image$$RW_IRAM2$$ZI$$Limit;
|
||||
#define HEAP_BEGIN (&Image$$RW_IRAM2$$ZI$$Limit)
|
||||
#elif __ICCARM__
|
||||
#pragma section="HEAP"
|
||||
#define HEAP_BEGIN (__segment_end("HEAP"))
|
||||
#else
|
||||
extern int __bss_end;
|
||||
#define HEAP_BEGIN (&__bss_end)
|
||||
#endif
|
||||
|
||||
#define HEAP_END HC32_SRAM_END
|
||||
|
||||
void PeripheralRegister_Unlock(void);
|
||||
void PeripheralClock_Config(void);
|
||||
void SystemBase_Config(void);
|
||||
void SystemClock_Config(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,778 @@
|
|||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#include <rtdevice.h>
|
||||
#include "board_config.h"
|
||||
#include "tca9539_port.h"
|
||||
|
||||
/**
|
||||
* The below functions will initialize HC32 board.
|
||||
*/
|
||||
|
||||
#if defined RT_USING_SERIAL
|
||||
rt_err_t rt_hw_board_uart_init(CM_USART_TypeDef *USARTx)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
|
||||
switch ((rt_uint32_t)USARTx)
|
||||
{
|
||||
#if defined(BSP_USING_UART1)
|
||||
case (rt_uint32_t)CM_USART1:
|
||||
/* Configure USART RX/TX pin. */
|
||||
GPIO_SetFunc(USART1_RX_PORT, USART1_RX_PIN, USART1_RX_FUNC);
|
||||
GPIO_SetFunc(USART1_TX_PORT, USART1_TX_PIN, USART1_TX_FUNC);
|
||||
break;
|
||||
#endif
|
||||
#if defined(BSP_USING_UART6)
|
||||
case (rt_uint32_t)CM_USART6:
|
||||
/* Configure USART RX/TX pin. */
|
||||
GPIO_SetFunc(USART6_RX_PORT, USART6_RX_PIN, USART6_RX_FUNC);
|
||||
GPIO_SetFunc(USART6_TX_PORT, USART6_TX_PIN, USART6_TX_FUNC);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
result = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(RT_USING_I2C)
|
||||
rt_err_t rt_hw_board_i2c_init(CM_I2C_TypeDef *I2Cx)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
stc_gpio_init_t stcGpioInit;
|
||||
(void)GPIO_StructInit(&stcGpioInit);
|
||||
|
||||
switch ((rt_uint32_t)I2Cx)
|
||||
{
|
||||
#if defined(BSP_USING_I2C1)
|
||||
case (rt_uint32_t)CM_I2C1:
|
||||
/* Configure I2C1 SDA/SCL pin. */
|
||||
GPIO_SetFunc(I2C1_SDA_PORT, I2C1_SDA_PIN, I2C1_SDA_FUNC);
|
||||
GPIO_SetFunc(I2C1_SCL_PORT, I2C1_SCL_PIN, I2C1_SCL_FUNC);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
result = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(RT_USING_ADC)
|
||||
rt_err_t rt_hw_board_adc_init(CM_ADC_TypeDef *ADCx)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
stc_gpio_init_t stcGpioInit;
|
||||
|
||||
(void)GPIO_StructInit(&stcGpioInit);
|
||||
stcGpioInit.u16PinAttr = PIN_ATTR_ANALOG;
|
||||
switch ((rt_uint32_t)ADCx)
|
||||
{
|
||||
#if defined(BSP_USING_ADC1)
|
||||
case (rt_uint32_t)CM_ADC1:
|
||||
(void)GPIO_Init(ADC1_CH_PORT, ADC1_CH_PIN, &stcGpioInit);
|
||||
break;
|
||||
#endif
|
||||
#if defined(BSP_USING_ADC2)
|
||||
case (rt_uint32_t)CM_ADC2:
|
||||
(void)GPIO_Init(ADC2_CH_PORT, ADC2_CH_PIN, &stcGpioInit);
|
||||
break;
|
||||
#endif
|
||||
#if defined(BSP_USING_ADC3)
|
||||
case (rt_uint32_t)CM_ADC3:
|
||||
(void)GPIO_Init(ADC3_CH_PORT, ADC3_CH_PIN, &stcGpioInit);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
result = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(RT_USING_DAC)
|
||||
rt_err_t rt_hw_board_dac_init(CM_DAC_TypeDef *DACx)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
stc_gpio_init_t stcGpioInit;
|
||||
|
||||
(void)GPIO_StructInit(&stcGpioInit);
|
||||
stcGpioInit.u16PinAttr = PIN_ATTR_ANALOG;
|
||||
switch ((rt_uint32_t)DACx)
|
||||
{
|
||||
#if defined(BSP_USING_DAC1)
|
||||
case (rt_uint32_t)CM_DAC1:
|
||||
(void)GPIO_Init(DAC1_CH1_PORT, DAC1_CH1_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(DAC1_CH2_PORT, DAC1_CH2_PIN, &stcGpioInit);
|
||||
break;
|
||||
#endif
|
||||
#if defined(BSP_USING_DAC2)
|
||||
case (rt_uint32_t)CM_DAC2:
|
||||
(void)GPIO_Init(DAC2_CH1_PORT, DAC2_CH1_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(DAC2_CH2_PORT, DAC2_CH2_PIN, &stcGpioInit);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
result = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(RT_USING_CAN)
|
||||
void CanPhyEnable(void)
|
||||
{
|
||||
#if defined(BSP_USING_CAN1) || defined (BSP_USING_MCAN1)
|
||||
TCA9539_WritePin(CAN1_STB_PORT, CAN1_STB_PIN, TCA9539_PIN_SET);
|
||||
TCA9539_ConfigPin(CAN1_STB_PORT, CAN1_STB_PIN, TCA9539_DIR_OUT);
|
||||
TCA9539_WritePin(CAN1_STB_PORT, CAN1_STB_PIN, TCA9539_PIN_RESET);
|
||||
#endif
|
||||
#if defined(BSP_USING_CAN2) || defined (BSP_USING_MCAN2)
|
||||
TCA9539_WritePin(CAN2_STB_PORT, CAN2_STB_PIN, TCA9539_PIN_SET);
|
||||
TCA9539_ConfigPin(CAN2_STB_PORT, CAN2_STB_PIN, TCA9539_DIR_OUT);
|
||||
TCA9539_WritePin(CAN2_STB_PORT, CAN2_STB_PIN, TCA9539_PIN_RESET);
|
||||
#endif
|
||||
}
|
||||
#if defined(BSP_USING_CAN)
|
||||
rt_err_t rt_hw_board_can_init(CM_CAN_TypeDef *CANx)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
|
||||
switch ((rt_uint32_t)CANx)
|
||||
{
|
||||
#if defined(BSP_USING_CAN1)
|
||||
case (rt_uint32_t)CM_CAN1:
|
||||
GPIO_SetFunc(CAN1_TX_PORT, CAN1_TX_PIN, CAN1_TX_PIN_FUNC);
|
||||
GPIO_SetFunc(CAN1_RX_PORT, CAN1_RX_PIN, CAN1_RX_PIN_FUNC);
|
||||
break;
|
||||
#endif
|
||||
#if defined(BSP_USING_CAN2)
|
||||
case (rt_uint32_t)CM_CAN2:
|
||||
GPIO_SetFunc(CAN2_TX_PORT, CAN2_TX_PIN, CAN2_TX_PIN_FUNC);
|
||||
GPIO_SetFunc(CAN2_RX_PORT, CAN2_RX_PIN, CAN2_RX_PIN_FUNC);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
result = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
#if defined(BSP_USING_MCAN)
|
||||
rt_err_t rt_hw_board_mcan_init(CM_MCAN_TypeDef *MCANx)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
|
||||
switch ((rt_uint32_t)MCANx)
|
||||
{
|
||||
#if defined(BSP_USING_MCAN1)
|
||||
case (rt_uint32_t)CM_MCAN1:
|
||||
GPIO_SetFunc(MCAN1_TX_PORT, MCAN1_TX_PIN, MCAN1_TX_PIN_FUNC);
|
||||
GPIO_SetFunc(MCAN1_RX_PORT, MCAN1_RX_PIN, MCAN1_RX_PIN_FUNC);
|
||||
break;
|
||||
#endif
|
||||
#if defined(BSP_USING_MCAN2)
|
||||
case (rt_uint32_t)CM_MCAN2:
|
||||
GPIO_SetFunc(MCAN2_TX_PORT, MCAN2_TX_PIN, MCAN2_TX_PIN_FUNC);
|
||||
GPIO_SetFunc(MCAN2_RX_PORT, MCAN2_RX_PIN, MCAN2_RX_PIN_FUNC);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
result = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
#if defined (RT_USING_SPI)
|
||||
rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
#if defined(BSP_USING_SPI1)
|
||||
stc_gpio_init_t stcGpioInit;
|
||||
#endif
|
||||
|
||||
switch ((rt_uint32_t)CM_SPIx)
|
||||
{
|
||||
#if defined(BSP_USING_SPI1)
|
||||
case (rt_uint32_t)CM_SPI1:
|
||||
GPIO_StructInit(&stcGpioInit);
|
||||
stcGpioInit.u16PinState = PIN_STAT_SET;
|
||||
stcGpioInit.u16PinDir = PIN_DIR_OUT;
|
||||
GPIO_Init(SPI1_WP_PORT, SPI1_WP_PIN, &stcGpioInit);
|
||||
GPIO_Init(SPI1_HOLD_PORT, SPI1_HOLD_PIN, &stcGpioInit);
|
||||
|
||||
(void)GPIO_StructInit(&stcGpioInit);
|
||||
stcGpioInit.u16PinDrv = PIN_HIGH_DRV;
|
||||
stcGpioInit.u16PinInputType = PIN_IN_TYPE_CMOS;
|
||||
(void)GPIO_Init(SPI1_SCK_PORT, SPI1_SCK_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(SPI1_MOSI_PORT, SPI1_MOSI_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(SPI1_MISO_PORT, SPI1_MISO_PIN, &stcGpioInit);
|
||||
GPIO_SetFunc(SPI1_SCK_PORT, SPI1_SCK_PIN, SPI1_SCK_FUNC);
|
||||
GPIO_SetFunc(SPI1_MOSI_PORT, SPI1_MOSI_PIN, SPI1_MOSI_FUNC);
|
||||
GPIO_SetFunc(SPI1_MISO_PORT, SPI1_MISO_PIN, SPI1_MISO_FUNC);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
result = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_ETH)
|
||||
/* PHY hardware reset time */
|
||||
#define PHY_HW_RST_DELAY (0x40U)
|
||||
|
||||
rt_err_t rt_hw_eth_phy_reset(CM_ETH_TypeDef *CM_ETHx)
|
||||
{
|
||||
TCA9539_ConfigPin(TCA9539_IO_PORT1, EIO_ETH_RST, TCA9539_DIR_OUT);
|
||||
TCA9539_WritePin(TCA9539_IO_PORT1, EIO_ETH_RST, TCA9539_PIN_RESET);
|
||||
rt_thread_mdelay(PHY_HW_RST_DELAY);
|
||||
TCA9539_WritePin(TCA9539_IO_PORT1, EIO_ETH_RST, TCA9539_PIN_SET);
|
||||
rt_thread_mdelay(PHY_HW_RST_DELAY);
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
rt_err_t rt_hw_eth_board_init(CM_ETH_TypeDef *CM_ETHx)
|
||||
{
|
||||
#if defined(ETH_INTERFACE_USING_RMII)
|
||||
GPIO_SetFunc(ETH_SMI_MDIO_PORT, ETH_SMI_MDIO_PIN, ETH_SMI_MDIO_FUNC);
|
||||
GPIO_SetFunc(ETH_SMI_MDC_PORT, ETH_SMI_MDC_PIN, ETH_SMI_MDC_FUNC);
|
||||
GPIO_SetFunc(ETH_RMII_TX_EN_PORT, ETH_RMII_TX_EN_PIN, ETH_RMII_TX_EN_FUNC);
|
||||
GPIO_SetFunc(ETH_RMII_TXD0_PORT, ETH_RMII_TXD0_PIN, ETH_RMII_TXD0_FUNC);
|
||||
GPIO_SetFunc(ETH_RMII_TXD1_PORT, ETH_RMII_TXD1_PIN, ETH_RMII_TXD1_FUNC);
|
||||
GPIO_SetFunc(ETH_RMII_REF_CLK_PORT, ETH_RMII_REF_CLK_PIN, ETH_RMII_REF_CLK_FUNC);
|
||||
GPIO_SetFunc(ETH_RMII_CRS_DV_PORT, ETH_RMII_CRS_DV_PIN, ETH_RMII_CRS_DV_FUNC);
|
||||
GPIO_SetFunc(ETH_RMII_RXD0_PORT, ETH_RMII_RXD0_PIN, ETH_RMII_RXD0_FUNC);
|
||||
GPIO_SetFunc(ETH_RMII_RXD1_PORT, ETH_RMII_RXD1_PIN, ETH_RMII_RXD1_FUNC);
|
||||
#else
|
||||
GPIO_SetFunc(ETH_SMI_MDIO_PORT, ETH_SMI_MDIO_PIN, ETH_SMI_MDIO_FUNC);
|
||||
GPIO_SetFunc(ETH_SMI_MDC_PORT, ETH_SMI_MDC_PIN, ETH_SMI_MDC_FUNC);
|
||||
GPIO_SetFunc(ETH_MII_TX_CLK_PORT, ETH_MII_TX_CLK_PIN, ETH_MII_TX_CLK_FUNC);
|
||||
GPIO_SetFunc(ETH_MII_TX_EN_PORT, ETH_MII_TX_EN_PIN, ETH_MII_TX_EN_FUNC);
|
||||
GPIO_SetFunc(ETH_MII_TXD0_PORT, ETH_MII_TXD0_PIN, ETH_MII_TXD0_FUNC);
|
||||
GPIO_SetFunc(ETH_MII_TXD1_PORT, ETH_MII_TXD1_PIN, ETH_MII_TXD1_FUNC);
|
||||
GPIO_SetFunc(ETH_MII_TXD2_PORT, ETH_MII_TXD2_PIN, ETH_MII_TXD2_FUNC);
|
||||
GPIO_SetFunc(ETH_MII_TXD3_PORT, ETH_MII_TXD3_PIN, ETH_MII_TXD3_FUNC);
|
||||
GPIO_SetFunc(ETH_MII_RX_CLK_PORT, ETH_MII_RX_CLK_PIN, ETH_MII_RX_CLK_FUNC);
|
||||
GPIO_SetFunc(ETH_MII_RX_DV_PORT, ETH_MII_RX_DV_PIN, ETH_MII_RX_DV_FUNC);
|
||||
GPIO_SetFunc(ETH_MII_RXD0_PORT, ETH_MII_RXD0_PIN, ETH_MII_RXD0_FUNC);
|
||||
GPIO_SetFunc(ETH_MII_RXD1_PORT, ETH_MII_RXD1_PIN, ETH_MII_RXD1_FUNC);
|
||||
GPIO_SetFunc(ETH_MII_RXD2_PORT, ETH_MII_RXD2_PIN, ETH_MII_RXD2_FUNC);
|
||||
GPIO_SetFunc(ETH_MII_RXD3_PORT, ETH_MII_RXD3_PIN, ETH_MII_RXD3_FUNC);
|
||||
GPIO_SetFunc(ETH_MII_RX_ER_PORT, ETH_MII_RX_ER_PIN, ETH_MII_RX_ER_FUNC);
|
||||
GPIO_SetFunc(ETH_MII_CRS_PORT, ETH_MII_CRS_PIN, ETH_MII_CRS_FUNC);
|
||||
GPIO_SetFunc(ETH_MII_COL_PORT, ETH_MII_COL_PIN, ETH_MII_COL_FUNC);
|
||||
#endif
|
||||
return RT_EOK;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined (RT_USING_SDIO)
|
||||
rt_err_t rt_hw_board_sdio_init(CM_SDIOC_TypeDef *SDIOCx)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
stc_gpio_init_t stcGpioInit;
|
||||
|
||||
switch ((rt_uint32_t)SDIOCx)
|
||||
{
|
||||
#if defined(BSP_USING_SDIO1)
|
||||
case (rt_uint32_t)CM_SDIOC1:
|
||||
/************************* Set pin drive capacity *************************/
|
||||
(void)GPIO_StructInit(&stcGpioInit);
|
||||
stcGpioInit.u16PinDrv = PIN_HIGH_DRV;
|
||||
(void)GPIO_Init(SDIOC1_CK_PORT, SDIOC1_CK_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(SDIOC1_CMD_PORT, SDIOC1_CMD_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(SDIOC1_D0_PORT, SDIOC1_D0_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(SDIOC1_D1_PORT, SDIOC1_D1_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(SDIOC1_D2_PORT, SDIOC1_D2_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(SDIOC1_D3_PORT, SDIOC1_D3_PIN, &stcGpioInit);
|
||||
|
||||
GPIO_SetFunc(SDIOC1_CK_PORT, SDIOC1_CK_PIN, SDIOC1_CK_FUNC);
|
||||
GPIO_SetFunc(SDIOC1_CMD_PORT, SDIOC1_CMD_PIN, SDIOC1_CMD_FUNC);
|
||||
GPIO_SetFunc(SDIOC1_D0_PORT, SDIOC1_D0_PIN, SDIOC1_D0_FUNC);
|
||||
GPIO_SetFunc(SDIOC1_D1_PORT, SDIOC1_D1_PIN, SDIOC1_D1_FUNC);
|
||||
GPIO_SetFunc(SDIOC1_D2_PORT, SDIOC1_D2_PIN, SDIOC1_D2_FUNC);
|
||||
GPIO_SetFunc(SDIOC1_D3_PORT, SDIOC1_D3_PIN, SDIOC1_D3_FUNC);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
result = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(RT_USING_PWM)
|
||||
#if defined(BSP_USING_PWM_TMRA)
|
||||
rt_err_t rt_hw_board_pwm_tmra_init(CM_TMRA_TypeDef *TMRAx)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
switch ((rt_uint32_t)TMRAx)
|
||||
{
|
||||
#if defined(BSP_USING_PWM_TMRA_1)
|
||||
case (rt_uint32_t)CM_TMRA_1:
|
||||
#ifdef BSP_USING_PWM_TMRA_1_CH1
|
||||
GPIO_SetFunc(PWM_TMRA_1_CH1_PORT, PWM_TMRA_1_CH1_PIN, PWM_TMRA_1_CH1_PIN_FUNC);
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM_TMRA_1_CH2
|
||||
GPIO_SetFunc(PWM_TMRA_1_CH2_PORT, PWM_TMRA_1_CH2_PIN, PWM_TMRA_1_CH2_PIN_FUNC);
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM_TMRA_1_CH3
|
||||
GPIO_SetFunc(PWM_TMRA_1_CH3_PORT, PWM_TMRA_1_CH3_PIN, PWM_TMRA_1_CH3_PIN_FUNC);
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM_TMRA_1_CH4
|
||||
GPIO_SetFunc(PWM_TMRA_1_CH4_PORT, PWM_TMRA_1_CH4_PIN, PWM_TMRA_1_CH4_PIN_FUNC);
|
||||
#endif
|
||||
break;
|
||||
#endif
|
||||
|
||||
default:
|
||||
result = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_PWM_TMR4)
|
||||
rt_err_t rt_hw_board_pwm_tmr4_init(CM_TMR4_TypeDef *TMR4x)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
switch ((rt_uint32_t)TMR4x)
|
||||
{
|
||||
#if defined(BSP_USING_PWM_TMR4_1)
|
||||
case (rt_uint32_t)CM_TMR4_1:
|
||||
#ifdef BSP_USING_PWM_TMR4_1_OUH
|
||||
GPIO_SetFunc(PWM_TMR4_1_OUH_PORT, PWM_TMR4_1_OUH_PIN, PWM_TMR4_1_OUH_PIN_FUNC);
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM_TMR4_1_OUL
|
||||
GPIO_SetFunc(PWM_TMR4_1_OUL_PORT, PWM_TMR4_1_OUL_PIN, PWM_TMR4_1_OUL_PIN_FUNC);
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM_TMR4_1_OVH
|
||||
GPIO_SetFunc(PWM_TMR4_1_OVH_PORT, PWM_TMR4_1_OVH_PIN, PWM_TMR4_1_OVH_PIN_FUNC);
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM_TMR4_1_OVL
|
||||
GPIO_SetFunc(PWM_TMR4_1_OVL_PORT, PWM_TMR4_1_OVL_PIN, PWM_TMR4_1_OVL_PIN_FUNC);
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM_TMR4_1_OWH
|
||||
GPIO_SetFunc(PWM_TMR4_1_OWH_PORT, PWM_TMR4_1_OWH_PIN, PWM_TMR4_1_OWH_PIN_FUNC);
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM_TMR4_1_OWL
|
||||
GPIO_SetFunc(PWM_TMR4_1_OWL_PORT, PWM_TMR4_1_OWL_PIN, PWM_TMR4_1_OWL_PIN_FUNC);
|
||||
#endif
|
||||
break;
|
||||
#endif
|
||||
|
||||
default:
|
||||
result = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_PWM_TMR6)
|
||||
rt_err_t rt_hw_board_pwm_tmr6_init(CM_TMR6_TypeDef *TMR6x)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
switch ((rt_uint32_t)TMR6x)
|
||||
{
|
||||
#if defined(BSP_USING_PWM_TMR6_1)
|
||||
case (rt_uint32_t)CM_TMR6_1:
|
||||
#ifdef BSP_USING_PWM_TMR6_1_A
|
||||
GPIO_SetFunc(PWM_TMR6_1_A_PORT, PWM_TMR6_1_A_PIN, PWM_TMR6_1_A_PIN_FUNC);
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM_TMR6_1_B
|
||||
GPIO_SetFunc(PWM_TMR6_1_B_PORT, PWM_TMR6_1_B_PIN, PWM_TMR6_1_B_PIN_FUNC);
|
||||
#endif
|
||||
break;
|
||||
#endif
|
||||
|
||||
default:
|
||||
result = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined (BSP_USING_INPUT_CAPTURE)
|
||||
rt_err_t rt_hw_board_input_capture_init(uint32_t *tmr_instance)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
|
||||
switch ((rt_uint32_t)tmr_instance)
|
||||
{
|
||||
#if defined (BSP_USING_INPUT_CAPTURE_TMR6_1)
|
||||
case (rt_uint32_t)CM_TMR6_1:
|
||||
GPIO_SetFunc(INPUT_CAPTURE_TMR6_1_PORT, INPUT_CAPTURE_TMR6_1_PIN, INPUT_CAPTURE_TMR6_FUNC);
|
||||
break;
|
||||
#endif
|
||||
#if defined (BSP_USING_INPUT_CAPTURE_TMR6_2)
|
||||
case (rt_uint32_t)CM_TMR6_2:
|
||||
GPIO_SetFunc(INPUT_CAPTURE_TMR6_2_PORT, INPUT_CAPTURE_TMR6_2_PIN, INPUT_CAPTURE_TMR6_FUNC);
|
||||
break;
|
||||
#endif
|
||||
#if defined (BSP_USING_INPUT_CAPTURE_TMR6_3)
|
||||
case (rt_uint32_t)CM_TMR6_3:
|
||||
GPIO_SetFunc(INPUT_CAPTURE_TMR6_3_PORT, INPUT_CAPTURE_TMR6_3_PIN, INPUT_CAPTURE_TMR6_FUNC);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
result = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined (BSP_USING_SDRAM)
|
||||
rt_err_t rt_hw_board_sdram_init(void)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
stc_gpio_init_t stcGpioInit;
|
||||
|
||||
/************************* Set pin drive capacity *************************/
|
||||
(void)GPIO_StructInit(&stcGpioInit);
|
||||
stcGpioInit.u16PinDrv = PIN_HIGH_DRV;
|
||||
/* DMC_CKE */
|
||||
(void)GPIO_Init(SDRAM_CKE_PORT, SDRAM_CKE_PIN, &stcGpioInit);
|
||||
/* DMC_CLK */
|
||||
(void)GPIO_Init(SDRAM_CLK_PORT, SDRAM_CLK_PIN, &stcGpioInit);
|
||||
/* DMC_LDQM && DMC_UDQM */
|
||||
(void)GPIO_Init(SDRAM_DQM0_PORT, SDRAM_DQM0_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(SDRAM_DQM1_PORT, SDRAM_DQM1_PIN, &stcGpioInit);
|
||||
/* DMC_BA[0:1] */
|
||||
(void)GPIO_Init(SDRAM_BA0_PORT, SDRAM_BA0_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(SDRAM_BA1_PORT, SDRAM_BA1_PIN, &stcGpioInit);
|
||||
/* DMC_CAS && DMC_RAS */
|
||||
(void)GPIO_Init(SDRAM_CAS_PORT, SDRAM_CAS_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(SDRAM_RAS_PORT, SDRAM_RAS_PIN, &stcGpioInit);
|
||||
/* DMC_WE */
|
||||
(void)GPIO_Init(SDRAM_WE_PORT, SDRAM_WE_PIN, &stcGpioInit);
|
||||
/* DMC_DATA[0:15] */
|
||||
(void)GPIO_Init(SDRAM_DATA0_PORT, SDRAM_DATA0_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(SDRAM_DATA1_PORT, SDRAM_DATA1_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(SDRAM_DATA2_PORT, SDRAM_DATA2_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(SDRAM_DATA3_PORT, SDRAM_DATA3_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(SDRAM_DATA4_PORT, SDRAM_DATA4_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(SDRAM_DATA5_PORT, SDRAM_DATA5_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(SDRAM_DATA6_PORT, SDRAM_DATA6_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(SDRAM_DATA7_PORT, SDRAM_DATA7_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(SDRAM_DATA8_PORT, SDRAM_DATA8_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(SDRAM_DATA9_PORT, SDRAM_DATA9_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(SDRAM_DATA10_PORT, SDRAM_DATA10_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(SDRAM_DATA11_PORT, SDRAM_DATA11_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(SDRAM_DATA12_PORT, SDRAM_DATA12_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(SDRAM_DATA13_PORT, SDRAM_DATA13_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(SDRAM_DATA14_PORT, SDRAM_DATA14_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(SDRAM_DATA15_PORT, SDRAM_DATA15_PIN, &stcGpioInit);
|
||||
/* DMC_ADD[0:12]*/
|
||||
(void)GPIO_Init(SDRAM_ADD0_PORT, SDRAM_ADD0_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(SDRAM_ADD1_PORT, SDRAM_ADD1_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(SDRAM_ADD2_PORT, SDRAM_ADD2_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(SDRAM_ADD3_PORT, SDRAM_ADD3_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(SDRAM_ADD4_PORT, SDRAM_ADD4_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(SDRAM_ADD5_PORT, SDRAM_ADD5_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(SDRAM_ADD6_PORT, SDRAM_ADD6_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(SDRAM_ADD7_PORT, SDRAM_ADD7_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(SDRAM_ADD8_PORT, SDRAM_ADD8_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(SDRAM_ADD9_PORT, SDRAM_ADD9_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(SDRAM_ADD10_PORT, SDRAM_ADD10_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(SDRAM_ADD11_PORT, SDRAM_ADD11_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(SDRAM_ADD12_PORT, SDRAM_ADD12_PIN, &stcGpioInit);
|
||||
|
||||
/************************** Set EXMC pin function *************************/
|
||||
/* DMC_CKE */
|
||||
GPIO_SetFunc(SDRAM_CKE_PORT, SDRAM_CKE_PIN, SDRAM_CKE_FUNC);
|
||||
/* DMC_CLK */
|
||||
GPIO_SetFunc(SDRAM_CLK_PORT, SDRAM_CLK_PIN, SDRAM_CLK_FUNC);
|
||||
/* DMC_LDQM && DMC_UDQM */
|
||||
GPIO_SetFunc(SDRAM_DQM0_PORT, SDRAM_DQM0_PIN, SDRAM_DQM0_FUNC);
|
||||
GPIO_SetFunc(SDRAM_DQM1_PORT, SDRAM_DQM1_PIN, SDRAM_DQM1_FUNC);
|
||||
/* DMC_BA[0:1] */
|
||||
GPIO_SetFunc(SDRAM_BA0_PORT, SDRAM_BA0_PIN, SDRAM_BA0_FUNC);
|
||||
GPIO_SetFunc(SDRAM_BA1_PORT, SDRAM_BA1_PIN, SDRAM_BA1_FUNC);
|
||||
/* DMC_CS */
|
||||
GPIO_SetFunc(SDRAM_CS_PORT, SDRAM_CS_PIN, SDRAM_CS_FUNC);
|
||||
/* DMC_CAS && DMC_RAS */
|
||||
GPIO_SetFunc(SDRAM_CAS_PORT, SDRAM_CAS_PIN, SDRAM_CAS_FUNC);
|
||||
GPIO_SetFunc(SDRAM_RAS_PORT, SDRAM_RAS_PIN, SDRAM_RAS_FUNC);
|
||||
/* DMC_WE */
|
||||
GPIO_SetFunc(SDRAM_WE_PORT, SDRAM_WE_PIN, SDRAM_WE_FUNC);
|
||||
/* DMC_DATA[0:15] */
|
||||
GPIO_SetFunc(SDRAM_DATA0_PORT, SDRAM_DATA0_PIN, SDRAM_DATA0_FUNC);
|
||||
GPIO_SetFunc(SDRAM_DATA1_PORT, SDRAM_DATA1_PIN, SDRAM_DATA1_FUNC);
|
||||
GPIO_SetFunc(SDRAM_DATA2_PORT, SDRAM_DATA2_PIN, SDRAM_DATA2_FUNC);
|
||||
GPIO_SetFunc(SDRAM_DATA3_PORT, SDRAM_DATA3_PIN, SDRAM_DATA3_FUNC);
|
||||
GPIO_SetFunc(SDRAM_DATA4_PORT, SDRAM_DATA4_PIN, SDRAM_DATA4_FUNC);
|
||||
GPIO_SetFunc(SDRAM_DATA5_PORT, SDRAM_DATA5_PIN, SDRAM_DATA5_FUNC);
|
||||
GPIO_SetFunc(SDRAM_DATA6_PORT, SDRAM_DATA6_PIN, SDRAM_DATA6_FUNC);
|
||||
GPIO_SetFunc(SDRAM_DATA7_PORT, SDRAM_DATA7_PIN, SDRAM_DATA7_FUNC);
|
||||
GPIO_SetFunc(SDRAM_DATA8_PORT, SDRAM_DATA8_PIN, SDRAM_DATA8_FUNC);
|
||||
GPIO_SetFunc(SDRAM_DATA9_PORT, SDRAM_DATA9_PIN, SDRAM_DATA9_FUNC);
|
||||
GPIO_SetFunc(SDRAM_DATA10_PORT, SDRAM_DATA10_PIN, SDRAM_DATA10_FUNC);
|
||||
GPIO_SetFunc(SDRAM_DATA11_PORT, SDRAM_DATA11_PIN, SDRAM_DATA11_FUNC);
|
||||
GPIO_SetFunc(SDRAM_DATA12_PORT, SDRAM_DATA12_PIN, SDRAM_DATA12_FUNC);
|
||||
GPIO_SetFunc(SDRAM_DATA13_PORT, SDRAM_DATA13_PIN, SDRAM_DATA13_FUNC);
|
||||
GPIO_SetFunc(SDRAM_DATA14_PORT, SDRAM_DATA14_PIN, SDRAM_DATA14_FUNC);
|
||||
GPIO_SetFunc(SDRAM_DATA15_PORT, SDRAM_DATA15_PIN, SDRAM_DATA15_FUNC);
|
||||
/* DMC_ADD[0:12]*/
|
||||
GPIO_SetFunc(SDRAM_ADD0_PORT, SDRAM_ADD0_PIN, SDRAM_ADD0_FUNC);
|
||||
GPIO_SetFunc(SDRAM_ADD1_PORT, SDRAM_ADD1_PIN, SDRAM_ADD1_FUNC);
|
||||
GPIO_SetFunc(SDRAM_ADD2_PORT, SDRAM_ADD2_PIN, SDRAM_ADD2_FUNC);
|
||||
GPIO_SetFunc(SDRAM_ADD3_PORT, SDRAM_ADD3_PIN, SDRAM_ADD3_FUNC);
|
||||
GPIO_SetFunc(SDRAM_ADD4_PORT, SDRAM_ADD4_PIN, SDRAM_ADD4_FUNC);
|
||||
GPIO_SetFunc(SDRAM_ADD5_PORT, SDRAM_ADD5_PIN, SDRAM_ADD5_FUNC);
|
||||
GPIO_SetFunc(SDRAM_ADD6_PORT, SDRAM_ADD6_PIN, SDRAM_ADD6_FUNC);
|
||||
GPIO_SetFunc(SDRAM_ADD7_PORT, SDRAM_ADD7_PIN, SDRAM_ADD7_FUNC);
|
||||
GPIO_SetFunc(SDRAM_ADD8_PORT, SDRAM_ADD8_PIN, SDRAM_ADD8_FUNC);
|
||||
GPIO_SetFunc(SDRAM_ADD9_PORT, SDRAM_ADD9_PIN, SDRAM_ADD9_FUNC);
|
||||
GPIO_SetFunc(SDRAM_ADD10_PORT, SDRAM_ADD10_PIN, SDRAM_ADD10_FUNC);
|
||||
GPIO_SetFunc(SDRAM_ADD11_PORT, SDRAM_ADD11_PIN, SDRAM_ADD11_FUNC);
|
||||
GPIO_SetFunc(SDRAM_ADD12_PORT, SDRAM_ADD12_PIN, SDRAM_ADD12_FUNC);
|
||||
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_PM
|
||||
void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode)
|
||||
{
|
||||
switch (run_mode)
|
||||
{
|
||||
case PM_RUN_MODE_HIGH_SPEED:
|
||||
case PM_RUN_MODE_NORMAL_SPEED:
|
||||
CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL);
|
||||
break;
|
||||
|
||||
case PM_RUN_MODE_LOW_SPEED:
|
||||
/* Ensure that system clock less than 8M */
|
||||
CLK_SetSysClockSrc(CLK_SYSCLK_SRC_XTAL);
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_USBFS)
|
||||
rt_err_t rt_hw_usbfs_board_init(void)
|
||||
{
|
||||
stc_gpio_init_t stcGpioCfg;
|
||||
(void)GPIO_StructInit(&stcGpioCfg);
|
||||
|
||||
stcGpioCfg.u16PinAttr = PIN_ATTR_ANALOG;
|
||||
(void)GPIO_Init(USBF_DM_PORT, USBF_DM_PIN, &stcGpioCfg);
|
||||
(void)GPIO_Init(USBF_DP_PORT, USBF_DP_PIN, &stcGpioCfg);
|
||||
#if defined(BSP_USING_USBD_FS)
|
||||
GPIO_SetFunc(USBF_VBUS_PORT, USBF_VBUS_PIN, USBF_VBUS_FUNC); /* VBUS */
|
||||
#endif
|
||||
#if defined(BSP_USING_USBH_FS)
|
||||
GPIO_SetFunc(USBF_DRVVBUS_PORT, USBF_DRVVBUS_PIN, USBF_DRVVBUS_FUNC); /* DRV VBUS */
|
||||
#endif
|
||||
return RT_EOK;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_USBHS)
|
||||
rt_err_t rt_hw_usbhs_board_init(void)
|
||||
{
|
||||
stc_gpio_init_t stcGpioCfg;
|
||||
(void)GPIO_StructInit(&stcGpioCfg);
|
||||
|
||||
#if defined(BSP_USING_USBHS_PHY_EMBED)
|
||||
/* USBHS work in embedded PHY */
|
||||
stcGpioCfg.u16PinAttr = PIN_ATTR_ANALOG;
|
||||
(void)GPIO_Init(USBH_DM_PORT, USBH_DM_PIN, &stcGpioCfg);
|
||||
(void)GPIO_Init(USBH_DP_PORT, USBH_DP_PIN, &stcGpioCfg);
|
||||
#if defined(BSP_USING_USBD_HS)
|
||||
GPIO_SetFunc(USBH_VBUS_PORT, USBH_VBUS_PIN, USBH_VBUS_FUNC);
|
||||
#endif
|
||||
#if defined(BSP_USING_USBH_HS)
|
||||
GPIO_OutputCmd(USBH_DRVVBUS_PORT, USBH_DRVVBUS_PIN, ENABLE);
|
||||
GPIO_SetPins(USBH_DRVVBUS_PORT, USBH_DRVVBUS_PIN); /* DRV VBUS with GPIO funciton */
|
||||
#endif
|
||||
#else
|
||||
/* Reset 3300 */
|
||||
TCA9539_WritePin(TCA9539_IO_PORT1, USB_3300_RESET_PIN, TCA9539_PIN_SET);
|
||||
TCA9539_ConfigPin(TCA9539_IO_PORT1, USB_3300_RESET_PIN, TCA9539_DIR_OUT);
|
||||
|
||||
(void)GPIO_StructInit(&stcGpioCfg);
|
||||
/* High drive capability */
|
||||
stcGpioCfg.u16PinDrv = PIN_HIGH_DRV;
|
||||
(void)GPIO_Init(USBH_ULPI_D0_PORT, USBH_ULPI_D0_PIN, &stcGpioCfg);
|
||||
(void)GPIO_Init(USBH_ULPI_D1_PORT, USBH_ULPI_D1_PIN, &stcGpioCfg);
|
||||
(void)GPIO_Init(USBH_ULPI_D2_PORT, USBH_ULPI_D2_PIN, &stcGpioCfg);
|
||||
(void)GPIO_Init(USBH_ULPI_D3_PORT, USBH_ULPI_D3_PIN, &stcGpioCfg);
|
||||
(void)GPIO_Init(USBH_ULPI_D4_PORT, USBH_ULPI_D4_PIN, &stcGpioCfg);
|
||||
(void)GPIO_Init(USBH_ULPI_D5_PORT, USBH_ULPI_D5_PIN, &stcGpioCfg);
|
||||
(void)GPIO_Init(USBH_ULPI_D6_PORT, USBH_ULPI_D6_PIN, &stcGpioCfg);
|
||||
(void)GPIO_Init(USBH_ULPI_D7_PORT, USBH_ULPI_D7_PIN, &stcGpioCfg);
|
||||
(void)GPIO_Init(USBH_ULPI_STP_PORT, USBH_ULPI_STP_PIN, &stcGpioCfg);
|
||||
|
||||
GPIO_SetFunc(USBH_ULPI_CLK_PORT, USBH_ULPI_CLK_PIN, USBH_ULPI_CLK_FUNC);
|
||||
GPIO_SetFunc(USBH_ULPI_DIR_PORT, USBH_ULPI_DIR_PIN, USBH_ULPI_DIR_FUNC);
|
||||
GPIO_SetFunc(USBH_ULPI_NXT_PORT, USBH_ULPI_NXT_PIN, USBH_ULPI_NXT_FUNC);
|
||||
GPIO_SetFunc(USBH_ULPI_STP_PORT, USBH_ULPI_STP_PIN, USBH_ULPI_STP_FUNC);
|
||||
GPIO_SetFunc(USBH_ULPI_D0_PORT, USBH_ULPI_D0_PIN, USBH_ULPI_D0_FUNC);
|
||||
GPIO_SetFunc(USBH_ULPI_D1_PORT, USBH_ULPI_D1_PIN, USBH_ULPI_D1_FUNC);
|
||||
GPIO_SetFunc(USBH_ULPI_D2_PORT, USBH_ULPI_D2_PIN, USBH_ULPI_D2_FUNC);
|
||||
GPIO_SetFunc(USBH_ULPI_D3_PORT, USBH_ULPI_D3_PIN, USBH_ULPI_D3_FUNC);
|
||||
GPIO_SetFunc(USBH_ULPI_D4_PORT, USBH_ULPI_D4_PIN, USBH_ULPI_D4_FUNC);
|
||||
GPIO_SetFunc(USBH_ULPI_D5_PORT, USBH_ULPI_D5_PIN, USBH_ULPI_D5_FUNC);
|
||||
GPIO_SetFunc(USBH_ULPI_D6_PORT, USBH_ULPI_D6_PIN, USBH_ULPI_D6_FUNC);
|
||||
GPIO_SetFunc(USBH_ULPI_D7_PORT, USBH_ULPI_D7_PIN, USBH_ULPI_D7_FUNC);
|
||||
|
||||
TCA9539_WritePin(TCA9539_IO_PORT1, USB_3300_RESET_PIN, TCA9539_PIN_RESET);
|
||||
#endif
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_QSPI)
|
||||
rt_err_t rt_hw_qspi_board_init(void)
|
||||
{
|
||||
stc_gpio_init_t stcGpioInit;
|
||||
|
||||
(void)GPIO_StructInit(&stcGpioInit);
|
||||
stcGpioInit.u16PinDrv = PIN_HIGH_DRV;
|
||||
#ifndef BSP_QSPI_USING_SOFT_CS
|
||||
(void)GPIO_Init(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, &stcGpioInit);
|
||||
GPIO_SetFunc(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, QSPI_FLASH_CS_FUNC);
|
||||
#endif
|
||||
(void)GPIO_Init(QSPI_FLASH_SCK_PORT, QSPI_FLASH_SCK_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(QSPI_FLASH_IO0_PORT, QSPI_FLASH_IO0_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(QSPI_FLASH_IO1_PORT, QSPI_FLASH_IO1_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(QSPI_FLASH_IO2_PORT, QSPI_FLASH_IO2_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(QSPI_FLASH_IO3_PORT, QSPI_FLASH_IO3_PIN, &stcGpioInit);
|
||||
GPIO_SetFunc(QSPI_FLASH_SCK_PORT, QSPI_FLASH_SCK_PIN, QSPI_FLASH_SCK_FUNC);
|
||||
GPIO_SetFunc(QSPI_FLASH_IO0_PORT, QSPI_FLASH_IO0_PIN, QSPI_FLASH_IO0_FUNC);
|
||||
GPIO_SetFunc(QSPI_FLASH_IO1_PORT, QSPI_FLASH_IO1_PIN, QSPI_FLASH_IO1_FUNC);
|
||||
GPIO_SetFunc(QSPI_FLASH_IO2_PORT, QSPI_FLASH_IO2_PIN, QSPI_FLASH_IO2_FUNC);
|
||||
GPIO_SetFunc(QSPI_FLASH_IO3_PORT, QSPI_FLASH_IO3_PIN, QSPI_FLASH_IO3_FUNC);
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_TMRA_PULSE_ENCODER)
|
||||
rt_err_t rt_hw_board_pulse_encoder_tmra_init(void)
|
||||
{
|
||||
#if defined(BSP_USING_PULSE_ENCODER_TMRA_1)
|
||||
GPIO_SetFunc(PULSE_ENCODER_TMRA_1_A_PORT, PULSE_ENCODER_TMRA_1_A_PIN, PULSE_ENCODER_TMRA_1_A_PIN_FUNC);
|
||||
GPIO_SetFunc(PULSE_ENCODER_TMRA_1_B_PORT, PULSE_ENCODER_TMRA_1_B_PIN, PULSE_ENCODER_TMRA_1_B_PIN_FUNC);
|
||||
#endif
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_TMR6_PULSE_ENCODER)
|
||||
rt_err_t rt_hw_board_pulse_encoder_tmr6_init(void)
|
||||
{
|
||||
#if defined(BSP_USING_PULSE_ENCODER_TMR6_1)
|
||||
GPIO_SetFunc(PULSE_ENCODER_TMR6_1_A_PORT, PULSE_ENCODER_TMR6_1_A_PIN, PULSE_ENCODER_TMR6_1_A_PIN_FUNC);
|
||||
GPIO_SetFunc(PULSE_ENCODER_TMR6_1_B_PORT, PULSE_ENCODER_TMR6_1_B_PIN, PULSE_ENCODER_TMR6_1_B_PIN_FUNC);
|
||||
#endif
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined (BSP_USING_NAND)
|
||||
rt_err_t rt_hw_board_nand_init(void)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
stc_gpio_init_t stcGpioInit;
|
||||
|
||||
/************************* Set pin drive capacity *************************/
|
||||
(void)GPIO_StructInit(&stcGpioInit);
|
||||
stcGpioInit.u16PinDrv = PIN_HIGH_DRV;
|
||||
|
||||
/* NFC_CE */
|
||||
(void)GPIO_Init(NAND_CE_PORT, NAND_CE_PIN, &stcGpioInit);
|
||||
/* NFC_RE */
|
||||
(void)GPIO_Init(NAND_RE_PORT, NAND_RE_PIN, &stcGpioInit);
|
||||
/* NFC_WE */
|
||||
(void)GPIO_Init(NAND_WE_PORT, NAND_WE_PIN, &stcGpioInit);
|
||||
/* NFC_CLE */
|
||||
(void)GPIO_Init(NAND_CLE_PORT, NAND_CLE_PIN, &stcGpioInit);
|
||||
/* NFC_ALE */
|
||||
(void)GPIO_Init(NAND_ALE_PORT, NAND_ALE_PIN, &stcGpioInit);
|
||||
/* NFC_WP */
|
||||
(void)GPIO_Init(NAND_WP_PORT, NAND_WP_PIN, &stcGpioInit);
|
||||
GPIO_SetPins(NAND_WP_PORT, NAND_WP_PIN);
|
||||
|
||||
/* NFC_DATA[0:7] */
|
||||
(void)GPIO_Init(NAND_DATA0_PORT, NAND_DATA0_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(NAND_DATA1_PORT, NAND_DATA1_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(NAND_DATA2_PORT, NAND_DATA2_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(NAND_DATA3_PORT, NAND_DATA3_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(NAND_DATA4_PORT, NAND_DATA4_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(NAND_DATA5_PORT, NAND_DATA5_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(NAND_DATA6_PORT, NAND_DATA6_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(NAND_DATA7_PORT, NAND_DATA7_PIN, &stcGpioInit);
|
||||
/* NFC_RB */
|
||||
(void)GPIO_Init(NAND_RB_PORT, NAND_RB_PIN, &stcGpioInit);
|
||||
|
||||
/************************** Set EXMC pin function *************************/
|
||||
/* NFC_CE */
|
||||
GPIO_SetFunc(NAND_CE_PORT, NAND_CE_PIN, NAND_CE_FUNC);
|
||||
/* NFC_RE */
|
||||
GPIO_SetFunc(NAND_RE_PORT, NAND_RE_PIN, NAND_RE_FUNC);
|
||||
/* NFC_WE */
|
||||
GPIO_SetFunc(NAND_WE_PORT, NAND_WE_PIN, NAND_WE_FUNC);
|
||||
/* NFC_CLE */
|
||||
GPIO_SetFunc(NAND_CLE_PORT, NAND_CLE_PIN, NAND_CLE_FUNC);
|
||||
/* NFC_ALE */
|
||||
GPIO_SetFunc(NAND_ALE_PORT, NAND_ALE_PIN, NAND_ALE_FUNC);
|
||||
/* NFC_WP */
|
||||
GPIO_SetFunc(NAND_WP_PORT, NAND_WP_PIN, NAND_WP_FUNC);
|
||||
/* NFC_RB */
|
||||
GPIO_SetFunc(NAND_RB_PORT, NAND_RB_PIN, NAND_RB_FUNC);
|
||||
/* NFC_DATA[0:7] */
|
||||
GPIO_SetFunc(NAND_DATA0_PORT, NAND_DATA0_PIN, NAND_DATA0_FUNC);
|
||||
GPIO_SetFunc(NAND_DATA1_PORT, NAND_DATA1_PIN, NAND_DATA1_FUNC);
|
||||
GPIO_SetFunc(NAND_DATA2_PORT, NAND_DATA2_PIN, NAND_DATA2_FUNC);
|
||||
GPIO_SetFunc(NAND_DATA3_PORT, NAND_DATA3_PIN, NAND_DATA3_FUNC);
|
||||
GPIO_SetFunc(NAND_DATA4_PORT, NAND_DATA4_PIN, NAND_DATA4_FUNC);
|
||||
GPIO_SetFunc(NAND_DATA5_PORT, NAND_DATA5_PIN, NAND_DATA5_FUNC);
|
||||
GPIO_SetFunc(NAND_DATA6_PORT, NAND_DATA6_PIN, NAND_DATA6_FUNC);
|
||||
GPIO_SetFunc(NAND_DATA7_PORT, NAND_DATA7_PIN, NAND_DATA7_FUNC);
|
||||
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,717 @@
|
|||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
|
||||
#ifndef __BOARD_CONFIG_H__
|
||||
#define __BOARD_CONFIG_H__
|
||||
|
||||
#include <rtconfig.h>
|
||||
#include "hc32_ll.h"
|
||||
#include "drv_config.h"
|
||||
|
||||
|
||||
/************************* XTAL port **********************/
|
||||
#define XTAL_PORT (GPIO_PORT_H)
|
||||
#define XTAL_IN_PIN (GPIO_PIN_01)
|
||||
#define XTAL_OUT_PIN (GPIO_PIN_00)
|
||||
|
||||
/************************ USART port **********************/
|
||||
#if defined(BSP_USING_UART1)
|
||||
#define USART1_RX_PORT (GPIO_PORT_H)
|
||||
#define USART1_RX_PIN (GPIO_PIN_13)
|
||||
#define USART1_RX_FUNC (GPIO_FUNC_33)
|
||||
|
||||
#define USART1_TX_PORT (GPIO_PORT_H)
|
||||
#define USART1_TX_PIN (GPIO_PIN_15)
|
||||
#define USART1_TX_FUNC (GPIO_FUNC_32)
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_UART6)
|
||||
#define USART6_RX_PORT (GPIO_PORT_D)
|
||||
#define USART6_RX_PIN (GPIO_PIN_06)
|
||||
#define USART6_RX_FUNC (GPIO_FUNC_37)
|
||||
|
||||
#define USART6_TX_PORT (GPIO_PORT_E)
|
||||
#define USART6_TX_PIN (GPIO_PIN_06)
|
||||
#define USART6_TX_FUNC (GPIO_FUNC_36)
|
||||
#endif
|
||||
|
||||
/************************ I2C port **********************/
|
||||
#if defined(BSP_USING_I2C1)
|
||||
#define I2C1_SDA_PORT (GPIO_PORT_F)
|
||||
#define I2C1_SDA_PIN (GPIO_PIN_10)
|
||||
#define I2C1_SDA_FUNC (GPIO_FUNC_48)
|
||||
|
||||
#define I2C1_SCL_PORT (GPIO_PORT_D)
|
||||
#define I2C1_SCL_PIN (GPIO_PIN_03)
|
||||
#define I2C1_SCL_FUNC (GPIO_FUNC_49)
|
||||
#endif
|
||||
|
||||
/*********** ADC configure *********/
|
||||
#if defined(BSP_USING_ADC1)
|
||||
#define ADC1_CH_PORT (GPIO_PORT_C) /* Default ADC123_IN10 */
|
||||
#define ADC1_CH_PIN (GPIO_PIN_00)
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_ADC2)
|
||||
#define ADC2_CH_PORT (GPIO_PORT_C) /* Default ADC123_IN11 */
|
||||
#define ADC2_CH_PIN (GPIO_PIN_01)
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_ADC3)
|
||||
#define ADC3_CH_PORT (GPIO_PORT_C) /* Default ADC123_IN12 */
|
||||
#define ADC3_CH_PIN (GPIO_PIN_02)
|
||||
#endif
|
||||
|
||||
/*********** DAC configure *********/
|
||||
#if defined(BSP_USING_DAC1)
|
||||
#define DAC1_CH1_PORT (GPIO_PORT_A)
|
||||
#define DAC1_CH1_PIN (GPIO_PIN_04)
|
||||
#define DAC1_CH2_PORT (GPIO_PORT_A)
|
||||
#define DAC1_CH2_PIN (GPIO_PIN_05)
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_DAC2)
|
||||
#define DAC2_CH1_PORT (GPIO_PORT_C)
|
||||
#define DAC2_CH1_PIN (GPIO_PIN_04)
|
||||
#define DAC2_CH2_PORT (GPIO_PORT_C)
|
||||
#define DAC2_CH2_PIN (GPIO_PIN_05)
|
||||
#endif
|
||||
|
||||
/*********** CAN/MCAN configure *********/
|
||||
#if defined(BSP_USING_CAN1)
|
||||
#define CAN1_TX_PORT (GPIO_PORT_I)
|
||||
#define CAN1_TX_PIN (GPIO_PIN_12)
|
||||
#define CAN1_TX_PIN_FUNC (GPIO_FUNC_60)
|
||||
|
||||
#define CAN1_RX_PORT (GPIO_PORT_G)
|
||||
#define CAN1_RX_PIN (GPIO_PIN_07)
|
||||
#define CAN1_RX_PIN_FUNC (GPIO_FUNC_61)
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_CAN2)
|
||||
#define CAN2_TX_PORT (GPIO_PORT_G)
|
||||
#define CAN2_TX_PIN (GPIO_PIN_09)
|
||||
#define CAN2_TX_PIN_FUNC (GPIO_FUNC_62)
|
||||
|
||||
#define CAN2_RX_PORT (GPIO_PORT_I)
|
||||
#define CAN2_RX_PIN (GPIO_PIN_03)
|
||||
#define CAN2_RX_PIN_FUNC (GPIO_FUNC_63)
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_MCAN1)
|
||||
#define MCAN1_TX_PORT (GPIO_PORT_I)
|
||||
#define MCAN1_TX_PIN (GPIO_PIN_12)
|
||||
#define MCAN1_TX_PIN_FUNC (GPIO_FUNC_28)
|
||||
|
||||
#define MCAN1_RX_PORT (GPIO_PORT_G)
|
||||
#define MCAN1_RX_PIN (GPIO_PIN_07)
|
||||
#define MCAN1_RX_PIN_FUNC (GPIO_FUNC_29)
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_MCAN2)
|
||||
#define MCAN2_TX_PORT (GPIO_PORT_G)
|
||||
#define MCAN2_TX_PIN (GPIO_PIN_09)
|
||||
#define MCAN2_TX_PIN_FUNC (GPIO_FUNC_30)
|
||||
|
||||
#define MCAN2_RX_PORT (GPIO_PORT_I)
|
||||
#define MCAN2_RX_PIN (GPIO_PIN_03)
|
||||
#define MCAN2_RX_PIN_FUNC (GPIO_FUNC_31)
|
||||
#endif
|
||||
|
||||
/************************* SPI port ***********************/
|
||||
#if defined(BSP_USING_SPI1)
|
||||
#define SPI1_CS_PORT (GPIO_PORT_C)
|
||||
#define SPI1_CS_PIN (GPIO_PIN_07)
|
||||
|
||||
#define SPI1_SCK_PORT (GPIO_PORT_C)
|
||||
#define SPI1_SCK_PIN (GPIO_PIN_06)
|
||||
#define SPI1_SCK_FUNC (GPIO_FUNC_40)
|
||||
|
||||
#define SPI1_MOSI_PORT (GPIO_PORT_B)
|
||||
#define SPI1_MOSI_PIN (GPIO_PIN_13)
|
||||
#define SPI1_MOSI_FUNC (GPIO_FUNC_41)
|
||||
|
||||
#define SPI1_MISO_PORT (GPIO_PORT_B)
|
||||
#define SPI1_MISO_PIN (GPIO_PIN_12)
|
||||
#define SPI1_MISO_FUNC (GPIO_FUNC_42)
|
||||
|
||||
#define SPI1_WP_PORT (GPIO_PORT_B)
|
||||
#define SPI1_WP_PIN (GPIO_PIN_10)
|
||||
|
||||
#define SPI1_HOLD_PORT (GPIO_PORT_B)
|
||||
#define SPI1_HOLD_PIN (GPIO_PIN_02)
|
||||
#endif
|
||||
|
||||
/************************* ETH port ***********************/
|
||||
|
||||
#if defined(BSP_USING_ETH)
|
||||
#if defined(ETH_INTERFACE_USING_RMII)
|
||||
#define ETH_SMI_MDIO_PORT (GPIO_PORT_A)
|
||||
#define ETH_SMI_MDIO_PIN (GPIO_PIN_02)
|
||||
#define ETH_SMI_MDIO_FUNC (GPIO_FUNC_11)
|
||||
|
||||
#define ETH_SMI_MDC_PORT (GPIO_PORT_C)
|
||||
#define ETH_SMI_MDC_PIN (GPIO_PIN_01)
|
||||
#define ETH_SMI_MDC_FUNC (GPIO_FUNC_11)
|
||||
|
||||
#define ETH_RMII_TX_EN_PORT (GPIO_PORT_G)
|
||||
#define ETH_RMII_TX_EN_PIN (GPIO_PIN_11)
|
||||
#define ETH_RMII_TX_EN_FUNC (GPIO_FUNC_11)
|
||||
|
||||
#define ETH_RMII_TXD0_PORT (GPIO_PORT_G)
|
||||
#define ETH_RMII_TXD0_PIN (GPIO_PIN_13)
|
||||
#define ETH_RMII_TXD0_FUNC (GPIO_FUNC_11)
|
||||
|
||||
#define ETH_RMII_TXD1_PORT (GPIO_PORT_G)
|
||||
#define ETH_RMII_TXD1_PIN (GPIO_PIN_14)
|
||||
#define ETH_RMII_TXD1_FUNC (GPIO_FUNC_11)
|
||||
|
||||
#define ETH_RMII_REF_CLK_PORT (GPIO_PORT_A)
|
||||
#define ETH_RMII_REF_CLK_PIN (GPIO_PIN_01)
|
||||
#define ETH_RMII_REF_CLK_FUNC (GPIO_FUNC_11)
|
||||
|
||||
#define ETH_RMII_CRS_DV_PORT (GPIO_PORT_A)
|
||||
#define ETH_RMII_CRS_DV_PIN (GPIO_PIN_07)
|
||||
#define ETH_RMII_CRS_DV_FUNC (GPIO_FUNC_11)
|
||||
|
||||
#define ETH_RMII_RXD0_PORT (GPIO_PORT_C)
|
||||
#define ETH_RMII_RXD0_PIN (GPIO_PIN_04)
|
||||
#define ETH_RMII_RXD0_FUNC (GPIO_FUNC_11)
|
||||
|
||||
#define ETH_RMII_RXD1_PORT (GPIO_PORT_C)
|
||||
#define ETH_RMII_RXD1_PIN (GPIO_PIN_05)
|
||||
#define ETH_RMII_RXD1_FUNC (GPIO_FUNC_11)
|
||||
#else
|
||||
#define ETH_SMI_MDIO_PORT (GPIO_PORT_A)
|
||||
#define ETH_SMI_MDIO_PIN (GPIO_PIN_02)
|
||||
#define ETH_SMI_MDIO_FUNC (GPIO_FUNC_11)
|
||||
|
||||
#define ETH_SMI_MDC_PORT (GPIO_PORT_C)
|
||||
#define ETH_SMI_MDC_PIN (GPIO_PIN_01)
|
||||
#define ETH_SMI_MDC_FUNC (GPIO_FUNC_11)
|
||||
|
||||
#define ETH_MII_TX_CLK_PORT (GPIO_PORT_B)
|
||||
#define ETH_MII_TX_CLK_PIN (GPIO_PIN_06)
|
||||
#define ETH_MII_TX_CLK_FUNC (GPIO_FUNC_11)
|
||||
|
||||
#define ETH_MII_TX_EN_PORT (GPIO_PORT_G)
|
||||
#define ETH_MII_TX_EN_PIN (GPIO_PIN_11)
|
||||
#define ETH_MII_TX_EN_FUNC (GPIO_FUNC_11)
|
||||
|
||||
#define ETH_MII_TXD0_PORT (GPIO_PORT_G)
|
||||
#define ETH_MII_TXD0_PIN (GPIO_PIN_13)
|
||||
#define ETH_MII_TXD0_FUNC (GPIO_FUNC_11)
|
||||
|
||||
#define ETH_MII_TXD1_PORT (GPIO_PORT_G)
|
||||
#define ETH_MII_TXD1_PIN (GPIO_PIN_14)
|
||||
#define ETH_MII_TXD1_FUNC (GPIO_FUNC_11)
|
||||
|
||||
#define ETH_MII_TXD2_PORT (GPIO_PORT_B)
|
||||
#define ETH_MII_TXD2_PIN (GPIO_PIN_09)
|
||||
#define ETH_MII_TXD2_FUNC (GPIO_FUNC_11)
|
||||
|
||||
#define ETH_MII_TXD3_PORT (GPIO_PORT_B)
|
||||
#define ETH_MII_TXD3_PIN (GPIO_PIN_08)
|
||||
#define ETH_MII_TXD3_FUNC (GPIO_FUNC_11)
|
||||
|
||||
#define ETH_MII_RX_CLK_PORT (GPIO_PORT_A)
|
||||
#define ETH_MII_RX_CLK_PIN (GPIO_PIN_01)
|
||||
#define ETH_MII_RX_CLK_FUNC (GPIO_FUNC_11)
|
||||
|
||||
#define ETH_MII_RX_DV_PORT (GPIO_PORT_A)
|
||||
#define ETH_MII_RX_DV_PIN (GPIO_PIN_07)
|
||||
#define ETH_MII_RX_DV_FUNC (GPIO_FUNC_11)
|
||||
|
||||
#define ETH_MII_RXD0_PORT (GPIO_PORT_C)
|
||||
#define ETH_MII_RXD0_PIN (GPIO_PIN_04)
|
||||
#define ETH_MII_RXD0_FUNC (GPIO_FUNC_11)
|
||||
|
||||
#define ETH_MII_RXD1_PORT (GPIO_PORT_C)
|
||||
#define ETH_MII_RXD1_PIN (GPIO_PIN_05)
|
||||
#define ETH_MII_RXD1_FUNC (GPIO_FUNC_11)
|
||||
|
||||
#define ETH_MII_RXD2_PORT (GPIO_PORT_B)
|
||||
#define ETH_MII_RXD2_PIN (GPIO_PIN_00)
|
||||
#define ETH_MII_RXD2_FUNC (GPIO_FUNC_11)
|
||||
|
||||
#define ETH_MII_RXD3_PORT (GPIO_PORT_B)
|
||||
#define ETH_MII_RXD3_PIN (GPIO_PIN_01)
|
||||
#define ETH_MII_RXD3_FUNC (GPIO_FUNC_11)
|
||||
|
||||
#define ETH_MII_RX_ER_PORT (GPIO_PORT_I)
|
||||
#define ETH_MII_RX_ER_PIN (GPIO_PIN_10)
|
||||
#define ETH_MII_RX_ER_FUNC (GPIO_FUNC_11)
|
||||
|
||||
#define ETH_MII_CRS_PORT (GPIO_PORT_H)
|
||||
#define ETH_MII_CRS_PIN (GPIO_PIN_02)
|
||||
#define ETH_MII_CRS_FUNC (GPIO_FUNC_11)
|
||||
|
||||
#define ETH_MII_COL_PORT (GPIO_PORT_H)
|
||||
#define ETH_MII_COL_PIN (GPIO_PIN_03)
|
||||
#define ETH_MII_COL_FUNC (GPIO_FUNC_11)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/************************ NAND port **********************/
|
||||
#if defined(BSP_USING_NAND)
|
||||
#define NAND_CE_PORT (GPIO_PORT_D) /* PD07 - EXMC_SMC_NFC_CS0 */
|
||||
#define NAND_CE_PIN (GPIO_PIN_07)
|
||||
#define NAND_CE_FUNC (GPIO_FUNC_21)
|
||||
|
||||
#define NAND_RE_PORT (GPIO_PORT_D) /* PD04 - EXMC_SMC_OE_NFC_RE */
|
||||
#define NAND_RE_PIN (GPIO_PIN_04)
|
||||
#define NAND_RE_FUNC (GPIO_FUNC_21)
|
||||
|
||||
#define NAND_WE_PORT (GPIO_PORT_D) /* PD05 - EXMC_SMC_NFC_WE */
|
||||
#define NAND_WE_PIN (GPIO_PIN_05)
|
||||
#define NAND_WE_FUNC (GPIO_FUNC_21)
|
||||
|
||||
#define NAND_CLE_PORT (GPIO_PORT_D) /* PD11 - EXMC_ADD16_DMC_BA0_NFC_CLE */
|
||||
#define NAND_CLE_PIN (GPIO_PIN_11)
|
||||
#define NAND_CLE_FUNC (GPIO_FUNC_21)
|
||||
|
||||
#define NAND_ALE_PORT (GPIO_PORT_D) /* PD12 - EXMC_ADD17_DMC_BA1_NFC_ALE */
|
||||
#define NAND_ALE_PIN (GPIO_PIN_12)
|
||||
#define NAND_ALE_FUNC (GPIO_FUNC_21)
|
||||
|
||||
#define NAND_WP_PORT (GPIO_PORT_G) /* PG15 - EXMC_BAA */
|
||||
#define NAND_WP_PIN (GPIO_PIN_15)
|
||||
#define NAND_WP_FUNC (GPIO_FUNC_12)
|
||||
|
||||
#define NAND_RB_PORT (GPIO_PORT_G) /* PG06 - EXMC_RB0 */
|
||||
#define NAND_RB_PIN (GPIO_PIN_06)
|
||||
#define NAND_RB_FUNC (GPIO_FUNC_12)
|
||||
|
||||
#define NAND_DATA0_PORT (GPIO_PORT_D) /* PD14 - EXMC_DATA0 */
|
||||
#define NAND_DATA0_PIN (GPIO_PIN_14)
|
||||
#define NAND_DATA0_FUNC (GPIO_FUNC_12)
|
||||
#define NAND_DATA1_PORT (GPIO_PORT_D) /* PD15 - EXMC_DATA1 */
|
||||
#define NAND_DATA1_PIN (GPIO_PIN_15)
|
||||
#define NAND_DATA1_FUNC (GPIO_FUNC_12)
|
||||
#define NAND_DATA2_PORT (GPIO_PORT_D) /* PD0 - EXMC_DATA2 */
|
||||
#define NAND_DATA2_PIN (GPIO_PIN_00)
|
||||
#define NAND_DATA2_FUNC (GPIO_FUNC_12)
|
||||
#define NAND_DATA3_PORT (GPIO_PORT_D) /* PD1 - EXMC_DATA3 */
|
||||
#define NAND_DATA3_PIN (GPIO_PIN_01)
|
||||
#define NAND_DATA3_FUNC (GPIO_FUNC_12)
|
||||
#define NAND_DATA4_PORT (GPIO_PORT_E) /* PE7 - EXMC_DATA4 */
|
||||
#define NAND_DATA4_PIN (GPIO_PIN_07)
|
||||
#define NAND_DATA4_FUNC (GPIO_FUNC_12)
|
||||
#define NAND_DATA5_PORT (GPIO_PORT_E) /* PE8 - EXMC_DATA5 */
|
||||
#define NAND_DATA5_PIN (GPIO_PIN_08)
|
||||
#define NAND_DATA5_FUNC (GPIO_FUNC_12)
|
||||
#define NAND_DATA6_PORT (GPIO_PORT_E) /* PE9 - EXMC_DATA6 */
|
||||
#define NAND_DATA6_PIN (GPIO_PIN_09)
|
||||
#define NAND_DATA6_FUNC (GPIO_FUNC_12)
|
||||
#define NAND_DATA7_PORT (GPIO_PORT_E) /* PE10 - EXMC_DATA7 */
|
||||
#define NAND_DATA7_PIN (GPIO_PIN_10)
|
||||
#define NAND_DATA7_FUNC (GPIO_FUNC_12)
|
||||
#endif
|
||||
|
||||
/************************ SDIOC port **********************/
|
||||
#if defined(BSP_USING_SDIO1)
|
||||
#define SDIOC1_CK_PORT (GPIO_PORT_C)
|
||||
#define SDIOC1_CK_PIN (GPIO_PIN_12)
|
||||
#define SDIOC1_CK_FUNC (GPIO_FUNC_9)
|
||||
|
||||
#define SDIOC1_CMD_PORT (GPIO_PORT_D)
|
||||
#define SDIOC1_CMD_PIN (GPIO_PIN_02)
|
||||
#define SDIOC1_CMD_FUNC (GPIO_FUNC_9)
|
||||
|
||||
#define SDIOC1_D0_PORT (GPIO_PORT_B)
|
||||
#define SDIOC1_D0_PIN (GPIO_PIN_07)
|
||||
#define SDIOC1_D0_FUNC (GPIO_FUNC_9)
|
||||
|
||||
#define SDIOC1_D1_PORT (GPIO_PORT_A)
|
||||
#define SDIOC1_D1_PIN (GPIO_PIN_08)
|
||||
#define SDIOC1_D1_FUNC (GPIO_FUNC_9)
|
||||
|
||||
#define SDIOC1_D2_PORT (GPIO_PORT_C)
|
||||
#define SDIOC1_D2_PIN (GPIO_PIN_10)
|
||||
#define SDIOC1_D2_FUNC (GPIO_FUNC_9)
|
||||
|
||||
#define SDIOC1_D3_PORT (GPIO_PORT_B)
|
||||
#define SDIOC1_D3_PIN (GPIO_PIN_05)
|
||||
#define SDIOC1_D3_FUNC (GPIO_FUNC_9)
|
||||
#endif
|
||||
|
||||
/************************ SDRAM port **********************/
|
||||
#if defined(BSP_USING_SDRAM)
|
||||
#define SDRAM_CKE_PORT (GPIO_PORT_C) /* PC03 - EXMC_DMC_CKE */
|
||||
#define SDRAM_CKE_PIN (GPIO_PIN_03)
|
||||
#define SDRAM_CKE_FUNC (GPIO_FUNC_21)
|
||||
|
||||
#define SDRAM_CLK_PORT (GPIO_PORT_G) /* PG08 - EXMC_DMC_CLK */
|
||||
#define SDRAM_CLK_PIN (GPIO_PIN_08)
|
||||
#define SDRAM_CLK_FUNC (GPIO_FUNC_21)
|
||||
|
||||
#define SDRAM_DQM0_PORT (GPIO_PORT_E) /* PE00 - EXMC_CE4 */
|
||||
#define SDRAM_DQM0_PIN (GPIO_PIN_00)
|
||||
#define SDRAM_DQM0_FUNC (GPIO_FUNC_21)
|
||||
#define SDRAM_DQM1_PORT (GPIO_PORT_E) /* PE01 - EXMC_CE5 */
|
||||
#define SDRAM_DQM1_PIN (GPIO_PIN_01)
|
||||
#define SDRAM_DQM1_FUNC (GPIO_FUNC_21)
|
||||
|
||||
#define SDRAM_BA0_PORT (GPIO_PORT_G) /* PG04 - EXMC_ADD14_DMC_BA0 */
|
||||
#define SDRAM_BA0_PIN (GPIO_PIN_04)
|
||||
#define SDRAM_BA0_FUNC (GPIO_FUNC_21)
|
||||
#define SDRAM_BA1_PORT (GPIO_PORT_G) /* PG05 - EXMC_ADD15_DMC_BA1 */
|
||||
#define SDRAM_BA1_PIN (GPIO_PIN_05)
|
||||
#define SDRAM_BA1_FUNC (GPIO_FUNC_21)
|
||||
|
||||
#define SDRAM_CS_PORT (GPIO_PORT_C) /* PC02 - EXMC_DMC_CS0 */
|
||||
#define SDRAM_CS_PIN (GPIO_PIN_02)
|
||||
#define SDRAM_CS_FUNC (GPIO_FUNC_21)
|
||||
|
||||
#define SDRAM_RAS_PORT (GPIO_PORT_F) /* PF11 - EXMC_DMC_RAS */
|
||||
#define SDRAM_RAS_PIN (GPIO_PIN_11)
|
||||
#define SDRAM_RAS_FUNC (GPIO_FUNC_21)
|
||||
|
||||
#define SDRAM_CAS_PORT (GPIO_PORT_G) /* PG15 - EXMC_DMC_CAS*/
|
||||
#define SDRAM_CAS_PIN (GPIO_PIN_15)
|
||||
#define SDRAM_CAS_FUNC (GPIO_FUNC_21)
|
||||
|
||||
#define SDRAM_WE_PORT (GPIO_PORT_C) /* PC00 - EXMC_DMC_WE */
|
||||
#define SDRAM_WE_PIN (GPIO_PIN_00)
|
||||
#define SDRAM_WE_FUNC (GPIO_FUNC_21)
|
||||
|
||||
#define SDRAM_ADD0_PORT (GPIO_PORT_F) /* PF00 - EXMC_ADD0 */
|
||||
#define SDRAM_ADD0_PIN (GPIO_PIN_00)
|
||||
#define SDRAM_ADD0_FUNC (GPIO_FUNC_12)
|
||||
|
||||
#define SDRAM_ADD1_PORT (GPIO_PORT_F) /* PF01 - EXMC_ADD1 */
|
||||
#define SDRAM_ADD1_PIN (GPIO_PIN_01)
|
||||
#define SDRAM_ADD1_FUNC (GPIO_FUNC_12)
|
||||
|
||||
#define SDRAM_ADD2_PORT (GPIO_PORT_F) /* PF02 - EXMC_ADD2 */
|
||||
#define SDRAM_ADD2_PIN (GPIO_PIN_02)
|
||||
#define SDRAM_ADD2_FUNC (GPIO_FUNC_12)
|
||||
|
||||
#define SDRAM_ADD3_PORT (GPIO_PORT_F) /* PF03 - EXMC_ADD3 */
|
||||
#define SDRAM_ADD3_PIN (GPIO_PIN_03)
|
||||
#define SDRAM_ADD3_FUNC (GPIO_FUNC_12)
|
||||
|
||||
#define SDRAM_ADD4_PORT (GPIO_PORT_F) /* PF04 - EXMC_ADD4 */
|
||||
#define SDRAM_ADD4_PIN (GPIO_PIN_04)
|
||||
#define SDRAM_ADD4_FUNC (GPIO_FUNC_12)
|
||||
|
||||
#define SDRAM_ADD5_PORT (GPIO_PORT_F) /* PF05 - EXMC_ADD5 */
|
||||
#define SDRAM_ADD5_PIN (GPIO_PIN_05)
|
||||
#define SDRAM_ADD5_FUNC (GPIO_FUNC_12)
|
||||
|
||||
#define SDRAM_ADD6_PORT (GPIO_PORT_F) /* PF12 - EXMC_ADD6 */
|
||||
#define SDRAM_ADD6_PIN (GPIO_PIN_12)
|
||||
#define SDRAM_ADD6_FUNC (GPIO_FUNC_12)
|
||||
|
||||
#define SDRAM_ADD7_PORT (GPIO_PORT_F) /* PF13 - EXMC_ADD7 */
|
||||
#define SDRAM_ADD7_PIN (GPIO_PIN_13)
|
||||
#define SDRAM_ADD7_FUNC (GPIO_FUNC_12)
|
||||
|
||||
#define SDRAM_ADD8_PORT (GPIO_PORT_F) /* PF14 - EXMC_ADD8 */
|
||||
#define SDRAM_ADD8_PIN (GPIO_PIN_14)
|
||||
#define SDRAM_ADD8_FUNC (GPIO_FUNC_12)
|
||||
|
||||
#define SDRAM_ADD9_PORT (GPIO_PORT_F) /* PF15 - EXMC_ADD9 */
|
||||
#define SDRAM_ADD9_PIN (GPIO_PIN_15)
|
||||
#define SDRAM_ADD9_FUNC (GPIO_FUNC_12)
|
||||
|
||||
#define SDRAM_ADD10_PORT (GPIO_PORT_G) /* PG00 - EXMC_ADD10 */
|
||||
#define SDRAM_ADD10_PIN (GPIO_PIN_00)
|
||||
#define SDRAM_ADD10_FUNC (GPIO_FUNC_12)
|
||||
|
||||
#define SDRAM_ADD11_PORT (GPIO_PORT_G) /* PG01 - EXMC_ADD11 */
|
||||
#define SDRAM_ADD11_PIN (GPIO_PIN_01)
|
||||
#define SDRAM_ADD11_FUNC (GPIO_FUNC_12)
|
||||
|
||||
#define SDRAM_ADD12_PORT (GPIO_PORT_G) /* PG02 - EXMC_ADD12 */
|
||||
#define SDRAM_ADD12_PIN (GPIO_PIN_02)
|
||||
#define SDRAM_ADD12_FUNC (GPIO_FUNC_12)
|
||||
|
||||
#define SDRAM_DATA0_PORT (GPIO_PORT_D) /* PD14 - EXMC_DATA0 */
|
||||
#define SDRAM_DATA0_PIN (GPIO_PIN_14)
|
||||
#define SDRAM_DATA0_FUNC (GPIO_FUNC_12)
|
||||
#define SDRAM_DATA1_PORT (GPIO_PORT_D) /* PD15 - EXMC_DATA1 */
|
||||
#define SDRAM_DATA1_PIN (GPIO_PIN_15)
|
||||
#define SDRAM_DATA1_FUNC (GPIO_FUNC_12)
|
||||
#define SDRAM_DATA2_PORT (GPIO_PORT_D) /* PD00 - EXMC_DATA2 */
|
||||
#define SDRAM_DATA2_PIN (GPIO_PIN_00)
|
||||
#define SDRAM_DATA2_FUNC (GPIO_FUNC_12)
|
||||
#define SDRAM_DATA3_PORT (GPIO_PORT_D) /* PD01 - EXMC_DATA3 */
|
||||
#define SDRAM_DATA3_PIN (GPIO_PIN_01)
|
||||
#define SDRAM_DATA3_FUNC (GPIO_FUNC_12)
|
||||
#define SDRAM_DATA4_PORT (GPIO_PORT_E) /* PE07 - EXMC_DATA4 */
|
||||
#define SDRAM_DATA4_PIN (GPIO_PIN_07)
|
||||
#define SDRAM_DATA4_FUNC (GPIO_FUNC_12)
|
||||
#define SDRAM_DATA5_PORT (GPIO_PORT_E) /* PE08 - EXMC_DATA5 */
|
||||
#define SDRAM_DATA5_PIN (GPIO_PIN_08)
|
||||
#define SDRAM_DATA5_FUNC (GPIO_FUNC_12)
|
||||
#define SDRAM_DATA6_PORT (GPIO_PORT_E) /* PE09 - EXMC_DATA6 */
|
||||
#define SDRAM_DATA6_PIN (GPIO_PIN_09)
|
||||
#define SDRAM_DATA6_FUNC (GPIO_FUNC_12)
|
||||
#define SDRAM_DATA7_PORT (GPIO_PORT_E) /* PE10 - EXMC_DATA7 */
|
||||
#define SDRAM_DATA7_PIN (GPIO_PIN_10)
|
||||
#define SDRAM_DATA7_FUNC (GPIO_FUNC_12)
|
||||
#define SDRAM_DATA8_PORT (GPIO_PORT_E) /* PE11 - EXMC_DATA8 */
|
||||
#define SDRAM_DATA8_PIN (GPIO_PIN_11)
|
||||
#define SDRAM_DATA8_FUNC (GPIO_FUNC_12)
|
||||
#define SDRAM_DATA9_PORT (GPIO_PORT_E) /* PE12 - EXMC_DATA9 */
|
||||
#define SDRAM_DATA9_PIN (GPIO_PIN_12)
|
||||
#define SDRAM_DATA9_FUNC (GPIO_FUNC_12)
|
||||
#define SDRAM_DATA10_PORT (GPIO_PORT_E) /* PE13 - EXMC_DATA10 */
|
||||
#define SDRAM_DATA10_PIN (GPIO_PIN_13)
|
||||
#define SDRAM_DATA10_FUNC (GPIO_FUNC_12)
|
||||
#define SDRAM_DATA11_PORT (GPIO_PORT_E) /* PE14 - EXMC_DATA11 */
|
||||
#define SDRAM_DATA11_PIN (GPIO_PIN_14)
|
||||
#define SDRAM_DATA11_FUNC (GPIO_FUNC_12)
|
||||
#define SDRAM_DATA12_PORT (GPIO_PORT_E) /* PE15 - EXMC_DATA12 */
|
||||
#define SDRAM_DATA12_PIN (GPIO_PIN_15)
|
||||
#define SDRAM_DATA12_FUNC (GPIO_FUNC_12)
|
||||
#define SDRAM_DATA13_PORT (GPIO_PORT_D) /* PD08 - EXMC_DATA13 */
|
||||
#define SDRAM_DATA13_PIN (GPIO_PIN_08)
|
||||
#define SDRAM_DATA13_FUNC (GPIO_FUNC_12)
|
||||
#define SDRAM_DATA14_PORT (GPIO_PORT_D) /* PD09 - EXMC_DATA14 */
|
||||
#define SDRAM_DATA14_PIN (GPIO_PIN_09)
|
||||
#define SDRAM_DATA14_FUNC (GPIO_FUNC_12)
|
||||
#define SDRAM_DATA15_PORT (GPIO_PORT_D) /* PD10 - EXMC_DATA15 */
|
||||
#define SDRAM_DATA15_PIN (GPIO_PIN_10)
|
||||
#define SDRAM_DATA15_FUNC (GPIO_FUNC_12)
|
||||
#endif
|
||||
|
||||
/************************ RTC/PM *****************************/
|
||||
#if defined(BSP_USING_RTC) || defined(RT_USING_PM)
|
||||
#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
|
||||
#define XTAL32_PORT (GPIO_PORT_C)
|
||||
#define XTAL32_IN_PIN (GPIO_PIN_15)
|
||||
#define XTAL32_OUT_PIN (GPIO_PIN_14)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(RT_USING_PWM)
|
||||
/*********** PWM_TMRA configure *********/
|
||||
#if defined(BSP_USING_PWM_TMRA_1)
|
||||
#if defined(BSP_USING_PWM_TMRA_1_CH1)
|
||||
#define PWM_TMRA_1_CH1_PORT (GPIO_PORT_A)
|
||||
#define PWM_TMRA_1_CH1_PIN (GPIO_PIN_08)
|
||||
#define PWM_TMRA_1_CH1_PIN_FUNC (GPIO_FUNC_4)
|
||||
#endif
|
||||
#if defined(BSP_USING_PWM_TMRA_1_CH2)
|
||||
#define PWM_TMRA_1_CH2_PORT (GPIO_PORT_A)
|
||||
#define PWM_TMRA_1_CH2_PIN (GPIO_PIN_09)
|
||||
#define PWM_TMRA_1_CH2_PIN_FUNC (GPIO_FUNC_4)
|
||||
#endif
|
||||
#if defined(BSP_USING_PWM_TMRA_1_CH3)
|
||||
#define PWM_TMRA_1_CH3_PORT (GPIO_PORT_A)
|
||||
#define PWM_TMRA_1_CH3_PIN (GPIO_PIN_10)
|
||||
#define PWM_TMRA_1_CH3_PIN_FUNC (GPIO_FUNC_4)
|
||||
#endif
|
||||
#if defined(BSP_USING_PWM_TMRA_1_CH4)
|
||||
#define PWM_TMRA_1_CH4_PORT (GPIO_PORT_A)
|
||||
#define PWM_TMRA_1_CH4_PIN (GPIO_PIN_11)
|
||||
#define PWM_TMRA_1_CH4_PIN_FUNC (GPIO_FUNC_4)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*********** PWM_TMR4 configure *********/
|
||||
#if defined(BSP_USING_PWM_TMR4_1)
|
||||
#if defined(BSP_USING_PWM_TMR4_1_OUH)
|
||||
#define PWM_TMR4_1_OUH_PORT (GPIO_PORT_E)
|
||||
#define PWM_TMR4_1_OUH_PIN (GPIO_PIN_09)
|
||||
#define PWM_TMR4_1_OUH_PIN_FUNC (GPIO_FUNC_2)
|
||||
#endif
|
||||
#if defined(BSP_USING_PWM_TMR4_1_OUL)
|
||||
#define PWM_TMR4_1_OUL_PORT (GPIO_PORT_E)
|
||||
#define PWM_TMR4_1_OUL_PIN (GPIO_PIN_08)
|
||||
#define PWM_TMR4_1_OUL_PIN_FUNC (GPIO_FUNC_2)
|
||||
#endif
|
||||
#if defined(BSP_USING_PWM_TMR4_1_OVH)
|
||||
#define PWM_TMR4_1_OVH_PORT (GPIO_PORT_E)
|
||||
#define PWM_TMR4_1_OVH_PIN (GPIO_PIN_11)
|
||||
#define PWM_TMR4_1_OVH_PIN_FUNC (GPIO_FUNC_2)
|
||||
#endif
|
||||
#if defined(BSP_USING_PWM_TMR4_1_OVL)
|
||||
#define PWM_TMR4_1_OVL_PORT (GPIO_PORT_E)
|
||||
#define PWM_TMR4_1_OVL_PIN (GPIO_PIN_10)
|
||||
#define PWM_TMR4_1_OVL_PIN_FUNC (GPIO_FUNC_2)
|
||||
#endif
|
||||
#if defined(BSP_USING_PWM_TMR4_1_OWH)
|
||||
#define PWM_TMR4_1_OWH_PORT (GPIO_PORT_E)
|
||||
#define PWM_TMR4_1_OWH_PIN (GPIO_PIN_13)
|
||||
#define PWM_TMR4_1_OWH_PIN_FUNC (GPIO_FUNC_2)
|
||||
#endif
|
||||
#if defined(BSP_USING_PWM_TMR4_1_OWL)
|
||||
#define PWM_TMR4_1_OWL_PORT (GPIO_PORT_E)
|
||||
#define PWM_TMR4_1_OWL_PIN (GPIO_PIN_12)
|
||||
#define PWM_TMR4_1_OWL_PIN_FUNC (GPIO_FUNC_2)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*********** PWM_TMR6 configure *********/
|
||||
#if defined(BSP_USING_PWM_TMR6_1)
|
||||
#if defined(BSP_USING_PWM_TMR6_1_A)
|
||||
#define PWM_TMR6_1_A_PORT (GPIO_PORT_F)
|
||||
#define PWM_TMR6_1_A_PIN (GPIO_PIN_13)
|
||||
#define PWM_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3)
|
||||
#endif
|
||||
#if defined(BSP_USING_PWM_TMR6_1_B)
|
||||
#define PWM_TMR6_1_B_PORT (GPIO_PORT_F)
|
||||
#define PWM_TMR6_1_B_PIN (GPIO_PIN_14)
|
||||
#define PWM_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_INPUT_CAPTURE)
|
||||
#define INPUT_CAPTURE_TMR6_FUNC (GPIO_FUNC_3)
|
||||
#if defined(BSP_USING_INPUT_CAPTURE_TMR6_1)
|
||||
#define INPUT_CAPTURE_TMR6_1_PORT (GPIO_PORT_B)
|
||||
#define INPUT_CAPTURE_TMR6_1_PIN (GPIO_PIN_09)
|
||||
#endif
|
||||
#if defined(BSP_USING_INPUT_CAPTURE_TMR6_2)
|
||||
#define INPUT_CAPTURE_TMR6_2_PORT (GPIO_PORT_E)
|
||||
#define INPUT_CAPTURE_TMR6_2_PIN (GPIO_PIN_07)
|
||||
#endif
|
||||
#if defined(BSP_USING_INPUT_CAPTURE_TMR6_3)
|
||||
#define INPUT_CAPTURE_TMR6_3_PORT (GPIO_PORT_A)
|
||||
#define INPUT_CAPTURE_TMR6_3_PIN (GPIO_PIN_00)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH)
|
||||
#if defined(BSP_USING_USBFS)
|
||||
/* USBFS Core*/
|
||||
#define USBF_DP_PORT (GPIO_PORT_A)
|
||||
#define USBF_DP_PIN (GPIO_PIN_12)
|
||||
#define USBF_DM_PORT (GPIO_PORT_A)
|
||||
#define USBF_DM_PIN (GPIO_PIN_11)
|
||||
#define USBF_VBUS_PORT (GPIO_PORT_A)
|
||||
#define USBF_VBUS_PIN (GPIO_PIN_09)
|
||||
#define USBF_VBUS_FUNC (GPIO_FUNC_10)
|
||||
#define USBF_DRVVBUS_PORT (GPIO_PORT_C)
|
||||
#define USBF_DRVVBUS_PIN (GPIO_PIN_09)
|
||||
#define USBF_DRVVBUS_FUNC (GPIO_FUNC_10)
|
||||
#endif
|
||||
#if defined(BSP_USING_USBHS)
|
||||
/* USBHS Core*/
|
||||
#if defined(BSP_USING_USBHS_PHY_EMBED)
|
||||
#define USBH_DP_PORT (GPIO_PORT_B)
|
||||
#define USBH_DP_PIN (GPIO_PIN_15)
|
||||
#define USBH_DP_FUNC (GPIO_FUNC_10)
|
||||
#define USBH_DM_PORT (GPIO_PORT_B)
|
||||
#define USBH_DM_PIN (GPIO_PIN_14)
|
||||
#define USBH_DM_FUNC (GPIO_FUNC_10)
|
||||
#define USBH_VBUS_PORT (GPIO_PORT_B)
|
||||
#define USBH_VBUS_PIN (GPIO_PIN_13)
|
||||
#define USBH_VBUS_FUNC (GPIO_FUNC_12)
|
||||
#define USBH_DRVVBUS_PORT (GPIO_PORT_B)
|
||||
#define USBH_DRVVBUS_PIN (GPIO_PIN_11)
|
||||
#define USBH_DRVVBUS_FUNC (GPIO_FUNC_10)
|
||||
#else
|
||||
/* USBHS Core, external PHY */
|
||||
#define USBH_ULPI_CLK_PORT (GPIO_PORT_E)
|
||||
#define USBH_ULPI_CLK_PIN (GPIO_PIN_12)
|
||||
#define USBH_ULPI_CLK_FUNC (GPIO_FUNC_10)
|
||||
#define USBH_ULPI_DIR_PORT (GPIO_PORT_C)
|
||||
#define USBH_ULPI_DIR_PIN (GPIO_PIN_02)
|
||||
#define USBH_ULPI_DIR_FUNC (GPIO_FUNC_10)
|
||||
#define USBH_ULPI_NXT_PORT (GPIO_PORT_C)
|
||||
#define USBH_ULPI_NXT_PIN (GPIO_PIN_03)
|
||||
#define USBH_ULPI_NXT_FUNC (GPIO_FUNC_10)
|
||||
#define USBH_ULPI_STP_PORT (GPIO_PORT_C)
|
||||
#define USBH_ULPI_STP_PIN (GPIO_PIN_00)
|
||||
#define USBH_ULPI_STP_FUNC (GPIO_FUNC_10)
|
||||
#define USBH_ULPI_D0_PORT (GPIO_PORT_E)
|
||||
#define USBH_ULPI_D0_PIN (GPIO_PIN_13)
|
||||
#define USBH_ULPI_D0_FUNC (GPIO_FUNC_10)
|
||||
#define USBH_ULPI_D1_PORT (GPIO_PORT_E)
|
||||
#define USBH_ULPI_D1_PIN (GPIO_PIN_14)
|
||||
#define USBH_ULPI_D1_FUNC (GPIO_FUNC_10)
|
||||
#define USBH_ULPI_D2_PORT (GPIO_PORT_E)
|
||||
#define USBH_ULPI_D2_PIN (GPIO_PIN_15)
|
||||
#define USBH_ULPI_D2_FUNC (GPIO_FUNC_10)
|
||||
#define USBH_ULPI_D3_PORT (GPIO_PORT_B)
|
||||
#define USBH_ULPI_D3_PIN (GPIO_PIN_10)
|
||||
#define USBH_ULPI_D3_FUNC (GPIO_FUNC_10)
|
||||
#define USBH_ULPI_D4_PORT (GPIO_PORT_B)
|
||||
#define USBH_ULPI_D4_PIN (GPIO_PIN_11)
|
||||
#define USBH_ULPI_D4_FUNC (GPIO_FUNC_10)
|
||||
#define USBH_ULPI_D5_PORT (GPIO_PORT_B)
|
||||
#define USBH_ULPI_D5_PIN (GPIO_PIN_12)
|
||||
#define USBH_ULPI_D5_FUNC (GPIO_FUNC_10)
|
||||
#define USBH_ULPI_D6_PORT (GPIO_PORT_B)
|
||||
#define USBH_ULPI_D6_PIN (GPIO_PIN_13)
|
||||
#define USBH_ULPI_D6_FUNC (GPIO_FUNC_10)
|
||||
#define USBH_ULPI_D7_PORT (GPIO_PORT_E)
|
||||
#define USBH_ULPI_D7_PIN (GPIO_PIN_11)
|
||||
#define USBH_ULPI_D7_FUNC (GPIO_FUNC_10)
|
||||
/* 3300 reset */
|
||||
#define USB_3300_RESET_PORT (EIO_PORT1)
|
||||
#define USB_3300_RESET_PIN (EIO_USB3300_RST)
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_QSPI)
|
||||
#ifndef BSP_QSPI_USING_SOFT_CS
|
||||
/* QSSN */
|
||||
#define QSPI_FLASH_CS_PORT (GPIO_PORT_C)
|
||||
#define QSPI_FLASH_CS_PIN (GPIO_PIN_07)
|
||||
#define QSPI_FLASH_CS_FUNC (GPIO_FUNC_18)
|
||||
#endif
|
||||
/* QSCK */
|
||||
#define QSPI_FLASH_SCK_PORT (GPIO_PORT_C)
|
||||
#define QSPI_FLASH_SCK_PIN (GPIO_PIN_06)
|
||||
#define QSPI_FLASH_SCK_FUNC (GPIO_FUNC_18)
|
||||
/* QSIO0 */
|
||||
#define QSPI_FLASH_IO0_PORT (GPIO_PORT_B)
|
||||
#define QSPI_FLASH_IO0_PIN (GPIO_PIN_13)
|
||||
#define QSPI_FLASH_IO0_FUNC (GPIO_FUNC_18)
|
||||
/* QSIO1 */
|
||||
#define QSPI_FLASH_IO1_PORT (GPIO_PORT_B)
|
||||
#define QSPI_FLASH_IO1_PIN (GPIO_PIN_12)
|
||||
#define QSPI_FLASH_IO1_FUNC (GPIO_FUNC_18)
|
||||
/* QSIO2 */
|
||||
#define QSPI_FLASH_IO2_PORT (GPIO_PORT_B)
|
||||
#define QSPI_FLASH_IO2_PIN (GPIO_PIN_10)
|
||||
#define QSPI_FLASH_IO2_FUNC (GPIO_FUNC_18)
|
||||
/* QSIO3 */
|
||||
#define QSPI_FLASH_IO3_PORT (GPIO_PORT_B)
|
||||
#define QSPI_FLASH_IO3_PIN (GPIO_PIN_02)
|
||||
#define QSPI_FLASH_IO3_FUNC (GPIO_FUNC_18)
|
||||
#endif
|
||||
|
||||
/*********** TMRA_PULSE_ENCODER configure *********/
|
||||
#if defined(RT_USING_PULSE_ENCODER)
|
||||
#if defined(BSP_USING_TMRA_PULSE_ENCODER)
|
||||
#if defined(BSP_USING_PULSE_ENCODER_TMRA_1)
|
||||
#define PULSE_ENCODER_TMRA_1_A_PORT (GPIO_PORT_A)
|
||||
#define PULSE_ENCODER_TMRA_1_A_PIN (GPIO_PIN_08)
|
||||
#define PULSE_ENCODER_TMRA_1_A_PIN_FUNC (GPIO_FUNC_4)
|
||||
#define PULSE_ENCODER_TMRA_1_B_PORT (GPIO_PORT_A)
|
||||
#define PULSE_ENCODER_TMRA_1_B_PIN (GPIO_PIN_09)
|
||||
#define PULSE_ENCODER_TMRA_1_B_PIN_FUNC (GPIO_FUNC_4)
|
||||
#endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */
|
||||
#endif /* BSP_USING_TMRA_PULSE_ENCODER */
|
||||
|
||||
#if defined(BSP_USING_TMR6_PULSE_ENCODER)
|
||||
#if defined(BSP_USING_PULSE_ENCODER_TMR6_1)
|
||||
#define PULSE_ENCODER_TMR6_1_A_PORT (GPIO_PORT_B)
|
||||
#define PULSE_ENCODER_TMR6_1_A_PIN (GPIO_PIN_09)
|
||||
#define PULSE_ENCODER_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3)
|
||||
#define PULSE_ENCODER_TMR6_1_B_PORT (GPIO_PORT_B)
|
||||
#define PULSE_ENCODER_TMR6_1_B_PIN (GPIO_PIN_08)
|
||||
#define PULSE_ENCODER_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3)
|
||||
#endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */
|
||||
#endif /* BSP_USING_TMR6_PULSE_ENCODER */
|
||||
#endif /* RT_USING_PULSE_ENCODER */
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -0,0 +1,153 @@
|
|||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __ADC_CONFIG_H__
|
||||
#define __ADC_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "irq_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_ADC1
|
||||
#ifndef ADC1_INIT_PARAMS
|
||||
#define ADC1_INIT_PARAMS \
|
||||
{ \
|
||||
.name = "adc1", \
|
||||
.vref = 3300, \
|
||||
.resolution = ADC_RESOLUTION_12BIT, \
|
||||
.data_align = ADC_DATAALIGN_RIGHT, \
|
||||
.eoc_poll_time_max = 100, \
|
||||
.hard_trig_enable = RT_FALSE, \
|
||||
.hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \
|
||||
.internal_trig0_comtrg0_enable = RT_FALSE, \
|
||||
.internal_trig0_comtrg1_enable = RT_FALSE, \
|
||||
.internal_trig0_sel = EVT_SRC_MAX, \
|
||||
.internal_trig1_comtrg0_enable = RT_FALSE, \
|
||||
.internal_trig1_comtrg1_enable = RT_FALSE, \
|
||||
.internal_trig1_sel = EVT_SRC_MAX, \
|
||||
.continue_conv_mode_enable = RT_FALSE, \
|
||||
.data_reg_auto_clear = RT_TRUE, \
|
||||
}
|
||||
#endif /* ADC1_INIT_PARAMS */
|
||||
|
||||
#if defined (BSP_ADC1_USING_DMA)
|
||||
#ifndef ADC1_EOCA_DMA_CONFIG
|
||||
#define ADC1_EOCA_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = ADC1_EOCA_DMA_INSTANCE, \
|
||||
.channel = ADC1_EOCA_DMA_CHANNEL, \
|
||||
.clock = ADC1_EOCA_DMA_CLOCK, \
|
||||
.trigger_select = ADC1_EOCA_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_ADC1_EOCA, \
|
||||
.flag = ADC1_EOCA_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = ADC1_EOCA_DMA_IRQn, \
|
||||
.irq_prio = ADC1_EOCA_DMA_INT_PRIO, \
|
||||
.int_src = ADC1_EOCA_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* ADC1_EOCA_DMA_CONFIG */
|
||||
#endif /* BSP_ADC1_USING_DMA */
|
||||
#endif /* BSP_USING_ADC1 */
|
||||
|
||||
#ifdef BSP_USING_ADC2
|
||||
#ifndef ADC2_INIT_PARAMS
|
||||
#define ADC2_INIT_PARAMS \
|
||||
{ \
|
||||
.name = "adc2", \
|
||||
.vref = 3300, \
|
||||
.resolution = ADC_RESOLUTION_12BIT, \
|
||||
.data_align = ADC_DATAALIGN_RIGHT, \
|
||||
.eoc_poll_time_max = 100, \
|
||||
.hard_trig_enable = RT_FALSE, \
|
||||
.hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \
|
||||
.internal_trig0_comtrg0_enable = RT_FALSE, \
|
||||
.internal_trig0_comtrg1_enable = RT_FALSE, \
|
||||
.internal_trig0_sel = EVT_SRC_MAX, \
|
||||
.internal_trig1_comtrg0_enable = RT_FALSE, \
|
||||
.internal_trig1_comtrg1_enable = RT_FALSE, \
|
||||
.internal_trig1_sel = EVT_SRC_MAX, \
|
||||
.continue_conv_mode_enable = RT_FALSE, \
|
||||
.data_reg_auto_clear = RT_TRUE, \
|
||||
}
|
||||
#endif /* ADC2_INIT_PARAMS */
|
||||
|
||||
#if defined (BSP_ADC2_USING_DMA)
|
||||
#ifndef ADC2_EOCA_DMA_CONFIG
|
||||
#define ADC2_EOCA_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = ADC2_EOCA_DMA_INSTANCE, \
|
||||
.channel = ADC2_EOCA_DMA_CHANNEL, \
|
||||
.clock = ADC2_EOCA_DMA_CLOCK, \
|
||||
.trigger_select = ADC2_EOCA_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_ADC2_EOCA, \
|
||||
.flag = ADC2_EOCA_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = ADC2_EOCA_DMA_IRQn, \
|
||||
.irq_prio = ADC2_EOCA_DMA_INT_PRIO, \
|
||||
.int_src = ADC2_EOCA_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* ADC2_EOCA_DMA_CONFIG */
|
||||
#endif /* BSP_ADC2_USING_DMA */
|
||||
#endif /* BSP_USING_ADC2 */
|
||||
|
||||
#ifdef BSP_USING_ADC3
|
||||
#ifndef ADC3_INIT_PARAMS
|
||||
#define ADC3_INIT_PARAMS \
|
||||
{ \
|
||||
.name = "adc3", \
|
||||
.vref = 3300, \
|
||||
.resolution = ADC_RESOLUTION_12BIT, \
|
||||
.data_align = ADC_DATAALIGN_RIGHT, \
|
||||
.eoc_poll_time_max = 100, \
|
||||
.hard_trig_enable = RT_FALSE, \
|
||||
.hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \
|
||||
.internal_trig0_comtrg0_enable = RT_FALSE, \
|
||||
.internal_trig0_comtrg1_enable = RT_FALSE, \
|
||||
.internal_trig0_sel = EVT_SRC_MAX, \
|
||||
.internal_trig1_comtrg0_enable = RT_FALSE, \
|
||||
.internal_trig1_comtrg1_enable = RT_FALSE, \
|
||||
.internal_trig1_sel = EVT_SRC_MAX, \
|
||||
.continue_conv_mode_enable = RT_FALSE, \
|
||||
.data_reg_auto_clear = RT_TRUE, \
|
||||
}
|
||||
#endif /* ADC3_INIT_PARAMS */
|
||||
#if defined (BSP_ADC3_USING_DMA)
|
||||
#ifndef ADC3_EOCA_DMA_CONFIG
|
||||
#define ADC3_EOCA_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = ADC3_EOCA_DMA_INSTANCE, \
|
||||
.channel = ADC3_EOCA_DMA_CHANNEL, \
|
||||
.clock = ADC3_EOCA_DMA_CLOCK, \
|
||||
.trigger_select = ADC3_EOCA_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_ADC3_EOCA, \
|
||||
.flag = ADC3_EOCA_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = ADC3_EOCA_DMA_IRQn, \
|
||||
.irq_prio = ADC3_EOCA_DMA_INT_PRIO, \
|
||||
.int_src = ADC3_EOCA_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* ADC3_EOCA_DMA_CONFIG */
|
||||
#endif /* BSP_ADC3_USING_DMA */
|
||||
#endif /* BSP_USING_ADC3 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ADC_CONFIG_H__ */
|
||||
|
|
@ -0,0 +1,130 @@
|
|||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __CAN_CONFIG_H__
|
||||
#define __CAN_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "irq_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_CAN1
|
||||
#define CAN1_CLOCK_SEL (CAN_CLOCK_SRC_40M)
|
||||
#define CAN1_NAME ("can1")
|
||||
#ifndef CAN1_INIT_PARAMS
|
||||
#define CAN1_INIT_PARAMS \
|
||||
{ \
|
||||
.name = CAN1_NAME, \
|
||||
.single_trans_mode = RT_FALSE \
|
||||
}
|
||||
#endif /* CAN1_INIT_PARAMS */
|
||||
#endif /* BSP_USING_CAN1 */
|
||||
|
||||
#ifdef BSP_USING_CAN2
|
||||
#define CAN2_CLOCK_SEL (CAN_CLOCK_SRC_40M)
|
||||
#define CAN2_NAME ("can2")
|
||||
#ifndef CAN2_INIT_PARAMS
|
||||
#define CAN2_INIT_PARAMS \
|
||||
{ \
|
||||
.name = CAN2_NAME, \
|
||||
.single_trans_mode = RT_FALSE \
|
||||
}
|
||||
#endif /* CAN2_INIT_PARAMS */
|
||||
#endif /* BSP_USING_CAN2 */
|
||||
|
||||
/* Bit time config
|
||||
Restrictions: u32TimeSeg1 >= u32TimeSeg2 + 1, u32TimeSeg2 >= u32SJW.
|
||||
|
||||
Baudrate = CANClock/(u32Prescaler*(u32TimeSeg1 + u32TimeSeg2))
|
||||
TQ = u32Prescaler / CANClock.
|
||||
Bit time = (u32TimeSeg2 + u32TimeSeg2) x TQ.
|
||||
|
||||
The following bit time configures are based on CAN Clock 40M
|
||||
*/
|
||||
#define CAN_BIT_TIME_CONFIG_1M_BAUD \
|
||||
{ \
|
||||
.u32Prescaler = 2, \
|
||||
.u32TimeSeg1 = 16, \
|
||||
.u32TimeSeg2 = 4, \
|
||||
.u32SJW = 4 \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_800K_BAUD \
|
||||
{ \
|
||||
.u32Prescaler = 2, \
|
||||
.u32TimeSeg1 = 20, \
|
||||
.u32TimeSeg2 = 5, \
|
||||
.u32SJW = 4 \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_500K_BAUD \
|
||||
{ \
|
||||
.u32Prescaler = 4, \
|
||||
.u32TimeSeg1 = 16, \
|
||||
.u32TimeSeg2 = 4, \
|
||||
.u32SJW = 4 \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_250K_BAUD \
|
||||
{ \
|
||||
.u32Prescaler = 8, \
|
||||
.u32TimeSeg1 = 16, \
|
||||
.u32TimeSeg2 = 4, \
|
||||
.u32SJW = 4 \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_125K_BAUD \
|
||||
{ \
|
||||
.u32Prescaler = 16, \
|
||||
.u32TimeSeg1 = 16, \
|
||||
.u32TimeSeg2 = 4, \
|
||||
.u32SJW = 4 \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_100K_BAUD \
|
||||
{ \
|
||||
.u32Prescaler = 20, \
|
||||
.u32TimeSeg1 = 16, \
|
||||
.u32TimeSeg2 = 4, \
|
||||
.u32SJW = 4 \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_50K_BAUD \
|
||||
{ \
|
||||
.u32Prescaler = 40, \
|
||||
.u32TimeSeg1 = 16, \
|
||||
.u32TimeSeg2 = 4, \
|
||||
.u32SJW = 4 \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_20K_BAUD \
|
||||
{ \
|
||||
.u32Prescaler = 100, \
|
||||
.u32TimeSeg1 = 16, \
|
||||
.u32TimeSeg2 = 4, \
|
||||
.u32SJW = 4 \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_10K_BAUD \
|
||||
{ \
|
||||
.u32Prescaler = 200, \
|
||||
.u32TimeSeg1 = 16, \
|
||||
.u32TimeSeg2 = 4, \
|
||||
.u32SJW = 4 \
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CAN_CONFIG_H__ */
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2023-05-12 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __DAC_CONFIG_H__
|
||||
#define __DAC_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_DAC1
|
||||
#ifndef DAC1_INIT_PARAMS
|
||||
#define DAC1_INIT_PARAMS \
|
||||
{ \
|
||||
.name = "dac1", \
|
||||
}
|
||||
#endif /* DAC1_INIT_PARAMS */
|
||||
#endif /* BSP_USING_DAC1 */
|
||||
|
||||
#ifdef BSP_USING_DAC2
|
||||
#ifndef DAC2_INIT_PARAMS
|
||||
#define DAC2_INIT_PARAMS \
|
||||
{ \
|
||||
.name = "dac2", \
|
||||
}
|
||||
#endif /* DAC2_INIT_PARAMS */
|
||||
#endif /* BSP_USING_DAC2 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __DAC_CONFIG_H__ */
|
||||
|
|
@ -0,0 +1,531 @@
|
|||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __DMA_CONFIG_H__
|
||||
#define __DMA_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "irq_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* DMA1 ch0 */
|
||||
#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
|
||||
#define SPI1_RX_DMA_INSTANCE CM_DMA1
|
||||
#define SPI1_RX_DMA_CHANNEL DMA_CH0
|
||||
#define SPI1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define SPI1_RX_DMA_TRIG_SELECT AOS_DMA1_0
|
||||
#define SPI1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
|
||||
#define SPI1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM
|
||||
#define SPI1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO
|
||||
#define SPI1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0
|
||||
#elif defined(BSP_USING_SDIO1) && !defined(SDIO1_RX_DMA_INSTANCE)
|
||||
#define SDIO1_RX_DMA_INSTANCE CM_DMA1
|
||||
#define SDIO1_RX_DMA_CHANNEL DMA_CH0
|
||||
#define SDIO1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define SDIO1_RX_DMA_TRIG_SELECT AOS_DMA1_0
|
||||
#define SDIO1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
|
||||
#define SDIO1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM
|
||||
#define SDIO1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO
|
||||
#define SDIO1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0
|
||||
#elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_INSTANCE)
|
||||
#define I2C1_TX_DMA_INSTANCE CM_DMA1
|
||||
#define I2C1_TX_DMA_CHANNEL DMA_CH0
|
||||
#define I2C1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define I2C1_TX_DMA_TRIG_SELECT AOS_DMA1_0
|
||||
#define I2C1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
|
||||
#define I2C1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM
|
||||
#define I2C1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO
|
||||
#define I2C1_TX_DMA_INT_SRC INT_SRC_DMA1_TC0
|
||||
#elif defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
|
||||
#define UART3_RX_DMA_INSTANCE CM_DMA1
|
||||
#define UART3_RX_DMA_CHANNEL DMA_CH0
|
||||
#define UART3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define UART3_RX_DMA_TRIG_SELECT AOS_DMA1_0
|
||||
#define UART3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
|
||||
#define UART3_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM
|
||||
#define UART3_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO
|
||||
#define UART3_RX_DMA_INT_SRC INT_SRC_DMA1_TC0
|
||||
#endif
|
||||
|
||||
/* DMA1 ch1 */
|
||||
#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
|
||||
#define SPI1_TX_DMA_INSTANCE CM_DMA1
|
||||
#define SPI1_TX_DMA_CHANNEL DMA_CH1
|
||||
#define SPI1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define SPI1_TX_DMA_TRIG_SELECT AOS_DMA1_1
|
||||
#define SPI1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
|
||||
#define SPI1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM
|
||||
#define SPI1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO
|
||||
#define SPI1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1
|
||||
#elif defined(BSP_USING_SDIO1) && !defined(SDIO1_TX_DMA_INSTANCE)
|
||||
#define SDIO1_TX_DMA_INSTANCE CM_DMA1
|
||||
#define SDIO1_TX_DMA_CHANNEL DMA_CH1
|
||||
#define SDIO1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define SDIO1_TX_DMA_TRIG_SELECT AOS_DMA1_1
|
||||
#define SDIO1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
|
||||
#define SDIO1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM
|
||||
#define SDIO1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO
|
||||
#define SDIO1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1
|
||||
#elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_INSTANCE)
|
||||
#define I2C1_RX_DMA_INSTANCE CM_DMA1
|
||||
#define I2C1_RX_DMA_CHANNEL DMA_CH1
|
||||
#define I2C1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define I2C1_RX_DMA_TRIG_SELECT AOS_DMA1_1
|
||||
#define I2C1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
|
||||
#define I2C1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM
|
||||
#define I2C1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO
|
||||
#define I2C1_RX_DMA_INT_SRC INT_SRC_DMA1_TC1
|
||||
#elif defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA_INSTANCE)
|
||||
#define UART3_TX_DMA_INSTANCE CM_DMA1
|
||||
#define UART3_TX_DMA_CHANNEL DMA_CH1
|
||||
#define UART3_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define UART3_TX_DMA_TRIG_SELECT AOS_DMA1_1
|
||||
#define UART3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
|
||||
#define UART3_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM
|
||||
#define UART3_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO
|
||||
#define UART3_TX_DMA_INT_SRC INT_SRC_DMA1_TC1
|
||||
#endif
|
||||
|
||||
/* DMA1 ch2 */
|
||||
#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
|
||||
#define SPI2_RX_DMA_INSTANCE CM_DMA1
|
||||
#define SPI2_RX_DMA_CHANNEL DMA_CH2
|
||||
#define SPI2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define SPI2_RX_DMA_TRIG_SELECT AOS_DMA1_2
|
||||
#define SPI2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
|
||||
#define SPI2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM
|
||||
#define SPI2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO
|
||||
#define SPI2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2
|
||||
#elif defined(BSP_USING_SDIO2) && !defined(SDIO2_RX_DMA_INSTANCE)
|
||||
#define SDIO2_RX_DMA_INSTANCE CM_DMA1
|
||||
#define SDIO2_RX_DMA_CHANNEL DMA_CH2
|
||||
#define SDIO2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define SDIO2_RX_DMA_TRIG_SELECT AOS_DMA1_2
|
||||
#define SDIO2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
|
||||
#define SDIO2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM
|
||||
#define SDIO2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO
|
||||
#define SDIO2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2
|
||||
#elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_INSTANCE)
|
||||
#define I2C2_TX_DMA_INSTANCE CM_DMA1
|
||||
#define I2C2_TX_DMA_CHANNEL DMA_CH2
|
||||
#define I2C2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define I2C2_TX_DMA_TRIG_SELECT AOS_DMA1_2
|
||||
#define I2C2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
|
||||
#define I2C2_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM
|
||||
#define I2C2_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO
|
||||
#define I2C2_TX_DMA_INT_SRC INT_SRC_DMA1_TC2
|
||||
#elif defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
|
||||
#define UART4_RX_DMA_INSTANCE CM_DMA1
|
||||
#define UART4_RX_DMA_CHANNEL DMA_CH2
|
||||
#define UART4_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define UART4_RX_DMA_TRIG_SELECT AOS_DMA1_2
|
||||
#define UART4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
|
||||
#define UART4_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM
|
||||
#define UART4_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO
|
||||
#define UART4_RX_DMA_INT_SRC INT_SRC_DMA1_TC2
|
||||
#endif
|
||||
|
||||
/* DMA1 ch3 */
|
||||
#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
|
||||
#define SPI2_TX_DMA_INSTANCE CM_DMA1
|
||||
#define SPI2_TX_DMA_CHANNEL DMA_CH3
|
||||
#define SPI2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define SPI2_TX_DMA_TRIG_SELECT AOS_DMA1_3
|
||||
#define SPI2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
|
||||
#define SPI2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM
|
||||
#define SPI2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO
|
||||
#define SPI2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3
|
||||
#elif defined(BSP_USING_SDIO2) && !defined(SDIO2_TX_DMA_INSTANCE)
|
||||
#define SDIO2_TX_DMA_INSTANCE CM_DMA1
|
||||
#define SDIO2_TX_DMA_CHANNEL DMA_CH3
|
||||
#define SDIO2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define SDIO2_TX_DMA_TRIG_SELECT AOS_DMA1_3
|
||||
#define SDIO2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
|
||||
#define SDIO2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM
|
||||
#define SDIO2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO
|
||||
#define SDIO2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3
|
||||
#elif defined(BSP_USING_QSPI) && !defined(QSPI_DMA_INSTANCE)
|
||||
#define QSPI_DMA_INSTANCE CM_DMA1
|
||||
#define QSPI_DMA_CHANNEL DMA_CH3
|
||||
#define QSPI_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define QSPI_DMA_TRIG_SELECT AOS_DMA1_3
|
||||
#define QSPI_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
|
||||
#define QSPI_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM
|
||||
#define QSPI_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO
|
||||
#define QSPI_DMA_INT_SRC INT_SRC_DMA1_TC3
|
||||
#elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_INSTANCE)
|
||||
#define I2C2_RX_DMA_INSTANCE CM_DMA1
|
||||
#define I2C2_RX_DMA_CHANNEL DMA_CH3
|
||||
#define I2C2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define I2C2_RX_DMA_TRIG_SELECT AOS_DMA1_3
|
||||
#define I2C2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
|
||||
#define I2C2_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM
|
||||
#define I2C2_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO
|
||||
#define I2C2_RX_DMA_INT_SRC INT_SRC_DMA1_TC3
|
||||
#elif defined(BSP_ADC1_USING_DMA) && !defined(ADC1_EOCA_DMA_INSTANCE)
|
||||
#define ADC1_EOCA_DMA_INSTANCE CM_DMA1
|
||||
#define ADC1_EOCA_DMA_CHANNEL DMA_CH3
|
||||
#define ADC1_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define ADC1_EOCA_DMA_TRIG_SELECT AOS_DMA1_3
|
||||
#define ADC1_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
|
||||
#define ADC1_EOCA_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM
|
||||
#define ADC1_EOCA_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO
|
||||
#define ADC1_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC3
|
||||
#elif defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE)
|
||||
#define UART4_TX_DMA_INSTANCE CM_DMA1
|
||||
#define UART4_TX_DMA_CHANNEL DMA_CH3
|
||||
#define UART4_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define UART4_TX_DMA_TRIG_SELECT AOS_DMA1_3
|
||||
#define UART4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
|
||||
#define UART4_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM
|
||||
#define UART4_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO
|
||||
#define UART4_TX_DMA_INT_SRC INT_SRC_DMA1_TC3
|
||||
#endif
|
||||
|
||||
/* DMA1 ch4 */
|
||||
#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
|
||||
#define SPI3_RX_DMA_INSTANCE CM_DMA1
|
||||
#define SPI3_RX_DMA_CHANNEL DMA_CH4
|
||||
#define SPI3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define SPI3_RX_DMA_TRIG_SELECT AOS_DMA1_4
|
||||
#define SPI3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4
|
||||
#define SPI3_RX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM
|
||||
#define SPI3_RX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO
|
||||
#define SPI3_RX_DMA_INT_SRC INT_SRC_DMA1_TC4
|
||||
#elif defined(BSP_I2C3_TX_USING_DMA) && !defined(I2C3_TX_DMA_INSTANCE)
|
||||
#define I2C3_TX_DMA_INSTANCE CM_DMA1
|
||||
#define I2C3_TX_DMA_CHANNEL DMA_CH4
|
||||
#define I2C3_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define I2C3_TX_DMA_TRIG_SELECT AOS_DMA1_4
|
||||
#define I2C3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4
|
||||
#define I2C3_TX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM
|
||||
#define I2C3_TX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO
|
||||
#define I2C3_TX_DMA_INT_SRC INT_SRC_DMA1_TC4
|
||||
#elif defined(BSP_ADC2_USING_DMA) && !defined(ADC2_EOCA_DMA_INSTANCE)
|
||||
#define ADC2_EOCA_DMA_INSTANCE CM_DMA1
|
||||
#define ADC2_EOCA_DMA_CHANNEL DMA_CH4
|
||||
#define ADC2_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define ADC2_EOCA_DMA_TRIG_SELECT AOS_DMA1_4
|
||||
#define ADC2_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH4
|
||||
#define ADC2_EOCA_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM
|
||||
#define ADC2_EOCA_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO
|
||||
#define ADC2_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC4
|
||||
#elif defined(BSP_UART8_RX_USING_DMA) && !defined(UART8_RX_DMA_INSTANCE)
|
||||
#define UART8_RX_DMA_INSTANCE CM_DMA1
|
||||
#define UART8_RX_DMA_CHANNEL DMA_CH4
|
||||
#define UART8_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define UART8_RX_DMA_TRIG_SELECT AOS_DMA1_4
|
||||
#define UART8_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4
|
||||
#define UART8_RX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM
|
||||
#define UART8_RX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO
|
||||
#define UART8_RX_DMA_INT_SRC INT_SRC_DMA1_TC4
|
||||
#endif
|
||||
|
||||
/* DMA1 ch5 */
|
||||
#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
|
||||
#define SPI3_TX_DMA_INSTANCE CM_DMA1
|
||||
#define SPI3_TX_DMA_CHANNEL DMA_CH5
|
||||
#define SPI3_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define SPI3_TX_DMA_TRIG_SELECT AOS_DMA1_5
|
||||
#define SPI3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5
|
||||
#define SPI3_TX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM
|
||||
#define SPI3_TX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO
|
||||
#define SPI3_TX_DMA_INT_SRC INT_SRC_DMA1_TC5
|
||||
#elif defined(BSP_I2C3_RX_USING_DMA) && !defined(I2C3_RX_DMA_INSTANCE)
|
||||
#define I2C3_RX_DMA_INSTANCE CM_DMA1
|
||||
#define I2C3_RX_DMA_CHANNEL DMA_CH5
|
||||
#define I2C3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define I2C3_RX_DMA_TRIG_SELECT AOS_DMA1_5
|
||||
#define I2C3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5
|
||||
#define I2C3_RX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM
|
||||
#define I2C3_RX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO
|
||||
#define I2C3_RX_DMA_INT_SRC INT_SRC_DMA1_TC5
|
||||
#elif defined(BSP_ADC3_USING_DMA) && !defined(ADC3_EOCA_DMA_INSTANCE)
|
||||
#define ADC3_EOCA_DMA_INSTANCE CM_DMA1
|
||||
#define ADC3_EOCA_DMA_CHANNEL DMA_CH5
|
||||
#define ADC3_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define ADC3_EOCA_DMA_TRIG_SELECT AOS_DMA1_5
|
||||
#define ADC3_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH5
|
||||
#define ADC3_EOCA_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM
|
||||
#define ADC3_EOCA_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO
|
||||
#define ADC3_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC5
|
||||
#elif defined(BSP_UART8_TX_USING_DMA) && !defined(UART8_TX_DMA_INSTANCE)
|
||||
#define UART8_TX_DMA_INSTANCE CM_DMA1
|
||||
#define UART8_TX_DMA_CHANNEL DMA_CH5
|
||||
#define UART8_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define UART8_TX_DMA_TRIG_SELECT AOS_DMA1_5
|
||||
#define UART8_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5
|
||||
#define UART8_TX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM
|
||||
#define UART8_TX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO
|
||||
#define UART8_TX_DMA_INT_SRC INT_SRC_DMA1_TC5
|
||||
#endif
|
||||
|
||||
/* DMA1 ch6 */
|
||||
#if defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
|
||||
#define SPI4_RX_DMA_INSTANCE CM_DMA1
|
||||
#define SPI4_RX_DMA_CHANNEL DMA_CH6
|
||||
#define SPI4_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define SPI4_RX_DMA_TRIG_SELECT AOS_DMA1_6
|
||||
#define SPI4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6
|
||||
#define SPI4_RX_DMA_IRQn BSP_DMA1_CH6_IRQ_NUM
|
||||
#define SPI4_RX_DMA_INT_PRIO BSP_DMA1_CH6_IRQ_PRIO
|
||||
#define SPI4_RX_DMA_INT_SRC INT_SRC_DMA1_TC6
|
||||
#elif defined(BSP_I2C4_TX_USING_DMA) && !defined(I2C4_TX_DMA_INSTANCE)
|
||||
#define I2C4_TX_DMA_INSTANCE CM_DMA1
|
||||
#define I2C4_TX_DMA_CHANNEL DMA_CH6
|
||||
#define I2C4_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define I2C4_TX_DMA_TRIG_SELECT AOS_DMA1_6
|
||||
#define I2C4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6
|
||||
#define I2C4_TX_DMA_IRQn BSP_DMA1_CH6_IRQ_NUM
|
||||
#define I2C4_TX_DMA_INT_PRIO BSP_DMA1_CH6_IRQ_PRIO
|
||||
#define I2C4_TX_DMA_INT_SRC INT_SRC_DMA1_TC6
|
||||
#elif defined(BSP_UART9_RX_USING_DMA) && !defined(UART9_RX_DMA_INSTANCE)
|
||||
#define UART9_RX_DMA_INSTANCE CM_DMA1
|
||||
#define UART9_RX_DMA_CHANNEL DMA_CH6
|
||||
#define UART9_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define UART9_RX_DMA_TRIG_SELECT AOS_DMA1_6
|
||||
#define UART9_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6
|
||||
#define UART9_RX_DMA_IRQn BSP_DMA1_CH6_IRQ_NUM
|
||||
#define UART9_RX_DMA_INT_PRIO BSP_DMA1_CH6_IRQ_PRIO
|
||||
#define UART9_RX_DMA_INT_SRC INT_SRC_DMA1_TC6
|
||||
#endif
|
||||
|
||||
/* DMA1 ch7 */
|
||||
#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
|
||||
#define SPI4_TX_DMA_INSTANCE CM_DMA1
|
||||
#define SPI4_TX_DMA_CHANNEL DMA_CH7
|
||||
#define SPI4_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define SPI4_TX_DMA_TRIG_SELECT AOS_DMA1_7
|
||||
#define SPI4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7
|
||||
#define SPI4_TX_DMA_IRQn BSP_DMA1_CH7_IRQ_NUM
|
||||
#define SPI4_TX_DMA_INT_PRIO BSP_DMA1_CH7_IRQ_PRIO
|
||||
#define SPI4_TX_DMA_INT_SRC INT_SRC_DMA1_TC7
|
||||
#elif defined(BSP_I2C4_RX_USING_DMA) && !defined(I2C4_RX_DMA_INSTANCE)
|
||||
#define I2C4_RX_DMA_INSTANCE CM_DMA1
|
||||
#define I2C4_RX_DMA_CHANNEL DMA_CH7
|
||||
#define I2C4_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define I2C4_RX_DMA_TRIG_SELECT AOS_DMA1_7
|
||||
#define I2C4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7
|
||||
#define I2C4_RX_DMA_IRQn BSP_DMA1_CH7_IRQ_NUM
|
||||
#define I2C4_RX_DMA_INT_PRIO BSP_DMA1_CH7_IRQ_PRIO
|
||||
#define I2C4_RX_DMA_INT_SRC INT_SRC_DMA1_TC7
|
||||
#elif defined(BSP_UART9_TX_USING_DMA) && !defined(UART9_TX_DMA_INSTANCE)
|
||||
#define UART9_TX_DMA_INSTANCE CM_DMA1
|
||||
#define UART9_TX_DMA_CHANNEL DMA_CH7
|
||||
#define UART9_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define UART9_TX_DMA_TRIG_SELECT AOS_DMA1_7
|
||||
#define UART9_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7
|
||||
#define UART9_TX_DMA_IRQn BSP_DMA1_CH7_IRQ_NUM
|
||||
#define UART9_TX_DMA_INT_PRIO BSP_DMA1_CH7_IRQ_PRIO
|
||||
#define UART9_TX_DMA_INT_SRC INT_SRC_DMA1_TC7
|
||||
#endif
|
||||
|
||||
/* DMA1 ch8 */
|
||||
#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
|
||||
#define SPI5_TX_DMA_INSTANCE CM_DMA1
|
||||
#define SPI5_TX_DMA_CHANNEL DMA_CH8
|
||||
#define SPI5_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define SPI5_TX_DMA_TRIG_SELECT AOS_DMA1_8
|
||||
#define SPI5_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH8
|
||||
#define SPI5_TX_DMA_IRQn BSP_DMA1_CH8_IRQ_NUM
|
||||
#define SPI5_TX_DMA_INT_PRIO BSP_DMA1_CH8_IRQ_PRIO
|
||||
#define SPI5_TX_DMA_INT_SRC INT_SRC_DMA1_TC8
|
||||
#endif
|
||||
|
||||
/* DMA1 ch9 */
|
||||
#if defined(BSP_SPI6_TX_USING_DMA) && !defined(SPI6_TX_DMA_INSTANCE)
|
||||
#define SPI6_TX_DMA_INSTANCE CM_DMA1
|
||||
#define SPI6_TX_DMA_CHANNEL DMA_CH9
|
||||
#define SPI6_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define SPI6_TX_DMA_TRIG_SELECT AOS_DMA1_9
|
||||
#define SPI6_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH9
|
||||
#define SPI6_TX_DMA_IRQn BSP_DMA1_CH9_IRQ_NUM
|
||||
#define SPI6_TX_DMA_INT_PRIO BSP_DMA1_CH9_IRQ_PRIO
|
||||
#define SPI6_TX_DMA_INT_SRC INT_SRC_DMA1_TC9
|
||||
#endif
|
||||
|
||||
/* DMA2 ch0 */
|
||||
#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
|
||||
#define UART1_RX_DMA_INSTANCE CM_DMA2
|
||||
#define UART1_RX_DMA_CHANNEL DMA_CH0
|
||||
#define UART1_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
|
||||
#define UART1_RX_DMA_TRIG_SELECT AOS_DMA2_0
|
||||
#define UART1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
|
||||
#define UART1_RX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM
|
||||
#define UART1_RX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO
|
||||
#define UART1_RX_DMA_INT_SRC INT_SRC_DMA2_TC0
|
||||
#elif defined(BSP_I2C5_TX_USING_DMA) && !defined(I2C5_TX_DMA_INSTANCE)
|
||||
#define I2C5_TX_DMA_INSTANCE CM_DMA2
|
||||
#define I2C5_TX_DMA_CHANNEL DMA_CH0
|
||||
#define I2C5_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
|
||||
#define I2C5_TX_DMA_TRIG_SELECT AOS_DMA2_0
|
||||
#define I2C5_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
|
||||
#define I2C5_TX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM
|
||||
#define I2C5_TX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO
|
||||
#define I2C5_TX_DMA_INT_SRC INT_SRC_DMA2_TC0
|
||||
#endif
|
||||
|
||||
/* DMA2 ch1 */
|
||||
#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
|
||||
#define UART1_TX_DMA_INSTANCE CM_DMA2
|
||||
#define UART1_TX_DMA_CHANNEL DMA_CH1
|
||||
#define UART1_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
|
||||
#define UART1_TX_DMA_TRIG_SELECT AOS_DMA2_1
|
||||
#define UART1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
|
||||
#define UART1_TX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM
|
||||
#define UART1_TX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO
|
||||
#define UART1_TX_DMA_INT_SRC INT_SRC_DMA2_TC1
|
||||
#elif defined(BSP_I2C5_RX_USING_DMA) && !defined(I2C5_RX_DMA_INSTANCE)
|
||||
#define I2C5_RX_DMA_INSTANCE CM_DMA2
|
||||
#define I2C5_RX_DMA_CHANNEL DMA_CH1
|
||||
#define I2C5_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
|
||||
#define I2C5_RX_DMA_TRIG_SELECT AOS_DMA2_1
|
||||
#define I2C5_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
|
||||
#define I2C5_RX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM
|
||||
#define I2C5_RX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO
|
||||
#define I2C5_RX_DMA_INT_SRC INT_SRC_DMA2_TC1
|
||||
#endif
|
||||
|
||||
/* DMA2 ch2 */
|
||||
#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
|
||||
#define UART2_RX_DMA_INSTANCE CM_DMA2
|
||||
#define UART2_RX_DMA_CHANNEL DMA_CH2
|
||||
#define UART2_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
|
||||
#define UART2_RX_DMA_TRIG_SELECT AOS_DMA2_2
|
||||
#define UART2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
|
||||
#define UART2_RX_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM
|
||||
#define UART2_RX_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO
|
||||
#define UART2_RX_DMA_INT_SRC INT_SRC_DMA2_TC2
|
||||
#elif defined(BSP_I2C6_TX_USING_DMA) && !defined(I2C6_TX_DMA_INSTANCE)
|
||||
#define I2C6_TX_DMA_INSTANCE CM_DMA2
|
||||
#define I2C6_TX_DMA_CHANNEL DMA_CH2
|
||||
#define I2C6_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
|
||||
#define I2C6_TX_DMA_TRIG_SELECT AOS_DMA2_2
|
||||
#define I2C6_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
|
||||
#define I2C6_TX_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM
|
||||
#define I2C6_TX_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO
|
||||
#define I2C6_TX_DMA_INT_SRC INT_SRC_DMA2_TC2
|
||||
#endif
|
||||
|
||||
/* DMA2 ch3 */
|
||||
#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
|
||||
#define UART2_TX_DMA_INSTANCE CM_DMA2
|
||||
#define UART2_TX_DMA_CHANNEL DMA_CH3
|
||||
#define UART2_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
|
||||
#define UART2_TX_DMA_TRIG_SELECT AOS_DMA2_3
|
||||
#define UART2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
|
||||
#define UART2_TX_DMA_IRQn BSP_DMA2_CH3_IRQ_NUM
|
||||
#define UART2_TX_DMA_INT_PRIO BSP_DMA2_CH3_IRQ_PRIO
|
||||
#define UART2_TX_DMA_INT_SRC INT_SRC_DMA2_TC3
|
||||
#elif defined(BSP_I2C6_RX_USING_DMA) && !defined(I2C6_RX_DMA_INSTANCE)
|
||||
#define I2C6_RX_DMA_INSTANCE CM_DMA2
|
||||
#define I2C6_RX_DMA_CHANNEL DMA_CH3
|
||||
#define I2C6_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
|
||||
#define I2C6_RX_DMA_TRIG_SELECT AOS_DMA2_3
|
||||
#define I2C6_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
|
||||
#define I2C6_RX_DMA_IRQn BSP_DMA2_CH3_IRQ_NUM
|
||||
#define I2C6_RX_DMA_INT_PRIO BSP_DMA2_CH3_IRQ_PRIO
|
||||
#define I2C6_RX_DMA_INT_SRC INT_SRC_DMA2_TC3
|
||||
#endif
|
||||
|
||||
/* DMA2 ch4 */
|
||||
#if defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE)
|
||||
#define UART5_RX_DMA_INSTANCE CM_DMA2
|
||||
#define UART5_RX_DMA_CHANNEL DMA_CH4
|
||||
#define UART5_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
|
||||
#define UART5_RX_DMA_TRIG_SELECT AOS_DMA2_4
|
||||
#define UART5_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4
|
||||
#define UART5_RX_DMA_IRQn BSP_DMA2_CH4_IRQ_NUM
|
||||
#define UART5_RX_DMA_INT_PRIO BSP_DMA2_CH4_IRQ_PRIO
|
||||
#define UART5_RX_DMA_INT_SRC INT_SRC_DMA2_TC4
|
||||
#elif defined(BSP_UART6_RX_USING_DMA) && !defined(UART6_RX_DMA_INSTANCE)
|
||||
#define UART6_RX_DMA_INSTANCE CM_DMA2
|
||||
#define UART6_RX_DMA_CHANNEL DMA_CH4
|
||||
#define UART6_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
|
||||
#define UART6_RX_DMA_TRIG_SELECT AOS_DMA2_4
|
||||
#define UART6_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4
|
||||
#define UART6_RX_DMA_IRQn BSP_DMA2_CH4_IRQ_NUM
|
||||
#define UART6_RX_DMA_INT_PRIO BSP_DMA2_CH4_IRQ_PRIO
|
||||
#define UART6_RX_DMA_INT_SRC INT_SRC_DMA2_TC4
|
||||
#endif
|
||||
|
||||
/* DMA2 ch5 */
|
||||
#if defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE)
|
||||
#define UART5_TX_DMA_INSTANCE CM_DMA2
|
||||
#define UART5_TX_DMA_CHANNEL DMA_CH5
|
||||
#define UART5_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
|
||||
#define UART5_TX_DMA_TRIG_SELECT AOS_DMA2_5
|
||||
#define UART5_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5
|
||||
#define UART5_TX_DMA_IRQn BSP_DMA2_CH5_IRQ_NUM
|
||||
#define UART5_TX_DMA_INT_PRIO BSP_DMA2_CH5_IRQ_PRIO
|
||||
#define UART5_TX_DMA_INT_SRC INT_SRC_DMA2_TC5
|
||||
#elif defined(BSP_UART6_TX_USING_DMA) && !defined(UART6_TX_DMA_INSTANCE)
|
||||
#define UART6_TX_DMA_INSTANCE CM_DMA2
|
||||
#define UART6_TX_DMA_CHANNEL DMA_CH5
|
||||
#define UART6_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
|
||||
#define UART6_TX_DMA_TRIG_SELECT AOS_DMA2_5
|
||||
#define UART6_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5
|
||||
#define UART6_TX_DMA_IRQn BSP_DMA2_CH5_IRQ_NUM
|
||||
#define UART6_TX_DMA_INT_PRIO BSP_DMA2_CH5_IRQ_PRIO
|
||||
#define UART6_TX_DMA_INT_SRC INT_SRC_DMA2_TC5
|
||||
#endif
|
||||
|
||||
/* DMA2 ch6 */
|
||||
#if defined(BSP_UART7_RX_USING_DMA) && !defined(UART7_RX_DMA_INSTANCE)
|
||||
#define UART7_RX_DMA_INSTANCE CM_DMA2
|
||||
#define UART7_RX_DMA_CHANNEL DMA_CH6
|
||||
#define UART7_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
|
||||
#define UART7_RX_DMA_TRIG_SELECT AOS_DMA2_6
|
||||
#define UART7_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6
|
||||
#define UART7_RX_DMA_IRQn BSP_DMA2_CH6_IRQ_NUM
|
||||
#define UART7_RX_DMA_INT_PRIO BSP_DMA2_CH6_IRQ_PRIO
|
||||
#define UART7_RX_DMA_INT_SRC INT_SRC_DMA2_TC6
|
||||
#elif defined(BSP_UART10_RX_USING_DMA) && !defined(UART10_RX_DMA_INSTANCE)
|
||||
#define UART10_RX_DMA_INSTANCE CM_DMA2
|
||||
#define UART10_RX_DMA_CHANNEL DMA_CH6
|
||||
#define UART10_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
|
||||
#define UART10_RX_DMA_TRIG_SELECT AOS_DMA2_6
|
||||
#define UART10_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6
|
||||
#define UART10_RX_DMA_IRQn BSP_DMA2_CH6_IRQ_NUM
|
||||
#define UART10_RX_DMA_INT_PRIO BSP_DMA2_CH6_IRQ_PRIO
|
||||
#define UART10_RX_DMA_INT_SRC INT_SRC_DMA2_TC6
|
||||
#endif
|
||||
|
||||
/* DMA2 ch7 */
|
||||
#if defined(BSP_UART7_TX_USING_DMA) && !defined(UART7_TX_DMA_INSTANCE)
|
||||
#define UART7_TX_DMA_INSTANCE CM_DMA2
|
||||
#define UART7_TX_DMA_CHANNEL DMA_CH7
|
||||
#define UART7_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
|
||||
#define UART7_TX_DMA_TRIG_SELECT AOS_DMA2_7
|
||||
#define UART7_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7
|
||||
#define UART7_TX_DMA_IRQn BSP_DMA2_CH7_IRQ_NUM
|
||||
#define UART7_TX_DMA_INT_PRIO BSP_DMA2_CH7_IRQ_PRIO
|
||||
#define UART7_TX_DMA_INT_SRC INT_SRC_DMA2_TC7
|
||||
#elif defined(BSP_UART10_TX_USING_DMA) && !defined(UART10_TX_DMA_INSTANCE)
|
||||
#define UART10_TX_DMA_INSTANCE CM_DMA2
|
||||
#define UART10_TX_DMA_CHANNEL DMA_CH7
|
||||
#define UART10_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
|
||||
#define UART10_TX_DMA_TRIG_SELECT AOS_DMA2_7
|
||||
#define UART10_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7
|
||||
#define UART10_TX_DMA_IRQn BSP_DMA2_CH7_IRQ_NUM
|
||||
#define UART10_TX_DMA_INT_PRIO BSP_DMA2_CH7_IRQ_PRIO
|
||||
#define UART10_TX_DMA_INT_SRC INT_SRC_DMA2_TC7
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __DMA_CONFIG_H__ */
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __ETH_CONFIG_H__
|
||||
#define __ETH_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "irq_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(BSP_USING_ETH)
|
||||
|
||||
#ifndef ETH_IRQ_CONFIG
|
||||
#define ETH_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_ETH_IRQ_NUM, \
|
||||
.irq_prio = BSP_ETH_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_ETH_GLB_INT, \
|
||||
}
|
||||
#endif /* ETH_IRQ_CONFIG */
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ETH_CONFIG_H__ */
|
||||
|
|
@ -0,0 +1,175 @@
|
|||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __GPIO_CONFIG_H__
|
||||
#define __GPIO_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "irq_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(RT_USING_PIN)
|
||||
|
||||
#ifndef EXTINT0_IRQ_CONFIG
|
||||
#define EXTINT0_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT0_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT0_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ0, \
|
||||
}
|
||||
#endif /* EXTINT1_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT1_IRQ_CONFIG
|
||||
#define EXTINT1_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT1_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT1_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ1, \
|
||||
}
|
||||
#endif /* EXTINT1_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT2_IRQ_CONFIG
|
||||
#define EXTINT2_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT2_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT2_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ2, \
|
||||
}
|
||||
#endif /* EXTINT2_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT3_IRQ_CONFIG
|
||||
#define EXTINT3_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT3_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT3_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ3, \
|
||||
}
|
||||
#endif /* EXTINT3_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT4_IRQ_CONFIG
|
||||
#define EXTINT4_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT4_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT4_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ4, \
|
||||
}
|
||||
#endif /* EXTINT4_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT5_IRQ_CONFIG
|
||||
#define EXTINT5_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT5_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT5_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ5, \
|
||||
}
|
||||
#endif /* EXTINT5_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT6_IRQ_CONFIG
|
||||
#define EXTINT6_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT6_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT6_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ6, \
|
||||
}
|
||||
#endif /* EXTINT6_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT7_IRQ_CONFIG
|
||||
#define EXTINT7_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT7_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT7_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ7, \
|
||||
}
|
||||
#endif /* EXTINT7_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT8_IRQ_CONFIG
|
||||
#define EXTINT8_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT8_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT8_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ8, \
|
||||
}
|
||||
#endif /* EXTINT8_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT9_IRQ_CONFIG
|
||||
#define EXTINT9_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT9_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT9_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ9, \
|
||||
}
|
||||
#endif /* EXTINT9_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT10_IRQ_CONFIG
|
||||
#define EXTINT10_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT10_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT10_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ10, \
|
||||
}
|
||||
#endif /* EXTINT10_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT11_IRQ_CONFIG
|
||||
#define EXTINT11_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT11_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT11_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ11, \
|
||||
}
|
||||
#endif /* EXTINT11_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT12_IRQ_CONFIG
|
||||
#define EXTINT12_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT12_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT12_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ12, \
|
||||
}
|
||||
#endif /* EXTINT12_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT13_IRQ_CONFIG
|
||||
#define EXTINT13_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT13_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT13_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ13, \
|
||||
}
|
||||
#endif /* EXTINT13_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT14_IRQ_CONFIG
|
||||
#define EXTINT14_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT14_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT14_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ14, \
|
||||
}
|
||||
#endif /* EXTINT14_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT15_IRQ_CONFIG
|
||||
#define EXTINT15_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT15_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT15_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ15, \
|
||||
}
|
||||
#endif /* EXTINT15_IRQ_CONFIG */
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __GPIO_CONFIG_H__ */
|
||||
|
|
@ -0,0 +1,331 @@
|
|||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __I2C_CONFIG_H__
|
||||
#define __I2C_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "irq_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_I2C1)
|
||||
#ifndef I2C1_CONFIG
|
||||
#define I2C1_CONFIG \
|
||||
{ \
|
||||
.name = "i2c1", \
|
||||
.Instance = CM_I2C1, \
|
||||
.clock = FCG1_PERIPH_I2C1, \
|
||||
.baudrate = 100000UL, \
|
||||
.timeout = 10000UL, \
|
||||
}
|
||||
#endif /* I2C1_CONFIG */
|
||||
#endif
|
||||
|
||||
#if defined(BSP_I2C1_USING_DMA)
|
||||
#ifndef I2C1_TX_DMA_CONFIG
|
||||
#define I2C1_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = I2C1_TX_DMA_INSTANCE, \
|
||||
.channel = I2C1_TX_DMA_CHANNEL, \
|
||||
.clock = I2C1_TX_DMA_CLOCK, \
|
||||
.trigger_select = I2C1_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_I2C1_TEI, \
|
||||
.flag = I2C1_TX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = I2C1_TX_DMA_IRQn, \
|
||||
.irq_prio = I2C1_TX_DMA_INT_PRIO, \
|
||||
.int_src = I2C1_TX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* I2C1_TX_DMA_CONFIG */
|
||||
|
||||
#ifndef I2C1_RX_DMA_CONFIG
|
||||
#define I2C1_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = I2C1_RX_DMA_INSTANCE, \
|
||||
.channel = I2C1_RX_DMA_CHANNEL, \
|
||||
.clock = I2C1_RX_DMA_CLOCK, \
|
||||
.trigger_select = I2C1_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_I2C1_RXI, \
|
||||
.flag = I2C1_RX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = I2C1_RX_DMA_IRQn, \
|
||||
.irq_prio = I2C1_RX_DMA_INT_PRIO, \
|
||||
.int_src = I2C1_RX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* I2C1_RX_DMA_CONFIG */
|
||||
#endif /* BSP_I2C1_USING_DMA */
|
||||
|
||||
#if defined(BSP_USING_I2C2)
|
||||
#ifndef I2C2_CONFIG
|
||||
#define I2C2_CONFIG \
|
||||
{ \
|
||||
.name = "i2c2", \
|
||||
.Instance = CM_I2C2, \
|
||||
.clock = FCG1_PERIPH_I2C2, \
|
||||
.baudrate = 100000UL, \
|
||||
.timeout = 10000UL, \
|
||||
}
|
||||
#endif /* I2C2_CONFIG */
|
||||
|
||||
#if defined(BSP_I2C2_USING_DMA)
|
||||
#ifndef I2C2_TX_DMA_CONFIG
|
||||
#define I2C2_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = I2C2_TX_DMA_INSTANCE, \
|
||||
.channel = I2C2_TX_DMA_CHANNEL, \
|
||||
.clock = I2C2_TX_DMA_CLOCK, \
|
||||
.trigger_select = I2C2_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_I2C2_TEI, \
|
||||
.flag = I2C2_TX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = I2C2_TX_DMA_IRQn, \
|
||||
.irq_prio = I2C2_TX_DMA_INT_PRIO, \
|
||||
.int_src = I2C2_TX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* I2C2_TX_DMA_CONFIG */
|
||||
|
||||
#ifndef I2C2_RX_DMA_CONFIG
|
||||
#define I2C2_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = I2C2_RX_DMA_INSTANCE, \
|
||||
.channel = I2C2_RX_DMA_CHANNEL, \
|
||||
.clock = I2C2_RX_DMA_CLOCK, \
|
||||
.trigger_select = I2C2_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_I2C2_RXI, \
|
||||
.flag = I2C2_RX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = I2C2_RX_DMA_IRQn, \
|
||||
.irq_prio = I2C2_RX_DMA_INT_PRIO, \
|
||||
.int_src = I2C2_RX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* I2C2_RX_DMA_CONFIG */
|
||||
#endif /* BSP_I2C2_USING_DMA */
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_I2C3)
|
||||
#ifndef I2C3_CONFIG
|
||||
#define I2C3_CONFIG \
|
||||
{ \
|
||||
.name = "i2c3", \
|
||||
.Instance = CM_I2C3, \
|
||||
.clock = FCG1_PERIPH_I2C3, \
|
||||
.baudrate = 100000UL, \
|
||||
.timeout = 10000UL, \
|
||||
}
|
||||
#endif /* I2C3_CONFIG */
|
||||
|
||||
#if defined(BSP_I2C3_USING_DMA)
|
||||
#ifndef I2C3_TX_DMA_CONFIG
|
||||
#define I2C3_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = I2C3_TX_DMA_INSTANCE, \
|
||||
.channel = I2C3_TX_DMA_CHANNEL, \
|
||||
.clock = I2C3_TX_DMA_CLOCK, \
|
||||
.trigger_select = I2C3_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_I2C3_TEI, \
|
||||
.flag = I2C3_TX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = I2C3_TX_DMA_IRQn, \
|
||||
.irq_prio = I2C3_TX_DMA_INT_PRIO, \
|
||||
.int_src = I2C3_TX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* I2C3_TX_DMA_CONFIG */
|
||||
|
||||
#ifndef I2C3_RX_DMA_CONFIG
|
||||
#define I2C3_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = I2C3_RX_DMA_INSTANCE, \
|
||||
.channel = I2C3_RX_DMA_CHANNEL, \
|
||||
.clock = I2C3_RX_DMA_CLOCK, \
|
||||
.trigger_select = I2C3_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_I2C3_RXI, \
|
||||
.flag = I2C3_RX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = I2C3_RX_DMA_IRQn, \
|
||||
.irq_prio = I2C3_RX_DMA_INT_PRIO, \
|
||||
.int_src = I2C3_RX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* I2C3_RX_DMA_CONFIG */
|
||||
#endif /* BSP_I2C3_USING_DMA */
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_I2C4)
|
||||
#ifndef I2C4_CONFIG
|
||||
#define I2C4_CONFIG \
|
||||
{ \
|
||||
.name = "i2c4", \
|
||||
.Instance = CM_I2C4, \
|
||||
.clock = FCG1_PERIPH_I2C4, \
|
||||
.baudrate = 100000UL, \
|
||||
.timeout = 10000UL, \
|
||||
}
|
||||
#endif /* I2C4_CONFIG */
|
||||
|
||||
#if defined(BSP_I2C4_USING_DMA)
|
||||
#ifndef I2C4_TX_DMA_CONFIG
|
||||
#define I2C4_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = I2C4_TX_DMA_INSTANCE, \
|
||||
.channel = I2C4_TX_DMA_CHANNEL, \
|
||||
.clock = I2C4_TX_DMA_CLOCK, \
|
||||
.trigger_select = I2C4_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_I2C4_TEI, \
|
||||
.flag = I2C4_TX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = I2C4_TX_DMA_IRQn, \
|
||||
.irq_prio = I2C4_TX_DMA_INT_PRIO, \
|
||||
.int_src = I2C4_TX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* I2C4_TX_DMA_CONFIG */
|
||||
|
||||
#ifndef I2C4_RX_DMA_CONFIG
|
||||
#define I2C4_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = I2C4_RX_DMA_INSTANCE, \
|
||||
.channel = I2C4_RX_DMA_CHANNEL, \
|
||||
.clock = I2C4_RX_DMA_CLOCK, \
|
||||
.trigger_select = I2C4_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_I2C4_RXI, \
|
||||
.flag = I2C4_RX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = I2C4_RX_DMA_IRQn, \
|
||||
.irq_prio = I2C4_RX_DMA_INT_PRIO, \
|
||||
.int_src = I2C4_RX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* I2C4_RX_DMA_CONFIG */
|
||||
#endif /* BSP_I2C4_USING_DMA */
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_I2C5)
|
||||
#ifndef I2C5_CONFIG
|
||||
#define I2C5_CONFIG \
|
||||
{ \
|
||||
.name = "i2c5", \
|
||||
.Instance = CM_I2C5, \
|
||||
.clock = FCG1_PERIPH_I2C5, \
|
||||
.baudrate = 100000UL, \
|
||||
.timeout = 10000UL, \
|
||||
}
|
||||
#endif /* I2C5_CONFIG */
|
||||
|
||||
#if defined(BSP_I2C5_USING_DMA)
|
||||
#ifndef I2C5_TX_DMA_CONFIG
|
||||
#define I2C5_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = I2C5_TX_DMA_INSTANCE, \
|
||||
.channel = I2C5_TX_DMA_CHANNEL, \
|
||||
.clock = I2C5_TX_DMA_CLOCK, \
|
||||
.trigger_select = I2C5_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_I2C5_TEI, \
|
||||
.flag = I2C5_TX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = I2C5_TX_DMA_IRQn, \
|
||||
.irq_prio = I2C5_TX_DMA_INT_PRIO, \
|
||||
.int_src = I2C5_TX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* I2C5_TX_DMA_CONFIG */
|
||||
|
||||
#ifndef I2C5_RX_DMA_CONFIG
|
||||
#define I2C5_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = I2C5_RX_DMA_INSTANCE, \
|
||||
.channel = I2C5_RX_DMA_CHANNEL, \
|
||||
.clock = I2C5_RX_DMA_CLOCK, \
|
||||
.trigger_select = I2C5_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_I2C5_RXI, \
|
||||
.flag = I2C5_RX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = I2C5_RX_DMA_IRQn, \
|
||||
.irq_prio = I2C5_RX_DMA_INT_PRIO, \
|
||||
.int_src = I2C5_RX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* I2C5_RX_DMA_CONFIG */
|
||||
#endif /* BSP_I2C5_USING_DMA */
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_I2C6)
|
||||
#ifndef I2C6_CONFIG
|
||||
#define I2C6_CONFIG \
|
||||
{ \
|
||||
.name = "i2c6", \
|
||||
.Instance = CM_I2C6, \
|
||||
.clock = FCG1_PERIPH_I2C6, \
|
||||
.baudrate = 100000UL, \
|
||||
.timeout = 10000UL, \
|
||||
}
|
||||
#endif /* I2C6_CONFIG */
|
||||
|
||||
#if defined(BSP_I2C6_USING_DMA)
|
||||
#ifndef I2C6_TX_DMA_CONFIG
|
||||
#define I2C6_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = I2C6_TX_DMA_INSTANCE, \
|
||||
.channel = I2C6_TX_DMA_CHANNEL, \
|
||||
.clock = I2C6_TX_DMA_CLOCK, \
|
||||
.trigger_select = I2C6_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_I2C6_TEI, \
|
||||
.flag = I2C6_TX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = I2C6_TX_DMA_IRQn, \
|
||||
.irq_prio = I2C6_TX_DMA_INT_PRIO, \
|
||||
.int_src = I2C6_TX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* I2C6_TX_DMA_CONFIG */
|
||||
|
||||
#ifndef I2C6_RX_DMA_CONFIG
|
||||
#define I2C6_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = I2C6_RX_DMA_INSTANCE, \
|
||||
.channel = I2C6_RX_DMA_CHANNEL, \
|
||||
.clock = I2C6_RX_DMA_CLOCK, \
|
||||
.trigger_select = I2C6_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_I2C6_RXI, \
|
||||
.flag = I2C6_RX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = I2C6_RX_DMA_IRQn, \
|
||||
.irq_prio = I2C6_RX_DMA_INT_PRIO, \
|
||||
.int_src = I2C6_RX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* I2C6_RX_DMA_CONFIG */
|
||||
#endif /* BSP_I2C6_USING_DMA */
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,608 @@
|
|||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __IRQ_CONFIG_H__
|
||||
#define __IRQ_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define BSP_EXTINT0_IRQ_NUM INT022_IRQn
|
||||
#define BSP_EXTINT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_EXTINT1_IRQ_NUM INT023_IRQn
|
||||
#define BSP_EXTINT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_EXTINT2_IRQ_NUM INT024_IRQn
|
||||
#define BSP_EXTINT2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_EXTINT3_IRQ_NUM INT025_IRQn
|
||||
#define BSP_EXTINT3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_EXTINT4_IRQ_NUM INT026_IRQn
|
||||
#define BSP_EXTINT4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_EXTINT5_IRQ_NUM INT027_IRQn
|
||||
#define BSP_EXTINT5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_EXTINT6_IRQ_NUM INT028_IRQn
|
||||
#define BSP_EXTINT6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_EXTINT7_IRQ_NUM INT029_IRQn
|
||||
#define BSP_EXTINT7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_EXTINT8_IRQ_NUM INT030_IRQn
|
||||
#define BSP_EXTINT8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_EXTINT9_IRQ_NUM INT031_IRQn
|
||||
#define BSP_EXTINT9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_EXTINT10_IRQ_NUM INT032_IRQn
|
||||
#define BSP_EXTINT10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_EXTINT11_IRQ_NUM INT033_IRQn
|
||||
#define BSP_EXTINT11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_EXTINT12_IRQ_NUM INT034_IRQn
|
||||
#define BSP_EXTINT12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_EXTINT13_IRQ_NUM INT035_IRQn
|
||||
#define BSP_EXTINT13_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_EXTINT14_IRQ_NUM INT036_IRQn
|
||||
#define BSP_EXTINT14_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_EXTINT15_IRQ_NUM INT037_IRQn
|
||||
#define BSP_EXTINT15_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
|
||||
/* DMA1 ch0 */
|
||||
#define BSP_DMA1_CH0_IRQ_NUM INT038_IRQn
|
||||
#define BSP_DMA1_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
/* DMA1 ch1 */
|
||||
#define BSP_DMA1_CH1_IRQ_NUM INT039_IRQn
|
||||
#define BSP_DMA1_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
/* DMA1 ch2 */
|
||||
#define BSP_DMA1_CH2_IRQ_NUM INT040_IRQn
|
||||
#define BSP_DMA1_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
/* DMA1 ch3 */
|
||||
#define BSP_DMA1_CH3_IRQ_NUM INT041_IRQn
|
||||
#define BSP_DMA1_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
/* DMA1 ch4 */
|
||||
#define BSP_DMA1_CH4_IRQ_NUM INT042_IRQn
|
||||
#define BSP_DMA1_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
/* DMA1 ch5 */
|
||||
#define BSP_DMA1_CH5_IRQ_NUM INT043_IRQn
|
||||
#define BSP_DMA1_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
/* DMA1 ch6 */
|
||||
#define BSP_DMA1_CH6_IRQ_NUM INT018_IRQn
|
||||
#define BSP_DMA1_CH6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
/* DMA1 ch7 */
|
||||
#define BSP_DMA1_CH7_IRQ_NUM INT019_IRQn
|
||||
#define BSP_DMA1_CH7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
/* DMA1 ch8 */
|
||||
#define BSP_DMA1_CH8_IRQ_NUM INT020_IRQn
|
||||
#define BSP_DMA1_CH8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
/* DMA1 ch9 */
|
||||
#define BSP_DMA1_CH9_IRQ_NUM INT021_IRQn
|
||||
#define BSP_DMA1_CH9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
|
||||
/* DMA2 ch0 */
|
||||
#define BSP_DMA2_CH0_IRQ_NUM INT044_IRQn
|
||||
#define BSP_DMA2_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
/* DMA2 ch1 */
|
||||
#define BSP_DMA2_CH1_IRQ_NUM INT045_IRQn
|
||||
#define BSP_DMA2_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
/* DMA2 ch2 */
|
||||
#define BSP_DMA2_CH2_IRQ_NUM INT046_IRQn
|
||||
#define BSP_DMA2_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
/* DMA2 ch3 */
|
||||
#define BSP_DMA2_CH3_IRQ_NUM INT047_IRQn
|
||||
#define BSP_DMA2_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
/* DMA2 ch4 */
|
||||
#define BSP_DMA2_CH4_IRQ_NUM INT048_IRQn
|
||||
#define BSP_DMA2_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
/* DMA2 ch5 */
|
||||
#define BSP_DMA2_CH5_IRQ_NUM INT049_IRQn
|
||||
#define BSP_DMA2_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
/* DMA2 ch6 */
|
||||
#define BSP_DMA2_CH6_IRQ_NUM INT020_IRQn
|
||||
#define BSP_DMA2_CH6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
/* DMA2 ch7 */
|
||||
#define BSP_DMA2_CH7_IRQ_NUM INT021_IRQn
|
||||
#define BSP_DMA2_CH7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
|
||||
#if defined(BSP_USING_ETH)
|
||||
#define BSP_ETH_IRQ_NUM INT104_IRQn
|
||||
#define BSP_ETH_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_UART1)
|
||||
#define BSP_UART1_RXERR_IRQ_NUM INT010_IRQn
|
||||
#define BSP_UART1_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_UART1_RX_IRQ_NUM INT089_IRQn
|
||||
#define BSP_UART1_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_UART1_TX_IRQ_NUM INT088_IRQn
|
||||
#define BSP_UART1_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
|
||||
#if defined(BSP_UART1_RX_USING_DMA)
|
||||
#define BSP_UART1_RXTO_IRQ_NUM INT006_IRQn
|
||||
#define BSP_UART1_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif
|
||||
|
||||
#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA)
|
||||
#define BSP_UART1_TX_CPLT_IRQ_NUM INT086_IRQn
|
||||
#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#elif defined(RT_USING_SERIAL_V2)
|
||||
#define BSP_UART1_TX_CPLT_IRQ_NUM INT086_IRQn
|
||||
#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif
|
||||
#endif /* BSP_USING_UART1 */
|
||||
|
||||
#if defined(BSP_USING_UART2)
|
||||
#define BSP_UART2_RXERR_IRQ_NUM INT011_IRQn
|
||||
#define BSP_UART2_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_UART2_RX_IRQ_NUM INT091_IRQn
|
||||
#define BSP_UART2_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_UART2_TX_IRQ_NUM INT090_IRQn
|
||||
#define BSP_UART2_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
|
||||
#if defined(BSP_UART2_RX_USING_DMA)
|
||||
#define BSP_UART2_RXTO_IRQ_NUM INT007_IRQn
|
||||
#define BSP_UART2_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif
|
||||
|
||||
#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA)
|
||||
#define BSP_UART2_TX_CPLT_IRQ_NUM INT087_IRQn
|
||||
#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#elif defined(RT_USING_SERIAL_V2)
|
||||
#define BSP_UART2_TX_CPLT_IRQ_NUM INT087_IRQn
|
||||
#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif
|
||||
#endif /* BSP_USING_UART2 */
|
||||
|
||||
#if defined(BSP_USING_UART3)
|
||||
#define BSP_UART3_RXERR_IRQ_NUM INT012_IRQn
|
||||
#define BSP_UART3_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_UART3_RX_IRQ_NUM INT095_IRQn
|
||||
#define BSP_UART3_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_UART3_TX_IRQ_NUM INT094_IRQn
|
||||
#define BSP_UART3_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
|
||||
#if defined(BSP_UART3_RX_USING_DMA)
|
||||
#define BSP_UART3_RXTO_IRQ_NUM INT068_IRQn
|
||||
#define BSP_UART3_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif
|
||||
|
||||
#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART3_TX_USING_DMA)
|
||||
#define BSP_UART3_TX_CPLT_IRQ_NUM INT092_IRQn
|
||||
#define BSP_UART3_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#elif defined(RT_USING_SERIAL_V2)
|
||||
#define BSP_UART3_TX_CPLT_IRQ_NUM INT092_IRQn
|
||||
#define BSP_UART3_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif
|
||||
#endif /* BSP_USING_UART3 */
|
||||
|
||||
#if defined(BSP_USING_UART4)
|
||||
#define BSP_UART4_RXERR_IRQ_NUM INT013_IRQn
|
||||
#define BSP_UART4_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_UART4_RX_IRQ_NUM INT097_IRQn
|
||||
#define BSP_UART4_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_UART4_TX_IRQ_NUM INT096_IRQn
|
||||
#define BSP_UART4_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
|
||||
#if defined(BSP_UART4_RX_USING_DMA)
|
||||
#define BSP_UART4_RXTO_IRQ_NUM INT069_IRQn
|
||||
#define BSP_UART4_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif
|
||||
|
||||
#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART4_TX_USING_DMA)
|
||||
#define BSP_UART4_TX_CPLT_IRQ_NUM INT093_IRQn
|
||||
#define BSP_UART4_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#elif defined(RT_USING_SERIAL_V2)
|
||||
#define BSP_UART4_TX_CPLT_IRQ_NUM INT093_IRQn
|
||||
#define BSP_UART4_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif
|
||||
#endif /* BSP_USING_UART4 */
|
||||
|
||||
#if defined(BSP_USING_UART5)
|
||||
#define BSP_UART5_RXERR_IRQ_NUM INT014_IRQn
|
||||
#define BSP_UART5_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_UART5_RX_IRQ_NUM INT101_IRQn
|
||||
#define BSP_UART5_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_UART5_TX_IRQ_NUM INT100_IRQn
|
||||
#define BSP_UART5_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
|
||||
#if defined(BSP_UART5_RX_USING_DMA)
|
||||
#define BSP_UART5_RXTO_IRQ_NUM INT070_IRQn
|
||||
#define BSP_UART5_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif
|
||||
|
||||
#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART5_TX_USING_DMA)
|
||||
#define BSP_UART5_TX_CPLT_IRQ_NUM INT098_IRQn
|
||||
#define BSP_UART5_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#elif defined(RT_USING_SERIAL_V2)
|
||||
#define BSP_UART5_TX_CPLT_IRQ_NUM INT098_IRQn
|
||||
#define BSP_UART5_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif
|
||||
#endif /* BSP_USING_UART5 */
|
||||
|
||||
#if defined(BSP_USING_UART6)
|
||||
#define BSP_UART6_RXERR_IRQ_NUM INT015_IRQn
|
||||
#define BSP_UART6_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_UART6_RX_IRQ_NUM INT103_IRQn
|
||||
#define BSP_UART6_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_UART6_TX_IRQ_NUM INT102_IRQn
|
||||
#define BSP_UART6_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
|
||||
#if defined(BSP_UART6_RX_USING_DMA)
|
||||
#define BSP_UART6_RXTO_IRQ_NUM INT008_IRQn
|
||||
#define BSP_UART6_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif
|
||||
|
||||
#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART6_TX_USING_DMA)
|
||||
#define BSP_UART6_TX_CPLT_IRQ_NUM INT099_IRQn
|
||||
#define BSP_UART6_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#elif defined(RT_USING_SERIAL_V2)
|
||||
#define BSP_UART6_TX_CPLT_IRQ_NUM INT099_IRQn
|
||||
#define BSP_UART6_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif
|
||||
#endif /* BSP_USING_UART6 */
|
||||
|
||||
#if defined(BSP_USING_UART7)
|
||||
#define BSP_UART7_RXERR_IRQ_NUM INT016_IRQn
|
||||
#define BSP_UART7_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_UART7_RX_IRQ_NUM INT107_IRQn
|
||||
#define BSP_UART7_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_UART7_TX_IRQ_NUM INT106_IRQn
|
||||
#define BSP_UART7_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
|
||||
#if defined(BSP_UART7_RX_USING_DMA)
|
||||
#define BSP_UART7_RXTO_IRQ_NUM INT009_IRQn
|
||||
#define BSP_UART7_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif
|
||||
|
||||
#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART7_TX_USING_DMA)
|
||||
#define BSP_UART7_TX_CPLT_IRQ_NUM INT105_IRQn
|
||||
#define BSP_UART7_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#elif defined(RT_USING_SERIAL_V2)
|
||||
#define BSP_UART7_TX_CPLT_IRQ_NUM INT105_IRQn
|
||||
#define BSP_UART7_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif
|
||||
#elif defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2)
|
||||
#define BSP_SPI1_ERR_IRQ_NUM INT009_IRQn
|
||||
#define BSP_SPI1_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_SPI2_ERR_IRQ_NUM INT016_IRQn
|
||||
#define BSP_SPI2_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif /* BSP_USING_UART7 */
|
||||
|
||||
#if defined(BSP_USING_SPI3)
|
||||
#define BSP_SPI3_ERR_IRQ_NUM INT092_IRQn
|
||||
#define BSP_SPI3_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_SPI4)
|
||||
#define BSP_SPI4_ERR_IRQ_NUM INT093_IRQn
|
||||
#define BSP_SPI4_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_SPI5)
|
||||
#define BSP_SPI5_ERR_IRQ_NUM INT098_IRQn
|
||||
#define BSP_SPI5_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_SPI6)
|
||||
#define BSP_SPI6_ERR_IRQ_NUM INT099_IRQn
|
||||
#define BSP_SPI6_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_UART8)
|
||||
#define BSP_UART8_RXERR_IRQ_NUM INT017_IRQn
|
||||
#define BSP_UART8_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_UART8_RX_IRQ_NUM INT109_IRQn
|
||||
#define BSP_UART8_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_UART8_TX_IRQ_NUM INT108_IRQn
|
||||
#define BSP_UART8_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
|
||||
#if defined(BSP_UART8_RX_USING_DMA)
|
||||
#define BSP_UART8_RXTO_IRQ_NUM INT071_IRQn
|
||||
#define BSP_UART8_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif
|
||||
|
||||
#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART8_TX_USING_DMA)
|
||||
#define BSP_UART8_TX_CPLT_IRQ_NUM INT107_IRQn
|
||||
#define BSP_UART8_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#elif defined(RT_USING_SERIAL_V2)
|
||||
#define BSP_UART8_TX_CPLT_IRQ_NUM INT107_IRQn
|
||||
#define BSP_UART8_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif
|
||||
#endif /* BSP_USING_UART8 */
|
||||
|
||||
#if defined(BSP_USING_UART9)
|
||||
#define BSP_UART9_RXERR_IRQ_NUM INT112_IRQn
|
||||
#define BSP_UART9_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_UART9_RX_IRQ_NUM INT110_IRQn
|
||||
#define BSP_UART9_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_UART9_TX_IRQ_NUM INT111_IRQn
|
||||
#define BSP_UART9_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
|
||||
#if defined(BSP_UART9_RX_USING_DMA)
|
||||
#define BSP_UART9_RXTO_IRQ_NUM INT072_IRQn
|
||||
#define BSP_UART9_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif
|
||||
|
||||
#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART9_TX_USING_DMA)
|
||||
#define BSP_UART9_TX_CPLT_IRQ_NUM INT113_IRQn
|
||||
#define BSP_UART9_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#elif defined(RT_USING_SERIAL_V2)
|
||||
#define BSP_UART9_TX_CPLT_IRQ_NUM INT113_IRQn
|
||||
#define BSP_UART9_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif
|
||||
#endif /* BSP_USING_UART9 */
|
||||
|
||||
#if defined(BSP_USING_UART10)
|
||||
#define BSP_UART10_RXERR_IRQ_NUM INT115_IRQn
|
||||
#define BSP_UART10_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_UART10_RX_IRQ_NUM INT114_IRQn
|
||||
#define BSP_UART10_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_UART10_TX_IRQ_NUM INT113_IRQn
|
||||
#define BSP_UART10_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
|
||||
#if defined(BSP_UART10_RX_USING_DMA)
|
||||
#define BSP_UART10_RXTO_IRQ_NUM INT073_IRQn
|
||||
#define BSP_UART10_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif
|
||||
|
||||
#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART10_TX_USING_DMA)
|
||||
#define BSP_UART10_TX_CPLT_IRQ_NUM INT112_IRQn
|
||||
#define BSP_UART10_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#elif defined(RT_USING_SERIAL_V2)
|
||||
#define BSP_UART10_TX_CPLT_IRQ_NUM INT112_IRQn
|
||||
#define BSP_UART10_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif
|
||||
#endif /* BSP_USING_UART10 */
|
||||
|
||||
#if defined(BSP_USING_CAN1)
|
||||
#define BSP_CAN1_IRQ_NUM INT092_IRQn
|
||||
#define BSP_CAN1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif /* BSP_USING_CAN1 */
|
||||
|
||||
#if defined(BSP_USING_CAN2)
|
||||
#define BSP_CAN2_IRQ_NUM INT093_IRQn
|
||||
#define BSP_CAN2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif /* BSP_USING_CAN2 */
|
||||
|
||||
#if defined(BSP_USING_MCAN1)
|
||||
#define BSP_MCAN1_INT0_IRQ_NUM INT124_IRQn
|
||||
#define BSP_MCAN1_INT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
|
||||
#define BSP_MCAN1_INT1_IRQ_NUM INT125_IRQn
|
||||
#define BSP_MCAN1_INT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_MCAN1 */
|
||||
|
||||
#if defined(BSP_USING_MCAN2)
|
||||
#define BSP_MCAN2_INT0_IRQ_NUM INT126_IRQn
|
||||
#define BSP_MCAN2_INT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
|
||||
#define BSP_MCAN2_INT1_IRQ_NUM INT127_IRQn
|
||||
#define BSP_MCAN2_INT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_MCAN2 */
|
||||
|
||||
#if defined(BSP_USING_SDIO1)
|
||||
#define BSP_SDIO1_IRQ_NUM INT004_IRQn
|
||||
#define BSP_SDIO1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif /* BSP_USING_SDIO1 */
|
||||
|
||||
#if defined(BSP_USING_SDIO2)
|
||||
#define BSP_SDIO2_IRQ_NUM INT005_IRQn
|
||||
#define BSP_SDIO2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif /* BSP_USING_SDIO2 */
|
||||
|
||||
#if defined(RT_USING_ALARM)
|
||||
#define BSP_RTC_ALARM_IRQ_NUM INT050_IRQn
|
||||
#define BSP_RTC_ALARM_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* RT_USING_ALARM */
|
||||
|
||||
|
||||
#if defined(BSP_USING_USBFS)
|
||||
#define BSP_USBFS_GLB_IRQ_NUM INT003_IRQn
|
||||
#define BSP_USBFS_GLB_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_USBFS */
|
||||
|
||||
#if defined(BSP_USING_USBHS)
|
||||
#define BSP_USBHS_GLB_IRQ_NUM INT000_IRQn
|
||||
#define BSP_USBHS_GLB_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_USBHS */
|
||||
|
||||
#if defined (BSP_USING_QSPI)
|
||||
#define BSP_QSPI_ERR_IRQ_NUM INT002_IRQn
|
||||
#define BSP_QSPI_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif /* BSP_USING_QSPI */
|
||||
|
||||
#if defined(BSP_USING_PULSE_ENCODER_TMRA_1)
|
||||
#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM INT074_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM INT075_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_PULSE_ENCODER_TMRA_1 */
|
||||
#if defined(BSP_USING_PULSE_ENCODER_TMRA_2)
|
||||
#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM INT076_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM INT077_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_PULSE_ENCODER_TMRA_2 */
|
||||
#if defined(BSP_USING_PULSE_ENCODER_TMRA_3)
|
||||
#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM INT080_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM INT081_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_PULSE_ENCODER_TMRA_3 */
|
||||
#if defined(BSP_USING_PULSE_ENCODER_TMRA_4)
|
||||
#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM INT082_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM INT083_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_PULSE_ENCODER_TMRA_4 */
|
||||
#if defined(BSP_USING_PULSE_ENCODER_TMRA_5)
|
||||
#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM INT092_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM INT093_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_PULSE_ENCODER_TMRA_5 */
|
||||
#if defined(BSP_USING_PULSE_ENCODER_TMRA_6)
|
||||
#define BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_NUM INT094_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_NUM INT095_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_PULSE_ENCODER_TMRA_6 */
|
||||
#if defined(BSP_USING_PULSE_ENCODER_TMRA_7)
|
||||
#define BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_NUM INT096_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_NUM INT097_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_PULSE_ENCODER_TMRA_7 */
|
||||
#if defined(BSP_USING_PULSE_ENCODER_TMRA_8)
|
||||
#define BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_NUM INT096_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_NUM INT097_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_PULSE_ENCODER_TMRA_8 */
|
||||
#if defined(BSP_USING_PULSE_ENCODER_TMRA_9)
|
||||
#define BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_NUM INT098_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_NUM INT099_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_PULSE_ENCODER_TMRA_9 */
|
||||
#if defined(BSP_USING_PULSE_ENCODER_TMRA_10)
|
||||
#define BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_NUM INT100_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_NUM INT101_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_PULSE_ENCODER_TMRA_10 */
|
||||
#if defined(BSP_USING_PULSE_ENCODER_TMRA_11)
|
||||
#define BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_NUM INT102_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_NUM INT103_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_PULSE_ENCODER_TMRA_11 */
|
||||
#if defined(BSP_USING_PULSE_ENCODER_TMRA_12)
|
||||
#define BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_NUM INT102_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_NUM INT103_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_PULSE_ENCODER_TMRA_12 */
|
||||
|
||||
#if defined(BSP_USING_PULSE_ENCODER_TMR6_1)
|
||||
#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM INT056_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM INT057_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_PULSE_ENCODER_TMR6_1 */
|
||||
#if defined(BSP_USING_PULSE_ENCODER_TMR6_2)
|
||||
#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM INT058_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM INT059_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_PULSE_ENCODER_TMR6_2 */
|
||||
#if defined(BSP_USING_PULSE_ENCODER_TMR6_3)
|
||||
#define BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_NUM INT062_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_NUM INT063_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_PULSE_ENCODER_TMR6_3 */
|
||||
#if defined(BSP_USING_PULSE_ENCODER_TMR6_4)
|
||||
#define BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_NUM INT068_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_NUM INT069_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_PULSE_ENCODER_TMR6_4 */
|
||||
#if defined(BSP_USING_PULSE_ENCODER_TMR6_5)
|
||||
#define BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_NUM INT074_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_NUM INT075_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_PULSE_ENCODER_TMR6_5 */
|
||||
#if defined(BSP_USING_PULSE_ENCODER_TMR6_6)
|
||||
#define BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_NUM INT076_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_NUM INT077_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_PULSE_ENCODER_TMR6_6 */
|
||||
#if defined(BSP_USING_PULSE_ENCODER_TMR6_7)
|
||||
#define BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_NUM INT080_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_NUM INT081_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_PULSE_ENCODER_TMR6_7 */
|
||||
#if defined(BSP_USING_PULSE_ENCODER_TMR6_8)
|
||||
#define BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_NUM INT082_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_NUM INT083_IRQn
|
||||
#define BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_PULSE_ENCODER_TMR6_8 */
|
||||
|
||||
#if defined(BSP_USING_TMRA_1)
|
||||
#define BSP_USING_TMRA_1_IRQ_NUM INT074_IRQn
|
||||
#define BSP_USING_TMRA_1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_TMRA_1 */
|
||||
#if defined(BSP_USING_TMRA_2)
|
||||
#define BSP_USING_TMRA_2_IRQ_NUM INT075_IRQn
|
||||
#define BSP_USING_TMRA_2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_TMRA_2 */
|
||||
#if defined(BSP_USING_TMRA_3)
|
||||
#define BSP_USING_TMRA_3_IRQ_NUM INT080_IRQn
|
||||
#define BSP_USING_TMRA_3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_TMRA_3 */
|
||||
#if defined(BSP_USING_TMRA_4)
|
||||
#define BSP_USING_TMRA_4_IRQ_NUM INT081_IRQn
|
||||
#define BSP_USING_TMRA_4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_TMRA_4 */
|
||||
#if defined(BSP_USING_TMRA_5)
|
||||
#define BSP_USING_TMRA_5_IRQ_NUM INT092_IRQn
|
||||
#define BSP_USING_TMRA_5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_TMRA_5 */
|
||||
#if defined(BSP_USING_TMRA_6)
|
||||
#define BSP_USING_TMRA_6_IRQ_NUM INT093_IRQn
|
||||
#define BSP_USING_TMRA_6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_TMRA_6 */
|
||||
#if defined(BSP_USING_TMRA_7)
|
||||
#define BSP_USING_TMRA_7_IRQ_NUM INT094_IRQn
|
||||
#define BSP_USING_TMRA_7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_TMRA_7 */
|
||||
#if defined(BSP_USING_TMRA_8)
|
||||
#define BSP_USING_TMRA_8_IRQ_NUM INT095_IRQn
|
||||
#define BSP_USING_TMRA_8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_TMRA_8 */
|
||||
#if defined(BSP_USING_TMRA_9)
|
||||
#define BSP_USING_TMRA_9_IRQ_NUM INT098_IRQn
|
||||
#define BSP_USING_TMRA_9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_TMRA_9 */
|
||||
#if defined(BSP_USING_TMRA_10)
|
||||
#define BSP_USING_TMRA_10_IRQ_NUM INT099_IRQn
|
||||
#define BSP_USING_TMRA_10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_TMRA_10 */
|
||||
#if defined(BSP_USING_TMRA_11)
|
||||
#define BSP_USING_TMRA_11_IRQ_NUM INT100_IRQn
|
||||
#define BSP_USING_TMRA_11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_TMRA_11 */
|
||||
#if defined(BSP_USING_TMRA_12)
|
||||
#define BSP_USING_TMRA_12_IRQ_NUM INT101_IRQn
|
||||
#define BSP_USING_TMRA_12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_TMRA_12 */
|
||||
|
||||
#if defined(BSP_USING_INPUT_CAPTURE)
|
||||
#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM (INT012_IRQn)
|
||||
#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
|
||||
#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM (INT013_IRQn)
|
||||
#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
|
||||
|
||||
#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM (INT014_IRQn)
|
||||
#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
|
||||
#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM (INT015_IRQn)
|
||||
#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
|
||||
|
||||
#define BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_NUM (INT016_IRQn)
|
||||
#define BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
|
||||
#define BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_NUM (INT017_IRQn)
|
||||
#define BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __IRQ_CONFIG_H__ */
|
||||
|
|
@ -0,0 +1,364 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
* Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2025-04-10 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __MCAN_CONFIG_H__
|
||||
#define __MCAN_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "irq_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/***********************************************************************************************/
|
||||
/***********************************************************************************************/
|
||||
/* The default configuration for MCANs. Users can modify the configurations based on the application.
|
||||
For the message RAM:
|
||||
1. MCAN1 and MCAN2 share 2048 bytes message RAM
|
||||
2. User can modify the definitions of filter number, Rx FIFO number, Tx FIFO number.
|
||||
3. MCAN has two configurable Receive FIFOs, Rx FIFO0 and Rx FIFO1. There use Rx FIFO0 only by default.
|
||||
If only one FIFO is needed, use Rx FIFO0. If Rx FIFO1 is needed, define it's macro between 1 and 64,
|
||||
and pay attention the total size of message RAM that to be allocated.
|
||||
*/
|
||||
|
||||
#ifdef RT_CAN_USING_CANFD
|
||||
#define MCAN_FD_SEL MCAN_FD_ISO_FD_BRS
|
||||
#define MCAN_TOTAL_FILTER_NUM (64U)
|
||||
#define MCAN_STD_FILTER_NUM (32U) /* Each standard filter element size is 4 bytes */
|
||||
#define MCAN_EXT_FILTER_NUM (32U) /* Each extended filter element size is 8 bytes */
|
||||
#define MCAN_TX_FIFO_NUM (11U)
|
||||
#define MCAN_RX_FIFO_NUM (12U)
|
||||
#define MCAN_DATA_FIELD_SIZE (MCAN_DATA_SIZE_64BYTE) /* Each FIFO element size is 64+8 bytes */
|
||||
#else
|
||||
#define MCAN_FD_SEL MCAN_FD_CLASSICAL
|
||||
#define MCAN_TOTAL_FILTER_NUM (64U)
|
||||
#define MCAN_STD_FILTER_NUM (32U) /* Each standard filter element size is 4 bytes */
|
||||
#define MCAN_EXT_FILTER_NUM (32U) /* Each extended filter element size is 8 bytes */
|
||||
#define MCAN_TX_FIFO_NUM (32U)
|
||||
#define MCAN_RX_FIFO_NUM (64U)
|
||||
#define MCAN_DATA_FIELD_SIZE (MCAN_DATA_SIZE_8BYTE) /* Each FIFO element size is 8+8 bytes */
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_MCAN1
|
||||
#define MCAN1_NAME ("mcan1")
|
||||
#define MCAN1_WORK_MODE (RT_CAN_MODE_NORMAL)
|
||||
#define MCAN1_TX_PRIV_MODE RT_CAN_MODE_NOPRIV /* RT_CAN_MODE_NOPRIV: Tx FIFO mode; RT_CAN_MODE_PRIV: Tx priority mode */
|
||||
|
||||
#define MCAN1_FD_SEL MCAN_FD_SEL
|
||||
|
||||
#define MCAN1_STD_FILTER_NUM MCAN_STD_FILTER_NUM
|
||||
#define MCAN1_EXT_FILTER_NUM MCAN_EXT_FILTER_NUM
|
||||
|
||||
#define MCAN1_RX_FIFO0_NUM MCAN_RX_FIFO_NUM
|
||||
#define MCAN1_RX_FIFO0_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE
|
||||
|
||||
#define MCAN1_TX_FIFO_NUM MCAN_TX_FIFO_NUM
|
||||
#define MCAN1_TX_FIFO_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE
|
||||
#define MCAN1_TX_NOTIFICATION_BUF ((1UL << MCAN1_TX_FIFO_NUM) - 1U)
|
||||
#endif /* BSP_USING_MCAN1 */
|
||||
|
||||
#ifdef BSP_USING_MCAN2
|
||||
#define MCAN2_NAME ("mcan2")
|
||||
#define MCAN2_WORK_MODE (RT_CAN_MODE_NORMAL)
|
||||
#define MCAN2_TX_PRIV_MODE RT_CAN_MODE_NOPRIV /* RT_CAN_MODE_NOPRIV: Tx FIFO mode; RT_CAN_MODE_PRIV: Tx priority mode */
|
||||
|
||||
#define MCAN2_FD_SEL MCAN_FD_SEL
|
||||
#define MCAN2_STD_FILTER_NUM MCAN_STD_FILTER_NUM
|
||||
#define MCAN2_EXT_FILTER_NUM MCAN_EXT_FILTER_NUM
|
||||
|
||||
#define MCAN2_RX_FIFO0_NUM MCAN_RX_FIFO_NUM
|
||||
#define MCAN2_RX_FIFO0_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE
|
||||
|
||||
#define MCAN2_TX_FIFO_NUM MCAN_TX_FIFO_NUM
|
||||
#define MCAN2_TX_FIFO_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE
|
||||
#define MCAN2_TX_NOTIFICATION_BUF ((1UL << MCAN2_TX_FIFO_NUM) - 1U)
|
||||
#endif /* BSP_USING_MCAN2 */
|
||||
|
||||
/***********************************************************************************************/
|
||||
/***********************************************************************************************/
|
||||
|
||||
/*
|
||||
Bit rate configuration examples for CAN FD.
|
||||
Nominal bit rate for CAN FD arbitration phase and data bit rate for CAN FD data phase.
|
||||
BitRate(bps) = MCANClock(Hz) / (Prescaler * (TimeSeg1 + TimeSeg2))
|
||||
SamplePoint(%) = TimeSeg1 / (TimeSeg1 + TimeSeg2)
|
||||
eg.
|
||||
BitRate(bps) = 40000000(Hz) / (2 * (16 + 4)) = 1000000 = 1M(bps)
|
||||
SamplePoint(%) = 16 / (16 + 4) = 80%
|
||||
The following bit rate configurations are based on the max MCAN Clock(40MHz).
|
||||
NOTE:
|
||||
1. It is better to limit u32NominalPrescaler and u32DataPrescaler between 1 and 2.
|
||||
1. The unit of u32SspOffset is MCANClock.
|
||||
2. For the corresponding function of u32TdcFilter, please refer to the reference manual for details(TDCR.TDCF).
|
||||
The u32TdcFilter can be get from PSR.TDCV.
|
||||
*/
|
||||
#define MCAN_FD_CFG_500K_1M \
|
||||
{ \
|
||||
.u32NominalPrescaler = 1, \
|
||||
.u32NominalTimeSeg1 = 64, \
|
||||
.u32NominalTimeSeg2 = 16, \
|
||||
.u32NominalSyncJumpWidth = 16, \
|
||||
.u32DataPrescaler = 1, \
|
||||
.u32DataTimeSeg1 = 32, \
|
||||
.u32DataTimeSeg2 = 8, \
|
||||
.u32DataSyncJumpWidth = 8, \
|
||||
.u32TDC = MCAN_FD_TDC_ENABLE, \
|
||||
.u32SspOffset = 32, \
|
||||
.u32TdcFilter = 32 + 1, \
|
||||
}
|
||||
|
||||
#define MCAN_FD_CFG_500K_2M \
|
||||
{ \
|
||||
.u32NominalPrescaler = 1, \
|
||||
.u32NominalTimeSeg1 = 64, \
|
||||
.u32NominalTimeSeg2 = 16, \
|
||||
.u32NominalSyncJumpWidth = 16, \
|
||||
.u32DataPrescaler = 1, \
|
||||
.u32DataTimeSeg1 = 16, \
|
||||
.u32DataTimeSeg2 = 4, \
|
||||
.u32DataSyncJumpWidth = 4, \
|
||||
.u32TDC = MCAN_FD_TDC_ENABLE, \
|
||||
.u32SspOffset = 16, \
|
||||
.u32TdcFilter = 16 + 1, \
|
||||
}
|
||||
|
||||
#define MCAN_FD_CFG_500K_4M \
|
||||
{ \
|
||||
.u32NominalPrescaler = 1, \
|
||||
.u32NominalTimeSeg1 = 64, \
|
||||
.u32NominalTimeSeg2 = 16, \
|
||||
.u32NominalSyncJumpWidth = 16, \
|
||||
.u32DataPrescaler = 1, \
|
||||
.u32DataTimeSeg1 = 8, \
|
||||
.u32DataTimeSeg2 = 2, \
|
||||
.u32DataSyncJumpWidth = 2, \
|
||||
.u32TDC = MCAN_FD_TDC_ENABLE, \
|
||||
.u32SspOffset = 8, \
|
||||
.u32TdcFilter = 8 + 1, \
|
||||
}
|
||||
|
||||
#define MCAN_FD_CFG_500K_5M \
|
||||
{ \
|
||||
.u32NominalPrescaler = 1, \
|
||||
.u32NominalTimeSeg1 = 64, \
|
||||
.u32NominalTimeSeg2 = 16, \
|
||||
.u32NominalSyncJumpWidth = 16, \
|
||||
.u32DataPrescaler = 1, \
|
||||
.u32DataTimeSeg1 = 6, \
|
||||
.u32DataTimeSeg2 = 2, \
|
||||
.u32DataSyncJumpWidth = 2, \
|
||||
.u32TDC = MCAN_FD_TDC_ENABLE, \
|
||||
.u32SspOffset = 6, \
|
||||
.u32TdcFilter = 6 + 1, \
|
||||
}
|
||||
|
||||
#define MCAN_FD_CFG_500K_8M \
|
||||
{ \
|
||||
.u32NominalPrescaler = 1, \
|
||||
.u32NominalTimeSeg1 = 64, \
|
||||
.u32NominalTimeSeg2 = 16, \
|
||||
.u32NominalSyncJumpWidth = 16, \
|
||||
.u32DataPrescaler = 1, \
|
||||
.u32DataTimeSeg1 = 4, \
|
||||
.u32DataTimeSeg2 = 1, \
|
||||
.u32DataSyncJumpWidth = 1, \
|
||||
.u32TDC = MCAN_FD_TDC_ENABLE, \
|
||||
.u32SspOffset = 4, \
|
||||
.u32TdcFilter = 4 + 1, \
|
||||
}
|
||||
|
||||
#define MCAN_FD_CFG_1M_1M \
|
||||
{ \
|
||||
.u32NominalPrescaler = 1, \
|
||||
.u32NominalTimeSeg1 = 32, \
|
||||
.u32NominalTimeSeg2 = 8, \
|
||||
.u32NominalSyncJumpWidth = 8, \
|
||||
.u32DataPrescaler = 1, \
|
||||
.u32DataTimeSeg1 = 32, \
|
||||
.u32DataTimeSeg2 = 8, \
|
||||
.u32DataSyncJumpWidth = 8, \
|
||||
.u32TDC = MCAN_FD_TDC_ENABLE, \
|
||||
.u32SspOffset = 2*32, \
|
||||
.u32TdcFilter = 2*32 + 1, \
|
||||
}
|
||||
|
||||
#define MCAN_FD_CFG_1M_2M \
|
||||
{ \
|
||||
.u32NominalPrescaler = 1, \
|
||||
.u32NominalTimeSeg1 = 32, \
|
||||
.u32NominalTimeSeg2 = 8, \
|
||||
.u32NominalSyncJumpWidth = 8, \
|
||||
.u32DataPrescaler = 1, \
|
||||
.u32DataTimeSeg1 = 16, \
|
||||
.u32DataTimeSeg2 = 4, \
|
||||
.u32DataSyncJumpWidth = 4, \
|
||||
.u32TDC = MCAN_FD_TDC_ENABLE, \
|
||||
.u32SspOffset = 16, \
|
||||
.u32TdcFilter = 16 + 1, \
|
||||
}
|
||||
|
||||
#define MCAN_FD_CFG_1M_4M \
|
||||
{ \
|
||||
.u32NominalPrescaler = 1, \
|
||||
.u32NominalTimeSeg1 = 32, \
|
||||
.u32NominalTimeSeg2 = 8, \
|
||||
.u32NominalSyncJumpWidth = 8, \
|
||||
.u32DataPrescaler = 1, \
|
||||
.u32DataTimeSeg1 = 8, \
|
||||
.u32DataTimeSeg2 = 2, \
|
||||
.u32DataSyncJumpWidth = 2, \
|
||||
.u32TDC = MCAN_FD_TDC_ENABLE, \
|
||||
.u32SspOffset = 8, \
|
||||
.u32TdcFilter = 8 + 1, \
|
||||
}
|
||||
|
||||
#define MCAN_FD_CFG_1M_5M \
|
||||
{ \
|
||||
.u32NominalPrescaler = 1, \
|
||||
.u32NominalTimeSeg1 = 32, \
|
||||
.u32NominalTimeSeg2 = 8, \
|
||||
.u32NominalSyncJumpWidth = 8, \
|
||||
.u32DataPrescaler = 1, \
|
||||
.u32DataTimeSeg1 = 6, \
|
||||
.u32DataTimeSeg2 = 2, \
|
||||
.u32DataSyncJumpWidth = 2, \
|
||||
.u32TDC = MCAN_FD_TDC_ENABLE, \
|
||||
.u32SspOffset = 6, \
|
||||
.u32TdcFilter = 6 + 1, \
|
||||
}
|
||||
|
||||
#define MCAN_FD_CFG_1M_8M \
|
||||
{ \
|
||||
.u32NominalPrescaler = 1, \
|
||||
.u32NominalTimeSeg1 = 32, \
|
||||
.u32NominalTimeSeg2 = 8, \
|
||||
.u32NominalSyncJumpWidth = 8, \
|
||||
.u32DataPrescaler = 1, \
|
||||
.u32DataTimeSeg1 = 4, \
|
||||
.u32DataTimeSeg2 = 1, \
|
||||
.u32DataSyncJumpWidth = 1, \
|
||||
.u32TDC = MCAN_FD_TDC_ENABLE, \
|
||||
.u32SspOffset = 4, \
|
||||
.u32TdcFilter = 4 + 1, \
|
||||
}
|
||||
|
||||
/*
|
||||
Bit rate configuration examples for classical CAN.
|
||||
BitRate(bps) = MCANClock(Hz) / (u32NominalPrescaler * (u32NominalTimeSeg1 + u32NominalTimeSeg2))
|
||||
SamplePoint(%) = u32NominalTimeSeg1 / (u32NominalTimeSeg1 + u32NominalTimeSeg2)
|
||||
eg.
|
||||
BitRate(bps) = 40000000(Hz) / (2 * (16 + 4)) = 1000000 = 1M(bps)
|
||||
SamplePoint(%) = 16 / (16 + 4) = 80%
|
||||
The following bit rate configurations are based on the max MCAN Clock(40MHz).
|
||||
*/
|
||||
#define MCAN_CC_CFG_1M \
|
||||
{ \
|
||||
.u32NominalPrescaler = 2, \
|
||||
.u32NominalTimeSeg1 = 16, \
|
||||
.u32NominalTimeSeg2 = 4, \
|
||||
.u32NominalSyncJumpWidth = 4, \
|
||||
}
|
||||
|
||||
#define MCAN_CC_CFG_800K \
|
||||
{ \
|
||||
.u32NominalPrescaler = 2, \
|
||||
.u32NominalTimeSeg1 = 20, \
|
||||
.u32NominalTimeSeg2 = 5, \
|
||||
.u32NominalSyncJumpWidth = 5, \
|
||||
}
|
||||
|
||||
#define MCAN_CC_CFG_500K \
|
||||
{ \
|
||||
.u32NominalPrescaler = 4, \
|
||||
.u32NominalTimeSeg1 = 16, \
|
||||
.u32NominalTimeSeg2 = 4, \
|
||||
.u32NominalSyncJumpWidth = 4, \
|
||||
}
|
||||
|
||||
#define MCAN_CC_CFG_250K \
|
||||
{ \
|
||||
.u32NominalPrescaler = 4, \
|
||||
.u32NominalTimeSeg1 = 32, \
|
||||
.u32NominalTimeSeg2 = 8, \
|
||||
.u32NominalSyncJumpWidth = 8, \
|
||||
}
|
||||
|
||||
#define MCAN_CC_CFG_125K \
|
||||
{ \
|
||||
.u32NominalPrescaler = 8, \
|
||||
.u32NominalTimeSeg1 = 32, \
|
||||
.u32NominalTimeSeg2 = 8, \
|
||||
.u32NominalSyncJumpWidth = 8, \
|
||||
}
|
||||
|
||||
#define MCAN_CC_CFG_100K \
|
||||
{ \
|
||||
.u32NominalPrescaler = 10, \
|
||||
.u32NominalTimeSeg1 = 32, \
|
||||
.u32NominalTimeSeg2 = 8, \
|
||||
.u32NominalSyncJumpWidth = 8, \
|
||||
}
|
||||
|
||||
#define MCAN_CC_CFG_50K \
|
||||
{ \
|
||||
.u32NominalPrescaler = 20, \
|
||||
.u32NominalTimeSeg1 = 32, \
|
||||
.u32NominalTimeSeg2 = 8, \
|
||||
.u32NominalSyncJumpWidth = 8, \
|
||||
}
|
||||
|
||||
#define MCAN_CC_CFG_20K \
|
||||
{ \
|
||||
.u32NominalPrescaler = 50, \
|
||||
.u32NominalTimeSeg1 = 32, \
|
||||
.u32NominalTimeSeg2 = 8, \
|
||||
.u32NominalSyncJumpWidth = 8, \
|
||||
}
|
||||
|
||||
#define MCAN_CC_CFG_10K \
|
||||
{ \
|
||||
.u32NominalPrescaler = 100, \
|
||||
.u32NominalTimeSeg1 = 32, \
|
||||
.u32NominalTimeSeg2 = 8, \
|
||||
.u32NominalSyncJumpWidth = 8, \
|
||||
}
|
||||
|
||||
#ifdef RT_CAN_USING_CANFD
|
||||
#define MCAN1_BAUD_RATE_CFG MCAN_FD_CFG_1M_4M
|
||||
#define MCAN1_NOMINAL_BAUD_RATE CANFD_DATA_BAUD_1M
|
||||
#define MCAN1_DATA_BAUD_RATE CANFD_DATA_BAUD_4M
|
||||
|
||||
#define MCAN2_BAUD_RATE_CFG MCAN_FD_CFG_1M_4M
|
||||
#define MCAN2_NOMINAL_BAUD_RATE CANFD_DATA_BAUD_1M
|
||||
#define MCAN2_DATA_BAUD_RATE CANFD_DATA_BAUD_4M
|
||||
|
||||
#else
|
||||
#define MCAN1_BAUD_RATE_CFG MCAN_CC_CFG_1M
|
||||
#define MCAN1_NOMINAL_BAUD_RATE CAN1MBaud
|
||||
#define MCAN1_DATA_BAUD_RATE 0
|
||||
|
||||
#define MCAN2_BAUD_RATE_CFG MCAN_CC_CFG_1M
|
||||
#define MCAN2_NOMINAL_BAUD_RATE CAN1MBaud
|
||||
#define MCAN2_DATA_BAUD_RATE 0
|
||||
|
||||
#endif /* #ifdef RT_CAN_USING_CANFD */
|
||||
|
||||
/***********************************************************************************************/
|
||||
/***********************************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __MCAN_CONFIG_H__ */
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,98 @@
|
|||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2023-05-12 CDT first version
|
||||
* 2024-06-13 CDT disable pm tickless timer
|
||||
*/
|
||||
|
||||
#ifndef __PM_CONFIG_H__
|
||||
#define __PM_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_PM
|
||||
extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode);
|
||||
|
||||
#ifndef PM_TICKLESS_TIMER_ENABLE_MASK
|
||||
#define PM_TICKLESS_TIMER_ENABLE_MASK (0UL)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief run mode config @ref pm_run_mode_config structure
|
||||
*/
|
||||
#ifndef PM_RUN_MODE_CFG
|
||||
#define PM_RUN_MODE_CFG \
|
||||
{ \
|
||||
.sys_clk_cfg = rt_hw_board_pm_sysclk_cfg \
|
||||
}
|
||||
#endif /* PM_RUN_MODE_CFG */
|
||||
|
||||
/**
|
||||
* @brief sleep idle config @ref pm_sleep_mode_idle_config structure
|
||||
*/
|
||||
#ifndef PM_SLEEP_IDLE_CFG
|
||||
#define PM_SLEEP_IDLE_CFG \
|
||||
{ \
|
||||
.pwc_sleep_type = PWC_SLEEP_WFE_INT, \
|
||||
}
|
||||
#endif /*PM_SLEEP_IDLE_CFG*/
|
||||
|
||||
/**
|
||||
* @brief sleep deep config @ref pm_sleep_mode_deep_config structure
|
||||
*/
|
||||
#ifndef PM_SLEEP_DEEP_CFG
|
||||
#define PM_SLEEP_DEEP_CFG \
|
||||
{ \
|
||||
{ \
|
||||
.u16Clock = PWC_STOP_CLK_KEEP, \
|
||||
.u8StopDrv = PWC_STOP_DRV_HIGH, \
|
||||
.u16ExBusHold = PWC_STOP_EXBUS_HIZ, \
|
||||
.u16FlashWait = PWC_STOP_FLASH_WAIT_ON, \
|
||||
}, \
|
||||
.pwc_stop_type = PWC_STOP_WFE_INT, \
|
||||
}
|
||||
#endif /*PM_SLEEP_DEEP_CFG*/
|
||||
|
||||
/**
|
||||
* @brief sleep standby config @ref pm_sleep_mode_standby_config structure
|
||||
*/
|
||||
#ifndef PM_SLEEP_STANDBY_CFG
|
||||
#define PM_SLEEP_STANDBY_CFG \
|
||||
{ \
|
||||
{ \
|
||||
.u8Mode = PWC_PD_MD1, \
|
||||
.u8IOState = PWC_PD_IO_KEEP1, \
|
||||
.u8VcapCtrl = PWC_PD_VCAP_0P047UF, \
|
||||
}, \
|
||||
}
|
||||
#endif /*PM_SLEEP_STANDBY_CFG*/
|
||||
|
||||
/**
|
||||
* @brief sleep shutdown config @ref pm_sleep_mode_shutdown_config structure
|
||||
*/
|
||||
#ifndef PM_SLEEP_SHUTDOWN_CFG
|
||||
#define PM_SLEEP_SHUTDOWN_CFG \
|
||||
{ \
|
||||
{ \
|
||||
.u8Mode = PWC_PD_MD3, \
|
||||
.u8IOState = PWC_PD_IO_KEEP1, \
|
||||
.u8VcapCtrl = PWC_PD_VCAP_0P047UF, \
|
||||
}, \
|
||||
}
|
||||
#endif /*PM_SLEEP_SHUTDOWN_CFG*/
|
||||
|
||||
#endif /* BSP_USING_PM */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __PM_CONFIG_H__ */
|
||||
|
|
@ -0,0 +1,544 @@
|
|||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2023-06-09 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __PULSE_ENCODER_CONFIG_H__
|
||||
#define __PULSE_ENCODER_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(RT_USING_PULSE_ENCODER)
|
||||
|
||||
#ifdef BSP_USING_PULSE_ENCODER_TMRA_1
|
||||
#ifndef PULSE_ENCODER_TMRA_1_CONFIG
|
||||
#define PULSE_ENCODER_TMRA_1_CONFIG \
|
||||
{ \
|
||||
.tmr_handler = CM_TMRA_1, \
|
||||
.u32PeriphClock = FCG2_PERIPH_TMRA_1, \
|
||||
.hw_count = \
|
||||
{ \
|
||||
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
|
||||
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
|
||||
}, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc_Ovf = INT_SRC_TMRA_1_OVF, \
|
||||
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM, \
|
||||
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO, \
|
||||
.enIntSrc_Udf = INT_SRC_TMRA_1_UDF, \
|
||||
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM, \
|
||||
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO, \
|
||||
}, \
|
||||
.u32PeriodValue = 1000UL, \
|
||||
.name = "pulse_a1" \
|
||||
}
|
||||
#endif /* PULSE_ENCODER_TMRA_1_CONFIG */
|
||||
#endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */
|
||||
|
||||
#ifdef BSP_USING_PULSE_ENCODER_TMRA_2
|
||||
#ifndef PULSE_ENCODER_TMRA_2_CONFIG
|
||||
#define PULSE_ENCODER_TMRA_2_CONFIG \
|
||||
{ \
|
||||
.tmr_handler = CM_TMRA_2, \
|
||||
.u32PeriphClock = FCG2_PERIPH_TMRA_2, \
|
||||
.hw_count = \
|
||||
{ \
|
||||
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
|
||||
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
|
||||
}, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc_Ovf = INT_SRC_TMRA_2_OVF, \
|
||||
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM, \
|
||||
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO, \
|
||||
.enIntSrc_Udf = INT_SRC_TMRA_2_UDF, \
|
||||
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM, \
|
||||
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO, \
|
||||
}, \
|
||||
.u32PeriodValue = 1000UL, \
|
||||
.name = "pulse_a2" \
|
||||
}
|
||||
#endif /* PULSE_ENCODER_TMRA_2_CONFIG */
|
||||
#endif /* BSP_USING_PULSE_ENCODER_TMRA_2 */
|
||||
|
||||
#ifdef BSP_USING_PULSE_ENCODER_TMRA_3
|
||||
#ifndef PULSE_ENCODER_TMRA_3_CONFIG
|
||||
#define PULSE_ENCODER_TMRA_3_CONFIG \
|
||||
{ \
|
||||
.tmr_handler = CM_TMRA_3, \
|
||||
.u32PeriphClock = FCG2_PERIPH_TMRA_3, \
|
||||
.hw_count = \
|
||||
{ \
|
||||
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
|
||||
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
|
||||
}, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc_Ovf = INT_SRC_TMRA_3_OVF, \
|
||||
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM, \
|
||||
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO, \
|
||||
.enIntSrc_Udf = INT_SRC_TMRA_3_UDF, \
|
||||
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM, \
|
||||
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO, \
|
||||
}, \
|
||||
.u32PeriodValue = 1000UL, \
|
||||
.name = "pulse_a3" \
|
||||
}
|
||||
#endif /* PULSE_ENCODER_TMRA_3_CONFIG */
|
||||
#endif /* BSP_USING_PULSE_ENCODER_TMRA_3 */
|
||||
|
||||
#ifdef BSP_USING_PULSE_ENCODER_TMRA_4
|
||||
#ifndef PULSE_ENCODER_TMRA_4_CONFIG
|
||||
#define PULSE_ENCODER_TMRA_4_CONFIG \
|
||||
{ \
|
||||
.tmr_handler = CM_TMRA_4, \
|
||||
.u32PeriphClock = FCG2_PERIPH_TMRA_4, \
|
||||
.hw_count = \
|
||||
{ \
|
||||
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
|
||||
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
|
||||
}, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc_Ovf = INT_SRC_TMRA_4_OVF, \
|
||||
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM, \
|
||||
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO, \
|
||||
.enIntSrc_Udf = INT_SRC_TMRA_4_UDF, \
|
||||
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM, \
|
||||
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO, \
|
||||
}, \
|
||||
.u32PeriodValue = 1000UL, \
|
||||
.name = "pulse_a4" \
|
||||
}
|
||||
#endif /* PULSE_ENCODER_TMRA_4_CONFIG */
|
||||
#endif /* BSP_USING_PULSE_ENCODER_TMRA_4 */
|
||||
|
||||
#ifdef BSP_USING_PULSE_ENCODER_TMRA_5
|
||||
#ifndef PULSE_ENCODER_TMRA_5_CONFIG
|
||||
#define PULSE_ENCODER_TMRA_5_CONFIG \
|
||||
{ \
|
||||
.tmr_handler = CM_TMRA_5, \
|
||||
.u32PeriphClock = FCG2_PERIPH_TMRA_5, \
|
||||
.hw_count = \
|
||||
{ \
|
||||
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
|
||||
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
|
||||
}, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc_Ovf = INT_SRC_TMRA_5_OVF, \
|
||||
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM, \
|
||||
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO, \
|
||||
.enIntSrc_Udf = INT_SRC_TMRA_5_UDF, \
|
||||
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM, \
|
||||
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO, \
|
||||
}, \
|
||||
.u32PeriodValue = 1000UL, \
|
||||
.name = "pulse_a5" \
|
||||
}
|
||||
#endif /* PULSE_ENCODER_TMRA_5_CONFIG */
|
||||
#endif /* BSP_USING_PULSE_ENCODER_TMRA_5 */
|
||||
|
||||
#ifdef BSP_USING_PULSE_ENCODER_TMRA_6
|
||||
#ifndef PULSE_ENCODER_TMRA_6_CONFIG
|
||||
#define PULSE_ENCODER_TMRA_6_CONFIG \
|
||||
{ \
|
||||
.tmr_handler = CM_TMRA_6, \
|
||||
.u32PeriphClock = FCG2_PERIPH_TMRA_6, \
|
||||
.hw_count = \
|
||||
{ \
|
||||
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
|
||||
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
|
||||
}, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc_Ovf = INT_SRC_TMRA_6_OVF, \
|
||||
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_NUM, \
|
||||
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_PRIO, \
|
||||
.enIntSrc_Udf = INT_SRC_TMRA_6_UDF, \
|
||||
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_NUM, \
|
||||
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_PRIO, \
|
||||
}, \
|
||||
.u32PeriodValue = 1000UL, \
|
||||
.name = "pulse_a6" \
|
||||
}
|
||||
#endif /* PULSE_ENCODER_TMRA_6_CONFIG */
|
||||
#endif /* BSP_USING_PULSE_ENCODER_TMRA_6 */
|
||||
|
||||
#ifdef BSP_USING_PULSE_ENCODER_TMRA_7
|
||||
#ifndef PULSE_ENCODER_TMRA_7_CONFIG
|
||||
#define PULSE_ENCODER_TMRA_7_CONFIG \
|
||||
{ \
|
||||
.tmr_handler = CM_TMRA_7, \
|
||||
.u32PeriphClock = FCG2_PERIPH_TMRA_7, \
|
||||
.hw_count = \
|
||||
{ \
|
||||
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
|
||||
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
|
||||
}, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc_Ovf = INT_SRC_TMRA_7_OVF, \
|
||||
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_NUM, \
|
||||
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_PRIO, \
|
||||
.enIntSrc_Udf = INT_SRC_TMRA_7_UDF, \
|
||||
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_NUM, \
|
||||
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_PRIO, \
|
||||
}, \
|
||||
.u32PeriodValue = 1000UL, \
|
||||
.name = "pulse_a7" \
|
||||
}
|
||||
#endif /* PULSE_ENCODER_TMRA_7_CONFIG */
|
||||
#endif /* BSP_USING_PULSE_ENCODER_TMRA_7 */
|
||||
|
||||
#ifdef BSP_USING_PULSE_ENCODER_TMRA_8
|
||||
#ifndef PULSE_ENCODER_TMRA_8_CONFIG
|
||||
#define PULSE_ENCODER_TMRA_8_CONFIG \
|
||||
{ \
|
||||
.tmr_handler = CM_TMRA_8, \
|
||||
.u32PeriphClock = FCG2_PERIPH_TMRA_8, \
|
||||
.hw_count = \
|
||||
{ \
|
||||
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
|
||||
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
|
||||
}, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc_Ovf = INT_SRC_TMRA_8_OVF, \
|
||||
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_NUM, \
|
||||
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_PRIO, \
|
||||
.enIntSrc_Udf = INT_SRC_TMRA_8_UDF, \
|
||||
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_NUM, \
|
||||
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_PRIO, \
|
||||
}, \
|
||||
.u32PeriodValue = 1000UL, \
|
||||
.name = "pulse_a8" \
|
||||
}
|
||||
#endif /* PULSE_ENCODER_TMRA_8_CONFIG */
|
||||
#endif /* BSP_USING_PULSE_ENCODER_TMRA_8 */
|
||||
|
||||
#ifdef BSP_USING_PULSE_ENCODER_TMRA_9
|
||||
#ifndef PULSE_ENCODER_TMRA_9_CONFIG
|
||||
#define PULSE_ENCODER_TMRA_9_CONFIG \
|
||||
{ \
|
||||
.tmr_handler = CM_TMRA_9, \
|
||||
.u32PeriphClock = FCG2_PERIPH_TMRA_9, \
|
||||
.hw_count = \
|
||||
{ \
|
||||
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
|
||||
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
|
||||
}, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc_Ovf = INT_SRC_TMRA_9_OVF, \
|
||||
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_NUM, \
|
||||
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_PRIO, \
|
||||
.enIntSrc_Udf = INT_SRC_TMRA_9_UDF, \
|
||||
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_NUM, \
|
||||
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_PRIO, \
|
||||
}, \
|
||||
.u32PeriodValue = 1000UL, \
|
||||
.name = "pulse_a9" \
|
||||
}
|
||||
#endif /* PULSE_ENCODER_TMRA_9_CONFIG */
|
||||
#endif /* BSP_USING_PULSE_ENCODER_TMRA_9 */
|
||||
|
||||
#ifdef BSP_USING_PULSE_ENCODER_TMRA_10
|
||||
#ifndef PULSE_ENCODER_TMRA_10_CONFIG
|
||||
#define PULSE_ENCODER_TMRA_10_CONFIG \
|
||||
{ \
|
||||
.tmr_handler = CM_TMRA_10, \
|
||||
.u32PeriphClock = FCG2_PERIPH_TMRA_10, \
|
||||
.hw_count = \
|
||||
{ \
|
||||
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
|
||||
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
|
||||
}, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc_Ovf = INT_SRC_TMRA_10_OVF, \
|
||||
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_NUM, \
|
||||
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_PRIO, \
|
||||
.enIntSrc_Udf = INT_SRC_TMRA_10_UDF, \
|
||||
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_NUM, \
|
||||
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_PRIO, \
|
||||
}, \
|
||||
.u32PeriodValue = 1000UL, \
|
||||
.name = "pulse_a10" \
|
||||
}
|
||||
#endif /* PULSE_ENCODER_TMRA_10_CONFIG */
|
||||
#endif /* BSP_USING_PULSE_ENCODER_TMRA_10 */
|
||||
|
||||
#ifdef BSP_USING_PULSE_ENCODER_TMRA_11
|
||||
#ifndef PULSE_ENCODER_TMRA_11_CONFIG
|
||||
#define PULSE_ENCODER_TMRA_11_CONFIG \
|
||||
{ \
|
||||
.tmr_handler = CM_TMRA_11, \
|
||||
.u32PeriphClock = FCG2_PERIPH_TMRA_11, \
|
||||
.hw_count = \
|
||||
{ \
|
||||
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
|
||||
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
|
||||
}, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc_Ovf = INT_SRC_TMRA_11_OVF, \
|
||||
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_NUM, \
|
||||
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_PRIO, \
|
||||
.enIntSrc_Udf = INT_SRC_TMRA_11_UDF, \
|
||||
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_NUM, \
|
||||
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_PRIO, \
|
||||
}, \
|
||||
.u32PeriodValue = 1000UL, \
|
||||
.name = "pulse_a11" \
|
||||
}
|
||||
#endif /* PULSE_ENCODER_TMRA_11_CONFIG */
|
||||
#endif /* BSP_USING_PULSE_ENCODER_TMRA_11 */
|
||||
|
||||
#ifdef BSP_USING_PULSE_ENCODER_TMRA_12
|
||||
#ifndef PULSE_ENCODER_TMRA_12_CONFIG
|
||||
#define PULSE_ENCODER_TMRA_12_CONFIG \
|
||||
{ \
|
||||
.tmr_handler = CM_TMRA_12, \
|
||||
.u32PeriphClock = FCG2_PERIPH_TMRA_12, \
|
||||
.hw_count = \
|
||||
{ \
|
||||
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
|
||||
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
|
||||
}, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc_Ovf = INT_SRC_TMRA_12_OVF, \
|
||||
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_NUM, \
|
||||
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_PRIO, \
|
||||
.enIntSrc_Udf = INT_SRC_TMRA_12_UDF, \
|
||||
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_NUM, \
|
||||
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_PRIO, \
|
||||
}, \
|
||||
.u32PeriodValue = 1000UL, \
|
||||
.name = "pulse_a12" \
|
||||
}
|
||||
#endif /* PULSE_ENCODER_TMRA_12_CONFIG */
|
||||
#endif /* BSP_USING_PULSE_ENCODER_TMRA_12 */
|
||||
|
||||
#ifdef BSP_USING_PULSE_ENCODER_TMR6_1
|
||||
#ifndef PULSE_ENCODER_TMR6_1_CONFIG
|
||||
#define PULSE_ENCODER_TMR6_1_CONFIG \
|
||||
{ \
|
||||
.tmr_handler = CM_TMR6_1, \
|
||||
.u32PeriphClock = FCG2_PERIPH_TMR6_1, \
|
||||
.hw_count = \
|
||||
{ \
|
||||
.u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \
|
||||
.u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \
|
||||
}, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc_Ovf = INT_SRC_TMR6_1_OVF, \
|
||||
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM, \
|
||||
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO, \
|
||||
.enIntSrc_Udf = INT_SRC_TMR6_1_UDF, \
|
||||
.enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM, \
|
||||
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO, \
|
||||
}, \
|
||||
.u32PeriodValue = 1000UL, \
|
||||
.name = "pulse_61" \
|
||||
}
|
||||
#endif /* PULSE_ENCODER_TMR6_1_CONFIG */
|
||||
#endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */
|
||||
|
||||
#ifdef BSP_USING_PULSE_ENCODER_TMR6_2
|
||||
#ifndef PULSE_ENCODER_TMR6_2_CONFIG
|
||||
#define PULSE_ENCODER_TMR6_2_CONFIG \
|
||||
{ \
|
||||
.tmr_handler = CM_TMR6_2, \
|
||||
.u32PeriphClock = FCG2_PERIPH_TMR6_2, \
|
||||
.hw_count = \
|
||||
{ \
|
||||
.u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \
|
||||
.u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \
|
||||
}, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc_Ovf = INT_SRC_TMR6_2_OVF, \
|
||||
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM, \
|
||||
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO, \
|
||||
.enIntSrc_Udf = INT_SRC_TMR6_2_UDF, \
|
||||
.enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM, \
|
||||
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO, \
|
||||
}, \
|
||||
.u32PeriodValue = 1000UL, \
|
||||
.name = "pulse_62" \
|
||||
}
|
||||
#endif /* PULSE_ENCODER_TMR6_2_CONFIG */
|
||||
#endif /* BSP_USING_PULSE_ENCODER_TMR6_2 */
|
||||
|
||||
#ifdef BSP_USING_PULSE_ENCODER_TMR6_3
|
||||
#ifndef PULSE_ENCODER_TMR6_3_CONFIG
|
||||
#define PULSE_ENCODER_TMR6_3_CONFIG \
|
||||
{ \
|
||||
.tmr_handler = CM_TMR6_3, \
|
||||
.u32PeriphClock = FCG2_PERIPH_TMR6_3, \
|
||||
.hw_count = \
|
||||
{ \
|
||||
.u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \
|
||||
.u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \
|
||||
}, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc_Ovf = INT_SRC_TMR6_3_OVF, \
|
||||
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_NUM, \
|
||||
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_PRIO, \
|
||||
.enIntSrc_Udf = INT_SRC_TMR6_3_UDF, \
|
||||
.enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_NUM, \
|
||||
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_PRIO, \
|
||||
}, \
|
||||
.u32PeriodValue = 1000UL, \
|
||||
.name = "pulse_63" \
|
||||
}
|
||||
#endif /* PULSE_ENCODER_TMR6_3_CONFIG */
|
||||
#endif /* BSP_USING_PULSE_ENCODER_TMR6_3 */
|
||||
|
||||
#ifdef BSP_USING_PULSE_ENCODER_TMR6_4
|
||||
#ifndef PULSE_ENCODER_TMR6_4_CONFIG
|
||||
#define PULSE_ENCODER_TMR6_4_CONFIG \
|
||||
{ \
|
||||
.tmr_handler = CM_TMR6_4, \
|
||||
.u32PeriphClock = FCG2_PERIPH_TMR6_4, \
|
||||
.hw_count = \
|
||||
{ \
|
||||
.u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \
|
||||
.u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \
|
||||
}, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc_Ovf = INT_SRC_TMR6_4_OVF, \
|
||||
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_NUM, \
|
||||
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_PRIO, \
|
||||
.enIntSrc_Udf = INT_SRC_TMR6_4_UDF, \
|
||||
.enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_NUM, \
|
||||
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_PRIO, \
|
||||
}, \
|
||||
.u32PeriodValue = 1000UL, \
|
||||
.name = "pulse_64" \
|
||||
}
|
||||
#endif /* PULSE_ENCODER_TMR6_4_CONFIG */
|
||||
#endif /* BSP_USING_PULSE_ENCODER_TMR6_4 */
|
||||
|
||||
#ifdef BSP_USING_PULSE_ENCODER_TMR6_5
|
||||
#ifndef PULSE_ENCODER_TMR6_5_CONFIG
|
||||
#define PULSE_ENCODER_TMR6_5_CONFIG \
|
||||
{ \
|
||||
.tmr_handler = CM_TMR6_5, \
|
||||
.u32PeriphClock = FCG2_PERIPH_TMR6_5, \
|
||||
.hw_count = \
|
||||
{ \
|
||||
.u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \
|
||||
.u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \
|
||||
}, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc_Ovf = INT_SRC_TMR6_5_OVF, \
|
||||
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_NUM, \
|
||||
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_PRIO, \
|
||||
.enIntSrc_Udf = INT_SRC_TMR6_5_UDF, \
|
||||
.enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_NUM, \
|
||||
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_PRIO, \
|
||||
}, \
|
||||
.u32PeriodValue = 1000UL, \
|
||||
.name = "pulse_65" \
|
||||
}
|
||||
#endif /* PULSE_ENCODER_TMR6_5_CONFIG */
|
||||
#endif /* BSP_USING_PULSE_ENCODER_TMR6_5 */
|
||||
|
||||
#ifdef BSP_USING_PULSE_ENCODER_TMR6_6
|
||||
#ifndef PULSE_ENCODER_TMR6_6_CONFIG
|
||||
#define PULSE_ENCODER_TMR6_6_CONFIG \
|
||||
{ \
|
||||
.tmr_handler = CM_TMR6_6, \
|
||||
.u32PeriphClock = FCG2_PERIPH_TMR6_6, \
|
||||
.hw_count = \
|
||||
{ \
|
||||
.u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \
|
||||
.u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \
|
||||
}, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc_Ovf = INT_SRC_TMR6_6_OVF, \
|
||||
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_NUM, \
|
||||
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_PRIO, \
|
||||
.enIntSrc_Udf = INT_SRC_TMR6_6_UDF, \
|
||||
.enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_NUM, \
|
||||
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_PRIO, \
|
||||
}, \
|
||||
.u32PeriodValue = 1000UL, \
|
||||
.name = "pulse_66" \
|
||||
}
|
||||
#endif /* PULSE_ENCODER_TMR6_6_CONFIG */
|
||||
#endif /* BSP_USING_PULSE_ENCODER_TMR6_6 */
|
||||
|
||||
#ifdef BSP_USING_PULSE_ENCODER_TMR6_7
|
||||
#ifndef PULSE_ENCODER_TMR6_7_CONFIG
|
||||
#define PULSE_ENCODER_TMR6_7_CONFIG \
|
||||
{ \
|
||||
.tmr_handler = CM_TMR6_7, \
|
||||
.u32PeriphClock = FCG2_PERIPH_TMR6_7, \
|
||||
.hw_count = \
|
||||
{ \
|
||||
.u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \
|
||||
.u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \
|
||||
}, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc_Ovf = INT_SRC_TMR6_7_OVF, \
|
||||
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_NUM, \
|
||||
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_PRIO, \
|
||||
.enIntSrc_Udf = INT_SRC_TMR6_7_UDF, \
|
||||
.enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_NUM, \
|
||||
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_PRIO, \
|
||||
}, \
|
||||
.u32PeriodValue = 1000UL, \
|
||||
.name = "pulse_67" \
|
||||
}
|
||||
#endif /* PULSE_ENCODER_TMR6_7_CONFIG */
|
||||
#endif /* BSP_USING_PULSE_ENCODER_TMR6_7 */
|
||||
|
||||
#ifdef BSP_USING_PULSE_ENCODER_TMR6_8
|
||||
#ifndef PULSE_ENCODER_TMR6_8_CONFIG
|
||||
#define PULSE_ENCODER_TMR6_8_CONFIG \
|
||||
{ \
|
||||
.tmr_handler = CM_TMR6_8, \
|
||||
.u32PeriphClock = FCG2_PERIPH_TMR6_8, \
|
||||
.hw_count = \
|
||||
{ \
|
||||
.u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \
|
||||
.u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \
|
||||
}, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc_Ovf = INT_SRC_TMR6_8_OVF, \
|
||||
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_NUM, \
|
||||
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_PRIO, \
|
||||
.enIntSrc_Udf = INT_SRC_TMR6_8_UDF, \
|
||||
.enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_NUM, \
|
||||
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_PRIO, \
|
||||
}, \
|
||||
.u32PeriodValue = 1000UL, \
|
||||
.name = "pulse_68" \
|
||||
}
|
||||
#endif /* PULSE_ENCODER_TMR6_8_CONFIG */
|
||||
#endif /* BSP_USING_PULSE_ENCODER_TMR6_8 */
|
||||
|
||||
#endif /* RT_USING_PULSE_ENCODER */
|
||||
|
||||
#endif /* __PULSE_ENCODER_CONFIG_H__ */
|
||||
|
|
@ -0,0 +1,881 @@
|
|||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2023-02-22 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __PWM_TMR_CONFIG_H__
|
||||
#define __PWM_TMR_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_PWM_TMRA
|
||||
|
||||
#ifdef BSP_USING_PWM_TMRA_1
|
||||
#ifndef PWM_TMRA_1_CONFIG
|
||||
#define PWM_TMRA_1_CONFIG \
|
||||
{ \
|
||||
.name = "pwm_a1", \
|
||||
.instance = CM_TMRA_1, \
|
||||
.channel = 0, \
|
||||
.stcTmraInit = \
|
||||
{ \
|
||||
.u8CountSrc = TMRA_CNT_SRC_SW, \
|
||||
.u32PeriodValue = 0xFFFF, \
|
||||
.sw_count = \
|
||||
{ \
|
||||
.u8ClockDiv = TMRA_CLK_DIV1, \
|
||||
.u8CountMode = TMRA_MD_SAWTOOTH, \
|
||||
.u8CountDir = TMRA_DIR_DOWN, \
|
||||
}, \
|
||||
.u8CountReload = TMRA_CNT_RELOAD_ENABLE\
|
||||
}, \
|
||||
.stcPwmInit = \
|
||||
{ \
|
||||
.u32CompareValue = 0x0000, \
|
||||
.u16StartPolarity = TMRA_PWM_LOW, \
|
||||
.u16StopPolarity = TMRA_PWM_LOW, \
|
||||
.u16CompareMatchPolarity = TMRA_PWM_HIGH, \
|
||||
.u16PeriodMatchPolarity = TMRA_PWM_LOW, \
|
||||
}, \
|
||||
}
|
||||
#endif /* PWM_TMRA_1_CONFIG */
|
||||
#endif /* BSP_USING_PWM_TMRA_1 */
|
||||
|
||||
#ifdef BSP_USING_PWM_TMRA_2
|
||||
#ifndef PWM_TMRA_2_CONFIG
|
||||
#define PWM_TMRA_2_CONFIG \
|
||||
{ \
|
||||
.name = "pwm_a2", \
|
||||
.instance = CM_TMRA_2, \
|
||||
.channel = 0, \
|
||||
.stcTmraInit = \
|
||||
{ \
|
||||
.u8CountSrc = TMRA_CNT_SRC_SW, \
|
||||
.u32PeriodValue = 0xFFFF, \
|
||||
.sw_count = \
|
||||
{ \
|
||||
.u8ClockDiv = TMRA_CLK_DIV1, \
|
||||
.u8CountMode = TMRA_MD_SAWTOOTH, \
|
||||
.u8CountDir = TMRA_DIR_DOWN, \
|
||||
}, \
|
||||
.u8CountReload = TMRA_CNT_RELOAD_ENABLE\
|
||||
}, \
|
||||
.stcPwmInit = \
|
||||
{ \
|
||||
.u32CompareValue = 0x0000, \
|
||||
.u16StartPolarity = TMRA_PWM_LOW, \
|
||||
.u16StopPolarity = TMRA_PWM_LOW, \
|
||||
.u16CompareMatchPolarity = TMRA_PWM_HIGH, \
|
||||
.u16PeriodMatchPolarity = TMRA_PWM_LOW, \
|
||||
}, \
|
||||
}
|
||||
#endif /* PWM_TMRA_2_CONFIG */
|
||||
#endif /* BSP_USING_PWM_TMRA_2 */
|
||||
|
||||
#ifdef BSP_USING_PWM_TMRA_3
|
||||
#ifndef PWM_TMRA_3_CONFIG
|
||||
#define PWM_TMRA_3_CONFIG \
|
||||
{ \
|
||||
.name = "pwm_a3", \
|
||||
.instance = CM_TMRA_3, \
|
||||
.channel = 0, \
|
||||
.stcTmraInit = \
|
||||
{ \
|
||||
.u8CountSrc = TMRA_CNT_SRC_SW, \
|
||||
.u32PeriodValue = 0xFFFF, \
|
||||
.sw_count = \
|
||||
{ \
|
||||
.u8ClockDiv = TMRA_CLK_DIV1, \
|
||||
.u8CountMode = TMRA_MD_SAWTOOTH, \
|
||||
.u8CountDir = TMRA_DIR_DOWN, \
|
||||
}, \
|
||||
.u8CountReload = TMRA_CNT_RELOAD_ENABLE\
|
||||
}, \
|
||||
.stcPwmInit = \
|
||||
{ \
|
||||
.u32CompareValue = 0x0000, \
|
||||
.u16StartPolarity = TMRA_PWM_LOW, \
|
||||
.u16StopPolarity = TMRA_PWM_LOW, \
|
||||
.u16CompareMatchPolarity = TMRA_PWM_HIGH, \
|
||||
.u16PeriodMatchPolarity = TMRA_PWM_LOW, \
|
||||
}, \
|
||||
}
|
||||
#endif /* PWM_TMRA_3_CONFIG */
|
||||
#endif /* BSP_USING_PWM_TMRA_3 */
|
||||
|
||||
#ifdef BSP_USING_PWM_TMRA_4
|
||||
#ifndef PWM_TMRA_4_CONFIG
|
||||
#define PWM_TMRA_4_CONFIG \
|
||||
{ \
|
||||
.name = "pwm_a4", \
|
||||
.instance = CM_TMRA_4, \
|
||||
.channel = 0, \
|
||||
.stcTmraInit = \
|
||||
{ \
|
||||
.u8CountSrc = TMRA_CNT_SRC_SW, \
|
||||
.u32PeriodValue = 0xFFFF, \
|
||||
.sw_count = \
|
||||
{ \
|
||||
.u8ClockDiv = TMRA_CLK_DIV1, \
|
||||
.u8CountMode = TMRA_MD_SAWTOOTH, \
|
||||
.u8CountDir = TMRA_DIR_DOWN, \
|
||||
}, \
|
||||
.u8CountReload = TMRA_CNT_RELOAD_ENABLE\
|
||||
}, \
|
||||
.stcPwmInit = \
|
||||
{ \
|
||||
.u32CompareValue = 0x0000, \
|
||||
.u16StartPolarity = TMRA_PWM_LOW, \
|
||||
.u16StopPolarity = TMRA_PWM_LOW, \
|
||||
.u16CompareMatchPolarity = TMRA_PWM_HIGH, \
|
||||
.u16PeriodMatchPolarity = TMRA_PWM_LOW, \
|
||||
}, \
|
||||
}
|
||||
#endif /* PWM_TMRA_4_CONFIG */
|
||||
#endif /* BSP_USING_PWM_TMRA_4 */
|
||||
|
||||
#ifdef BSP_USING_PWM_TMRA_5
|
||||
#ifndef PWM_TMRA_5_CONFIG
|
||||
#define PWM_TMRA_5_CONFIG \
|
||||
{ \
|
||||
.name = "pwm_a5", \
|
||||
.instance = CM_TMRA_5, \
|
||||
.channel = 0, \
|
||||
.stcTmraInit = \
|
||||
{ \
|
||||
.u8CountSrc = TMRA_CNT_SRC_SW, \
|
||||
.u32PeriodValue = 0xFFFF, \
|
||||
.sw_count = \
|
||||
{ \
|
||||
.u8ClockDiv = TMRA_CLK_DIV1, \
|
||||
.u8CountMode = TMRA_MD_SAWTOOTH, \
|
||||
.u8CountDir = TMRA_DIR_DOWN, \
|
||||
}, \
|
||||
.u8CountReload = TMRA_CNT_RELOAD_ENABLE\
|
||||
}, \
|
||||
.stcPwmInit = \
|
||||
{ \
|
||||
.u32CompareValue = 0x0000, \
|
||||
.u16StartPolarity = TMRA_PWM_LOW, \
|
||||
.u16StopPolarity = TMRA_PWM_LOW, \
|
||||
.u16CompareMatchPolarity = TMRA_PWM_HIGH, \
|
||||
.u16PeriodMatchPolarity = TMRA_PWM_LOW, \
|
||||
}, \
|
||||
}
|
||||
#endif /* PWM_TMRA_5_CONFIG */
|
||||
#endif /* BSP_USING_PWM_TMRA_5 */
|
||||
|
||||
#ifdef BSP_USING_PWM_TMRA_6
|
||||
#ifndef PWM_TMRA_6_CONFIG
|
||||
#define PWM_TMRA_6_CONFIG \
|
||||
{ \
|
||||
.name = "pwm_a6", \
|
||||
.instance = CM_TMRA_6, \
|
||||
.channel = 0, \
|
||||
.stcTmraInit = \
|
||||
{ \
|
||||
.u8CountSrc = TMRA_CNT_SRC_SW, \
|
||||
.u32PeriodValue = 0xFFFF, \
|
||||
.sw_count = \
|
||||
{ \
|
||||
.u8ClockDiv = TMRA_CLK_DIV1, \
|
||||
.u8CountMode = TMRA_MD_SAWTOOTH, \
|
||||
.u8CountDir = TMRA_DIR_DOWN, \
|
||||
}, \
|
||||
.u8CountReload = TMRA_CNT_RELOAD_ENABLE\
|
||||
}, \
|
||||
.stcPwmInit = \
|
||||
{ \
|
||||
.u32CompareValue = 0x0000, \
|
||||
.u16StartPolarity = TMRA_PWM_LOW, \
|
||||
.u16StopPolarity = TMRA_PWM_LOW, \
|
||||
.u16CompareMatchPolarity = TMRA_PWM_HIGH, \
|
||||
.u16PeriodMatchPolarity = TMRA_PWM_LOW, \
|
||||
}, \
|
||||
}
|
||||
#endif /* PWM_TMRA_6_CONFIG */
|
||||
#endif /* BSP_USING_PWM_TMRA_6 */
|
||||
|
||||
#ifdef BSP_USING_PWM_TMRA_7
|
||||
#ifndef PWM_TMRA_7_CONFIG
|
||||
#define PWM_TMRA_7_CONFIG \
|
||||
{ \
|
||||
.name = "pwm_a7", \
|
||||
.instance = CM_TMRA_7, \
|
||||
.channel = 0, \
|
||||
.stcTmraInit = \
|
||||
{ \
|
||||
.u8CountSrc = TMRA_CNT_SRC_SW, \
|
||||
.u32PeriodValue = 0xFFFF, \
|
||||
.sw_count = \
|
||||
{ \
|
||||
.u8ClockDiv = TMRA_CLK_DIV1, \
|
||||
.u8CountMode = TMRA_MD_SAWTOOTH, \
|
||||
.u8CountDir = TMRA_DIR_DOWN, \
|
||||
}, \
|
||||
.u8CountReload = TMRA_CNT_RELOAD_ENABLE\
|
||||
}, \
|
||||
.stcPwmInit = \
|
||||
{ \
|
||||
.u32CompareValue = 0x0000, \
|
||||
.u16StartPolarity = TMRA_PWM_LOW, \
|
||||
.u16StopPolarity = TMRA_PWM_LOW, \
|
||||
.u16CompareMatchPolarity = TMRA_PWM_HIGH, \
|
||||
.u16PeriodMatchPolarity = TMRA_PWM_LOW, \
|
||||
}, \
|
||||
}
|
||||
#endif /* PWM_TMRA_7_CONFIG */
|
||||
#endif /* BSP_USING_PWM_TMRA_7 */
|
||||
|
||||
#ifdef BSP_USING_PWM_TMRA_8
|
||||
#ifndef PWM_TMRA_8_CONFIG
|
||||
#define PWM_TMRA_8_CONFIG \
|
||||
{ \
|
||||
.name = "pwm_a8", \
|
||||
.instance = CM_TMRA_8, \
|
||||
.channel = 0, \
|
||||
.stcTmraInit = \
|
||||
{ \
|
||||
.u8CountSrc = TMRA_CNT_SRC_SW, \
|
||||
.u32PeriodValue = 0xFFFF, \
|
||||
.sw_count = \
|
||||
{ \
|
||||
.u8ClockDiv = TMRA_CLK_DIV1, \
|
||||
.u8CountMode = TMRA_MD_SAWTOOTH, \
|
||||
.u8CountDir = TMRA_DIR_DOWN, \
|
||||
}, \
|
||||
.u8CountReload = TMRA_CNT_RELOAD_ENABLE\
|
||||
}, \
|
||||
.stcPwmInit = \
|
||||
{ \
|
||||
.u32CompareValue = 0x0000, \
|
||||
.u16StartPolarity = TMRA_PWM_LOW, \
|
||||
.u16StopPolarity = TMRA_PWM_LOW, \
|
||||
.u16CompareMatchPolarity = TMRA_PWM_HIGH, \
|
||||
.u16PeriodMatchPolarity = TMRA_PWM_LOW, \
|
||||
}, \
|
||||
}
|
||||
#endif /* PWM_TMRA_8_CONFIG */
|
||||
#endif /* BSP_USING_PWM_TMRA_8 */
|
||||
|
||||
#ifdef BSP_USING_PWM_TMRA_9
|
||||
#ifndef PWM_TMRA_9_CONFIG
|
||||
#define PWM_TMRA_9_CONFIG \
|
||||
{ \
|
||||
.name = "pwm_a9", \
|
||||
.instance = CM_TMRA_9, \
|
||||
.channel = 0, \
|
||||
.stcTmraInit = \
|
||||
{ \
|
||||
.u8CountSrc = TMRA_CNT_SRC_SW, \
|
||||
.u32PeriodValue = 0xFFFF, \
|
||||
.sw_count = \
|
||||
{ \
|
||||
.u8ClockDiv = TMRA_CLK_DIV1, \
|
||||
.u8CountMode = TMRA_MD_SAWTOOTH, \
|
||||
.u8CountDir = TMRA_DIR_DOWN, \
|
||||
}, \
|
||||
.u8CountReload = TMRA_CNT_RELOAD_ENABLE\
|
||||
}, \
|
||||
.stcPwmInit = \
|
||||
{ \
|
||||
.u32CompareValue = 0x0000, \
|
||||
.u16StartPolarity = TMRA_PWM_LOW, \
|
||||
.u16StopPolarity = TMRA_PWM_LOW, \
|
||||
.u16CompareMatchPolarity = TMRA_PWM_HIGH, \
|
||||
.u16PeriodMatchPolarity = TMRA_PWM_LOW, \
|
||||
}, \
|
||||
}
|
||||
#endif /* PWM_TMRA_9_CONFIG */
|
||||
#endif /* BSP_USING_PWM_TMRA_9 */
|
||||
|
||||
#ifdef BSP_USING_PWM_TMRA_10
|
||||
#ifndef PWM_TMRA_10_CONFIG
|
||||
#define PWM_TMRA_10_CONFIG \
|
||||
{ \
|
||||
.name = "pwm_a10", \
|
||||
.instance = CM_TMRA_10, \
|
||||
.channel = 0, \
|
||||
.stcTmraInit = \
|
||||
{ \
|
||||
.u8CountSrc = TMRA_CNT_SRC_SW, \
|
||||
.u32PeriodValue = 0xFFFF, \
|
||||
.sw_count = \
|
||||
{ \
|
||||
.u8ClockDiv = TMRA_CLK_DIV1, \
|
||||
.u8CountMode = TMRA_MD_SAWTOOTH, \
|
||||
.u8CountDir = TMRA_DIR_DOWN, \
|
||||
}, \
|
||||
.u8CountReload = TMRA_CNT_RELOAD_ENABLE\
|
||||
}, \
|
||||
.stcPwmInit = \
|
||||
{ \
|
||||
.u32CompareValue = 0x0000, \
|
||||
.u16StartPolarity = TMRA_PWM_LOW, \
|
||||
.u16StopPolarity = TMRA_PWM_LOW, \
|
||||
.u16CompareMatchPolarity = TMRA_PWM_HIGH, \
|
||||
.u16PeriodMatchPolarity = TMRA_PWM_LOW, \
|
||||
}, \
|
||||
}
|
||||
#endif /* PWM_TMRA_10_CONFIG */
|
||||
#endif /* BSP_USING_PWM_TMRA_10 */
|
||||
|
||||
#ifdef BSP_USING_PWM_TMRA_11
|
||||
#ifndef PWM_TMRA_11_CONFIG
|
||||
#define PWM_TMRA_11_CONFIG \
|
||||
{ \
|
||||
.name = "pwm_a11", \
|
||||
.instance = CM_TMRA_11, \
|
||||
.channel = 0, \
|
||||
.stcTmraInit = \
|
||||
{ \
|
||||
.u8CountSrc = TMRA_CNT_SRC_SW, \
|
||||
.u32PeriodValue = 0xFFFF, \
|
||||
.sw_count = \
|
||||
{ \
|
||||
.u8ClockDiv = TMRA_CLK_DIV1, \
|
||||
.u8CountMode = TMRA_MD_SAWTOOTH, \
|
||||
.u8CountDir = TMRA_DIR_DOWN, \
|
||||
}, \
|
||||
.u8CountReload = TMRA_CNT_RELOAD_ENABLE\
|
||||
}, \
|
||||
.stcPwmInit = \
|
||||
{ \
|
||||
.u32CompareValue = 0x0000, \
|
||||
.u16StartPolarity = TMRA_PWM_LOW, \
|
||||
.u16StopPolarity = TMRA_PWM_LOW, \
|
||||
.u16CompareMatchPolarity = TMRA_PWM_HIGH, \
|
||||
.u16PeriodMatchPolarity = TMRA_PWM_LOW, \
|
||||
}, \
|
||||
}
|
||||
#endif /* PWM_TMRA_11_CONFIG */
|
||||
#endif /* BSP_USING_PWM_TMRA_11 */
|
||||
|
||||
#ifdef BSP_USING_PWM_TMRA_12
|
||||
#ifndef PWM_TMRA_12_CONFIG
|
||||
#define PWM_TMRA_12_CONFIG \
|
||||
{ \
|
||||
.name = "pwm_a12", \
|
||||
.instance = CM_TMRA_12, \
|
||||
.channel = 0, \
|
||||
.stcTmraInit = \
|
||||
{ \
|
||||
.u8CountSrc = TMRA_CNT_SRC_SW, \
|
||||
.u32PeriodValue = 0xFFFF, \
|
||||
.sw_count = \
|
||||
{ \
|
||||
.u8ClockDiv = TMRA_CLK_DIV1, \
|
||||
.u8CountMode = TMRA_MD_SAWTOOTH, \
|
||||
.u8CountDir = TMRA_DIR_DOWN, \
|
||||
}, \
|
||||
.u8CountReload = TMRA_CNT_RELOAD_ENABLE\
|
||||
}, \
|
||||
.stcPwmInit = \
|
||||
{ \
|
||||
.u32CompareValue = 0x0000, \
|
||||
.u16StartPolarity = TMRA_PWM_LOW, \
|
||||
.u16StopPolarity = TMRA_PWM_LOW, \
|
||||
.u16CompareMatchPolarity = TMRA_PWM_HIGH, \
|
||||
.u16PeriodMatchPolarity = TMRA_PWM_LOW, \
|
||||
}, \
|
||||
}
|
||||
#endif /* PWM_TMRA_12_CONFIG */
|
||||
#endif /* BSP_USING_PWM_TMRA_12 */
|
||||
|
||||
#endif /* BSP_USING_PWM_TMRA */
|
||||
|
||||
#ifdef BSP_USING_PWM_TMR4
|
||||
|
||||
#ifdef BSP_USING_PWM_TMR4_1
|
||||
#ifndef PWM_TMR4_1_CONFIG
|
||||
#define PWM_TMR4_1_CONFIG \
|
||||
{ \
|
||||
.name = "pwm_t41", \
|
||||
.instance = CM_TMR4_1, \
|
||||
.channel = 0, \
|
||||
.stcTmr4Init = \
|
||||
{ \
|
||||
.u16ClockDiv = TMR4_CLK_DIV1, \
|
||||
.u16PeriodValue = 0xFFFFU, \
|
||||
.u16CountMode = TMR4_MD_SAWTOOTH, \
|
||||
.u16ClockSrc = TMR4_CLK_SRC_INTERNCLK,\
|
||||
}, \
|
||||
.stcTmr4OcInit = \
|
||||
{ \
|
||||
.u16CompareValue = 0x0000, \
|
||||
.u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \
|
||||
.u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED,\
|
||||
.u16CompareValueBufCond = TMR4_OC_BUF_COND_IMMED, \
|
||||
.u16BufLinkTransObject = 0U, \
|
||||
}, \
|
||||
.stcTmr4PwmInit = \
|
||||
{ \
|
||||
.u16Mode = TMR4_PWM_MD_THROUGH, \
|
||||
.u16ClockDiv = TMR4_PWM_CLK_DIV1, \
|
||||
.u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD,\
|
||||
}, \
|
||||
}
|
||||
#endif /* PWM_TMR4_1_CONFIG */
|
||||
#endif /* BSP_USING_PWM_TMR4_1 */
|
||||
|
||||
#ifdef BSP_USING_PWM_TMR4_2
|
||||
#ifndef PWM_TMR4_2_CONFIG
|
||||
#define PWM_TMR4_2_CONFIG \
|
||||
{ \
|
||||
.name = "pwm_t42", \
|
||||
.instance = CM_TMR4_2, \
|
||||
.channel = 0, \
|
||||
.stcTmr4Init = \
|
||||
{ \
|
||||
.u16ClockDiv = TMR4_CLK_DIV1, \
|
||||
.u16PeriodValue = 0xFFFFU, \
|
||||
.u16CountMode = TMR4_MD_SAWTOOTH, \
|
||||
.u16ClockSrc = TMR4_CLK_SRC_INTERNCLK,\
|
||||
}, \
|
||||
.stcTmr4OcInit = \
|
||||
{ \
|
||||
.u16CompareValue = 0x0000, \
|
||||
.u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \
|
||||
.u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED,\
|
||||
.u16CompareValueBufCond = TMR4_OC_BUF_COND_IMMED, \
|
||||
.u16BufLinkTransObject = 0U, \
|
||||
}, \
|
||||
.stcTmr4PwmInit = \
|
||||
{ \
|
||||
.u16Mode = TMR4_PWM_MD_THROUGH, \
|
||||
.u16ClockDiv = TMR4_PWM_CLK_DIV1, \
|
||||
.u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD,\
|
||||
}, \
|
||||
}
|
||||
#endif /* PWM_TMR4_2_CONFIG */
|
||||
#endif /* BSP_USING_PWM_TMR4_2 */
|
||||
|
||||
#ifdef BSP_USING_PWM_TMR4_3
|
||||
#ifndef PWM_TMR4_3_CONFIG
|
||||
#define PWM_TMR4_3_CONFIG \
|
||||
{ \
|
||||
.name = "pwm_t43", \
|
||||
.instance = CM_TMR4_3, \
|
||||
.channel = 0, \
|
||||
.stcTmr4Init = \
|
||||
{ \
|
||||
.u16ClockDiv = TMR4_CLK_DIV1, \
|
||||
.u16PeriodValue = 0xFFFFU, \
|
||||
.u16CountMode = TMR4_MD_SAWTOOTH, \
|
||||
.u16ClockSrc = TMR4_CLK_SRC_INTERNCLK,\
|
||||
}, \
|
||||
.stcTmr4OcInit = \
|
||||
{ \
|
||||
.u16CompareValue = 0x0000, \
|
||||
.u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \
|
||||
.u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED,\
|
||||
.u16CompareValueBufCond = TMR4_OC_BUF_COND_IMMED, \
|
||||
.u16BufLinkTransObject = 0U, \
|
||||
}, \
|
||||
.stcTmr4PwmInit = \
|
||||
{ \
|
||||
.u16Mode = TMR4_PWM_MD_THROUGH, \
|
||||
.u16ClockDiv = TMR4_PWM_CLK_DIV1, \
|
||||
.u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD,\
|
||||
}, \
|
||||
}
|
||||
#endif /* PWM_TMR4_3_CONFIG */
|
||||
#endif /* BSP_USING_PWM_TMR4_3 */
|
||||
|
||||
#endif /* BSP_USING_PWM_TMR4 */
|
||||
|
||||
#ifdef BSP_USING_PWM_TMR6
|
||||
|
||||
#ifdef BSP_USING_PWM_TMR6_1
|
||||
#ifndef PWM_TMR6_1_CONFIG
|
||||
#define PWM_TMR6_1_CONFIG \
|
||||
{ \
|
||||
.name = "pwm_t61", \
|
||||
.instance = CM_TMR6_1, \
|
||||
.channel = 0, \
|
||||
.stcTmr6Init = \
|
||||
{ \
|
||||
.u8CountSrc = TMR6_CNT_SRC_SW, \
|
||||
.sw_count = \
|
||||
{ \
|
||||
.u32ClockDiv = TMR6_CLK_DIV1, \
|
||||
.u32CountMode = TMR6_MD_SAWTOOTH, \
|
||||
.u32CountDir = TMR6_CNT_UP, \
|
||||
}, \
|
||||
.u32PeriodValue = 0xFFFF, \
|
||||
.u32CountReload = TMR6_CNT_RELOAD_ON, \
|
||||
}, \
|
||||
.stcPwmInit = \
|
||||
{ \
|
||||
{ \
|
||||
.u32CompareValue = 0x0000, \
|
||||
.u32StartPolarity = TMR6_PWM_HIGH, \
|
||||
.u32StopPolarity = TMR6_PWM_HIGH, \
|
||||
.u32CountUpMatchAPolarity = TMR6_PWM_LOW, \
|
||||
.u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \
|
||||
.u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \
|
||||
.u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \
|
||||
.u32UdfPolarity = TMR6_PWM_HOLD, \
|
||||
.u32OvfPolarity = TMR6_PWM_HIGH, \
|
||||
}, \
|
||||
{ \
|
||||
.u32CompareValue = 0x0000, \
|
||||
.u32StartPolarity = TMR6_PWM_HIGH, \
|
||||
.u32StopPolarity = TMR6_PWM_HIGH, \
|
||||
.u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \
|
||||
.u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \
|
||||
.u32CountUpMatchBPolarity = TMR6_PWM_LOW, \
|
||||
.u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \
|
||||
.u32UdfPolarity = TMR6_PWM_HOLD, \
|
||||
.u32OvfPolarity = TMR6_PWM_HIGH, \
|
||||
} \
|
||||
}, \
|
||||
}
|
||||
#endif /* PWM_TMR6_1_CONFIG */
|
||||
#endif /* BSP_USING_PWM_TMR6_1 */
|
||||
#ifdef BSP_USING_PWM_TMR6_2
|
||||
#ifndef PWM_TMR6_2_CONFIG
|
||||
#define PWM_TMR6_2_CONFIG \
|
||||
{ \
|
||||
.name = "pwm_t62", \
|
||||
.instance = CM_TMR6_2, \
|
||||
.channel = 0, \
|
||||
.stcTmr6Init = \
|
||||
{ \
|
||||
.u8CountSrc = TMR6_CNT_SRC_SW, \
|
||||
.sw_count = \
|
||||
{ \
|
||||
.u32ClockDiv = TMR6_CLK_DIV1, \
|
||||
.u32CountMode = TMR6_MD_SAWTOOTH, \
|
||||
.u32CountDir = TMR6_CNT_UP, \
|
||||
}, \
|
||||
.u32PeriodValue = 0xFFFF, \
|
||||
.u32CountReload = TMR6_CNT_RELOAD_ON, \
|
||||
}, \
|
||||
.stcPwmInit = \
|
||||
{ \
|
||||
{ \
|
||||
.u32CompareValue = 0x0000, \
|
||||
.u32StartPolarity = TMR6_PWM_HIGH, \
|
||||
.u32StopPolarity = TMR6_PWM_HIGH, \
|
||||
.u32CountUpMatchAPolarity = TMR6_PWM_LOW, \
|
||||
.u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \
|
||||
.u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \
|
||||
.u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \
|
||||
.u32UdfPolarity = TMR6_PWM_HOLD, \
|
||||
.u32OvfPolarity = TMR6_PWM_HIGH, \
|
||||
}, \
|
||||
{ \
|
||||
.u32CompareValue = 0x0000, \
|
||||
.u32StartPolarity = TMR6_PWM_HIGH, \
|
||||
.u32StopPolarity = TMR6_PWM_HIGH, \
|
||||
.u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \
|
||||
.u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \
|
||||
.u32CountUpMatchBPolarity = TMR6_PWM_LOW, \
|
||||
.u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \
|
||||
.u32UdfPolarity = TMR6_PWM_HOLD, \
|
||||
.u32OvfPolarity = TMR6_PWM_HIGH, \
|
||||
} \
|
||||
}, \
|
||||
}
|
||||
#endif /* PWM_TMR6_2_CONFIG */
|
||||
#endif /* BSP_USING_PWM_TMR6_2 */
|
||||
#ifdef BSP_USING_PWM_TMR6_3
|
||||
#ifndef PWM_TMR6_3_CONFIG
|
||||
#define PWM_TMR6_3_CONFIG \
|
||||
{ \
|
||||
.name = "pwm_t63", \
|
||||
.instance = CM_TMR6_3, \
|
||||
.channel = 0, \
|
||||
.stcTmr6Init = \
|
||||
{ \
|
||||
.u8CountSrc = TMR6_CNT_SRC_SW, \
|
||||
.sw_count = \
|
||||
{ \
|
||||
.u32ClockDiv = TMR6_CLK_DIV1, \
|
||||
.u32CountMode = TMR6_MD_SAWTOOTH, \
|
||||
.u32CountDir = TMR6_CNT_UP, \
|
||||
}, \
|
||||
.u32PeriodValue = 0xFFFF, \
|
||||
.u32CountReload = TMR6_CNT_RELOAD_ON, \
|
||||
}, \
|
||||
.stcPwmInit = \
|
||||
{ \
|
||||
{ \
|
||||
.u32CompareValue = 0x0000, \
|
||||
.u32StartPolarity = TMR6_PWM_HIGH, \
|
||||
.u32StopPolarity = TMR6_PWM_HIGH, \
|
||||
.u32CountUpMatchAPolarity = TMR6_PWM_LOW, \
|
||||
.u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \
|
||||
.u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \
|
||||
.u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \
|
||||
.u32UdfPolarity = TMR6_PWM_HOLD, \
|
||||
.u32OvfPolarity = TMR6_PWM_HIGH, \
|
||||
}, \
|
||||
{ \
|
||||
.u32CompareValue = 0x0000, \
|
||||
.u32StartPolarity = TMR6_PWM_HIGH, \
|
||||
.u32StopPolarity = TMR6_PWM_HIGH, \
|
||||
.u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \
|
||||
.u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \
|
||||
.u32CountUpMatchBPolarity = TMR6_PWM_LOW, \
|
||||
.u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \
|
||||
.u32UdfPolarity = TMR6_PWM_HOLD, \
|
||||
.u32OvfPolarity = TMR6_PWM_HIGH, \
|
||||
} \
|
||||
}, \
|
||||
}
|
||||
#endif /* PWM_TMR6_3_CONFIG */
|
||||
#endif /* BSP_USING_PWM_TMR6_3 */
|
||||
#ifdef BSP_USING_PWM_TMR6_4
|
||||
#ifndef PWM_TMR6_4_CONFIG
|
||||
#define PWM_TMR6_4_CONFIG \
|
||||
{ \
|
||||
.name = "pwm_t64", \
|
||||
.instance = CM_TMR6_4, \
|
||||
.channel = 0, \
|
||||
.stcTmr6Init = \
|
||||
{ \
|
||||
.u8CountSrc = TMR6_CNT_SRC_SW, \
|
||||
.sw_count = \
|
||||
{ \
|
||||
.u32ClockDiv = TMR6_CLK_DIV1, \
|
||||
.u32CountMode = TMR6_MD_SAWTOOTH, \
|
||||
.u32CountDir = TMR6_CNT_UP, \
|
||||
}, \
|
||||
.u32PeriodValue = 0xFFFF, \
|
||||
.u32CountReload = TMR6_CNT_RELOAD_ON, \
|
||||
}, \
|
||||
.stcPwmInit = \
|
||||
{ \
|
||||
{ \
|
||||
.u32CompareValue = 0x0000, \
|
||||
.u32StartPolarity = TMR6_PWM_HIGH, \
|
||||
.u32StopPolarity = TMR6_PWM_HIGH, \
|
||||
.u32CountUpMatchAPolarity = TMR6_PWM_LOW, \
|
||||
.u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \
|
||||
.u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \
|
||||
.u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \
|
||||
.u32UdfPolarity = TMR6_PWM_HOLD, \
|
||||
.u32OvfPolarity = TMR6_PWM_HIGH, \
|
||||
}, \
|
||||
{ \
|
||||
.u32CompareValue = 0x0000, \
|
||||
.u32StartPolarity = TMR6_PWM_HIGH, \
|
||||
.u32StopPolarity = TMR6_PWM_HIGH, \
|
||||
.u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \
|
||||
.u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \
|
||||
.u32CountUpMatchBPolarity = TMR6_PWM_LOW, \
|
||||
.u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \
|
||||
.u32UdfPolarity = TMR6_PWM_HOLD, \
|
||||
.u32OvfPolarity = TMR6_PWM_HIGH, \
|
||||
} \
|
||||
}, \
|
||||
}
|
||||
#endif /* PWM_TMR6_4_CONFIG */
|
||||
#endif /* BSP_USING_PWM_TMR6_4 */
|
||||
#ifdef BSP_USING_PWM_TMR6_5
|
||||
#ifndef PWM_TMR6_5_CONFIG
|
||||
#define PWM_TMR6_5_CONFIG \
|
||||
{ \
|
||||
.name = "pwm_t65", \
|
||||
.instance = CM_TMR6_5, \
|
||||
.channel = 0, \
|
||||
.stcTmr6Init = \
|
||||
{ \
|
||||
.u8CountSrc = TMR6_CNT_SRC_SW, \
|
||||
.sw_count = \
|
||||
{ \
|
||||
.u32ClockDiv = TMR6_CLK_DIV1, \
|
||||
.u32CountMode = TMR6_MD_SAWTOOTH, \
|
||||
.u32CountDir = TMR6_CNT_UP, \
|
||||
}, \
|
||||
.u32PeriodValue = 0xFFFF, \
|
||||
.u32CountReload = TMR6_CNT_RELOAD_ON, \
|
||||
}, \
|
||||
.stcPwmInit = \
|
||||
{ \
|
||||
{ \
|
||||
.u32CompareValue = 0x0000, \
|
||||
.u32StartPolarity = TMR6_PWM_HIGH, \
|
||||
.u32StopPolarity = TMR6_PWM_HIGH, \
|
||||
.u32CountUpMatchAPolarity = TMR6_PWM_LOW, \
|
||||
.u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \
|
||||
.u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \
|
||||
.u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \
|
||||
.u32UdfPolarity = TMR6_PWM_HOLD, \
|
||||
.u32OvfPolarity = TMR6_PWM_HIGH, \
|
||||
}, \
|
||||
{ \
|
||||
.u32CompareValue = 0x0000, \
|
||||
.u32StartPolarity = TMR6_PWM_HIGH, \
|
||||
.u32StopPolarity = TMR6_PWM_HIGH, \
|
||||
.u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \
|
||||
.u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \
|
||||
.u32CountUpMatchBPolarity = TMR6_PWM_LOW, \
|
||||
.u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \
|
||||
.u32UdfPolarity = TMR6_PWM_HOLD, \
|
||||
.u32OvfPolarity = TMR6_PWM_HIGH, \
|
||||
} \
|
||||
}, \
|
||||
}
|
||||
#endif /* PWM_TMR6_5_CONFIG */
|
||||
#endif /* BSP_USING_PWM_TMR6_5 */
|
||||
#ifdef BSP_USING_PWM_TMR6_6
|
||||
#ifndef PWM_TMR6_6_CONFIG
|
||||
#define PWM_TMR6_6_CONFIG \
|
||||
{ \
|
||||
.name = "pwm_t66", \
|
||||
.instance = CM_TMR6_6, \
|
||||
.channel = 0, \
|
||||
.stcTmr6Init = \
|
||||
{ \
|
||||
.u8CountSrc = TMR6_CNT_SRC_SW, \
|
||||
.sw_count = \
|
||||
{ \
|
||||
.u32ClockDiv = TMR6_CLK_DIV1, \
|
||||
.u32CountMode = TMR6_MD_SAWTOOTH, \
|
||||
.u32CountDir = TMR6_CNT_UP, \
|
||||
}, \
|
||||
.u32PeriodValue = 0xFFFF, \
|
||||
.u32CountReload = TMR6_CNT_RELOAD_ON, \
|
||||
}, \
|
||||
.stcPwmInit = \
|
||||
{ \
|
||||
{ \
|
||||
.u32CompareValue = 0x0000, \
|
||||
.u32StartPolarity = TMR6_PWM_HIGH, \
|
||||
.u32StopPolarity = TMR6_PWM_HIGH, \
|
||||
.u32CountUpMatchAPolarity = TMR6_PWM_LOW, \
|
||||
.u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \
|
||||
.u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \
|
||||
.u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \
|
||||
.u32UdfPolarity = TMR6_PWM_HOLD, \
|
||||
.u32OvfPolarity = TMR6_PWM_HIGH, \
|
||||
}, \
|
||||
{ \
|
||||
.u32CompareValue = 0x0000, \
|
||||
.u32StartPolarity = TMR6_PWM_HIGH, \
|
||||
.u32StopPolarity = TMR6_PWM_HIGH, \
|
||||
.u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \
|
||||
.u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \
|
||||
.u32CountUpMatchBPolarity = TMR6_PWM_LOW, \
|
||||
.u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \
|
||||
.u32UdfPolarity = TMR6_PWM_HOLD, \
|
||||
.u32OvfPolarity = TMR6_PWM_HIGH, \
|
||||
} \
|
||||
}, \
|
||||
}
|
||||
#endif /* PWM_TMR6_6_CONFIG */
|
||||
#endif /* BSP_USING_PWM_TMR6_6 */
|
||||
#ifdef BSP_USING_PWM_TMR6_7
|
||||
#ifndef PWM_TMR6_7_CONFIG
|
||||
#define PWM_TMR6_7_CONFIG \
|
||||
{ \
|
||||
.name = "pwm_t67", \
|
||||
.instance = CM_TMR6_7, \
|
||||
.channel = 0, \
|
||||
.stcTmr6Init = \
|
||||
{ \
|
||||
.u8CountSrc = TMR6_CNT_SRC_SW, \
|
||||
.sw_count = \
|
||||
{ \
|
||||
.u32ClockDiv = TMR6_CLK_DIV1, \
|
||||
.u32CountMode = TMR6_MD_SAWTOOTH, \
|
||||
.u32CountDir = TMR6_CNT_UP, \
|
||||
}, \
|
||||
.u32PeriodValue = 0xFFFF, \
|
||||
.u32CountReload = TMR6_CNT_RELOAD_ON, \
|
||||
}, \
|
||||
.stcPwmInit = \
|
||||
{ \
|
||||
{ \
|
||||
.u32CompareValue = 0x0000, \
|
||||
.u32StartPolarity = TMR6_PWM_HIGH, \
|
||||
.u32StopPolarity = TMR6_PWM_HIGH, \
|
||||
.u32CountUpMatchAPolarity = TMR6_PWM_LOW, \
|
||||
.u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \
|
||||
.u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \
|
||||
.u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \
|
||||
.u32UdfPolarity = TMR6_PWM_HOLD, \
|
||||
.u32OvfPolarity = TMR6_PWM_HIGH, \
|
||||
}, \
|
||||
{ \
|
||||
.u32CompareValue = 0x0000, \
|
||||
.u32StartPolarity = TMR6_PWM_HIGH, \
|
||||
.u32StopPolarity = TMR6_PWM_HIGH, \
|
||||
.u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \
|
||||
.u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \
|
||||
.u32CountUpMatchBPolarity = TMR6_PWM_LOW, \
|
||||
.u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \
|
||||
.u32UdfPolarity = TMR6_PWM_HOLD, \
|
||||
.u32OvfPolarity = TMR6_PWM_HIGH, \
|
||||
} \
|
||||
}, \
|
||||
}
|
||||
#endif /* PWM_TMR6_7_CONFIG */
|
||||
#endif /* BSP_USING_PWM_TMR6_7 */
|
||||
#ifdef BSP_USING_PWM_TMR6_8
|
||||
#ifndef PWM_TMR6_8_CONFIG
|
||||
#define PWM_TMR6_8_CONFIG \
|
||||
{ \
|
||||
.name = "pwm_t68", \
|
||||
.instance = CM_TMR6_8, \
|
||||
.channel = 0, \
|
||||
.stcTmr6Init = \
|
||||
{ \
|
||||
.u8CountSrc = TMR6_CNT_SRC_SW, \
|
||||
.sw_count = \
|
||||
{ \
|
||||
.u32ClockDiv = TMR6_CLK_DIV1, \
|
||||
.u32CountMode = TMR6_MD_SAWTOOTH, \
|
||||
.u32CountDir = TMR6_CNT_UP, \
|
||||
}, \
|
||||
.u32PeriodValue = 0xFFFF, \
|
||||
.u32CountReload = TMR6_CNT_RELOAD_ON, \
|
||||
}, \
|
||||
.stcPwmInit = \
|
||||
{ \
|
||||
{ \
|
||||
.u32CompareValue = 0x0000, \
|
||||
.u32StartPolarity = TMR6_PWM_HIGH, \
|
||||
.u32StopPolarity = TMR6_PWM_HIGH, \
|
||||
.u32CountUpMatchAPolarity = TMR6_PWM_LOW, \
|
||||
.u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \
|
||||
.u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \
|
||||
.u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \
|
||||
.u32UdfPolarity = TMR6_PWM_HOLD, \
|
||||
.u32OvfPolarity = TMR6_PWM_HIGH, \
|
||||
}, \
|
||||
{ \
|
||||
.u32CompareValue = 0x0000, \
|
||||
.u32StartPolarity = TMR6_PWM_HIGH, \
|
||||
.u32StopPolarity = TMR6_PWM_HIGH, \
|
||||
.u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \
|
||||
.u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \
|
||||
.u32CountUpMatchBPolarity = TMR6_PWM_LOW, \
|
||||
.u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \
|
||||
.u32UdfPolarity = TMR6_PWM_HOLD, \
|
||||
.u32OvfPolarity = TMR6_PWM_HIGH, \
|
||||
} \
|
||||
}, \
|
||||
}
|
||||
#endif /* PWM_TMR6_8_CONFIG */
|
||||
#endif /* BSP_USING_PWM_TMR6_8 */
|
||||
|
||||
#endif /* BSP_USING_PWM_TMR6 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __PWM_TMRA_CONFIG_H__ */
|
||||
|
|
@ -0,0 +1,80 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
* Copyright (c) 2022-2025, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2025-04-15 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __QSPI_CONFIG_H__
|
||||
#define __QSPI_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "irq_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_QSPI
|
||||
#ifndef QSPI_BUS_CONFIG
|
||||
#define QSPI_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = CM_QSPI, \
|
||||
.clock = FCG1_PERIPH_QSPI, \
|
||||
.timeout = 5000UL, \
|
||||
.err_irq.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_QSPI_ERR_IRQ_NUM, \
|
||||
.irq_prio = BSP_QSPI_ERR_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_QSPI_INTR, \
|
||||
}, \
|
||||
}
|
||||
#endif /* QSPI_BUS_CONFIG */
|
||||
|
||||
#ifndef QSPI_INIT_PARAMS
|
||||
#define QSPI_INIT_PARAMS \
|
||||
{ \
|
||||
.u32PrefetchMode = QSPI_PREFETCH_MD_INVD, \
|
||||
.u32SetupTime = QSPI_QSSN_SETUP_ADVANCE_QSCK0P5, \
|
||||
.u32ReleaseTime = QSPI_QSSN_RELEASE_DELAY_QSCK32, \
|
||||
.u32IntervalTime = QSPI_QSSN_INTERVAL_QSCK1, \
|
||||
}
|
||||
#endif /* QSPI_INIT_PARAMS */
|
||||
|
||||
#define QSPI_WP_PIN_LEVEL QSPI_WP_PIN_HIGH
|
||||
|
||||
#ifdef BSP_QSPI_USING_DMA
|
||||
#ifndef QSPI_DMA_CONFIG
|
||||
#define QSPI_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = QSPI_DMA_INSTANCE, \
|
||||
.channel = QSPI_DMA_CHANNEL, \
|
||||
.clock = QSPI_DMA_CLOCK, \
|
||||
.trigger_select = QSPI_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_AOS_STRG, \
|
||||
.flag = QSPI_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = QSPI_DMA_IRQn, \
|
||||
.irq_prio = QSPI_DMA_INT_PRIO, \
|
||||
.int_src = QSPI_DMA_INT_SRC, \
|
||||
} \
|
||||
}
|
||||
#endif /* QSPI_DMA_CONFIG */
|
||||
|
||||
/* unit: half-word, DMA data width of QSPI transmitting is 16bit */
|
||||
#ifndef QSPI_DMA_TX_BUFSIZE
|
||||
#define QSPI_DMA_TX_BUFSIZE 256
|
||||
#endif /* QSPI_DMA_TX_BUFSIZE */
|
||||
#endif /* BSP_QSPI_USING_DMA */
|
||||
#endif /* BSP_USING_QSPI */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__QSPI_CONFIG_H__ */
|
||||
|
|
@ -0,0 +1,93 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
* Copyright (c) 2022-2025, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2025-04-15 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __SDIO_CONFIG_H__
|
||||
#define __SDIO_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "irq_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(BSP_USING_SDIO1)
|
||||
#ifndef SDIO1_BUS_CONFIG
|
||||
#define SDIO1_BUS_CONFIG \
|
||||
{ \
|
||||
.name = "sdio1", \
|
||||
.instance = CM_SDIOC1, \
|
||||
.clock = FCG1_PERIPH_SDIOC1, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_SDIO1_IRQ_NUM, \
|
||||
.irq_prio = BSP_SDIO1_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_SDIOC1_SD, \
|
||||
}, \
|
||||
.dma_rx = \
|
||||
{ \
|
||||
.Instance = SDIO1_RX_DMA_INSTANCE, \
|
||||
.channel = SDIO1_RX_DMA_CHANNEL, \
|
||||
.clock = SDIO1_RX_DMA_CLOCK, \
|
||||
.trigger_select = SDIO1_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SDIOC1_DMAR, \
|
||||
}, \
|
||||
.dma_tx = \
|
||||
{ \
|
||||
.Instance = SDIO1_TX_DMA_INSTANCE, \
|
||||
.channel = SDIO1_TX_DMA_CHANNEL, \
|
||||
.clock = SDIO1_TX_DMA_CLOCK, \
|
||||
.trigger_select = SDIO1_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SDIOC1_DMAW, \
|
||||
}, \
|
||||
}
|
||||
#endif /* SDIO1_BUS_CONFIG */
|
||||
#endif /* BSP_USING_SDIO1 */
|
||||
|
||||
#if defined(BSP_USING_SDIO2)
|
||||
#ifndef SDIO2_BUS_CONFIG
|
||||
#define SDIO2_BUS_CONFIG \
|
||||
{ \
|
||||
.name = "sdio2", \
|
||||
.instance = CM_SDIOC2, \
|
||||
.clock = FCG1_PERIPH_SDIOC2, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_SDIO2_IRQ_NUM, \
|
||||
.irq_prio = BSP_SDIO2_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_SDIOC2_SD, \
|
||||
}, \
|
||||
.dma_rx = \
|
||||
{ \
|
||||
.Instance = SDIO2_RX_DMA_INSTANCE, \
|
||||
.channel = SDIO2_RX_DMA_CHANNEL, \
|
||||
.clock = SDIO2_RX_DMA_CLOCK, \
|
||||
.trigger_select = SDIO2_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SDIOC2_DMAR, \
|
||||
}, \
|
||||
.dma_tx = \
|
||||
{ \
|
||||
.Instance = SDIO2_TX_DMA_INSTANCE, \
|
||||
.channel = SDIO2_TX_DMA_CHANNEL, \
|
||||
.clock = SDIO2_TX_DMA_CLOCK, \
|
||||
.trigger_select = SDIO2_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SDIOC2_DMAW, \
|
||||
}, \
|
||||
}
|
||||
#endif /* SDIO2_BUS_CONFIG */
|
||||
#endif /* BSP_USING_SDIO2 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,376 @@
|
|||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __SPI_CONFIG_H__
|
||||
#define __SPI_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "irq_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef BSP_USING_SPI1
|
||||
#ifndef SPI1_BUS_CONFIG
|
||||
#define SPI1_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = CM_SPI1, \
|
||||
.bus_name = "spi1", \
|
||||
.clock = FCG1_PERIPH_SPI1, \
|
||||
.timeout = 5000UL, \
|
||||
.err_irq.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_SPI1_ERR_IRQ_NUM, \
|
||||
.irq_prio = BSP_SPI1_ERR_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_SPI1_SPEI, \
|
||||
}, \
|
||||
}
|
||||
#endif /* SPI1_BUS_CONFIG */
|
||||
#endif /* BSP_USING_SPI1 */
|
||||
|
||||
#ifdef BSP_SPI1_TX_USING_DMA
|
||||
#ifndef SPI1_TX_DMA_CONFIG
|
||||
#define SPI1_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI1_TX_DMA_INSTANCE, \
|
||||
.channel = SPI1_TX_DMA_CHANNEL, \
|
||||
.clock = SPI1_TX_DMA_CLOCK, \
|
||||
.trigger_select = SPI1_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SPI1_SPTI, \
|
||||
.flag = SPI1_TX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = SPI1_TX_DMA_IRQn, \
|
||||
.irq_prio = SPI1_TX_DMA_INT_PRIO, \
|
||||
.int_src = SPI1_TX_DMA_INT_SRC, \
|
||||
} \
|
||||
}
|
||||
#endif /* SPI1_TX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI1_TX_USING_DMA */
|
||||
|
||||
#ifdef BSP_SPI1_RX_USING_DMA
|
||||
#ifndef SPI1_RX_DMA_CONFIG
|
||||
#define SPI1_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI1_RX_DMA_INSTANCE, \
|
||||
.channel = SPI1_RX_DMA_CHANNEL, \
|
||||
.clock = SPI1_RX_DMA_CLOCK, \
|
||||
.trigger_select = SPI1_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SPI1_SPRI, \
|
||||
.flag = SPI1_RX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = SPI1_RX_DMA_IRQn, \
|
||||
.irq_prio = SPI1_RX_DMA_INT_PRIO, \
|
||||
.int_src = SPI1_RX_DMA_INT_SRC, \
|
||||
} \
|
||||
}
|
||||
#endif /* SPI1_RX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI1_RX_USING_DMA */
|
||||
|
||||
#ifdef BSP_USING_SPI2
|
||||
#ifndef SPI2_BUS_CONFIG
|
||||
#define SPI2_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = CM_SPI2, \
|
||||
.bus_name = "spi2", \
|
||||
.clock = FCG1_PERIPH_SPI2, \
|
||||
.timeout = 5000UL, \
|
||||
.err_irq.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_SPI2_ERR_IRQ_NUM, \
|
||||
.irq_prio = BSP_SPI2_ERR_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_SPI2_SPEI, \
|
||||
}, \
|
||||
}
|
||||
#endif /* SPI2_BUS_CONFIG */
|
||||
#endif /* BSP_USING_SPI2 */
|
||||
|
||||
#ifdef BSP_SPI2_TX_USING_DMA
|
||||
#ifndef SPI2_TX_DMA_CONFIG
|
||||
#define SPI2_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI2_TX_DMA_INSTANCE, \
|
||||
.channel = SPI2_TX_DMA_CHANNEL, \
|
||||
.clock = SPI2_TX_DMA_CLOCK, \
|
||||
.trigger_select = SPI2_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SPI2_SPTI, \
|
||||
.flag = SPI2_TX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = SPI2_TX_DMA_IRQn, \
|
||||
.irq_prio = SPI2_TX_DMA_INT_PRIO, \
|
||||
.int_src = SPI2_TX_DMA_INT_SRC, \
|
||||
} \
|
||||
}
|
||||
#endif /* SPI2_TX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI2_TX_USING_DMA */
|
||||
|
||||
#ifdef BSP_SPI2_RX_USING_DMA
|
||||
#ifndef SPI2_RX_DMA_CONFIG
|
||||
#define SPI2_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI2_RX_DMA_INSTANCE, \
|
||||
.channel = SPI2_RX_DMA_CHANNEL, \
|
||||
.clock = SPI2_RX_DMA_CLOCK, \
|
||||
.trigger_select = SPI2_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SPI2_SPRI, \
|
||||
.flag = SPI2_RX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = SPI2_RX_DMA_IRQn, \
|
||||
.irq_prio = SPI2_RX_DMA_INT_PRIO, \
|
||||
.int_src = SPI2_RX_DMA_INT_SRC, \
|
||||
} \
|
||||
}
|
||||
#endif /* SPI2_RX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI2_RX_USING_DMA */
|
||||
|
||||
#ifdef BSP_USING_SPI3
|
||||
#ifndef SPI3_BUS_CONFIG
|
||||
#define SPI3_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = CM_SPI3, \
|
||||
.bus_name = "spi3", \
|
||||
.clock = FCG1_PERIPH_SPI3, \
|
||||
.timeout = 5000UL, \
|
||||
.err_irq.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_SPI3_ERR_IRQ_NUM, \
|
||||
.irq_prio = BSP_SPI3_ERR_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_SPI3_SPEI, \
|
||||
}, \
|
||||
}
|
||||
#endif /* SPI3_BUS_CONFIG */
|
||||
#endif /* BSP_USING_SPI3 */
|
||||
|
||||
|
||||
#ifdef BSP_SPI3_TX_USING_DMA
|
||||
#ifndef SPI3_TX_DMA_CONFIG
|
||||
#define SPI3_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI3_TX_DMA_INSTANCE, \
|
||||
.channel = SPI3_TX_DMA_CHANNEL, \
|
||||
.clock = SPI3_TX_DMA_CLOCK, \
|
||||
.trigger_select = SPI3_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SPI3_SPTI, \
|
||||
.flag = SPI3_TX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = SPI3_TX_DMA_IRQn, \
|
||||
.irq_prio = SPI3_TX_DMA_INT_PRIO, \
|
||||
.int_src = SPI3_TX_DMA_INT_SRC, \
|
||||
} \
|
||||
}
|
||||
#endif /* SPI3_TX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI3_TX_USING_DMA */
|
||||
|
||||
#ifdef BSP_SPI3_RX_USING_DMA
|
||||
#ifndef SPI3_RX_DMA_CONFIG
|
||||
#define SPI3_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI3_RX_DMA_INSTANCE, \
|
||||
.channel = SPI3_RX_DMA_CHANNEL, \
|
||||
.clock = SPI3_RX_DMA_CLOCK, \
|
||||
.trigger_select = SPI3_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SPI3_SPRI, \
|
||||
.flag = SPI3_RX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = SPI3_RX_DMA_IRQn, \
|
||||
.irq_prio = SPI3_RX_DMA_INT_PRIO, \
|
||||
.int_src = SPI3_RX_DMA_INT_SRC, \
|
||||
} \
|
||||
}
|
||||
#endif /* SPI3_RX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI3_RX_USING_DMA */
|
||||
|
||||
#ifdef BSP_USING_SPI4
|
||||
#ifndef SPI4_BUS_CONFIG
|
||||
#define SPI4_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = CM_SPI4, \
|
||||
.bus_name = "spi4", \
|
||||
.clock = FCG1_PERIPH_SPI4, \
|
||||
.timeout = 5000UL, \
|
||||
.err_irq.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_SPI4_ERR_IRQ_NUM, \
|
||||
.irq_prio = BSP_SPI4_ERR_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_SPI4_SPEI, \
|
||||
}, \
|
||||
}
|
||||
#endif /* SPI4_BUS_CONFIG */
|
||||
#endif /* BSP_USING_SPI4 */
|
||||
|
||||
#ifdef BSP_SPI4_TX_USING_DMA
|
||||
#ifndef SPI4_TX_DMA_CONFIG
|
||||
#define SPI4_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI4_TX_DMA_INSTANCE, \
|
||||
.channel = SPI4_TX_DMA_CHANNEL, \
|
||||
.clock = SPI4_TX_DMA_CLOCK, \
|
||||
.trigger_select = SPI4_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SPI4_SPTI, \
|
||||
.flag = SPI4_TX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = SPI4_TX_DMA_IRQn, \
|
||||
.irq_prio = SPI4_TX_DMA_INT_PRIO, \
|
||||
.int_src = SPI4_TX_DMA_INT_SRC, \
|
||||
} \
|
||||
}
|
||||
#endif /* SPI4_TX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI4_TX_USING_DMA */
|
||||
|
||||
#ifdef BSP_SPI4_RX_USING_DMA
|
||||
#ifndef SPI4_RX_DMA_CONFIG
|
||||
#define SPI4_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI4_RX_DMA_INSTANCE, \
|
||||
.channel = SPI4_RX_DMA_CHANNEL, \
|
||||
.clock = SPI4_RX_DMA_CLOCK, \
|
||||
.trigger_select = SPI4_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SPI4_SPRI, \
|
||||
.flag = SPI4_RX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = SPI4_RX_DMA_IRQn, \
|
||||
.irq_prio = SPI4_RX_DMA_INT_PRIO, \
|
||||
.int_src = SPI4_RX_DMA_INT_SRC, \
|
||||
} \
|
||||
}
|
||||
#endif /* SPI4_RX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI4_RX_USING_DMA */
|
||||
|
||||
#ifdef BSP_USING_SPI5
|
||||
#ifndef SPI5_BUS_CONFIG
|
||||
#define SPI5_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = CM_SPI5, \
|
||||
.bus_name = "spi5", \
|
||||
.clock = FCG1_PERIPH_SPI5, \
|
||||
.timeout = 5000UL, \
|
||||
.err_irq.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_SPI5_ERR_IRQ_NUM, \
|
||||
.irq_prio = BSP_SPI5_ERR_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_SPI5_SPEI, \
|
||||
}, \
|
||||
}
|
||||
#endif /* SPI5_BUS_CONFIG */
|
||||
#endif /* BSP_USING_SPI5 */
|
||||
|
||||
#ifdef BSP_SPI5_TX_USING_DMA
|
||||
#ifndef SPI5_TX_DMA_CONFIG
|
||||
#define SPI5_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI5_TX_DMA_INSTANCE, \
|
||||
.channel = SPI5_TX_DMA_CHANNEL, \
|
||||
.clock = SPI5_TX_DMA_CLOCK, \
|
||||
.trigger_select = SPI5_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SPI5_SPTI, \
|
||||
.flag = SPI5_TX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = SPI5_TX_DMA_IRQn, \
|
||||
.irq_prio = SPI5_TX_DMA_INT_PRIO, \
|
||||
.int_src = SPI5_TX_DMA_INT_SRC, \
|
||||
} \
|
||||
}
|
||||
#endif /* SPI5_TX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI5_TX_USING_DMA */
|
||||
|
||||
#ifdef BSP_SPI5_RX_USING_DMA
|
||||
#ifndef SPI5_RX_DMA_CONFIG
|
||||
#define SPI5_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI5_RX_DMA_INSTANCE, \
|
||||
.channel = SPI5_RX_DMA_CHANNEL, \
|
||||
.clock = SPI5_RX_DMA_CLOCK, \
|
||||
.trigger_select = SPI5_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SPI5_SPRI, \
|
||||
.flag = SPI5_RX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = SPI5_RX_DMA_IRQn, \
|
||||
.irq_prio = SPI5_RX_DMA_INT_PRIO, \
|
||||
.int_src = SPI5_RX_DMA_INT_SRC, \
|
||||
} \
|
||||
}
|
||||
#endif /* SPI5_RX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI5_RX_USING_DMA */
|
||||
|
||||
#ifdef BSP_USING_SPI6
|
||||
#ifndef SPI6_BUS_CONFIG
|
||||
#define SPI6_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = CM_SPI6, \
|
||||
.bus_name = "spi6", \
|
||||
.clock = FCG1_PERIPH_SPI6, \
|
||||
.timeout = 5000UL, \
|
||||
.err_irq.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_SPI6_ERR_IRQ_NUM, \
|
||||
.irq_prio = BSP_SPI6_ERR_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_SPI6_SPEI, \
|
||||
}, \
|
||||
}
|
||||
#endif /* SPI6_BUS_CONFIG */
|
||||
#endif /* BSP_USING_SPI6 */
|
||||
|
||||
#ifdef BSP_SPI6_TX_USING_DMA
|
||||
#ifndef SPI6_TX_DMA_CONFIG
|
||||
#define SPI6_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI6_TX_DMA_INSTANCE, \
|
||||
.channel = SPI6_TX_DMA_CHANNEL, \
|
||||
.clock = SPI6_TX_DMA_CLOCK, \
|
||||
.trigger_select = SPI6_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SPI6_SPTI, \
|
||||
.flag = SPI6_TX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = SPI6_TX_DMA_IRQn, \
|
||||
.irq_prio = SPI6_TX_DMA_INT_PRIO, \
|
||||
.int_src = SPI6_TX_DMA_INT_SRC, \
|
||||
} \
|
||||
}
|
||||
#endif /* SPI6_TX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI6_TX_USING_DMA */
|
||||
|
||||
#ifdef BSP_SPI6_RX_USING_DMA
|
||||
#ifndef SPI6_RX_DMA_CONFIG
|
||||
#define SPI6_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI6_RX_DMA_INSTANCE, \
|
||||
.channel = SPI6_RX_DMA_CHANNEL, \
|
||||
.clock = SPI6_RX_DMA_CLOCK, \
|
||||
.trigger_select = SPI6_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SPI6_SPRI, \
|
||||
.flag = SPI6_RX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = SPI6_RX_DMA_IRQn, \
|
||||
.irq_prio = SPI6_RX_DMA_INT_PRIO, \
|
||||
.int_src = SPI6_RX_DMA_INT_SRC, \
|
||||
} \
|
||||
}
|
||||
#endif /* SPI6_RX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI6_RX_USING_DMA */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__SPI_CONFIG_H__ */
|
||||
|
|
@ -0,0 +1,247 @@
|
|||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2023-06-21 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __TMR_CONFIG_H__
|
||||
#define __TMR_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_TMRA_1
|
||||
#ifndef TMRA_1_CONFIG
|
||||
#define TMRA_1_CONFIG \
|
||||
{ \
|
||||
.tmr_handle = CM_TMRA_1, \
|
||||
.clock_source = CLK_BUS_PCLK0, \
|
||||
.clock = FCG2_PERIPH_TMRA_1, \
|
||||
.flag = TMRA_FLAG_OVF, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc = INT_SRC_TMRA_1_OVF, \
|
||||
.enIRQn = BSP_USING_TMRA_1_IRQ_NUM, \
|
||||
.u8Int_Prio = BSP_USING_TMRA_1_IRQ_PRIO, \
|
||||
}, \
|
||||
.name = "tmra_1" \
|
||||
}
|
||||
#endif /* TMRA_1_CONFIG */
|
||||
#endif /* BSP_USING_TMRA_1 */
|
||||
|
||||
#ifdef BSP_USING_TMRA_2
|
||||
#ifndef TMRA_2_CONFIG
|
||||
#define TMRA_2_CONFIG \
|
||||
{ \
|
||||
.tmr_handle = CM_TMRA_2, \
|
||||
.clock_source = CLK_BUS_PCLK0, \
|
||||
.clock = FCG2_PERIPH_TMRA_2, \
|
||||
.flag = TMRA_FLAG_OVF, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc = INT_SRC_TMRA_2_OVF, \
|
||||
.enIRQn = BSP_USING_TMRA_2_IRQ_NUM, \
|
||||
.u8Int_Prio = BSP_USING_TMRA_2_IRQ_PRIO, \
|
||||
}, \
|
||||
.name = "tmra_2" \
|
||||
}
|
||||
#endif /* TMRA_2_CONFIG */
|
||||
#endif /* BSP_USING_TMRA_2 */
|
||||
|
||||
#ifdef BSP_USING_TMRA_3
|
||||
#ifndef TMRA_3_CONFIG
|
||||
#define TMRA_3_CONFIG \
|
||||
{ \
|
||||
.tmr_handle = CM_TMRA_3, \
|
||||
.clock_source = CLK_BUS_PCLK0, \
|
||||
.clock = FCG2_PERIPH_TMRA_3, \
|
||||
.flag = TMRA_FLAG_OVF, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc = INT_SRC_TMRA_3_OVF, \
|
||||
.enIRQn = BSP_USING_TMRA_3_IRQ_NUM, \
|
||||
.u8Int_Prio = BSP_USING_TMRA_3_IRQ_PRIO, \
|
||||
}, \
|
||||
.name = "tmra_3" \
|
||||
}
|
||||
#endif /* TMRA_3_CONFIG */
|
||||
#endif /* BSP_USING_TMRA_3 */
|
||||
|
||||
#ifdef BSP_USING_TMRA_4
|
||||
#ifndef TMRA_4_CONFIG
|
||||
#define TMRA_4_CONFIG \
|
||||
{ \
|
||||
.tmr_handle = CM_TMRA_4, \
|
||||
.clock_source = CLK_BUS_PCLK0, \
|
||||
.clock = FCG2_PERIPH_TMRA_4, \
|
||||
.flag = TMRA_FLAG_OVF, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc = INT_SRC_TMRA_4_OVF, \
|
||||
.enIRQn = BSP_USING_TMRA_4_IRQ_NUM, \
|
||||
.u8Int_Prio = BSP_USING_TMRA_4_IRQ_PRIO, \
|
||||
}, \
|
||||
.name = "tmra_4" \
|
||||
}
|
||||
#endif /* TMRA_4_CONFIG */
|
||||
#endif /* BSP_USING_TMRA_4 */
|
||||
|
||||
#ifdef BSP_USING_TMRA_5
|
||||
#ifndef TMRA_5_CONFIG
|
||||
#define TMRA_5_CONFIG \
|
||||
{ \
|
||||
.tmr_handle = CM_TMRA_5, \
|
||||
.clock_source = CLK_BUS_PCLK1, \
|
||||
.clock = FCG2_PERIPH_TMRA_5, \
|
||||
.flag = TMRA_FLAG_OVF, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc = INT_SRC_TMRA_5_OVF, \
|
||||
.enIRQn = BSP_USING_TMRA_5_IRQ_NUM, \
|
||||
.u8Int_Prio = BSP_USING_TMRA_5_IRQ_PRIO, \
|
||||
}, \
|
||||
.name = "tmra_5" \
|
||||
}
|
||||
#endif /* TMRA_5_CONFIG */
|
||||
#endif /* BSP_USING_TMRA_5 */
|
||||
|
||||
#ifdef BSP_USING_TMRA_6
|
||||
#ifndef TMRA_6_CONFIG
|
||||
#define TMRA_6_CONFIG \
|
||||
{ \
|
||||
.tmr_handle = CM_TMRA_6, \
|
||||
.clock_source = CLK_BUS_PCLK1, \
|
||||
.clock = FCG2_PERIPH_TMRA_6, \
|
||||
.flag = TMRA_FLAG_OVF, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc = INT_SRC_TMRA_6_OVF, \
|
||||
.enIRQn = BSP_USING_TMRA_6_IRQ_NUM, \
|
||||
.u8Int_Prio = BSP_USING_TMRA_6_IRQ_PRIO, \
|
||||
}, \
|
||||
.name = "tmra_6" \
|
||||
}
|
||||
#endif /* TMRA_6_CONFIG */
|
||||
#endif /* BSP_USING_TMRA_6 */
|
||||
|
||||
#ifdef BSP_USING_TMRA_7
|
||||
#ifndef TMRA_7_CONFIG
|
||||
#define TMRA_7_CONFIG \
|
||||
{ \
|
||||
.tmr_handle = CM_TMRA_7, \
|
||||
.clock_source = CLK_BUS_PCLK1, \
|
||||
.clock = FCG2_PERIPH_TMRA_7, \
|
||||
.flag = TMRA_FLAG_OVF, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc = INT_SRC_TMRA_7_OVF, \
|
||||
.enIRQn = BSP_USING_TMRA_7_IRQ_NUM, \
|
||||
.u8Int_Prio = BSP_USING_TMRA_7_IRQ_PRIO, \
|
||||
}, \
|
||||
.name = "tmra_7" \
|
||||
}
|
||||
#endif /* TMRA_7_CONFIG */
|
||||
#endif /* BSP_USING_TMRA_7 */
|
||||
|
||||
#ifdef BSP_USING_TMRA_8
|
||||
#ifndef TMRA_8_CONFIG
|
||||
#define TMRA_8_CONFIG \
|
||||
{ \
|
||||
.tmr_handle = CM_TMRA_8, \
|
||||
.clock_source = CLK_BUS_PCLK1, \
|
||||
.clock = FCG2_PERIPH_TMRA_8, \
|
||||
.flag = TMRA_FLAG_OVF, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc = INT_SRC_TMRA_8_OVF, \
|
||||
.enIRQn = BSP_USING_TMRA_8_IRQ_NUM, \
|
||||
.u8Int_Prio = BSP_USING_TMRA_8_IRQ_PRIO, \
|
||||
}, \
|
||||
.name = "tmra_8" \
|
||||
}
|
||||
#endif /* TMRA_8_CONFIG */
|
||||
#endif /* BSP_USING_TMRA_8 */
|
||||
|
||||
#ifdef BSP_USING_TMRA_9
|
||||
#ifndef TMRA_9_CONFIG
|
||||
#define TMRA_9_CONFIG \
|
||||
{ \
|
||||
.tmr_handle = CM_TMRA_9, \
|
||||
.clock_source = CLK_BUS_PCLK1, \
|
||||
.clock = FCG2_PERIPH_TMRA_9, \
|
||||
.flag = TMRA_FLAG_OVF, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc = INT_SRC_TMRA_9_OVF, \
|
||||
.enIRQn = BSP_USING_TMRA_9_IRQ_NUM, \
|
||||
.u8Int_Prio = BSP_USING_TMRA_9_IRQ_PRIO, \
|
||||
}, \
|
||||
.name = "tmra_9" \
|
||||
}
|
||||
#endif /* TMRA_9_CONFIG */
|
||||
#endif /* BSP_USING_TMRA_9 */
|
||||
|
||||
#ifdef BSP_USING_TMRA_10
|
||||
#ifndef TMRA_10_CONFIG
|
||||
#define TMRA_10_CONFIG \
|
||||
{ \
|
||||
.tmr_handle = CM_TMRA_10, \
|
||||
.clock_source = CLK_BUS_PCLK1, \
|
||||
.clock = FCG2_PERIPH_TMRA_10, \
|
||||
.flag = TMRA_FLAG_OVF, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc = INT_SRC_TMRA_10_OVF, \
|
||||
.enIRQn = BSP_USING_TMRA_10_IRQ_NUM, \
|
||||
.u8Int_Prio = BSP_USING_TMRA_10_IRQ_PRIO, \
|
||||
}, \
|
||||
.name = "tmra_10" \
|
||||
}
|
||||
#endif /* TMRA_10_CONFIG */
|
||||
#endif /* BSP_USING_TMRA_10 */
|
||||
|
||||
#ifdef BSP_USING_TMRA_11
|
||||
#ifndef TMRA_11_CONFIG
|
||||
#define TMRA_11_CONFIG \
|
||||
{ \
|
||||
.tmr_handle = CM_TMRA_11, \
|
||||
.clock_source = CLK_BUS_PCLK1, \
|
||||
.clock = FCG2_PERIPH_TMRA_11, \
|
||||
.flag = TMRA_FLAG_OVF, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc = INT_SRC_TMRA_11_OVF, \
|
||||
.enIRQn = BSP_USING_TMRA_11_IRQ_NUM, \
|
||||
.u8Int_Prio = BSP_USING_TMRA_11_IRQ_PRIO, \
|
||||
}, \
|
||||
.name = "tmra_11" \
|
||||
}
|
||||
#endif /* TMRA_11_CONFIG */
|
||||
#endif /* BSP_USING_TMRA_11 */
|
||||
|
||||
#ifdef BSP_USING_TMRA_12
|
||||
#ifndef TMRA_12_CONFIG
|
||||
#define TMRA_12_CONFIG \
|
||||
{ \
|
||||
.tmr_handle = CM_TMRA_12, \
|
||||
.clock_source = CLK_BUS_PCLK1, \
|
||||
.clock = FCG2_PERIPH_TMRA_12, \
|
||||
.flag = TMRA_FLAG_OVF, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc = INT_SRC_TMRA_12_OVF, \
|
||||
.enIRQn = BSP_USING_TMRA_12_IRQ_NUM, \
|
||||
.u8Int_Prio = BSP_USING_TMRA_12_IRQ_PRIO, \
|
||||
}, \
|
||||
.name = "tmra_12" \
|
||||
}
|
||||
#endif /* TMRA_12_CONFIG */
|
||||
#endif /* BSP_USING_TMRA_12 */
|
||||
#endif /* __TMR_CONFIG_H__ */
|
||||
|
|
@ -0,0 +1,69 @@
|
|||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2025-01-10 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __IC_CONFIG_H__
|
||||
#define __IC_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined (BSP_USING_INPUT_CAPTURE_TMR6_1)
|
||||
#define IC1_NAME "ic1"
|
||||
#define INPUT_CAPTURE_CFG_TMR6_1 \
|
||||
{ \
|
||||
.name = IC1_NAME, \
|
||||
.ch = TMR6_CH_A, \
|
||||
.clk_div = TMR6_CLK_DIV32, \
|
||||
.first_edge = TMR6_CAPT_COND_PWMA_RISING, \
|
||||
.irq_num_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM, \
|
||||
.irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO, \
|
||||
.irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM, \
|
||||
.irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO, \
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined (BSP_USING_INPUT_CAPTURE_TMR6_2)
|
||||
#define IC2_NAME "ic2"
|
||||
#define INPUT_CAPTURE_CFG_TMR6_2 \
|
||||
{ \
|
||||
.name = IC2_NAME, \
|
||||
.ch = TMR6_CH_A, \
|
||||
.clk_div = TMR6_CLK_DIV32, \
|
||||
.first_edge = TMR6_CAPT_COND_TRIGB_RISING, \
|
||||
.irq_num_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM, \
|
||||
.irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO, \
|
||||
.irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM, \
|
||||
.irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO, \
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined (BSP_USING_INPUT_CAPTURE_TMR6_3)
|
||||
#define IC3_NAME "ic3"
|
||||
#define INPUT_CAPTURE_CFG_TMR6_3 \
|
||||
{ \
|
||||
.name = IC3_NAME, \
|
||||
.ch = TMR6_CH_B, \
|
||||
.clk_div = TMR6_CLK_DIV16, \
|
||||
.first_edge = TMR6_CAPT_COND_TRIGC_FALLING, \
|
||||
.irq_num_cap = BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_NUM, \
|
||||
.irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_PRIO, \
|
||||
.irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_NUM, \
|
||||
.irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_PRIO, \
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __IC_CONFIG_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,168 @@
|
|||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2023-02-14 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __USB_APP_CONF_H__
|
||||
#define __USB_APP_CONF_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "rtconfig.h"
|
||||
|
||||
/* USB MODE CONFIGURATION */
|
||||
/*
|
||||
USB_FS_MODE, USB_HS_MODE, USB_HS_EXTERNAL_PHY defined comment
|
||||
(1) If only defined USB_FS_MODE:
|
||||
MCU USBFS core work in full speed using internal PHY.
|
||||
(2) If only defined USB_HS_MODE:
|
||||
MCU USBHS core work in full speed using internal PHY.
|
||||
(3) If both defined USB_HS_MODE && USB_HS_EXTERNAL_PHY
|
||||
MCU USBHS core work in high speed using external PHY.
|
||||
(4) Other combination:
|
||||
Not support, forbid!!
|
||||
*/
|
||||
|
||||
#if defined(BSP_USING_USBHS)
|
||||
#define USB_HS_MODE
|
||||
#endif
|
||||
#if defined(BSP_USING_USBFS)
|
||||
#define USB_FS_MODE
|
||||
#endif
|
||||
#if !defined(BSP_USING_USBHS) && !defined(BSP_USING_USBFS)
|
||||
#define USB_FS_MODE
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_USBD)
|
||||
#define USE_DEVICE_MODE
|
||||
#endif
|
||||
#if defined(BSP_USING_USBH)
|
||||
#define USE_HOST_MODE
|
||||
#endif
|
||||
#if !defined(BSP_USING_USBD) && !defined(BSP_USING_USBH)
|
||||
#define USE_DEVICE_MODE
|
||||
#endif
|
||||
|
||||
#if defined(USB_HS_MODE) && defined(BSP_USING_USBHS_PHY_EXTERN)
|
||||
#define USB_HS_EXTERNAL_PHY
|
||||
#endif
|
||||
|
||||
#ifndef USB_HS_MODE
|
||||
#ifndef USB_FS_MODE
|
||||
#error "USB_HS_MODE or USB_FS_MODE should be defined"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef USE_DEVICE_MODE
|
||||
#ifndef USE_HOST_MODE
|
||||
#error "USE_DEVICE_MODE or USE_HOST_MODE should be defined"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_USBD)
|
||||
/* USB DEVICE FIFO CONFIGURATION */
|
||||
#ifdef USB_FS_MODE
|
||||
#define RX_FIFO_FS_SIZE (128U)
|
||||
#define TX0_FIFO_FS_SIZE (32U)
|
||||
#define TX1_FIFO_FS_SIZE (32U)
|
||||
#define TX2_FIFO_FS_SIZE (32U)
|
||||
#define TX3_FIFO_FS_SIZE (32U)
|
||||
#define TX4_FIFO_FS_SIZE (32U)
|
||||
#define TX5_FIFO_FS_SIZE (32U)
|
||||
#define TX6_FIFO_FS_SIZE (32U)
|
||||
#define TX7_FIFO_FS_SIZE (32U)
|
||||
#define TX8_FIFO_FS_SIZE (32U)
|
||||
#define TX9_FIFO_FS_SIZE (32U)
|
||||
#define TX10_FIFO_FS_SIZE (32U)
|
||||
#define TX11_FIFO_FS_SIZE (32U)
|
||||
#define TX12_FIFO_FS_SIZE (32U)
|
||||
#define TX13_FIFO_FS_SIZE (32U)
|
||||
#define TX14_FIFO_FS_SIZE (32U)
|
||||
#define TX15_FIFO_FS_SIZE (32U)
|
||||
|
||||
#if ((RX_FIFO_FS_SIZE + \
|
||||
TX0_FIFO_FS_SIZE + TX1_FIFO_FS_SIZE + TX2_FIFO_FS_SIZE + TX3_FIFO_FS_SIZE + TX4_FIFO_FS_SIZE + \
|
||||
TX5_FIFO_FS_SIZE + TX6_FIFO_FS_SIZE + TX7_FIFO_FS_SIZE + TX8_FIFO_FS_SIZE + TX9_FIFO_FS_SIZE + \
|
||||
TX10_FIFO_FS_SIZE + TX11_FIFO_FS_SIZE + TX12_FIFO_FS_SIZE + TX13_FIFO_FS_SIZE + TX14_FIFO_FS_SIZE + \
|
||||
TX15_FIFO_FS_SIZE) > 640U)
|
||||
#error "The USB max FIFO size is 640 x 4 Bytes!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef USB_HS_MODE
|
||||
#define RX_FIFO_HS_SIZE (512U)
|
||||
#define TX0_FIFO_HS_SIZE (64U)
|
||||
#define TX1_FIFO_HS_SIZE (64U)
|
||||
#define TX2_FIFO_HS_SIZE (64U)
|
||||
#define TX3_FIFO_HS_SIZE (64U)
|
||||
#define TX4_FIFO_HS_SIZE (64U)
|
||||
#define TX5_FIFO_HS_SIZE (64U)
|
||||
#define TX6_FIFO_HS_SIZE (64U)
|
||||
#define TX7_FIFO_HS_SIZE (64U)
|
||||
#define TX8_FIFO_HS_SIZE (64U)
|
||||
#define TX9_FIFO_HS_SIZE (64U)
|
||||
#define TX10_FIFO_HS_SIZE (64U)
|
||||
#define TX11_FIFO_HS_SIZE (64U)
|
||||
#define TX12_FIFO_HS_SIZE (64U)
|
||||
#define TX13_FIFO_HS_SIZE (64U)
|
||||
#define TX14_FIFO_HS_SIZE (64U)
|
||||
#define TX15_FIFO_HS_SIZE (64U)
|
||||
|
||||
#if ((RX_FIFO_HS_SIZE + \
|
||||
TX0_FIFO_HS_SIZE + TX1_FIFO_HS_SIZE + TX2_FIFO_HS_SIZE + TX3_FIFO_HS_SIZE + TX4_FIFO_HS_SIZE + \
|
||||
TX5_FIFO_HS_SIZE + TX6_FIFO_HS_SIZE + TX7_FIFO_HS_SIZE + TX8_FIFO_HS_SIZE + TX9_FIFO_HS_SIZE + \
|
||||
TX10_FIFO_HS_SIZE + TX11_FIFO_HS_SIZE + TX12_FIFO_HS_SIZE + TX13_FIFO_HS_SIZE + TX14_FIFO_HS_SIZE + \
|
||||
TX15_FIFO_HS_SIZE) > 2048U)
|
||||
#error "The USB max FIFO size is 2048 x 4 Bytes!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_USBD_VBUS_SENSING)
|
||||
#define VBUS_SENSING_ENABLED
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_USBH)
|
||||
/* USB HOST FIFO CONFIGURATION */
|
||||
#ifdef USB_FS_MODE
|
||||
#define RX_FIFO_FS_SIZE (128U)
|
||||
#define TXH_NP_FS_FIFOSIZ (32U)
|
||||
#define TXH_P_FS_FIFOSIZ (64U)
|
||||
|
||||
#if ((RX_FIFO_FS_SIZE + TXH_NP_FS_FIFOSIZ + TXH_P_FS_FIFOSIZ) > 640U)
|
||||
#error "The USB max FIFO size is 640 x 4 Bytes!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef USB_HS_MODE
|
||||
#define RX_FIFO_HS_SIZE (512U)
|
||||
#define TXH_NP_HS_FIFOSIZ (128U)
|
||||
#define TXH_P_HS_FIFOSIZ (256U)
|
||||
|
||||
#if ((RX_FIFO_FS_SIZE + TXH_NP_FS_FIFOSIZ + TXH_P_FS_FIFOSIZ) > 2048U)
|
||||
#error "The USB max FIFO size is 2048 x 4 Bytes!"
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __USB_APP_CONF_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2023-02-14 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __USB_BSP_H__
|
||||
#define __USB_BSP_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "hc32_ll_utility.h"
|
||||
|
||||
extern void usb_udelay(const uint32_t usec);
|
||||
extern void usb_mdelay(const uint32_t msec);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __USB_BSP_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __DRV_CONFIG_H__
|
||||
#define __DRV_CONFIG_H__
|
||||
|
||||
#include <board.h>
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "dma_config.h"
|
||||
#include "uart_config.h"
|
||||
#include "spi_config.h"
|
||||
#include "adc_config.h"
|
||||
#include "dac_config.h"
|
||||
#include "gpio_config.h"
|
||||
#include "eth_config.h"
|
||||
#include "can_config.h"
|
||||
#include "mcan_config.h"
|
||||
#include "sdio_config.h"
|
||||
#include "pm_config.h"
|
||||
#include "i2c_config.h"
|
||||
#include "qspi_config.h"
|
||||
#include "pulse_encoder_config.h"
|
||||
#include "timer_config.h"
|
||||
#include "tmr_capture_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,206 @@
|
|||
/**
|
||||
*******************************************************************************
|
||||
* @file template/source/hc32f4xx_conf.h
|
||||
* @brief This file contains HC32 Series Device Driver Library usage management.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2024-09-13 CDT First version
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2025, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32F4XX_CONF_H__
|
||||
#define __HC32F4XX_CONF_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include <rtconfig.h>
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
* @brief This is the list of modules to be used in the Device Driver Library.
|
||||
* Select the modules you need to use to DDL_ON.
|
||||
* @note LL_ICG_ENABLE must be turned on(DDL_ON) to ensure that the chip works
|
||||
* properly.
|
||||
* @note LL_UTILITY_ENABLE must be turned on(DDL_ON) if using Device Driver
|
||||
* Library.
|
||||
* @note LL_PRINT_ENABLE must be turned on(DDL_ON) if using printf function.
|
||||
*/
|
||||
#define LL_ICG_ENABLE (DDL_ON)
|
||||
#define LL_UTILITY_ENABLE (DDL_ON)
|
||||
#define LL_PRINT_ENABLE (DDL_OFF)
|
||||
|
||||
#define LL_ADC_ENABLE (DDL_ON)
|
||||
#define LL_AOS_ENABLE (DDL_ON)
|
||||
#define LL_CAN_ENABLE (DDL_ON)
|
||||
#define LL_CLK_ENABLE (DDL_ON)
|
||||
#define LL_CMP_ENABLE (DDL_ON)
|
||||
#define LL_CRC_ENABLE (DDL_ON)
|
||||
#define LL_CTC_ENABLE (DDL_ON)
|
||||
#define LL_DAC_ENABLE (DDL_ON)
|
||||
#define LL_DBGC_ENABLE (DDL_OFF)
|
||||
#define LL_DCU_ENABLE (DDL_ON)
|
||||
#define LL_DMA_ENABLE (DDL_ON)
|
||||
#define LL_DMC_ENABLE (DDL_ON)
|
||||
#define LL_DVP_ENABLE (DDL_ON)
|
||||
#define LL_EFM_ENABLE (DDL_ON)
|
||||
#define LL_EMB_ENABLE (DDL_ON)
|
||||
#define LL_ERMU_ENABLE (DDL_ON)
|
||||
#define LL_ETH_ENABLE (DDL_ON)
|
||||
#define LL_EVENT_PORT_ENABLE (DDL_OFF)
|
||||
#define LL_FCG_ENABLE (DDL_ON)
|
||||
#define LL_FCM_ENABLE (DDL_ON)
|
||||
#define LL_FMAC_ENABLE (DDL_ON)
|
||||
#define LL_GPIO_ENABLE (DDL_ON)
|
||||
#define LL_HASH_ENABLE (DDL_ON)
|
||||
#define LL_I2C_ENABLE (DDL_ON)
|
||||
#define LL_I2S_ENABLE (DDL_ON)
|
||||
#define LL_INTERRUPTS_ENABLE (DDL_ON)
|
||||
#define LL_INTERRUPTS_SHARE_ENABLE (DDL_ON)
|
||||
#define LL_KEYSCAN_ENABLE (DDL_ON)
|
||||
#define LL_MAU_ENABLE (DDL_ON)
|
||||
#define LL_MCAN_ENABLE (DDL_ON)
|
||||
#define LL_MPU_ENABLE (DDL_ON)
|
||||
#define LL_NFC_ENABLE (DDL_ON)
|
||||
#define LL_OTS_ENABLE (DDL_ON)
|
||||
#define LL_PWC_ENABLE (DDL_ON)
|
||||
#define LL_QSPI_ENABLE (DDL_ON)
|
||||
#define LL_RMU_ENABLE (DDL_ON)
|
||||
#define LL_RTC_ENABLE (DDL_ON)
|
||||
#define LL_SDIOC_ENABLE (DDL_ON)
|
||||
#define LL_SKE_ENABLE (DDL_ON)
|
||||
#define LL_SMC_ENABLE (DDL_ON)
|
||||
#define LL_SPI_ENABLE (DDL_ON)
|
||||
#define LL_SRAM_ENABLE (DDL_ON)
|
||||
#define LL_SWDT_ENABLE (DDL_ON)
|
||||
#define LL_TMR0_ENABLE (DDL_ON)
|
||||
#define LL_TMR2_ENABLE (DDL_ON)
|
||||
#define LL_TMR4_ENABLE (DDL_ON)
|
||||
#define LL_TMR6_ENABLE (DDL_ON)
|
||||
#define LL_TMRA_ENABLE (DDL_ON)
|
||||
#define LL_TRNG_ENABLE (DDL_ON)
|
||||
#define LL_USART_ENABLE (DDL_ON)
|
||||
#define LL_USB_ENABLE (DDL_ON)
|
||||
#define LL_WDT_ENABLE (DDL_ON)
|
||||
|
||||
/**
|
||||
* @brief The following is a list of currently supported BSP boards.
|
||||
*/
|
||||
#define BSP_EV_HC32F4A8_LQFP176 (11U)
|
||||
|
||||
/**
|
||||
* @brief The macro BSP_EV_HC32F4XX is used to specify the BSP board currently
|
||||
* in use.
|
||||
* The value should be set to one of the list of currently supported BSP boards.
|
||||
* @note If there is no supported BSP board or the BSP function is not used,
|
||||
* the value needs to be set to 0U.
|
||||
*/
|
||||
#define BSP_EV_HC32F4XX (0U)
|
||||
|
||||
/**
|
||||
* @brief This is the list of BSP components to be used.
|
||||
* Select the components you need to use to DDL_ON.
|
||||
*/
|
||||
#define BSP_24CXX_ENABLE (DDL_OFF)
|
||||
#define BSP_XPT20XX_ENABLE (DDL_OFF)
|
||||
#define BSP_W9825G6KH_ENABLE (DDL_OFF)
|
||||
#define BSP_IS62WV51216_ENABLE (DDL_OFF)
|
||||
#define BSP_MT29F2G08AB_ENABLE (DDL_OFF)
|
||||
#define BSP_NT35510_ENABLE (DDL_OFF)
|
||||
#define BSP_OV5640_ENABLE (DDL_OFF)
|
||||
#define BSP_RTL8201_ENABLE (DDL_OFF)
|
||||
#define BSP_TCA9539_ENABLE (DDL_OFF)
|
||||
#define BSP_W25QXX_ENABLE (DDL_OFF)
|
||||
#define BSP_WM8988_ENABLE (DDL_OFF)
|
||||
|
||||
/**
|
||||
* @brief Ethernet and PHY Configuration.
|
||||
*/
|
||||
/* MAC ADDRESS */
|
||||
#define ETH_MAC_ADDR0 (0x02U)
|
||||
#define ETH_MAC_ADDR1 (0x00U)
|
||||
#define ETH_MAC_ADDR2 (0x00U)
|
||||
#define ETH_MAC_ADDR3 (0x00U)
|
||||
#define ETH_MAC_ADDR4 (0x00U)
|
||||
#define ETH_MAC_ADDR5 (0x00U)
|
||||
|
||||
/* Common PHY Registers */
|
||||
#define PHY_BCR (0x00U) /*!< Basic Control Register */
|
||||
#define PHY_BSR (0x01U) /*!< Basic Status Register */
|
||||
|
||||
#define PHY_SOFT_RESET (0x8000U) /*!< PHY Soft Reset */
|
||||
#define PHY_LOOPBACK (0x4000U) /*!< Select loop-back mode */
|
||||
#define PHY_FULLDUPLEX_100M (0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */
|
||||
#define PHY_HALFDUPLEX_100M (0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */
|
||||
#define PHY_FULLDUPLEX_10M (0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */
|
||||
#define PHY_HALFDUPLEX_10M (0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */
|
||||
#define PHY_AUTONEGOTIATION (0x1000U) /*!< Enable auto-negotiation function */
|
||||
#define PHY_POWERDOWN (0x0800U) /*!< Select the power down mode */
|
||||
#define PHY_ISOLATE (0x0400U) /*!< Isolate PHY from MII */
|
||||
#define PHY_RESTART_AUTONEGOTIATION (0x0200U) /*!< Restart auto-negotiation function */
|
||||
|
||||
#define PHY_100BASE_TX_FD (0x4000U) /*!< 100Base-TX full duplex support */
|
||||
#define PHY_100BASE_TX_HD (0x2000U) /*!< 100Base-TX half duplex support */
|
||||
#define PHY_10BASE_T_FD (0x1000U) /*!< 10Base-T full duplex support */
|
||||
#define PHY_10BASE_T_HD (0x0800U) /*!< 10Base-T half duplex support */
|
||||
#define PHY_AUTONEGO_COMPLETE (0x0020U) /*!< Auto-Negotiation process completed */
|
||||
#define PHY_LINK_STATUS (0x0004U) /*!< Valid link established */
|
||||
#define PHY_JABBER_DETECTION (0x0002U) /*!< Jabber condition detected */
|
||||
|
||||
#if defined (ETH_PHY_USING_RTL8201F)
|
||||
/* PHY(RTL8201F) Address*/
|
||||
#define ETH_PHY_ADDR (0x00U)
|
||||
|
||||
/* PHY Configuration delay(ms) */
|
||||
#define ETH_PHY_RST_DELAY (0x0080UL)
|
||||
#define ETH_PHY_CONFIG_DELAY (0x0800UL)
|
||||
#define ETH_PHY_RD_TIMEOUT (0x0005UL)
|
||||
#define ETH_PHY_WR_TIMEOUT (0x0005UL)
|
||||
|
||||
/* PHY Status Register */
|
||||
#define PHY_SR (PHY_BCR) /*!< PHY status register */
|
||||
|
||||
#define PHY_DUPLEX_STATUS (PHY_FULLDUPLEX_10M) /*!< PHY Duplex mask */
|
||||
#define PHY_SPEED_STATUS (PHY_HALFDUPLEX_100M) /*!< PHY Speed mask */
|
||||
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32F4XX_CONF_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
|
|
@ -0,0 +1,112 @@
|
|||
/***************************************************************************//**
|
||||
* \file HC32F4A8.icf
|
||||
* \version 1.0
|
||||
*
|
||||
* \brief Linker file for the IAR compiler.
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright (C) 2022-2025, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*******************************************************************************/
|
||||
/*###ICF### Section handled by ICF editor, don't touch! *****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
|
||||
// Check that necessary symbols have been passed to linker via command line interface
|
||||
if((!isdefinedsymbol(_LINK_RAM_)) && (!isdefinedsymbol(_LINK_FLASH_))) {
|
||||
error "Link location not defined or not supported!";
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Memory address and size definitions
|
||||
******************************************************************************/
|
||||
define symbol ram1_base_address = 0x1FFE0000;
|
||||
define symbol ram1_end_address = 0x2005FFFF;
|
||||
|
||||
if(isdefinedsymbol(_LINK_RAM_)) {
|
||||
define symbol ram_start_reserve = 0x20000;
|
||||
define symbol rom1_base_address = ram1_base_address;
|
||||
define symbol rom1_end_address = rom1_base_address + ram_start_reserve - 0x01;
|
||||
define symbol rom2_base_address = 0x0;
|
||||
define symbol rom2_end_address = 0x0;
|
||||
define symbol rom3_base_address = 0x0;
|
||||
define symbol rom3_end_address = 0x0;
|
||||
} else {
|
||||
define symbol ram_start_reserve = 0x0;
|
||||
define symbol rom1_base_address = 0x0;
|
||||
define symbol rom3_base_address = 0x03000000;
|
||||
define symbol rom3_end_address = 0x030017FF;
|
||||
if (isdefinedsymbol(_HC32F4A8_2M_)) {
|
||||
define symbol rom1_end_address = 0x001FFFFF;
|
||||
define symbol rom2_base_address = 0x0;
|
||||
define symbol rom2_end_address = 0x0;
|
||||
} else if (isdefinedsymbol(_HC32F4A8_1M_SINGLE_)) {
|
||||
define symbol rom1_end_address = 0x000FFFFF;
|
||||
define symbol rom2_base_address = 0x0;
|
||||
define symbol rom2_end_address = 0x0;
|
||||
} else if (isdefinedsymbol(_HC32F4A8_1M_DUAL_)) {
|
||||
define symbol rom1_end_address = 0x0007FFFF;
|
||||
define symbol rom2_base_address = 0x00100000;
|
||||
define symbol rom2_end_address = 0x0017FFFF;
|
||||
}
|
||||
}
|
||||
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = rom1_base_address;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_IROM1_start__ = rom1_base_address;
|
||||
define symbol __ICFEDIT_region_IROM1_end__ = rom1_end_address;
|
||||
define symbol __ICFEDIT_region_IROM2_start__ = rom2_base_address;
|
||||
define symbol __ICFEDIT_region_IROM2_end__ = rom2_end_address;
|
||||
define symbol __ICFEDIT_region_IROM3_start__ = rom3_base_address;
|
||||
define symbol __ICFEDIT_region_IROM3_end__ = rom3_end_address;
|
||||
define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM1_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_IRAM1_start__ = ram1_base_address + ram_start_reserve;
|
||||
define symbol __ICFEDIT_region_IRAM1_end__ = ram1_end_address;
|
||||
define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000;
|
||||
define symbol __ICFEDIT_region_IRAM2_end__ = 0x200F0FFF;
|
||||
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
|
||||
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x2000;
|
||||
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x2000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Memory definitions
|
||||
******************************************************************************/
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]
|
||||
| mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
|
||||
define region OTP_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
|
||||
| mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in OTP_region { readonly section .otp_data };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
|
|
@ -0,0 +1,270 @@
|
|||
/******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
/*****************************************************************************/
|
||||
/* File HC32F4A8xI.ld */
|
||||
/* Abstract Linker script for HC32F4A8 Device with */
|
||||
/* 2MByte FLASH, 516KByte RAM */
|
||||
/* Version V1.0 */
|
||||
/* Date 2022-03-31 */
|
||||
/*****************************************************************************/
|
||||
|
||||
/* Custom defines, according to section 7.7 of the user manual.
|
||||
Take OTP sector 16 for example. */
|
||||
__OTP_DATA_START = 0x03000000;
|
||||
__OTP_DATA_SIZE = 2048;
|
||||
__OTP_LOCK_START = 0x03001840;
|
||||
__OTP_LOCK_SIZE = 4;
|
||||
|
||||
/* Use contiguous memory regions for simple. */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx): ORIGIN = 0x00000000, LENGTH = 2M
|
||||
OTP_DATA (rx): ORIGIN = __OTP_DATA_START, LENGTH = __OTP_DATA_SIZE
|
||||
OTP_LOCK (rx): ORIGIN = __OTP_LOCK_START, LENGTH = __OTP_LOCK_SIZE
|
||||
RAM (rwx): ORIGIN = 0x1FFE0000, LENGTH = 512K
|
||||
RAMB (rwx): ORIGIN = 0x200F0000, LENGTH = 4K
|
||||
}
|
||||
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.vectors :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.vectors))
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.icg_sec 0x00000400 :
|
||||
{
|
||||
KEEP(*(.icg_sec))
|
||||
} >FLASH
|
||||
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_stext = .;
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
*(.text) /* remaining code */
|
||||
*(.text.*) /* remaining code */
|
||||
*(.rodata) /* read-only data (constants) */
|
||||
*(.rodata*)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.gnu.linkonce.t*)
|
||||
|
||||
/* section information for finsh shell */
|
||||
. = ALIGN(4);
|
||||
__fsymtab_start = .;
|
||||
KEEP(*(FSymTab))
|
||||
__fsymtab_end = .;
|
||||
. = ALIGN(4);
|
||||
__vsymtab_start = .;
|
||||
KEEP(*(VSymTab))
|
||||
__vsymtab_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
/* section information for initial. */
|
||||
. = ALIGN(4);
|
||||
__rt_init_start = .;
|
||||
KEEP(*(SORT(.rti_fn*)))
|
||||
__rt_init_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
} >FLASH
|
||||
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata)
|
||||
*(.rodata*)
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} >FLASH
|
||||
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} >FLASH
|
||||
__exidx_end = .;
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* preinit data */
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.init_array :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* init data */
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* finit data */
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
__etext = ALIGN(4);
|
||||
|
||||
.otp_data_sec :
|
||||
{
|
||||
KEEP(*(.otp_data_sec))
|
||||
} >OTP_DATA
|
||||
|
||||
.otp_lock_sec :
|
||||
{
|
||||
KEEP(*(.otp_lock_sec))
|
||||
} >OTP_LOCK
|
||||
|
||||
.data : AT (__etext)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__data_start__ = .;
|
||||
*(vtable)
|
||||
*(.data)
|
||||
*(.data*)
|
||||
*(.gnu.linkonce.d*)
|
||||
. = ALIGN(4);
|
||||
*(.ramfunc)
|
||||
*(.ramfunc*)
|
||||
. = ALIGN(4);
|
||||
__data_end__ = .;
|
||||
} >RAM
|
||||
|
||||
.heap_stack (COPY) :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__end__ = .;
|
||||
PROVIDE(end = .);
|
||||
PROVIDE(_end = .);
|
||||
*(.heap*)
|
||||
. = ALIGN(8);
|
||||
__HeapLimit = .;
|
||||
|
||||
__StackLimit = .;
|
||||
*(.stack*)
|
||||
. = ALIGN(8);
|
||||
__StackTop = .;
|
||||
} >RAM
|
||||
|
||||
__etext_ramb = __etext + ALIGN (SIZEOF(.data), 4);
|
||||
.ramb_data : AT (__etext_ramb)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__data_start_ramb__ = .;
|
||||
*(.ramb_data)
|
||||
*(.ramb_data*)
|
||||
. = ALIGN(4);
|
||||
__data_end_ramb__ = .;
|
||||
} >RAMB
|
||||
|
||||
__bss_start = .;
|
||||
.bss __StackTop (NOLOAD):
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = .;
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = .;
|
||||
__bss_end__ = _ebss;
|
||||
. = ALIGN(4);
|
||||
*(.noinit*)
|
||||
. = ALIGN(4);
|
||||
} >RAM
|
||||
__bss_end = .;
|
||||
|
||||
.ramb_bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__bss_start_ramb__ = .;
|
||||
*(.ramb_bss)
|
||||
*(.ramb_bss*)
|
||||
. = ALIGN(4);
|
||||
__bss_end_ramb__ = .;
|
||||
} >RAMB
|
||||
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a (*)
|
||||
libm.a (*)
|
||||
libgcc.a (*)
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
|
||||
PROVIDE(_stack = __StackTop);
|
||||
PROVIDE(_Min_Heap_Size = __HeapLimit - __HeapBase);
|
||||
PROVIDE(_Min_Stack_Size = __StackTop - __StackLimit);
|
||||
|
||||
__RamEnd = ORIGIN(RAM) + LENGTH(RAM);
|
||||
ASSERT(__StackTop <= __RamEnd, "region RAM overflowed with stack")
|
||||
|
||||
/* Stabs debugging sections. */
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
/* DWARF debug sections.
|
||||
* Symbols in the DWARF debugging sections are relative to the beginning
|
||||
* of the section so we begin them at 0. */
|
||||
/* DWARF 1 */
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
/* GNU DWARF 1 extensions */
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
/* DWARF 1.1 and DWARF 2 */
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
/* DWARF 2 */
|
||||
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
/* SGI/MIPS DWARF 2 extensions */
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
}
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
; ****************************************************************
|
||||
; Scatter-Loading Description File
|
||||
; ****************************************************************
|
||||
LR_IROM1 0x00000000 0x00200000 { ; load region size_region
|
||||
ER_IROM1 0x00000000 0x00200000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
.ANY (+XO)
|
||||
}
|
||||
RW_IRAM1 0x1FFE0000 UNINIT 0x00000008 { ; RW data
|
||||
*(.bss.noinit)
|
||||
}
|
||||
RW_IRAM2 0x1FFE0008 0x0007FFF8 { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
.ANY (RAMCODE)
|
||||
}
|
||||
RW_IRAMB 0x200F0000 0x00001000 { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef _FAL_CFG_H_
|
||||
#define _FAL_CFG_H_
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <board.h>
|
||||
|
||||
/* enable hc32f4 onchip flash driver sample */
|
||||
#define FAL_FLASH_PORT_DRIVER_HC32F4
|
||||
/* enable SFUD flash driver sample */
|
||||
#define FAL_FLASH_PORT_DRIVER_SFUD
|
||||
|
||||
extern const struct fal_flash_dev hc32_onchip_flash;
|
||||
extern struct fal_flash_dev ext_nor_flash0;
|
||||
|
||||
/* flash device table */
|
||||
#define FAL_FLASH_DEV_TABLE \
|
||||
{ \
|
||||
&hc32_onchip_flash, \
|
||||
&ext_nor_flash0, \
|
||||
}
|
||||
|
||||
/* ====================== Partition Configuration ========================== */
|
||||
#ifdef FAL_PART_HAS_TABLE_CFG
|
||||
/* partition table */
|
||||
#define FAL_PART_TABLE \
|
||||
{ \
|
||||
{FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 2 * 1024 * 1024, 0}, \
|
||||
{FAL_PART_MAGIC_WROD, "filesystem", "w25q64", 0, 8 * 1024 * 1024, 0}, \
|
||||
}
|
||||
#endif /* FAL_PART_HAS_TABLE_CFG */
|
||||
|
||||
#endif /* _FAL_CFG_H_ */
|
||||
|
|
@ -0,0 +1,84 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
* Copyright (c) 2022-2025, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2025-04-11 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __NAND_PORT_H__
|
||||
#define __NAND_PORT_H__
|
||||
|
||||
/******************** NAND chip information ***********************************/
|
||||
#define NAND_BYTES_PER_PAGE 2048UL
|
||||
#define NAND_SPARE_AREA_SIZE 64UL
|
||||
#define NAND_PAGES_PER_BLOCK 64UL
|
||||
#define NAND_BYTES_PER_BLOCK (NAND_PAGES_PER_BLOCK * NAND_BYTES_PER_PAGE)
|
||||
#define NAND_BLOCKS_PER_PLANE 1024UL
|
||||
#define NAND_PLANE_PER_DEVICE 2UL
|
||||
#define NAND_DEVICE_BLOCKS (NAND_BLOCKS_PER_PLANE * NAND_PLANE_PER_DEVICE)
|
||||
#define NAND_DEVICE_PAGES (NAND_DEVICE_BLOCKS * NAND_PAGES_PER_BLOCK)
|
||||
|
||||
/******************** EXMC_NFC configure **************************************/
|
||||
/* chip: EXMC_NFC_BANK0~7 */
|
||||
#define NAND_EXMC_NFC_BANK EXMC_NFC_BANK0
|
||||
|
||||
/* density:2Gbit */
|
||||
#define NAND_EXMC_NFC_BANK_CAPACITY EXMC_NFC_BANK_CAPACITY_2GBIT
|
||||
|
||||
/* device width: 8-bit */
|
||||
#define NAND_EXMC_NFC_MEMORY_WIDTH EXMC_NFC_MEMORY_WIDTH_8BIT
|
||||
|
||||
/* page size: 2KByte */
|
||||
#define NAND_EXMC_NFC_PAGE_SIZE EXMC_NFC_PAGE_SIZE_2KBYTE
|
||||
|
||||
/* row address cycle: 3 */
|
||||
#define NAND_EXMC_NFC_ROW_ADDR_CYCLE EXMC_NFC_3_ROW_ADDR_CYCLE
|
||||
|
||||
/* ECC mode */
|
||||
#define NAND_EXMC_NFC_ECC_MD EXMC_NFC_1BIT_ECC
|
||||
|
||||
/* timing configuration(EXCLK clock frequency: 60MHz@3.3V) */
|
||||
/* TS: ALE/CLE/CE setup time(min=10ns) */
|
||||
#define NAND_TS 1U
|
||||
|
||||
/* TWP: WE# pulse width (min=10ns) */
|
||||
#define NAND_TWP 1U
|
||||
|
||||
/* TRP: RE# pulse width (MT29F2G08AB min=10ns and EXMC t_data_s min=24ns) */
|
||||
#define NAND_TRP 2U
|
||||
|
||||
/* TTH: ALE/CLE/CE hold time (min=5ns) */
|
||||
#define NAND_TH 1U
|
||||
|
||||
/* TWH: WE# pulse width HIGH (min=10ns) */
|
||||
#define NAND_TWH 1U
|
||||
|
||||
/* TRH: RE# pulse width HIGH (min=7ns) */
|
||||
#define NAND_TRH 1U
|
||||
|
||||
/* TRR: Ready to RE# LOW (min=20ns) */
|
||||
#define NAND_TRR 2U
|
||||
|
||||
/* TWB: WE# HIGH to busy (max=100ns) */
|
||||
#define NAND_TWB 1U
|
||||
|
||||
/* TWB: WE# HIGH to busy (max=100ns) */
|
||||
#define NAND_TRB 1U
|
||||
|
||||
/* TCCS: Change read column and Change write column delay */
|
||||
#define NAND_TCCS 5U
|
||||
|
||||
/* TWTR: WE# HIGH to RE# LOW (min=60ns) */
|
||||
#define NAND_TWTR 4U
|
||||
|
||||
/* TRTW: RE# HIGH to WE# LOW (min=100ns) */
|
||||
#define NAND_TRTW 7U
|
||||
|
||||
/* TADL: ALE to data start (min=70ns) */
|
||||
#define NAND_TADL 5U
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,87 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
* Copyright (c) 2022-2025, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2025-04-07 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __SDRAM_PORT_H__
|
||||
#define __SDRAM_PORT_H__
|
||||
|
||||
/* parameters for sdram peripheral */
|
||||
|
||||
/* chip#0/1/2/3: EXMC_DMC_CHIP0/1/2/3 */
|
||||
#define SDRAM_CHIP EXMC_DMC_CHIP0
|
||||
/* bank address */
|
||||
#define SDRAM_BANK_ADDR (0x80000000UL)
|
||||
/* size(kbyte):32MB = 32*1024*1KBytes */
|
||||
#define SDRAM_SIZE (32UL * 1024UL * 1024UL)
|
||||
/* auto precharge pin: EXMC_DMC_AUTO_PRECHARGE_A8/10 */
|
||||
#define SDRAM_AUTO_PRECHARGE_PIN EXMC_DMC_AUTO_PRECHARGE_A10
|
||||
/* data width: EXMC_DMC_MEMORY_WIDTH_16BIT, EXMC_DMC_MEMORY_WIDTH_32BIT */
|
||||
#define SDRAM_DATA_WIDTH EXMC_DMC_MEMORY_WIDTH_16BIT
|
||||
/* column bit numbers: EXMC_DMC_COLUMN_BITS_NUM8/9/10/11/12 */
|
||||
#define SDRAM_COLUMN_BITS EXMC_DMC_COLUMN_BITS_NUM9
|
||||
/* row bit numbers: EXMC_DMC_ROW_BITS_NUM11/12/13/14/15/16 */
|
||||
#define SDRAM_ROW_BITS EXMC_DMC_ROW_BITS_NUM13
|
||||
/* cas latency clock number: 2, 3 */
|
||||
#define SDRAM_CAS_LATENCY 2UL
|
||||
/* burst length: EXMC_DMC_BURST_1BEAT/2BEAT/4BEAT/8BEAT/16BEAT */
|
||||
#define SDRAM_BURST_LENGTH EXMC_DMC_BURST_1BEAT
|
||||
|
||||
/* operating mode: SDRAM_MODEREG_OPERATING_MODE_STANDARD */
|
||||
#define SDRAM_MODEREG_OPERATING_MODE SDRAM_MODEREG_OPERATING_MODE_STANDARD
|
||||
/* burst type: SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL/INTERLEAVED */
|
||||
#define SDRAM_MODEREG_BURST_TYPE SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL
|
||||
/* write burst mode: SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED/SINGLE */
|
||||
#define SDRAM_MODEREG_WRITEBURST_MODE SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED
|
||||
|
||||
/* timing configuration(EXCLK clock frequency: 60MHz) */
|
||||
/* refresh rate counter (EXCLK clock) */
|
||||
#define SDRAM_REFRESH_COUNT (900U)
|
||||
/* TMDR: mode register command time (EXCLK clock) */
|
||||
#define SDRAM_TMDR 2U
|
||||
/* TRAS: RAS to precharge delay time (EXCLK clock) */
|
||||
#define SDRAM_TRAS 3U
|
||||
/* TRC: active bank x to active bank x delay time (EXCLK clock) */
|
||||
#define SDRAM_TRC 4U
|
||||
/* TRCD: RAS to CAS minimum delay time (EXCLK clock) */
|
||||
#define SDRAM_TRCD_B 3U
|
||||
#define SDRAM_TRCD_P 0U
|
||||
/* TRFC: autorefresh command time (EXCLK clock) */
|
||||
#define SDRAM_TRFC_B 4U
|
||||
#define SDRAM_TRFC_P 0U
|
||||
/* TRP: precharge to RAS delay time (EXCLK clock) */
|
||||
#define SDRAM_TRP_B 3U
|
||||
#define SDRAM_TRP_P 0U
|
||||
/* TRRD: active bank x to active bank y delay time (EXCLK clock) */
|
||||
#define SDRAM_TRRD 2U
|
||||
/* TWR: write to precharge delay time (EXCLK clock). */
|
||||
#define SDRAM_TWR 2U
|
||||
/* TWTR: write to read delay time (EXCLK clock). */
|
||||
#define SDRAM_TWTR 1U
|
||||
/* TXP: exit power-down command time (EXCLK clock). */
|
||||
#define SDRAM_TXP 1U
|
||||
/* TXSR: exit self-refresh command time (EXCLK clock). */
|
||||
#define SDRAM_TXSR 5U
|
||||
/* TESR: self-refresh command time (EXCLK clock). */
|
||||
#define SDRAM_TESR 5U
|
||||
|
||||
/* memory mode register */
|
||||
#define SDRAM_MODEREG_BURST_LENGTH_1 (0x0000U)
|
||||
#define SDRAM_MODEREG_BURST_LENGTH_2 (0x0001U)
|
||||
#define SDRAM_MODEREG_BURST_LENGTH_4 (0x0002U)
|
||||
#define SDRAM_MODEREG_BURST_LENGTH_8 (0x0004U)
|
||||
#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL (0x0000U)
|
||||
#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED (0x0008U)
|
||||
#define SDRAM_MODEREG_CAS_LATENCY_2 (0x0020U)
|
||||
#define SDRAM_MODEREG_CAS_LATENCY_3 (0x0030U)
|
||||
#define SDRAM_MODEREG_OPERATING_MODE_STANDARD (0x0000U)
|
||||
#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED (0x0000U)
|
||||
#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE (0x0200U)
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,67 @@
|
|||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __TCA9539_PORT_H__
|
||||
#define __TCA9539_PORT_H__
|
||||
|
||||
#include "tca9539.h"
|
||||
|
||||
/**
|
||||
* @defgroup HC32F4A8_EV_IO_Function_Sel Expand IO function definition
|
||||
* @{
|
||||
*/
|
||||
#define EIO_USBFS_OC (TCA9539_IO_PIN0) /* USBFS over-current, input */
|
||||
#define EIO_USBHS_OC (TCA9539_IO_PIN1) /* USBHS over-current, input */
|
||||
#define EIO_SDIC1_CD (TCA9539_IO_PIN2) /* SDIC1 card detect, input */
|
||||
#define EIO_SCI_CD (TCA9539_IO_PIN3) /* Smart card detect, input */
|
||||
#define EIO_TOUCH_INT (TCA9539_IO_PIN4) /* Touch screen interrupt, input */
|
||||
#define EIO_LIN_SLEEP (TCA9539_IO_PIN5) /* LIN PHY sleep, output */
|
||||
#define EIO_RTCS_CTRST (TCA9539_IO_PIN6) /* 'CS' for Resistor touch panel or 'Reset' for Cap touch panel, output */
|
||||
#define EIO_LCD_RST (TCA9539_IO_PIN7) /* LCD panel reset, output */
|
||||
|
||||
#define EIO_CAM_RST (TCA9539_IO_PIN0) /* Camera module reset, output */
|
||||
#define EIO_CAM_STB (TCA9539_IO_PIN1) /* Camera module standby, output */
|
||||
#define EIO_USB3300_RST (TCA9539_IO_PIN2) /* USBHS PHY USB3300 reset, output */
|
||||
#define EIO_ETH_RST (TCA9539_IO_PIN3) /* ETH PHY reset, output */
|
||||
#define EIO_CAN_STB (TCA9539_IO_PIN4) /* CAN PHY standby, output */
|
||||
#define EIO_LED_RED (TCA9539_IO_PIN5) /* Red LED, output */
|
||||
#define EIO_LED_YELLOW (TCA9539_IO_PIN6) /* Yellow LED, output */
|
||||
#define EIO_LED_BLUE (TCA9539_IO_PIN7) /* Blue LED, output */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup BSP_LED_PortPin_Sel BSP LED port/pin definition
|
||||
* @{
|
||||
*/
|
||||
#define LED_RED_PORT (TCA9539_IO_PORT1)
|
||||
#define LED_RED_PIN (EIO_LED_RED)
|
||||
#define LED_YELLOW_PORT (TCA9539_IO_PORT1)
|
||||
#define LED_YELLOW_PIN (EIO_LED_YELLOW)
|
||||
#define LED_BLUE_PORT (TCA9539_IO_PORT1)
|
||||
#define LED_BLUE_PIN (EIO_LED_BLUE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup BSP CAN PHY STB port/pin definition
|
||||
* @{
|
||||
*/
|
||||
#define CAN1_STB_PORT (TCA9539_IO_PORT1)
|
||||
#define CAN1_STB_PIN (TCA9539_IO_PIN4)
|
||||
#define CAN2_STB_PORT (TCA9539_IO_PORT1)
|
||||
#define CAN2_STB_PIN (TCA9539_IO_PIN5)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 2.2 MiB |
|
|
@ -0,0 +1,84 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.jlink.launchConfigurationType">
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.PERIPHERALS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <peripherals/> "/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doConnectToRunning" value="false"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doContinue" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doDebugInRam" value="false"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doFirstReset" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerAllocateConsole" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerAllocateSemihostingConsole" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerInitRegs" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerLocalOnly" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerSilent" value="false"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerVerifyDownload" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doSecondReset" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doStartGdbServer" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableFlashBreakpoints" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableSemihosting" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableSemihostingIoclientGdbClient" value="false"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableSemihostingIoclientTelnet" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableSwo" value="true"/>
|
||||
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.firstResetSpeed" value="1000"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.firstResetType" value=""/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbClientOtherCommands" value="set mem inaccessible-by-default off"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbClientOtherOptions" value=""/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerConnection" value="usb"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerConnectionAddress" value=""/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDebugInterface" value="swd"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDeviceEndianness" value="little"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDeviceName" value="HC32F4A8"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDeviceSpeed" value="1000"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerExecutable" value="${jlink_path}/${jlink_gdbserver}"/>
|
||||
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerGdbPortNumber" value="2331"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerLog" value=""/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerOther" value="-singlerun -strict -timeout 0 -nogui"/>
|
||||
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerSwoPortNumber" value="2332"/>
|
||||
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerTelnetPortNumber" value="2333"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.interfaceSpeed" value="auto"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.otherInitCommands" value=""/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.otherRunCommands" value=""/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.secondResetType" value=""/>
|
||||
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetCpuFreq" value="0"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetPortMask" value="0x1"/>
|
||||
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetSwoFreq" value="0"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/./packages/hc32f4a8_ddl-latest/cmsis/Device/HDSC/hc32f4xx/Source/GCC/svd/HC32F4A8.svd"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU J-Link"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
|
||||
<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="2331"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cross_prefix}gdb${cross_suffix}"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
|
||||
<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/rtthread.elf"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="project"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.553091094"/>
|
||||
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
|
||||
<listEntry value="/project"/>
|
||||
</listAttribute>
|
||||
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
|
||||
<listEntry value="4"/>
|
||||
</listAttribute>
|
||||
<listAttribute key="org.eclipse.debug.ui.favoriteGroups">
|
||||
<listEntry value="org.eclipse.debug.ui.launchGroup.debug"/>
|
||||
</listAttribute>
|
||||
<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="Context string"/> "/>
|
||||
<stringAttribute key="org.eclipse.embedcdt.debug.gdbjtag.core.PERIPHERALS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <peripherals> <peripheral name="GPIO"/> </peripherals> "/>
|
||||
<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
|
||||
</launchConfiguration>
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,10 @@
|
|||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<workspace>
|
||||
<project>
|
||||
<path>$WS_DIR$\project.ewp</path>
|
||||
</project>
|
||||
<batchBuild/>
|
||||
</workspace>
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,179 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
|
||||
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Extensions>
|
||||
<cExt>*.c</cExt>
|
||||
<aExt>*.s*; *.src; *.a*</aExt>
|
||||
<oExt>*.obj; *.o</oExt>
|
||||
<lExt>*.lib</lExt>
|
||||
<tExt>*.txt; *.h; *.inc</tExt>
|
||||
<pExt>*.plm</pExt>
|
||||
<CppX>*.cpp</CppX>
|
||||
<nMigrate>0</nMigrate>
|
||||
</Extensions>
|
||||
|
||||
<DaveTm>
|
||||
<dwLowDateTime>0</dwLowDateTime>
|
||||
<dwHighDateTime>0</dwHighDateTime>
|
||||
</DaveTm>
|
||||
|
||||
<Target>
|
||||
<TargetName>rt-thread</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>8000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
||||
<BeepAtEnd>1</BeepAtEnd>
|
||||
<RunSim>0</RunSim>
|
||||
<RunTarget>1</RunTarget>
|
||||
<RunAbUc>0</RunAbUc>
|
||||
</OPTTT>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<FlashByte>65535</FlashByte>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
</OPTHX>
|
||||
<OPTLEX>
|
||||
<PageWidth>79</PageWidth>
|
||||
<PageLength>66</PageLength>
|
||||
<TabStop>8</TabStop>
|
||||
<ListingPath>.\build\keil\List\</ListingPath>
|
||||
</OPTLEX>
|
||||
<ListingPage>
|
||||
<CreateCListing>1</CreateCListing>
|
||||
<CreateAListing>1</CreateAListing>
|
||||
<CreateLListing>1</CreateLListing>
|
||||
<CreateIListing>0</CreateIListing>
|
||||
<AsmCond>1</AsmCond>
|
||||
<AsmSymb>1</AsmSymb>
|
||||
<AsmXref>0</AsmXref>
|
||||
<CCond>1</CCond>
|
||||
<CCode>0</CCode>
|
||||
<CListInc>0</CListInc>
|
||||
<CSymb>0</CSymb>
|
||||
<LinkerCodeListing>0</LinkerCodeListing>
|
||||
</ListingPage>
|
||||
<OPTXL>
|
||||
<LMap>1</LMap>
|
||||
<LComments>1</LComments>
|
||||
<LGenerateSymbols>1</LGenerateSymbols>
|
||||
<LLibSym>1</LLibSym>
|
||||
<LLines>1</LLines>
|
||||
<LLocSym>1</LLocSym>
|
||||
<LPubSym>1</LPubSym>
|
||||
<LXref>0</LXref>
|
||||
<LExpSel>0</LExpSel>
|
||||
</OPTXL>
|
||||
<OPTFL>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<IsCurrentTarget>1</IsCurrentTarget>
|
||||
</OPTFL>
|
||||
<CpuCode>255</CpuCode>
|
||||
<DebugOpt>
|
||||
<uSim>0</uSim>
|
||||
<uTrg>1</uTrg>
|
||||
<sLdApp>1</sLdApp>
|
||||
<sGomain>1</sGomain>
|
||||
<sRbreak>1</sRbreak>
|
||||
<sRwatch>1</sRwatch>
|
||||
<sRmem>1</sRmem>
|
||||
<sRfunc>1</sRfunc>
|
||||
<sRbox>1</sRbox>
|
||||
<tLdApp>1</tLdApp>
|
||||
<tGomain>1</tGomain>
|
||||
<tRbreak>1</tRbreak>
|
||||
<tRwatch>1</tRwatch>
|
||||
<tRmem>1</tRmem>
|
||||
<tRfunc>0</tRfunc>
|
||||
<tRbox>1</tRbox>
|
||||
<tRtrace>1</tRtrace>
|
||||
<sRSysVw>1</sRSysVw>
|
||||
<tRSysVw>1</tRSysVw>
|
||||
<sRunDeb>0</sRunDeb>
|
||||
<sLrtime>0</sLrtime>
|
||||
<bEvRecOn>1</bEvRecOn>
|
||||
<bSchkAxf>0</bSchkAxf>
|
||||
<bTchkAxf>0</bTchkAxf>
|
||||
<nTsel>3</nTsel>
|
||||
<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
<sDlgPa></sDlgPa>
|
||||
<sIfile></sIfile>
|
||||
<tDll></tDll>
|
||||
<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
||||
<tIfile></tIfile>
|
||||
<pMon>BIN\CMSIS_AGDI.dll</pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>CMSIS_AGDI</Key>
|
||||
<Name>-X"" -O206 -S0 -C0 -P00 -FO15 -FD1FFE0000 -FC4000 -FN2 -FF0HC32F4A8_2M -FS00 -FL0200000 -FP0($$Device:HC32F4A8SITB$FlashARM/HC32F4A8_2M.FLM) -FF1HC32F4A8_otp -FS13000000 -FL11800 -FP1($$Device:HC32F4A8SITB$FlashARM/HC32F4A8_otp.FLM)</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<Breakpoint/>
|
||||
<Tracepoint>
|
||||
<THDelay>0</THDelay>
|
||||
</Tracepoint>
|
||||
<DebugFlag>
|
||||
<trace>0</trace>
|
||||
<periodic>0</periodic>
|
||||
<aLwin>1</aLwin>
|
||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
<aPa>0</aPa>
|
||||
<viewmode>1</viewmode>
|
||||
<vrSel>0</vrSel>
|
||||
<aSym>0</aSym>
|
||||
<aTbox>0</aTbox>
|
||||
<AscS1>0</AscS1>
|
||||
<AscS2>0</AscS2>
|
||||
<AscS3>0</AscS3>
|
||||
<aSer3>0</aSer3>
|
||||
<eProf>0</eProf>
|
||||
<aLa>0</aLa>
|
||||
<aPa1>0</aPa1>
|
||||
<AscS4>0</AscS4>
|
||||
<aSer4>0</aSer4>
|
||||
<StkLoc>0</StkLoc>
|
||||
<TrcWin>0</TrcWin>
|
||||
<newCpu>0</newCpu>
|
||||
<uProt>0</uProt>
|
||||
</DebugFlag>
|
||||
<LintExecutable></LintExecutable>
|
||||
<LintConfigFile></LintConfigFile>
|
||||
<bLintAuto>0</bLintAuto>
|
||||
<bAutoGenD>0</bAutoGenD>
|
||||
<LntExFlags>0</LntExFlags>
|
||||
<pMisraName></pMisraName>
|
||||
<pszMrule></pszMrule>
|
||||
<pSingCmds></pSingCmds>
|
||||
<pMultCmds></pMultCmds>
|
||||
<pMisraNamep></pMisraNamep>
|
||||
<pszMrulep></pszMrulep>
|
||||
<pSingCmdsp></pSingCmdsp>
|
||||
<pMultCmdsp></pMultCmdsp>
|
||||
<DebugDescription>
|
||||
<Enable>1</Enable>
|
||||
<EnableFlashSeq>0</EnableFlashSeq>
|
||||
<EnableLog>0</EnableLog>
|
||||
<Protocol>2</Protocol>
|
||||
<DbgClock>1000000</DbgClock>
|
||||
</DebugDescription>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
|
||||
</ProjectOpt>
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,427 @@
|
|||
#ifndef RT_CONFIG_H__
|
||||
#define RT_CONFIG_H__
|
||||
|
||||
/* RT-Thread Kernel */
|
||||
|
||||
/* klibc options */
|
||||
|
||||
/* rt_vsnprintf options */
|
||||
|
||||
/* end of rt_vsnprintf options */
|
||||
|
||||
/* rt_vsscanf options */
|
||||
|
||||
/* end of rt_vsscanf options */
|
||||
|
||||
/* rt_memset options */
|
||||
|
||||
/* end of rt_memset options */
|
||||
|
||||
/* rt_memcpy options */
|
||||
|
||||
/* end of rt_memcpy options */
|
||||
|
||||
/* rt_memmove options */
|
||||
|
||||
/* end of rt_memmove options */
|
||||
|
||||
/* rt_memcmp options */
|
||||
|
||||
/* end of rt_memcmp options */
|
||||
|
||||
/* rt_strstr options */
|
||||
|
||||
/* end of rt_strstr options */
|
||||
|
||||
/* rt_strcasecmp options */
|
||||
|
||||
/* end of rt_strcasecmp options */
|
||||
|
||||
/* rt_strncpy options */
|
||||
|
||||
/* end of rt_strncpy options */
|
||||
|
||||
/* rt_strcpy options */
|
||||
|
||||
/* end of rt_strcpy options */
|
||||
|
||||
/* rt_strncmp options */
|
||||
|
||||
/* end of rt_strncmp options */
|
||||
|
||||
/* rt_strcmp options */
|
||||
|
||||
/* end of rt_strcmp options */
|
||||
|
||||
/* rt_strlen options */
|
||||
|
||||
/* end of rt_strlen options */
|
||||
|
||||
/* rt_strnlen options */
|
||||
|
||||
/* end of rt_strnlen options */
|
||||
/* end of klibc options */
|
||||
#define RT_NAME_MAX 8
|
||||
#define RT_CPUS_NR 1
|
||||
#define RT_ALIGN_SIZE 8
|
||||
#define RT_THREAD_PRIORITY_32
|
||||
#define RT_THREAD_PRIORITY_MAX 32
|
||||
#define RT_TICK_PER_SECOND 1000
|
||||
#define RT_USING_OVERFLOW_CHECK
|
||||
#define RT_USING_HOOK
|
||||
#define RT_HOOK_USING_FUNC_PTR
|
||||
#define RT_USING_IDLE_HOOK
|
||||
#define RT_IDLE_HOOK_LIST_SIZE 4
|
||||
#define IDLE_THREAD_STACK_SIZE 256
|
||||
#define RT_USING_TIMER_SOFT
|
||||
#define RT_TIMER_THREAD_PRIO 4
|
||||
#define RT_TIMER_THREAD_STACK_SIZE 512
|
||||
|
||||
/* kservice options */
|
||||
|
||||
/* end of kservice options */
|
||||
#define RT_USING_DEBUG
|
||||
#define RT_DEBUGING_ASSERT
|
||||
#define RT_DEBUGING_COLOR
|
||||
#define RT_DEBUGING_CONTEXT
|
||||
|
||||
/* Inter-Thread communication */
|
||||
|
||||
#define RT_USING_SEMAPHORE
|
||||
#define RT_USING_MUTEX
|
||||
#define RT_USING_EVENT
|
||||
#define RT_USING_MAILBOX
|
||||
#define RT_USING_MESSAGEQUEUE
|
||||
/* end of Inter-Thread communication */
|
||||
|
||||
/* Memory Management */
|
||||
|
||||
#define RT_USING_MEMPOOL
|
||||
#define RT_USING_SMALL_MEM
|
||||
#define RT_USING_SMALL_MEM_AS_HEAP
|
||||
#define RT_USING_HEAP
|
||||
/* end of Memory Management */
|
||||
#define RT_USING_DEVICE
|
||||
#define RT_USING_CONSOLE
|
||||
#define RT_CONSOLEBUF_SIZE 128
|
||||
#define RT_CONSOLE_DEVICE_NAME "uart1"
|
||||
#define RT_VER_NUM 0x50200
|
||||
#define RT_BACKTRACE_LEVEL_MAX_NR 32
|
||||
/* end of RT-Thread Kernel */
|
||||
#define RT_USING_HW_ATOMIC
|
||||
#define RT_USING_CPU_FFS
|
||||
#define ARCH_ARM
|
||||
#define ARCH_ARM_CORTEX_M
|
||||
#define ARCH_ARM_CORTEX_M4
|
||||
|
||||
/* RT-Thread Components */
|
||||
|
||||
#define RT_USING_COMPONENTS_INIT
|
||||
#define RT_USING_USER_MAIN
|
||||
#define RT_MAIN_THREAD_STACK_SIZE 2048
|
||||
#define RT_MAIN_THREAD_PRIORITY 10
|
||||
#define RT_USING_MSH
|
||||
#define RT_USING_FINSH
|
||||
#define FINSH_USING_MSH
|
||||
#define FINSH_THREAD_NAME "tshell"
|
||||
#define FINSH_THREAD_PRIORITY 20
|
||||
#define FINSH_THREAD_STACK_SIZE 4096
|
||||
#define FINSH_USING_HISTORY
|
||||
#define FINSH_HISTORY_LINES 5
|
||||
#define FINSH_USING_SYMTAB
|
||||
#define FINSH_CMD_SIZE 80
|
||||
#define MSH_USING_BUILT_IN_COMMANDS
|
||||
#define FINSH_USING_DESCRIPTION
|
||||
#define FINSH_ARG_MAX 10
|
||||
#define FINSH_USING_OPTION_COMPLETION
|
||||
|
||||
/* DFS: device virtual file system */
|
||||
|
||||
/* end of DFS: device virtual file system */
|
||||
|
||||
/* Device Drivers */
|
||||
|
||||
#define RT_USING_DEVICE_IPC
|
||||
#define RT_UNAMED_PIPE_NUMBER 64
|
||||
#define RT_USING_SYSTEM_WORKQUEUE
|
||||
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
|
||||
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
|
||||
#define RT_USING_SERIAL
|
||||
#define RT_USING_SERIAL_V1
|
||||
#define RT_SERIAL_USING_DMA
|
||||
#define RT_SERIAL_RB_BUFSZ 64
|
||||
#define RT_USING_CAN
|
||||
#define RT_CAN_USING_HDR
|
||||
#define RT_USING_I2C
|
||||
#define RT_USING_I2C_BITOPS
|
||||
#define RT_USING_PIN
|
||||
/* end of Device Drivers */
|
||||
|
||||
/* C/C++ and POSIX layer */
|
||||
|
||||
/* ISO-ANSI C layer */
|
||||
|
||||
/* Timezone and Daylight Saving Time */
|
||||
|
||||
#define RT_LIBC_USING_LIGHT_TZ_DST
|
||||
#define RT_LIBC_TZ_DEFAULT_HOUR 8
|
||||
#define RT_LIBC_TZ_DEFAULT_MIN 0
|
||||
#define RT_LIBC_TZ_DEFAULT_SEC 0
|
||||
/* end of Timezone and Daylight Saving Time */
|
||||
/* end of ISO-ANSI C layer */
|
||||
|
||||
/* POSIX (Portable Operating System Interface) layer */
|
||||
|
||||
|
||||
/* Interprocess Communication (IPC) */
|
||||
|
||||
|
||||
/* Socket is in the 'Network' category */
|
||||
|
||||
/* end of Interprocess Communication (IPC) */
|
||||
/* end of POSIX (Portable Operating System Interface) layer */
|
||||
/* end of C/C++ and POSIX layer */
|
||||
|
||||
/* Network */
|
||||
|
||||
/* end of Network */
|
||||
|
||||
/* Memory protection */
|
||||
|
||||
/* end of Memory protection */
|
||||
|
||||
/* Utilities */
|
||||
|
||||
/* end of Utilities */
|
||||
|
||||
/* Using USB legacy version */
|
||||
|
||||
/* end of Using USB legacy version */
|
||||
/* end of RT-Thread Components */
|
||||
|
||||
/* RT-Thread Utestcases */
|
||||
|
||||
/* end of RT-Thread Utestcases */
|
||||
|
||||
/* RT-Thread online packages */
|
||||
|
||||
/* IoT - internet of things */
|
||||
|
||||
|
||||
/* Wi-Fi */
|
||||
|
||||
/* Marvell WiFi */
|
||||
|
||||
/* end of Marvell WiFi */
|
||||
|
||||
/* Wiced WiFi */
|
||||
|
||||
/* end of Wiced WiFi */
|
||||
|
||||
/* CYW43012 WiFi */
|
||||
|
||||
/* end of CYW43012 WiFi */
|
||||
|
||||
/* BL808 WiFi */
|
||||
|
||||
/* end of BL808 WiFi */
|
||||
|
||||
/* CYW43439 WiFi */
|
||||
|
||||
/* end of CYW43439 WiFi */
|
||||
/* end of Wi-Fi */
|
||||
|
||||
/* IoT Cloud */
|
||||
|
||||
/* end of IoT Cloud */
|
||||
/* end of IoT - internet of things */
|
||||
|
||||
/* security packages */
|
||||
|
||||
/* end of security packages */
|
||||
|
||||
/* language packages */
|
||||
|
||||
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
|
||||
|
||||
/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */
|
||||
|
||||
/* XML: Extensible Markup Language */
|
||||
|
||||
/* end of XML: Extensible Markup Language */
|
||||
/* end of language packages */
|
||||
|
||||
/* multimedia packages */
|
||||
|
||||
/* LVGL: powerful and easy-to-use embedded GUI library */
|
||||
|
||||
/* end of LVGL: powerful and easy-to-use embedded GUI library */
|
||||
|
||||
/* u8g2: a monochrome graphic library */
|
||||
|
||||
/* end of u8g2: a monochrome graphic library */
|
||||
/* end of multimedia packages */
|
||||
|
||||
/* tools packages */
|
||||
|
||||
/* end of tools packages */
|
||||
|
||||
/* system packages */
|
||||
|
||||
/* enhanced kernel services */
|
||||
|
||||
/* end of enhanced kernel services */
|
||||
|
||||
/* acceleration: Assembly language or algorithmic acceleration packages */
|
||||
|
||||
/* end of acceleration: Assembly language or algorithmic acceleration packages */
|
||||
|
||||
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
|
||||
|
||||
/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
|
||||
|
||||
/* Micrium: Micrium software products porting for RT-Thread */
|
||||
|
||||
/* end of Micrium: Micrium software products porting for RT-Thread */
|
||||
/* end of system packages */
|
||||
|
||||
/* peripheral libraries and drivers */
|
||||
|
||||
/* HAL & SDK Drivers */
|
||||
|
||||
/* STM32 HAL & SDK Drivers */
|
||||
|
||||
/* end of STM32 HAL & SDK Drivers */
|
||||
|
||||
/* Infineon HAL Packages */
|
||||
|
||||
/* end of Infineon HAL Packages */
|
||||
|
||||
/* Kendryte SDK */
|
||||
|
||||
/* end of Kendryte SDK */
|
||||
|
||||
/* HC32_DDL: DDL library file for HC32 */
|
||||
|
||||
#define PKG_USING_HC32F4A8_DDL
|
||||
#define PKG_USING_HC32F4A8_DDL_LATEST_VERSION
|
||||
/* end of HC32_DDL: DDL library file for HC32 */
|
||||
/* end of HAL & SDK Drivers */
|
||||
|
||||
/* sensors drivers */
|
||||
|
||||
/* end of sensors drivers */
|
||||
|
||||
/* touch drivers */
|
||||
|
||||
/* end of touch drivers */
|
||||
/* end of peripheral libraries and drivers */
|
||||
|
||||
/* AI packages */
|
||||
|
||||
/* end of AI packages */
|
||||
|
||||
/* Signal Processing and Control Algorithm Packages */
|
||||
|
||||
/* end of Signal Processing and Control Algorithm Packages */
|
||||
|
||||
/* miscellaneous packages */
|
||||
|
||||
/* project laboratory */
|
||||
|
||||
/* end of project laboratory */
|
||||
|
||||
/* samples: kernel and components samples */
|
||||
|
||||
/* end of samples: kernel and components samples */
|
||||
|
||||
/* entertainment: terminal games and other interesting software packages */
|
||||
|
||||
/* end of entertainment: terminal games and other interesting software packages */
|
||||
/* end of miscellaneous packages */
|
||||
|
||||
/* Arduino libraries */
|
||||
|
||||
|
||||
/* Projects and Demos */
|
||||
|
||||
/* end of Projects and Demos */
|
||||
|
||||
/* Sensors */
|
||||
|
||||
/* end of Sensors */
|
||||
|
||||
/* Display */
|
||||
|
||||
/* end of Display */
|
||||
|
||||
/* Timing */
|
||||
|
||||
/* end of Timing */
|
||||
|
||||
/* Data Processing */
|
||||
|
||||
/* end of Data Processing */
|
||||
|
||||
/* Data Storage */
|
||||
|
||||
/* Communication */
|
||||
|
||||
/* end of Communication */
|
||||
|
||||
/* Device Control */
|
||||
|
||||
/* end of Device Control */
|
||||
|
||||
/* Other */
|
||||
|
||||
/* end of Other */
|
||||
|
||||
/* Signal IO */
|
||||
|
||||
/* end of Signal IO */
|
||||
|
||||
/* Uncategorized */
|
||||
|
||||
/* end of Arduino libraries */
|
||||
/* end of RT-Thread online packages */
|
||||
#define SOC_FAMILY_HC32
|
||||
#define SOC_SERIES_HC32F4
|
||||
|
||||
/* Hardware Drivers Config */
|
||||
|
||||
#define SOC_HC32F4A8SI
|
||||
|
||||
/* On-chip Drivers */
|
||||
|
||||
#define BSP_USING_ON_CHIP_FLASH_CACHE
|
||||
#define BSP_USING_ON_CHIP_FLASH_ICODE_CACHE
|
||||
#define BSP_USING_ON_CHIP_FLASH_DCODE_CACHE
|
||||
#define BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH
|
||||
/* end of On-chip Drivers */
|
||||
|
||||
/* Onboard Peripheral Drivers */
|
||||
|
||||
#define BSP_USING_TCA9539
|
||||
#define BSP_USING_EXT_IO
|
||||
/* end of Onboard Peripheral Drivers */
|
||||
|
||||
/* On-chip Peripheral Drivers */
|
||||
|
||||
#define BSP_USING_GPIO
|
||||
#define BSP_USING_UART
|
||||
#define BSP_USING_UART1
|
||||
#define BSP_USING_I2C
|
||||
#define BSP_USING_I2C_HW
|
||||
#define BSP_USING_I2C1
|
||||
#define RT_USING_CAN_MCAN
|
||||
#define BSP_USING_MCAN
|
||||
#define BSP_USING_MCAN1
|
||||
#define BSP_USING_MCAN2
|
||||
/* end of On-chip Peripheral Drivers */
|
||||
|
||||
/* Board extended module Drivers */
|
||||
|
||||
/* end of Hardware Drivers Config */
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,150 @@
|
|||
import os
|
||||
|
||||
# toolchains options
|
||||
ARCH='arm'
|
||||
CPU='cortex-m4'
|
||||
CROSS_TOOL='gcc'
|
||||
|
||||
# bsp lib config
|
||||
BSP_LIBRARY_TYPE = None
|
||||
|
||||
if os.getenv('RTT_CC'):
|
||||
CROSS_TOOL = os.getenv('RTT_CC')
|
||||
if os.getenv('RTT_ROOT'):
|
||||
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||
|
||||
# cross_tool provides the cross compiler
|
||||
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
|
||||
if CROSS_TOOL == 'gcc':
|
||||
PLATFORM = 'gcc'
|
||||
if os.getenv('RTT_EXEC_PATH'):
|
||||
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
|
||||
else:
|
||||
EXEC_PATH = r'C:/Users/XXYYZZ'
|
||||
elif CROSS_TOOL == 'keil':
|
||||
PLATFORM = 'armcc'
|
||||
EXEC_PATH = r'C:/Keil_v5'
|
||||
elif CROSS_TOOL == 'iar':
|
||||
PLATFORM = 'iccarm'
|
||||
EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.4'
|
||||
|
||||
BUILD = 'debug'
|
||||
|
||||
if PLATFORM == 'gcc':
|
||||
# toolchains
|
||||
PREFIX = 'arm-none-eabi-'
|
||||
CC = PREFIX + 'gcc'
|
||||
AS = PREFIX + 'gcc'
|
||||
AR = PREFIX + 'ar'
|
||||
CXX = PREFIX + 'g++'
|
||||
LINK = PREFIX + 'gcc'
|
||||
TARGET_EXT = 'elf'
|
||||
SIZE = PREFIX + 'size'
|
||||
OBJDUMP = PREFIX + 'objdump'
|
||||
OBJCPY = PREFIX + 'objcopy'
|
||||
|
||||
DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections'
|
||||
CFLAGS = DEVICE + ' -Dgcc'
|
||||
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
|
||||
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.ld'
|
||||
|
||||
CPATH = ''
|
||||
LPATH = ''
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -O0 -gdwarf-2 -g'
|
||||
AFLAGS += ' -gdwarf-2'
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
|
||||
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
|
||||
|
||||
elif PLATFORM == 'armcc':
|
||||
# toolchains
|
||||
CC = 'armcc'
|
||||
CXX = 'armcc'
|
||||
AS = 'armasm'
|
||||
AR = 'armar'
|
||||
LINK = 'armlink'
|
||||
TARGET_EXT = 'axf'
|
||||
|
||||
DEVICE = ' --cpu Cortex-M4.fp '
|
||||
CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
|
||||
AFLAGS = DEVICE + ' --apcs=interwork '
|
||||
LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict'
|
||||
CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
|
||||
LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib'
|
||||
|
||||
CFLAGS += ' -D__MICROLIB '
|
||||
AFLAGS += ' --pd "__MICROLIB SETA 1" '
|
||||
LFLAGS += ' --library_type=microlib '
|
||||
EXEC_PATH += '/ARM/ARMCC/bin/'
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -g -O0'
|
||||
AFLAGS += ' -g'
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
CFLAGS += ' -std=c99'
|
||||
|
||||
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
|
||||
|
||||
elif PLATFORM == 'iccarm':
|
||||
# toolchains
|
||||
CC = 'iccarm'
|
||||
CXX = 'iccarm'
|
||||
AS = 'iasmarm'
|
||||
AR = 'iarchive'
|
||||
LINK = 'ilinkarm'
|
||||
TARGET_EXT = 'out'
|
||||
|
||||
DEVICE = '-Dewarm'
|
||||
|
||||
CFLAGS = DEVICE
|
||||
CFLAGS += ' --diag_suppress Pa050'
|
||||
CFLAGS += ' --no_cse'
|
||||
CFLAGS += ' --no_unroll'
|
||||
CFLAGS += ' --no_inline'
|
||||
CFLAGS += ' --no_code_motion'
|
||||
CFLAGS += ' --no_tbaa'
|
||||
CFLAGS += ' --no_clustering'
|
||||
CFLAGS += ' --no_scheduling'
|
||||
CFLAGS += ' --endian=little'
|
||||
CFLAGS += ' --cpu=Cortex-M4'
|
||||
CFLAGS += ' -e'
|
||||
CFLAGS += ' --fpu=VFPv4_sp'
|
||||
CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
|
||||
CFLAGS += ' --silent'
|
||||
|
||||
AFLAGS = DEVICE
|
||||
AFLAGS += ' -s+'
|
||||
AFLAGS += ' -w+'
|
||||
AFLAGS += ' -r'
|
||||
AFLAGS += ' --cpu Cortex-M4'
|
||||
AFLAGS += ' --fpu VFPv4_sp'
|
||||
AFLAGS += ' -S'
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' --debug'
|
||||
CFLAGS += ' -On'
|
||||
else:
|
||||
CFLAGS += ' -Oh'
|
||||
|
||||
LFLAGS = ' --config "board/linker_scripts/link.icf"'
|
||||
LFLAGS += ' --entry __iar_program_start'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
|
||||
EXEC_PATH = EXEC_PATH + '/arm/bin/'
|
||||
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
|
||||
|
||||
def dist_handle(BSP_ROOT, dist_dir):
|
||||
import sys
|
||||
cwd_path = os.getcwd()
|
||||
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
|
||||
from sdk_dist import dist_do_building
|
||||
dist_do_building(BSP_ROOT, dist_dir)
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,10 @@
|
|||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<workspace>
|
||||
<project>
|
||||
<path>$WS_DIR$\template.ewp</path>
|
||||
</project>
|
||||
<batchBuild/>
|
||||
</workspace>
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,179 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
|
||||
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Extensions>
|
||||
<cExt>*.c</cExt>
|
||||
<aExt>*.s*; *.src; *.a*</aExt>
|
||||
<oExt>*.obj; *.o</oExt>
|
||||
<lExt>*.lib</lExt>
|
||||
<tExt>*.txt; *.h; *.inc</tExt>
|
||||
<pExt>*.plm</pExt>
|
||||
<CppX>*.cpp</CppX>
|
||||
<nMigrate>0</nMigrate>
|
||||
</Extensions>
|
||||
|
||||
<DaveTm>
|
||||
<dwLowDateTime>0</dwLowDateTime>
|
||||
<dwHighDateTime>0</dwHighDateTime>
|
||||
</DaveTm>
|
||||
|
||||
<Target>
|
||||
<TargetName>rt-thread</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>8000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
||||
<BeepAtEnd>1</BeepAtEnd>
|
||||
<RunSim>0</RunSim>
|
||||
<RunTarget>1</RunTarget>
|
||||
<RunAbUc>0</RunAbUc>
|
||||
</OPTTT>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<FlashByte>65535</FlashByte>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
</OPTHX>
|
||||
<OPTLEX>
|
||||
<PageWidth>79</PageWidth>
|
||||
<PageLength>66</PageLength>
|
||||
<TabStop>8</TabStop>
|
||||
<ListingPath>.\build\keil\List\</ListingPath>
|
||||
</OPTLEX>
|
||||
<ListingPage>
|
||||
<CreateCListing>1</CreateCListing>
|
||||
<CreateAListing>1</CreateAListing>
|
||||
<CreateLListing>1</CreateLListing>
|
||||
<CreateIListing>0</CreateIListing>
|
||||
<AsmCond>1</AsmCond>
|
||||
<AsmSymb>1</AsmSymb>
|
||||
<AsmXref>0</AsmXref>
|
||||
<CCond>1</CCond>
|
||||
<CCode>0</CCode>
|
||||
<CListInc>0</CListInc>
|
||||
<CSymb>0</CSymb>
|
||||
<LinkerCodeListing>0</LinkerCodeListing>
|
||||
</ListingPage>
|
||||
<OPTXL>
|
||||
<LMap>1</LMap>
|
||||
<LComments>1</LComments>
|
||||
<LGenerateSymbols>1</LGenerateSymbols>
|
||||
<LLibSym>1</LLibSym>
|
||||
<LLines>1</LLines>
|
||||
<LLocSym>1</LLocSym>
|
||||
<LPubSym>1</LPubSym>
|
||||
<LXref>0</LXref>
|
||||
<LExpSel>0</LExpSel>
|
||||
</OPTXL>
|
||||
<OPTFL>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<IsCurrentTarget>1</IsCurrentTarget>
|
||||
</OPTFL>
|
||||
<CpuCode>255</CpuCode>
|
||||
<DebugOpt>
|
||||
<uSim>0</uSim>
|
||||
<uTrg>1</uTrg>
|
||||
<sLdApp>1</sLdApp>
|
||||
<sGomain>1</sGomain>
|
||||
<sRbreak>1</sRbreak>
|
||||
<sRwatch>1</sRwatch>
|
||||
<sRmem>1</sRmem>
|
||||
<sRfunc>1</sRfunc>
|
||||
<sRbox>1</sRbox>
|
||||
<tLdApp>1</tLdApp>
|
||||
<tGomain>1</tGomain>
|
||||
<tRbreak>1</tRbreak>
|
||||
<tRwatch>1</tRwatch>
|
||||
<tRmem>1</tRmem>
|
||||
<tRfunc>0</tRfunc>
|
||||
<tRbox>1</tRbox>
|
||||
<tRtrace>1</tRtrace>
|
||||
<sRSysVw>1</sRSysVw>
|
||||
<tRSysVw>1</tRSysVw>
|
||||
<sRunDeb>0</sRunDeb>
|
||||
<sLrtime>0</sLrtime>
|
||||
<bEvRecOn>1</bEvRecOn>
|
||||
<bSchkAxf>0</bSchkAxf>
|
||||
<bTchkAxf>0</bTchkAxf>
|
||||
<nTsel>3</nTsel>
|
||||
<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
<sDlgPa></sDlgPa>
|
||||
<sIfile></sIfile>
|
||||
<tDll></tDll>
|
||||
<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
||||
<tIfile></tIfile>
|
||||
<pMon>BIN\CMSIS_AGDI.dll</pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>CMSIS_AGDI</Key>
|
||||
<Name>-X"" -O206 -S0 -C0 -P00 -FO15 -FD1FFE0000 -FC4000 -FN2 -FF0HC32F4A8_2M -FS00 -FL0200000 -FP0($$Device:HC32F4A8SITB$FlashARM/HC32F4A8_2M.FLM) -FF1HC32F4A8_otp -FS13000000 -FL11800 -FP1($$Device:HC32F4A8SITB$FlashARM/HC32F4A8_otp.FLM)</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<Breakpoint/>
|
||||
<Tracepoint>
|
||||
<THDelay>0</THDelay>
|
||||
</Tracepoint>
|
||||
<DebugFlag>
|
||||
<trace>0</trace>
|
||||
<periodic>0</periodic>
|
||||
<aLwin>1</aLwin>
|
||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
<aPa>0</aPa>
|
||||
<viewmode>1</viewmode>
|
||||
<vrSel>0</vrSel>
|
||||
<aSym>0</aSym>
|
||||
<aTbox>0</aTbox>
|
||||
<AscS1>0</AscS1>
|
||||
<AscS2>0</AscS2>
|
||||
<AscS3>0</AscS3>
|
||||
<aSer3>0</aSer3>
|
||||
<eProf>0</eProf>
|
||||
<aLa>0</aLa>
|
||||
<aPa1>0</aPa1>
|
||||
<AscS4>0</AscS4>
|
||||
<aSer4>0</aSer4>
|
||||
<StkLoc>0</StkLoc>
|
||||
<TrcWin>0</TrcWin>
|
||||
<newCpu>0</newCpu>
|
||||
<uProt>0</uProt>
|
||||
</DebugFlag>
|
||||
<LintExecutable></LintExecutable>
|
||||
<LintConfigFile></LintConfigFile>
|
||||
<bLintAuto>0</bLintAuto>
|
||||
<bAutoGenD>0</bAutoGenD>
|
||||
<LntExFlags>0</LntExFlags>
|
||||
<pMisraName></pMisraName>
|
||||
<pszMrule></pszMrule>
|
||||
<pSingCmds></pSingCmds>
|
||||
<pMultCmds></pMultCmds>
|
||||
<pMisraNamep></pMisraNamep>
|
||||
<pszMrulep></pszMrulep>
|
||||
<pSingCmdsp></pSingCmdsp>
|
||||
<pMultCmdsp></pMultCmdsp>
|
||||
<DebugDescription>
|
||||
<Enable>1</Enable>
|
||||
<EnableFlashSeq>0</EnableFlashSeq>
|
||||
<EnableLog>0</EnableLog>
|
||||
<Protocol>2</Protocol>
|
||||
<DbgClock>1000000</DbgClock>
|
||||
</DebugDescription>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
|
||||
</ProjectOpt>
|
||||
|
|
@ -0,0 +1,390 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
|
||||
|
||||
<SchemaVersion>2.1</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Targets>
|
||||
<Target>
|
||||
<TargetName>rt-thread</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
|
||||
<uAC6>0</uAC6>
|
||||
<TargetOption>
|
||||
<TargetCommonOption>
|
||||
<Device>HC32F4A8SITB</Device>
|
||||
<Vendor>HDSC</Vendor>
|
||||
<PackID>HDSC.HC32F4A8.1.0.0</PackID>
|
||||
<PackURL>https://raw.githubusercontent.com/hdscmcu/pack/master/</PackURL>
|
||||
<Cpu>IROM1(0x00000000,0x200000) IROM2(0x03000000,0x1800) IRAM1(0x1FFE0000,0x80000) IRAM2(0x200F0000,0x1000) CPUTYPE("Cortex-M4") FPU2 CLOCK(8000000) ESEL ELITTLE</Cpu>
|
||||
<FlashUtilSpec></FlashUtilSpec>
|
||||
<StartupFile></StartupFile>
|
||||
<FlashDriverDll>CMSIS_AGDI(-S0 -C0 -P00 -FO15 -FD1FFE0000 -FC4000 -FN2 -FF0HC32F4A8_2M -FS00 -FL0200000 -FP0($$Device:HC32F4A8SITB$FlashARM/HC32F4A8_2M.FLM) -FF1HC32F4A8_otp -FS13000000 -FL11800 -FP1($$Device:HC32F4A8SITB$FlashARM/HC32F4A8_otp.FLM))</FlashDriverDll>
|
||||
<DeviceId>0</DeviceId>
|
||||
<RegisterFile>$$Device:HC32F4A8SITB$Device\Include\HC32F4A8SITB.h</RegisterFile>
|
||||
<MemoryEnv></MemoryEnv>
|
||||
<Cmp></Cmp>
|
||||
<Asm></Asm>
|
||||
<Linker></Linker>
|
||||
<OHString></OHString>
|
||||
<InfinionOptionDll></InfinionOptionDll>
|
||||
<SLE66CMisc></SLE66CMisc>
|
||||
<SLE66AMisc></SLE66AMisc>
|
||||
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||
<SFDFile>./packages/hc32f4a8_ddl-latest/cmsis/Device/HDSC/hc32f4xx/Source/ARM/sfr/HC32F4A8.SFR</SFDFile>
|
||||
<bCustSvd>1</bCustSvd>
|
||||
<UseEnv>0</UseEnv>
|
||||
<BinPath></BinPath>
|
||||
<IncludePath></IncludePath>
|
||||
<LibPath></LibPath>
|
||||
<RegisterFilePath></RegisterFilePath>
|
||||
<DBRegisterFilePath></DBRegisterFilePath>
|
||||
<TargetStatus>
|
||||
<Error>0</Error>
|
||||
<ExitCodeStop>0</ExitCodeStop>
|
||||
<ButtonStop>0</ButtonStop>
|
||||
<NotGenerated>0</NotGenerated>
|
||||
<InvalidFlash>1</InvalidFlash>
|
||||
</TargetStatus>
|
||||
<OutputDirectory>.\build\keil\Obj\</OutputDirectory>
|
||||
<OutputName>rt-thread</OutputName>
|
||||
<CreateExecutable>1</CreateExecutable>
|
||||
<CreateLib>0</CreateLib>
|
||||
<CreateHexFile>1</CreateHexFile>
|
||||
<DebugInformation>1</DebugInformation>
|
||||
<BrowseInformation>0</BrowseInformation>
|
||||
<ListingPath>.\build\keil\List\</ListingPath>
|
||||
<HexFormatSelection>1</HexFormatSelection>
|
||||
<Merge32K>0</Merge32K>
|
||||
<CreateBatchFile>0</CreateBatchFile>
|
||||
<BeforeCompile>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopU1X>0</nStopU1X>
|
||||
<nStopU2X>0</nStopU2X>
|
||||
</BeforeCompile>
|
||||
<BeforeMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopB1X>0</nStopB1X>
|
||||
<nStopB2X>0</nStopB2X>
|
||||
</BeforeMake>
|
||||
<AfterMake>
|
||||
<RunUserProg1>1</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopA1X>0</nStopA1X>
|
||||
<nStopA2X>0</nStopA2X>
|
||||
</AfterMake>
|
||||
<SelectedForBatchBuild>0</SelectedForBatchBuild>
|
||||
<SVCSIdString></SVCSIdString>
|
||||
</TargetCommonOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>0</UseCPPCompiler>
|
||||
<RVCTCodeConst>0</RVCTCodeConst>
|
||||
<RVCTZI>0</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>1</IncludeInBuild>
|
||||
<AlwaysBuild>0</AlwaysBuild>
|
||||
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||
<PublicsOnly>0</PublicsOnly>
|
||||
<StopOnExitCode>3</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
<ComprImg>1</ComprImg>
|
||||
</CommonProperty>
|
||||
<DllOption>
|
||||
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||
<SimDllArguments> -REMAP -MPU</SimDllArguments>
|
||||
<SimDlgDll>DCM.DLL</SimDlgDll>
|
||||
<SimDlgDllArguments>-pCM4</SimDlgDllArguments>
|
||||
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||
<TargetDllArguments> -MPU</TargetDllArguments>
|
||||
<TargetDlgDll>TCM.DLL</TargetDlgDll>
|
||||
<TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
|
||||
</DllOption>
|
||||
<DebugOption>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
<Oh166RecLen>16</Oh166RecLen>
|
||||
</OPTHX>
|
||||
</DebugOption>
|
||||
<Utilities>
|
||||
<Flash1>
|
||||
<UseTargetDll>1</UseTargetDll>
|
||||
<UseExternalTool>0</UseExternalTool>
|
||||
<RunIndependent>0</RunIndependent>
|
||||
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||
<Capability>1</Capability>
|
||||
<DriverSelection>4096</DriverSelection>
|
||||
</Flash1>
|
||||
<bUseTDR>1</bUseTDR>
|
||||
<Flash2>BIN\UL2CM3.DLL</Flash2>
|
||||
<Flash3></Flash3>
|
||||
<Flash4></Flash4>
|
||||
<pFcarmOut></pFcarmOut>
|
||||
<pFcarmGrp></pFcarmGrp>
|
||||
<pFcArmRoot></pFcArmRoot>
|
||||
<FcArmLst>0</FcArmLst>
|
||||
</Utilities>
|
||||
<TargetArmAds>
|
||||
<ArmAdsMisc>
|
||||
<GenerateListings>0</GenerateListings>
|
||||
<asHll>1</asHll>
|
||||
<asAsm>1</asAsm>
|
||||
<asMacX>1</asMacX>
|
||||
<asSyms>1</asSyms>
|
||||
<asFals>1</asFals>
|
||||
<asDbgD>1</asDbgD>
|
||||
<asForm>1</asForm>
|
||||
<ldLst>0</ldLst>
|
||||
<ldmm>1</ldmm>
|
||||
<ldXref>1</ldXref>
|
||||
<BigEnd>0</BigEnd>
|
||||
<AdsALst>1</AdsALst>
|
||||
<AdsACrf>1</AdsACrf>
|
||||
<AdsANop>0</AdsANop>
|
||||
<AdsANot>0</AdsANot>
|
||||
<AdsLLst>1</AdsLLst>
|
||||
<AdsLmap>1</AdsLmap>
|
||||
<AdsLcgr>1</AdsLcgr>
|
||||
<AdsLsym>1</AdsLsym>
|
||||
<AdsLszi>1</AdsLszi>
|
||||
<AdsLtoi>1</AdsLtoi>
|
||||
<AdsLsun>1</AdsLsun>
|
||||
<AdsLven>1</AdsLven>
|
||||
<AdsLsxf>1</AdsLsxf>
|
||||
<RvctClst>0</RvctClst>
|
||||
<GenPPlst>0</GenPPlst>
|
||||
<AdsCpuType>"Cortex-M4"</AdsCpuType>
|
||||
<RvctDeviceName></RvctDeviceName>
|
||||
<mOS>0</mOS>
|
||||
<uocRom>0</uocRom>
|
||||
<uocRam>0</uocRam>
|
||||
<hadIROM>1</hadIROM>
|
||||
<hadIRAM>1</hadIRAM>
|
||||
<hadXRAM>0</hadXRAM>
|
||||
<uocXRam>0</uocXRam>
|
||||
<RvdsVP>1</RvdsVP>
|
||||
<RvdsMve>0</RvdsMve>
|
||||
<hadIRAM2>1</hadIRAM2>
|
||||
<hadIROM2>0</hadIROM2>
|
||||
<StupSel>8</StupSel>
|
||||
<useUlib>0</useUlib>
|
||||
<EndSel>1</EndSel>
|
||||
<uLtcg>0</uLtcg>
|
||||
<nSecure>0</nSecure>
|
||||
<RoSelD>3</RoSelD>
|
||||
<RwSelD>3</RwSelD>
|
||||
<CodeSel>0</CodeSel>
|
||||
<OptFeed>0</OptFeed>
|
||||
<NoZi1>0</NoZi1>
|
||||
<NoZi2>0</NoZi2>
|
||||
<NoZi3>0</NoZi3>
|
||||
<NoZi4>0</NoZi4>
|
||||
<NoZi5>0</NoZi5>
|
||||
<Ro1Chk>0</Ro1Chk>
|
||||
<Ro2Chk>0</Ro2Chk>
|
||||
<Ro3Chk>0</Ro3Chk>
|
||||
<Ir1Chk>1</Ir1Chk>
|
||||
<Ir2Chk>0</Ir2Chk>
|
||||
<Ra1Chk>0</Ra1Chk>
|
||||
<Ra2Chk>0</Ra2Chk>
|
||||
<Ra3Chk>0</Ra3Chk>
|
||||
<Im1Chk>1</Im1Chk>
|
||||
<Im2Chk>0</Im2Chk>
|
||||
<OnChipMemories>
|
||||
<Ocm1>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm1>
|
||||
<Ocm2>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm2>
|
||||
<Ocm3>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm3>
|
||||
<Ocm4>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm4>
|
||||
<Ocm5>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm5>
|
||||
<Ocm6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm6>
|
||||
<IRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x1FFE0000</StartAddress>
|
||||
<Size>0x80000</Size>
|
||||
</IRAM>
|
||||
<IROM>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x200000</Size>
|
||||
</IROM>
|
||||
<XRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</XRAM>
|
||||
<OCR_RVCT1>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT1>
|
||||
<OCR_RVCT2>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT2>
|
||||
<OCR_RVCT3>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT3>
|
||||
<OCR_RVCT4>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x200000</Size>
|
||||
</OCR_RVCT4>
|
||||
<OCR_RVCT5>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x03000000</StartAddress>
|
||||
<Size>0x1800</Size>
|
||||
</OCR_RVCT5>
|
||||
<OCR_RVCT6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT6>
|
||||
<OCR_RVCT7>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT7>
|
||||
<OCR_RVCT8>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT8>
|
||||
<OCR_RVCT9>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x1FFE0000</StartAddress>
|
||||
<Size>0x80000</Size>
|
||||
</OCR_RVCT9>
|
||||
<OCR_RVCT10>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x200F0000</StartAddress>
|
||||
<Size>0x1000</Size>
|
||||
</OCR_RVCT10>
|
||||
</OnChipMemories>
|
||||
<RvctStartVector></RvctStartVector>
|
||||
</ArmAdsMisc>
|
||||
<Cads>
|
||||
<interw>1</interw>
|
||||
<Optim>1</Optim>
|
||||
<oTime>0</oTime>
|
||||
<SplitLS>0</SplitLS>
|
||||
<OneElfS>1</OneElfS>
|
||||
<Strict>0</Strict>
|
||||
<EnumInt>0</EnumInt>
|
||||
<PlainCh>0</PlainCh>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<wLevel>2</wLevel>
|
||||
<uThumb>0</uThumb>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<uC99>1</uC99>
|
||||
<uGnu>1</uGnu>
|
||||
<useXO>0</useXO>
|
||||
<v6Lang>0</v6Lang>
|
||||
<v6LangP>0</v6LangP>
|
||||
<vShortEn>0</vShortEn>
|
||||
<vShortWch>0</vShortWch>
|
||||
<v6Lto>0</v6Lto>
|
||||
<v6WtE>0</v6WtE>
|
||||
<v6Rtti>0</v6Rtti>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
<Aads>
|
||||
<interw>1</interw>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<thumb>0</thumb>
|
||||
<SplitLS>0</SplitLS>
|
||||
<SwStkChk>0</SwStkChk>
|
||||
<NoWarn>0</NoWarn>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<useXO>0</useXO>
|
||||
<uClangAs>0</uClangAs>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Aads>
|
||||
<LDads>
|
||||
<umfTarg>0</umfTarg>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<noStLib>0</noStLib>
|
||||
<RepFail>1</RepFail>
|
||||
<useFile>0</useFile>
|
||||
<TextAddressRange>0x00000000</TextAddressRange>
|
||||
<DataAddressRange>0x1FFE0000</DataAddressRange>
|
||||
<pXoBase></pXoBase>
|
||||
<ScatterFile>.\board\linker_scripts\link.sct</ScatterFile>
|
||||
<IncludeLibs></IncludeLibs>
|
||||
<IncludeLibsPath></IncludeLibsPath>
|
||||
<Misc></Misc>
|
||||
<LinkerInputFile></LinkerInputFile>
|
||||
<DisabledWarnings></DisabledWarnings>
|
||||
</LDads>
|
||||
</TargetArmAds>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
</Targets>
|
||||
|
||||
<RTE>
|
||||
<apis/>
|
||||
<components/>
|
||||
<files/>
|
||||
</RTE>
|
||||
|
||||
</Project>
|
||||
|
|
@ -20,7 +20,8 @@ extern "C" {
|
|||
#endif
|
||||
|
||||
|
||||
#define HC32_FLASH_SIZE_GRANULARITY (8 * 1024)
|
||||
#define HC32_FLASH_ERASE_GRANULARITY (8 * 1024)
|
||||
#define HC32_FLASH_WRITE_GRANULARITY (4)
|
||||
#define HC32_FLASH_SIZE (2 * 1024 * 1024)
|
||||
#define HC32_FLASH_START_ADDRESS (0)
|
||||
#define HC32_FLASH_END_ADDRESS (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE)
|
||||
|
|
|
|||
|
|
@ -231,6 +231,30 @@ extern "C" {
|
|||
#define I2C4_RX_DMA_INT_SRC INT_SRC_DMA1_TC7
|
||||
#endif
|
||||
|
||||
/* DMA1 ch8 */
|
||||
#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
|
||||
#define SPI5_TX_DMA_INSTANCE CM_DMA1
|
||||
#define SPI5_TX_DMA_CHANNEL DMA_CH8
|
||||
#define SPI5_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define SPI5_TX_DMA_TRIG_SELECT AOS_DMA1_8
|
||||
#define SPI5_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH8
|
||||
#define SPI5_TX_DMA_IRQn BSP_DMA1_CH8_IRQ_NUM
|
||||
#define SPI5_TX_DMA_INT_PRIO BSP_DMA1_CH8_IRQ_PRIO
|
||||
#define SPI5_TX_DMA_INT_SRC INT_SRC_DMA1_TC8
|
||||
#endif
|
||||
|
||||
/* DMA1 ch9 */
|
||||
#if defined(BSP_SPI6_TX_USING_DMA) && !defined(SPI6_TX_DMA_INSTANCE)
|
||||
#define SPI6_TX_DMA_INSTANCE CM_DMA1
|
||||
#define SPI6_TX_DMA_CHANNEL DMA_CH9
|
||||
#define SPI6_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define SPI6_TX_DMA_TRIG_SELECT AOS_DMA1_9
|
||||
#define SPI6_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH9
|
||||
#define SPI6_TX_DMA_IRQn BSP_DMA1_CH9_IRQ_NUM
|
||||
#define SPI6_TX_DMA_INT_PRIO BSP_DMA1_CH9_IRQ_PRIO
|
||||
#define SPI6_TX_DMA_INT_SRC INT_SRC_DMA1_TC9
|
||||
#endif
|
||||
|
||||
/* DMA2 ch0 */
|
||||
#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
|
||||
#define UART1_RX_DMA_INSTANCE CM_DMA2
|
||||
|
|
|
|||
|
|
@ -74,6 +74,12 @@ extern "C" {
|
|||
/* DMA1 ch7 */
|
||||
#define BSP_DMA1_CH7_IRQ_NUM INT019_IRQn
|
||||
#define BSP_DMA1_CH7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
/* DMA1 ch8 */
|
||||
#define BSP_DMA1_CH8_IRQ_NUM INT020_IRQn
|
||||
#define BSP_DMA1_CH8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
/* DMA1 ch9 */
|
||||
#define BSP_DMA1_CH9_IRQ_NUM INT021_IRQn
|
||||
#define BSP_DMA1_CH9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
|
||||
/* DMA2 ch0 */
|
||||
#define BSP_DMA2_CH0_IRQ_NUM INT044_IRQn
|
||||
|
|
@ -235,6 +241,16 @@ extern "C" {
|
|||
#define BSP_SPI4_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_SPI5)
|
||||
#define BSP_SPI5_ERR_IRQ_NUM INT098_IRQn
|
||||
#define BSP_SPI5_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_SPI6)
|
||||
#define BSP_SPI6_ERR_IRQ_NUM INT099_IRQn
|
||||
#define BSP_SPI6_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_UART8)
|
||||
#define BSP_UART8_RXERR_IRQ_NUM INT017_IRQn
|
||||
#define BSP_UART8_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
|
|
|
|||
|
|
@ -38,11 +38,11 @@ if GetDepend(['RT_USING_ADC']):
|
|||
if GetDepend(['RT_USING_DAC']):
|
||||
src += ['drv_dac.c']
|
||||
|
||||
if GetDepend(['RT_USING_CAN', 'BSP_USING_CAN']):
|
||||
src += ['drv_can.c']
|
||||
|
||||
if GetDepend(['RT_USING_CAN', 'BSP_USING_MCAN']):
|
||||
src += ['drv_mcan.c']
|
||||
if GetDepend(['RT_USING_CAN']):
|
||||
if GetDepend(['BSP_USING_CAN']):
|
||||
src += ['drv_can.c']
|
||||
if GetDepend(['BSP_USING_MCAN']):
|
||||
src += ['drv_mcan.c']
|
||||
|
||||
if GetDepend(['RT_USING_RTC']):
|
||||
src += ['drv_rtc.c']
|
||||
|
|
|
|||
|
|
@ -28,7 +28,7 @@
|
|||
#define TSEG1_MAX_FOR_CAN2_0 (65U)
|
||||
#define TSEG2_MIN_FOR_CAN2_0 (1U)
|
||||
#define TSEG2_MAX_FOR_CAN2_0 (8U)
|
||||
#if defined(HC32F4A0) || defined(HC32F472)
|
||||
#if defined(HC32F4A0) || defined(HC32F472) || defined(HC32F4A8)
|
||||
#define TSJW_MIN_FOR_CAN2_0 (1U)
|
||||
#define TSJW_MAX_FOR_CAN2_0 (16U)
|
||||
#elif defined(HC32F460)
|
||||
|
|
@ -78,6 +78,9 @@
|
|||
baud == (CANFD_DATA_BAUD_4M) || \
|
||||
baud == (CANFD_DATA_BAUD_5M) || \
|
||||
baud == (CANFD_DATA_BAUD_8M))
|
||||
#define IS_CAN_FRAME(frame) ((frame) == CAN_FRAME_CLASSIC || \
|
||||
(frame) == CAN_FRAME_ISO_FD || \
|
||||
(frame) == CAN_FRAME_NON_ISO_FD)
|
||||
|
||||
#define CAN_BIT_TIMING_CANFD_ARBITRATION (1U << 1)
|
||||
#define CAN_BIT_TIMING_CANFD_DATA (1U << 2)
|
||||
|
|
@ -85,7 +88,7 @@
|
|||
#endif
|
||||
|
||||
#define NUM_PRESCALE_MAX (256U)
|
||||
#if defined(HC32F4A0)
|
||||
#if defined(HC32F4A0) || defined(HC32F4A8)
|
||||
#define CAN_FILTER_COUNT (16U)
|
||||
#define CAN1_INT_SRC (INT_SRC_CAN1_HOST)
|
||||
#define CAN2_INT_SRC (INT_SRC_CAN2_HOST)
|
||||
|
|
@ -206,24 +209,24 @@ static const struct canfd_baud_rate_tab _g_baudrate_fd[] =
|
|||
{
|
||||
{CAN_CLOCK_SRC_20M, CAN_BIT_TIMING_CANFD_ARBITRATION, CANFD_ARBITRATION_BAUD_250K, 1U, 64U, 16U, 16U},
|
||||
{CAN_CLOCK_SRC_20M, CAN_BIT_TIMING_CANFD_ARBITRATION, CANFD_ARBITRATION_BAUD_500K, 1U, 32U, 8U, 8U},
|
||||
{CAN_CLOCK_SRC_20M, CAN_BIT_TIMING_CANFD_ARBITRATION | CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_1M, 1U, 16U, 4U, 4U},
|
||||
{CAN_CLOCK_SRC_20M, CAN_BIT_TIMING_CANFD_ARBITRATION | CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_2M, 1U, 8U, 2U, 2U},
|
||||
{CAN_CLOCK_SRC_20M, CAN_BIT_TIMING_CANFD_ARBITRATION | CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_4M, 1U, 4U, 1U, 1U},
|
||||
{CAN_CLOCK_SRC_20M, CAN_BIT_TIMING_CANFD_ARBITRATION | CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_5M, 1U, 3U, 1U, 1U},
|
||||
{CAN_CLOCK_SRC_20M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_1M, 1U, 16U, 4U, 4U},
|
||||
{CAN_CLOCK_SRC_20M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_2M, 1U, 8U, 2U, 2U},
|
||||
{CAN_CLOCK_SRC_20M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_4M, 1U, 4U, 1U, 1U},
|
||||
{CAN_CLOCK_SRC_20M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_5M, 1U, 3U, 1U, 1U},
|
||||
{CAN_CLOCK_SRC_40M, CAN_BIT_TIMING_CANFD_ARBITRATION, CANFD_ARBITRATION_BAUD_250K, 2U, 64U, 16U, 16U},
|
||||
{CAN_CLOCK_SRC_40M, CAN_BIT_TIMING_CANFD_ARBITRATION, CANFD_ARBITRATION_BAUD_500K, 1U, 64U, 16U, 16U},
|
||||
{CAN_CLOCK_SRC_40M, CAN_BIT_TIMING_CANFD_ARBITRATION, CANFD_DATA_BAUD_1M, 1U, 32U, 8U, 8U},
|
||||
{CAN_CLOCK_SRC_40M, CAN_BIT_TIMING_CANFD_ARBITRATION | CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_2M, 1U, 16U, 4U, 4U},
|
||||
{CAN_CLOCK_SRC_40M, CAN_BIT_TIMING_CANFD_ARBITRATION | CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_4M, 1U, 8U, 2U, 2U},
|
||||
{CAN_CLOCK_SRC_40M, CAN_BIT_TIMING_CANFD_ARBITRATION | CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_5M, 1U, 6U, 2U, 2U},
|
||||
{CAN_CLOCK_SRC_40M, CAN_BIT_TIMING_CANFD_ARBITRATION | CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_8M, 1U, 4U, 1U, 1U},
|
||||
{CAN_CLOCK_SRC_40M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_1M, 2U, 16U, 4U, 4U},
|
||||
{CAN_CLOCK_SRC_40M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_2M, 1U, 16U, 4U, 4U},
|
||||
{CAN_CLOCK_SRC_40M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_4M, 1U, 8U, 2U, 2U},
|
||||
{CAN_CLOCK_SRC_40M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_5M, 1U, 6U, 2U, 2U},
|
||||
{CAN_CLOCK_SRC_40M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_8M, 1U, 4U, 1U, 1U},
|
||||
{CAN_CLOCK_SRC_80M, CAN_BIT_TIMING_CANFD_ARBITRATION, CANFD_ARBITRATION_BAUD_250K, 4U, 64U, 16U},
|
||||
{CAN_CLOCK_SRC_80M, CAN_BIT_TIMING_CANFD_ARBITRATION, CANFD_ARBITRATION_BAUD_500K, 2U, 64U, 16U},
|
||||
{CAN_CLOCK_SRC_80M, CAN_BIT_TIMING_CANFD_ARBITRATION, CANFD_DATA_BAUD_1M, 2U, 32U, 8U, 8U},
|
||||
{CAN_CLOCK_SRC_80M, CAN_BIT_TIMING_CANFD_ARBITRATION | CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_2M, 2U, 16U, 4U, 4U},
|
||||
{CAN_CLOCK_SRC_80M, CAN_BIT_TIMING_CANFD_ARBITRATION | CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_4M, 1U, 16U, 4U, 4U},
|
||||
{CAN_CLOCK_SRC_80M, CAN_BIT_TIMING_CANFD_ARBITRATION | CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_5M, 1U, 12U, 4U, 4U},
|
||||
{CAN_CLOCK_SRC_80M, CAN_BIT_TIMING_CANFD_ARBITRATION | CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_8M, 1U, 8U, 2U, 2U},
|
||||
{CAN_CLOCK_SRC_80M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_1M, 4U, 16U, 4U, 4U},
|
||||
{CAN_CLOCK_SRC_80M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_2M, 2U, 16U, 4U, 4U},
|
||||
{CAN_CLOCK_SRC_80M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_4M, 1U, 16U, 4U, 4U},
|
||||
{CAN_CLOCK_SRC_80M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_5M, 1U, 12U, 4U, 4U},
|
||||
{CAN_CLOCK_SRC_80M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_8M, 1U, 8U, 2U, 2U},
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -233,7 +236,7 @@ static can_device _g_can_dev_array[] =
|
|||
{
|
||||
{0},
|
||||
CAN1_INIT_PARAMS,
|
||||
#if defined(HC32F4A0) || defined(HC32F472)
|
||||
#if defined(HC32F4A0) || defined(HC32F472) || defined(HC32F4A8)
|
||||
.instance = CM_CAN1,
|
||||
#elif defined (HC32F460)
|
||||
.instance = CM_CAN,
|
||||
|
|
@ -741,26 +744,6 @@ static void _init_ll_struct_canfd(can_device *p_can_dev)
|
|||
}
|
||||
RT_ASSERT((p_can_dev->ll_init.pstcCanFd != RT_NULL));
|
||||
CAN_FD_StructInit(p_can_dev->ll_init.pstcCanFd);
|
||||
switch ((rt_uint32_t)p_can_dev->instance)
|
||||
{
|
||||
#ifdef BSP_USING_CAN1
|
||||
case (rt_uint32_t)CM_CAN1:
|
||||
p_can_dev->ll_init.pstcCanFd->u8Mode = CAN1_CANFD_MODE;
|
||||
break;
|
||||
#endif
|
||||
#ifdef BSP_USING_CAN2
|
||||
case (rt_uint32_t)CM_CAN2:
|
||||
p_can_dev->ll_init.pstcCanFd->u8Mode = CAN2_CANFD_MODE;
|
||||
break;
|
||||
#endif
|
||||
#ifdef BSP_USING_CAN3
|
||||
case (rt_uint32_t)CM_CAN3:
|
||||
p_can_dev->ll_init.pstcCanFd->u8Mode = CAN3_CANFD_MODE;
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static rt_err_t _config_can_bit_timing(can_device *p_can_dev, void *arg)
|
||||
|
|
@ -814,11 +797,23 @@ static rt_err_t _canfd_control(can_device *p_can_dev, int cmd, void *arg)
|
|||
p_can_dev->rt_can.config.baud_rate = argval;
|
||||
break;
|
||||
case RT_CAN_CMD_SET_CANFD:
|
||||
argval = (rt_uint32_t) arg;
|
||||
if (p_can_dev->rt_can.config.enable_canfd == argval)
|
||||
{
|
||||
break;
|
||||
}
|
||||
p_can_dev->rt_can.config.enable_canfd = (rt_uint32_t) argval;
|
||||
|
||||
RT_ASSERT(IS_CAN_FRAME(argval));
|
||||
if (argval != CAN_FRAME_CLASSIC)
|
||||
{
|
||||
p_can_dev->ll_init.pstcCanFd->u8Mode = (argval == CAN_FRAME_ISO_FD) ? CAN_FD_MD_ISO : CAN_FD_MD_BOSCH;
|
||||
}
|
||||
CAN_Init(p_can_dev->instance, &p_can_dev->ll_init);
|
||||
p_can_dev->rt_can.config.enable_canfd = argval;
|
||||
argval = (argval > CAN_FRAME_CLASSIC) ? ENABLE : DISABLE;
|
||||
#if defined(HC32F472) || defined(HC32F4A8)
|
||||
CAN_FD_Cmd(p_can_dev->instance, (en_functional_state_t)argval);
|
||||
#endif
|
||||
break;
|
||||
case RT_CAN_CMD_SET_BAUD_FD:
|
||||
argval = (rt_uint32_t) arg;
|
||||
|
|
@ -1271,7 +1266,7 @@ void CAN3_Handler(void)
|
|||
static void _enable_can_clock(void)
|
||||
{
|
||||
#if defined(BSP_USING_CAN1)
|
||||
#if defined(HC32F4A0) || defined(HC32F472)
|
||||
#if defined(HC32F4A0) || defined(HC32F472) || defined(HC32F4A8)
|
||||
FCG_Fcg1PeriphClockCmd(FCG1_PERIPH_CAN1, ENABLE);
|
||||
#elif defined(HC32F460)
|
||||
FCG_Fcg1PeriphClockCmd(FCG1_PERIPH_CAN, ENABLE);
|
||||
|
|
@ -1332,7 +1327,7 @@ static void _init_ll_struct_filter(can_device *p_can_dev)
|
|||
p_can_dev->ll_init.u16FilterSelect = CAN_FILTER1;
|
||||
}
|
||||
|
||||
static void _init_struct_by_static_cfg(can_device *p_can_dev)
|
||||
static void _init_default_cfg(can_device *p_can_dev)
|
||||
{
|
||||
struct can_configure rt_can_config = CANDEFAULTCONFIG;
|
||||
|
||||
|
|
@ -1347,16 +1342,15 @@ static void _init_struct_by_static_cfg(can_device *p_can_dev)
|
|||
rt_can_config.sndboxnumber = 1;
|
||||
p_can_dev->rt_can.config = rt_can_config;
|
||||
|
||||
CAN_StructInit(&p_can_dev->ll_init);
|
||||
if (p_can_dev->init.single_trans_mode)
|
||||
{
|
||||
p_can_dev->ll_init.u8PTBSingleShotTx = CAN_PTB_SINGLESHOT_TX_ENABLE;
|
||||
}
|
||||
|
||||
#ifdef RT_CAN_USING_CANFD
|
||||
_init_ll_struct_canfd(p_can_dev);
|
||||
#endif
|
||||
_init_ll_struct_filter(p_can_dev);
|
||||
|
||||
}
|
||||
|
||||
extern rt_err_t rt_hw_board_can_init(CM_CAN_TypeDef *CANx);
|
||||
|
|
@ -1370,8 +1364,7 @@ int rt_hw_can_init(void)
|
|||
uint32_t i = 0;
|
||||
for (; i < CAN_INDEX_MAX; i++)
|
||||
{
|
||||
CAN_StructInit(&_g_can_dev_array[i].ll_init);
|
||||
_init_struct_by_static_cfg(&_g_can_dev_array[i]);
|
||||
_init_default_cfg(&_g_can_dev_array[i]);
|
||||
|
||||
/* register CAN device */
|
||||
rt_hw_board_can_init(_g_can_dev_array[i].instance);
|
||||
|
|
|
|||
|
|
@ -42,6 +42,10 @@ extern "C" {
|
|||
#define CANFD_DATA_BAUD_5M (5*1000*1000UL)
|
||||
#define CANFD_DATA_BAUD_8M (8*1000*1000UL)
|
||||
|
||||
#define CAN_FRAME_CLASSIC (0x0U)
|
||||
#define CAN_FRAME_ISO_FD (0x2U)
|
||||
#define CAN_FRAME_NON_ISO_FD (0x4U)
|
||||
|
||||
/* hc32 can device */
|
||||
struct can_dev_init_params
|
||||
{
|
||||
|
|
|
|||
|
|
@ -358,9 +358,7 @@ static void hc32_eth_irq_handle(stc_eth_handle_t *eth_handle)
|
|||
result = eth_device_ready(&(hc32_eth_device.parent));
|
||||
if (result != RT_EOK)
|
||||
{
|
||||
#if defined (RT_USING_ULOG) || defined (ULOG_USING_ISR_LOG)
|
||||
LOG_I("eth rx complete callback err = %d", result);
|
||||
#endif
|
||||
}
|
||||
/* Clear the Eth DMA Rx IT pending bits */
|
||||
ETH_DMA_ClearStatus(ETH_DMA_FLAG_RIS | ETH_DMA_FLAG_NIS);
|
||||
|
|
@ -467,9 +465,7 @@ static void eth_phy_irq_handler(void *args)
|
|||
rt_uint16_t status = 0;
|
||||
|
||||
ETH_PHY_ReadReg(&EthHandle, PHY_IISDR, &status);
|
||||
#if defined (RT_USING_ULOG) || defined (ULOG_USING_ISR_LOG)
|
||||
LOG_D("phy interrupt status reg is 0x%X", status);
|
||||
#endif
|
||||
#endif
|
||||
hc32_phy_link_change();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -76,11 +76,11 @@ int hc32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size)
|
|||
*/
|
||||
int hc32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
|
||||
{
|
||||
uint8_t u8MemBuf[4] = {0xFF, 0xFF, 0xFF, 0xFF};
|
||||
uint8_t u8MemBuf[HC32_FLASH_WRITE_GRANULARITY];
|
||||
rt_err_t result = RT_EOK;
|
||||
rt_uint32_t newAddr = addr, offsetVal = 0;
|
||||
rt_uint32_t index = 0, u32Cnt = 0;
|
||||
#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F448)
|
||||
#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F448) || defined (HC32F4A8)
|
||||
rt_uint32_t FirstSector = 0, NumOfSectors = 0;
|
||||
#endif
|
||||
|
||||
|
|
@ -94,9 +94,13 @@ int hc32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
|
|||
return -RT_EINVAL;
|
||||
}
|
||||
|
||||
for (u32Cnt = 0; u32Cnt < HC32_FLASH_WRITE_GRANULARITY; u32Cnt++)
|
||||
{
|
||||
u8MemBuf[u32Cnt] = 0xFF;
|
||||
}
|
||||
/* EFM_FWMC write enable */
|
||||
EFM_FWMC_Cmd(ENABLE);
|
||||
#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F448)
|
||||
#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F448) || defined (HC32F4A8)
|
||||
/* calculate sector information */
|
||||
FirstSector = addr / EFM_SECTOR_SIZE,
|
||||
NumOfSectors = GetSectorNum(addr, size);
|
||||
|
|
@ -104,22 +108,22 @@ int hc32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
|
|||
EFM_SequenceSectorOperateCmd(FirstSector, NumOfSectors, ENABLE);
|
||||
#endif
|
||||
/* Word align */
|
||||
if (0U != (addr % 4))
|
||||
if (0U != (addr % HC32_FLASH_WRITE_GRANULARITY))
|
||||
{
|
||||
newAddr = (addr / 4 + 1U) * 4;
|
||||
newAddr = (addr / HC32_FLASH_WRITE_GRANULARITY + 1U) * HC32_FLASH_WRITE_GRANULARITY;
|
||||
offsetVal = newAddr - addr;
|
||||
if (offsetVal >= size)
|
||||
{
|
||||
result = -RT_ERROR;
|
||||
index = 4 - offsetVal;
|
||||
if (LL_OK == EFM_ReadByte(newAddr - 4, u8MemBuf, index))
|
||||
index = HC32_FLASH_WRITE_GRANULARITY - offsetVal;
|
||||
if (LL_OK == EFM_ReadByte(newAddr - HC32_FLASH_WRITE_GRANULARITY, u8MemBuf, index))
|
||||
{
|
||||
for (u32Cnt = 0; u32Cnt < size; u32Cnt++)
|
||||
{
|
||||
u8MemBuf[index + u32Cnt] = buf[u32Cnt];
|
||||
}
|
||||
/* program */
|
||||
if (LL_OK == EFM_Program(newAddr - 4, u8MemBuf, 4))
|
||||
if (LL_OK == EFM_Program(newAddr - HC32_FLASH_WRITE_GRANULARITY, u8MemBuf, HC32_FLASH_WRITE_GRANULARITY))
|
||||
{
|
||||
result = RT_EOK;
|
||||
}
|
||||
|
|
@ -139,7 +143,7 @@ int hc32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
|
|||
}
|
||||
|
||||
__exit:
|
||||
#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F448)
|
||||
#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F448) || defined (HC32F4A8)
|
||||
/* Sectors enable write protection */
|
||||
EFM_SequenceSectorOperateCmd(FirstSector, NumOfSectors, DISABLE);
|
||||
#endif
|
||||
|
|
@ -165,7 +169,7 @@ int hc32_flash_erase(rt_uint32_t addr, size_t size)
|
|||
rt_err_t result = RT_EOK;
|
||||
rt_uint32_t NumOfSectors = 0;
|
||||
rt_uint32_t SectorVal = 0, u32Addr = addr;
|
||||
#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F448)
|
||||
#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F448) || defined (HC32F4A8)
|
||||
rt_uint32_t FirstSector = 0;
|
||||
#endif
|
||||
|
||||
|
|
@ -183,7 +187,7 @@ int hc32_flash_erase(rt_uint32_t addr, size_t size)
|
|||
EFM_FWMC_Cmd(ENABLE);
|
||||
/* calculate sector information */
|
||||
NumOfSectors = GetSectorNum(addr, size);
|
||||
#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F448)
|
||||
#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F448) || defined (HC32F4A8)
|
||||
FirstSector = addr / EFM_SECTOR_SIZE,
|
||||
/* Sectors disable write protection */
|
||||
EFM_SequenceSectorOperateCmd(FirstSector, NumOfSectors, ENABLE);
|
||||
|
|
@ -198,7 +202,7 @@ int hc32_flash_erase(rt_uint32_t addr, size_t size)
|
|||
}
|
||||
u32Addr += EFM_SECTOR_SIZE;
|
||||
}
|
||||
#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F448)
|
||||
#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F448) || defined (HC32F4A8)
|
||||
/* Sectors enable write protection */
|
||||
EFM_SequenceSectorOperateCmd(FirstSector, NumOfSectors, DISABLE);
|
||||
#endif
|
||||
|
|
@ -223,9 +227,9 @@ const struct fal_flash_dev hc32_onchip_flash =
|
|||
.name = "onchip_flash",
|
||||
.addr = HC32_FLASH_START_ADDRESS,
|
||||
.len = HC32_FLASH_SIZE,
|
||||
.blk_size = HC32_FLASH_SIZE_GRANULARITY,
|
||||
.blk_size = HC32_FLASH_ERASE_GRANULARITY,
|
||||
.ops = {NULL, fal_flash_read, fal_flash_write, fal_flash_erase},
|
||||
.write_gran = 4
|
||||
.write_gran = HC32_FLASH_WRITE_GRANULARITY
|
||||
};
|
||||
|
||||
static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size)
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@
|
|||
#define GPIO_PORT(pin) ((uint8_t)(((pin) >> 4) & 0x0F))
|
||||
#define GPIO_PIN(pin) ((uint16_t)(0x01U << GPIO_PIN_INDEX(pin)))
|
||||
|
||||
#if defined (HC32F4A0)
|
||||
#if defined (HC32F4A0) || defined (HC32F4A8)
|
||||
#define PIN_MAX_NUM ((GPIO_PORT_I * 16) + (__CLZ(__RBIT(GPIO_PIN_13))) + 1)
|
||||
#elif defined (HC32F460)
|
||||
#define PIN_MAX_NUM ((GPIO_PORT_H * 16) + (__CLZ(__RBIT(GPIO_PIN_02))) + 1)
|
||||
|
|
|
|||
|
|
@ -67,7 +67,7 @@ rt_err_t hc32_install_irq_handler(struct hc32_irq_config *irq_config,
|
|||
stcIrqSignConfig.pfnCallback = irq_hdr;
|
||||
if (LL_OK == INTC_IrqSignIn(&stcIrqSignConfig))
|
||||
nvic_config:
|
||||
#elif defined (HC32F460) || defined (HC32F4A0)
|
||||
#elif defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8)
|
||||
stcIrqSignConfig.enIRQn = irq_config->irq_num;
|
||||
stcIrqSignConfig.enIntSrc = irq_config->int_src;
|
||||
stcIrqSignConfig.pfnCallback = irq_hdr;
|
||||
|
|
|
|||
|
|
@ -47,10 +47,6 @@ struct hc32_irq_config
|
|||
rt_err_t hc32_install_irq_handler(struct hc32_irq_config *irq_config,
|
||||
void (*irq_hdr)(void),
|
||||
rt_bool_t irq_enable);
|
||||
#if defined (HC32F448) || defined (HC32F472)
|
||||
rt_err_t hc32_install_independ_irq_handler(struct hc32_irq_config *irq_config,
|
||||
rt_bool_t irq_enable);
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
|
|
|||
|
|
@ -28,6 +28,10 @@ typedef struct hc32_mcan_config_struct
|
|||
struct hc32_irq_config int0_cfg; /* MCAN interrupt line 0 configuration */
|
||||
uint32_t int1_sel;
|
||||
struct hc32_irq_config int1_cfg; /* MCAN interrupt line 1 configuration */
|
||||
#if defined(HC32F4A8)
|
||||
func_ptr_t irq_callback0;
|
||||
func_ptr_t irq_callback1;
|
||||
#endif
|
||||
} hc32_mcan_config_t;
|
||||
|
||||
typedef struct hc32_mcan_driver_struct
|
||||
|
|
@ -55,19 +59,21 @@ typedef struct mcan_baud_rate_struct
|
|||
#define IS_MCAN_CC_BAUD_RATE(baud) ((baud) == (CAN10kBaud) || \
|
||||
(baud) == (CAN20kBaud) || \
|
||||
(baud) == (CAN50kBaud) || \
|
||||
(baud) == (CAN100kBaud) || \
|
||||
(baud) == (CAN125kBaud) || \
|
||||
(baud) == (CAN250kBaud) || \
|
||||
(baud) == (CAN500kBaud) || \
|
||||
(baud) == (CAN800kBaud) || \
|
||||
(baud) == (CAN1MBaud))
|
||||
|
||||
#define IS_MCAN_NOMINAL_BAUD_RATE(baud) ((baud) == (CAN500kBaud) || \
|
||||
(baud) == (CAN1MBaud))
|
||||
|
||||
#define IS_MCAN_DATA_BAUD_RATE(baud) ((baud) == (MCANFD_DATA_BAUD_1M) || \
|
||||
(baud) == (MCANFD_DATA_BAUD_2M) || \
|
||||
(baud) == (MCANFD_DATA_BAUD_4M) || \
|
||||
(baud) == (MCANFD_DATA_BAUD_5M) || \
|
||||
(baud) == (MCANFD_DATA_BAUD_8M))
|
||||
#define IS_MCAN_DATA_BAUD_RATE(baud) ((baud) == (CANFD_DATA_BAUD_1M) || \
|
||||
(baud) == (CANFD_DATA_BAUD_2M) || \
|
||||
(baud) == (CANFD_DATA_BAUD_4M) || \
|
||||
(baud) == (CANFD_DATA_BAUD_5M) || \
|
||||
(baud) == (CANFD_DATA_BAUD_8M))
|
||||
|
||||
#define IS_CAN_VALID_ID(ide, id) ((((ide) == 0) && ((id) <= MCAN_STD_ID_MASK)) || \
|
||||
(((ide) == 1) && ((id) <= MCAN_EXT_ID_MASK)))
|
||||
|
|
@ -79,7 +85,7 @@ typedef struct mcan_baud_rate_struct
|
|||
#define MCAN_TX_INT (MCAN_INT_TX_CPLT)
|
||||
#define MCAN_ERR_INT (MCAN_INT_ARB_PHASE_ERROR | MCAN_INT_DATA_PHASE_ERROR | MCAN_INT_ERR_LOG_OVF | \
|
||||
MCAN_INT_ERR_PASSIVE | MCAN_INT_ERR_WARNING | MCAN_INT_BUS_OFF)
|
||||
#define MCAN_INT0_SEL MCAN_RX_INT
|
||||
#define MCAN_INT0_SEL (MCAN_RX_INT)
|
||||
#define MCAN_INT1_SEL (MCAN_TX_INT | MCAN_ERR_INT)
|
||||
|
||||
/****************************************************************************************
|
||||
|
|
@ -88,19 +94,18 @@ typedef struct mcan_baud_rate_struct
|
|||
#ifdef RT_CAN_USING_CANFD
|
||||
static const mcan_baud_rate_t m_mcan_fd_baud_rate[] =
|
||||
{
|
||||
{CAN500kBaud, MCANFD_DATA_BAUD_1M, MCAN_FD_CFG_500K_1M},
|
||||
{CAN500kBaud, MCANFD_DATA_BAUD_2M, MCAN_FD_CFG_500K_2M},
|
||||
{CAN500kBaud, MCANFD_DATA_BAUD_4M, MCAN_FD_CFG_500K_4M},
|
||||
{CAN500kBaud, MCANFD_DATA_BAUD_5M, MCAN_FD_CFG_500K_5M},
|
||||
{CAN500kBaud, MCANFD_DATA_BAUD_8M, MCAN_FD_CFG_500K_8M},
|
||||
{CAN1MBaud, MCANFD_DATA_BAUD_1M, MCAN_FD_CFG_1M_1M},
|
||||
{CAN1MBaud, MCANFD_DATA_BAUD_2M, MCAN_FD_CFG_1M_2M},
|
||||
{CAN1MBaud, MCANFD_DATA_BAUD_4M, MCAN_FD_CFG_1M_4M},
|
||||
{CAN1MBaud, MCANFD_DATA_BAUD_5M, MCAN_FD_CFG_1M_5M},
|
||||
{CAN1MBaud, MCANFD_DATA_BAUD_8M, MCAN_FD_CFG_1M_8M},
|
||||
{CAN500kBaud, CANFD_DATA_BAUD_1M, MCAN_FD_CFG_500K_1M},
|
||||
{CAN500kBaud, CANFD_DATA_BAUD_2M, MCAN_FD_CFG_500K_2M},
|
||||
{CAN500kBaud, CANFD_DATA_BAUD_4M, MCAN_FD_CFG_500K_4M},
|
||||
{CAN500kBaud, CANFD_DATA_BAUD_5M, MCAN_FD_CFG_500K_5M},
|
||||
{CAN500kBaud, CANFD_DATA_BAUD_8M, MCAN_FD_CFG_500K_8M},
|
||||
{CAN1MBaud, CANFD_DATA_BAUD_1M, MCAN_FD_CFG_1M_1M},
|
||||
{CAN1MBaud, CANFD_DATA_BAUD_2M, MCAN_FD_CFG_1M_2M},
|
||||
{CAN1MBaud, CANFD_DATA_BAUD_4M, MCAN_FD_CFG_1M_4M},
|
||||
{CAN1MBaud, CANFD_DATA_BAUD_5M, MCAN_FD_CFG_1M_5M},
|
||||
{CAN1MBaud, CANFD_DATA_BAUD_8M, MCAN_FD_CFG_1M_8M},
|
||||
};
|
||||
#endif
|
||||
|
||||
#else
|
||||
static const mcan_baud_rate_t m_mcan_cc_baud_rate[] =
|
||||
{
|
||||
{CAN1MBaud, 0, MCAN_CC_CFG_1M},
|
||||
|
|
@ -113,6 +118,7 @@ static const mcan_baud_rate_t m_mcan_cc_baud_rate[] =
|
|||
{CAN20kBaud, 0, MCAN_CC_CFG_20K},
|
||||
{CAN10kBaud, 0, MCAN_CC_CFG_10K},
|
||||
};
|
||||
#endif
|
||||
|
||||
/****************************************************************************************
|
||||
* Constants
|
||||
|
|
@ -152,9 +158,9 @@ static hc32_mcan_driver_t m_mcan_driver_list[] =
|
|||
.instance = CM_MCAN1,
|
||||
.init_para = {.stcBitTime = MCAN1_BAUD_RATE_CFG},
|
||||
.int0_sel = MCAN_INT0_SEL,
|
||||
.int0_cfg = {MCAN1_INT0_IRQn, BSP_MCAN1_INT0_IRQ_PRIO, INT_SRC_MCAN1_INT0},
|
||||
.int0_cfg = {BSP_MCAN1_INT0_IRQ_NUM, BSP_MCAN1_INT0_IRQ_PRIO, INT_SRC_MCAN1_INT0},
|
||||
.int1_sel = MCAN_INT1_SEL,
|
||||
.int1_cfg = {MCAN1_INT1_IRQn, BSP_MCAN1_INT0_IRQ_PRIO, INT_SRC_MCAN1_INT1},
|
||||
.int1_cfg = {BSP_MCAN1_INT1_IRQ_NUM, BSP_MCAN1_INT0_IRQ_PRIO, INT_SRC_MCAN1_INT1},
|
||||
}
|
||||
},
|
||||
#endif
|
||||
|
|
@ -165,9 +171,9 @@ static hc32_mcan_driver_t m_mcan_driver_list[] =
|
|||
.instance = CM_MCAN2,
|
||||
.init_para = {.stcBitTime = MCAN2_BAUD_RATE_CFG},
|
||||
.int0_sel = MCAN_INT0_SEL,
|
||||
.int0_cfg = {MCAN2_INT0_IRQn, BSP_MCAN2_INT0_IRQ_PRIO, INT_SRC_MCAN2_INT0},
|
||||
.int0_cfg = {BSP_MCAN2_INT0_IRQ_NUM, BSP_MCAN2_INT0_IRQ_PRIO, INT_SRC_MCAN2_INT0},
|
||||
.int1_sel = MCAN_INT1_SEL,
|
||||
.int1_cfg = {MCAN2_INT1_IRQn, BSP_MCAN2_INT1_IRQ_PRIO, INT_SRC_MCAN2_INT1},
|
||||
.int1_cfg = {BSP_MCAN2_INT1_IRQ_NUM, BSP_MCAN2_INT1_IRQ_PRIO, INT_SRC_MCAN2_INT1},
|
||||
}
|
||||
},
|
||||
#endif
|
||||
|
|
@ -228,6 +234,10 @@ static rt_ssize_t mcan_sendmsg(struct rt_can_device *device, const void *buf, rt
|
|||
*/
|
||||
static rt_ssize_t mcan_recvmsg(struct rt_can_device *device, void *buf, rt_uint32_t boxno);
|
||||
|
||||
#ifdef RT_CAN_USING_CANFD
|
||||
static void mcan_copy_bt_to_cfg(struct can_configure *cfg, const stc_mcan_bit_time_config_t *ll_bt);
|
||||
#endif
|
||||
|
||||
static const struct rt_can_ops m_mcan_ops =
|
||||
{
|
||||
mcan_configure,
|
||||
|
|
@ -268,13 +278,14 @@ static rt_err_t mcan_configure(struct rt_can_device *device, struct can_configur
|
|||
hard->init_para.stcBitTime.u32NominalTimeSeg1 = cfg->can_timing.num_seg1;
|
||||
hard->init_para.stcBitTime.u32NominalTimeSeg2 = cfg->can_timing.num_seg2;
|
||||
hard->init_para.stcBitTime.u32NominalSyncJumpWidth = cfg->can_timing.num_sjw;
|
||||
|
||||
hard->init_para.stcBitTime.u32DataPrescaler = cfg->canfd_timing.prescaler;
|
||||
hard->init_para.stcBitTime.u32DataTimeSeg1 = cfg->canfd_timing.num_seg1;
|
||||
hard->init_para.stcBitTime.u32DataTimeSeg2 = cfg->canfd_timing.num_seg2;
|
||||
hard->init_para.stcBitTime.u32DataSyncJumpWidth = cfg->canfd_timing.num_sjw;
|
||||
hard->init_para.stcBitTime.u32SspOffset = cfg->canfd_timing.num_sspoff;
|
||||
|
||||
if (cfg->use_bit_timing >= 2)
|
||||
{
|
||||
hard->init_para.stcBitTime.u32DataPrescaler = cfg->canfd_timing.prescaler;
|
||||
hard->init_para.stcBitTime.u32DataTimeSeg1 = cfg->canfd_timing.num_seg1;
|
||||
hard->init_para.stcBitTime.u32DataTimeSeg2 = cfg->canfd_timing.num_seg2;
|
||||
hard->init_para.stcBitTime.u32DataSyncJumpWidth = cfg->canfd_timing.num_sjw;
|
||||
hard->init_para.stcBitTime.u32SspOffset = cfg->canfd_timing.num_sspoff;
|
||||
}
|
||||
cfg->use_bit_timing = 0;
|
||||
}
|
||||
else
|
||||
|
|
@ -289,6 +300,7 @@ static rt_err_t mcan_configure(struct rt_can_device *device, struct can_configur
|
|||
(cfg->baud_rate_fd == m_mcan_fd_baud_rate[i].baud_rate_fd))
|
||||
{
|
||||
hard->init_para.stcBitTime = m_mcan_fd_baud_rate[i].ll_bt;
|
||||
mcan_copy_bt_to_cfg(cfg, &m_mcan_fd_baud_rate[i].ll_bt);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
@ -371,6 +383,7 @@ static void mcan_control_set_int(hc32_mcan_driver_t *driver, int cmd, void *arg)
|
|||
en_functional_state_t new_state = DISABLE;
|
||||
rt_uint32_t int_flag = (rt_uint32_t)arg;
|
||||
hc32_mcan_config_t *hard = &driver->mcan;
|
||||
rt_uint32_t tmp;
|
||||
|
||||
if (cmd == RT_DEVICE_CTRL_SET_INT)
|
||||
{
|
||||
|
|
@ -389,7 +402,6 @@ static void mcan_control_set_int(hc32_mcan_driver_t *driver, int cmd, void *arg)
|
|||
}
|
||||
break;
|
||||
case RT_DEVICE_FLAG_INT_TX:
|
||||
rt_uint32_t tmp;
|
||||
tmp = hard->init_para.stcMsgRam.u32TxBufferNum + hard->init_para.stcMsgRam.u32TxFifoQueueNum;
|
||||
if (tmp >= 32)
|
||||
{
|
||||
|
|
@ -427,7 +439,6 @@ static void mcan_control_set_int(hc32_mcan_driver_t *driver, int cmd, void *arg)
|
|||
|
||||
static rt_err_t mcan_control_set_filter(hc32_mcan_driver_t *driver, int cmd, void *arg)
|
||||
{
|
||||
//rt_uint8_t sf_cnt = 0, ef_cnt = 0;
|
||||
rt_uint8_t sf_default_idx = 0, ef_default_idx = 0;
|
||||
stc_mcan_filter_t ll_filter;
|
||||
hc32_mcan_config_t *hard = &driver->mcan;
|
||||
|
|
@ -466,8 +477,7 @@ static rt_err_t mcan_control_set_filter(hc32_mcan_driver_t *driver, int cmd, voi
|
|||
ll_filter.u32FilterIndex = device_filter->items[i].hdr_bank;
|
||||
}
|
||||
RT_ASSERT(ll_filter.u32FilterIndex < hard->init_para.stcMsgRam.u32StdFilterNum);
|
||||
m_mcan1_std_filters[ll_filter.u32FilterIndex] = ll_filter;
|
||||
//sf_cnt++;
|
||||
hard->init_para.stcFilter.pstcStdFilterList[ll_filter.u32FilterIndex] = ll_filter;
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -483,8 +493,7 @@ static rt_err_t mcan_control_set_filter(hc32_mcan_driver_t *driver, int cmd, voi
|
|||
ll_filter.u32FilterIndex = device_filter->items[i].hdr_bank;
|
||||
}
|
||||
RT_ASSERT(ll_filter.u32FilterIndex < hard->init_para.stcMsgRam.u32ExtFilterNum);
|
||||
m_mcan1_ext_filters[ll_filter.u32FilterIndex] = ll_filter;
|
||||
//ef_cnt++;
|
||||
hard->init_para.stcFilter.pstcExtFilterList[ll_filter.u32FilterIndex] = ll_filter;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -503,7 +512,7 @@ static rt_err_t mcan_control_set_mode(hc32_mcan_driver_t *driver, int cmd, void
|
|||
}
|
||||
if (argval == driver->can_device.config.mode)
|
||||
{
|
||||
return -RT_EOK;
|
||||
return RT_EOK;
|
||||
}
|
||||
cfg->mode = argval;
|
||||
return RT_EOK;
|
||||
|
|
@ -512,7 +521,6 @@ static rt_err_t mcan_control_set_mode(hc32_mcan_driver_t *driver, int cmd, void
|
|||
static rt_err_t mcan_control_set_priv(hc32_mcan_driver_t *driver, int cmd, void *arg, struct can_configure *cfg)
|
||||
{
|
||||
rt_uint32_t argval = (rt_uint32_t)arg;
|
||||
//hc32_mcan_config_t *hard = &driver->mcan;
|
||||
|
||||
(void)cmd;
|
||||
RT_ASSERT(IS_RT_CAN_PRIV_MODE(argval));
|
||||
|
|
@ -522,12 +530,13 @@ static rt_err_t mcan_control_set_priv(hc32_mcan_driver_t *driver, int cmd, void
|
|||
}
|
||||
if (argval == driver->can_device.config.privmode)
|
||||
{
|
||||
return -RT_EPERM;
|
||||
return RT_EOK;
|
||||
}
|
||||
cfg->privmode = argval;
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
#ifdef RT_CAN_USING_CANFD
|
||||
static void mcan_copy_bt_to_cfg(struct can_configure *cfg, const stc_mcan_bit_time_config_t *ll_bt)
|
||||
{
|
||||
cfg->can_timing.prescaler = ll_bt->u32NominalPrescaler;
|
||||
|
|
@ -541,13 +550,15 @@ static void mcan_copy_bt_to_cfg(struct can_configure *cfg, const stc_mcan_bit_ti
|
|||
cfg->canfd_timing.num_sjw = ll_bt->u32DataSyncJumpWidth;
|
||||
cfg->canfd_timing.num_sspoff = ll_bt->u32SspOffset;
|
||||
}
|
||||
#endif
|
||||
|
||||
static rt_err_t mcan_control_set_fd(hc32_mcan_driver_t *driver, int cmd, void *arg, struct can_configure *cfg)
|
||||
{
|
||||
rt_uint32_t i, len;
|
||||
rt_uint32_t argval = (rt_uint32_t)arg;
|
||||
//hc32_mcan_config_t *hard = &driver->mcan;
|
||||
|
||||
#ifdef RT_CAN_USING_CANFD
|
||||
struct rt_can_bit_timing_config *timing_configs = NULL;
|
||||
#endif
|
||||
switch (cmd)
|
||||
{
|
||||
#ifdef RT_CAN_USING_CANFD
|
||||
|
|
@ -560,7 +571,7 @@ static rt_err_t mcan_control_set_fd(hc32_mcan_driver_t *driver, int cmd, void *a
|
|||
}
|
||||
if (driver->can_device.config.baud_rate == argval)
|
||||
{
|
||||
return -RT_EPERM;
|
||||
return RT_EOK;
|
||||
}
|
||||
len = sizeof(m_mcan_fd_baud_rate) / sizeof(m_mcan_fd_baud_rate[0]);
|
||||
for (i = 0; i < len; i++)
|
||||
|
|
@ -570,7 +581,7 @@ static rt_err_t mcan_control_set_fd(hc32_mcan_driver_t *driver, int cmd, void *a
|
|||
{
|
||||
cfg->baud_rate = argval;
|
||||
cfg->baud_rate_fd = driver->can_device.config.baud_rate_fd;
|
||||
mcan_copy_bt_to_cfg(cfg, &m_mcan_cc_baud_rate[i].ll_bt);
|
||||
mcan_copy_bt_to_cfg(cfg, &m_mcan_fd_baud_rate[i].ll_bt);
|
||||
return RT_EOK;
|
||||
}
|
||||
}
|
||||
|
|
@ -594,14 +605,14 @@ static rt_err_t mcan_control_set_fd(hc32_mcan_driver_t *driver, int cmd, void *a
|
|||
{
|
||||
cfg->baud_rate_fd = argval;
|
||||
cfg->baud_rate = driver->can_device.config.baud_rate;
|
||||
mcan_copy_bt_to_cfg(cfg, &m_mcan_cc_baud_rate[i].ll_bt);
|
||||
mcan_copy_bt_to_cfg(cfg, &m_mcan_fd_baud_rate[i].ll_bt);
|
||||
return RT_EOK;
|
||||
}
|
||||
}
|
||||
return -RT_ERROR;
|
||||
|
||||
case RT_CAN_CMD_SET_BITTIMING:
|
||||
struct rt_can_bit_timing_config *timing_configs = (struct rt_can_bit_timing_config *)arg;
|
||||
timing_configs = (struct rt_can_bit_timing_config *)arg;
|
||||
RT_ASSERT(timing_configs != RT_NULL);
|
||||
RT_ASSERT(timing_configs->count == 1 || timing_configs->count == 2);
|
||||
if ((timing_configs == NULL) || ((timing_configs->count != 1) && (timing_configs->count != 2)))
|
||||
|
|
@ -624,7 +635,7 @@ static rt_err_t mcan_control_set_fd(hc32_mcan_driver_t *driver, int cmd, void *a
|
|||
}
|
||||
if (argval == driver->can_device.config.enable_canfd)
|
||||
{
|
||||
return -RT_EPERM;
|
||||
return RT_EOK;
|
||||
}
|
||||
cfg->enable_canfd = argval;
|
||||
return RT_EOK;
|
||||
|
|
@ -637,7 +648,7 @@ static rt_err_t mcan_control_set_fd(hc32_mcan_driver_t *driver, int cmd, void *a
|
|||
}
|
||||
if (argval == driver->can_device.config.baud_rate)
|
||||
{
|
||||
return -RT_EPERM;
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
len = sizeof(m_mcan_cc_baud_rate) / sizeof(m_mcan_cc_baud_rate[0]);
|
||||
|
|
@ -654,8 +665,6 @@ static rt_err_t mcan_control_set_fd(hc32_mcan_driver_t *driver, int cmd, void *a
|
|||
return -RT_ERROR;
|
||||
#endif
|
||||
}
|
||||
|
||||
return -RT_ERROR;
|
||||
}
|
||||
|
||||
static void mcan_control_get_status(hc32_mcan_driver_t *driver, int cmd, void *arg)
|
||||
|
|
@ -958,7 +967,7 @@ rt_inline void mcan_isr(hc32_mcan_driver_t *driver)
|
|||
/****************************************************************************************
|
||||
* mcan irq handler
|
||||
****************************************************************************************/
|
||||
#if defined(HC32F448)
|
||||
#if defined(HC32F448) || defined(HC32F4A8)
|
||||
#if defined(BSP_USING_MCAN1)
|
||||
void MCAN1_INT0_Handler(void)
|
||||
{
|
||||
|
|
@ -1006,7 +1015,7 @@ void MCAN2_INT1_Handler(void)
|
|||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* #if defined(BSP_USING_MCAN2) */
|
||||
#endif /* #if defined(HC32F448) IRQ handler */
|
||||
#endif
|
||||
|
||||
/****************************************************************************************
|
||||
* mcan initialization configurations
|
||||
|
|
@ -1031,12 +1040,21 @@ static void mcan_irq_config(hc32_mcan_config_t *hard)
|
|||
NVIC_SetPriority(hard->int1_cfg.irq_num, hard->int1_cfg.irq_prio);
|
||||
NVIC_EnableIRQ(hard->int1_cfg.irq_num);
|
||||
}
|
||||
#endif /* #if defined(HC32F448) mcan_irq_config */
|
||||
#elif defined(HC32F4A8)
|
||||
if (hard->int0_sel != 0)
|
||||
{
|
||||
hc32_install_irq_handler(&hard->int0_cfg, hard->irq_callback0, RT_TRUE);
|
||||
}
|
||||
if (hard->int1_sel != 0)
|
||||
{
|
||||
hc32_install_irq_handler(&hard->int1_cfg, hard->irq_callback1, RT_TRUE);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
static void mcan_enable_periph_clock(void)
|
||||
{
|
||||
#if defined(HC32F448)
|
||||
#if defined(HC32F448) || defined(HC32F4A8)
|
||||
#if defined(BSP_USING_MCAN1)
|
||||
FCG_Fcg1PeriphClockCmd(FCG1_PERIPH_MCAN1, ENABLE);
|
||||
#endif
|
||||
|
|
@ -1056,6 +1074,7 @@ static void mcan_set_init_para(void)
|
|||
{
|
||||
struct rt_can_device *device;
|
||||
stc_mcan_init_t *hard_init;
|
||||
|
||||
#if defined(BSP_USING_MCAN1)
|
||||
device = &m_mcan_driver_list[MCAN1_INDEX].can_device;
|
||||
hard_init = &m_mcan_driver_list[MCAN1_INDEX].mcan.init_para;
|
||||
|
|
@ -1096,8 +1115,8 @@ static void mcan_set_init_para(void)
|
|||
hard_init->stcFilter.pstcExtFilterList = m_mcan1_ext_filters;
|
||||
hard_init->stcFilter.u32StdFilterConfigNum = hard_init->stcMsgRam.u32StdFilterNum;
|
||||
hard_init->stcFilter.u32ExtFilterConfigNum = hard_init->stcMsgRam.u32ExtFilterNum;
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_MCAN2)
|
||||
device = &m_mcan_driver_list[MCAN2_INDEX].can_device;
|
||||
hard_init = &m_mcan_driver_list[MCAN2_INDEX].mcan.init_para;
|
||||
|
|
@ -1151,28 +1170,58 @@ static void init_can_cfg(hc32_mcan_driver_t *driver)
|
|||
can_cfg.maxhdr = MCAN_TOTAL_FILTER_NUM;
|
||||
#endif
|
||||
#ifdef RT_CAN_USING_CANFD
|
||||
can_cfg.baud_rate_fd = MCANFD_DATA_BAUD_4M;
|
||||
can_cfg.enable_canfd = MCAN_FD_ISO_FD_NO_BRS;
|
||||
can_cfg.baud_rate_fd = CANFD_DATA_BAUD_4M;
|
||||
can_cfg.enable_canfd = MCAN_FD_SEL;
|
||||
#endif
|
||||
can_cfg.sndboxnumber = MCAN_TX_FIFO_NUM;
|
||||
driver->can_device.config = can_cfg;
|
||||
}
|
||||
|
||||
extern rt_err_t rt_hw_board_can_init(CM_MCAN_TypeDef *MCANx);
|
||||
#if defined(HC32F4A8)
|
||||
/**
|
||||
* @brief This function gets mcan irq handle.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
static void mcan_get_irq_callback(void)
|
||||
{
|
||||
#ifdef BSP_USING_MCAN1
|
||||
m_mcan_driver_list[MCAN1_INDEX].mcan.irq_callback0 = MCAN1_INT0_Handler;
|
||||
m_mcan_driver_list[MCAN1_INDEX].mcan.irq_callback1 = MCAN1_INT1_Handler;
|
||||
#endif
|
||||
#ifdef BSP_USING_MCAN2
|
||||
m_mcan_driver_list[MCAN2_INDEX].mcan.irq_callback0 = MCAN2_INT0_Handler;
|
||||
m_mcan_driver_list[MCAN2_INDEX].mcan.irq_callback1 = MCAN2_INT1_Handler;
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
extern rt_err_t rt_hw_board_mcan_init(CM_MCAN_TypeDef *MCANx);
|
||||
extern void CanPhyEnable(void);
|
||||
static rt_err_t rt_hw_mcan_init(void)
|
||||
{
|
||||
rt_uint32_t i;
|
||||
rt_uint32_t i, filter;
|
||||
rt_uint32_t tx_boxnum;
|
||||
hc32_mcan_config_t *hard;
|
||||
|
||||
mcan_enable_periph_clock();
|
||||
mcan_set_init_para();
|
||||
|
||||
#if defined(HC32F4A8)
|
||||
mcan_get_irq_callback();
|
||||
#endif
|
||||
for (i = 0; i < MCAN_DEV_CNT; i++)
|
||||
{
|
||||
hard = &m_mcan_driver_list[i].mcan;
|
||||
|
||||
for (filter = 0; filter < hard->init_para.stcMsgRam.u32StdFilterNum; filter++)
|
||||
{
|
||||
hard->init_para.stcFilter.pstcStdFilterList[filter].u32IdType = MCAN_STD_ID;
|
||||
}
|
||||
for (filter = 0; filter < hard->init_para.stcMsgRam.u32ExtFilterNum; filter++)
|
||||
{
|
||||
hard->init_para.stcFilter.pstcExtFilterList[filter].u32IdType = MCAN_EXT_ID;
|
||||
}
|
||||
|
||||
/* MCAN IRQ configuration */
|
||||
mcan_irq_config(hard);
|
||||
|
||||
|
|
@ -1202,15 +1251,13 @@ static rt_err_t rt_hw_mcan_init(void)
|
|||
init_can_cfg(&m_mcan_driver_list[i]);
|
||||
|
||||
/* GPIO initialization */
|
||||
rt_hw_board_can_init(hard->instance);
|
||||
rt_hw_board_mcan_init(hard->instance);
|
||||
|
||||
/* Register CAN device */
|
||||
rt_hw_can_register(&m_mcan_driver_list[i].can_device,
|
||||
hard->name,
|
||||
&m_mcan_ops,
|
||||
&m_mcan_driver_list[i]);
|
||||
|
||||
MCAN_Start(hard->instance);
|
||||
}
|
||||
|
||||
/* Onboard CAN transceiver enable */
|
||||
|
|
|
|||
|
|
@ -15,35 +15,17 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <board.h>
|
||||
#include <rtdevice.h>
|
||||
#include <rtthread.h>
|
||||
#include "drv_can.h"
|
||||
|
||||
/* Attention !!!
|
||||
* If RT_CAN_USING_CANFD is enabled, RT_CAN_CMD_SET_BITTIMING is more recommended
|
||||
* than RT_CAN_CMD_SET_BAUD_FD.
|
||||
* because sample point is not specified by config when using RT_CAN_CMD_SET_BAUD_FD
|
||||
* but in range [MCAN_SAMPLEPOINT_MIN/1000, MCAN_SAMPLEPOINT_MAX/1000]
|
||||
* this may not match with your application
|
||||
*/
|
||||
#define MCAN_SAMPLEPOINT_MIN (700U)
|
||||
#define MCAN_SAMPLEPOINT_MAX (850U)
|
||||
/* The arguments of RT command RT_CAN_CMD_SET_CANFD */
|
||||
#define MCAN_FD_CLASSICAL 0 /* CAN classical */
|
||||
#define MCAN_FD_ISO_FD_NO_BRS 1 /* ISO CAN FD without BRS */
|
||||
#define MCAN_FD_ISO_FD_BRS 2 /* ISO CAN FD with BRS */
|
||||
#define MCAN_FD_NON_ISO_FD_NO_BRS 3 /* non-ISO CAN FD without BRS */
|
||||
#define MCAN_FD_NON_ISO_FD_BRS 4 /* non-ISO CAN FD with BRS */
|
||||
|
||||
#define MCAN_CLOCK_SRC_20M (20*1000*1000UL)
|
||||
#define MCAN_CLOCK_SRC_40M (40*1000*1000UL)
|
||||
#define MCAN_CLOCK_SRC_80M (80*1000*1000UL)
|
||||
|
||||
#define MCANFD_NOMINAL_BAUD_500K (500*1000UL)
|
||||
#define MCANFD_NOMINAL_BAUD_1M (1000*1000UL)
|
||||
|
||||
#define MCANFD_DATA_BAUD_1M (1*1000*1000UL)
|
||||
#define MCANFD_DATA_BAUD_2M (2*1000*1000UL)
|
||||
#define MCANFD_DATA_BAUD_4M (4*1000*1000UL)
|
||||
#define MCANFD_DATA_BAUD_5M (5*1000*1000UL)
|
||||
#define MCANFD_DATA_BAUD_8M (8*1000*1000UL)
|
||||
|
||||
|
||||
int rt_hw_mcan_init(void);
|
||||
#define MCAN_FD_ARG_MIN MCAN_FD_ISO_FD_NO_BRS
|
||||
#define MCAN_FD_ARG_MAX MCAN_FD_NON_ISO_FD_BRS
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
|
|
|||
|
|
@ -266,6 +266,7 @@ static rt_err_t _nand_read_page(struct rt_mtd_nand_device *device,
|
|||
rt_uint32_t spare_len)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
stc_exmc_nfc_column_t stcColumn;
|
||||
struct rthw_nand *hw_nand = (struct rthw_nand *)device;
|
||||
|
||||
RT_ASSERT(device != RT_NULL);
|
||||
|
|
@ -312,8 +313,11 @@ static rt_err_t _nand_read_page(struct rt_mtd_nand_device *device,
|
|||
{
|
||||
RT_ASSERT(spare_len <= device->oob_free);
|
||||
|
||||
if (LL_OK != EXMC_NFC_Read(hw_nand->nfc_bank, page, (rt_uint32_t)device->page_size,
|
||||
(rt_uint32_t *)spare, (spare_len >> 2), DISABLE, NAND_READ_TIMEOUT))
|
||||
stcColumn.u32Bank = hw_nand->nfc_bank;
|
||||
stcColumn.u32Page = page;
|
||||
stcColumn.u32Column = (rt_uint32_t)device->page_size;
|
||||
if (LL_OK != EXMC_NFC_Read(&stcColumn, (rt_uint32_t *)spare,
|
||||
(spare_len >> 2), DISABLE, NAND_READ_TIMEOUT))
|
||||
{
|
||||
result = -RT_EIO;
|
||||
goto _exit;
|
||||
|
|
@ -334,6 +338,7 @@ static rt_err_t _nand_write_page(struct rt_mtd_nand_device *device,
|
|||
rt_uint32_t spare_len)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
stc_exmc_nfc_column_t stcColumn;
|
||||
struct rthw_nand *hw_nand = (struct rthw_nand *)device;
|
||||
|
||||
RT_ASSERT(device != RT_NULL);
|
||||
|
|
@ -376,8 +381,11 @@ static rt_err_t _nand_write_page(struct rt_mtd_nand_device *device,
|
|||
{
|
||||
RT_ASSERT(spare_len <= device->oob_free);
|
||||
|
||||
if (LL_OK != EXMC_NFC_Write(hw_nand->nfc_bank, page, (rt_uint32_t)device->page_size,
|
||||
(rt_uint32_t *)spare, (spare_len >> 2), DISABLE, NAND_WRITE_TIMEOUT))
|
||||
stcColumn.u32Bank = hw_nand->nfc_bank;
|
||||
stcColumn.u32Page = page;
|
||||
stcColumn.u32Column = (rt_uint32_t)device->page_size;
|
||||
if (LL_OK != EXMC_NFC_Write(&stcColumn, (rt_uint32_t *)spare,
|
||||
(spare_len >> 2), DISABLE, NAND_WRITE_TIMEOUT))
|
||||
{
|
||||
result = -RT_EIO;
|
||||
goto _exit;
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@
|
|||
* 2024-02-28 CDT support HC32F448
|
||||
* 2024-02-29 CDT Support multi line write/read
|
||||
* 2024-04-18 CDT support HC32F472
|
||||
* 2025-04-14 CDT support HC32F4A8
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
|
|
@ -327,7 +328,7 @@ static int32_t hc32_qspi_send_cmd(struct hc32_qspi_bus *qspi_bus, struct rt_qspi
|
|||
/* Set custom read mode */
|
||||
QSPI_SetReadMode(QSPI_RD_MD_CUSTOM_FAST_RD);
|
||||
#endif
|
||||
#elif defined (HC32F448)
|
||||
#elif defined (HC32F448) || defined (HC32F4A8)
|
||||
if (LL_OK != hc32_qspi_check_direct_comm_param(message, QSPI_DIRECT_COMM_LINE_MULTI))
|
||||
{
|
||||
return LL_ERR_INVD_PARAM;
|
||||
|
|
@ -350,7 +351,7 @@ static void hc32_qspi_word_to_byte(uint32_t u32Word, uint8_t *pu8Byte, uint8_t u
|
|||
while ((u32ByteNum--) != 0UL);
|
||||
}
|
||||
|
||||
#if defined (HC32F448)
|
||||
#if defined (HC32F448) || defined (HC32F4A8)
|
||||
static rt_uint32_t hc32_qspi_get_dcom_protocol_line(rt_uint8_t protocol_line)
|
||||
{
|
||||
rt_uint32_t dcom_protocol_line;
|
||||
|
|
@ -378,7 +379,7 @@ static void hc32_qspi_write_direct_comm_value(rt_uint8_t protocol_line, rt_uint8
|
|||
#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472)
|
||||
(void)protocol_line;
|
||||
QSPI_WriteDirectCommValue(value);
|
||||
#elif defined (HC32F448)
|
||||
#elif defined (HC32F448) || defined (HC32F4A8)
|
||||
QSPI_WriteDirectCommValue(hc32_qspi_get_dcom_protocol_line(protocol_line), value);
|
||||
#endif
|
||||
}
|
||||
|
|
@ -434,7 +435,7 @@ static int32_t hc32_qspi_write_instr(struct hc32_qspi_bus *qspi_bus, struct rt_q
|
|||
/* Enter direct communication mode */
|
||||
SET_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME);
|
||||
#endif
|
||||
#elif defined (HC32F448)
|
||||
#elif defined (HC32F448) || defined (HC32F4A8)
|
||||
/* Enter direct communication mode */
|
||||
SET_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME);
|
||||
#endif
|
||||
|
|
@ -487,7 +488,7 @@ static int32_t hc32_qspi_write_instr(struct hc32_qspi_bus *qspi_bus, struct rt_q
|
|||
DMA_StructInit(&stcDmaInit);
|
||||
#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472)
|
||||
stcDmaInit.u32DataWidth = DMA_DATAWIDTH_8BIT;
|
||||
#elif defined (HC32F448)
|
||||
#elif defined (HC32F448) || defined (HC32F4A8)
|
||||
rt_uint16_t dcom_line = (rt_uint16_t)hc32_qspi_get_dcom_protocol_line(message->qspi_data_lines);
|
||||
stcDmaInit.u32DataWidth = DMA_DATAWIDTH_16BIT;
|
||||
#endif
|
||||
|
|
@ -509,7 +510,7 @@ static int32_t hc32_qspi_write_instr(struct hc32_qspi_bus *qspi_bus, struct rt_q
|
|||
|
||||
#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472)
|
||||
src_addr = (rt_uint32_t)&pu8WriteBuf[u32TxIndex];
|
||||
#elif defined (HC32F448)
|
||||
#elif defined (HC32F448) || defined (HC32F4A8)
|
||||
if (u32DmaTransSize > qspi_bus->config->dma_tx_buf_size)
|
||||
{
|
||||
LOG_E("qspi dma transmit size over buffer size!");
|
||||
|
|
@ -563,7 +564,7 @@ static int32_t hc32_qspi_write_instr(struct hc32_qspi_bus *qspi_bus, struct rt_q
|
|||
/* Exit direct communication mode */
|
||||
CLR_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME);
|
||||
#endif
|
||||
#elif defined (HC32F448)
|
||||
#elif defined (HC32F448) || defined (HC32F4A8)
|
||||
/* Exit direct communication mode */
|
||||
CLR_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME);
|
||||
#endif
|
||||
|
|
@ -584,7 +585,7 @@ static int32_t hc32_qspi_read_instr(struct hc32_qspi_bus *qspi_bus, struct rt_qs
|
|||
uint32_t u32RxIndex = 0U;
|
||||
rt_uint32_t u32TimeoutCnt;
|
||||
#endif
|
||||
#if defined (HC32F448)
|
||||
#if defined (HC32F448) || defined (HC32F4A8)
|
||||
rt_uint32_t u32ReadMd;
|
||||
#endif
|
||||
|
||||
|
|
@ -593,7 +594,7 @@ static int32_t hc32_qspi_read_instr(struct hc32_qspi_bus *qspi_bus, struct rt_qs
|
|||
/* Enter direct communication mode */
|
||||
SET_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME);
|
||||
#endif
|
||||
#elif defined (HC32F448)
|
||||
#elif defined (HC32F448) || defined (HC32F4A8)
|
||||
if ((message->instruction.qspi_lines == 4) || (message->address.qspi_lines == 4) ||
|
||||
(message->qspi_data_lines == 4))
|
||||
{
|
||||
|
|
@ -707,7 +708,7 @@ static int32_t hc32_qspi_read_instr(struct hc32_qspi_bus *qspi_bus, struct rt_qs
|
|||
/* Exit direct communication mode */
|
||||
CLR_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME);
|
||||
#endif
|
||||
#elif defined (HC32F448)
|
||||
#elif defined (HC32F448) || defined (HC32F4A8)
|
||||
if ((message->instruction.qspi_lines == 4) || (message->address.qspi_lines == 4) ||
|
||||
(message->qspi_data_lines == 4))
|
||||
{
|
||||
|
|
@ -1094,7 +1095,7 @@ static void hc32_get_qspi_info(void)
|
|||
#ifdef BSP_QSPI_USING_DMA
|
||||
static struct dma_config qspi_dma = QSPI_DMA_CONFIG;
|
||||
qspi_config.dma_qspi = &qspi_dma;
|
||||
#if defined (HC32F448)
|
||||
#if defined (HC32F448) || defined (HC32F4A8)
|
||||
qspi_config.dma_tx_buf_size = QSPI_DMA_TX_BUFSIZE;
|
||||
qspi_config.dma_tx_buf = rt_malloc(qspi_config.dma_tx_buf_size << 1);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -39,7 +39,7 @@ struct hc32_qspi_config
|
|||
struct hc32_qspi_irq_config err_irq;
|
||||
#ifdef BSP_QSPI_USING_DMA
|
||||
struct dma_config *dma_qspi;
|
||||
#if defined (HC32F448)
|
||||
#if defined (HC32F448) || defined (HC32F4A8)
|
||||
rt_uint16_t *dma_tx_buf;
|
||||
rt_uint16_t dma_tx_buf_size; /* unit: half-word, DMA data width of QSPI transmitting is 16bit */
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -685,7 +685,7 @@ static rt_uint32_t _sdio_clock_get(CM_SDIOC_TypeDef *SDIOCx)
|
|||
rt_uint32_t clk;
|
||||
|
||||
(void)SDIOCx;
|
||||
#if defined (HC32F4A0)
|
||||
#if defined (HC32F4A0) || defined (HC32F4A8)
|
||||
clk = CLK_GetBusClockFreq(CLK_BUS_PCLK1);
|
||||
#elif defined (HC32F460)
|
||||
clk = CLK_GetBusClockFreq(CLK_BUS_EXCLK);
|
||||
|
|
|
|||
|
|
@ -84,9 +84,9 @@ static rt_int32_t _sdram_verify_clock_frequency(void)
|
|||
{
|
||||
rt_int32_t ret = RT_EOK;
|
||||
|
||||
#if defined (HC32F4A0)
|
||||
/* EXCLK max frequency for SDRAM: 40MHz */
|
||||
if (CLK_GetBusClockFreq(CLK_BUS_EXCLK) > (40 * 1000000))
|
||||
#if defined (HC32F4A0) || defined (HC32F4A8)
|
||||
/* EXCLK max frequency for SDRAM */
|
||||
if (CLK_GetBusClockFreq(CLK_BUS_EXCLK) > EXMC_EXCLK_DMC_MAX_FREQ)
|
||||
{
|
||||
ret = -RT_ERROR;
|
||||
}
|
||||
|
|
@ -124,7 +124,9 @@ static rt_int32_t _sdram_init(void)
|
|||
|
||||
/* configure DMC width && refresh period & chip & timing. */
|
||||
(void)EXMC_DMC_StructInit(&stcDmcInit);
|
||||
#if defined (HC32F4A0)
|
||||
stcDmcInit.u32SampleClock = EXMC_DMC_SAMPLE_CLK_EXTCLK;
|
||||
#endif
|
||||
stcDmcInit.u32RefreshPeriod = SDRAM_REFRESH_COUNT;
|
||||
stcDmcInit.u32ColumnBitsNumber = SDRAM_COLUMN_BITS;
|
||||
stcDmcInit.u32RowBitsNumber = SDRAM_ROW_BITS;
|
||||
|
|
|
|||
|
|
@ -27,6 +27,11 @@ extern "C" {
|
|||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
#if defined (HC32F4A0)
|
||||
#define EXMC_EXCLK_DMC_MAX_FREQ (40UL * 1000000UL)
|
||||
#elif defined (HC32F4A8)
|
||||
#define EXMC_EXCLK_DMC_MAX_FREQ (120UL * 1000000UL)
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@
|
|||
* 2023-09-30 CDT Delete dma transmit interrupt
|
||||
* 2024-02-20 CDT support HC32F448
|
||||
* 2024-04-16 CDT support HC32F472
|
||||
* 2025-04-09 CDT support HC32F4A8
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
|
|
@ -32,12 +33,16 @@
|
|||
/*******************************************************************************
|
||||
* Local pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
//#define DRV_DEBUG
|
||||
// #define DRV_DEBUG
|
||||
#define LOG_TAG "drv.spi"
|
||||
#include <drv_log.h>
|
||||
|
||||
/* SPI max division */
|
||||
#define SPI_MAX_DIV_VAL (0x7U) /* Div256 */
|
||||
#if defined(HC32F4A0) || defined(HC32F460)
|
||||
#define SPI_MAX_DIV_VAL (0x7U) /* Div256 */
|
||||
#elif defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8)
|
||||
#define SPI_MAX_DIV_VAL (0x39U)
|
||||
#endif
|
||||
|
||||
#ifdef BSP_SPI_USING_DMA
|
||||
#define DMA_CH_REG(reg_base, ch) (*(__IO uint32_t *)((uint32_t)(&(reg_base)) + ((ch) * 0x40UL)))
|
||||
|
|
@ -205,13 +210,24 @@ static rt_err_t hc32_spi_init(struct hc32_spi *spi_drv, struct rt_spi_configurat
|
|||
break;
|
||||
}
|
||||
}
|
||||
#if defined(HC32F4A0) || defined(HC32F460)
|
||||
stcSpiInit.u32BaudRatePrescaler = (u32Cnt << SPI_CFG2_MBR_POS);
|
||||
#elif defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8)
|
||||
if (u32Cnt <= 15U)
|
||||
{
|
||||
stcSpiInit.u32BaudRatePrescaler = (u32Cnt << SPI_CFG1_CLKDIV_POS);
|
||||
}
|
||||
else
|
||||
{
|
||||
stcSpiInit.u32BaudRatePrescaler = (((7U + ((u32Cnt - 15U) & 0x07U)) << SPI_CFG1_CLKDIV_POS) | ((1U + ((u32Cnt - 15U) >> 3U)) << SPI_CFG2_MBR_POS));
|
||||
}
|
||||
#endif
|
||||
/* slave limit */
|
||||
if ((cfg->mode & RT_SPI_SLAVE) && (stcSpiInit.u32BaudRatePrescaler < SPI_BR_CLK_DIV8))
|
||||
{
|
||||
stcSpiInit.u32BaudRatePrescaler = SPI_BR_CLK_DIV8;
|
||||
}
|
||||
LOG_D("Bus freq: %d, SPI freq: %d, BaudRatePrescaler: %d", u32BusFreq, cfg->max_hz, stcSpiInit.u32BaudRatePrescaler);
|
||||
LOG_D("Bus freq: %d, SPI freq: %d, BaudRatePrescaler: %d, u32Cnt: %d", u32BusFreq, cfg->max_hz, stcSpiInit.u32BaudRatePrescaler, u32Cnt);
|
||||
|
||||
/* spi port init */
|
||||
rt_hw_spi_board_init(spi_instance);
|
||||
|
|
@ -312,7 +328,7 @@ static void hc32_spi_enable(CM_SPI_TypeDef *SPIx)
|
|||
{
|
||||
SPI_Cmd(SPIx, ENABLE);
|
||||
}
|
||||
#elif defined (HC32F448) || defined (HC32F472)
|
||||
#elif defined (HC32F448) || defined (HC32F472) || defined (HC32F4A8)
|
||||
if ((SPIx->CR & SPI_CR_SPE) != SPI_CR_SPE)
|
||||
{
|
||||
SPI_Cmd(SPIx, ENABLE);
|
||||
|
|
@ -333,7 +349,7 @@ static void hc32_spi_set_trans_mode(CM_SPI_TypeDef *SPIx, uint32_t u32Mode)
|
|||
{
|
||||
CLR_REG32_BIT(SPIx->CR1, SPI_CR1_TXMDS);
|
||||
}
|
||||
#elif defined (HC32F448) || defined (HC32F472)
|
||||
#elif defined (HC32F448) || defined (HC32F472) || defined (HC32F4A8)
|
||||
if (SPI_SEND_ONLY == u32Mode)
|
||||
{
|
||||
SET_REG32_BIT(SPIx->CR, SPI_CR_TXMDS);
|
||||
|
|
@ -352,7 +368,7 @@ static uint32_t hc32_spi_get_trans_mode(CM_SPI_TypeDef *SPIx)
|
|||
{
|
||||
#if defined (HC32F460) || defined (HC32F4A0)
|
||||
return READ_REG32_BIT(SPIx->CR1, SPI_CR1_TXMDS);
|
||||
#elif defined (HC32F448) || defined (HC32F472)
|
||||
#elif defined (HC32F448) || defined (HC32F472) || defined (HC32F4A8)
|
||||
return READ_REG32_BIT(SPIx->CR, SPI_CR_TXMDS);
|
||||
#else
|
||||
#error "Please select first the target HC32xxxx device used in your application."
|
||||
|
|
@ -473,6 +489,8 @@ static int32_t hc32_spi_dma_trans(struct hc32_spi_config *spi_config, const uint
|
|||
while ((RESET == DMA_GetTransCompleteStatus(DmaInstance, DmaFlag)) &&
|
||||
(u32TimeoutCnt < spi_config->timeout))
|
||||
{
|
||||
rt_thread_mdelay(1);
|
||||
u32TimeoutCnt++;
|
||||
}
|
||||
if (u32TimeoutCnt >= spi_config->timeout)
|
||||
{
|
||||
|
|
@ -542,7 +560,7 @@ static rt_ssize_t hc32_spi_xfer(struct rt_spi_device *device, struct rt_spi_mess
|
|||
if (message->send_buf && message->recv_buf)
|
||||
{
|
||||
hc32_spi_set_trans_mode(spi_instance, SPI_FULL_DUPLEX);
|
||||
if ((spi_drv->spi_dma_flag & RT_DEVICE_FLAG_DMA_TX) && (spi_drv->spi_dma_flag & RT_DEVICE_FLAG_DMA_RX) && (send_length > 32))
|
||||
if ((spi_drv->spi_dma_flag & RT_DEVICE_FLAG_DMA_TX) && (spi_drv->spi_dma_flag & RT_DEVICE_FLAG_DMA_RX))
|
||||
{
|
||||
state = hc32_spi_dma_trans(spi_drv->config, send_buf, recv_buf, send_length);
|
||||
}
|
||||
|
|
@ -555,7 +573,7 @@ static rt_ssize_t hc32_spi_xfer(struct rt_spi_device *device, struct rt_spi_mess
|
|||
else if (message->send_buf)
|
||||
{
|
||||
hc32_spi_set_trans_mode(spi_instance, SPI_SEND_ONLY);
|
||||
if ((spi_drv->spi_dma_flag & RT_DEVICE_FLAG_DMA_TX) && (send_length > 32))
|
||||
if (spi_drv->spi_dma_flag & RT_DEVICE_FLAG_DMA_TX)
|
||||
{
|
||||
state = hc32_spi_dma_trans(spi_drv->config, send_buf, RT_NULL, send_length);
|
||||
}
|
||||
|
|
@ -599,6 +617,8 @@ static rt_ssize_t hc32_spi_xfer(struct rt_spi_device *device, struct rt_spi_mess
|
|||
while ((RESET == SPI_GetStatus(spi_instance, SPI_FLAG_IDLE)) &&
|
||||
(u32TimeoutCnt < spi_drv->config->timeout))
|
||||
{
|
||||
rt_thread_mdelay(1);
|
||||
u32TimeoutCnt++;
|
||||
}
|
||||
if (u32TimeoutCnt >= spi_drv->config->timeout)
|
||||
{
|
||||
|
|
@ -657,7 +677,7 @@ rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name,
|
|||
|
||||
static void hc32_spi_err_irq_handle(struct hc32_spi *spi)
|
||||
{
|
||||
#if defined (HC32F448) ||defined (HC32F472)
|
||||
#if defined (HC32F448) ||defined (HC32F472) || defined (HC32F4A8)
|
||||
#define SPI_FLAG_OVERLOAD SPI_FLAG_OVERRUN
|
||||
#define SPI_FLAG_UNDERLOAD SPI_FLAG_UNDERRUN
|
||||
#endif
|
||||
|
|
@ -748,6 +768,12 @@ static void hc32_spi4_err_irq_handler(void)
|
|||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* BSP_USING_SPI4 */
|
||||
#if defined (HC32F472)
|
||||
void SPI4_Handler(void)
|
||||
{
|
||||
hc32_spi4_err_irq_handler();
|
||||
}
|
||||
#endif /* HC32F472 */
|
||||
|
||||
#if defined(BSP_USING_SPI5)
|
||||
static void hc32_spi5_err_irq_handler(void)
|
||||
|
|
@ -884,9 +910,9 @@ static int hc32_hw_spi_bus_init(void)
|
|||
spi_bus_obj[i].config = &spi_config[i];
|
||||
spi_bus_obj[i].spi_bus.parent.user_data = &spi_config[i];
|
||||
/* register the handle */
|
||||
#if defined (HC32F460) || defined (HC32F4A0)
|
||||
#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8)
|
||||
hc32_install_irq_handler(&spi_config[i].err_irq.irq_config, spi_config[i].err_irq.irq_callback, RT_FALSE);
|
||||
#elif defined (HC32F488)
|
||||
#elif defined (HC32F448) || defined (HC32F472)
|
||||
INTC_IntSrcCmd(spi_config[i].err_irq.irq_config.int_src, DISABLE);
|
||||
NVIC_DisableIRQ(spi_config[i].err_irq.irq_config.irq_num);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -47,12 +47,17 @@
|
|||
|
||||
#if defined (HC32F460)
|
||||
#define FCG_USART_CLK FCG_Fcg1PeriphClockCmd
|
||||
#elif defined (HC32F4A0) || defined (HC32F448) || defined (HC32F472)
|
||||
#elif defined (HC32F4A0) || defined (HC32F448) || defined (HC32F472) || defined (HC32F4A8)
|
||||
#define FCG_USART_CLK FCG_Fcg3PeriphClockCmd
|
||||
#endif
|
||||
|
||||
#define FCG_TMR0_CLK FCG_Fcg2PeriphClockCmd
|
||||
#define FCG_DMA_CLK FCG_Fcg0PeriphClockCmd
|
||||
#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472)
|
||||
#define USART_MAX_CLK_DIV USART_CLK_DIV64
|
||||
#elif defined (HC32F448) || defined (HC32F4A8)
|
||||
#define USART_MAX_CLK_DIV USART_CLK_DIV1024
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions (declared in header file with 'extern')
|
||||
|
|
@ -219,7 +224,7 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_co
|
|||
{
|
||||
uart_init.u32FirstBit = USART_FIRST_BIT_MSB;
|
||||
}
|
||||
#if defined (HC32F4A0) || defined (HC32F448) || defined (HC32F472)
|
||||
#if defined (HC32F4A0) || defined (HC32F448) || defined (HC32F472) || defined (HC32F4A8)
|
||||
switch (cfg->flowcontrol)
|
||||
{
|
||||
case RT_SERIAL_FLOWCONTROL_NONE:
|
||||
|
|
@ -252,8 +257,14 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_co
|
|||
int32_t i32Ret = LL_ERR;
|
||||
USART_DeInit(uart->config->Instance);
|
||||
USART_UART_Init(uart->config->Instance, &uart_init, NULL);
|
||||
for (u32Div = 0UL; u32Div <= USART_CLK_DIV64; u32Div++)
|
||||
for (u32Div = 0UL; u32Div <= USART_MAX_CLK_DIV; u32Div++)
|
||||
{
|
||||
#if defined (HC32F448) || defined (HC32F4A8)
|
||||
if (u32Div == (USART_CLK_DIV64 + 1U))
|
||||
{
|
||||
u32Div = USART_CLK_DIV128;
|
||||
}
|
||||
#endif
|
||||
USART_SetClockDiv(uart->config->Instance, u32Div);
|
||||
if ((LL_OK == USART_SetBaudrate(uart->config->Instance, uart_init.u32Baudrate, &f32Error)) &&
|
||||
((-UART_BAUDRATE_ERR_MAX <= f32Error) && (f32Error <= UART_BAUDRATE_ERR_MAX)))
|
||||
|
|
@ -268,7 +279,7 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_co
|
|||
}
|
||||
|
||||
/* Enable error interrupt */
|
||||
#if defined (HC32F460) || defined (HC32F4A0)
|
||||
#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8)
|
||||
NVIC_EnableIRQ(uart->config->rxerr_irq.irq_config.irq_num);
|
||||
#elif defined (HC32F448) || defined (HC32F472)
|
||||
INTC_IntSrcCmd(uart->config->tx_int_src, ENABLE);
|
||||
|
|
@ -296,7 +307,7 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg
|
|||
case RT_DEVICE_CTRL_CLR_INT:
|
||||
if (RT_DEVICE_FLAG_INT_RX == ctrl_arg)
|
||||
{
|
||||
#if defined (HC32F460) || defined (HC32F4A0)
|
||||
#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8)
|
||||
NVIC_DisableIRQ(uart->config->rx_irq.irq_config.irq_num);
|
||||
INTC_IrqSignOut(uart->config->rx_irq.irq_config.irq_num);
|
||||
#elif defined (HC32F448) || defined (HC32F472)
|
||||
|
|
@ -305,7 +316,7 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg
|
|||
}
|
||||
else if (RT_DEVICE_FLAG_INT_TX == ctrl_arg)
|
||||
{
|
||||
#if defined (HC32F460) || defined (HC32F4A0)
|
||||
#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8)
|
||||
NVIC_DisableIRQ(uart->config->tx_irq.irq_config.irq_num);
|
||||
USART_FuncCmd(uart->config->Instance, USART_INT_TX_EMPTY, DISABLE);
|
||||
INTC_IrqSignOut(uart->config->tx_irq.irq_config.irq_num);
|
||||
|
|
@ -327,7 +338,7 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg
|
|||
break;
|
||||
/* Enable interrupt */
|
||||
case RT_DEVICE_CTRL_SET_INT:
|
||||
#if defined (HC32F460) || defined (HC32F4A0)
|
||||
#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8)
|
||||
if (RT_DEVICE_FLAG_INT_RX == ctrl_arg)
|
||||
{
|
||||
hc32_install_irq_handler(&uart->config->rx_irq.irq_config, uart->config->rx_irq.irq_callback, RT_TRUE);
|
||||
|
|
@ -521,9 +532,31 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial)
|
|||
{
|
||||
RT_ASSERT(TMR0_CH_B == ch);
|
||||
}
|
||||
#elif defined (HC32F4A8)
|
||||
if ((CM_USART1 == uart->config->Instance) || (CM_USART3 == uart->config->Instance) || (CM_USART5 == uart->config->Instance) ||
|
||||
(CM_USART6 == uart->config->Instance) || (CM_USART9 == uart->config->Instance))
|
||||
{
|
||||
RT_ASSERT(TMR0_CH_A == ch);
|
||||
}
|
||||
else if ((CM_USART2 == uart->config->Instance) || (CM_USART4 == uart->config->Instance) || (CM_USART7 == uart->config->Instance) ||
|
||||
(CM_USART8 == uart->config->Instance) || (CM_USART10 == uart->config->Instance))
|
||||
{
|
||||
RT_ASSERT(TMR0_CH_B == ch);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined (HC32F4A8)
|
||||
if ((CM_TMR0_4 == uart->config->rx_timeout->TMR0_Instance) || (CM_TMR0_5 == uart->config->rx_timeout->TMR0_Instance))
|
||||
{
|
||||
FCG_Fcg3PeriphClockCmd(uart->config->rx_timeout->clock, ENABLE);
|
||||
}
|
||||
else
|
||||
{
|
||||
FCG_TMR0_CLK(uart->config->rx_timeout->clock, ENABLE);
|
||||
}
|
||||
#elif defined (HC32F460) || defined (HC32F4A0) || defined (HC32F448) || defined (HC32F472)
|
||||
FCG_TMR0_CLK(uart->config->rx_timeout->clock, ENABLE);
|
||||
#endif
|
||||
|
||||
/* TIMER0 basetimer function initialize */
|
||||
TMR0_SetCountValue(TMR0_Instance, ch, 0U);
|
||||
|
|
@ -559,7 +592,7 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial)
|
|||
/* Clear compare flag */
|
||||
TMR0_ClearStatus(TMR0_Instance, (uint32_t)(0x1UL << (ch * TMR0_STFLR_CMFB_POS)));
|
||||
|
||||
#if defined (HC32F460) || defined (HC32F4A0)
|
||||
#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8)
|
||||
NVIC_EnableIRQ(uart->config->rx_timeout->irq_config.irq_num);
|
||||
#endif
|
||||
USART_ClearStatus(uart->config->Instance, USART_FLAG_RX_TIMEOUT);
|
||||
|
|
@ -673,7 +706,8 @@ static void hc32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
|
|||
|
||||
#if defined (BSP_UART1_RX_USING_DMA) || defined (BSP_UART2_RX_USING_DMA) || defined (BSP_UART3_RX_USING_DMA) || \
|
||||
defined (BSP_UART4_RX_USING_DMA) || defined (BSP_UART5_RX_USING_DMA) || defined (BSP_UART6_RX_USING_DMA) || \
|
||||
defined (BSP_UART7_RX_USING_DMA)
|
||||
defined (BSP_UART7_RX_USING_DMA) || defined (BSP_UART8_RX_USING_DMA) || defined (BSP_UART9_RX_USING_DMA) || \
|
||||
defined (BSP_UART10_RX_USING_DMA)
|
||||
static void hc32_uart_dma_rx_irq_handler(struct hc32_uart *uart)
|
||||
{
|
||||
rt_base_t level;
|
||||
|
|
@ -732,7 +766,8 @@ static void hc32_uart_rxto_irq_handler(struct hc32_uart *uart)
|
|||
|
||||
#if defined (BSP_UART1_TX_USING_DMA) || defined (BSP_UART2_TX_USING_DMA) || defined (BSP_UART3_TX_USING_DMA) || \
|
||||
defined (BSP_UART4_TX_USING_DMA) || defined (BSP_UART5_TX_USING_DMA) || defined (BSP_UART6_TX_USING_DMA) || \
|
||||
defined (BSP_UART7_TX_USING_DMA)
|
||||
defined (BSP_UART7_TX_USING_DMA) || defined (BSP_UART8_TX_USING_DMA) || defined (BSP_UART9_TX_USING_DMA) || \
|
||||
defined (BSP_UART10_TX_USING_DMA)
|
||||
static void hc32_uart_tc_irq_handler(struct hc32_uart *uart)
|
||||
{
|
||||
RT_ASSERT(uart != RT_NULL);
|
||||
|
|
@ -789,7 +824,7 @@ static void hc32_usart_handler(struct hc32_uart *uart)
|
|||
#endif
|
||||
|
||||
#if defined (BSP_USING_UART1)
|
||||
#if defined (HC32F460) || defined (HC32F4A0)
|
||||
#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8)
|
||||
static void hc32_uart1_rx_irq_handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
|
|
@ -822,7 +857,7 @@ static void hc32_uart1_rxerr_irq_handler(void)
|
|||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* HC32F460, HC32F4A0 */
|
||||
#endif
|
||||
|
||||
#if defined (RT_SERIAL_USING_DMA)
|
||||
#if defined (BSP_UART1_TX_USING_DMA)
|
||||
|
|
@ -846,7 +881,7 @@ void USART1_TxComplete_Handler(void)
|
|||
#endif /* BSP_UART1_TX_USING_DMA */
|
||||
|
||||
#if defined (BSP_UART1_RX_USING_DMA)
|
||||
#if defined (HC32F460) || defined (HC32F4A0)
|
||||
#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8)
|
||||
static void hc32_uart1_rxto_irq_handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
|
|
@ -857,7 +892,7 @@ static void hc32_uart1_rxto_irq_handler(void)
|
|||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* HC32F460, HC32F4A0 */
|
||||
#endif
|
||||
|
||||
static void hc32_uart1_dma_rx_irq_handler(void)
|
||||
{
|
||||
|
|
@ -883,11 +918,11 @@ void USART1_Handler(void)
|
|||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* HC32F448, HC32F472 */
|
||||
#endif
|
||||
#endif /* BSP_USING_UART1 */
|
||||
|
||||
#if defined (BSP_USING_UART2)
|
||||
#if defined (HC32F460) || defined (HC32F4A0)
|
||||
#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8)
|
||||
static void hc32_uart2_rx_irq_handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
|
|
@ -920,7 +955,7 @@ static void hc32_uart2_rxerr_irq_handler(void)
|
|||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* HC32F460, HC32F4A0 */
|
||||
#endif
|
||||
|
||||
#if defined (RT_SERIAL_USING_DMA)
|
||||
#if defined (BSP_UART2_TX_USING_DMA)
|
||||
|
|
@ -944,7 +979,7 @@ void USART2_TxComplete_Handler(void)
|
|||
#endif /* BSP_UART2_TX_USING_DMA */
|
||||
|
||||
#if defined (BSP_UART2_RX_USING_DMA)
|
||||
#if defined (HC32F460) || defined (HC32F4A0)
|
||||
#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8)
|
||||
static void hc32_uart2_rxto_irq_handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
|
|
@ -955,7 +990,7 @@ static void hc32_uart2_rxto_irq_handler(void)
|
|||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* HC32F460, HC32F4A0 */
|
||||
#endif
|
||||
|
||||
static void hc32_uart2_dma_rx_irq_handler(void)
|
||||
{
|
||||
|
|
@ -981,11 +1016,11 @@ void USART2_Handler(void)
|
|||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* HC32F448, HC32F472 */
|
||||
#endif
|
||||
#endif /* BSP_USING_UART2 */
|
||||
|
||||
#if defined (BSP_USING_UART3)
|
||||
#if defined (HC32F460) || defined (HC32F4A0)
|
||||
#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8)
|
||||
static void hc32_uart3_rx_irq_handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
|
|
@ -1058,7 +1093,7 @@ static void hc32_uart3_dma_rx_irq_handler(void)
|
|||
}
|
||||
#endif /* BSP_UART3_RX_USING_DMA */
|
||||
#endif /* RT_SERIAL_USING_DMA */
|
||||
#endif /* HC32F460, HC32F4A0 */
|
||||
#endif /* HC32F460, HC32F4A0, HC32F4A8 */
|
||||
|
||||
#if defined (HC32F448) || defined (HC32F472)
|
||||
void USART3_Handler(void)
|
||||
|
|
@ -1071,11 +1106,11 @@ void USART3_Handler(void)
|
|||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* HC32F448, HC32F472 */
|
||||
#endif
|
||||
#endif /* BSP_USING_UART3 */
|
||||
|
||||
#if defined (BSP_USING_UART4)
|
||||
#if defined (HC32F460) || defined (HC32F4A0)
|
||||
#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8)
|
||||
static void hc32_uart4_rx_irq_handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
|
|
@ -1108,7 +1143,7 @@ static void hc32_uart4_rxerr_irq_handler(void)
|
|||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* HC32F460, HC32F4A0 */
|
||||
#endif
|
||||
|
||||
#if defined (RT_SERIAL_USING_DMA)
|
||||
#if defined (BSP_UART4_TX_USING_DMA)
|
||||
|
|
@ -1128,11 +1163,11 @@ void USART4_TxComplete_Handler(void)
|
|||
{
|
||||
hc32_uart4_tc_irq_handler();
|
||||
}
|
||||
#endif /* HC32F448, HC32F472 */
|
||||
#endif
|
||||
#endif /* BSP_UART4_TX_USING_DMA */
|
||||
|
||||
#if defined (BSP_UART4_RX_USING_DMA)
|
||||
#if defined (HC32F460) || defined (HC32F4A0)
|
||||
#if defined (HC32F460) || defined (HC32F4A8)
|
||||
static void hc32_uart4_rxto_irq_handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
|
|
@ -1143,7 +1178,7 @@ static void hc32_uart4_rxto_irq_handler(void)
|
|||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* HC32F460, HC32F4A0 */
|
||||
#endif
|
||||
|
||||
static void hc32_uart4_dma_rx_irq_handler(void)
|
||||
{
|
||||
|
|
@ -1169,11 +1204,11 @@ void USART4_Handler(void)
|
|||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* HC32F448, HC32F472 */
|
||||
#endif
|
||||
#endif /* BSP_USING_UART4 */
|
||||
|
||||
#if defined (BSP_USING_UART5)
|
||||
#if defined (HC32F460) || defined (HC32F4A0)
|
||||
#if defined (HC32F4A0) || defined (HC32F4A8)
|
||||
static void hc32_uart5_rx_irq_handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
|
|
@ -1206,9 +1241,8 @@ static void hc32_uart5_rxerr_irq_handler(void)
|
|||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* HC32F460, HC32F4A0 */
|
||||
#endif
|
||||
|
||||
#if defined (HC32F448) || defined (HC32F472)
|
||||
#if defined (RT_SERIAL_USING_DMA)
|
||||
#if defined (BSP_UART5_TX_USING_DMA)
|
||||
static void hc32_uart5_tc_irq_handler(void)
|
||||
|
|
@ -1222,13 +1256,28 @@ static void hc32_uart5_tc_irq_handler(void)
|
|||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
#if defined (HC32F448) || defined (HC32F472)
|
||||
void USART5_TxComplete_Handler(void)
|
||||
{
|
||||
hc32_uart5_tc_irq_handler();
|
||||
}
|
||||
#endif
|
||||
#endif /* BSP_UART5_TX_USING_DMA */
|
||||
|
||||
#if defined (BSP_UART5_RX_USING_DMA)
|
||||
#if defined (HC32F4A8)
|
||||
static void hc32_uart5_rxto_irq_handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
hc32_uart_rxto_irq_handler(&uart_obj[UART5_INDEX]);
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif
|
||||
|
||||
static void hc32_uart5_dma_rx_irq_handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
|
|
@ -1242,6 +1291,7 @@ static void hc32_uart5_dma_rx_irq_handler(void)
|
|||
#endif /* BSP_UART5_RX_USING_DMA */
|
||||
#endif /* RT_SERIAL_USING_DMA */
|
||||
|
||||
#if defined (HC32F448) || defined (HC32F472)
|
||||
void USART5_Handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
|
|
@ -1252,11 +1302,11 @@ void USART5_Handler(void)
|
|||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* HC32F448, HC32F472 */
|
||||
#endif
|
||||
#endif /* BSP_USING_UART5 */
|
||||
|
||||
#if defined (BSP_USING_UART6)
|
||||
#if defined (HC32F460) || defined (HC32F4A0)
|
||||
#if defined (HC32F4A0) || defined (HC32F4A8)
|
||||
static void hc32_uart6_rx_irq_handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
|
|
@ -1328,7 +1378,7 @@ static void hc32_uart6_dma_rx_irq_handler(void)
|
|||
}
|
||||
#endif /* BSP_UART6_RX_USING_DMA */
|
||||
#endif /* RT_SERIAL_USING_DMA */
|
||||
#endif /* HC32F460, HC32F4A0 */
|
||||
#endif /* HC32F4A0, HC32F4A8 */
|
||||
|
||||
#if defined (HC32F448) || defined (HC32F472)
|
||||
void USART6_Handler(void)
|
||||
|
|
@ -1341,7 +1391,7 @@ void USART6_Handler(void)
|
|||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* HC32F448, HC32F472 */
|
||||
#endif
|
||||
#endif /* BSP_USING_UART6 */
|
||||
|
||||
#if defined (BSP_USING_UART7)
|
||||
|
|
@ -1451,6 +1501,45 @@ static void hc32_uart8_rxerr_irq_handler(void)
|
|||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
#if defined (RT_SERIAL_USING_DMA)
|
||||
#if defined (BSP_UART8_TX_USING_DMA)
|
||||
static void hc32_uart8_tc_irq_handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
hc32_uart_tc_irq_handler(&uart_obj[UART8_INDEX]);
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* BSP_UART8_TX_USING_DMA */
|
||||
|
||||
#if defined (BSP_UART8_RX_USING_DMA)
|
||||
static void hc32_uart8_rxto_irq_handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
hc32_uart_rxto_irq_handler(&uart_obj[UART8_INDEX]);
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
static void hc32_uart8_dma_rx_irq_handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
hc32_uart_dma_rx_irq_handler(&uart_obj[UART8_INDEX]);
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* BSP_UART8_RX_USING_DMA */
|
||||
#endif /* RT_SERIAL_USING_DMA */
|
||||
#endif /* BSP_USING_UART8 */
|
||||
|
||||
#if defined (BSP_USING_UART9)
|
||||
|
|
@ -1486,6 +1575,45 @@ static void hc32_uart9_rxerr_irq_handler(void)
|
|||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
#if defined (RT_SERIAL_USING_DMA)
|
||||
#if defined (BSP_UART9_TX_USING_DMA)
|
||||
static void hc32_uart9_tc_irq_handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
hc32_uart_tc_irq_handler(&uart_obj[UART9_INDEX]);
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* BSP_UART9_TX_USING_DMA */
|
||||
|
||||
#if defined (BSP_UART9_RX_USING_DMA)
|
||||
static void hc32_uart9_rxto_irq_handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
hc32_uart_rxto_irq_handler(&uart_obj[UART9_INDEX]);
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
static void hc32_uart9_dma_rx_irq_handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
hc32_uart_dma_rx_irq_handler(&uart_obj[UART9_INDEX]);
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* BSP_UART9_RX_USING_DMA */
|
||||
#endif /* RT_SERIAL_USING_DMA */
|
||||
#endif /* BSP_USING_UART9 */
|
||||
|
||||
#if defined (BSP_USING_UART10)
|
||||
|
|
@ -1521,6 +1649,45 @@ static void hc32_uart10_rxerr_irq_handler(void)
|
|||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
#if defined (RT_SERIAL_USING_DMA)
|
||||
#if defined (BSP_UART10_TX_USING_DMA)
|
||||
static void hc32_uart10_tc_irq_handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
hc32_uart_tc_irq_handler(&uart_obj[UART10_INDEX]);
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* BSP_UART10_TX_USING_DMA */
|
||||
|
||||
#if defined (BSP_UART10_RX_USING_DMA)
|
||||
static void hc32_uart10_rxto_irq_handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
hc32_uart_rxto_irq_handler(&uart_obj[UART10_INDEX]);
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
static void hc32_uart10_dma_rx_irq_handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
hc32_uart_dma_rx_irq_handler(&uart_obj[UART10_INDEX]);
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* BSP_UART10_RX_USING_DMA */
|
||||
#endif /* RT_SERIAL_USING_DMA */
|
||||
#endif /* BSP_USING_UART10 */
|
||||
|
||||
/**
|
||||
|
|
@ -1538,7 +1705,7 @@ static void hc32_uart_get_dma_info(void)
|
|||
static struct dma_config uart1_dma_rx = UART1_DMA_RX_CONFIG;
|
||||
static struct hc32_uart_rxto uart1_rx_timeout = UART1_RXTO_CONFIG;
|
||||
uart1_dma_rx.irq_callback = hc32_uart1_dma_rx_irq_handler;
|
||||
#if defined (HC32F460) || defined (HC32F4A0)
|
||||
#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8)
|
||||
uart1_rx_timeout.irq_callback = hc32_uart1_rxto_irq_handler;
|
||||
#endif
|
||||
uart_config[UART1_INDEX].rx_timeout = &uart1_rx_timeout;
|
||||
|
|
@ -1561,7 +1728,7 @@ static void hc32_uart_get_dma_info(void)
|
|||
static struct dma_config uart2_dma_rx = UART2_DMA_RX_CONFIG;
|
||||
static struct hc32_uart_rxto uart2_rx_timeout = UART2_RXTO_CONFIG;
|
||||
uart2_dma_rx.irq_callback = hc32_uart2_dma_rx_irq_handler;
|
||||
#if defined (HC32F460) || defined (HC32F4A0)
|
||||
#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8)
|
||||
uart2_rx_timeout.irq_callback = hc32_uart2_rxto_irq_handler;
|
||||
#endif
|
||||
uart_config[UART2_INDEX].rx_timeout = &uart2_rx_timeout;
|
||||
|
|
@ -1579,7 +1746,6 @@ static void hc32_uart_get_dma_info(void)
|
|||
|
||||
#ifdef BSP_USING_UART3
|
||||
uart_obj[UART3_INDEX].uart_dma_flag = 0;
|
||||
#if defined (HC32F460)
|
||||
#ifdef BSP_UART3_RX_USING_DMA
|
||||
uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
|
||||
static struct dma_config uart3_dma_rx = UART3_DMA_RX_CONFIG;
|
||||
|
|
@ -1598,7 +1764,6 @@ static void hc32_uart_get_dma_info(void)
|
|||
uart_config[UART3_INDEX].tc_irq = &uart3_tc_irq;
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_UART4
|
||||
uart_obj[UART4_INDEX].uart_dma_flag = 0;
|
||||
|
|
@ -1607,7 +1772,7 @@ static void hc32_uart_get_dma_info(void)
|
|||
static struct dma_config uart4_dma_rx = UART4_DMA_RX_CONFIG;
|
||||
static struct hc32_uart_rxto uart4_rx_timeout = UART4_RXTO_CONFIG;
|
||||
uart4_dma_rx.irq_callback = hc32_uart4_dma_rx_irq_handler;
|
||||
#if defined (HC32F460)
|
||||
#if defined (HC32F460) || defined (HC32F4A8)
|
||||
uart4_rx_timeout.irq_callback = hc32_uart4_rxto_irq_handler;
|
||||
#endif
|
||||
uart_config[UART4_INDEX].rx_timeout = &uart4_rx_timeout;
|
||||
|
|
@ -1625,12 +1790,14 @@ static void hc32_uart_get_dma_info(void)
|
|||
|
||||
#ifdef BSP_USING_UART5
|
||||
uart_obj[UART5_INDEX].uart_dma_flag = 0;
|
||||
#if defined (HC32F448) || defined (HC32F472)
|
||||
#ifdef BSP_UART5_RX_USING_DMA
|
||||
uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
|
||||
static struct dma_config uart5_dma_rx = UART5_DMA_RX_CONFIG;
|
||||
static struct hc32_uart_rxto uart5_rx_timeout = UART5_RXTO_CONFIG;
|
||||
uart5_dma_rx.irq_callback = hc32_uart5_dma_rx_irq_handler;
|
||||
#if defined (HC32F4A8)
|
||||
uart5_rx_timeout.irq_callback = hc32_uart5_rxto_irq_handler;
|
||||
#endif
|
||||
uart_config[UART5_INDEX].rx_timeout = &uart5_rx_timeout;
|
||||
uart_config[UART5_INDEX].dma_rx = &uart5_dma_rx;
|
||||
#endif
|
||||
|
|
@ -1643,11 +1810,9 @@ static void hc32_uart_get_dma_info(void)
|
|||
uart_config[UART5_INDEX].tc_irq = &uart5_tc_irq;
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_UART6
|
||||
uart_obj[UART6_INDEX].uart_dma_flag = 0;
|
||||
#if defined (HC32F4A0)
|
||||
#ifdef BSP_UART6_RX_USING_DMA
|
||||
uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
|
||||
static struct dma_config uart6_dma_rx = UART6_DMA_RX_CONFIG;
|
||||
|
|
@ -1666,11 +1831,9 @@ static void hc32_uart_get_dma_info(void)
|
|||
uart_config[UART6_INDEX].tc_irq = &uart6_tc_irq;
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_UART7
|
||||
uart_obj[UART7_INDEX].uart_dma_flag = 0;
|
||||
#if defined (HC32F4A0)
|
||||
#ifdef BSP_UART7_RX_USING_DMA
|
||||
uart_obj[UART7_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
|
||||
static struct dma_config uart7_dma_rx = UART7_DMA_RX_CONFIG;
|
||||
|
|
@ -1689,22 +1852,72 @@ static void hc32_uart_get_dma_info(void)
|
|||
uart_config[UART7_INDEX].tc_irq = &uart7_tc_irq;
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_UART8
|
||||
uart_obj[UART8_INDEX].uart_dma_flag = 0;
|
||||
#ifdef BSP_UART8_RX_USING_DMA
|
||||
uart_obj[UART8_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
|
||||
static struct dma_config uart8_dma_rx = UART8_DMA_RX_CONFIG;
|
||||
static struct hc32_uart_rxto uart8_rx_timeout = UART8_RXTO_CONFIG;
|
||||
uart8_dma_rx.irq_callback = hc32_uart8_dma_rx_irq_handler;
|
||||
uart8_rx_timeout.irq_callback = hc32_uart8_rxto_irq_handler;
|
||||
uart_config[UART8_INDEX].rx_timeout = &uart8_rx_timeout;
|
||||
uart_config[UART8_INDEX].dma_rx = &uart8_dma_rx;
|
||||
#endif
|
||||
#ifdef BSP_UART8_TX_USING_DMA
|
||||
uart_obj[UART8_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
|
||||
static struct dma_config uart8_dma_tx = UART8_DMA_TX_CONFIG;
|
||||
uart_config[UART8_INDEX].dma_tx = &uart8_dma_tx;
|
||||
static struct hc32_uart_irq_config uart8_tc_irq = UART8_TX_CPLT_CONFIG;
|
||||
uart8_tc_irq.irq_callback = hc32_uart8_tc_irq_handler;
|
||||
uart_config[UART8_INDEX].tc_irq = &uart8_tc_irq;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_UART9
|
||||
uart_obj[UART9_INDEX].uart_dma_flag = 0;
|
||||
#ifdef BSP_UART9_RX_USING_DMA
|
||||
uart_obj[UART9_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
|
||||
static struct dma_config uart9_dma_rx = UART9_DMA_RX_CONFIG;
|
||||
static struct hc32_uart_rxto uart9_rx_timeout = UART9_RXTO_CONFIG;
|
||||
uart9_dma_rx.irq_callback = hc32_uart9_dma_rx_irq_handler;
|
||||
uart9_rx_timeout.irq_callback = hc32_uart9_rxto_irq_handler;
|
||||
uart_config[UART9_INDEX].rx_timeout = &uart9_rx_timeout;
|
||||
uart_config[UART9_INDEX].dma_rx = &uart9_dma_rx;
|
||||
#endif
|
||||
#ifdef BSP_UART9_TX_USING_DMA
|
||||
uart_obj[UART9_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
|
||||
static struct dma_config uart9_dma_tx = UART9_DMA_TX_CONFIG;
|
||||
uart_config[UART9_INDEX].dma_tx = &uart9_dma_tx;
|
||||
static struct hc32_uart_irq_config uart9_tc_irq = UART9_TX_CPLT_CONFIG;
|
||||
uart9_tc_irq.irq_callback = hc32_uart9_tc_irq_handler;
|
||||
uart_config[UART9_INDEX].tc_irq = &uart9_tc_irq;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_UART10
|
||||
uart_obj[UART10_INDEX].uart_dma_flag = 0;
|
||||
#ifdef BSP_UART10_RX_USING_DMA
|
||||
uart_obj[UART10_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
|
||||
static struct dma_config uart10_dma_rx = UART10_DMA_RX_CONFIG;
|
||||
static struct hc32_uart_rxto uart10_rx_timeout = UART10_RXTO_CONFIG;
|
||||
uart10_dma_rx.irq_callback = hc32_uart10_dma_rx_irq_handler;
|
||||
uart10_rx_timeout.irq_callback = hc32_uart10_rxto_irq_handler;
|
||||
uart_config[UART10_INDEX].rx_timeout = &uart10_rx_timeout;
|
||||
uart_config[UART10_INDEX].dma_rx = &uart10_dma_rx;
|
||||
#endif
|
||||
#ifdef BSP_UART10_TX_USING_DMA
|
||||
uart_obj[UART10_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
|
||||
static struct dma_config uart10_dma_tx = UART10_DMA_TX_CONFIG;
|
||||
uart_config[UART10_INDEX].dma_tx = &uart10_dma_tx;
|
||||
static struct hc32_uart_irq_config uart10_tc_irq = UART10_TX_CPLT_CONFIG;
|
||||
uart10_tc_irq.irq_callback = hc32_uart10_tc_irq_handler;
|
||||
uart_config[UART10_INDEX].tc_irq = &uart10_tc_irq;
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
#if defined (HC32F460) || defined (HC32F4A0)
|
||||
#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8)
|
||||
/**
|
||||
* @brief This function gets uart irq handle.
|
||||
* @param None
|
||||
|
|
@ -1781,7 +1994,7 @@ int rt_hw_usart_init(void)
|
|||
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
|
||||
|
||||
hc32_uart_get_dma_info();
|
||||
#if defined (HC32F460) || defined (HC32F4A0)
|
||||
#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8)
|
||||
hc32_get_uart_callback();
|
||||
#endif
|
||||
for (int i = 0; i < obj_num; i++)
|
||||
|
|
@ -1790,7 +2003,7 @@ int rt_hw_usart_init(void)
|
|||
uart_obj[i].serial.ops = &hc32_uart_ops;
|
||||
uart_obj[i].serial.config = config;
|
||||
uart_obj[i].config = &uart_config[i];
|
||||
#if defined (HC32F460) || defined (HC32F4A0)
|
||||
#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8)
|
||||
/* register the handle */
|
||||
hc32_install_irq_handler(&uart_config[i].rxerr_irq.irq_config, uart_config[i].rxerr_irq.irq_callback, RT_FALSE);
|
||||
#endif
|
||||
|
|
@ -1798,7 +2011,7 @@ int rt_hw_usart_init(void)
|
|||
if (uart_obj[i].uart_dma_flag & RT_DEVICE_FLAG_DMA_RX)
|
||||
{
|
||||
hc32_install_irq_handler(&uart_config[i].dma_rx->irq_config, uart_config[i].dma_rx->irq_callback, RT_FALSE);
|
||||
#if defined (HC32F460) || defined (HC32F4A0)
|
||||
#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8)
|
||||
hc32_install_irq_handler(&uart_config[i].rx_timeout->irq_config, uart_config[i].rx_timeout->irq_callback, RT_FALSE);
|
||||
#endif
|
||||
}
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@ struct hc32_uart_rxto
|
|||
rt_uint32_t channel;
|
||||
rt_uint32_t clock;
|
||||
rt_size_t timeout_bits;
|
||||
#if defined (HC32F460) || defined (HC32F4A0)
|
||||
#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8)
|
||||
struct hc32_irq_config irq_config;
|
||||
func_ptr_t irq_callback;
|
||||
#endif
|
||||
|
|
@ -53,7 +53,7 @@ struct hc32_uart_config
|
|||
const char *name;
|
||||
CM_USART_TypeDef *Instance;
|
||||
rt_uint32_t clock;
|
||||
#if defined (HC32F460) || defined (HC32F4A0)
|
||||
#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8)
|
||||
struct hc32_uart_irq_config rxerr_irq;
|
||||
struct hc32_uart_irq_config rx_irq;
|
||||
struct hc32_uart_irq_config tx_irq;
|
||||
|
|
|
|||
|
|
@ -48,13 +48,18 @@
|
|||
#if defined (HC32F460)
|
||||
#define FCG_USART_CLK FCG_Fcg1PeriphClockCmd
|
||||
|
||||
#elif defined (HC32F4A0) || defined (HC32F448) || defined (HC32F472)
|
||||
#elif defined (HC32F4A0) || defined (HC32F448) || defined (HC32F472) || defined (HC32F4A8)
|
||||
#define FCG_USART_CLK FCG_Fcg3PeriphClockCmd
|
||||
|
||||
#endif
|
||||
|
||||
#define FCG_TMR0_CLK FCG_Fcg2PeriphClockCmd
|
||||
#define FCG_DMA_CLK FCG_Fcg0PeriphClockCmd
|
||||
#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472)
|
||||
#define USART_MAX_CLK_DIV USART_CLK_DIV64
|
||||
#elif defined (HC32F448) || defined (HC32F4A8)
|
||||
#define USART_MAX_CLK_DIV USART_CLK_DIV1024
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions (declared in header file with 'extern')
|
||||
|
|
@ -221,7 +226,7 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_co
|
|||
{
|
||||
uart_init.u32FirstBit = USART_FIRST_BIT_MSB;
|
||||
}
|
||||
#if defined (HC32F4A0) || defined (HC32F448) || defined (HC32F472)
|
||||
#if defined (HC32F4A0) || defined (HC32F448) || defined (HC32F472) || defined (HC32F4A8)
|
||||
switch (cfg->flowcontrol)
|
||||
{
|
||||
case RT_SERIAL_FLOWCONTROL_NONE:
|
||||
|
|
@ -251,8 +256,14 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_co
|
|||
int32_t i32Ret = LL_ERR;
|
||||
USART_DeInit(uart->config->Instance);
|
||||
USART_UART_Init(uart->config->Instance, &uart_init, NULL);
|
||||
for (u32Div = 0UL; u32Div <= USART_CLK_DIV64; u32Div++)
|
||||
for (u32Div = 0UL; u32Div <= USART_MAX_CLK_DIV; u32Div++)
|
||||
{
|
||||
#if defined (HC32F448) || defined (HC32F4A8)
|
||||
if (u32Div == (USART_CLK_DIV64 + 1U))
|
||||
{
|
||||
u32Div = USART_CLK_DIV128;
|
||||
}
|
||||
#endif
|
||||
USART_SetClockDiv(uart->config->Instance, u32Div);
|
||||
if ((LL_OK == USART_SetBaudrate(uart->config->Instance, uart_init.u32Baudrate, &f32Error)) &&
|
||||
((-UART_BAUDRATE_ERR_MAX <= f32Error) && (f32Error <= UART_BAUDRATE_ERR_MAX)))
|
||||
|
|
@ -267,7 +278,7 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_co
|
|||
}
|
||||
|
||||
/* Enable error interrupt */
|
||||
#if defined (HC32F460) || defined (HC32F4A0)
|
||||
#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8)
|
||||
NVIC_EnableIRQ(uart->config->rxerr_irq.irq_config.irq_num);
|
||||
#elif defined (HC32F448) || defined (HC32F472)
|
||||
INTC_IntSrcCmd(uart->config->tx_int_src, ENABLE);
|
||||
|
|
@ -319,7 +330,7 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg
|
|||
case RT_DEVICE_CTRL_CLR_INT:
|
||||
if (RT_DEVICE_FLAG_INT_RX == ctrl_arg)
|
||||
{
|
||||
#if defined (HC32F460) || defined (HC32F4A0)
|
||||
#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8)
|
||||
NVIC_DisableIRQ(uart->config->rx_irq.irq_config.irq_num);
|
||||
INTC_IrqSignOut(uart->config->rx_irq.irq_config.irq_num);
|
||||
#elif defined (HC32F448) || defined (HC32F472)
|
||||
|
|
@ -328,7 +339,7 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg
|
|||
}
|
||||
else if (RT_DEVICE_FLAG_INT_TX == ctrl_arg)
|
||||
{
|
||||
#if defined (HC32F460) || defined (HC32F4A0)
|
||||
#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8)
|
||||
NVIC_DisableIRQ(uart->config->tx_irq.irq_config.irq_num);
|
||||
NVIC_DisableIRQ(uart->config->tc_irq.irq_config.irq_num);
|
||||
USART_FuncCmd(uart->config->Instance, (USART_INT_TX_EMPTY | USART_INT_TX_CPLT), DISABLE);
|
||||
|
|
@ -354,7 +365,7 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg
|
|||
break;
|
||||
/* Enable interrupt */
|
||||
case RT_DEVICE_CTRL_SET_INT:
|
||||
#if defined (HC32F460) || defined (HC32F4A0)
|
||||
#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8)
|
||||
if (RT_DEVICE_FLAG_INT_RX == ctrl_arg)
|
||||
{
|
||||
hc32_install_irq_handler(&uart->config->rx_irq.irq_config, uart->config->rx_irq.irq_callback, RT_TRUE);
|
||||
|
|
@ -593,9 +604,31 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial)
|
|||
{
|
||||
RT_ASSERT(TMR0_CH_B == ch);
|
||||
}
|
||||
#elif defined (HC32F4A8)
|
||||
if ((CM_USART1 == uart->config->Instance) || (CM_USART3 == uart->config->Instance) || (CM_USART5 == uart->config->Instance) ||
|
||||
(CM_USART6 == uart->config->Instance) || (CM_USART9 == uart->config->Instance))
|
||||
{
|
||||
RT_ASSERT(TMR0_CH_A == ch);
|
||||
}
|
||||
else if ((CM_USART2 == uart->config->Instance) || (CM_USART4 == uart->config->Instance) || (CM_USART7 == uart->config->Instance) ||
|
||||
(CM_USART8 == uart->config->Instance) || (CM_USART10 == uart->config->Instance))
|
||||
{
|
||||
RT_ASSERT(TMR0_CH_B == ch);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined (HC32F4A8)
|
||||
if ((CM_TMR0_4 == uart->config->rx_timeout->TMR0_Instance) || (CM_TMR0_5 == uart->config->rx_timeout->TMR0_Instance))
|
||||
{
|
||||
FCG_Fcg3PeriphClockCmd(uart->config->rx_timeout->clock, ENABLE);
|
||||
}
|
||||
else
|
||||
{
|
||||
FCG_TMR0_CLK(uart->config->rx_timeout->clock, ENABLE);
|
||||
}
|
||||
#elif defined (HC32F460) || defined (HC32F4A0) || defined (HC32F448) || defined (HC32F472)
|
||||
FCG_TMR0_CLK(uart->config->rx_timeout->clock, ENABLE);
|
||||
#endif
|
||||
|
||||
/* TIMER0 basetimer function initialize */
|
||||
TMR0_SetCountValue(TMR0_Instance, ch, 0U);
|
||||
|
|
@ -631,7 +664,7 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial)
|
|||
/* Clear compare flag */
|
||||
TMR0_ClearStatus(TMR0_Instance, (uint32_t)(0x1UL << (ch * TMR0_STFLR_CMFB_POS)));
|
||||
|
||||
#if defined (HC32F460) || defined (HC32F4A0)
|
||||
#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8)
|
||||
NVIC_EnableIRQ(uart->config->rx_timeout->irq_config.irq_num);
|
||||
#endif
|
||||
USART_ClearStatus(uart->config->Instance, USART_FLAG_RX_TIMEOUT);
|
||||
|
|
@ -745,7 +778,8 @@ static void hc32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
|
|||
|
||||
#if defined (BSP_UART1_RX_USING_DMA) || defined (BSP_UART2_RX_USING_DMA) || defined (BSP_UART3_RX_USING_DMA) || \
|
||||
defined (BSP_UART4_RX_USING_DMA) || defined (BSP_UART5_RX_USING_DMA) || defined (BSP_UART6_RX_USING_DMA) || \
|
||||
defined (BSP_UART7_RX_USING_DMA)
|
||||
defined (BSP_UART7_RX_USING_DMA) || defined (BSP_UART8_RX_USING_DMA) || defined (BSP_UART9_RX_USING_DMA) || \
|
||||
defined (BSP_UART10_RX_USING_DMA)
|
||||
static void hc32_uart_dma_rx_irq_handler(struct hc32_uart *uart)
|
||||
{
|
||||
rt_base_t level;
|
||||
|
|
@ -845,7 +879,7 @@ static void hc32_usart_handler(struct hc32_uart *uart)
|
|||
#endif
|
||||
|
||||
#if defined (BSP_USING_UART1)
|
||||
#if defined (HC32F460) || defined (HC32F4A0)
|
||||
#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8)
|
||||
static void hc32_uart1_rx_irq_handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
|
|
@ -878,7 +912,7 @@ static void hc32_uart1_rxerr_irq_handler(void)
|
|||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* HC32F460, HC32F4A0 */
|
||||
#endif
|
||||
|
||||
static void hc32_uart1_tc_irq_handler(void)
|
||||
{
|
||||
|
|
@ -893,7 +927,7 @@ static void hc32_uart1_tc_irq_handler(void)
|
|||
|
||||
#if defined (RT_SERIAL_USING_DMA)
|
||||
#if defined (BSP_UART1_RX_USING_DMA)
|
||||
#if defined (HC32F460) || defined (HC32F4A0)
|
||||
#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8)
|
||||
static void hc32_uart1_rxto_irq_handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
|
|
@ -904,7 +938,7 @@ static void hc32_uart1_rxto_irq_handler(void)
|
|||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* HC32F460, HC32F4A0 */
|
||||
#endif
|
||||
|
||||
static void hc32_uart1_dma_rx_irq_handler(void)
|
||||
{
|
||||
|
|
@ -941,11 +975,11 @@ void USART1_TxComplete_Handler(void)
|
|||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* HC32F448, HC32F472 */
|
||||
#endif
|
||||
#endif /* BSP_USING_UART1 */
|
||||
|
||||
#if defined (BSP_USING_UART2)
|
||||
#if defined (HC32F460) || defined (HC32F4A0)
|
||||
#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8)
|
||||
static void hc32_uart2_rx_irq_handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
|
|
@ -978,7 +1012,7 @@ static void hc32_uart2_rxerr_irq_handler(void)
|
|||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* HC32F460, HC32F4A0 */
|
||||
#endif
|
||||
|
||||
static void hc32_uart2_tc_irq_handler(void)
|
||||
{
|
||||
|
|
@ -993,7 +1027,7 @@ static void hc32_uart2_tc_irq_handler(void)
|
|||
|
||||
#if defined (RT_SERIAL_USING_DMA)
|
||||
#if defined (BSP_UART2_RX_USING_DMA)
|
||||
#if defined (HC32F460) || defined (HC32F4A0)
|
||||
#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8)
|
||||
static void hc32_uart2_rxto_irq_handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
|
|
@ -1004,7 +1038,7 @@ static void hc32_uart2_rxto_irq_handler(void)
|
|||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* HC32F460, HC32F4A0 */
|
||||
#endif
|
||||
|
||||
static void hc32_uart2_dma_rx_irq_handler(void)
|
||||
{
|
||||
|
|
@ -1041,11 +1075,11 @@ void USART2_TxComplete_Handler(void)
|
|||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* HC32F448, HC32F472 */
|
||||
#endif
|
||||
#endif /* BSP_USING_UART2 */
|
||||
|
||||
#if defined (BSP_USING_UART3)
|
||||
#if defined (HC32F460) || defined (HC32F4A0)
|
||||
#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8)
|
||||
static void hc32_uart3_rx_irq_handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
|
|
@ -1078,7 +1112,7 @@ static void hc32_uart3_rxerr_irq_handler(void)
|
|||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* HC32F460, HC32F4A0 */
|
||||
#endif
|
||||
|
||||
static void hc32_uart3_tc_irq_handler(void)
|
||||
{
|
||||
|
|
@ -1093,7 +1127,7 @@ static void hc32_uart3_tc_irq_handler(void)
|
|||
|
||||
#if defined (RT_SERIAL_USING_DMA)
|
||||
#if defined (BSP_UART3_RX_USING_DMA)
|
||||
#if defined (HC32F460) || defined (HC32F4A0)
|
||||
#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8)
|
||||
static void hc32_uart3_rxto_irq_handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
|
|
@ -1116,7 +1150,7 @@ static void hc32_uart3_dma_rx_irq_handler(void)
|
|||
rt_interrupt_leave();
|
||||
|
||||
}
|
||||
#endif /* HC32F460, HC32F4A0 */
|
||||
#endif
|
||||
#endif /* BSP_UART3_RX_USING_DMA */
|
||||
#endif /* RT_SERIAL_USING_DMA */
|
||||
|
||||
|
|
@ -1142,11 +1176,11 @@ void USART3_TxComplete_Handler(void)
|
|||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* HC32F448, HC32F472 */
|
||||
#endif
|
||||
#endif /* BSP_USING_UART3 */
|
||||
|
||||
#if defined (BSP_USING_UART4)
|
||||
#if defined (HC32F460) || defined (HC32F4A0)
|
||||
#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8)
|
||||
static void hc32_uart4_rx_irq_handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
|
|
@ -1179,7 +1213,7 @@ static void hc32_uart4_rxerr_irq_handler(void)
|
|||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* HC32F460, HC32F4A0 */
|
||||
#endif
|
||||
|
||||
static void hc32_uart4_tc_irq_handler(void)
|
||||
{
|
||||
|
|
@ -1194,7 +1228,7 @@ static void hc32_uart4_tc_irq_handler(void)
|
|||
|
||||
#if defined (RT_SERIAL_USING_DMA)
|
||||
#if defined (BSP_UART4_RX_USING_DMA)
|
||||
#if defined (HC32F460) || defined (HC32F4A0)
|
||||
#if defined (HC32F460) || defined (HC32F4A8)
|
||||
static void hc32_uart4_rxto_irq_handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
|
|
@ -1205,7 +1239,7 @@ static void hc32_uart4_rxto_irq_handler(void)
|
|||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* HC32F460, HC32F4A0 */
|
||||
#endif
|
||||
|
||||
static void hc32_uart4_dma_rx_irq_handler(void)
|
||||
{
|
||||
|
|
@ -1242,11 +1276,24 @@ void USART4_TxComplete_Handler(void)
|
|||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* HC32F448, HC32F472 */
|
||||
#endif
|
||||
#endif /* BSP_USING_UART4 */
|
||||
|
||||
#if defined (BSP_USING_UART5)
|
||||
#if defined (HC32F460) || defined (HC32F4A0)
|
||||
#if defined (HC32F4A0) || defined (HC32F4A8)
|
||||
#if defined (HC32F4A8)
|
||||
static void hc32_uart5_rxto_irq_handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
hc32_uart_rxto_irq_handler(&uart_obj[UART5_INDEX]);
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif
|
||||
|
||||
static void hc32_uart5_rx_irq_handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
|
|
@ -1279,7 +1326,7 @@ static void hc32_uart5_rxerr_irq_handler(void)
|
|||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* HC32F460, HC32F4A0 */
|
||||
#endif
|
||||
|
||||
static void hc32_uart5_tc_irq_handler(void)
|
||||
{
|
||||
|
|
@ -1329,11 +1376,11 @@ void USART5_TxComplete_Handler(void)
|
|||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* HC32F448, HC32F472 */
|
||||
#endif
|
||||
#endif /* BSP_USING_UART5 */
|
||||
|
||||
#if defined (BSP_USING_UART6)
|
||||
#if defined (HC32F460) || defined (HC32F4A0)
|
||||
#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8)
|
||||
static void hc32_uart6_rx_irq_handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
|
|
@ -1366,7 +1413,7 @@ static void hc32_uart6_rxerr_irq_handler(void)
|
|||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* HC32F460, HC32F4A0 */
|
||||
#endif
|
||||
|
||||
static void hc32_uart6_tc_irq_handler(void)
|
||||
{
|
||||
|
|
@ -1403,7 +1450,7 @@ static void hc32_uart6_dma_rx_irq_handler(void)
|
|||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* HC32F460, HC32F4A0 */
|
||||
#endif
|
||||
#endif /* BSP_UART6_RX_USING_DMA */
|
||||
#endif /* RT_SERIAL_USING_DMA */
|
||||
|
||||
|
|
@ -1429,7 +1476,7 @@ void USART6_TxComplete_Handler(void)
|
|||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* HC32F448, HC32F472 */
|
||||
#endif
|
||||
#endif /* BSP_USING_UART6 */
|
||||
|
||||
#if defined (BSP_USING_UART7)
|
||||
|
|
@ -1662,7 +1709,7 @@ static void hc32_uart_get_info(void)
|
|||
static struct dma_config uart1_dma_rx = UART1_DMA_RX_CONFIG;
|
||||
static struct hc32_uart_rxto uart1_rx_timeout = UART1_RXTO_CONFIG;
|
||||
uart1_dma_rx.irq_callback = hc32_uart1_dma_rx_irq_handler;
|
||||
#if defined (HC32F460) || defined (HC32F4A0)
|
||||
#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8)
|
||||
uart1_rx_timeout.irq_callback = hc32_uart1_rxto_irq_handler;
|
||||
#endif
|
||||
uart_config[UART1_INDEX].rx_timeout = &uart1_rx_timeout;
|
||||
|
|
@ -1685,7 +1732,7 @@ static void hc32_uart_get_info(void)
|
|||
static struct dma_config uart2_dma_rx = UART2_DMA_RX_CONFIG;
|
||||
static struct hc32_uart_rxto uart2_rx_timeout = UART2_RXTO_CONFIG;
|
||||
uart2_dma_rx.irq_callback = hc32_uart2_dma_rx_irq_handler;
|
||||
#if defined (HC32F460) || defined (HC32F4A0)
|
||||
#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8)
|
||||
uart2_rx_timeout.irq_callback = hc32_uart2_rxto_irq_handler;
|
||||
#endif
|
||||
uart_config[UART2_INDEX].rx_timeout = &uart2_rx_timeout;
|
||||
|
|
@ -1703,7 +1750,7 @@ static void hc32_uart_get_info(void)
|
|||
uart_obj[UART3_INDEX].serial.config = config;
|
||||
uart_obj[UART3_INDEX].serial.config.rx_bufsz = BSP_UART3_RX_BUFSIZE;
|
||||
uart_obj[UART3_INDEX].serial.config.tx_bufsz = BSP_UART3_TX_BUFSIZE;
|
||||
#if defined (HC32F460)
|
||||
#if defined (HC32F460) || defined (HC32F4A8)
|
||||
#ifdef BSP_UART3_RX_USING_DMA
|
||||
uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
|
||||
static struct dma_config uart3_dma_rx = UART3_DMA_RX_CONFIG;
|
||||
|
|
@ -1732,7 +1779,7 @@ static void hc32_uart_get_info(void)
|
|||
static struct dma_config uart4_dma_rx = UART4_DMA_RX_CONFIG;
|
||||
static struct hc32_uart_rxto uart4_rx_timeout = UART4_RXTO_CONFIG;
|
||||
uart4_dma_rx.irq_callback = hc32_uart4_dma_rx_irq_handler;
|
||||
#if defined (HC32F460)
|
||||
#if defined (HC32F460) || defined (HC32F4A8)
|
||||
uart4_rx_timeout.irq_callback = hc32_uart4_rxto_irq_handler;
|
||||
#endif
|
||||
uart_config[UART4_INDEX].rx_timeout = &uart4_rx_timeout;
|
||||
|
|
@ -1757,6 +1804,9 @@ static void hc32_uart_get_info(void)
|
|||
static struct dma_config uart5_dma_rx = UART5_DMA_RX_CONFIG;
|
||||
static struct hc32_uart_rxto uart5_rx_timeout = UART5_RXTO_CONFIG;
|
||||
uart5_dma_rx.irq_callback = hc32_uart5_dma_rx_irq_handler;
|
||||
#if defined (HC32F4A8)
|
||||
uart5_rx_timeout.irq_callback = hc32_uart5_rxto_irq_handler;
|
||||
#endif
|
||||
uart_config[UART5_INDEX].rx_timeout = &uart5_rx_timeout;
|
||||
uart_config[UART5_INDEX].dma_rx = &uart5_dma_rx;
|
||||
#endif
|
||||
|
|
@ -1836,7 +1886,7 @@ static void hc32_uart_get_info(void)
|
|||
#endif
|
||||
}
|
||||
|
||||
#if defined (HC32F460) || defined (HC32F4A0)
|
||||
#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8)
|
||||
/**
|
||||
* @brief This function gets uart irq handle.
|
||||
* @param None
|
||||
|
|
@ -1988,7 +2038,7 @@ int rt_hw_usart_init(void)
|
|||
/* init UART object */
|
||||
uart_obj[i].serial.ops = &hc32_uart_ops;
|
||||
uart_obj[i].config = &uart_config[i];
|
||||
#if defined (HC32F460) || defined (HC32F4A0)
|
||||
#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8)
|
||||
/* register the handle */
|
||||
hc32_install_irq_handler(&uart_config[i].rxerr_irq.irq_config, uart_config[i].rxerr_irq.irq_callback, RT_FALSE);
|
||||
#endif
|
||||
|
|
@ -1996,7 +2046,7 @@ int rt_hw_usart_init(void)
|
|||
if (uart_obj[i].uart_dma_flag & RT_DEVICE_FLAG_DMA_RX)
|
||||
{
|
||||
hc32_install_irq_handler(&uart_config[i].dma_rx->irq_config, uart_config[i].dma_rx->irq_callback, RT_FALSE);
|
||||
#if defined (HC32F460) || defined (HC32F4A0)
|
||||
#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8)
|
||||
hc32_install_irq_handler(&uart_config[i].rx_timeout->irq_config, uart_config[i].rx_timeout->irq_callback, RT_FALSE);
|
||||
#endif
|
||||
}
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@ struct hc32_uart_rxto
|
|||
rt_uint32_t channel;
|
||||
rt_uint32_t clock;
|
||||
rt_size_t timeout_bits;
|
||||
#if defined (HC32F460) || defined (HC32F4A0)
|
||||
#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8)
|
||||
struct hc32_irq_config irq_config;
|
||||
func_ptr_t irq_callback;
|
||||
#endif
|
||||
|
|
@ -53,7 +53,7 @@ struct hc32_uart_config
|
|||
const char *name;
|
||||
CM_USART_TypeDef *Instance;
|
||||
rt_uint32_t clock;
|
||||
#if defined (HC32F460) || defined (HC32F4A0)
|
||||
#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8)
|
||||
struct hc32_uart_irq_config rxerr_irq;
|
||||
struct hc32_uart_irq_config rx_irq;
|
||||
struct hc32_uart_irq_config tx_irq;
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@
|
|||
#include "dev_spi_flash_sfud.h"
|
||||
#endif
|
||||
|
||||
#if defined(HC32F4A0) || defined(HC32F448)
|
||||
#if defined(HC32F4A0) || defined(HC32F448) || defined(HC32F4A8)
|
||||
#define SPI_BUS_NAME "spi1"
|
||||
#define SPI_FLASH_DEVICE_NAME "spi10"
|
||||
#define SPI_FLASH_CHIP "w25q64"
|
||||
|
|
|
|||
|
|
@ -27,7 +27,7 @@
|
|||
#define BSP_TCA9539_I2C_BUS_NAME "i2c1"
|
||||
#define BSP_TCA9539_DEV_ADDR (0x74U)
|
||||
|
||||
#if defined(HC32F4A0)
|
||||
#if defined(HC32F4A0) || defined(HC32F4A8)
|
||||
#define TCA9539_RST_PIN (45) /* PC13 */
|
||||
#elif defined(HC32F448)
|
||||
#define TCA9539_RST_PIN (31) /* PB15 */
|
||||
|
|
|
|||
|
|
@ -43,7 +43,7 @@ if GetDepend(['BSP_USING_ADC']):
|
|||
if GetDepend(['BSP_USING_DAC']):
|
||||
src += ['test_dac.c']
|
||||
|
||||
if GetDepend(['BSP_USING_CAN']):
|
||||
if GetDepend(['BSP_USING_CAN']) or GetDepend(['BSP_USING_MCAN']):
|
||||
src += ['test_can.c']
|
||||
|
||||
if GetDepend(['BSP_USING_RTC']):
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue