From 980a376e9b56f2048a8cc1ae2002fa52ccbbb04d Mon Sep 17 00:00:00 2001 From: Wang Chen Date: Wed, 2 Apr 2025 15:04:51 +0800 Subject: [PATCH] bsp: k230: support canmv board Some changes to support canmv board, such as: - Address constant, some may need be set as configuration later. - link script - build script Signed-off-by: Wang Chen --- bsp/k230/board/board.c | 4 +- bsp/k230/board/board.h | 174 +++++++++++++++++++++++++++++++++++- bsp/k230/link.lds | 2 +- bsp/k230/link_stacksize.lds | 2 +- bsp/k230/rtconfig.py | 18 ++-- 5 files changed, 188 insertions(+), 12 deletions(-) diff --git a/bsp/k230/board/board.c b/bsp/k230/board/board.c index 14e35beee3..3ab1bd29a4 100644 --- a/bsp/k230/board/board.c +++ b/bsp/k230/board/board.c @@ -24,14 +24,14 @@ #include "page.h" /* respect to boot loader, must be 0xFFFFFFC000200000 */ -RT_STATIC_ASSERT(kmem_region, KERNEL_VADDR_START == 0xFFFFFFC000220000); +RT_STATIC_ASSERT(kmem_region, KERNEL_VADDR_START == 0xffffffc000020000); rt_region_t init_page_region = {(rt_size_t)RT_HW_PAGE_START, (rt_size_t)RT_HW_PAGE_END}; extern size_t MMUTable[]; struct mem_desc platform_mem_desc[] = { - {KERNEL_VADDR_START, (rt_size_t)RT_HW_PAGE_END - 1, (rt_size_t)ARCH_MAP_FAILED, NORMAL_MEM}, + {KERNEL_VADDR_START, (rt_size_t)0xFFFFFFC020000000 - 1, (rt_size_t)ARCH_MAP_FAILED, NORMAL_MEM}, }; #define NUM_MEM_DESC (sizeof(platform_mem_desc) / sizeof(platform_mem_desc[0])) diff --git a/bsp/k230/board/board.h b/bsp/k230/board/board.h index 1947c2b0bb..ebb6cf1eaf 100644 --- a/bsp/k230/board/board.h +++ b/bsp/k230/board/board.h @@ -16,13 +16,13 @@ extern unsigned int __sram_size; extern unsigned int __sram_base; extern unsigned int __sram_end; -#define RAM_END (rt_size_t)((void *)&__sram_end) +#define RAM_END (rt_size_t)((void *)&__sram_end) extern unsigned int __bss_start; extern unsigned int __bss_end; #define RT_HW_HEAP_BEGIN ((void *)&__bss_end) -#define RT_HW_HEAP_END ((void *)(((rt_size_t)RT_HW_HEAP_BEGIN) + 8 * 1024 * 1024)) +#define RT_HW_HEAP_END ((void *)(((rt_size_t)RT_HW_HEAP_BEGIN) + 0x2000000 )) #define RT_HW_PAGE_START ((void *)((rt_size_t)RT_HW_HEAP_END + sizeof(rt_size_t))) #define RT_HW_PAGE_END ((void *)(RAM_END)) @@ -30,4 +30,174 @@ extern unsigned int __bss_end; void rt_hw_board_init(void); void rt_init_user_mem(struct rt_thread *thread, const char *name, unsigned long *entry); +#define TIMER_CLK_FREQ (27000000) + +/* From K230 Technical Reference Manual, chapter 1.5 Address Space mapping */ +#define SRAM_BASE_ADDR (0x80200000UL) +#define SRAM_IO_SIZE (0x00200000UL) + +#define KPU_BASE_ADDR (0x80400000UL) +#define KPU_IO_SIZE (0x00000800UL) + +#define FFT_BASE_ADDR (0x80400800UL) +#define FFT_IO_SIZE (0x00000400UL) + +#define AI2D_BASE_ADDR (0x80400C00UL) +#define AI2D_IO_SIZE (0x00000400UL) + +#define GSDMA_BASE_ADDR (0x80800000UL) +#define GSDMA_IO_SIZE (0x00004000UL) + +#define DMA_BASE_ADDR (0x80804000UL) +#define DMA_IO_SIZE (0x00004000UL) + +#define DECOMP_BASE_ADDR (0x80808000UL) +#define DECOMP_IO_SIZE (0x00004000UL) + +#define NON_AI2D_BASE_ADDR (0x8080C000UL) +#define NON_AI2D_IO_SIZE (0x00004000UL) + +#define ISP_BASE_ADDR (0x90000000UL) +#define ISP_IO_SIZE (0x00008000UL) + +#define DEWARP_BASE_ADDR (0x90008000UL) +#define DEWARP_IO_SIZE (0x00001000UL) + +#define CSI_BASE_ADDR (0x90009000UL) +#define CSI_IO_SIZE (0x00002000UL) + +#define VPU_BASE_ADDR (0x90400000UL) +#define VPU_IO_SIZE (0x00010000UL) + +/*2.5D*/ +#define TAAH_GPU_BASE_ADDR (0x90800000UL) +#define TAAH_GPU_IO_SIZE (0x00040000UL) + +#define VO_BASE_ADDR (0x90840000UL) +#define VO_IO_SIZE (0x00010000UL) + +#define DSI_BASE_ADDR (0x90850000UL) +#define DSI_IO_SIZE (0x00001000UL) + +#define GPU_ENGINE_BASE_ADDR (0x90A00000UL) +#define GPU_ENGINE_IO_SIZE (0x00000800UL) + +#define PMU_BASE_ADDR (0x91000000UL) +#define PMU_IO_SIZE (0x00000C00UL) + +#define RTC_BASE_ADDR (0x91000C00UL) +#define RTC_IO_SIZE (0x00000400UL) + +#define CMU_BASE_ADDR (0x91100000UL) +#define CMU_IO_SIZE (0x00001000UL) + +#define RMU_BASE_ADDR (0x91101000UL) +#define RMU_IO_SIZE (0x00001000UL) + +#define BOOT_BASE_ADDR (0x91102000UL) +#define BOOT_IO_SIZE (0x00001000UL) + +#define PWR_BASE_ADDR (0x91103000UL) +#define PWR_IO_SIZE (0x00001000UL) + +#define MAILBOX_BASE_ADDR (0x91104000UL) +#define MAILBOX_IO_SIZE (0x00001000UL) + +#define IOMUX_BASE_ADDR (0x91105000UL) +#define IOMUX_IO_SIZE (0x00000800UL) + +#define HW_TIMER_BASE_ADDR (0x91105800UL) +#define HW_TIMER_IO_SIZE (0x00000800UL) + +#define WDT0_BASE_ADDR (0x91106000UL) +#define WDT0_IO_SIZE (0x00000800UL) + +#define WDT1_BASE_ADDR (0x91106800UL) +#define WDT1_IO_SIZE (0x00000800UL) + +#define TS_BASE_ADDR (0x91107000UL) +#define TS_IO_SIZE (0x00000800UL) + +#define HDI_BASE_ADDR (0x91107800UL) +#define HDI_IO_SIZE (0x00000800UL) + +#define STC_BASE_ADDR (0x91108000UL) +#define STC_IO_SIZE (0x00001000UL) + +#define BOOTROM_BASE_ADDR (0x91200000UL) +#define BOOTROM_IO_SIZE (0x00010000UL) + +#define SECURITY_BASE_ADDR (0x91210000UL) +#define SECURITY_IO_SIZE (0x00008000UL) + +#define UART0_BASE_ADDR (0x91400000UL) +#define UART0_IO_SIZE (0x00001000UL) + +#define UART1_BASE_ADDR (0x91401000UL) +#define UART1_IO_SIZE (0x00001000UL) + +#define UART2_BASE_ADDR (0x91402000UL) +#define UART2_IO_SIZE (0x00001000UL) + +#define UART3_BASE_ADDR (0x91403000UL) +#define UART3_IO_SIZE (0x00001000UL) + +#define UART4_BASE_ADDR (0x91404000UL) +#define UART4_IO_SIZE (0x00001000UL) + +#define I2C0_BASE_ADDR (0x91405000UL) +#define I2C0_IO_SIZE (0x00001000UL) + +#define I2C1_BASE_ADDR (0x91406000UL) +#define I2C1_IO_SIZE (0x00001000UL) + +#define I2C2_BASE_ADDR (0x91407000UL) +#define I2C2_IO_SIZE (0x00001000UL) + +#define I2C3_BASE_ADDR (0x91408000UL) +#define I2C3_IO_SIZE (0x00001000UL) + +#define I2C4_BASE_ADDR (0x91409000UL) +#define I2C4_IO_SIZE (0x00001000UL) + +#define PWM_BASE_ADDR (0x9140A000UL) +#define PWM_IO_SIZE (0x00001000UL) + +#define GPIO0_BASE_ADDR (0x9140B000UL) +#define GPIO0_IO_SIZE (0x00001000UL) + +#define GPIO1_BASE_ADDR (0x9140C000UL) +#define GPIO1_IO_SIZE (0x00001000UL) + +#define ADC_BASE_ADDR (0x9140D000UL) +#define ADC_IO_SIZE (0x00001000UL) + +#define CODEC_BASE_ADDR (0x9140E000UL) +#define CODEC_IO_SIZE (0x00001000UL) + +#define AUDIO_BASE_ADDR (0x9140F000UL) +#define AUDIO_IO_SIZE (0x00001000UL) + +#define USB2_BASE_ADDR (0x91500000UL) +#define USB2_IO_SIZE (0x00080000UL) + +#define SD_HC_BASE_ADDR (0x91580000UL) +#define SD_HC_IO_SIZE (0x00002000UL) + +#define SPI_QOPI_BASE_ADDR (0x91582000UL) +#define SPI_QOPI_IO_SIZE (0x00002000UL) + +#define SPI_OPI_BASE_ADDR (0x91584000UL) +#define SPI_OPI_IO_SIZE (0x00001000UL) + +#define HI_SYS_CONFIG_BASE_ADDR (0x91585000UL) +#define HI_SYS_CONFIG_IO_SIZE (0x00000400UL) + +#define DDRC_CONF_BASE_ADDR (0x98000000UL) +#define DDRC_CONF_IO_SIZE (0x02000000UL) + +#define SPI_XIP_FLASH_BASE_ADDR (0xC0000000UL) +#define SPI_XIP_FLASH_IO_SIZE (0x08000000UL) + +#define IO_SPACE_BASE_ADDR (KPU_BASE_ADDR) #endif diff --git a/bsp/k230/link.lds b/bsp/k230/link.lds index ad731cd615..3f3818cdd7 100644 --- a/bsp/k230/link.lds +++ b/bsp/k230/link.lds @@ -22,7 +22,7 @@ OUTPUT_ARCH( "riscv" ) MEMORY { - SRAM(wx) : ORIGIN = 0xFFFFFFC000220000, LENGTH = 64M - 128K + SRAM : ORIGIN = 0xffffffc000020000, LENGTH = 262012K } ENTRY(_start) diff --git a/bsp/k230/link_stacksize.lds b/bsp/k230/link_stacksize.lds index 13e6ee8b1c..89ab4af217 100644 --- a/bsp/k230/link_stacksize.lds +++ b/bsp/k230/link_stacksize.lds @@ -1 +1 @@ -__STACKSIZE__ = 8192; \ No newline at end of file +__STACKSIZE__ = 65536; \ No newline at end of file diff --git a/bsp/k230/rtconfig.py b/bsp/k230/rtconfig.py index 5d7f5b3b21..4cd6df869a 100644 --- a/bsp/k230/rtconfig.py +++ b/bsp/k230/rtconfig.py @@ -1,4 +1,5 @@ import os +import re # toolchains options ARCH ='risc-v' @@ -13,14 +14,18 @@ if os.getenv('RTT_CC'): if CROSS_TOOL == 'gcc': PLATFORM = 'gcc' - EXEC_PATH = r'/opt/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1/bin' + EXEC_PATH = r'/opt/toolchain/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu_rtt/bin' else: print('Please make sure your toolchains is GNU GCC!') exit(0) -EXEC_PATH = os.getenv('RTT_EXEC_PATH', EXEC_PATH) +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') -BUILD = 'debug' +if re.match("-DDBGLV=0", os.getenv('KCFLAGS', '-DDBGLV=0')): + BUILD = 'release' +else: + BUILD = 'debug' if PLATFORM == 'gcc': # toolchains @@ -36,7 +41,7 @@ if PLATFORM == 'gcc': OBJDUMP = PREFIX + 'objdump' OBJCPY = PREFIX + 'objcopy' - DEVICE = ' -mcmodel=medany -march=rv64imafdc -mabi=lp64' + DEVICE = ' -mcmodel=medany -march=rv64imafdcv -mabi=lp64d' CFLAGS = DEVICE + ' -Wno-cpp -fvar-tracking -ffreestanding -fno-common -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -D_POSIX_SOURCE ' AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -D__ASSEMBLY__' LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T link.lds' + ' -lsupc++ -lgcc -static' @@ -44,10 +49,11 @@ if PLATFORM == 'gcc': LPATH = '' if BUILD == 'debug': - CFLAGS += ' -O2 -g -gdwarf-2' - AFLAGS += ' -g -gdwarf-2' + CFLAGS += ' -O0 -gdwarf-2' + AFLAGS += ' -gdwarf-2' else: CFLAGS += ' -O2 -g -gdwarf-2' + CFLAGS += ' ' + os.getenv('KCFLAGS', '-DDBGLV=0') CXXFLAGS = CFLAGS