delete swm320-lq100 bsp

This commit is contained in:
yanmowudi 2022-02-11 14:49:32 +08:00 committed by guo
parent 0c35b803fa
commit 98b98124c7
134 changed files with 15 additions and 46848 deletions

View File

@ -147,7 +147,6 @@ jobs:
- {RTT_BSP: "wch/arm/ch32f103c8-core", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "wch/arm/ch32f203r-evt", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "swm320", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "swm320-lq100", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "beaglebone", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "zynqmp-r5-axu4ev", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "frdm-k64f", RTT_TOOL_CHAIN: "sourcery-arm"}

1
Jenkinsfile vendored
View File

@ -104,7 +104,6 @@ pipeline {
// ['stm32/stm32l496-ali-developer', 'sourcery-arm'], /* CI compile C99 not support */
// ['stm32/stm32l496-st-nucleo', 'sourcery-arm'], /* CI compile C99 not support */
['stm32f20x', 'sourcery-arm'],
['swm320-lq100', 'sourcery-arm'],
['beaglebone', 'sourcery-arm'],
['frdm-k64f', 'sourcery-arm'],
['xplorer4330/M4', 'sourcery-arm'],

View File

@ -705,7 +705,6 @@ Path:
bsp 列表:
- swm320
- swm320-lq100
------
@ -716,7 +715,6 @@ Copyright: COPYRIGHT 2012 Synwit Technology
Path:
- bsp/swm320/libraries/CMSIS/DeviceSupport
- bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver
------
@ -727,7 +725,6 @@ Copyright: Copyright (c) 2009 - 2014 ARM LIMITED
Path:
- bsp/swm320/libraries/CMSIS
- bsp/swm320-lq100/Libraries/CMSIS/CoreSupport
### tae32f5300

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@ -1,690 +0,0 @@
#
# Automatically generated file; DO NOT EDIT.
# RT-Thread Configuration
#
#
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=8
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=1000
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
CONFIG_RT_HOOK_USING_FUNC_PTR=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=256
# CONFIG_RT_USING_TIMER_SOFT is not set
#
# kservice optimization
#
# CONFIG_RT_KSERVICE_USING_STDLIB is not set
# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
# CONFIG_RT_USING_TINY_FFS is not set
# CONFIG_RT_PRINTF_LONGLONG is not set
CONFIG_RT_DEBUG=y
CONFIG_RT_DEBUG_COLOR=y
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
#
# Inter-Thread communication
#
CONFIG_RT_USING_SEMAPHORE=y
CONFIG_RT_USING_MUTEX=y
CONFIG_RT_USING_EVENT=y
CONFIG_RT_USING_MAILBOX=y
CONFIG_RT_USING_MESSAGEQUEUE=y
# CONFIG_RT_USING_SIGNALS is not set
#
# Memory Management
#
CONFIG_RT_USING_MEMPOOL=y
# CONFIG_RT_USING_SMALL_MEM is not set
# CONFIG_RT_USING_SLAB is not set
CONFIG_RT_USING_MEMHEAP=y
CONFIG_RT_MEMHEAP_FAST_MODE=y
# CONFIG_RT_MEMHEAP_BSET_MODE is not set
# CONFIG_RT_USING_SMALL_MEM_AS_HEAP is not set
CONFIG_RT_USING_MEMHEAP_AS_HEAP=y
CONFIG_RT_USING_MEMHEAP_AUTO_BINDING=y
# CONFIG_RT_USING_SLAB_AS_HEAP is not set
# CONFIG_RT_USING_USERHEAP is not set
# CONFIG_RT_USING_NOHEAP is not set
# CONFIG_RT_USING_MEMTRACE is not set
# CONFIG_RT_USING_HEAP_ISR is not set
CONFIG_RT_USING_HEAP=y
#
# Kernel Device Object
#
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_DEVICE_OPS is not set
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
CONFIG_RT_VER_NUM=0x40100
CONFIG_ARCH_ARM=y
CONFIG_RT_USING_CPU_FFS=y
CONFIG_ARCH_ARM_CORTEX_M=y
CONFIG_ARCH_ARM_CORTEX_M4=y
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
#
# RT-Thread Components
#
CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
CONFIG_RT_MAIN_THREAD_PRIORITY=10
# CONFIG_RT_USING_LEGACY is not set
#
# C++ features
#
# CONFIG_RT_USING_CPLUSPLUS is not set
#
# Command shell
#
CONFIG_RT_USING_FINSH=y
CONFIG_RT_USING_MSH=y
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_THREAD_NAME="tshell"
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_CMD_SIZE=80
CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_ARG_MAX=10
#
# Device virtual file system
#
# CONFIG_RT_USING_DFS is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
CONFIG_RT_USING_SERIAL=y
CONFIG_RT_USING_SERIAL_V1=y
# CONFIG_RT_USING_SERIAL_V2 is not set
# CONFIG_RT_SERIAL_USING_DMA is not set
CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
# CONFIG_RT_USING_PHY is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
# CONFIG_RT_USING_TOUCH is not set
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_PULSE_ENCODER is not set
# CONFIG_RT_USING_INPUT_CAPTURE is not set
# CONFIG_RT_USING_WIFI is not set
#
# Using USB
#
# CONFIG_RT_USING_USB is not set
# CONFIG_RT_USING_USB_HOST is not set
# CONFIG_RT_USING_USB_DEVICE is not set
#
# POSIX layer and C standard library
#
CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
#
# POSIX (Portable Operating System Interface) layer
#
# CONFIG_RT_USING_POSIX_FS is not set
# CONFIG_RT_USING_POSIX_DELAY is not set
# CONFIG_RT_USING_POSIX_CLOCK is not set
# CONFIG_RT_USING_POSIX_TIMER is not set
# CONFIG_RT_USING_PTHREADS is not set
# CONFIG_RT_USING_MODULE is not set
#
# Interprocess Communication (IPC)
#
# CONFIG_RT_USING_POSIX_PIPE is not set
# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
#
# Socket is in the 'Network' category
#
#
# Network
#
#
# Socket abstraction layer
#
# CONFIG_RT_USING_SAL is not set
#
# Network interface device
#
# CONFIG_RT_USING_NETDEV is not set
#
# light weight TCP/IP stack
#
# CONFIG_RT_USING_LWIP is not set
#
# AT commands
#
# CONFIG_RT_USING_AT is not set
#
# VBUS(Virtual Software BUS)
#
# CONFIG_RT_USING_VBUS is not set
#
# Utilities
#
# CONFIG_RT_USING_RYM is not set
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
# CONFIG_RT_USING_VAR_EXPORT is not set
# CONFIG_RT_USING_RT_LINK is not set
# CONFIG_RT_USING_LWP is not set
#
# RT-Thread Utestcases
#
# CONFIG_RT_USING_UTESTCASES is not set
#
# RT-Thread online packages
#
#
# IoT - internet of things
#
# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_UMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_WEBNET is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_MYMQTT is not set
# CONFIG_PKG_USING_KAWAII_MQTT is not set
# CONFIG_PKG_USING_BC28_MQTT is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_LIBMODBUS is not set
# CONFIG_PKG_USING_FREEMODBUS is not set
# CONFIG_PKG_USING_LJSON is not set
# CONFIG_PKG_USING_EZXML is not set
# CONFIG_PKG_USING_NANOPB is not set
#
# Wi-Fi
#
#
# Marvell WiFi
#
# CONFIG_PKG_USING_WLANMARVELL is not set
#
# Wiced WiFi
#
# CONFIG_PKG_USING_WLAN_WICED is not set
# CONFIG_PKG_USING_RW007 is not set
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_CMUX is not set
# CONFIG_PKG_USING_PPP_DEVICE is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
# CONFIG_PKG_USING_ATSRV_SOCKET is not set
# CONFIG_PKG_USING_WIZNET is not set
# CONFIG_PKG_USING_ZB_COORDINATOR is not set
#
# IoT Cloud
#
# CONFIG_PKG_USING_ONENET is not set
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
# CONFIG_PKG_USING_JOYLINK is not set
# CONFIG_PKG_USING_EZ_IOT_OS is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
# CONFIG_PKG_USING_IPMSG is not set
# CONFIG_PKG_USING_LSSDP is not set
# CONFIG_PKG_USING_AIRKISS_OPEN is not set
# CONFIG_PKG_USING_LIBRWS is not set
# CONFIG_PKG_USING_TCPSERVER is not set
# CONFIG_PKG_USING_PROTOBUF_C is not set
# CONFIG_PKG_USING_DLT645 is not set
# CONFIG_PKG_USING_QXWZ is not set
# CONFIG_PKG_USING_SMTP_CLIENT is not set
# CONFIG_PKG_USING_ABUP_FOTA is not set
# CONFIG_PKG_USING_LIBCURL2RTT is not set
# CONFIG_PKG_USING_CAPNP is not set
# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
# CONFIG_PKG_USING_AGILE_TELNET is not set
# CONFIG_PKG_USING_NMEALIB is not set
# CONFIG_PKG_USING_AGILE_JSMN is not set
# CONFIG_PKG_USING_PDULIB is not set
# CONFIG_PKG_USING_BTSTACK is not set
# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
# CONFIG_PKG_USING_MAVLINK is not set
# CONFIG_PKG_USING_RAPIDJSON is not set
# CONFIG_PKG_USING_BSAL is not set
# CONFIG_PKG_USING_AGILE_MODBUS is not set
# CONFIG_PKG_USING_AGILE_FTP is not set
# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
# CONFIG_PKG_USING_RT_LINK_HW is not set
# CONFIG_PKG_USING_LORA_PKT_FWD is not set
# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
# CONFIG_PKG_USING_HM is not set
# CONFIG_PKG_USING_SMALL_MODBUS is not set
# CONFIG_PKG_USING_NET_SERVER is not set
#
# security packages
#
# CONFIG_PKG_USING_MBEDTLS is not set
# CONFIG_PKG_USING_LIBSODIUM is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
# CONFIG_PKG_USING_TFM is not set
# CONFIG_PKG_USING_YD_CRYPTO is not set
#
# language packages
#
# CONFIG_PKG_USING_LUATOS_SOC is not set
# CONFIG_PKG_USING_LUA is not set
# CONFIG_PKG_USING_JERRYSCRIPT is not set
# CONFIG_PKG_USING_MICROPYTHON is not set
# CONFIG_PKG_USING_PIKASCRIPT is not set
#
# multimedia packages
#
#
# LVGL: powerful and easy-to-use embedded GUI library
#
# CONFIG_PKG_USING_LVGL is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
#
# u8g2: a monochrome graphic library
#
# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
# CONFIG_PKG_USING_U8G2 is not set
# CONFIG_PKG_USING_OPENMV is not set
# CONFIG_PKG_USING_MUPDF is not set
# CONFIG_PKG_USING_STEMWIN is not set
# CONFIG_PKG_USING_WAVPLAYER is not set
# CONFIG_PKG_USING_TJPGD is not set
# CONFIG_PKG_USING_PDFGEN is not set
# CONFIG_PKG_USING_HELIX is not set
# CONFIG_PKG_USING_AZUREGUIX is not set
# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
# CONFIG_PKG_USING_NUEMWIN is not set
# CONFIG_PKG_USING_MP3PLAYER is not set
# CONFIG_PKG_USING_TINYJPEG is not set
# CONFIG_PKG_USING_UGUI is not set
#
# PainterEngine: A cross-platform graphics application framework written in C language
#
# CONFIG_PKG_USING_PAINTERENGINE is not set
# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
# CONFIG_PKG_USING_MCURSES is not set
# CONFIG_PKG_USING_TERMBOX is not set
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_QRCODE is not set
#
# tools packages
#
# CONFIG_PKG_USING_CMBACKTRACE is not set
# CONFIG_PKG_USING_EASYFLASH is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_SEGGER_RTT is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ULOG_FILE is not set
# CONFIG_PKG_USING_LOGMGR is not set
# CONFIG_PKG_USING_ADBD is not set
# CONFIG_PKG_USING_COREMARK is not set
# CONFIG_PKG_USING_DHRYSTONE is not set
# CONFIG_PKG_USING_MEMORYPERF is not set
# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
# CONFIG_PKG_USING_BS8116A is not set
# CONFIG_PKG_USING_GPS_RMC is not set
# CONFIG_PKG_USING_URLENCODE is not set
# CONFIG_PKG_USING_UMCN is not set
# CONFIG_PKG_USING_LWRB2RTT is not set
# CONFIG_PKG_USING_CPU_USAGE is not set
# CONFIG_PKG_USING_GBK2UTF8 is not set
# CONFIG_PKG_USING_VCONSOLE is not set
# CONFIG_PKG_USING_KDB is not set
# CONFIG_PKG_USING_WAMR is not set
# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
# CONFIG_PKG_USING_LWLOG is not set
# CONFIG_PKG_USING_ANV_TRACE is not set
# CONFIG_PKG_USING_ANV_MEMLEAK is not set
# CONFIG_PKG_USING_ANV_TESTSUIT is not set
# CONFIG_PKG_USING_ANV_BENCH is not set
# CONFIG_PKG_USING_DEVMEM is not set
# CONFIG_PKG_USING_REGEX is not set
# CONFIG_PKG_USING_MEM_SANDBOX is not set
# CONFIG_PKG_USING_SOLAR_TERMS is not set
# CONFIG_PKG_USING_GAN_ZHI is not set
# CONFIG_PKG_USING_FDT is not set
#
# system packages
#
#
# enhanced kernel services
#
# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
#
# POSIX extension functions
#
# CONFIG_PKG_USING_POSIX_GETLINE is not set
# CONFIG_PKG_USING_POSIX_WCWIDTH is not set
# CONFIG_PKG_USING_POSIX_ITOA is not set
# CONFIG_PKG_USING_POSIX_STRINGS is not set
#
# acceleration: Assembly language or algorithmic acceleration packages
#
# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
# CONFIG_PKG_USING_QFPLIB_M3 is not set
#
# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
#
# CONFIG_PKG_USING_CMSIS_5 is not set
# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
#
# Micrium: Micrium software products porting for RT-Thread
#
# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
# CONFIG_PKG_USING_UC_CRC is not set
# CONFIG_PKG_USING_UC_CLK is not set
# CONFIG_PKG_USING_UC_COMMON is not set
# CONFIG_PKG_USING_UC_MODBUS is not set
# CONFIG_RT_USING_ARDUINO is not set
# CONFIG_PKG_USING_GUIENGINE is not set
# CONFIG_PKG_USING_PERSIMMON is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_FAL is not set
# CONFIG_PKG_USING_FLASHDB is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
# CONFIG_PKG_USING_DFS_JFFS2 is not set
# CONFIG_PKG_USING_DFS_UFFS is not set
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_THREAD_POOL is not set
# CONFIG_PKG_USING_ROBOTS is not set
# CONFIG_PKG_USING_EV is not set
# CONFIG_PKG_USING_SYSWATCH is not set
# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
# CONFIG_PKG_USING_PLCCORE is not set
# CONFIG_PKG_USING_RAMDISK is not set
# CONFIG_PKG_USING_MININI is not set
# CONFIG_PKG_USING_QBOOT is not set
# CONFIG_PKG_USING_PPOOL is not set
# CONFIG_PKG_USING_OPENAMP is not set
# CONFIG_PKG_USING_LPM is not set
# CONFIG_PKG_USING_TLSF is not set
# CONFIG_PKG_USING_EVENT_RECORDER is not set
# CONFIG_PKG_USING_ARM_2D is not set
# CONFIG_PKG_USING_MCUBOOT is not set
# CONFIG_PKG_USING_TINYUSB is not set
# CONFIG_PKG_USING_USB_STACK is not set
#
# peripheral libraries and drivers
#
# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_SHT3X is not set
# CONFIG_PKG_USING_AS7341 is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_SX12XX is not set
# CONFIG_PKG_USING_SIGNAL_LED is not set
# CONFIG_PKG_USING_LEDBLINK is not set
# CONFIG_PKG_USING_LITTLED is not set
# CONFIG_PKG_USING_LKDGUI is not set
# CONFIG_PKG_USING_NRF5X_SDK is not set
# CONFIG_PKG_USING_NRFX is not set
# CONFIG_PKG_USING_WM_LIBRARIES is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_INFRARED is not set
# CONFIG_PKG_USING_AGILE_BUTTON is not set
# CONFIG_PKG_USING_AGILE_LED is not set
# CONFIG_PKG_USING_AT24CXX is not set
# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_PCA9685 is not set
# CONFIG_PKG_USING_I2C_TOOLS is not set
# CONFIG_PKG_USING_NRF24L01 is not set
# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
# CONFIG_PKG_USING_MAX17048 is not set
# CONFIG_PKG_USING_RPLIDAR is not set
# CONFIG_PKG_USING_AS608 is not set
# CONFIG_PKG_USING_RC522 is not set
# CONFIG_PKG_USING_WS2812B is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
# CONFIG_PKG_USING_MULTI_RTIMER is not set
# CONFIG_PKG_USING_MAX7219 is not set
# CONFIG_PKG_USING_BEEP is not set
# CONFIG_PKG_USING_EASYBLINK is not set
# CONFIG_PKG_USING_PMS_SERIES is not set
# CONFIG_PKG_USING_CAN_YMODEM is not set
# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
# CONFIG_PKG_USING_QLED is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_AGILE_CONSOLE is not set
# CONFIG_PKG_USING_LD3320 is not set
# CONFIG_PKG_USING_WK2124 is not set
# CONFIG_PKG_USING_LY68L6400 is not set
# CONFIG_PKG_USING_DM9051 is not set
# CONFIG_PKG_USING_SSD1306 is not set
# CONFIG_PKG_USING_QKEY is not set
# CONFIG_PKG_USING_RS485 is not set
# CONFIG_PKG_USING_RS232 is not set
# CONFIG_PKG_USING_NES is not set
# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
# CONFIG_PKG_USING_VDEVICE is not set
# CONFIG_PKG_USING_SGM706 is not set
# CONFIG_PKG_USING_STM32WB55_SDK is not set
# CONFIG_PKG_USING_RDA58XX is not set
# CONFIG_PKG_USING_LIBNFC is not set
# CONFIG_PKG_USING_MFOC is not set
# CONFIG_PKG_USING_TMC51XX is not set
# CONFIG_PKG_USING_TCA9534 is not set
# CONFIG_PKG_USING_KOBUKI is not set
# CONFIG_PKG_USING_ROSSERIAL is not set
# CONFIG_PKG_USING_MICRO_ROS is not set
# CONFIG_PKG_USING_MCP23008 is not set
# CONFIG_PKG_USING_BLUETRUM_SDK is not set
# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
# CONFIG_PKG_USING_BL_MCU_SDK is not set
# CONFIG_PKG_USING_SOFT_SERIAL is not set
# CONFIG_PKG_USING_MB85RS16 is not set
# CONFIG_PKG_USING_CW2015 is not set
#
# AI packages
#
# CONFIG_PKG_USING_LIBANN is not set
# CONFIG_PKG_USING_NNOM is not set
# CONFIG_PKG_USING_ONNX_BACKEND is not set
# CONFIG_PKG_USING_ONNX_PARSER is not set
# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
# CONFIG_PKG_USING_ELAPACK is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_QUEST is not set
# CONFIG_PKG_USING_NAXOS is not set
#
# miscellaneous packages
#
#
# samples: kernel and components samples
#
# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
#
# entertainment: terminal games and other interesting software packages
#
# CONFIG_PKG_USING_CMATRIX is not set
# CONFIG_PKG_USING_SL is not set
# CONFIG_PKG_USING_CAL is not set
# CONFIG_PKG_USING_ACLOCK is not set
# CONFIG_PKG_USING_THREES is not set
# CONFIG_PKG_USING_2048 is not set
# CONFIG_PKG_USING_SNAKE is not set
# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_DONUT is not set
# CONFIG_PKG_USING_COWSAY is not set
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
# CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_LZMA is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_MINIZIP is not set
# CONFIG_PKG_USING_DSTR is not set
# CONFIG_PKG_USING_TINYFRAME is not set
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
# CONFIG_PKG_USING_DIGITALCTRL is not set
# CONFIG_PKG_USING_UPACKER is not set
# CONFIG_PKG_USING_UPARAM is not set
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_VI is not set
# CONFIG_PKG_USING_KI is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_CRCLIB is not set
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_STATE_MACHINE is not set
# CONFIG_PKG_USING_DESIGN_PATTERN is not set
# CONFIG_PKG_USING_CONTROLLER is not set
# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
#
# Hardware Drivers Config
#
CONFIG_SOC_SWM320=y
#
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_UART=y
CONFIG_BSP_USING_UART0=y
# CONFIG_BSP_USING_UART1 is not set
# CONFIG_BSP_USING_UART2 is not set
# CONFIG_BSP_USING_UART3 is not set
CONFIG_BSP_USING_GPIO=y
# CONFIG_BSP_USING_ADC is not set
# CONFIG_BSP_USING_TIM is not set
# CONFIG_BSP_USING_I2C is not set
# CONFIG_BSP_USING_PWM is not set
# CONFIG_BSP_USING_RTC is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_WDT is not set
# CONFIG_BSP_USING_CRC is not set
#
# Onboard Peripheral Drivers
#
# CONFIG_BSP_USING_SDIO is not set
# CONFIG_BSP_USING_EXT_SRAM is not set
# CONFIG_BSP_USING_NOR_FLASH is not set
#
# Offboard Peripheral Drivers
#

View File

@ -1,25 +0,0 @@
mainmenu "RT-Thread Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config RTT_DIR
string
option env="RTT_ROOT"
default "../.."
config PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
source "drivers/Kconfig"
config SOC_SWM320
bool
select ARCH_ARM_CORTEX_M4
default y

View File

@ -1,135 +0,0 @@
/* ----------------------------------------------------------------------
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
*
* $Date: 31. July 2014
* $Revision: V1.4.4
*
* Project: CMSIS DSP Library
* Title: arm_common_tables.h
*
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
*
* Target Processor: Cortex-M4/Cortex-M3
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */
#ifndef _ARM_COMMON_TABLES_H
#define _ARM_COMMON_TABLES_H
#include "arm_math.h"
extern const uint16_t armBitRevTable[1024];
extern const q15_t armRecipTableQ15[64];
extern const q31_t armRecipTableQ31[64];
//extern const q31_t realCoefAQ31[1024];
//extern const q31_t realCoefBQ31[1024];
extern const float32_t twiddleCoef_16[32];
extern const float32_t twiddleCoef_32[64];
extern const float32_t twiddleCoef_64[128];
extern const float32_t twiddleCoef_128[256];
extern const float32_t twiddleCoef_256[512];
extern const float32_t twiddleCoef_512[1024];
extern const float32_t twiddleCoef_1024[2048];
extern const float32_t twiddleCoef_2048[4096];
extern const float32_t twiddleCoef_4096[8192];
#define twiddleCoef twiddleCoef_4096
extern const q31_t twiddleCoef_16_q31[24];
extern const q31_t twiddleCoef_32_q31[48];
extern const q31_t twiddleCoef_64_q31[96];
extern const q31_t twiddleCoef_128_q31[192];
extern const q31_t twiddleCoef_256_q31[384];
extern const q31_t twiddleCoef_512_q31[768];
extern const q31_t twiddleCoef_1024_q31[1536];
extern const q31_t twiddleCoef_2048_q31[3072];
extern const q31_t twiddleCoef_4096_q31[6144];
extern const q15_t twiddleCoef_16_q15[24];
extern const q15_t twiddleCoef_32_q15[48];
extern const q15_t twiddleCoef_64_q15[96];
extern const q15_t twiddleCoef_128_q15[192];
extern const q15_t twiddleCoef_256_q15[384];
extern const q15_t twiddleCoef_512_q15[768];
extern const q15_t twiddleCoef_1024_q15[1536];
extern const q15_t twiddleCoef_2048_q15[3072];
extern const q15_t twiddleCoef_4096_q15[6144];
extern const float32_t twiddleCoef_rfft_32[32];
extern const float32_t twiddleCoef_rfft_64[64];
extern const float32_t twiddleCoef_rfft_128[128];
extern const float32_t twiddleCoef_rfft_256[256];
extern const float32_t twiddleCoef_rfft_512[512];
extern const float32_t twiddleCoef_rfft_1024[1024];
extern const float32_t twiddleCoef_rfft_2048[2048];
extern const float32_t twiddleCoef_rfft_4096[4096];
/* floating-point bit reversal tables */
#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20)
#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48)
#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56)
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
/* fixed-point bit reversal tables */
#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12)
#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24)
#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56)
#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112)
#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240)
#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480)
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
/* Tables for Fast Math Sine and Cosine */
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
#endif /* ARM_COMMON_TABLES_H */

View File

@ -1,79 +0,0 @@
/* ----------------------------------------------------------------------
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
*
* $Date: 31. July 2014
* $Revision: V1.4.4
*
* Project: CMSIS DSP Library
* Title: arm_const_structs.h
*
* Description: This file has constant structs that are initialized for
* user convenience. For example, some can be given as
* arguments to the arm_cfft_f32() function.
*
* Target Processor: Cortex-M4/Cortex-M3
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */
#ifndef _ARM_CONST_STRUCTS_H
#define _ARM_CONST_STRUCTS_H
#include "arm_math.h"
#include "arm_common_tables.h"
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
#endif

File diff suppressed because it is too large Load Diff

View File

@ -1,692 +0,0 @@
/**************************************************************************/ /**
* @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version V4.00
* @date 22. August 2014
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2014 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined(__ICCARM__)
#pragma system_include /* treat file as system include file for MISRA check */
#endif
#ifndef __CORE_CM0_H_GENERIC
#define __CORE_CM0_H_GENERIC
#ifdef __cplusplus
extern "C"
{
#endif
/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/** \ingroup Cortex_M0
@{
*/
/* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
__CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
#define __CORTEX_M (0x00) /*!< Cortex-M Core */
#if defined(__CC_ARM)
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined(__GNUC__)
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#elif defined(__ICCARM__)
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#elif defined(__TMS470__)
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline
#elif defined(__TASKING__)
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
#elif defined(__CSMC__)
#define __packed
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
#define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
#define __STATIC_INLINE static inline
#endif
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0
#if defined(__CC_ARM)
#if defined __TARGET_FPU_VFP
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined(__GNUC__)
#if defined(__VFP_FP__) && !defined(__SOFTFP__)
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined(__ICCARM__)
#if defined __ARMVFP__
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined(__TMS470__)
#if defined __TI__VFP_SUPPORT____
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined(__TASKING__)
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined(__CSMC__) /* Cosmic */
#if (__CSMC__ & 0x400) // FPU present for parser
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include <stdint.h> /* standard types definitions */
#include <core_cmInstr.h> /* Core Instruction Access */
#include <core_cmFunc.h> /* Core Function Access */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0_H_DEPENDANT
#define __CORE_CM0_H_DEPENDANT
#ifdef __cplusplus
extern "C"
{
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0_REV
#define __CM0_REV 0x0000
#warning "__CM0_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/*@} end of group Cortex_M0 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/** \defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/** \brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
#if (__CORTEX_M != 0x04)
uint32_t _reserved0 : 27; /*!< bit: 0..26 Reserved */
#else
uint32_t _reserved0 : 16; /*!< bit: 0..15 Reserved */
uint32_t GE : 4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1 : 7; /*!< bit: 20..26 Reserved */
#endif
uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */
uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */
uint32_t C : 1; /*!< bit: 29 Carry condition code flag */
uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */
uint32_t N : 1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/** \brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0 : 23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */
#if (__CORTEX_M != 0x04)
uint32_t _reserved0 : 15; /*!< bit: 9..23 Reserved */
#else
uint32_t _reserved0 : 7; /*!< bit: 9..15 Reserved */
uint32_t GE : 4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1 : 4; /*!< bit: 20..23 Reserved */
#endif
uint32_t T : 1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t IT : 2; /*!< bit: 25..26 saved IT state (read 0) */
uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */
uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */
uint32_t C : 1; /*!< bit: 29 Carry condition code flag */
uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */
uint32_t N : 1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/** \brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV : 1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL : 1; /*!< bit: 1 Stack to be used */
uint32_t FPCA : 1; /*!< bit: 2 FP extension active flag */
uint32_t _reserved0 : 29; /*!< bit: 3..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/*@} end of group CMSIS_CORE */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31];
__IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31];
__IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31];
__IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31];
uint32_t RESERVED4[64];
__IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/** \brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/** \brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
are only accessible over DAP and not via processor. Therefore
they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Cortex-M0 Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *)SCB_BASE) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *)SysTick_BASE) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *)NVIC_BASE) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ((((uint32_t)(IRQn)) & 0x03) * 8)
#define _SHP_IDX(IRQn) (((((uint32_t)(IRQn)&0x0F) - 8) >> 2))
#define _IP_IDX(IRQn) (((uint32_t)(IRQn) >> 2))
/** \brief Enable External Interrupt
The function enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[0] = (1 << ((uint32_t)(IRQn)&0x1F));
}
/** \brief Disable External Interrupt
The function disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[0] = (1 << ((uint32_t)(IRQn)&0x1F));
}
/** \brief Get Pending Interrupt
The function reads the pending register in the NVIC and returns the pending bit
for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return ((uint32_t)((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn)&0x1F))) ? 1 : 0));
}
/** \brief Set Pending Interrupt
The function sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn)&0x1F));
}
/** \brief Clear Pending Interrupt
The function clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn)&0x1F)); /* Clear pending interrupt */
}
/** \brief Set Interrupt Priority
The function sets the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if (IRQn < 0)
{
SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn));
}
else
{
NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn));
}
}
/** \brief Get Interrupt Priority
The function reads the priority of an interrupt. The interrupt
number can be positive to specify an external (device specific)
interrupt, or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority. Value is aligned automatically to the implemented
priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if (IRQn < 0)
{
return ((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));
} /* get priority for Cortex-M0 system interrupts */
else
{
return ((uint32_t)(((NVIC->IP[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));
} /* get priority for device specific interrupts */
}
/** \brief System Reset
The function initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
while (1)
; /* wait until reset */
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if (__Vendor_SysTickConfig == 0)
/** \brief System Tick Configuration
The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)
return (1); /* Reload value impossible */
SysTick->LOAD = ticks - 1; /* set reload register */
NVIC_SetPriority(SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

View File

@ -1,804 +0,0 @@
/**************************************************************************/ /**
* @file core_cm0plus.h
* @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
* @version V4.00
* @date 22. August 2014
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2014 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined(__ICCARM__)
#pragma system_include /* treat file as system include file for MISRA check */
#endif
#ifndef __CORE_CM0PLUS_H_GENERIC
#define __CORE_CM0PLUS_H_GENERIC
#ifdef __cplusplus
extern "C"
{
#endif
/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/** \ingroup Cortex-M0+
@{
*/
/* CMSIS CM0P definitions */
#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
#define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
__CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
#define __CORTEX_M (0x00) /*!< Cortex-M Core */
#if defined(__CC_ARM)
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined(__GNUC__)
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#elif defined(__ICCARM__)
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#elif defined(__TMS470__)
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline
#elif defined(__TASKING__)
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
#elif defined(__CSMC__)
#define __packed
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
#define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
#define __STATIC_INLINE static inline
#endif
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0
#if defined(__CC_ARM)
#if defined __TARGET_FPU_VFP
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined(__GNUC__)
#if defined(__VFP_FP__) && !defined(__SOFTFP__)
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined(__ICCARM__)
#if defined __ARMVFP__
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined(__TMS470__)
#if defined __TI__VFP_SUPPORT____
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined(__TASKING__)
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined(__CSMC__) /* Cosmic */
#if (__CSMC__ & 0x400) // FPU present for parser
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include <stdint.h> /* standard types definitions */
#include <core_cmInstr.h> /* Core Instruction Access */
#include <core_cmFunc.h> /* Core Function Access */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0PLUS_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0PLUS_H_DEPENDANT
#define __CORE_CM0PLUS_H_DEPENDANT
#ifdef __cplusplus
extern "C"
{
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0PLUS_REV
#define __CM0PLUS_REV 0x0000
#warning "__CM0PLUS_REV not defined in device header file; using default!"
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __VTOR_PRESENT
#define __VTOR_PRESENT 0
#warning "__VTOR_PRESENT not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/*@} end of group Cortex-M0+ */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
- Core MPU Register
******************************************************************************/
/** \defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/** \brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
#if (__CORTEX_M != 0x04)
uint32_t _reserved0 : 27; /*!< bit: 0..26 Reserved */
#else
uint32_t _reserved0 : 16; /*!< bit: 0..15 Reserved */
uint32_t GE : 4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1 : 7; /*!< bit: 20..26 Reserved */
#endif
uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */
uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */
uint32_t C : 1; /*!< bit: 29 Carry condition code flag */
uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */
uint32_t N : 1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/** \brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0 : 23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */
#if (__CORTEX_M != 0x04)
uint32_t _reserved0 : 15; /*!< bit: 9..23 Reserved */
#else
uint32_t _reserved0 : 7; /*!< bit: 9..15 Reserved */
uint32_t GE : 4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1 : 4; /*!< bit: 20..23 Reserved */
#endif
uint32_t T : 1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t IT : 2; /*!< bit: 25..26 saved IT state (read 0) */
uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */
uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */
uint32_t C : 1; /*!< bit: 29 Carry condition code flag */
uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */
uint32_t N : 1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/** \brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV : 1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL : 1; /*!< bit: 1 Stack to be used */
uint32_t FPCA : 1; /*!< bit: 2 FP extension active flag */
uint32_t _reserved0 : 29; /*!< bit: 3..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/*@} end of group CMSIS_CORE */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31];
__IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31];
__IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31];
__IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31];
uint32_t RESERVED4[64];
__IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/** \brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
#if (__VTOR_PRESENT == 1)
__IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
#else
uint32_t RESERVED0;
#endif
__IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
#if (__VTOR_PRESENT == 1)
/* SCB Interrupt Control State Register Definitions */
#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
#endif
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/** \brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
#if (__MPU_PRESENT == 1)
/** \ingroup CMSIS_core_register
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
\brief Type definitions for the Memory Protection Unit (MPU)
@{
*/
/** \brief Structure type to access the Memory Protection Unit (MPU).
*/
typedef struct
{
__I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
__IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
__IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
} MPU_Type;
/* MPU Type Register */
#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register */
#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register */
#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register */
#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
/* MPU Region Attribute and Size Register */
#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
/*@} end of group CMSIS_MPU */
#endif
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
are only accessible over DAP and not via processor. Therefore
they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Cortex-M0+ Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *)SCB_BASE) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *)SysTick_BASE) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *)NVIC_BASE) /*!< NVIC configuration struct */
#if (__MPU_PRESENT == 1)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *)MPU_BASE) /*!< Memory Protection Unit */
#endif
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ((((uint32_t)(IRQn)) & 0x03) * 8)
#define _SHP_IDX(IRQn) (((((uint32_t)(IRQn)&0x0F) - 8) >> 2))
#define _IP_IDX(IRQn) (((uint32_t)(IRQn) >> 2))
/** \brief Enable External Interrupt
The function enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[0] = (1 << ((uint32_t)(IRQn)&0x1F));
}
/** \brief Disable External Interrupt
The function disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[0] = (1 << ((uint32_t)(IRQn)&0x1F));
}
/** \brief Get Pending Interrupt
The function reads the pending register in the NVIC and returns the pending bit
for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return ((uint32_t)((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn)&0x1F))) ? 1 : 0));
}
/** \brief Set Pending Interrupt
The function sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn)&0x1F));
}
/** \brief Clear Pending Interrupt
The function clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn)&0x1F)); /* Clear pending interrupt */
}
/** \brief Set Interrupt Priority
The function sets the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if (IRQn < 0)
{
SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn));
}
else
{
NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn));
}
}
/** \brief Get Interrupt Priority
The function reads the priority of an interrupt. The interrupt
number can be positive to specify an external (device specific)
interrupt, or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority. Value is aligned automatically to the implemented
priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if (IRQn < 0)
{
return ((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));
} /* get priority for Cortex-M0 system interrupts */
else
{
return ((uint32_t)(((NVIC->IP[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));
} /* get priority for device specific interrupts */
}
/** \brief System Reset
The function initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
while (1)
; /* wait until reset */
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if (__Vendor_SysTickConfig == 0)
/** \brief System Tick Configuration
The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)
return (1); /* Reload value impossible */
SysTick->LOAD = ticks - 1; /* set reload register */
NVIC_SetPriority(SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0PLUS_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

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/**************************************************************************/ /**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V4.00
* @date 28. August 2014
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2014 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
#if defined(__CC_ARM) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return (__regControl);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return (__regIPSR);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return (__regAPSR);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return (__regXPSR);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return (__regProcessStackPointer);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return (__regMainStackPointer);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return (__regPriMask);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return (__regBasePri);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xff);
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return (__regFaultMask);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1);
}
#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
return (__regfpscr);
#else
return (0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
#elif defined(__GNUC__) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief Enable IRQ Interrupts
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)
{
__ASM volatile("cpsie i"
:
:
: "memory");
}
/** \brief Disable IRQ Interrupts
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)
{
__ASM volatile("cpsid i"
:
:
: "memory");
}
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
__ASM volatile("MRS %0, control"
: "=r"(result));
return (result);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile("MSR control, %0"
:
: "r"(control)
: "memory");
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile("MRS %0, ipsr"
: "=r"(result));
return (result);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t result;
__ASM volatile("MRS %0, apsr"
: "=r"(result));
return (result);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
{
uint32_t result;
__ASM volatile("MRS %0, xpsr"
: "=r"(result));
return (result);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t result;
__ASM volatile("MRS %0, psp\n"
: "=r"(result));
return (result);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile("MSR psp, %0\n"
:
: "r"(topOfProcStack)
: "sp");
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t result;
__ASM volatile("MRS %0, msp\n"
: "=r"(result));
return (result);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile("MSR msp, %0\n"
:
: "r"(topOfMainStack)
: "sp");
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile("MRS %0, primask"
: "=r"(result));
return (result);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile("MSR primask, %0"
:
: "r"(priMask)
: "memory");
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)
{
__ASM volatile("cpsie f"
:
:
: "memory");
}
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)
{
__ASM volatile("cpsid f"
:
:
: "memory");
}
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
__ASM volatile("MRS %0, basepri_max"
: "=r"(result));
return (result);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
{
__ASM volatile("MSR basepri, %0"
:
: "r"(value)
: "memory");
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
__ASM volatile("MRS %0, faultmask"
: "=r"(result));
return (result);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile("MSR faultmask, %0"
:
: "r"(faultMask)
: "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
uint32_t result;
/* Empty asm statement works as a scheduling barrier */
__ASM volatile("");
__ASM volatile("VMRS %0, fpscr"
: "=r"(result));
__ASM volatile("");
return (result);
#else
return (0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
/* Empty asm statement works as a scheduling barrier */
__ASM volatile("");
__ASM volatile("VMSR fpscr, %0"
:
: "r"(fpscr)
: "vfpcc");
__ASM volatile("");
#endif
}
#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
#elif defined(__ICCARM__) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined(__TMS470__) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined(__TASKING__) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#elif defined(__CSMC__) /*------------------ COSMIC Compiler -------------------*/
/* Cosmic specific functions */
#include <cmsis_csm.h>
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */

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@ -1,870 +0,0 @@
/**************************************************************************/ /**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V4.00
* @date 28. August 2014
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2014 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
#if defined(__CC_ARM) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
#define __WFI __wfi
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
#define __ISB() __isb(0xF)
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() __dsb(0xF)
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() __dmb(0xF)
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
#endif
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __RBIT __rbit
/** \brief LDR Exclusive (8 bit)
This function executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDREXB(ptr) ((uint8_t)__ldrex(ptr))
/** \brief LDR Exclusive (16 bit)
This function executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDREXH(ptr) ((uint16_t)__ldrex(ptr))
/** \brief LDR Exclusive (32 bit)
This function executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDREXW(ptr) ((uint32_t)__ldrex(ptr))
/** \brief STR Exclusive (8 bit)
This function executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXB(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (16 bit)
This function executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXH(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (32 bit)
This function executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXW(value, ptr) __strex(value, ptr)
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
/** \brief Rotate Right with Extend (32 bit)
This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
{
rrx r0, r0
bx lr
}
#endif
/** \brief LDRT Unprivileged (8 bit)
This function executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDRBT(ptr) ((uint8_t)__ldrt(ptr))
/** \brief LDRT Unprivileged (16 bit)
This function executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDRHT(ptr) ((uint16_t)__ldrt(ptr))
/** \brief LDRT Unprivileged (32 bit)
This function executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDRT(ptr) ((uint32_t)__ldrt(ptr))
/** \brief STRT Unprivileged (8 bit)
This function executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRBT(value, ptr) __strt(value, ptr)
/** \brief STRT Unprivileged (16 bit)
This function executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRHT(value, ptr) __strt(value, ptr)
/** \brief STRT Unprivileged (32 bit)
This function executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRT(value, ptr) __strt(value, ptr)
#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
#elif defined(__GNUC__) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/* Define macros for porting to both thumb1 and thumb2.
* For thumb1, use low register (r0-r7), specified by constrant "l"
* Otherwise, use general registers, specified by constrant "r" */
#if defined(__thumb__) && !defined(__thumb2__)
#define __CMSIS_GCC_OUT_REG(r) "=l"(r)
#define __CMSIS_GCC_USE_REG(r) "l"(r)
#else
#define __CMSIS_GCC_OUT_REG(r) "=r"(r)
#define __CMSIS_GCC_USE_REG(r) "r"(r)
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
{
__ASM volatile("nop");
}
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
{
__ASM volatile("wfi");
}
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
{
__ASM volatile("wfe");
}
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
{
__ASM volatile("sev");
}
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
{
__ASM volatile("isb");
}
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
{
__ASM volatile("dsb");
}
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
{
__ASM volatile("dmb");
}
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
return __builtin_bswap32(value);
#else
uint32_t result;
__ASM volatile("rev %0, %1"
: __CMSIS_GCC_OUT_REG(result)
: __CMSIS_GCC_USE_REG(value));
return (result);
#endif
}
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
__ASM volatile("rev16 %0, %1"
: __CMSIS_GCC_OUT_REG(result)
: __CMSIS_GCC_USE_REG(value));
return (result);
}
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
return (short)__builtin_bswap16(value);
#else
uint32_t result;
__ASM volatile("revsh %0, %1"
: __CMSIS_GCC_OUT_REG(result)
: __CMSIS_GCC_USE_REG(value));
return (result);
#endif
}
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << (32 - op2));
}
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __ASM volatile("bkpt " #value)
#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
__ASM volatile("rbit %0, %1"
: "=r"(result)
: "r"(value));
return (result);
}
/** \brief LDR Exclusive (8 bit)
This function executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile("ldrexb %0, %1"
: "=r"(result)
: "Q"(*addr));
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile("ldrexb %0, [%1]"
: "=r"(result)
: "r"(addr)
: "memory");
#endif
return ((uint8_t)result); /* Add explicit type cast here */
}
/** \brief LDR Exclusive (16 bit)
This function executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile("ldrexh %0, %1"
: "=r"(result)
: "Q"(*addr));
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile("ldrexh %0, [%1]"
: "=r"(result)
: "r"(addr)
: "memory");
#endif
return ((uint16_t)result); /* Add explicit type cast here */
}
/** \brief LDR Exclusive (32 bit)
This function executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile("ldrex %0, %1"
: "=r"(result)
: "Q"(*addr));
return (result);
}
/** \brief STR Exclusive (8 bit)
This function executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
__ASM volatile("strexb %0, %2, %1"
: "=&r"(result), "=Q"(*addr)
: "r"((uint32_t)value));
return (result);
}
/** \brief STR Exclusive (16 bit)
This function executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
__ASM volatile("strexh %0, %2, %1"
: "=&r"(result), "=Q"(*addr)
: "r"((uint32_t)value));
return (result);
}
/** \brief STR Exclusive (32 bit)
This function executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile("strex %0, %2, %1"
: "=&r"(result), "=Q"(*addr)
: "r"(value));
return (result);
}
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
{
__ASM volatile("clrex" ::
: "memory");
}
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT(ARG1, ARG2) \
( \
{ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM("ssat %0, %1, %2" \
: "=r"(__RES) \
: "I"(ARG2), "r"(__ARG1)); \
__RES; \
})
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT(ARG1, ARG2) \
( \
{ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM("usat %0, %1, %2" \
: "=r"(__RES) \
: "I"(ARG2), "r"(__ARG1)); \
__RES; \
})
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
__attribute__((always_inline)) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
{
uint32_t result;
__ASM volatile("clz %0, %1"
: "=r"(result)
: "r"(value));
return ((uint8_t)result); /* Add explicit type cast here */
}
/** \brief Rotate Right with Extend (32 bit)
This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
{
uint32_t result;
__ASM volatile("rrx %0, %1"
: __CMSIS_GCC_OUT_REG(result)
: __CMSIS_GCC_USE_REG(value));
return (result);
}
/** \brief LDRT Unprivileged (8 bit)
This function executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile("ldrbt %0, %1"
: "=r"(result)
: "Q"(*addr));
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile("ldrbt %0, [%1]"
: "=r"(result)
: "r"(addr)
: "memory");
#endif
return ((uint8_t)result); /* Add explicit type cast here */
}
/** \brief LDRT Unprivileged (16 bit)
This function executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile("ldrht %0, %1"
: "=r"(result)
: "Q"(*addr));
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile("ldrht %0, [%1]"
: "=r"(result)
: "r"(addr)
: "memory");
#endif
return ((uint16_t)result); /* Add explicit type cast here */
}
/** \brief LDRT Unprivileged (32 bit)
This function executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile("ldrt %0, %1"
: "=r"(result)
: "Q"(*addr));
return (result);
}
/** \brief STRT Unprivileged (8 bit)
This function executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
{
__ASM volatile("strbt %1, %0"
: "=Q"(*addr)
: "r"((uint32_t)value));
}
/** \brief STRT Unprivileged (16 bit)
This function executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
{
__ASM volatile("strht %1, %0"
: "=Q"(*addr)
: "r"((uint32_t)value));
}
/** \brief STRT Unprivileged (32 bit)
This function executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
{
__ASM volatile("strt %1, %0"
: "=Q"(*addr)
: "r"(value));
}
#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
#elif defined(__ICCARM__) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined(__TMS470__) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined(__TASKING__) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#elif defined(__CSMC__) /*------------------ COSMIC Compiler -------------------*/
/* Cosmic specific functions */
#include <cmsis_csm.h>
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H */

View File

@ -1,830 +0,0 @@
/**************************************************************************/ /**
* @file core_cmSimd.h
* @brief CMSIS Cortex-M SIMD Header File
* @version V4.00
* @date 22. August 2014
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2014 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined(__ICCARM__)
#pragma system_include /* treat file as system include file for MISRA check */
#endif
#ifndef __CORE_CMSIMD_H
#define __CORE_CMSIMD_H
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Hardware Abstraction Layer
******************************************************************************/
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if defined(__CC_ARM) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1, ARG2, ARG3) (((((uint32_t)(ARG1))) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL))
#define __PKHTB(ARG1, ARG2, ARG3) (((((uint32_t)(ARG1))) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL))
#define __SMMLA(ARG1, ARG2, ARG3) ((int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32)) >> \
32))
#elif defined(__GNUC__) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile("sadd8 %0, %1, %2"
: "=r"(result)
: "r"(op1), "r"(op2));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile("qadd8 %0, %1, %2"
: "=r"(result)
: "r"(op1), "r"(op2));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile("shadd8 %0, %1, %2"
: "=r"(result)
: "r"(op1), "r"(op2));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile("uadd8 %0, %1, %2"
: "=r"(result)
: "r"(op1), "r"(op2));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile("uqadd8 %0, %1, %2"
: "=r"(result)
: "r"(op1), "r"(op2));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile("uhadd8 %0, %1, %2"
: "=r"(result)
: "r"(op1), "r"(op2));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile("ssub8 %0, %1, %2"
: "=r"(result)
: "r"(op1), "r"(op2));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile("qsub8 %0, %1, %2"
: "=r"(result)
: "r"(op1), "r"(op2));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile("shsub8 %0, %1, %2"
: "=r"(result)
: "r"(op1), "r"(op2));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile("usub8 %0, %1, %2"
: "=r"(result)
: "r"(op1), "r"(op2));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile("uqsub8 %0, %1, %2"
: "=r"(result)
: "r"(op1), "r"(op2));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile("uhsub8 %0, %1, %2"
: "=r"(result)
: "r"(op1), "r"(op2));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile("sadd16 %0, %1, %2"
: "=r"(result)
: "r"(op1), "r"(op2));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile("qadd16 %0, %1, %2"
: "=r"(result)
: "r"(op1), "r"(op2));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile("shadd16 %0, %1, %2"
: "=r"(result)
: "r"(op1), "r"(op2));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile("uadd16 %0, %1, %2"
: "=r"(result)
: "r"(op1), "r"(op2));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile("uqadd16 %0, %1, %2"
: "=r"(result)
: "r"(op1), "r"(op2));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile("uhadd16 %0, %1, %2"
: "=r"(result)
: "r"(op1), "r"(op2));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile("ssub16 %0, %1, %2"
: "=r"(result)
: "r"(op1), "r"(op2));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile("qsub16 %0, %1, %2"
: "=r"(result)
: "r"(op1), "r"(op2));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile("shsub16 %0, %1, %2"
: "=r"(result)
: "r"(op1), "r"(op2));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile("usub16 %0, %1, %2"
: "=r"(result)
: "r"(op1), "r"(op2));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile("uqsub16 %0, %1, %2"
: "=r"(result)
: "r"(op1), "r"(op2));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile("uhsub16 %0, %1, %2"
: "=r"(result)
: "r"(op1), "r"(op2));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile("sasx %0, %1, %2"
: "=r"(result)
: "r"(op1), "r"(op2));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile("qasx %0, %1, %2"
: "=r"(result)
: "r"(op1), "r"(op2));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile("shasx %0, %1, %2"
: "=r"(result)
: "r"(op1), "r"(op2));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile("uasx %0, %1, %2"
: "=r"(result)
: "r"(op1), "r"(op2));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile("uqasx %0, %1, %2"
: "=r"(result)
: "r"(op1), "r"(op2));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile("uhasx %0, %1, %2"
: "=r"(result)
: "r"(op1), "r"(op2));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile("ssax %0, %1, %2"
: "=r"(result)
: "r"(op1), "r"(op2));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile("qsax %0, %1, %2"
: "=r"(result)
: "r"(op1), "r"(op2));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile("shsax %0, %1, %2"
: "=r"(result)
: "r"(op1), "r"(op2));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile("usax %0, %1, %2"
: "=r"(result)
: "r"(op1), "r"(op2));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile("uqsax %0, %1, %2"
: "=r"(result)
: "r"(op1), "r"(op2));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile("uhsax %0, %1, %2"
: "=r"(result)
: "r"(op1), "r"(op2));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile("usad8 %0, %1, %2"
: "=r"(result)
: "r"(op1), "r"(op2));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile("usada8 %0, %1, %2, %3"
: "=r"(result)
: "r"(op1), "r"(op2), "r"(op3));
return (result);
}
#define __SSAT16(ARG1, ARG2) \
( \
{ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM("ssat16 %0, %1, %2" \
: "=r"(__RES) \
: "I"(ARG2), "r"(__ARG1)); \
__RES; \
})
#define __USAT16(ARG1, ARG2) \
( \
{ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM("usat16 %0, %1, %2" \
: "=r"(__RES) \
: "I"(ARG2), "r"(__ARG1)); \
__RES; \
})
__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
{
uint32_t result;
__ASM volatile("uxtb16 %0, %1"
: "=r"(result)
: "r"(op1));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile("uxtab16 %0, %1, %2"
: "=r"(result)
: "r"(op1), "r"(op2));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
{
uint32_t result;
__ASM volatile("sxtb16 %0, %1"
: "=r"(result)
: "r"(op1));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile("sxtab16 %0, %1, %2"
: "=r"(result)
: "r"(op1), "r"(op2));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile("smuad %0, %1, %2"
: "=r"(result)
: "r"(op1), "r"(op2));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile("smuadx %0, %1, %2"
: "=r"(result)
: "r"(op1), "r"(op2));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD(uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile("smlad %0, %1, %2, %3"
: "=r"(result)
: "r"(op1), "r"(op2), "r"(op3));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX(uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile("smladx %0, %1, %2, %3"
: "=r"(result)
: "r"(op1), "r"(op2), "r"(op3));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD(uint32_t op1, uint32_t op2, uint64_t acc)
{
union llreg_u
{
uint32_t w32[2];
uint64_t w64;
} llr;
llr.w64 = acc;
#ifndef __ARMEB__ // Little endian
__ASM volatile("smlald %0, %1, %2, %3"
: "=r"(llr.w32[0]), "=r"(llr.w32[1])
: "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1]));
#else // Big endian
__ASM volatile("smlald %0, %1, %2, %3"
: "=r"(llr.w32[1]), "=r"(llr.w32[0])
: "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0]));
#endif
return (llr.w64);
}
__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX(uint32_t op1, uint32_t op2, uint64_t acc)
{
union llreg_u
{
uint32_t w32[2];
uint64_t w64;
} llr;
llr.w64 = acc;
#ifndef __ARMEB__ // Little endian
__ASM volatile("smlaldx %0, %1, %2, %3"
: "=r"(llr.w32[0]), "=r"(llr.w32[1])
: "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1]));
#else // Big endian
__ASM volatile("smlaldx %0, %1, %2, %3"
: "=r"(llr.w32[1]), "=r"(llr.w32[0])
: "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0]));
#endif
return (llr.w64);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile("smusd %0, %1, %2"
: "=r"(result)
: "r"(op1), "r"(op2));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile("smusdx %0, %1, %2"
: "=r"(result)
: "r"(op1), "r"(op2));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD(uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile("smlsd %0, %1, %2, %3"
: "=r"(result)
: "r"(op1), "r"(op2), "r"(op3));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX(uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile("smlsdx %0, %1, %2, %3"
: "=r"(result)
: "r"(op1), "r"(op2), "r"(op3));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD(uint32_t op1, uint32_t op2, uint64_t acc)
{
union llreg_u
{
uint32_t w32[2];
uint64_t w64;
} llr;
llr.w64 = acc;
#ifndef __ARMEB__ // Little endian
__ASM volatile("smlsld %0, %1, %2, %3"
: "=r"(llr.w32[0]), "=r"(llr.w32[1])
: "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1]));
#else // Big endian
__ASM volatile("smlsld %0, %1, %2, %3"
: "=r"(llr.w32[1]), "=r"(llr.w32[0])
: "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0]));
#endif
return (llr.w64);
}
__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX(uint32_t op1, uint32_t op2, uint64_t acc)
{
union llreg_u
{
uint32_t w32[2];
uint64_t w64;
} llr;
llr.w64 = acc;
#ifndef __ARMEB__ // Little endian
__ASM volatile("smlsldx %0, %1, %2, %3"
: "=r"(llr.w32[0]), "=r"(llr.w32[1])
: "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1]));
#else // Big endian
__ASM volatile("smlsldx %0, %1, %2, %3"
: "=r"(llr.w32[1]), "=r"(llr.w32[0])
: "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0]));
#endif
return (llr.w64);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile("sel %0, %1, %2"
: "=r"(result)
: "r"(op1), "r"(op2));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile("qadd %0, %1, %2"
: "=r"(result)
: "r"(op1), "r"(op2));
return (result);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile("qsub %0, %1, %2"
: "=r"(result)
: "r"(op1), "r"(op2));
return (result);
}
#define __PKHBT(ARG1, ARG2, ARG3) \
( \
{ \
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
__ASM("pkhbt %0, %1, %2, lsl %3" \
: "=r"(__RES) \
: "r"(__ARG1), "r"(__ARG2), "I"(ARG3)); \
__RES; \
})
#define __PKHTB(ARG1, ARG2, ARG3) \
( \
{ \
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
if (ARG3 == 0) \
__ASM("pkhtb %0, %1, %2" \
: "=r"(__RES) \
: "r"(__ARG1), "r"(__ARG2)); \
else \
__ASM("pkhtb %0, %1, %2, asr %3" \
: "=r"(__RES) \
: "r"(__ARG1), "r"(__ARG2), "I"(ARG3)); \
__RES; \
})
__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA(int32_t op1, int32_t op2, int32_t op3)
{
int32_t result;
__ASM volatile("smmla %0, %1, %2, %3"
: "=r"(result)
: "r"(op1), "r"(op2), "r"(op3));
return (result);
}
#elif defined(__ICCARM__) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined(__TMS470__) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined(__TASKING__) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/* not yet supported */
#elif defined(__CSMC__) /*------------------ COSMIC Compiler -------------------*/
/* Cosmic specific functions */
#include <cmsis_csm.h>
#endif
/*@} end of group CMSIS_SIMD_intrinsics */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CMSIMD_H */

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@ -1,558 +0,0 @@
;******************************************************************************************************************************************
; 文件名称: startup_SWM320.s
; 功能说明: SWM2400单片机的启动文件
; 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1
; 注意事项:
; 版本日期: V1.1.0 2017年10月25日
; 升级记录:
;
;
;******************************************************************************************************************************************
; @attention
;
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
; REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
; FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
; OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
; -ECTION WITH THEIR PRODUCTS.
;
; COPYRIGHT 2012 Synwit Technology
;******************************************************************************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00001000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD GPIOA0_Handler
DCD GPIOA1_Handler
DCD GPIOA2_Handler
DCD GPIOA3_Handler
DCD GPIOA4_Handler
DCD GPIOA5_Handler
DCD GPIOA6_Handler
DCD GPIOA7_Handler
DCD GPIOB0_Handler
DCD GPIOB1_Handler
DCD GPIOB2_Handler
DCD GPIOB3_Handler
DCD GPIOB4_Handler
DCD GPIOB5_Handler
DCD GPIOB6_Handler
DCD GPIOB7_Handler
DCD GPIOC0_Handler
DCD GPIOC1_Handler
DCD GPIOC2_Handler
DCD GPIOC3_Handler
DCD GPIOC4_Handler
DCD GPIOC5_Handler
DCD GPIOC6_Handler
DCD GPIOC7_Handler
DCD GPIOM0_Handler
DCD GPIOM1_Handler
DCD GPIOM2_Handler
DCD GPIOM3_Handler
DCD GPIOM4_Handler
DCD GPIOM5_Handler
DCD GPIOM6_Handler
DCD GPIOM7_Handler
DCD DMA_Handler
DCD LCD_Handler
DCD NORFLC_Handler
DCD CAN_Handler
DCD PULSE_Handler
DCD WDT_Handler
DCD PWM_Handler
DCD UART0_Handler
DCD UART1_Handler
DCD UART2_Handler
DCD UART3_Handler
DCD 0
DCD I2C0_Handler
DCD I2C1_Handler
DCD SPI0_Handler
DCD ADC0_Handler
DCD RTC_Handler
DCD BOD_Handler
DCD SDIO_Handler
DCD GPIOA_Handler
DCD GPIOB_Handler
DCD GPIOC_Handler
DCD GPIOM_Handler
DCD GPION_Handler
DCD GPIOP_Handler
DCD ADC1_Handler
DCD FPU_Handler
DCD SPI1_Handler
DCD TIMR0_Handler
DCD TIMR1_Handler
DCD TIMR2_Handler
DCD TIMR3_Handler
DCD TIMR4_Handler
DCD TIMR5_Handler
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
GPIOA0_Handler PROC
EXPORT GPIOA0_Handler [WEAK]
B .
ENDP
GPIOA1_Handler PROC
EXPORT GPIOA1_Handler [WEAK]
B .
ENDP
GPIOA2_Handler PROC
EXPORT GPIOA2_Handler [WEAK]
B .
ENDP
GPIOA3_Handler PROC
EXPORT GPIOA3_Handler [WEAK]
B .
ENDP
GPIOA4_Handler PROC
EXPORT GPIOA4_Handler [WEAK]
B .
ENDP
GPIOA5_Handler PROC
EXPORT GPIOA5_Handler [WEAK]
B .
ENDP
GPIOA6_Handler PROC
EXPORT GPIOA6_Handler [WEAK]
B .
ENDP
GPIOA7_Handler PROC
EXPORT GPIOA7_Handler [WEAK]
B .
ENDP
GPIOB0_Handler PROC
EXPORT GPIOB0_Handler [WEAK]
B .
ENDP
GPIOB1_Handler PROC
EXPORT GPIOB1_Handler [WEAK]
B .
ENDP
GPIOB2_Handler PROC
EXPORT GPIOB2_Handler [WEAK]
B .
ENDP
GPIOB3_Handler PROC
EXPORT GPIOB3_Handler [WEAK]
B .
ENDP
GPIOB4_Handler PROC
EXPORT GPIOB4_Handler [WEAK]
B .
ENDP
GPIOB5_Handler PROC
EXPORT GPIOB5_Handler [WEAK]
B .
ENDP
GPIOB6_Handler PROC
EXPORT GPIOB6_Handler [WEAK]
B .
ENDP
GPIOB7_Handler PROC
EXPORT GPIOB7_Handler [WEAK]
B .
ENDP
GPIOC0_Handler PROC
EXPORT GPIOC0_Handler [WEAK]
B .
ENDP
GPIOC1_Handler PROC
EXPORT GPIOC1_Handler [WEAK]
B .
ENDP
GPIOC2_Handler PROC
EXPORT GPIOC2_Handler [WEAK]
B .
ENDP
GPIOC3_Handler PROC
EXPORT GPIOC3_Handler [WEAK]
B .
ENDP
GPIOC4_Handler PROC
EXPORT GPIOC4_Handler [WEAK]
B .
ENDP
GPIOC5_Handler PROC
EXPORT GPIOC5_Handler [WEAK]
B .
ENDP
GPIOC6_Handler PROC
EXPORT GPIOC6_Handler [WEAK]
B .
ENDP
GPIOC7_Handler PROC
EXPORT GPIOC7_Handler [WEAK]
B .
ENDP
GPIOM0_Handler PROC
EXPORT GPIOM0_Handler [WEAK]
B .
ENDP
GPIOM1_Handler PROC
EXPORT GPIOM1_Handler [WEAK]
B .
ENDP
GPIOM2_Handler PROC
EXPORT GPIOM2_Handler [WEAK]
B .
ENDP
GPIOM3_Handler PROC
EXPORT GPIOM3_Handler [WEAK]
B .
ENDP
GPIOM4_Handler PROC
EXPORT GPIOM4_Handler [WEAK]
B .
ENDP
GPIOM5_Handler PROC
EXPORT GPIOM5_Handler [WEAK]
B .
ENDP
GPIOM6_Handler PROC
EXPORT GPIOM6_Handler [WEAK]
B .
ENDP
GPIOM7_Handler PROC
EXPORT GPIOM7_Handler [WEAK]
B .
ENDP
DMA_Handler PROC
EXPORT DMA_Handler [WEAK]
B .
ENDP
LCD_Handler PROC
EXPORT LCD_Handler [WEAK]
B .
ENDP
NORFLC_Handler PROC
EXPORT NORFLC_Handler [WEAK]
B .
ENDP
CAN_Handler PROC
EXPORT CAN_Handler [WEAK]
B .
ENDP
PULSE_Handler PROC
EXPORT PULSE_Handler [WEAK]
B .
ENDP
WDT_Handler PROC
EXPORT WDT_Handler [WEAK]
B .
ENDP
PWM_Handler PROC
EXPORT PWM_Handler [WEAK]
B .
ENDP
UART0_Handler PROC
EXPORT UART0_Handler [WEAK]
B .
ENDP
UART1_Handler PROC
EXPORT UART1_Handler [WEAK]
B .
ENDP
UART2_Handler PROC
EXPORT UART2_Handler [WEAK]
B .
ENDP
UART3_Handler PROC
EXPORT UART3_Handler [WEAK]
B .
ENDP
I2C0_Handler PROC
EXPORT I2C0_Handler [WEAK]
B .
ENDP
I2C1_Handler PROC
EXPORT I2C1_Handler [WEAK]
B .
ENDP
SPI0_Handler PROC
EXPORT SPI0_Handler [WEAK]
B .
ENDP
ADC0_Handler PROC
EXPORT ADC0_Handler [WEAK]
B .
ENDP
RTC_Handler PROC
EXPORT RTC_Handler [WEAK]
B .
ENDP
BOD_Handler PROC
EXPORT BOD_Handler [WEAK]
B .
ENDP
SDIO_Handler PROC
EXPORT SDIO_Handler [WEAK]
B .
ENDP
GPIOA_Handler PROC
EXPORT GPIOA_Handler [WEAK]
B .
ENDP
GPIOB_Handler PROC
EXPORT GPIOB_Handler [WEAK]
B .
ENDP
GPIOC_Handler PROC
EXPORT GPIOC_Handler [WEAK]
B .
ENDP
GPIOM_Handler PROC
EXPORT GPIOM_Handler [WEAK]
B .
ENDP
GPION_Handler PROC
EXPORT GPION_Handler [WEAK]
B .
ENDP
GPIOP_Handler PROC
EXPORT GPIOP_Handler [WEAK]
B .
ENDP
ADC1_Handler PROC
EXPORT ADC1_Handler [WEAK]
B .
ENDP
FPU_Handler PROC
EXPORT FPU_Handler [WEAK]
B .
ENDP
SPI1_Handler PROC
EXPORT SPI1_Handler [WEAK]
B .
ENDP
TIMR0_Handler PROC
EXPORT TIMR0_Handler [WEAK]
B .
ENDP
TIMR1_Handler PROC
EXPORT TIMR1_Handler [WEAK]
B .
ENDP
TIMR2_Handler PROC
EXPORT TIMR2_Handler [WEAK]
B .
ENDP
TIMR3_Handler PROC
EXPORT TIMR3_Handler [WEAK]
B .
ENDP
TIMR4_Handler PROC
EXPORT TIMR4_Handler [WEAK]
B .
ENDP
TIMR5_Handler PROC
EXPORT TIMR5_Handler [WEAK]
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END

View File

@ -1,406 +0,0 @@
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the application's entry point.*/
bl entry
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
/* External Interrupts */
.word GPIOA0_Handler
.word GPIOA1_Handler
.word GPIOA2_Handler
.word GPIOA3_Handler
.word GPIOA4_Handler
.word GPIOA5_Handler
.word GPIOA6_Handler
.word GPIOA7_Handler
.word GPIOB0_Handler
.word GPIOB1_Handler
.word GPIOB2_Handler
.word GPIOB3_Handler
.word GPIOB4_Handler
.word GPIOB5_Handler
.word GPIOB6_Handler
.word GPIOB7_Handler
.word GPIOC0_Handler
.word GPIOC1_Handler
.word GPIOC2_Handler
.word GPIOC3_Handler
.word GPIOC4_Handler
.word GPIOC5_Handler
.word GPIOC6_Handler
.word GPIOC7_Handler
.word GPIOM0_Handler
.word GPIOM1_Handler
.word GPIOM2_Handler
.word GPIOM3_Handler
.word GPIOM4_Handler
.word GPIOM5_Handler
.word GPIOM6_Handler
.word GPIOM7_Handler
.word DMA_Handler
.word LCD_Handler
.word NORFLC_Handler
.word CAN_Handler
.word PULSE_Handler
.word WDT_Handler
.word PWM_Handler
.word UART0_Handler
.word UART1_Handler
.word UART2_Handler
.word UART3_Handler
.word 0
.word I2C0_Handler
.word I2C1_Handler
.word SPI0_Handler
.word ADC0_Handler
.word RTC_Handler
.word ANAC_Handler
.word SDIO_Handler
.word GPIOA_Handler
.word GPIOB_Handler
.word GPIOC_Handler
.word GPIOM_Handler
.word GPION_Handler
.word GPIOP_Handler
.word ADC1_Handler
.word FPU_Handler
.word SPI1_Handler
.word TIMR0_Handler
.word TIMR1_Handler
.word TIMR2_Handler
.word TIMR3_Handler
.word TIMR4_Handler
.word TIMR5_Handler
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak GPIOA0_Handler
.thumb_set GPIOA0_Handler,Default_Handler
.weak GPIOA1_Handler
.thumb_set GPIOA1_Handler,Default_Handler
.weak GPIOA2_Handler
.thumb_set GPIOA2_Handler,Default_Handler
.weak GPIOA3_Handler
.thumb_set GPIOA3_Handler,Default_Handler
.weak GPIOA4_Handler
.thumb_set GPIOA4_Handler,Default_Handler
.weak GPIOA5_Handler
.thumb_set GPIOA5_Handler,Default_Handler
.weak GPIOA6_Handler
.thumb_set GPIOA6_Handler,Default_Handler
.weak GPIOA7_Handler
.thumb_set GPIOA7_Handler,Default_Handler
.weak GPIOB0_Handler
.thumb_set GPIOB0_Handler,Default_Handler
.weak GPIOB1_Handler
.thumb_set GPIOB1_Handler,Default_Handler
.weak GPIOB2_Handler
.thumb_set GPIOB2_Handler,Default_Handler
.weak GPIOB3_Handler
.thumb_set GPIOB3_Handler,Default_Handler
.weak GPIOB4_Handler
.thumb_set GPIOB4_Handler,Default_Handler
.weak GPIOB5_Handler
.thumb_set GPIOB5_Handler,Default_Handler
.weak GPIOB6_Handler
.thumb_set GPIOB6_Handler,Default_Handler
.weak GPIOB7_Handler
.thumb_set GPIOB7_Handler,Default_Handler
.weak GPIOC0_Handler
.thumb_set GPIOC0_Handler,Default_Handler
.weak GPIOC1_Handler
.thumb_set GPIOC1_Handler,Default_Handler
.weak GPIOC2_Handler
.thumb_set GPIOC2_Handler,Default_Handler
.weak GPIOC3_Handler
.thumb_set GPIOC3_Handler,Default_Handler
.weak GPIOC4_Handler
.thumb_set GPIOC4_Handler,Default_Handler
.weak GPIOC5_Handler
.thumb_set GPIOC5_Handler,Default_Handler
.weak GPIOC6_Handler
.thumb_set GPIOC6_Handler,Default_Handler
.weak GPIOC7_Handler
.thumb_set GPIOC7_Handler,Default_Handler
.weak GPIOM0_Handler
.thumb_set GPIOM0_Handler,Default_Handler
.weak GPIOM1_Handler
.thumb_set GPIOM1_Handler,Default_Handler
.weak GPIOM2_Handler
.thumb_set GPIOM2_Handler,Default_Handler
.weak GPIOM3_Handler
.thumb_set GPIOM3_Handler,Default_Handler
.weak GPIOM4_Handler
.thumb_set GPIOM4_Handler,Default_Handler
.weak GPIOM5_Handler
.thumb_set GPIOM5_Handler,Default_Handler
.weak GPIOM6_Handler
.thumb_set GPIOM6_Handler,Default_Handler
.weak GPIOM7_Handler
.thumb_set GPIOM7_Handler,Default_Handler
.weak DMA_Handler
.thumb_set DMA_Handler,Default_Handler
.weak LCD_Handler
.thumb_set LCD_Handler,Default_Handler
.weak NORFLC_Handler
.thumb_set NORFLC_Handler,Default_Handler
.weak CAN_Handler
.thumb_set CAN_Handler,Default_Handler
.weak PULSE_Handler
.thumb_set PULSE_Handler,Default_Handler
.weak WDT_Handler
.thumb_set WDT_Handler,Default_Handler
.weak PWM_Handler
.thumb_set PWM_Handler,Default_Handler
.weak UART0_Handler
.thumb_set UART0_Handler,Default_Handler
.weak UART1_Handler
.thumb_set UART1_Handler,Default_Handler
.weak UART2_Handler
.thumb_set UART2_Handler,Default_Handler
.weak UART3_Handler
.thumb_set UART3_Handler,Default_Handler
.weak I2C0_Handler
.thumb_set I2C0_Handler,Default_Handler
.weak I2C1_Handler
.thumb_set I2C1_Handler,Default_Handler
.weak SPI0_Handler
.thumb_set SPI0_Handler,Default_Handler
.weak ADC0_Handler
.thumb_set ADC0_Handler,Default_Handler
.weak RTC_Handler
.thumb_set RTC_Handler,Default_Handler
.weak ANAC_Handler
.thumb_set ANAC_Handler,Default_Handler
.weak SDIO_Handler
.thumb_set SDIO_Handler,Default_Handler
.weak GPIOA_Handler
.thumb_set GPIOA_Handler,Default_Handler
.weak GPIOB_Handler
.thumb_set GPIOB_Handler,Default_Handler
.weak GPIOC_Handler
.thumb_set GPIOC_Handler,Default_Handler
.weak GPIOM_Handler
.thumb_set GPIOM_Handler,Default_Handler
.weak GPION_Handler
.thumb_set GPION_Handler,Default_Handler
.weak GPIOP_Handler
.thumb_set GPIOP_Handler,Default_Handler
.weak ADC1_Handler
.thumb_set ADC1_Handler,Default_Handler
.weak FPU_Handler
.thumb_set FPU_Handler,Default_Handler
.weak SPI1_Handler
.thumb_set SPI1_Handler,Default_Handler
.weak TIMR0_Handler
.thumb_set TIMR0_Handler,Default_Handler
.weak TIMR1_Handler
.thumb_set TIMR1_Handler,Default_Handler
.weak TIMR2_Handler
.thumb_set TIMR2_Handler,Default_Handler
.weak TIMR3_Handler
.thumb_set TIMR3_Handler,Default_Handler
.weak TIMR4_Handler
.thumb_set TIMR4_Handler,Default_Handler
.weak TIMR5_Handler
.thumb_set TIMR5_Handler,Default_Handler

View File

@ -1,500 +0,0 @@
;******************************************************************************************************************************************
; 文件名称: startup_SWM2400.s
; 功能说明: SWM2400单片机的启动文件
; 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1
; 注意事项:
; 版本日期: V1.0.0 2016年1月30日
; 升级记录:
;
;
;******************************************************************************************************************************************
; @attention
;
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
; REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
; FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
; OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
; -ECTION WITH THEIR PRODUCTS.
;
; COPYRIGHT 2012 Synwit Technology
;******************************************************************************************************************************************
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD GPIOA0_Handler
DCD GPIOA1_Handler
DCD GPIOA2_Handler
DCD GPIOA3_Handler
DCD GPIOA4_Handler
DCD GPIOA5_Handler
DCD GPIOA6_Handler
DCD GPIOA7_Handler
DCD GPIOB0_Handler
DCD GPIOB1_Handler
DCD GPIOB2_Handler
DCD GPIOB3_Handler
DCD GPIOB4_Handler
DCD GPIOB5_Handler
DCD GPIOB6_Handler
DCD GPIOB7_Handler
DCD GPIOC0_Handler
DCD GPIOC1_Handler
DCD GPIOC2_Handler
DCD GPIOC3_Handler
DCD GPIOC4_Handler
DCD GPIOC5_Handler
DCD GPIOC6_Handler
DCD GPIOC7_Handler
DCD GPIOM0_Handler
DCD GPIOM1_Handler
DCD GPIOM2_Handler
DCD GPIOM3_Handler
DCD GPIOM4_Handler
DCD GPIOM5_Handler
DCD GPIOM6_Handler
DCD GPIOM7_Handler
DCD DMA_Handler
DCD LCD_Handler
DCD NORFLC_Handler
DCD CAN_Handler
DCD PULSE_Handler
DCD WDT_Handler
DCD PWM_Handler
DCD UART0_Handler
DCD UART1_Handler
DCD UART2_Handler
DCD UART3_Handler
DCD 0
DCD I2C0_Handler
DCD I2C1_Handler
DCD SPI0_Handler
DCD ADC0_Handler
DCD RTC_Handler
DCD BOD_Handler
DCD SDIO_Handler
DCD GPIOA_Handler
DCD GPIOB_Handler
DCD GPIOC_Handler
DCD GPIOM_Handler
DCD GPION_Handler
DCD GPIOP_Handler
DCD ADC1_Handler
DCD FPU_Handler
DCD SPI1_Handler
DCD TIMR0_Handler
DCD TIMR1_Handler
DCD TIMR2_Handler
DCD TIMR3_Handler
DCD TIMR4_Handler
DCD TIMR5_Handler
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK GPIOA0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOA0_Handler
B GPIOA0_Handler
PUBWEAK GPIOA1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOA1_Handler
B GPIOA1_Handler
PUBWEAK GPIOA2_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOA2_Handler
B GPIOA2_Handler
PUBWEAK GPIOA3_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOA3_Handler
B GPIOA3_Handler
PUBWEAK GPIOA4_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOA4_Handler
B GPIOA4_Handler
PUBWEAK GPIOA5_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOA5_Handler
B GPIOA5_Handler
PUBWEAK GPIOA6_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOA6_Handler
B GPIOA6_Handler
PUBWEAK GPIOA7_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOA7_Handler
B GPIOA7_Handler
PUBWEAK GPIOB0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOB0_Handler
B GPIOB0_Handler
PUBWEAK GPIOB1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOB1_Handler
B GPIOB1_Handler
PUBWEAK GPIOB2_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOB2_Handler
B GPIOB2_Handler
PUBWEAK GPIOB3_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOB3_Handler
B GPIOB3_Handler
PUBWEAK GPIOB4_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOB4_Handler
B GPIOB4_Handler
PUBWEAK GPIOB5_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOB5_Handler
B GPIOB5_Handler
PUBWEAK GPIOB6_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOB6_Handler
B GPIOB6_Handler
PUBWEAK GPIOB7_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOB7_Handler
B GPIOB7_Handler
PUBWEAK GPIOC0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOC0_Handler
B GPIOC0_Handler
PUBWEAK GPIOC1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOC1_Handler
B GPIOC1_Handler
PUBWEAK GPIOC2_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOC2_Handler
B GPIOC2_Handler
PUBWEAK GPIOC3_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOC3_Handler
B GPIOC3_Handler
PUBWEAK GPIOC4_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOC4_Handler
B GPIOC4_Handler
PUBWEAK GPIOC5_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOC5_Handler
B GPIOC5_Handler
PUBWEAK GPIOC6_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOC6_Handler
B GPIOC6_Handler
PUBWEAK GPIOC7_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOC7_Handler
B GPIOC7_Handler
PUBWEAK GPIOM0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOM0_Handler
B GPIOM0_Handler
PUBWEAK GPIOM1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOM1_Handler
B GPIOM1_Handler
PUBWEAK GPIOM2_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOM2_Handler
B GPIOM2_Handler
PUBWEAK GPIOM3_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOM3_Handler
B GPIOM3_Handler
PUBWEAK GPIOM4_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOM4_Handler
B GPIOM4_Handler
PUBWEAK GPIOM5_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOM5_Handler
B GPIOM5_Handler
PUBWEAK GPIOM6_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOM6_Handler
B GPIOM6_Handler
PUBWEAK GPIOM7_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOM7_Handler
B GPIOM7_Handler
PUBWEAK DMA_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA_Handler
B DMA_Handler
PUBWEAK LCD_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
LCD_Handler
B LCD_Handler
PUBWEAK NORFLC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NORFLC_Handler
B NORFLC_Handler
PUBWEAK CAN_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN_Handler
B CAN_Handler
PUBWEAK PULSE_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PULSE_Handler
B PULSE_Handler
PUBWEAK WDT_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
WDT_Handler
B WDT_Handler
PUBWEAK PWM_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PWM_Handler
B PWM_Handler
PUBWEAK UART0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UART0_Handler
B UART0_Handler
PUBWEAK UART1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UART1_Handler
B UART1_Handler
PUBWEAK UART2_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UART2_Handler
B UART2_Handler
PUBWEAK UART3_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UART3_Handler
B UART3_Handler
PUBWEAK I2C0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C0_Handler
B I2C0_Handler
PUBWEAK I2C1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_Handler
B I2C1_Handler
PUBWEAK SPI0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI0_Handler
B SPI0_Handler
PUBWEAK ADC0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC0_Handler
B ADC0_Handler
PUBWEAK RTC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_Handler
B RTC_Handler
PUBWEAK BOD_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BOD_Handler
B BOD_Handler
PUBWEAK SDIO_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SDIO_Handler
B SDIO_Handler
PUBWEAK GPIOA_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOA_Handler
B GPIOA_Handler
PUBWEAK GPIOB_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOB_Handler
B GPIOB_Handler
PUBWEAK GPIOC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOC_Handler
B GPIOC_Handler
PUBWEAK GPIOM_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOM_Handler
B GPIOM_Handler
PUBWEAK GPION_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPION_Handler
B GPION_Handler
PUBWEAK GPIOP_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOP_Handler
B GPIOP_Handler
PUBWEAK ADC1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC1_Handler
B ADC1_Handler
PUBWEAK FPU_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
FPU_Handler
B FPU_Handler
PUBWEAK SPI1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI1_Handler
B SPI1_Handler
PUBWEAK TIMR0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
TIMR0_Handler
B TIMR0_Handler
PUBWEAK TIMR1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
TIMR1_Handler
B TIMR1_Handler
PUBWEAK TIMR2_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
TIMR2_Handler
B TIMR2_Handler
PUBWEAK TIMR3_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
TIMR3_Handler
B TIMR3_Handler
PUBWEAK TIMR4_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
TIMR4_Handler
B TIMR4_Handler
PUBWEAK TIMR5_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
TIMR5_Handler
B TIMR5_Handler
END

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@ -1,281 +0,0 @@
/******************************************************************************************************************************************
* : system_SWM320.c
* : SWM320单片机的时钟设置
* : http://www.synwit.com.cn/e/tool/gbook/?bid=1
* :
* : V1.1.0 20171025
* :
*
*
*******************************************************************************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
* -ECTION WITH THEIR PRODUCTS.
*
* COPYRIGHT 2012 Synwit Technology
*******************************************************************************************************************************************/
#include <stdint.h>
#include "SWM320.h"
/******************************************************************************************************************************************
*
*****************************************************************************************************************************************/
#define SYS_CLK_20MHz 0 //0 内部高频20MHz RC振荡器
#define SYS_CLK_40MHz 1 //1 内部高频40MHz RC振荡器
#define SYS_CLK_32KHz 2 //2 内部低频32KHz RC振荡器
#define SYS_CLK_XTAL 3 //3 外部晶体振荡器2-30MHz
#define SYS_CLK_PLL 4 //4 片内锁相环输出
#define SYS_CLK SYS_CLK_PLL
#define SYS_CLK_DIV_1 0
#define SYS_CLK_DIV_2 1
#define SYS_CLK_DIV SYS_CLK_DIV_1
#define __HSI (20000000UL) //高速内部时钟
#define __LSI (32000UL) //低速内部时钟
#define __HSE (20000000UL) //高速外部时钟
/********************************** PLL 设定 **********************************************
* VCO输出频率 = PLL输入时钟 / INDIV * 4 * FBDIV
* PLL输出频率 = PLL输入时钟 / INDIV * 4 * FBDIV / OUTDIV = VCO输出频率 / OUTDIV
* VCO输出频率需要在 [600MHz, 1200MHz]
*****************************************************************************************/
#define SYS_PLL_SRC SYS_CLK_20MHz //可取值SYS_CLK_20MHz、SYS_CLK_XTAL
#define PLL_IN_DIV 5
#define PLL_FB_DIV 60
#define PLL_OUT_DIV8 0
#define PLL_OUT_DIV4 1
#define PLL_OUT_DIV2 2
#define PLL_OUT_DIV PLL_OUT_DIV8
uint32_t SystemCoreClock = __HSI; //System Clock Frequency (Core Clock)
uint32_t CyclesPerUs = (__HSI / 1000000); //Cycles per micro second
/******************************************************************************************************************************************
* :
* : This function is used to update the variable SystemCoreClock and must be called whenever the core clock is changed
* :
* :
* :
******************************************************************************************************************************************/
void SystemCoreClockUpdate(void)
{
if (SYS->CLKSEL & SYS_CLKSEL_SYS_Msk) //SYS_CLK <= HFCK
{
if (SYS->CLKSEL & SYS_CLKSEL_HFCK_Msk) //HFCK <= XTAL
{
SystemCoreClock = __HSE;
}
else //HFCK <= HRC
{
if (SYS->HRCCR & SYS_HRCCR_DBL_Msk) //HRC = 40MHz
{
SystemCoreClock = __HSI * 2;
}
else //HRC = 20MHz
{
SystemCoreClock = __HSI;
}
}
}
else //SYS_CLK <= LFCK
{
if (SYS->CLKSEL & SYS_CLKSEL_LFCK_Msk) //LFCK <= PLL
{
if (SYS->PLLCR & SYS_PLLCR_INSEL_Msk) //PLL_SRC <= HRC
{
SystemCoreClock = __HSI;
}
else //PLL_SRC <= XTAL
{
SystemCoreClock = __HSE;
}
SystemCoreClock = SystemCoreClock / PLL_IN_DIV * PLL_FB_DIV * 4 / (2 << (2 - PLL_OUT_DIV));
}
else //LFCK <= LRC
{
SystemCoreClock = __LSI;
}
}
if (SYS->CLKDIV & SYS_CLKDIV_SYS_Msk)
SystemCoreClock /= 2;
CyclesPerUs = SystemCoreClock / 1000000;
}
/******************************************************************************************************************************************
* :
* : The necessary initializaiton of systerm
* :
* :
* :
******************************************************************************************************************************************/
void SystemInit(void)
{
SYS->CLKEN |= (1 << SYS_CLKEN_ANAC_Pos);
Flash_Param_at_xMHz(120);
switch (SYS_CLK)
{
case SYS_CLK_20MHz: //0 内部高频20MHz RC振荡器
switchCLK_20MHz();
break;
case SYS_CLK_40MHz: //1 内部高频40MHz RC振荡器
switchCLK_40MHz();
break;
case SYS_CLK_32KHz: //2 内部低频32KHz RC振荡器
switchCLK_32KHz();
break;
case SYS_CLK_XTAL: //3 外部晶体振荡器2-30MHz
switchCLK_XTAL();
break;
case SYS_CLK_PLL: //4 片内锁相环输出
switchCLK_PLL();
break;
}
SYS->CLKDIV &= ~SYS_CLKDIV_SYS_Msk;
SYS->CLKDIV |= (SYS_CLK_DIV << SYS_CLKDIV_SYS_Pos);
SystemCoreClockUpdate();
if (SystemCoreClock > 80000000)
{
Flash_Param_at_xMHz(120);
}
else if (SystemCoreClock > 40000000)
{
Flash_Param_at_xMHz(80);
}
else if (SystemCoreClock > 30000000)
{
Flash_Param_at_xMHz(40);
}
else
{
Flash_Param_at_xMHz(30);
}
}
static void delay_3ms(void)
{
uint32_t i;
if (((SYS->CLKSEL & SYS_CLKSEL_SYS_Msk) == 0) &&
((SYS->CLKSEL & SYS_CLKSEL_LFCK_Msk) == 0)) //32KHz
{
for (i = 0; i < 20; i++)
__NOP();
}
else
{
for (i = 0; i < 20000; i++)
__NOP();
}
}
void switchCLK_20MHz(void)
{
SYS->HRCCR = (0 << SYS_HRCCR_OFF_Pos) |
(0 << SYS_HRCCR_DBL_Pos); //HRC = 20MHz
delay_3ms();
SYS->CLKSEL &= ~SYS_CLKSEL_HFCK_Msk; //HFCK <= HRC
SYS->CLKSEL |= (1 << SYS_CLKSEL_SYS_Pos); //SYS_CLK <= HFCK
}
void switchCLK_40MHz(void)
{
SYS->HRCCR = (0 << SYS_HRCCR_OFF_Pos) |
(1 << SYS_HRCCR_DBL_Pos); //HRC = 40MHz
delay_3ms();
SYS->CLKSEL &= ~SYS_CLKSEL_HFCK_Msk; //HFCK <= HRC
SYS->CLKSEL |= (1 << SYS_CLKSEL_SYS_Pos); //SYS_CLK <= HFCK
}
void switchCLK_32KHz(void)
{
SYS->CLKEN |= (1 << SYS_CLKEN_RTCBKP_Pos);
SYS->LRCCR &= ~(1 << SYS_LRCCR_OFF_Pos);
delay_3ms();
SYS->CLKSEL &= ~SYS_CLKSEL_LFCK_Msk; //LFCK <= LRC
SYS->CLKSEL &= ~SYS_CLKSEL_SYS_Msk; //SYS_CLK <= LFCK
}
void switchCLK_XTAL(void)
{
SYS->XTALCR = (1 << SYS_XTALCR_EN_Pos);
delay_3ms();
delay_3ms();
SYS->CLKSEL |= (1 << SYS_CLKSEL_HFCK_Pos); //HFCK <= XTAL
SYS->CLKSEL |= (1 << SYS_CLKSEL_SYS_Pos); //SYS_CLK <= HFCK
}
void switchCLK_PLL(void)
{
PLLInit();
SYS->PLLCR |= (1 << SYS_PLLCR_OUTEN_Pos);
SYS->CLKSEL |= (1 << SYS_CLKSEL_LFCK_Pos); //LFCK <= PLL
SYS->CLKSEL &= ~SYS_CLKSEL_SYS_Msk; //SYS_CLK <= LFCK
}
void PLLInit(void)
{
if (SYS_PLL_SRC == SYS_CLK_20MHz)
{
SYS->HRCCR = (0 << SYS_HRCCR_OFF_Pos) |
(0 << SYS_HRCCR_DBL_Pos); //HRC = 20MHz
delay_3ms();
SYS->PLLCR |= (1 << SYS_PLLCR_INSEL_Pos); //PLL_SRC <= HRC
}
else if (SYS_PLL_SRC == SYS_CLK_XTAL)
{
SYS->XTALCR = (1 << SYS_XTALCR_EN_Pos);
delay_3ms();
delay_3ms();
SYS->PLLCR &= ~(1 << SYS_PLLCR_INSEL_Pos); //PLL_SRC <= XTAL
}
SYS->PLLDIV &= ~(SYS_PLLDIV_INDIV_Msk |
SYS_PLLDIV_FBDIV_Msk |
SYS_PLLDIV_OUTDIV_Msk);
SYS->PLLDIV |= (PLL_IN_DIV << SYS_PLLDIV_INDIV_Pos) |
(PLL_FB_DIV << SYS_PLLDIV_FBDIV_Pos) |
(PLL_OUT_DIV << SYS_PLLDIV_OUTDIV_Pos);
SYS->PLLCR &= ~(1 << SYS_PLLCR_OFF_Pos);
while (SYS->PLLLOCK == 0)
; //等待PLL锁定
}

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@ -1,28 +0,0 @@
#ifndef __SYSTEM_SWM320_H__
#define __SYSTEM_SWM320_H__
#ifdef __cplusplus
extern "C"
{
#endif
extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock)
extern uint32_t CyclesPerUs; // Cycles per micro second
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
extern void switchCLK_20MHz(void);
extern void switchCLK_40MHz(void);
extern void switchCLK_32KHz(void);
extern void switchCLK_XTAL(void);
extern void switchCLK_PLL(void);
extern void PLLInit(void);
#ifdef __cplusplus
}
#endif
#endif //__SYSTEM_SWM320_H__

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@ -1,17 +0,0 @@
from building import *
import rtconfig
cwd = GetCurrentDir()
src = Glob('CMSIS/DeviceSupport/*.c')
CPPPATH = [cwd + '/CMSIS/CoreSupport', cwd + '/CMSIS/DeviceSupport', cwd + '/SWM320_StdPeriph_Driver']
src += Glob('SWM320_StdPeriph_Driver/*.c')
if rtconfig.CROSS_TOOL == 'gcc':
src += ['CMSIS/DeviceSupport/startup/gcc/startup_SWM320.s']
elif rtconfig.CROSS_TOOL == 'keil':
src += ['CMSIS/DeviceSupport/startup/arm/startup_SWM320.s']
elif rtconfig.CROSS_TOOL == 'iar':
src += ['CMSIS/DeviceSupport/startup/iar/startup_SWM320.s']
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

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@ -1,525 +0,0 @@
/******************************************************************************************************************************************
* : SWM320_adc.c
* : SWM320单片机的ADC数模转换器功能驱动库
* : http://www.synwit.com.cn/e/tool/gbook/?bid=1
* :
* : V1.1.0 20171025
* :
*******************************************************************************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
* -ECTION WITH THEIR PRODUCTS.
*
* COPYRIGHT 2012 Synwit Technology
*******************************************************************************************************************************************/
#include "SWM320.h"
#include "SWM320_adc.h"
/******************************************************************************************************************************************
* : ADC_Init()
* : ADC模数转换器初始化
* : ADC_TypeDef * ADCx ADCADC0ADC1
* ADC_InitStructure * initStruct ADC各相关定值的结构体
* :
* :
******************************************************************************************************************************************/
void ADC_Init(ADC_TypeDef *ADCx, ADC_InitStructure *initStruct)
{
switch ((uint32_t)ADCx)
{
case ((uint32_t)ADC0):
SYS->CLKEN |= (0x01 << SYS_CLKEN_ADC0_Pos);
break;
case ((uint32_t)ADC1):
SYS->CLKEN |= (0x01 << SYS_CLKEN_ADC1_Pos);
break;
}
ADC_Close(ADCx); //一些关键寄存器只能在ADC关闭时设置
if (initStruct->clk_src == ADC_CLKSRC_HRC)
{
ADCx->CTRL |= (1 << ADC_CTRL_CLKSRC_Pos);
ADCx->CTRL2 &= ~ADC_CTRL2_CLKDIV_Msk;
ADCx->CTRL2 |= (initStruct->clk_div << ADC_CTRL2_CLKDIV_Pos);
}
else
{
if (SYS->PLLCR & SYS_PLLCR_OFF_Msk)
PLLInit();
ADCx->CTRL &= ~(1 << ADC_CTRL_CLKSRC_Pos);
SYS->PLLDIV &= ~SYS_PLLDIV_ADVCO_Msk;
SYS->PLLDIV |= ((initStruct->clk_src - 2) << SYS_PLLDIV_ADVCO_Pos);
SYS->PLLDIV &= ~SYS_PLLDIV_ADDIV_Msk;
SYS->PLLDIV |= (initStruct->clk_div << SYS_PLLDIV_ADDIV_Pos);
}
ADCx->CALIBSET = (ADCx == ADC0) ? SYS->BKP[0] : SYS->BKP[1];
ADCx->CALIBEN = (1 << ADC_CALIBEN_OFFSET_Pos) | (1 << ADC_CALIBEN_K_Pos);
ADCx->CTRL2 &= ~(ADC_CTRL2_ADCEVCM_Msk | ADC_CTRL2_PGAIVCM_Msk | ADC_CTRL2_PGAGAIN_Msk | ADC_CTRL2_PGAVCM_Msk);
ADCx->CTRL2 |= (0 << ADC_CTRL2_ADCEVCM_Pos) |
(initStruct->pga_ref << ADC_CTRL2_PGAIVCM_Pos) |
(6 << ADC_CTRL2_PGAGAIN_Pos) |
((uint32_t)6 << ADC_CTRL2_PGAVCM_Pos);
ADCx->CTRL &= ~(0xFF << ADC_CTRL_CH0_Pos);
ADCx->CTRL |= (initStruct->channels << ADC_CTRL_CH0_Pos);
ADCx->CTRL &= ~(ADC_CTRL_AVG_Msk | ADC_CTRL_TRIG_Msk | ADC_CTRL_CONT_Msk);
ADCx->CTRL |= (initStruct->samplAvg << ADC_CTRL_AVG_Pos) |
(initStruct->trig_src << ADC_CTRL_TRIG_Pos) |
(initStruct->Continue << ADC_CTRL_CONT_Pos);
ADCx->IF = 0xFFFFFFFF; //清除中断标志
ADCx->IE &= ~(ADC_IE_CH0EOC_Msk | ADC_IE_CH1EOC_Msk | ADC_IE_CH2EOC_Msk | ADC_IE_CH3EOC_Msk |
ADC_IE_CH4EOC_Msk | ADC_IE_CH5EOC_Msk | ADC_IE_CH6EOC_Msk | ADC_IE_CH7EOC_Msk);
ADCx->IE |= (((initStruct->EOC_IEn & ADC_CH0) ? 1 : 0) << ADC_IE_CH0EOC_Pos) |
(((initStruct->EOC_IEn & ADC_CH1) ? 1 : 0) << ADC_IE_CH1EOC_Pos) |
(((initStruct->EOC_IEn & ADC_CH2) ? 1 : 0) << ADC_IE_CH2EOC_Pos) |
(((initStruct->EOC_IEn & ADC_CH3) ? 1 : 0) << ADC_IE_CH3EOC_Pos) |
(((initStruct->EOC_IEn & ADC_CH4) ? 1 : 0) << ADC_IE_CH4EOC_Pos) |
(((initStruct->EOC_IEn & ADC_CH5) ? 1 : 0) << ADC_IE_CH5EOC_Pos) |
(((initStruct->EOC_IEn & ADC_CH6) ? 1 : 0) << ADC_IE_CH6EOC_Pos) |
(((initStruct->EOC_IEn & ADC_CH7) ? 1 : 0) << ADC_IE_CH7EOC_Pos);
ADCx->IE &= ~(ADC_IE_CH0OVF_Msk | ADC_IE_CH1OVF_Msk | ADC_IE_CH2OVF_Msk | ADC_IE_CH3OVF_Msk |
ADC_IE_CH4OVF_Msk | ADC_IE_CH5OVF_Msk | ADC_IE_CH6OVF_Msk | ADC_IE_CH7OVF_Msk);
ADCx->IE |= (((initStruct->OVF_IEn & ADC_CH0) ? 1 : 0) << ADC_IE_CH0OVF_Pos) |
(((initStruct->OVF_IEn & ADC_CH1) ? 1 : 0) << ADC_IE_CH1OVF_Pos) |
(((initStruct->OVF_IEn & ADC_CH2) ? 1 : 0) << ADC_IE_CH2OVF_Pos) |
(((initStruct->OVF_IEn & ADC_CH3) ? 1 : 0) << ADC_IE_CH3OVF_Pos) |
(((initStruct->OVF_IEn & ADC_CH4) ? 1 : 0) << ADC_IE_CH4OVF_Pos) |
(((initStruct->OVF_IEn & ADC_CH5) ? 1 : 0) << ADC_IE_CH5OVF_Pos) |
(((initStruct->OVF_IEn & ADC_CH6) ? 1 : 0) << ADC_IE_CH6OVF_Pos) |
(((initStruct->OVF_IEn & ADC_CH7) ? 1 : 0) << ADC_IE_CH7OVF_Pos);
ADCx->IE &= ~(ADC_IE_CH0HFULL_Msk | ADC_IE_CH1HFULL_Msk | ADC_IE_CH2HFULL_Msk | ADC_IE_CH3HFULL_Msk |
ADC_IE_CH4HFULL_Msk | ADC_IE_CH5HFULL_Msk | ADC_IE_CH6HFULL_Msk | ADC_IE_CH7HFULL_Msk);
ADCx->IE |= (((initStruct->HFULL_IEn & ADC_CH0) ? 1 : 0) << ADC_IE_CH0HFULL_Pos) |
(((initStruct->HFULL_IEn & ADC_CH1) ? 1 : 0) << ADC_IE_CH1HFULL_Pos) |
(((initStruct->HFULL_IEn & ADC_CH2) ? 1 : 0) << ADC_IE_CH2HFULL_Pos) |
(((initStruct->HFULL_IEn & ADC_CH3) ? 1 : 0) << ADC_IE_CH3HFULL_Pos) |
(((initStruct->HFULL_IEn & ADC_CH4) ? 1 : 0) << ADC_IE_CH4HFULL_Pos) |
(((initStruct->HFULL_IEn & ADC_CH5) ? 1 : 0) << ADC_IE_CH5HFULL_Pos) |
(((initStruct->HFULL_IEn & ADC_CH6) ? 1 : 0) << ADC_IE_CH6HFULL_Pos) |
(((initStruct->HFULL_IEn & ADC_CH7) ? 1 : 0) << ADC_IE_CH7HFULL_Pos);
ADCx->IE &= ~(uint32_t)(ADC_IE_CH0FULL_Msk | ADC_IE_CH1FULL_Msk | ADC_IE_CH2FULL_Msk | ADC_IE_CH3FULL_Msk |
ADC_IE_CH4FULL_Msk | ADC_IE_CH5FULL_Msk | ADC_IE_CH6FULL_Msk | ADC_IE_CH7FULL_Msk);
ADCx->IE |= (((initStruct->FULL_IEn & ADC_CH0) ? 1 : 0) << ADC_IE_CH0FULL_Pos) |
(((initStruct->FULL_IEn & ADC_CH1) ? 1 : 0) << ADC_IE_CH1FULL_Pos) |
(((initStruct->FULL_IEn & ADC_CH2) ? 1 : 0) << ADC_IE_CH2FULL_Pos) |
(((initStruct->FULL_IEn & ADC_CH3) ? 1 : 0) << ADC_IE_CH3FULL_Pos) |
(((initStruct->FULL_IEn & ADC_CH4) ? 1 : 0) << ADC_IE_CH4FULL_Pos) |
(((initStruct->FULL_IEn & ADC_CH5) ? 1 : 0) << ADC_IE_CH5FULL_Pos) |
(((initStruct->FULL_IEn & ADC_CH6) ? 1 : 0) << ADC_IE_CH6FULL_Pos) |
(((initStruct->FULL_IEn & ADC_CH7) ? 1 : 0) << ADC_IE_CH7FULL_Pos);
switch ((uint32_t)ADCx)
{
case ((uint32_t)ADC0):
if (initStruct->EOC_IEn | initStruct->OVF_IEn | initStruct->HFULL_IEn | initStruct->FULL_IEn)
{
NVIC_EnableIRQ(ADC0_IRQn);
}
else
{
NVIC_DisableIRQ(ADC0_IRQn);
}
break;
case ((uint32_t)ADC1):
if (initStruct->EOC_IEn | initStruct->OVF_IEn | initStruct->HFULL_IEn | initStruct->FULL_IEn)
{
NVIC_EnableIRQ(ADC1_IRQn);
}
else
{
NVIC_DisableIRQ(ADC1_IRQn);
}
break;
}
}
/******************************************************************************************************************************************
* : ADC_Open()
* : ADC开启ADC转换
* : ADC_TypeDef * ADCx ADCADC
* :
* :
******************************************************************************************************************************************/
void ADC_Open(ADC_TypeDef *ADCx)
{
ADCx->CTRL |= (0x01 << ADC_CTRL_EN_Pos);
}
/******************************************************************************************************************************************
* : ADC_Close()
* : ADC关闭ADC转换
* : ADC_TypeDef * ADCx ADCADC
* :
* :
******************************************************************************************************************************************/
void ADC_Close(ADC_TypeDef *ADCx)
{
ADCx->CTRL &= ~(0x01 << ADC_CTRL_EN_Pos);
}
/******************************************************************************************************************************************
* : ADC_Start()
* : ADC转换
* : ADC_TypeDef * ADCx ADCADC
* :
* :
******************************************************************************************************************************************/
void ADC_Start(ADC_TypeDef *ADCx)
{
ADCx->START |= (0x01 << ADC_START_GO_Pos);
}
/******************************************************************************************************************************************
* : ADC_Stop()
* : ADC转换
* : ADC_TypeDef * ADCx ADCADC
* :
* :
******************************************************************************************************************************************/
void ADC_Stop(ADC_TypeDef *ADCx)
{
ADCx->START &= ~(0x01 << ADC_START_GO_Pos);
}
static uint32_t chn2idx(uint32_t chn)
{
uint32_t idx = 0;
switch (chn)
{
case 0x01:
idx = 0;
break;
case 0x02:
idx = 1;
break;
case 0x04:
idx = 2;
break;
case 0x08:
idx = 3;
break;
case 0x10:
idx = 4;
break;
case 0x20:
idx = 5;
break;
case 0x40:
idx = 6;
break;
case 0x80:
idx = 7;
break;
}
return idx;
}
/******************************************************************************************************************************************
* : ADC_Read()
* :
* : ADC_TypeDef * ADCx ADCADC
* uint32_t chn ADC_CH0ADC_CH1... ... ADC_CH7
* : uint32_t
* :
******************************************************************************************************************************************/
uint32_t ADC_Read(ADC_TypeDef *ADCx, uint32_t chn)
{
uint32_t dat = 0;
uint32_t idx = chn2idx(chn);
dat = ADCx->CH[idx].DATA;
ADCx->CH[idx].STAT = 0x01; //清除EOC标志
return dat;
}
/******************************************************************************************************************************************
* : ADC_IsEOC()
* : End Of Conversion
* : ADC_TypeDef * ADCx ADCADC
* uint32_t chn ADC_CH0ADC_CH1... ... ADC_CH7
* : uint32_t 1 0
* :
******************************************************************************************************************************************/
uint32_t ADC_IsEOC(ADC_TypeDef *ADCx, uint32_t chn)
{
uint32_t idx = chn2idx(chn);
return (ADCx->CH[idx].STAT & ADC_STAT_EOC_Msk) ? 1 : 0;
}
/******************************************************************************************************************************************
* : ADC_ChnSelect()
* : ADC通道选通
* : ADC_TypeDef * ADCx ADCADC
* uint32_t chns ADC_CH0ADC_CH1... ... ADC_CH7及其组合
* :
* :
******************************************************************************************************************************************/
void ADC_ChnSelect(ADC_TypeDef *ADCx, uint32_t chns)
{
ADCx->CTRL &= ~(0xFF << ADC_CTRL_CH0_Pos);
ADCx->CTRL |= (chns << ADC_CTRL_CH0_Pos);
}
/******************************************************************************************************************************************
* : ADC_IntEOCEn()
* : 使
* : ADC_TypeDef * ADCx ADCADC
* uint32_t chn ADC_CH0ADC_CH1... ... ADC_CH7
* :
* :
******************************************************************************************************************************************/
void ADC_IntEOCEn(ADC_TypeDef *ADCx, uint32_t chn)
{
uint32_t idx = chn2idx(chn);
ADCx->IE |= (0x01 << (idx * 4));
}
/******************************************************************************************************************************************
* : ADC_IntEOCDis()
* :
* : ADC_TypeDef * ADCx ADCADC
* uint32_t chn ADC_CH0ADC_CH1... ... ADC_CH7
* :
* :
******************************************************************************************************************************************/
void ADC_IntEOCDis(ADC_TypeDef *ADCx, uint32_t chn)
{
uint32_t idx = chn2idx(chn);
ADCx->IE &= ~(0x01 << (idx * 4));
}
/******************************************************************************************************************************************
* : ADC_IntEOCClr()
* :
* : ADC_TypeDef * ADCx ADCADC
* uint32_t chn ADC_CH0ADC_CH1... ... ADC_CH7
* :
* :
******************************************************************************************************************************************/
void ADC_IntEOCClr(ADC_TypeDef *ADCx, uint32_t chn)
{
uint32_t idx = chn2idx(chn);
ADCx->IF = (0x01 << (idx * 4));
}
/******************************************************************************************************************************************
* : ADC_IntEOCStat()
* :
* : ADC_TypeDef * ADCx ADCADC
* uint32_t chn ADC_CH0ADC_CH1... ... ADC_CH7
* : uint32_t 1 0
* :
******************************************************************************************************************************************/
uint32_t ADC_IntEOCStat(ADC_TypeDef *ADCx, uint32_t chn)
{
uint32_t idx = chn2idx(chn);
return (ADCx->IF & (0x01 << (idx * 4))) ? 1 : 0;
}
/******************************************************************************************************************************************
* : ADC_IntOVFEn()
* : 使
* : ADC_TypeDef * ADCx ADCADC
* uint32_t chn ADC_CH0ADC_CH1... ... ADC_CH7
* :
* :
******************************************************************************************************************************************/
void ADC_IntOVFEn(ADC_TypeDef *ADCx, uint32_t chn)
{
uint32_t idx = chn2idx(chn);
ADCx->IE |= (0x01 << (idx * 4 + 1));
}
/******************************************************************************************************************************************
* : ADC_IntOVFDis()
* :
* : ADC_TypeDef * ADCx ADCADC
* uint32_t chn ADC_CH0ADC_CH1... ... ADC_CH7
* :
* :
******************************************************************************************************************************************/
void ADC_IntOVFDis(ADC_TypeDef *ADCx, uint32_t chn)
{
uint32_t idx = chn2idx(chn);
ADCx->IE &= ~(0x01 << (idx * 4 + 1));
}
/******************************************************************************************************************************************
* : ADC_IntOVFClr()
* :
* : ADC_TypeDef * ADCx ADCADC
* uint32_t chn ADC_CH0ADC_CH1... ... ADC_CH7
* :
* :
******************************************************************************************************************************************/
void ADC_IntOVFClr(ADC_TypeDef *ADCx, uint32_t chn)
{
uint32_t idx = chn2idx(chn);
ADCx->IF = (0x01 << (idx * 4 + 1));
}
/******************************************************************************************************************************************
* : ADC_IntOVFStat()
* :
* : ADC_TypeDef * ADCx ADCADC
* uint32_t chn ADC_CH0ADC_CH1... ... ADC_CH7
* : uint32_t 1 0
* :
******************************************************************************************************************************************/
uint32_t ADC_IntOVFStat(ADC_TypeDef *ADCx, uint32_t chn)
{
uint32_t idx = chn2idx(chn);
return (ADCx->IF & (0x01 << (idx * 4 + 1))) ? 1 : 0;
}
/******************************************************************************************************************************************
* : ADC_IntHFULLEn()
* : FIFO半满中断使能
* : ADC_TypeDef * ADCx ADCADC
* uint32_t chn ADC_CH0ADC_CH1... ... ADC_CH7
* :
* :
******************************************************************************************************************************************/
void ADC_IntHFULLEn(ADC_TypeDef *ADCx, uint32_t chn)
{
uint32_t idx = chn2idx(chn);
ADCx->IE |= (0x01 << (idx * 4 + 2));
}
/******************************************************************************************************************************************
* : ADC_IntHFULLDis()
* : FIFO半满中断禁止
* : ADC_TypeDef * ADCx ADCADC
* uint32_t chn ADC_CH0ADC_CH1... ... ADC_CH7
* :
* :
******************************************************************************************************************************************/
void ADC_IntHFULLDis(ADC_TypeDef *ADCx, uint32_t chn)
{
uint32_t idx = chn2idx(chn);
ADCx->IE &= ~(0x01 << (idx * 4 + 2));
}
/******************************************************************************************************************************************
* : ADC_IntHFULLClr()
* : FIFO半满中断标志清除
* : ADC_TypeDef * ADCx ADCADC
* uint32_t chn ADC_CH0ADC_CH1... ... ADC_CH7
* :
* :
******************************************************************************************************************************************/
void ADC_IntHFULLClr(ADC_TypeDef *ADCx, uint32_t chn)
{
uint32_t idx = chn2idx(chn);
ADCx->IF = (0x01 << (idx * 4 + 2));
}
/******************************************************************************************************************************************
* : ADC_IntHFULLStat()
* : FIFO半满中断状态
* : ADC_TypeDef * ADCx ADCADC
* uint32_t chn ADC_CH0ADC_CH1... ... ADC_CH7
* : uint32_t 1 0
* :
******************************************************************************************************************************************/
uint32_t ADC_IntHFULLStat(ADC_TypeDef *ADCx, uint32_t chn)
{
uint32_t idx = chn2idx(chn);
return (ADCx->IF & (0x01 << (idx * 4 + 2))) ? 1 : 0;
}
/******************************************************************************************************************************************
* : ADC_IntFULLEn()
* : FIFO满中断使能
* : ADC_TypeDef * ADCx ADCADC
* uint32_t chn ADC_CH0ADC_CH1... ... ADC_CH7
* :
* :
******************************************************************************************************************************************/
void ADC_IntFULLEn(ADC_TypeDef *ADCx, uint32_t chn)
{
uint32_t idx = chn2idx(chn);
ADCx->IE |= (0x01 << (idx * 4 + 3));
}
/******************************************************************************************************************************************
* : ADC_IntFULLDis()
* : FIFO满中断禁止
* : ADC_TypeDef * ADCx ADCADC
* uint32_t chn ADC_CH0ADC_CH1... ... ADC_CH7
* :
* :
******************************************************************************************************************************************/
void ADC_IntFULLDis(ADC_TypeDef *ADCx, uint32_t chn)
{
uint32_t idx = chn2idx(chn);
ADCx->IE &= ~(0x01 << (idx * 4 + 3));
}
/******************************************************************************************************************************************
* : ADC_IntFULLClr()
* : FIFO满中断标志清除
* : ADC_TypeDef * ADCx ADCADC
* uint32_t chn ADC_CH0ADC_CH1... ... ADC_CH7
* :
* :
******************************************************************************************************************************************/
void ADC_IntFULLClr(ADC_TypeDef *ADCx, uint32_t chn)
{
uint32_t idx = chn2idx(chn);
ADCx->IF = (0x01 << (idx * 4 + 3));
}
/******************************************************************************************************************************************
* : ADC_IntFULLStat()
* : FIFO满中断状态
* : ADC_TypeDef * ADCx ADCADC
* uint32_t chn ADC_CH0ADC_CH1... ... ADC_CH7
* : uint32_t 1 0
* :
******************************************************************************************************************************************/
uint32_t ADC_IntFULLStat(ADC_TypeDef *ADCx, uint32_t chn)
{
uint32_t idx = chn2idx(chn);
return (ADCx->IF & (0x01 << (idx * 4 + 3))) ? 1 : 0;
}

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@ -1,77 +0,0 @@
#ifndef __SWM320_ADC_H__
#define __SWM320_ADC_H__
typedef struct
{
uint8_t clk_src; //ADC转换时钟源ADC_CLKSRC_HRC、ADC_CLKSRC_VCO_DIV16、ADC_CLKSRC_VCO_DIV32、ADC_CLKSRC_VCO_DIV32
uint8_t clk_div; //ADC转换时钟分频取值1--31
uint8_t pga_ref; //PGA基准PGA_REF_INTERNAL、PGA_REF_EXTERNAL
uint8_t channels; //ADC转换通道选中ADC_CH0、ADC_CH1、... ... 、ADC_CH7及其组合即“按位或”运算
uint8_t samplAvg; //采样取平均触发启动ADC转换后ADC在一个通道上连续采样、转换多次并将它们的平均值作为该通道转换结果
uint8_t trig_src; //ADC触发方式ADC_TRIGSRC_SW、ADC_TRIGSRC_PWM、ADC_TRIGSRC_TIMR2、ADC_TRIGSRC_TIMR3
uint8_t Continue; //在软件触发模式下1 连续转换模式启动后一直采样、转换直到软件清除START位
// 0 单次转换模式转换完成后START位自动清除停止转换
uint8_t EOC_IEn; //EOC中断使能可针对每个通道设置其有效值为ADC_CH0、ADC_CH1、... ... 、ADC_CH7及其组合即“按位或”运算
uint8_t OVF_IEn; //OVF中断使能可针对每个通道设置其有效值为ADC_CH0、ADC_CH1、... ... 、ADC_CH7及其组合即“按位或”运算
uint8_t HFULL_IEn; //FIFO半满中断使能可针对每个通道设置其有效值为ADC_CH0、ADC_CH1、... ... 、ADC_CH7及其组合即“按位或”运算
uint8_t FULL_IEn; //FIFO 满中断使能可针对每个通道设置其有效值为ADC_CH0、ADC_CH1、... ... 、ADC_CH7及其组合即“按位或”运算
} ADC_InitStructure;
#define ADC_CH0 0x01
#define ADC_CH1 0x02
#define ADC_CH2 0x04
#define ADC_CH3 0x08
#define ADC_CH4 0x10
#define ADC_CH5 0x20
#define ADC_CH6 0x40
#define ADC_CH7 0x80
#define ADC_CLKSRC_HRC 1
#define ADC_CLKSRC_VCO_DIV16 2
#define ADC_CLKSRC_VCO_DIV32 3
#define ADC_CLKSRC_VCO_DIV64 4
#define ADC_AVG_SAMPLE1 0
#define ADC_AVG_SAMPLE2 1 //一次启动连续采样、转换2次并计算两次结果的平均值作为转换结果
#define ADC_AVG_SAMPLE4 3
#define ADC_AVG_SAMPLE8 7
#define ADC_AVG_SAMPLE16 15
#define ADC_TRIGSRC_SW 0 //软件触发即ADC->START.GO写1启动转换
#define ADC_TRIGSRC_PWM 1
#define PGA_REF_INTERNAL 1 //PGA输入共模电平由内部电路产生ADC_REFP和ADC_REFN可悬空
#define PGA_REF_EXTERNAL 0 //PGA输入共模电平由外部引脚提供(ADC_REFP + ADC_REFN) 电平值须与量程相同
void ADC_Init(ADC_TypeDef *ADCx, ADC_InitStructure *initStruct); //ADC模数转换器初始化
void ADC_Open(ADC_TypeDef *ADCx); //ADC开启可以软件启动、或硬件触发ADC转换
void ADC_Close(ADC_TypeDef *ADCx); //ADC关闭无法软件启动、或硬件触发ADC转换
void ADC_Start(ADC_TypeDef *ADCx); //启动指定ADC开始模数转换
void ADC_Stop(ADC_TypeDef *ADCx); //关闭指定ADC停止模数转换
uint32_t ADC_Read(ADC_TypeDef *ADCx, uint32_t chn); //从指定通道读取转换结果
uint32_t ADC_IsEOC(ADC_TypeDef *ADCx, uint32_t chn); //指定通道是否End Of Conversion
void ADC_ChnSelect(ADC_TypeDef *ADCx, uint32_t chns);
void ADC_IntEOCEn(ADC_TypeDef *ADCx, uint32_t chn); //转换完成中断使能
void ADC_IntEOCDis(ADC_TypeDef *ADCx, uint32_t chn); //转换完成中断禁止
void ADC_IntEOCClr(ADC_TypeDef *ADCx, uint32_t chn); //转换完成中断标志清除
uint32_t ADC_IntEOCStat(ADC_TypeDef *ADCx, uint32_t chn); //转换完成中断状态
void ADC_IntOVFEn(ADC_TypeDef *ADCx, uint32_t chn); //数据溢出中断使能
void ADC_IntOVFDis(ADC_TypeDef *ADCx, uint32_t chn); //数据溢出中断禁止
void ADC_IntOVFClr(ADC_TypeDef *ADCx, uint32_t chn); //数据溢出中断标志清除
uint32_t ADC_IntOVFStat(ADC_TypeDef *ADCx, uint32_t chn); //数据溢出中断状态
void ADC_IntHFULLEn(ADC_TypeDef *ADCx, uint32_t chn); //FIFO半满中断使能
void ADC_IntHFULLDis(ADC_TypeDef *ADCx, uint32_t chn); //FIFO半满中断禁止
void ADC_IntHFULLClr(ADC_TypeDef *ADCx, uint32_t chn); //FIFO半满中断标志清除
uint32_t ADC_IntHFULLStat(ADC_TypeDef *ADCx, uint32_t chn); //FIFO半满中断状态
void ADC_IntFULLEn(ADC_TypeDef *ADCx, uint32_t chn); //FIFO满中断使能
void ADC_IntFULLDis(ADC_TypeDef *ADCx, uint32_t chn); //FIFO满中断禁止
void ADC_IntFULLClr(ADC_TypeDef *ADCx, uint32_t chn); //FIFO满中断标志清除
uint32_t ADC_IntFULLStat(ADC_TypeDef *ADCx, uint32_t chn); //FIFO满中断状态
#endif //__SWM320_ADC_H__

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@ -1,603 +0,0 @@
/******************************************************************************************************************************************
* : SWM320_can.c
* : SWM320单片机的CAN模块驱动库
* : http://www.synwit.com.cn/e/tool/gbook/?bid=1
* :
* : V1.1.0 20171025
* :
*
*
*******************************************************************************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
* -ECTION WITH THEIR PRODUCTS.
*
* COPYRIGHT 2012 Synwit Technology
*******************************************************************************************************************************************/
#include "SWM320.h"
#include "SWM320_can.h"
/******************************************************************************************************************************************
* : CAN_Init()
* : CAN接口初始化
* : CAN_TypeDef * CANx CAN接口CAN
* CAN_InitStructure * initStruct CAN接口相关设定值的结构体
* :
* :
******************************************************************************************************************************************/
void CAN_Init(CAN_TypeDef *CANx, CAN_InitStructure *initStruct)
{
switch ((uint32_t)CANx)
{
case ((uint32_t)CAN):
SYS->CLKEN |= (0x01 << SYS_CLKEN_CAN_Pos);
break;
}
CAN_Close(CANx); //一些关键寄存器只能在CAN关闭时设置
CANx->CR &= ~(CAN_CR_LOM_Msk | CAN_CR_STM_Msk | CAN_CR_AFM_Msk);
CANx->CR |= (initStruct->Mode << CAN_CR_LOM_Pos) |
(initStruct->FilterMode << CAN_CR_AFM_Pos);
CANx->FILTER.AMR[3] = initStruct->FilterMask32b & 0xFF;
CANx->FILTER.AMR[2] = (initStruct->FilterMask32b >> 8) & 0xFF;
CANx->FILTER.AMR[1] = (initStruct->FilterMask32b >> 16) & 0xFF;
CANx->FILTER.AMR[0] = (initStruct->FilterMask32b >> 24) & 0xFF;
CANx->FILTER.ACR[3] = initStruct->FilterCheck32b & 0xFF;
CANx->FILTER.ACR[2] = (initStruct->FilterCheck32b >> 8) & 0xFF;
CANx->FILTER.ACR[1] = (initStruct->FilterCheck32b >> 16) & 0xFF;
CANx->FILTER.ACR[0] = (initStruct->FilterCheck32b >> 24) & 0xFF;
CANx->BT1 = (0 << CAN_BT1_SAM_Pos) |
(initStruct->CAN_BS1 << CAN_BT1_TSEG1_Pos) |
(initStruct->CAN_BS2 << CAN_BT1_TSEG2_Pos);
CANx->BT0 = (initStruct->CAN_SJW << CAN_BT0_SJW_Pos) |
((SystemCoreClock / 2 / initStruct->Baudrate / (1 + (initStruct->CAN_BS1 + 1) + (initStruct->CAN_BS2 + 1)) - 1) << CAN_BT0_BRP_Pos);
CANx->RXERR = 0; //只能在复位模式下清除
CANx->TXERR = 0;
CANx->IE = (initStruct->RXNotEmptyIEn << CAN_IE_RXDA_Pos) |
(initStruct->RXOverflowIEn << CAN_IE_RXOV_Pos) |
(initStruct->ArbitrLostIEn << CAN_IE_ARBLOST_Pos) |
(initStruct->ErrPassiveIEn << CAN_IE_ERRPASS_Pos);
switch ((uint32_t)CANx)
{
case ((uint32_t)CAN):
if (initStruct->RXNotEmptyIEn | initStruct->RXOverflowIEn | initStruct->ArbitrLostIEn | initStruct->ErrPassiveIEn)
{
NVIC_EnableIRQ(CAN_IRQn);
}
else
{
NVIC_DisableIRQ(CAN_IRQn);
}
break;
}
}
/******************************************************************************************************************************************
* : CAN_Open()
* : CAN接口打开
* : CAN_TypeDef * CANx CAN接口CAN
* :
* :
******************************************************************************************************************************************/
void CAN_Open(CAN_TypeDef *CANx)
{
CANx->CR &= ~(0x01 << CAN_CR_RST_Pos); //退出复位模式,进入工作模式
}
/******************************************************************************************************************************************
* : CAN_Close()
* : CAN接口关闭
* : CAN_TypeDef * CANx CAN接口CAN
* :
* :
******************************************************************************************************************************************/
void CAN_Close(CAN_TypeDef *CANx)
{
CANx->CR |= (0x01 << CAN_CR_RST_Pos); //进入复位模式,不能发送和接收数据
}
/******************************************************************************************************************************************
* : CAN_Transmit()
* : CAN发送数据
* : CAN_TypeDef * CANx CAN接口CAN
* uint32_t format CAN_FRAME_STD CAN_FRAME_EXT
* uint32_t id ID
* uint8_t data[]
* uint32_t size
* uint32_t once 使NAK
* :
* :
******************************************************************************************************************************************/
void CAN_Transmit(CAN_TypeDef *CANx, uint32_t format, uint32_t id, uint8_t data[], uint32_t size, uint32_t once)
{
uint32_t i;
if (format == CAN_FRAME_STD)
{
CANx->FRAME.INFO = (0 << CAN_INFO_FF_Pos) |
(0 << CAN_INFO_RTR_Pos) |
(size << CAN_INFO_DLC_Pos);
CANx->FRAME.DATA[0] = id >> 3;
CANx->FRAME.DATA[1] = id << 5;
for (i = 0; i < size; i++)
{
CANx->FRAME.DATA[i + 2] = data[i];
}
}
else //if(format == CAN_FRAME_EXT)
{
CANx->FRAME.INFO = (1 << CAN_INFO_FF_Pos) |
(0 << CAN_INFO_RTR_Pos) |
(size << CAN_INFO_DLC_Pos);
CANx->FRAME.DATA[0] = id >> 21;
CANx->FRAME.DATA[1] = id >> 13;
CANx->FRAME.DATA[2] = id >> 5;
CANx->FRAME.DATA[3] = id << 3;
for (i = 0; i < size; i++)
{
CANx->FRAME.DATA[i + 4] = data[i];
}
}
if (CANx->CR & CAN_CR_STM_Msk)
{
CANx->CMD = (1 << CAN_CMD_SRR_Pos);
}
else
{
if (once == 0)
{
CANx->CMD = (1 << CAN_CMD_TXREQ_Pos);
}
else
{
CANx->CMD = (1 << CAN_CMD_TXREQ_Pos) | (1 << CAN_CMD_ABTTX_Pos);
}
}
}
/******************************************************************************************************************************************
* : CAN_TransmitRequest()
* : CAN发送远程请求
* : CAN_TypeDef * CANx CAN接口CAN
* uint32_t format CAN_FRAME_STD CAN_FRAME_EXT
* uint32_t id ID
* uint32_t once 使NAK
* :
* :
******************************************************************************************************************************************/
void CAN_TransmitRequest(CAN_TypeDef *CANx, uint32_t format, uint32_t id, uint32_t once)
{
if (format == CAN_FRAME_STD)
{
CANx->FRAME.INFO = (0 << CAN_INFO_FF_Pos) |
(1 << CAN_INFO_RTR_Pos) |
(0 << CAN_INFO_DLC_Pos);
CANx->FRAME.DATA[0] = id >> 3;
CANx->FRAME.DATA[1] = id << 5;
}
else //if(format == CAN_FRAME_EXT)
{
CANx->FRAME.INFO = (1 << CAN_INFO_FF_Pos) |
(1 << CAN_INFO_RTR_Pos) |
(0 << CAN_INFO_DLC_Pos);
CANx->FRAME.DATA[0] = id >> 21;
CANx->FRAME.DATA[1] = id >> 13;
CANx->FRAME.DATA[2] = id >> 5;
CANx->FRAME.DATA[3] = id << 3;
}
if (once == 0)
{
CANx->CMD = (1 << CAN_CMD_TXREQ_Pos);
}
else
{
CANx->CMD = (1 << CAN_CMD_TXREQ_Pos) | (1 << CAN_CMD_ABTTX_Pos);
}
}
/******************************************************************************************************************************************
* : CAN_Receive()
* : CAN接收数据
* : CAN_TypeDef * CANx CAN接口CAN
* CAN_RXMessage *msg
* :
* :
******************************************************************************************************************************************/
void CAN_Receive(CAN_TypeDef *CANx, CAN_RXMessage *msg)
{
uint32_t i;
msg->format = (CANx->FRAME.INFO & CAN_INFO_FF_Msk) >> CAN_INFO_FF_Pos;
msg->remote = (CANx->FRAME.INFO & CAN_INFO_RTR_Msk) >> CAN_INFO_RTR_Pos;
msg->size = (CANx->FRAME.INFO & CAN_INFO_DLC_Msk) >> CAN_INFO_DLC_Pos;
if (msg->format == CAN_FRAME_STD)
{
msg->id = (CANx->FRAME.DATA[0] << 3) | (CANx->FRAME.DATA[1] >> 5);
for (i = 0; i < msg->size; i++)
{
msg->data[i] = CANx->FRAME.DATA[i + 2];
}
}
else //if(msg->format == CAN_FRAME_EXT)
{
msg->id = (CANx->FRAME.DATA[0] << 21) | (CANx->FRAME.DATA[1] << 13) | (CANx->FRAME.DATA[2] << 5) | (CANx->FRAME.DATA[3] >> 3);
for (i = 0; i < msg->size; i++)
{
msg->data[i] = CANx->FRAME.DATA[i + 4];
}
}
CANx->CMD = (1 << CAN_CMD_RRB_Pos);
}
/******************************************************************************************************************************************
* : CAN_TXComplete()
* :
* : CAN_TypeDef * CANx CAN接口CAN
* : uint32_t 1 0
* : Abort也会触发发送完成
******************************************************************************************************************************************/
uint32_t CAN_TXComplete(CAN_TypeDef *CANx)
{
return (CANx->SR & CAN_SR_TXBR_Msk) ? 1 : 0;
}
/******************************************************************************************************************************************
* : CAN_TXSuccess()
* :
* : CAN_TypeDef * CANx CAN接口CAN
* : uint32_t 1 0
* :
******************************************************************************************************************************************/
uint32_t CAN_TXSuccess(CAN_TypeDef *CANx)
{
return (CANx->SR & CAN_SR_TXOK_Msk) ? 1 : 0;
}
/******************************************************************************************************************************************
* : CAN_AbortTransmit()
* :
* : CAN_TypeDef * CANx CAN接口CAN
* :
* :
******************************************************************************************************************************************/
void CAN_AbortTransmit(CAN_TypeDef *CANx)
{
CANx->CMD = (1 << CAN_CMD_ABTTX_Pos);
}
/******************************************************************************************************************************************
* : CAN_TXBufferReady()
* : TX Buffer是否准备好可以写入消息
* : CAN_TypeDef * CANx CAN接口CAN
* : uint32_t 1 0
* :
******************************************************************************************************************************************/
uint32_t CAN_TXBufferReady(CAN_TypeDef *CANx)
{
return (CANx->SR & CAN_SR_TXBR_Msk) ? 1 : 0;
}
/******************************************************************************************************************************************
* : CAN_RXDataAvailable()
* : RX FIFO中是否有数据可读出
* : CAN_TypeDef * CANx CAN接口CAN
* : uint32_t 1 0
* :
******************************************************************************************************************************************/
uint32_t CAN_RXDataAvailable(CAN_TypeDef *CANx)
{
return (CANx->SR & CAN_SR_RXDA_Msk) ? 1 : 0;
}
/******************************************************************************************************************************************
* : CAN_SetBaudrate()
* :
* : CAN_TypeDef * CANx CAN接口CAN
* uint32_t baudrate
* uint32_t CAN_BS1 CAN_BS1_1tqCAN_BS1_2tq... ... CAN_BS1_16tq
* uint32_t CAN_BS2 CAN_BS2_1tqCAN_BS2_2tq... ... CAN_BS2_8tq
* uint32_t CAN_SJW CAN_SJW_1tqCAN_SJW_2tqCAN_SJW_3tqCAN_SJW_4tq
* :
* : CAN_Close()CAN模块
******************************************************************************************************************************************/
void CAN_SetBaudrate(CAN_TypeDef *CANx, uint32_t baudrate, uint32_t CAN_BS1, uint32_t CAN_BS2, uint32_t CAN_SJW)
{
CANx->BT1 = (0 << CAN_BT1_SAM_Pos) |
(CAN_BS1 << CAN_BT1_TSEG1_Pos) |
(CAN_BS2 << CAN_BT1_TSEG2_Pos);
CANx->BT0 = (CAN_SJW << CAN_BT0_SJW_Pos) |
((SystemCoreClock / 2 / baudrate / (1 + (CAN_BS1 + 1) + (CAN_BS2 + 1)) - 1) << CAN_BT0_BRP_Pos);
}
/******************************************************************************************************************************************
* : CAN_SetFilter32b()
* : 132
* : CAN_TypeDef * CANx CAN接口CAN
* uint32_t check mask一起决定了接收到的Message是否是自己需要的check & (~mask) == ID & (~mask)Message通过过滤
* uint32_t mask
* :
* : CAN_Close()CAN模块
******************************************************************************************************************************************/
void CAN_SetFilter32b(CAN_TypeDef *CANx, uint32_t check, uint32_t mask)
{
CANx->CR &= ~CAN_CR_AFM_Msk;
CANx->CR |= (CAN_FILTER_32b << CAN_CR_AFM_Pos);
CANx->FILTER.AMR[3] = mask & 0xFF;
CANx->FILTER.AMR[2] = (mask >> 8) & 0xFF;
CANx->FILTER.AMR[1] = (mask >> 16) & 0xFF;
CANx->FILTER.AMR[0] = (mask >> 24) & 0xFF;
CANx->FILTER.ACR[3] = check & 0xFF;
CANx->FILTER.ACR[2] = (check >> 8) & 0xFF;
CANx->FILTER.ACR[1] = (check >> 16) & 0xFF;
CANx->FILTER.ACR[0] = (check >> 24) & 0xFF;
}
/******************************************************************************************************************************************
* : CAN_SetFilter16b()
* : 216
* : CAN_TypeDef * CANx CAN接口CAN
* uint16_t check1 mask一起决定了接收到的Message是否是自己需要的check & (~mask) == ID & (~mask)Message通过过滤
* uint16_t mask1
* uint16_t check2
* uint16_t mask2
* :
* : CAN_Close()CAN模块
******************************************************************************************************************************************/
void CAN_SetFilter16b(CAN_TypeDef *CANx, uint16_t check1, uint16_t mask1, uint16_t check2, uint16_t mask2)
{
CANx->CR &= ~CAN_CR_AFM_Msk;
CANx->CR |= (CAN_FILTER_16b << CAN_CR_AFM_Pos);
CANx->FILTER.AMR[3] = mask1 & 0xFF;
CANx->FILTER.AMR[2] = (mask1 >> 8) & 0xFF;
CANx->FILTER.AMR[1] = mask2 & 0xFF;
CANx->FILTER.AMR[0] = (mask2 >> 8) & 0xFF;
CANx->FILTER.ACR[3] = check1 & 0xFF;
CANx->FILTER.ACR[2] = (check1 >> 8) & 0xFF;
CANx->FILTER.ACR[1] = check2 & 0xFF;
CANx->FILTER.ACR[0] = (check2 >> 8) & 0xFF;
}
/******************************************************************************************************************************************
* : CAN_INTRXNotEmptyEn()
* : RX FIFO中有数据时使
* : CAN_TypeDef * CANx CAN接口CAN
* :
* :
******************************************************************************************************************************************/
void CAN_INTRXNotEmptyEn(CAN_TypeDef *CANx)
{
CANx->IE |= (1 << CAN_IE_RXDA_Pos);
}
/******************************************************************************************************************************************
* : CAN_INTRXNotEmptyDis()
* : RX FIFO中有数据时
* : CAN_TypeDef * CANx CAN接口CAN
* :
* :
******************************************************************************************************************************************/
void CAN_INTRXNotEmptyDis(CAN_TypeDef *CANx)
{
CANx->IE &= ~(1 << CAN_IE_RXDA_Pos);
}
/******************************************************************************************************************************************
* : CAN_INTTXBufEmptyEn()
* : TX Buffer空时触发中断使能
* : CAN_TypeDef * CANx CAN接口CAN
* :
* :
******************************************************************************************************************************************/
void CAN_INTTXBufEmptyEn(CAN_TypeDef *CANx)
{
CANx->IE |= (1 << CAN_IE_TXBR_Pos);
}
/******************************************************************************************************************************************
* : CAN_INTTXBufEmptyDis()
* : TX Buffer空时触发中断禁止
* : CAN_TypeDef * CANx CAN接口CAN
* :
* :
******************************************************************************************************************************************/
void CAN_INTTXBufEmptyDis(CAN_TypeDef *CANx)
{
CANx->IE &= ~(1 << CAN_IE_TXBR_Pos);
}
/******************************************************************************************************************************************
* : CAN_INTErrWarningEn()
* : TXERR/RXERR计数值达到Error Warning Limit时触发中断使能
* : CAN_TypeDef * CANx CAN接口CAN
* :
* :
******************************************************************************************************************************************/
void CAN_INTErrWarningEn(CAN_TypeDef *CANx)
{
CANx->IE |= (1 << CAN_IE_ERRWARN_Pos);
}
/******************************************************************************************************************************************
* : CAN_INTErrWarningDis()
* : TXERR/RXERR计数值达到Error Warning Limit时触发中断禁止
* : CAN_TypeDef * CANx CAN接口CAN
* :
* :
******************************************************************************************************************************************/
void CAN_INTErrWarningDis(CAN_TypeDef *CANx)
{
CANx->IE &= ~(1 << CAN_IE_ERRWARN_Pos);
}
/******************************************************************************************************************************************
* : CAN_INTRXOverflowEn()
* : RX FIFO 使
* : CAN_TypeDef * CANx CAN接口CAN
* :
* :
******************************************************************************************************************************************/
void CAN_INTRXOverflowEn(CAN_TypeDef *CANx)
{
CANx->IE |= (1 << CAN_IE_RXOV_Pos);
}
/******************************************************************************************************************************************
* : CAN_INTRXOverflowDis()
* : RX FIFO
* : CAN_TypeDef * CANx CAN接口CAN
* :
* :
******************************************************************************************************************************************/
void CAN_INTRXOverflowDis(CAN_TypeDef *CANx)
{
CANx->IE &= ~(1 << CAN_IE_RXOV_Pos);
}
/******************************************************************************************************************************************
* : CAN_INTRXOverflowClear()
* : RX FIFO
* : CAN_TypeDef * CANx CAN接口CAN
* :
* :
******************************************************************************************************************************************/
void CAN_INTRXOverflowClear(CAN_TypeDef *CANx)
{
CANx->CMD = (1 << CAN_CMD_CLROV_Pos);
}
/******************************************************************************************************************************************
* : CAN_INTWakeupEn()
* : 使
* : CAN_TypeDef * CANx CAN接口CAN
* :
* :
******************************************************************************************************************************************/
void CAN_INTWakeupEn(CAN_TypeDef *CANx)
{
CANx->IE |= (1 << CAN_IE_WKUP_Pos);
}
/******************************************************************************************************************************************
* : CAN_INTWakeupDis()
* :
* : CAN_TypeDef * CANx CAN接口CAN
* :
* :
******************************************************************************************************************************************/
void CAN_INTWakeupDis(CAN_TypeDef *CANx)
{
CANx->IE &= ~(1 << CAN_IE_WKUP_Pos);
}
/******************************************************************************************************************************************
* : CAN_INTErrPassiveEn()
* : TXERR/RXERR计数值达到127时中断使能
* : CAN_TypeDef * CANx CAN接口CAN
* :
* :
******************************************************************************************************************************************/
void CAN_INTErrPassiveEn(CAN_TypeDef *CANx)
{
CANx->IE |= (1 << CAN_IE_ERRPASS_Pos);
}
/******************************************************************************************************************************************
* : CAN_INTErrPassiveDis()
* : TXERR/RXERR计数值达到127时中断禁止
* : CAN_TypeDef * CANx CAN接口CAN
* :
* :
******************************************************************************************************************************************/
void CAN_INTErrPassiveDis(CAN_TypeDef *CANx)
{
CANx->IE &= ~(1 << CAN_IE_ERRPASS_Pos);
}
/******************************************************************************************************************************************
* : CAN_INTArbitrLostEn()
* : 使
* : CAN_TypeDef * CANx CAN接口CAN
* :
* :
******************************************************************************************************************************************/
void CAN_INTArbitrLostEn(CAN_TypeDef *CANx)
{
CANx->IE |= (1 << CAN_IE_ARBLOST_Pos);
}
/******************************************************************************************************************************************
* : CAN_INTArbitrLostDis()
* :
* : CAN_TypeDef * CANx CAN接口CAN
* :
* :
******************************************************************************************************************************************/
void CAN_INTArbitrLostDis(CAN_TypeDef *CANx)
{
CANx->IE &= ~(1 << CAN_IE_ARBLOST_Pos);
}
/******************************************************************************************************************************************
* : CAN_INTBusErrorEn()
* : 线使
* : CAN_TypeDef * CANx CAN接口CAN
* :
* :
******************************************************************************************************************************************/
void CAN_INTBusErrorEn(CAN_TypeDef *CANx)
{
CANx->IE |= (1 << CAN_IE_BUSERR_Pos);
}
/******************************************************************************************************************************************
* : CAN_INTBusErrorDis()
* : 线
* : CAN_TypeDef * CANx CAN接口CAN
* :
* :
******************************************************************************************************************************************/
void CAN_INTBusErrorDis(CAN_TypeDef *CANx)
{
CANx->IE &= ~(1 << CAN_IE_BUSERR_Pos);
}
/******************************************************************************************************************************************
* : CAN_INTStat()
* :
* : CAN_TypeDef * CANx CAN接口CAN
* : uint32_t
* : CANx->IF读取清零ISR中只能读取一次
******************************************************************************************************************************************/
uint32_t CAN_INTStat(CAN_TypeDef *CANx)
{
return CANx->IF;
}

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#ifndef __SWM320_CAN_H__
#define __SWM320_CAN_H__
#define CAN_FRAME_STD 0
#define CAN_FRAME_EXT 1
typedef struct
{
uint8_t Mode; //CAN_MODE_NORMAL、CAN_MODE_LISTEN、CAN_MODE_SELFTEST
uint8_t CAN_BS1; //CAN_BS1_1tq、CAN_BS1_2tq、... ... 、CAN_BS1_16tq
uint8_t CAN_BS2; //CAN_BS2_1tq、CAN_BS2_2tq、... ... 、CAN_BS2_8tq
uint8_t CAN_SJW; //CAN_SJW_1tq、CAN_SJW_2tq、CAN_SJW_3tq、CAN_SJW_4tq
uint32_t Baudrate; //波特率即位传输速率取值1--1000000
uint8_t FilterMode; //CAN_FILTER_16b、CAN_FILTER_32b
union
{
uint32_t FilterMask32b; //FilterCheck & (~FilterMask) == ID & (~FilterMask)的Message通过过滤
struct
{ // 0 must match 1 don't care
uint16_t FilterMask16b1;
uint16_t FilterMask16b2;
};
};
union
{
uint32_t FilterCheck32b;
struct
{
uint16_t FilterCheck16b1;
uint16_t FilterCheck16b2;
};
};
uint8_t RXNotEmptyIEn; //接收FIFO非空有数据可读
uint8_t RXOverflowIEn; //接收FIFO溢出有数据丢失
uint8_t ArbitrLostIEn; //控制器丢失仲裁变成接收方
uint8_t ErrPassiveIEn; //接收/发送错误计数值达到127
} CAN_InitStructure;
#define CAN_MODE_NORMAL 0 //常规模式
#define CAN_MODE_LISTEN 1 //监听模式
#define CAN_MODE_SELFTEST 2 //自测模式
#define CAN_BS1_1tq 0
#define CAN_BS1_2tq 1
#define CAN_BS1_3tq 2
#define CAN_BS1_4tq 3
#define CAN_BS1_5tq 4
#define CAN_BS1_6tq 5
#define CAN_BS1_7tq 6
#define CAN_BS1_8tq 7
#define CAN_BS1_9tq 8
#define CAN_BS1_10tq 9
#define CAN_BS1_11tq 10
#define CAN_BS1_12tq 11
#define CAN_BS1_13tq 12
#define CAN_BS1_14tq 13
#define CAN_BS1_15tq 14
#define CAN_BS1_16tq 15
#define CAN_BS2_1tq 0
#define CAN_BS2_2tq 1
#define CAN_BS2_3tq 2
#define CAN_BS2_4tq 3
#define CAN_BS2_5tq 4
#define CAN_BS2_6tq 5
#define CAN_BS2_7tq 6
#define CAN_BS2_8tq 7
#define CAN_SJW_1tq 0
#define CAN_SJW_2tq 1
#define CAN_SJW_3tq 2
#define CAN_SJW_4tq 3
#define CAN_FILTER_16b 0 //两个16位过滤器
#define CAN_FILTER_32b 1 //一个32位过滤器
typedef struct
{
uint32_t id; //消息ID
uint8_t format; //帧格式CAN_FRAME_STD、CAN_FRAME_EXT
uint8_t remote; //消息是否为远程帧
uint8_t size; //接收到的数据个数
uint8_t data[8]; //接收到的数据
} CAN_RXMessage;
void CAN_Init(CAN_TypeDef *CANx, CAN_InitStructure *initStruct);
void CAN_Open(CAN_TypeDef *CANx);
void CAN_Close(CAN_TypeDef *CANx);
void CAN_Transmit(CAN_TypeDef *CANx, uint32_t format, uint32_t id, uint8_t data[], uint32_t size, uint32_t once);
void CAN_TransmitRequest(CAN_TypeDef *CANx, uint32_t format, uint32_t id, uint32_t once);
void CAN_Receive(CAN_TypeDef *CANx, CAN_RXMessage *msg);
uint32_t CAN_TXComplete(CAN_TypeDef *CANx);
uint32_t CAN_TXSuccess(CAN_TypeDef *CANx);
void CAN_AbortTransmit(CAN_TypeDef *CANx);
uint32_t CAN_TXBufferReady(CAN_TypeDef *CANx);
uint32_t CAN_RXDataAvailable(CAN_TypeDef *CANx);
void CAN_SetBaudrate(CAN_TypeDef *CANx, uint32_t baudrate, uint32_t CAN_BS1, uint32_t CAN_BS2, uint32_t CAN_SJW);
void CAN_SetFilter32b(CAN_TypeDef *CANx, uint32_t check, uint32_t mask);
void CAN_SetFilter16b(CAN_TypeDef *CANx, uint16_t check1, uint16_t mask1, uint16_t check2, uint16_t mask2);
void CAN_INTRXNotEmptyEn(CAN_TypeDef *CANx);
void CAN_INTRXNotEmptyDis(CAN_TypeDef *CANx);
void CAN_INTTXBufEmptyEn(CAN_TypeDef *CANx);
void CAN_INTTXBufEmptyDis(CAN_TypeDef *CANx);
void CAN_INTErrWarningEn(CAN_TypeDef *CANx);
void CAN_INTErrWarningDis(CAN_TypeDef *CANx);
void CAN_INTRXOverflowEn(CAN_TypeDef *CANx);
void CAN_INTRXOverflowDis(CAN_TypeDef *CANx);
void CAN_INTRXOverflowClear(CAN_TypeDef *CANx);
void CAN_INTWakeupEn(CAN_TypeDef *CANx);
void CAN_INTWakeupDis(CAN_TypeDef *CANx);
void CAN_INTErrPassiveEn(CAN_TypeDef *CANx);
void CAN_INTErrPassiveDis(CAN_TypeDef *CANx);
void CAN_INTArbitrLostEn(CAN_TypeDef *CANx);
void CAN_INTArbitrLostDis(CAN_TypeDef *CANx);
void CAN_INTBusErrorEn(CAN_TypeDef *CANx);
void CAN_INTBusErrorDis(CAN_TypeDef *CANx);
uint32_t CAN_INTStat(CAN_TypeDef *CANx);
#endif //__SWM320_CAN_H__

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@ -1,50 +0,0 @@
/******************************************************************************************************************************************
* : SWM320_crc.c
* : SWM320单片机的CRC模块驱动库
* : http://www.synwit.com.cn/e/tool/gbook/?bid=1
* :
* : V1.1.0 20171025
* :
*
*
*******************************************************************************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
* -ECTION WITH THEIR PRODUCTS.
*
* COPYRIGHT 2012 Synwit Technology
*******************************************************************************************************************************************/
#include "SWM320.h"
#include "SWM320_crc.h"
/******************************************************************************************************************************************
* : CRC_Init()
* : CRC
* : CRC_TypeDef * CRCx CRC接口CRC
* uint32_t mode CRC32_IN32CRC32_IN16CRC32_IN8CRC16_IN16CRC16_IN8
* uint32_t out_not
* uint32_t out_rev
* uint32_t ini_val CRC初始值
* :
* :
******************************************************************************************************************************************/
void CRC_Init(CRC_TypeDef *CRCx, uint32_t mode, uint32_t out_not, uint32_t out_rev, uint32_t ini_val)
{
switch ((uint32_t)CRCx)
{
case ((uint32_t)CRC):
SYS->CLKEN |= (0x01 << SYS_CLKEN_CRC_Pos);
break;
}
CRCx->CR = (1 << CRC_CR_EN_Pos) |
(mode << CRC_CR_CRC16_Pos) |
(out_not << CRC_CR_ONOT_Pos) |
(out_rev << CRC_CR_OREV_Pos);
CRCx->INIVAL = ini_val;
}

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@ -1,36 +0,0 @@
#ifndef __SWM320_CRC_H__
#define __SWM320_CRC_H__
#define CRC32_IN32 0 //CRC32算法输入数据32位
#define CRC32_IN16 2 //CRC32算法输入数据16位
#define CRC32_IN8 4 //CRC32算法输入数据 8位
#define CRC16_IN16 3 //CRC16算法输入数据16位
#define CRC16_IN8 5 //CRC16算法输入数据 8位
void CRC_Init(CRC_TypeDef *CRCx, uint32_t mode, uint32_t out_not, uint32_t out_rev, uint32_t ini_val);
/******************************************************************************************************************************************
* : CRC_Write()
* : CRC写入数据
* : uint32_t data
* :
* :
******************************************************************************************************************************************/
static __INLINE void CRC_Write(uint32_t data)
{
CRC->DATAIN = data;
}
/******************************************************************************************************************************************
* : CRC_Result()
* : CRC计算结果
* :
* : uint32_t CRC
* :
******************************************************************************************************************************************/
static __INLINE uint32_t CRC_Result(void)
{
return CRC->RESULT;
}
#endif //__SWM320_CRC_H__

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@ -1,140 +0,0 @@
/******************************************************************************************************************************************
* : SWM320_dma.c
* : SWM320单片机的DMA功能驱动库
* : http://www.synwit.com.cn/e/tool/gbook/?bid=1
* :
* : V1.1.0 20171025
* :
*
*
*******************************************************************************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
* -ECTION WITH THEIR PRODUCTS.
*
* COPYRIGHT 2012 Synwit Technology
*******************************************************************************************************************************************/
#include "SWM320.h"
#include "SWM320_dma.h"
/******************************************************************************************************************************************
* : DMA_CHM_Config()
* : DMA通道配置Flash和RAM间
* : uint32_t chn DMA_CH0DMA_CH1DMA_CH2
* uint32_t src_addr 200
* uint32_t src_addr_incr 0 1
* uint32_t dst_addr 200
* uint32_t dst_addr_incr 0 1
* uint32_t num_word 1024
* uint32_t int_en 使1 0
* :
* :
******************************************************************************************************************************************/
void DMA_CHM_Config(uint32_t chn, uint32_t src_addr, uint32_t src_addr_incr, uint32_t dst_addr, uint32_t dst_addr_incr, uint32_t num_word, uint32_t int_en)
{
DMA->EN = 1; //每个通道都有自己独立的开关控制,所以总开关可以是一直开启的
DMA_CH_Close(chn); //配置前先关闭该通道
DMA->CH[chn].SRC = src_addr;
DMA->CH[chn].DST = dst_addr;
DMA->CH[chn].CR = ((num_word * 4 - 1) << DMA_CR_LEN_Pos) |
(0 << DMA_CR_AUTORE_Pos);
DMA->CH[chn].AM = (src_addr_incr << DMA_AM_SRCAM_Pos) |
(dst_addr_incr << DMA_AM_DSTAM_Pos) |
(0 << DMA_AM_BURST_Pos);
DMA->IF = (1 << chn); //清除中断标志
DMA->IE |= (1 << chn);
if (int_en)
DMA->IM &= ~(1 << chn);
else
DMA->IM |= (1 << chn);
if (int_en)
{
NVIC_EnableIRQ(DMA_IRQn);
}
else
{
//不能调用NVIC_DisalbeIRQ(DMA_IRQn)因为其他通道可能使用DMA中断
}
}
/******************************************************************************************************************************************
* : DMA_CH_Open()
* : DMA通道打开
* : uint32_t chn DMA_CH0DMA_CH1DMA_CH2
* :
* :
******************************************************************************************************************************************/
void DMA_CH_Open(uint32_t chn)
{
DMA->CH[chn].CR |= (1 << DMA_CR_TXEN_Pos);
}
/******************************************************************************************************************************************
* : DMA_CH_Close()
* : DMA通道关闭
* : uint32_t chn DMA_CH0DMA_CH1DMA_CH2
* :
* :
******************************************************************************************************************************************/
void DMA_CH_Close(uint32_t chn)
{
DMA->CH[chn].CR &= ~(1 << DMA_CR_TXEN_Pos);
}
/******************************************************************************************************************************************
* : DMA_CH_INTEn()
* : DMA中断使能
* : uint32_t chn DMA_CH0DMA_CH1DMA_CH2
* :
* :
******************************************************************************************************************************************/
void DMA_CH_INTEn(uint32_t chn)
{
DMA->IM &= ~(1 << chn);
}
/******************************************************************************************************************************************
* : DMA_CH_INTDis()
* : DMA中断禁止
* : uint32_t chn DMA_CH0DMA_CH1DMA_CH2
* :
* :
******************************************************************************************************************************************/
void DMA_CH_INTDis(uint32_t chn)
{
DMA->IM |= (1 << chn);
}
/******************************************************************************************************************************************
* : DMA_CH_INTClr()
* : DMA中断标志清除
* : uint32_t chn DMA_CH0DMA_CH1DMA_CH2
* :
* :
******************************************************************************************************************************************/
void DMA_CH_INTClr(uint32_t chn)
{
DMA->IF = (1 << chn);
}
/******************************************************************************************************************************************
* : DMA_CH_INTStat()
* : DMA中断状态查询
* : uint32_t chn DMA_CH0DMA_CH1DMA_CH2
* : uint32_t 1 0
* :
******************************************************************************************************************************************/
uint32_t DMA_CH_INTStat(uint32_t chn)
{
return (DMA->IF & (1 << chn)) ? 1 : 0;
}

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#ifndef __SWM320_DMA_H__
#define __SWM320_DMA_H__
#define DMA_CH0 0
#define DMA_CH1 1
#define DMA_CH2 2
void DMA_CHM_Config(uint32_t chn, uint32_t src_addr, uint32_t src_addr_incr, uint32_t dst_addr, uint32_t dst_addr_incr, uint32_t num_word, uint32_t int_en); //DMA通道配置用于存储器间如Flash和RAM间搬运数据
void DMA_CH_Open(uint32_t chn); //DMA通道打开
void DMA_CH_Close(uint32_t chn); //DMA通道关闭
void DMA_CH_INTEn(uint32_t chn); //DMA中断使能数据搬运完成后触发中断
void DMA_CH_INTDis(uint32_t chn); //DMA中断禁止数据搬运完成后不触发中断
void DMA_CH_INTClr(uint32_t chn); //DMA中断标志清除
uint32_t DMA_CH_INTStat(uint32_t chn); //DMA中断状态查询1 数据搬运完成 0 数据搬运未完成
#endif //__SWM320_DMA_H__

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/******************************************************************************************************************************************
* : SWM320_exti.c
* : SWM320单片机的外部中断功能驱动库
* : http://www.synwit.com.cn/e/tool/gbook/?bid=1
* :
* : V1.1.0 20171025
* :
*
*******************************************************************************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
* -ECTION WITH THEIR PRODUCTS.
*
* COPYRIGHT 2012 Synwit Technology
*******************************************************************************************************************************************/
#include "SWM320.h"
#include "SWM320_exti.h"
/******************************************************************************************************************************************
* : EXTI_Init()
* :
* : GPIO_TypeDef * GPIOx GPIO端口GPIOAGPIOBGPIOCGPIOMGPIONGPIOP
* uint32_t n GPIO引脚PIN0PIN1PIN2... ... PIN22PIN23
* uint32_t mode EXTI_FALL_EDGEEXTI_RISE_EDGEEXTI_BOTH_EDGEEXTI_LOW_LEVELEXTI_HIGH_LEVEL
* :
* : GPIOAGPIOBGPIOCGPIOM的PIN0--7NVIC中的引脚中断GPIOA0_IRQnNVIC的组中断GPIOA_IRQn
* NVIC_EnableIRQ()使NVIC中断NVIC_EnableIRQ(GPIOA0_IRQn)NVIC_EnableIRQ(GPIOA_IRQn)
******************************************************************************************************************************************/
void EXTI_Init(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t mode)
{
EXTI_Close(GPIOx, n); //配置关键寄存器前先关闭
if (mode & 0x10)
{
GPIOx->INTLVLTRG |= (0x01 << n); //电平触发
if (mode & 0x01)
GPIOx->INTRISEEN |= (0x01 << n); //高电平触发
else
GPIOx->INTRISEEN &= ~(0x01 << n); //低电平触发
}
else
{
GPIOx->INTLVLTRG &= ~(0x01 << n); //边沿触发
if (mode & 0x02)
{
GPIOx->INTBE |= (0x01 << n); //双边沿触发
}
else
{
GPIOx->INTBE &= ~(0x01 << n); //单边沿触发
if (mode & 0x01)
GPIOx->INTRISEEN |= (0x01 << n); //上升沿触发
else
GPIOx->INTRISEEN &= ~(0x01 << n); //下降沿触发
}
}
GPIOx->INTCLR = (1 << n); //清除掉因为模式配置可能产生的中断
}
/******************************************************************************************************************************************
* : EXTI_Open()
* : 使
* : GPIO_TypeDef * GPIOx GPIO端口GPIOAGPIOBGPIOCGPIOMGPIONGPIOP
* uint32_t n GPIO引脚PIN0PIN1PIN2... ... PIN22PIN23
* :
* :
******************************************************************************************************************************************/
void EXTI_Open(GPIO_TypeDef *GPIOx, uint32_t n)
{
GPIOx->INTEN |= (0x01 << n);
}
/******************************************************************************************************************************************
* : EXTI_Close()
* :
* : GPIO_TypeDef * GPIOx GPIO端口GPIOAGPIOBGPIOCGPIOMGPIONGPIOP
* uint32_t n GPIO引脚PIN0PIN1PIN2... ... PIN22PIN23
* :
* :
******************************************************************************************************************************************/
void EXTI_Close(GPIO_TypeDef *GPIOx, uint32_t n)
{
GPIOx->INTEN &= ~(0x01 << n);
}
/******************************************************************************************************************************************
* : EXTI_State()
* :
* : GPIO_TypeDef * GPIOx GPIO端口GPIOAGPIOBGPIOCGPIOMGPIONGPIOP
* uint32_t n GPIO引脚PIN0PIN1PIN2... ... PIN22PIN23
* : uint32_t 1 0
* :
******************************************************************************************************************************************/
uint32_t EXTI_State(GPIO_TypeDef *GPIOx, uint32_t n)
{
return (GPIOx->INTSTAT >> n) & 0x01;
}
/******************************************************************************************************************************************
* : EXTI_RawState()
* : //
* : GPIO_TypeDef * GPIOx GPIO端口GPIOAGPIOBGPIOCGPIOMGPIONGPIOP
* uint32_t n GPIO引脚PIN0PIN1PIN2... ... PIN22PIN23
* : uint32_t 1 / 0 /
* :
******************************************************************************************************************************************/
uint32_t EXTI_RawState(GPIO_TypeDef *GPIOx, uint32_t n)
{
return (GPIOx->INTRAWSTAT >> n) & 0x01;
}
/******************************************************************************************************************************************
* : EXTI_Clear()
* :
* : GPIO_TypeDef * GPIOx GPIO端口GPIOAGPIOBGPIOCGPIOMGPIONGPIOP
* uint32_t n GPIO引脚PIN0PIN1PIN2... ... PIN22PIN23
* :
* : 沿
******************************************************************************************************************************************/
void EXTI_Clear(GPIO_TypeDef *GPIOx, uint32_t n)
{
GPIOx->INTCLR = (0x01 << n);
}

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#ifndef __SWM320_EXTI_H__
#define __SWM320_EXTI_H__
void EXTI_Init(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t mode); //指定引脚外部中断初始化
void EXTI_Open(GPIO_TypeDef *GPIOx, uint32_t n); //指定引脚外部中断打开(即使能)
void EXTI_Close(GPIO_TypeDef *GPIOx, uint32_t n); //指定引脚外部中断关闭(即禁能)
uint32_t EXTI_State(GPIO_TypeDef *GPIOx, uint32_t n); //指定引脚是否触发了中断
uint32_t EXTI_RawState(GPIO_TypeDef *GPIOx, uint32_t n); //指定引脚是否满足过/了中断触发条件,当此中断关闭时可通过调用此函数以查询的方式检测引脚上是否满足过/了中断触发条件
void EXTI_Clear(GPIO_TypeDef *GPIOx, uint32_t n); //指定引脚外部中断清除(即清除中断标志,以免再次进入此中断)
#define EXTI_FALL_EDGE 0x00 //下降沿触发中断
#define EXTI_RISE_EDGE 0x01 //上升沿触发中断
#define EXTI_BOTH_EDGE 0x02 //双边沿触发中断
#define EXTI_LOW_LEVEL 0x10 //低电平触发中断
#define EXTI_HIGH_LEVEL 0x11 //高电平触发中断
#endif //__SWM320_EXTI_H__

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/******************************************************************************************************************************************
* : SWM320_flash.c
* : 使IAP功能将片上Flash模拟成EEPROM来保存数据
* : http://www.synwit.com.cn/e/tool/gbook/?bid=1
* :
* : V1.1.0 20171025
* :
*******************************************************************************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
* -ECTION WITH THEIR PRODUCTS.
*
* COPYRIGHT 2012 Synwit Technology
*******************************************************************************************************************************************/
#include "SWM320.h"
#include "SWM320_flash.h"
IAP_Cache_Reset_t IAP_Cache_Reset = (IAP_Cache_Reset_t)0x11000601;
IAP_Flash_Param_t IAP_Flash_Param = (IAP_Flash_Param_t)0x11000681;
IAP_Flash_Erase_t IAP_Flash_Erase = (IAP_Flash_Erase_t)0x11000781;
IAP_Flash_Write_t IAP_Flash_Write = (IAP_Flash_Write_t)0x11000801;
/******************************************************************************************************************************************
* : FLASH_Erase()
* : Flash擦除
* : uint32_t addr 4K Byte
* :
* :
******************************************************************************************************************************************/
void FLASH_Erase(uint32_t addr)
{
__disable_irq();
IAP_Flash_Erase(addr / 0x1000);
IAP_Cache_Reset();
__enable_irq();
}
/******************************************************************************************************************************************
* : FLASH_Write()
* : Flash写入
* : uint32_t addr
* uint32_t buff[]
* uint32_t count 44
* :
* : 44
******************************************************************************************************************************************/
void FLASH_Write(uint32_t addr, uint32_t buff[], uint32_t count)
{
__disable_irq();
IAP_Flash_Write(addr, (uint32_t)buff, count / 4);
IAP_Cache_Reset();
__enable_irq();
}
/******************************************************************************************************************************************
* : Flash_Param_at_xMHz()
* : Flash参数设置成xMHz主频下运行时所需的参数
* : uint32_t x
* :
* :
******************************************************************************************************************************************/
void Flash_Param_at_xMHz(uint32_t x)
{
__disable_irq();
switch (x)
{
case 30:
IAP_Flash_Param(0x489, 0xabf41f25);
break;
case 40:
IAP_Flash_Param(0x489, 0xabf42929);
break;
case 80:
IAP_Flash_Param(0x489, 0xabf8524d);
break;
case 120:
default:
IAP_Flash_Param(0x48a, 0xabfc7a6e);
break;
}
__enable_irq();
}

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#ifndef __SWM320_FLASH_H__
#define __SWM320_FLASH_H__
void FLASH_Erase(uint32_t addr);
void FLASH_Write(uint32_t addr, uint32_t buff[], uint32_t count);
void Flash_Param_at_xMHz(uint32_t x);
typedef void (*IAP_Cache_Reset_t)(void);
typedef void (*IAP_Flash_Param_t)(uint32_t cfg0, uint32_t cfg1);
typedef void (*IAP_Flash_Erase_t)(uint32_t sector);
typedef void (*IAP_Flash_Write_t)(uint32_t flash_addr, uint32_t ram_addr, uint32_t count);
extern IAP_Cache_Reset_t IAP_Cache_Reset;
extern IAP_Flash_Param_t IAP_Flash_Param;
extern IAP_Flash_Erase_t IAP_Flash_Erase;
extern IAP_Flash_Write_t IAP_Flash_Write;
#endif //__SWM320_FLASH_H__

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/******************************************************************************************************************************************
* : SWM320_gpio.c
* : SWM320单片机的通用输入输出功能驱动库
* : http://www.synwit.com.cn/e/tool/gbook/?bid=1
* :
* : V1.1.0 20171025
* :
*
*
*******************************************************************************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
* -ECTION WITH THEIR PRODUCTS.
*
* COPYRIGHT 2012 Synwit Technology
*******************************************************************************************************************************************/
#include "SWM320.h"
#include "SWM320_gpio.h"
/******************************************************************************************************************************************
* : GPIO_Init()
* :
* : GPIO_TypeDef * GPIOx GPIO端口GPIOAGPIOBGPIOCGPIOMGPIONGPIOP
* uint32_t n GPIO引脚PIN0PIN1PIN2... ... PIN22PIN23
* uint32_t dir 0 1
* uint32_t pull_up 0 1
* uint32_t pull_down 0 1
* :
* : GPIOAGPIOCGPIOMGPIOP只有上拉GPIOBGPION只有下拉PN0PN1PN2三个引脚有上拉没下拉
******************************************************************************************************************************************/
void GPIO_Init(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t dir, uint32_t pull_up, uint32_t pull_down)
{
switch ((uint32_t)GPIOx)
{
case ((uint32_t)GPIOA):
SYS->CLKEN |= (0x01 << SYS_CLKEN_GPIOA_Pos);
PORT_Init(PORTA, n, 0, 1); //PORTA.PINn引脚配置为GPIO功能数字输入开启
if (dir == 1)
{
GPIOA->DIR |= (0x01 << n);
}
else
{
GPIOA->DIR &= ~(0x01 << n);
}
if (pull_up == 1)
PORT->PORTA_PULLU |= (0x01 << n);
else
PORT->PORTA_PULLU &= ~(0x01 << n);
break;
case ((uint32_t)GPIOB):
SYS->CLKEN |= (0x01 << SYS_CLKEN_GPIOB_Pos);
PORT_Init(PORTB, n, 0, 1); //PORTB.PINn引脚配置为GPIO功能数字输入开启
if (dir == 1)
{
GPIOB->DIR |= (0x01 << n);
}
else
{
GPIOB->DIR &= ~(0x01 << n);
}
if (pull_down == 1)
PORT->PORTB_PULLD |= (0x01 << n);
else
PORT->PORTB_PULLD &= ~(0x01 << n);
break;
case ((uint32_t)GPIOC):
SYS->CLKEN |= (0x01 << SYS_CLKEN_GPIOC_Pos);
PORT_Init(PORTC, n, 0, 1); //PORTC.PINn引脚配置为GPIO功能数字输入开启
if (dir == 1)
{
GPIOC->DIR |= (0x01 << n);
}
else
{
GPIOC->DIR &= ~(0x01 << n);
}
if (pull_up == 1)
PORT->PORTC_PULLU |= (0x01 << n);
else
PORT->PORTC_PULLU &= ~(0x01 << n);
break;
case ((uint32_t)GPIOM):
SYS->CLKEN |= (0x01 << SYS_CLKEN_GPIOM_Pos);
PORT_Init(PORTM, n, 0, 1); //PORTM.PINn引脚配置为GPIO功能数字输入开启
if (dir == 1)
{
GPIOM->DIR |= (0x01 << n);
}
else
{
GPIOM->DIR &= ~(0x01 << n);
}
if (pull_up == 1)
PORT->PORTM_PULLU |= (0x01 << n);
else
PORT->PORTM_PULLU &= ~(0x01 << n);
break;
case ((uint32_t)GPION):
SYS->CLKEN |= (0x01 << SYS_CLKEN_GPION_Pos);
PORT_Init(PORTN, n, 0, 1); //PORTN.PINn引脚配置为GPIO功能数字输入开启
if (dir == 1)
{
GPION->DIR |= (0x01 << n);
}
else
{
GPION->DIR &= ~(0x01 << n);
}
if (pull_down == 1)
PORT->PORTN_PULLD |= (0x01 << n);
else
PORT->PORTN_PULLD &= ~(0x01 << n);
break;
case ((uint32_t)GPIOP):
SYS->CLKEN |= (0x01 << SYS_CLKEN_GPIOP_Pos);
PORT_Init(PORTP, n, 0, 1); //PORTP.PINn引脚配置为GPIO功能数字输入开启
if (dir == 1)
{
GPIOP->DIR |= (0x01 << n);
}
else
{
GPIOP->DIR &= ~(0x01 << n);
}
if (pull_up == 1)
PORT->PORTP_PULLU |= (0x01 << n);
else
PORT->PORTP_PULLU &= ~(0x01 << n);
break;
}
}
/******************************************************************************************************************************************
* : GPIO_SetBit()
* :
* : GPIO_TypeDef * GPIOx GPIO端口GPIOAGPIOBGPIOCGPIOMGPIONGPIOP
* uint32_t n GPIO引脚PIN0PIN1PIN2... ... PIN22PIN23
* :
* :
******************************************************************************************************************************************/
void GPIO_SetBit(GPIO_TypeDef *GPIOx, uint32_t n)
{
GPIOx->DATA |= (0x01 << n);
}
/******************************************************************************************************************************************
* : GPIO_ClrBit()
* :
* : GPIO_TypeDef * GPIOx GPIO端口GPIOAGPIOBGPIOCGPIOMGPIONGPIOP
* uint32_t n GPIO引脚PIN0PIN1PIN2... ... PIN22PIN23
* :
* :
******************************************************************************************************************************************/
void GPIO_ClrBit(GPIO_TypeDef *GPIOx, uint32_t n)
{
GPIOx->DATA &= ~(0x01 << n);
}
/******************************************************************************************************************************************
* : GPIO_InvBit()
* :
* : GPIO_TypeDef * GPIOx GPIO端口GPIOAGPIOBGPIOCGPIOMGPIONGPIOP
* uint32_t n GPIO引脚PIN0PIN1PIN2... ... PIN22PIN23
* :
* :
******************************************************************************************************************************************/
void GPIO_InvBit(GPIO_TypeDef *GPIOx, uint32_t n)
{
GPIOx->DATA ^= (0x01 << n);
}
/******************************************************************************************************************************************
* : GPIO_GetBit()
* :
* : GPIO_TypeDef * GPIOx GPIO端口GPIOAGPIOBGPIOCGPIOMGPIONGPIOP
* uint32_t n GPIO引脚PIN0PIN1PIN2... ... PIN22PIN23
* : 0 1
* :
******************************************************************************************************************************************/
uint32_t GPIO_GetBit(GPIO_TypeDef *GPIOx, uint32_t n)
{
return ((GPIOx->DATA >> n) & 0x01);
}
/******************************************************************************************************************************************
* : GPIO_SetBits()
* : n开始的w位连续引脚的电平置高
* : GPIO_TypeDef * GPIOx GPIO端口GPIOAGPIOBGPIOCGPIOMGPIONGPIOP
* uint32_t n GPIO引脚PIN0PIN1PIN2... ... PIN22PIN23
* uint32_t w
* :
* :
******************************************************************************************************************************************/
void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w)
{
uint32_t bits;
bits = 0xFFFFFF >> (24 - w);
GPIOx->DATA |= (bits << n);
}
/******************************************************************************************************************************************
* : GPIO_ClrBits()
* : n开始的w位连续引脚的电平置低
* : GPIO_TypeDef * GPIOx GPIO端口GPIOAGPIOBGPIOCGPIOMGPIONGPIOP
* uint32_t n GPIO引脚PIN0PIN1PIN2... ... PIN22PIN23
* uint32_t w
* :
* :
******************************************************************************************************************************************/
void GPIO_ClrBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w)
{
uint32_t bits;
bits = 0xFFFFFF >> (24 - w);
GPIOx->DATA &= ~(bits << n);
}
/******************************************************************************************************************************************
* : GPIO_InvBits()
* : n开始的w位连续引脚的电平反转
* : GPIO_TypeDef * GPIOx GPIO端口GPIOAGPIOBGPIOCGPIOMGPIONGPIOP
* uint32_t n GPIO引脚PIN0PIN1PIN2... ... PIN22PIN23
* uint32_t w
* :
* :
******************************************************************************************************************************************/
void GPIO_InvBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w)
{
uint32_t bits;
bits = 0xFFFFFF >> (24 - w);
GPIOx->DATA ^= (bits << n);
}
/******************************************************************************************************************************************
* : GPIO_GetBits()
* : n开始的w位连续引脚的电平状态
* : GPIO_TypeDef * GPIOx GPIO端口GPIOAGPIOBGPIOCGPIOMGPIONGPIOP
* uint32_t n GPIO引脚PIN0PIN1PIN2... ... PIN22PIN23
* uint32_t w
* : n开始的w位连续引脚的电平状态 0 1
* 0n的电平状态1n+1... ...w位表示引脚n+w的电平状态
* :
******************************************************************************************************************************************/
uint32_t GPIO_GetBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w)
{
uint32_t bits;
bits = 0xFFFFFF >> (24 - w);
return ((GPIOx->DATA >> n) & bits);
}
/******************************************************************************************************************************************
* : GPIO_AtomicSetBit()
* : --ISR打断
* : GPIO_TypeDef * GPIOx GPIO端口GPIOAGPIOBGPIOCGPIOD
* uint32_t n GPIO引脚PIN0PIN1PIN2... ... PIN14PIN15
* :
* : GPIOx的16个引脚中ISR中操作时GPIOx的引脚必须都用GPIO_Atomic类型函数操作
******************************************************************************************************************************************/
void GPIO_AtomicSetBit(GPIO_TypeDef *GPIOx, uint32_t n)
{
*((volatile uint32_t *)(0x42000000 + ((uint32_t)&GPIOx->DATA - 0x40000000) * 32 + n * 4)) = 1;
}
/******************************************************************************************************************************************
* : GPIO_AtomicClrBit()
* : --ISR打断
* : GPIO_TypeDef * GPIOx GPIO端口GPIOAGPIOBGPIOCGPIOD
* uint32_t n GPIO引脚PIN0PIN1PIN2... ... PIN14PIN15
* :
* : GPIOx的16个引脚中ISR中操作时GPIOx的引脚必须都用GPIO_Atomic类型函数操作
******************************************************************************************************************************************/
void GPIO_AtomicClrBit(GPIO_TypeDef *GPIOx, uint32_t n)
{
*((volatile uint32_t *)(0x42000000 + ((uint32_t)&GPIOx->DATA - 0x40000000) * 32 + n * 4)) = 0;
}
/******************************************************************************************************************************************
* : GPIO_AtomicInvBit()
* : --ISR打断
* : GPIO_TypeDef * GPIOx GPIO端口GPIOAGPIOBGPIOCGPIOD
* uint32_t n GPIO引脚PIN0PIN1PIN2... ... PIN14PIN15
* :
* : GPIOx的16个引脚中ISR中操作时GPIOx的引脚必须都用GPIO_Atomic类型函数操作
******************************************************************************************************************************************/
void GPIO_AtomicInvBit(GPIO_TypeDef *GPIOx, uint32_t n)
{
*((volatile uint32_t *)(0x42000000 + ((uint32_t)&GPIOx->DATA - 0x40000000) * 32 + n * 4)) = 1 - *((volatile uint32_t *)(0x42000000 + ((uint32_t)&GPIOx->DATA - 0x40000000) * 32 + n * 4));
}
/******************************************************************************************************************************************
* : GPIO_AtomicSetBits()
* : n开始的w位连续引脚的电平置高--ISR打断
* : GPIO_TypeDef * GPIOx GPIO端口GPIOAGPIOBGPIOCGPIOD
* uint32_t n GPIO引脚PIN0PIN1PIN2... ... PIN14PIN15
* uint32_t w
* :
* : GPIOx的16个引脚中ISR中操作时GPIOx的引脚必须都用GPIO_Atomic类型函数操作
******************************************************************************************************************************************/
void GPIO_AtomicSetBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w)
{
uint32_t bits;
bits = 0xFFFFFF >> (24 - w);
__disable_irq();
GPIOx->DATA |= (bits << n);
__enable_irq();
}
/******************************************************************************************************************************************
* : GPIO_AtomicClrBits()
* : n开始的w位连续引脚的电平置低--ISR打断
* : GPIO_TypeDef * GPIOx GPIO端口GPIOAGPIOBGPIOCGPIOD
* uint32_t n GPIO引脚PIN0PIN1PIN2... ... PIN14PIN15
* uint32_t w
* :
* : GPIOx的16个引脚中ISR中操作时GPIOx的引脚必须都用GPIO_Atomic类型函数操作
******************************************************************************************************************************************/
void GPIO_AtomicClrBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w)
{
uint32_t bits;
bits = 0xFFFFFF >> (24 - w);
__disable_irq();
GPIOx->DATA &= ~(bits << n);
__enable_irq();
}
/******************************************************************************************************************************************
* : GPIO_AtomicInvBits()
* : n开始的w位连续引脚的电平反转--ISR打断
* : GPIO_TypeDef * GPIOx GPIO端口GPIOAGPIOBGPIOCGPIOD
* uint32_t n GPIO引脚PIN0PIN1PIN2... ... PIN14PIN15
* uint32_t w
* :
* : GPIOx的16个引脚中ISR中操作时GPIOx的引脚必须都用GPIO_Atomic类型函数操作
******************************************************************************************************************************************/
void GPIO_AtomicInvBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w)
{
uint32_t bits;
bits = 0xFFFFFF >> (24 - w);
__disable_irq();
GPIOx->DATA ^= (bits << n);
__enable_irq();
}

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#ifndef __SWM320_GPIO_H__
#define __SWM320_GPIO_H__
void GPIO_Init(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t dir, uint32_t pull_up, uint32_t pull_down); //引脚初始化,包含引脚方向、上拉电阻、下拉电阻
void GPIO_SetBit(GPIO_TypeDef *GPIOx, uint32_t n); //将参数指定的引脚电平置高
void GPIO_ClrBit(GPIO_TypeDef *GPIOx, uint32_t n); //将参数指定的引脚电平置低
void GPIO_InvBit(GPIO_TypeDef *GPIOx, uint32_t n); //将参数指定的引脚电平反转
uint32_t GPIO_GetBit(GPIO_TypeDef *GPIOx, uint32_t n); //读取参数指定的引脚的电平状态
void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w); //将参数指定的从n开始的w位连续引脚的电平置高
void GPIO_ClrBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w); //将参数指定的从n开始的w位连续引脚的电平置低
void GPIO_InvBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w); //将参数指定的从n开始的w位连续引脚的电平反转
uint32_t GPIO_GetBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w); //读取参数指定的从n开始的w位连续引脚的电平状态
void GPIO_AtomicSetBit(GPIO_TypeDef *GPIOx, uint32_t n);
void GPIO_AtomicClrBit(GPIO_TypeDef *GPIOx, uint32_t n);
void GPIO_AtomicInvBit(GPIO_TypeDef *GPIOx, uint32_t n);
void GPIO_AtomicSetBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w);
void GPIO_AtomicClrBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w);
void GPIO_AtomicInvBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w);
#endif //__SWM320_GPIO_H__

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@ -1,219 +0,0 @@
/******************************************************************************************************************************************
* : SWM320_i2c.c
* : SWM320单片机的I2C串行接口功能驱动库
* : http://www.synwit.com.cn/e/tool/gbook/?bid=1
* :
* : V1.1.0 20171025
* :
*
*
*******************************************************************************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIES AT PROVIDING CUSTOMERS WITH CODING INFORMATION
* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIEE. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIES ARISING FROM THE CONTENT
* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
* -ECTION WITH THEIR PRODUCTS.
*
* COPYRIGHT 2012 Synwit Technology
*******************************************************************************************************************************************/
#include "SWM320.h"
#include "SWM320_i2c.h"
/******************************************************************************************************************************************
* : I2C_Init()
* : I2C初始化
* : I2C_TypeDef * I2Cx I2CI2C0I2C1
* I2C_InitStructure * initStruct I2C相关设定值的结构体
* :
* :
******************************************************************************************************************************************/
void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitStructure *initStruct)
{
switch ((uint32_t)I2Cx)
{
case ((uint32_t)I2C0):
SYS->CLKEN |= (0x01 << SYS_CLKEN_I2C0_Pos);
break;
case ((uint32_t)I2C1):
SYS->CLKEN |= (0x01 << SYS_CLKEN_I2C1_Pos);
break;
}
I2C_Close(I2Cx); //一些关键寄存器只能在I2C关闭时设置
if (initStruct->Master == 1)
{
I2Cx->CLKDIV = SystemCoreClock / 5 / initStruct->MstClk;
I2Cx->MSTCMD = (I2Cx->MSTCMD & (~I2C_MSTCMD_IF_Msk)) | (1 << I2C_MSTCMD_IF_Pos); //使能中断之前先清除中断标志
I2Cx->CTRL &= ~I2C_CTRL_MSTIE_Msk;
I2Cx->CTRL |= (initStruct->MstIEn << I2C_CTRL_MSTIE_Pos);
switch ((uint32_t)I2Cx)
{
case ((uint32_t)I2C0):
if (initStruct->MstIEn)
{
NVIC_EnableIRQ(I2C0_IRQn);
}
else
{
NVIC_DisableIRQ(I2C0_IRQn);
}
break;
case ((uint32_t)I2C1):
if (initStruct->MstIEn)
{
NVIC_EnableIRQ(I2C1_IRQn);
}
else
{
NVIC_DisableIRQ(I2C1_IRQn);
}
break;
}
}
else
{
I2Cx->SLVCR |= (1 << I2C_SLVCR_SLAVE_Pos);
I2Cx->SLVCR &= ~(I2C_SLVCR_ADDR7b_Msk | I2C_SLVCR_ADDR_Msk);
I2Cx->SLVCR |= (1 << I2C_SLVCR_ACK_Pos) |
(initStruct->Addr7b << I2C_SLVCR_ADDR7b_Pos) |
(initStruct->SlvAddr << I2C_SLVCR_ADDR_Pos);
I2Cx->SLVIF = I2C_SLVIF_RXEND_Msk | I2C_SLVIF_TXEND_Msk | I2C_SLVIF_STADET_Msk | I2C_SLVIF_STODET_Msk; //清中断标志
I2Cx->SLVCR &= ~(I2C_SLVCR_IM_RXEND_Msk | I2C_SLVCR_IM_TXEND_Msk | I2C_SLVCR_IM_STADET_Msk | I2C_SLVCR_IM_STODET_Msk |
I2C_SLVCR_IM_RDREQ_Msk | I2C_SLVCR_IM_WRREQ_Msk);
I2Cx->SLVCR |= ((initStruct->SlvRxEndIEn ? 0 : 1) << I2C_SLVCR_IM_RXEND_Pos) |
((initStruct->SlvTxEndIEn ? 0 : 1) << I2C_SLVCR_IM_TXEND_Pos) |
((initStruct->SlvSTADetIEn ? 0 : 1) << I2C_SLVCR_IM_STADET_Pos) |
((initStruct->SlvSTODetIEn ? 0 : 1) << I2C_SLVCR_IM_STODET_Pos) |
((initStruct->SlvRdReqIEn ? 0 : 1) << I2C_SLVCR_IM_RDREQ_Pos) |
((initStruct->SlvWrReqIEn ? 0 : 1) << I2C_SLVCR_IM_WRREQ_Pos);
switch ((uint32_t)I2Cx)
{
case ((uint32_t)I2C0):
if (initStruct->SlvRxEndIEn | initStruct->SlvTxEndIEn | initStruct->SlvSTADetIEn |
initStruct->SlvSTODetIEn | initStruct->SlvRdReqIEn | initStruct->SlvWrReqIEn)
{
NVIC_EnableIRQ(I2C0_IRQn);
}
else
{
NVIC_DisableIRQ(I2C0_IRQn);
}
break;
case ((uint32_t)I2C1):
if (initStruct->SlvRxEndIEn | initStruct->SlvTxEndIEn | initStruct->SlvSTADetIEn |
initStruct->SlvSTODetIEn | initStruct->SlvRdReqIEn | initStruct->SlvWrReqIEn)
{
NVIC_EnableIRQ(I2C1_IRQn);
}
else
{
NVIC_DisableIRQ(I2C1_IRQn);
}
break;
}
}
}
/******************************************************************************************************************************************
* : I2C_Open()
* : I2C打开
* : I2C_TypeDef * I2Cx I2CI2C0I2C1
* :
* :
******************************************************************************************************************************************/
void I2C_Open(I2C_TypeDef *I2Cx)
{
I2Cx->CTRL |= (0x01 << I2C_CTRL_EN_Pos);
}
/******************************************************************************************************************************************
* : I2C_Close()
* : I2C关闭
* : I2C_TypeDef * I2Cx I2CI2C0I2C1
* :
* :
******************************************************************************************************************************************/
void I2C_Close(I2C_TypeDef *I2Cx)
{
I2Cx->CTRL &= ~I2C_CTRL_EN_Msk;
}
/******************************************************************************************************************************************
* : I2C_Start()
* :
* : I2C_TypeDef * I2Cx I2CI2C0I2C1
* uint8_t addr
* : uint8_t 1 ACK 0 NACK
* :
******************************************************************************************************************************************/
uint8_t I2C_Start(I2C_TypeDef *I2Cx, uint8_t addr)
{
I2Cx->MSTDAT = addr;
I2Cx->MSTCMD = (1 << I2C_MSTCMD_STA_Pos) |
(1 << I2C_MSTCMD_WR_Pos); //发送起始位和从机地址
while (I2Cx->MSTCMD & I2C_MSTCMD_TIP_Msk)
__NOP(); //等待发送完成
return (I2Cx->MSTCMD & I2C_MSTCMD_RXACK_Msk) ? 0 : 1;
}
/******************************************************************************************************************************************
* : I2C_Stop()
* :
* : I2C_TypeDef * I2Cx I2CI2C0I2C1
* :
* :
******************************************************************************************************************************************/
void I2C_Stop(I2C_TypeDef *I2Cx)
{
I2Cx->MSTCMD = (1 << I2C_MSTCMD_STO_Pos);
while (I2Cx->MSTCMD & I2C_MSTCMD_TIP_Msk)
__NOP(); //等待发送完成
}
/******************************************************************************************************************************************
* : I2C_Write()
* :
* : I2C_TypeDef * I2Cx I2CI2C0I2C1
* uint8_t data
* : uint8_t 1 ACK 0 NACK
* :
******************************************************************************************************************************************/
uint8_t I2C_Write(I2C_TypeDef *I2Cx, uint8_t data)
{
I2Cx->MSTDAT = data;
I2Cx->MSTCMD = (1 << I2C_MSTCMD_WR_Pos);
while (I2Cx->MSTCMD & I2C_MSTCMD_TIP_Msk)
__NOP(); //等待发送完成
return (I2Cx->MSTCMD & I2C_MSTCMD_RXACK_Msk) ? 0 : 1;
}
/******************************************************************************************************************************************
* : I2C_Read()
* :
* : I2C_TypeDef * I2Cx I2CI2C0I2C1
* uint8_t ack 1 ACK 0 NACK
* : uint8_t
* :
******************************************************************************************************************************************/
uint8_t I2C_Read(I2C_TypeDef *I2Cx, uint8_t ack)
{
I2Cx->MSTCMD = (1 << I2C_MSTCMD_RD_Pos) |
((ack ? 0 : 1) << I2C_MSTCMD_ACK_Pos);
while (I2Cx->MSTCMD & I2C_MSTCMD_TIP_Msk)
__NOP(); //等待接收完成
return I2Cx->MSTDAT;
}

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@ -1,31 +0,0 @@
#ifndef __SWM320_I2C_H__
#define __SWM320_I2C_H__
typedef struct
{
uint8_t Master; //1 主机模式
uint8_t Addr7b; //1 7位地址 0 10位地址
uint32_t MstClk; //主机传输时钟频率
uint8_t MstIEn; //主机模式中断使能
uint16_t SlvAddr; //从机地址
uint8_t SlvRxEndIEn; //从机接收完成中断使能
uint8_t SlvTxEndIEn; //从机发送完成中断使能
uint8_t SlvSTADetIEn; //从机检测到起始中断使能
uint8_t SlvSTODetIEn; //从机检测到终止中断使能
uint8_t SlvRdReqIEn; //从机接收到读请求中断使能
uint8_t SlvWrReqIEn; //从机接收到写请求中断使能
} I2C_InitStructure;
void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitStructure *initStruct);
void I2C_Open(I2C_TypeDef *I2Cx);
void I2C_Close(I2C_TypeDef *I2Cx);
uint8_t I2C_Start(I2C_TypeDef *I2Cx, uint8_t addr);
void I2C_Stop(I2C_TypeDef *I2Cx);
uint8_t I2C_Write(I2C_TypeDef *I2Cx, uint8_t data);
uint8_t I2C_Read(I2C_TypeDef *I2Cx, uint8_t ack);
#endif //__SWM320_I2C_H__

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@ -1,147 +0,0 @@
/******************************************************************************************************************************************
* : SWM320_lcd.c
* : SWM320单片机的LCD功能驱动库
* : http://www.synwit.com.cn/e/tool/gbook/?bid=1
* :
* : V1.1.0 20171025
* :
*
*
*******************************************************************************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
* -ECTION WITH THEIR PRODUCTS.
*
* COPYRIGHT 2012 Synwit Technology
*******************************************************************************************************************************************/
#include "SWM320.h"
#include "SWM320_lcd.h"
#include <string.h>
/******************************************************************************************************************************************
* : LCD_Init()
* : LCD初始化
* : LCD_TypeDef * LCDx LCDLCD
* LCD_InitStructure * initStruct LCD相关设定值的结构体
* :
* :
******************************************************************************************************************************************/
void LCD_Init(LCD_TypeDef *LCDx, LCD_InitStructure *initStruct)
{
switch ((uint32_t)LCDx)
{
case ((uint32_t)LCD):
SYS->CLKEN |= (0x01 << SYS_CLKEN_LCD_Pos);
break;
}
LCDx->CR0 = ((initStruct->HnPixel - 1) << LCD_CR0_HPIX_Pos) |
((initStruct->VnPixel - 1) << LCD_CR0_VPIX_Pos) |
(initStruct->ClkAlways << LCD_CR0_DCLK_Pos) |
(initStruct->HsyncWidth << LCD_CR0_HLOW_Pos);
LCDx->CR1 = ((initStruct->Hfp - 1) << LCD_CR1_HFP_Pos) |
((initStruct->Hbp - 1) << LCD_CR1_HBP_Pos) |
((initStruct->Vfp - 1) << LCD_CR1_VFP_Pos) |
((initStruct->Vbp - 1) << LCD_CR1_VBP_Pos) |
(initStruct->ClkDiv << LCD_CR1_DCLKDIV_Pos) |
(initStruct->SamplEdge << LCD_CR1_DCLKINV_Pos);
LCDx->IE = 1;
LCDx->IF = 1; //清除标志
if (initStruct->IntEOTEn)
LCD_INTEn(LCDx);
else
LCD_INTDis(LCDx);
switch ((uint32_t)LCDx)
{
case ((uint32_t)LCD):
if (initStruct->IntEOTEn)
{
NVIC_EnableIRQ(LCD_IRQn);
}
else
{
NVIC_DisableIRQ(LCD_IRQn);
}
break;
}
}
/******************************************************************************************************************************************
* : LCD_Start()
* :
* : LCD_TypeDef * LCDx LCDLCD
* :
* :
******************************************************************************************************************************************/
void LCD_Start(LCD_TypeDef *LCDx)
{
LCDx->START |= (1 << LCD_START_GO_Pos) | (1 << LCD_START_BURST_Pos);
}
/******************************************************************************************************************************************
* : LCD_IsBusy()
* :
* : LCD_TypeDef * LCDx LCDLCD
* : uint32_t 1 0
* :
******************************************************************************************************************************************/
uint32_t LCD_IsBusy(LCD_TypeDef *LCDx)
{
return (LCDx->START & LCD_START_GO_Msk) ? 1 : 0;
}
/******************************************************************************************************************************************
* : LCD_INTEn()
* : LCD中断使能
* : LCD_TypeDef * LCDx LCDLCD
* :
* :
******************************************************************************************************************************************/
void LCD_INTEn(LCD_TypeDef *LCDx)
{
LCDx->IM = 0;
}
/******************************************************************************************************************************************
* : LCD_INTDis()
* : LCD中断禁止
* : LCD_TypeDef * LCDx LCDLCD
* :
* :
******************************************************************************************************************************************/
void LCD_INTDis(LCD_TypeDef *LCDx)
{
LCDx->IM = 1;
}
/******************************************************************************************************************************************
* : LCD_INTClr()
* : LCD中断标志清除
* : LCD_TypeDef * LCDx LCDLCD
* :
* :
******************************************************************************************************************************************/
void LCD_INTClr(LCD_TypeDef *LCDx)
{
LCDx->IF = 1;
}
/******************************************************************************************************************************************
* : LCD_INTStat()
* : LCD中断状态查询
* : LCD_TypeDef * LCDx LCDLCD
* : uint32_t 1 0
* :
******************************************************************************************************************************************/
uint32_t LCD_INTStat(LCD_TypeDef *LCDx)
{
return (LCDx->IF & 0x01) ? 1 : 0;
}

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#ifndef __SWM320_LCD_H__
#define __SWM320_LCD_H__
typedef struct
{
uint16_t HnPixel; //水平方向像素个数最大取值1024
uint16_t VnPixel; //垂直方向像素个数,最大取值 768
uint8_t Hfp; //horizonal front porch最大取值32
uint8_t Hbp; //horizonal back porch 最大取值128
uint8_t Vfp; //vertical front porch 最大取值8
uint8_t Vbp; //vertical back porch 最大取值32
uint8_t ClkDiv; //系统时钟经ClkDiv分频后产生DOCCLK0 2分频 1 4分频 2 6分频 ... ... 31 64分频
uint8_t SamplEdge; //屏幕在DOTCLK的哪个边沿采样数据LCD_SAMPLEDGE_RISE、LCD_SAMPLEDGE_FALL
uint8_t ClkAlways; //1 一直输出DOTCLK 0 只在传输数据时输出DOTCLK
uint8_t HsyncWidth; //HSYNC低电平持续多少个DOTCLK取值LCD_HSYNC_1DOTCLK、LCD_HSYNC_2DOTCLK、LCD_HSYNC_3DOTCLK、LCD_HSYNC_4DOTCLK
uint8_t IntEOTEn; //End of Transter传输完成中断使能
} LCD_InitStructure;
#define LCD_SAMPLEDGE_RISE 0 //屏幕在DOTCLK的上升沿采样数据
#define LCD_SAMPLEDGE_FALL 1 //屏幕在DOTCLK的下降沿采样数据
#define LCD_HSYNC_1DOTCLK 0 //1个DOTCLK
#define LCD_HSYNC_2DOTCLK 1
#define LCD_HSYNC_3DOTCLK 2
#define LCD_HSYNC_4DOTCLK 3
#define LCD_CLKDIV_2 0
#define LCD_CLKDIV_4 1
#define LCD_CLKDIV_6 2
#define LCD_CLKDIV_8 3
#define LCD_CLKDIV_10 4
#define LCD_CLKDIV_12 5
#define LCD_CLKDIV_14 6
#define LCD_CLKDIV_16 7
#define LCD_CLKDIV_18 8
#define LCD_CLKDIV_20 9
#define LCD_CLKDIV_22 10
#define LCD_CLKDIV_24 11
#define LCD_CLKDIV_26 12
#define LCD_CLKDIV_28 13
#define LCD_CLKDIV_30 14
#define LCD_CLKDIV_32 15
#define LCD_CLKDIV_34 16
#define LCD_CLKDIV_36 17
#define LCD_CLKDIV_38 18
#define LCD_CLKDIV_40 19
#define LCD_CLKDIV_42 20
#define LCD_CLKDIV_44 21
#define LCD_CLKDIV_46 22
#define LCD_CLKDIV_48 23
#define LCD_CLKDIV_50 24
#define LCD_CLKDIV_52 25
#define LCD_CLKDIV_54 26
#define LCD_CLKDIV_56 27
#define LCD_CLKDIV_58 28
#define LCD_CLKDIV_60 29
#define LCD_CLKDIV_62 30
#define LCD_CLKDIV_64 31
void LCD_Init(LCD_TypeDef *LCDx, LCD_InitStructure *initStruct);
void LCD_Start(LCD_TypeDef *LCDx);
uint32_t LCD_IsBusy(LCD_TypeDef *LCDx);
void LCD_INTEn(LCD_TypeDef *LCDx);
void LCD_INTDis(LCD_TypeDef *LCDx);
void LCD_INTClr(LCD_TypeDef *LCDx);
uint32_t LCD_INTStat(LCD_TypeDef *LCDx);
#endif //__SWM320_LCD_H__

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@ -1,187 +0,0 @@
/******************************************************************************************************************************************
* : SWM320_norflash.c
* : SWM320单片机的NOR Flash驱动程序
* : http://www.synwit.com.cn/e/tool/gbook/?bid=1
* :
* : V1.1.0 20171025
* :
*
*
*******************************************************************************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
* -ECTION WITH THEIR PRODUCTS.
*
* COPYRIGHT 2012 Synwit Technology
*******************************************************************************************************************************************/
#include "SWM320.h"
#include "SWM320_norflash.h"
/******************************************************************************************************************************************
* : NORFL_Init()
* : NOR Flash控制器初始化
* : NORFL_InitStructure * initStruct NOR Flash控制器相关设定值的结构体
* :
* :
******************************************************************************************************************************************/
void NORFL_Init(NORFL_InitStructure *initStruct)
{
uint32_t i;
// 配置SRAM前需要刷新下SDRAM控制器
do
{
SYS->CLKEN |= (1 << SYS_CLKEN_SDRAM_Pos);
while (SDRAMC->REFDONE == 0)
;
SDRAMC->REFRESH &= ~(1 << SDRAMC_REFRESH_EN_Pos);
for (i = 0; i < 1000; i++)
__NOP();
SYS->CLKEN &= ~(1 << SYS_CLKEN_SDRAM_Pos);
} while (0);
SYS->CLKEN |= (1 << SYS_CLKEN_NORFL_Pos);
NORFLC->CR = ((initStruct->DataWidth == 8 ? 1 : 0) << NORFLC_CR_BYTEIF_Pos) |
(initStruct->WELowPulseTime << NORFLC_CR_WRTIME_Pos) |
(initStruct->OEPreValidTime << NORFLC_CR_RDTIME_Pos);
NORFLC->IE = 3;
NORFLC->IF = 3; // 清除中断标志
if (initStruct->OperFinishIEn)
NORFLC->IM &= ~(1 << NORFLC_IM_FINISH_Pos);
else
NORFLC->IM |= (1 << NORFLC_IM_FINISH_Pos);
if (initStruct->OperTimeoutIEn)
NORFLC->IM &= ~(1 << NORFLC_IM_TIMEOUT_Pos);
else
NORFLC->IM |= (1 << NORFLC_IM_TIMEOUT_Pos);
}
/******************************************************************************************************************************************
* : NORFL_ChipErase()
* : NOR Flash整片擦除
* :
* : uint32_t 0 1
* :
******************************************************************************************************************************************/
uint32_t NORFL_ChipErase(void)
{
uint32_t res;
NORFLC->CMD = (NORFL_CMD_CHIP_ERASE << NORFLC_CMD_CMD_Pos);
while (((NORFLC->IF & NORFLC_IF_FINISH_Msk) == 0) &&
((NORFLC->IF & NORFLC_IF_TIMEOUT_Msk) == 0))
__NOP();
if (NORFLC->IF & NORFLC_IF_FINISH_Msk)
res = 0;
else
res = 1;
NORFLC->IF = NORFLC_IF_FINISH_Msk | NORFLC_IF_TIMEOUT_Msk;
return res;
}
/******************************************************************************************************************************************
* : NORFL_SectorErase()
* : NOR Flash扇区擦除
* : uint32_t addr
* : uint32_t 0 1
* : MX29LV128DB 88K25564K MX29LV128DT 25564K88K
******************************************************************************************************************************************/
uint32_t NORFL_SectorErase(uint32_t addr)
{
uint32_t res;
NORFLC->ADDR = addr;
NORFLC->CMD = (NORFL_CMD_SECTOR_ERASE << NORFLC_CMD_CMD_Pos);
while (((NORFLC->IF & NORFLC_IF_FINISH_Msk) == 0) &&
((NORFLC->IF & NORFLC_IF_TIMEOUT_Msk) == 0))
__NOP();
if (NORFLC->IF & NORFLC_IF_FINISH_Msk)
res = 0;
else
res = 1;
NORFLC->IF = NORFLC_IF_FINISH_Msk | NORFLC_IF_TIMEOUT_Msk;
return res;
}
/******************************************************************************************************************************************
* : NORFL_Write()
* : NOR Flash写
* : uint32_t addr
* uint32_t data
* : uint32_t 0 1
* : 线16线8
******************************************************************************************************************************************/
uint32_t NORFL_Write(uint32_t addr, uint32_t data)
{
uint32_t res;
NORFLC->ADDR = addr;
NORFLC->CMD = (NORFL_CMD_PROGRAM << NORFLC_CMD_CMD_Pos) | (data << NORFLC_CMD_DATA_Pos);
while (((NORFLC->IF & NORFLC_IF_FINISH_Msk) == 0) &&
((NORFLC->IF & NORFLC_IF_TIMEOUT_Msk) == 0))
__NOP();
if (NORFLC->IF & NORFLC_IF_FINISH_Msk)
res = 0;
else
res = 1;
NORFLC->IF = NORFLC_IF_FINISH_Msk | NORFLC_IF_TIMEOUT_Msk;
return res;
}
/******************************************************************************************************************************************
* : NORFL_Read()
* : NOR Flash读
* : uint32_t addr
* : uint32_t
* : 线16线8
******************************************************************************************************************************************/
uint32_t NORFL_Read(uint32_t addr)
{
NORFLC->ADDR = addr;
NORFLC->CMD = (NORFL_CMD_READ << NORFLC_CMD_CMD_Pos);
return (NORFLC->CMD & NORFLC_CMD_DATA_Msk);
}
/******************************************************************************************************************************************
* : NORFL_ReadID()
* : NOR Flash读ID
* : uint32_t id_addr ID地址
* : uint16_t ID
* :
******************************************************************************************************************************************/
uint16_t NORFL_ReadID(uint32_t id_addr)
{
uint16_t id;
NORFLC->CMD = (NORFL_CMD_AUTO_SELECT << NORFLC_CMD_CMD_Pos);
NORFLC->ADDR = id_addr;
NORFLC->CMD = (NORFL_CMD_READ << NORFLC_CMD_CMD_Pos);
id = NORFLC->CMD & NORFLC_CMD_DATA_Msk;
NORFLC->CMD = (NORFL_CMD_RESET << NORFLC_CMD_CMD_Pos); // 退出ID读取模式
return id;
}

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#ifndef __SWM320_NORFLASH_H__
#define __SWM320_NORFLASH_H__
typedef struct
{
uint8_t DataWidth; // 8、16
uint8_t WELowPulseTime; // WE# pulse width单位为系统时钟周期最大值为7
uint8_t OEPreValidTime; // Valid data output after OE# low单位为系统时钟周期最大值为15
uint8_t OperFinishIEn; // 操作(写入、擦除)完成中断使能
uint8_t OperTimeoutIEn;
} NORFL_InitStructure;
void NORFL_Init(NORFL_InitStructure *initStruct);
uint32_t NORFL_ChipErase(void);
uint32_t NORFL_SectorErase(uint32_t addr);
uint32_t NORFL_Write(uint32_t addr, uint32_t data);
uint32_t NORFL_Read(uint32_t addr);
uint16_t NORFL_ReadID(uint32_t id_addr);
/* 当前版本总线读只支持字读
#define NORFL_Read8(addr) *((volatile uint8_t *)(NORFLM_BASE + addr))
#define NORFL_Read16(addr) *((volatile uint16_t *)(NORFLM_BASE + addr)) */
#define NORFL_Read32(addr) *((volatile uint32_t *)(NORFLM_BASE + addr))
#define NORFL_CMD_READ 0
#define NORFL_CMD_RESET 1
#define NORFL_CMD_AUTO_SELECT 2
#define NORFL_CMD_PROGRAM 3
#define NORFL_CMD_CHIP_ERASE 4
#define NORFL_CMD_SECTOR_ERASE 5
#endif // __SWM320_NORFLASH_H__

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/******************************************************************************************************************************************
* : SWM320_port.c
* : SWM320单片机的端口引脚功能选择库函数
* : http://www.synwit.com.cn/e/tool/gbook/?bid=1
* :
* : V1.1.0 20171025
* :
*
*
*******************************************************************************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
* -ECTION WITH THEIR PRODUCTS.
*
* COPYRIGHT 2012 Synwit Technology
*******************************************************************************************************************************************/
#include "SWM320.h"
#include "SWM320_port.h"
/******************************************************************************************************************************************
* : PORT_Init()
* : "SWM320_port.h"
* : uint32_t PORTx PORT端口PORTAPORTBPORTCPORTMPORTNPORTP
* uint32_t n PORT引脚PIN0PIN1PIN2... ... PIN22PIN23
* uint32_t func "SWM320_port.h"
* uint32_t digit_in_en 使
* :
* : n为偶数时func取值只能是FUNMUX0开头的FUNMUX0_UART0_RXD
* n为奇数时func取值只能是FUNMUX1开头的FUNMUX1_UART0_TXD
******************************************************************************************************************************************/
void PORT_Init(uint32_t PORTx, uint32_t n, uint32_t func, uint32_t digit_in_en)
{
switch ((uint32_t)PORTx)
{
case ((uint32_t)PORTA):
if (func > 99)
{
if (n < PIN6)
{
PORT->PORTA_MUX0 &= ~(0x1F << (n * 5));
PORT->PORTA_MUX0 |= (func - 100) << (n * 5);
}
else if (n < PIN12)
{
PORT->PORTA_MUX1 &= ~(0x1F << ((n - 6) * 5));
PORT->PORTA_MUX1 |= (func - 100) << ((n - 6) * 5);
}
}
PORT->PORTA_SEL &= ~(0x03 << (n * 2));
PORT->PORTA_SEL |= (func > 99 ? 1 : func) << (n * 2);
PORT->PORTA_INEN &= ~(0x01 << n);
PORT->PORTA_INEN |= (digit_in_en << n);
break;
case ((uint32_t)PORTB):
if (func > 99)
{
if (n < PIN6)
{
PORT->PORTB_MUX0 &= ~(0x1F << (n * 5));
PORT->PORTB_MUX0 |= (func - 100) << (n * 5);
}
else if (n < PIN12)
{
PORT->PORTB_MUX1 &= ~(0x1F << ((n - 6) * 5));
PORT->PORTB_MUX1 |= (func - 100) << ((n - 6) * 5);
}
}
PORT->PORTB_SEL &= ~(0x03 << (n * 2));
PORT->PORTB_SEL |= (func > 99 ? 1 : func) << (n * 2);
PORT->PORTB_INEN &= ~(0x01 << n);
PORT->PORTB_INEN |= (digit_in_en << n);
break;
case ((uint32_t)PORTC):
if (func > 99)
{
if (n < PIN6)
{
PORT->PORTC_MUX0 &= ~(0x1F << (n * 5));
PORT->PORTC_MUX0 |= (func - 100) << (n * 5);
}
else if (n < PIN12)
{
PORT->PORTC_MUX1 &= ~(0x1F << ((n - 6) * 5));
PORT->PORTC_MUX1 |= (func - 100) << ((n - 6) * 5);
}
}
PORT->PORTC_SEL &= ~(0x03 << (n * 2));
PORT->PORTC_SEL |= (func > 99 ? 1 : func) << (n * 2);
PORT->PORTC_INEN &= ~(0x01 << n);
PORT->PORTC_INEN |= (digit_in_en << n);
break;
case ((uint32_t)PORTM):
if (func > 99)
{
if (n < PIN6)
{
PORT->PORTM_MUX0 &= ~(0x1F << (n * 5));
PORT->PORTM_MUX0 |= (func - 100) << (n * 5);
}
else if (n < PIN12)
{
PORT->PORTM_MUX1 &= ~(0x1F << ((n - 6) * 5));
PORT->PORTM_MUX1 |= (func - 100) << ((n - 6) * 5);
}
else if (n < PIN18)
{
PORT->PORTM_MUX2 &= ~(0x1F << ((n - 12) * 5));
PORT->PORTM_MUX2 |= (func - 100) << ((n - 12) * 5);
}
else if (n < PIN24)
{
PORT->PORTM_MUX3 &= ~(0x1F << ((n - 18) * 5));
PORT->PORTM_MUX3 |= (func - 100) << ((n - 18) * 5);
}
}
if (n < 16)
{
PORT->PORTM_SEL0 &= ~(0x03 << (n * 2));
PORT->PORTM_SEL0 |= (func > 99 ? 1 : func) << (n * 2);
}
else
{
PORT->PORTM_SEL1 &= ~(0x03 << ((n - 16) * 2));
PORT->PORTM_SEL1 |= (func > 99 ? 1 : func) << ((n - 16) * 2);
}
PORT->PORTM_INEN &= ~(0x01 << n);
PORT->PORTM_INEN |= (digit_in_en << n);
break;
case ((uint32_t)PORTN):
if (func > 99)
{
if (n < PIN6)
{
PORT->PORTN_MUX0 &= ~(0x1F << (n * 5));
PORT->PORTN_MUX0 |= (func - 100) << (n * 5);
}
else if (n < PIN12)
{
PORT->PORTN_MUX1 &= ~(0x1F << ((n - 6) * 5));
PORT->PORTN_MUX1 |= (func - 100) << ((n - 6) * 5);
}
else if (n < PIN18)
{
PORT->PORTN_MUX2 &= ~(0x1F << ((n - 12) * 5));
PORT->PORTN_MUX2 |= (func - 100) << ((n - 12) * 5);
}
}
if (n < 16)
{
PORT->PORTN_SEL0 &= ~(0x03 << (n * 2));
PORT->PORTN_SEL0 |= (func > 99 ? 1 : func) << (n * 2);
}
else
{
PORT->PORTN_SEL1 &= ~(0x03 << ((n - 16) * 2));
PORT->PORTN_SEL1 |= (func > 99 ? 1 : func) << ((n - 16) * 2);
}
PORT->PORTN_INEN &= ~(0x01 << n);
PORT->PORTN_INEN |= (digit_in_en << n);
break;
case ((uint32_t)PORTP):
if (func > 99)
{
if (n < PIN6)
{
PORT->PORTP_MUX0 &= ~(0x1F << (n * 5));
PORT->PORTP_MUX0 |= (func - 100) << (n * 5);
}
else if (n < PIN12)
{
PORT->PORTP_MUX1 &= ~(0x1F << ((n - 6) * 5));
PORT->PORTP_MUX1 |= (func - 100) << ((n - 6) * 5);
}
else if (n < PIN18)
{
PORT->PORTP_MUX2 &= ~(0x1F << ((n - 12) * 5));
PORT->PORTP_MUX2 |= (func - 100) << ((n - 12) * 5);
}
else if (n < PIN24)
{
PORT->PORTP_MUX3 &= ~(0x1F << ((n - 18) * 5));
PORT->PORTP_MUX3 |= (func - 100) << ((n - 18) * 5);
}
}
if (n < 16)
{
PORT->PORTP_SEL0 &= ~(0x03 << (n * 2));
PORT->PORTP_SEL0 |= (func > 99 ? 1 : func) << (n * 2);
}
else
{
PORT->PORTP_SEL1 &= ~(0x03 << ((n - 16) * 2));
PORT->PORTP_SEL1 |= (func > 99 ? 1 : func) << ((n - 16) * 2);
}
PORT->PORTP_INEN &= ~(0x01 << n);
PORT->PORTP_INEN |= (digit_in_en << n);
break;
}
}

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#ifndef __SWM320_PORT_H__
#define __SWM320_PORT_H__
void PORT_Init(uint32_t PORTx, uint32_t n, uint32_t func, uint32_t digit_in_en); //端口引脚功能选择,其可取值如下:
#define PORTA 0
#define PORTB 1
#define PORTC 2
#define PORTM 3
#define PORTN 4
#define PORTP 5
#define PORTA_PIN0_GPIO 0
#define PORTA_PIN0_FUNMUX 1
#define PORTA_PIN0_SWCLK 2
#define PORTA_PIN1_GPIO 0
#define PORTA_PIN1_FUNMUX 1
#define PORTA_PIN1_SWDIO 2
#define PORTA_PIN2_GPIO 0
#define PORTA_PIN2_FUNMUX 1
#define PORTA_PIN3_GPIO 0
#define PORTA_PIN3_FUNMUX 1
#define PORTA_PIN4_GPIO 0
#define PORTA_PIN4_FUNMUX 1
#define PORTA_PIN5_GPIO 0
#define PORTA_PIN5_FUNMUX 1
#define PORTA_PIN6_GPIO 0
#define PORTA_PIN6_FUNMUX 1
#define PORTA_PIN7_GPIO 0
#define PORTA_PIN7_FUNMUX 1
#define PORTA_PIN8_GPIO 0
#define PORTA_PIN8_FUNMUX 1
#define PORTA_PIN9_GPIO 0
#define PORTA_PIN9_FUNMUX 1
#define PORTA_PIN9_ADC0_IN7 3
#define PORTA_PIN10_GPIO 0
#define PORTA_PIN10_FUNMUX 1
#define PORTA_PIN10_ADC0_IN6 3
#define PORTA_PIN11_GPIO 0
#define PORTA_PIN11_FUNMUX 1
#define PORTA_PIN11_ADC0_IN5 3
#define PORTA_PIN12_GPIO 0
#define PORTA_PIN12_ADC0_IN4 3
#define PORTB_PIN0_GPIO 0
#define PORTB_PIN0_FUNMUX 1
#define PORTB_PIN0_SD_DETECT 2
#define PORTB_PIN1_GPIO 0
#define PORTB_PIN1_FUNMUX 1
#define PORTB_PIN1_SD_CLK 2
#define PORTB_PIN2_GPIO 0
#define PORTB_PIN2_FUNMUX 1
#define PORTB_PIN2_SD_CMD 2
#define PORTB_PIN3_GPIO 0
#define PORTB_PIN3_FUNMUX 1
#define PORTB_PIN3_SD_D0 2
#define PORTB_PIN4_GPIO 0
#define PORTB_PIN4_FUNMUX 1
#define PORTB_PIN4_SD_D1 2
#define PORTB_PIN5_GPIO 0
#define PORTB_PIN5_FUNMUX 1
#define PORTB_PIN5_SD_D2 2
#define PORTB_PIN6_GPIO 0
#define PORTB_PIN6_FUNMUX 1
#define PORTB_PIN6_SD_D3 2
#define PORTB_PIN7_GPIO 0
#define PORTB_PIN7_FUNMUX 1
#define PORTB_PIN7_SD_D4 2
#define PORTB_PIN8_GPIO 0
#define PORTB_PIN8_FUNMUX 1
#define PORTB_PIN8_SD_D5 2
#define PORTB_PIN9_GPIO 0
#define PORTB_PIN9_FUNMUX 1
#define PORTB_PIN9_SD_D6 2
#define PORTB_PIN10_GPIO 0
#define PORTB_PIN10_FUNMUX 1
#define PORTB_PIN10_SD_D7 2
#define PORTB_PIN11_GPIO 0
#define PORTB_PIN11_FUNMUX 1
#define PORTB_PIN12_GPIO 0
#define PORTC_PIN0_GPIO 0
#define PORTC_PIN0_FUNMUX 1
#define PORTC_PIN1_GPIO 0
#define PORTC_PIN1_FUNMUX 1
#define PORTC_PIN2_GPIO 0
#define PORTC_PIN2_FUNMUX 1
#define PORTC_PIN3_GPIO 0
#define PORTC_PIN3_FUNMUX 1
#define PORTC_PIN4_GPIO 0
#define PORTC_PIN4_FUNMUX 1
#define PORTC_PIN4_ADC1_IN3 3
#define PORTC_PIN5_GPIO 0
#define PORTC_PIN5_FUNMUX 1
#define PORTC_PIN5_ADC1_IN2 3
#define PORTC_PIN6_GPIO 0
#define PORTC_PIN6_FUNMUX 1
#define PORTC_PIN6_ADC1_IN1 3
#define PORTC_PIN7_GPIO 0
#define PORTC_PIN7_FUNMUX 1
#define PORTC_PIN7_ADC1_IN0 3
#define PORTM_PIN0_GPIO 0
#define PORTM_PIN0_FUNMUX 1
#define PORTM_PIN0_NORFL_D15 2
#define PORTM_PIN1_GPIO 0
#define PORTM_PIN1_FUNMUX 1
#define PORTM_PIN1_NORFL_D14 2
#define PORTM_PIN2_GPIO 0
#define PORTM_PIN2_FUNMUX 1
#define PORTM_PIN2_NORFL_D13 2
#define PORTM_PIN3_GPIO 0
#define PORTM_PIN3_FUNMUX 1
#define PORTM_PIN3_NORFL_D12 2
#define PORTM_PIN4_GPIO 0
#define PORTM_PIN4_FUNMUX 1
#define PORTM_PIN4_NORFL_D11 2
#define PORTM_PIN5_GPIO 0
#define PORTM_PIN5_FUNMUX 1
#define PORTM_PIN5_NORFL_D10 2
#define PORTM_PIN6_GPIO 0
#define PORTM_PIN6_FUNMUX 1
#define PORTM_PIN6_NORFL_D9 2
#define PORTM_PIN7_GPIO 0
#define PORTM_PIN7_FUNMUX 1
#define PORTM_PIN7_NORFL_D8 2
#define PORTM_PIN8_GPIO 0
#define PORTM_PIN8_FUNMUX 1
#define PORTM_PIN8_NORFL_D7 2
#define PORTM_PIN9_GPIO 0
#define PORTM_PIN9_FUNMUX 1
#define PORTM_PIN9_NORFL_D6 2
#define PORTM_PIN10_GPIO 0
#define PORTM_PIN10_FUNMUX 1
#define PORTM_PIN10_NORFL_D5 2
#define PORTM_PIN11_GPIO 0
#define PORTM_PIN11_FUNMUX 1
#define PORTM_PIN11_NORFL_D4 2
#define PORTM_PIN12_GPIO 0
#define PORTM_PIN12_FUNMUX 1
#define PORTM_PIN12_NORFL_D3 2
#define PORTM_PIN13_GPIO 0
#define PORTM_PIN13_FUNMUX 1
#define PORTM_PIN13_NORFL_D2 2
#define PORTM_PIN14_GPIO 0
#define PORTM_PIN14_FUNMUX 1
#define PORTM_PIN14_NORFL_D1 2
#define PORTM_PIN15_GPIO 0
#define PORTM_PIN15_FUNMUX 1
#define PORTM_PIN15_NORFL_D0 2
#define PORTM_PIN16_GPIO 0
#define PORTM_PIN16_FUNMUX 1
#define PORTM_PIN16_NORFL_OEN 2
#define PORTM_PIN17_GPIO 0
#define PORTM_PIN17_FUNMUX 1
#define PORTM_PIN17_NORFL_WEN 2
#define PORTM_PIN18_GPIO 0
#define PORTM_PIN18_FUNMUX 1
#define PORTM_PIN18_NORFL_CSN 2
#define PORTM_PIN19_GPIO 0
#define PORTM_PIN19_FUNMUX 1
#define PORTM_PIN19_SDRAM_CSN 2
#define PORTM_PIN20_GPIO 0
#define PORTM_PIN20_FUNMUX 1
#define PORTM_PIN20_SRAM_CSN 2
#define PORTM_PIN21_GPIO 0
#define PORTM_PIN21_FUNMUX 1
#define PORTM_PIN21_SDRAM_CKE 2
#define PORTN_PIN0_GPIO 0
#define PORTN_PIN0_FUNMUX 1
#define PORTN_PIN0_LCD_D0 2
#define PORTN_PIN0_ADC1_IN4 3
#define PORTN_PIN1_GPIO 0
#define PORTN_PIN1_FUNMUX 1
#define PORTN_PIN1_LCD_D1 2
#define PORTN_PIN1_ADC1_IN5 3
#define PORTN_PIN2_GPIO 0
#define PORTN_PIN2_FUNMUX 1
#define PORTN_PIN2_LCD_D2 2
#define PORTN_PIN2_ADC1_IN6 3
#define PORTN_PIN3_GPIO 0
#define PORTN_PIN3_FUNMUX 1
#define PORTN_PIN3_LCD_D3 2
#define PORTN_PIN4_GPIO 0
#define PORTN_PIN4_FUNMUX 1
#define PORTN_PIN4_LCD_D4 2
#define PORTN_PIN5_GPIO 0
#define PORTN_PIN5_FUNMUX 1
#define PORTN_PIN5_LCD_D5 2
#define PORTN_PIN6_GPIO 0
#define PORTN_PIN6_FUNMUX 1
#define PORTN_PIN6_LCD_D6 2
#define PORTN_PIN7_GPIO 0
#define PORTN_PIN7_FUNMUX 1
#define PORTN_PIN7_LCD_D7 2
#define PORTN_PIN8_GPIO 0
#define PORTN_PIN8_FUNMUX 1
#define PORTN_PIN8_LCD_D8 2
#define PORTN_PIN9_GPIO 0
#define PORTN_PIN9_FUNMUX 1
#define PORTN_PIN9_LCD_D9 2
#define PORTN_PIN10_GPIO 0
#define PORTN_PIN10_FUNMUX 1
#define PORTN_PIN10_LCD_D10 2
#define PORTN_PIN11_GPIO 0
#define PORTN_PIN11_FUNMUX 1
#define PORTN_PIN11_LCD_D11 2
#define PORTN_PIN12_GPIO 0
#define PORTN_PIN12_FUNMUX 1
#define PORTN_PIN12_LCD_D12 2
#define PORTN_PIN13_GPIO 0
#define PORTN_PIN13_FUNMUX 1
#define PORTN_PIN13_LCD_D13 2
#define PORTN_PIN14_GPIO 0
#define PORTN_PIN14_FUNMUX 1
#define PORTN_PIN14_LCD_D14 2
#define PORTN_PIN15_GPIO 0
#define PORTN_PIN15_FUNMUX 1
#define PORTN_PIN15_LCD_D15 2
#define PORTN_PIN16_GPIO 0
#define PORTN_PIN16_FUNMUX 1
#define PORTN_PIN16_LCD_RD 2
#define PORTN_PIN16_LCD_DOTCK 2
#define PORTN_PIN17_GPIO 0
#define PORTN_PIN17_FUNMUX 1
#define PORTN_PIN17_LCD_CS 2
#define PORTN_PIN17_LCD_VSYNC 2
#define PORTN_PIN18_GPIO 0
#define PORTN_PIN18_LCD_RS 2
#define PORTN_PIN18_LCD_DATEN 2 //Data Enable
#define PORTN_PIN19_GPIO 0
#define PORTN_PIN19_LCD_WR 2
#define PORTN_PIN19_LCD_HSYNC 2
#define PORTP_PIN0_GPIO 0
#define PORTP_PIN0_FUNMUX 1
#define PORTP_PIN0_NORFL_A0 2
#define PORTP_PIN1_GPIO 0
#define PORTP_PIN1_FUNMUX 1
#define PORTP_PIN1_NORFL_A1 2
#define PORTP_PIN2_GPIO 0
#define PORTP_PIN2_FUNMUX 1
#define PORTP_PIN2_NORFL_A2 2
#define PORTP_PIN2_SD_D7 3
#define PORTP_PIN3_GPIO 0
#define PORTP_PIN3_FUNMUX 1
#define PORTP_PIN3_NORFL_A3 2
#define PORTP_PIN3_SD_D6 3
#define PORTP_PIN4_GPIO 0
#define PORTP_PIN4_FUNMUX 1
#define PORTP_PIN4_NORFL_A4 2
#define PORTP_PIN4_SD_D5 3
#define PORTP_PIN5_GPIO 0
#define PORTP_PIN5_FUNMUX 1
#define PORTP_PIN5_NORFL_A5 2
#define PORTP_PIN5_SD_D4 3
#define PORTP_PIN6_GPIO 0
#define PORTP_PIN6_FUNMUX 1
#define PORTP_PIN6_NORFL_A6 2
#define PORTP_PIN6_SD_D3 3
#define PORTP_PIN7_GPIO 0
#define PORTP_PIN7_FUNMUX 1
#define PORTP_PIN7_NORFL_A7 2
#define PORTP_PIN7_SD_D2 3
#define PORTP_PIN8_GPIO 0
#define PORTP_PIN8_FUNMUX 1
#define PORTP_PIN8_NORFL_A8 2
#define PORTP_PIN8_SD_D1 3
#define PORTP_PIN9_GPIO 0
#define PORTP_PIN9_FUNMUX 1
#define PORTP_PIN9_NORFL_A9 2
#define PORTP_PIN9_SD_D0 3
#define PORTP_PIN10_GPIO 0
#define PORTP_PIN10_FUNMUX 1
#define PORTP_PIN10_NORFL_A10 2
#define PORTP_PIN10_SD_CMD 3
#define PORTP_PIN11_GPIO 0
#define PORTP_PIN11_FUNMUX 1
#define PORTP_PIN11_NORFL_A11 2
#define PORTP_PIN11_SD_CLK 3
#define PORTP_PIN12_GPIO 0
#define PORTP_PIN12_FUNMUX 1
#define PORTP_PIN12_NORFL_A12 2
#define PORTP_PIN12_SD_DETECT 3
#define PORTP_PIN13_GPIO 0
#define PORTP_PIN13_FUNMUX 1
#define PORTP_PIN13_NORFL_A13 2
#define PORTP_PIN13_SDRAM_CLK 2
#define PORTP_PIN14_GPIO 0
#define PORTP_PIN14_FUNMUX 1
#define PORTP_PIN14_NORFL_A14 2
#define PORTP_PIN14_SDRAM_CAS 2
#define PORTP_PIN15_GPIO 0
#define PORTP_PIN15_FUNMUX 1
#define PORTP_PIN15_NORFL_A15 2
#define PORTP_PIN15_SDRAM_RAS 2
#define PORTP_PIN16_GPIO 0
#define PORTP_PIN16_FUNMUX 1
#define PORTP_PIN16_NORFL_A16 2
#define PORTP_PIN16_SDRAM_LDQ 2
#define PORTP_PIN17_GPIO 0
#define PORTP_PIN17_FUNMUX 1
#define PORTP_PIN17_NORFL_A17 2
#define PORTP_PIN17_SDRAM_UDQ 2
#define PORTP_PIN18_GPIO 0
#define PORTP_PIN18_FUNMUX 1
#define PORTP_PIN18_NORFL_A18 2
#define PORTP_PIN19_GPIO 0
#define PORTP_PIN19_FUNMUX 1
#define PORTP_PIN19_NORFL_A19 2
#define PORTP_PIN20_GPIO 0
#define PORTP_PIN20_FUNMUX 1
#define PORTP_PIN20_NORFL_A20 2
#define PORTP_PIN20_SDRAM_BA0 2
#define PORTP_PIN21_GPIO 0
#define PORTP_PIN21_FUNMUX 1
#define PORTP_PIN21_NORFL_A21 2
#define PORTP_PIN21_SDRAM_BA1 2
#define PORTP_PIN22_GPIO 0
#define PORTP_PIN22_FUNMUX 1
#define PORTP_PIN22_NORFL_A22 2
#define PORTP_PIN23_GPIO 0
#define PORTP_PIN23_FUNMUX 1
#define PORTP_PIN23_NORFL_A23 2
/* 下面宏定义的取值全部在正确值的基础上“加100”以区分上面宏定义的值从而方便库函数的编写*/
/* 下面这些值是偶数编号引脚的功能取值如PIN0、PIN2、... */
#define FUNMUX0_UART0_RXD 100
#define FUNMUX0_UART1_RXD 101
#define FUNMUX0_UART2_RXD 102
#define FUNMUX0_UART3_RXD 103
#define FUNMUX0_I2C0_SCL 105
#define FUNMUX0_I2C1_SCL 106
#define FUNMUX0_PWM0A_OUT 107
#define FUNMUX0_PWM2A_OUT 108
#define FUNMUX0_PWM4A_OUT 109
#define FUNMUX0_PWM0B_OUT 110
#define FUNMUX0_PWM2B_OUT 111
#define FUNMUX0_PWM4B_OUT 112
#define FUNMUX0_PWM_BREAK 113
#define FUNMUX0_TIMR0_IN 114
#define FUNMUX0_TIMR2_IN 115
#define FUNMUX0_CAN_RX 116
#define FUNMUX0_SPI0_SSEL 117
#define FUNMUX0_SPI0_MOSI 118
#define FUNMUX0_SPI1_SSEL 119
#define FUNMUX0_SPI1_MOSI 120
#define FUNMUX0_UART0_CTS 121
#define FUNMUX0_UART1_CTS 122
#define FUNMUX0_UART2_CTS 123
#define FUNMUX0_UART3_CTS 124
/* 下面这些值是奇数编号引脚的功能取值如PIN1、PIN3、... */
#define FUNMUX1_UART0_TXD 100
#define FUNMUX1_UART1_TXD 101
#define FUNMUX1_UART2_TXD 102
#define FUNMUX1_UART3_TXD 103
#define FUNMUX1_I2C0_SDA 105
#define FUNMUX1_I2C1_SDA 106
#define FUNMUX1_PWM1A_OUT 107
#define FUNMUX1_PWM3A_OUT 108
#define FUNMUX1_PWM5A_OUT 109
#define FUNMUX1_PWM1B_OUT 110
#define FUNMUX1_PWM3B_OUT 111
#define FUNMUX1_PWM5B_OUT 112
#define FUNMUX1_PULSE_IN 113
#define FUNMUX1_TIMR1_IN 114
#define FUNMUX1_TIMR3_IN 115
#define FUNMUX1_CAN_TX 116
#define FUNMUX1_SPI0_SCLK 117
#define FUNMUX1_SPI0_MISO 118
#define FUNMUX1_SPI1_SCLK 119
#define FUNMUX1_SPI1_MISO 120
#define FUNMUX1_UART0_RTS 121
#define FUNMUX1_UART1_RTS 122
#define FUNMUX1_UART2_RTS 123
#define FUNMUX1_UART3_RTS 124
#endif //__SWM320_PORT_H__

View File

@ -1,744 +0,0 @@
/******************************************************************************************************************************************
* : SWM320_pwm.c
* : SWM320单片机的PWM功能驱动库
* : http://www.synwit.com.cn/e/tool/gbook/?bid=1
* :
* : V1.1.0 20171025
* :
*
*
*******************************************************************************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
* -ECTION WITH THEIR PRODUCTS.
*
* COPYRIGHT 2012 Synwit Technology
*******************************************************************************************************************************************/
#include "SWM320.h"
#include "SWM320_pwm.h"
/******************************************************************************************************************************************
* : PWM_Init()
* : PWM初始化
* : PWM_TypeDef * PWMx PWMPWM0PWM1PWM2PWM3PWM4PWM5
* PWM_InitStructure * initStruct PWM相关设定值的结构体
* :
* :
******************************************************************************************************************************************/
void PWM_Init(PWM_TypeDef *PWMx, PWM_InitStructure *initStruct)
{
uint32_t bit_offset = 0;
SYS->CLKEN |= (0x01 << SYS_CLKEN_PWM_Pos);
SYS->CLKDIV &= ~SYS_CLKDIV_PWM_Msk;
SYS->CLKDIV |= (initStruct->clk_div << SYS_CLKDIV_PWM_Pos);
PWM_Stop(PWMx, 1, 1); //一些关键寄存器只能在PWM停止时设置
PWMx->MODE = initStruct->mode;
PWMx->PERA = initStruct->cycleA;
PWMx->HIGHA = initStruct->hdutyA;
PWMx->DZA = initStruct->deadzoneA;
PWMx->PERB = initStruct->cycleB;
PWMx->HIGHB = initStruct->hdutyB;
PWMx->DZB = initStruct->deadzoneB;
PWMx->INIOUT &= ~(PWM_INIOUT_PWMA_Msk | PWM_INIOUT_PWMB_Msk);
PWMx->INIOUT |= (initStruct->initLevelA << PWM_INIOUT_PWMA_Pos) |
(initStruct->initLevelB << PWM_INIOUT_PWMB_Pos);
PWMG->IM = 0x00000000;
switch ((uint32_t)PWMx)
{
case ((uint32_t)PWM0):
bit_offset = 0;
break;
case ((uint32_t)PWM1):
bit_offset = 2;
break;
case ((uint32_t)PWM2):
bit_offset = 4;
break;
case ((uint32_t)PWM3):
bit_offset = 6;
break;
case ((uint32_t)PWM4):
bit_offset = 8;
break;
case ((uint32_t)PWM5):
bit_offset = 10;
break;
}
PWMG->IRS = ((0x01 << bit_offset) | (0x01 << (bit_offset + 1)) | (0x01 << (bit_offset + 12)) | (0x01 << (bit_offset + 13))); //清除中断标志
PWMG->IE &= ~((0x01 << bit_offset) | (0x01 << (bit_offset + 1)) | (0x01 << (bit_offset + 12)) | (0x01 << (bit_offset + 13)));
PWMG->IE |= (initStruct->NCycleAIEn << bit_offset) | (initStruct->NCycleBIEn << (bit_offset + 1)) |
(initStruct->HEndAIEn << (bit_offset + 12)) | (initStruct->HEndBIEn << (bit_offset + 13));
if (initStruct->NCycleAIEn | initStruct->NCycleBIEn | initStruct->HEndAIEn | initStruct->HEndBIEn)
{
NVIC_EnableIRQ(PWM_IRQn);
}
else if ((PWMG->IE & (~((0x01 << bit_offset) | (0x01 << (bit_offset + 1)) | (0x01 << (bit_offset + 12)) | (0x01 << (bit_offset + 13))))) == 0)
{
NVIC_DisableIRQ(PWM_IRQn);
}
}
/******************************************************************************************************************************************
* : PWM_Start()
* : PWMPWM输出
* : PWM_TypeDef * PWMx PWMPWM0PWM1PWM2PWM3PWM4PWM5
* uint32_t chA 0 A不启动 1 A启动
* uint32_t chB 0 B不启动 1 B启动
* :
* :
******************************************************************************************************************************************/
void PWM_Start(PWM_TypeDef *PWMx, uint32_t chA, uint32_t chB)
{
switch ((uint32_t)PWMx)
{
case ((uint32_t)PWM0):
PWMG->CHEN |= (chA << PWMG_CHEN_PWM0A_Pos) | (chB << PWMG_CHEN_PWM0B_Pos);
break;
case ((uint32_t)PWM1):
PWMG->CHEN |= (chA << PWMG_CHEN_PWM1A_Pos) | (chB << PWMG_CHEN_PWM1B_Pos);
break;
case ((uint32_t)PWM2):
PWMG->CHEN |= (chA << PWMG_CHEN_PWM2A_Pos) | (chB << PWMG_CHEN_PWM2B_Pos);
break;
case ((uint32_t)PWM3):
PWMG->CHEN |= (chA << PWMG_CHEN_PWM3A_Pos) | (chB << PWMG_CHEN_PWM3B_Pos);
break;
case ((uint32_t)PWM4):
PWMG->CHEN |= (chA << PWMG_CHEN_PWM4A_Pos) | (chB << PWMG_CHEN_PWM4B_Pos);
break;
case ((uint32_t)PWM5):
PWMG->CHEN |= (chA << PWMG_CHEN_PWM5A_Pos) | (chB << PWMG_CHEN_PWM5B_Pos);
break;
}
}
/******************************************************************************************************************************************
* : PWM_Stop()
* : PWMPWM输出
* : PWM_TypeDef * PWMx PWMPWM0PWM1PWM2PWM3PWM4PWM5
* uint32_t chA 0 A不关闭 1 A关闭
* uint32_t chB 0 B不关闭 1 B关闭
* :
* :
******************************************************************************************************************************************/
void PWM_Stop(PWM_TypeDef *PWMx, uint32_t chA, uint32_t chB)
{
switch ((uint32_t)PWMx)
{
case ((uint32_t)PWM0):
PWMG->CHEN &= ~((chA << PWMG_CHEN_PWM0A_Pos) | (chB << PWMG_CHEN_PWM0B_Pos));
break;
case ((uint32_t)PWM1):
PWMG->CHEN &= ~((chA << PWMG_CHEN_PWM1A_Pos) | (chB << PWMG_CHEN_PWM1B_Pos));
break;
case ((uint32_t)PWM2):
PWMG->CHEN &= ~((chA << PWMG_CHEN_PWM2A_Pos) | (chB << PWMG_CHEN_PWM2B_Pos));
break;
case ((uint32_t)PWM3):
PWMG->CHEN &= ~((chA << PWMG_CHEN_PWM3A_Pos) | (chB << PWMG_CHEN_PWM3B_Pos));
break;
case ((uint32_t)PWM4):
PWMG->CHEN &= ~((chA << PWMG_CHEN_PWM4A_Pos) | (chB << PWMG_CHEN_PWM4B_Pos));
break;
case ((uint32_t)PWM5):
PWMG->CHEN &= ~((chA << PWMG_CHEN_PWM5A_Pos) | (chB << PWMG_CHEN_PWM5B_Pos));
break;
}
}
/******************************************************************************************************************************************
* : PWM_SetCycle()
* :
* : PWM_TypeDef * PWMx PWMPWM0PWM1PWM2PWM3PWM4PWM5
* uint32_t chn PWM_CH_APWM_CH_B
* uint16_t cycle
* :
* :
******************************************************************************************************************************************/
void PWM_SetCycle(PWM_TypeDef *PWMx, uint32_t chn, uint16_t cycle)
{
if (chn == PWM_CH_A)
PWMx->PERA = cycle;
else if (chn == PWM_CH_B)
PWMx->PERB = cycle;
}
/******************************************************************************************************************************************
* : PWM_GetCycle()
* :
* : PWM_TypeDef * PWMx PWMPWM0PWM1PWM2PWM3PWM4PWM5
* uint32_t chn PWM_CH_APWM_CH_B
* : uint16_t
* :
******************************************************************************************************************************************/
uint16_t PWM_GetCycle(PWM_TypeDef *PWMx, uint32_t chn)
{
uint16_t cycle = 0;
if (chn == PWM_CH_A)
cycle = PWMx->PERA;
else if (chn == PWM_CH_B)
cycle = PWMx->PERB;
return cycle;
}
/******************************************************************************************************************************************
* : PWM_SetHDuty()
* :
* : PWM_TypeDef * PWMx PWMPWM0PWM1PWM2PWM3PWM4PWM5
* uint32_t chn PWM_CH_APWM_CH_B
* uint16_t hduty
* :
* :
******************************************************************************************************************************************/
void PWM_SetHDuty(PWM_TypeDef *PWMx, uint32_t chn, uint16_t hduty)
{
if (chn == PWM_CH_A)
PWMx->HIGHA = hduty;
else if (chn == PWM_CH_B)
PWMx->HIGHB = hduty;
}
/******************************************************************************************************************************************
* : PWM_GetHDuty()
* :
* : PWM_TypeDef * PWMx PWMPWM0PWM1PWM2PWM3PWM4PWM5
* uint32_t chn PWM_CH_APWM_CH_B
* : uint16_t
* :
******************************************************************************************************************************************/
uint16_t PWM_GetHDuty(PWM_TypeDef *PWMx, uint32_t chn)
{
uint16_t hduty = 0;
if (chn == PWM_CH_A)
hduty = PWMx->HIGHA;
else if (chn == PWM_CH_B)
hduty = PWMx->HIGHB;
return hduty;
}
/******************************************************************************************************************************************
* : PWM_SetDeadzone()
* :
* : PWM_TypeDef * PWMx PWMPWM0PWM1PWM2PWM3PWM4PWM5
* uint32_t chn PWM_CH_APWM_CH_B
* uint8_t deadzone
* :
* :
******************************************************************************************************************************************/
void PWM_SetDeadzone(PWM_TypeDef *PWMx, uint32_t chn, uint8_t deadzone)
{
if (chn == PWM_CH_A)
PWMx->DZA = deadzone;
else if (chn == PWM_CH_B)
PWMx->DZB = deadzone;
}
/******************************************************************************************************************************************
* : PWM_GetDeadzone()
* :
* : PWM_TypeDef * PWMx PWMPWM0PWM1PWM2PWM3PWM4PWM5
* uint32_t chn PWM_CH_APWM_CH_B
* : uint8_t
* :
******************************************************************************************************************************************/
uint8_t PWM_GetDeadzone(PWM_TypeDef *PWMx, uint32_t chn)
{
uint8_t deadzone = 0;
if (chn == PWM_CH_A)
deadzone = PWMx->DZA;
else if (chn == PWM_CH_B)
deadzone = PWMx->DZB;
return deadzone;
}
/******************************************************************************************************************************************
* : PWM_IntNCycleEn()
* : 使
* : PWM_TypeDef * PWMx PWMPWM0PWM1PWM2PWM3PWM4PWM5
* uint32_t chn PWM_CH_APWM_CH_B
* :
* :
******************************************************************************************************************************************/
void PWM_IntNCycleEn(PWM_TypeDef *PWMx, uint32_t chn)
{
switch ((uint32_t)PWMx)
{
case ((uint32_t)PWM0):
if (chn == PWM_CH_A)
PWMG->IE |= (0x01 << PWMG_IE_NEWP0A_Pos);
else
PWMG->IE |= (0x01 << PWMG_IE_NEWP0B_Pos);
break;
case ((uint32_t)PWM1):
if (chn == PWM_CH_A)
PWMG->IE |= (0x01 << PWMG_IE_NEWP1A_Pos);
else
PWMG->IE |= (0x01 << PWMG_IE_NEWP1B_Pos);
break;
case ((uint32_t)PWM2):
if (chn == PWM_CH_A)
PWMG->IE |= (0x01 << PWMG_IE_NEWP2A_Pos);
else
PWMG->IE |= (0x01 << PWMG_IE_NEWP2B_Pos);
break;
case ((uint32_t)PWM3):
if (chn == PWM_CH_A)
PWMG->IE |= (0x01 << PWMG_IE_NEWP3A_Pos);
else
PWMG->IE |= (0x01 << PWMG_IE_NEWP3B_Pos);
break;
case ((uint32_t)PWM4):
if (chn == PWM_CH_A)
PWMG->IE |= (0x01 << PWMG_IE_NEWP4A_Pos);
else
PWMG->IE |= (0x01 << PWMG_IE_NEWP4B_Pos);
break;
case ((uint32_t)PWM5):
if (chn == PWM_CH_A)
PWMG->IE |= (0x01 << PWMG_IE_NEWP5A_Pos);
else
PWMG->IE |= (0x01 << PWMG_IE_NEWP5B_Pos);
break;
}
}
/******************************************************************************************************************************************
* : PWM_IntNCycleDis()
* :
* : PWM_TypeDef * PWMx PWMPWM0PWM1PWM2PWM3PWM4PWM5
* uint32_t chn PWM_CH_APWM_CH_B
* :
* :
******************************************************************************************************************************************/
void PWM_IntNCycleDis(PWM_TypeDef *PWMx, uint32_t chn)
{
switch ((uint32_t)PWMx)
{
case ((uint32_t)PWM0):
if (chn == PWM_CH_A)
PWMG->IE &= ~(0x01 << PWMG_IE_NEWP0A_Pos);
else
PWMG->IE &= ~(0x01 << PWMG_IE_NEWP0B_Pos);
break;
case ((uint32_t)PWM1):
if (chn == PWM_CH_A)
PWMG->IE &= ~(0x01 << PWMG_IE_NEWP1A_Pos);
else
PWMG->IE &= ~(0x01 << PWMG_IE_NEWP1B_Pos);
break;
case ((uint32_t)PWM2):
if (chn == PWM_CH_A)
PWMG->IE &= ~(0x01 << PWMG_IE_NEWP2A_Pos);
else
PWMG->IE &= ~(0x01 << PWMG_IE_NEWP2B_Pos);
break;
case ((uint32_t)PWM3):
if (chn == PWM_CH_A)
PWMG->IE &= ~(0x01 << PWMG_IE_NEWP3A_Pos);
else
PWMG->IE &= ~(0x01 << PWMG_IE_NEWP3B_Pos);
break;
case ((uint32_t)PWM4):
if (chn == PWM_CH_A)
PWMG->IE &= ~(0x01 << PWMG_IE_NEWP4A_Pos);
else
PWMG->IE &= ~(0x01 << PWMG_IE_NEWP4B_Pos);
break;
case ((uint32_t)PWM5):
if (chn == PWM_CH_A)
PWMG->IE &= ~(0x01 << PWMG_IE_NEWP5A_Pos);
else
PWMG->IE &= ~(0x01 << PWMG_IE_NEWP5B_Pos);
break;
}
}
/******************************************************************************************************************************************
* : PWM_IntNCycleClr()
* :
* : PWM_TypeDef * PWMx PWMPWM0PWM1PWM2PWM3PWM4PWM5
* uint32_t chn PWM_CH_APWM_CH_B
* :
* :
******************************************************************************************************************************************/
void PWM_IntNCycleClr(PWM_TypeDef *PWMx, uint32_t chn)
{
switch ((uint32_t)PWMx)
{
case ((uint32_t)PWM0):
if (chn == PWM_CH_A)
PWMG->IRS = (0x01 << PWMG_IRS_NEWP0A_Pos);
else
PWMG->IRS = (0x01 << PWMG_IRS_NEWP0B_Pos);
break;
case ((uint32_t)PWM1):
if (chn == PWM_CH_A)
PWMG->IRS = (0x01 << PWMG_IRS_NEWP1A_Pos);
else
PWMG->IRS = (0x01 << PWMG_IRS_NEWP1B_Pos);
break;
case ((uint32_t)PWM2):
if (chn == PWM_CH_A)
PWMG->IRS = (0x01 << PWMG_IRS_NEWP2A_Pos);
else
PWMG->IRS = (0x01 << PWMG_IRS_NEWP2B_Pos);
break;
case ((uint32_t)PWM3):
if (chn == PWM_CH_A)
PWMG->IRS = (0x01 << PWMG_IRS_NEWP3A_Pos);
else
PWMG->IRS = (0x01 << PWMG_IRS_NEWP3B_Pos);
break;
case ((uint32_t)PWM4):
if (chn == PWM_CH_A)
PWMG->IRS = (0x01 << PWMG_IRS_NEWP4A_Pos);
else
PWMG->IRS = (0x01 << PWMG_IRS_NEWP4B_Pos);
break;
case ((uint32_t)PWM5):
if (chn == PWM_CH_A)
PWMG->IRS = (0x01 << PWMG_IRS_NEWP5A_Pos);
else
PWMG->IRS = (0x01 << PWMG_IRS_NEWP5B_Pos);
break;
}
}
/******************************************************************************************************************************************
* : PWM_IntNCycleStat()
* :
* : PWM_TypeDef * PWMx PWMPWM0PWM1PWM2PWM3PWM4PWM5
* uint32_t chn PWM_CH_APWM_CH_B
* : uint32_t 1 0
* :
******************************************************************************************************************************************/
uint32_t PWM_IntNCycleStat(PWM_TypeDef *PWMx, uint32_t chn)
{
uint32_t int_stat = 0;
switch ((uint32_t)PWMx)
{
case ((uint32_t)PWM0):
if (chn == PWM_CH_A)
int_stat = (PWMG->IF & PWMG_IF_NEWP0A_Msk);
else
int_stat = (PWMG->IF & PWMG_IF_NEWP0B_Msk);
break;
case ((uint32_t)PWM1):
if (chn == PWM_CH_A)
int_stat = (PWMG->IF & PWMG_IF_NEWP1A_Msk);
else
int_stat = (PWMG->IF & PWMG_IF_NEWP1B_Msk);
break;
case ((uint32_t)PWM2):
if (chn == PWM_CH_A)
int_stat = (PWMG->IF & PWMG_IF_NEWP2A_Msk);
else
int_stat = (PWMG->IF & PWMG_IF_NEWP2B_Msk);
break;
case ((uint32_t)PWM3):
if (chn == PWM_CH_A)
int_stat = (PWMG->IF & PWMG_IF_NEWP3A_Msk);
else
int_stat = (PWMG->IF & PWMG_IF_NEWP3B_Msk);
break;
case ((uint32_t)PWM4):
if (chn == PWM_CH_A)
int_stat = (PWMG->IF & PWMG_IF_NEWP4A_Msk);
else
int_stat = (PWMG->IF & PWMG_IF_NEWP4B_Msk);
break;
case ((uint32_t)PWM5):
if (chn == PWM_CH_A)
int_stat = (PWMG->IF & PWMG_IF_NEWP5A_Msk);
else
int_stat = (PWMG->IF & PWMG_IF_NEWP5B_Msk);
break;
}
return int_stat;
}
/******************************************************************************************************************************************
* : PWM_IntHEndEn()
* : 使
* : PWM_TypeDef * PWMx PWMPWM0PWM1PWM2PWM3PWM4PWM5
* uint32_t chn PWM_CH_APWM_CH_B
* :
* :
******************************************************************************************************************************************/
void PWM_IntHEndEn(PWM_TypeDef *PWMx, uint32_t chn)
{
switch ((uint32_t)PWMx)
{
case ((uint32_t)PWM0):
if (chn == PWM_CH_A)
PWMG->IE |= (0x01 << PWMG_IE_HEND0A_Pos);
else
PWMG->IE |= (0x01 << PWMG_IE_HEND0B_Pos);
break;
case ((uint32_t)PWM1):
if (chn == PWM_CH_A)
PWMG->IE |= (0x01 << PWMG_IE_HEND1A_Pos);
else
PWMG->IE |= (0x01 << PWMG_IE_HEND1B_Pos);
break;
case ((uint32_t)PWM2):
if (chn == PWM_CH_A)
PWMG->IE |= (0x01 << PWMG_IE_HEND2A_Pos);
else
PWMG->IE |= (0x01 << PWMG_IE_HEND2B_Pos);
break;
case ((uint32_t)PWM3):
if (chn == PWM_CH_A)
PWMG->IE |= (0x01 << PWMG_IE_HEND3A_Pos);
else
PWMG->IE |= (0x01 << PWMG_IE_HEND3B_Pos);
break;
case ((uint32_t)PWM4):
if (chn == PWM_CH_A)
PWMG->IE |= (0x01 << PWMG_IE_HEND4A_Pos);
else
PWMG->IE |= (0x01 << PWMG_IE_HEND4B_Pos);
break;
case ((uint32_t)PWM5):
if (chn == PWM_CH_A)
PWMG->IE |= (0x01 << PWMG_IE_HEND5A_Pos);
else
PWMG->IE |= (0x01 << PWMG_IE_HEND5B_Pos);
break;
}
}
/******************************************************************************************************************************************
* : PWM_IntHEndDis()
* :
* : PWM_TypeDef * PWMx PWMPWM0PWM1PWM2PWM3PWM4PWM5
* uint32_t chn PWM_CH_APWM_CH_B
* :
* :
******************************************************************************************************************************************/
void PWM_IntHEndDis(PWM_TypeDef *PWMx, uint32_t chn)
{
switch ((uint32_t)PWMx)
{
case ((uint32_t)PWM0):
if (chn == PWM_CH_A)
PWMG->IE &= ~(0x01 << PWMG_IE_HEND0A_Pos);
else
PWMG->IE &= ~(0x01 << PWMG_IE_HEND0B_Pos);
break;
case ((uint32_t)PWM1):
if (chn == PWM_CH_A)
PWMG->IE &= ~(0x01 << PWMG_IE_HEND1A_Pos);
else
PWMG->IE &= ~(0x01 << PWMG_IE_HEND1B_Pos);
break;
case ((uint32_t)PWM2):
if (chn == PWM_CH_A)
PWMG->IE &= ~(0x01 << PWMG_IE_HEND2A_Pos);
else
PWMG->IE &= ~(0x01 << PWMG_IE_HEND2B_Pos);
break;
case ((uint32_t)PWM3):
if (chn == PWM_CH_A)
PWMG->IE &= ~(0x01 << PWMG_IE_HEND3A_Pos);
else
PWMG->IE &= ~(0x01 << PWMG_IE_HEND3B_Pos);
break;
case ((uint32_t)PWM4):
if (chn == PWM_CH_A)
PWMG->IE &= ~(0x01 << PWMG_IE_HEND4A_Pos);
else
PWMG->IE &= ~(0x01 << PWMG_IE_HEND4B_Pos);
break;
case ((uint32_t)PWM5):
if (chn == PWM_CH_A)
PWMG->IE &= ~(0x01 << PWMG_IE_HEND5A_Pos);
else
PWMG->IE &= ~(0x01 << PWMG_IE_HEND5B_Pos);
break;
}
}
/******************************************************************************************************************************************
* : PWM_IntHEndClr()
* :
* : PWM_TypeDef * PWMx PWMPWM0PWM1PWM2PWM3PWM4PWM5
* uint32_t chn PWM_CH_APWM_CH_B
* :
* :
******************************************************************************************************************************************/
void PWM_IntHEndClr(PWM_TypeDef *PWMx, uint32_t chn)
{
switch ((uint32_t)PWMx)
{
case ((uint32_t)PWM0):
if (chn == PWM_CH_A)
PWMG->IRS = (0x01 << PWMG_IRS_HEND0A_Pos);
else
PWMG->IRS = (0x01 << PWMG_IRS_HEND0B_Pos);
break;
case ((uint32_t)PWM1):
if (chn == PWM_CH_A)
PWMG->IRS = (0x01 << PWMG_IRS_HEND1A_Pos);
else
PWMG->IRS = (0x01 << PWMG_IRS_HEND1B_Pos);
break;
case ((uint32_t)PWM2):
if (chn == PWM_CH_A)
PWMG->IRS = (0x01 << PWMG_IRS_HEND2A_Pos);
else
PWMG->IRS = (0x01 << PWMG_IRS_HEND2B_Pos);
break;
case ((uint32_t)PWM3):
if (chn == PWM_CH_A)
PWMG->IRS = (0x01 << PWMG_IRS_HEND3A_Pos);
else
PWMG->IRS = (0x01 << PWMG_IRS_HEND3B_Pos);
break;
case ((uint32_t)PWM4):
if (chn == PWM_CH_A)
PWMG->IRS = (0x01 << PWMG_IRS_HEND4A_Pos);
else
PWMG->IRS = (0x01 << PWMG_IRS_HEND4B_Pos);
break;
case ((uint32_t)PWM5):
if (chn == PWM_CH_A)
PWMG->IRS = (0x01 << PWMG_IRS_HEND5A_Pos);
else
PWMG->IRS = (0x01 << PWMG_IRS_HEND5B_Pos);
break;
}
}
/******************************************************************************************************************************************
* : PWM_IntHEndStat()
* :
* : PWM_TypeDef * PWMx PWMPWM0PWM1PWM2PWM3PWM4PWM5
* uint32_t chn PWM_CH_APWM_CH_B
* : uint32_t 1 0
* :
******************************************************************************************************************************************/
uint32_t PWM_IntHEndStat(PWM_TypeDef *PWMx, uint32_t chn)
{
uint32_t int_stat = 0;
switch ((uint32_t)PWMx)
{
case ((uint32_t)PWM0):
if (chn == PWM_CH_A)
int_stat = (PWMG->IF & PWMG_IF_HEND0A_Msk);
else
int_stat = (PWMG->IF & PWMG_IF_HEND0B_Msk);
break;
case ((uint32_t)PWM1):
if (chn == PWM_CH_A)
int_stat = (PWMG->IF & PWMG_IF_HEND1A_Msk);
else
int_stat = (PWMG->IF & PWMG_IF_HEND1B_Msk);
break;
case ((uint32_t)PWM2):
if (chn == PWM_CH_A)
int_stat = (PWMG->IF & PWMG_IF_HEND2A_Msk);
else
int_stat = (PWMG->IF & PWMG_IF_HEND2B_Msk);
break;
case ((uint32_t)PWM3):
if (chn == PWM_CH_A)
int_stat = (PWMG->IF & PWMG_IF_HEND3A_Msk);
else
int_stat = (PWMG->IF & PWMG_IF_HEND3B_Msk);
break;
case ((uint32_t)PWM4):
if (chn == PWM_CH_A)
int_stat = (PWMG->IF & PWMG_IF_HEND4A_Msk);
else
int_stat = (PWMG->IF & PWMG_IF_HEND4B_Msk);
break;
case ((uint32_t)PWM5):
if (chn == PWM_CH_A)
int_stat = (PWMG->IF & PWMG_IF_HEND5A_Msk);
else
int_stat = (PWMG->IF & PWMG_IF_HEND5B_Msk);
break;
}
return int_stat;
}

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@ -1,57 +0,0 @@
#ifndef __SWM320_PWM_H__
#define __SWM320_PWM_H__
typedef struct
{
uint8_t clk_div; //PWM_CLKDIV_1、PWM_CLKDIV_8
uint8_t mode; //PWM_MODE_INDEP、PWM_MODE_COMPL、PWM_MODE_INDEP_CALIGN、PWM_MODE_COMPL_CALIGN
uint16_t cycleA; //A路周期
uint16_t hdutyA; //A路占空比
uint16_t deadzoneA; //A路死区时长取值0--1023
uint8_t initLevelA; //A路初始输出电平0 低电平 1 高电平
uint16_t cycleB; //B路周期
uint16_t hdutyB; //B路占空比
uint16_t deadzoneB; //B路死区时长取值0--1023
uint8_t initLevelB; //B路初始输出电平0 低电平 1 高电平
uint8_t HEndAIEn; //A路高电平结束中断使能
uint8_t NCycleAIEn; //A路新周期开始中断使能
uint8_t HEndBIEn; //B路高电平结束中断使能
uint8_t NCycleBIEn; //B路新周期开始中断使能
} PWM_InitStructure;
#define PWM_CLKDIV_1 0
#define PWM_CLKDIV_8 1
#define PWM_MODE_INDEP 0 //A路和B路为两路独立输出
#define PWM_MODE_COMPL 1 //A路和B路为一路互补输出
#define PWM_MODE_INDEP_CALIGN 3 //A路和B路为两路独立输出中心对齐
#define PWM_MODE_COMPL_CALIGN 4 //A路和B路为一路互补输出中心对齐
#define PWM_CH_A 0
#define PWM_CH_B 1
void PWM_Init(PWM_TypeDef *PWMx, PWM_InitStructure *initStruct); //PWM初始化
void PWM_Start(PWM_TypeDef *PWMx, uint32_t chA, uint32_t chB); //启动PWM开始PWM输出
void PWM_Stop(PWM_TypeDef *PWMx, uint32_t chA, uint32_t chB); //关闭PWM停止PWM输出
void PWM_SetCycle(PWM_TypeDef *PWMx, uint32_t chn, uint16_t cycle); //设置周期
uint16_t PWM_GetCycle(PWM_TypeDef *PWMx, uint32_t chn); //获取周期
void PWM_SetHDuty(PWM_TypeDef *PWMx, uint32_t chn, uint16_t hduty); //设置高电平时长
uint16_t PWM_GetHDuty(PWM_TypeDef *PWMx, uint32_t chn); //获取高电平时长
void PWM_SetDeadzone(PWM_TypeDef *PWMx, uint32_t chn, uint8_t deadzone); //设置死区时长
uint8_t PWM_GetDeadzone(PWM_TypeDef *PWMx, uint32_t chn); //获取死区时长
void PWM_IntNCycleEn(PWM_TypeDef *PWMx, uint32_t chn); //新周期开始中断使能
void PWM_IntNCycleDis(PWM_TypeDef *PWMx, uint32_t chn); //新周期开始中断禁能
void PWM_IntNCycleClr(PWM_TypeDef *PWMx, uint32_t chn); //新周期开始中断标志清除
uint32_t PWM_IntNCycleStat(PWM_TypeDef *PWMx, uint32_t chn); //新周期开始中断是否发生
void PWM_IntHEndEn(PWM_TypeDef *PWMx, uint32_t chn); //高电平结束中断使能
void PWM_IntHEndDis(PWM_TypeDef *PWMx, uint32_t chn); //高电平结束中断禁能
void PWM_IntHEndClr(PWM_TypeDef *PWMx, uint32_t chn); //高电平结束中断标志清除
uint32_t PWM_IntHEndStat(PWM_TypeDef *PWMx, uint32_t chn); //高电平结束中断是否发生
#endif //__SWM320_PWM_H__

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@ -1,419 +0,0 @@
/******************************************************************************************************************************************
* : SWM320_rtc.c
* : SWM320单片机的RTC驱动库
* : http://www.synwit.com.cn/e/tool/gbook/?bid=1
* :
* : V1.1.0 20171025
* :
*
*
*******************************************************************************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
* -ECTION WITH THEIR PRODUCTS.
*
* COPYRIGHT 2012 Synwit Technology
*******************************************************************************************************************************************/
#include "SWM320.h"
#include "SWM320_rtc.h"
static uint32_t calcWeekDay(uint32_t year, uint32_t month, uint32_t date);
/******************************************************************************************************************************************
* : RTC_Init()
* : RTC初始化
* : RTC_TypeDef * RTCx RTCRTC
* RTC_InitStructure * initStruct RTC相关设定值的结构体
* :
* :
******************************************************************************************************************************************/
void RTC_Init(RTC_TypeDef *RTCx, RTC_InitStructure *initStruct)
{
SYS->CLKEN |= (1 << SYS_CLKEN_RTCBKP_Pos);
SYS->LRCCR &= ~(1 << SYS_LRCCR_OFF_Pos); //RTC使用32KHz RC时钟
SYS->CLKEN |= (1 << SYS_CLKEN_RTC_Pos) |
((uint32_t)1 << SYS_CLKEN_ALIVE_Pos);
RTC_Stop(RTCx);
while (RTCx->CFGABLE == 0)
;
RTCx->MINSEC = (initStruct->Second << RTC_MINSEC_SEC_Pos) |
(initStruct->Minute << RTC_MINSEC_MIN_Pos);
RTCx->DATHUR = (initStruct->Hour << RTC_DATHUR_HOUR_Pos) |
(initStruct->Date << RTC_DATHUR_DATE_Pos);
RTCx->MONDAY = (calcWeekDay(initStruct->Year, initStruct->Month, initStruct->Date) << RTC_MONDAY_DAY_Pos) |
(initStruct->Month << RTC_MONDAY_MON_Pos);
RTCx->YEAR = initStruct->Year;
RTCx->LOAD = 1 << RTC_LOAD_TIME_Pos;
RTCx->IF = 0x1F;
RTCx->IE = (initStruct->SecondIEn << RTC_IE_SEC_Pos) |
(initStruct->MinuteIEn << RTC_IE_MIN_Pos);
if (initStruct->SecondIEn | initStruct->MinuteIEn)
{
NVIC_EnableIRQ(RTC_IRQn);
}
else
{
NVIC_DisableIRQ(RTC_IRQn);
}
}
/******************************************************************************************************************************************
* : RTC_Start()
* : RTC
* : RTC_TypeDef * RTCx RTCRTC
* :
* :
******************************************************************************************************************************************/
void RTC_Start(RTC_TypeDef *RTCx)
{
RTCx->EN = 1;
}
/******************************************************************************************************************************************
* : RTC_Stop()
* : RTC
* : RTC_TypeDef * RTCx RTCRTC
* :
* :
******************************************************************************************************************************************/
void RTC_Stop(RTC_TypeDef *RTCx)
{
RTCx->EN = 0;
}
/******************************************************************************************************************************************
* : RTC_GetDateTime()
* :
* : RTC_TypeDef * RTCx RTCRTC
* RTC_DateTime * dateTime
* :
* :
******************************************************************************************************************************************/
void RTC_GetDateTime(RTC_TypeDef *RTCx, RTC_DateTime *dateTime)
{
dateTime->Year = RTCx->YEAR;
dateTime->Month = (RTCx->MONDAY & RTC_MONDAY_MON_Msk) >> RTC_MONDAY_MON_Pos;
dateTime->Date = (RTCx->DATHUR & RTC_DATHUR_DATE_Msk) >> RTC_DATHUR_DATE_Pos;
dateTime->Day = 1 << ((RTCx->MONDAY & RTC_MONDAY_DAY_Msk) >> RTC_MONDAY_DAY_Pos);
dateTime->Hour = (RTCx->DATHUR & RTC_DATHUR_HOUR_Msk) >> RTC_DATHUR_HOUR_Pos;
dateTime->Minute = (RTCx->MINSEC & RTC_MINSEC_MIN_Msk) >> RTC_MINSEC_MIN_Pos;
dateTime->Second = (RTCx->MINSEC & RTC_MINSEC_SEC_Msk) >> RTC_MINSEC_SEC_Pos;
}
/******************************************************************************************************************************************
* : RTC_AlarmSetup()
* : RTC闹钟设定
* : RTC_TypeDef * RTCx RTCRTC
* RTC_AlarmStructure * alarmStruct RTC闹钟设定值的结构体
* :
* :
******************************************************************************************************************************************/
void RTC_AlarmSetup(RTC_TypeDef *RTCx, RTC_AlarmStructure *alarmStruct)
{
while (RTCx->CFGABLE == 0)
;
RTCx->MINSECAL = (alarmStruct->Second << RTC_MINSECAL_SEC_Pos) |
(alarmStruct->Minute << RTC_MINSECAL_MIN_Pos);
RTCx->DAYHURAL = (alarmStruct->Hour << RTC_DAYHURAL_HOUR_Pos) |
(alarmStruct->Days << RTC_DAYHURAL_SUN_Pos);
RTCx->LOAD = 1 << RTC_LOAD_ALARM_Pos;
while (RTCx->LOAD & RTC_LOAD_ALARM_Msk)
;
RTCx->IF = (1 << RTC_IF_ALARM_Pos);
RTCx->IE &= ~RTC_IE_ALARM_Msk;
RTCx->IE |= (alarmStruct->AlarmIEn << RTC_IE_ALARM_Pos);
if (alarmStruct->AlarmIEn)
NVIC_EnableIRQ(RTC_IRQn);
}
/******************************************************************************************************************************************
* : calcWeekDay()
* :
* : uint32_t year
* uint32_t month
* uint32_t date
* : uint32_t 0 1 ... ... 6
* :
******************************************************************************************************************************************/
static uint32_t calcWeekDay(uint32_t year, uint32_t month, uint32_t date)
{
uint32_t i, cnt = 0;
const uint32_t daysOfMonth[13] = {0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31};
for (i = 1; i < month; i++)
cnt += daysOfMonth[i];
cnt += date;
if ((year % 4 == 0) && ((year % 100 != 0) || (year % 400 == 0)) && (month >= 3))
cnt += 1;
cnt += (year - 1901) * 365;
for (i = 1901; i < year; i++)
{
if ((i % 4 == 0) && ((i % 100 != 0) || (i % 400 == 0)))
cnt += 1;
}
return (cnt + 1) % 7;
}
/******************************************************************************************************************************************
* : RTC_IntSecondEn()
* : 使
* : RTC_TypeDef * RTCx RTCRTC
* :
* :
******************************************************************************************************************************************/
void RTC_IntSecondEn(RTC_TypeDef *RTCx)
{
RTCx->IE |= (1 << RTC_IE_SEC_Pos);
}
/******************************************************************************************************************************************
* : RTC_IntSecondDis()
* :
* : RTC_TypeDef * RTCx RTCRTC
* :
* :
******************************************************************************************************************************************/
void RTC_IntSecondDis(RTC_TypeDef *RTCx)
{
RTCx->IE &= ~(1 << RTC_IE_SEC_Pos);
}
/******************************************************************************************************************************************
* : RTC_IntSecondClr()
* :
* : RTC_TypeDef * RTCx RTCRTC
* :
* :
******************************************************************************************************************************************/
void RTC_IntSecondClr(RTC_TypeDef *RTCx)
{
RTCx->IF = (1 << RTC_IF_SEC_Pos);
}
/******************************************************************************************************************************************
* : RTC_IntSecondStat()
* :
* : RTC_TypeDef * RTCx RTCRTC
* : uint32_t 1 0
* :
******************************************************************************************************************************************/
uint32_t RTC_IntSecondStat(RTC_TypeDef *RTCx)
{
return (RTCx->IF & RTC_IF_SEC_Msk) ? 1 : 0;
}
/******************************************************************************************************************************************
* : RTC_IntMinuteEn()
* : 使
* : RTC_TypeDef * RTCx RTCRTC
* :
* :
******************************************************************************************************************************************/
void RTC_IntMinuteEn(RTC_TypeDef *RTCx)
{
RTCx->IE |= (1 << RTC_IE_MIN_Pos);
}
/******************************************************************************************************************************************
* : RTC_IntMinuteDis()
* :
* : RTC_TypeDef * RTCx RTCRTC
* :
* :
******************************************************************************************************************************************/
void RTC_IntMinuteDis(RTC_TypeDef *RTCx)
{
RTCx->IE &= ~(1 << RTC_IE_MIN_Pos);
}
/******************************************************************************************************************************************
* : RTC_IntMinuteClr()
* :
* : RTC_TypeDef * RTCx RTCRTC
* :
* :
******************************************************************************************************************************************/
void RTC_IntMinuteClr(RTC_TypeDef *RTCx)
{
RTCx->IF = (1 << RTC_IF_MIN_Pos);
}
/******************************************************************************************************************************************
* : RTC_IntMinuteStat()
* :
* : RTC_TypeDef * RTCx RTCRTC
* : uint32_t 1 0
* :
******************************************************************************************************************************************/
uint32_t RTC_IntMinuteStat(RTC_TypeDef *RTCx)
{
return (RTCx->IF & RTC_IF_MIN_Msk) ? 1 : 0;
}
/******************************************************************************************************************************************
* : RTC_IntHourEn()
* : 使
* : RTC_TypeDef * RTCx RTCRTC
* :
* :
******************************************************************************************************************************************/
void RTC_IntHourEn(RTC_TypeDef *RTCx)
{
RTCx->IE |= (1 << RTC_IE_HOUR_Pos);
}
/******************************************************************************************************************************************
* : RTC_IntHourDis()
* :
* : RTC_TypeDef * RTCx RTCRTC
* :
* :
******************************************************************************************************************************************/
void RTC_IntHourDis(RTC_TypeDef *RTCx)
{
RTCx->IE &= ~(1 << RTC_IE_HOUR_Pos);
}
/******************************************************************************************************************************************
* : RTC_IntHourClr()
* :
* : RTC_TypeDef * RTCx RTCRTC
* :
* :
******************************************************************************************************************************************/
void RTC_IntHourClr(RTC_TypeDef *RTCx)
{
RTCx->IF = (1 << RTC_IF_HOUR_Pos);
}
/******************************************************************************************************************************************
* : RTC_IntHourStat()
* :
* : RTC_TypeDef * RTCx RTCRTC
* : uint32_t 1 0
* :
******************************************************************************************************************************************/
uint32_t RTC_IntHourStat(RTC_TypeDef *RTCx)
{
return (RTCx->IF & RTC_IF_HOUR_Msk) ? 1 : 0;
}
/******************************************************************************************************************************************
* : RTC_IntDateEn()
* : 使
* : RTC_TypeDef * RTCx RTCRTC
* :
* :
******************************************************************************************************************************************/
void RTC_IntDateEn(RTC_TypeDef *RTCx)
{
RTCx->IE |= (1 << RTC_IE_DATE_Pos);
}
/******************************************************************************************************************************************
* : RTC_IntDateDis()
* :
* : RTC_TypeDef * RTCx RTCRTC
* :
* :
******************************************************************************************************************************************/
void RTC_IntDateDis(RTC_TypeDef *RTCx)
{
RTCx->IE &= ~(1 << RTC_IE_DATE_Pos);
}
/******************************************************************************************************************************************
* : RTC_IntDateClr()
* :
* : RTC_TypeDef * RTCx RTCRTC
* :
* :
******************************************************************************************************************************************/
void RTC_IntDateClr(RTC_TypeDef *RTCx)
{
RTCx->IF = (1 << RTC_IF_DATE_Pos);
}
/******************************************************************************************************************************************
* : RTC_IntDateStat()
* :
* : RTC_TypeDef * RTCx RTCRTC
* : uint32_t 1 0
* :
******************************************************************************************************************************************/
uint32_t RTC_IntDateStat(RTC_TypeDef *RTCx)
{
return (RTCx->IF & RTC_IF_DATE_Msk) ? 1 : 0;
}
/******************************************************************************************************************************************
* : RTC_IntAlarmEn()
* : 使
* : RTC_TypeDef * RTCx RTCRTC
* :
* :
******************************************************************************************************************************************/
void RTC_IntAlarmEn(RTC_TypeDef *RTCx)
{
RTCx->IE |= (1 << RTC_IE_ALARM_Pos);
}
/******************************************************************************************************************************************
* : RTC_IntAlarmDis()
* :
* : RTC_TypeDef * RTCx RTCRTC
* :
* :
******************************************************************************************************************************************/
void RTC_IntAlarmDis(RTC_TypeDef *RTCx)
{
RTCx->IE &= ~(1 << RTC_IE_ALARM_Pos);
}
/******************************************************************************************************************************************
* : RTC_IntAlarmClr()
* :
* : RTC_TypeDef * RTCx RTCRTC
* :
* :
******************************************************************************************************************************************/
void RTC_IntAlarmClr(RTC_TypeDef *RTCx)
{
RTCx->IF = (1 << RTC_IF_ALARM_Pos);
}
/******************************************************************************************************************************************
* : RTC_IntAlarmStat()
* :
* : RTC_TypeDef * RTCx RTCRTC
* : uint32_t 1 0
* :
******************************************************************************************************************************************/
uint32_t RTC_IntAlarmStat(RTC_TypeDef *RTCx)
{
return (RTCx->IF & RTC_IF_ALARM_Msk) ? 1 : 0;
}

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@ -1,73 +0,0 @@
#ifndef __SWM320_RTC_H__
#define __SWM320_RTC_H__
#define RTC_SUN 0x01
#define RTC_MON 0x02
#define RTC_TUE 0x04
#define RTC_WED 0x08
#define RTC_THU 0x10
#define RTC_FRI 0x20
#define RTC_SAT 0x40
typedef struct
{
uint16_t Year;
uint8_t Month; //取值1--12
uint8_t Date; //取值1--31
uint8_t Hour; //取值0--23
uint8_t Minute; //取值0--59
uint8_t Second; //取值0--59
uint8_t SecondIEn;
uint8_t MinuteIEn;
} RTC_InitStructure;
typedef struct
{
uint8_t Days; //RTC_SUN、RTC_MON、RTC_TUE、RTC_WED、RTC_THU、RTC_FRI、RTC_SAT及其或运算组合
uint8_t Hour;
uint8_t Minute;
uint8_t Second;
uint8_t AlarmIEn;
} RTC_AlarmStructure;
typedef struct
{
uint16_t Year;
uint8_t Month;
uint8_t Date;
uint8_t Day; //RTC_SUN、RTC_MON、RTC_TUE、RTC_WED、RTC_THU、RTC_FRI、RTC_SAT
uint8_t Hour;
uint8_t Minute;
uint8_t Second;
} RTC_DateTime;
void RTC_Init(RTC_TypeDef *RTCx, RTC_InitStructure *initStruct);
void RTC_Start(RTC_TypeDef *RTCx);
void RTC_Stop(RTC_TypeDef *RTCx);
void RTC_GetDateTime(RTC_TypeDef *RTCx, RTC_DateTime *dateTime);
void RTC_AlarmSetup(RTC_TypeDef *RTCx, RTC_AlarmStructure *alarmStruct);
void RTC_IntSecondEn(RTC_TypeDef *RTCx);
void RTC_IntSecondDis(RTC_TypeDef *RTCx);
void RTC_IntSecondClr(RTC_TypeDef *RTCx);
uint32_t RTC_IntSecondStat(RTC_TypeDef *RTCx);
void RTC_IntMinuteEn(RTC_TypeDef *RTCx);
void RTC_IntMinuteDis(RTC_TypeDef *RTCx);
void RTC_IntMinuteClr(RTC_TypeDef *RTCx);
uint32_t RTC_IntMinuteStat(RTC_TypeDef *RTCx);
void RTC_IntHourEn(RTC_TypeDef *RTCx);
void RTC_IntHourDis(RTC_TypeDef *RTCx);
void RTC_IntHourClr(RTC_TypeDef *RTCx);
uint32_t RTC_IntHourStat(RTC_TypeDef *RTCx);
void RTC_IntDateEn(RTC_TypeDef *RTCx);
void RTC_IntDateDis(RTC_TypeDef *RTCx);
void RTC_IntDateClr(RTC_TypeDef *RTCx);
uint32_t RTC_IntDateStat(RTC_TypeDef *RTCx);
void RTC_IntAlarmEn(RTC_TypeDef *RTCx);
void RTC_IntAlarmDis(RTC_TypeDef *RTCx);
void RTC_IntAlarmClr(RTC_TypeDef *RTCx);
uint32_t RTC_IntAlarmStat(RTC_TypeDef *RTCx);
#endif //__SWM320_RTC_H__

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@ -1,626 +0,0 @@
/******************************************************************************************************************************************
* : SWM320_sdio.c
* : SWM320单片机的SDIO接口驱动库
* : http://www.synwit.com.cn/e/tool/gbook/?bid=1
* : 512
* : V1.1.0 20171025
* :
*
*
*******************************************************************************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
* -ECTION WITH THEIR PRODUCTS.
*
* COPYRIGHT 2012 Synwit Technology
*******************************************************************************************************************************************/
#include "SWM320.h"
#include "SWM320_sdio.h"
SD_CardInfo SD_cardInfo;
/******************************************************************************************************************************************
* : SDIO_Init()
* : SDIO读写SD卡初始化4线512
* : uint32_t freq SDIO_CLK时钟频率
* : uint32_t SD_RES_OK SD_RES_ERR SD_RES_TIMEOUT
* :
******************************************************************************************************************************************/
uint32_t SDIO_Init(uint32_t freq)
{
uint32_t res;
uint32_t resp, resps[4];
SYS->CLKDIV &= ~SYS_CLKDIV_SDIO_Msk;
if (SystemCoreClock > 80000000) //SDIO时钟需要小于52MHz
SYS->CLKDIV |= (2 << SYS_CLKDIV_SDIO_Pos); //SDCLK = SYSCLK / 4
else
SYS->CLKDIV |= (1 << SYS_CLKDIV_SDIO_Pos); //SDCLK = SYSCLK / 2
SYS->CLKEN |= (0x01 << SYS_CLKEN_SDIO_Pos);
SDIO->CR2 = (1 << SDIO_CR2_RSTALL_Pos);
SDIO->CR1 = (1 << SDIO_CR1_CDSRC_Pos) |
(0 << SDIO_CR1_8BIT_Pos) |
(0 << SDIO_CR1_4BIT_Pos) |
(1 << SDIO_CR1_PWRON_Pos) |
(7 << SDIO_CR1_VOLT_Pos);
SDIO->CR2 = (1 << SDIO_CR2_CLKEN_Pos) |
(1 << SDIO_CR2_SDCLKEN_Pos) |
(calcSDCLKDiv(100000) << SDIO_CR2_SDCLKDIV_Pos) |
(0xC << SDIO_CR2_TIMEOUT_Pos); // 2**25 SDIO_CLK
while ((SDIO->CR2 & SDIO_CR2_CLKRDY_Msk) == 0)
;
SDIO->IFE = 0xFFFFFFFF;
SDIO_SendCmd(SD_CMD_GO_IDLE_STATE, 0x00, SD_RESP_NO, 0); //CMD0: GO_IDLE_STATE
res = SDIO_SendCmd(SD_CMD_SEND_IF_COND, 0x1AA, SD_RESP_32b, &resp); //CMD8: SEND_IF_COND, 检测工作电压、检测是否支持SD 2.0
if (res != SD_RES_OK)
return res;
if (resp == 0x1AA)
SD_cardInfo.CardType = SDIO_STD_CAPACITY_SD_CARD_V2_0;
else
SD_cardInfo.CardType = SDIO_STD_CAPACITY_SD_CARD_V1_1;
do //ACMD41: SD_CMD_SD_APP_OP_COND
{
res = SDIO_SendCmd(SD_CMD_APP_CMD, 0x00, SD_RESP_32b, &resp);
if (res != SD_RES_OK)
return res;
if (resp != 0x120)
return SD_RES_ERR; //不是SD卡可能是MMC卡
if (SD_cardInfo.CardType == SDIO_STD_CAPACITY_SD_CARD_V2_0)
SDIO_SendCmd(SD_CMD_SD_APP_OP_COND, 0x80100000 | 0x40000000, SD_RESP_32b, &resp);
else
SDIO_SendCmd(SD_CMD_SD_APP_OP_COND, 0x80100000 | 0x00000000, SD_RESP_32b, &resp);
} while (((resp >> 31) & 0x01) == 0); //上电没完成时resp[31] == 0
if (((resp >> 30) & 0x01) == 1)
SD_cardInfo.CardType = SDIO_HIGH_CAPACITY_SD_CARD;
SDIO_SendCmd(SD_CMD_ALL_SEND_CID, 0x00, SD_RESP_128b, resps); //CMD2: SD_CMD_ALL_SEND_CID获取CID
parseCID(resps);
SDIO_SendCmd(SD_CMD_SET_REL_ADDR, 0x00, SD_RESP_32b, &resp); //CMD3: SD_CMD_SET_REL_ADDR设置RCA
SD_cardInfo.RCA = resp >> 16;
SDIO_SendCmd(SD_CMD_SEND_CSD, SD_cardInfo.RCA << 16, SD_RESP_128b, resps); //CMD9: SD_CMD_SEND_CSD获取CSD
parseCSD(resps);
if (SD_cardInfo.CardBlockSize < 0x200)
return SD_RES_ERR; //本驱动只支持以512字节为单位的读写所以最大读写单位必须不小于512
SDIO->CR2 &= ~(SDIO_CR2_SDCLKEN_Msk | SDIO_CR2_SDCLKDIV_Msk);
SDIO->CR2 |= (1 << SDIO_CR2_SDCLKEN_Pos) |
(calcSDCLKDiv(freq) << SDIO_CR2_SDCLKDIV_Pos); //初始化完成SDCLK切换到高速
SDIO_SendCmd(SD_CMD_SEL_DESEL_CARD, SD_cardInfo.RCA << 16, SD_RESP_32b_busy, &resp); //CMD7: 选中卡从Standy模式进入Transfer模式
SDIO->IF = SDIO_IF_TRXDONE_Msk;
SDIO_SendCmd(SD_CMD_APP_CMD, SD_cardInfo.RCA << 16, SD_RESP_32b, &resp);
SDIO_SendCmd(SD_CMD_APP_SD_SET_BUSWIDTH, SD_BUSWIDTH_4b, SD_RESP_32b, &resp); //切换成4位总线模式
SDIO->CR1 |= (1 << SDIO_CR1_4BIT_Pos);
SDIO_SendCmd(SD_CMD_SET_BLOCKLEN, 512, SD_RESP_32b, &resp); //固定块大小位512字节
SDIO->BLK = 512;
return SD_RES_OK;
}
/******************************************************************************************************************************************
* : SDIO_BlockWrite()
* : SD卡写入数据
* : uint32_t block_addr SD卡块地址512
* uint32_t buff[]
* : uint32_t SD_RES_OK SD_RES_ERR SD_RES_TIMEOUT
* :
******************************************************************************************************************************************/
uint32_t SDIO_BlockWrite(uint32_t block_addr, uint32_t buff[])
{
uint32_t res, i;
uint32_t addr, resp;
if (SD_cardInfo.CardType == SDIO_HIGH_CAPACITY_SD_CARD)
addr = block_addr;
else
addr = block_addr * 512;
res = SDIO_SendCmdWithData(SD_CMD_WRITE_SINGLE_BLOCK, addr, SD_RESP_32b, &resp, 0, 1);
if (res != SD_RES_OK)
return res;
while ((SDIO->IF & SDIO_IF_BUFWRRDY_Msk) == 0)
__NOP();
SDIO->IF = SDIO_IF_BUFWRRDY_Msk;
for (i = 0; i < 512 / 4; i++)
SDIO->DATA = buff[i];
while ((SDIO->IF & SDIO_IF_TRXDONE_Msk) == 0)
__NOP();
SDIO->IF = SDIO_IF_TRXDONE_Msk;
return SD_RES_OK;
}
/******************************************************************************************************************************************
* : SDIO_MultiBlockWrite()
* : SD卡写入多块数据
* : uint32_t block_addr SD卡块地址512
* uint16_t block_cnt
* uint32_t buff[]
* : uint32_t SD_RES_OK SD_RES_ERR SD_RES_TIMEOUT
* :
******************************************************************************************************************************************/
uint32_t SDIO_MultiBlockWrite(uint32_t block_addr, uint16_t block_cnt, uint32_t buff[])
{
uint32_t res, i, j;
uint32_t addr, resp;
if (SD_cardInfo.CardType == SDIO_HIGH_CAPACITY_SD_CARD)
addr = block_addr;
else
addr = block_addr * 512;
res = SDIO_SendCmdWithData(SD_CMD_WRITE_MULT_BLOCK, addr, SD_RESP_32b, &resp, 0, block_cnt);
if (res != SD_RES_OK)
return res;
for (i = 0; i < block_cnt; i++)
{
while ((SDIO->IF & SDIO_IF_BUFWRRDY_Msk) == 0)
__NOP();
SDIO->IF = SDIO_IF_BUFWRRDY_Msk;
for (j = 0; j < 512 / 4; j++)
SDIO->DATA = buff[i * (512 / 4) + j];
}
while ((SDIO->IF & SDIO_IF_TRXDONE_Msk) == 0)
__NOP();
SDIO->IF = SDIO_IF_TRXDONE_Msk;
return SD_RES_OK;
}
/******************************************************************************************************************************************
* : SDIO_DMABlockWrite()
* : DMA向SD卡写入多块数据
* : uint32_t block_addr SD卡块地址512
* uint16_t block_cnt
* uint32_t buff[]
* : uint32_t SD_RES_OK SD_RES_ERR SD_RES_TIMEOUT
* :
******************************************************************************************************************************************/
uint32_t SDIO_DMABlockWrite(uint32_t block_addr, uint16_t block_cnt, uint32_t buff[])
{
uint32_t res;
uint32_t addr, resp;
if (SD_cardInfo.CardType == SDIO_HIGH_CAPACITY_SD_CARD)
addr = block_addr;
else
addr = block_addr * 512;
SDIO->DMA_MEM_ADDR = (uint32_t)buff;
res = SDIO_SendCmdWithDataByDMA(SD_CMD_WRITE_MULT_BLOCK, addr, SD_RESP_32b, &resp, 0, block_cnt);
if (res != SD_RES_OK)
return res;
while ((SDIO->IF & SDIO_IF_TRXDONE_Msk) == 0)
__NOP();
SDIO->IF = SDIO_IF_TRXDONE_Msk;
return SD_RES_OK;
}
/******************************************************************************************************************************************
* : SDIO_BlockRead()
* : SD卡读出数据
* : uint32_t block_addr SD卡块地址512
* uint32_t buff[]
* : uint32_t SD_RES_OK SD_RES_ERR SD_RES_TIMEOUT
* :
******************************************************************************************************************************************/
uint32_t SDIO_BlockRead(uint32_t block_addr, uint32_t buff[])
{
uint32_t res, i;
uint32_t addr, resp;
if (SD_cardInfo.CardType == SDIO_HIGH_CAPACITY_SD_CARD)
addr = block_addr;
else
addr = block_addr * 512;
res = SDIO_SendCmdWithData(SD_CMD_READ_SINGLE_BLOCK, addr, SD_RESP_32b, &resp, 1, 1);
if (res != SD_RES_OK)
return res;
while ((SDIO->IF & SDIO_IF_BUFRDRDY_Msk) == 0)
__NOP();
SDIO->IF = SDIO_IF_BUFRDRDY_Msk;
for (i = 0; i < 512 / 4; i++)
buff[i] = SDIO->DATA;
while ((SDIO->IF & SDIO_IF_TRXDONE_Msk) == 0)
__NOP();
SDIO->IF = SDIO_IF_TRXDONE_Msk;
return SD_RES_OK;
}
/******************************************************************************************************************************************
* : SDIO_MultiBlockRead()
* : SD卡读出多块数据
* : uint32_t block_addr SD卡块地址512
* uint16_t block_cnt
* uint32_t buff[]
* : uint32_t SD_RES_OK SD_RES_ERR SD_RES_TIMEOUT
* :
******************************************************************************************************************************************/
uint32_t SDIO_MultiBlockRead(uint32_t block_addr, uint16_t block_cnt, uint32_t buff[])
{
uint32_t res, i, j;
uint32_t addr, resp;
if (SD_cardInfo.CardType == SDIO_HIGH_CAPACITY_SD_CARD)
addr = block_addr;
else
addr = block_addr * 512;
res = SDIO_SendCmdWithData(SD_CMD_READ_MULT_BLOCK, addr, SD_RESP_32b, &resp, 1, block_cnt);
if (res != SD_RES_OK)
return res;
for (i = 0; i < block_cnt; i++)
{
while ((SDIO->IF & SDIO_IF_BUFRDRDY_Msk) == 0)
__NOP();
SDIO->IF = SDIO_IF_BUFRDRDY_Msk;
for (j = 0; j < 512 / 4; j++)
buff[i * (512 / 4) + j] = SDIO->DATA;
}
while ((SDIO->IF & SDIO_IF_TRXDONE_Msk) == 0)
__NOP();
SDIO->IF = SDIO_IF_TRXDONE_Msk;
return SD_RES_OK;
}
/******************************************************************************************************************************************
* : SDIO_DMABlockRead()
* : DMA从SD卡读出多块数据
* : uint32_t block_addr SD卡块地址512
* uint16_t block_cnt
* uint32_t buff[]
* : uint32_t SD_RES_OK SD_RES_ERR SD_RES_TIMEOUT
* :
******************************************************************************************************************************************/
uint32_t SDIO_DMABlockRead(uint32_t block_addr, uint16_t block_cnt, uint32_t buff[])
{
uint32_t res;
uint32_t addr, resp;
if (SD_cardInfo.CardType == SDIO_HIGH_CAPACITY_SD_CARD)
addr = block_addr;
else
addr = block_addr * 512;
SDIO->DMA_MEM_ADDR = (uint32_t)buff;
res = SDIO_SendCmdWithDataByDMA(SD_CMD_READ_MULT_BLOCK, addr, SD_RESP_32b, &resp, 1, block_cnt);
if (res != SD_RES_OK)
return res;
while ((SDIO->IF & SDIO_IF_TRXDONE_Msk) == 0)
__NOP();
SDIO->IF = SDIO_IF_TRXDONE_Msk;
return SD_RES_OK;
}
/******************************************************************************************************************************************
* : _SDIO_SendCmd()
* : SDIO向SD卡发送命令
* : uint32_t cmd
* uint32_t arg
* uint32_t resp_type SD_RESP_NOSD_RESP_32bSD_RESP_128bSD_RESP_32b_busy
* uint32_t *resp_data
* uint32_t have_data
* uint32_t data_read 1 SD卡 0 SD卡
* uint16_t block_cnt
* uint32_t use_dma 1 使DMA搬运数据
* : uint32_t SD_RES_OK SD_RES_ERR SD_RES_TIMEOUT
* :
******************************************************************************************************************************************/
uint32_t _SDIO_SendCmd(uint32_t cmd, uint32_t arg, uint32_t resp_type, uint32_t *resp_data, uint32_t have_data, uint32_t data_read, uint16_t block_cnt, uint32_t use_dma)
{
SDIO->BLK &= ~SDIO_BLK_COUNT_Msk;
SDIO->BLK |= (block_cnt << SDIO_BLK_COUNT_Pos);
SDIO->ARG = arg;
SDIO->CMD = (cmd << SDIO_CMD_CMDINDX_Pos) |
(0 << SDIO_CMD_CMDTYPE_Pos) |
(0 << SDIO_CMD_IDXCHECK_Pos) |
(0 << SDIO_CMD_CRCCHECK_Pos) |
(resp_type << SDIO_CMD_RESPTYPE_Pos) |
(have_data << SDIO_CMD_HAVEDATA_Pos) |
(data_read << SDIO_CMD_DIRREAD_Pos) |
((block_cnt > 1) << SDIO_CMD_MULTBLK_Pos) |
((block_cnt > 1) << SDIO_CMD_BLKCNTEN_Pos) |
((block_cnt > 1) << SDIO_CMD_AUTOCMD12_Pos) |
(use_dma << SDIO_CMD_DMAEN_Pos);
while ((SDIO->IF & SDIO_IF_CMDDONE_Msk) == 0)
{
if (SDIO->IF & SDIO_IF_CMDTIMEOUT_Msk)
{
SDIO->IF = SDIO_IF_CMDTIMEOUT_Msk;
return SD_RES_TIMEOUT;
}
else if (SDIO->IF & SDIO_IF_ERROR_Msk)
{
SDIO->IF = 0xFFFFFFFF;
return SD_RES_ERR;
}
}
SDIO->IF = SDIO_IF_CMDDONE_Msk;
if (resp_type == SD_RESP_32b)
{
resp_data[0] = SDIO->RESP[0];
}
else if (resp_type == SD_RESP_128b)
{
//寄存器中将CID/CSD[127-8]依次存放在了RESP3-0[119-0]最低位的CRC被丢掉
//读出数据时调整了顺序将CID/CSD[127-8]存放在resp_data0-3[127-8]最低8位填充0x00
resp_data[0] = (SDIO->RESP[3] << 8) + ((SDIO->RESP[2] >> 24) & 0xFF);
resp_data[1] = (SDIO->RESP[2] << 8) + ((SDIO->RESP[1] >> 24) & 0xFF);
resp_data[2] = (SDIO->RESP[1] << 8) + ((SDIO->RESP[0] >> 24) & 0xFF);
resp_data[3] = (SDIO->RESP[0] << 8) + 0x00;
}
return SD_RES_OK;
}
void parseCID(uint32_t CID_Tab[4])
{
uint8_t tmp = 0;
/*!< Byte 0 */
tmp = (uint8_t)((CID_Tab[0] & 0xFF000000) >> 24);
SD_cardInfo.SD_cid.ManufacturerID = tmp;
/*!< Byte 1 */
tmp = (uint8_t)((CID_Tab[0] & 0x00FF0000) >> 16);
SD_cardInfo.SD_cid.OEM_AppliID = tmp << 8;
/*!< Byte 2 */
tmp = (uint8_t)((CID_Tab[0] & 0x000000FF00) >> 8);
SD_cardInfo.SD_cid.OEM_AppliID |= tmp;
/*!< Byte 3 */
tmp = (uint8_t)(CID_Tab[0] & 0x000000FF);
SD_cardInfo.SD_cid.ProdName1 = tmp << 24;
/*!< Byte 4 */
tmp = (uint8_t)((CID_Tab[1] & 0xFF000000) >> 24);
SD_cardInfo.SD_cid.ProdName1 |= tmp << 16;
/*!< Byte 5 */
tmp = (uint8_t)((CID_Tab[1] & 0x00FF0000) >> 16);
SD_cardInfo.SD_cid.ProdName1 |= tmp << 8;
/*!< Byte 6 */
tmp = (uint8_t)((CID_Tab[1] & 0x0000FF00) >> 8);
SD_cardInfo.SD_cid.ProdName1 |= tmp;
/*!< Byte 7 */
tmp = (uint8_t)(CID_Tab[1] & 0x000000FF);
SD_cardInfo.SD_cid.ProdName2 = tmp;
/*!< Byte 8 */
tmp = (uint8_t)((CID_Tab[2] & 0xFF000000) >> 24);
SD_cardInfo.SD_cid.ProdRev = tmp;
/*!< Byte 9 */
tmp = (uint8_t)((CID_Tab[2] & 0x00FF0000) >> 16);
SD_cardInfo.SD_cid.ProdSN = tmp << 24;
/*!< Byte 10 */
tmp = (uint8_t)((CID_Tab[2] & 0x0000FF00) >> 8);
SD_cardInfo.SD_cid.ProdSN |= tmp << 16;
/*!< Byte 11 */
tmp = (uint8_t)(CID_Tab[2] & 0x000000FF);
SD_cardInfo.SD_cid.ProdSN |= tmp << 8;
/*!< Byte 12 */
tmp = (uint8_t)((CID_Tab[3] & 0xFF000000) >> 24);
SD_cardInfo.SD_cid.ProdSN |= tmp;
/*!< Byte 13 */
tmp = (uint8_t)((CID_Tab[3] & 0x00FF0000) >> 16);
SD_cardInfo.SD_cid.Reserved1 |= (tmp & 0xF0) >> 4;
SD_cardInfo.SD_cid.ManufactDate = (tmp & 0x0F) << 8;
/*!< Byte 14 */
tmp = (uint8_t)((CID_Tab[3] & 0x0000FF00) >> 8);
SD_cardInfo.SD_cid.ManufactDate |= tmp;
}
void parseCSD(uint32_t CSD_Tab[4])
{
uint8_t tmp = 0;
/*!< Byte 0 */
tmp = (uint8_t)((CSD_Tab[0] & 0xFF000000) >> 24);
SD_cardInfo.SD_csd.CSDStruct = (tmp & 0xC0) >> 6;
SD_cardInfo.SD_csd.SysSpecVersion = (tmp & 0x3C) >> 2;
SD_cardInfo.SD_csd.Reserved1 = tmp & 0x03;
/*!< Byte 1 */
tmp = (uint8_t)((CSD_Tab[0] & 0x00FF0000) >> 16);
SD_cardInfo.SD_csd.TAAC = tmp;
/*!< Byte 2 */
tmp = (uint8_t)((CSD_Tab[0] & 0x0000FF00) >> 8);
SD_cardInfo.SD_csd.NSAC = tmp;
/*!< Byte 3 */
tmp = (uint8_t)(CSD_Tab[0] & 0x000000FF);
SD_cardInfo.SD_csd.MaxBusClkFrec = tmp;
/*!< Byte 4 */
tmp = (uint8_t)((CSD_Tab[1] & 0xFF000000) >> 24);
SD_cardInfo.SD_csd.CardComdClasses = tmp << 4;
/*!< Byte 5 */
tmp = (uint8_t)((CSD_Tab[1] & 0x00FF0000) >> 16);
SD_cardInfo.SD_csd.CardComdClasses |= (tmp & 0xF0) >> 4;
SD_cardInfo.SD_csd.RdBlockLen = tmp & 0x0F;
/*!< Byte 6 */
tmp = (uint8_t)((CSD_Tab[1] & 0x0000FF00) >> 8);
SD_cardInfo.SD_csd.PartBlockRead = (tmp & 0x80) >> 7;
SD_cardInfo.SD_csd.WrBlockMisalign = (tmp & 0x40) >> 6;
SD_cardInfo.SD_csd.RdBlockMisalign = (tmp & 0x20) >> 5;
SD_cardInfo.SD_csd.DSRImpl = (tmp & 0x10) >> 4;
SD_cardInfo.SD_csd.Reserved2 = 0; /*!< Reserved */
if ((SD_cardInfo.CardType == SDIO_STD_CAPACITY_SD_CARD_V1_1) ||
(SD_cardInfo.CardType == SDIO_STD_CAPACITY_SD_CARD_V2_0))
{
SD_cardInfo.SD_csd.DeviceSize = (tmp & 0x03) << 10;
/*!< Byte 7 */
tmp = (uint8_t)(CSD_Tab[1] & 0x000000FF);
SD_cardInfo.SD_csd.DeviceSize |= (tmp) << 2;
/*!< Byte 8 */
tmp = (uint8_t)((CSD_Tab[2] & 0xFF000000) >> 24);
SD_cardInfo.SD_csd.DeviceSize |= (tmp & 0xC0) >> 6;
SD_cardInfo.SD_csd.MaxRdCurrentVDDMin = (tmp & 0x38) >> 3;
SD_cardInfo.SD_csd.MaxRdCurrentVDDMax = (tmp & 0x07);
/*!< Byte 9 */
tmp = (uint8_t)((CSD_Tab[2] & 0x00FF0000) >> 16);
SD_cardInfo.SD_csd.MaxWrCurrentVDDMin = (tmp & 0xE0) >> 5;
SD_cardInfo.SD_csd.MaxWrCurrentVDDMax = (tmp & 0x1C) >> 2;
SD_cardInfo.SD_csd.DeviceSizeMul = (tmp & 0x03) << 1;
/*!< Byte 10 */
tmp = (uint8_t)((CSD_Tab[2] & 0x0000FF00) >> 8);
SD_cardInfo.SD_csd.DeviceSizeMul |= (tmp & 0x80) >> 7;
SD_cardInfo.CardCapacity = (SD_cardInfo.SD_csd.DeviceSize + 1);
SD_cardInfo.CardCapacity *= (1 << (SD_cardInfo.SD_csd.DeviceSizeMul + 2));
SD_cardInfo.CardBlockSize = 1 << (SD_cardInfo.SD_csd.RdBlockLen);
SD_cardInfo.CardCapacity *= SD_cardInfo.CardBlockSize;
}
else if (SD_cardInfo.CardType == SDIO_HIGH_CAPACITY_SD_CARD)
{
/*!< Byte 7 */
tmp = (uint8_t)(CSD_Tab[1] & 0x000000FF);
SD_cardInfo.SD_csd.DeviceSize = (tmp & 0x3F) << 16;
/*!< Byte 8 */
tmp = (uint8_t)((CSD_Tab[2] & 0xFF000000) >> 24);
SD_cardInfo.SD_csd.DeviceSize |= (tmp << 8);
/*!< Byte 9 */
tmp = (uint8_t)((CSD_Tab[2] & 0x00FF0000) >> 16);
SD_cardInfo.SD_csd.DeviceSize |= (tmp);
/*!< Byte 10 */
tmp = (uint8_t)((CSD_Tab[2] & 0x0000FF00) >> 8);
SD_cardInfo.CardCapacity = (uint64_t)(SD_cardInfo.SD_csd.DeviceSize + 1) * 512 * 1024;
SD_cardInfo.CardBlockSize = 512;
}
SD_cardInfo.SD_csd.EraseGrSize = (tmp & 0x40) >> 6;
SD_cardInfo.SD_csd.EraseGrMul = (tmp & 0x3F) << 1;
/*!< Byte 11 */
tmp = (uint8_t)(CSD_Tab[2] & 0x000000FF);
SD_cardInfo.SD_csd.EraseGrMul |= (tmp & 0x80) >> 7;
SD_cardInfo.SD_csd.WrProtectGrSize = (tmp & 0x7F);
/*!< Byte 12 */
tmp = (uint8_t)((CSD_Tab[3] & 0xFF000000) >> 24);
SD_cardInfo.SD_csd.WrProtectGrEnable = (tmp & 0x80) >> 7;
SD_cardInfo.SD_csd.ManDeflECC = (tmp & 0x60) >> 5;
SD_cardInfo.SD_csd.WrSpeedFact = (tmp & 0x1C) >> 2;
SD_cardInfo.SD_csd.MaxWrBlockLen = (tmp & 0x03) << 2;
/*!< Byte 13 */
tmp = (uint8_t)((CSD_Tab[3] & 0x00FF0000) >> 16);
SD_cardInfo.SD_csd.MaxWrBlockLen |= (tmp & 0xC0) >> 6;
SD_cardInfo.SD_csd.WriteBlockPaPartial = (tmp & 0x20) >> 5;
SD_cardInfo.SD_csd.Reserved3 = 0;
SD_cardInfo.SD_csd.ContentProtectAppli = (tmp & 0x01);
/*!< Byte 14 */
tmp = (uint8_t)((CSD_Tab[3] & 0x0000FF00) >> 8);
SD_cardInfo.SD_csd.FileFormatGrouop = (tmp & 0x80) >> 7;
SD_cardInfo.SD_csd.CopyFlag = (tmp & 0x40) >> 6;
SD_cardInfo.SD_csd.PermWrProtect = (tmp & 0x20) >> 5;
SD_cardInfo.SD_csd.TempWrProtect = (tmp & 0x10) >> 4;
SD_cardInfo.SD_csd.FileFormat = (tmp & 0x0C) >> 2;
SD_cardInfo.SD_csd.ECC = (tmp & 0x03);
}
uint32_t calcSDCLKDiv(uint32_t freq)
{
uint32_t prediv = ((SYS->CLKDIV & SYS_CLKDIV_SDIO_Msk) >> SYS_CLKDIV_SDIO_Pos);
uint32_t clkdiv = (SystemCoreClock / (1 << prediv)) / freq;
uint32_t regdiv = 0;
if (clkdiv > 128)
regdiv = 0x80;
else if (clkdiv > 64)
regdiv = 0x40;
else if (clkdiv > 32)
regdiv = 0x20;
else if (clkdiv > 16)
regdiv = 0x10;
else if (clkdiv > 8)
regdiv = 0x08;
else if (clkdiv > 4)
regdiv = 0x04;
else if (clkdiv > 2)
regdiv = 0x02;
else if (clkdiv > 1)
regdiv = 0x01;
else
regdiv = 0x00;
return regdiv;
}

View File

@ -1,141 +0,0 @@
#ifndef __SWM320_SDIO_H__
#define __SWM320_SDIO_H__
#define SD_CMD_GO_IDLE_STATE ((uint8_t)0)
#define SD_CMD_SEND_OP_COND ((uint8_t)1)
#define SD_CMD_ALL_SEND_CID ((uint8_t)2)
#define SD_CMD_SET_REL_ADDR ((uint8_t)3)
#define SD_CMD_SET_DSR ((uint8_t)4)
#define SD_CMD_HS_SWITCH ((uint8_t)6)
#define SD_CMD_SEL_DESEL_CARD ((uint8_t)7)
#define SD_CMD_SEND_IF_COND ((uint8_t)8)
#define SD_CMD_SEND_CSD ((uint8_t)9)
#define SD_CMD_SEND_CID ((uint8_t)10)
#define SD_CMD_STOP_TRANSMISSION ((uint8_t)12)
#define SD_CMD_SEND_STATUS ((uint8_t)13)
#define SD_CMD_SET_BLOCKLEN ((uint8_t)16)
#define SD_CMD_READ_SINGLE_BLOCK ((uint8_t)17)
#define SD_CMD_READ_MULT_BLOCK ((uint8_t)18)
#define SD_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24)
#define SD_CMD_WRITE_MULT_BLOCK ((uint8_t)25)
#define SD_CMD_PROG_CID ((uint8_t)26)
#define SD_CMD_PROG_CSD ((uint8_t)27)
#define SD_CMD_APP_CMD ((uint8_t)55)
/*Following commands are SD Card Specific commands.
SDIO_APP_CMD should be sent before sending these commands. */
#define SD_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6)
#define SD_CMD_SD_APP_STAUS ((uint8_t)13)
#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22)
#define SD_CMD_SD_APP_OP_COND ((uint8_t)41)
#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42)
#define SD_CMD_SD_APP_SEND_SCR ((uint8_t)51)
#define SD_CMD_SDIO_RW_DIRECT ((uint8_t)52)
#define SD_CMD_SDIO_RW_EXTENDED ((uint8_t)53)
#define SD_RESP_NO 0 //0 无响应
#define SD_RESP_32b 2 //2 32位响应
#define SD_RESP_128b 1 //1 128位响应
#define SD_RESP_32b_busy 3 //3 32位响应check Busy after response
#define SD_BUSWIDTH_1b 0
#define SD_BUSWIDTH_4b 2
#define SD_RES_OK 0
#define SD_RES_ERR 1
#define SD_RES_TIMEOUT 2
typedef struct
{
__IO uint8_t CSDStruct; // CSD structure
__IO uint8_t SysSpecVersion; // System specification version
__IO uint8_t Reserved1; // Reserved
__IO uint8_t TAAC; // Data read access-time 1
__IO uint8_t NSAC; // Data read access-time 2 in CLK cycles
__IO uint8_t MaxBusClkFrec; // Max. bus clock frequency
__IO uint16_t CardComdClasses; //< Card command classes
__IO uint8_t RdBlockLen; // Max. read data block length
__IO uint8_t PartBlockRead; // Partial blocks for read allowed
__IO uint8_t WrBlockMisalign; // Write block misalignment
__IO uint8_t RdBlockMisalign; // Read block misalignment
__IO uint8_t DSRImpl; // DSR implemented
__IO uint8_t Reserved2; // Reserved
__IO uint32_t DeviceSize; // Device Size
__IO uint8_t MaxRdCurrentVDDMin; // Max. read current @ VDD min
__IO uint8_t MaxRdCurrentVDDMax; // Max. read current @ VDD max
__IO uint8_t MaxWrCurrentVDDMin; // Max. write current @ VDD min
__IO uint8_t MaxWrCurrentVDDMax; // Max. write current @ VDD max
__IO uint8_t DeviceSizeMul; // Device size multiplier
__IO uint8_t EraseGrSize; // Erase group size
__IO uint8_t EraseGrMul; // Erase group size multiplier
__IO uint8_t WrProtectGrSize; // Write protect group size
__IO uint8_t WrProtectGrEnable; // Write protect group enable
__IO uint8_t ManDeflECC; // Manufacturer default ECC
__IO uint8_t WrSpeedFact; // Write speed factor
__IO uint8_t MaxWrBlockLen; // Max. write data block length
__IO uint8_t WriteBlockPaPartial; // Partial blocks for write allowed
__IO uint8_t Reserved3; // Reserded
__IO uint8_t ContentProtectAppli; // Content protection application
__IO uint8_t FileFormatGrouop; // File format group
__IO uint8_t CopyFlag; // Copy flag (OTP)
__IO uint8_t PermWrProtect; // Permanent write protection
__IO uint8_t TempWrProtect; // Temporary write protection
__IO uint8_t FileFormat; // File Format
__IO uint8_t ECC; // ECC code
} SD_CSD;
typedef struct
{
__IO uint8_t ManufacturerID; // ManufacturerID
__IO uint16_t OEM_AppliID; // OEM/Application ID
__IO uint32_t ProdName1; // Product Name part1
__IO uint8_t ProdName2; // Product Name part2
__IO uint8_t ProdRev; // Product Revision
__IO uint32_t ProdSN; // Product Serial Number
__IO uint8_t Reserved1; // Reserved1
__IO uint16_t ManufactDate; // Manufacturing Date
} SD_CID;
#define SDIO_STD_CAPACITY_SD_CARD_V1_1 ((uint32_t)0x00000000)
#define SDIO_STD_CAPACITY_SD_CARD_V2_0 ((uint32_t)0x00000001)
#define SDIO_HIGH_CAPACITY_SD_CARD ((uint32_t)0x00000002)
#define SDIO_MULTIMEDIA_CARD ((uint32_t)0x00000003)
#define SDIO_SECURE_DIGITAL_IO_CARD ((uint32_t)0x00000004)
#define SDIO_HIGH_SPEED_MULTIMEDIA_CARD ((uint32_t)0x00000005)
#define SDIO_SECURE_DIGITAL_IO_COMBO_CARD ((uint32_t)0x00000006)
#define SDIO_HIGH_CAPACITY_MMC_CARD ((uint32_t)0x00000007)
typedef struct
{
SD_CSD SD_csd;
SD_CID SD_cid;
uint64_t CardCapacity; // Card Capacity
uint32_t CardBlockSize; // Card Block Size
uint16_t RCA;
uint8_t CardType;
} SD_CardInfo;
extern SD_CardInfo SD_cardInfo;
uint32_t SDIO_Init(uint32_t freq);
uint32_t SDIO_BlockWrite(uint32_t block_addr, uint32_t buff[]);
uint32_t SDIO_BlockRead(uint32_t block_addr, uint32_t buff[]);
uint32_t SDIO_MultiBlockWrite(uint32_t block_addr, uint16_t block_cnt, uint32_t buff[]);
uint32_t SDIO_MultiBlockRead(uint32_t block_addr, uint16_t block_cnt, uint32_t buff[]);
uint32_t SDIO_DMABlockWrite(uint32_t block_addr, uint16_t block_cnt, uint32_t buff[]);
uint32_t SDIO_DMABlockRead(uint32_t block_addr, uint16_t block_cnt, uint32_t buff[]);
uint32_t _SDIO_SendCmd(uint32_t cmd, uint32_t arg, uint32_t resp_type, uint32_t *resp_data, uint32_t have_data, uint32_t data_read, uint16_t block_cnt, uint32_t use_dma);
#define SDIO_SendCmd(cmd, arg, resp_type, resp_data) _SDIO_SendCmd(cmd, arg, resp_type, resp_data, 0, 0, 0, 0)
#define SDIO_SendCmdWithData(cmd, arg, resp_type, resp_data, data_read, block_cnt) _SDIO_SendCmd(cmd, arg, resp_type, resp_data, 1, data_read, block_cnt, 0)
#define SDIO_SendCmdWithDataByDMA(cmd, arg, resp_type, resp_data, data_read, block_cnt) _SDIO_SendCmd(cmd, arg, resp_type, resp_data, 1, data_read, block_cnt, 1)
void parseCID(uint32_t CID_Tab[4]);
void parseCSD(uint32_t CID_Tab[4]);
uint32_t calcSDCLKDiv(uint32_t freq_sel);
#endif //__SWM320_SDIO_H__

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@ -1,116 +0,0 @@
/******************************************************************************************************************************************
* : SWM320_sdram.c
* : SWM320单片机的SDRAM驱动程序
* : http://www.synwit.com.cn/e/tool/gbook/?bid=1
* :
* : V1.1.0 20171025
* :
*
*
*******************************************************************************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
* -ECTION WITH THEIR PRODUCTS.
*
* COPYRIGHT 2012 Synwit Technology
*******************************************************************************************************************************************/
#include "SWM320.h"
#include "SWM320_sdram.h"
/******************************************************************************************************************************************
* : SDRAM_Init()
* : SDRAM控制器初始化
* : SDRAM_InitStructure * initStruct SDRAM
* :
* :
******************************************************************************************************************************************/
void SDRAM_Init(SDRAM_InitStructure *initStruct)
{
uint32_t row_n;
SYS->CLKEN |= (1 << SYS_CLKEN_SDRAM_Pos);
SYS->CLKDIV &= ~SYS_CLKDIV_SDRAM_Msk;
SYS->CLKDIV |= (1 << SYS_CLKDIV_SDRAM_Pos); //2分频
SDRAMC->CR0 = (2 << SDRAMC_CR0_BURSTLEN_Pos) | //2 Burst Length为4
(initStruct->CASLatency << SDRAMC_CR0_CASDELAY_Pos);
SDRAMC->CR1 = (initStruct->CellSize << SDRAMC_CR1_CELLSIZE_Pos) |
(initStruct->CellWidth << SDRAMC_CR1_CELL32BIT_Pos) |
(initStruct->CellBank << SDRAMC_CR1_BANK_Pos) |
(0 << SDRAMC_CR1_32BIT_Pos) |
(initStruct->TimeTMRD << SDRAMC_CR1_TMRD_Pos) |
(initStruct->TimeTRRD << SDRAMC_CR1_TRRD_Pos) |
(initStruct->TimeTRAS << SDRAMC_CR1_TRAS_Pos) |
(initStruct->TimeTRC << SDRAMC_CR1_TRC_Pos) |
(initStruct->TimeTRCD << SDRAMC_CR1_TRCD_Pos) |
(initStruct->TimeTRP << SDRAMC_CR1_TRP_Pos);
SDRAMC->LATCH = 0x02;
switch (initStruct->CellSize)
{
case SDRAM_CELLSIZE_16Mb:
row_n = 11;
break;
case SDRAM_CELLSIZE_64Mb:
row_n = 12;
break;
case SDRAM_CELLSIZE_128Mb:
row_n = 12;
break;
case SDRAM_CELLSIZE_256Mb:
row_n = 13;
break;
default:
row_n = 13;
break;
}
SDRAMC->REFRESH = (1 << SDRAMC_REFRESH_EN_Pos) |
(((SystemCoreClock / 2) / 1000 * 64 / (1 << row_n)) << SDRAMC_REFRESH_RATE_Pos);
while (SDRAMC->REFDONE == 0)
;
}
/******************************************************************************************************************************************
* : SDRAM_Enable()
* : SDRAM使能使SDRAM
* :
* :
* :
******************************************************************************************************************************************/
void SDRAM_Enable(void)
{
uint32_t i;
SYS->CLKEN |= (1 << SYS_CLKEN_SDRAM_Pos);
SDRAMC->REFRESH |= (1 << SDRAMC_REFRESH_EN_Pos);
for (i = 0; i < 100; i++)
__NOP();
}
/******************************************************************************************************************************************
* : SDRAM_Disable()
* : SDRAM禁能SDRAM颗粒进入低功耗模式
* :
* :
* :
******************************************************************************************************************************************/
void SDRAM_Disable(void)
{
uint32_t i;
SYS->CLKEN |= (1 << SYS_CLKEN_SDRAM_Pos);
SDRAMC->REFRESH &= ~(1 << SDRAMC_REFRESH_EN_Pos);
for (i = 0; i < 100; i++)
__NOP();
}

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@ -1,81 +0,0 @@
#ifndef __SWM320_SDRAM_H__
#define __SWM320_SDRAM_H__
typedef struct
{
uint8_t CellSize; // SDRAM颗粒的容量SDRAM_CELLSIZE_16Mb、SDRAM_CELLSIZE_64Mb、SDRAM_CELLSIZE_128Mb、SDRAM_CELLSIZE_256Mb
uint8_t CellBank; // SDRAM颗粒有几个bankSDRAM_CELLBANK_2、SDRAM_CELLBANK_4
uint8_t CellWidth; // SDRAM颗粒的位宽SDRAM_CELLWIDTH_16、SDRAM_CELLWIDTH_32
uint8_t CASLatency; // 列地址到有效数据输出间隔SDRAM_CASLATENCY_2、SDRAM_CASLATENCY_3
uint8_t TimeTMRD; // MRS to New Command
uint8_t TimeTRRD; // Activate to activate on different banks
uint8_t TimeTRAS; // Self refresh time最小Self-refresh周期
uint8_t TimeTRC; // Row cycle delayRefresh命令到Activate命令间延时也是两个连续Refresh命令间延时
uint8_t TimeTRCD; // Row to column delay行地址到列地址间延时也即Activate命令到读写命令间延时
uint8_t TimeTRP; // Row precharge delayPrecharge命令到另一个命令间延时
} SDRAM_InitStructure;
#define SDRAM_CELLSIZE_16Mb 3
#define SDRAM_CELLSIZE_64Mb 0
#define SDRAM_CELLSIZE_128Mb 1
#define SDRAM_CELLSIZE_256Mb 2
#define SDRAM_CELLBANK_2 0
#define SDRAM_CELLBANK_4 1
#define SDRAM_CELLWIDTH_16 0
#define SDRAM_CELLWIDTH_32 1
#define SDRAM_CASLATENCY_2 2
#define SDRAM_CASLATENCY_3 3
#define SDRAM_TMRD_3 3
#define SDRAM_TMRD_4 4
#define SDRAM_TMRD_5 5
#define SDRAM_TMRD_6 6
#define SDRAM_TMRD_7 7
#define SDRAM_TRRD_2 2
#define SDRAM_TRRD_3 3
#define SDRAM_TRAS_2 2
#define SDRAM_TRAS_3 3
#define SDRAM_TRAS_4 4
#define SDRAM_TRAS_5 5
#define SDRAM_TRAS_6 6
#define SDRAM_TRAS_7 7
#define SDRAM_TRC_2 2
#define SDRAM_TRC_3 3
#define SDRAM_TRC_4 4
#define SDRAM_TRC_5 5
#define SDRAM_TRC_6 6
#define SDRAM_TRC_7 7
#define SDRAM_TRC_8 8
#define SDRAM_TRC_9 9
#define SDRAM_TRC_10 10
#define SDRAM_TRC_11 11
#define SDRAM_TRC_12 12
#define SDRAM_TRC_13 13
#define SDRAM_TRC_14 14
#define SDRAM_TRC_15 15
#define SDRAM_TRCD_3 3
#define SDRAM_TRCD_4 4
#define SDRAM_TRCD_5 5
#define SDRAM_TRCD_6 6
#define SDRAM_TRCD_7 7
#define SDRAM_TRP_3 3
#define SDRAM_TRP_4 4
#define SDRAM_TRP_5 5
#define SDRAM_TRP_6 6
#define SDRAM_TRP_7 7
void SDRAM_Init(SDRAM_InitStructure *initStruct);
void SDRAM_Enable(void);
void SDRAM_Disable(void);
#endif //__SWM320_SDRAM_H__

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@ -1,543 +0,0 @@
/******************************************************************************************************************************************
* : SWM320_spi.c
* : SWM320单片机的SPI功能驱动库
* : http://www.synwit.com.cn/e/tool/gbook/?bid=1
* :
* : V1.1.0 20171025
* :
*
*
*******************************************************************************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
* -ECTION WITH THEIR PRODUCTS.
*
* COPYRIGHT 2012 Synwit Technology
*******************************************************************************************************************************************/
#include "SWM320.h"
#include "SWM320_spi.h"
/******************************************************************************************************************************************
* : SPI_Init()
* : SPI同步串行接口初始化FIFO触发设定
* : SPI_TypeDef * SPIx SPISPI0SPI1
* SPI_InitStructure * initStruct SPI相关设定值的结构体
* :
* :
******************************************************************************************************************************************/
void SPI_Init(SPI_TypeDef *SPIx, SPI_InitStructure *initStruct)
{
switch ((uint32_t)SPIx)
{
case ((uint32_t)SPI0):
SYS->CLKEN |= (0x01 << SYS_CLKEN_SPI0_Pos);
break;
case ((uint32_t)SPI1):
SYS->CLKEN |= (0x01 << SYS_CLKEN_SPI0_Pos); //与SPI0使用同一位时钟使能
break;
}
SPI_Close(SPIx); //一些关键寄存器只能在SPI关闭时设置
SPIx->CTRL &= ~(SPI_CTRL_FFS_Msk | SPI_CTRL_CPHA_Msk | SPI_CTRL_CPOL_Msk |
SPI_CTRL_SIZE_Msk | SPI_CTRL_MSTR_Msk | SPI_CTRL_CLKDIV_Msk | SPI_CTRL_SSN_H_Msk);
SPIx->CTRL |= (initStruct->FrameFormat << SPI_CTRL_FFS_Pos) |
(initStruct->SampleEdge << SPI_CTRL_CPHA_Pos) |
(initStruct->IdleLevel << SPI_CTRL_CPOL_Pos) |
((initStruct->WordSize - 1) << SPI_CTRL_SIZE_Pos) |
(initStruct->Master << SPI_CTRL_MSTR_Pos) |
(initStruct->clkDiv << SPI_CTRL_CLKDIV_Pos) |
(0 << SPI_CTRL_SSN_H_Pos);
SPIx->IF = (0x01 << SPI_IF_RFOVF_Pos); //清除中断标志
SPIx->IE &= ~(SPI_IE_RFHF_Msk | SPI_IE_TFHF_Msk | SPI_IE_FTC_Msk);
SPIx->IE |= (initStruct->RXHFullIEn << SPI_IE_RFHF_Pos) |
(initStruct->TXEmptyIEn << SPI_IE_TFHF_Pos) |
(initStruct->TXCompleteIEn << SPI_IE_FTC_Pos);
switch ((uint32_t)SPIx)
{
case ((uint32_t)SPI0):
if (initStruct->RXHFullIEn | initStruct->TXEmptyIEn | initStruct->TXCompleteIEn)
{
NVIC_EnableIRQ(SPI0_IRQn);
}
else
{
NVIC_DisableIRQ(SPI0_IRQn);
}
break;
case ((uint32_t)SPI1):
if (initStruct->RXHFullIEn | initStruct->TXEmptyIEn | initStruct->TXCompleteIEn)
{
NVIC_EnableIRQ(SPI1_IRQn);
}
else
{
NVIC_DisableIRQ(SPI1_IRQn);
}
break;
}
}
/******************************************************************************************************************************************
* : SPI_Open()
* : SPI打开
* : SPI_TypeDef * SPIx SPISPI0SPI1
* :
* :
******************************************************************************************************************************************/
void SPI_Open(SPI_TypeDef *SPIx)
{
SPIx->CTRL |= (0x01 << SPI_CTRL_EN_Pos);
}
/******************************************************************************************************************************************
* : SPI_Close()
* : SPI关闭
* : SPI_TypeDef * SPIx SPISPI0SPI1
* :
* :
******************************************************************************************************************************************/
void SPI_Close(SPI_TypeDef *SPIx)
{
SPIx->CTRL &= ~SPI_CTRL_EN_Msk;
}
/******************************************************************************************************************************************
* : SPI_Read()
* :
* : SPI_TypeDef * SPIx SPISPI0SPI1
* : uint32_t
* :
******************************************************************************************************************************************/
uint32_t SPI_Read(SPI_TypeDef *SPIx)
{
return SPIx->DATA;
}
/******************************************************************************************************************************************
* : SPI_Write()
* :
* : SPI_TypeDef * SPIx SPISPI0SPI1
* uint32_t
* :
* :
******************************************************************************************************************************************/
void SPI_Write(SPI_TypeDef *SPIx, uint32_t data)
{
SPIx->DATA = data;
}
/******************************************************************************************************************************************
* : SPI_WriteWithWait()
* :
* : SPI_TypeDef * SPIx SPISPI0SPI1SPI1
* uint32_t
* :
* :
******************************************************************************************************************************************/
void SPI_WriteWithWait(SPI_TypeDef *SPIx, uint32_t data)
{
SPIx->STAT |= (1 << SPI_STAT_WTC_Pos);
SPIx->DATA = data;
while ((SPIx->STAT & SPI_STAT_WTC_Msk) == 0)
;
}
/******************************************************************************************************************************************
* : SPI_ReadWrite()
* :
* : SPI_TypeDef * SPIx SPISPI0SPI1
* uint32_t data
* : uint32_t
* : SPI模块SPI_Write()SPI_Write()SPI_STAT_RFNE状态
******************************************************************************************************************************************/
uint32_t SPI_ReadWrite(SPI_TypeDef *SPIx, uint32_t data)
{
SPIx->DATA = data;
while (!(SPIx->STAT & SPI_STAT_RFNE_Msk))
;
return SPIx->DATA;
}
/******************************************************************************************************************************************
* : SPI_IsRXEmpty()
* : FIFO是否空SPI_Read()
* : SPI_TypeDef * SPIx SPISPI0SPI1
* : uint32_t 1 FIFO空 0 FIFO非空
* :
******************************************************************************************************************************************/
uint32_t SPI_IsRXEmpty(SPI_TypeDef *SPIx)
{
return (SPIx->STAT & SPI_STAT_RFNE_Msk) ? 0 : 1;
}
/******************************************************************************************************************************************
* : SPI_IsTXFull()
* : FIFO是否满SPI_Write()
* : SPI_TypeDef * SPIx SPISPI0SPI1
* : uint32_t 1 FIFO满 0 FIFO不满
* :
******************************************************************************************************************************************/
uint32_t SPI_IsTXFull(SPI_TypeDef *SPIx)
{
return (SPIx->STAT & SPI_STAT_TFNF_Msk) ? 0 : 1;
}
/******************************************************************************************************************************************
* : SPI_IsTXEmpty()
* : FIFO是否空
* : SPI_TypeDef * SPIx SPISPI0SPI1
* : uint32_t 1 FIFO空 0 FIFO非空
* :
******************************************************************************************************************************************/
uint32_t SPI_IsTXEmpty(SPI_TypeDef *SPIx)
{
return (SPIx->STAT & SPI_STAT_TFE_Msk) ? 1 : 0;
}
/******************************************************************************************************************************************
* : SPI_INTRXHalfFullEn()
* : FIFO半满中断使能
* : SPI_TypeDef * SPIx SPISPI0SPI1
* :
* :
******************************************************************************************************************************************/
void SPI_INTRXHalfFullEn(SPI_TypeDef *SPIx)
{
SPIx->IE |= (0x01 << SPI_IE_RFHF_Pos);
}
/******************************************************************************************************************************************
* : SPI_INTRXHalfFullDis()
* : FIFO半满中断禁止
* : SPI_TypeDef * SPIx SPISPI0SPI1
* :
* :
******************************************************************************************************************************************/
void SPI_INTRXHalfFullDis(SPI_TypeDef *SPIx)
{
SPIx->IE &= ~(0x01 << SPI_IE_RFHF_Pos);
}
/******************************************************************************************************************************************
* : SPI_INTRXHalfFullClr()
* : FIFO半满中断标志清除
* : SPI_TypeDef * SPIx SPISPI0SPI1
* :
* :
******************************************************************************************************************************************/
void SPI_INTRXHalfFullClr(SPI_TypeDef *SPIx)
{
SPIx->IF = (1 << SPI_IF_RFHF_Pos);
}
/******************************************************************************************************************************************
* : SPI_INTRXHalfFullStat()
* : FIFO半满中断状态
* : SPI_TypeDef * SPIx SPISPI0SPI1
* : uint32_t 1 FIFO达到半满 0 FIFO未达到半满
* :
******************************************************************************************************************************************/
uint32_t SPI_INTRXHalfFullStat(SPI_TypeDef *SPIx)
{
return (SPIx->IF & SPI_IF_RFHF_Msk) ? 1 : 0;
}
/******************************************************************************************************************************************
* : SPI_INTRXFullEn()
* : FIFO满中断使能
* : SPI_TypeDef * SPIx SPISPI0SPI1
* :
* :
******************************************************************************************************************************************/
void SPI_INTRXFullEn(SPI_TypeDef *SPIx)
{
SPIx->IE |= (0x01 << SPI_IE_RFF_Pos);
}
/******************************************************************************************************************************************
* : SPI_INTRXFullDis()
* : FIFO满中断禁止
* : SPI_TypeDef * SPIx SPISPI0SPI1
* :
* :
******************************************************************************************************************************************/
void SPI_INTRXFullDis(SPI_TypeDef *SPIx)
{
SPIx->IE &= ~(0x01 << SPI_IE_RFF_Pos);
}
/******************************************************************************************************************************************
* : SPI_INTRXFullClr()
* : FIFO满中断标志清除
* : SPI_TypeDef * SPIx SPISPI0SPI1
* :
* :
******************************************************************************************************************************************/
void SPI_INTRXFullClr(SPI_TypeDef *SPIx)
{
SPIx->IF = (1 << SPI_IF_RFF_Pos);
}
/******************************************************************************************************************************************
* : SPI_INTRXFullStat()
* : FIFO满中断状态
* : SPI_TypeDef * SPIx SPISPI0SPI1
* : uint32_t 1 FIFO满 0 FIFO未满
* :
******************************************************************************************************************************************/
uint32_t SPI_INTRXFullStat(SPI_TypeDef *SPIx)
{
return (SPIx->IF & SPI_IF_RFF_Msk) ? 1 : 0;
}
/******************************************************************************************************************************************
* : SPI_INTRXOverflowEn()
* : FIFO溢出中断使能
* : SPI_TypeDef * SPIx SPISPI0SPI1
* :
* :
******************************************************************************************************************************************/
void SPI_INTRXOverflowEn(SPI_TypeDef *SPIx)
{
SPIx->IE |= (0x01 << SPI_IE_RFOVF_Pos);
}
/******************************************************************************************************************************************
* : SPI_INTRXOverflowDis()
* : FIFO溢出中断禁止
* : SPI_TypeDef * SPIx SPISPI0SPI1
* :
* :
******************************************************************************************************************************************/
void SPI_INTRXOverflowDis(SPI_TypeDef *SPIx)
{
SPIx->IE &= ~(0x01 << SPI_IE_RFOVF_Pos);
}
/******************************************************************************************************************************************
* : SPI_INTRXOverflowClr()
* : FIFO溢出中断标志清除
* : SPI_TypeDef * SPIx SPISPI0SPI1
* :
* :
******************************************************************************************************************************************/
void SPI_INTRXOverflowClr(SPI_TypeDef *SPIx)
{
SPIx->IF = (0x01 << SPI_IF_RFOVF_Pos);
}
/******************************************************************************************************************************************
* : SPI_INTRXOverflowStat()
* : FIFO溢出中断状态
* : SPI_TypeDef * SPIx SPISPI0SPI1
* : uint32_t 1 FIFO溢出 0 FIFO未溢出
* :
******************************************************************************************************************************************/
uint32_t SPI_INTRXOverflowStat(SPI_TypeDef *SPIx)
{
return (SPIx->IF & SPI_IF_RFOVF_Msk) ? 1 : 0;
}
/******************************************************************************************************************************************
* : SPI_INTTXHalfFullEn()
* : FIFO半满中断使能
* : SPI_TypeDef * SPIx SPISPI0SPI1
* :
* :
******************************************************************************************************************************************/
void SPI_INTTXHalfFullEn(SPI_TypeDef *SPIx)
{
SPIx->IE |= (0x01 << SPI_IE_TFHF_Pos);
}
/******************************************************************************************************************************************
* : SPI_INTTXHalfFullDis()
* : FIFO半满中断禁止
* : SPI_TypeDef * SPIx SPISPI0SPI1
* :
* :
******************************************************************************************************************************************/
void SPI_INTTXHalfFullDis(SPI_TypeDef *SPIx)
{
SPIx->IE &= ~(0x01 << SPI_IE_TFHF_Pos);
}
/******************************************************************************************************************************************
* : SPI_INTTXHalfFullClr()
* : FIFO半满中断标志清除
* : SPI_TypeDef * SPIx SPISPI0SPI1
* :
* :
******************************************************************************************************************************************/
void SPI_INTTXHalfFullClr(SPI_TypeDef *SPIx)
{
SPIx->IF = (1 << SPI_IF_TFHF_Pos);
}
/******************************************************************************************************************************************
* : SPI_INTTXHalfFullStat()
* : FIFO半满中断状态
* : SPI_TypeDef * SPIx SPISPI0SPI1
* : uint32_t 1 FIFO达到半满 0 FIFO未达到半满
* :
******************************************************************************************************************************************/
uint32_t SPI_INTTXHalfFullStat(SPI_TypeDef *SPIx)
{
return (SPIx->IF & SPI_IF_TFHF_Msk) ? 1 : 0;
}
/******************************************************************************************************************************************
* : SPI_INTTXEmptyEn()
* : FIFO空中断使能
* : SPI_TypeDef * SPIx SPISPI0SPI1
* :
* :
******************************************************************************************************************************************/
void SPI_INTTXEmptyEn(SPI_TypeDef *SPIx)
{
SPIx->IE |= (0x01 << SPI_IE_TFE_Pos);
}
/******************************************************************************************************************************************
* : SPI_INTTXEmptyDis()
* : FIFO空中断禁止
* : SPI_TypeDef * SPIx SPISPI0SPI1
* :
* :
******************************************************************************************************************************************/
void SPI_INTTXEmptyDis(SPI_TypeDef *SPIx)
{
SPIx->IE &= ~(0x01 << SPI_IE_TFE_Pos);
}
/******************************************************************************************************************************************
* : SPI_INTTXEmptyClr()
* : FIFO空中断标志清除
* : SPI_TypeDef * SPIx SPISPI0SPI1
* :
* :
******************************************************************************************************************************************/
void SPI_INTTXEmptyClr(SPI_TypeDef *SPIx)
{
SPIx->IF = (1 << SPI_IF_TFE_Pos);
}
/******************************************************************************************************************************************
* : SPI_INTTXEmptyStat()
* : FIFO空中断状态
* : SPI_TypeDef * SPIx SPISPI0SPI1
* : uint32_t 1 FIFO空 0 FIFO非空
* :
******************************************************************************************************************************************/
uint32_t SPI_INTTXEmptyStat(SPI_TypeDef *SPIx)
{
return (SPIx->IF & SPI_IF_TFE_Msk) ? 1 : 0;
}
/******************************************************************************************************************************************
* : SPI_INTTXCompleteEn()
* : FIFO空且发送移位寄存器空中断使能
* : SPI_TypeDef * SPIx SPISPI0SPI1
* :
* :
******************************************************************************************************************************************/
void SPI_INTTXCompleteEn(SPI_TypeDef *SPIx)
{
SPIx->IE |= (0x01 << SPI_IE_FTC_Pos);
}
/******************************************************************************************************************************************
* : SPI_INTTXCompleteDis()
* : FIFO空且发送移位寄存器空中断禁止
* : SPI_TypeDef * SPIx SPISPI0SPI1
* :
* :
******************************************************************************************************************************************/
void SPI_INTTXCompleteDis(SPI_TypeDef *SPIx)
{
SPIx->IE &= ~(0x01 << SPI_IE_FTC_Pos);
}
/******************************************************************************************************************************************
* : SPI_INTTXCompleteClr()
* : FIFO空且发送移位寄存器空中断状态清除
* : SPI_TypeDef * SPIx SPISPI0SPI1
* :
* :
******************************************************************************************************************************************/
void SPI_INTTXCompleteClr(SPI_TypeDef *SPIx)
{
SPIx->IF = (1 << SPI_IF_FTC_Pos);
}
/******************************************************************************************************************************************
* : SPI_INTTXCompleteStat()
* : FIFO空且发送移位寄存器空中断状态
* : SPI_TypeDef * SPIx SPISPI0SPI1
* : uint32_t 1 FIFO空且发送移位寄存器空 0 FIFO或发送移位寄存器非空
* :
******************************************************************************************************************************************/
uint32_t SPI_INTTXCompleteStat(SPI_TypeDef *SPIx)
{
return (SPIx->IF & SPI_IF_FTC_Msk) ? 1 : 0;
}
/******************************************************************************************************************************************
* : SPI_INTTXWordCompleteEn()
* : FIFO字发送完成中断使能
* : SPI_TypeDef * SPIx SPISPI0SPI1
* :
* :
******************************************************************************************************************************************/
void SPI_INTTXWordCompleteEn(SPI_TypeDef *SPIx)
{
SPIx->IE |= (0x01 << SPI_IE_WTC_Pos);
}
/******************************************************************************************************************************************
* : SPI_INTTXWordCompleteDis()
* : FIFO字发送完成中断禁止
* : SPI_TypeDef * SPIx SPISPI0SPI1
* :
* :
******************************************************************************************************************************************/
void SPI_INTTXWordCompleteDis(SPI_TypeDef *SPIx)
{
SPIx->IE &= ~(0x01 << SPI_IE_WTC_Pos);
}
/******************************************************************************************************************************************
* : SPI_INTTXWordCompleteClr()
* : FIFO字发送完成中断标志清除
* : SPI_TypeDef * SPIx SPISPI0SPI1
* :
* :
******************************************************************************************************************************************/
void SPI_INTTXWordCompleteClr(SPI_TypeDef *SPIx)
{
SPIx->IF = (1 << SPI_IF_WTC_Pos);
}
/******************************************************************************************************************************************
* : SPI_INTTXWordCompleteStat()
* : FIFO字发送完成中断状态
* : SPI_TypeDef * SPIx SPISPI0SPI1
* : uint32_t 1 0
* :
******************************************************************************************************************************************/
uint32_t SPI_INTTXWordCompleteStat(SPI_TypeDef *SPIx)
{
return (SPIx->IF & SPI_IF_WTC_Msk) ? 1 : 0;
}

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@ -1,80 +0,0 @@
#ifndef __SWM320_SPI_H__
#define __SWM320_SPI_H__
typedef struct
{
uint8_t FrameFormat; //帧格式SPI_FORMAT_SPI、SPI_FORMAT_TI_SSI
uint8_t SampleEdge; //在SPI帧格式下选择数据采样边沿SPI_FIRST_EDGE、SPI_SECOND_EDGE
uint8_t IdleLevel; //在SPI帧格式下选择空闲时无数据传输时时钟线的电平SPI_LOW_LEVEL、SPI_HIGH_LEVEL
uint8_t WordSize; //字长度, 有效值4-16
uint8_t Master; //1 主机模式 0 从机模式
uint8_t clkDiv; //SPI_CLK = SYS_CLK / clkDiv有效值SPI_CLKDIV_4、SPI_CLKDIV_8、... ... 、SPI_CLKDIV_512
uint8_t RXHFullIEn; //接收FIFO半满中断使能
uint8_t TXEmptyIEn; //发送FIFO 空中断使能
uint8_t TXCompleteIEn; //发送FIFO 空且发送移位寄存器空中断使能
} SPI_InitStructure;
#define SPI_FORMAT_SPI 0 //Motorola SPI 格式
#define SPI_FORMAT_TI_SSI 1 //TI SSI 格式
#define SPI_FIRST_EDGE 0 //第一个时钟沿开始采样
#define SPI_SECOND_EDGE 1 //第二个时钟沿开始采样
#define SPI_LOW_LEVEL 0 //空闲时时钟线保持低电平
#define SPI_HIGH_LEVEL 1 //空闲时时钟线保持高电平
#define SPI_CLKDIV_4 0
#define SPI_CLKDIV_8 1
#define SPI_CLKDIV_16 2
#define SPI_CLKDIV_32 3
#define SPI_CLKDIV_64 4
#define SPI_CLKDIV_128 5
#define SPI_CLKDIV_256 6
#define SPI_CLKDIV_512 7
void SPI_Init(SPI_TypeDef *SPIx, SPI_InitStructure *initStruct); //SPI初始化
void SPI_Open(SPI_TypeDef *SPIx); //SPI打开允许收发
void SPI_Close(SPI_TypeDef *SPIx); //SPI关闭禁止收发
uint32_t SPI_Read(SPI_TypeDef *SPIx);
void SPI_Write(SPI_TypeDef *SPIx, uint32_t data);
void SPI_WriteWithWait(SPI_TypeDef *SPIx, uint32_t data);
uint32_t SPI_ReadWrite(SPI_TypeDef *SPIx, uint32_t data);
uint32_t SPI_IsRXEmpty(SPI_TypeDef *SPIx); //接收FIFO是否空如果不空则可以继续SPI_Read()
uint32_t SPI_IsTXFull(SPI_TypeDef *SPIx); //发送FIFO是否满如果不满则可以继续SPI_Write()
uint32_t SPI_IsTXEmpty(SPI_TypeDef *SPIx); //发送FIFO是否空
void SPI_INTRXHalfFullEn(SPI_TypeDef *SPIx);
void SPI_INTRXHalfFullDis(SPI_TypeDef *SPIx);
void SPI_INTRXHalfFullClr(SPI_TypeDef *SPIx);
uint32_t SPI_INTRXHalfFullStat(SPI_TypeDef *SPIx);
void SPI_INTRXFullEn(SPI_TypeDef *SPIx);
void SPI_INTRXFullDis(SPI_TypeDef *SPIx);
void SPI_INTRXFullClr(SPI_TypeDef *SPIx);
uint32_t SPI_INTRXFullStat(SPI_TypeDef *SPIx);
void SPI_INTRXOverflowEn(SPI_TypeDef *SPIx);
void SPI_INTRXOverflowDis(SPI_TypeDef *SPIx);
void SPI_INTRXOverflowClr(SPI_TypeDef *SPIx);
uint32_t SPI_INTRXOverflowStat(SPI_TypeDef *SPIx);
void SPI_INTTXHalfFullEn(SPI_TypeDef *SPIx);
void SPI_INTTXHalfFullDis(SPI_TypeDef *SPIx);
void SPI_INTTXHalfFullClr(SPI_TypeDef *SPIx);
uint32_t SPI_INTTXHalfFullStat(SPI_TypeDef *SPIx);
void SPI_INTTXEmptyEn(SPI_TypeDef *SPIx);
void SPI_INTTXEmptyDis(SPI_TypeDef *SPIx);
void SPI_INTTXEmptyClr(SPI_TypeDef *SPIx);
uint32_t SPI_INTTXEmptyStat(SPI_TypeDef *SPIx);
void SPI_INTTXCompleteEn(SPI_TypeDef *SPIx);
void SPI_INTTXCompleteDis(SPI_TypeDef *SPIx);
void SPI_INTTXCompleteClr(SPI_TypeDef *SPIx);
uint32_t SPI_INTTXCompleteStat(SPI_TypeDef *SPIx);
void SPI_INTTXWordCompleteEn(SPI_TypeDef *SPIx);
void SPI_INTTXWordCompleteDis(SPI_TypeDef *SPIx);
void SPI_INTTXWordCompleteClr(SPI_TypeDef *SPIx);
uint32_t SPI_INTTXWordCompleteStat(SPI_TypeDef *SPIx);
#endif //__SWM320_SPI_H__

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@ -1,56 +0,0 @@
/******************************************************************************************************************************************
* : SWM320_sram.c
* : SWM320单片机的SRAM驱动程序
* : http://www.synwit.com.cn/e/tool/gbook/?bid=1
* :
* : V1.1.0 20171025
* :
*
*
*******************************************************************************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
* -ECTION WITH THEIR PRODUCTS.
*
* COPYRIGHT 2012 Synwit Technology
*******************************************************************************************************************************************/
#include "SWM320.h"
#include "SWM320_sram.h"
/******************************************************************************************************************************************
* : SRAM_Init()
* : SRAM控制器初始化
* : SRAM_InitStructure * initStruct SRAM
* :
* :
******************************************************************************************************************************************/
void SRAM_Init(SRAM_InitStructure *initStruct)
{
uint32_t i;
// 配置SRAM前需要刷新下SDRAM控制器
do
{
SYS->CLKEN |= (1 << SYS_CLKEN_SDRAM_Pos);
while (SDRAMC->REFDONE == 0)
;
SDRAMC->REFRESH &= ~(1 << SDRAMC_REFRESH_EN_Pos);
for (i = 0; i < 1000; i++)
__NOP();
SYS->CLKEN &= ~(1 << SYS_CLKEN_SDRAM_Pos);
} while (0);
SYS->CLKEN |= (1 << SYS_CLKEN_RAMC_Pos);
for (i = 0; i < 10; i++)
__NOP();
SRAMC->CR = (initStruct->ClkDiv << SRAMC_CR_RWTIME_Pos) |
(initStruct->DataWidth << SRAMC_CR_BYTEIF_Pos) |
(0 << SRAMC_CR_HBLBDIS_Pos); // 使能字节、半字访问
}

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@ -1,29 +0,0 @@
#ifndef __SWM320_SRAM_H__
#define __SWM320_SRAM_H__
typedef struct
{
uint8_t ClkDiv; //SRAM_CLKDIV_5...SRAM_CLKDIV_16根据SRAM芯片所能跑的最高频率选择合适分频
uint8_t DataWidth; //SRAM_DATAWIDTH_8、SRAM_DATAWIDTH_16
} SRAM_InitStructure;
#define SRAM_CLKDIV_4 3
#define SRAM_CLKDIV_5 4
#define SRAM_CLKDIV_6 5
#define SRAM_CLKDIV_7 6
#define SRAM_CLKDIV_8 7
#define SRAM_CLKDIV_9 8
#define SRAM_CLKDIV_10 9
#define SRAM_CLKDIV_11 10
#define SRAM_CLKDIV_12 11
#define SRAM_CLKDIV_13 12
#define SRAM_CLKDIV_14 13
#define SRAM_CLKDIV_15 14
#define SRAM_CLKDIV_16 15
#define SRAM_DATAWIDTH_8 1
#define SRAM_DATAWIDTH_16 0
void SRAM_Init(SRAM_InitStructure *initStruct);
#endif //__SWM320_SRAM_H__

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@ -1,441 +0,0 @@
/******************************************************************************************************************************************
* : SWM320_timr.c
* : SWM320单片机的计数器/
* : http://www.synwit.com.cn/e/tool/gbook/?bid=1
* :
* : V1.1.0 20171025
* :
*
*
*******************************************************************************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
* -ECTION WITH THEIR PRODUCTS.
*
* COPYRIGHT 2012 Synwit Technology
*******************************************************************************************************************************************/
#include "SWM320.h"
#include "SWM320_timr.h"
/******************************************************************************************************************************************
* : TIMR_Init()
* : TIMR定时器/
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2TIMR3TIMR4TIMR5
* uint32_t mode TIMR_MODE_TIMER TIMR_MODE_COUNTER
* uint32_t period /
* uint32_t int_en 使
* :
* :
******************************************************************************************************************************************/
void TIMR_Init(TIMR_TypeDef *TIMRx, uint32_t mode, uint32_t period, uint32_t int_en)
{
SYS->CLKEN |= (0x01 << SYS_CLKEN_TIMR_Pos);
TIMR_Stop(TIMRx); //一些关键寄存器只能在定时器停止时设置
TIMRx->CTRL &= ~TIMR_CTRL_CLKSRC_Msk;
TIMRx->CTRL |= mode << TIMR_CTRL_CLKSRC_Pos;
TIMRx->LDVAL = period;
switch ((uint32_t)TIMRx)
{
case ((uint32_t)TIMR0):
TIMRG->IF = (1 << TIMRG_IF_TIMR0_Pos); //使能中断前清除中断标志
TIMRG->IE &= ~TIMRG_IE_TIMR0_Msk;
TIMRG->IE |= (int_en << TIMRG_IE_TIMR0_Pos);
if (int_en)
NVIC_EnableIRQ(TIMR0_IRQn);
break;
case ((uint32_t)TIMR1):
TIMRG->IF = (1 << TIMRG_IF_TIMR1_Pos);
TIMRG->IE &= ~TIMRG_IE_TIMR1_Msk;
TIMRG->IE |= (int_en << TIMRG_IE_TIMR1_Pos);
if (int_en)
NVIC_EnableIRQ(TIMR1_IRQn);
break;
case ((uint32_t)TIMR2):
TIMRG->IF = (1 << TIMRG_IF_TIMR2_Pos);
TIMRG->IE &= ~TIMRG_IE_TIMR2_Msk;
TIMRG->IE |= (int_en << TIMRG_IE_TIMR2_Pos);
if (int_en)
NVIC_EnableIRQ(TIMR2_IRQn);
break;
case ((uint32_t)TIMR3):
TIMRG->IF = (1 << TIMRG_IF_TIMR3_Pos);
TIMRG->IE &= ~TIMRG_IE_TIMR3_Msk;
TIMRG->IE |= (int_en << TIMRG_IE_TIMR3_Pos);
if (int_en)
NVIC_EnableIRQ(TIMR3_IRQn);
break;
case ((uint32_t)TIMR4):
TIMRG->IF = (1 << TIMRG_IF_TIMR4_Pos);
TIMRG->IE &= ~TIMRG_IE_TIMR4_Msk;
TIMRG->IE |= (int_en << TIMRG_IE_TIMR4_Pos);
if (int_en)
NVIC_EnableIRQ(TIMR4_IRQn);
break;
case ((uint32_t)TIMR5):
TIMRG->IF = (1 << TIMRG_IF_TIMR5_Pos);
TIMRG->IE &= ~TIMRG_IE_TIMR5_Msk;
TIMRG->IE |= (int_en << TIMRG_IE_TIMR5_Pos);
if (int_en)
NVIC_EnableIRQ(TIMR5_IRQn);
break;
}
}
/******************************************************************************************************************************************
* : TIMR_Start()
* : /
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2TIMR3TIMR4TIMR5
* :
* :
******************************************************************************************************************************************/
void TIMR_Start(TIMR_TypeDef *TIMRx)
{
TIMRx->CTRL |= TIMR_CTRL_EN_Msk;
}
/******************************************************************************************************************************************
* : TIMR_Stop()
* :
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2TIMR3TIMR4TIMR5
* :
* :
******************************************************************************************************************************************/
void TIMR_Stop(TIMR_TypeDef *TIMRx)
{
TIMRx->CTRL &= ~TIMR_CTRL_EN_Msk;
}
/******************************************************************************************************************************************
* : TIMR_Halt()
* :
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2TIMR3TIMR4TIMR5
* :
* :
******************************************************************************************************************************************/
void TIMR_Halt(TIMR_TypeDef *TIMRx)
{
switch ((uint32_t)TIMRx)
{
case ((uint32_t)TIMR0):
TIMRG->HALT |= (0x01 << TIMRG_HALT_TIMR0_Pos);
break;
case ((uint32_t)TIMR1):
TIMRG->HALT |= (0x01 << TIMRG_HALT_TIMR1_Pos);
break;
case ((uint32_t)TIMR2):
TIMRG->HALT |= (0x01 << TIMRG_HALT_TIMR2_Pos);
break;
case ((uint32_t)TIMR3):
TIMRG->HALT |= (0x01 << TIMRG_HALT_TIMR3_Pos);
break;
case ((uint32_t)TIMR4):
TIMRG->HALT |= (0x01 << TIMRG_HALT_TIMR4_Pos);
break;
case ((uint32_t)TIMR5):
TIMRG->HALT |= (0x01 << TIMRG_HALT_TIMR5_Pos);
break;
}
}
/******************************************************************************************************************************************
* : TIMR_Resume()
* :
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2TIMR3TIMR4TIMR5
* :
* :
******************************************************************************************************************************************/
void TIMR_Resume(TIMR_TypeDef *TIMRx)
{
switch ((uint32_t)TIMRx)
{
case ((uint32_t)TIMR0):
TIMRG->HALT &= ~(0x01 << TIMRG_HALT_TIMR0_Pos);
break;
case ((uint32_t)TIMR1):
TIMRG->HALT &= ~(0x01 << TIMRG_HALT_TIMR1_Pos);
break;
case ((uint32_t)TIMR2):
TIMRG->HALT &= ~(0x01 << TIMRG_HALT_TIMR2_Pos);
break;
case ((uint32_t)TIMR3):
TIMRG->HALT &= ~(0x01 << TIMRG_HALT_TIMR3_Pos);
break;
case ((uint32_t)TIMR4):
TIMRG->HALT &= ~(0x01 << TIMRG_HALT_TIMR4_Pos);
break;
case ((uint32_t)TIMR5):
TIMRG->HALT &= ~(0x01 << TIMRG_HALT_TIMR5_Pos);
break;
}
}
/******************************************************************************************************************************************
* : TIMR_SetPeriod()
* : /
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2TIMR3TIMR4TIMR5
* uint32_t period /
* :
* :
******************************************************************************************************************************************/
void TIMR_SetPeriod(TIMR_TypeDef *TIMRx, uint32_t period)
{
TIMRx->LDVAL = period;
}
/******************************************************************************************************************************************
* : TIMR_GetPeriod()
* : /
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2TIMR3TIMR4TIMR5
* : uint32_t /
* :
******************************************************************************************************************************************/
uint32_t TIMR_GetPeriod(TIMR_TypeDef *TIMRx)
{
return TIMRx->LDVAL;
}
/******************************************************************************************************************************************
* : TIMR_GetCurValue()
* :
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2TIMR3TIMR4TIMR5
* : uint32_t
* :
******************************************************************************************************************************************/
uint32_t TIMR_GetCurValue(TIMR_TypeDef *TIMRx)
{
return TIMRx->CVAL;
}
/******************************************************************************************************************************************
* : TIMR_INTEn()
* : 使
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2TIMR3TIMR4TIMR5
* :
* :
******************************************************************************************************************************************/
void TIMR_INTEn(TIMR_TypeDef *TIMRx)
{
switch ((uint32_t)TIMRx)
{
case ((uint32_t)TIMR0):
TIMRG->IE |= (0x01 << TIMRG_IE_TIMR0_Pos);
NVIC_EnableIRQ(TIMR0_IRQn);
break;
case ((uint32_t)TIMR1):
TIMRG->IE |= (0x01 << TIMRG_IE_TIMR1_Pos);
NVIC_EnableIRQ(TIMR1_IRQn);
break;
case ((uint32_t)TIMR2):
TIMRG->IE |= (0x01 << TIMRG_IE_TIMR2_Pos);
NVIC_EnableIRQ(TIMR2_IRQn);
break;
case ((uint32_t)TIMR3):
TIMRG->IE |= (0x01 << TIMRG_IE_TIMR3_Pos);
NVIC_EnableIRQ(TIMR3_IRQn);
break;
case ((uint32_t)TIMR4):
TIMRG->IE |= (0x01 << TIMRG_IE_TIMR4_Pos);
NVIC_EnableIRQ(TIMR4_IRQn);
break;
case ((uint32_t)TIMR5):
TIMRG->IE |= (0x01 << TIMRG_IE_TIMR5_Pos);
NVIC_EnableIRQ(TIMR5_IRQn);
break;
}
}
/******************************************************************************************************************************************
* : TIMR_INTDis()
* :
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2TIMR3TIMR4TIMR5
* :
* :
******************************************************************************************************************************************/
void TIMR_INTDis(TIMR_TypeDef *TIMRx)
{
switch ((uint32_t)TIMRx)
{
case ((uint32_t)TIMR0):
TIMRG->IE &= ~(0x01 << TIMRG_IE_TIMR0_Pos);
break;
case ((uint32_t)TIMR1):
TIMRG->IE &= ~(0x01 << TIMRG_IE_TIMR1_Pos);
break;
case ((uint32_t)TIMR2):
TIMRG->IE &= ~(0x01 << TIMRG_IE_TIMR2_Pos);
break;
case ((uint32_t)TIMR3):
TIMRG->IE &= ~(0x01 << TIMRG_IE_TIMR3_Pos);
break;
case ((uint32_t)TIMR4):
TIMRG->IE &= ~(0x01 << TIMRG_IE_TIMR4_Pos);
break;
case ((uint32_t)TIMR5):
TIMRG->IE &= ~(0x01 << TIMRG_IE_TIMR5_Pos);
break;
}
}
/******************************************************************************************************************************************
* : TIMR_INTClr()
* :
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2TIMR3TIMR4TIMR5
* :
* :
******************************************************************************************************************************************/
void TIMR_INTClr(TIMR_TypeDef *TIMRx)
{
switch ((uint32_t)TIMRx)
{
case ((uint32_t)TIMR0):
TIMRG->IF = (0x01 << TIMRG_IF_TIMR0_Pos);
break;
case ((uint32_t)TIMR1):
TIMRG->IF = (0x01 << TIMRG_IF_TIMR1_Pos);
break;
case ((uint32_t)TIMR2):
TIMRG->IF = (0x01 << TIMRG_IF_TIMR2_Pos);
break;
case ((uint32_t)TIMR3):
TIMRG->IF = (0x01 << TIMRG_IF_TIMR3_Pos);
break;
case ((uint32_t)TIMR4):
TIMRG->IF = (0x01 << TIMRG_IF_TIMR4_Pos);
break;
case ((uint32_t)TIMR5):
TIMRG->IF = (0x01 << TIMRG_IF_TIMR5_Pos);
break;
}
}
/******************************************************************************************************************************************
* : TIMR_INTStat()
* :
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2TIMR3TIMR4TIMR5
* : uint32_t 0 TIMRx未产生中断 1 TIMRx产生了中断
* :
******************************************************************************************************************************************/
uint32_t TIMR_INTStat(TIMR_TypeDef *TIMRx)
{
switch ((uint32_t)TIMRx)
{
case ((uint32_t)TIMR0):
return (TIMRG->IF & TIMRG_IF_TIMR0_Msk) ? 1 : 0;
case ((uint32_t)TIMR1):
return (TIMRG->IF & TIMRG_IF_TIMR1_Msk) ? 1 : 0;
case ((uint32_t)TIMR2):
return (TIMRG->IF & TIMRG_IF_TIMR2_Msk) ? 1 : 0;
case ((uint32_t)TIMR3):
return (TIMRG->IF & TIMRG_IF_TIMR3_Msk) ? 1 : 0;
case ((uint32_t)TIMR4):
return (TIMRG->IF & TIMRG_IF_TIMR4_Msk) ? 1 : 0;
case ((uint32_t)TIMR5):
return (TIMRG->IF & TIMRG_IF_TIMR5_Msk) ? 1 : 0;
}
return 0;
}
/******************************************************************************************************************************************
* : Pulse_Init()
* :
* : uint32_t pulse PULSE_LOW PULSE_HIGH
* uint32_t int_en 使
* :
* :
******************************************************************************************************************************************/
void Pulse_Init(uint32_t pulse, uint32_t int_en)
{
SYS->CLKEN |= (0x01 << SYS_CLKEN_TIMR_Pos);
TIMRG->PCTRL = (0 << TIMRG_PCTRL_CLKSRC_Pos) | // 系统时钟作为时钟源
(pulse << TIMRG_PCTRL_HIGH_Pos) |
(0 << TIMRG_PCTRL_EN_Pos);
TIMRG->IE |= (1 << TIMRG_IE_PULSE_Pos); //使能才能查询中断标志
if (int_en)
NVIC_EnableIRQ(PULSE_IRQn);
}
/******************************************************************************************************************************************
* : Pulse_Start()
* :
* :
* :
* :
******************************************************************************************************************************************/
void Pulse_Start(void)
{
TIMRG->PCTRL |= (1 << TIMRG_PCTRL_EN_Pos);
}
/******************************************************************************************************************************************
* : Pulse_Done()
* :
* :
* : uint32_t 1 0
* :
******************************************************************************************************************************************/
uint32_t Pulse_Done(void)
{
if (TIMRG->IF & TIMRG_IF_PULSE_Msk)
{
TIMRG->IF = TIMRG_IF_PULSE_Msk; // 清除中断标志
return 1;
}
else
{
return 0;
}
}

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@ -1,29 +0,0 @@
#ifndef __SWM320_TIMR_H__
#define __SWM320_TIMR_H__
#define TIMR_MODE_TIMER 0
#define TIMR_MODE_COUNTER 1
void TIMR_Init(TIMR_TypeDef *TIMRx, uint32_t mode, uint32_t period, uint32_t int_en); //定时器/计数器初始化
void TIMR_Start(TIMR_TypeDef *TIMRx); //启动定时器,从初始值开始计时/计数
void TIMR_Stop(TIMR_TypeDef *TIMRx); //停止定时器
void TIMR_Halt(TIMR_TypeDef *TIMRx); //暂停定时器,计数值保持不变
void TIMR_Resume(TIMR_TypeDef *TIMRx); //恢复定时器,从暂停处继续计数
void TIMR_SetPeriod(TIMR_TypeDef *TIMRx, uint32_t period); //设置定时/计数周期
uint32_t TIMR_GetPeriod(TIMR_TypeDef *TIMRx); //获取定时/计数周期
uint32_t TIMR_GetCurValue(TIMR_TypeDef *TIMRx); //获取当前计数值
void TIMR_INTEn(TIMR_TypeDef *TIMRx); //使能中断
void TIMR_INTDis(TIMR_TypeDef *TIMRx); //禁能中断
void TIMR_INTClr(TIMR_TypeDef *TIMRx); //清除中断标志
uint32_t TIMR_INTStat(TIMR_TypeDef *TIMRx); //获取中断状态
#define PULSE_LOW 0
#define PULSE_HIGH 1
void Pulse_Init(uint32_t pulse, uint32_t int_en);
void Pulse_Start(void);
uint32_t Pulse_Done(void);
#endif //__SWM320_TIMR_H__

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@ -1,567 +0,0 @@
/******************************************************************************************************************************************
* : SWM320_uart.c
* : SWM320单片机的UART串口功能驱动库
* : http://www.synwit.com.cn/e/tool/gbook/?bid=1
* : LIN功能相关的函数
* : V1.1.0 20171025
* :
*
*
*******************************************************************************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
* -ECTION WITH THEIR PRODUCTS.
*
* COPYRIGHT 2012 Synwit Technology
*******************************************************************************************************************************************/
#include "SWM320.h"
#include "SWM320_uart.h"
/******************************************************************************************************************************************
* : UART_Init()
* : UART串口初始化
* : UART_TypeDef * UARTx UART串口UART0UART1UART2UART3
* UART_InitStructure * initStruct UART串口相关设定值的结构体
* :
* :
******************************************************************************************************************************************/
void UART_Init(UART_TypeDef *UARTx, UART_InitStructure *initStruct)
{
switch ((uint32_t)UARTx)
{
case ((uint32_t)UART0):
SYS->CLKEN |= (0x01 << SYS_CLKEN_UART0_Pos);
break;
case ((uint32_t)UART1):
SYS->CLKEN |= (0x01 << SYS_CLKEN_UART1_Pos);
break;
case ((uint32_t)UART2):
SYS->CLKEN |= (0x01 << SYS_CLKEN_UART2_Pos);
break;
case ((uint32_t)UART3):
SYS->CLKEN |= (0x01 << SYS_CLKEN_UART3_Pos);
break;
}
UART_Close(UARTx); //一些关键寄存器只能在串口关闭时设置
UARTx->CTRL |= (0x01 << UART_CTRL_BAUDEN_Pos);
UARTx->BAUD &= ~UART_BAUD_BAUD_Msk;
UARTx->BAUD |= ((SystemCoreClock / 16 / initStruct->Baudrate - 1) << UART_BAUD_BAUD_Pos);
UARTx->CTRL &= ~(UART_CTRL_DATA9b_Msk | UART_CTRL_PARITY_Msk | UART_CTRL_STOP2b_Msk);
UARTx->CTRL |= (initStruct->DataBits << UART_CTRL_DATA9b_Pos) |
(initStruct->Parity << UART_CTRL_PARITY_Pos) |
(initStruct->StopBits << UART_CTRL_STOP2b_Pos);
/* 在SWM320中当 RXLVL >= RXTHR 时触发中断如果RXTHR设置为0的话在未接收到数据时就会一直触发中断
RXLVL > RXTHR SWM320中RXTHR不能为0的问题APIRXTHR设置值加一
*/
switch ((uint32_t)UARTx) // 软件复位不能清零 NVIC 寄存器,若不手动清除,下面的代码清零 RXTHR 时会导致一直进入 ISR
{
case ((uint32_t)UART0):
NVIC_DisableIRQ(UART0_IRQn);
break;
case ((uint32_t)UART1):
NVIC_DisableIRQ(UART1_IRQn);
break;
case ((uint32_t)UART2):
NVIC_DisableIRQ(UART2_IRQn);
break;
case ((uint32_t)UART3):
NVIC_DisableIRQ(UART3_IRQn);
break;
}
UARTx->FIFO &= ~(UART_FIFO_RXTHR_Msk | UART_FIFO_TXTHR_Msk);
UARTx->FIFO |= ((initStruct->RXThreshold + 1) << UART_FIFO_RXTHR_Pos) |
(initStruct->TXThreshold << UART_FIFO_TXTHR_Pos);
UARTx->CTRL &= ~UART_CTRL_TOTIME_Msk;
UARTx->CTRL |= (initStruct->TimeoutTime << UART_CTRL_TOTIME_Pos);
UARTx->CTRL &= ~(UART_CTRL_RXIE_Msk | UART_CTRL_TXIE_Msk | UART_CTRL_TOIE_Msk);
UARTx->CTRL |= (initStruct->RXThresholdIEn << UART_CTRL_RXIE_Pos) |
(initStruct->TXThresholdIEn << UART_CTRL_TXIE_Pos) |
(initStruct->TimeoutIEn << UART_CTRL_TOIE_Pos);
switch ((uint32_t)UARTx)
{
case ((uint32_t)UART0):
if (initStruct->RXThresholdIEn | initStruct->TXThresholdIEn | initStruct->TimeoutIEn)
{
NVIC_EnableIRQ(UART0_IRQn);
}
else
{
NVIC_DisableIRQ(UART0_IRQn);
}
break;
case ((uint32_t)UART1):
if (initStruct->RXThresholdIEn | initStruct->TXThresholdIEn | initStruct->TimeoutIEn)
{
NVIC_EnableIRQ(UART1_IRQn);
}
else
{
NVIC_DisableIRQ(UART1_IRQn);
}
break;
case ((uint32_t)UART2):
if (initStruct->RXThresholdIEn | initStruct->TXThresholdIEn | initStruct->TimeoutIEn)
{
NVIC_EnableIRQ(UART2_IRQn);
}
else
{
NVIC_DisableIRQ(UART2_IRQn);
}
break;
case ((uint32_t)UART3):
if (initStruct->RXThresholdIEn | initStruct->TXThresholdIEn | initStruct->TimeoutIEn)
{
NVIC_EnableIRQ(UART3_IRQn);
}
else
{
NVIC_DisableIRQ(UART3_IRQn);
}
break;
}
}
/******************************************************************************************************************************************
* : UART_Open()
* : UART串口打开
* : UART_TypeDef * UARTx UART串口UART0UART1UART2UART3
* :
* :
******************************************************************************************************************************************/
void UART_Open(UART_TypeDef *UARTx)
{
UARTx->CTRL |= (0x01 << UART_CTRL_EN_Pos);
}
/******************************************************************************************************************************************
* : UART_Close()
* : UART串口关闭
* : UART_TypeDef * UARTx UART串口UART0UART1UART2UART3
* :
* :
******************************************************************************************************************************************/
void UART_Close(UART_TypeDef *UARTx)
{
UARTx->CTRL &= ~(0x01 << UART_CTRL_EN_Pos);
}
/******************************************************************************************************************************************
* : UART_WriteByte()
* :
* : UART_TypeDef * UARTx UART串口UART0UART1UART2UART3UART4
* uint32_t data
* :
* :
******************************************************************************************************************************************/
void UART_WriteByte(UART_TypeDef *UARTx, uint32_t data)
{
UARTx->DATA = data;
}
/******************************************************************************************************************************************
* : UART_ReadByte()
* : Valid
* : UART_TypeDef * UARTx UART串口UART0UART1UART2UART3UART4
* uint32_t * data
* : uint32_t 0 UART_ERR_PARITY
* :
******************************************************************************************************************************************/
uint32_t UART_ReadByte(UART_TypeDef *UARTx, uint32_t *data)
{
uint32_t reg = UARTx->DATA;
*data = (reg & UART_DATA_DATA_Msk);
if (reg & UART_DATA_PAERR_Msk)
return UART_ERR_PARITY;
return 0;
}
/******************************************************************************************************************************************
* : UART_IsTXBusy()
* : UART是否正在发送数据
* : UART_TypeDef * UARTx UART串口UART0UART1UART2UART3
* : uint32_t 1 UART正在发送数据 0
* :
******************************************************************************************************************************************/
uint32_t UART_IsTXBusy(UART_TypeDef *UARTx)
{
return (UARTx->CTRL & UART_CTRL_TXIDLE_Msk) ? 0 : 1;
}
/******************************************************************************************************************************************
* : UART_IsRXFIFOEmpty()
* : FIFO是否为空
* : UART_TypeDef * UARTx UART串口UART0UART1UART2UART3
* : uint32_t 1 FIFO空 0 FIFO非空
* :
******************************************************************************************************************************************/
uint32_t UART_IsRXFIFOEmpty(UART_TypeDef *UARTx)
{
return (UARTx->CTRL & UART_CTRL_RXNE_Msk) ? 0 : 1;
}
/******************************************************************************************************************************************
* : UART_IsTXFIFOFull()
* : FIFO是否为满
* : UART_TypeDef * UARTx UART串口UART0UART1UART2UART3
* : uint32_t 1 FIFO满 0 FIFO不满
* :
******************************************************************************************************************************************/
uint32_t UART_IsTXFIFOFull(UART_TypeDef *UARTx)
{
return (UARTx->CTRL & UART_CTRL_TXFF_Msk) ? 1 : 0;
}
/******************************************************************************************************************************************
* : UART_SetBaudrate()
* :
* : UART_TypeDef * UARTx UART串口UART0UART1UART2UART3
* uint32_t baudrate
* :
* : 使UART_Close()
******************************************************************************************************************************************/
void UART_SetBaudrate(UART_TypeDef *UARTx, uint32_t baudrate)
{
UARTx->BAUD &= ~UART_BAUD_BAUD_Msk;
UARTx->BAUD |= ((SystemCoreClock / 16 / baudrate - 1) << UART_BAUD_BAUD_Pos);
}
/******************************************************************************************************************************************
* : UART_GetBaudrate()
* :
* : UART_TypeDef * UARTx UART串口UART0UART1UART2UART3
* : uint32_t
* :
******************************************************************************************************************************************/
uint32_t UART_GetBaudrate(UART_TypeDef *UARTx)
{
return SystemCoreClock / 16 / (((UARTx->BAUD & UART_BAUD_BAUD_Msk) >> UART_BAUD_BAUD_Pos) + 1);
}
/******************************************************************************************************************************************
* : UART_CTSConfig()
* : UART CTS流控配置
* : UART_TypeDef * UARTx UART串口UART0UART1UART2UART3
* uint32_t enable 1 使CTS流控 0 CTS流控
* uint32_t polarity 0 CTS输入为低表示可以发送数据 1 CTS输入为高表示可以发送数据
* :
* :
******************************************************************************************************************************************/
void UART_CTSConfig(UART_TypeDef *UARTx, uint32_t enable, uint32_t polarity)
{
UARTx->CTSCR &= ~(UART_CTSCR_EN_Msk | UART_CTSCR_POL_Msk);
UARTx->CTSCR |= (enable << UART_CTSCR_EN_Pos) |
(polarity << UART_CTSCR_POL_Pos);
}
/******************************************************************************************************************************************
* : UART_CTSLineState()
* : UART CTS线当前状态
* : UART_TypeDef * UARTx UART串口UART0UART1UART2UART3
* : uint32_t 0 CTS线当前为低电平 1 CTS线当前为高电平
* :
******************************************************************************************************************************************/
uint32_t UART_CTSLineState(UART_TypeDef *UARTx)
{
return (UARTx->CTSCR & UART_CTSCR_STAT_Msk) ? 1 : 0;
}
/******************************************************************************************************************************************
* : UART_RTSConfig()
* : UART RTS流控配置
* : UART_TypeDef * UARTx UART串口UART0UART1UART2UART3
* uint32_t enable 1 使RTS流控 0 RTS流控
* uint32_t polarity 0 RTS输出低表示可以接收数据 1 RTS输出高表示可以接收数据
* uint32_t threshold RTS流控的触发阈值UART_RTS_1BYTEUART_RTS_2BYTEUART_RTS_4BYTEUART_RTS_6BYTE
* :
* :
******************************************************************************************************************************************/
void UART_RTSConfig(UART_TypeDef *UARTx, uint32_t enable, uint32_t polarity, uint32_t threshold)
{
UARTx->RTSCR &= ~(UART_RTSCR_EN_Msk | UART_RTSCR_POL_Msk | UART_RTSCR_THR_Msk);
UARTx->RTSCR |= (enable << UART_RTSCR_EN_Pos) |
(polarity << UART_RTSCR_POL_Pos) |
(threshold << UART_RTSCR_THR_Pos);
}
/******************************************************************************************************************************************
* : UART_RTSLineState()
* : UART RTS线当前状态
* : UART_TypeDef * UARTx UART串口UART0UART1UART2UART3
* : uint32_t 0 RTS线当前为低电平 1 RTS线当前为高电平
* :
******************************************************************************************************************************************/
uint32_t UART_RTSLineState(UART_TypeDef *UARTx)
{
return (UARTx->RTSCR & UART_RTSCR_STAT_Msk) ? 1 : 0;
}
/******************************************************************************************************************************************
* : UART_LINConfig()
* : UART LIN功能配置
* : UART_TypeDef * UARTx UART串口UART0UART1UART2UART3
* uint32_t detectedIEn Break中断使能
* uint32_t generatedIEn Break发送完成中断使能
* :
* :
******************************************************************************************************************************************/
void UART_LINConfig(UART_TypeDef *UARTx, uint32_t detectedIEn, uint32_t generatedIEn)
{
UARTx->LINCR &= ~(UART_LINCR_BRKDETIE_Msk | UART_LINCR_GENBRKIE_Msk);
UARTx->LINCR |= (detectedIEn << UART_LINCR_BRKDETIE_Pos) |
(generatedIEn << UART_LINCR_GENBRKIE_Pos);
}
/******************************************************************************************************************************************
* : UART_LINGenerate()
* : UART LIN产生/Break
* : UART_TypeDef * UARTx UART串口UART0UART1UART2UART3
* :
* :
******************************************************************************************************************************************/
void UART_LINGenerate(UART_TypeDef *UARTx)
{
UARTx->LINCR |= (1 << UART_LINCR_GENBRK_Pos);
}
/******************************************************************************************************************************************
* : UART_LINIsDetected()
* : UART LIN是否检测到Break
* : UART_TypeDef * UARTx UART串口UART0UART1UART2UART3
* : uint32_t 1 LIN Break 0 LIN Break
* :
******************************************************************************************************************************************/
uint32_t UART_LINIsDetected(UART_TypeDef *UARTx)
{
return (UARTx->LINCR & UART_LINCR_BRKDETIF_Msk) ? 1 : 0;
}
/******************************************************************************************************************************************
* : UART_LINIsGenerated()
* : UART LIN Break是否发送完成
* : UART_TypeDef * UARTx UART串口UART0UART1UART2UART3
* : uint32_t 1 LIN Break 0 LIN Break发送未完成
* :
******************************************************************************************************************************************/
uint32_t UART_LINIsGenerated(UART_TypeDef *UARTx)
{
return (UARTx->LINCR & UART_LINCR_GENBRKIF_Msk) ? 1 : 0;
}
/******************************************************************************************************************************************
* : UART_ABRStart()
* : UART
* : UART_TypeDef * UARTx UART串口UART0UART1UART2UART3
* uint32_t detectChar
* 80xFF0xFE0xF80x800xFF0xFE0xF80x80
* 90x1FF0x1FE0x1F80x1800x1FF0x1FE0x1F80x180
* :
* :
******************************************************************************************************************************************/
void UART_ABRStart(UART_TypeDef *UARTx, uint32_t detectChar)
{
uint32_t bits;
if ((detectChar == 0xFF) || (detectChar == 0x1FF))
bits = 0;
else if ((detectChar == 0xFE) || (detectChar == 0x1FE))
bits = 1;
else if ((detectChar == 0xF8) || (detectChar == 0x1F8))
bits = 2;
else if ((detectChar == 0x80) || (detectChar == 0x180))
bits = 3;
else
while (1)
;
UARTx->BAUD &= ~(UART_BAUD_ABREN_Msk | UART_BAUD_ABRBIT_Msk);
UARTx->BAUD |= (1 << UART_BAUD_ABREN_Pos) |
(bits << UART_BAUD_ABRBIT_Pos);
}
/******************************************************************************************************************************************
* : UART_ABRIsDone()
* : UART
* : UART_TypeDef * UARTx UART串口UART0UART1UART2UART3
* : uint32_t 0 UART_ABR_RES_OK UART_ABR_RES_ERR
* :
******************************************************************************************************************************************/
uint32_t UART_ABRIsDone(UART_TypeDef *UARTx)
{
if (UARTx->BAUD & UART_BAUD_ABREN_Msk)
{
return 0;
}
else if (UARTx->BAUD & UART_BAUD_ABRERR_Msk)
{
return UART_ABR_RES_ERR;
}
else
{
return UART_ABR_RES_OK;
}
}
/******************************************************************************************************************************************
* : UART_INTRXThresholdEn()
* : RX FIFO中数据个数 >= RXThreshold时
* : UART_TypeDef * UARTx UART串口UART0UART1UART2UART3
* :
* :
******************************************************************************************************************************************/
void UART_INTRXThresholdEn(UART_TypeDef *UARTx)
{
UARTx->CTRL |= (0x01 << UART_CTRL_RXIE_Pos);
}
/******************************************************************************************************************************************
* : UART_INTRXThresholdDis()
* : RX FIFO中数据个数 >= RXThreshold时
* : UART_TypeDef * UARTx UART串口UART0UART1UART2UART3
* :
* :
******************************************************************************************************************************************/
void UART_INTRXThresholdDis(UART_TypeDef *UARTx)
{
UARTx->CTRL &= ~(0x01 << UART_CTRL_RXIE_Pos);
}
/******************************************************************************************************************************************
* : UART_INTRXThresholdStat()
* : RX FIFO中数据个数 >= RXThreshold
* : UART_TypeDef * UARTx UART串口UART0UART1UART2UART3
* : uint32_t 1 RX FIFO中数据个数 >= RXThreshold 0 RX FIFO中数据个数 < RXThreshold
* : RXIF = RXTHRF & RXIE
******************************************************************************************************************************************/
uint32_t UART_INTRXThresholdStat(UART_TypeDef *UARTx)
{
return (UARTx->BAUD & UART_BAUD_RXIF_Msk) ? 1 : 0;
}
/******************************************************************************************************************************************
* : UART_INTTXThresholdEn()
* : TX FIFO中数据个数 <= TXThreshold时
* : UART_TypeDef * UARTx UART串口UART0UART1UART2UART3
* :
* :
******************************************************************************************************************************************/
void UART_INTTXThresholdEn(UART_TypeDef *UARTx)
{
UARTx->CTRL |= (0x01 << UART_CTRL_TXIE_Pos);
}
/******************************************************************************************************************************************
* : UART_INTTXThresholdDis()
* : TX FIFO中数据个数 <= TXThreshold时
* : UART_TypeDef * UARTx UART串口UART0UART1UART2UART3
* :
* :
******************************************************************************************************************************************/
void UART_INTTXThresholdDis(UART_TypeDef *UARTx)
{
UARTx->CTRL &= ~(0x01 << UART_CTRL_TXIE_Pos);
}
/******************************************************************************************************************************************
* : UART_INTTXThresholdStat()
* : TX FIFO中数据个数 <= TXThreshold
* : UART_TypeDef * UARTx UART串口UART0UART1UART2UART3
* : uint32_t 1 TX FIFO中数据个数 <= TXThreshold 0 TX FIFO中数据个数 > TXThreshold
* : TXIF = TXTHRF & TXIE
******************************************************************************************************************************************/
uint32_t UART_INTTXThresholdStat(UART_TypeDef *UARTx)
{
return (UARTx->BAUD & UART_BAUD_TXIF_Msk) ? 1 : 0;
}
/******************************************************************************************************************************************
* : UART_INTTimeoutEn()
* :
* : UART_TypeDef * UARTx UART串口UART0UART1UART2UART3
* :
* :
******************************************************************************************************************************************/
void UART_INTTimeoutEn(UART_TypeDef *UARTx)
{
UARTx->CTRL |= (0x01 << UART_CTRL_TOIE_Pos);
}
/******************************************************************************************************************************************
* : UART_INTTimeoutDis()
* :
* : UART_TypeDef * UARTx UART串口UART0UART1UART2UART3
* :
* :
******************************************************************************************************************************************/
void UART_INTTimeoutDis(UART_TypeDef *UARTx)
{
UARTx->CTRL &= ~(0x01 << UART_CTRL_TOIE_Pos);
}
/******************************************************************************************************************************************
* : UART_INTTimeoutStat()
* : TimeoutTime/(Baudrate/10) RX线上接收到数据时触发中断
* : UART_TypeDef * UARTx UART串口UART0UART1UART2UART3
* : uint32_t 1 0
* :
******************************************************************************************************************************************/
uint32_t UART_INTTimeoutStat(UART_TypeDef *UARTx)
{
return (UARTx->BAUD & UART_BAUD_TOIF_Msk) ? 1 : 0;
}
/******************************************************************************************************************************************
* : UART_INTTXDoneEn()
* : FIFO空且发送移位寄存器空中断使能
* : UART_TypeDef * UARTx UART串口UART0UART1UART2UART3
* :
* :
******************************************************************************************************************************************/
void UART_INTTXDoneEn(UART_TypeDef *UARTx)
{
UARTx->CTRL |= (0x01 << UART_CTRL_TXDOIE_Pos);
}
/******************************************************************************************************************************************
* : UART_INTTXDoneDis()
* : FIFO空且发送移位寄存器空中断禁止
* : UART_TypeDef * UARTx UART串口UART0UART1UART2UART3
* :
* :
******************************************************************************************************************************************/
void UART_INTTXDoneDis(UART_TypeDef *UARTx)
{
UARTx->CTRL &= ~(0x01 << UART_CTRL_TXDOIE_Pos);
}
/******************************************************************************************************************************************
* : UART_INTTXDoneStat()
* : FIFO空且发送移位寄存器空中断状态
* : UART_TypeDef * UARTx UART串口UART0UART1UART2UART3
* : uint32_t 1 FIFO空且发送移位寄存器空 0 FIFO或发送移位寄存器未空
* :
******************************************************************************************************************************************/
uint32_t UART_INTTXDoneStat(UART_TypeDef *UARTx)
{
return (UARTx->BAUD & UART_BAUD_TXDOIF_Msk) ? 1 : 0;
}

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@ -1,90 +0,0 @@
#ifndef __SWM320_UART_H__
#define __SWM320_UART_H__
typedef struct
{
uint32_t Baudrate;
uint8_t DataBits; //数据位位数可取值UART_DATA_8BIT、UART_DATA_9BIT
uint8_t Parity; //奇偶校验位可取值UART_PARITY_NONE、UART_PARITY_ODD、UART_PARITY_EVEN、UART_PARITY_ONE、UART_PARITY_ZERO
uint8_t StopBits; //停止位位数可取值UART_STOP_1BIT、UART_STOP_2BIT
uint8_t RXThreshold; //取值0--7
uint8_t RXThresholdIEn; //当RX FIFO中数据个数 > RXThreshold时触发中断
uint8_t TXThreshold; //取值0--7
uint8_t TXThresholdIEn; //当TX FIFO中数据个数 <= TXThreshold时触发中断
uint8_t TimeoutTime; //超时时长 = TimeoutTime/(Baudrate/10) 秒
uint8_t TimeoutIEn; //超时中断RX FIFO非空且超过 TimeoutTime/(Baudrate/10) 秒没有在RX线上接收到数据时触发中断
} UART_InitStructure;
#define UART_DATA_8BIT 0
#define UART_DATA_9BIT 1
#define UART_PARITY_NONE 0
#define UART_PARITY_ODD 1
#define UART_PARITY_EVEN 3
#define UART_PARITY_ONE 5
#define UART_PARITY_ZERO 7
#define UART_STOP_1BIT 0
#define UART_STOP_2BIT 1
#define UART_RTS_1BYTE 0
#define UART_RTS_2BYTE 1
#define UART_RTS_4BYTE 2
#define UART_RTS_6BYTE 3
#define UART_ABR_RES_OK 1
#define UART_ABR_RES_ERR 2
#define UART_ERR_FRAME 1
#define UART_ERR_PARITY 2
#define UART_ERR_NOISE 3
void UART_Init(UART_TypeDef *UARTx, UART_InitStructure *initStruct); //UART串口初始化
void UART_Open(UART_TypeDef *UARTx);
void UART_Close(UART_TypeDef *UARTx);
void UART_WriteByte(UART_TypeDef *UARTx, uint32_t data); //发送一个字节数据
uint32_t UART_ReadByte(UART_TypeDef *UARTx, uint32_t *data); //读取一个字节数据并指出数据是否Valid
uint32_t UART_IsTXBusy(UART_TypeDef *UARTx);
uint32_t UART_IsRXFIFOEmpty(UART_TypeDef *UARTx); //接收FIFO是否空如果不空则可以继续UART_ReadByte()
uint32_t UART_IsTXFIFOFull(UART_TypeDef *UARTx); //发送FIFO是否满如果不满则可以继续UART_WriteByte()
void UART_SetBaudrate(UART_TypeDef *UARTx, uint32_t baudrate); //设置波特率
uint32_t UART_GetBaudrate(UART_TypeDef *UARTx); //获取当前使用的波特率
void UART_CTSConfig(UART_TypeDef *UARTx, uint32_t enable, uint32_t polarity);
uint32_t UART_CTSLineState(UART_TypeDef *UARTx);
void UART_RTSConfig(UART_TypeDef *UARTx, uint32_t enable, uint32_t polarity, uint32_t threshold);
uint32_t UART_RTSLineState(UART_TypeDef *UARTx);
void UART_LINConfig(UART_TypeDef *UARTx, uint32_t detectedIEn, uint32_t generatedIEn);
void UART_LINGenerate(UART_TypeDef *UARTx);
uint32_t UART_LINIsDetected(UART_TypeDef *UARTx);
uint32_t UART_LINIsGenerated(UART_TypeDef *UARTx);
void UART_ABRStart(UART_TypeDef *UARTx, uint32_t detectChar);
uint32_t UART_ABRIsDone(UART_TypeDef *UARTx);
void UART_INTRXThresholdEn(UART_TypeDef *UARTx);
void UART_INTRXThresholdDis(UART_TypeDef *UARTx);
uint32_t UART_INTRXThresholdStat(UART_TypeDef *UARTx);
void UART_INTTXThresholdEn(UART_TypeDef *UARTx);
void UART_INTTXThresholdDis(UART_TypeDef *UARTx);
uint32_t UART_INTTXThresholdStat(UART_TypeDef *UARTx);
void UART_INTTimeoutEn(UART_TypeDef *UARTx);
void UART_INTTimeoutDis(UART_TypeDef *UARTx);
uint32_t UART_INTTimeoutStat(UART_TypeDef *UARTx);
void UART_INTTXDoneEn(UART_TypeDef *UARTx);
void UART_INTTXDoneDis(UART_TypeDef *UARTx);
uint32_t UART_INTTXDoneStat(UART_TypeDef *UARTx);
#endif //__SWM320_UART_H__

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@ -1,127 +0,0 @@
/******************************************************************************************************************************************
* : SWM320_wdt.c
* : SWM320单片机的WDT看门狗功能驱动库
* : http://www.synwit.com.cn/e/tool/gbook/?bid=1
* :
* : V1.1.0 20171025
* :
*
*
*******************************************************************************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
* -ECTION WITH THEIR PRODUCTS.
*
* COPYRIGHT 2012 Synwit Technology
*******************************************************************************************************************************************/
#include "SWM320.h"
#include "SWM320_wdt.h"
/******************************************************************************************************************************************
* : WDT_Init()
* : WDT看门狗初始化
* : WDT_TypeDef * WDTx WDT
* uint32_t peroid 0--4294967295
* uint32_t mode WDT_MODE_RESET WDT_MODE_INTERRUPT
* :
* :
******************************************************************************************************************************************/
void WDT_Init(WDT_TypeDef *WDTx, uint32_t peroid, uint32_t mode)
{
SYS->CLKEN |= (0x01 << SYS_CLKEN_WDT_Pos);
WDT_Stop(WDTx); //设置前先关闭
if (mode == WDT_MODE_RESET)
{
WDTx->LOAD = peroid / 2; //第一个计数周期置位中断标志、第二个计数周期将芯片复位
NVIC_DisableIRQ(WDT_IRQn);
WDTx->CR |= (1 << WDT_CR_RSTEN_Pos);
}
else //mode == WDT_MODE_INTERRUPT
{
WDTx->LOAD = peroid;
NVIC_EnableIRQ(WDT_IRQn);
WDTx->CR &= ~(1 << WDT_CR_RSTEN_Pos);
}
}
/******************************************************************************************************************************************
* : WDT_Start()
* : WDT
* : WDT_TypeDef * WDTx WDT
* :
* :
******************************************************************************************************************************************/
void WDT_Start(WDT_TypeDef *WDTx)
{
WDTx->CR |= (0x01 << WDT_CR_EN_Pos);
}
/******************************************************************************************************************************************
* : WDT_Stop()
* : WDT
* : WDT_TypeDef * WDTx WDT
* :
* :
******************************************************************************************************************************************/
void WDT_Stop(WDT_TypeDef *WDTx)
{
WDTx->CR &= ~(0x01 << WDT_CR_EN_Pos);
}
/******************************************************************************************************************************************
* : WDT_Feed()
* :
* : WDT_TypeDef * WDTx WDT
* :
* :
******************************************************************************************************************************************/
void WDT_Feed(WDT_TypeDef *WDTx)
{
WDTx->FEED = 0x55;
}
/******************************************************************************************************************************************
* : WDT_GetValue()
* :
* : WDT_TypeDef * WDTx WDT
* : int32_t
* :
******************************************************************************************************************************************/
int32_t WDT_GetValue(WDT_TypeDef *WDTx)
{
return WDTx->VALUE;
}
/******************************************************************************************************************************************
* : WDT_INTClr()
* :
* : WDT_TypeDef * WDTx WDT
* :
* :
******************************************************************************************************************************************/
void WDT_INTClr(WDT_TypeDef *WDTx)
{
WDTx->IF = 1;
}
/******************************************************************************************************************************************
* : WDT_INTStat()
* :
* : WDT_TypeDef * WDTx WDT
* : int32_t 1 0
* :
******************************************************************************************************************************************/
uint32_t WDT_INTStat(WDT_TypeDef *WDTx)
{
return WDTx->IF;
}

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@ -1,18 +0,0 @@
#ifndef __SWM320_WDT_H__
#define __SWM320_WDT_H__
#define WDT_MODE_RESET 0
#define WDT_MODE_INTERRUPT 1
void WDT_Init(WDT_TypeDef *WDTx, uint32_t peroid, uint32_t mode); //WDT看门狗初始化
void WDT_Start(WDT_TypeDef *WDTx); //启动指定WDT开始倒计时
void WDT_Stop(WDT_TypeDef *WDTx); //关闭指定WDT停止倒计时
void WDT_Feed(WDT_TypeDef *WDTx); //喂狗,重新从装载值开始倒计时
int32_t WDT_GetValue(WDT_TypeDef *WDTx); //获取指定看门狗定时器的当前倒计时值
void WDT_INTClr(WDT_TypeDef *WDTx); //中断标志清除
uint32_t WDT_INTStat(WDT_TypeDef *WDTx); //中断状态查询
#endif //__SWM320_WDT_H__

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@ -1,118 +0,0 @@
# SWXT-LQ100-32102 V1.1 板级支持包 说明
标签: SYNWIT、Cortex-M4、SWM320VET7、国产MCU
---
## 1. 简介
本文档为 SWXT-LQ100-32102 V1.1 的 BSP(板级支持包) 说明。
通过阅读本文档,开发者可以快速地上手该 BSP将 RT-Thread 运行在开发板上。
### 1.1 开发板介绍
SWXT-LQ100-32102 V1.1 开发板由华芯微特提供,可满足基础测试及高端开发需求。
开发板外观如下图所示:
SWXT_LQ100-32102 V1.1
![SWXT-LQ100-32102](figures/SWXT-LQ100-32102.jpg "SWXT-LQ100-32102 V1.1")
SWXT-LQ100-32102 V1.1 开发板板载资源如下:
- MCUSWM320VET7-50 ARM 32-bit Cortex-M4主频 120MHz512KB FLASH 128KB SRAM2.23.6V
- 常用外设
- LED1 个D2 红绿蓝三色LED
- 按键3 个K1、K2、K3
- Nor Flash S29GL128M
- SRAM IS62WV51216BLL
- 常用接口USB打印接口TFT LCD接口SD卡接口
- 调试接口SWD
更多详细信息请咨询[华芯微特技术支持](https://www.synwit.cn)
### 1.2 MCU 简介
SWM320VET7 是 SYNWIT 公司的一款面向工业控制、白色家电、电机驱动等领域的芯片。包括如下硬件特性:
| 硬件 | 描述 |
| -- | -- |
|芯片型号| SWM320VET7 |
|CPU| ARM Cortex-M4 |
|主频| 120MHz |
|片内SRAM| 128KB |
|片内Flash| 512KB |
## 2. 编译说明
本 BSP 为开发者提供 MDK5 工程。下面以 MDK5 开发环境为例,介绍如何将系统运行起来。
双击 project.uvprojx 文件,打开 MDK5 工程,编译并下载程序到开发板。
> 工程默认配置使用 Jlink 仿真器下载程序,在通过 Jlink 连接开发板到 PC 的基础上,点击下载按钮即可下载程序到开发板
推荐熟悉 RT_Thread 的用户使用[env工具](https://www.rt-thread.org/page/download.html)可以在console下进入到 `bsp/swm320-lq100` 目录中,运行以下命令:
`scons`
来编译这个板级支持包。如果编译正确无误会产生rtthread.elf、rtthread.bin文件。其中 rtthread.bin 可以烧写到设备中运行。
## 3. 烧写及执行
### 3.1 硬件连接
- 使用 USB B-Type 数据线连接开发板到 PC注意需要下载安装串口驱动支持 CH340 芯片,使用 MDK5 需要安装 SWM320 相关的 pack
> USB B-Type 数据线用于串口通讯,同时供电
- 使用 Jlink 连接开发板到 PC (需要 Jlink 驱动)
将串口 0 引脚为:`[PA2/PA3]`和 USB 转串口模块 P2 相连串口配置方式为115200-N-8-1。
当使用 [env工具](https://www.rt-thread.org/page/download.html) 正确编译产生出rtthread.bin映像文件后可以使用 ISP 的方式来烧写到设备中。
**建议使用 keil 软件直接下载**。ISP 下载较复杂。
### 3.2 运行结果
如果编译 & 烧写无误当复位设备后会在串口上看到板子上的蓝色LED闪烁。串口打印RT-Thread的启动logo信息
```
\ | /
- RT - Thread Operating System
/ | \ 4.0.0 build Dec 11 2018
2006 - 2018 Copyright by rt-thread team
msh />
```
## 4. 驱动支持情况及计划
| **片上外设** | **支持情况** | **备注** |
| :----------------- | :----------: | :----------------------------------- |
| GPIO | 支持 | PA0, PA1... PP23 ---> PIN: 0, 1...100 |
| UART | 支持 | UART0/1/2/3 |
| ADC | 支持 | ADC0/1 |
| TIM | 支持 | TIM0/1/2/3/4/5 |
| I2C | 支持 | 软件 I2C0/1 |
| PWM | 支持 | PWM0/1/2/3/4/5 |
| RTC | 支持 | RTC |
| SPI | 支持 | SPI0/1 |
| WDT | 支持 | WDT |
| CRC | 支持 | CRC |
| SDIO | 支持 | SDIO |
| SRAM | 支持 | SRAM |
| NOR FLASH | 支持 | NOR FLASH |
| CAN | 暂不支持 | |
## 5. 联系人信息
- [yanmowudi](https://github.com/yanmowudi)
- [邮箱](lik@synwit.cn)
## 参考资料
* [RT-Thread 文档中心](https://www.rt-thread.org/document/site/)
* [SWM320数据手册](https://www.synwit.cn/col.jsp?id=155)

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@ -1,14 +0,0 @@
# for module compiling
import os
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')

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@ -1,41 +0,0 @@
import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
try:
from building import *
except:
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
print(RTT_ROOT)
exit(-1)
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
if rtconfig.PLATFORM == 'iar':
env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
env.Replace(ARFLAGS = [''])
env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map')
Export('RTT_ROOT')
Export('rtconfig')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
# make a building
DoBuilding(TARGET, objs)

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@ -1,9 +0,0 @@
from building import *
cwd = GetCurrentDir()
CPPPATH = [cwd, str(Dir('#'))]
src = Glob('*.c')
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

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@ -1,583 +0,0 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#include <rtthread.h>
#include <rtdevice.h>
#define LED_PIN 11
int main(void)
{
int count = 1;
rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT);
while (count++)
{
rt_pin_write(LED_PIN, PIN_HIGH);
rt_thread_mdelay(1000);
rt_pin_write(LED_PIN, PIN_LOW);
rt_thread_mdelay(1000);
}
return RT_EOK;
}
// #ifdef RT_USING_PIN
// #define KEY1_PIN 31
// void key1_cb(void *args)
// {
// rt_kprintf("key1 irq!\n");
// }
// static int pin_sample(int argc, char *argv[])
// {
// rt_pin_mode(KEY1_PIN, PIN_IRQ_MODE_FALLING);
// rt_pin_attach_irq(KEY1_PIN, PIN_IRQ_MODE_FALLING, key1_cb, RT_NULL);
// rt_pin_irq_enable(KEY1_PIN, PIN_IRQ_ENABLE);
// return RT_EOK;
// }
// MSH_CMD_EXPORT(pin_sample, pin sample);
// #endif
#ifdef RT_USING_ADC
#define ADC_DEV_NAME "adc1"
#define ADC_DEV_CHANNEL 0
#define REFER_VOLTAGE 330
#define CONVERT_BITS (1 << 12)
static int adc_vol_sample(int argc, char *argv[])
{
rt_adc_device_t adc_dev;
rt_uint32_t value, vol;
rt_err_t ret = RT_EOK;
adc_dev = (rt_adc_device_t)rt_device_find(ADC_DEV_NAME);
if (adc_dev == RT_NULL)
{
rt_kprintf("adc sample run failed! can't find %s device!\n", ADC_DEV_NAME);
return RT_ERROR;
}
ret = rt_adc_enable(adc_dev, ADC_DEV_CHANNEL);
value = rt_adc_read(adc_dev, ADC_DEV_CHANNEL);
rt_kprintf("the value is :%d,", value);
vol = value * REFER_VOLTAGE / CONVERT_BITS;
rt_kprintf("the voltage is :%d.%02d \n", vol / 100, vol % 100);
ret = rt_adc_disable(adc_dev, ADC_DEV_CHANNEL);
return ret;
}
MSH_CMD_EXPORT(adc_vol_sample, adc voltage convert sample);
#endif
#ifdef RT_USING_HWTIMER
#define HWTIMER_DEV_NAME "timer0"
static rt_err_t timeout_cb(rt_device_t dev, rt_size_t size)
{
rt_kprintf("this is hwtimer timeout callback fucntion!\n");
rt_kprintf("tick is :%d !\n", rt_tick_get());
return 0;
}
static int hwtimer_sample(int argc, char *argv[])
{
rt_err_t ret = RT_EOK;
rt_hwtimerval_t timeout_s;
rt_device_t hw_dev = RT_NULL;
rt_hwtimer_mode_t mode;
hw_dev = rt_device_find(HWTIMER_DEV_NAME);
if (hw_dev == RT_NULL)
{
rt_kprintf("hwtimer sample run failed! can't find %s device!\n", HWTIMER_DEV_NAME);
return RT_ERROR;
}
ret = rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR);
if (ret != RT_EOK)
{
rt_kprintf("open %s device failed!\n", HWTIMER_DEV_NAME);
return ret;
}
rt_device_set_rx_indicate(hw_dev, timeout_cb);
mode = HWTIMER_MODE_PERIOD;
//mode = HWTIMER_MODE_ONESHOT;
ret = rt_device_control(hw_dev, HWTIMER_CTRL_MODE_SET, &mode);
if (ret != RT_EOK)
{
rt_kprintf("set mode failed! ret is :%d\n", ret);
return ret;
}
timeout_s.sec = 2;
timeout_s.usec = 0;
if (rt_device_write(hw_dev, 0, &timeout_s, sizeof(timeout_s)) != sizeof(timeout_s))
{
rt_kprintf("set timeout value failed\n");
return RT_ERROR;
}
rt_thread_mdelay(3500);
rt_device_read(hw_dev, 0, &timeout_s, sizeof(timeout_s));
rt_kprintf("Read: Sec = %d, Usec = %d\n", timeout_s.sec, timeout_s.usec);
return ret;
}
MSH_CMD_EXPORT(hwtimer_sample, hwtimer sample);
#endif
#ifdef RT_USING_PWM
#define PWM_DEV_NAME "pwm0" /* PWM设备名称 */
#define PWM_DEV_CHANNEL 0 /* PWM通道 */
struct rt_device_pwm *pwm_dev; /* PWM设备句柄 */
static int pwm_sample(int argc, char *argv[])
{
rt_uint32_t period, pulse;
period = 500000; /* 周期为0.5ms,单位为纳秒ns */
pulse = 250000; /* PWM脉冲宽度值,单位为纳秒ns */
pwm_dev = (struct rt_device_pwm *)rt_device_find(PWM_DEV_NAME);
if (pwm_dev == RT_NULL)
{
rt_kprintf("pwm sample run failed! can't find %s device!\n", PWM_DEV_NAME);
return RT_ERROR;
}
rt_pwm_set(pwm_dev, PWM_DEV_CHANNEL, period, pulse);
rt_pwm_enable(pwm_dev, PWM_DEV_CHANNEL);
return RT_EOK;
}
MSH_CMD_EXPORT(pwm_sample, pwm sample);
#endif
#ifdef RT_USING_RTC
#include <sys/time.h>
static int rtc_sample(int argc, char *argv[])
{
rt_err_t ret = RT_EOK;
time_t now;
ret = set_date(2020, 2, 28);
if (ret != RT_EOK)
{
rt_kprintf("set RTC date failed\n");
return ret;
}
ret = set_time(23, 59, 55);
if (ret != RT_EOK)
{
rt_kprintf("set RTC time failed\n");
return ret;
}
//rt_thread_mdelay(3000);
now = time(RT_NULL);
rt_kprintf("%s\n", ctime(&now));
return ret;
}
MSH_CMD_EXPORT(rtc_sample, rtc sample);
#endif
#ifdef RT_USING_WDT
#define WDT_DEVICE_NAME "wdt"
static rt_device_t wdg_dev;
static void idle_hook(void)
{
rt_device_control(wdg_dev, RT_DEVICE_CTRL_WDT_KEEPALIVE, RT_NULL);
rt_kprintf("feed the dog!\n ");
}
static int wdt_sample(int argc, char *argv[])
{
rt_err_t ret = RT_EOK;
rt_uint32_t timeout = 1;
char device_name[RT_NAME_MAX];
if (argc == 2)
{
rt_strncpy(device_name, argv[1], RT_NAME_MAX);
}
else
{
rt_strncpy(device_name, WDT_DEVICE_NAME, RT_NAME_MAX);
}
wdg_dev = rt_device_find(device_name);
if (!wdg_dev)
{
rt_kprintf("find %s failed!\n", device_name);
return RT_ERROR;
}
ret = rt_device_init(wdg_dev);
if (ret != RT_EOK)
{
rt_kprintf("initialize %s failed!\n", device_name);
return RT_ERROR;
}
ret = rt_device_control(wdg_dev, RT_DEVICE_CTRL_WDT_SET_TIMEOUT, &timeout);
if (ret != RT_EOK)
{
rt_kprintf("set %s timeout failed!\n", device_name);
return RT_ERROR;
}
ret = rt_device_control(wdg_dev, RT_DEVICE_CTRL_WDT_START, RT_NULL);
if (ret != RT_EOK)
{
rt_kprintf("start %s failed!\n", device_name);
return -RT_ERROR;
}
// rt_thread_idle_sethook(idle_hook);
return ret;
}
MSH_CMD_EXPORT(wdt_sample, wdt sample);
#endif
#ifdef RT_USING_SPI
#define W25Q_SPI_DEVICE_NAME "spi00"
#define W25Q_FLASH_NAME "norflash0"
#include "drv_spi.h"
#include "spi_flash_sfud.h"
#include <dfs_file.h>
#include <unistd.h>
#include <stdio.h>
#include <sys/stat.h>
#include <sys/statfs.h>
static int rt_hw_spi_flash_init(void)
{
rt_hw_spi_device_attach("spi0", "spi00", GPIOP, PIN22);
if (RT_NULL == rt_sfud_flash_probe(W25Q_FLASH_NAME, W25Q_SPI_DEVICE_NAME))
{
return -RT_ERROR;
};
return RT_EOK;
}
INIT_COMPONENT_EXPORT(rt_hw_spi_flash_init);
static void spi_w25q_sample(int argc, char *argv[])
{
struct rt_spi_device *spi_dev_w25q;
char name[RT_NAME_MAX];
rt_uint8_t w25x_read_id = 0x90;
rt_uint8_t id[5] = {0};
if (argc == 2)
{
rt_strncpy(name, argv[1], RT_NAME_MAX);
}
else
{
rt_strncpy(name, W25Q_SPI_DEVICE_NAME, RT_NAME_MAX);
}
/* 查找 spi 设备获取设备句柄 */
spi_dev_w25q = (struct rt_spi_device *)rt_device_find(name);
struct rt_spi_configuration cfg;
cfg.data_width = 8;
cfg.mode = RT_SPI_MASTER | RT_SPI_MODE_0 | RT_SPI_MSB;
cfg.max_hz = 30 * 1000 * 1000; /* 20M */
rt_spi_configure(spi_dev_w25q, &cfg);
if (!spi_dev_w25q)
{
rt_kprintf("spi sample run failed! can't find %s device!\n", name);
}
else
{
/* 方式1使用 rt_spi_send_then_recv()发送命令读取ID */
rt_spi_send_then_recv(spi_dev_w25q, &w25x_read_id, 1, id, 5);
rt_kprintf("use rt_spi_send_then_recv() read w25q ID is:%x%x\n", id[3], id[4]);
/* 方式2使用 rt_spi_transfer_message()发送命令读取ID */
struct rt_spi_message msg1, msg2;
msg1.send_buf = &w25x_read_id;
msg1.recv_buf = RT_NULL;
msg1.length = 1;
msg1.cs_take = 1;
msg1.cs_release = 0;
msg1.next = &msg2;
msg2.send_buf = RT_NULL;
msg2.recv_buf = id;
msg2.length = 5;
msg2.cs_take = 0;
msg2.cs_release = 1;
msg2.next = RT_NULL;
rt_spi_transfer_message(spi_dev_w25q, &msg1);
rt_kprintf("use rt_spi_transfer_message() read w25q ID is:%x%x\n", id[3], id[4]);
}
}
static void spi_flash_elmfat_sample(void)
{
int fd, size;
struct statfs elm_stat;
char str[] = "elmfat mount to W25Q flash.\r\n", buf[80];
if (dfs_mkfs("elm", W25Q_FLASH_NAME) == 0)
rt_kprintf("make elmfat filesystem success.\n");
if (dfs_mount(W25Q_FLASH_NAME, "/", "elm", 0, 0) == 0)
rt_kprintf("elmfat filesystem mount success.\n");
if (statfs("/", &elm_stat) == 0)
rt_kprintf("elmfat filesystem block size: %d, total blocks: %d, free blocks: %d.\n",
elm_stat.f_bsize, elm_stat.f_blocks, elm_stat.f_bfree);
if (mkdir("/user", 0x777) == 0)
rt_kprintf("make a directory: '/user'.\n");
rt_kprintf("Write string '%s' to /user/test.txt.\n", str);
fd = open("/user/test.txt", O_WRONLY | O_CREAT);
if (fd >= 0)
{
if (write(fd, str, sizeof(str)) == sizeof(str))
rt_kprintf("Write data done.\n");
close(fd);
}
fd = open("/user/test.txt", O_RDONLY);
if (fd >= 0)
{
size = read(fd, buf, sizeof(buf));
close(fd);
if (size == sizeof(str))
rt_kprintf("Read data from file test.txt(size: %d): %s \n", size, buf);
}
}
MSH_CMD_EXPORT(spi_flash_elmfat_sample, spi flash elmfat sample);
MSH_CMD_EXPORT(spi_w25q_sample, spi w25q sample);
#endif
//#ifdef RT_USING_SPI
//#define SD_SPI_DEVICE_NAME "spi10"
//#define SDCARD_NAME "sd0"
//#include "drv_spi.h"
// #include <dfs_file.h>
// #include <unistd.h>
// #include <stdio.h>
// #include <sys/stat.h>
// #include <sys/statfs.h>
//#include "spi_msd.h"
//static int rt_hw_spi1_tfcard(void)
//{
// rt_hw_spi_device_attach("spi1", SD_SPI_DEVICE_NAME, GPIOB, PIN6);
// return msd_init(SDCARD_NAME, SD_SPI_DEVICE_NAME);
//}
//INIT_DEVICE_EXPORT(rt_hw_spi1_tfcard);
//static void elmfat_sample(void)
//{
// int fd, size;
// struct statfs elm_stat;
// char str[] = "elmfat mount to sdcard.", buf[80];
// if (dfs_mkfs("elm", SDCARD_NAME) == 0)
// rt_kprintf("make elmfat filesystem success.\n");
// if (dfs_mount(SDCARD_NAME, "/", "elm", 0, 0) == 0)
// rt_kprintf("elmfat filesystem mount success.\n");
// if (statfs("/", &elm_stat) == 0)
// rt_kprintf("elmfat filesystem block size: %d, total blocks: %d, free blocks: %d.\n",
// elm_stat.f_bsize, elm_stat.f_blocks, elm_stat.f_bfree);
// if (mkdir("/user", 0x777) == 0)
// rt_kprintf("make a directory: '/user'.\n");
// rt_kprintf("Write string '%s' to /user/test.txt.\n", str);
// fd = open("/user/test.txt", O_WRONLY | O_CREAT);
// if (fd >= 0)
// {
// if (write(fd, str, sizeof(str)) == sizeof(str))
// rt_kprintf("Write data done.\n");
// close(fd);
// }
// fd = open("/user/test.txt", O_RDONLY);
// if (fd >= 0)
// {
// size = read(fd, buf, sizeof(buf));
// close(fd);
// if (size == sizeof(str))
// rt_kprintf("Read data from file test.txt(size: %d): %s \n", size, buf);
// }
//}
//MSH_CMD_EXPORT(elmfat_sample, elmfat sample);
//#endif
#ifdef RT_USING_SDIO
#define SDCARD_NAME "sd0"
#include <dfs_file.h>
#include <unistd.h>
#include <stdio.h>
#include <sys/stat.h>
#include <sys/statfs.h>
static void sdio_elmfat_sample(void)
{
int fd, size;
struct statfs elm_stat;
char str[] = "elmfat mount to sdcard.\n", buf[80];
if (dfs_mkfs("elm", SDCARD_NAME) == 0)
rt_kprintf("make elmfat filesystem success.\n");
if (dfs_mount(SDCARD_NAME, "/", "elm", 0, 0) == 0)
rt_kprintf("elmfat filesystem mount success.\n");
if (statfs("/", &elm_stat) == 0)
rt_kprintf("elmfat filesystem block size: %d, total blocks: %d, free blocks: %d.\n",
elm_stat.f_bsize, elm_stat.f_blocks, elm_stat.f_bfree);
if (mkdir("/user", 0x777) == 0)
rt_kprintf("make a directory: '/user'.\n");
rt_kprintf("Write string '%s' to /user/test.txt.\n", str);
fd = open("/user/test.txt", O_WRONLY | O_CREAT);
if (fd >= 0)
{
if (write(fd, str, sizeof(str)) == sizeof(str))
rt_kprintf("Write data done.\n");
close(fd);
}
fd = open("/user/test.txt", O_RDONLY);
if (fd >= 0)
{
size = read(fd, buf, sizeof(buf));
close(fd);
if (size == sizeof(str))
rt_kprintf("Read data from file test.txt(size: %d): %s \n", size, buf);
}
}
MSH_CMD_EXPORT(sdio_elmfat_sample, sdio elmfat sample);
#endif
#ifdef RT_USING_HWCRYPTO
static void crypto_sample(void)
{
rt_uint8_t temp[] = {0, 1, 2, 3, 4, 5, 6, 7};
struct rt_hwcrypto_ctx *ctx;
rt_uint32_t result = 0;
struct hwcrypto_crc_cfg cfg =
{
.last_val = 0x0,
.poly = 0x04C11DB7,
.width = 8,
.xorout = 0x00000000,
.flags = 0,
};
ctx = rt_hwcrypto_crc_create(rt_hwcrypto_dev_default(), HWCRYPTO_CRC_CRC32);
rt_hwcrypto_crc_cfg(ctx, &cfg);
result = rt_hwcrypto_crc_update(ctx, temp, sizeof(temp));
rt_kprintf("result: 0x%08x \n", result);
rt_hwcrypto_crc_destroy(ctx);
}
MSH_CMD_EXPORT(crypto_sample, crypto sample);
#endif
#ifdef BSP_USING_NOR_FLASH
#define NORFLASH_DEV_NAME "nor"
static int norflash_sample(int argc, char *argv[])
{
rt_err_t ret = RT_EOK;
rt_device_t hw_dev = RT_NULL;
hw_dev = rt_device_find(NORFLASH_DEV_NAME);
if (hw_dev == RT_NULL)
{
rt_kprintf("norflash sample run failed! can't find %s device!\n", NORFLASH_DEV_NAME);
return RT_ERROR;
}
else
{
rt_kprintf("norflash sample run success! find %s device!\n", NORFLASH_DEV_NAME);
}
ret = rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR);
if (ret != RT_EOK)
{
rt_kprintf("open %s device failed!\n", NORFLASH_DEV_NAME);
return ret;
}
else
{
rt_kprintf("open %s device success!\n", NORFLASH_DEV_NAME);
}
struct rt_mtd_nor_device *hw_nor;
hw_nor = RT_MTD_NOR_DEVICE(hw_dev);
long id = hw_nor->ops->read_id(hw_nor);
rt_kprintf("id = %08x!\n", id);
// rt_device_set_rx_indicate(hw_dev, timeout_cb);
// mode = HWTIMER_MODE_PERIOD;
// //mode = HWTIMER_MODE_ONESHOT;
// ret = rt_device_control(hw_dev, HWTIMER_CTRL_MODE_SET, &mode);
// if (ret != RT_EOK)
// {
// rt_kprintf("set mode failed! ret is :%d\n", ret);
// return ret;
// }
// timeout_s.sec = 2;
// timeout_s.usec = 0;
// if (rt_device_write(hw_dev, 0, &timeout_s, sizeof(timeout_s)) != sizeof(timeout_s))
// {
// rt_kprintf("set timeout value failed\n");
// return RT_ERROR;
// }
// rt_thread_mdelay(3500);
// rt_device_read(hw_dev, 0, &timeout_s, sizeof(timeout_s));
// rt_kprintf("Read: Sec = %d, Usec = %d\n", timeout_s.sec, timeout_s.usec);
return ret;
}
MSH_CMD_EXPORT(norflash_sample, norflash sample);
#endif

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@ -1,305 +0,0 @@
menu "Hardware Drivers Config"
config SOC_SWM320
bool
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
default y
menu "On-chip Peripheral Drivers"
menuconfig BSP_USING_UART
bool "Enable UART"
default y
select RT_USING_SERIAL
if BSP_USING_UART
config BSP_USING_UART0
bool "Enable UART0 (A2/RX,A3/TX)"
default y
config BSP_USING_UART1
bool "Enable UART1 (C2/RX,C3/TX)"
default n
config BSP_USING_UART2
bool "Enable UART2 (C4/RX,C5/TX)"
default n
config BSP_USING_UART3
bool "Enable UART3 (C6/RX,C7/TX)"
default n
endif
config BSP_USING_GPIO
bool "Enable GPIO"
select RT_USING_PIN
default y
menuconfig BSP_USING_ADC
bool "Enable ADC"
default n
select RT_USING_ADC
if BSP_USING_ADC
config BSP_USING_ADC0
bool "Enable ADC0"
default n
if BSP_USING_ADC0
config BSP_USING_ADC0_CHN0
bool "Enable ADC0_CHN0"
default n
config BSP_USING_ADC0_CHN1
bool "Enable ADC0_CHN1"
default n
config BSP_USING_ADC0_CHN2
bool "Enable ADC0_CHN2"
default n
config BSP_USING_ADC0_CHN3
bool "Enable ADC0_CHN3"
default n
config BSP_USING_ADC0_CHN4
bool "Enable ADC0_CHN4(A12)"
default n
config BSP_USING_ADC0_CHN5
bool "Enable ADC0_CHN5(A11)"
default n
config BSP_USING_ADC0_CHN6
bool "Enable ADC0_CHN6(A10)"
default n
config BSP_USING_ADC0_CHN7
bool "Enable ADC0_CHN7(A9)"
default n
endif
config BSP_USING_ADC1
bool "Enable ADC1"
default n
if BSP_USING_ADC1
config BSP_USING_ADC1_CHN0
bool "Enable ADC1_CHN0(C7)"
default n
config BSP_USING_ADC1_CHN1
bool "Enable ADC1_CHN1(C6)"
default n
config BSP_USING_ADC1_CHN2
bool "Enable ADC1_CHN2(C5)"
default n
config BSP_USING_ADC1_CHN3
bool "Enable ADC1_CHN3(C4)"
default n
config BSP_USING_ADC1_CHN4
bool "Enable ADC1_CHN4(N0)"
default n
config BSP_USING_ADC1_CHN5
bool "Enable ADC1_CHN5(N1)"
default n
config BSP_USING_ADC1_CHN6
bool "Enable ADC1_CHN6(N2)"
default n
config BSP_USING_ADC1_CHN7
bool "Enable ADC1_CHN7"
default n
endif
endif
menuconfig BSP_USING_TIM
bool "Enable HWTIMER"
default n
select RT_USING_HWTIMER
if BSP_USING_TIM
config BSP_USING_TIM0
bool "Enable TIM0"
default n
config BSP_USING_TIM1
bool "Enable TIM1"
default n
config BSP_USING_TIM2
bool "Enable TIM2"
default n
config BSP_USING_TIM3
bool "Enable TIM3"
default n
config BSP_USING_TIM4
bool "Enable TIM4"
default n
config BSP_USING_TIM5
bool "Enable TIM5"
default n
endif
menuconfig BSP_USING_I2C
bool "Enable I2C BUS (software simulation)"
default n
select RT_USING_I2C
select RT_USING_I2C_BITOPS
select RT_USING_PIN
if BSP_USING_I2C
config BSP_USING_I2C0
bool "Enable I2C0"
default n
if BSP_USING_I2C0
comment "Notice: PC2 --> 28; PC3 --> 29"
config BSP_I2C0_SCL_PIN
int "I2C0 scl pin number"
range 0 99
default 28
config BSP_I2C0_SDA_PIN
int "I2C0 sda pin number"
range 0 99
default 29
endif
config BSP_USING_I2C1
bool "Enable I2C1"
default n
if BSP_USING_I2C1
comment "Notice: PC6 --> 32; PC7 --> 33"
config BSP_I2C1_SCL_PIN
int "I2C1 scl pin number"
range 0 99
default 32
config BSP_I2C1_SDA_PIN
int "I2C1 sda pin number"
range 0 99
default 33
endif
endif
menuconfig BSP_USING_PWM
bool "Enable PWM"
default n
select RT_USING_PWM
if BSP_USING_PWM
config BSP_USING_PWM0
bool "Enable PWM0"
default n
if BSP_USING_PWM0
config BSP_USING_PWM0A
bool "Enable PWM0A (C2)"
default n
config BSP_USING_PWM0B
bool "Enable PWM0B (C4)"
default n
endif
config BSP_USING_PWM1
bool "Enable PWM1"
default n
if BSP_USING_PWM1
config BSP_USING_PWM1A
bool "Enable PWM1A (C3)"
default n
config BSP_USING_PWM1B
bool "Enable PWM1B (C5)"
default n
endif
config BSP_USING_PWM2
bool "Enable PWM2"
default n
if BSP_USING_PWM2
config BSP_USING_PWM2A
bool "Enable PWM2A (N4)"
default n
config BSP_USING_PWM2B
bool "Enable PWM2B (N6)"
default n
endif
config BSP_USING_PWM3
bool "Enable PWM3"
default n
if BSP_USING_PWM3
config BSP_USING_PWM3A
bool "Enable PWM3A (N3)"
default n
config BSP_USING_PWM3B
bool "Enable PWM3B (N5)"
default n
endif
config BSP_USING_PWM4
bool "Enable PWM4"
default n
if BSP_USING_PWM4
config BSP_USING_PWM4A
bool "Enable PWM4A (N8)"
default n
config BSP_USING_PWM4B
bool "Enable PWM4B (N10)"
default n
endif
config BSP_USING_PWM5
bool "Enable PWM5"
default n
if BSP_USING_PWM5
config BSP_USING_PWM5A
bool "Enable PWM5A (N7)"
default n
config BSP_USING_PWM5B
bool "Enable PWM5B (N9)"
default n
endif
endif
config BSP_USING_RTC
bool "Enable RTC"
select RT_USING_RTC
default n
menuconfig BSP_USING_SPI
bool "Enable SPI BUS"
default n
select RT_USING_SPI
if BSP_USING_SPI
config BSP_USING_SPI0
bool "Enable SPI0 BUS(CS/P22,MISO/P19,MOSI/P18,CLK/P23)"
default n
config BSP_USING_SPI1
bool "Enable SPI1 BUS(CS/B6,MISO/B3,MOSI/B2,CLK/B1)"
default n
endif
config BSP_USING_WDT
bool "Enable Watchdog Timer"
select RT_USING_WDT
default n
config BSP_USING_CRC
bool "Enable CRC (CRC-32 0x04C11DB7 Polynomial)"
select RT_USING_HWCRYPTO
select RT_HWCRYPTO_USING_CRC
default n
endmenu
menu "Onboard Peripheral Drivers"
config BSP_USING_SDIO
bool "Enable SDCARD (sdio)"
select RT_USING_SDIO
select RT_USING_DFS
select RT_USING_DFS_ELMFAT
default n
menuconfig BSP_USING_EXT_SRAM
bool "Enable external sram"
select RT_USING_MEMHEAP
select RT_USING_MEMHEAP_AS_HEAP
default n
if BSP_USING_EXT_SRAM
config BSP_EXT_SRAM_SIZE
hex "external sram size"
default 0x100000
endif
menuconfig BSP_USING_NOR_FLASH
bool "Enable mtd nor flash"
select RT_USING_MTD_NOR
select PKG_USING_FTL_SRC
default n
if BSP_USING_NOR_FLASH
config BSP_NOR_FLASH_SIZE
hex "mtd nor flash size"
default 0x1000000
config BSP_NOR_FLASH_SECTOR_SIZE
hex "mtd nor flsah sector"
default 0x10000
endif
endmenu
menu "Offboard Peripheral Drivers"
endmenu
endmenu

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@ -1,52 +0,0 @@
from building import *
cwd = GetCurrentDir()
CPPPATH = [cwd]
src = Split('''
board.c
''')
if GetDepend(['RT_USING_SERIAL']):
src += ['drv_uart.c']
if GetDepend(['RT_USING_PIN']):
src += ['drv_gpio.c']
if GetDepend(['RT_USING_ADC']):
src += ['drv_adc.c']
if GetDepend(['RT_USING_HWTIMER']):
src += ['drv_hwtimer.c']
if GetDepend(['RT_USING_I2C']):
src += ['drv_soft_i2c.c']
if GetDepend(['RT_USING_PWM']):
src += ['drv_pwm.c']
if GetDepend(['RT_USING_RTC']):
src += ['drv_rtc.c']
if GetDepend(['RT_USING_SPI']):
src += ['drv_spi.c']
if GetDepend(['RT_USING_WDT']):
src += ['drv_wdt.c']
if GetDepend(['RT_USING_SDIO']):
src += ['drv_sdio.c']
if GetDepend(['RT_USING_HWCRYPTO']):
src += ['drv_crypto.c']
if GetDepend(['BSP_USING_EXT_SRAM']):
src += ['drv_sram.c']
if GetDepend(['BSP_USING_NOR_FLASH']):
src += ['drv_nor_flash.c']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

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@ -1,80 +0,0 @@
/*
* Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-05-31 ZYH first version
* 2018-12-10 Zohar_Lee format file
*/
#include "board.h"
static void bsp_clock_config(void)
{
SystemInit();
SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
SysTick->CTRL |= 0x00000004UL;
}
void SysTick_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
rt_tick_increase();
/* leave interrupt */
rt_interrupt_leave();
}
/**
* This function will delay for some us.
*
* @param us the delay time of us
*/
void rt_hw_us_delay(rt_uint32_t us)
{
rt_uint32_t ticks;
rt_uint32_t told, tnow, tcnt = 0;
rt_uint32_t reload = SysTick->LOAD;
ticks = us * reload / (1000000 / RT_TICK_PER_SECOND);
told = SysTick->VAL;
while (1)
{
tnow = SysTick->VAL;
if (tnow != told)
{
if (tnow < told)
{
tcnt += told - tnow;
}
else
{
tcnt += reload - tnow + told;
}
told = tnow;
if (tcnt >= ticks)
{
break;
}
}
}
}
void rt_hw_board_init()
{
bsp_clock_config();
#ifdef RT_USING_HEAP
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
#endif
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
}

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@ -1,57 +0,0 @@
/*
* Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-05-31 ZYH first version
* 2018-12-10 Zohar_Lee format file
*/
#ifndef __BOARD_H__
#define __BOARD_H__
#include <rtthread.h>
#include <rthw.h>
#include <rtdevice.h>
#include <string.h>
#include <SWM320.h>
#ifdef __cplusplus
extern "C"
{
#endif
#define SRAM_BASE 0x20000000
#define SRAM_SIZE 0x20000
#define SRAM_END (SRAM_BASE + SRAM_SIZE)
#ifdef BSP_USING_EXT_SRAM
#define EXT_SRAM_BASE SRAMM_BASE
#define EXT_SRAM_SIZE BSP_EXT_SRAM_SIZE
#define EXT_SRAM_BEGIN EXT_SRAM_BASE
#define EXT_SRAM_END (EXT_SRAM_BASE + EXT_SRAM_SIZE)
#endif
#if defined(__ARMCC_VERSION)
extern int Image$$RW_IRAM1$$ZI$$Limit;
#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
#elif __ICCARM__
#pragma section = "HEAP"
#define HEAP_BEGIN (__segment_end("HEAP"))
#else
extern int __bss_end;
#define HEAP_BEGIN ((void *)&__bss_end)
#endif
#define HEAP_END SRAM_END
#define HEAP_SIZE (HEAP_END - (rt_uint32_t)HEAP_BEGIN)
void rt_hw_board_init(void);
#ifdef __cplusplus
}
#endif
#endif /* __BOARD_H__ */

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@ -1,217 +0,0 @@
/*
* Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-5-26 lik first version
*/
#include "drv_adc.h"
#ifdef RT_USING_ADC
#ifdef BSP_USING_ADC
//#define DRV_DEBUG
#define LOG_TAG "drv.adc"
#include <drv_log.h>
static struct swm_adc_cfg adc_cfg[] =
{
#ifdef BSP_USING_ADC0
ADC0_CFG,
#endif
#ifdef BSP_USING_ADC1
ADC1_CFG,
#endif
};
static struct swm_adc adc_drv[sizeof(adc_cfg) / sizeof(adc_cfg[0])];
static rt_err_t swm_adc_enabled(struct rt_adc_device *adc_device, rt_uint32_t channel, rt_bool_t enabled)
{
struct swm_adc_cfg *cfg = RT_NULL;
RT_ASSERT(adc_device != RT_NULL);
cfg = adc_device->parent.user_data;
if (enabled)
{
ADC_Open(cfg->ADCx);
}
else
{
ADC_Close(cfg->ADCx);
}
return RT_EOK;
}
static rt_uint32_t swm_adc_get_channel(rt_uint32_t channel)
{
rt_uint32_t swm_channel = 0;
switch (channel)
{
case 0:
swm_channel = ADC_CH0;
break;
case 1:
swm_channel = ADC_CH1;
break;
case 2:
swm_channel = ADC_CH2;
break;
case 3:
swm_channel = ADC_CH3;
break;
case 4:
swm_channel = ADC_CH4;
break;
case 5:
swm_channel = ADC_CH5;
break;
case 6:
swm_channel = ADC_CH6;
break;
case 7:
swm_channel = ADC_CH7;
break;
}
return swm_channel;
}
static rt_err_t swm_get_adc_value(struct rt_adc_device *adc_device, rt_uint32_t channel, rt_uint32_t *value)
{
uint32_t adc_chn;
struct swm_adc_cfg *cfg = RT_NULL;
RT_ASSERT(adc_device != RT_NULL);
RT_ASSERT(value != RT_NULL);
cfg = adc_device->parent.user_data;
if (channel < 8)
{
/* set stm32 ADC channel */
adc_chn = swm_adc_get_channel(channel);
}
else
{
LOG_E("ADC channel must be between 0 and 7.");
return -RT_ERROR;
}
/* start ADC */
ADC_Start(cfg->ADCx);
/* Wait for the ADC to convert */
while ((cfg->ADCx->CH[channel].STAT & 0x01) == 0)
;
/* get ADC value */
*value = (rt_uint32_t)ADC_Read(cfg->ADCx, adc_chn);
return RT_EOK;
}
static const struct rt_adc_ops swm_adc_ops =
{
.enabled = swm_adc_enabled,
.convert = swm_get_adc_value,
};
static int rt_hw_adc_init(void)
{
int i = 0;
int result = RT_EOK;
for (i = 0; i < sizeof(adc_cfg) / sizeof(adc_cfg[0]); i++)
{
/* ADC init */
adc_drv[i].cfg = &adc_cfg[i];
if (adc_drv[i].cfg->ADCx == ADC0)
{
#ifdef BSP_USING_ADC0_CHN0
adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH0;
#endif
#ifdef BSP_USING_ADC0_CHN1
adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH1;
#endif
#ifdef BSP_USING_ADC0_CHN2
adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH2;
#endif
#ifdef BSP_USING_ADC0_CHN3
adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH3;
#endif
#ifdef BSP_USING_ADC0_CHN4
adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH4;
PORT_Init(PORTA, PIN12, PORTA_PIN12_ADC0_IN4, 0); //PA.12 => ADC0.CH4
#endif
#ifdef BSP_USING_ADC0_CHN5
adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH5;
PORT_Init(PORTA, PIN11, PORTA_PIN11_ADC0_IN5, 0); //PA.11 => ADC0.CH5
#endif
#ifdef BSP_USING_ADC0_CHN6
adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH6;
PORT_Init(PORTA, PIN10, PORTA_PIN10_ADC0_IN6, 0); //PA.10 => ADC0.CH6
#endif
#ifdef BSP_USING_ADC0_CHN7
adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH7;
PORT_Init(PORTA, PIN9, PORTA_PIN9_ADC0_IN7, 0); //PA.9 => ADC0.CH7
#endif
}
else if (adc_drv[i].cfg->ADCx == ADC1)
{
#ifdef BSP_USING_ADC1_CHN0
adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH0;
PORT_Init(PORTC, PIN7, PORTC_PIN7_ADC1_IN0, 0); //PC.7 => ADC1.CH0
#endif
#ifdef BSP_USING_ADC1_CHN1
adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH1;
PORT_Init(PORTC, PIN6, PORTC_PIN6_ADC1_IN1, 0); //PC.6 => ADC1.CH1
#endif
#ifdef BSP_USING_ADC1_CHN2
adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH2;
PORT_Init(PORTC, PIN5, PORTC_PIN5_ADC1_IN2, 0); //PC.5 => ADC1.CH2
#endif
#ifdef BSP_USING_ADC1_CHN3
adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH3;
PORT_Init(PORTC, PIN4, PORTC_PIN4_ADC1_IN3, 0); //PC.4 => ADC1.CH3
#endif
#ifdef BSP_USING_ADC1_CHN4
adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH4;
PORT_Init(PORTN, PIN0, PORTN_PIN0_ADC1_IN4, 0); //PN.0 => ADC1.CH4
#endif
#ifdef BSP_USING_ADC1_CHN5
adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH5;
PORT_Init(PORTN, PIN1, PORTN_PIN1_ADC1_IN5, 0); //PN.1 => ADC1.CH5
#endif
#ifdef BSP_USING_ADC1_CHN6
adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH6;
PORT_Init(PORTN, PIN2, PORTN_PIN2_ADC1_IN6, 0); //PN.2 => ADC1.CH6
#endif
#ifdef BSP_USING_ADC1_CHN7
adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH7;
#endif
}
ADC_Init(adc_drv[i].cfg->ADCx, &(adc_drv[i].cfg->adc_initstruct));
ADC_Open(adc_drv[i].cfg->ADCx);
/* register ADC device */
if (rt_hw_adc_register(&adc_drv[i].adc_device, adc_drv[i].cfg->name, &swm_adc_ops, adc_drv[i].cfg) == RT_EOK)
{
LOG_D("%s init success", adc_drv[i].cfg->name);
}
else
{
LOG_E("%s register failed", adc_drv[i].cfg->name);
result = -RT_ERROR;
}
}
return result;
}
INIT_BOARD_EXPORT(rt_hw_adc_init);
#endif /* BSP_USING_ADC */
#endif /* RT_USING_ADC */

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@ -1,71 +0,0 @@
/*
* Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-5-26 lik first version
*/
#ifndef __DRV_ADC_H__
#define __DRV_ADC_H__
#include "board.h"
struct swm_adc_cfg
{
const char *name;
ADC_TypeDef *ADCx;
ADC_InitStructure adc_initstruct;
};
struct swm_adc
{
struct swm_adc_cfg *cfg;
struct rt_adc_device adc_device;
};
#ifdef BSP_USING_ADC0
#ifndef ADC0_CFG
#define ADC0_CFG \
{ \
.name = "adc0", \
.ADCx = ADC0, \
.adc_initstruct.clk_src = ADC_CLKSRC_VCO_DIV64, \
.adc_initstruct.clk_div = 25, \
.adc_initstruct.pga_ref = PGA_REF_INTERNAL, \
.adc_initstruct.channels = 0, \
.adc_initstruct.samplAvg = ADC_AVG_SAMPLE1, \
.adc_initstruct.trig_src = ADC_TRIGSRC_SW, \
.adc_initstruct.Continue = 0, \
.adc_initstruct.EOC_IEn = 0, \
.adc_initstruct.OVF_IEn = 0, \
.adc_initstruct.HFULL_IEn = 0, \
.adc_initstruct.FULL_IEn = 0, \
}
#endif /* ADC0_CFG */
#endif /* BSP_USING_ADC0 */
#ifdef BSP_USING_ADC1
#ifndef ADC1_CFG
#define ADC1_CFG \
{ \
.name = "adc1", \
.ADCx = ADC1, \
.adc_initstruct.clk_src = ADC_CLKSRC_VCO_DIV64, \
.adc_initstruct.clk_div = 25, \
.adc_initstruct.pga_ref = PGA_REF_INTERNAL, \
.adc_initstruct.channels = 0, \
.adc_initstruct.samplAvg = ADC_AVG_SAMPLE1, \
.adc_initstruct.trig_src = ADC_TRIGSRC_SW, \
.adc_initstruct.Continue = 0, \
.adc_initstruct.EOC_IEn = 0, \
.adc_initstruct.OVF_IEn = 0, \
.adc_initstruct.HFULL_IEn = 0, \
.adc_initstruct.FULL_IEn = 0, \
}
#endif /* ADC1_CFG */
#endif /* BSP_USING_ADC1 */
#endif /* __DRV_ADC_H__ */

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@ -1,226 +0,0 @@
/*
* Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-07-10 lik first version
*/
#include "drv_crypto.h"
#include <string.h>
#ifdef RT_USING_HWCRYPTO
struct swm_hwcrypto_device
{
struct rt_hwcrypto_device dev;
struct rt_mutex mutex;
};
#ifdef BSP_USING_CRC
static struct hwcrypto_crc_cfg crc_backup_cfg;
static rt_uint32_t _crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, rt_size_t length)
{
rt_uint32_t result = 0;
struct swm_hwcrypto_device *swm_hw_dev = (struct swm_hwcrypto_device *)ctx->parent.device->user_data;
struct swm_crc_cfg *hw_crc_cfg = (struct swm_crc_cfg *)(ctx->parent.contex);
rt_mutex_take(&swm_hw_dev->mutex, RT_WAITING_FOREVER);
if (memcmp(&crc_backup_cfg, &ctx->crc_cfg, sizeof(struct hwcrypto_crc_cfg)) != 0)
{
hw_crc_cfg->CRCx = CRC;
hw_crc_cfg->inival = ctx->crc_cfg.last_val;
switch (ctx->crc_cfg.width)
{
case 8:
hw_crc_cfg->crc_inbits = 2;
break;
case 16:
hw_crc_cfg->crc_inbits = 1;
break;
case 32:
hw_crc_cfg->crc_inbits = 0;
break;
default:
goto _exit;
}
switch (ctx->crc_cfg.poly)
{
case 0x1021:
hw_crc_cfg->crc_1632 = 1;
break;
case 0x04C11DB7:
hw_crc_cfg->crc_1632 = 0;
break;
default:
goto _exit;
}
hw_crc_cfg->crc_out_not = 0;
switch (ctx->crc_cfg.flags)
{
case 0:
case CRC_FLAG_REFIN:
hw_crc_cfg->crc_out_rev = 0;
break;
case CRC_FLAG_REFOUT:
case CRC_FLAG_REFIN | CRC_FLAG_REFOUT:
hw_crc_cfg->crc_out_rev = 1;
break;
default:
goto _exit;
}
CRC_Init(hw_crc_cfg->CRCx, (hw_crc_cfg->crc_inbits << 1) | hw_crc_cfg->crc_1632, hw_crc_cfg->crc_out_not, hw_crc_cfg->crc_out_rev, hw_crc_cfg->inival);
memcpy(&crc_backup_cfg, &ctx->crc_cfg, sizeof(struct hwcrypto_crc_cfg));
}
for (uint32_t i = 0; i < length; i++)
CRC_Write((uint32_t)in[i]);
result = CRC_Result();
ctx->crc_cfg.last_val = result;
crc_backup_cfg.last_val = ctx->crc_cfg.last_val;
result = (result ? result ^ (ctx->crc_cfg.xorout) : result);
_exit:
rt_mutex_release(&swm_hw_dev->mutex);
return result;
}
static const struct hwcrypto_crc_ops crc_ops =
{
.update = _crc_update,
};
#endif /* BSP_USING_CRC */
static rt_err_t _crypto_create(struct rt_hwcrypto_ctx *ctx)
{
rt_err_t res = RT_EOK;
switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK)
{
#if defined(BSP_USING_CRC)
case HWCRYPTO_TYPE_CRC:
{
struct swm_crc_cfg *contex = rt_calloc(1, sizeof(struct swm_crc_cfg));
if (RT_NULL == contex)
{
res = -RT_ERROR;
break;
}
contex->CRCx = DEFAULT_CRC;
contex->inival = DEFAULT_INIVAL;
contex->crc_inbits = DEFAULT_INBITS;
contex->crc_1632 = DEFAULT_CRC1632;
contex->crc_out_not = DEFAULT_OUT_NOT;
contex->crc_out_rev = DEFAULT_OUT_REV;
ctx->contex = contex;
((struct hwcrypto_crc *)ctx)->ops = &crc_ops;
break;
}
#endif /* BSP_USING_CRC */
default:
res = -RT_ERROR;
break;
}
return res;
}
static void _crypto_destroy(struct rt_hwcrypto_ctx *ctx)
{
struct swm_crc_cfg *hw_crc_cfg = (struct swm_crc_cfg *)(ctx->contex);
switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK)
{
#if defined(BSP_USING_CRC)
case HWCRYPTO_TYPE_CRC:
hw_crc_cfg->CRCx->CR &= ~CRC_CR_EN_Msk;
break;
#endif /* BSP_USING_CRC */
default:
break;
}
rt_free(ctx->contex);
}
static rt_err_t _crypto_clone(struct rt_hwcrypto_ctx *des, const struct rt_hwcrypto_ctx *src)
{
rt_err_t res = RT_EOK;
switch (src->type & HWCRYPTO_MAIN_TYPE_MASK)
{
#if defined(BSP_USING_CRC)
case HWCRYPTO_TYPE_CRC:
if (des->contex && src->contex)
{
rt_memcpy(des->contex, src->contex, sizeof(struct swm_crc_cfg));
}
break;
#endif /* BSP_USING_CRC */
default:
res = -RT_ERROR;
break;
}
return res;
}
static void _crypto_reset(struct rt_hwcrypto_ctx *ctx)
{
struct swm_crc_cfg *hw_crc_cfg = (struct swm_crc_cfg *)(ctx->contex);
switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK)
{
#if defined(BSP_USING_CRC)
case HWCRYPTO_TYPE_CRC:
hw_crc_cfg->CRCx->CR &= ~CRC_CR_EN_Msk;
break;
#endif /* BSP_USING_CRC */
default:
break;
}
}
static const struct rt_hwcrypto_ops _ops =
{
.create = _crypto_create,
.destroy = _crypto_destroy,
.copy = _crypto_clone,
.reset = _crypto_reset,
};
int rt_hw_crypto_init(void)
{
static struct swm_hwcrypto_device _crypto_dev;
rt_uint32_t cpuid[2] = {0};
_crypto_dev.dev.ops = &_ops;
cpuid[0] = SCB->CPUID;
_crypto_dev.dev.id = 0;
rt_memcpy(&_crypto_dev.dev.id, cpuid, 8);
_crypto_dev.dev.user_data = &_crypto_dev;
if (rt_hwcrypto_register(&_crypto_dev.dev, RT_HWCRYPTO_DEFAULT_NAME) != RT_EOK)
{
return -1;
}
rt_mutex_init(&_crypto_dev.mutex, RT_HWCRYPTO_DEFAULT_NAME, RT_IPC_FLAG_PRIO);
return 0;
}
INIT_BOARD_EXPORT(rt_hw_crypto_init);
#endif /* RT_USING_HWCRYPTO */

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@ -1,40 +0,0 @@
/*
* Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-07-10 lik first version
*/
#ifndef __DRV_CRYPTO_H__
#define __DRV_CRYPTO_H__
#include "board.h"
/* swm config class */
struct swm_crc_cfg
{
CRC_TypeDef *CRCx;
uint32_t inival;
uint8_t crc_inbits;
uint8_t crc_1632;
uint8_t crc_out_not;
uint8_t crc_out_rev;
};
#ifdef BSP_USING_CRC
#define DEFAULT_CRC (CRC)
#define DEFAULT_INIVAL (0x00000000)
#define DEFAULT_INBITS (2)
#define DEFAULT_CRC1632 (0)
#define DEFAULT_OUT_NOT (0)
#define DEFAULT_OUT_REV (0)
#endif /* BSP_USING_CRC */
int rt_hw_crypto_init(void);
#endif /* __DRV_CRYPTO_H__ */

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@ -1,528 +0,0 @@
/*
* Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-05-31 ZYH first version
* 2018-12-10 Zohar_Lee fix bug
* 2020-07-10 lik rewrite
*/
#include "drv_gpio.h"
#ifdef RT_USING_PIN
#ifdef BSP_USING_GPIO
static const struct swm_pin_index pins[] =
{
__SWM_PIN(0, A, 0),
__SWM_PIN(1, A, 1),
__SWM_PIN(2, A, 2),
__SWM_PIN(3, A, 3),
__SWM_PIN(4, A, 4),
__SWM_PIN(5, A, 5),
__SWM_PIN(6, A, 6),
__SWM_PIN(7, A, 7),
__SWM_PIN(8, A, 8),
__SWM_PIN(9, A, 9),
__SWM_PIN(10, A, 10),
__SWM_PIN(11, A, 11),
__SWM_PIN(12, A, 12),
__SWM_PIN(13, B, 0),
__SWM_PIN(14, B, 1),
__SWM_PIN(15, B, 2),
__SWM_PIN(16, B, 3),
__SWM_PIN(17, B, 4),
__SWM_PIN(18, B, 5),
__SWM_PIN(19, B, 6),
__SWM_PIN(20, B, 7),
__SWM_PIN(21, B, 8),
__SWM_PIN(22, B, 9),
__SWM_PIN(23, B, 10),
__SWM_PIN(24, B, 11),
__SWM_PIN(25, B, 12),
__SWM_PIN(26, C, 0),
__SWM_PIN(27, C, 1),
__SWM_PIN(28, C, 2),
__SWM_PIN(29, C, 3),
__SWM_PIN(30, C, 4),
__SWM_PIN(31, C, 5),
__SWM_PIN(32, C, 6),
__SWM_PIN(33, C, 7),
__SWM_PIN(34, M, 0),
__SWM_PIN(35, M, 1),
__SWM_PIN(36, M, 2),
__SWM_PIN(37, M, 3),
__SWM_PIN(38, M, 4),
__SWM_PIN(39, M, 5),
__SWM_PIN(40, M, 6),
__SWM_PIN(41, M, 7),
__SWM_PIN(42, M, 8),
__SWM_PIN(43, M, 9),
__SWM_PIN(44, M, 10),
__SWM_PIN(45, M, 11),
__SWM_PIN(46, M, 12),
__SWM_PIN(47, M, 13),
__SWM_PIN(48, M, 14),
__SWM_PIN(49, M, 15),
__SWM_PIN(50, M, 16),
__SWM_PIN(51, M, 17),
__SWM_PIN(52, M, 18),
__SWM_PIN(53, M, 19),
__SWM_PIN(54, M, 20),
__SWM_PIN(55, M, 21),
__SWM_PIN(56, N, 0),
__SWM_PIN(57, N, 1),
__SWM_PIN(58, N, 2),
__SWM_PIN(59, N, 3),
__SWM_PIN(60, N, 4),
__SWM_PIN(61, N, 5),
__SWM_PIN(62, N, 6),
__SWM_PIN(63, N, 7),
__SWM_PIN(64, N, 8),
__SWM_PIN(65, N, 9),
__SWM_PIN(66, N, 10),
__SWM_PIN(67, N, 11),
__SWM_PIN(68, N, 12),
__SWM_PIN(69, N, 13),
__SWM_PIN(70, N, 14),
__SWM_PIN(71, N, 15),
__SWM_PIN(72, N, 16),
__SWM_PIN(73, N, 17),
__SWM_PIN(74, N, 18),
__SWM_PIN(75, N, 19),
__SWM_PIN(76, P, 0),
__SWM_PIN(77, P, 1),
__SWM_PIN(78, P, 2),
__SWM_PIN(79, P, 3),
__SWM_PIN(80, P, 4),
__SWM_PIN(81, P, 5),
__SWM_PIN(82, P, 6),
__SWM_PIN(83, P, 7),
__SWM_PIN(84, P, 8),
__SWM_PIN(85, P, 9),
__SWM_PIN(86, P, 10),
__SWM_PIN(87, P, 11),
__SWM_PIN(88, P, 12),
__SWM_PIN(89, P, 13),
__SWM_PIN(90, P, 14),
__SWM_PIN(91, P, 15),
__SWM_PIN(92, P, 16),
__SWM_PIN(93, P, 17),
__SWM_PIN(94, P, 18),
__SWM_PIN(95, P, 19),
__SWM_PIN(96, P, 20),
__SWM_PIN(97, P, 21),
__SWM_PIN(98, P, 22),
__SWM_PIN(99, P, 23)};
static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
{
{0, 0, RT_NULL, RT_NULL},
{1, 0, RT_NULL, RT_NULL},
{2, 0, RT_NULL, RT_NULL},
{3, 0, RT_NULL, RT_NULL},
{4, 0, RT_NULL, RT_NULL},
{5, 0, RT_NULL, RT_NULL},
{6, 0, RT_NULL, RT_NULL},
{7, 0, RT_NULL, RT_NULL},
{8, 0, RT_NULL, RT_NULL},
{9, 0, RT_NULL, RT_NULL},
{10, 0, RT_NULL, RT_NULL},
{11, 0, RT_NULL, RT_NULL},
{12, 0, RT_NULL, RT_NULL},
{13, 0, RT_NULL, RT_NULL},
{14, 0, RT_NULL, RT_NULL},
{15, 0, RT_NULL, RT_NULL},
{16, 0, RT_NULL, RT_NULL},
{17, 0, RT_NULL, RT_NULL},
{18, 0, RT_NULL, RT_NULL},
{19, 0, RT_NULL, RT_NULL},
{20, 0, RT_NULL, RT_NULL},
{21, 0, RT_NULL, RT_NULL},
{22, 0, RT_NULL, RT_NULL},
{23, 0, RT_NULL, RT_NULL},
{24, 0, RT_NULL, RT_NULL},
{25, 0, RT_NULL, RT_NULL},
{26, 0, RT_NULL, RT_NULL},
{27, 0, RT_NULL, RT_NULL},
{28, 0, RT_NULL, RT_NULL},
{29, 0, RT_NULL, RT_NULL},
{30, 0, RT_NULL, RT_NULL},
{31, 0, RT_NULL, RT_NULL},
{32, 0, RT_NULL, RT_NULL},
{33, 0, RT_NULL, RT_NULL},
{34, 0, RT_NULL, RT_NULL},
{35, 0, RT_NULL, RT_NULL},
{36, 0, RT_NULL, RT_NULL},
{37, 0, RT_NULL, RT_NULL},
{38, 0, RT_NULL, RT_NULL},
{39, 0, RT_NULL, RT_NULL},
{40, 0, RT_NULL, RT_NULL},
{41, 0, RT_NULL, RT_NULL},
{42, 0, RT_NULL, RT_NULL},
{43, 0, RT_NULL, RT_NULL},
{44, 0, RT_NULL, RT_NULL},
{45, 0, RT_NULL, RT_NULL},
{46, 0, RT_NULL, RT_NULL},
{47, 0, RT_NULL, RT_NULL},
{48, 0, RT_NULL, RT_NULL},
{49, 0, RT_NULL, RT_NULL},
{50, 0, RT_NULL, RT_NULL},
{51, 0, RT_NULL, RT_NULL},
{52, 0, RT_NULL, RT_NULL},
{53, 0, RT_NULL, RT_NULL},
{54, 0, RT_NULL, RT_NULL},
{55, 0, RT_NULL, RT_NULL},
{56, 0, RT_NULL, RT_NULL},
{57, 0, RT_NULL, RT_NULL},
{58, 0, RT_NULL, RT_NULL},
{59, 0, RT_NULL, RT_NULL},
{60, 0, RT_NULL, RT_NULL},
{61, 0, RT_NULL, RT_NULL},
{62, 0, RT_NULL, RT_NULL},
{63, 0, RT_NULL, RT_NULL},
{64, 0, RT_NULL, RT_NULL},
{65, 0, RT_NULL, RT_NULL},
{66, 0, RT_NULL, RT_NULL},
{67, 0, RT_NULL, RT_NULL},
{68, 0, RT_NULL, RT_NULL},
{69, 0, RT_NULL, RT_NULL},
{70, 0, RT_NULL, RT_NULL},
{71, 0, RT_NULL, RT_NULL},
{72, 0, RT_NULL, RT_NULL},
{73, 0, RT_NULL, RT_NULL},
{74, 0, RT_NULL, RT_NULL},
{75, 0, RT_NULL, RT_NULL},
{76, 0, RT_NULL, RT_NULL},
{77, 0, RT_NULL, RT_NULL},
{78, 0, RT_NULL, RT_NULL},
{79, 0, RT_NULL, RT_NULL},
{80, 0, RT_NULL, RT_NULL},
{81, 0, RT_NULL, RT_NULL},
{82, 0, RT_NULL, RT_NULL},
{83, 0, RT_NULL, RT_NULL},
{84, 0, RT_NULL, RT_NULL},
{85, 0, RT_NULL, RT_NULL},
{86, 0, RT_NULL, RT_NULL},
{87, 0, RT_NULL, RT_NULL},
{88, 0, RT_NULL, RT_NULL},
{89, 0, RT_NULL, RT_NULL},
{90, 0, RT_NULL, RT_NULL},
{91, 0, RT_NULL, RT_NULL},
{92, 0, RT_NULL, RT_NULL},
{93, 0, RT_NULL, RT_NULL},
{94, 0, RT_NULL, RT_NULL},
{95, 0, RT_NULL, RT_NULL},
{96, 0, RT_NULL, RT_NULL},
{97, 0, RT_NULL, RT_NULL},
{98, 0, RT_NULL, RT_NULL},
{99, 0, RT_NULL, RT_NULL}};
#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
static const struct swm_pin_index *get_pin(uint8_t pin)
{
const struct swm_pin_index *index;
if (pin < ITEM_NUM(pins))
{
index = &pins[pin];
if (index->gpio == GPIO0)
index = RT_NULL;
}
else
{
index = RT_NULL;
}
return index;
}
static void swm_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
{
const struct swm_pin_index *index;
index = get_pin(pin);
if (index == RT_NULL)
{
return;
}
if (value)
{
GPIO_SetBit(index->gpio, index->pin);
}
else
{
GPIO_ClrBit(index->gpio, index->pin);
}
}
static int swm_pin_read(rt_device_t dev, rt_base_t pin)
{
const struct swm_pin_index *index;
index = get_pin(pin);
if (index == RT_NULL)
{
return PIN_LOW;
}
return (int)GPIO_GetBit(index->gpio, index->pin);
}
static void swm_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
{
const struct swm_pin_index *index;
int dir = 0;
int pull_up = 0;
int pull_down = 0;
index = get_pin(pin);
if (index == RT_NULL)
{
return;
}
/* Configure GPIO_InitStructure */
switch (mode)
{
case PIN_MODE_OUTPUT:
/* output setting */
dir = 1;
break;
case PIN_MODE_INPUT:
/* input setting: not pull. */
dir = 0;
break;
case PIN_MODE_INPUT_PULLUP:
/* input setting: pull up. */
dir = 0;
pull_up = 1;
break;
case PIN_MODE_INPUT_PULLDOWN:
/* input setting: pull down. */
dir = 0;
pull_down = 1;
break;
case PIN_MODE_OUTPUT_OD:
/* output setting: od. */
dir = 1;
pull_up = 1;
break;
}
GPIO_Init(index->gpio, index->pin, dir, pull_up, pull_down);
}
static rt_err_t swm_pin_attach_irq(struct rt_device *device,
rt_int32_t pin,
rt_uint32_t mode,
void (*hdr)(void *args),
void *args)
{
const struct swm_pin_index *index;
rt_base_t level;
index = get_pin(pin);
if (index == RT_NULL)
{
return RT_ENOSYS;
}
level = rt_hw_interrupt_disable();
if (pin_irq_hdr_tab[pin].pin == pin &&
pin_irq_hdr_tab[pin].mode == mode &&
pin_irq_hdr_tab[pin].hdr == hdr &&
pin_irq_hdr_tab[pin].args == args)
{
rt_hw_interrupt_enable(level);
return RT_EOK;
}
pin_irq_hdr_tab[pin].pin = pin;
pin_irq_hdr_tab[pin].mode = mode;
pin_irq_hdr_tab[pin].hdr = hdr;
pin_irq_hdr_tab[pin].args = args;
rt_hw_interrupt_enable(level);
return RT_EOK;
}
static rt_err_t swm_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
{
const struct swm_pin_index *index;
rt_base_t level;
index = get_pin(pin);
if (index == RT_NULL)
{
return RT_ENOSYS;
}
level = rt_hw_interrupt_disable();
pin_irq_hdr_tab[pin].mode = 0;
pin_irq_hdr_tab[pin].hdr = RT_NULL;
pin_irq_hdr_tab[pin].args = RT_NULL;
rt_hw_interrupt_enable(level);
return RT_EOK;
}
static rt_err_t swm_pin_irq_enable(struct rt_device *device,
rt_base_t pin,
rt_uint32_t enabled)
{
const struct swm_pin_index *index;
rt_base_t level = 0;
index = get_pin(pin);
if (index == RT_NULL)
{
return RT_ENOSYS;
}
if (enabled == PIN_IRQ_ENABLE)
{
switch (pin_irq_hdr_tab[pin].mode)
{
case PIN_IRQ_MODE_RISING:
GPIO_Init(index->gpio, index->pin, 0, 0, 1);
EXTI_Init(index->gpio, index->pin, EXTI_RISE_EDGE);
break;
case PIN_IRQ_MODE_FALLING:
GPIO_Init(index->gpio, index->pin, 0, 1, 0);
EXTI_Init(index->gpio, index->pin, EXTI_FALL_EDGE);
break;
case PIN_IRQ_MODE_RISING_FALLING:
GPIO_Init(index->gpio, index->pin, 0, 1, 1);
EXTI_Init(index->gpio, index->pin, EXTI_BOTH_EDGE);
break;
case PIN_IRQ_MODE_HIGH_LEVEL:
GPIO_Init(index->gpio, index->pin, 0, 0, 1);
EXTI_Init(index->gpio, index->pin, EXTI_HIGH_LEVEL);
break;
case PIN_IRQ_MODE_LOW_LEVEL:
GPIO_Init(index->gpio, index->pin, 0, 1, 0);
EXTI_Init(index->gpio, index->pin, EXTI_LOW_LEVEL);
break;
default:
return RT_EINVAL;
}
level = rt_hw_interrupt_disable();
NVIC_EnableIRQ(index->irq);
EXTI_Open(index->gpio, index->pin);
rt_hw_interrupt_enable(level);
}
else if (enabled == PIN_IRQ_DISABLE)
{
level = rt_hw_interrupt_disable();
NVIC_DisableIRQ(index->irq);
EXTI_Close(index->gpio, index->pin);
rt_hw_interrupt_enable(level);
}
else
{
return -RT_ENOSYS;
}
return RT_EOK;
}
const static struct rt_pin_ops swm_pin_ops =
{
.pin_mode = swm_pin_mode,
.pin_write = swm_pin_write,
.pin_read = swm_pin_read,
.pin_attach_irq = swm_pin_attach_irq,
.pin_detach_irq = swm_pin_detach_irq,
.pin_irq_enable = swm_pin_irq_enable};
static void rt_hw_pin_isr(GPIO_TypeDef *GPIOx)
{
static int gpio[24];
int index = 0;
static int init = 0;
const struct swm_pin_index *pin;
if (init == 0)
{
init = 1;
for (pin = &pins[0];
pin->index < ITEM_NUM(pins);
pin++)
{
if (pin->gpio == GPIOx)
{
gpio[index] = pin->index;
index++;
RT_ASSERT(index <= 24)
}
}
}
for (index = 0; index < 24; index++)
{
pin = get_pin(gpio[index]);
if (EXTI_State(pin->gpio, pin->pin))
{
EXTI_Clear(pin->gpio, pin->pin);
if (pin_irq_hdr_tab[pin->index].hdr)
{
pin_irq_hdr_tab[pin->index].hdr(pin_irq_hdr_tab[pin->index].args);
}
}
}
}
void GPIOA_Handler(void)
{
rt_interrupt_enter();
rt_hw_pin_isr(GPIOA);
rt_interrupt_leave();
}
void GPIOB_Handler(void)
{
rt_interrupt_enter();
rt_hw_pin_isr(GPIOB);
rt_interrupt_leave();
}
void GPIOC_Handler(void)
{
rt_interrupt_enter();
rt_hw_pin_isr(GPIOC);
rt_interrupt_leave();
}
void GPIOM_Handler(void)
{
rt_interrupt_enter();
rt_hw_pin_isr(GPIOM);
rt_interrupt_leave();
}
void GPION_Handler(void)
{
rt_interrupt_enter();
rt_hw_pin_isr(GPION);
rt_interrupt_leave();
}
void GPIOP_Handler(void)
{
rt_interrupt_enter();
rt_hw_pin_isr(GPIOP);
rt_interrupt_leave();
}
int rt_hw_pin_init(void)
{
return rt_device_pin_register("pin", &swm_pin_ops, RT_NULL);
}
INIT_BOARD_EXPORT(rt_hw_pin_init);
#endif /* BSP_USING_GPIO */
#endif /* RT_USING_PIN */

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/*
* Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-10 Zohar_Lee first version
* 2020-07-10 lik rewrite
*/
#ifndef __DRV_GPIO_H__
#define __DRV_GPIO_H__
#include "board.h"
#define __SWM_PIN(index, gpio, pin_index) \
{ \
index, GPIO##gpio, PIN##pin_index, GPIO##gpio##_IRQn \
}
#define GPIO0 ((GPIO_TypeDef *)(0))
#define GPIO0_IRQn (GPIOA0_IRQn)
struct swm_pin_index
{
uint32_t index;
GPIO_TypeDef *gpio;
uint32_t pin;
IRQn_Type irq;
};
typedef struct swm_pin_index pin_t;
int rt_hw_pin_init(void);
#endif /* __DRV_GPIO_H__ */

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@ -1,256 +0,0 @@
/*
* Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-10 Zohar_Lee first version
* 2020-07-10 lik format file
*/
#include "drv_hwtimer.h"
#ifdef RT_USING_HWTIMER
#ifdef BSP_USING_TIM
enum
{
#ifdef BSP_USING_TIM0
TIM0_INDEX,
#endif
#ifdef BSP_USING_TIM1
TIM1_INDEX,
#endif
#ifdef BSP_USING_TIM2
TIM2_INDEX,
#endif
#ifdef BSP_USING_TIM3
TIM3_INDEX,
#endif
#ifdef BSP_USING_TIM4
TIM4_INDEX,
#endif
#ifdef BSP_USING_TIM5
TIM5_INDEX,
#endif
};
static struct swm_hwtimer_cfg hwtimer_cfg[] =
{
#ifdef BSP_USING_TIM0
TIM0_CFG,
#endif
#ifdef BSP_USING_TIM1
TIM1_CFG,
#endif
#ifdef BSP_USING_TIM2
TIM2_CFG,
#endif
#ifdef BSP_USING_TIM3
TIM3_CFG,
#endif
#ifdef BSP_USING_TIM4
TIM4_CFG,
#endif
#ifdef BSP_USING_TIM5
TIM5_CFG,
#endif
};
static struct swm_hwtimer hwtimer_drv[sizeof(hwtimer_cfg) / sizeof(hwtimer_cfg[0])] = {0};
static void swm_timer_init(struct rt_hwtimer_device *timer_device, rt_uint32_t state)
{
struct swm_hwtimer_cfg *cfg = RT_NULL;
RT_ASSERT(timer_device != RT_NULL);
if (state)
{
cfg = timer_device->parent.user_data;
TIMR_Init(cfg->TIMRx, TIMR_MODE_TIMER, SystemCoreClock, 1);
timer_device->freq = SystemCoreClock;
}
}
static rt_err_t swm_timer_start(rt_hwtimer_t *timer_device, rt_uint32_t cnt, rt_hwtimer_mode_t opmode)
{
rt_err_t result = RT_EOK;
struct swm_hwtimer_cfg *cfg = RT_NULL;
RT_ASSERT(timer_device != RT_NULL);
cfg = timer_device->parent.user_data;
if (opmode == HWTIMER_MODE_ONESHOT)
{
/* set timer to single mode */
timer_device->mode = HWTIMER_MODE_ONESHOT;
}
else
{
timer_device->mode = HWTIMER_MODE_PERIOD;
}
TIMR_SetPeriod(cfg->TIMRx, cnt);
TIMR_Stop(cfg->TIMRx);
TIMR_Start(cfg->TIMRx);
return result;
}
static void swm_timer_stop(rt_hwtimer_t *timer_device)
{
struct swm_hwtimer_cfg *cfg = RT_NULL;
RT_ASSERT(timer_device != RT_NULL);
cfg = timer_device->parent.user_data;
/* stop timer */
TIMR_Stop(cfg->TIMRx);
}
static rt_uint32_t swm_timer_count_get(rt_hwtimer_t *timer_device)
{
struct swm_hwtimer_cfg *cfg = RT_NULL;
RT_ASSERT(timer_device != RT_NULL);
cfg = timer_device->parent.user_data;
return TIMR_GetCurValue(cfg->TIMRx);
}
static rt_err_t swm_timer_ctrl(rt_hwtimer_t *timer_device, rt_uint32_t cmd, void *args)
{
struct swm_hwtimer_cfg *cfg = RT_NULL;
rt_err_t result = RT_EOK;
RT_ASSERT(timer_device != RT_NULL);
RT_ASSERT(args != RT_NULL);
cfg = timer_device->parent.user_data;
switch (cmd)
{
case HWTIMER_CTRL_FREQ_SET:
{
rt_uint32_t freq;
freq = *(rt_uint32_t *)args;
TIMR_Init(cfg->TIMRx, TIMR_MODE_TIMER, SystemCoreClock / freq, 1);
}
break;
default:
{
result = -RT_ENOSYS;
}
break;
}
return result;
}
static const struct rt_hwtimer_info _info = TIM_DEV_INFO_CONFIG;
static struct rt_hwtimer_ops swm_hwtimer_ops =
{
.init = swm_timer_init,
.start = swm_timer_start,
.stop = swm_timer_stop,
.count_get = swm_timer_count_get,
.control = swm_timer_ctrl};
void rt_hw_hwtimer_isr(rt_hwtimer_t *timer_device)
{
struct swm_hwtimer_cfg *cfg = RT_NULL;
RT_ASSERT(timer_device != RT_NULL);
cfg = timer_device->parent.user_data;
TIMR_INTClr(cfg->TIMRx);
rt_device_hwtimer_isr(timer_device);
}
#ifdef BSP_USING_TIM0
void TIMR0_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
rt_hw_hwtimer_isr(&(hwtimer_drv[TIM0_INDEX].time_device));
/* leave interrupt */
rt_interrupt_leave();
}
#endif //BSP_USING_TIM0
#ifdef BSP_USING_TIM1
void TIMR1_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
rt_hw_hwtimer_isr(&(hwtimer_drv[TIM1_INDEX].time_device));
/* leave interrupt */
rt_interrupt_leave();
}
#endif //BSP_USING_TIM1
#ifdef BSP_USING_TIM2
void TIMR2_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
rt_hw_hwtimer_isr(&(hwtimer_drv[TIM2_INDEX].time_device));
/* leave interrupt */
rt_interrupt_leave();
}
#endif //BSP_USING_TIM2
#ifdef BSP_USING_TIM3
void TIMR3_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
rt_hw_hwtimer_isr(&(hwtimer_drv[TIM3_INDEX].time_device));
/* leave interrupt */
rt_interrupt_leave();
}
#endif //BSP_USING_TIM3
#ifdef BSP_USING_TIM4
void TIMR4_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
rt_hw_hwtimer_isr(&(hwtimer_drv[TIM4_INDEX].time_device));
/* leave interrupt */
rt_interrupt_leave();
}
#endif //BSP_USING_TIM4
#ifdef BSP_USING_TIM5
void TIMR5_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
rt_hw_hwtimer_isr(&(hwtimer_drv[TIM5_INDEX].time_device));
/* leave interrupt */
rt_interrupt_leave();
}
#endif //BSP_USING_TIM5
static int rt_hw_hwtimer_init(void)
{
int i = 0;
int result = RT_EOK;
for (i = 0; i < sizeof(hwtimer_cfg) / sizeof(hwtimer_cfg[0]); i++)
{
hwtimer_drv[i].cfg = &hwtimer_cfg[i];
hwtimer_drv[i].time_device.info = &_info;
hwtimer_drv[i].time_device.ops = &swm_hwtimer_ops;
if (rt_device_hwtimer_register(&hwtimer_drv[i].time_device, hwtimer_drv[i].cfg->name, hwtimer_drv[i].cfg) == RT_EOK)
{
;
}
else
{
result = -RT_ERROR;
}
}
return result;
}
INIT_BOARD_EXPORT(rt_hw_hwtimer_init);
#endif /* BSP_USING_TIM */
#endif /* RT_USING_HWTIMER */

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/*
* Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-10 Zohar_Lee first version
* 2020-07-10 lik rewrite
*/
#ifndef __DRV_HWTIMER_H__
#define __DRV_HWTIMER_H__
#include "board.h"
struct swm_hwtimer_cfg
{
char *name;
TIMR_TypeDef *TIMRx;
};
struct swm_hwtimer
{
struct swm_hwtimer_cfg *cfg;
rt_hwtimer_t time_device;
};
#ifndef TIM_DEV_INFO_CONFIG
#define TIM_DEV_INFO_CONFIG \
{ \
.maxfreq = 120000000, \
.minfreq = 120000000, \
.maxcnt = 0xFFFFFFFF, \
.cntmode = HWTIMER_CNTMODE_DW, \
}
#endif /* TIM_DEV_INFO_CONFIG */
#ifdef BSP_USING_TIM0
#ifndef TIM0_CFG
#define TIM0_CFG \
{ \
.name = "timer0", \
.TIMRx = TIMR0, \
}
#endif /* TIM0_CFG */
#endif /* BSP_USING_TIM0 */
#ifdef BSP_USING_TIM1
#ifndef TIM1_CFG
#define TIM1_CFG \
{ \
.name = "timer1", \
.TIMRx = TIMR1, \
}
#endif /* TIM1_CFG */
#endif /* BSP_USING_TIM1 */
#ifdef BSP_USING_TIM2
#ifndef TIM2_CFG
#define TIM2_CFG \
{ \
.name = "timer2", \
.TIMRx = TIMR2, \
}
#endif /* TIM2_CFG */
#endif /* BSP_USING_TIM2 */
#ifdef BSP_USING_TIM3
#ifndef TIM3_CFG
#define TIM3_CFG \
{ \
.name = "timer3", \
.TIMRx = TIMR3, \
}
#endif /* TIM3_CFG */
#endif /* BSP_USING_TIM3 */
#ifdef BSP_USING_TIM4
#ifndef TIM4_CFG
#define TIM4_CFG \
{ \
.name = "timer4", \
.TIMRx = TIMR4, \
}
#endif /* TIM4_CFG */
#endif /* BSP_USING_TIM4 */
#ifdef BSP_USING_TIM5
#ifndef TIM5_CFG
#define TIM5_CFG \
{ \
.name = "timer5", \
.TIMRx = TIMR5, \
}
#endif /* TIM5_CFG */
#endif /* BSP_USING_TIM5 */
int rt_hw_hwtimer_init(void);
#endif /* __DRV_HWTIMER_H__ */

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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-11-15 SummerGift first version
*/
/*
* NOTE: DO NOT include this file on the header file.
*/
#ifndef LOG_TAG
#define DBG_TAG "drv"
#else
#define DBG_TAG LOG_TAG
#endif /* LOG_TAG */
#ifdef DRV_DEBUG
#define DBG_LVL DBG_LOG
#else
#define DBG_LVL DBG_INFO
#endif /* DRV_DEBUG */
#include <rtdbg.h>

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/*
* Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-05-31 ZYH first version
* 2018-12-10 Zohar_Lee format file
* 2020-07-10 lik rewrite
*/
#include "drv_nor_flash.h"
#ifdef BSP_USING_NOR_FLASH
#define DRV_DEBUG
#define LOG_TAG "drv.norflash"
#include <drv_log.h>
static struct rt_mutex flash_lock;
/* RT-Thread MTD device interface */
static long swm_norflash_read_id(struct rt_mtd_nor_device *device)
{
return 0xdeadbeef;
}
static rt_size_t swm_norflash_read(struct rt_mtd_nor_device *device,
rt_off_t position,
rt_uint8_t *data,
rt_uint32_t size)
{
rt_mutex_take(&flash_lock, RT_WAITING_FOREVER);
memcpy(data, ((const void *)(NORFLM_BASE + position)), size);
rt_mutex_release(&flash_lock);
return size;
}
static rt_size_t swm_norflash_write(struct rt_mtd_nor_device *device,
rt_off_t position,
const rt_uint8_t *data,
rt_uint32_t size)
{
rt_size_t i;
const rt_uint16_t *hwdata = (const rt_uint16_t *)data;
rt_mutex_take(&flash_lock, RT_WAITING_FOREVER);
for (i = 0; i < size / 2; i++)
{
NORFL_Write(position, hwdata[i]);
position += 2;
}
rt_mutex_release(&flash_lock);
return size;
}
static rt_err_t swm_norflash_erase_block(struct rt_mtd_nor_device *device,
rt_off_t offset,
rt_uint32_t length)
{
rt_mutex_take(&flash_lock, RT_WAITING_FOREVER);
NORFL_SectorErase(offset);
rt_mutex_release(&flash_lock);
return RT_EOK;
}
const static struct rt_mtd_nor_driver_ops mtd_ops =
{
swm_norflash_read_id,
swm_norflash_read,
swm_norflash_write,
swm_norflash_erase_block};
static struct rt_mtd_nor_device mtd;
int rt_hw_norflash_init(void)
{
NORFL_InitStructure NORFL_InitStruct;
PORT->PORTP_SEL0 = 0xAAAAAAAA; //PP0-23 => ADDR0-23
PORT->PORTP_SEL1 = 0xAAAA;
PORT->PORTM_SEL0 = 0xAAAAAAAA; //PM0-15 => DATA15-0
PORT->PORTM_INEN = 0xFFFF;
PORT->PORTM_SEL1 = 0xAAA; //PM16 => OEN、PM17 => WEN、PM18 => NORFL_CSN、PM19 => SDRAM_CSN、PM20 => SRAM_CSN、PM21 => SDRAM_CKE
NORFL_InitStruct.DataWidth = 16;
NORFL_InitStruct.WELowPulseTime = 5;
NORFL_InitStruct.OEPreValidTime = 12;
NORFL_InitStruct.OperFinishIEn = 0;
NORFL_InitStruct.OperTimeoutIEn = 0;
NORFL_Init(&NORFL_InitStruct);
/* set page size and block size */
mtd.block_size = BLOCK_SIZE; /* 64kByte */
mtd.ops = &mtd_ops;
/* initialize mutex */
if (rt_mutex_init(&flash_lock, "nor", RT_IPC_FLAG_PRIO) != RT_EOK)
{
rt_kprintf("init sd lock mutex failed\n");
return -RT_ERROR;
}
mtd.block_start = 0;
mtd.block_end = BLOCK_COUNTER;
/* register MTD device */
rt_mtd_nor_register_device("nor", &mtd);
return RT_EOK;
}
INIT_DEVICE_EXPORT(rt_hw_norflash_init);
#endif /* BSP_USING_NOR_FLASH */

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/*
* Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-10 Zohar_Lee first version
* 2020-07-10 lik rewrite
*/
#ifndef DRV_NOR_FLASH_H__
#define DRV_NOR_FLASH_H__
#include "board.h"
#define BLOCK_SIZE (64 * 1024)
#define FLASH_SIZE (BSP_NOR_FLASH_SIZE)
#define BLOCK_COUNTER (FLASH_SIZE / BLOCK_SIZE)
int rt_hw_norflash_init(void);
#endif

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/*
* Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-10 Zohar_Lee first version
* 2020-07-10 lik format file
*/
#include "drv_pwm.h"
#ifdef RT_USING_PWM
#ifdef BSP_USING_PWM
//#define DRV_DEBUG
#define LOG_TAG "drv.pwm"
#include <drv_log.h>
#define MIN_PERIOD 2
#define MIN_PULSE 1
static struct swm_pwm_cfg pwm_cfg[] =
{
#ifdef BSP_USING_PWM0
PWM0_CFG,
#endif
#ifdef BSP_USING_PWM1
PWM1_CFG,
#endif
#ifdef BSP_USING_PWM2
PWM2_CFG,
#endif
#ifdef BSP_USING_PWM3
PWM3_CFG,
#endif
#ifdef BSP_USING_PWM4
PWM4_CFG,
#endif
#ifdef BSP_USING_PWM5
PWM5_CFG,
#endif
};
static struct swm_pwm pwm_drv[sizeof(pwm_cfg) / sizeof(pwm_cfg[0])] = {0};
static rt_err_t swm_pwm_control(struct rt_device_pwm *pwm_device, int cmd, void *arg);
static struct rt_pwm_ops pwm_ops =
{
swm_pwm_control};
static rt_err_t swm_pwm_enable(struct rt_device_pwm *pwm_device, struct rt_pwm_configuration *configuration, rt_bool_t enable)
{
struct swm_pwm_cfg *cfg = RT_NULL;
RT_ASSERT(pwm_device != RT_NULL);
cfg = pwm_device->parent.user_data;
if (!enable)
{
if (PWM_CH_A == configuration->channel)
{
PWM_Stop(cfg->PWMx, 1, 0);
}
if (PWM_CH_B == configuration->channel)
{
PWM_Stop(cfg->PWMx, 0, 1);
}
}
else
{
if (PWM_CH_A == configuration->channel)
{
PWM_Start(cfg->PWMx, 1, 0);
}
if (PWM_CH_B == configuration->channel)
{
PWM_Start(cfg->PWMx, 0, 1);
}
}
return RT_EOK;
}
static rt_err_t swm_pwm_get(struct rt_device_pwm *pwm_device, struct rt_pwm_configuration *configuration)
{
rt_uint64_t tim_clock;
tim_clock = SystemCoreClock / 8;
struct swm_pwm_cfg *cfg = RT_NULL;
RT_ASSERT(pwm_device != RT_NULL);
cfg = pwm_device->parent.user_data;
/* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */
tim_clock /= 1000000UL;
configuration->period = PWM_GetCycle(cfg->PWMx, configuration->channel) * 1000UL / tim_clock;
configuration->pulse = PWM_GetHDuty(cfg->PWMx, configuration->channel) * 1000UL / tim_clock;
return RT_EOK;
}
static rt_err_t swm_pwm_set(struct rt_device_pwm *pwm_device, struct rt_pwm_configuration *configuration)
{
rt_uint32_t period, pulse;
rt_uint64_t tim_clock;
tim_clock = SystemCoreClock / 8;
struct swm_pwm_cfg *cfg = RT_NULL;
RT_ASSERT(pwm_device != RT_NULL);
cfg = pwm_device->parent.user_data;
/* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */
/* when SystemCoreClock = 120MHz, configuration->period max 4.369ms */
/* when SystemCoreClock = 20MHz, configuration->period max 26.214ms */
tim_clock /= 1000000UL;
period = (unsigned long long)configuration->period * tim_clock / 1000ULL;
pulse = (unsigned long long)configuration->pulse * tim_clock / 1000ULL;
if (period < MIN_PERIOD)
{
period = MIN_PERIOD;
}
if (pulse < MIN_PULSE)
{
pulse = MIN_PULSE;
}
PWM_SetCycle(cfg->PWMx, configuration->channel, period);
PWM_SetHDuty(cfg->PWMx, configuration->channel, pulse);
return RT_EOK;
}
static rt_err_t swm_pwm_control(struct rt_device_pwm *pwm_device, int cmd, void *arg)
{
RT_ASSERT(pwm_device != RT_NULL);
struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
switch (cmd)
{
case PWM_CMD_ENABLE:
return swm_pwm_enable(pwm_device, configuration, RT_TRUE);
case PWM_CMD_DISABLE:
return swm_pwm_enable(pwm_device, configuration, RT_FALSE);
case PWM_CMD_SET:
return swm_pwm_set(pwm_device, configuration);
case PWM_CMD_GET:
return swm_pwm_get(pwm_device, configuration);
default:
return RT_EINVAL;
}
}
int rt_hw_pwm_init(void)
{
int i = 0;
int result = RT_EOK;
for (i = 0; i < sizeof(pwm_cfg) / sizeof(pwm_cfg[0]); i++)
{
pwm_drv[i].cfg = &pwm_cfg[i];
if (pwm_drv[i].cfg->PWMx == PWM0)
{
#ifdef BSP_USING_PWM0A
PORT_Init(PORTC, PIN2, FUNMUX0_PWM0A_OUT, 0);
#endif
#ifdef BSP_USING_PWM0B
PORT_Init(PORTC, PIN4, FUNMUX0_PWM0B_OUT, 0);
#endif
}
else if (pwm_drv[i].cfg->PWMx == PWM1)
{
#ifdef BSP_USING_PWM1A
PORT_Init(PORTC, PIN3, FUNMUX1_PWM1A_OUT, 0);
#endif
#ifdef BSP_USING_PWM1B
PORT_Init(PORTC, PIN5, FUNMUX1_PWM1B_OUT, 0);
#endif
}
else if (pwm_drv[i].cfg->PWMx == PWM2)
{
#ifdef BSP_USING_PWM2A
PORT_Init(PORTN, PIN4, FUNMUX0_PWM2A_OUT, 0);
#endif
#ifdef BSP_USING_PWM2B
PORT_Init(PORTN, PIN6, FUNMUX0_PWM2B_OUT, 0);
#endif
}
else if (pwm_drv[i].cfg->PWMx == PWM3)
{
#ifdef BSP_USING_PWM3A
PORT_Init(PORTN, PIN3, FUNMUX1_PWM3A_OUT, 0);
#endif
#ifdef BSP_USING_PWM3B
PORT_Init(PORTN, PIN5, FUNMUX1_PWM3B_OUT, 0);
#endif
}
else if (pwm_drv[i].cfg->PWMx == PWM4)
{
#ifdef BSP_USING_PWM4A
PORT_Init(PORTN, PIN8, FUNMUX0_PWM4A_OUT, 0);
#endif
#ifdef BSP_USING_PWM4B
PORT_Init(PORTN, PIN10, FUNMUX0_PWM4B_OUT, 0);
#endif
}
else if (pwm_drv[i].cfg->PWMx == PWM5)
{
#ifdef BSP_USING_PWM5A
PORT_Init(PORTN, PIN7, FUNMUX1_PWM5A_OUT, 0);
#endif
#ifdef BSP_USING_PWM5B
PORT_Init(PORTN, PIN9, FUNMUX1_PWM5B_OUT, 0);
#endif
}
PWM_Init(pwm_drv[i].cfg->PWMx, &(pwm_drv[i].cfg->pwm_initstruct));
if (rt_device_pwm_register(&pwm_drv[i].pwm_device, pwm_drv[i].cfg->name, &pwm_ops, pwm_drv[i].cfg) == RT_EOK)
{
LOG_D("%s register success", pwm_drv[i].cfg->name);
}
else
{
LOG_E("%s register failed", pwm_drv[i].cfg->name);
result = -RT_ERROR;
}
}
return result;
}
INIT_DEVICE_EXPORT(rt_hw_pwm_init);
#endif /* BSP_USING_PWM */
#endif /* RT_USING_PWM */

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@ -1,164 +0,0 @@
/*
* Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-10 Zohar_Lee first version
* 2020-07-10 lik rewrite
*/
#ifndef __DRV_PWM_H__
#define __DRV_PWM_H__
#include "board.h"
struct swm_pwm_cfg
{
const char *name;
PWM_TypeDef *PWMx;
PWM_InitStructure pwm_initstruct;
};
struct swm_pwm
{
struct swm_pwm_cfg *cfg;
struct rt_device_pwm pwm_device;
};
#ifdef BSP_USING_PWM0
#ifndef PWM0_CFG
#define PWM0_CFG \
{ \
.name = "pwm0", \
.PWMx = PWM0, \
.pwm_initstruct.clk_div = PWM_CLKDIV_8, \
.pwm_initstruct.mode = PWM_MODE_INDEP, \
.pwm_initstruct.cycleA = 10000, \
.pwm_initstruct.hdutyA = 5000, \
.pwm_initstruct.initLevelA = 1, \
.pwm_initstruct.cycleB = 10000, \
.pwm_initstruct.hdutyB = 5000, \
.pwm_initstruct.initLevelB = 1, \
.pwm_initstruct.HEndAIEn = 0, \
.pwm_initstruct.NCycleAIEn = 0, \
.pwm_initstruct.HEndBIEn = 0, \
.pwm_initstruct.NCycleBIEn = 0, \
}
#endif /* PWM0_CFG */
#endif /* BSP_USING_PWM0 */
#ifdef BSP_USING_PWM1
#ifndef PWM1_CFG
#define PWM1_CFG \
{ \
.name = "pwm1", \
.PWMx = PWM1, \
.pwm_initstruct.clk_div = PWM_CLKDIV_8, \
.pwm_initstruct.mode = PWM_MODE_INDEP, \
.pwm_initstruct.cycleA = 10000, \
.pwm_initstruct.hdutyA = 5000, \
.pwm_initstruct.initLevelA = 1, \
.pwm_initstruct.cycleB = 10000, \
.pwm_initstruct.hdutyB = 5000, \
.pwm_initstruct.initLevelB = 1, \
.pwm_initstruct.HEndAIEn = 0, \
.pwm_initstruct.NCycleAIEn = 0, \
.pwm_initstruct.HEndBIEn = 0, \
.pwm_initstruct.NCycleBIEn = 0, \
}
#endif /* PWM1_CFG */
#endif /* BSP_USING_PWM1 */
#ifdef BSP_USING_PWM2
#ifndef PWM2_CFG
#define PWM2_CFG \
{ \
.name = "pwm2", \
.PWMx = PWM2, \
.pwm_initstruct.clk_div = PWM_CLKDIV_8, \
.pwm_initstruct.mode = PWM_MODE_INDEP, \
.pwm_initstruct.cycleA = 10000, \
.pwm_initstruct.hdutyA = 5000, \
.pwm_initstruct.initLevelA = 1, \
.pwm_initstruct.cycleB = 10000, \
.pwm_initstruct.hdutyB = 5000, \
.pwm_initstruct.initLevelB = 1, \
.pwm_initstruct.HEndAIEn = 0, \
.pwm_initstruct.NCycleAIEn = 0, \
.pwm_initstruct.HEndBIEn = 0, \
.pwm_initstruct.NCycleBIEn = 0, \
}
#endif /* PWM2_CFG */
#endif /* BSP_USING_PWM2 */
#ifdef BSP_USING_PWM3
#ifndef PWM3_CFG
#define PWM3_CFG \
{ \
.name = "pwm3", \
.PWMx = PWM3, \
.pwm_initstruct.clk_div = PWM_CLKDIV_8, \
.pwm_initstruct.mode = PWM_MODE_INDEP, \
.pwm_initstruct.cycleA = 10000, \
.pwm_initstruct.hdutyA = 5000, \
.pwm_initstruct.initLevelA = 1, \
.pwm_initstruct.cycleB = 10000, \
.pwm_initstruct.hdutyB = 5000, \
.pwm_initstruct.initLevelB = 1, \
.pwm_initstruct.HEndAIEn = 0, \
.pwm_initstruct.NCycleAIEn = 0, \
.pwm_initstruct.HEndBIEn = 0, \
.pwm_initstruct.NCycleBIEn = 0, \
}
#endif /* PWM3_CFG */
#endif /* BSP_USING_PWM3 */
#ifdef BSP_USING_PWM4
#ifndef PWM4_CFG
#define PWM4_CFG \
{ \
.name = "pwm4", \
.PWMx = PWM4, \
.pwm_initstruct.clk_div = PWM_CLKDIV_8, \
.pwm_initstruct.mode = PWM_MODE_INDEP, \
.pwm_initstruct.cycleA = 10000, \
.pwm_initstruct.hdutyA = 5000, \
.pwm_initstruct.initLevelA = 1, \
.pwm_initstruct.cycleB = 10000, \
.pwm_initstruct.hdutyB = 5000, \
.pwm_initstruct.initLevelB = 1, \
.pwm_initstruct.HEndAIEn = 0, \
.pwm_initstruct.NCycleAIEn = 0, \
.pwm_initstruct.HEndBIEn = 0, \
.pwm_initstruct.NCycleBIEn = 0, \
}
#endif /* PWM4_CFG */
#endif /* BSP_USING_PWM4 */
#ifdef BSP_USING_PWM5
#ifndef PWM5_CFG
#define PWM5_CFG \
{ \
.name = "pwm5", \
.PWMx = PWM5, \
.pwm_initstruct.clk_div = PWM_CLKDIV_8, \
.pwm_initstruct.mode = PWM_MODE_INDEP, \
.pwm_initstruct.cycleA = 10000, \
.pwm_initstruct.hdutyA = 5000, \
.pwm_initstruct.initLevelA = 1, \
.pwm_initstruct.cycleB = 10000, \
.pwm_initstruct.hdutyB = 5000, \
.pwm_initstruct.initLevelB = 1, \
.pwm_initstruct.HEndAIEn = 0, \
.pwm_initstruct.NCycleAIEn = 0, \
.pwm_initstruct.HEndBIEn = 0, \
.pwm_initstruct.NCycleBIEn = 0, \
}
#endif /* PWM5_CFG */
#endif /* BSP_USING_PWM5 */
int rt_hw_pwm_init(void);
#endif /* __DRV_PWM_H__ */

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