mirror of https://github.com/RT-Thread/rt-thread
code format
This commit is contained in:
bigmagic
parent
39224e4888
commit
a97b0a0d39
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@ -14,7 +14,6 @@
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#include <rtthread.h>
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#include "ls2k1000.h"
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struct loongson_pll {
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rt_uint64_t PLL_SYS_0;
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rt_uint64_t PLL_SYS_1;
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@ -36,6 +36,5 @@ struct loongson_gpio {
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int loongson_pin_init(void);
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#endif
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@ -53,7 +53,6 @@
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#define FIFO_TRIGGER_8 0x80 /* trigger at 8 chars */
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#define FIFO_TRIGGER_14 0xc0 /* trigger at 14 chars */
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// 线路控制寄存器
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/* character format control register */
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#define CFCR_DLAB 0x80 /* divisor latch */
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#define CFCR_SBREAK 0x40 /* send break */
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@ -64,11 +64,11 @@
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#define LS2K_GPIO2_INT_IRQ (62)
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#define LS2K_GPIO3_INT_IRQ (63)
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#define MAX_INTR 64
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#define LIOINTC0_IRQBASE 0
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#define LIOINTC1_IRQBASE 32
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#define MAX_INTR (64)
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#define LIOINTC0_IRQBASE (0)
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#define LIOINTC1_IRQBASE (32)
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#define LIOINTC_SHIFT_INTx 4
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#define LIOINTC_SHIFT_INTx (4)
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#define LIOINTC_COREx_INTy(x, y) ((1 << x) | (1 << (y + LIOINTC_SHIFT_INTx)))
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#define LIOINTC_INTC_CHIP_START 0x20
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@ -6,8 +6,8 @@
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#define APB_BASE CKSEG1ADDR(0xbfe00000)
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#define UART0_BASE_ADDR 0xbfe00000
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#define UART0_OFF 0x0
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#define UART0_BASE_ADDR (0xbfe00000)
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#define UART0_OFF (0x0)
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#define UART0_BASE CKSEG1ADDR(UART0_BASE_ADDR + UART0_OFF)
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#define UARTx_BASE(x) ((APB_BASE | (0x0 << 12) | (x << 8)))
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@ -18,11 +18,11 @@
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#define LIOINTC1_BASE CKSEG1ADDR(0x1fe11440)
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#define CORE0_INTISR1 CKSEG1ADDR(0x1fe11048)
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#define GPIO_BASE 0xFFFFFFFFBFE10500
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#define PLL_SYS_BASE 0xFFFFFFFFBFE10480
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#define RTC_BASE 0xFFFFFFFFBFE07820
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#define GPIO_BASE (0xFFFFFFFFBFE10500)
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#define PLL_SYS_BASE (0xFFFFFFFFBFE10480)
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#define RTC_BASE (0xFFFFFFFFBFE07820)
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#define GEN_CONFIG0_REG 0xFFFFFFFFBfe10420
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#define GEN_CONFIG0_REG (0xFFFFFFFFBfe10420)
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void rt_hw_timer_handler(void);
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void rt_hw_uart_init(void);
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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* Copyright (c) 2006-2020, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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@ -260,7 +260,6 @@ s32 synopGMAC_check_phy_init(synopGMACPciNetworkAdapter *adapter)
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return gmacdev->Speed | (gmacdev->DuplexMode << 4);
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}
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static int Mac_change_check(u8 *macaddr0, u8 *macaddr1)
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{
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int i;
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@ -894,7 +893,6 @@ int rt_hw_eth_init(void)
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struct synopGMACNetworkAdapter *synopGMACadapter;
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static u8 mac_addr0[6] = DEFAULT_MAC_ADDRESS;
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int index;
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//rt_kprintf("rt_hw_eth_init 1\n");
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rt_sem_init(&sem_ack, "tx_ack", 1, RT_IPC_FLAG_FIFO);
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rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
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@ -958,8 +956,6 @@ int rt_hw_eth_init(void)
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eth_device_init(&(eth_dev.parent), "e0");
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eth_device_linkchange(ð_dev.parent, RT_TRUE); //linkup the e0 for lwip to check
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//rt_kprintf("rt_hw_eth_init 2\n");
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return 0;
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}
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INIT_COMPONENT_EXPORT(rt_hw_eth_init);
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@ -860,7 +860,6 @@ void synopGMAC_promisc_disable(synopGMACdevice *gmacdev)
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return;
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}
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/**
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* Enables unicast hash filtering.
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* When enabled GMAC performs the destination address filtering of unicast frames according to the hash table.
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@ -1032,7 +1031,6 @@ void synopGMAC_pause_control(synopGMACdevice *gmacdev)
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synopGMACWriteReg(gmacdev -> MacBase,GmacFlowControl,mac_flow_control_reg);
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return;
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}
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/**
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@ -1355,7 +1353,6 @@ void synopGMAC_tx_desc_init_ring(DmaDesc *desc, bool last_ring_desc)
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desc -> status = 0;
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#endif
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//sw
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desc -> buffer1 = 0;
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desc -> buffer2 = 0;
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desc -> data1 = 0;
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@ -1365,8 +1362,6 @@ void synopGMAC_tx_desc_init_ring(DmaDesc *desc, bool last_ring_desc)
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return;
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}
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/**
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* Initialize the rx descriptors for chain mode of operation.
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* - Status field is initialized to 0.
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@ -1409,7 +1404,6 @@ void synopGMAC_tx_desc_init_chain(DmaDesc * desc)
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return;
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}
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s32 synopGMAC_init_tx_rx_desc_queue(synopGMACdevice *gmacdev)
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{
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s32 i;
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@ -1817,7 +1811,6 @@ void synopGMAC_get_desc_data(DmaDesc *desc,u32 *Status,u32 *Buffer1,u32 *Length1
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}
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return;
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}
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#ifdef ENH_DESC_8W
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@ -1912,10 +1905,7 @@ s32 synopGMAC_get_tx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1
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u32 txover = gmacdev->TxBusy;
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DmaDesc * txdesc = gmacdev->TxBusyDesc;
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int i;
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//sw: dbg
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//pci_sync_cache(0, (vm_offset_t)txdesc, 64, SYNC_R);
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//pci_sync_cache(0, (vm_offset_t)txdesc, 64, SYNC_W);
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#if SYNOP_TX_DEBUG
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@ -2008,7 +1998,8 @@ s32 synopGMAC_set_tx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u
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(gmacdev->BusyTxDesc)++; //busy tx descriptor is reduced by one as it will be handed over to Processor now
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if(synopGMAC_is_tx_desc_chained(txdesc)){
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if(synopGMAC_is_tx_desc_chained(txdesc))
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{
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txdesc->length |= ((Length1 <<DescSize1Shift) & DescSize1Mask);
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#ifdef ENH_DESC
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txdesc->status |= (DescTxFirst | DescTxLast | DescTxIntEnable); //ENH_DESC
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@ -2019,7 +2010,8 @@ s32 synopGMAC_set_tx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u
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txdesc->buffer1 = Buffer1;
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txdesc->data1 = Data1;
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if(offload_needed){
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if(offload_needed)
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{
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/*
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Make sure that the OS you are running supports the IP and TCP checkusm offloaidng,
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before calling any of the functions given below.
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@ -2037,7 +2029,8 @@ s32 synopGMAC_set_tx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u
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gmacdev->TxNext = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? 0 : txnext + 1;
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gmacdev->TxNextDesc = (DmaDesc *)txdesc->data2;
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}
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else{
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else
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{
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// printf("synopGMAC_set_tx_qptr:in ring mode\n");
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txdesc->length |= (((Length1 <<DescSize1Shift) & DescSize1Mask) | ((Length2 <<DescSize2Shift) & DescSize2Mask));
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#ifdef ENH_DESC
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@ -2052,7 +2045,8 @@ s32 synopGMAC_set_tx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u
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txdesc->buffer2 = Buffer2;
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txdesc->data2 = Data2;
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if(offload_needed){
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if(offload_needed)
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{
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/*
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Make sure that the OS you are running supports the IP and TCP checkusm offloaidng,
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before calling any of the functions given below.
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@ -2639,7 +2633,6 @@ void synopGMAC_take_desc_ownership_tx(synopGMACdevice * gmacdev)
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synopGMAC_take_desc_ownership(desc + i);
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}
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}
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}
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/**
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@ -2669,14 +2662,7 @@ void synopGMAC_disable_dma_rx(synopGMACdevice * gmacdev)
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data &= (~DmaRxStart);
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synopGMACWriteReg(gmacdev->DmaBase, DmaControl ,data);
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}
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/*******************PMT APIs***************************************/
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/**
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* Enables the assertion of PMT interrupt.
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* This enables the assertion of PMT interrupt due to Magic Pkt or Wakeup frame
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@ -2835,9 +2821,9 @@ void synopGMAC_write_wakeup_frame_register(synopGMACdevice *gmacdev, u32 * filte
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}
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#endif
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/*******************PMT APIs***************************************/
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/*******************MMC APIs***************************************/
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/**
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* Freezes the MMC counters.
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* This function call freezes the MMC counters. None of the MMC counters are updated
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@ -3081,7 +3067,6 @@ void synopGMAC_rx_tcpip_chksum_drop_disable(synopGMACdevice *gmacdev)
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* \return returns TRUE or FALSE
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*/
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#ifdef ENH_DESC_8W
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/**
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* This function indicates whether extended status is available in the RDES0.
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* Any function which accesses the fields of extended status register must ensure a check on this has been made
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@ -3132,8 +3117,6 @@ bool synopGMAC_ES_is_IP_payload_error(synopGMACdevice *gmacdev,u32 ext_status)
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}
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#endif
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/**
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* Decodes the Rx Descriptor status to various checksum error conditions.
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* @param[in] pointer to synopGMACdevice.
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@ -3172,7 +3155,6 @@ bool synopGMAC_is_tx_ipv4header_checksum_error(synopGMACdevice *gmacdev, u32 sta
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return((status & DescTxIpv4ChkError) == DescTxIpv4ChkError);
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}
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/**
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* Checks if any payload checksum error in the frame just transmitted.
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* This serves as indication that error occureed in the payload checksum insertion.
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@ -3199,7 +3181,6 @@ void synopGMAC_tx_checksum_offload_bypass(synopGMACdevice *gmacdev, DmaDesc *des
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#else
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desc->length = (desc->length & (~DescTxCisMask));
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#endif
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}
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/**
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* The check summ offload engine is enabled to do only IPV4 header checksum.
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@ -3215,7 +3196,6 @@ void synopGMAC_tx_checksum_offload_ipv4hdr(synopGMACdevice *gmacdev, DmaDesc *de
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#else
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desc->length = ((desc->length & (~DescTxCisMask)) | DescTxCisIpv4HdrCs);
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#endif
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}
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/**
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@ -3233,7 +3213,6 @@ void synopGMAC_tx_checksum_offload_tcponly(synopGMACdevice *gmacdev, DmaDesc *de
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#else
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desc->length = ((desc->length & (~DescTxCisMask)) | DescTxCisTcpOnlyCs);
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#endif
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}
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/**
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* The check summ offload engine is enabled to do complete checksum computation.
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@ -3254,14 +3233,7 @@ void synopGMAC_tx_checksum_offload_tcp_pseudo(synopGMACdevice *gmacdev, DmaDesc
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}
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/*******************Ip checksum offloading APIs***************************************/
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/*******************IEEE 1588 Timestamping API***************************************/
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/*
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* At this time the driver supports the IEEE time stamping feature when the Enhanced Descriptors are enabled.
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* For normal descriptor and the IEEE time stamp (version 1), driver support is not proviced
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@ -3295,7 +3267,6 @@ void synopGMAC_TS_disable(synopGMACdevice *gmacdev)
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return;
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}
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/**
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* Enable the interrupt to get timestamping interrupt.
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* This enables the host to get the interrupt when (1) system time is greater or equal to the
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@ -3344,7 +3315,6 @@ void synopGMAC_TS_mac_addr_filt_disable(synopGMACdevice *gmacdev)
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return;
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}
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/**
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* Selet the type of clock mode for PTP.
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* Please note to use one of the follwoing as the clk_type argument.
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@ -3493,7 +3463,6 @@ void synopGMAC_TS_ptp_over_ethernet_disable(synopGMACdevice *gmacdev)
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return;
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}
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/**
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* Snoop PTP packet for version 2 format
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* When set the PTP packets are snooped using the version 2 format.
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@ -3588,7 +3557,6 @@ s32 synopGMAC_TS_addend_update(synopGMACdevice *gmacdev, u32 addend_value)
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return -ESYNOPGMACPHYERR;
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}
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return -ESYNOPGMACNOERR;
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}
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/**
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* time stamp Update
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@ -15,17 +15,17 @@
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#define SYNOP_GMAC_DEV_H 1
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/*******************************************************************/
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#define SYNOP_LOOPBACK_MODE 0
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#define SYNOP_LOOPBACK_DEBUG 0
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#define SYNOP_PHY_LOOPBACK 0
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#define SYNOP_LOOPBACK_MODE (0)
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#define SYNOP_LOOPBACK_DEBUG (0)
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#define SYNOP_PHY_LOOPBACK (0)
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#define SYNOP_TX_TEST 0
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#define SYNOP_RX_TEST 0
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#define SYNOP_TX_TEST (0)
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#define SYNOP_RX_TEST (0)
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#define SYNOP_TOP_DEBUG 0
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#define SYNOP_REG_DEBUG 0
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#define SYNOP_RX_DEBUG 0
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#define SYNOP_TX_DEBUG 0
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#define SYNOP_TOP_DEBUG (0)
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#define SYNOP_REG_DEBUG (0)
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#define SYNOP_RX_DEBUG (0)
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#define SYNOP_TX_DEBUG (0)
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#define ENH_DESC
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/*******************************************************************/
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@ -148,7 +148,6 @@ typedef struct synopGMACDeviceStruct
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u64 PhyBase; /* PHY device address on MII interface */
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u32 Version; /* Gmac Revision version */
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dma_addr_t TxDescDma; /* Dma-able address of first tx descriptor either in ring or chain mode, this is used by the GMAC device*/
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dma_addr_t RxDescDma; /* Dma-able address of first rx descriptor either in ring or chain mode, this is used by the GMAC device*/
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DmaDesc *TxDesc; /* start address of TX descriptors ring or chain, this is used by the driver */
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@ -178,19 +177,15 @@ typedef struct synopGMACDeviceStruct
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u32 DuplexMode; /* Duplex mode of the Phy */
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u32 Speed; /* Speed of the Phy */
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u32 LoopBackMode; /* Loopback status of the Phy */
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// void * FirstTxDesc;
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// void * FirstRxDesc;
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// u32 skb_array[RECEIVE_DESC_SIZE];
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} synopGMACdevice;
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/* Below is "88E1011/88E1011S Integrated 10/100/1000 Gigabit Ethernet Transceiver"
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* Register and their layouts. This Phy has been used in the Dot Aster GMAC Phy daughter.
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* Since the Phy register map is standard, this map hardly changes to a different Ppy
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*/
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enum MiiRegisters
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{
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PHY_CONTROL_REG = 0x0000, /*Control Register*/
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@ -218,10 +213,8 @@ enum MiiRegisters
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PHY_CBL_DIAG_REG = 0x001c, /*Cable diagnostic registers*/
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};
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/* This is Control register layout. Control register is of 16 bit wide.
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*/
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enum Mii_GEN_CTRL
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{ /* Description bits R/W default value */
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Mii_reset = 0x8000,
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@ -281,8 +274,6 @@ enum Mii_Loop_Back
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LOOPBACK = 1,
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};
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/**********************************************************
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* GMAC registers Map
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* For Pci based system address is BARx + GmacRegisterBase
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@ -502,7 +493,6 @@ enum GmacFrameFilterReg
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GmacPromiscuousModeOff = 0x00000000, /* Receive filtered packets only 0 */
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};
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/*GmacGmiiAddr = 0x0010, GMII address Register(ext. Phy) Layout */
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enum GmacGmiiAddrReg
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{
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@ -532,7 +522,6 @@ enum GmacGmiiDataReg
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GmiiDataMask = 0x0000FFFF, /* (GD)GMII Data 15:0 RW 0x0000 */
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};
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/*GmacFlowControl = 0x0018, Flow control Register Layout */
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enum GmacFlowControlReg
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{
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@ -573,7 +562,6 @@ enum GmacInterruptStatusBitDefinition
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GmacPcsAnComplete = 0x00000004, /* set when AN is complete in TBI/RTBI/SGMIII phy interface */
|
||||
GmacPcsLnkStsChange = 0x00000002, /* set if any lnk status change in TBI/RTBI/SGMII interface */
|
||||
GmacRgmiiIntSts = 0x00000001, /* set if any change in lnk status of RGMII interface */
|
||||
|
||||
};
|
||||
|
||||
/* GmacInterruptMask = 0x003C, Mac Interrupt Mask register */
|
||||
|
|
@ -591,7 +579,6 @@ enum GmacInterruptMaskBitDefinition
|
|||
* For Pci based system address is BARx + GmaDmaBase
|
||||
* For any other system translation is done accordingly
|
||||
**********************************************************/
|
||||
|
||||
enum DmaRegisters
|
||||
{
|
||||
DmaBusMode = 0x0000, /* CSR0 - Bus Mode Register */
|
||||
|
|
@ -654,7 +641,6 @@ enum DmaBusModeReg
|
|||
DmaResetOff = 0x00000000, /* 0 */
|
||||
};
|
||||
|
||||
|
||||
/*DmaStatus = 0x0014, CSR5 - Dma status Register */
|
||||
enum DmaStatusReg
|
||||
{
|
||||
|
|
@ -883,28 +869,21 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */
|
|||
DescTxExcDeferral = 0x00000004, /* (ED)Tx - excessive deferral 2 */
|
||||
DescTxUnderflow = 0x00000002, /* (UF)Tx - late data arrival from the memory 1 */
|
||||
DescTxDeferred = 0x00000001, /* (DB)Tx - frame transmision deferred 0 */
|
||||
|
||||
/*
|
||||
This explains the RDES1/TDES1 bits layout
|
||||
--------------------------------------------------------------------
|
||||
RDES1/TDES1 | Control Bits | Byte Count Buffer 2 | Byte Count Buffer 1 |
|
||||
--------------------------------------------------------------------
|
||||
|
||||
*/
|
||||
// DmaDescriptorLength length word of DMA descriptor
|
||||
|
||||
|
||||
RxDisIntCompl = 0x80000000, /* (Disable Rx int on completion) 31 */
|
||||
RxDescEndOfRing = 0x00008000, /* (TER)End of descriptors ring 15 */
|
||||
RxDescChain = 0x00004000, /* (TCH)Second buffer address is chain address 14 */
|
||||
|
||||
|
||||
DescSize2Mask = 0x1FFF0000, /* (TBS2) Buffer 2 size 28:16 */
|
||||
DescSize2Shift = 16,
|
||||
DescSize1Mask = 0x00001FFF, /* (TBS1) Buffer 1 size 12:0 */
|
||||
DescSize1Shift = 0,
|
||||
|
||||
|
||||
/*
|
||||
This explains the RDES4 Extended Status bits layout
|
||||
--------------------------------------------------------------------
|
||||
|
|
@ -1023,7 +1002,6 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */
|
|||
|
||||
*/
|
||||
//DmaDescriptorLength length word of DMA descriptor
|
||||
|
||||
DescTxIntEnable = 0x80000000, /* (IC)Tx - interrupt on completion 31 */
|
||||
DescTxLast = 0x40000000, /* (LS)Tx - Last segment of the frame 30 */
|
||||
DescTxFirst = 0x20000000, /* (FS)Tx - First segment of the frame 29 */
|
||||
|
|
@ -1043,7 +1021,6 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */
|
|||
DescSize1Mask = 0x000007FF, /* (TBS1) Buffer 1 size 10:0 */
|
||||
DescSize1Shift = 0,
|
||||
|
||||
|
||||
DescTxCisMask = 0x18000000, /* Tx checksum offloading control mask 28:27 */
|
||||
DescTxCisBypass = 0x00000000, /* Checksum bypass */
|
||||
DescTxCisIpv4HdrCs = 0x08000000, /* IPv4 header checksum */
|
||||
|
|
@ -1138,8 +1115,6 @@ enum InitialRegisters
|
|||
/* Half-duplex mode */
|
||||
GmacGmiiAddrInitHdx = GmiiCsrClk2,
|
||||
|
||||
|
||||
|
||||
/**********************************************
|
||||
*DMA configurations
|
||||
**********************************************/
|
||||
|
|
@ -1249,6 +1224,7 @@ enum MMC_RX
|
|||
|
||||
GmacMmcRxWatchdobError = 0x01DC, /*Number of frames rx with error due to watchdog timeout error */
|
||||
};
|
||||
|
||||
enum MMC_IP_RELATED
|
||||
{
|
||||
GmacMmcRxIpcIntrMask = 0x0200, /*Maintains the mask for interrupt generated from rx IPC statistic counters */
|
||||
|
|
@ -1300,7 +1276,6 @@ enum MMC_CNTRL_REG_BIT_DESCRIPTIONS
|
|||
GmacMmcCounterResetOnRead = 0x00000004, /* when set MMC counters will be reset to 0 after read */
|
||||
GmacMmcCounterStopRollover = 0x00000002, /* when set counters will not rollover after max value */
|
||||
GmacMmcCounterReset = 0x00000001, /* when set all counters wil be reset (automatically cleared after 1 clk) */
|
||||
|
||||
};
|
||||
|
||||
enum MMC_RX_INTR_MASK_AND_STATUS_BIT_DESCRIPTIONS
|
||||
|
|
@ -1359,7 +1334,6 @@ enum MMC_TX_INTR_MASK_AND_STATUS_BIT_DESCRIPTIONS
|
|||
GmacMmcTxBcFramesInt = 0x00000004, /* set when GmacMmcTxBcFramesG counter reaches half of max value */
|
||||
GmacMmcTxFrameGbInt = 0x00000002, /* set when GmacMmcTxFrameCountGb counter reaches half of max value */
|
||||
GmacMmcTxOctetGbInt = 0x00000001, /* set when GmacMmcTxOctetCountGb counter reaches half of max value */
|
||||
|
||||
};
|
||||
|
||||
|
||||
|
|
@ -1394,9 +1368,6 @@ enum GmacPmtCtrlStatusBitDefinition
|
|||
GmacPmtPowerDown = 0x00000001, /* Power Down */
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
||||
/**********************************************************
|
||||
* IEEE 1588-2008 Precision Time Protocol (PTP) Support
|
||||
**********************************************************/
|
||||
|
|
@ -1414,8 +1385,6 @@ enum PTPMessageType
|
|||
Management = 0xD,
|
||||
};
|
||||
|
||||
|
||||
|
||||
typedef struct TimeStampStruct
|
||||
{
|
||||
u32 TSversion; /* PTP Version 1 or PTP version2 */
|
||||
|
|
@ -1516,7 +1485,6 @@ enum GmacTSStatusReg
|
|||
GmacTSSecondsOverflow = 0x00000001, /* Time Stamp Seconds Overflow 0 RO 0 */
|
||||
};
|
||||
|
||||
|
||||
/**********************************************************
|
||||
* Time stamp related functions
|
||||
**********************************************************/
|
||||
|
|
|
|||
|
|
@ -7,7 +7,6 @@
|
|||
* Date Author Notes
|
||||
* 2020-07-26 lizhirui the first version
|
||||
*/
|
||||
|
||||
#ifndef __MIPS_MMU_H__
|
||||
#define __MIPS_MMU_H__
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
* Copyright (c) 2006-2020, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
|
|
@ -19,7 +19,7 @@
|
|||
#define MEMWT (2<<2) /* write through, no write allocate */
|
||||
#define SHAREDEVICE (1<<2) /* shared device */
|
||||
#define STRONGORDER (0<<2) /* strong ordered */
|
||||
#define XN (1<<4) /* eXecute Never */
|
||||
#define XN (1<<4) /* execute Never */
|
||||
#ifdef RT_USING_USERSPACE
|
||||
#define AP_RW (1<<10) /* supervisor=RW, user=No */
|
||||
#define AP_RO ((1<<10) |(1 << 15)) /* supervisor=RW, user=No */
|
||||
|
|
|
|||
Loading…
Reference in New Issue