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first commit of tm4c123bsp, validate on MDK5

This commit is contained in:
LYH-ux 2020-06-24 19:54:42 +08:00
parent 3408c57d9e
commit aebdcaccbb
149 changed files with 153048 additions and 0 deletions
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478
bsp/tm4c123bsp/.config Normal file
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#
# Automatically generated file; DO NOT EDIT.
# RT-Thread Configuration
#
#
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=8
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=1000
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=256
CONFIG_RT_USING_TIMER_SOFT=y
CONFIG_RT_TIMER_THREAD_PRIO=4
CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
CONFIG_RT_DEBUG=y
# CONFIG_RT_DEBUG_COLOR is not set
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
#
# Inter-Thread communication
#
CONFIG_RT_USING_SEMAPHORE=y
CONFIG_RT_USING_MUTEX=y
CONFIG_RT_USING_EVENT=y
CONFIG_RT_USING_MAILBOX=y
CONFIG_RT_USING_MESSAGEQUEUE=y
# CONFIG_RT_USING_SIGNALS is not set
#
# Memory Management
#
CONFIG_RT_USING_MEMPOOL=y
# CONFIG_RT_USING_MEMHEAP is not set
# CONFIG_RT_USING_NOHEAP is not set
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
# CONFIG_RT_USING_MEMTRACE is not set
CONFIG_RT_USING_HEAP=y
#
# Kernel Device Object
#
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_DEVICE_OPS is not set
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
CONFIG_RT_VER_NUM=0x40003
# CONFIG_RT_USING_CPU_FFS is not set
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
#
# RT-Thread Components
#
CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
CONFIG_RT_MAIN_THREAD_PRIORITY=10
#
# C++ features
#
# CONFIG_RT_USING_CPLUSPLUS is not set
#
# Command shell
#
CONFIG_RT_USING_FINSH=y
CONFIG_FINSH_THREAD_NAME="tshell"
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_CMD_SIZE=80
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_USING_MSH_DEFAULT=y
# CONFIG_FINSH_USING_MSH_ONLY is not set
CONFIG_FINSH_ARG_MAX=10
#
# Device virtual file system
#
# CONFIG_RT_USING_DFS is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_PIPE_BUFSZ=512
CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048
CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
CONFIG_RT_USING_SERIAL=y
CONFIG_RT_SERIAL_USING_DMA=y
CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
CONFIG_RT_USING_PIN=y
CONFIG_RT_USING_ADC=y
CONFIG_RT_USING_PWM=y
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
CONFIG_RT_USING_SPI=y
# CONFIG_RT_USING_QSPI is not set
# CONFIG_RT_USING_SPI_MSD is not set
# CONFIG_RT_USING_SFUD is not set
# CONFIG_RT_USING_ENC28J60 is not set
# CONFIG_RT_USING_SPI_WIFI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
# CONFIG_RT_USING_TOUCH is not set
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_PULSE_ENCODER is not set
# CONFIG_RT_USING_INPUT_CAPTURE is not set
# CONFIG_RT_USING_WIFI is not set
#
# Using USB
#
# CONFIG_RT_USING_USB_HOST is not set
# CONFIG_RT_USING_USB_DEVICE is not set
#
# POSIX layer and C standard library
#
CONFIG_RT_USING_LIBC=y
# CONFIG_RT_USING_PTHREADS is not set
# CONFIG_RT_USING_MODULE is not set
#
# Network
#
#
# Socket abstraction layer
#
# CONFIG_RT_USING_SAL is not set
#
# Network interface device
#
# CONFIG_RT_USING_NETDEV is not set
#
# light weight TCP/IP stack
#
# CONFIG_RT_USING_LWIP is not set
#
# AT commands
#
# CONFIG_RT_USING_AT is not set
#
# VBUS(Virtual Software BUS)
#
# CONFIG_RT_USING_VBUS is not set
#
# Utilities
#
# CONFIG_RT_USING_RYM is not set
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
#
# RT-Thread online packages
#
#
# IoT - internet of things
#
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_UMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_WEBNET is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_MYMQTT is not set
# CONFIG_PKG_USING_KAWAII_MQTT is not set
# CONFIG_PKG_USING_BC28_MQTT is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_LIBMODBUS is not set
# CONFIG_PKG_USING_FREEMODBUS is not set
# CONFIG_PKG_USING_LJSON is not set
# CONFIG_PKG_USING_EZXML is not set
# CONFIG_PKG_USING_NANOPB is not set
#
# Wi-Fi
#
#
# Marvell WiFi
#
# CONFIG_PKG_USING_WLANMARVELL is not set
#
# Wiced WiFi
#
# CONFIG_PKG_USING_WLAN_WICED is not set
# CONFIG_PKG_USING_RW007 is not set
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_CMUX is not set
# CONFIG_PKG_USING_PPP_DEVICE is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
# CONFIG_PKG_USING_ATSRV_SOCKET is not set
# CONFIG_PKG_USING_WIZNET is not set
#
# IoT Cloud
#
# CONFIG_PKG_USING_ONENET is not set
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
# CONFIG_PKG_USING_JOYLINK is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
# CONFIG_PKG_USING_IPMSG is not set
# CONFIG_PKG_USING_LSSDP is not set
# CONFIG_PKG_USING_AIRKISS_OPEN is not set
# CONFIG_PKG_USING_LIBRWS is not set
# CONFIG_PKG_USING_TCPSERVER is not set
# CONFIG_PKG_USING_PROTOBUF_C is not set
# CONFIG_PKG_USING_ONNX_PARSER is not set
# CONFIG_PKG_USING_ONNX_BACKEND is not set
# CONFIG_PKG_USING_DLT645 is not set
# CONFIG_PKG_USING_QXWZ is not set
# CONFIG_PKG_USING_SMTP_CLIENT is not set
# CONFIG_PKG_USING_ABUP_FOTA is not set
# CONFIG_PKG_USING_LIBCURL2RTT is not set
# CONFIG_PKG_USING_CAPNP is not set
# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
# CONFIG_PKG_USING_AGILE_TELNET is not set
#
# security packages
#
# CONFIG_PKG_USING_MBEDTLS is not set
# CONFIG_PKG_USING_libsodium is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
# CONFIG_PKG_USING_TFM is not set
#
# language packages
#
# CONFIG_PKG_USING_LUA is not set
# CONFIG_PKG_USING_JERRYSCRIPT is not set
# CONFIG_PKG_USING_MICROPYTHON is not set
#
# multimedia packages
#
# CONFIG_PKG_USING_OPENMV is not set
# CONFIG_PKG_USING_MUPDF is not set
# CONFIG_PKG_USING_STEMWIN is not set
# CONFIG_PKG_USING_WAVPLAYER is not set
# CONFIG_PKG_USING_TJPGD is not set
#
# tools packages
#
# CONFIG_PKG_USING_CMBACKTRACE is not set
# CONFIG_PKG_USING_EASYFLASH is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ADBD is not set
# CONFIG_PKG_USING_COREMARK is not set
# CONFIG_PKG_USING_DHRYSTONE is not set
# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
# CONFIG_PKG_USING_BS8116A is not set
# CONFIG_PKG_USING_URLENCODE is not set
#
# system packages
#
# CONFIG_PKG_USING_GUIENGINE is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_FAL is not set
# CONFIG_PKG_USING_FLASHDB is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
# CONFIG_PKG_USING_CMSIS is not set
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
# CONFIG_PKG_USING_THREAD_POOL is not set
# CONFIG_PKG_USING_ROBOTS is not set
# CONFIG_PKG_USING_EV is not set
# CONFIG_PKG_USING_SYSWATCH is not set
# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
# CONFIG_PKG_USING_PLCCORE is not set
#
# peripheral libraries and drivers
#
# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_SHT3X is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_U8G2 is not set
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_SX12XX is not set
# CONFIG_PKG_USING_SIGNAL_LED is not set
# CONFIG_PKG_USING_LEDBLINK is not set
# CONFIG_PKG_USING_LITTLED is not set
# CONFIG_PKG_USING_LKDGUI is not set
# CONFIG_PKG_USING_NRF5X_SDK is not set
# CONFIG_PKG_USING_NRFX is not set
# CONFIG_PKG_USING_WM_LIBRARIES is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_INFRARED is not set
# CONFIG_PKG_USING_ROSSERIAL is not set
# CONFIG_PKG_USING_AGILE_BUTTON is not set
# CONFIG_PKG_USING_AGILE_LED is not set
# CONFIG_PKG_USING_AT24CXX is not set
# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_PCA9685 is not set
# CONFIG_PKG_USING_I2C_TOOLS is not set
# CONFIG_PKG_USING_NRF24L01 is not set
# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
# CONFIG_PKG_USING_MAX17048 is not set
# CONFIG_PKG_USING_RPLIDAR is not set
# CONFIG_PKG_USING_AS608 is not set
# CONFIG_PKG_USING_RC522 is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
# CONFIG_PKG_USING_MULTI_RTIMER is not set
# CONFIG_PKG_USING_MAX7219 is not set
# CONFIG_PKG_USING_BEEP is not set
# CONFIG_PKG_USING_EASYBLINK is not set
# CONFIG_PKG_USING_PMS_SERIES is not set
# CONFIG_PKG_USING_CAN_YMODEM is not set
# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
# CONFIG_BSP_USING_SPI1 is not set
# CONFIG_BSP_USING_SPI2 is not set
# CONFIG_BSP_USING_SPI3 is not set
#
# miscellaneous packages
#
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
# CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_DSTR is not set
# CONFIG_PKG_USING_TINYFRAME is not set
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
# CONFIG_PKG_USING_DIGITALCTRL is not set
# CONFIG_PKG_USING_UPACKER is not set
# CONFIG_PKG_USING_UPARAM is not set
#
# samples: kernel and components samples
#
# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_VI is not set
# CONFIG_PKG_USING_NNOM is not set
# CONFIG_PKG_USING_LIBANN is not set
# CONFIG_PKG_USING_ELAPACK is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_UKAL is not set
#
# Hardware Drivers Config
#
CONFIG_tm4c123=y
#
# Onboard Peripheral Drivers
#
CONFIG_BSP_USING_USB_TO_USART=y
# CONFIG_BSP_USING_RS485_OR_RS232 is not set
# CONFIG_BSP_USING_SPI_FLASH is not set
# CONFIG_BSP_USING_RGB is not set
# CONFIG_BSP_USING_POT is not set
# CONFIG_BSP_USING_EEPROM is not set
# CONFIG_BSP_USING_ETH is not set
# CONFIG_BSP_USING_SDCARD is not set
#
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_GPIO=y
CONFIG_BSP_USING_UART=y
CONFIG_BSP_USING_UART0=y
CONFIG_BSP_USING_UART1=y
# CONFIG_BSP_UART1_RX_USING_DMA is not set
# CONFIG_BSP_USING_UART2 is not set
# CONFIG_BSP_USING_UART3 is not set
# CONFIG_BSP_USING_ON_CHIP_FLASH is not set
CONFIG_BSP_USING_SPI=y
CONFIG_BSP_USING_SPI0=y
# CONFIG_BSP_USING_I2C1 is not set
# CONFIG_BSP_USING_TIM is not set
CONFIG_BSP_USING_PWM=y
# CONFIG_BSP_USING_PWM0 is not set
# CONFIG_BSP_USING_PWM1 is not set
# CONFIG_BSP_USING_PWM2 is not set
# CONFIG_BSP_USING_PWM3 is not set
# CONFIG_BSP_USING_PWM4 is not set
# CONFIG_BSP_USING_PWM5 is not set
# CONFIG_BSP_USING_PWM6 is not set
CONFIG_BSP_USING_PWM7=y
CONFIG_BSP_USING_ADC=y
CONFIG_BSP_USING_ADC0=y
# CONFIG_BSP_USING_ADC1 is not set
# CONFIG_BSP_USING_ONCHIP_RTC is not set
# CONFIG_BSP_USING_WDT is not set
# CONFIG_BSP_USING_SDIO is not set
# CONFIG_BSP_USING_CAN is not set
# CONFIG_BSP_USING_USBD is not set
# CONFIG_BSP_USING_CRC is not set
#
# Board extended module Drivers
#

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bsp/tm4c123bsp/Kconfig Normal file
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mainmenu "RT-Thread Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config RTT_DIR
string
option env="RTT_ROOT"
default "../.."
config PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
source "board/Kconfig"

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bsp/tm4c123bsp/README.md Normal file
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# BSP README 模板
## 简介
本文档为ek-tm4c123gxl开发板的 BSP (板级支持包) 说明。
主要内容如下：
- 开发板资源介绍
- BSP 快速上手
- 进阶使用方法
通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
## 开发板介绍
【此处简单介绍一下开发板】
开发板外观如下图所示：
![](E:\00MyWorkSpace\tm4c123_rtos\tm4c123bsp\figures\board.jpg)
该开发板常用 **板载资源** 如下：
- MCU：TM4C123Gh6PM，主频 80MHz，256KB FLASH ，32KB RAM
- 外部 RAM：型号，xMB
- 外部 FLASH：型号，xMB
- 常用外设
- LED：1个三色，（红色，PF1），（蓝色，PF2）,（绿色，PF3）
- 按键：2个，SW1（PF4），SW2（兼具唤醒功能，PF0）
- 常用接口：ICDI（具串口功能）、USB接口
- 调试接口，ICDI
开发板更多详细信息请参考【TI】 [TM4C123G开发板介绍](https://www.ti.com/tool/EK-TM4C123GXL?DCMP=stellaris-launchpad&HQS=tm4c123g-launchpad)。
## 外设支持
本 BSP 目前对外设的支持情况如下：
| **板载外设** | **支持情况** | **备注** |
| :----------------- | :----------: | :------------------------------------- |
| USB 转串口 | 支持 | |
| SPI Flash | 暂不支持 | |
| 以太网 | 暂不支持 | |
| SD卡 | 暂不支持 | |
| CAN | 暂不支持 | |
| **片上外设** | **支持情况** | **备注** |
| GPIO | 支持 | PF0, PF1... PF4---> PIN: 0, 1...4 |
| UART | 支持 | UART0/1/2/3 |
| SPI | 支持 | SPI0/1/2 |
| I2C | 支持 | 软件 I2C |
| SDIO | 暂不支持 | 即将支持 |
| RTC | 暂不支持 | 即将支持 |
| PWM | 支持 | PWM0/1/2/3/4/5/6/7 |
| USB Device | 暂不支持 | 即将支持 |
| USB Host | 暂不支持 | 即将支持 |
| IWG | 暂不支持 | 即将支持 |
| **扩展模块** | **支持情况** | **备注** |
| xxx 模块 | 支持 | |
## 使用说明
使用说明分为如下两个章节：
- 快速上手
本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
- 进阶使用
本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
### 快速上手
本 BSP 为开发者提供 MDK4、MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
#### 硬件连接
使用数据线连接开发板到 PC，打开电源开关。
#### 编译下载
双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
> 工程默认配置使用 ICDI 仿真器下载程序，在通过USB连接开发板的基础上，点击下载按钮即可下载程序到开发板
#### 运行结果
下载程序成功之后，系统会自动运行，【这里写开发板运行起来之后的现象，如：LED 闪烁等】。
连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息:
```bash
\ | /
- RT - Thread Operating System
/ | \ 3.1.1 build Nov 19 2018
2006 - 2018 Copyright by rt-thread team
msh >
```
### 进阶使用
此 BSP 默认只开启了 GPIO 和 串口0 的功能，如果需使用 SD 卡、Flash 等更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下：
1. 在 bsp 下打开 env 工具。
2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
3. 输入`pkgs --update`命令更新软件包。
4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。
本章节更多详细的介绍请结合 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)学习使用。
## 注意事项
- 本BSP配置片上外设在board/tm4c123gh6pz_config.c/h中进行配置。配置时钟在board.c文件中进行
## 联系人信息
维护人:
- [AHTYDHD](https://github.com/LYH-ux), 邮箱：<1780328728@qq.com>

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# for module compiling
import os
Import('RTT_ROOT')
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')

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import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
# set RTT_ROOT
#if not os.getenv("RTT_ROOT"):
#RTT_ROOT="rt-thread"
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
try:
from building import *
except:
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
print(RTT_ROOT)
exit(-1)
TARGET = 'rt-thread.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
if rtconfig.PLATFORM == 'iar':
env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
env.Replace(ARFLAGS = [''])
env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map')
Export('RTT_ROOT')
Export('rtconfig')
SDK_ROOT = os.path.abspath('./')
if os.path.exists(SDK_ROOT + '/libraries'):
libraries_path_prefix = SDK_ROOT + '/libraries'
else:
libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
SDK_LIB = libraries_path_prefix
Export('SDK_LIB')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
tm4c123_library = 'TivaWare_C_series'
rtconfig.BSP_LIBRARY_TYPE = tm4c123_library
# include libraries
objs.extend(SConscript(os.path.join(libraries_path_prefix, tm4c123_library, 'SConscript')))
# include drivers
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'Drivers', 'SConscript')))
# make a building
DoBuilding(TARGET, objs)

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Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
src = Glob('*.c')
CPPPATH = [cwd, str(Dir('#'))]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-11-06 SummerGift first version
*/
#include <rtthread.h>
#include <rtdevice.h>
int main(void)
{
int count = 1;
/* set LED0 pin mode to output */
rt_pin_mode(2, PIN_MODE_OUTPUT);
while (count++)
{
rt_pin_write(2, PIN_HIGH);
rt_thread_mdelay(500);
rt_pin_write(2, PIN_LOW);
rt_thread_mdelay(500);
}
return RT_EOK;
}

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menu "Hardware Drivers Config"
config tm4c123
bool
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
default y
menu "Onboard Peripheral Drivers"
config BSP_USING_USB_TO_USART
bool "Enable USB TO USART (uart1)"
select BSP_USING_UART
select BSP_USING_UART1
default y
config BSP_USING_RS485_OR_RS232
bool "Enable RS485/RS232 (uart2 be shared)"
select BSP_USING_UART2
default n
config BSP_USING_SPI_FLASH
bool "Enable SPI FLASH (W25Q64 spi1)"
select BSP_USING_SPI
select BSP_USING_SPI1
select RT_USING_SFUD
select RT_SFUD_USING_SFDP
default n
config BSP_USING_RGB
bool "Enable RGB LED (timer3 channel2 - 4)"
select RT_USING_PWM
select BSP_USING_PWM
select BSP_USING_PWM3
select BSP_USING_PWM3_CH2
select BSP_USING_PWM3_CH3
select BSP_USING_PWM3_CH4
default n
config BSP_USING_POT
bool "Enable potentiometer"
select BSP_USING_ADC
select BSP_USING_ADC1
default n
config BSP_USING_EEPROM
bool "Enable I2C EEPROM (i2c1)"
select BSP_USING_I2C1
default n
config BSP_USING_ETH
bool "Enable Ethernet Driver (spi2)"
default n
select PKG_USING_WIZNET
select WIZNET_DEVICE_EXTERN_CONFIG
select BSP_USING_SPI2
if BSP_USING_ETH
if WIZNET_DEVICE_EXTERN_CONFIG
config WIZ_SPI_DEVICE
string
default "spi20"
config WIZ_RST_PIN
int
default 111
config WIZ_IRQ_PIN
int
default 104
endif
config EXTERNAL_PHY_ADDRESS
hex
default 0x00
endif
config BSP_USING_SDCARD
bool "Enable SDCARD (sdio)"
select BSP_USING_SDIO
select RT_USING_DFS
select RT_USING_DFS_ELMFAT
default n
endmenu
menu "On-chip Peripheral Drivers"
config BSP_USING_GPIO
bool "Enable GPIO"
select RT_USING_PIN
default y
menuconfig BSP_USING_UART
bool "Enable UART"
default y
select RT_USING_SERIAL
if BSP_USING_UART
config BSP_USING_UART0
bool "Enable UART0"
default y
config BSP_USING_UART1
bool "Enable UART1"
default n
config BSP_UART1_RX_USING_DMA
bool "Enable UART1 RX DMA"
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
default n
config BSP_USING_UART2
bool "Enable UART2"
default n
config BSP_UART2_RX_USING_DMA
bool "Enable UART2 RX DMA"
depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
default n
config BSP_USING_UART3
bool "Enable UART3"
default n
config BSP_UART3_RX_USING_DMA
bool "Enable UART3 RX DMA"
depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA
default n
endif
config BSP_USING_ON_CHIP_FLASH
bool "Enable on-chip FLASH"
default n
menuconfig BSP_USING_SPI
bool "Enable SPI BUS"
default n
select RT_USING_SPI
if BSP_USING_SPI
config BSP_USING_SPI0
bool "Enable SPI0 BUS"
default n
config BSP_USING_SPI1
bool "Enable SPI1 BUS"
default n
config BSP_SPI1_TX_USING_DMA
bool "Enable SPI1 TX DMA"
depends on BSP_USING_SPI1
default n
config BSP_SPI1_RX_USING_DMA
bool "Enable SPI1 RX DMA"
depends on BSP_USING_SPI1
select BSP_SPI1_TX_USING_DMA
default n
config BSP_USING_SPI2
bool "Enable SPI2 BUS"
default n
config BSP_SPI2_TX_USING_DMA
bool "Enable SPI2 TX DMA"
depends on BSP_USING_SPI2
default n
config BSP_SPI2_RX_USING_DMA
bool "Enable SPI2 RX DMA"
depends on BSP_USING_SPI2
select BSP_SPI2_TX_USING_DMA
default n
config BSP_USING_SPI3
bool "Enable SPI3 BUS"
default n
config BSP_SPI3_TX_USING_DMA
bool "Enable SPI3 TX DMA"
depends on BSP_USING_SPI3
default n
config BSP_SPI3_RX_USING_DMA
bool "Enable SPI3 RX DMA"
depends on BSP_USING_SPI3
select BSP_SPI3_TX_USING_DMA
default n
endif
menuconfig BSP_USING_I2C1
bool "Enable I2C1 BUS (software simulation)"
default n
select RT_USING_I2C
select RT_USING_I2C_BITOPS
select RT_USING_PIN
if BSP_USING_I2C1
config BSP_I2C1_SCL_PIN
int "i2c1 scl pin number"
range 0 175
default 22
config BSP_I2C1_SDA_PIN
int "I2C1 sda pin number"
range 0 175
default 23
endif
menuconfig BSP_USING_TIM
bool "Enable timer"
default n
select RT_USING_HWTIMER
if BSP_USING_TIM
config BSP_USING_TIM2
bool "Enable TIM2"
default n
config BSP_USING_TIM3
bool "Enable TIM3"
default n
config BSP_USING_TIM4
bool "Enable TIM4"
default n
config BSP_USING_TIM5
bool "Enable TIM5"
default n
endif
menuconfig BSP_USING_PWM
bool "Enable pwm"
default n
select RT_USING_PWM
if BSP_USING_PWM
menuconfig BSP_USING_PWM0
bool "Enable pwm0"
default n
if BSP_USING_PWM0
config BSP_USING_PWM0_CH1
bool "Enable PWM0 channel1"
default y
config BSP_USING_PWM0_CH2
bool "Enable PWM0 channel2"
default n
endif
config BSP_USING_PWM1
bool "Enable pwm1"
default n
config BSP_USING_PWM2
bool "Enable pwm2"
default n
config BSP_USING_PWM3
bool "Enable pwm3"
default n
config BSP_USING_PWM4
bool "Enable pwm4"
default n
config BSP_USING_PWM5
bool "Enable pwm5"
default n
config BSP_USING_PWM6
bool "Enable pwm6"
default n
config BSP_USING_PWM7
bool "Enable pwm7"
default n
endif
menuconfig BSP_USING_ADC
bool "Enable ADC"
default n
select RT_USING_ADC
if BSP_USING_ADC
config BSP_USING_ADC0
bool "Enable ADC0"
default n
config BSP_USING_ADC1
bool "Enable ADC1"
default n
endif
menuconfig BSP_USING_ONCHIP_RTC
bool "Enable RTC"
select RT_USING_RTC
select RT_USING_LIBC
default n
if BSP_USING_ONCHIP_RTC
choice
prompt "Select clock source"
default BSP_RTC_USING_LSE
config BSP_RTC_USING_LSE
bool "RTC USING LSE"
config BSP_RTC_USING_LSI
bool "RTC USING LSI"
endchoice
endif
config BSP_USING_WDT
bool "Enable Watchdog Timer"
select RT_USING_WDT
default n
config BSP_USING_SDIO
bool "Enable SDIO"
select RT_USING_SDIO
select RT_USING_DFS
default n
menuconfig BSP_USING_CAN
bool "Enable CAN"
default n
select RT_USING_CAN
if BSP_USING_CAN
config BSP_USING_CAN1
bool "using CAN1"
default n
endif
config BSP_USING_USBD
bool "Enable USB device"
select RT_USING_USB_DEVICE
default n
if BSP_USING_USBD
config BSP_USB_CONNECT_PIN
int "USB connect pin"
default 67
config BSP_USB_PULL_UP_STATUS
int "USB PULL UP STATUS"
default 0
endif
config BSP_USING_CRC
bool "Enable CRC (CRC-32 0x04C11DB7 Polynomial)"
select RT_USING_HWCRYPTO
select RT_HWCRYPTO_USING_CRC
# "Crypto device frame dose not support above 8-bits granularity"
# "Reserve progress, running well, about 32-bits granularity, such as stm32f1, stm32f4"
default n
endmenu
menu "Board extended module Drivers"
endmenu
endmenu

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import os
import rtconfig
from building import *
Import('SDK_LIB')
cwd = GetCurrentDir()
# add general drivers
src = Split('''
board.c
tm4c123_config.c
''')
path = [cwd]
#path += [cwd + '/CubeMX_Config/Inc']
startup_path_prefix = SDK_LIB
if rtconfig.CROSS_TOOL == 'gcc':
src += [startup_path_prefix + '/TivaWare_C_series/tm4c123_driverlib/startup/gcc/startup_gcc.c']
elif rtconfig.CROSS_TOOL == 'keil':
src += [startup_path_prefix + '/TivaWare_C_series/tm4c123_driverlib/startup/arm/startup_rvmdk.S']
elif rtconfig.CROSS_TOOL == 'iar':
src += [startup_path_prefix + '/TivaWare_C_series/tm4c123_driverlib/startup/iar/startup_rvmdk.S']
CPPDEFINES = ['PART_TM4C123GH6PM']
CPPDEFINES += ['TARGET_IS_TM4C123_RB1']
CPPDEFINES += ['rvmdk']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
Return('group')

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/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-07-24 Tanek the first version
* 2018-11-12 Ernest Chen modify copyright
*/
#include <stdint.h>
#include <stdbool.h>
#include "hw_ints.h"
#include "hw_sysctl.h"
#include "hw_memmap.h"
#include "hw_types.h"
#include "fpu.h"
#include "debug.h"
#include "pin_map.h"
#include "rom.h"
#include "sysctl.h"
#include "systick.h"
#include "hw_ints.h"
#include "board.h"
// Holds the system core clock, which is the system clock
// frequency supplied to the SysTick timer and the processor
// core clock.
uint32_t SystemCoreClock;
void SystemCoreClockUpdate(void)
{
FPULazyStackingEnable();
//
// Set the clocking to run directly from the crystal.
//
SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ |
SYSCTL_OSC_MAIN);
SystemCoreClock = SysCtlClockGet();
}
void SysTickConfig()
{
SysTickDisable();
SysTickPeriodSet(SystemCoreClock/RT_TICK_PER_SECOND);
SysTickIntEnable();
SysTickEnable();
}
/**
* This function will initial your board.
*/
void rt_hw_board_init()
{
/* System Clock Update */
SystemCoreClockUpdate();
/* System Tick Configuration */
SysTickConfig();
#ifdef RT_USING_SERIAL
rt_hw_usart_init();
#endif
#ifdef RT_USING_PIN
rt_hw_pin_init();
#endif
#ifdef RT_USING_PWM
rt_hw_pwm_init();
#endif
/* Call components board initial (use INIT_BOARD_EXPORT()) */
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP)
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
#endif
}
void SysTick_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
rt_tick_increase();
/* leave interrupt */
rt_interrupt_leave();
}

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#ifndef _BOARD_H_
#define _BOARD_H_
#include <rthw.h>
#include <rtthread.h>
#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP)
#define TM4C123_SRAM1_START (0x20000000)
#define TM4C123_SRAM1_END (TM4C123_SRAM1_START + 32 * 1024) // end address = 0x20000000(base adddress) + 32K(RAM size)
#if defined(__CC_ARM) || defined(__CLANG_ARM)
extern int Image$$RW_IRAM$$ZI$$Limit; // RW_IRAM
#define HEAP_BEGIN ((void *)&Image$$RW_IRAM$$ZI$$Limit)
#endif
#define HEAP_END TM4C123_SRAM1_END
#endif
#ifdef RT_USING_PIN
#include "drv_gpio.h"
#endif /* RT_USING_PIN */
#ifdef RT_USING_SERIAL
#include "drv_uart.h"
#endif /* RT_USING_SERIAL */
#ifdef RT_USING_PWM
#include "drv_pwm.h"
#endif /* RT_USING_PWM*/
#ifdef RT_USING_SPI
#include "drv_spi.h"
#endif /* RT_USING_SPI*/
#endif /*_BOARD_H_*/

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//*****************************************************************************
//
// hello.icf - Linker configuration file for hello.
//
// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 2.1.4.178 of the EK-TM4C123GXL Firmware Package.
//
//*****************************************************************************
//
// Define a memory region that covers the entire 4 GB addressible space of the
// processor.
//
define memory mem with size = 4G;
//
// Define a region for the on-chip flash.
//
define region FLASH = mem:[from 0x00000000 to 0x0003ffff];
//
// Define a region for the on-chip SRAM.
//
define region SRAM = mem:[from 0x20000000 to 0x20007fff];
//
// Define a block for the heap. The size should be set to something other
// than zero if things in the C library that require the heap are used.
//
define block HEAP with alignment = 8, size = 0x00000000 { };
//
// Indicate that the read/write values should be initialized by copying from
// flash.
//
initialize by copy { readwrite };
//
// Indicate that the noinit values should be left alone. This includes the
// stack, which if initialized will destroy the return address from the
// initialization code, causing the processor to branch to zero and fault.
//
do not initialize { section .noinit };
//
// Place the interrupt vectors at the start of flash.
//
place at start of FLASH { readonly section .intvec };
//
// Place the remainder of the read-only items into flash.
//
place in FLASH { readonly };
//
// Place the RAM vector table at the start of SRAM.
//
place at start of SRAM { section VTABLE };
//
// Place all read/write items into SRAM.
//
place in SRAM { readwrite, block HEAP };

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/******************************************************************************
*
* hello.ld - Linker configuration file for hello.
*
* Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved.
* Software License Agreement
*
* Texas Instruments (TI) is supplying this software for use solely and
* exclusively on TI's microcontroller products. The software is owned by
* TI and/or its suppliers, and is protected under applicable copyright
* laws. You may not combine this software with "viral" open-source
* software in order to form a larger program.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
* NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
* CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
* DAMAGES, FOR ANY REASON WHATSOEVER.
*
* This is part of revision 2.1.4.178 of the EK-TM4C123GXL Firmware Package.
*
*****************************************************************************/
MEMORY
{
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
}
SECTIONS
{
.text :
{
_text = .;
KEEP(*(.isr_vector))
*(.text*)
*(.rodata*)
_etext = .;
} > FLASH
.data : AT(ADDR(.text) + SIZEOF(.text))
{
_data = .;
_ldata = LOADADDR (.data);
*(vtable)
*(.data*)
_edata = .;
} > SRAM
.bss :
{
_bss = .;
*(.bss*)
*(COMMON)
_ebss = .;
} > SRAM
}

47
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;******************************************************************************
;
; hello.sct - Linker configuration file for hello.
;
; Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved.
; Software License Agreement
;
; Texas Instruments (TI) is supplying this software for use solely and
; exclusively on TI's microcontroller products. The software is owned by
; TI and/or its suppliers, and is protected under applicable copyright
; laws. You may not combine this software with "viral" open-source
; software in order to form a larger program.
;
; THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
; NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
; NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
; A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
; CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
; DAMAGES, FOR ANY REASON WHATSOEVER.
;
; This is part of revision 2.1.4.178 of the EK-TM4C123GXL Firmware Package.
;
;******************************************************************************
LR_IROM 0x00000000 0x00040000
{
;
; Specify the Execution Address of the code and the size.
;
ER_IROM 0x00000000 0x00040000
{
*.o (RESET, +First)
* (InRoot$$Sections, +RO)
}
;
; Specify the Execution Address of the data area.
;
RW_IRAM 0x20000000 0x00008000
{
;
; Uncomment the following line in order to use IntRegister().
;
;* (vtable, +First)
* (+RW, +ZI)
}
}

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#include "stdbool.h"
#include "stdint.h"
#include "hw_memmap.h"
#include "pin_map.h"
#include "sysctl.h"
#include "pwm.h"
#include "gpio.h"
#include "uart.h"
#include "adc.h"
#include "ssi.h"
#include "tm4c123_config.h"
void uart_hw_config(void)
{
SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
GPIOPinConfigure(GPIO_PA0_U0RX);
GPIOPinConfigure(GPIO_PA1_U0TX);
GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
SysCtlPeripheralEnable(SYSCTL_PERIPH_UART1);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
GPIOPinConfigure(GPIO_PC4_U1RX);
GPIOPinConfigure(GPIO_PC5_U1TX);
GPIOPinTypeUART(GPIO_PORTC_BASE, GPIO_PIN_4 | GPIO_PIN_5);
}
void pwm_hw_config(void)
{
SysCtlPWMClockSet(SYSCTL_PWMDIV_2);
//GPIO port D needs to be enabled so these pins can be used.
SysCtlPeripheralEnable(SYSCTL_PERIPH_PWM1);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
// Configure the GPIO pin muxing to select PWM functions for these pins.
GPIOPinConfigure(GPIO_PF2_M1PWM6);
GPIOPinConfigure(GPIO_PF3_M1PWM7);
// Configure the GPIO pad for PWM function on pins PF2 and PF3
GPIOPinTypePWM(GPIO_PORTF_BASE, GPIO_PIN_2|GPIO_PIN_3);
}
void adc_hw_config(void)
{
// The ADC0 peripheral must be enabled for use.
//
SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC0);
// GPIO port D needs to be enabled
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
// Select the analog ADC function for these pins.
GPIOPinTypeADC(GPIO_PORTD_BASE, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3);
}
void spi_hw_config(void)
{
SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
GPIOPinConfigure(GPIO_PA2_SSI0CLK);
//GPIOPinConfigure(GPIO_PA3_SSI0FSS);
GPIOPinConfigure(GPIO_PA4_SSI0RX);
GPIOPinConfigure(GPIO_PA5_SSI0TX);
GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_5 | GPIO_PIN_4 | GPIO_PIN_2);
}

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bsp/tm4c123bsp/board/tm4c123_config.h Normal file
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#ifndef _TM4C123GH6PZ_CONFIG_H_
#define _TM4C123GH6PZ_CONFIG_H_
#ifdef __cplusplus
extern "C" {
#endif
void uart_hw_config(void);
void pwm_hw_config(void);
void adc_hw_config(void);
void spi_hw_config(void);
#ifdef __cplusplus
}
#endif
#endif /*_TM4C123GH6PZ_CONFIG_H_*/

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bsp/tm4c123bsp/libraries/Drivers/SConscript Normal file
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Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
# add the general drivers.
src = Split("""
""")
if GetDepend(['RT_USING_PIN']):
src += ['drv_gpio.c']
if GetDepend(['RT_USING_SERIAL']):
src += ['drv_uart.c']
if GetDepend(['RT_USING_HWTIMER']):
src += ['drv_hwtimer.c']
if GetDepend(['RT_USING_PWM']):
src += ['drv_pwm.c']
if GetDepend(['RT_USING_SPI']):
src += ['drv_spi.c']
if GetDepend(['RT_USING_QSPI']):
src += ['drv_qspi.c']
if GetDepend(['RT_USING_I2C', 'RT_USING_I2C_BITOPS']):
if GetDepend('BSP_USING_I2C1') or GetDepend('BSP_USING_I2C2') or GetDepend('BSP_USING_I2C3') or GetDepend('BSP_USING_I2C4'):
src += ['drv_soft_i2c.c']
if GetDepend(['BSP_USING_ETH', 'RT_USING_LWIP']):
src += ['drv_eth.c']
if GetDepend(['RT_USING_ADC']):
src += Glob('drv_adc.c')
if GetDepend(['RT_USING_CAN']):
src += ['drv_can.c']
if GetDepend(['RT_USING_PM', 'SOC_SERIES_STM32L4']):
src += ['drv_pm.c']
src += ['drv_lptim.c']
if GetDepend('BSP_USING_SDRAM'):
src += ['drv_sdram.c']
if GetDepend('BSP_USING_LCD'):
src += ['drv_lcd.c']
if GetDepend('BSP_USING_LCD_MIPI'):
src += ['drv_lcd_mipi.c']
if GetDepend('BSP_USING_ONCHIP_RTC'):
src += ['drv_rtc.c']
if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F0']):
src += ['drv_flash/drv_flash_f0.c']
if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F1']):
src += ['drv_flash/drv_flash_f1.c']
if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F2']):
src += ['drv_flash/drv_flash_f2.c']
if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F4']):
src += ['drv_flash/drv_flash_f4.c']
if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F7']):
src += ['drv_flash/drv_flash_f7.c']
if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32L4']):
src += ['drv_flash/drv_flash_l4.c']
if GetDepend('RT_USING_HWCRYPTO'):
src += ['drv_crypto.c']
if GetDepend(['BSP_USING_WDT']):
src += ['drv_wdt.c']
if GetDepend(['BSP_USING_SDIO']):
src += ['drv_sdio.c']
if GetDepend(['BSP_USING_USBD']):
src += ['drv_usbd.c']
if GetDepend(['BSP_USING_PULSE_ENCODER']):
src += ['drv_pulse_encoder.c']
#src += ['drv_common.c']
path = [cwd]
path += [cwd + '/config']
if GetDepend('BSP_USING_ON_CHIP_FLASH'):
path += [cwd + '/drv_flash']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
Return('group')

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bsp/tm4c123bsp/libraries/Drivers/config/adc_config.h Normal file
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#ifndef _ADC_CONFIG_H_
#define _ADC_CONFIG_H_
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_ADC0
#ifndef ADC0_CONFIG
#define ADC0_CONFIG \
{ \
.name ="adc0", \
.adcbase = ADC0_BASE, \
.channel = 0 , \
.sequence = 2 , \
.trigermode = ADC_TRIGGER_PROCESSOR, \
.sequencepriority = 0 \
}
#endif /* ADC0_CONFIG */
#endif /* BSP_USING_ADC0 */
#ifdef BSP_USING_ADC1
#ifndef ADC1_CONFIG
#define ADC1_CONFIG \
{ \
.name = "adc1", \
.adcbase = ADC1_BASE, \
.channel = 0 , \
.sequence = 3 , \
.syncMode = ADC_TRIGGER_PROCESSOR, \
.sequencepriority = 0 \
}
#endif /* ADC1_CONFIG */
#endif /* BSP_USING_ADC1 */
#ifdef __cplusplus
}
#endif
#endif /*_ADC_CONFIG_H_*/

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#ifndef _PWM_CONFIG_H_
#define _PWM_CONFIG_H_
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_PWM0
#ifndef PWM0_CONFIG
#define PWM0_CONFIG \
{ \
.name = "pwm0", \
.channel = 0 , \
.counterMode = PWM_GEN_MODE_UP_DOWN , \
.syncMode = PWM_GEN_MODE_NO_SYNC \
}
#endif /* PWM0_CONFIG */
#endif /* BSP_USING_PWM0 */
#ifdef BSP_USING_PWM1
#ifndef PWM1_CONFIG
#define PWM1_CONFIG \
{ \
.name = "pwm1", \
.channel = 0 , \
.counterMode = PWM_GEN_MODE_UP_DOWN , \
.syncMode = PWM_GEN_MODE_NO_SYNC \
}
#endif /* PWM1_CONFIG */
#endif /* BSP_USING_PWM1 */
#ifdef BSP_USING_PWM2
#ifndef PWM2_CONFIG
#define PWM2_CONFIG \
{ \
.name = "pwm2", \
.channel = 0 , \
.counterMode = PWM_GEN_MODE_UP_DOWN , \
.syncMode = PWM_GEN_MODE_NO_SYNC \
}
#endif /* PWM2_CONFIG */
#endif /* BSP_USING_PWM2 */
#ifdef BSP_USING_PWM3
#ifndef PWM3_CONFIG
#define PWM3_CONFIG \
{ \
.name = "pwm3", \
.channel = 0 , \
.counterMode = PWM_GEN_MODE_UP_DOWN , \
.syncMode = PWM_GEN_MODE_NO_SYNC \
}
#endif /* PWM3_CONFIG */
#endif /* BSP_USING_PWM3 */
#ifdef BSP_USING_PWM4
#ifndef PWM4_CONFIG
#define PWM4_CONFIG \
{ \
.name = "pwm4", \
.channel = 0 , \
.counterMode = PWM_GEN_MODE_UP_DOWN , \
.syncMode = PWM_GEN_MODE_NO_SYNC \
}
#endif /* PWM4_CONFIG */
#endif /* BSP_USING_PWM4 */
#ifdef BSP_USING_PWM5
#ifndef PWM5_CONFIG
#define PWM5_CONFIG \
{ \
.name = "pwm5", \
.channel = 0 , \
.counterMode = PWM_GEN_MODE_UP_DOWN , \
.syncMode = PWM_GEN_MODE_NO_SYNC \
}
#endif /* PWM5_CONFIG */
#endif /* BSP_USING_PWM5 */
#ifdef BSP_USING_PWM6
#ifndef PWM6_CONFIG
#define PWM6_CONFIG \
{ \
.name = "pwm6", \
.channel = 0 , \
.counterMode = PWM_GEN_MODE_UP_DOWN , \
.syncMode = PWM_GEN_MODE_NO_SYNC \
}
#endif /* PWM6_CONFIG */
#endif /* BSP_USING_PWM6 */
#ifdef BSP_USING_PWM7
#ifndef PWM7_CONFIG
#define PWM7_CONFIG \
{ \
.name = "pwm7", \
.channel = 0 , \
.counterMode = PWM_GEN_MODE_UP_DOWN , \
.syncMode = PWM_GEN_MODE_NO_SYNC \
}
#endif /* PWM7_CONFIG */
#endif /* BSP_USING_PWM7 */
#ifdef __cplusplus
}
#endif
#endif /*_PWM_CONFIG_H_*/

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bsp/tm4c123bsp/libraries/Drivers/config/spi_config.h Normal file
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#ifndef __SPI_CONFIG_H__
#define __SPI_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_SPI0
#ifndef SPI0_BUS_CONFIG
#define SPI0_BUS_CONFIG \
{ \
.base = SSI0_BASE, \
.bus_name = "spi0", \
}
#endif /* SPI0_BUS_CONFIG */
#endif /* BSP_USING_SPI0 */
#ifdef BSP_USING_SPI1
#ifndef SPI1_BUS_CONFIG
#define SPI1_BUS_CONFIG \
{ \
.base = SSI1_BASE, \
.bus_name = "spi1", \
}
#endif /* SPI1_BUS_CONFIG */
#endif /* BSP_USING_SPI1 */
#ifdef BSP_USING_SPI2
#ifndef SPI2_BUS_CONFIG
#define SPI2_BUS_CONFIG \
{ \
.base = SSI2_BASE, \
.bus_name = "spi2", \
}
#endif /* SPI2_BUS_CONFIG */
#endif /* BSP_USING_SPI2 */
#ifdef BSP_USING_SPI3
#ifndef SPI3_BUS_CONFIG
#define SPI3_BUS_CONFIG \
{ \
.base = SSI3_BASE, \
.bus_name = "spi3", \
}
#endif /* SPI3_BUS_CONFIG */
#endif /* BSP_USING_SPI3 */
#ifdef __cplusplus
}
#endif
#endif /*__SPI_CONFIG_H__ */

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#ifndef __UART_CONFIG_H__
#define __UART_CONFIG_H__
#ifdef __cplusplus
extern "C" {
#endif
#if defined(BSP_USING_UART0)
#ifndef UART0_CONFIG
#define UART0_CONFIG \
{ \
.name = "uart0", \
.uartbase = UART0_BASE, \
.baudrate = 115200, \
.mode = UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | \
UART_CONFIG_PAR_NONE \
}
#endif /* UART1_CONFIG */
#endif /* BSP_USING_UART1*/
#if defined(BSP_USING_UART1)
#ifndef UART1_CONFIG
#define UART1_CONFIG \
{ \
.name = "uart1", \
.uartbase = UART1_BASE, \
.baudrate = 115200, \
.mode = UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | \
UART_CONFIG_PAR_NONE \
}
#endif /* UART1_CONFIG */
#endif /* BSP_USING_UART1*/
#if defined(BSP_USING_UART2)
#ifndef UART2_CONFIG
#define UART2_CONFIG \
{ \
.name = "uart2", \
.uartbase = UART2_BASE, \
.baudrate = 115200, \
.mode = UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | \
UART_CONFIG_PAR_NONE \
}
#endif /* UART2_CONFIG */
#endif /* BSP_USING_UART2*/
#if defined(BSP_USING_UART3)
#ifndef UART3_CONFIG
#define UART3_CONFIG \
{ \
.name = "uart3", \
.uartbase = UART3_BASE, \
.baudrate = 115200, \
.mode = UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | \
UART_CONFIG_PAR_NONE \
}
#endif /* UART3_CONFIG */
#endif /* BSP_USING_UART3*/
#ifdef __cplusplus
}
#endif
#endif

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#include "drv_adc.h"
#include <stdint.h>
#include <stdbool.h>
#include <string.h>
#include "hw_memmap.h"
#include "adc.h"
#include "sysctl.h"
#ifdef RT_USING_ADC
#include "adc_config.h"
#include "tm4c123_config.h"
#define LOG_TAG "drv.adc"
#include <drv_log.h>
static struct tm4c123_adc_config adc_config[] =
{
#ifdef BSP_USING_ADC0
ADC0_CONFIG,
#endif
#ifdef BSP_USING_ADC1
ADC1_CONFIG,
#endif
};
struct tm4c123_adc
{
struct tm4c123_adc_config *config;
struct rt_adc_device adc_device;
};
static struct tm4c123_adc adc_obj[sizeof(adc_config) / sizeof(adc_config[0])]={0};
static rt_err_t tm4c123_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled)
{
RT_ASSERT(device != RT_NULL);
//stm32_adc_handler = device->parent.user_data;
if (enabled)
{
ADCSequenceEnable(ADC0_BASE, 2);
ADCIntClear(ADC0_BASE, 2);
}
else
{
ADCSequenceDisable(ADC0_BASE, 2);
}
return RT_EOK;
}
static rt_err_t tm4c123_get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
{
RT_ASSERT(device != RT_NULL);
RT_ASSERT(value != RT_NULL);
uint32_t pui32ADC0Value[4]={0};
// Trigger the ADC conversion.
//
ADCProcessorTrigger(ADC0_BASE, 2);
//
// Wait for conversion to be completed.
//
while(!ADCIntStatus(ADC0_BASE, 2, false))
{
}
//
// Clear the ADC interrupt flag.
//
ADCIntClear(ADC0_BASE, 2);
//
// Read ADC Value.
//
ADCSequenceDataGet(ADC0_BASE, 2, pui32ADC0Value);
/* get ADC value */
*value = (rt_uint32_t)pui32ADC0Value[channel];
return RT_EOK;
}
static const struct rt_adc_ops tm4c123_adc_ops =
{
.enabled = tm4c123_adc_enabled,
.convert = tm4c123_get_adc_value,
};
static rt_err_t tm4c123_hw_adc_init(struct tm4c123_adc *device)
{
uint32_t adcbase = device->config->adcbase;
uint32_t sequencenum = device->config->sequence;
ADCSequenceConfigure(adcbase, sequencenum,
device->config->trigermode, 0);
ADCSequenceStepConfigure(ADC0_BASE, 2, 0, ADC_CTL_CH7 );
ADCSequenceStepConfigure(ADC0_BASE, 2, 1, ADC_CTL_CH6 | ADC_CTL_IE );
ADCSequenceStepConfigure(ADC0_BASE, 2, 2, ADC_CTL_CH5 );
//Tell the ADC logic
// that this is the last conversion on sequence 3 (ADC_CTL_END).
ADCSequenceStepConfigure(ADC0_BASE, 2, 3, ADC_CTL_CH4 | ADC_CTL_IE |
ADC_CTL_END);
return RT_EOK;
}
static int tm4c123_adc_init(void)
{
int i = 0;
rt_size_t obj_num = sizeof(adc_obj) / sizeof(struct tm4c123_adc);
rt_err_t result = RT_EOK;
adc_hw_config();
for (i = 0; i < obj_num; i++)
{
/* ADC init */
adc_obj[i].config = &adc_config[i];
if(tm4c123_hw_adc_init(&adc_obj[i])!= RT_EOK)
{
LOG_E("%s init failed", adc_obj[i].config->name);
result = -RT_ERROR;
return result;
}
else
{
LOG_D("%s init success", adc_obj[i].config->name);
/* register adc device */
if (rt_hw_adc_register(&adc_obj[i].adc_device, adc_obj[i].config->name, &tm4c123_adc_ops,RT_NULL) == RT_EOK)
{
LOG_D("%s register success", adc_obj[i].config->name);
}
else
{
LOG_E("%s register failed", adc_obj[i].config->name);
result = -RT_ERROR;
}
}
}
return result;
}
INIT_APP_EXPORT(tm4c123_adc_init);
#endif /*RT_UING_ADC*/

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#ifndef _DRV_ADC_H_
#define _DRV_ADC_H_
#include<stdint.h>
#include<rtthread.h>
#include<rtdevice.h>
#include<rthw.h>
struct tm4c123_adc_config
{
const char *name;
uint32_t adcbase;
uint32_t channel;
uint32_t sequence;
uint32_t trigermode;
uint32_t sequencepriority;
};
#endif /*_DRV_ADC_H_*/

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bsp/tm4c123bsp/libraries/Drivers/drv_flash/drv_flash.h Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-5 SummerGift first version
*/
#ifndef __DRV_FLASH_H__
#define __DRV_FLASH_H__
#include <rtthread.h>
#include "rtdevice.h"
#include <rthw.h>
#include <drv_common.h>
#ifdef __cplusplus
extern "C" {
#endif
int stm32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size);
int stm32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size);
int stm32_flash_erase(rt_uint32_t addr, size_t size);
#ifdef __cplusplus
}
#endif
#endif /* __DRV_FLASH_H__ */

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bsp/tm4c123bsp/libraries/Drivers/drv_flash/drv_flash_f1.c Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-5 SummerGift first version
*/
#include "board.h"
#ifdef BSP_USING_ON_CHIP_FLASH
#include "drv_config.h"
#include "drv_flash.h"
#if defined(PKG_USING_FAL)
#include "fal.h"
#endif
//#define DRV_DEBUG
#define LOG_TAG "drv.flash"
#include <drv_log.h>
/**
* @brief Gets the page of a given address
* @param Addr: Address of the FLASH Memory
* @retval The page of a given address
*/
static uint32_t GetPage(uint32_t addr)
{
uint32_t page = 0;
page = RT_ALIGN_DOWN(addr, FLASH_PAGE_SIZE);
return page;
}
/**
* Read data from flash.
* @note This operation's units is word.
*
* @param addr flash address
* @param buf buffer to store read data
* @param size read bytes size
*
* @return result
*/
int stm32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size)
{
size_t i;
if ((addr + size) > STM32_FLASH_END_ADDRESS)
{
LOG_E("read outrange flash size! addr is (0x%p)", (void *)(addr + size));
return -RT_EINVAL;
}
for (i = 0; i < size; i++, buf++, addr++)
{
*buf = *(rt_uint8_t *) addr;
}
return size;
}
/**
* Write data to flash.
* @note This operation's units is word.
* @note This operation must after erase. @see flash_erase.
*
* @param addr flash address
* @param buf the write data buffer
* @param size write bytes size
*
* @return result
*/
int stm32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
{
rt_err_t result = RT_EOK;
rt_uint32_t end_addr = addr + size;
if (addr % 4 != 0)
{
LOG_E("write addr must be 4-byte alignment");
return -RT_EINVAL;
}
if ((end_addr) > STM32_FLASH_END_ADDRESS)
{
LOG_E("write outrange flash size! addr is (0x%p)", (void *)(addr + size));
return -RT_EINVAL;
}
HAL_FLASH_Unlock();
while (addr < end_addr)
{
if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, addr, *((rt_uint32_t *)buf)) == HAL_OK)
{
if (*(rt_uint32_t *)addr != *(rt_uint32_t *)buf)
{
result = -RT_ERROR;
break;
}
addr += 4;
buf += 4;
}
else
{
result = -RT_ERROR;
break;
}
}
HAL_FLASH_Lock();
if (result != RT_EOK)
{
return result;
}
return size;
}
/**
* Erase data on flash.
* @note This operation is irreversible.
* @note This operation's units is different which on many chips.
*
* @param addr flash address
* @param size erase bytes size
*
* @return result
*/
int stm32_flash_erase(rt_uint32_t addr, size_t size)
{
rt_err_t result = RT_EOK;
uint32_t PAGEError = 0;
/*Variable used for Erase procedure*/
FLASH_EraseInitTypeDef EraseInitStruct;
if ((addr + size) > STM32_FLASH_END_ADDRESS)
{
LOG_E("ERROR: erase outrange flash size! addr is (0x%p)\n", (void *)(addr + size));
return -RT_EINVAL;
}
HAL_FLASH_Unlock();
/* Fill EraseInit structure*/
EraseInitStruct.TypeErase = FLASH_TYPEERASE_PAGES;
EraseInitStruct.PageAddress = GetPage(addr);
EraseInitStruct.NbPages = (size + FLASH_PAGE_SIZE - 1) / FLASH_PAGE_SIZE;
if (HAL_FLASHEx_Erase(&EraseInitStruct, &PAGEError) != HAL_OK)
{
result = -RT_ERROR;
goto __exit;
}
__exit:
HAL_FLASH_Lock();
if (result != RT_EOK)
{
return result;
}
LOG_D("erase done: addr (0x%p), size %d", (void *)addr, size);
return size;
}
#if defined(PKG_USING_FAL)
static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size);
static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size);
static int fal_flash_erase(long offset, size_t size);
const struct fal_flash_dev stm32_onchip_flash = { "onchip_flash", STM32_FLASH_START_ADRESS, STM32_FLASH_SIZE, FLASH_PAGE_SIZE, {NULL, fal_flash_read, fal_flash_write, fal_flash_erase} };
static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size)
{
return stm32_flash_read(stm32_onchip_flash.addr + offset, buf, size);
}
static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size)
{
return stm32_flash_write(stm32_onchip_flash.addr + offset, buf, size);
}
static int fal_flash_erase(long offset, size_t size)
{
return stm32_flash_erase(stm32_onchip_flash.addr + offset, size);
}
#endif
#endif /* BSP_USING_ON_CHIP_FLASH */

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#include <rthw.h>
#include <rtthread.h>
#include <rtdevice.h>
#include <stdint.h>
#include <stdbool.h>
#include "hw_memmap.h"
#include "sysctl.h"
#include "gpio.h"
#include "pin_map.h"
#include "interrupt.h"
#include "rom_map.h"
#include "drv_gpio.h"
#ifdef RT_USING_PIN
static const struct pin_index pins[] =
{
_TM4C_PIN(0 ,F, 0 ),
_TM4C_PIN(1 ,F, 1 ),
_TM4C_PIN(2 ,F, 2 ),
_TM4C_PIN(3 ,F, 3 ),
_TM4C_PIN(4 ,F, 4 )
};
static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
{
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL}
};
static uint32_t pin_irq_enable_mask=0;
#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
static const struct pin_index *get_pin(uint8_t pin)
{
const struct pin_index *index;
if (pin < ITEM_NUM(pins))
{
index = &pins[pin];
if (index->index == -1)
index = RT_NULL;
}
else
{
index = RT_NULL;
}
return index;
};
static void tm4c123_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
{
const struct pin_index *index;
index = get_pin(pin);
if (index == RT_NULL)
{
return;
}
if(mode == PIN_MODE_INPUT)
{
GPIOPinTypeGPIOInput(index ->gpioBaseAddress, index->pin);
}
else if(mode == PIN_MODE_OUTPUT)
{
GPIOPinTypeGPIOOutput(index->gpioBaseAddress, index->pin);
}
else if(mode == PIN_MODE_INPUT_PULLUP)
{
//
// Make the pin(s) be inputs.
//
GPIODirModeSet(index->gpioBaseAddress, index->pin, GPIO_DIR_MODE_IN);
//
// Set the pad(s) for standard pullup operation.
//
GPIOPadConfigSet(index->gpioBaseAddress, index->pin, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU);
}
else if(mode == PIN_MODE_INPUT_PULLDOWN)
{
//
// Make the pin(s) be inputs.
//
GPIODirModeSet(index->gpioBaseAddress, index->pin, GPIO_DIR_MODE_IN);
//
// Set the pad(s) for standard pulldown operation.
//
GPIOPadConfigSet(index->gpioBaseAddress, index->pin, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPD);
}
else if(mode == PIN_MODE_OUTPUT_OD)
{
//
// Set the pad(s) for standard push-pull operation.
GPIOPadConfigSet(index->gpioBaseAddress, index->pin, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD);
//
// Make the pin(s) be outputs.
GPIODirModeSet(index->gpioBaseAddress, index->pin, GPIO_DIR_MODE_OUT);
}
}
static void tm4c123_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t ui8Val)
{
const struct pin_index *index;
index = get_pin(pin);
if( index == RT_NULL)
{
return;
}
if(ui8Val)
{
GPIOPinWrite(index ->gpioBaseAddress, index->pin, index->pin );
}
else
{
GPIOPinWrite(index ->gpioBaseAddress, index->pin, 0 );
}
}
static int tm4c123_pin_read(rt_device_t dev, rt_base_t pin)
{
const struct pin_index *index;
int value = 0;
index = get_pin(pin);
if( index == RT_NULL)
{
return value;
}
value = GPIOPinRead(index ->gpioBaseAddress , index ->pin );
return value;
}
static rt_err_t tm4c123_pin_attach_irq(rt_device_t device, rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args), void *args )
{
//const struct pin_index *index;
return RT_EOK;
}
static rt_err_t tm4c123_pin_dettach_irq(rt_device_t device, rt_int32_t pin)
{
//const struct pin_index *index;
return RT_EOK;
}
static rt_err_t tm4c123_pin_irq_enable(rt_device_t device, rt_base_t pin,
rt_uint32_t enabled)
{
//const struct pin_index *index;
//const struct pin_irq_map *irqmap;
return RT_EOK;
}
const static struct rt_pin_ops _tm4c123_pin_ops =
{
tm4c123_pin_mode,
tm4c123_pin_write,
tm4c123_pin_read,
tm4c123_pin_attach_irq,
tm4c123_pin_dettach_irq,
tm4c123_pin_irq_enable,
};
int rt_hw_pin_init(void)
{
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
return rt_device_pin_register("pin", &_tm4c123_pin_ops, RT_NULL);
}
INIT_BOARD_EXPORT(rt_hw_pin_init);
#endif /*RT_USING_PIN*/

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#ifndef _DRV_GPIO_H_
#define _DRV_GPIO_H_
#include <stdint.h>
#include <rtthread.h>
#define _TM4C_PIN(index, gpioport, gpio_index) \
{ \
index, GPIO_PORT##gpioport##_BASE, GPIO_PIN_##gpio_index \
}
#define _TM4C_PIN_RESERVE \
{ \
-1, 0, 0 \
}
/* TM4C123 GPIO driver*/
struct pin_index
{
int index;
uint32_t gpioBaseAddress;
uint32_t pin;
};
extern int rt_hw_pin_init(void);
#endif /*_DRV_GPIO_H_*/

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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-11-15 SummerGift first version
*/
/*
* NOTE: DO NOT include this file on the header file.
*/
#ifndef LOG_TAG
#define DBG_TAG "drv"
#else
#define DBG_TAG LOG_TAG
#endif /* LOG_TAG */
#ifdef DRV_DEBUG
#define DBG_LVL DBG_LOG
#else
#define DBG_LVL DBG_INFO
#endif /* DRV_DEBUG */
#include <rtdbg.h>

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#include "drv_pwm.h"
#include <stdint.h>
#include <stdbool.h>
#include <string.h>
#include "hw_memmap.h"
#include "pwm.h"
#include "sysctl.h"
#ifdef RT_USING_PWM
#include "pwm_config.h"
#include "tm4c123_config.h"
#define LOG_TAG "drv.pwm"
#include <drv_log.h>
enum
{
#ifdef BSP_USING_PWM0
PWM0_INDEX,
#endif
#ifdef BSP_USING_PWM1
PWM1_INDEX,
#endif
#ifdef BSP_USING_PWM2
PWM2_INDEX,
#endif
#ifdef BSP_USING_PWM3
PWM3_INDEX,
#endif
#ifdef BSP_USING_PWM4
PWM4_INDEX,
#endif
#ifdef BSP_USING_PWM5
PWM5_INDEX,
#endif
#ifdef BSP_USING_PWM6
PWM6_INDEX,
#endif
#ifdef BSP_USING_PWM7
PWM7_INDEX,
#endif
};
static struct tm4c123_pwm_config pwm_config[] =
{
#ifdef BSP_USING_PWM0
PWM0_CONFIG,
#endif
#ifdef BSP_USING_PWM1
PWM1_CONFIG,
#endif
#ifdef BSP_USING_PWM2
PWM2_CONFIG,
#endif
#ifdef BSP_USING_PWM3
PWM3_CONFIG,
#endif
#ifdef BSP_USING_PWM4
PWM4_CONFIG,
#endif
#ifdef BSP_USING_PWM5
PWM5_CONFIG,
#endif
#ifdef BSP_USING_PWM6
PWM6_CONFIG,
#endif
#ifdef BSP_USING_PWM7
PWM7_CONFIG,
#endif
};
static struct tm4c123_pwm pwm_obj[sizeof(pwm_config) / sizeof(pwm_config[0])] = {0};
static rt_err_t tm4c123_pwm_control(struct rt_device_pwm *device, int cmd, void *arg);
static struct rt_pwm_ops drv_ops =
{
tm4c123_pwm_control
};
static rt_err_t drv_pwm_enable(char* name, struct rt_pwm_configuration *configuration, rt_bool_t enable)
{
/* Converts the channel number to the channel number of Hal library */
int num = name[3]-0x30;
if (!enable)
{
if( num<=3 )
{
PWMOutputState(PWM0_BASE, PWM_OUT_0_BIT<<(num*2+(configuration->channel-1)), false);
}
else
{
PWMOutputState(PWM1_BASE, PWM_OUT_0_BIT<<((num%4)*2+(configuration->channel-1)), false);
}
}
else
{
if( num<=3 )
{
PWMOutputState(PWM0_BASE, PWM_OUT_0_BIT<<(num*2+(configuration->channel-1)), true);
}
else
{
PWMOutputState(PWM1_BASE, PWM_OUT_0_BIT<<((num%4)*2+(configuration->channel-1)), true);
}
}
return RT_EOK;
}
static rt_err_t drv_pwm_get(char* name, struct rt_pwm_configuration *configuration)
{
switch(name[3])
{
case '0':
configuration->period = PWMGenPeriodGet(PWM0_BASE, PWM_GEN_0);
configuration->pulse= PWMPulseWidthGet(PWM0_BASE, PWM_OUT_0+(uint32_t)(configuration->channel-1));
break;
case '1':
configuration->period = PWMGenPeriodGet(PWM0_BASE, PWM_GEN_1);
configuration->pulse= PWMPulseWidthGet(PWM0_BASE, PWM_OUT_2+(uint32_t)(configuration->channel-1));
break;
case '2':
configuration->period = PWMGenPeriodGet(PWM0_BASE, PWM_GEN_2);
configuration->pulse= PWMPulseWidthGet(PWM0_BASE, PWM_OUT_4+(uint32_t)(configuration->channel-1));
break;
case '3':
configuration->period = PWMGenPeriodGet(PWM0_BASE, PWM_GEN_3);
configuration->pulse= PWMPulseWidthGet(PWM0_BASE, PWM_OUT_6+(uint32_t)(configuration->channel-1));
break;
case '4':
configuration->period = PWMGenPeriodGet(PWM1_BASE, PWM_GEN_0);
configuration->pulse= PWMPulseWidthGet(PWM1_BASE, PWM_OUT_0+(uint32_t)(configuration->channel-1));
break;
case '5':
configuration->period = PWMGenPeriodGet(PWM1_BASE, PWM_GEN_1);
configuration->pulse= PWMPulseWidthGet(PWM1_BASE, PWM_OUT_2+(uint32_t)(configuration->channel-1));
break;
case '6':
configuration->period = PWMGenPeriodGet(PWM1_BASE, PWM_GEN_2);
configuration->pulse= PWMPulseWidthGet(PWM1_BASE, PWM_OUT_4+(uint32_t)(configuration->channel-1));
break;
case '7':
configuration->period = PWMGenPeriodGet(PWM1_BASE, PWM_GEN_3);
configuration->pulse= PWMPulseWidthGet(PWM1_BASE, PWM_OUT_6+(uint32_t)(configuration->channel-1));
break;
default:
break;
}
return RT_EOK;
}
static rt_err_t drv_pwm_set(char *name, struct rt_pwm_configuration *configuration)
{
uint32_t sysPwmClock = SysCtlPWMClockGet();
switch(name[3])
{
case '0':
PWMGenPeriodSet(PWM0_BASE, PWM_GEN_0, configuration->period/1000*(sysPwmClock/1000000)); // t(s)/(1/f) = ticks ns/1000/1000000
PWMPulseWidthSet(PWM0_BASE, PWM_OUT_0+(uint32_t)(configuration->channel-1),configuration->pulse/1000*(sysPwmClock/1000000));
PWMGenEnable(PWM0_BASE, PWM_GEN_0);
break;
case '1':
PWMGenPeriodSet(PWM0_BASE, PWM_GEN_1, configuration->period/1000*(sysPwmClock/1000000));
PWMPulseWidthSet(PWM0_BASE, PWM_OUT_0+(uint32_t)(configuration->channel-1),configuration->pulse/1000*(sysPwmClock/1000000));
PWMGenEnable(PWM0_BASE, PWM_GEN_1);
break;
case '2':
PWMGenPeriodSet(PWM0_BASE, PWM_GEN_2, configuration->period/1000*(sysPwmClock/1000000));
PWMPulseWidthSet(PWM0_BASE, PWM_OUT_0+(uint32_t)(configuration->channel-1),configuration->pulse/1000*(sysPwmClock/1000000));
PWMGenEnable(PWM0_BASE, PWM_GEN_2);
break;
case '3':
PWMGenPeriodSet(PWM0_BASE, PWM_GEN_3, configuration->period/1000*(sysPwmClock/1000000));
PWMPulseWidthSet(PWM0_BASE, PWM_OUT_0+(uint32_t)(configuration->channel-1),configuration->pulse/1000*(sysPwmClock/1000000));
PWMGenEnable(PWM0_BASE, PWM_GEN_3);
break;
case '4':
PWMGenPeriodSet(PWM1_BASE, PWM_GEN_0, configuration->period/1000*(sysPwmClock/1000000));
PWMPulseWidthSet(PWM1_BASE, PWM_OUT_0+(uint32_t)(configuration->channel-1),configuration->pulse/1000*(sysPwmClock/1000000));
PWMGenEnable(PWM1_BASE, PWM_GEN_0);
break;
case '5':
PWMGenPeriodSet(PWM1_BASE, PWM_GEN_1, configuration->period/1000*(sysPwmClock/1000000));
PWMPulseWidthSet(PWM1_BASE, PWM_OUT_2+(uint32_t)(configuration->channel-1),configuration->pulse/1000*(sysPwmClock/1000000));
PWMGenEnable(PWM1_BASE, PWM_GEN_1);
break;
case '6':
PWMGenPeriodSet(PWM1_BASE, PWM_GEN_2, configuration->period/1000*(sysPwmClock/1000000));
PWMPulseWidthSet(PWM1_BASE, PWM_OUT_4+(uint32_t)(configuration->channel-1),configuration->pulse/1000*(sysPwmClock/1000000));
PWMGenEnable(PWM1_BASE, PWM_GEN_2);
break;
case '7':
PWMGenPeriodSet(PWM1_BASE, PWM_GEN_3, configuration->period/1000*(sysPwmClock/1000000));
PWMPulseWidthSet(PWM1_BASE, PWM_OUT_6+(uint32_t)(configuration->channel-1),configuration->pulse/1000*(sysPwmClock/1000000));
PWMGenEnable(PWM1_BASE, PWM_GEN_3);
break;
default:
break;
}
return RT_EOK;
}
static rt_err_t tm4c123_pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
{
struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
switch (cmd)
{
case PWM_CMD_ENABLE:
return drv_pwm_enable(device->parent.parent.name, configuration, RT_TRUE);
case PWM_CMD_DISABLE:
return drv_pwm_enable(device->parent.parent.name, configuration, RT_FALSE);
case PWM_CMD_SET:
return drv_pwm_set(device->parent.parent.name, configuration);
case PWM_CMD_GET:
return drv_pwm_get(device->parent.parent.name, configuration);
default:
return RT_EINVAL;
}
}
static rt_err_t tm4c123_hw_pwm_init(struct tm4c123_pwm *device)
{
rt_err_t result = RT_EOK;
RT_ASSERT(device != RT_NULL);
pwm_hw_config();
switch( device->config->name[3])
{
case '0':
PWMGenConfigure(PWM0_BASE, PWM_GEN_0, device->config->counterMode |
device->config->syncMode);
break;
case '1':
PWMGenConfigure(PWM0_BASE, PWM_GEN_1, device->config->counterMode |
device->config->syncMode);
break;
case '2':
PWMGenConfigure(PWM0_BASE, PWM_GEN_2, device->config->counterMode |
device->config->syncMode);
break;
case '3':
PWMGenConfigure(PWM0_BASE, PWM_GEN_3, device->config->counterMode |
device->config->syncMode);
break;
case '4':
PWMGenConfigure(PWM1_BASE, PWM_GEN_0, device->config->counterMode |
device->config->syncMode);
break;
case '5':
PWMGenConfigure(PWM1_BASE, PWM_GEN_1, device->config->counterMode |
device->config->syncMode);
break;
case '6':
PWMGenConfigure(PWM1_BASE, PWM_GEN_2, device->config->counterMode |
device->config->syncMode);
break;
case '7':
PWMGenConfigure(PWM1_BASE, PWM_GEN_3, device->config->counterMode |
device->config->syncMode);
break;
default:
LOG_E("%s PWMGenConfigure failed", device->config->name);
result = -RT_ERROR;
return result;
}
return result;
}
int rt_hw_pwm_init(void)
{
int i = 0;
rt_size_t obj_num = sizeof(pwm_obj) / sizeof(struct tm4c123_pwm);
rt_err_t result = RT_EOK;
for(i=0 ; i< obj_num;i++)
{
pwm_obj[i].config = &pwm_config[i];
pwm_obj[i].pwm_device.ops = &drv_ops;
/*pwm_init*/
if(tm4c123_hw_pwm_init(&pwm_obj[i])!= RT_EOK)
{
LOG_E("%s init failed", pwm_obj[i].config->name);
result = -RT_ERROR;
return result;
}
else
{
LOG_D("%s init success", pwm_obj[i].config->name);
/* register pwm device */
if (rt_device_pwm_register(&pwm_obj[i].pwm_device, pwm_obj[i].config->name, &drv_ops,RT_NULL) == RT_EOK)
{
LOG_D("%s register success", pwm_obj[i].config->name);
}
else
{
LOG_E("%s register failed", pwm_obj[i].config->name);
result = -RT_ERROR;
}
}
}
return result;
}
#endif

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#ifndef _DRV_PWM_H_
#define _DRV_PWM_H_
#include<rtdevice.h>
#include<rthw.h>
struct tm4c123_pwm
{
struct tm4c123_pwm_config *config;
struct rt_device_pwm pwm_device;
};
/* tm4c123 config class */
struct tm4c123_pwm_config
{
rt_uint8_t channel;
char *name;
uint32_t counterMode;
uint32_t syncMode;
};
int rt_hw_pwm_init(void);
#endif /*_DRV_PWM_H_*/

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#include "drv_spi.h"
#include <stdint.h>
#include <stdbool.h>
#include <string.h>
#include "hw_memmap.h"
#include "ssi.h"
#include "gpio.h"
#include "sysctl.h"
#ifdef RT_USING_SPI
#if defined(BSP_USING_SPI0) || defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2) || defined(BSP_USING_SPI3)
/* this driver can be disabled at menuconfig → RT-Thread Components → Device Drivers */
#include "tm4c123_config.h"
#include "spi_config.h"
#include <string.h>
//#define DRV_DEBUG
#define LOG_TAG "drv.spi"
#include <drv_log.h>
enum
{
#ifdef BSP_USING_SPI0
SPI0_INDEX,
#endif
#ifdef BSP_USING_SPI1
SPI1_INDEX,
#endif
#ifdef BSP_USING_SPI2
SPI2_INDEX,
#endif
#ifdef BSP_USING_SPI3
SPI3_INDEX,
#endif
};
static struct tm4c123_spi_config spi_config[] =
{
#ifdef BSP_USING_SPI0
SPI0_BUS_CONFIG,
#endif
#ifdef BSP_USING_SPI1
SPI1_BUS_CONFIG,
#endif
#ifdef BSP_USING_SPI2
SPI2_BUS_CONFIG,
#endif
#ifdef BSP_USING_SPI3
SPI3_BUS_CONFIG,
#endif
};
static struct tm4c123_spi spi_bus_obj[sizeof(spi_config) / sizeof(spi_config[0])] = {0};
static rt_err_t tm4c123_spi_configure(struct tm4c123_spi *spi_drv, struct rt_spi_configuration *cfg)
{
RT_ASSERT(spi_drv != RT_NULL);
RT_ASSERT(cfg != RT_NULL);
uint32_t ui32Protocol,ui32Mode;
uint32_t ui32BitRate = (uint32_t)cfg->max_hz;
uint32_t ui32DataWidth = (uint32_t)cfg->data_width;
uint32_t pui32DataRx[1];
rt_uint8_t ui8Protocol = 0;
if (cfg->mode & RT_SPI_SLAVE)
{
ui32Mode = SSI_MODE_SLAVE;
}
else
{
ui32Mode = SSI_MODE_MASTER;
}
if (cfg->mode & RT_SPI_CPHA)
{
ui8Protocol += 1;
}
else
{
ui8Protocol += 0;
}
if (cfg->mode & RT_SPI_CPOL)
{
ui8Protocol += 2;
}
else
{
ui8Protocol += 0;
}
switch( ui8Protocol)
{
case 0:
ui32Protocol = SSI_FRF_MOTO_MODE_0;
break;
case 1:
ui32Protocol = SSI_FRF_MOTO_MODE_1;
break;
case 2:
ui32Protocol = SSI_FRF_MOTO_MODE_2;
break;
case 3:
ui32Protocol = SSI_FRF_MOTO_MODE_3;
break;
default:
ui32Protocol = SSI_FRF_MOTO_MODE_0;
break;
}
SSIConfigSetExpClk(spi_drv->config->base, SysCtlClockGet(), ui32Protocol,
ui32Mode, ui32BitRate, ui32DataWidth);
LOG_D("ssiclk freq: %d, SPI limiting freq: %d",SysCtlClockGet(),cfg->max_hz);
/* DMA configuration */
SSIEnable(spi_drv->config->base);
while(SSIDataGetNonBlocking(SSI0_BASE, &pui32DataRx[0]))
{
}
LOG_D("%s init done", spi_drv->config->bus_name);
return RT_EOK;
}
static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
{
rt_size_t message_length;
rt_uint8_t *recv_buf;
const rt_uint8_t *send_buf;
uint32_t ReadData=0;
int i = 0;
RT_ASSERT(device != RT_NULL);
RT_ASSERT(device->bus != RT_NULL);
RT_ASSERT(device->bus->parent.user_data != RT_NULL);
RT_ASSERT(message != RT_NULL);
struct tm4c123_spi *spi_drv = rt_container_of(device->bus, struct tm4c123_spi, spi_bus);
struct tm4c123_hw_spi_cs *cs = device->parent.user_data;
if (message->cs_take)
{
GPIOPinWrite(cs->portbase, cs->GPIO_Pin, 0);
}
LOG_D("%s transfer prepare and start", spi_drv->config->bus_name);
LOG_D("%s sendbuf: %X, recvbuf: %X, length: %d",
spi_drv->config->bus_name,
(uint32_t)message->send_buf,
(uint32_t)message->recv_buf, message->length);
message_length = message->length;
recv_buf = message->recv_buf;
send_buf = message->send_buf;
if (message->send_buf && message->recv_buf)
{
for(i=0; i< message_length; i++)
{
SSIDataPut(spi_drv->config->base, (uint32_t)send_buf[i]);
while(SSIBusy(spi_drv->config->base))
{
}
SSIDataGet(spi_drv->config->base, &ReadData);
recv_buf[i] = (unsigned char)ReadData;
}
}
else if (message->send_buf)
{
for(i=0; i< message_length; i++)
{
SSIDataPut(spi_drv->config->base, (uint32_t)send_buf[i]);
while(SSIBusy(spi_drv->config->base))
{
}
SSIDataGet(spi_drv->config->base, &ReadData);
}
}
else
{
for(i=0; i< message_length; i++)
{
SSIDataPut(spi_drv->config->base, (uint32_t)0xff);
while(SSIBusy(spi_drv->config->base))
{
}
SSIDataGet(spi_drv->config->base, &ReadData);
recv_buf[i] = (unsigned char)ReadData;
}
}
LOG_D("%s transfer done", spi_drv->config->bus_name);
if (message->cs_release)
{
GPIOPinWrite(cs->portbase, cs->GPIO_Pin, cs->GPIO_Pin);
}
return message->length;
}
static rt_err_t spi_configure(struct rt_spi_device *device,
struct rt_spi_configuration *configuration)
{
RT_ASSERT(device != RT_NULL);
RT_ASSERT(configuration != RT_NULL);
struct tm4c123_spi *spi_drv = rt_container_of(device->bus, struct tm4c123_spi, spi_bus);
spi_drv->cfg = configuration;
return tm4c123_spi_configure(spi_drv, configuration);
}
static const struct rt_spi_ops tm4c123_spi_ops =
{
.configure = spi_configure,
.xfer = spixfer,
};
static int rt_hw_spi_bus_init(void)
{
rt_err_t result;
for (int i = 0; i < sizeof(spi_config) / sizeof(spi_config[0]); i++)
{
spi_bus_obj[i].config = &spi_config[i];
spi_bus_obj[i].spi_bus.parent.user_data = &spi_config[i];
result = rt_spi_bus_register(&spi_bus_obj[i].spi_bus, spi_config[i].bus_name, &tm4c123_spi_ops);
RT_ASSERT(result == RT_EOK);
LOG_D("%s bus init done", spi_config[i].bus_name);
}
return result;
}
/**
* Attach the spi device to SPI bus, this function must be used after initialization.
*/
rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, uint32_t portindex ,uint32_t cs_gpiobase, uint32_t cs_gpio_pin)
{
RT_ASSERT(bus_name != RT_NULL);
RT_ASSERT(device_name != RT_NULL);
rt_err_t result;
struct rt_spi_device *spi_device;
struct tm4c123_hw_spi_cs *cs_pin;
/* initialize the cs pin && select the slave*/
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA+portindex);
GPIOPinTypeGPIOOutput(cs_gpiobase, cs_gpio_pin);
GPIOPinWrite(cs_gpiobase, cs_gpio_pin, cs_gpio_pin);
/* attach the device to spi bus*/
spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
RT_ASSERT(spi_device != RT_NULL);
cs_pin = (struct tm4c123_hw_spi_cs *)rt_malloc(sizeof(struct tm4c123_hw_spi_cs));
RT_ASSERT(cs_pin != RT_NULL);
cs_pin->portbase = cs_gpiobase;
cs_pin->GPIO_Pin = cs_gpio_pin;
result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin);
if (result != RT_EOK)
{
LOG_E("%s attach to %s faild, %d\n", device_name, bus_name, result);
}
RT_ASSERT(result == RT_EOK);
LOG_D("%s attach to %s done", device_name, bus_name);
return result;
}
int rt_hw_spi_init(void)
{
spi_hw_config();
return rt_hw_spi_bus_init();
}
INIT_BOARD_EXPORT(rt_hw_spi_init);
#endif /* defined(BSP_USING_SPI0) || defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2) || defined(BSP_USING_SPI3) */
#endif /*RT_USING_SPI*/

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#ifndef __DRV_SPI_H_
#define __DRV_SPI_H_
#include <rtdevice.h>
#include <rthw.h>
#include "drivers/spi.h"
rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, uint32_t portindex, uint32_t cs_gpiobase, uint32_t cs_gpio_pin);
struct tm4c123_hw_spi_cs
{
uint32_t portbase;
uint32_t GPIO_Pin;
};
struct tm4c123_spi_config
{
uint32_t base;
char * bus_name;
};
/* tm4c123 spi dirver class */
struct tm4c123_spi
{
struct tm4c123_spi_config *config;
struct rt_spi_configuration *cfg;
struct rt_spi_bus spi_bus;
};
struct tm4c123_spi_device
{
rt_uint32_t pin;
char *bus_name;
char *device_name;
};
#define SPI_USING_RX_DMA_FLAG (1<<0)
#define SPI_USING_TX_DMA_FLAG (1<<1)
#endif /*__DRV_SPI_H_ */

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#include <stdint.h>
#include <stdbool.h>
#include "hw_memmap.h"
#include "hw_ints.h"
#include "sysctl.h"
#include "gpio.h"
#include "pin_map.h"
#include "interrupt.h"
#include "rom_map.h"
#include "uart.h"
#include "drv_uart.h"
#include "uart_config.h"
#include "tm4c123_config.h"
#ifdef RT_USING_SERIAL
#define LOG_TAG "drv.uart"
#include <drv_log.h>
#if !defined(BSP_USING_UART0)&&!defined(BSP_USING_UART1)&&!defined(BSP_USING_UART2)&&!defined(BSP_USING_UART3)
#error "Please define at least one BSP_USING_UARTx"
#endif
enum {
#ifdef BSP_USING_UART0
UART0_INDEX,
#endif
#ifdef BSP_USING_UART1
UART1_INDEX,
#endif
#ifdef BSP_USING_UART2
UART2_INDEX,
#endif
#ifdef BSP_USING_UART3
UART3_INDEX,
#endif
};
uint32_t uart_intbase[]=
{
#ifdef BSP_USING_UART0
INT_UART0,
#endif
#ifdef BSP_USING_UART1
INT_UART1,
#endif
#ifdef BSP_USING_UART2
INT_UART2,
#endif
#ifdef BSP_USING_UART3
INT_UART3
#endif
};
static struct tm4c123_uart_config uart_config[] =
{
#ifdef BSP_USING_UART0
UART0_CONFIG,
#endif
#ifdef BSP_USING_UART1
UART1_CONFIG,
#endif
#ifdef BSP_USING_UART2
UART2_CONFIG,
#endif
#ifdef BSP_USING_UART3
UART3_CONFIG,
#endif
};
static struct tm4c123_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0};
//struct serial_configure
//{
// rt_uint32_t baud_rate; /* ??? */
// rt_uint32_t data_bits :4; /* ??? */
// rt_uint32_t stop_bits :2; /* ??? */
// rt_uint32_t parity :2; /* ????? */
// rt_uint32_t bit_order :1; /* ?????????? */
// rt_uint32_t invert :1; /* ?? */
// rt_uint32_t bufsz :16; /* ????????? */
// rt_uint32_t reserved :4; /* ??? */
//};
//rtservice.h
//#define rt_container_of(ptr, type, member) ((type *)((char *)(ptr) - (unsigned long)(&((type *)0)->member)))
static rt_err_t tm4c123_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
{
struct tm4c123_uart *uart;
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(cfg != RT_NULL);
uart = rt_container_of(serial, struct tm4c123_uart, serial);
UARTFIFOLevelSet(uart->config->uartbase, UART_FIFO_TX1_8, UART_FIFO_RX1_8);
UARTConfigSetExpClk(uart->config->uartbase, SysCtlClockGet(), uart->config->baudrate,
uart->config->mode);
return RT_EOK;
}
static rt_err_t tm4c123_control(struct rt_serial_device *serial, int cmd, void *arg)
{
struct tm4c123_uart *uart;
#ifdef RT_SERIAL_USING_DMA
rt_ubase_t ctrl_arg = (rt_ubase_t)arg;
#endif
RT_ASSERT(serial != RT_NULL);
uart = rt_container_of(serial, struct tm4c123_uart, serial);
switch (cmd)
{
/* disable interrupt */
case RT_DEVICE_CTRL_CLR_INT:
/* disable rx irq */
IntDisable(uart->uartintbase);
/* disable interrupt */
//UARTIntDisable(UART0_BASE, UART_INT_RX | UART_INT_RT);
UARTIntDisable(uart->config->uartbase, UART_INT_RX);
break;
/* enable interrupt */
case RT_DEVICE_CTRL_SET_INT:
/* enable rx irq */
IntEnable(uart->uartintbase);
//UARTIntEnable(UART0_BASE, UART_INT_RX | UART_INT_RT);
UARTIntEnable(uart->config->uartbase, UART_INT_RX);
break;
#ifdef RT_SERIAL_USING_DMA
case RT_DEVICE_CTRL_CONFIG:
break;
#endif
}
return RT_EOK;
}
static int tm4c123_putc(struct rt_serial_device *serial, char c)
{
struct tm4c123_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = rt_container_of(serial, struct tm4c123_uart, serial);
UARTCharPut(uart->config->uartbase, c);
return 1;
}
static int tm4c123_getc(struct rt_serial_device *serial)
{
int ch;
struct tm4c123_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = rt_container_of(serial, struct tm4c123_uart, serial);
ch = -1;
ch = UARTCharGetNonBlocking(uart->config->uartbase);
return ch;
}
static rt_size_t tm4c123_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction)
{
struct tm4c123_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = rt_container_of(serial, struct tm4c123_uart, serial);
if (size == 0)
{
return 0;
}
// if (RT_SERIAL_DMA_TX == direction)
// {
// if (HAL_UART_Transmit_DMA(&uart->handle, buf, size) == HAL_OK)
// {
// return size;
// }
// else
// {
// return 0;
// }
// }
return 0;
}
static const struct rt_uart_ops tm4c123_uart_ops =
{
.configure = tm4c123_configure,
.control = tm4c123_control,
.putc = tm4c123_putc,
.getc = tm4c123_getc,
.dma_transmit = tm4c123_dma_transmit
};
/**
* Uart common interrupt process. This need add to uart ISR.
*
* @param serial serial device
*/
static void uart_isr(struct rt_serial_device *serial)
{
struct tm4c123_uart *uart;
uint32_t ui32Ints;
#ifdef RT_SERIAL_USING_DMA
rt_size_t recv_total_index, recv_len;
rt_base_t level;
#endif
RT_ASSERT(serial != RT_NULL);
uart = rt_container_of(serial, struct tm4c123_uart, serial);
ui32Ints = UARTIntStatus(uart->config->uartbase, true);
UARTIntClear(uart->config->uartbase, ui32Ints);
/* UART in mode Receiver -------------------------------------------------*/
if(ui32Ints & (UART_INT_RX | UART_INT_RT))
{
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
}
}
#if defined(BSP_USING_UART0)
void UART0IntHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
uart_isr(&(uart_obj[UART0_INDEX].serial));
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#if defined(BSP_USING_UART1)
void UART1IntHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
uart_isr(&(uart_obj[UART1_INDEX].serial));
/* leave interrupt */
rt_interrupt_leave();
}
//#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA)
//void UART1_DMA_RX_IRQHandler(void)
//{
// /* enter interrupt */
// rt_interrupt_enter();
// HAL_DMA_IRQHandler(&uart_obj[UART1_INDEX].dma_rx.handle);
// /* leave interrupt */
// rt_interrupt_leave();
//}
//#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA) */
//#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA)
//void UART1_DMA_TX_IRQHandler(void)
//{
// /* enter interrupt */
// rt_interrupt_enter();
// HAL_DMA_IRQHandler(&uart_obj[UART1_INDEX].dma_tx.handle);
// /* leave interrupt */
// rt_interrupt_leave();
//}
//#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA) */
#endif /* BSP_USING_UART1 */
static void tm4c123_uart_get_dma_config(void)
{
#ifdef BSP_USING_UART1
#endif
}
int rt_hw_usart_init(void)
{
rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct tm4c123_uart);
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
rt_err_t result = 0;
//tm4c123_uart_get_dma_config();
uart_hw_config();
for (int i = 0; i < obj_num; i++)
{
uart_obj[i].config = &uart_config[i];
uart_obj[i].uartintbase = uart_intbase[i];
uart_obj[i].serial.ops = &tm4c123_uart_ops;
uart_obj[i].serial.config = config;
/* register UART device */
result = rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name,
RT_DEVICE_FLAG_RDWR
| RT_DEVICE_FLAG_INT_RX
| RT_DEVICE_FLAG_INT_TX
| uart_obj[i].uart_dma_flag
, NULL);
RT_ASSERT(result == RT_EOK);
}
return result;
}
#endif /* RT_USING_SERIAL */

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#ifndef _DRV_UART_H_
#define _DRV_UART_H_
#include <stdint.h>
#include <rthw.h>
#include <rtthread.h>
#include "rtdevice.h"
/* tm4c123 config class */
struct tm4c123_uart_config
{
const char *name;
uint32_t uartbase;
uint32_t baudrate;
uint32_t mode;
//struct dma_config *dma_rx;
//struct dma_config *dma_tx;
};
/* tm4c123 uart dirver class */
struct tm4c123_uart
{
struct tm4c123_uart_config *config;
uint32_t uartintbase;
#ifdef RT_SERIAL_USING_DMA
#endif
rt_uint16_t uart_dma_flag;
struct rt_serial_device serial;
};
extern int rt_hw_usart_init(void);
#endif /*_DRV_UART_H_*/

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bsp/tm4c123bsp/libraries/TivaWare_C_series/SConscript Normal file
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import rtconfig
Import('RTT_ROOT')
from building import *
# get current directory
cwd = GetCurrentDir()
# The set of source files associated with this SConscript file.
src = Split("""
tm4c123_driverlib/src/sysctl.c
tm4c123_driverlib/src/systick.c
tm4c123_driverlib/src/interrupt.c
tm4c123_driverlib/src/fpu.c
tm4c123_driverlib/src/cpu.c
tm4c123_driverlib/src/gpio.c
""")
#if GetDepend(['RT_USING_PIN']):
if GetDepend(['RT_USING_SERIAL']):
src += ['tm4c123_driverlib/src/uart.c']
#if GetDepend(['RT_USING_I2C']):
if GetDepend(['RT_USING_SPI']):
src += ['tm4c123_driverlib/src/ssi.c']
#if GetDepend(['RT_USING_USB_HOST']) or GetDepend(['RT_USING_USB_DEVICE']):
#if GetDepend(['RT_USING_CAN']):
#if GetDepend(['RT_USING_HWTIMER'])
if GetDepend(['RT_USING_PWM']) or GetDepend(['RT_USING_PULSE_ENCODER']):
src += ['tm4c123_driverlib/src/pwm.c']
#if GetDepend(['BSP_USING_ETH']):
if GetDepend(['RT_USING_ADC']):
src += ['tm4c123_driverlib/src/adc.c']
#if GetDepend(['RT_USING_RTC']):
#if GetDepend(['RT_USING_WDT']):
#if GetDepend(['RT_USING_SDIO']):
#if GetDepend(['RT_USING_AUDIO']):
#if GetDepend(['RT_USING_MTD_NOR']):
#if GetDepend(['RT_USING_MTD_NAND']):
#if GetDepend(['BSP_USING_ON_CHIP_FLASH']):
path = [cwd + '/tm4c123_driverlib',
cwd + '/tm4c123_driverlib/driverlib',
cwd + '/tm4c123_driverlib/driverlib/inc']
group = DefineGroup('TM4C123_HAL', src, depend = [''], CPPPATH = path)
Return('group')

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bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/adc.h Normal file
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//*****************************************************************************
//
// adc.h - ADC headers for using the ADC driver functions.
//
// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __DRIVERLIB_ADC_H__
#define __DRIVERLIB_ADC_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to ADCSequenceConfigure as the ui32Trigger
// parameter.
//
//*****************************************************************************
#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event
#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event
#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event
#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event
#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event
#define ADC_TRIGGER_TIMER 0x00000005 // Timer event
#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event
#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event
#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event
#define ADC_TRIGGER_PWM3 0x00000009 // PWM3 event
#define ADC_TRIGGER_NEVER 0x0000000E // Never Trigger
#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event
#define ADC_TRIGGER_PWM_MOD0 0x00000000 // PWM triggers from PWM0
#define ADC_TRIGGER_PWM_MOD1 0x00000010 // PWM triggers from PWM1
//*****************************************************************************
//
// Values that can be passed to ADCSequenceStepConfigure as the ui32Config
// parameter.
//
//*****************************************************************************
#define ADC_CTL_TS 0x00000080 // Temperature sensor select
#define ADC_CTL_IE 0x00000040 // Interrupt enable
#define ADC_CTL_END 0x00000020 // Sequence end select
#define ADC_CTL_D 0x00000010 // Differential select
#define ADC_CTL_CH0 0x00000000 // Input channel 0
#define ADC_CTL_CH1 0x00000001 // Input channel 1
#define ADC_CTL_CH2 0x00000002 // Input channel 2
#define ADC_CTL_CH3 0x00000003 // Input channel 3
#define ADC_CTL_CH4 0x00000004 // Input channel 4
#define ADC_CTL_CH5 0x00000005 // Input channel 5
#define ADC_CTL_CH6 0x00000006 // Input channel 6
#define ADC_CTL_CH7 0x00000007 // Input channel 7
#define ADC_CTL_CH8 0x00000008 // Input channel 8
#define ADC_CTL_CH9 0x00000009 // Input channel 9
#define ADC_CTL_CH10 0x0000000A // Input channel 10
#define ADC_CTL_CH11 0x0000000B // Input channel 11
#define ADC_CTL_CH12 0x0000000C // Input channel 12
#define ADC_CTL_CH13 0x0000000D // Input channel 13
#define ADC_CTL_CH14 0x0000000E // Input channel 14
#define ADC_CTL_CH15 0x0000000F // Input channel 15
#define ADC_CTL_CH16 0x00000100 // Input channel 16
#define ADC_CTL_CH17 0x00000101 // Input channel 17
#define ADC_CTL_CH18 0x00000102 // Input channel 18
#define ADC_CTL_CH19 0x00000103 // Input channel 19
#define ADC_CTL_CH20 0x00000104 // Input channel 20
#define ADC_CTL_CH21 0x00000105 // Input channel 21
#define ADC_CTL_CH22 0x00000106 // Input channel 22
#define ADC_CTL_CH23 0x00000107 // Input channel 23
#define ADC_CTL_CMP0 0x00080000 // Select Comparator 0
#define ADC_CTL_CMP1 0x00090000 // Select Comparator 1
#define ADC_CTL_CMP2 0x000A0000 // Select Comparator 2
#define ADC_CTL_CMP3 0x000B0000 // Select Comparator 3
#define ADC_CTL_CMP4 0x000C0000 // Select Comparator 4
#define ADC_CTL_CMP5 0x000D0000 // Select Comparator 5
#define ADC_CTL_CMP6 0x000E0000 // Select Comparator 6
#define ADC_CTL_CMP7 0x000F0000 // Select Comparator 7
#define ADC_CTL_SHOLD_4 0x00000000 // Sample and hold 4 ADC clocks
#define ADC_CTL_SHOLD_8 0x00200000 // Sample and hold 8 ADC clocks
#define ADC_CTL_SHOLD_16 0x00400000 // Sample and hold 16 ADC clocks
#define ADC_CTL_SHOLD_32 0x00600000 // Sample and hold 32 ADC clocks
#define ADC_CTL_SHOLD_64 0x00800000 // Sample and hold 64 ADC clocks
#define ADC_CTL_SHOLD_128 0x00A00000 // Sample and hold 128 ADC clocks
#define ADC_CTL_SHOLD_256 0x00C00000 // Sample and hold 256 ADC clocks
//*****************************************************************************
//
// Values that can be passed to ADCComparatorConfigure as part of the
// ui32Config parameter.
//
//*****************************************************************************
#define ADC_COMP_TRIG_NONE 0x00000000 // Trigger Disabled
#define ADC_COMP_TRIG_LOW_ALWAYS \
0x00001000 // Trigger Low Always
#define ADC_COMP_TRIG_LOW_ONCE 0x00001100 // Trigger Low Once
#define ADC_COMP_TRIG_LOW_HALWAYS \
0x00001200 // Trigger Low Always (Hysteresis)
#define ADC_COMP_TRIG_LOW_HONCE 0x00001300 // Trigger Low Once (Hysteresis)
#define ADC_COMP_TRIG_MID_ALWAYS \
0x00001400 // Trigger Mid Always
#define ADC_COMP_TRIG_MID_ONCE 0x00001500 // Trigger Mid Once
#define ADC_COMP_TRIG_HIGH_ALWAYS \
0x00001C00 // Trigger High Always
#define ADC_COMP_TRIG_HIGH_ONCE 0x00001D00 // Trigger High Once
#define ADC_COMP_TRIG_HIGH_HALWAYS \
0x00001E00 // Trigger High Always (Hysteresis)
#define ADC_COMP_TRIG_HIGH_HONCE \
0x00001F00 // Trigger High Once (Hysteresis)
#define ADC_COMP_INT_NONE 0x00000000 // Interrupt Disabled
#define ADC_COMP_INT_LOW_ALWAYS \
0x00000010 // Interrupt Low Always
#define ADC_COMP_INT_LOW_ONCE 0x00000011 // Interrupt Low Once
#define ADC_COMP_INT_LOW_HALWAYS \
0x00000012 // Interrupt Low Always
// (Hysteresis)
#define ADC_COMP_INT_LOW_HONCE 0x00000013 // Interrupt Low Once (Hysteresis)
#define ADC_COMP_INT_MID_ALWAYS \
0x00000014 // Interrupt Mid Always
#define ADC_COMP_INT_MID_ONCE 0x00000015 // Interrupt Mid Once
#define ADC_COMP_INT_HIGH_ALWAYS \
0x0000001C // Interrupt High Always
#define ADC_COMP_INT_HIGH_ONCE 0x0000001D // Interrupt High Once
#define ADC_COMP_INT_HIGH_HALWAYS \
0x0000001E // Interrupt High Always
// (Hysteresis)
#define ADC_COMP_INT_HIGH_HONCE \
0x0000001F // Interrupt High Once (Hysteresis)
//*****************************************************************************
//
// Values that can be used to modify the sequence number passed to
// ADCProcessorTrigger in order to get cross-module synchronous processor
// triggers.
//
//*****************************************************************************
#define ADC_TRIGGER_WAIT 0x08000000 // Wait for the synchronous trigger
#define ADC_TRIGGER_SIGNAL 0x80000000 // Signal the synchronous trigger
//*****************************************************************************
//
// Values that can be passed to ADCPhaseDelaySet as the ui32Phase parameter and
// returned from ADCPhaseDelayGet.
//
//*****************************************************************************
#define ADC_PHASE_0 0x00000000 // 0 degrees
#define ADC_PHASE_22_5 0x00000001 // 22.5 degrees
#define ADC_PHASE_45 0x00000002 // 45 degrees
#define ADC_PHASE_67_5 0x00000003 // 67.5 degrees
#define ADC_PHASE_90 0x00000004 // 90 degrees
#define ADC_PHASE_112_5 0x00000005 // 112.5 degrees
#define ADC_PHASE_135 0x00000006 // 135 degrees
#define ADC_PHASE_157_5 0x00000007 // 157.5 degrees
#define ADC_PHASE_180 0x00000008 // 180 degrees
#define ADC_PHASE_202_5 0x00000009 // 202.5 degrees
#define ADC_PHASE_225 0x0000000A // 225 degrees
#define ADC_PHASE_247_5 0x0000000B // 247.5 degrees
#define ADC_PHASE_270 0x0000000C // 270 degrees
#define ADC_PHASE_292_5 0x0000000D // 292.5 degrees
#define ADC_PHASE_315 0x0000000E // 315 degrees
#define ADC_PHASE_337_5 0x0000000F // 337.5 degrees
//*****************************************************************************
//
// Values that can be passed to ADCReferenceSet as the ui32Ref parameter.
//
//*****************************************************************************
#define ADC_REF_INT 0x00000000 // Internal reference
#define ADC_REF_EXT_3V 0x00000001 // External 3V reference
//*****************************************************************************
//
// Values that can be passed to ADCIntDisableEx(), ADCIntEnableEx(),
// ADCIntClearEx() and ADCIntStatusEx().
//
//*****************************************************************************
#define ADC_INT_SS0 0x00000001
#define ADC_INT_SS1 0x00000002
#define ADC_INT_SS2 0x00000004
#define ADC_INT_SS3 0x00000008
#define ADC_INT_DMA_SS0 0x00000100
#define ADC_INT_DMA_SS1 0x00000200
#define ADC_INT_DMA_SS2 0x00000400
#define ADC_INT_DMA_SS3 0x00000800
#define ADC_INT_DCON_SS0 0x00010000
#define ADC_INT_DCON_SS1 0x00020000
#define ADC_INT_DCON_SS2 0x00040000
#define ADC_INT_DCON_SS3 0x00080000
//*****************************************************************************
//
// Values that can be passed to ADCClockConfigSet() and ADCClockConfigGet().
//
//*****************************************************************************
#define ADC_CLOCK_RATE_FULL 0x00000070
#define ADC_CLOCK_RATE_HALF 0x00000050
#define ADC_CLOCK_RATE_FOURTH 0x00000030
#define ADC_CLOCK_RATE_EIGHTH 0x00000010
#define ADC_CLOCK_SRC_PLL 0x00000000
#define ADC_CLOCK_SRC_PIOSC 0x00000001
#define ADC_CLOCK_SRC_ALTCLK 0x00000001
#define ADC_CLOCK_SRC_MOSC 0x00000002
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void ADCIntRegister(uint32_t ui32Base, uint32_t ui32SequenceNum,
void (*pfnHandler)(void));
extern void ADCIntUnregister(uint32_t ui32Base, uint32_t ui32SequenceNum);
extern void ADCIntDisable(uint32_t ui32Base, uint32_t ui32SequenceNum);
extern void ADCIntEnable(uint32_t ui32Base, uint32_t ui32SequenceNum);
extern uint32_t ADCIntStatus(uint32_t ui32Base, uint32_t ui32SequenceNum,
bool bMasked);
extern void ADCIntClear(uint32_t ui32Base, uint32_t ui32SequenceNum);
extern void ADCSequenceEnable(uint32_t ui32Base, uint32_t ui32SequenceNum);
extern void ADCSequenceDisable(uint32_t ui32Base, uint32_t ui32SequenceNum);
extern void ADCSequenceConfigure(uint32_t ui32Base, uint32_t ui32SequenceNum,
uint32_t ui32Trigger, uint32_t ui32Priority);
extern void ADCSequenceStepConfigure(uint32_t ui32Base,
uint32_t ui32SequenceNum,
uint32_t ui32Step, uint32_t ui32Config);
extern int32_t ADCSequenceOverflow(uint32_t ui32Base,
uint32_t ui32SequenceNum);
extern void ADCSequenceOverflowClear(uint32_t ui32Base,
uint32_t ui32SequenceNum);
extern int32_t ADCSequenceUnderflow(uint32_t ui32Base,
uint32_t ui32SequenceNum);
extern void ADCSequenceUnderflowClear(uint32_t ui32Base,
uint32_t ui32SequenceNum);
extern int32_t ADCSequenceDataGet(uint32_t ui32Base, uint32_t ui32SequenceNum,
uint32_t *pui32Buffer);
extern void ADCProcessorTrigger(uint32_t ui32Base, uint32_t ui32SequenceNum);
extern void ADCSoftwareOversampleConfigure(uint32_t ui32Base,
uint32_t ui32SequenceNum,
uint32_t ui32Factor);
extern void ADCSoftwareOversampleStepConfigure(uint32_t ui32Base,
uint32_t ui32SequenceNum,
uint32_t ui32Step,
uint32_t ui32Config);
extern void ADCSoftwareOversampleDataGet(uint32_t ui32Base,
uint32_t ui32SequenceNum,
uint32_t *pui32Buffer,
uint32_t ui32Count);
extern void ADCHardwareOversampleConfigure(uint32_t ui32Base,
uint32_t ui32Factor);
extern void ADCClockConfigSet(uint32_t ui32Base, uint32_t ui32Config,
uint32_t ui32ClockDiv);
extern uint32_t ADCClockConfigGet(uint32_t ui32Base, uint32_t *pui32ClockDiv);
extern void ADCComparatorConfigure(uint32_t ui32Base, uint32_t ui32Comp,
uint32_t ui32Config);
extern void ADCComparatorRegionSet(uint32_t ui32Base, uint32_t ui32Comp,
uint32_t ui32LowRef, uint32_t ui32HighRef);
extern void ADCComparatorReset(uint32_t ui32Base, uint32_t ui32Comp,
bool bTrigger, bool bInterrupt);
extern void ADCComparatorIntDisable(uint32_t ui32Base,
uint32_t ui32SequenceNum);
extern void ADCComparatorIntEnable(uint32_t ui32Base,
uint32_t ui32SequenceNum);
extern uint32_t ADCComparatorIntStatus(uint32_t ui32Base);
extern void ADCComparatorIntClear(uint32_t ui32Base, uint32_t ui32Status);
extern void ADCIntDisableEx(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void ADCIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags);
extern uint32_t ADCIntStatusEx(uint32_t ui32Base, bool bMasked);
extern void ADCIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void ADCSequenceDMAEnable(uint32_t ui32Base, uint32_t ui32SequenceNum);
extern void ADCSequenceDMADisable(uint32_t ui32Base, uint32_t ui32SequenceNum);
extern bool ADCBusy(uint32_t ui32Base);
extern void ADCReferenceSet(uint32_t ui32Base, uint32_t ui32Ref);
extern uint32_t ADCReferenceGet(uint32_t ui32Base);
extern void ADCPhaseDelaySet(uint32_t ui32Base, uint32_t ui32Phase);
extern uint32_t ADCPhaseDelayGet(uint32_t ui32Base);
extern void ADCSampleRateSet(uint32_t ui32Base, uint32_t ui32ADCClock,
uint32_t ui32Rate);
extern uint32_t ADCSampleRateGet(uint32_t ui32Base);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_ADC_H__

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//*****************************************************************************
//
// aes.h - Defines and Macros for the AES module.
//
// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __DRIVERLIB_AES_H__
#define __DRIVERLIB_AES_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following defines are used to specify the operation direction in the
// ui32Config argument in the AESConfig function. Only one is permitted.
//
//*****************************************************************************
#define AES_CFG_DIR_ENCRYPT 0x00000004
#define AES_CFG_DIR_DECRYPT 0x00000000
//*****************************************************************************
//
// The following defines are used to specify the key size in the ui32Config
// argument in the AESConfig function. Only one is permitted.
//
//*****************************************************************************
#define AES_CFG_KEY_SIZE_128BIT 0x00000008
#define AES_CFG_KEY_SIZE_192BIT 0x00000010
#define AES_CFG_KEY_SIZE_256BIT 0x00000018
//*****************************************************************************
//
// The following defines are used to specify the mode of operation in the
// ui32Config argument in the AESConfig function. Only one is permitted.
//
//*****************************************************************************
#define AES_CFG_MODE_M 0x2007fe60
#define AES_CFG_MODE_ECB 0x00000000
#define AES_CFG_MODE_CBC 0x00000020
#define AES_CFG_MODE_CTR 0x00000040
#define AES_CFG_MODE_ICM 0x00000200
#define AES_CFG_MODE_CFB 0x00000400
#define AES_CFG_MODE_XTS_TWEAKJL \
0x00000800
#define AES_CFG_MODE_XTS_K2IJL \
0x00001000
#define AES_CFG_MODE_XTS_K2ILJ0 \
0x00001800
#define AES_CFG_MODE_F8 0x00002000
#define AES_CFG_MODE_F9 0x20004000
#define AES_CFG_MODE_CBCMAC 0x20008000
#define AES_CFG_MODE_GCM_HLY0ZERO \
0x20010000
#define AES_CFG_MODE_GCM_HLY0CALC \
0x20020040
#define AES_CFG_MODE_GCM_HY0CALC \
0x20030040
#define AES_CFG_MODE_CCM 0x20040040
//*****************************************************************************
//
// The following defines are used to specify the counter width in the
// ui32Config argument in the AESConfig function. It is only required to
// be defined when using CTR, CCM, or GCM modes. Only one length is permitted.
//
//*****************************************************************************
#define AES_CFG_CTR_WIDTH_32 0x00000000
#define AES_CFG_CTR_WIDTH_64 0x00000080
#define AES_CFG_CTR_WIDTH_96 0x00000100
#define AES_CFG_CTR_WIDTH_128 0x00000180
//*****************************************************************************
//
// The following defines are used to define the width of the length field for
// CCM operation through the ui32Config argument in the AESConfig function.
// This value is also known as L. Only one is permitted.
//
//*****************************************************************************
#define AES_CFG_CCM_L_1 0x00000000
#define AES_CFG_CCM_L_2 0x00080000
#define AES_CFG_CCM_L_3 0x00100000
#define AES_CFG_CCM_L_4 0x00180000
#define AES_CFG_CCM_L_5 0x00200000
#define AES_CFG_CCM_L_6 0x00280000
#define AES_CFG_CCM_L_7 0x00300000
#define AES_CFG_CCM_L_8 0x00380000
//*****************************************************************************
//
// The following defines are used to define the length of the authentication
// field for CCM operations through the ui32Config argument in the AESConfig
// function. This value is also known as M. Only one is permitted.
//
//*****************************************************************************
#define AES_CFG_CCM_M_4 0x00400000
#define AES_CFG_CCM_M_6 0x00800000
#define AES_CFG_CCM_M_8 0x00c00000
#define AES_CFG_CCM_M_10 0x01000000
#define AES_CFG_CCM_M_12 0x01400000
#define AES_CFG_CCM_M_14 0x01800000
#define AES_CFG_CCM_M_16 0x01c00000
//*****************************************************************************
//
// Interrupt flags for use with the AESIntEnable, AESIntDisable, and
// AESIntStatus functions.
//
//*****************************************************************************
#define AES_INT_CONTEXT_IN 0x00000001
#define AES_INT_CONTEXT_OUT 0x00000008
#define AES_INT_DATA_IN 0x00000002
#define AES_INT_DATA_OUT 0x00000004
#define AES_INT_DMA_CONTEXT_IN 0x00010000
#define AES_INT_DMA_CONTEXT_OUT 0x00080000
#define AES_INT_DMA_DATA_IN 0x00020000
#define AES_INT_DMA_DATA_OUT 0x00040000
//*****************************************************************************
//
// Defines used when enabling and disabling DMA requests in the
// AESEnableDMA and AESDisableDMA functions.
//
//*****************************************************************************
#define AES_DMA_DATA_IN 0x00000020
#define AES_DMA_DATA_OUT 0x00000040
#define AES_DMA_CONTEXT_IN 0x00000080
#define AES_DMA_CONTEXT_OUT 0x00000100
//*****************************************************************************
//
// Function prototypes.
//
//*****************************************************************************
extern void AESAuthLengthSet(uint32_t ui32Base, uint32_t ui32Length);
extern void AESConfigSet(uint32_t ui32Base, uint32_t ui32Config);
extern void AESDataRead(uint32_t ui32Base, uint32_t *pui32Dest);
extern bool AESDataReadNonBlocking(uint32_t ui32Base, uint32_t *pui32Dest);
extern bool AESDataProcess(uint32_t ui32Base, uint32_t *pui32Src,
uint32_t *pui32Dest, uint32_t ui32Length);
extern bool AESDataAuth(uint32_t ui32Base, uint32_t *pui32Src,
uint32_t ui32Length, uint32_t *pui32Tag);
extern bool AESDataProcessAuth(uint32_t ui32Base, uint32_t *pui32Src,
uint32_t *pui32Dest, uint32_t ui32Length,
uint32_t *pui32AuthSrc,
uint32_t ui32AuthLength, uint32_t *pui32Tag);
extern void AESDataWrite(uint32_t ui32Base, uint32_t *pui32Src);
extern bool AESDataWriteNonBlocking(uint32_t ui32Base, uint32_t *pui32Src);
extern void AESDMADisable(uint32_t ui32Base, uint32_t ui32Flags);
extern void AESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags);
extern void AESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void AESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void AESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void AESIntRegister(uint32_t ui32Base, void (*pfnHandler)(void));
extern uint32_t AESIntStatus(uint32_t ui32Base, bool bMasked);
extern void AESIntUnregister(uint32_t ui32Base);
extern void AESIVSet(uint32_t ui32Base, uint32_t *pui32IVdata);
extern void AESIVRead(uint32_t ui32Base, uint32_t *pui32IVdata);
extern void AESKey1Set(uint32_t ui32Base, uint32_t *pui32Key,
uint32_t ui32Keysize);
extern void AESKey2Set(uint32_t ui32Base, uint32_t *pui32Key,
uint32_t ui32Keysize);
extern void AESKey3Set(uint32_t ui32Base, uint32_t *pui32Key);
extern void AESLengthSet(uint32_t ui32Base, uint64_t ui64Length);
extern void AESReset(uint32_t ui32Base);
extern void AESTagRead(uint32_t ui32Base, uint32_t *pui32TagData);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_AES_H__

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//*****************************************************************************
//
// can.h - Defines and Macros for the CAN controller.
//
// Copyright (c) 2006-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __DRIVERLIB_CAN_H__
#define __DRIVERLIB_CAN_H__
//*****************************************************************************
//
//! \addtogroup can_api
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Miscellaneous defines for Message ID Types
//
//*****************************************************************************
//*****************************************************************************
//
// These are the flags used by the tCANMsgObject.ui32Flags value when calling
// the CANMessageSet() and CANMessageGet() functions.
//
//*****************************************************************************
//
//! This indicates that transmit interrupts are enabled.
//
#define MSG_OBJ_TX_INT_ENABLE 0x00000001
//
//! This indicates that receive interrupts are enabled.
//
#define MSG_OBJ_RX_INT_ENABLE 0x00000002
//
//! This indicates that a message object is using an extended identifier.
//
#define MSG_OBJ_EXTENDED_ID 0x00000004
//
//! This indicates that a message object is using filtering based on the
//! object's message identifier.
//
#define MSG_OBJ_USE_ID_FILTER 0x00000008
//
//! This indicates that new data was available in the message object.
//
#define MSG_OBJ_NEW_DATA 0x00000080
//
//! This indicates that data was lost since this message object was last
//! read.
//
#define MSG_OBJ_DATA_LOST 0x00000100
//
//! This indicates that a message object uses or is using filtering
//! based on the direction of the transfer. If the direction filtering is
//! used, then ID filtering must also be enabled.
//
#define MSG_OBJ_USE_DIR_FILTER (0x00000010 | MSG_OBJ_USE_ID_FILTER)
//
//! This indicates that a message object uses or is using message
//! identifier filtering based on the extended identifier. If the extended
//! identifier filtering is used, then ID filtering must also be enabled.
//
#define MSG_OBJ_USE_EXT_FILTER (0x00000020 | MSG_OBJ_USE_ID_FILTER)
//
//! This indicates that a message object is a remote frame.
//
#define MSG_OBJ_REMOTE_FRAME 0x00000040
//
//! This indicates that this message object is part of a FIFO structure and
//! not the final message object in a FIFO.
//
#define MSG_OBJ_FIFO 0x00000200
//
//! This indicates that a message object has no flags set.
//
#define MSG_OBJ_NO_FLAGS 0x00000000
//*****************************************************************************
//
//! This define is used with the flag values to allow checking only status
//! flags and not configuration flags.
//
//*****************************************************************************
#define MSG_OBJ_STATUS_MASK (MSG_OBJ_NEW_DATA | MSG_OBJ_DATA_LOST)
//*****************************************************************************
//
//! The structure used for encapsulating all the items associated with a CAN
//! message object in the CAN controller.
//
//*****************************************************************************
typedef struct
{
//
//! The CAN message identifier used for 11 or 29 bit identifiers.
//
uint32_t ui32MsgID;
//
//! The message identifier mask used when identifier filtering is enabled.
//
uint32_t ui32MsgIDMask;
//
//! This value holds various status flags and settings specified by
//! tCANObjFlags.
//
uint32_t ui32Flags;
//
//! This value is the number of bytes of data in the message object.
//
uint32_t ui32MsgLen;
//
//! This is a pointer to the message object's data.
//
uint8_t *pui8MsgData;
}
tCANMsgObject;
//*****************************************************************************
//
//! This structure is used for encapsulating the values associated with setting
//! up the bit timing for a CAN controller. The structure is used when calling
//! the CANGetBitTiming and CANSetBitTiming functions.
//
//*****************************************************************************
typedef struct
{
//
//! This value holds the sum of the Synchronization, Propagation, and Phase
//! Buffer 1 segments, measured in time quanta. The valid values for this
//! setting range from 2 to 16.
//
uint32_t ui32SyncPropPhase1Seg;
//
//! This value holds the Phase Buffer 2 segment in time quanta. The valid
//! values for this setting range from 1 to 8.
//
uint32_t ui32Phase2Seg;
//
//! This value holds the Resynchronization Jump Width in time quanta. The
//! valid values for this setting range from 1 to 4.
//
uint32_t ui32SJW;
//
//! This value holds the CAN_CLK divider used to determine time quanta.
//! The valid values for this setting range from 1 to 1023.
//
uint32_t ui32QuantumPrescaler;
}
tCANBitClkParms;
//*****************************************************************************
//
//! This data type is used to identify the interrupt status register. This is
//! used when calling the CANIntStatus() function.
//
//*****************************************************************************
typedef enum
{
//
//! Read the CAN interrupt status information.
//
CAN_INT_STS_CAUSE,
//
//! Read a message object's interrupt status.
//
CAN_INT_STS_OBJECT
}
tCANIntStsReg;
//*****************************************************************************
//
//! This data type is used to identify which of several status registers to
//! read when calling the CANStatusGet() function.
//
//*****************************************************************************
typedef enum
{
//
//! Read the full CAN controller status.
//
CAN_STS_CONTROL,
//
//! Read the full 32-bit mask of message objects with a transmit request
//! set.
//
CAN_STS_TXREQUEST,
//
//! Read the full 32-bit mask of message objects with new data available.
//
CAN_STS_NEWDAT,
//
//! Read the full 32-bit mask of message objects that are enabled.
//
CAN_STS_MSGVAL
}
tCANStsReg;
//*****************************************************************************
//
// These definitions are used to specify interrupt sources to CANIntEnable()
// and CANIntDisable().
//
//*****************************************************************************
//
//! This flag is used to allow a CAN controller to generate error
//! interrupts.
//
#define CAN_INT_ERROR 0x00000008
//
//! This flag is used to allow a CAN controller to generate status
//! interrupts.
//
#define CAN_INT_STATUS 0x00000004
//
//! This flag is used to allow a CAN controller to generate any CAN
//! interrupts. If this is not set, then no interrupts are generated
//! by the CAN controller.
//
#define CAN_INT_MASTER 0x00000002
//*****************************************************************************
//
//! This definition is used to determine the type of message object that is
//! set up via a call to the CANMessageSet() API.
//
//*****************************************************************************
typedef enum
{
//
//! Transmit message object.
//
MSG_OBJ_TYPE_TX,
//
//! Transmit remote request message object
//
MSG_OBJ_TYPE_TX_REMOTE,
//
//! Receive message object.
//
MSG_OBJ_TYPE_RX,
//
//! Receive remote request message object.
//
MSG_OBJ_TYPE_RX_REMOTE,
//
//! Remote frame receive remote, with auto-transmit message object.
//
MSG_OBJ_TYPE_RXTX_REMOTE
}
tMsgObjType;
//*****************************************************************************
//
// The following enumeration contains all error or status indicators that can
// be returned when calling the CANStatusGet() function.
//
//*****************************************************************************
//
//! CAN controller has entered a Bus Off state.
//
#define CAN_STATUS_BUS_OFF 0x00000080
//
//! CAN controller error level has reached warning level.
//
#define CAN_STATUS_EWARN 0x00000040
//
//! CAN controller error level has reached error passive level.
//
#define CAN_STATUS_EPASS 0x00000020
//
//! A message was received successfully since the last read of this status.
//
#define CAN_STATUS_RXOK 0x00000010
//
//! A message was transmitted successfully since the last read of this
//! status.
//
#define CAN_STATUS_TXOK 0x00000008
//
//! This is the mask for the last error code field.
//
#define CAN_STATUS_LEC_MSK 0x00000007
//
//! There was no error.
//
#define CAN_STATUS_LEC_NONE 0x00000000
//
//! A bit stuffing error has occurred.
//
#define CAN_STATUS_LEC_STUFF 0x00000001
//
//! A formatting error has occurred.
//
#define CAN_STATUS_LEC_FORM 0x00000002
//
//! An acknowledge error has occurred.
//
#define CAN_STATUS_LEC_ACK 0x00000003
//
//! The bus remained a bit level of 1 for longer than is allowed.
//
#define CAN_STATUS_LEC_BIT1 0x00000004
//
//! The bus remained a bit level of 0 for longer than is allowed.
//
#define CAN_STATUS_LEC_BIT0 0x00000005
//
//! A CRC error has occurred.
//
#define CAN_STATUS_LEC_CRC 0x00000006
//
//! This is the mask for the CAN Last Error Code (LEC).
//
#define CAN_STATUS_LEC_MASK 0x00000007
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void CANBitTimingGet(uint32_t ui32Base, tCANBitClkParms *psClkParms);
extern void CANBitTimingSet(uint32_t ui32Base, tCANBitClkParms *psClkParms);
extern uint32_t CANBitRateSet(uint32_t ui32Base, uint32_t ui32SourceClock,
uint32_t ui32BitRate);
extern void CANDisable(uint32_t ui32Base);
extern void CANEnable(uint32_t ui32Base);
extern bool CANErrCntrGet(uint32_t ui32Base, uint32_t *pui32RxCount,
uint32_t *pui32TxCount);
extern void CANInit(uint32_t ui32Base);
extern void CANIntClear(uint32_t ui32Base, uint32_t ui32IntClr);
extern void CANIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void CANIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void CANIntRegister(uint32_t ui32Base, void (*pfnHandler)(void));
extern uint32_t CANIntStatus(uint32_t ui32Base, tCANIntStsReg eIntStsReg);
extern void CANIntUnregister(uint32_t ui32Base);
extern void CANMessageClear(uint32_t ui32Base, uint32_t ui32ObjID);
extern void CANMessageGet(uint32_t ui32Base, uint32_t ui32ObjID,
tCANMsgObject *psMsgObject, bool bClrPendingInt);
extern void CANMessageSet(uint32_t ui32Base, uint32_t ui32ObjID,
tCANMsgObject *psMsgObject, tMsgObjType eMsgType);
extern bool CANRetryGet(uint32_t ui32Base);
extern void CANRetrySet(uint32_t ui32Base, bool bAutoRetry);
extern uint32_t CANStatusGet(uint32_t ui32Base, tCANStsReg eStatusReg);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_CAN_H__

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//*****************************************************************************
//
// comp.h - Prototypes for the analog comparator driver.
//
// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __DRIVERLIB_COMP_H__
#define __DRIVERLIB_COMP_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to ComparatorConfigure() as the ui32Config
// parameter. For each group (in other words, COMP_TRIG_xxx, COMP_INT_xxx, and
// so on), one of the values may be selected and combined together with values
// from the other groups via a logical OR.
//
//*****************************************************************************
#define COMP_TRIG_NONE 0x00000000 // No ADC trigger
#define COMP_TRIG_HIGH 0x00000880 // Trigger when high
#define COMP_TRIG_LOW 0x00000800 // Trigger when low
#define COMP_TRIG_FALL 0x00000820 // Trigger on falling edge
#define COMP_TRIG_RISE 0x00000840 // Trigger on rising edge
#define COMP_TRIG_BOTH 0x00000860 // Trigger on both edges
#define COMP_INT_HIGH 0x00000010 // Interrupt when high
#define COMP_INT_LOW 0x00000000 // Interrupt when low
#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge
#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge
#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges
#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin
#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin
#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference
#define COMP_OUTPUT_NORMAL 0x00000000 // Comparator output normal
#define COMP_OUTPUT_INVERT 0x00000002 // Comparator output inverted
//*****************************************************************************
//
// Values that can be passed to ComparatorSetRef() as the ui32Ref parameter.
//
//*****************************************************************************
#define COMP_REF_OFF 0x00000000 // Turn off the internal reference
#define COMP_REF_0V 0x00000300 // Internal reference of 0V
#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V
#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V
#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V
#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V
#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V
#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V
#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V
#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V
#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V
#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V
#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V
#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V
#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V
#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V
#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V
#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V
#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V
#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V
#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V
#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V
#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V
#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V
#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V
#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V
#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V
#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V
#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void ComparatorConfigure(uint32_t ui32Base, uint32_t ui32Comp,
uint32_t ui32Config);
extern void ComparatorRefSet(uint32_t ui32Base, uint32_t ui32Ref);
extern bool ComparatorValueGet(uint32_t ui32Base, uint32_t ui32Comp);
extern void ComparatorIntRegister(uint32_t ui32Base, uint32_t ui32Comp,
void (*pfnHandler)(void));
extern void ComparatorIntUnregister(uint32_t ui32Base, uint32_t ui32Comp);
extern void ComparatorIntEnable(uint32_t ui32Base, uint32_t ui32Comp);
extern void ComparatorIntDisable(uint32_t ui32Base, uint32_t ui32Comp);
extern bool ComparatorIntStatus(uint32_t ui32Base, uint32_t ui32Comp,
bool bMasked);
extern void ComparatorIntClear(uint32_t ui32Base, uint32_t ui32Comp);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_COMP_H__

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//*****************************************************************************
//
// cpu.h - Prototypes for the CPU instruction wrapper functions.
//
// Copyright (c) 2006-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __DRIVERLIB_CPU_H__
#define __DRIVERLIB_CPU_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Prototypes.
//
//*****************************************************************************
extern uint32_t CPUcpsid(void);
extern uint32_t CPUcpsie(void);
extern uint32_t CPUprimask(void);
extern void CPUwfi(void);
extern uint32_t CPUbasepriGet(void);
extern void CPUbasepriSet(uint32_t ui32NewBasepri);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_CPU_H__

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//*****************************************************************************
//
// crc.h - Defines and Macros for CRC module.
//
// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __DRIVERLIB_CRC_H__
#define __DRIVERLIB_CRC_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following defines are used in the ui32Config argument of the
// ECConfig function.
//
//*****************************************************************************
#define CRC_CFG_INIT_SEED 0x00000000 // Initialize with seed
#define CRC_CFG_INIT_0 0x00004000 // Initialize to all '0s'
#define CRC_CFG_INIT_1 0x00006000 // Initialize to all '1s'
#define CRC_CFG_SIZE_8BIT 0x00001000 // Input Data Size
#define CRC_CFG_SIZE_32BIT 0x00000000 // Input Data Size
#define CRC_CFG_RESINV 0x00000200 // Result Inverse Enable
#define CRC_CFG_OBR 0x00000100 // Output Reverse Enable
#define CRC_CFG_IBR 0x00000080 // Bit reverse enable
#define CRC_CFG_ENDIAN_SBHW 0x00000020 // Swap byte in half-word
#define CRC_CFG_ENDIAN_SHW 0x00000010 // Swap half-word
#define CRC_CFG_TYPE_P8005 0x00000000 // Polynomial 0x8005
#define CRC_CFG_TYPE_P1021 0x00000001 // Polynomial 0x1021
#define CRC_CFG_TYPE_P4C11DB7 0x00000002 // Polynomial 0x4C11DB7
#define CRC_CFG_TYPE_P1EDC6F41 0x00000003 // Polynomial 0x1EDC6F41
#define CRC_CFG_TYPE_TCPCHKSUM 0x00000008 // TCP checksum
//*****************************************************************************
//
// Function prototypes.
//
//*****************************************************************************
#if 0
extern void ECClockGatingReqest(uint32_t ui32Base, uint32_t ui32ECIP,
bool bGate);
#endif
extern void CRCConfigSet(uint32_t ui32Base, uint32_t ui32CRCConfig);
extern uint32_t CRCDataProcess(uint32_t ui32Base, uint32_t *pui32DataIn,
uint32_t ui32DataLength, bool bPPResult);
extern void CRCDataWrite(uint32_t ui32Base, uint32_t ui32Data);
extern uint32_t CRCResultRead(uint32_t ui32Base, bool bPPResult);
extern void CRCSeedSet(uint32_t ui32Base, uint32_t ui32Seed);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_CRC_H__

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//*****************************************************************************
//
// debug.h - Macros for assisting debug of the driver library.
//
// Copyright (c) 2006-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __DRIVERLIB_DEBUG_H__
#define __DRIVERLIB_DEBUG_H__
//*****************************************************************************
//
// Prototype for the function that is called when an invalid argument is passed
// to an API. This is only used when doing a DEBUG build.
//
//*****************************************************************************
extern void __error__(char *pcFilename, uint32_t ui32Line);
//*****************************************************************************
//
// The ASSERT macro, which does the actual assertion checking. Typically, this
// will be for procedure arguments.
//
//*****************************************************************************
#ifdef DEBUG
#define ASSERT(expr) do \
{ \
if(!(expr)) \
{ \
__error__(__FILE__, __LINE__); \
} \
} \
while(0)
#else
#define ASSERT(expr)
#endif
#endif // __DRIVERLIB_DEBUG_H__

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//*****************************************************************************
//
// des.h - Defines and Macros for the DES module.
//
// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __DRIVERLIB_DES_H__
#define __DRIVERLIB_DES_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following defines are used to specify the direction with the
// ui32Config argument in the DESConfig() function. Only one is permitted.
//
//*****************************************************************************
#define DES_CFG_DIR_DECRYPT 0x00000000
#define DES_CFG_DIR_ENCRYPT 0x00000004
//*****************************************************************************
//
// The following defines are used to specify the operational with the
// ui32Config argument in the DESConfig() function. Only one is permitted.
//
//*****************************************************************************
#define DES_CFG_MODE_ECB 0x00000000
#define DES_CFG_MODE_CBC 0x00000010
#define DES_CFG_MODE_CFB 0x00000020
//*****************************************************************************
//
// The following defines are used to select between single DES and triple DES
// with the ui32Config argument in the DESConfig() function. Only one is
// permitted.
//
//*****************************************************************************
#define DES_CFG_SINGLE 0x00000000
#define DES_CFG_TRIPLE 0x00000008
//*****************************************************************************
//
// The following defines are used with the DESIntEnable(), DESIntDisable() and
// DESIntStatus() functions.
//
//*****************************************************************************
#define DES_INT_CONTEXT_IN 0x00000001
#define DES_INT_DATA_IN 0x00000002
#define DES_INT_DATA_OUT 0x00000004
#define DES_INT_DMA_CONTEXT_IN 0x00010000
#define DES_INT_DMA_DATA_IN 0x00020000
#define DES_INT_DMA_DATA_OUT 0x00040000
//*****************************************************************************
//
// The following defines are used with the DESEnableDMA() and DESDisableDMA()
// functions.
//
//*****************************************************************************
#define DES_DMA_CONTEXT_IN 0x00000080
#define DES_DMA_DATA_OUT 0x00000040
#define DES_DMA_DATA_IN 0x00000020
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void DESConfigSet(uint32_t ui32Base, uint32_t ui32Config);
extern void DESDataRead(uint32_t ui32Base, uint32_t *pui32Dest);
extern bool DESDataReadNonBlocking(uint32_t ui32Base, uint32_t *pui32Dest);
extern bool DESDataProcess(uint32_t ui32Base, uint32_t *pui32Src,
uint32_t *pui32Dest, uint32_t ui32Length);
extern void DESDataWrite(uint32_t ui32Base, uint32_t *pui32Src);
extern bool DESDataWriteNonBlocking(uint32_t ui32Base, uint32_t *pui32Src);
extern void DESDMADisable(uint32_t ui32Base, uint32_t ui32Flags);
extern void DESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags);
extern void DESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void DESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void DESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void DESIntRegister(uint32_t ui32Base, void (*pfnHandler)(void));
extern uint32_t DESIntStatus(uint32_t ui32Base, bool bMasked);
extern void DESIntUnregister(uint32_t ui32Base);
extern bool DESIVSet(uint32_t ui32Base, uint32_t *pui32IVdata);
extern void DESKeySet(uint32_t ui32Base, uint32_t *pui32Key);
extern void DESLengthSet(uint32_t ui32Base, uint32_t ui32Length);
extern void DESReset(uint32_t ui32Base);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_DES_H__

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//*****************************************************************************
//
// eeprom.h - Prototypes for the EEPROM driver.
//
// Copyright (c) 2010-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __DRIVERLIB_EEPROM_H__
#define __DRIVERLIB_EEPROM_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
//! \addtogroup eeprom_api
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// Values returned by EEPROMInit.
//
//*****************************************************************************
//
//! This value may be returned from a call to EEPROMInit(). It indicates that
//! no previous write operations were interrupted by a reset event and that the
//! EEPROM peripheral is ready for use.
//
#define EEPROM_INIT_OK 0
//
//! This value may be returned from a call to EEPROMInit(). It indicates that
//! a previous data or protection write operation was interrupted by a reset
//! event and that the EEPROM peripheral was unable to clean up after the
//! problem. This situation may be resolved with another reset or may be fatal
//! depending upon the cause of the problem. For example, if the voltage to
//! the part is unstable, retrying once the voltage has stabilized may clear
//! the error.
//
#define EEPROM_INIT_ERROR 2
//*****************************************************************************
//
// Error indicators returned by various EEPROM API calls. These will be ORed
// together into the final return code.
//
//*****************************************************************************
//
//! This return code bit indicates that an attempt was made to read from
//! the EEPROM while a write operation was in progress.
//
#define EEPROM_RC_WRBUSY 0x00000020
//
//! This return code bit indicates that an attempt was made to write a
//! value but the destination permissions disallow write operations. This
//! may be due to the destination block being locked, access protection set
//! to prohibit writes or an attempt to write a password when one is already
//! written.
//
#define EEPROM_RC_NOPERM 0x00000010
//
//! This return code bit indicates that the EEPROM programming state machine
//! is currently copying to or from the internal copy buffer to make room for
//! a newly written value. It is provided as a status indicator and does not
//! indicate an error.
//
#define EEPROM_RC_WKCOPY 0x00000008
//
//! This return code bit indicates that the EEPROM programming state machine
//! is currently erasing the internal copy buffer. It is provided as a
//! status indicator and does not indicate an error.
//
#define EEPROM_RC_WKERASE 0x00000004
//
//! This return code bit indicates that the EEPROM programming state machine
//! is currently working. No new write operations should be attempted until
//! this bit is clear.
//
#define EEPROM_RC_WORKING 0x00000001
//*****************************************************************************
//
// Values that can be passed to EEPROMBlockProtectSet() in the ui32Protect
// parameter, and returned by EEPROMBlockProtectGet().
//
//*****************************************************************************
//
//! This bit may be ORed with the protection option passed to
//! EEPROMBlockProtectSet() or returned from EEPROMBlockProtectGet(). It
//! restricts EEPROM access to threads running in supervisor mode and prevents
//! access to an EEPROM block when the CPU is in user mode.
//
#define EEPROM_PROT_SUPERVISOR_ONLY 0x00000008
//
//! This value may be passed to EEPROMBlockProtectSet() or returned from
//! EEPROMBlockProtectGet(). It indicates that the block should offer
//! read/write access when no password is set or when a password is set and
//! the block is unlocked, and read-only access when a password is set but
//! the block is locked.
//
#define EEPROM_PROT_RW_LRO_URW 0x00000000
//
//! This value may be passed to EEPROMBlockProtectSet() or returned from
//! EEPROMBlockProtectGet(). It indicates that the block should offer neither
//! read nor write access unless it is protected by a password and unlocked.
//
#define EEPROM_PROT_NA_LNA_URW 0x00000001
//
//! This value may be passed to EEPROMBlockProtectSet() or returned from
//! EEPROMBlockProtectGet(). It indicates that the block should offer
//! read-only access when no password is set or when a password is set and the
//! block is unlocked. When a password is set and the block is locked, neither
//! read nor write access is permitted.
//
#define EEPROM_PROT_RO_LNA_URO 0x00000002
//*****************************************************************************
//
//! This value may be passed to EEPROMIntEnable() and EEPROMIntDisable() and is
//! returned by EEPROMIntStatus() if an EEPROM interrupt is currently being
//! signaled.
//
//*****************************************************************************
#define EEPROM_INT_PROGRAM 0x00000004
//*****************************************************************************
//
//! Returns the EEPROM block number containing a given offset address.
//!
//! \param ui32Addr is the linear, byte address of the EEPROM location whose
//! block number is to be returned. This is a zero-based offset from the start
//! of the EEPROM storage.
//!
//! This macro may be used to translate an EEPROM address offset into a
//! block number suitable for use in any of the driver's block protection
//! functions. The address provided is expressed as a byte offset from the
//! base of the EEPROM.
//!
//! \return Returns the zero-based block number which contains the passed
//! address.
//
//*****************************************************************************
#define EEPROMBlockFromAddr(ui32Addr) ((ui32Addr) >> 6)
//*****************************************************************************
//
//! Returns the offset address of the first word in an EEPROM block.
//!
//! \param ui32Block is the index of the EEPROM block whose first word address
//! is to be returned.
//!
//! This macro may be used to determine the address of the first word in a
//! given EEPROM block. The address returned is expressed as a byte offset
//! from the base of EEPROM storage.
//!
//! \return Returns the address of the first word in the given EEPROM block.
//
//*****************************************************************************
#define EEPROMAddrFromBlock(ui32Block) ((ui32Block) << 6)
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern uint32_t EEPROMInit(void);
extern uint32_t EEPROMSizeGet(void);
extern uint32_t EEPROMBlockCountGet(void);
extern void EEPROMRead(uint32_t *pui32Data, uint32_t ui32Address,
uint32_t ui32Count);
extern uint32_t EEPROMProgram(uint32_t *pui32Data,
uint32_t ui32Address,
uint32_t ui32Count);
extern uint32_t EEPROMProgramNonBlocking(uint32_t ui32Data,
uint32_t ui32Address);
extern uint32_t EEPROMStatusGet(void);
extern uint32_t EEPROMMassErase(void);
extern uint32_t EEPROMBlockProtectGet(uint32_t ui32Block);
extern uint32_t EEPROMBlockProtectSet(uint32_t ui32Block,
uint32_t ui32Protect);
extern uint32_t EEPROMBlockPasswordSet(uint32_t ui32Block,
uint32_t *pui32Password,
uint32_t ui32Count);
extern uint32_t EEPROMBlockLock(uint32_t ui32Block);
extern uint32_t EEPROMBlockUnlock(uint32_t ui32Block,
uint32_t *pui32Password,
uint32_t ui32Count);
extern void EEPROMBlockHide(uint32_t ui32Block);
extern void EEPROMIntEnable(uint32_t ui32IntFlags);
extern void EEPROMIntDisable(uint32_t ui32IntFlags);
extern uint32_t EEPROMIntStatus(bool bMasked);
extern void EEPROMIntClear(uint32_t ui32IntFlags);
#ifndef DEPRECATED
//*****************************************************************************
//
// The following definitions appeared in previous revisions of this file
// but have been deprecated and should not be used by applications.
//
//*****************************************************************************
//
// This value used to be one of those which could be returned from a call to
// EEPROMInit(). It transpires that it is was incorrect and has been removed
// after EEPROMInit() was reworked for TivaWare 2.1.
//
#define EEPROM_INIT_RETRY 1
//
// This return code is not available from any Tiva part and has been removed.
//
#define EEPROM_RC_INVPL 0x00000100
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_EEPROM_H__

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//*****************************************************************************
//
// epi.h - Prototypes and macros for the EPI module.
//
// Copyright (c) 2008-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __DRIVERLIB_EPI_H__
#define __DRIVERLIB_EPI_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to EPIModeSet()
//
//*****************************************************************************
#define EPI_MODE_GENERAL 0x00000010
#define EPI_MODE_SDRAM 0x00000011
#define EPI_MODE_HB8 0x00000012
#define EPI_MODE_HB16 0x00000013
#define EPI_MODE_DISABLE 0x00000000
//*****************************************************************************
//
// Values that can be passed to EPIConfigSDRAMSet()
//
//*****************************************************************************
#define EPI_SDRAM_CORE_FREQ_0_15 \
0x00000000
#define EPI_SDRAM_CORE_FREQ_15_30 \
0x40000000
#define EPI_SDRAM_CORE_FREQ_30_50 \
0x80000000
#define EPI_SDRAM_CORE_FREQ_50_100 \
0xC0000000
#define EPI_SDRAM_LOW_POWER 0x00000200
#define EPI_SDRAM_FULL_POWER 0x00000000
#define EPI_SDRAM_SIZE_64MBIT 0x00000000
#define EPI_SDRAM_SIZE_128MBIT 0x00000001
#define EPI_SDRAM_SIZE_256MBIT 0x00000002
#define EPI_SDRAM_SIZE_512MBIT 0x00000003
//*****************************************************************************
//
// Values that can be passed to EPIConfigGPModeSet()
//
//*****************************************************************************
#define EPI_GPMODE_CLKPIN 0x80000000
#define EPI_GPMODE_CLKGATE 0x40000000
#define EPI_GPMODE_FRAME50 0x04000000
#define EPI_GPMODE_WRITE2CYCLE 0x00080000
#define EPI_GPMODE_ASIZE_NONE 0x00000000
#define EPI_GPMODE_ASIZE_4 0x00000010
#define EPI_GPMODE_ASIZE_12 0x00000020
#define EPI_GPMODE_ASIZE_20 0x00000030
#define EPI_GPMODE_DSIZE_8 0x00000000
#define EPI_GPMODE_DSIZE_16 0x00000001
#define EPI_GPMODE_DSIZE_24 0x00000002
#define EPI_GPMODE_DSIZE_32 0x00000003
//*****************************************************************************
//
// Values that can be passed to EPIConfigHB8ModeSet()
//
//*****************************************************************************
#define EPI_HB8_USE_TXEMPTY 0x00800000
#define EPI_HB8_USE_RXFULL 0x00400000
#define EPI_HB8_WRHIGH 0x00200000
#define EPI_HB8_RDHIGH 0x00100000
#define EPI_HB8_ALE_HIGH 0x00080000
#define EPI_HB8_ALE_LOW 0x00000000
#define EPI_HB8_WRWAIT_0 0x00000000
#define EPI_HB8_WRWAIT_1 0x00000040
#define EPI_HB8_WRWAIT_2 0x00000080
#define EPI_HB8_WRWAIT_3 0x000000C0
#define EPI_HB8_RDWAIT_0 0x00000000
#define EPI_HB8_RDWAIT_1 0x00000010
#define EPI_HB8_RDWAIT_2 0x00000020
#define EPI_HB8_RDWAIT_3 0x00000030
#define EPI_HB8_MODE_ADMUX 0x00000000
#define EPI_HB8_MODE_ADDEMUX 0x00000001
#define EPI_HB8_MODE_SRAM 0x00000002
#define EPI_HB8_MODE_FIFO 0x00000003
#define EPI_HB8_WORD_ACCESS 0x00000100
#define EPI_HB8_CSCFG_ALE 0x00000000
#define EPI_HB8_CSCFG_CS 0x00000200
#define EPI_HB8_CSCFG_DUAL_CS 0x00000400
#define EPI_HB8_CSCFG_ALE_DUAL_CS \
0x00000600
#define EPI_HB8_CSCFG_ALE_SINGLE_CS \
0x00001000
#define EPI_HB8_CSCFG_QUAD_CS 0x00001200
#define EPI_HB8_CSCFG_ALE_QUAD_CS \
0x00001400
#define EPI_HB8_CSBAUD 0x00000800
#define EPI_HB8_CLOCK_GATE 0x80000000
#define EPI_HB8_CLOCK_GATE_IDLE \
0x40000000
#define EPI_HB8_CLOCK_INVERT 0x20000000
#define EPI_HB8_IN_READY_EN 0x10000000
#define EPI_HB8_IN_READY_EN_INVERT \
0x18000000
#define EPI_HB8_CSCFG_MASK 0x00001600
//*****************************************************************************
//
// Values that can be passed to EPIConfigHB16ModeSet()
//
//*****************************************************************************
#define EPI_HB16_USE_TXEMPTY 0x00800000
#define EPI_HB16_USE_RXFULL 0x00400000
#define EPI_HB16_WRHIGH 0x00200000
#define EPI_HB16_RDHIGH 0x00100000
#define EPI_HB16_WRWAIT_0 0x00000000
#define EPI_HB16_WRWAIT_1 0x00000040
#define EPI_HB16_WRWAIT_2 0x00000080
#define EPI_HB16_WRWAIT_3 0x000000C0
#define EPI_HB16_RDWAIT_0 0x00000000
#define EPI_HB16_RDWAIT_1 0x00000010
#define EPI_HB16_RDWAIT_2 0x00000020
#define EPI_HB16_RDWAIT_3 0x00000030
#define EPI_HB16_MODE_ADMUX 0x00000000
#define EPI_HB16_MODE_ADDEMUX 0x00000001
#define EPI_HB16_MODE_SRAM 0x00000002
#define EPI_HB16_MODE_FIFO 0x00000003
#define EPI_HB16_BSEL 0x00000004
#define EPI_HB16_WORD_ACCESS 0x00000100
#define EPI_HB16_CSCFG_ALE 0x00000000
#define EPI_HB16_CSCFG_CS 0x00000200
#define EPI_HB16_CSCFG_DUAL_CS 0x00000400
#define EPI_HB16_CSCFG_ALE_DUAL_CS \
0x00000600
#define EPI_HB16_CSCFG_ALE_SINGLE_CS \
0x00001000
#define EPI_HB16_CSCFG_QUAD_CS 0x00001200
#define EPI_HB16_CSCFG_ALE_QUAD_CS \
0x00001400
#define EPI_HB16_CLOCK_GATE 0x80000000
#define EPI_HB16_CLOCK_GATE_IDLE \
0x40000000
#define EPI_HB16_CLOCK_INVERT 0x20000000
#define EPI_HB16_IN_READY_EN 0x10000000
#define EPI_HB16_IN_READY_EN_INVERTED \
0x18000000
#define EPI_HB16_ALE_HIGH 0x00080000
#define EPI_HB16_ALE_LOW 0x00000000
#define EPI_HB16_BURST_TRAFFIC 0x00010000
#define EPI_HB16_CSBAUD 0x00000800
#define EPI_HB16_CSCFG_MASK 0x00001600
//*****************************************************************************
//
// Values that can be passed to EPIConfigHB8TimingSet().
//
//*****************************************************************************
#define EPI_HB8_IN_READY_DELAY_1 \
0x01000000
#define EPI_HB8_IN_READY_DELAY_2 \
0x02000000
#define EPI_HB8_IN_READY_DELAY_3 \
0x03000000
#define EPI_HB8_CAP_WIDTH_1 0x00001000
#define EPI_HB8_CAP_WIDTH_2 0x00002000
#define EPI_HB8_WRWAIT_MINUS_DISABLE \
0x00000000
#define EPI_HB8_WRWAIT_MINUS_ENABLE \
0x00000010
#define EPI_HB8_RDWAIT_MINUS_DISABLE \
0x00000000
#define EPI_HB8_RDWAIT_MINUS_ENABLE \
0x00000001
//*****************************************************************************
//
// Values that can be passed to EPIConfigHB16TimingSet().
//
//*****************************************************************************
#define EPI_HB16_IN_READY_DELAY_1 \
0x01000000
#define EPI_HB16_IN_READY_DELAY_2 \
0x02000000
#define EPI_HB16_IN_READY_DELAY_3 \
0x03000000
#define EPI_HB16_PSRAM_NO_LIMIT 0x00000000
#define EPI_HB16_PSRAM_128 0x00010000
#define EPI_HB16_PSRAM_256 0x00020000
#define EPI_HB16_PSRAM_512 0x00030000
#define EPI_HB16_PSRAM_1024 0x00040000
#define EPI_HB16_PSRAM_2048 0x00050000
#define EPI_HB16_PSRAM_4096 0x00060000
#define EPI_HB16_PSRAM_8192 0x00070000
#define EPI_HB16_CAP_WIDTH_1 0x00001000
#define EPI_HB16_CAP_WIDTH_2 0x00002000
#define EPI_HB16_WRWAIT_MINUS_DISABLE \
0x00000000
#define EPI_HB16_WRWAIT_MINUS_ENABLE \
0x00000008
#define EPI_HB16_RDWAIT_MINUS_DISABLE \
0x00000000
#define EPI_HB16_RDWAIT_MINUS_ENABLE \
0x00000001
//*****************************************************************************
//
// Values that can be passed to EPIAddressMapSet().
//
//*****************************************************************************
#define EPI_ADDR_PER_SIZE_256B 0x00000000
#define EPI_ADDR_PER_SIZE_64KB 0x00000040
#define EPI_ADDR_PER_SIZE_16MB 0x00000080
#define EPI_ADDR_PER_SIZE_256MB 0x000000C0
#define EPI_ADDR_PER_BASE_NONE 0x00000000
#define EPI_ADDR_PER_BASE_A 0x00000010
#define EPI_ADDR_PER_BASE_C 0x00000020
#define EPI_ADDR_RAM_SIZE_256B 0x00000000
#define EPI_ADDR_RAM_SIZE_64KB 0x00000004
#define EPI_ADDR_RAM_SIZE_16MB 0x00000008
#define EPI_ADDR_RAM_SIZE_256MB 0x0000000C
#define EPI_ADDR_RAM_BASE_NONE 0x00000000
#define EPI_ADDR_RAM_BASE_6 0x00000001
#define EPI_ADDR_RAM_BASE_8 0x00000002
#define EPI_ADDR_QUAD_MODE 0x00000033
#define EPI_ADDR_CODE_SIZE_256B 0x00000000
#define EPI_ADDR_CODE_SIZE_64KB 0x00000400
#define EPI_ADDR_CODE_SIZE_16MB 0x00000800
#define EPI_ADDR_CODE_SIZE_256MB \
0x00000C00
#define EPI_ADDR_CODE_BASE_NONE 0x00000000
#define EPI_ADDR_CODE_BASE_1 0x00000100
//*****************************************************************************
//
// Values that can be passed to EPINonBlockingReadConfigure()
//
//*****************************************************************************
#define EPI_NBCONFIG_SIZE_8 1
#define EPI_NBCONFIG_SIZE_16 2
#define EPI_NBCONFIG_SIZE_32 3
//*****************************************************************************
//
// Values that can be passed to EPIFIFOConfig()
//
//*****************************************************************************
#define EPI_FIFO_CONFIG_WTFULLERR \
0x00020000
#define EPI_FIFO_CONFIG_RSTALLERR \
0x00010000
#define EPI_FIFO_CONFIG_TX_EMPTY \
0x00000000
#define EPI_FIFO_CONFIG_TX_1_4 0x00000020
#define EPI_FIFO_CONFIG_TX_1_2 0x00000030
#define EPI_FIFO_CONFIG_TX_3_4 0x00000040
#define EPI_FIFO_CONFIG_RX_1_8 0x00000001
#define EPI_FIFO_CONFIG_RX_1_4 0x00000002
#define EPI_FIFO_CONFIG_RX_1_2 0x00000003
#define EPI_FIFO_CONFIG_RX_3_4 0x00000004
#define EPI_FIFO_CONFIG_RX_7_8 0x00000005
#define EPI_FIFO_CONFIG_RX_FULL 0x00000006
//*****************************************************************************
//
// Values that can be passed to EPIIntEnable(), EPIIntDisable(), or returned
// as flags from EPIIntStatus()
//
//*****************************************************************************
#define EPI_INT_DMA_TX_DONE 0x00000010
#define EPI_INT_DMA_RX_DONE 0x00000008
#define EPI_INT_TXREQ 0x00000004
#define EPI_INT_RXREQ 0x00000002
#define EPI_INT_ERR 0x00000001
//*****************************************************************************
//
// Values that can be passed to EPIIntErrorClear(), or returned as flags from
// EPIIntErrorStatus()
//
//*****************************************************************************
#define EPI_INT_ERR_DMAWRIC 0x00000010
#define EPI_INT_ERR_DMARDIC 0x00000008
#define EPI_INT_ERR_WTFULL 0x00000004
#define EPI_INT_ERR_RSTALL 0x00000002
#define EPI_INT_ERR_TIMEOUT 0x00000001
#ifdef rvmdk
//*****************************************************************************
//
// Keil case.
//
//*****************************************************************************
inline void
EPIWorkaroundWordWrite(uint32_t *pui32Addr, uint32_t ui32Value)
{
uint32_t ui32Scratch;
__asm
{
//
// Add a NOP to ensure we don’t have a flash read immediately before
// the EPI read.
//
NOP
//
// Perform the write we're actually interested in.
//
STR ui32Value, [pui32Addr]
//
// Read from SRAM to ensure that we don't have an EPI write followed by
// a flash read.
//
LDR ui32Scratch, [__current_sp()]
}
}
inline uint32_t
EPIWorkaroundWordRead(uint32_t *pui32Addr)
{
uint32_t ui32Value, ui32Scratch;
__asm
{
//
// Add a NOP to ensure we don’t have a flash read immediately before
// the EPI read.
//
NOP
//
// Perform the read we're actually interested in.
//
LDR ui32Value, [pui32Addr]
//
// Read from SRAM to ensure that we don't have an EPI read followed by
// a flash read.
//
LDR ui32Scratch, [__current_sp()]
}
return(ui32Value);
}
inline void
EPIWorkaroundHWordWrite(uint16_t *pui16Addr, uint16_t ui16Value)
{
uint32_t ui32Scratch;
__asm
{
//
// Add a NOP to ensure we don’t have a flash read immediately before
// the EPI read.
//
NOP
//
// Perform the write we're actually interested in.
//
STRH ui16Value, [pui16Addr]
//
// Read from SRAM to ensure that we don't have an EPI write followed by
// a flash read.
//
LDR ui32Scratch, [__current_sp()]
}
}
inline uint16_t
EPIWorkaroundHWordRead(uint16_t *pui16Addr)
{
uint32_t ui32Scratch;
uint16_t ui16Value;
__asm
{
//
// Add a NOP to ensure we don’t have a flash read immediately before
// the EPI read.
//
NOP
//
// Perform the read we're actually interested in.
//
LDRH ui16Value, [pui16Addr]
//
// Read from SRAM to ensure that we don't have an EPI read followed by
// a flash read.
//
LDR ui32Scratch, [__current_sp()]
}
return(ui16Value);
}
inline void
EPIWorkaroundByteWrite(uint8_t *pui8Addr, uint8_t ui8Value)
{
uint32_t ui32Scratch;
__asm
{
//
// Add a NOP to ensure we don’t have a flash read immediately before
// the EPI read.
//
NOP
//
// Perform the write we're actually interested in.
//
STRB ui8Value, [pui8Addr]
//
// Read from SRAM to ensure that we don't have an EPI write followed by
// a flash read.
//
LDR ui32Scratch, [__current_sp()]
}
}
inline uint8_t
EPIWorkaroundByteRead(uint8_t *pui8Addr)
{
uint32_t ui32Scratch;
uint8_t ui8Value;
__asm
{
//
// Add a NOP to ensure we don’t have a flash read immediately before
// the EPI read.
//
NOP
//
// Perform the read we're actually interested in.
//
LDRB ui8Value, [pui8Addr]
//
// Read from SRAM to ensure that we don't have an EPI read followed by
// a flash read.
//
LDR ui32Scratch, [__current_sp()]
}
return(ui8Value);
}
#endif
#ifdef ccs
//*****************************************************************************
//
// Code Composer Studio versions of these functions can be found in separate
// source file epi_workaround_ccs.s.
//
//*****************************************************************************
extern void EPIWorkaroundWordWrite(uint32_t *pui32Addr, uint32_t ui32Value);
extern uint32_t EPIWorkaroundWordRead(uint32_t *pui32Addr);
extern void EPIWorkaroundHWordWrite(uint16_t *pui16Addr, uint16_t ui16Value);
extern uint16_t EPIWorkaroundHWordRead(uint16_t *pui16Addr);
extern void EPIWorkaroundByteWrite(uint8_t *pui8Addr, uint8_t ui8Value);
extern uint8_t EPIWorkaroundByteRead(uint8_t *pui8Addr);
#endif
#if (defined gcc) || (defined ewarm) || (defined sourcerygxx) || \
(defined codered)
//*****************************************************************************
//
// GCC-based toolchain and IAR case.
//
//*****************************************************************************
inline void
EPIWorkaroundWordWrite(uint32_t *pui32Addr, uint32_t ui32Value)
{
volatile register uint32_t ui32Scratch;
__asm volatile (
//
// Add a NOP to ensure we don’t have a flash read immediately before
// the EPI read.
//
" NOP\n"
" STR %[value],[%[addr]]\n"
" LDR %[scratch],[sp]\n"
: [scratch] "=r" (ui32Scratch)
: [addr] "r" (pui32Addr), [value] "r" (ui32Value)
);
//
// Keep the compiler from generating a warning.
//
ui32Scratch = ui32Scratch;
}
inline uint32_t
EPIWorkaroundWordRead(uint32_t *pui32Addr)
{
volatile register uint32_t ui32Data, ui32Scratch;
//
// ui32Scratch is not used other than to add a padding read following the
// "real" read.
//
__asm volatile(
//
// Add a NOP to ensure we don’t have a flash read immediately before
// the EPI read.
//
" NOP\n"
" LDR %[ret],[%[addr]]\n"
" LDR %[scratch],[sp]\n"
: [ret] "=r" (ui32Data),
[scratch] "=r" (ui32Scratch)
: [addr] "r" (pui32Addr)
);
//
// Keep the compiler from generating a warning.
//
ui32Scratch = ui32Scratch;
return(ui32Data);
}
inline void
EPIWorkaroundHWordWrite(uint16_t *pui16Addr, uint16_t ui16Value)
{
volatile register uint32_t ui32Scratch;
__asm volatile (
//
// Add a NOP to ensure we don’t have a flash read immediately before
// the EPI read.
//
" NOP\n"
" STRH %[value],[%[addr]]\n"
" LDR %[scratch],[sp]\n"
: [scratch] "=r" (ui32Scratch)
: [addr] "r" (pui16Addr), [value] "r" (ui16Value)
);
//
// Keep the compiler from generating a warning.
//
ui32Scratch = ui32Scratch;
}
inline uint16_t
EPIWorkaroundHWordRead(uint16_t *pui16Addr)
{
register uint16_t ui16Data;
register uint32_t ui32Scratch;
//
// ui32Scratch is not used other than to add a padding read following the
// "real" read.
//
__asm volatile(
//
// Add a NOP to ensure we don’t have a flash read immediately before
// the EPI read.
//
" NOP\n"
" LDRH %[ret],[%[addr]]\n"
" LDR %[scratch],[sp]\n"
: [ret] "=r" (ui16Data),
[scratch] "=r" (ui32Scratch)
: [addr] "r" (pui16Addr)
);
//
// Keep the compiler from generating a warning.
//
ui32Scratch = ui32Scratch;
return(ui16Data);
}
inline void
EPIWorkaroundByteWrite(uint8_t *pui8Addr, uint8_t ui8Value)
{
volatile register uint32_t ui32Scratch;
__asm volatile (
//
// Add a NOP to ensure we don’t have a flash read immediately before
// the EPI read.
//
" NOP\n"
" STRB %[value],[%[addr]]\n"
" LDR %[scratch],[sp]\n"
: [scratch] "=r" (ui32Scratch)
: [addr] "r" (pui8Addr), [value] "r" (ui8Value)
);
//
// Keep the compiler from generating a warning.
//
ui32Scratch = ui32Scratch;
}
inline uint8_t
EPIWorkaroundByteRead(uint8_t *pui8Addr)
{
register uint8_t ui8Data;
register uint32_t ui32Scratch;
//
// ui32Scratch is not used other than to add a padding read following the
// "real" read.
//
__asm volatile(
//
// Add a NOP to ensure we don’t have a flash read immediately before
// the EPI read.
//
" NOP\n"
" LDRB %[ret],[%[addr]]\n"
" LDR %[scratch],[sp]\n"
: [ret] "=r" (ui8Data),
[scratch] "=r" (ui32Scratch)
: [addr] "r" (pui8Addr)
);
//
// Keep the compiler from generating a warning.
//
ui32Scratch = ui32Scratch;
return(ui8Data);
}
#endif
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void EPIModeSet(uint32_t ui32Base, uint32_t ui32Mode);
extern void EPIDividerSet(uint32_t ui32Base, uint32_t ui32Divider);
extern void EPIDividerCSSet(uint32_t ui32Base, uint32_t ui32CS,
uint32_t ui32Divider);
extern void EPIDMATxCount(uint32_t ui32Base, uint32_t ui32Count);
extern void EPIConfigGPModeSet(uint32_t ui32Base, uint32_t ui32Config,
uint32_t ui32FrameCount, uint32_t ui32MaxWait);
extern void EPIConfigHB8Set(uint32_t ui32Base, uint32_t ui32Config,
uint32_t ui32MaxWait);
extern void EPIConfigHB16Set(uint32_t ui32Base, uint32_t ui32Config,
uint32_t ui32MaxWait);
extern void EPIConfigHB8CSSet(uint32_t ui32Base, uint32_t ui32CS,
uint32_t ui32Config);
extern void EPIConfigHB16CSSet(uint32_t ui32Base, uint32_t ui32CS,
uint32_t ui32Config);
extern void EPIConfigHB8TimingSet(uint32_t ui32Base, uint32_t ui32CS,
uint32_t ui32Config);
extern void EPIConfigHB16TimingSet(uint32_t ui32Base, uint32_t ui32CS,
uint32_t ui32Config);
extern void EPIPSRAMConfigRegSet(uint32_t ui32Base, uint32_t ui32CS,
uint32_t ui32CR);
extern void EPIPSRAMConfigRegRead(uint32_t ui32Base, uint32_t ui32CS);
extern bool EPIPSRAMConfigRegGetNonBlocking(uint32_t ui32Base,
uint32_t ui32CS,
uint32_t *pui32CR);
extern uint32_t EPIPSRAMConfigRegGet(uint32_t ui32Base, uint32_t ui32CS);
extern void EPIConfigSDRAMSet(uint32_t ui32Base, uint32_t ui32Config,
uint32_t ui32Refresh);
extern void EPIAddressMapSet(uint32_t ui32Base, uint32_t ui32Map);
extern void EPINonBlockingReadConfigure(uint32_t ui32Base,
uint32_t ui32Channel,
uint32_t ui32DataSize,
uint32_t ui32Address);
extern void EPINonBlockingReadStart(uint32_t ui32Base,
uint32_t ui32Channel,
uint32_t ui32Count);
extern void EPINonBlockingReadStop(uint32_t ui32Base,
uint32_t ui32Channel);
extern uint32_t EPINonBlockingReadCount(uint32_t ui32Base,
uint32_t ui32Channel);
extern uint32_t EPINonBlockingReadAvail(uint32_t ui32Base);
extern uint32_t EPINonBlockingReadGet32(uint32_t ui32Base,
uint32_t ui32Count,
uint32_t *pui32Buf);
extern uint32_t EPINonBlockingReadGet16(uint32_t ui32Base,
uint32_t ui32Count,
uint16_t *pui16Buf);
extern uint32_t EPINonBlockingReadGet8(uint32_t ui32Base,
uint32_t ui32Count,
uint8_t *pui8Buf);
extern void EPIFIFOConfig(uint32_t ui32Base, uint32_t ui32Config);
extern uint32_t EPIWriteFIFOCountGet(uint32_t ui32Base);
extern void EPIIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void EPIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
extern uint32_t EPIIntStatus(uint32_t ui32Base, bool bMasked);
extern uint32_t EPIIntErrorStatus(uint32_t ui32Base);
extern void EPIIntErrorClear(uint32_t ui32Base, uint32_t ui32ErrFlags);
extern void EPIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void));
extern void EPIIntUnregister(uint32_t ui32Base);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_EPI_H__

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//*****************************************************************************
//
// flash.h - Prototypes for the flash driver.
//
// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __DRIVERLIB_FLASH_H__
#define __DRIVERLIB_FLASH_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to FlashProtectSet(), and returned by
// FlashProtectGet().
//
//*****************************************************************************
typedef enum
{
FlashReadWrite, // Flash can be read and written
FlashReadOnly, // Flash can only be read
FlashExecuteOnly // Flash can only be executed
}
tFlashProtection;
//*****************************************************************************
//
// Values passed to FlashIntEnable(), FlashIntDisable() and FlashIntClear() and
// returned from FlashIntStatus().
//
//*****************************************************************************
#define FLASH_INT_PROGRAM 0x00000002 // Programming Interrupt Mask
#define FLASH_INT_ACCESS 0x00000001 // Access Interrupt Mask
#define FLASH_INT_EEPROM 0x00000004 // EEPROM Interrupt Mask
#define FLASH_INT_VOLTAGE_ERR 0x00000200 // Voltage Error Interrupt Mask
#define FLASH_INT_DATA_ERR 0x00000400 // Invalid Data Interrupt Mask
#define FLASH_INT_ERASE_ERR 0x00000800 // Erase Error Interrupt Mask
#define FLASH_INT_PROGRAM_ERR 0x00002000 // Program Verify Error Interrupt Mask
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern int32_t FlashErase(uint32_t ui32Address);
extern int32_t FlashProgram(uint32_t *pui32Data, uint32_t ui32Address,
uint32_t ui32Count);
extern tFlashProtection FlashProtectGet(uint32_t ui32Address);
extern int32_t FlashProtectSet(uint32_t ui32Address,
tFlashProtection eProtect);
extern int32_t FlashProtectSave(void);
extern int32_t FlashUserGet(uint32_t *pui32User0, uint32_t *pui32User1);
extern int32_t FlashUserSet(uint32_t ui32User0, uint32_t ui32User1);
extern int32_t FlashAllUserRegisterGet(uint32_t *pui32User0,
uint32_t *pui32User1,
uint32_t *pui32User2,
uint32_t *pui32User3);
extern int32_t FlashAllUserRegisterSet(uint32_t ui32User0,
uint32_t ui32User1,
uint32_t ui32User2,
uint32_t ui32User3);
extern int32_t FlashUserSave(void);
extern int32_t FlashAllUserRegisterSave(void);
extern void FlashIntRegister(void (*pfnHandler)(void));
extern void FlashIntUnregister(void);
extern void FlashIntEnable(uint32_t ui32IntFlags);
extern void FlashIntDisable(uint32_t ui32IntFlags);
extern uint32_t FlashIntStatus(bool bMasked);
extern void FlashIntClear(uint32_t ui32IntFlags);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_FLASH_H__

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//*****************************************************************************
//
// fpu.h - Prototypes for the floatint point manipulation routines.
//
// Copyright (c) 2011-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __DRIVERLIB_FPU_H__
#define __DRIVERLIB_FPU_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to FPUHalfPrecisionSet as the ui32Mode parameter.
//
//*****************************************************************************
#define FPU_HALF_IEEE 0x00000000
#define FPU_HALF_ALTERNATE 0x04000000
//*****************************************************************************
//
// Values that can be passed to FPUNaNModeSet as the ui32Mode parameter.
//
//*****************************************************************************
#define FPU_NAN_PROPAGATE 0x00000000
#define FPU_NAN_DEFAULT 0x02000000
//*****************************************************************************
//
// Values that can be passed to FPUFlushToZeroModeSet as the ui32Mode
// parameter.
//
//*****************************************************************************
#define FPU_FLUSH_TO_ZERO_DIS 0x00000000
#define FPU_FLUSH_TO_ZERO_EN 0x01000000
//*****************************************************************************
//
// Values that can be passed to FPURoundingModeSet as the ui32Mode parameter.
//
//*****************************************************************************
#define FPU_ROUND_NEAREST 0x00000000
#define FPU_ROUND_POS_INF 0x00400000
#define FPU_ROUND_NEG_INF 0x00800000
#define FPU_ROUND_ZERO 0x00c00000
//*****************************************************************************
//
// Prototypes.
//
//*****************************************************************************
extern void FPUEnable(void);
extern void FPUDisable(void);
extern void FPUStackingEnable(void);
extern void FPULazyStackingEnable(void);
extern void FPUStackingDisable(void);
extern void FPUHalfPrecisionModeSet(uint32_t ui32Mode);
extern void FPUNaNModeSet(uint32_t ui32Mode);
extern void FPUFlushToZeroModeSet(uint32_t ui32Mode);
extern void FPURoundingModeSet(uint32_t ui32Mode);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_FPU_H__

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//*****************************************************************************
//
// gpio.h - Defines and Macros for GPIO API.
//
// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __DRIVERLIB_GPIO_H__
#define __DRIVERLIB_GPIO_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following values define the bit field for the ui8Pins argument to
// several of the APIs.
//
//*****************************************************************************
#define GPIO_PIN_0 0x00000001 // GPIO pin 0
#define GPIO_PIN_1 0x00000002 // GPIO pin 1
#define GPIO_PIN_2 0x00000004 // GPIO pin 2
#define GPIO_PIN_3 0x00000008 // GPIO pin 3
#define GPIO_PIN_4 0x00000010 // GPIO pin 4
#define GPIO_PIN_5 0x00000020 // GPIO pin 5
#define GPIO_PIN_6 0x00000040 // GPIO pin 6
#define GPIO_PIN_7 0x00000080 // GPIO pin 7
//*****************************************************************************
//
// Values that can be passed to GPIODirModeSet as the ui32PinIO parameter, and
// returned from GPIODirModeGet.
//
//*****************************************************************************
#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input
#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output
#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function
//*****************************************************************************
//
// Values that can be passed to GPIOIntTypeSet as the ui32IntType parameter,
// and returned from GPIOIntTypeGet.
//
//*****************************************************************************
#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge
#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge
#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges
#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level
#define GPIO_HIGH_LEVEL 0x00000006 // Interrupt on high level
#define GPIO_DISCRETE_INT 0x00010000 // Interrupt for individual pins
//*****************************************************************************
//
// Values that can be passed to GPIOPadConfigSet as the ui32Strength parameter,
// and returned by GPIOPadConfigGet in the *pui32Strength parameter.
//
//*****************************************************************************
#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength
#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength
#define GPIO_STRENGTH_6MA 0x00000065 // 6mA drive strength
#define GPIO_STRENGTH_8MA 0x00000066 // 8mA drive strength
#define GPIO_STRENGTH_8MA_SC 0x0000006E // 8mA drive with slew rate control
#define GPIO_STRENGTH_10MA 0x00000075 // 10mA drive strength
#define GPIO_STRENGTH_12MA 0x00000077 // 12mA drive strength
//*****************************************************************************
//
// Values that can be passed to GPIOPadConfigSet as the ui32PadType parameter,
// and returned by GPIOPadConfigGet in the *pui32PadType parameter.
//
//*****************************************************************************
#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull
#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up
#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down
#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain
#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator
#define GPIO_PIN_TYPE_WAKE_HIGH 0x00000208 // Hibernate wake, high
#define GPIO_PIN_TYPE_WAKE_LOW 0x00000108 // Hibernate wake, low
//*****************************************************************************
//
// Values that can be passed to GPIOIntEnable() and GPIOIntDisable() functions
// in the ui32IntFlags parameter.
//
//*****************************************************************************
#define GPIO_INT_PIN_0 0x00000001
#define GPIO_INT_PIN_1 0x00000002
#define GPIO_INT_PIN_2 0x00000004
#define GPIO_INT_PIN_3 0x00000008
#define GPIO_INT_PIN_4 0x00000010
#define GPIO_INT_PIN_5 0x00000020
#define GPIO_INT_PIN_6 0x00000040
#define GPIO_INT_PIN_7 0x00000080
#define GPIO_INT_DMA 0x00000100
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void GPIODirModeSet(uint32_t ui32Port, uint8_t ui8Pins,
uint32_t ui32PinIO);
extern uint32_t GPIODirModeGet(uint32_t ui32Port, uint8_t ui8Pin);
extern void GPIOIntTypeSet(uint32_t ui32Port, uint8_t ui8Pins,
uint32_t ui32IntType);
extern uint32_t GPIOIntTypeGet(uint32_t ui32Port, uint8_t ui8Pin);
extern void GPIOPadConfigSet(uint32_t ui32Port, uint8_t ui8Pins,
uint32_t ui32Strength, uint32_t ui32PadType);
extern void GPIOPadConfigGet(uint32_t ui32Port, uint8_t ui8Pin,
uint32_t *pui32Strength, uint32_t *pui32PadType);
extern void GPIOIntEnable(uint32_t ui32Port, uint32_t ui32IntFlags);
extern void GPIOIntDisable(uint32_t ui32Port, uint32_t ui32IntFlags);
extern uint32_t GPIOIntStatus(uint32_t ui32Port, bool bMasked);
extern void GPIOIntClear(uint32_t ui32Port, uint32_t ui32IntFlags);
extern void GPIOIntRegister(uint32_t ui32Port, void (*pfnIntHandler)(void));
extern void GPIOIntUnregister(uint32_t ui32Port);
extern void GPIOIntRegisterPin(uint32_t ui32Port, uint32_t ui32Pin,
void (*pfnIntHandler)(void));
extern void GPIOIntUnregisterPin(uint32_t ui32Port, uint32_t ui32Pin);
extern int32_t GPIOPinRead(uint32_t ui32Port, uint8_t ui8Pins);
extern void GPIOPinWrite(uint32_t ui32Port, uint8_t ui8Pins, uint8_t ui8Val);
extern void GPIOPinConfigure(uint32_t ui32PinConfig);
extern void GPIOPinTypeADC(uint32_t ui32Port, uint8_t ui8Pins);
extern void GPIOPinTypeCAN(uint32_t ui32Port, uint8_t ui8Pins);
extern void GPIOPinTypeComparator(uint32_t ui32Port, uint8_t ui8Pins);
extern void GPIOPinTypeComparatorOutput(uint32_t ui32Port, uint8_t ui8Pins);
extern void GPIOPinTypeDIVSCLK(uint32_t ui32Port, uint8_t ui8Pins);
extern void GPIOPinTypeEPI(uint32_t ui32Port, uint8_t ui8Pins);
extern void GPIOPinTypeEthernetLED(uint32_t ui32Port, uint8_t ui8Pins);
extern void GPIOPinTypeEthernetMII(uint32_t ui32Port, uint8_t ui8Pins);
extern void GPIOPinTypeGPIOInput(uint32_t ui32Port, uint8_t ui8Pins);
extern void GPIOPinTypeGPIOOutput(uint32_t ui32Port, uint8_t ui8Pins);
extern void GPIOPinTypeGPIOOutputOD(uint32_t ui32Port, uint8_t ui8Pins);
extern void GPIOPinTypeHibernateRTCCLK(uint32_t ui32Port, uint8_t ui8Pins);
extern void GPIOPinTypeI2C(uint32_t ui32Port, uint8_t ui8Pins);
extern void GPIOPinTypeI2CSCL(uint32_t ui32Port, uint8_t ui8Pins);
extern void GPIOPinTypeLCD(uint32_t ui32Port, uint8_t ui8Pins);
extern void GPIOPinTypeOneWire(uint32_t ui32Port, uint8_t ui8Pins);
extern void GPIOPinTypePWM(uint32_t ui32Port, uint8_t ui8Pins);
extern void GPIOPinTypeQEI(uint32_t ui32Port, uint8_t ui8Pins);
extern void GPIOPinTypeSSI(uint32_t ui32Port, uint8_t ui8Pins);
extern void GPIOPinTypeTimer(uint32_t ui32Port, uint8_t ui8Pins);
extern void GPIOPinTypeTrace(uint32_t ui32Port, uint8_t ui8Pins);
extern void GPIOPinTypeUART(uint32_t ui32Port, uint8_t ui8Pins);
extern void GPIOPinTypeUSBAnalog(uint32_t ui32Port, uint8_t ui8Pins);
extern void GPIOPinTypeUSBDigital(uint32_t ui32Port, uint8_t ui8Pins);
extern void GPIOPinTypeWakeHigh(uint32_t ui32Port, uint8_t ui8Pins);
extern void GPIOPinTypeWakeLow(uint32_t ui32Port, uint8_t ui8Pins);
extern uint32_t GPIOPinWakeStatus(uint32_t ui32Port);
extern void GPIODMATriggerEnable(uint32_t ui32Port, uint8_t ui8Pins);
extern void GPIODMATriggerDisable(uint32_t ui32Port, uint8_t ui8Pins);
extern void GPIOADCTriggerEnable(uint32_t ui32Port, uint8_t ui8Pins);
extern void GPIOADCTriggerDisable(uint32_t ui32Port, uint8_t ui8Pins);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_GPIO_H__

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//*****************************************************************************
//
// hibernate.h - API definition for the Hibernation module.
//
// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __DRIVERLIB_HIBERNATE_H__
#define __DRIVERLIB_HIBERNATE_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Macros need to configure wake events for HibernateWakeSet()
//
//*****************************************************************************
#define HIBERNATE_WAKE_PIN 0x00000010
#define HIBERNATE_WAKE_RTC 0x00000008
#define HIBERNATE_WAKE_LOW_BAT 0x00000200
#define HIBERNATE_WAKE_GPIO 0x00000010
#define HIBERNATE_WAKE_RESET 0x00100010
#define HIBERNATE_WAKE_TAMPER 0x08000010
//*****************************************************************************
//
// Macros needed to configure low battery detect for HibernateLowBatSet()
//
//*****************************************************************************
#define HIBERNATE_LOW_BAT_DETECT \
0x00000020
#define HIBERNATE_LOW_BAT_ABORT 0x000000A0
#define HIBERNATE_LOW_BAT_1_9V 0x00000000
#define HIBERNATE_LOW_BAT_2_1V 0x00002000
#define HIBERNATE_LOW_BAT_2_3V 0x00004000
#define HIBERNATE_LOW_BAT_2_5V 0x00006000
//*****************************************************************************
//
// Macros defining interrupt source bits for the interrupt functions.
//
//*****************************************************************************
#define HIBERNATE_INT_VDDFAIL 0x00000080
#define HIBERNATE_INT_RESET_WAKE \
0x00000040
#define HIBERNATE_INT_GPIO_WAKE 0x00000020
#define HIBERNATE_INT_WR_COMPLETE \
0x00000010
#define HIBERNATE_INT_PIN_WAKE 0x00000008
#define HIBERNATE_INT_LOW_BAT 0x00000004
#define HIBERNATE_INT_RTC_MATCH_0 \
0x00000001
//*****************************************************************************
//
// Macros defining oscillator configuration options for the
// HibernateClockConfig() function.
//
//*****************************************************************************
#define HIBERNATE_OSC_LFIOSC 0x00080000
#define HIBERNATE_OSC_LOWDRIVE 0x00000000
#define HIBERNATE_OSC_HIGHDRIVE 0x00020000
#define HIBERNATE_OSC_DISABLE 0x00010000
#define HIBERNATE_OUT_WRSTALL 0x20000000
#define HIBERNATE_OUT_SYSCLK 0x00000001
#define HIBERNATE_OUT_ALT1CLK 0x00000002
//*****************************************************************************
//
// The following defines are used with the HibernateCounterMode() API.
//
//*****************************************************************************
#define HIBERNATE_COUNTER_RTC 0x00000000
#define HIBERNATE_COUNTER_12HR 0x00000001
#define HIBERNATE_COUNTER_24HR 0x00000005
//*****************************************************************************
//
// Tamper event configuration options used with HibernateTamperEventsConfig().
//
//*****************************************************************************
#define HIBERNATE_TAMPER_EVENTS_NO_HIB_WAKE \
0x00000000
#define HIBERNATE_TAMPER_EVENTS_HIB_WAKE \
0x00000800
#define HIBERNATE_TAMPER_EVENTS_NO_ERASE_HIB_MEM \
0x00000000
#define HIBERNATE_TAMPER_EVENTS_ERASE_LOW_HIB_MEM \
0x00000100
#define HIBERNATE_TAMPER_EVENTS_ERASE_HIGH_HIB_MEM \
0x00000200
#define HIBERNATE_TAMPER_EVENTS_ERASE_ALL_HIB_MEM \
0x00000300
//*****************************************************************************
//
// Status flags returned by the HibernateTamperStatus() function.
//
//*****************************************************************************
#define HIBERNATE_TAMPER_STATUS_INACTIVE \
0x00000010
#define HIBERNATE_TAMPER_STATUS_ACTIVE \
0x00000020
#define HIBERNATE_TAMPER_STATUS_EVENT \
0x00000040
#define HIBERNATE_TAMPER_STATUS_EXT_OSC_ACTIVE \
0x00000008
#define HIBERNATE_TAMPER_STATUS_EXT_OSC_INACTIVE \
0x00000002
#define HIBERNATE_TAMPER_STATUS_EXT_OSC_VALID \
0x00000004
#define HIBERNATE_TAMPER_STATUS_EXT_OSC_FAILED \
0x00000001
//*****************************************************************************
//
// Configuration options used with HibernateTamperIOEnable().
//
//*****************************************************************************
#define HIBERNATE_TAMPER_IO_TRIGGER_LOW \
0x00000000
#define HIBERNATE_TAMPER_IO_TRIGGER_HIGH \
0x00000002
#define HIBERNATE_TAMPER_IO_WPU_DISABLED \
0x00000000
#define HIBERNATE_TAMPER_IO_WPU_ENABLED \
0x00000004
#define HIBERNATE_TAMPER_IO_MATCH_SHORT \
0x00000000
#define HIBERNATE_TAMPER_IO_MATCH_LONG \
0x00000008
//*****************************************************************************
//
// Tamper log event flags.
//
//*****************************************************************************
#define HIBERNATE_TAMPER_EVENT_0 \
0x00000001
#define HIBERNATE_TAMPER_EVENT_1 \
0x00000002
#define HIBERNATE_TAMPER_EVENT_2 \
0x00000004
#define HIBERNATE_TAMPER_EVENT_3 \
0x00000008
#define HIBERNATE_TAMPER_EVENT_EXT_OSC \
0x00010000
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void HibernateGPIORetentionEnable(void);
extern void HibernateGPIORetentionDisable(void);
extern bool HibernateGPIORetentionGet(void);
extern void HibernateEnableExpClk(uint32_t ui32HibClk);
extern void HibernateDisable(void);
extern void HibernateRTCEnable(void);
extern void HibernateRTCDisable(void);
extern void HibernateWakeSet(uint32_t ui32WakeFlags);
extern uint32_t HibernateWakeGet(void);
extern void HibernateLowBatSet(uint32_t ui32LowBatFlags);
extern uint32_t HibernateLowBatGet(void);
extern void HibernateRTCSet(uint32_t ui32RTCValue);
extern uint32_t HibernateRTCGet(void);
extern void HibernateRTCMatchSet(uint32_t ui32Match, uint32_t ui32Value);
extern uint32_t HibernateRTCMatchGet(uint32_t ui32Match);
extern void HibernateRTCTrimSet(uint32_t ui32Trim);
extern uint32_t HibernateRTCTrimGet(void);
extern void HibernateDataSet(uint32_t *pui32Data, uint32_t ui32Count);
extern void HibernateDataGet(uint32_t *pui32Data, uint32_t ui32Count);
extern void HibernateRequest(void);
extern void HibernateIntEnable(uint32_t ui32IntFlags);
extern void HibernateIntDisable(uint32_t ui32IntFlags);
extern void HibernateIntRegister(void (*pfnHandler)(void));
extern void HibernateIntUnregister(void);
extern uint32_t HibernateIntStatus(bool bMasked);
extern void HibernateIntClear(uint32_t ui32IntFlags);
extern uint32_t HibernateIsActive(void);
extern void HibernateRTCSSMatchSet(uint32_t ui32Match, uint32_t ui32Value);
extern uint32_t HibernateRTCSSMatchGet(uint32_t ui32Match);
extern uint32_t HibernateRTCSSGet(void);
extern void HibernateClockConfig(uint32_t ui32Config);
extern void HibernateBatCheckStart(void);
extern uint32_t HibernateBatCheckDone(void);
extern void HibernateCounterMode(uint32_t ui32Config);
extern void HibernateCalendarSet(struct tm *psTime);
extern int HibernateCalendarGet(struct tm *psTime);
extern void HibernateCalendarMatchSet(uint32_t ui32Index, struct tm *psTime);
extern void HibernateCalendarMatchGet(uint32_t ui32Index, struct tm *psTime);
extern void HibernateTamperEnable(void);
extern void HibernateTamperEventsConfig(uint32_t ui32Config);
extern bool HibernateTamperEventsGet(uint32_t ui32Index, uint32_t *pui32RTC,
uint32_t *pui32Event);
extern void HibernateTamperEventsClear(void);
extern void HibernateTamperEventsClearNoLock(void);
extern void HibernateTamperUnLock(void);
extern void HibernateTamperLock(void);
extern void HibernateTamperDisable(void);
extern void HibernateTamperIOEnable(uint32_t ui32Input, uint32_t ui32Config);
extern void HibernateTamperIODisable(uint32_t ui32Input);
extern uint32_t HibernateTamperStatusGet(void);
extern void HibernateTamperExtOscRecover(void);
extern bool HibernateTamperExtOscValid(void);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_HIBERNATE_H__

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//*****************************************************************************
//
// i2c.h - Prototypes for the I2C Driver.
//
// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __DRIVERLIB_I2C_H__
#define __DRIVERLIB_I2C_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Defines for the API.
//
//*****************************************************************************
//*****************************************************************************
//
// Interrupt defines.
//
//*****************************************************************************
#define I2C_INT_MASTER 0x00000001
#define I2C_INT_SLAVE 0x00000002
//*****************************************************************************
//
// I2C Master commands.
//
//*****************************************************************************
#define I2C_MASTER_CMD_SINGLE_SEND \
0x00000007
#define I2C_MASTER_CMD_SINGLE_RECEIVE \
0x00000007
#define I2C_MASTER_CMD_BURST_SEND_START \
0x00000003
#define I2C_MASTER_CMD_BURST_SEND_CONT \
0x00000001
#define I2C_MASTER_CMD_BURST_SEND_FINISH \
0x00000005
#define I2C_MASTER_CMD_BURST_SEND_STOP \
0x00000004
#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \
0x00000004
#define I2C_MASTER_CMD_BURST_RECEIVE_START \
0x0000000b
#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \
0x00000009
#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \
0x00000005
#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \
0x00000004
#define I2C_MASTER_CMD_QUICK_COMMAND \
0x00000027
#define I2C_MASTER_CMD_HS_MASTER_CODE_SEND \
0x00000013
#define I2C_MASTER_CMD_FIFO_SINGLE_SEND \
0x00000046
#define I2C_MASTER_CMD_FIFO_SINGLE_RECEIVE \
0x00000046
#define I2C_MASTER_CMD_FIFO_BURST_SEND_START \
0x00000042
#define I2C_MASTER_CMD_FIFO_BURST_SEND_CONT \
0x00000040
#define I2C_MASTER_CMD_FIFO_BURST_SEND_FINISH \
0x00000044
#define I2C_MASTER_CMD_FIFO_BURST_SEND_ERROR_STOP \
0x00000004
#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_START \
0x0000004a
#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_CONT \
0x00000048
#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_FINISH \
0x00000044
#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_ERROR_STOP \
0x00000004
//*****************************************************************************
//
// I2C Master glitch filter configuration.
//
//*****************************************************************************
#define I2C_MASTER_GLITCH_FILTER_DISABLED \
0
#define I2C_MASTER_GLITCH_FILTER_1 \
0x00010000
#define I2C_MASTER_GLITCH_FILTER_2 \
0x00020000
#define I2C_MASTER_GLITCH_FILTER_3 \
0x00030000
#define I2C_MASTER_GLITCH_FILTER_4 \
0x00040000
#define I2C_MASTER_GLITCH_FILTER_8 \
0x00050000
#define I2C_MASTER_GLITCH_FILTER_16 \
0x00060000
#define I2C_MASTER_GLITCH_FILTER_32 \
0x00070000
//*****************************************************************************
//
// I2C Master error status.
//
//*****************************************************************************
#define I2C_MASTER_ERR_NONE 0
#define I2C_MASTER_ERR_ADDR_ACK 0x00000004
#define I2C_MASTER_ERR_DATA_ACK 0x00000008
#define I2C_MASTER_ERR_ARB_LOST 0x00000010
#define I2C_MASTER_ERR_CLK_TOUT 0x00000080
//*****************************************************************************
//
// I2C Slave action requests
//
//*****************************************************************************
#define I2C_SLAVE_ACT_NONE 0
#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data
#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data
#define I2C_SLAVE_ACT_RREQ_FBR 0x00000005 // Master has sent first byte
#define I2C_SLAVE_ACT_OWN2SEL 0x00000008 // Master requested secondary slave
#define I2C_SLAVE_ACT_QCMD 0x00000010 // Master has sent a Quick Command
#define I2C_SLAVE_ACT_QCMD_DATA 0x00000020 // Master Quick Command value
//*****************************************************************************
//
// Miscellaneous I2C driver definitions.
//
//*****************************************************************************
#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries
//*****************************************************************************
//
// I2C Master interrupts.
//
//*****************************************************************************
#define I2C_MASTER_INT_RX_FIFO_FULL \
0x00000800 // RX FIFO Full Interrupt
#define I2C_MASTER_INT_TX_FIFO_EMPTY \
0x00000400 // TX FIFO Empty Interrupt
#define I2C_MASTER_INT_RX_FIFO_REQ \
0x00000200 // RX FIFO Request Interrupt
#define I2C_MASTER_INT_TX_FIFO_REQ \
0x00000100 // TX FIFO Request Interrupt
#define I2C_MASTER_INT_ARB_LOST \
0x00000080 // Arb Lost Interrupt
#define I2C_MASTER_INT_STOP 0x00000040 // Stop Condition Interrupt
#define I2C_MASTER_INT_START 0x00000020 // Start Condition Interrupt
#define I2C_MASTER_INT_NACK 0x00000010 // Addr/Data NACK Interrupt
#define I2C_MASTER_INT_TX_DMA_DONE \
0x00000008 // TX DMA Complete Interrupt
#define I2C_MASTER_INT_RX_DMA_DONE \
0x00000004 // RX DMA Complete Interrupt
#define I2C_MASTER_INT_TIMEOUT 0x00000002 // Clock Timeout Interrupt
#define I2C_MASTER_INT_DATA 0x00000001 // Data Interrupt
//*****************************************************************************
//
// I2C Slave interrupts.
//
//*****************************************************************************
#define I2C_SLAVE_INT_RX_FIFO_FULL \
0x00000100 // RX FIFO Full Interrupt
#define I2C_SLAVE_INT_TX_FIFO_EMPTY \
0x00000080 // TX FIFO Empty Interrupt
#define I2C_SLAVE_INT_RX_FIFO_REQ \
0x00000040 // RX FIFO Request Interrupt
#define I2C_SLAVE_INT_TX_FIFO_REQ \
0x00000020 // TX FIFO Request Interrupt
#define I2C_SLAVE_INT_TX_DMA_DONE \
0x00000010 // TX DMA Complete Interrupt
#define I2C_SLAVE_INT_RX_DMA_DONE \
0x00000008 // RX DMA Complete Interrupt
#define I2C_SLAVE_INT_STOP 0x00000004 // Stop Condition Interrupt
#define I2C_SLAVE_INT_START 0x00000002 // Start Condition Interrupt
#define I2C_SLAVE_INT_DATA 0x00000001 // Data Interrupt
//*****************************************************************************
//
// I2C Slave FIFO configuration macros.
//
//*****************************************************************************
#define I2C_SLAVE_TX_FIFO_ENABLE \
0x00000002
#define I2C_SLAVE_RX_FIFO_ENABLE \
0x00000004
//*****************************************************************************
//
// I2C FIFO configuration macros.
//
//*****************************************************************************
#define I2C_FIFO_CFG_TX_MASTER 0x00000000
#define I2C_FIFO_CFG_TX_SLAVE 0x00008000
#define I2C_FIFO_CFG_RX_MASTER 0x00000000
#define I2C_FIFO_CFG_RX_SLAVE 0x80000000
#define I2C_FIFO_CFG_TX_MASTER_DMA \
0x00002000
#define I2C_FIFO_CFG_TX_SLAVE_DMA \
0x0000a000
#define I2C_FIFO_CFG_RX_MASTER_DMA \
0x20000000
#define I2C_FIFO_CFG_RX_SLAVE_DMA \
0xa0000000
#define I2C_FIFO_CFG_TX_NO_TRIG 0x00000000
#define I2C_FIFO_CFG_TX_TRIG_1 0x00000001
#define I2C_FIFO_CFG_TX_TRIG_2 0x00000002
#define I2C_FIFO_CFG_TX_TRIG_3 0x00000003
#define I2C_FIFO_CFG_TX_TRIG_4 0x00000004
#define I2C_FIFO_CFG_TX_TRIG_5 0x00000005
#define I2C_FIFO_CFG_TX_TRIG_6 0x00000006
#define I2C_FIFO_CFG_TX_TRIG_7 0x00000007
#define I2C_FIFO_CFG_TX_TRIG_8 0x00000008
#define I2C_FIFO_CFG_RX_NO_TRIG 0x00000000
#define I2C_FIFO_CFG_RX_TRIG_1 0x00010000
#define I2C_FIFO_CFG_RX_TRIG_2 0x00020000
#define I2C_FIFO_CFG_RX_TRIG_3 0x00030000
#define I2C_FIFO_CFG_RX_TRIG_4 0x00040000
#define I2C_FIFO_CFG_RX_TRIG_5 0x00050000
#define I2C_FIFO_CFG_RX_TRIG_6 0x00060000
#define I2C_FIFO_CFG_RX_TRIG_7 0x00070000
#define I2C_FIFO_CFG_RX_TRIG_8 0x00080000
//*****************************************************************************
//
// I2C FIFO status.
//
//*****************************************************************************
#define I2C_FIFO_RX_BELOW_TRIG_LEVEL \
0x00040000
#define I2C_FIFO_RX_FULL 0x00020000
#define I2C_FIFO_RX_EMPTY 0x00010000
#define I2C_FIFO_TX_BELOW_TRIG_LEVEL \
0x00000004
#define I2C_FIFO_TX_FULL 0x00000002
#define I2C_FIFO_TX_EMPTY 0x00000001
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void I2CIntRegister(uint32_t ui32Base, void(*pfnHandler)(void));
extern void I2CIntUnregister(uint32_t ui32Base);
extern void I2CTxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config);
extern void I2CTxFIFOFlush(uint32_t ui32Base);
extern void I2CRxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config);
extern void I2CRxFIFOFlush(uint32_t ui32Base);
extern uint32_t I2CFIFOStatus(uint32_t ui32Base);
extern void I2CFIFODataPut(uint32_t ui32Base, uint8_t ui8Data);
extern uint32_t I2CFIFODataPutNonBlocking(uint32_t ui32Base,
uint8_t ui8Data);
extern uint32_t I2CFIFODataGet(uint32_t ui32Base);
extern uint32_t I2CFIFODataGetNonBlocking(uint32_t ui32Base,
uint8_t *pui8Data);
extern void I2CMasterBurstLengthSet(uint32_t ui32Base,
uint8_t ui8Length);
extern uint32_t I2CMasterBurstCountGet(uint32_t ui32Base);
extern void I2CMasterGlitchFilterConfigSet(uint32_t ui32Base,
uint32_t ui32Config);
extern void I2CSlaveFIFOEnable(uint32_t ui32Base, uint32_t ui32Config);
extern void I2CSlaveFIFODisable(uint32_t ui32Base);
extern bool I2CMasterBusBusy(uint32_t ui32Base);
extern bool I2CMasterBusy(uint32_t ui32Base);
extern void I2CMasterControl(uint32_t ui32Base, uint32_t ui32Cmd);
extern uint32_t I2CMasterDataGet(uint32_t ui32Base);
extern void I2CMasterDataPut(uint32_t ui32Base, uint8_t ui8Data);
extern void I2CMasterDisable(uint32_t ui32Base);
extern void I2CMasterEnable(uint32_t ui32Base);
extern uint32_t I2CMasterErr(uint32_t ui32Base);
extern void I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk,
bool bFast);
extern void I2CMasterIntClear(uint32_t ui32Base);
extern void I2CMasterIntDisable(uint32_t ui32Base);
extern void I2CMasterIntEnable(uint32_t ui32Base);
extern bool I2CMasterIntStatus(uint32_t ui32Base, bool bMasked);
extern void I2CMasterIntEnableEx(uint32_t ui32Base,
uint32_t ui32IntFlags);
extern void I2CMasterIntDisableEx(uint32_t ui32Base,
uint32_t ui32IntFlags);
extern uint32_t I2CMasterIntStatusEx(uint32_t ui32Base,
bool bMasked);
extern void I2CMasterIntClearEx(uint32_t ui32Base,
uint32_t ui32IntFlags);
extern void I2CMasterTimeoutSet(uint32_t ui32Base, uint32_t ui32Value);
extern void I2CSlaveACKOverride(uint32_t ui32Base, bool bEnable);
extern void I2CSlaveACKValueSet(uint32_t ui32Base, bool bACK);
extern uint32_t I2CMasterLineStateGet(uint32_t ui32Base);
extern void I2CMasterSlaveAddrSet(uint32_t ui32Base,
uint8_t ui8SlaveAddr,
bool bReceive);
extern uint32_t I2CSlaveDataGet(uint32_t ui32Base);
extern void I2CSlaveDataPut(uint32_t ui32Base, uint8_t ui8Data);
extern void I2CSlaveDisable(uint32_t ui32Base);
extern void I2CSlaveEnable(uint32_t ui32Base);
extern void I2CSlaveInit(uint32_t ui32Base, uint8_t ui8SlaveAddr);
extern void I2CSlaveAddressSet(uint32_t ui32Base, uint8_t ui8AddrNum,
uint8_t ui8SlaveAddr);
extern void I2CSlaveIntClear(uint32_t ui32Base);
extern void I2CSlaveIntDisable(uint32_t ui32Base);
extern void I2CSlaveIntEnable(uint32_t ui32Base);
extern void I2CSlaveIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void I2CSlaveIntDisableEx(uint32_t ui32Base,
uint32_t ui32IntFlags);
extern void I2CSlaveIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags);
extern bool I2CSlaveIntStatus(uint32_t ui32Base, bool bMasked);
extern uint32_t I2CSlaveIntStatusEx(uint32_t ui32Base,
bool bMasked);
extern uint32_t I2CSlaveStatus(uint32_t ui32Base);
extern void I2CLoopbackEnable(uint32_t ui32Base);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_I2C_H__

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//*****************************************************************************
//
// asmdefs.h - Macros to allow assembly code be portable among toolchains.
//
// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
//
//*****************************************************************************
#ifndef __ASMDEFS_H__
#define __ASMDEFS_H__
//*****************************************************************************
//
// The defines required for code_red.
//
//*****************************************************************************
#ifdef codered
//
// The assembly code preamble required to put the assembler into the correct
// configuration.
//
.syntax unified
.thumb
//
// Section headers.
//
#define __LIBRARY__ @
#define __TEXT__ .text
#define __DATA__ .data
#define __BSS__ .bss
#define __TEXT_NOROOT__ .text
//
// Assembler nmenonics.
//
#define __ALIGN__ .balign 4
#define __END__ .end
#define __EXPORT__ .globl
#define __IMPORT__ .extern
#define __LABEL__ :
#define __STR__ .ascii
#define __THUMB_LABEL__ .thumb_func
#define __WORD__ .word
#define __INLINE_DATA__
#endif // codered
//*****************************************************************************
//
// The defines required for EW-ARM.
//
//*****************************************************************************
#ifdef ewarm
//
// Section headers.
//
#define __LIBRARY__ module
#define __TEXT__ rseg CODE:CODE(2)
#define __DATA__ rseg DATA:DATA(2)
#define __BSS__ rseg DATA:DATA(2)
#define __TEXT_NOROOT__ rseg CODE:CODE:NOROOT(2)
//
// Assembler nmenonics.
//
#define __ALIGN__ alignrom 2
#define __END__ end
#define __EXPORT__ export
#define __IMPORT__ import
#define __LABEL__
#define __STR__ dcb
#define __THUMB_LABEL__ thumb
#define __WORD__ dcd
#define __INLINE_DATA__ data
#endif // ewarm
//*****************************************************************************
//
// The defines required for GCC.
//
//*****************************************************************************
#if defined(gcc)
//
// The assembly code preamble required to put the assembler into the correct
// configuration.
//
.syntax unified
.thumb
//
// Section headers.
//
#define __LIBRARY__ @
#define __TEXT__ .text
#define __DATA__ .data
#define __BSS__ .bss
#define __TEXT_NOROOT__ .text
//
// Assembler nmenonics.
//
#define __ALIGN__ .balign 4
#define __END__ .end
#define __EXPORT__ .globl
#define __IMPORT__ .extern
#define __LABEL__ :
#define __STR__ .ascii
#define __THUMB_LABEL__ .thumb_func
#define __WORD__ .word
#define __INLINE_DATA__
#endif // gcc
//*****************************************************************************
//
// The defines required for RV-MDK.
//
//*****************************************************************************
#ifdef rvmdk
//
// The assembly code preamble required to put the assembler into the correct
// configuration.
//
thumb
require8
preserve8
//
// Section headers.
//
#define __LIBRARY__ ;
#define __TEXT__ area ||.text||, code, readonly, align=2
#define __DATA__ area ||.data||, data, align=2
#define __BSS__ area ||.bss||, noinit, align=2
#define __TEXT_NOROOT__ area ||.text||, code, readonly, align=2
//
// Assembler nmenonics.
//
#define __ALIGN__ align 4
#define __END__ end
#define __EXPORT__ export
#define __IMPORT__ import
#define __LABEL__
#define __STR__ dcb
#define __THUMB_LABEL__
#define __WORD__ dcd
#define __INLINE_DATA__
#endif // rvmdk
//*****************************************************************************
//
// The defines required for Sourcery G++.
//
//*****************************************************************************
#if defined(sourcerygxx)
//
// The assembly code preamble required to put the assembler into the correct
// configuration.
//
.syntax unified
.thumb
//
// Section headers.
//
#define __LIBRARY__ @
#define __TEXT__ .text
#define __DATA__ .data
#define __BSS__ .bss
#define __TEXT_NOROOT__ .text
//
// Assembler nmenonics.
//
#define __ALIGN__ .balign 4
#define __END__ .end
#define __EXPORT__ .globl
#define __IMPORT__ .extern
#define __LABEL__ :
#define __STR__ .ascii
#define __THUMB_LABEL__ .thumb_func
#define __WORD__ .word
#define __INLINE_DATA__
#endif // sourcerygxx
#endif // __ASMDEF_H__

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//*****************************************************************************
//
// hw_aes.h - Macros used when accessing the AES hardware.
//
// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_AES_H__
#define __HW_AES_H__
//*****************************************************************************
//
// The following are defines for the AES register offsets.
//
//*****************************************************************************
#define AES_O_KEY2_6 0x00000000 // AES Key 2_6
#define AES_O_KEY2_7 0x00000004 // AES Key 2_7
#define AES_O_KEY2_4 0x00000008 // AES Key 2_4
#define AES_O_KEY2_5 0x0000000C // AES Key 2_5
#define AES_O_KEY2_2 0x00000010 // AES Key 2_2
#define AES_O_KEY2_3 0x00000014 // AES Key 2_3
#define AES_O_KEY2_0 0x00000018 // AES Key 2_0
#define AES_O_KEY2_1 0x0000001C // AES Key 2_1
#define AES_O_KEY1_6 0x00000020 // AES Key 1_6
#define AES_O_KEY1_7 0x00000024 // AES Key 1_7
#define AES_O_KEY1_4 0x00000028 // AES Key 1_4
#define AES_O_KEY1_5 0x0000002C // AES Key 1_5
#define AES_O_KEY1_2 0x00000030 // AES Key 1_2
#define AES_O_KEY1_3 0x00000034 // AES Key 1_3
#define AES_O_KEY1_0 0x00000038 // AES Key 1_0
#define AES_O_KEY1_1 0x0000003C // AES Key 1_1
#define AES_O_IV_IN_0 0x00000040 // AES Initialization Vector Input
// 0
#define AES_O_IV_IN_1 0x00000044 // AES Initialization Vector Input
// 1
#define AES_O_IV_IN_2 0x00000048 // AES Initialization Vector Input
// 2
#define AES_O_IV_IN_3 0x0000004C // AES Initialization Vector Input
// 3
#define AES_O_CTRL 0x00000050 // AES Control
#define AES_O_C_LENGTH_0 0x00000054 // AES Crypto Data Length 0
#define AES_O_C_LENGTH_1 0x00000058 // AES Crypto Data Length 1
#define AES_O_AUTH_LENGTH 0x0000005C // AES Authentication Data Length
#define AES_O_DATA_IN_0 0x00000060 // AES Data RW Plaintext/Ciphertext
// 0
#define AES_O_DATA_IN_1 0x00000064 // AES Data RW Plaintext/Ciphertext
// 1
#define AES_O_DATA_IN_2 0x00000068 // AES Data RW Plaintext/Ciphertext
// 2
#define AES_O_DATA_IN_3 0x0000006C // AES Data RW Plaintext/Ciphertext
// 3
#define AES_O_TAG_OUT_0 0x00000070 // AES Hash Tag Out 0
#define AES_O_TAG_OUT_1 0x00000074 // AES Hash Tag Out 1
#define AES_O_TAG_OUT_2 0x00000078 // AES Hash Tag Out 2
#define AES_O_TAG_OUT_3 0x0000007C // AES Hash Tag Out 3
#define AES_O_REVISION 0x00000080 // AES IP Revision Identifier
#define AES_O_SYSCONFIG 0x00000084 // AES System Configuration
#define AES_O_SYSSTATUS 0x00000088 // AES System Status
#define AES_O_IRQSTATUS 0x0000008C // AES Interrupt Status
#define AES_O_IRQENABLE 0x00000090 // AES Interrupt Enable
#define AES_O_DIRTYBITS 0x00000094 // AES Dirty Bits
#define AES_O_DMAIM 0xFFFFA020 // AES DMA Interrupt Mask
#define AES_O_DMARIS 0xFFFFA024 // AES DMA Raw Interrupt Status
#define AES_O_DMAMIS 0xFFFFA028 // AES DMA Masked Interrupt Status
#define AES_O_DMAIC 0xFFFFA02C // AES DMA Interrupt Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY2_6 register.
//
//*****************************************************************************
#define AES_KEY2_6_KEY_M 0xFFFFFFFF // Key Data
#define AES_KEY2_6_KEY_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY2_7 register.
//
//*****************************************************************************
#define AES_KEY2_7_KEY_M 0xFFFFFFFF // Key Data
#define AES_KEY2_7_KEY_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY2_4 register.
//
//*****************************************************************************
#define AES_KEY2_4_KEY_M 0xFFFFFFFF // Key Data
#define AES_KEY2_4_KEY_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY2_5 register.
//
//*****************************************************************************
#define AES_KEY2_5_KEY_M 0xFFFFFFFF // Key Data
#define AES_KEY2_5_KEY_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY2_2 register.
//
//*****************************************************************************
#define AES_KEY2_2_KEY_M 0xFFFFFFFF // Key Data
#define AES_KEY2_2_KEY_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY2_3 register.
//
//*****************************************************************************
#define AES_KEY2_3_KEY_M 0xFFFFFFFF // Key Data
#define AES_KEY2_3_KEY_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY2_0 register.
//
//*****************************************************************************
#define AES_KEY2_0_KEY_M 0xFFFFFFFF // Key Data
#define AES_KEY2_0_KEY_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY2_1 register.
//
//*****************************************************************************
#define AES_KEY2_1_KEY_M 0xFFFFFFFF // Key Data
#define AES_KEY2_1_KEY_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY1_6 register.
//
//*****************************************************************************
#define AES_KEY1_6_KEY_M 0xFFFFFFFF // Key Data
#define AES_KEY1_6_KEY_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY1_7 register.
//
//*****************************************************************************
#define AES_KEY1_7_KEY_M 0xFFFFFFFF // Key Data
#define AES_KEY1_7_KEY_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY1_4 register.
//
//*****************************************************************************
#define AES_KEY1_4_KEY_M 0xFFFFFFFF // Key Data
#define AES_KEY1_4_KEY_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY1_5 register.
//
//*****************************************************************************
#define AES_KEY1_5_KEY_M 0xFFFFFFFF // Key Data
#define AES_KEY1_5_KEY_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY1_2 register.
//
//*****************************************************************************
#define AES_KEY1_2_KEY_M 0xFFFFFFFF // Key Data
#define AES_KEY1_2_KEY_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY1_3 register.
//
//*****************************************************************************
#define AES_KEY1_3_KEY_M 0xFFFFFFFF // Key Data
#define AES_KEY1_3_KEY_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY1_0 register.
//
//*****************************************************************************
#define AES_KEY1_0_KEY_M 0xFFFFFFFF // Key Data
#define AES_KEY1_0_KEY_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY1_1 register.
//
//*****************************************************************************
#define AES_KEY1_1_KEY_M 0xFFFFFFFF // Key Data
#define AES_KEY1_1_KEY_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the AES_O_IV_IN_0 register.
//
//*****************************************************************************
#define AES_IV_IN_0_DATA_M 0xFFFFFFFF // Initialization Vector Input
#define AES_IV_IN_0_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the AES_O_IV_IN_1 register.
//
//*****************************************************************************
#define AES_IV_IN_1_DATA_M 0xFFFFFFFF // Initialization Vector Input
#define AES_IV_IN_1_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the AES_O_IV_IN_2 register.
//
//*****************************************************************************
#define AES_IV_IN_2_DATA_M 0xFFFFFFFF // Initialization Vector Input
#define AES_IV_IN_2_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the AES_O_IV_IN_3 register.
//
//*****************************************************************************
#define AES_IV_IN_3_DATA_M 0xFFFFFFFF // Initialization Vector Input
#define AES_IV_IN_3_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the AES_O_CTRL register.
//
//*****************************************************************************
#define AES_CTRL_CTXTRDY 0x80000000 // Context Data Registers Ready
#define AES_CTRL_SVCTXTRDY 0x40000000 // AES TAG/IV Block(s) Ready
#define AES_CTRL_SAVE_CONTEXT 0x20000000 // TAG or Result IV Save
#define AES_CTRL_CCM_M_M 0x01C00000 // Counter with CBC-MAC (CCM)
#define AES_CTRL_CCM_L_M 0x00380000 // L Value
#define AES_CTRL_CCM_L_2 0x00080000 // width = 2
#define AES_CTRL_CCM_L_4 0x00180000 // width = 4
#define AES_CTRL_CCM_L_8 0x00380000 // width = 8
#define AES_CTRL_CCM 0x00040000 // AES-CCM Mode Enable
#define AES_CTRL_GCM_M 0x00030000 // AES-GCM Mode Enable
#define AES_CTRL_GCM_NOP 0x00000000 // No operation
#define AES_CTRL_GCM_HLY0ZERO 0x00010000 // GHASH with H loaded and
// Y0-encrypted forced to zero
#define AES_CTRL_GCM_HLY0CALC 0x00020000 // GHASH with H loaded and
// Y0-encrypted calculated
// internally
#define AES_CTRL_GCM_HY0CALC 0x00030000 // Autonomous GHASH (both H and
// Y0-encrypted calculated
// internally)
#define AES_CTRL_CBCMAC 0x00008000 // AES-CBC MAC Enable
#define AES_CTRL_F9 0x00004000 // AES f9 Mode Enable
#define AES_CTRL_F8 0x00002000 // AES f8 Mode Enable
#define AES_CTRL_XTS_M 0x00001800 // AES-XTS Operation Enabled
#define AES_CTRL_XTS_NOP 0x00000000 // No operation
#define AES_CTRL_XTS_TWEAKJL 0x00000800 // Previous/intermediate tweak
// value and j loaded (value is
// loaded via IV, j is loaded via
// the AAD length register)
#define AES_CTRL_XTS_K2IJL 0x00001000 // Key2, n and j are loaded (n is
// loaded via IV, j is loaded via
// the AAD length register)
#define AES_CTRL_XTS_K2ILJ0 0x00001800 // Key2 and n are loaded; j=0 (n is
// loaded via IV)
#define AES_CTRL_CFB 0x00000400 // Full block AES cipher feedback
// mode (CFB128) Enable
#define AES_CTRL_ICM 0x00000200 // AES Integer Counter Mode (ICM)
// Enable
#define AES_CTRL_CTR_WIDTH_M 0x00000180 // AES-CTR Mode Counter Width
#define AES_CTRL_CTR_WIDTH_32 0x00000000 // Counter is 32 bits
#define AES_CTRL_CTR_WIDTH_64 0x00000080 // Counter is 64 bits
#define AES_CTRL_CTR_WIDTH_96 0x00000100 // Counter is 96 bits
#define AES_CTRL_CTR_WIDTH_128 0x00000180 // Counter is 128 bits
#define AES_CTRL_CTR 0x00000040 // Counter Mode
#define AES_CTRL_MODE 0x00000020 // ECB/CBC Mode
#define AES_CTRL_KEY_SIZE_M 0x00000018 // Key Size
#define AES_CTRL_KEY_SIZE_128 0x00000008 // Key is 128 bits
#define AES_CTRL_KEY_SIZE_192 0x00000010 // Key is 192 bits
#define AES_CTRL_KEY_SIZE_256 0x00000018 // Key is 256 bits
#define AES_CTRL_DIRECTION 0x00000004 // Encryption/Decryption Selection
#define AES_CTRL_INPUT_READY 0x00000002 // Input Ready Status
#define AES_CTRL_OUTPUT_READY 0x00000001 // Output Ready Status
#define AES_CTRL_CCM_M_S 22
//*****************************************************************************
//
// The following are defines for the bit fields in the AES_O_C_LENGTH_0
// register.
//
//*****************************************************************************
#define AES_C_LENGTH_0_LENGTH_M 0xFFFFFFFF // Data Length
#define AES_C_LENGTH_0_LENGTH_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the AES_O_C_LENGTH_1
// register.
//
//*****************************************************************************
#define AES_C_LENGTH_1_LENGTH_M 0xFFFFFFFF // Data Length
#define AES_C_LENGTH_1_LENGTH_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the AES_O_AUTH_LENGTH
// register.
//
//*****************************************************************************
#define AES_AUTH_LENGTH_AUTH_M 0xFFFFFFFF // Authentication Data Length
#define AES_AUTH_LENGTH_AUTH_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the AES_O_DATA_IN_0
// register.
//
//*****************************************************************************
#define AES_DATA_IN_0_DATA_M 0xFFFFFFFF // Secure Data RW
// Plaintext/Ciphertext
#define AES_DATA_IN_0_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the AES_O_DATA_IN_1
// register.
//
//*****************************************************************************
#define AES_DATA_IN_1_DATA_M 0xFFFFFFFF // Secure Data RW
// Plaintext/Ciphertext
#define AES_DATA_IN_1_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the AES_O_DATA_IN_2
// register.
//
//*****************************************************************************
#define AES_DATA_IN_2_DATA_M 0xFFFFFFFF // Secure Data RW
// Plaintext/Ciphertext
#define AES_DATA_IN_2_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the AES_O_DATA_IN_3
// register.
//
//*****************************************************************************
#define AES_DATA_IN_3_DATA_M 0xFFFFFFFF // Secure Data RW
// Plaintext/Ciphertext
#define AES_DATA_IN_3_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the AES_O_TAG_OUT_0
// register.
//
//*****************************************************************************
#define AES_TAG_OUT_0_HASH_M 0xFFFFFFFF // Hash Result
#define AES_TAG_OUT_0_HASH_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the AES_O_TAG_OUT_1
// register.
//
//*****************************************************************************
#define AES_TAG_OUT_1_HASH_M 0xFFFFFFFF // Hash Result
#define AES_TAG_OUT_1_HASH_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the AES_O_TAG_OUT_2
// register.
//
//*****************************************************************************
#define AES_TAG_OUT_2_HASH_M 0xFFFFFFFF // Hash Result
#define AES_TAG_OUT_2_HASH_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the AES_O_TAG_OUT_3
// register.
//
//*****************************************************************************
#define AES_TAG_OUT_3_HASH_M 0xFFFFFFFF // Hash Result
#define AES_TAG_OUT_3_HASH_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the AES_O_REVISION register.
//
//*****************************************************************************
#define AES_REVISION_M 0xFFFFFFFF // Revision number
#define AES_REVISION_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the AES_O_SYSCONFIG
// register.
//
//*****************************************************************************
#define AES_SYSCONFIG_K3 0x00001000 // K3 Select
#define AES_SYSCONFIG_KEYENC 0x00000800 // Key Encoding
#define AES_SYSCONFIG_MAP_CONTEXT_OUT_ON_DATA_OUT \
0x00000200 // Map Context Out on Data Out
// Enable
#define AES_SYSCONFIG_DMA_REQ_CONTEXT_OUT_EN \
0x00000100 // DMA Request Context Out Enable
#define AES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN \
0x00000080 // DMA Request Context In Enable
#define AES_SYSCONFIG_DMA_REQ_DATA_OUT_EN \
0x00000040 // DMA Request Data Out Enable
#define AES_SYSCONFIG_DMA_REQ_DATA_IN_EN \
0x00000020 // DMA Request Data In Enable
#define AES_SYSCONFIG_SOFTRESET 0x00000002 // Soft reset
//*****************************************************************************
//
// The following are defines for the bit fields in the AES_O_SYSSTATUS
// register.
//
//*****************************************************************************
#define AES_SYSSTATUS_RESETDONE 0x00000001 // Reset Done
//*****************************************************************************
//
// The following are defines for the bit fields in the AES_O_IRQSTATUS
// register.
//
//*****************************************************************************
#define AES_IRQSTATUS_CONTEXT_OUT \
0x00000008 // Context Output Interrupt Status
#define AES_IRQSTATUS_DATA_OUT 0x00000004 // Data Out Interrupt Status
#define AES_IRQSTATUS_DATA_IN 0x00000002 // Data In Interrupt Status
#define AES_IRQSTATUS_CONTEXT_IN \
0x00000001 // Context In Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the AES_O_IRQENABLE
// register.
//
//*****************************************************************************
#define AES_IRQENABLE_CONTEXT_OUT \
0x00000008 // Context Out Interrupt Enable
#define AES_IRQENABLE_DATA_OUT 0x00000004 // Data Out Interrupt Enable
#define AES_IRQENABLE_DATA_IN 0x00000002 // Data In Interrupt Enable
#define AES_IRQENABLE_CONTEXT_IN \
0x00000001 // Context In Interrupt Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the AES_O_DIRTYBITS
// register.
//
//*****************************************************************************
#define AES_DIRTYBITS_S_DIRTY 0x00000002 // AES Dirty Bit
#define AES_DIRTYBITS_S_ACCESS 0x00000001 // AES Access Bit
//*****************************************************************************
//
// The following are defines for the bit fields in the AES_O_DMAIM register.
//
//*****************************************************************************
#define AES_DMAIM_DOUT 0x00000008 // Data Out DMA Done Interrupt Mask
#define AES_DMAIM_DIN 0x00000004 // Data In DMA Done Interrupt Mask
#define AES_DMAIM_COUT 0x00000002 // Context Out DMA Done Interrupt
// Mask
#define AES_DMAIM_CIN 0x00000001 // Context In DMA Done Interrupt
// Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the AES_O_DMARIS register.
//
//*****************************************************************************
#define AES_DMARIS_DOUT 0x00000008 // Data Out DMA Done Raw Interrupt
// Status
#define AES_DMARIS_DIN 0x00000004 // Data In DMA Done Raw Interrupt
// Status
#define AES_DMARIS_COUT 0x00000002 // Context Out DMA Done Raw
// Interrupt Status
#define AES_DMARIS_CIN 0x00000001 // Context In DMA Done Raw
// Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the AES_O_DMAMIS register.
//
//*****************************************************************************
#define AES_DMAMIS_DOUT 0x00000008 // Data Out DMA Done Masked
// Interrupt Status
#define AES_DMAMIS_DIN 0x00000004 // Data In DMA Done Masked
// Interrupt Status
#define AES_DMAMIS_COUT 0x00000002 // Context Out DMA Done Masked
// Interrupt Status
#define AES_DMAMIS_CIN 0x00000001 // Context In DMA Done Raw
// Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the AES_O_DMAIC register.
//
//*****************************************************************************
#define AES_DMAIC_DOUT 0x00000008 // Data Out DMA Done Interrupt
// Clear
#define AES_DMAIC_DIN 0x00000004 // Data In DMA Done Interrupt Clear
#define AES_DMAIC_COUT 0x00000002 // Context Out DMA Done Masked
// Interrupt Status
#define AES_DMAIC_CIN 0x00000001 // Context In DMA Done Raw
// Interrupt Status
#endif // __HW_AES_H__

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//*****************************************************************************
//
// hw_can.h - Defines and macros used when accessing the CAN controllers.
//
// Copyright (c) 2006-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_CAN_H__
#define __HW_CAN_H__
//*****************************************************************************
//
// The following are defines for the CAN register offsets.
//
//*****************************************************************************
#define CAN_O_CTL 0x00000000 // CAN Control
#define CAN_O_STS 0x00000004 // CAN Status
#define CAN_O_ERR 0x00000008 // CAN Error Counter
#define CAN_O_BIT 0x0000000C // CAN Bit Timing
#define CAN_O_INT 0x00000010 // CAN Interrupt
#define CAN_O_TST 0x00000014 // CAN Test
#define CAN_O_BRPE 0x00000018 // CAN Baud Rate Prescaler
// Extension
#define CAN_O_IF1CRQ 0x00000020 // CAN IF1 Command Request
#define CAN_O_IF1CMSK 0x00000024 // CAN IF1 Command Mask
#define CAN_O_IF1MSK1 0x00000028 // CAN IF1 Mask 1
#define CAN_O_IF1MSK2 0x0000002C // CAN IF1 Mask 2
#define CAN_O_IF1ARB1 0x00000030 // CAN IF1 Arbitration 1
#define CAN_O_IF1ARB2 0x00000034 // CAN IF1 Arbitration 2
#define CAN_O_IF1MCTL 0x00000038 // CAN IF1 Message Control
#define CAN_O_IF1DA1 0x0000003C // CAN IF1 Data A1
#define CAN_O_IF1DA2 0x00000040 // CAN IF1 Data A2
#define CAN_O_IF1DB1 0x00000044 // CAN IF1 Data B1
#define CAN_O_IF1DB2 0x00000048 // CAN IF1 Data B2
#define CAN_O_IF2CRQ 0x00000080 // CAN IF2 Command Request
#define CAN_O_IF2CMSK 0x00000084 // CAN IF2 Command Mask
#define CAN_O_IF2MSK1 0x00000088 // CAN IF2 Mask 1
#define CAN_O_IF2MSK2 0x0000008C // CAN IF2 Mask 2
#define CAN_O_IF2ARB1 0x00000090 // CAN IF2 Arbitration 1
#define CAN_O_IF2ARB2 0x00000094 // CAN IF2 Arbitration 2
#define CAN_O_IF2MCTL 0x00000098 // CAN IF2 Message Control
#define CAN_O_IF2DA1 0x0000009C // CAN IF2 Data A1
#define CAN_O_IF2DA2 0x000000A0 // CAN IF2 Data A2
#define CAN_O_IF2DB1 0x000000A4 // CAN IF2 Data B1
#define CAN_O_IF2DB2 0x000000A8 // CAN IF2 Data B2
#define CAN_O_TXRQ1 0x00000100 // CAN Transmission Request 1
#define CAN_O_TXRQ2 0x00000104 // CAN Transmission Request 2
#define CAN_O_NWDA1 0x00000120 // CAN New Data 1
#define CAN_O_NWDA2 0x00000124 // CAN New Data 2
#define CAN_O_MSG1INT 0x00000140 // CAN Message 1 Interrupt Pending
#define CAN_O_MSG2INT 0x00000144 // CAN Message 2 Interrupt Pending
#define CAN_O_MSG1VAL 0x00000160 // CAN Message 1 Valid
#define CAN_O_MSG2VAL 0x00000164 // CAN Message 2 Valid
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_CTL register.
//
//*****************************************************************************
#define CAN_CTL_TEST 0x00000080 // Test Mode Enable
#define CAN_CTL_CCE 0x00000040 // Configuration Change Enable
#define CAN_CTL_DAR 0x00000020 // Disable Automatic-Retransmission
#define CAN_CTL_EIE 0x00000008 // Error Interrupt Enable
#define CAN_CTL_SIE 0x00000004 // Status Interrupt Enable
#define CAN_CTL_IE 0x00000002 // CAN Interrupt Enable
#define CAN_CTL_INIT 0x00000001 // Initialization
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_STS register.
//
//*****************************************************************************
#define CAN_STS_BOFF 0x00000080 // Bus-Off Status
#define CAN_STS_EWARN 0x00000040 // Warning Status
#define CAN_STS_EPASS 0x00000020 // Error Passive
#define CAN_STS_RXOK 0x00000010 // Received a Message Successfully
#define CAN_STS_TXOK 0x00000008 // Transmitted a Message
// Successfully
#define CAN_STS_LEC_M 0x00000007 // Last Error Code
#define CAN_STS_LEC_NONE 0x00000000 // No Error
#define CAN_STS_LEC_STUFF 0x00000001 // Stuff Error
#define CAN_STS_LEC_FORM 0x00000002 // Format Error
#define CAN_STS_LEC_ACK 0x00000003 // ACK Error
#define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 Error
#define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 Error
#define CAN_STS_LEC_CRC 0x00000006 // CRC Error
#define CAN_STS_LEC_NOEVENT 0x00000007 // No Event
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_ERR register.
//
//*****************************************************************************
#define CAN_ERR_RP 0x00008000 // Received Error Passive
#define CAN_ERR_REC_M 0x00007F00 // Receive Error Counter
#define CAN_ERR_TEC_M 0x000000FF // Transmit Error Counter
#define CAN_ERR_REC_S 8
#define CAN_ERR_TEC_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_BIT register.
//
//*****************************************************************************
#define CAN_BIT_TSEG2_M 0x00007000 // Time Segment after Sample Point
#define CAN_BIT_TSEG1_M 0x00000F00 // Time Segment Before Sample Point
#define CAN_BIT_SJW_M 0x000000C0 // (Re)Synchronization Jump Width
#define CAN_BIT_BRP_M 0x0000003F // Baud Rate Prescaler
#define CAN_BIT_TSEG2_S 12
#define CAN_BIT_TSEG1_S 8
#define CAN_BIT_SJW_S 6
#define CAN_BIT_BRP_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_INT register.
//
//*****************************************************************************
#define CAN_INT_INTID_M 0x0000FFFF // Interrupt Identifier
#define CAN_INT_INTID_NONE 0x00000000 // No interrupt pending
#define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_TST register.
//
//*****************************************************************************
#define CAN_TST_RX 0x00000080 // Receive Observation
#define CAN_TST_TX_M 0x00000060 // Transmit Control
#define CAN_TST_TX_CANCTL 0x00000000 // CAN Module Control
#define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point
#define CAN_TST_TX_DOMINANT 0x00000040 // Driven Low
#define CAN_TST_TX_RECESSIVE 0x00000060 // Driven High
#define CAN_TST_LBACK 0x00000010 // Loopback Mode
#define CAN_TST_SILENT 0x00000008 // Silent Mode
#define CAN_TST_BASIC 0x00000004 // Basic Mode
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_BRPE register.
//
//*****************************************************************************
#define CAN_BRPE_BRPE_M 0x0000000F // Baud Rate Prescaler Extension
#define CAN_BRPE_BRPE_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1CRQ register.
//
//*****************************************************************************
#define CAN_IF1CRQ_BUSY 0x00008000 // Busy Flag
#define CAN_IF1CRQ_MNUM_M 0x0000003F // Message Number
#define CAN_IF1CRQ_MNUM_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1CMSK register.
//
//*****************************************************************************
#define CAN_IF1CMSK_WRNRD 0x00000080 // Write, Not Read
#define CAN_IF1CMSK_MASK 0x00000040 // Access Mask Bits
#define CAN_IF1CMSK_ARB 0x00000020 // Access Arbitration Bits
#define CAN_IF1CMSK_CONTROL 0x00000010 // Access Control Bits
#define CAN_IF1CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit
#define CAN_IF1CMSK_NEWDAT 0x00000004 // Access New Data
#define CAN_IF1CMSK_TXRQST 0x00000004 // Access Transmission Request
#define CAN_IF1CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3
#define CAN_IF1CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1MSK1 register.
//
//*****************************************************************************
#define CAN_IF1MSK1_IDMSK_M 0x0000FFFF // Identifier Mask
#define CAN_IF1MSK1_IDMSK_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1MSK2 register.
//
//*****************************************************************************
#define CAN_IF1MSK2_MXTD 0x00008000 // Mask Extended Identifier
#define CAN_IF1MSK2_MDIR 0x00004000 // Mask Message Direction
#define CAN_IF1MSK2_IDMSK_M 0x00001FFF // Identifier Mask
#define CAN_IF1MSK2_IDMSK_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1ARB1 register.
//
//*****************************************************************************
#define CAN_IF1ARB1_ID_M 0x0000FFFF // Message Identifier
#define CAN_IF1ARB1_ID_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1ARB2 register.
//
//*****************************************************************************
#define CAN_IF1ARB2_MSGVAL 0x00008000 // Message Valid
#define CAN_IF1ARB2_XTD 0x00004000 // Extended Identifier
#define CAN_IF1ARB2_DIR 0x00002000 // Message Direction
#define CAN_IF1ARB2_ID_M 0x00001FFF // Message Identifier
#define CAN_IF1ARB2_ID_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1MCTL register.
//
//*****************************************************************************
#define CAN_IF1MCTL_NEWDAT 0x00008000 // New Data
#define CAN_IF1MCTL_MSGLST 0x00004000 // Message Lost
#define CAN_IF1MCTL_INTPND 0x00002000 // Interrupt Pending
#define CAN_IF1MCTL_UMASK 0x00001000 // Use Acceptance Mask
#define CAN_IF1MCTL_TXIE 0x00000800 // Transmit Interrupt Enable
#define CAN_IF1MCTL_RXIE 0x00000400 // Receive Interrupt Enable
#define CAN_IF1MCTL_RMTEN 0x00000200 // Remote Enable
#define CAN_IF1MCTL_TXRQST 0x00000100 // Transmit Request
#define CAN_IF1MCTL_EOB 0x00000080 // End of Buffer
#define CAN_IF1MCTL_DLC_M 0x0000000F // Data Length Code
#define CAN_IF1MCTL_DLC_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1DA1 register.
//
//*****************************************************************************
#define CAN_IF1DA1_DATA_M 0x0000FFFF // Data
#define CAN_IF1DA1_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1DA2 register.
//
//*****************************************************************************
#define CAN_IF1DA2_DATA_M 0x0000FFFF // Data
#define CAN_IF1DA2_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1DB1 register.
//
//*****************************************************************************
#define CAN_IF1DB1_DATA_M 0x0000FFFF // Data
#define CAN_IF1DB1_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1DB2 register.
//
//*****************************************************************************
#define CAN_IF1DB2_DATA_M 0x0000FFFF // Data
#define CAN_IF1DB2_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF2CRQ register.
//
//*****************************************************************************
#define CAN_IF2CRQ_BUSY 0x00008000 // Busy Flag
#define CAN_IF2CRQ_MNUM_M 0x0000003F // Message Number
#define CAN_IF2CRQ_MNUM_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF2CMSK register.
//
//*****************************************************************************
#define CAN_IF2CMSK_WRNRD 0x00000080 // Write, Not Read
#define CAN_IF2CMSK_MASK 0x00000040 // Access Mask Bits
#define CAN_IF2CMSK_ARB 0x00000020 // Access Arbitration Bits
#define CAN_IF2CMSK_CONTROL 0x00000010 // Access Control Bits
#define CAN_IF2CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit
#define CAN_IF2CMSK_NEWDAT 0x00000004 // Access New Data
#define CAN_IF2CMSK_TXRQST 0x00000004 // Access Transmission Request
#define CAN_IF2CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3
#define CAN_IF2CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF2MSK1 register.
//
//*****************************************************************************
#define CAN_IF2MSK1_IDMSK_M 0x0000FFFF // Identifier Mask
#define CAN_IF2MSK1_IDMSK_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF2MSK2 register.
//
//*****************************************************************************
#define CAN_IF2MSK2_MXTD 0x00008000 // Mask Extended Identifier
#define CAN_IF2MSK2_MDIR 0x00004000 // Mask Message Direction
#define CAN_IF2MSK2_IDMSK_M 0x00001FFF // Identifier Mask
#define CAN_IF2MSK2_IDMSK_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF2ARB1 register.
//
//*****************************************************************************
#define CAN_IF2ARB1_ID_M 0x0000FFFF // Message Identifier
#define CAN_IF2ARB1_ID_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF2ARB2 register.
//
//*****************************************************************************
#define CAN_IF2ARB2_MSGVAL 0x00008000 // Message Valid
#define CAN_IF2ARB2_XTD 0x00004000 // Extended Identifier
#define CAN_IF2ARB2_DIR 0x00002000 // Message Direction
#define CAN_IF2ARB2_ID_M 0x00001FFF // Message Identifier
#define CAN_IF2ARB2_ID_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF2MCTL register.
//
//*****************************************************************************
#define CAN_IF2MCTL_NEWDAT 0x00008000 // New Data
#define CAN_IF2MCTL_MSGLST 0x00004000 // Message Lost
#define CAN_IF2MCTL_INTPND 0x00002000 // Interrupt Pending
#define CAN_IF2MCTL_UMASK 0x00001000 // Use Acceptance Mask
#define CAN_IF2MCTL_TXIE 0x00000800 // Transmit Interrupt Enable
#define CAN_IF2MCTL_RXIE 0x00000400 // Receive Interrupt Enable
#define CAN_IF2MCTL_RMTEN 0x00000200 // Remote Enable
#define CAN_IF2MCTL_TXRQST 0x00000100 // Transmit Request
#define CAN_IF2MCTL_EOB 0x00000080 // End of Buffer
#define CAN_IF2MCTL_DLC_M 0x0000000F // Data Length Code
#define CAN_IF2MCTL_DLC_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF2DA1 register.
//
//*****************************************************************************
#define CAN_IF2DA1_DATA_M 0x0000FFFF // Data
#define CAN_IF2DA1_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF2DA2 register.
//
//*****************************************************************************
#define CAN_IF2DA2_DATA_M 0x0000FFFF // Data
#define CAN_IF2DA2_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF2DB1 register.
//
//*****************************************************************************
#define CAN_IF2DB1_DATA_M 0x0000FFFF // Data
#define CAN_IF2DB1_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF2DB2 register.
//
//*****************************************************************************
#define CAN_IF2DB2_DATA_M 0x0000FFFF // Data
#define CAN_IF2DB2_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_TXRQ1 register.
//
//*****************************************************************************
#define CAN_TXRQ1_TXRQST_M 0x0000FFFF // Transmission Request Bits
#define CAN_TXRQ1_TXRQST_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_TXRQ2 register.
//
//*****************************************************************************
#define CAN_TXRQ2_TXRQST_M 0x0000FFFF // Transmission Request Bits
#define CAN_TXRQ2_TXRQST_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_NWDA1 register.
//
//*****************************************************************************
#define CAN_NWDA1_NEWDAT_M 0x0000FFFF // New Data Bits
#define CAN_NWDA1_NEWDAT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_NWDA2 register.
//
//*****************************************************************************
#define CAN_NWDA2_NEWDAT_M 0x0000FFFF // New Data Bits
#define CAN_NWDA2_NEWDAT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_MSG1INT register.
//
//*****************************************************************************
#define CAN_MSG1INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits
#define CAN_MSG1INT_INTPND_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_MSG2INT register.
//
//*****************************************************************************
#define CAN_MSG2INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits
#define CAN_MSG2INT_INTPND_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_MSG1VAL register.
//
//*****************************************************************************
#define CAN_MSG1VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits
#define CAN_MSG1VAL_MSGVAL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_MSG2VAL register.
//
//*****************************************************************************
#define CAN_MSG2VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits
#define CAN_MSG2VAL_MSGVAL_S 0
#endif // __HW_CAN_H__

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//*****************************************************************************
//
// hw_ccm.h - Macros used when accessing the CCM hardware.
//
// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_CCM_H__
#define __HW_CCM_H__
//*****************************************************************************
//
// The following are defines for the EC register offsets.
//
//*****************************************************************************
#define CCM_O_CRCCTRL 0x00000400 // CRC Control
#define CCM_O_CRCSEED 0x00000410 // CRC SEED/Context
#define CCM_O_CRCDIN 0x00000414 // CRC Data Input
#define CCM_O_CRCRSLTPP 0x00000418 // CRC Post Processing Result
//*****************************************************************************
//
// The following are defines for the bit fields in the CCM_O_CRCCTRL register.
//
//*****************************************************************************
#define CCM_CRCCTRL_INIT_M 0x00006000 // CRC Initialization
#define CCM_CRCCTRL_INIT_SEED 0x00000000 // Use the CRCSEED register context
// as the starting value
#define CCM_CRCCTRL_INIT_0 0x00004000 // Initialize to all '0s'
#define CCM_CRCCTRL_INIT_1 0x00006000 // Initialize to all '1s'
#define CCM_CRCCTRL_SIZE 0x00001000 // Input Data Size
#define CCM_CRCCTRL_RESINV 0x00000200 // Result Inverse Enable
#define CCM_CRCCTRL_OBR 0x00000100 // Output Reverse Enable
#define CCM_CRCCTRL_BR 0x00000080 // Bit reverse enable
#define CCM_CRCCTRL_ENDIAN_M 0x00000030 // Endian Control
#define CCM_CRCCTRL_ENDIAN_SBHW 0x00000000 // Configuration unchanged. (B3,
// B2, B1, B0)
#define CCM_CRCCTRL_ENDIAN_SHW 0x00000010 // Bytes are swapped in half-words
// but half-words are not swapped
// (B2, B3, B0, B1)
#define CCM_CRCCTRL_ENDIAN_SHWNB \
0x00000020 // Half-words are swapped but bytes
// are not swapped in half-word.
// (B1, B0, B3, B2)
#define CCM_CRCCTRL_ENDIAN_SBSW 0x00000030 // Bytes are swapped in half-words
// and half-words are swapped. (B0,
// B1, B2, B3)
#define CCM_CRCCTRL_TYPE_M 0x0000000F // Operation Type
#define CCM_CRCCTRL_TYPE_P8055 0x00000000 // Polynomial 0x8005
#define CCM_CRCCTRL_TYPE_P1021 0x00000001 // Polynomial 0x1021
#define CCM_CRCCTRL_TYPE_P4C11DB7 \
0x00000002 // Polynomial 0x4C11DB7
#define CCM_CRCCTRL_TYPE_P1EDC6F41 \
0x00000003 // Polynomial 0x1EDC6F41
#define CCM_CRCCTRL_TYPE_TCPCHKSUM \
0x00000008 // TCP checksum
//*****************************************************************************
//
// The following are defines for the bit fields in the CCM_O_CRCSEED register.
//
//*****************************************************************************
#define CCM_CRCSEED_SEED_M 0xFFFFFFFF // SEED/Context Value
#define CCM_CRCSEED_SEED_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CCM_O_CRCDIN register.
//
//*****************************************************************************
#define CCM_CRCDIN_DATAIN_M 0xFFFFFFFF // Data Input
#define CCM_CRCDIN_DATAIN_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CCM_O_CRCRSLTPP
// register.
//
//*****************************************************************************
#define CCM_CRCRSLTPP_RSLTPP_M 0xFFFFFFFF // Post Processing Result
#define CCM_CRCRSLTPP_RSLTPP_S 0
#endif // __HW_CCM_H__

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//*****************************************************************************
//
// hw_comp.h - Macros used when accessing the comparator hardware.
//
// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_COMP_H__
#define __HW_COMP_H__
//*****************************************************************************
//
// The following are defines for the Comparator register offsets.
//
//*****************************************************************************
#define COMP_O_ACMIS 0x00000000 // Analog Comparator Masked
// Interrupt Status
#define COMP_O_ACRIS 0x00000004 // Analog Comparator Raw Interrupt
// Status
#define COMP_O_ACINTEN 0x00000008 // Analog Comparator Interrupt
// Enable
#define COMP_O_ACREFCTL 0x00000010 // Analog Comparator Reference
// Voltage Control
#define COMP_O_ACSTAT0 0x00000020 // Analog Comparator Status 0
#define COMP_O_ACCTL0 0x00000024 // Analog Comparator Control 0
#define COMP_O_ACSTAT1 0x00000040 // Analog Comparator Status 1
#define COMP_O_ACCTL1 0x00000044 // Analog Comparator Control 1
#define COMP_O_ACSTAT2 0x00000060 // Analog Comparator Status 2
#define COMP_O_ACCTL2 0x00000064 // Analog Comparator Control 2
#define COMP_O_PP 0x00000FC0 // Analog Comparator Peripheral
// Properties
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_ACMIS register.
//
//*****************************************************************************
#define COMP_ACMIS_IN2 0x00000004 // Comparator 2 Masked Interrupt
// Status
#define COMP_ACMIS_IN1 0x00000002 // Comparator 1 Masked Interrupt
// Status
#define COMP_ACMIS_IN0 0x00000001 // Comparator 0 Masked Interrupt
// Status
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_ACRIS register.
//
//*****************************************************************************
#define COMP_ACRIS_IN2 0x00000004 // Comparator 2 Interrupt Status
#define COMP_ACRIS_IN1 0x00000002 // Comparator 1 Interrupt Status
#define COMP_ACRIS_IN0 0x00000001 // Comparator 0 Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_ACINTEN register.
//
//*****************************************************************************
#define COMP_ACINTEN_IN2 0x00000004 // Comparator 2 Interrupt Enable
#define COMP_ACINTEN_IN1 0x00000002 // Comparator 1 Interrupt Enable
#define COMP_ACINTEN_IN0 0x00000001 // Comparator 0 Interrupt Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_ACREFCTL
// register.
//
//*****************************************************************************
#define COMP_ACREFCTL_EN 0x00000200 // Resistor Ladder Enable
#define COMP_ACREFCTL_RNG 0x00000100 // Resistor Ladder Range
#define COMP_ACREFCTL_VREF_M 0x0000000F // Resistor Ladder Voltage Ref
#define COMP_ACREFCTL_VREF_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_ACSTAT0 register.
//
//*****************************************************************************
#define COMP_ACSTAT0_OVAL 0x00000002 // Comparator Output Value
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_ACCTL0 register.
//
//*****************************************************************************
#define COMP_ACCTL0_TOEN 0x00000800 // Trigger Output Enable
#define COMP_ACCTL0_ASRCP_M 0x00000600 // Analog Source Positive
#define COMP_ACCTL0_ASRCP_PIN 0x00000000 // Pin value of Cn+
#define COMP_ACCTL0_ASRCP_PIN0 0x00000200 // Pin value of C0+
#define COMP_ACCTL0_ASRCP_REF 0x00000400 // Internal voltage reference
#define COMP_ACCTL0_TSLVAL 0x00000080 // Trigger Sense Level Value
#define COMP_ACCTL0_TSEN_M 0x00000060 // Trigger Sense
#define COMP_ACCTL0_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
#define COMP_ACCTL0_TSEN_FALL 0x00000020 // Falling edge
#define COMP_ACCTL0_TSEN_RISE 0x00000040 // Rising edge
#define COMP_ACCTL0_TSEN_BOTH 0x00000060 // Either edge
#define COMP_ACCTL0_ISLVAL 0x00000010 // Interrupt Sense Level Value
#define COMP_ACCTL0_ISEN_M 0x0000000C // Interrupt Sense
#define COMP_ACCTL0_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
#define COMP_ACCTL0_ISEN_FALL 0x00000004 // Falling edge
#define COMP_ACCTL0_ISEN_RISE 0x00000008 // Rising edge
#define COMP_ACCTL0_ISEN_BOTH 0x0000000C // Either edge
#define COMP_ACCTL0_CINV 0x00000002 // Comparator Output Invert
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_ACSTAT1 register.
//
//*****************************************************************************
#define COMP_ACSTAT1_OVAL 0x00000002 // Comparator Output Value
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_ACCTL1 register.
//
//*****************************************************************************
#define COMP_ACCTL1_TOEN 0x00000800 // Trigger Output Enable
#define COMP_ACCTL1_ASRCP_M 0x00000600 // Analog Source Positive
#define COMP_ACCTL1_ASRCP_PIN 0x00000000 // Pin value of Cn+
#define COMP_ACCTL1_ASRCP_PIN0 0x00000200 // Pin value of C0+
#define COMP_ACCTL1_ASRCP_REF 0x00000400 // Internal voltage reference
#define COMP_ACCTL1_TSLVAL 0x00000080 // Trigger Sense Level Value
#define COMP_ACCTL1_TSEN_M 0x00000060 // Trigger Sense
#define COMP_ACCTL1_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
#define COMP_ACCTL1_TSEN_FALL 0x00000020 // Falling edge
#define COMP_ACCTL1_TSEN_RISE 0x00000040 // Rising edge
#define COMP_ACCTL1_TSEN_BOTH 0x00000060 // Either edge
#define COMP_ACCTL1_ISLVAL 0x00000010 // Interrupt Sense Level Value
#define COMP_ACCTL1_ISEN_M 0x0000000C // Interrupt Sense
#define COMP_ACCTL1_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
#define COMP_ACCTL1_ISEN_FALL 0x00000004 // Falling edge
#define COMP_ACCTL1_ISEN_RISE 0x00000008 // Rising edge
#define COMP_ACCTL1_ISEN_BOTH 0x0000000C // Either edge
#define COMP_ACCTL1_CINV 0x00000002 // Comparator Output Invert
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_ACSTAT2 register.
//
//*****************************************************************************
#define COMP_ACSTAT2_OVAL 0x00000002 // Comparator Output Value
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_ACCTL2 register.
//
//*****************************************************************************
#define COMP_ACCTL2_TOEN 0x00000800 // Trigger Output Enable
#define COMP_ACCTL2_ASRCP_M 0x00000600 // Analog Source Positive
#define COMP_ACCTL2_ASRCP_PIN 0x00000000 // Pin value of Cn+
#define COMP_ACCTL2_ASRCP_PIN0 0x00000200 // Pin value of C0+
#define COMP_ACCTL2_ASRCP_REF 0x00000400 // Internal voltage reference
#define COMP_ACCTL2_TSLVAL 0x00000080 // Trigger Sense Level Value
#define COMP_ACCTL2_TSEN_M 0x00000060 // Trigger Sense
#define COMP_ACCTL2_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
#define COMP_ACCTL2_TSEN_FALL 0x00000020 // Falling edge
#define COMP_ACCTL2_TSEN_RISE 0x00000040 // Rising edge
#define COMP_ACCTL2_TSEN_BOTH 0x00000060 // Either edge
#define COMP_ACCTL2_ISLVAL 0x00000010 // Interrupt Sense Level Value
#define COMP_ACCTL2_ISEN_M 0x0000000C // Interrupt Sense
#define COMP_ACCTL2_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
#define COMP_ACCTL2_ISEN_FALL 0x00000004 // Falling edge
#define COMP_ACCTL2_ISEN_RISE 0x00000008 // Rising edge
#define COMP_ACCTL2_ISEN_BOTH 0x0000000C // Either edge
#define COMP_ACCTL2_CINV 0x00000002 // Comparator Output Invert
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_PP register.
//
//*****************************************************************************
#define COMP_PP_C2O 0x00040000 // Comparator Output 2 Present
#define COMP_PP_C1O 0x00020000 // Comparator Output 1 Present
#define COMP_PP_C0O 0x00010000 // Comparator Output 0 Present
#define COMP_PP_CMP2 0x00000004 // Comparator 2 Present
#define COMP_PP_CMP1 0x00000002 // Comparator 1 Present
#define COMP_PP_CMP0 0x00000001 // Comparator 0 Present
#endif // __HW_COMP_H__

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//*****************************************************************************
//
// hw_des.h - Macros used when accessing the DES hardware.
//
// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_DES_H__
#define __HW_DES_H__
//*****************************************************************************
//
// The following are defines for the DES register offsets.
//
//*****************************************************************************
#define DES_O_KEY3_L 0x00000000 // DES Key 3 LSW for 192-Bit Key
#define DES_O_KEY3_H 0x00000004 // DES Key 3 MSW for 192-Bit Key
#define DES_O_KEY2_L 0x00000008 // DES Key 2 LSW for 128-Bit Key
#define DES_O_KEY2_H 0x0000000C // DES Key 2 MSW for 128-Bit Key
#define DES_O_KEY1_L 0x00000010 // DES Key 1 LSW for 64-Bit Key
#define DES_O_KEY1_H 0x00000014 // DES Key 1 MSW for 64-Bit Key
#define DES_O_IV_L 0x00000018 // DES Initialization Vector
#define DES_O_IV_H 0x0000001C // DES Initialization Vector
#define DES_O_CTRL 0x00000020 // DES Control
#define DES_O_LENGTH 0x00000024 // DES Cryptographic Data Length
#define DES_O_DATA_L 0x00000028 // DES LSW Data RW
#define DES_O_DATA_H 0x0000002C // DES MSW Data RW
#define DES_O_REVISION 0x00000030 // DES Revision Number
#define DES_O_SYSCONFIG 0x00000034 // DES System Configuration
#define DES_O_SYSSTATUS 0x00000038 // DES System Status
#define DES_O_IRQSTATUS 0x0000003C // DES Interrupt Status
#define DES_O_IRQENABLE 0x00000040 // DES Interrupt Enable
#define DES_O_DIRTYBITS 0x00000044 // DES Dirty Bits
#define DES_O_DMAIM 0xFFFF8030 // DES DMA Interrupt Mask
#define DES_O_DMARIS 0xFFFF8034 // DES DMA Raw Interrupt Status
#define DES_O_DMAMIS 0xFFFF8038 // DES DMA Masked Interrupt Status
#define DES_O_DMAIC 0xFFFF803C // DES DMA Interrupt Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the DES_O_KEY3_L register.
//
//*****************************************************************************
#define DES_KEY3_L_KEY_M 0xFFFFFFFF // Key Data
#define DES_KEY3_L_KEY_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the DES_O_KEY3_H register.
//
//*****************************************************************************
#define DES_KEY3_H_KEY_M 0xFFFFFFFF // Key Data
#define DES_KEY3_H_KEY_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the DES_O_KEY2_L register.
//
//*****************************************************************************
#define DES_KEY2_L_KEY_M 0xFFFFFFFF // Key Data
#define DES_KEY2_L_KEY_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the DES_O_KEY2_H register.
//
//*****************************************************************************
#define DES_KEY2_H_KEY_M 0xFFFFFFFF // Key Data
#define DES_KEY2_H_KEY_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the DES_O_KEY1_L register.
//
//*****************************************************************************
#define DES_KEY1_L_KEY_M 0xFFFFFFFF // Key Data
#define DES_KEY1_L_KEY_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the DES_O_KEY1_H register.
//
//*****************************************************************************
#define DES_KEY1_H_KEY_M 0xFFFFFFFF // Key Data
#define DES_KEY1_H_KEY_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the DES_O_IV_L register.
//
//*****************************************************************************
#define DES_IV_L_M 0xFFFFFFFF // Initialization vector for CBC,
// CFB modes (LSW)
#define DES_IV_L_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the DES_O_IV_H register.
//
//*****************************************************************************
#define DES_IV_H_M 0xFFFFFFFF // Initialization vector for CBC,
// CFB modes (MSW)
#define DES_IV_H_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the DES_O_CTRL register.
//
//*****************************************************************************
#define DES_CTRL_CONTEXT 0x80000000 // If 1, this read-only status bit
// indicates that the context data
// registers can be overwritten and
// the host is permitted to write
// the next context
#define DES_CTRL_MODE_M 0x00000030 // Select CBC, ECB or CFB mode0x0:
// ECB mode0x1: CBC mode0x2: CFB
// mode0x3: reserved
#define DES_CTRL_TDES 0x00000008 // Select DES or triple DES
// encryption/decryption
#define DES_CTRL_DIRECTION 0x00000004 // Select encryption/decryption
// 0x0: decryption is selected0x1:
// Encryption is selected
#define DES_CTRL_INPUT_READY 0x00000002 // When 1, ready to encrypt/decrypt
// data
#define DES_CTRL_OUTPUT_READY 0x00000001 // When 1, Data decrypted/encrypted
// ready
#define DES_CTRL_MODE_S 4
//*****************************************************************************
//
// The following are defines for the bit fields in the DES_O_LENGTH register.
//
//*****************************************************************************
#define DES_LENGTH_M 0xFFFFFFFF // Cryptographic data length in
// bytes for all modes
#define DES_LENGTH_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the DES_O_DATA_L register.
//
//*****************************************************************************
#define DES_DATA_L_M 0xFFFFFFFF // Data for encryption/decryption,
// LSW
#define DES_DATA_L_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the DES_O_DATA_H register.
//
//*****************************************************************************
#define DES_DATA_H_M 0xFFFFFFFF // Data for encryption/decryption,
// MSW
#define DES_DATA_H_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the DES_O_REVISION register.
//
//*****************************************************************************
#define DES_REVISION_M 0xFFFFFFFF // Revision number
#define DES_REVISION_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the DES_O_SYSCONFIG
// register.
//
//*****************************************************************************
#define DES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN \
0x00000080 // DMA Request Context In Enable
#define DES_SYSCONFIG_DMA_REQ_DATA_OUT_EN \
0x00000040 // DMA Request Data Out Enable
#define DES_SYSCONFIG_DMA_REQ_DATA_IN_EN \
0x00000020 // DMA Request Data In Enable
#define DES_SYSCONFIG_SIDLE_M 0x0000000C // Sidle mode
#define DES_SYSCONFIG_SIDLE_FORCE \
0x00000000 // Force-idle mode
#define DES_SYSCONFIG_SOFTRESET 0x00000002 // Soft reset
//*****************************************************************************
//
// The following are defines for the bit fields in the DES_O_SYSSTATUS
// register.
//
//*****************************************************************************
#define DES_SYSSTATUS_RESETDONE 0x00000001 // Reset Done
//*****************************************************************************
//
// The following are defines for the bit fields in the DES_O_IRQSTATUS
// register.
//
//*****************************************************************************
#define DES_IRQSTATUS_DATA_OUT 0x00000004 // This bit indicates data output
// interrupt is active and triggers
// the interrupt output
#define DES_IRQSTATUS_DATA_IN 0x00000002 // This bit indicates data input
// interrupt is active and triggers
// the interrupt output
#define DES_IRQSTATUS_CONTEX_IN 0x00000001 // This bit indicates context
// interrupt is active and triggers
// the interrupt output
//*****************************************************************************
//
// The following are defines for the bit fields in the DES_O_IRQENABLE
// register.
//
//*****************************************************************************
#define DES_IRQENABLE_M_DATA_OUT \
0x00000004 // If this bit is set to 1 the data
// output interrupt is enabled
#define DES_IRQENABLE_M_DATA_IN 0x00000002 // If this bit is set to 1 the data
// input interrupt is enabled
#define DES_IRQENABLE_M_CONTEX_IN \
0x00000001 // If this bit is set to 1 the
// context interrupt is enabled
//*****************************************************************************
//
// The following are defines for the bit fields in the DES_O_DIRTYBITS
// register.
//
//*****************************************************************************
#define DES_DIRTYBITS_S_DIRTY 0x00000002 // This bit is set to 1 by the
// module if any of the DES_*
// registers is written
#define DES_DIRTYBITS_S_ACCESS 0x00000001 // This bit is set to 1 by the
// module if any of the DES_*
// registers is read
//*****************************************************************************
//
// The following are defines for the bit fields in the DES_O_DMAIM register.
//
//*****************************************************************************
#define DES_DMAIM_DOUT 0x00000004 // Data Out DMA Done Interrupt Mask
#define DES_DMAIM_DIN 0x00000002 // Data In DMA Done Interrupt Mask
#define DES_DMAIM_CIN 0x00000001 // Context In DMA Done Interrupt
// Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the DES_O_DMARIS register.
//
//*****************************************************************************
#define DES_DMARIS_DOUT 0x00000004 // Data Out DMA Done Raw Interrupt
// Status
#define DES_DMARIS_DIN 0x00000002 // Data In DMA Done Raw Interrupt
// Status
#define DES_DMARIS_CIN 0x00000001 // Context In DMA Done Raw
// Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the DES_O_DMAMIS register.
//
//*****************************************************************************
#define DES_DMAMIS_DOUT 0x00000004 // Data Out DMA Done Masked
// Interrupt Status
#define DES_DMAMIS_DIN 0x00000002 // Data In DMA Done Masked
// Interrupt Status
#define DES_DMAMIS_CIN 0x00000001 // Context In DMA Done Raw
// Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the DES_O_DMAIC register.
//
//*****************************************************************************
#define DES_DMAIC_DOUT 0x00000004 // Data Out DMA Done Interrupt
// Clear
#define DES_DMAIC_DIN 0x00000002 // Data In DMA Done Interrupt Clear
#define DES_DMAIC_CIN 0x00000001 // Context In DMA Done Raw
// Interrupt Status
#endif // __HW_DES_H__

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//*****************************************************************************
//
// hw_eeprom.h - Macros used when accessing the EEPROM controller.
//
// Copyright (c) 2011-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_EEPROM_H__
#define __HW_EEPROM_H__
//*****************************************************************************
//
// The following are defines for the EEPROM register offsets.
//
//*****************************************************************************
#define EEPROM_EESIZE 0x400AF000 // EEPROM Size Information
#define EEPROM_EEBLOCK 0x400AF004 // EEPROM Current Block
#define EEPROM_EEOFFSET 0x400AF008 // EEPROM Current Offset
#define EEPROM_EERDWR 0x400AF010 // EEPROM Read-Write
#define EEPROM_EERDWRINC 0x400AF014 // EEPROM Read-Write with Increment
#define EEPROM_EEDONE 0x400AF018 // EEPROM Done Status
#define EEPROM_EESUPP 0x400AF01C // EEPROM Support Control and
// Status
#define EEPROM_EEUNLOCK 0x400AF020 // EEPROM Unlock
#define EEPROM_EEPROT 0x400AF030 // EEPROM Protection
#define EEPROM_EEPASS0 0x400AF034 // EEPROM Password
#define EEPROM_EEPASS1 0x400AF038 // EEPROM Password
#define EEPROM_EEPASS2 0x400AF03C // EEPROM Password
#define EEPROM_EEINT 0x400AF040 // EEPROM Interrupt
#define EEPROM_EEHIDE0 0x400AF050 // EEPROM Block Hide 0
#define EEPROM_EEHIDE 0x400AF050 // EEPROM Block Hide
#define EEPROM_EEHIDE1 0x400AF054 // EEPROM Block Hide 1
#define EEPROM_EEHIDE2 0x400AF058 // EEPROM Block Hide 2
#define EEPROM_EEDBGME 0x400AF080 // EEPROM Debug Mass Erase
#define EEPROM_PP 0x400AFFC0 // EEPROM Peripheral Properties
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EESIZE register.
//
//*****************************************************************************
#define EEPROM_EESIZE_WORDCNT_M 0x0000FFFF // Number of 32-Bit Words
#define EEPROM_EESIZE_BLKCNT_M 0x07FF0000 // Number of 16-Word Blocks
#define EEPROM_EESIZE_WORDCNT_S 0
#define EEPROM_EESIZE_BLKCNT_S 16
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EEBLOCK register.
//
//*****************************************************************************
#define EEPROM_EEBLOCK_BLOCK_M 0x0000FFFF // Current Block
#define EEPROM_EEBLOCK_BLOCK_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EEOFFSET
// register.
//
//*****************************************************************************
#define EEPROM_EEOFFSET_OFFSET_M \
0x0000000F // Current Address Offset
#define EEPROM_EEOFFSET_OFFSET_S \
0
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EERDWR register.
//
//*****************************************************************************
#define EEPROM_EERDWR_VALUE_M 0xFFFFFFFF // EEPROM Read or Write Data
#define EEPROM_EERDWR_VALUE_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EERDWRINC
// register.
//
//*****************************************************************************
#define EEPROM_EERDWRINC_VALUE_M \
0xFFFFFFFF // EEPROM Read or Write Data with
// Increment
#define EEPROM_EERDWRINC_VALUE_S \
0
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EEDONE register.
//
//*****************************************************************************
#define EEPROM_EEDONE_WORKING 0x00000001 // EEPROM Working
#define EEPROM_EEDONE_WKERASE 0x00000004 // Working on an Erase
#define EEPROM_EEDONE_WKCOPY 0x00000008 // Working on a Copy
#define EEPROM_EEDONE_NOPERM 0x00000010 // Write Without Permission
#define EEPROM_EEDONE_WRBUSY 0x00000020 // Write Busy
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EESUPP register.
//
//*****************************************************************************
#define EEPROM_EESUPP_ERETRY 0x00000004 // Erase Must Be Retried
#define EEPROM_EESUPP_PRETRY 0x00000008 // Programming Must Be Retried
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EEUNLOCK
// register.
//
//*****************************************************************************
#define EEPROM_EEUNLOCK_UNLOCK_M \
0xFFFFFFFF // EEPROM Unlock
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EEPROT register.
//
//*****************************************************************************
#define EEPROM_EEPROT_PROT_M 0x00000007 // Protection Control
#define EEPROM_EEPROT_PROT_RWNPW \
0x00000000 // This setting is the default. If
// there is no password, the block
// is not protected and is readable
// and writable
#define EEPROM_EEPROT_PROT_RWPW 0x00000001 // If there is a password, the
// block is readable or writable
// only when unlocked
#define EEPROM_EEPROT_PROT_RONPW \
0x00000002 // If there is no password, the
// block is readable, not writable
#define EEPROM_EEPROT_ACC 0x00000008 // Access Control
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EEPASS0 register.
//
//*****************************************************************************
#define EEPROM_EEPASS0_PASS_M 0xFFFFFFFF // Password
#define EEPROM_EEPASS0_PASS_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EEPASS1 register.
//
//*****************************************************************************
#define EEPROM_EEPASS1_PASS_M 0xFFFFFFFF // Password
#define EEPROM_EEPASS1_PASS_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EEPASS2 register.
//
//*****************************************************************************
#define EEPROM_EEPASS2_PASS_M 0xFFFFFFFF // Password
#define EEPROM_EEPASS2_PASS_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EEINT register.
//
//*****************************************************************************
#define EEPROM_EEINT_INT 0x00000001 // Interrupt Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EEHIDE0 register.
//
//*****************************************************************************
#define EEPROM_EEHIDE0_HN_M 0xFFFFFFFE // Hide Block
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EEHIDE register.
//
//*****************************************************************************
#define EEPROM_EEHIDE_HN_M 0xFFFFFFFE // Hide Block
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EEHIDE1 register.
//
//*****************************************************************************
#define EEPROM_EEHIDE1_HN_M 0xFFFFFFFF // Hide Block
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EEHIDE2 register.
//
//*****************************************************************************
#define EEPROM_EEHIDE2_HN_M 0xFFFFFFFF // Hide Block
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EEDBGME register.
//
//*****************************************************************************
#define EEPROM_EEDBGME_ME 0x00000001 // Mass Erase
#define EEPROM_EEDBGME_KEY_M 0xFFFF0000 // Erase Key
#define EEPROM_EEDBGME_KEY_S 16
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_PP register.
//
//*****************************************************************************
#define EEPROM_PP_SIZE_M 0x0000FFFF // EEPROM Size
#define EEPROM_PP_SIZE_64 0x00000000 // 64 bytes of EEPROM
#define EEPROM_PP_SIZE_128 0x00000001 // 128 bytes of EEPROM
#define EEPROM_PP_SIZE_256 0x00000003 // 256 bytes of EEPROM
#define EEPROM_PP_SIZE_512 0x00000007 // 512 bytes of EEPROM
#define EEPROM_PP_SIZE_1K 0x0000000F // 1 KB of EEPROM
#define EEPROM_PP_SIZE_2K 0x0000001F // 2 KB of EEPROM
#define EEPROM_PP_SIZE_3K 0x0000003F // 3 KB of EEPROM
#define EEPROM_PP_SIZE_4K 0x0000007F // 4 KB of EEPROM
#define EEPROM_PP_SIZE_5K 0x000000FF // 5 KB of EEPROM
#define EEPROM_PP_SIZE_6K 0x000001FF // 6 KB of EEPROM
#define EEPROM_PP_SIZE_S 0
#endif // __HW_EEPROM_H__

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//*****************************************************************************
//
// hw_epi.h - Macros for use in accessing the EPI registers.
//
// Copyright (c) 2008-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_EPI_H__
#define __HW_EPI_H__
//*****************************************************************************
//
// The following are defines for the External Peripheral Interface register
// offsets.
//
//*****************************************************************************
#define EPI_O_CFG 0x00000000 // EPI Configuration
#define EPI_O_BAUD 0x00000004 // EPI Main Baud Rate
#define EPI_O_BAUD2 0x00000008 // EPI Main Baud Rate
#define EPI_O_HB16CFG 0x00000010 // EPI Host-Bus 16 Configuration
#define EPI_O_GPCFG 0x00000010 // EPI General-Purpose
// Configuration
#define EPI_O_SDRAMCFG 0x00000010 // EPI SDRAM Configuration
#define EPI_O_HB8CFG 0x00000010 // EPI Host-Bus 8 Configuration
#define EPI_O_HB8CFG2 0x00000014 // EPI Host-Bus 8 Configuration 2
#define EPI_O_HB16CFG2 0x00000014 // EPI Host-Bus 16 Configuration 2
#define EPI_O_ADDRMAP 0x0000001C // EPI Address Map
#define EPI_O_RSIZE0 0x00000020 // EPI Read Size 0
#define EPI_O_RADDR0 0x00000024 // EPI Read Address 0
#define EPI_O_RPSTD0 0x00000028 // EPI Non-Blocking Read Data 0
#define EPI_O_RSIZE1 0x00000030 // EPI Read Size 1
#define EPI_O_RADDR1 0x00000034 // EPI Read Address 1
#define EPI_O_RPSTD1 0x00000038 // EPI Non-Blocking Read Data 1
#define EPI_O_STAT 0x00000060 // EPI Status
#define EPI_O_RFIFOCNT 0x0000006C // EPI Read FIFO Count
#define EPI_O_READFIFO0 0x00000070 // EPI Read FIFO
#define EPI_O_READFIFO1 0x00000074 // EPI Read FIFO Alias 1
#define EPI_O_READFIFO2 0x00000078 // EPI Read FIFO Alias 2
#define EPI_O_READFIFO3 0x0000007C // EPI Read FIFO Alias 3
#define EPI_O_READFIFO4 0x00000080 // EPI Read FIFO Alias 4
#define EPI_O_READFIFO5 0x00000084 // EPI Read FIFO Alias 5
#define EPI_O_READFIFO6 0x00000088 // EPI Read FIFO Alias 6
#define EPI_O_READFIFO7 0x0000008C // EPI Read FIFO Alias 7
#define EPI_O_FIFOLVL 0x00000200 // EPI FIFO Level Selects
#define EPI_O_WFIFOCNT 0x00000204 // EPI Write FIFO Count
#define EPI_O_DMATXCNT 0x00000208 // EPI DMA Transmit Count
#define EPI_O_IM 0x00000210 // EPI Interrupt Mask
#define EPI_O_RIS 0x00000214 // EPI Raw Interrupt Status
#define EPI_O_MIS 0x00000218 // EPI Masked Interrupt Status
#define EPI_O_EISC 0x0000021C // EPI Error and Interrupt Status
// and Clear
#define EPI_O_HB8CFG3 0x00000308 // EPI Host-Bus 8 Configuration 3
#define EPI_O_HB16CFG3 0x00000308 // EPI Host-Bus 16 Configuration 3
#define EPI_O_HB16CFG4 0x0000030C // EPI Host-Bus 16 Configuration 4
#define EPI_O_HB8CFG4 0x0000030C // EPI Host-Bus 8 Configuration 4
#define EPI_O_HB8TIME 0x00000310 // EPI Host-Bus 8 Timing Extension
#define EPI_O_HB16TIME 0x00000310 // EPI Host-Bus 16 Timing Extension
#define EPI_O_HB8TIME2 0x00000314 // EPI Host-Bus 8 Timing Extension
#define EPI_O_HB16TIME2 0x00000314 // EPI Host-Bus 16 Timing Extension
#define EPI_O_HB16TIME3 0x00000318 // EPI Host-Bus 16 Timing Extension
#define EPI_O_HB8TIME3 0x00000318 // EPI Host-Bus 8 Timing Extension
#define EPI_O_HB8TIME4 0x0000031C // EPI Host-Bus 8 Timing Extension
#define EPI_O_HB16TIME4 0x0000031C // EPI Host-Bus 16 Timing Extension
#define EPI_O_HBPSRAM 0x00000360 // EPI Host-Bus PSRAM
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_CFG register.
//
//*****************************************************************************
#define EPI_CFG_INTDIV 0x00000100 // Integer Clock Divider Enable
#define EPI_CFG_BLKEN 0x00000010 // Block Enable
#define EPI_CFG_MODE_M 0x0000000F // Mode Select
#define EPI_CFG_MODE_NONE 0x00000000 // General Purpose
#define EPI_CFG_MODE_SDRAM 0x00000001 // SDRAM
#define EPI_CFG_MODE_HB8 0x00000002 // 8-Bit Host-Bus (HB8)
#define EPI_CFG_MODE_HB16 0x00000003 // 16-Bit Host-Bus (HB16)
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_BAUD register.
//
//*****************************************************************************
#define EPI_BAUD_COUNT1_M 0xFFFF0000 // Baud Rate Counter 1
#define EPI_BAUD_COUNT0_M 0x0000FFFF // Baud Rate Counter 0
#define EPI_BAUD_COUNT1_S 16
#define EPI_BAUD_COUNT0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_BAUD2 register.
//
//*****************************************************************************
#define EPI_BAUD2_COUNT1_M 0xFFFF0000 // CS3n Baud Rate Counter 1
#define EPI_BAUD2_COUNT0_M 0x0000FFFF // CS2n Baud Rate Counter 0
#define EPI_BAUD2_COUNT1_S 16
#define EPI_BAUD2_COUNT0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_HB16CFG register.
//
//*****************************************************************************
#define EPI_HB16CFG_CLKGATE 0x80000000 // Clock Gated
#define EPI_HB16CFG_CLKGATEI 0x40000000 // Clock Gated Idle
#define EPI_HB16CFG_CLKINV 0x20000000 // Invert Output Clock Enable
#define EPI_HB16CFG_RDYEN 0x10000000 // Input Ready Enable
#define EPI_HB16CFG_IRDYINV 0x08000000 // Input Ready Invert
#define EPI_HB16CFG_XFFEN 0x00800000 // External FIFO FULL Enable
#define EPI_HB16CFG_XFEEN 0x00400000 // External FIFO EMPTY Enable
#define EPI_HB16CFG_WRHIGH 0x00200000 // WRITE Strobe Polarity
#define EPI_HB16CFG_RDHIGH 0x00100000 // READ Strobe Polarity
#define EPI_HB16CFG_ALEHIGH 0x00080000 // ALE Strobe Polarity
#define EPI_HB16CFG_WRCRE 0x00040000 // PSRAM Configuration Register
// Write
#define EPI_HB16CFG_RDCRE 0x00020000 // PSRAM Configuration Register
// Read
#define EPI_HB16CFG_BURST 0x00010000 // Burst Mode
#define EPI_HB16CFG_MAXWAIT_M 0x0000FF00 // Maximum Wait
#define EPI_HB16CFG_WRWS_M 0x000000C0 // Write Wait States
#define EPI_HB16CFG_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks
#define EPI_HB16CFG_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks
#define EPI_HB16CFG_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks
#define EPI_HB16CFG_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks
#define EPI_HB16CFG_RDWS_M 0x00000030 // Read Wait States
#define EPI_HB16CFG_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks
#define EPI_HB16CFG_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks
#define EPI_HB16CFG_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks
#define EPI_HB16CFG_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks
#define EPI_HB16CFG_BSEL 0x00000004 // Byte Select Configuration
#define EPI_HB16CFG_MODE_M 0x00000003 // Host Bus Sub-Mode
#define EPI_HB16CFG_MODE_ADMUX 0x00000000 // ADMUX - AD[15:0]
#define EPI_HB16CFG_MODE_ADNMUX 0x00000001 // ADNONMUX - D[15:0]
#define EPI_HB16CFG_MODE_SRAM 0x00000002 // Continuous Read - D[15:0]
#define EPI_HB16CFG_MODE_XFIFO 0x00000003 // XFIFO - D[15:0]
#define EPI_HB16CFG_MAXWAIT_S 8
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_GPCFG register.
//
//*****************************************************************************
#define EPI_GPCFG_CLKPIN 0x80000000 // Clock Pin
#define EPI_GPCFG_CLKGATE 0x40000000 // Clock Gated
#define EPI_GPCFG_FRM50 0x04000000 // 50/50 Frame
#define EPI_GPCFG_FRMCNT_M 0x03C00000 // Frame Count
#define EPI_GPCFG_WR2CYC 0x00080000 // 2-Cycle Writes
#define EPI_GPCFG_ASIZE_M 0x00000030 // Address Bus Size
#define EPI_GPCFG_ASIZE_NONE 0x00000000 // No address
#define EPI_GPCFG_ASIZE_4BIT 0x00000010 // Up to 4 bits wide
#define EPI_GPCFG_ASIZE_12BIT 0x00000020 // Up to 12 bits wide. This size
// cannot be used with 24-bit data
#define EPI_GPCFG_ASIZE_20BIT 0x00000030 // Up to 20 bits wide. This size
// cannot be used with data sizes
// other than 8
#define EPI_GPCFG_DSIZE_M 0x00000003 // Size of Data Bus
#define EPI_GPCFG_DSIZE_4BIT 0x00000000 // 8 Bits Wide (EPI0S0 to EPI0S7)
#define EPI_GPCFG_DSIZE_16BIT 0x00000001 // 16 Bits Wide (EPI0S0 to EPI0S15)
#define EPI_GPCFG_DSIZE_24BIT 0x00000002 // 24 Bits Wide (EPI0S0 to EPI0S23)
#define EPI_GPCFG_DSIZE_32BIT 0x00000003 // 32 Bits Wide (EPI0S0 to EPI0S31)
#define EPI_GPCFG_FRMCNT_S 22
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_SDRAMCFG register.
//
//*****************************************************************************
#define EPI_SDRAMCFG_FREQ_M 0xC0000000 // EPI Frequency Range
#define EPI_SDRAMCFG_FREQ_NONE 0x00000000 // 0 - 15 MHz
#define EPI_SDRAMCFG_FREQ_15MHZ 0x40000000 // 15 - 30 MHz
#define EPI_SDRAMCFG_FREQ_30MHZ 0x80000000 // 30 - 50 MHz
#define EPI_SDRAMCFG_RFSH_M 0x07FF0000 // Refresh Counter
#define EPI_SDRAMCFG_SLEEP 0x00000200 // Sleep Mode
#define EPI_SDRAMCFG_SIZE_M 0x00000003 // Size of SDRAM
#define EPI_SDRAMCFG_SIZE_8MB 0x00000000 // 64 megabits (8MB)
#define EPI_SDRAMCFG_SIZE_16MB 0x00000001 // 128 megabits (16MB)
#define EPI_SDRAMCFG_SIZE_32MB 0x00000002 // 256 megabits (32MB)
#define EPI_SDRAMCFG_SIZE_64MB 0x00000003 // 512 megabits (64MB)
#define EPI_SDRAMCFG_RFSH_S 16
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_HB8CFG register.
//
//*****************************************************************************
#define EPI_HB8CFG_CLKGATE 0x80000000 // Clock Gated
#define EPI_HB8CFG_CLKGATEI 0x40000000 // Clock Gated when Idle
#define EPI_HB8CFG_CLKINV 0x20000000 // Invert Output Clock Enable
#define EPI_HB8CFG_RDYEN 0x10000000 // Input Ready Enable
#define EPI_HB8CFG_IRDYINV 0x08000000 // Input Ready Invert
#define EPI_HB8CFG_XFFEN 0x00800000 // External FIFO FULL Enable
#define EPI_HB8CFG_XFEEN 0x00400000 // External FIFO EMPTY Enable
#define EPI_HB8CFG_WRHIGH 0x00200000 // WRITE Strobe Polarity
#define EPI_HB8CFG_RDHIGH 0x00100000 // READ Strobe Polarity
#define EPI_HB8CFG_ALEHIGH 0x00080000 // ALE Strobe Polarity
#define EPI_HB8CFG_MAXWAIT_M 0x0000FF00 // Maximum Wait
#define EPI_HB8CFG_WRWS_M 0x000000C0 // Write Wait States
#define EPI_HB8CFG_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks
#define EPI_HB8CFG_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks
#define EPI_HB8CFG_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks
#define EPI_HB8CFG_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks
#define EPI_HB8CFG_RDWS_M 0x00000030 // Read Wait States
#define EPI_HB8CFG_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks
#define EPI_HB8CFG_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks
#define EPI_HB8CFG_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks
#define EPI_HB8CFG_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks
#define EPI_HB8CFG_MODE_M 0x00000003 // Host Bus Sub-Mode
#define EPI_HB8CFG_MODE_MUX 0x00000000 // ADMUX - AD[7:0]
#define EPI_HB8CFG_MODE_NMUX 0x00000001 // ADNONMUX - D[7:0]
#define EPI_HB8CFG_MODE_SRAM 0x00000002 // Continuous Read - D[7:0]
#define EPI_HB8CFG_MODE_FIFO 0x00000003 // XFIFO - D[7:0]
#define EPI_HB8CFG_MAXWAIT_S 8
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_HB8CFG2 register.
//
//*****************************************************************************
#define EPI_HB8CFG2_CSCFGEXT 0x08000000 // Chip Select Extended
// Configuration
#define EPI_HB8CFG2_CSBAUD 0x04000000 // Chip Select Baud Rate and
// Multiple Sub-Mode Configuration
// enable
#define EPI_HB8CFG2_CSCFG_M 0x03000000 // Chip Select Configuration
#define EPI_HB8CFG2_CSCFG_ALE 0x00000000 // ALE Configuration
#define EPI_HB8CFG2_CSCFG_CS 0x01000000 // CSn Configuration
#define EPI_HB8CFG2_CSCFG_DCS 0x02000000 // Dual CSn Configuration
#define EPI_HB8CFG2_CSCFG_ADCS 0x03000000 // ALE with Dual CSn Configuration
#define EPI_HB8CFG2_WRHIGH 0x00200000 // CS1n WRITE Strobe Polarity
#define EPI_HB8CFG2_RDHIGH 0x00100000 // CS1n READ Strobe Polarity
#define EPI_HB8CFG2_ALEHIGH 0x00080000 // CS1n ALE Strobe Polarity
#define EPI_HB8CFG2_WRWS_M 0x000000C0 // CS1n Write Wait States
#define EPI_HB8CFG2_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks
#define EPI_HB8CFG2_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks
#define EPI_HB8CFG2_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks
#define EPI_HB8CFG2_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks
#define EPI_HB8CFG2_RDWS_M 0x00000030 // CS1n Read Wait States
#define EPI_HB8CFG2_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks
#define EPI_HB8CFG2_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks
#define EPI_HB8CFG2_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks
#define EPI_HB8CFG2_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks
#define EPI_HB8CFG2_MODE_M 0x00000003 // CS1n Host Bus Sub-Mode
#define EPI_HB8CFG2_MODE_ADMUX 0x00000000 // ADMUX - AD[7:0]
#define EPI_HB8CFG2_MODE_AD 0x00000001 // ADNONMUX - D[7:0]
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_HB16CFG2 register.
//
//*****************************************************************************
#define EPI_HB16CFG2_CSCFGEXT 0x08000000 // Chip Select Extended
// Configuration
#define EPI_HB16CFG2_CSBAUD 0x04000000 // Chip Select Baud Rate and
// Multiple Sub-Mode Configuration
// enable
#define EPI_HB16CFG2_CSCFG_M 0x03000000 // Chip Select Configuration
#define EPI_HB16CFG2_CSCFG_ALE 0x00000000 // ALE Configuration
#define EPI_HB16CFG2_CSCFG_CS 0x01000000 // CSn Configuration
#define EPI_HB16CFG2_CSCFG_DCS 0x02000000 // Dual CSn Configuration
#define EPI_HB16CFG2_CSCFG_ADCS 0x03000000 // ALE with Dual CSn Configuration
#define EPI_HB16CFG2_WRHIGH 0x00200000 // CS1n WRITE Strobe Polarity
#define EPI_HB16CFG2_RDHIGH 0x00100000 // CS1n READ Strobe Polarity
#define EPI_HB16CFG2_ALEHIGH 0x00080000 // CS1n ALE Strobe Polarity
#define EPI_HB16CFG2_WRCRE 0x00040000 // CS1n PSRAM Configuration
// Register Write
#define EPI_HB16CFG2_RDCRE 0x00020000 // CS1n PSRAM Configuration
// Register Read
#define EPI_HB16CFG2_BURST 0x00010000 // CS1n Burst Mode
#define EPI_HB16CFG2_WRWS_M 0x000000C0 // CS1n Write Wait States
#define EPI_HB16CFG2_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks
#define EPI_HB16CFG2_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks
#define EPI_HB16CFG2_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks
#define EPI_HB16CFG2_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks
#define EPI_HB16CFG2_RDWS_M 0x00000030 // CS1n Read Wait States
#define EPI_HB16CFG2_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks
#define EPI_HB16CFG2_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks
#define EPI_HB16CFG2_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks
#define EPI_HB16CFG2_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks
#define EPI_HB16CFG2_MODE_M 0x00000003 // CS1n Host Bus Sub-Mode
#define EPI_HB16CFG2_MODE_ADMUX 0x00000000 // ADMUX - AD[15:0]
#define EPI_HB16CFG2_MODE_AD 0x00000001 // ADNONMUX - D[15:0]
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_ADDRMAP register.
//
//*****************************************************************************
#define EPI_ADDRMAP_ECSZ_M 0x00000C00 // External Code Size
#define EPI_ADDRMAP_ECSZ_256B 0x00000000 // 256 bytes; lower address range:
// 0x00 to 0xFF
#define EPI_ADDRMAP_ECSZ_64KB 0x00000400 // 64 KB; lower address range:
// 0x0000 to 0xFFFF
#define EPI_ADDRMAP_ECSZ_16MB 0x00000800 // 16 MB; lower address range:
// 0x00.0000 to 0xFF.FFFF
#define EPI_ADDRMAP_ECSZ_256MB 0x00000C00 // 256MB; lower address range:
// 0x000.0000 to 0x0FFF.FFFF
#define EPI_ADDRMAP_ECADR_M 0x00000300 // External Code Address
#define EPI_ADDRMAP_ECADR_NONE 0x00000000 // Not mapped
#define EPI_ADDRMAP_ECADR_1000 0x00000100 // At 0x1000.0000
#define EPI_ADDRMAP_EPSZ_M 0x000000C0 // External Peripheral Size
#define EPI_ADDRMAP_EPSZ_256B 0x00000000 // 256 bytes; lower address range:
// 0x00 to 0xFF
#define EPI_ADDRMAP_EPSZ_64KB 0x00000040 // 64 KB; lower address range:
// 0x0000 to 0xFFFF
#define EPI_ADDRMAP_EPSZ_16MB 0x00000080 // 16 MB; lower address range:
// 0x00.0000 to 0xFF.FFFF
#define EPI_ADDRMAP_EPSZ_256MB 0x000000C0 // 256 MB; lower address range:
// 0x000.0000 to 0xFFF.FFFF
#define EPI_ADDRMAP_EPADR_M 0x00000030 // External Peripheral Address
#define EPI_ADDRMAP_EPADR_NONE 0x00000000 // Not mapped
#define EPI_ADDRMAP_EPADR_A000 0x00000010 // At 0xA000.0000
#define EPI_ADDRMAP_EPADR_C000 0x00000020 // At 0xC000.0000
#define EPI_ADDRMAP_EPADR_HBQS 0x00000030 // Only to be used with Host Bus
// quad chip select. In quad chip
// select mode, CS2n maps to
// 0xA000.0000 and CS3n maps to
// 0xC000.0000
#define EPI_ADDRMAP_ERSZ_M 0x0000000C // External RAM Size
#define EPI_ADDRMAP_ERSZ_256B 0x00000000 // 256 bytes; lower address range:
// 0x00 to 0xFF
#define EPI_ADDRMAP_ERSZ_64KB 0x00000004 // 64 KB; lower address range:
// 0x0000 to 0xFFFF
#define EPI_ADDRMAP_ERSZ_16MB 0x00000008 // 16 MB; lower address range:
// 0x00.0000 to 0xFF.FFFF
#define EPI_ADDRMAP_ERSZ_256MB 0x0000000C // 256 MB; lower address range:
// 0x000.0000 to 0xFFF.FFFF
#define EPI_ADDRMAP_ERADR_M 0x00000003 // External RAM Address
#define EPI_ADDRMAP_ERADR_NONE 0x00000000 // Not mapped
#define EPI_ADDRMAP_ERADR_6000 0x00000001 // At 0x6000.0000
#define EPI_ADDRMAP_ERADR_8000 0x00000002 // At 0x8000.0000
#define EPI_ADDRMAP_ERADR_HBQS 0x00000003 // Only to be used with Host Bus
// quad chip select. In quad chip
// select mode, CS0n maps to
// 0x6000.0000 and CS1n maps to
// 0x8000.0000
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_RSIZE0 register.
//
//*****************************************************************************
#define EPI_RSIZE0_SIZE_M 0x00000003 // Current Size
#define EPI_RSIZE0_SIZE_8BIT 0x00000001 // Byte (8 bits)
#define EPI_RSIZE0_SIZE_16BIT 0x00000002 // Half-word (16 bits)
#define EPI_RSIZE0_SIZE_32BIT 0x00000003 // Word (32 bits)
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_RADDR0 register.
//
//*****************************************************************************
#define EPI_RADDR0_ADDR_M 0xFFFFFFFF // Current Address
#define EPI_RADDR0_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_RPSTD0 register.
//
//*****************************************************************************
#define EPI_RPSTD0_POSTCNT_M 0x00001FFF // Post Count
#define EPI_RPSTD0_POSTCNT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_RSIZE1 register.
//
//*****************************************************************************
#define EPI_RSIZE1_SIZE_M 0x00000003 // Current Size
#define EPI_RSIZE1_SIZE_8BIT 0x00000001 // Byte (8 bits)
#define EPI_RSIZE1_SIZE_16BIT 0x00000002 // Half-word (16 bits)
#define EPI_RSIZE1_SIZE_32BIT 0x00000003 // Word (32 bits)
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_RADDR1 register.
//
//*****************************************************************************
#define EPI_RADDR1_ADDR_M 0xFFFFFFFF // Current Address
#define EPI_RADDR1_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_RPSTD1 register.
//
//*****************************************************************************
#define EPI_RPSTD1_POSTCNT_M 0x00001FFF // Post Count
#define EPI_RPSTD1_POSTCNT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_STAT register.
//
//*****************************************************************************
#define EPI_STAT_XFFULL 0x00000100 // External FIFO Full
#define EPI_STAT_XFEMPTY 0x00000080 // External FIFO Empty
#define EPI_STAT_INITSEQ 0x00000040 // Initialization Sequence
#define EPI_STAT_WBUSY 0x00000020 // Write Busy
#define EPI_STAT_NBRBUSY 0x00000010 // Non-Blocking Read Busy
#define EPI_STAT_ACTIVE 0x00000001 // Register Active
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_RFIFOCNT register.
//
//*****************************************************************************
#define EPI_RFIFOCNT_COUNT_M 0x0000000F // FIFO Count
#define EPI_RFIFOCNT_COUNT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_READFIFO0
// register.
//
//*****************************************************************************
#define EPI_READFIFO0_DATA_M 0xFFFFFFFF // Reads Data
#define EPI_READFIFO0_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_READFIFO1
// register.
//
//*****************************************************************************
#define EPI_READFIFO1_DATA_M 0xFFFFFFFF // Reads Data
#define EPI_READFIFO1_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_READFIFO2
// register.
//
//*****************************************************************************
#define EPI_READFIFO2_DATA_M 0xFFFFFFFF // Reads Data
#define EPI_READFIFO2_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_READFIFO3
// register.
//
//*****************************************************************************
#define EPI_READFIFO3_DATA_M 0xFFFFFFFF // Reads Data
#define EPI_READFIFO3_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_READFIFO4
// register.
//
//*****************************************************************************
#define EPI_READFIFO4_DATA_M 0xFFFFFFFF // Reads Data
#define EPI_READFIFO4_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_READFIFO5
// register.
//
//*****************************************************************************
#define EPI_READFIFO5_DATA_M 0xFFFFFFFF // Reads Data
#define EPI_READFIFO5_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_READFIFO6
// register.
//
//*****************************************************************************
#define EPI_READFIFO6_DATA_M 0xFFFFFFFF // Reads Data
#define EPI_READFIFO6_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_READFIFO7
// register.
//
//*****************************************************************************
#define EPI_READFIFO7_DATA_M 0xFFFFFFFF // Reads Data
#define EPI_READFIFO7_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_FIFOLVL register.
//
//*****************************************************************************
#define EPI_FIFOLVL_WFERR 0x00020000 // Write Full Error
#define EPI_FIFOLVL_RSERR 0x00010000 // Read Stall Error
#define EPI_FIFOLVL_WRFIFO_M 0x00000070 // Write FIFO
#define EPI_FIFOLVL_WRFIFO_EMPT 0x00000000 // Interrupt is triggered while
// WRFIFO is empty.
#define EPI_FIFOLVL_WRFIFO_2 0x00000020 // Interrupt is triggered until
// there are only two slots
// available. Thus, trigger is
// deasserted when there are two
// WRFIFO entries present. This
// configuration is optimized for
// bursts of 2
#define EPI_FIFOLVL_WRFIFO_1 0x00000030 // Interrupt is triggered until
// there is one WRFIFO entry
// available. This configuration
// expects only single writes
#define EPI_FIFOLVL_WRFIFO_NFULL \
0x00000040 // Trigger interrupt when WRFIFO is
// not full, meaning trigger will
// continue to assert until there
// are four entries in the WRFIFO
#define EPI_FIFOLVL_RDFIFO_M 0x00000007 // Read FIFO
#define EPI_FIFOLVL_RDFIFO_EMPT 0x00000000 // Empty
#define EPI_FIFOLVL_RDFIFO_1 0x00000001 // Trigger when there are 1 or more
// entries in the NBRFIFO
#define EPI_FIFOLVL_RDFIFO_2 0x00000002 // Trigger when there are 2 or more
// entries in the NBRFIFO
#define EPI_FIFOLVL_RDFIFO_4 0x00000003 // Trigger when there are 4 or more
// entries in the NBRFIFO
#define EPI_FIFOLVL_RDFIFO_6 0x00000004 // Trigger when there are 6 or more
// entries in the NBRFIFO
#define EPI_FIFOLVL_RDFIFO_7 0x00000005 // Trigger when there are 7 or more
// entries in the NBRFIFO
#define EPI_FIFOLVL_RDFIFO_8 0x00000006 // Trigger when there are 8 entries
// in the NBRFIFO
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_WFIFOCNT register.
//
//*****************************************************************************
#define EPI_WFIFOCNT_WTAV_M 0x00000007 // Available Write Transactions
#define EPI_WFIFOCNT_WTAV_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_DMATXCNT register.
//
//*****************************************************************************
#define EPI_DMATXCNT_TXCNT_M 0x0000FFFF // DMA Count
#define EPI_DMATXCNT_TXCNT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_IM register.
//
//*****************************************************************************
#define EPI_IM_DMAWRIM 0x00000010 // Write uDMA Interrupt Mask
#define EPI_IM_DMARDIM 0x00000008 // Read uDMA Interrupt Mask
#define EPI_IM_WRIM 0x00000004 // Write FIFO Empty Interrupt Mask
#define EPI_IM_RDIM 0x00000002 // Read FIFO Full Interrupt Mask
#define EPI_IM_ERRIM 0x00000001 // Error Interrupt Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_RIS register.
//
//*****************************************************************************
#define EPI_RIS_DMAWRRIS 0x00000010 // Write uDMA Raw Interrupt Status
#define EPI_RIS_DMARDRIS 0x00000008 // Read uDMA Raw Interrupt Status
#define EPI_RIS_WRRIS 0x00000004 // Write Raw Interrupt Status
#define EPI_RIS_RDRIS 0x00000002 // Read Raw Interrupt Status
#define EPI_RIS_ERRRIS 0x00000001 // Error Raw Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_MIS register.
//
//*****************************************************************************
#define EPI_MIS_DMAWRMIS 0x00000010 // Write uDMA Masked Interrupt
// Status
#define EPI_MIS_DMARDMIS 0x00000008 // Read uDMA Masked Interrupt
// Status
#define EPI_MIS_WRMIS 0x00000004 // Write Masked Interrupt Status
#define EPI_MIS_RDMIS 0x00000002 // Read Masked Interrupt Status
#define EPI_MIS_ERRMIS 0x00000001 // Error Masked Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_EISC register.
//
//*****************************************************************************
#define EPI_EISC_DMAWRIC 0x00000010 // Write uDMA Interrupt Clear
#define EPI_EISC_DMARDIC 0x00000008 // Read uDMA Interrupt Clear
#define EPI_EISC_WTFULL 0x00000004 // Write FIFO Full Error
#define EPI_EISC_RSTALL 0x00000002 // Read Stalled Error
#define EPI_EISC_TOUT 0x00000001 // Timeout Error
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_HB8CFG3 register.
//
//*****************************************************************************
#define EPI_HB8CFG3_WRHIGH 0x00200000 // CS2n WRITE Strobe Polarity
#define EPI_HB8CFG3_RDHIGH 0x00100000 // CS2n READ Strobe Polarity
#define EPI_HB8CFG3_ALEHIGH 0x00080000 // CS2n ALE Strobe Polarity
#define EPI_HB8CFG3_WRWS_M 0x000000C0 // CS2n Write Wait States
#define EPI_HB8CFG3_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks
#define EPI_HB8CFG3_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks
#define EPI_HB8CFG3_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks
#define EPI_HB8CFG3_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks
#define EPI_HB8CFG3_RDWS_M 0x00000030 // CS2n Read Wait States
#define EPI_HB8CFG3_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks
#define EPI_HB8CFG3_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks
#define EPI_HB8CFG3_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks
#define EPI_HB8CFG3_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks
#define EPI_HB8CFG3_MODE_M 0x00000003 // CS2n Host Bus Sub-Mode
#define EPI_HB8CFG3_MODE_ADMUX 0x00000000 // ADMUX - AD[7:0]
#define EPI_HB8CFG3_MODE_AD 0x00000001 // ADNONMUX - D[7:0]
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_HB16CFG3 register.
//
//*****************************************************************************
#define EPI_HB16CFG3_WRHIGH 0x00200000 // CS2n WRITE Strobe Polarity
#define EPI_HB16CFG3_RDHIGH 0x00100000 // CS2n READ Strobe Polarity
#define EPI_HB16CFG3_ALEHIGH 0x00080000 // CS2n ALE Strobe Polarity
#define EPI_HB16CFG3_WRCRE 0x00040000 // CS2n PSRAM Configuration
// Register Write
#define EPI_HB16CFG3_RDCRE 0x00020000 // CS2n PSRAM Configuration
// Register Read
#define EPI_HB16CFG3_BURST 0x00010000 // CS2n Burst Mode
#define EPI_HB16CFG3_WRWS_M 0x000000C0 // CS2n Write Wait States
#define EPI_HB16CFG3_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks
#define EPI_HB16CFG3_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks
#define EPI_HB16CFG3_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks
#define EPI_HB16CFG3_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks
#define EPI_HB16CFG3_RDWS_M 0x00000030 // CS2n Read Wait States
#define EPI_HB16CFG3_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks
#define EPI_HB16CFG3_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks
#define EPI_HB16CFG3_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks
#define EPI_HB16CFG3_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks
#define EPI_HB16CFG3_MODE_M 0x00000003 // CS2n Host Bus Sub-Mode
#define EPI_HB16CFG3_MODE_ADMUX 0x00000000 // ADMUX - AD[15:0]
#define EPI_HB16CFG3_MODE_AD 0x00000001 // ADNONMUX - D[15:0]
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_HB16CFG4 register.
//
//*****************************************************************************
#define EPI_HB16CFG4_WRHIGH 0x00200000 // CS3n WRITE Strobe Polarity
#define EPI_HB16CFG4_RDHIGH 0x00100000 // CS3n READ Strobe Polarity
#define EPI_HB16CFG4_ALEHIGH 0x00080000 // CS3n ALE Strobe Polarity
#define EPI_HB16CFG4_WRCRE 0x00040000 // CS3n PSRAM Configuration
// Register Write
#define EPI_HB16CFG4_RDCRE 0x00020000 // CS3n PSRAM Configuration
// Register Read
#define EPI_HB16CFG4_BURST 0x00010000 // CS3n Burst Mode
#define EPI_HB16CFG4_WRWS_M 0x000000C0 // CS3n Write Wait States
#define EPI_HB16CFG4_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks
#define EPI_HB16CFG4_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks
#define EPI_HB16CFG4_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks
#define EPI_HB16CFG4_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks
#define EPI_HB16CFG4_RDWS_M 0x00000030 // CS3n Read Wait States
#define EPI_HB16CFG4_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks
#define EPI_HB16CFG4_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks
#define EPI_HB16CFG4_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks
#define EPI_HB16CFG4_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks
#define EPI_HB16CFG4_MODE_M 0x00000003 // CS3n Host Bus Sub-Mode
#define EPI_HB16CFG4_MODE_ADMUX 0x00000000 // ADMUX - AD[15:0]
#define EPI_HB16CFG4_MODE_AD 0x00000001 // ADNONMUX - D[15:0]
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_HB8CFG4 register.
//
//*****************************************************************************
#define EPI_HB8CFG4_WRHIGH 0x00200000 // CS3n WRITE Strobe Polarity
#define EPI_HB8CFG4_RDHIGH 0x00100000 // CS2n READ Strobe Polarity
#define EPI_HB8CFG4_ALEHIGH 0x00080000 // CS3n ALE Strobe Polarity
#define EPI_HB8CFG4_WRWS_M 0x000000C0 // CS3n Write Wait States
#define EPI_HB8CFG4_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks
#define EPI_HB8CFG4_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks
#define EPI_HB8CFG4_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks
#define EPI_HB8CFG4_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks
#define EPI_HB8CFG4_RDWS_M 0x00000030 // CS3n Read Wait States
#define EPI_HB8CFG4_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks
#define EPI_HB8CFG4_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks
#define EPI_HB8CFG4_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks
#define EPI_HB8CFG4_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks
#define EPI_HB8CFG4_MODE_M 0x00000003 // CS3n Host Bus Sub-Mode
#define EPI_HB8CFG4_MODE_ADMUX 0x00000000 // ADMUX - AD[7:0]
#define EPI_HB8CFG4_MODE_AD 0x00000001 // ADNONMUX - D[7:0]
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_HB8TIME register.
//
//*****************************************************************************
#define EPI_HB8TIME_IRDYDLY_M 0x03000000 // CS0n Input Ready Delay
#define EPI_HB8TIME_CAPWIDTH_M 0x00003000 // CS0n Inter-transfer Capture
// Width
#define EPI_HB8TIME_WRWSM 0x00000010 // Write Wait State Minus One
#define EPI_HB8TIME_RDWSM 0x00000001 // Read Wait State Minus One
#define EPI_HB8TIME_IRDYDLY_S 24
#define EPI_HB8TIME_CAPWIDTH_S 12
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_HB16TIME register.
//
//*****************************************************************************
#define EPI_HB16TIME_IRDYDLY_M 0x03000000 // CS0n Input Ready Delay
#define EPI_HB16TIME_PSRAMSZ_M 0x00070000 // PSRAM Row Size
#define EPI_HB16TIME_PSRAMSZ_0 0x00000000 // No row size limitation
#define EPI_HB16TIME_PSRAMSZ_128B \
0x00010000 // 128 B
#define EPI_HB16TIME_PSRAMSZ_256B \
0x00020000 // 256 B
#define EPI_HB16TIME_PSRAMSZ_512B \
0x00030000 // 512 B
#define EPI_HB16TIME_PSRAMSZ_1KB \
0x00040000 // 1024 B
#define EPI_HB16TIME_PSRAMSZ_2KB \
0x00050000 // 2048 B
#define EPI_HB16TIME_PSRAMSZ_4KB \
0x00060000 // 4096 B
#define EPI_HB16TIME_PSRAMSZ_8KB \
0x00070000 // 8192 B
#define EPI_HB16TIME_CAPWIDTH_M 0x00003000 // CS0n Inter-transfer Capture
// Width
#define EPI_HB16TIME_WRWSM 0x00000010 // Write Wait State Minus One
#define EPI_HB16TIME_RDWSM 0x00000001 // Read Wait State Minus One
#define EPI_HB16TIME_IRDYDLY_S 24
#define EPI_HB16TIME_CAPWIDTH_S 12
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_HB8TIME2 register.
//
//*****************************************************************************
#define EPI_HB8TIME2_IRDYDLY_M 0x03000000 // CS1n Input Ready Delay
#define EPI_HB8TIME2_CAPWIDTH_M 0x00003000 // CS1n Inter-transfer Capture
// Width
#define EPI_HB8TIME2_WRWSM 0x00000010 // CS1n Write Wait State Minus One
#define EPI_HB8TIME2_RDWSM 0x00000001 // CS1n Read Wait State Minus One
#define EPI_HB8TIME2_IRDYDLY_S 24
#define EPI_HB8TIME2_CAPWIDTH_S 12
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_HB16TIME2
// register.
//
//*****************************************************************************
#define EPI_HB16TIME2_IRDYDLY_M 0x03000000 // CS1n Input Ready Delay
#define EPI_HB16TIME2_PSRAMSZ_M 0x00070000 // PSRAM Row Size
#define EPI_HB16TIME2_PSRAMSZ_0 0x00000000 // No row size limitation
#define EPI_HB16TIME2_PSRAMSZ_128B \
0x00010000 // 128 B
#define EPI_HB16TIME2_PSRAMSZ_256B \
0x00020000 // 256 B
#define EPI_HB16TIME2_PSRAMSZ_512B \
0x00030000 // 512 B
#define EPI_HB16TIME2_PSRAMSZ_1KB \
0x00040000 // 1024 B
#define EPI_HB16TIME2_PSRAMSZ_2KB \
0x00050000 // 2048 B
#define EPI_HB16TIME2_PSRAMSZ_4KB \
0x00060000 // 4096 B
#define EPI_HB16TIME2_PSRAMSZ_8KB \
0x00070000 // 8192 B
#define EPI_HB16TIME2_CAPWIDTH_M \
0x00003000 // CS1n Inter-transfer Capture
// Width
#define EPI_HB16TIME2_WRWSM 0x00000010 // CS1n Write Wait State Minus One
#define EPI_HB16TIME2_RDWSM 0x00000001 // CS1n Read Wait State Minus One
#define EPI_HB16TIME2_IRDYDLY_S 24
#define EPI_HB16TIME2_CAPWIDTH_S \
12
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_HB16TIME3
// register.
//
//*****************************************************************************
#define EPI_HB16TIME3_IRDYDLY_M 0x03000000 // CS2n Input Ready Delay
#define EPI_HB16TIME3_PSRAMSZ_M 0x00070000 // PSRAM Row Size
#define EPI_HB16TIME3_PSRAMSZ_0 0x00000000 // No row size limitation
#define EPI_HB16TIME3_PSRAMSZ_128B \
0x00010000 // 128 B
#define EPI_HB16TIME3_PSRAMSZ_256B \
0x00020000 // 256 B
#define EPI_HB16TIME3_PSRAMSZ_512B \
0x00030000 // 512 B
#define EPI_HB16TIME3_PSRAMSZ_1KB \
0x00040000 // 1024 B
#define EPI_HB16TIME3_PSRAMSZ_2KB \
0x00050000 // 2048 B
#define EPI_HB16TIME3_PSRAMSZ_4KB \
0x00060000 // 4096 B
#define EPI_HB16TIME3_PSRAMSZ_8KB \
0x00070000 // 8192 B
#define EPI_HB16TIME3_CAPWIDTH_M \
0x00003000 // CS2n Inter-transfer Capture
// Width
#define EPI_HB16TIME3_WRWSM 0x00000010 // CS2n Write Wait State Minus One
#define EPI_HB16TIME3_RDWSM 0x00000001 // CS2n Read Wait State Minus One
#define EPI_HB16TIME3_IRDYDLY_S 24
#define EPI_HB16TIME3_CAPWIDTH_S \
12
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_HB8TIME3 register.
//
//*****************************************************************************
#define EPI_HB8TIME3_IRDYDLY_M 0x03000000 // CS2n Input Ready Delay
#define EPI_HB8TIME3_CAPWIDTH_M 0x00003000 // CS2n Inter-transfer Capture
// Width
#define EPI_HB8TIME3_WRWSM 0x00000010 // CS2n Write Wait State Minus One
#define EPI_HB8TIME3_RDWSM 0x00000001 // CS2n Read Wait State Minus One
#define EPI_HB8TIME3_IRDYDLY_S 24
#define EPI_HB8TIME3_CAPWIDTH_S 12
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_HB8TIME4 register.
//
//*****************************************************************************
#define EPI_HB8TIME4_IRDYDLY_M 0x03000000 // CS3n Input Ready Delay
#define EPI_HB8TIME4_CAPWIDTH_M 0x00003000 // CS3n Inter-transfer Capture
// Width
#define EPI_HB8TIME4_WRWSM 0x00000010 // CS3n Write Wait State Minus One
#define EPI_HB8TIME4_RDWSM 0x00000001 // CS3n Read Wait State Minus One
#define EPI_HB8TIME4_IRDYDLY_S 24
#define EPI_HB8TIME4_CAPWIDTH_S 12
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_HB16TIME4
// register.
//
//*****************************************************************************
#define EPI_HB16TIME4_IRDYDLY_M 0x03000000 // CS3n Input Ready Delay
#define EPI_HB16TIME4_PSRAMSZ_M 0x00070000 // PSRAM Row Size
#define EPI_HB16TIME4_PSRAMSZ_0 0x00000000 // No row size limitation
#define EPI_HB16TIME4_PSRAMSZ_128B \
0x00010000 // 128 B
#define EPI_HB16TIME4_PSRAMSZ_256B \
0x00020000 // 256 B
#define EPI_HB16TIME4_PSRAMSZ_512B \
0x00030000 // 512 B
#define EPI_HB16TIME4_PSRAMSZ_1KB \
0x00040000 // 1024 B
#define EPI_HB16TIME4_PSRAMSZ_2KB \
0x00050000 // 2048 B
#define EPI_HB16TIME4_PSRAMSZ_4KB \
0x00060000 // 4096 B
#define EPI_HB16TIME4_PSRAMSZ_8KB \
0x00070000 // 8192 B
#define EPI_HB16TIME4_CAPWIDTH_M \
0x00003000 // CS3n Inter-transfer Capture
// Width
#define EPI_HB16TIME4_WRWSM 0x00000010 // CS3n Write Wait State Minus One
#define EPI_HB16TIME4_RDWSM 0x00000001 // CS3n Read Wait State Minus One
#define EPI_HB16TIME4_IRDYDLY_S 24
#define EPI_HB16TIME4_CAPWIDTH_S \
12
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_HBPSRAM register.
//
//*****************************************************************************
#define EPI_HBPSRAM_CR_M 0x001FFFFF // PSRAM Config Register
#define EPI_HBPSRAM_CR_S 0
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the EPI_O_FIFOLVL
// register.
//
//*****************************************************************************
#define EPI_FIFOLVL_WRFIFO_1_4 0x00000020 // Trigger when there are up to 3
// spaces available in the WFIFO
#define EPI_FIFOLVL_WRFIFO_1_2 0x00000030 // Trigger when there are up to 2
// spaces available in the WFIFO
#define EPI_FIFOLVL_WRFIFO_3_4 0x00000040 // Trigger when there is 1 space
// available in the WFIFO
#define EPI_FIFOLVL_RDFIFO_1_8 0x00000001 // Trigger when there are 1 or more
// entries in the NBRFIFO
#define EPI_FIFOLVL_RDFIFO_1_4 0x00000002 // Trigger when there are 2 or more
// entries in the NBRFIFO
#define EPI_FIFOLVL_RDFIFO_1_2 0x00000003 // Trigger when there are 4 or more
// entries in the NBRFIFO
#define EPI_FIFOLVL_RDFIFO_3_4 0x00000004 // Trigger when there are 6 or more
// entries in the NBRFIFO
#define EPI_FIFOLVL_RDFIFO_7_8 0x00000005 // Trigger when there are 7 or more
// entries in the NBRFIFO
#define EPI_FIFOLVL_RDFIFO_FULL 0x00000006 // Trigger when there are 8 entries
// in the NBRFIFO
#endif
#endif // __HW_EPI_H__

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//*****************************************************************************
//
// hw_fan.h - Macros used when accessing the fan control hardware.
//
// Copyright (c) 2010-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_FAN_H__
#define __HW_FAN_H__
//*****************************************************************************
//
// The following are defines for the Fan Control register offsets.
//
//*****************************************************************************
#endif // __HW_FAN_H__

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//*****************************************************************************
//
// hw_flash.h - Macros used when accessing the flash controller.
//
// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_FLASH_H__
#define __HW_FLASH_H__
//*****************************************************************************
//
// The following are defines for the FLASH register offsets.
//
//*****************************************************************************
#define FLASH_FMA 0x400FD000 // Flash Memory Address
#define FLASH_FMD 0x400FD004 // Flash Memory Data
#define FLASH_FMC 0x400FD008 // Flash Memory Control
#define FLASH_FCRIS 0x400FD00C // Flash Controller Raw Interrupt
// Status
#define FLASH_FCIM 0x400FD010 // Flash Controller Interrupt Mask
#define FLASH_FCMISC 0x400FD014 // Flash Controller Masked
// Interrupt Status and Clear
#define FLASH_FMC2 0x400FD020 // Flash Memory Control 2
#define FLASH_FWBVAL 0x400FD030 // Flash Write Buffer Valid
#define FLASH_FLPEKEY 0x400FD03C // Flash Program/Erase Key
#define FLASH_FWBN 0x400FD100 // Flash Write Buffer n
#define FLASH_PP 0x400FDFC0 // Flash Peripheral Properties
#define FLASH_FSIZE 0x400FDFC0 // Flash Size
#define FLASH_SSIZE 0x400FDFC4 // SRAM Size
#define FLASH_CONF 0x400FDFC8 // Flash Configuration Register
#define FLASH_ROMSWMAP 0x400FDFCC // ROM Software Map
#define FLASH_DMASZ 0x400FDFD0 // Flash DMA Address Size
#define FLASH_DMAST 0x400FDFD4 // Flash DMA Starting Address
#define FLASH_RVP 0x400FE0D4 // Reset Vector Pointer
#define FLASH_RMCTL 0x400FE0F0 // ROM Control
#define FLASH_BOOTCFG 0x400FE1D0 // Boot Configuration
#define FLASH_USERREG0 0x400FE1E0 // User Register 0
#define FLASH_USERREG1 0x400FE1E4 // User Register 1
#define FLASH_USERREG2 0x400FE1E8 // User Register 2
#define FLASH_USERREG3 0x400FE1EC // User Register 3
#define FLASH_FMPRE0 0x400FE200 // Flash Memory Protection Read
// Enable 0
#define FLASH_FMPRE1 0x400FE204 // Flash Memory Protection Read
// Enable 1
#define FLASH_FMPRE2 0x400FE208 // Flash Memory Protection Read
// Enable 2
#define FLASH_FMPRE3 0x400FE20C // Flash Memory Protection Read
// Enable 3
#define FLASH_FMPRE4 0x400FE210 // Flash Memory Protection Read
// Enable 4
#define FLASH_FMPRE5 0x400FE214 // Flash Memory Protection Read
// Enable 5
#define FLASH_FMPRE6 0x400FE218 // Flash Memory Protection Read
// Enable 6
#define FLASH_FMPRE7 0x400FE21C // Flash Memory Protection Read
// Enable 7
#define FLASH_FMPRE8 0x400FE220 // Flash Memory Protection Read
// Enable 8
#define FLASH_FMPRE9 0x400FE224 // Flash Memory Protection Read
// Enable 9
#define FLASH_FMPRE10 0x400FE228 // Flash Memory Protection Read
// Enable 10
#define FLASH_FMPRE11 0x400FE22C // Flash Memory Protection Read
// Enable 11
#define FLASH_FMPRE12 0x400FE230 // Flash Memory Protection Read
// Enable 12
#define FLASH_FMPRE13 0x400FE234 // Flash Memory Protection Read
// Enable 13
#define FLASH_FMPRE14 0x400FE238 // Flash Memory Protection Read
// Enable 14
#define FLASH_FMPRE15 0x400FE23C // Flash Memory Protection Read
// Enable 15
#define FLASH_FMPPE0 0x400FE400 // Flash Memory Protection Program
// Enable 0
#define FLASH_FMPPE1 0x400FE404 // Flash Memory Protection Program
// Enable 1
#define FLASH_FMPPE2 0x400FE408 // Flash Memory Protection Program
// Enable 2
#define FLASH_FMPPE3 0x400FE40C // Flash Memory Protection Program
// Enable 3
#define FLASH_FMPPE4 0x400FE410 // Flash Memory Protection Program
// Enable 4
#define FLASH_FMPPE5 0x400FE414 // Flash Memory Protection Program
// Enable 5
#define FLASH_FMPPE6 0x400FE418 // Flash Memory Protection Program
// Enable 6
#define FLASH_FMPPE7 0x400FE41C // Flash Memory Protection Program
// Enable 7
#define FLASH_FMPPE8 0x400FE420 // Flash Memory Protection Program
// Enable 8
#define FLASH_FMPPE9 0x400FE424 // Flash Memory Protection Program
// Enable 9
#define FLASH_FMPPE10 0x400FE428 // Flash Memory Protection Program
// Enable 10
#define FLASH_FMPPE11 0x400FE42C // Flash Memory Protection Program
// Enable 11
#define FLASH_FMPPE12 0x400FE430 // Flash Memory Protection Program
// Enable 12
#define FLASH_FMPPE13 0x400FE434 // Flash Memory Protection Program
// Enable 13
#define FLASH_FMPPE14 0x400FE438 // Flash Memory Protection Program
// Enable 14
#define FLASH_FMPPE15 0x400FE43C // Flash Memory Protection Program
// Enable 15
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FMA register.
//
//*****************************************************************************
#define FLASH_FMA_OFFSET_M 0x000FFFFF // Address Offset
#define FLASH_FMA_OFFSET_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FMD register.
//
//*****************************************************************************
#define FLASH_FMD_DATA_M 0xFFFFFFFF // Data Value
#define FLASH_FMD_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FMC register.
//
//*****************************************************************************
#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key
#define FLASH_FMC_COMT 0x00000008 // Commit Register Value
#define FLASH_FMC_MERASE 0x00000004 // Mass Erase Flash Memory
#define FLASH_FMC_ERASE 0x00000002 // Erase a Page of Flash Memory
#define FLASH_FMC_WRITE 0x00000001 // Write a Word into Flash Memory
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FCRIS register.
//
//*****************************************************************************
#define FLASH_FCRIS_PROGRIS 0x00002000 // Program Verify Error Raw
// Interrupt Status
#define FLASH_FCRIS_ERRIS 0x00000800 // Erase Verify Error Raw Interrupt
// Status
#define FLASH_FCRIS_INVDRIS 0x00000400 // Invalid Data Raw Interrupt
// Status
#define FLASH_FCRIS_VOLTRIS 0x00000200 // Pump Voltage Raw Interrupt
// Status
#define FLASH_FCRIS_ERIS 0x00000004 // EEPROM Raw Interrupt Status
#define FLASH_FCRIS_PRIS 0x00000002 // Programming Raw Interrupt Status
#define FLASH_FCRIS_ARIS 0x00000001 // Access Raw Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FCIM register.
//
//*****************************************************************************
#define FLASH_FCIM_PROGMASK 0x00002000 // PROGVER Interrupt Mask
#define FLASH_FCIM_ERMASK 0x00000800 // ERVER Interrupt Mask
#define FLASH_FCIM_INVDMASK 0x00000400 // Invalid Data Interrupt Mask
#define FLASH_FCIM_VOLTMASK 0x00000200 // VOLT Interrupt Mask
#define FLASH_FCIM_EMASK 0x00000004 // EEPROM Interrupt Mask
#define FLASH_FCIM_PMASK 0x00000002 // Programming Interrupt Mask
#define FLASH_FCIM_AMASK 0x00000001 // Access Interrupt Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FCMISC register.
//
//*****************************************************************************
#define FLASH_FCMISC_PROGMISC 0x00002000 // PROGVER Masked Interrupt Status
// and Clear
#define FLASH_FCMISC_ERMISC 0x00000800 // ERVER Masked Interrupt Status
// and Clear
#define FLASH_FCMISC_INVDMISC 0x00000400 // Invalid Data Masked Interrupt
// Status and Clear
#define FLASH_FCMISC_VOLTMISC 0x00000200 // VOLT Masked Interrupt Status and
// Clear
#define FLASH_FCMISC_EMISC 0x00000004 // EEPROM Masked Interrupt Status
// and Clear
#define FLASH_FCMISC_PMISC 0x00000002 // Programming Masked Interrupt
// Status and Clear
#define FLASH_FCMISC_AMISC 0x00000001 // Access Masked Interrupt Status
// and Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FMC2 register.
//
//*****************************************************************************
#define FLASH_FMC2_WRKEY 0xA4420000 // FLASH write key
#define FLASH_FMC2_WRBUF 0x00000001 // Buffered Flash Memory Write
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FWBVAL register.
//
//*****************************************************************************
#define FLASH_FWBVAL_FWB_M 0xFFFFFFFF // Flash Memory Write Buffer
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FLPEKEY register.
//
//*****************************************************************************
#define FLASH_FLPEKEY_PEKEY_M 0x0000FFFF // Key Value
#define FLASH_FLPEKEY_PEKEY_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FWBN register.
//
//*****************************************************************************
#define FLASH_FWBN_DATA_M 0xFFFFFFFF // Data
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_PP register.
//
//*****************************************************************************
#define FLASH_PP_PFC 0x40000000 // Prefetch Buffer Mode
#define FLASH_PP_FMM 0x20000000 // Flash Mirror Mode
#define FLASH_PP_DFA 0x10000000 // DMA Flash Access
#define FLASH_PP_EESS_M 0x00780000 // EEPROM Sector Size of the
// physical bank
#define FLASH_PP_EESS_1KB 0x00000000 // 1 KB
#define FLASH_PP_EESS_2KB 0x00080000 // 2 KB
#define FLASH_PP_EESS_4KB 0x00100000 // 4 KB
#define FLASH_PP_EESS_8KB 0x00180000 // 8 KB
#define FLASH_PP_MAINSS_M 0x00070000 // Flash Sector Size of the
// physical bank
#define FLASH_PP_MAINSS_1KB 0x00000000 // 1 KB
#define FLASH_PP_MAINSS_2KB 0x00010000 // 2 KB
#define FLASH_PP_MAINSS_4KB 0x00020000 // 4 KB
#define FLASH_PP_MAINSS_8KB 0x00030000 // 8 KB
#define FLASH_PP_MAINSS_16KB 0x00040000 // 16 KB
#define FLASH_PP_SIZE_M 0x0000FFFF // Flash Size
#define FLASH_PP_SIZE_512KB 0x000000FF // 512 KB of Flash
#define FLASH_PP_SIZE_1MB 0x000001FF // 1024 KB of Flash
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FSIZE register.
//
//*****************************************************************************
#define FLASH_FSIZE_SIZE_M 0x0000FFFF // Flash Size
#define FLASH_FSIZE_SIZE_32KB 0x0000000F // 32 KB of Flash
#define FLASH_FSIZE_SIZE_64KB 0x0000001F // 64 KB of Flash
#define FLASH_FSIZE_SIZE_128KB 0x0000003F // 128 KB of Flash
#define FLASH_FSIZE_SIZE_256KB 0x0000007F // 256 KB of Flash
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_SSIZE register.
//
//*****************************************************************************
#define FLASH_SSIZE_SIZE_M 0x0000FFFF // SRAM Size
#define FLASH_SSIZE_SIZE_12KB 0x0000002F // 12 KB of SRAM
#define FLASH_SSIZE_SIZE_24KB 0x0000005F // 24 KB of SRAM
#define FLASH_SSIZE_SIZE_32KB 0x0000007F // 32 KB of SRAM
#define FLASH_SSIZE_SIZE_256KB 0x000003FF // 256 KB of SRAM
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_CONF register.
//
//*****************************************************************************
#define FLASH_CONF_FMME 0x40000000 // Flash Mirror Mode Enable
#define FLASH_CONF_SPFE 0x20000000 // Single Prefetch Mode Enable
#define FLASH_CONF_CLRTV 0x00100000 // Clear Valid Tags
#define FLASH_CONF_FPFON 0x00020000 // Force Prefetch On
#define FLASH_CONF_FPFOFF 0x00010000 // Force Prefetch Off
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_ROMSWMAP register.
//
//*****************************************************************************
#define FLASH_ROMSWMAP_SAFERTOS 0x00000001 // SafeRTOS Present
#define FLASH_ROMSWMAP_SW0EN_M 0x00000003 // ROM SW Region 0 Availability
#define FLASH_ROMSWMAP_SW0EN_NOTVIS \
0x00000000 // Software region not available to
// the core
#define FLASH_ROMSWMAP_SW0EN_CORE \
0x00000001 // Region available to core
#define FLASH_ROMSWMAP_SW1EN_M 0x0000000C // ROM SW Region 1 Availability
#define FLASH_ROMSWMAP_SW1EN_NOTVIS \
0x00000000 // Software region not available to
// the core
#define FLASH_ROMSWMAP_SW1EN_CORE \
0x00000004 // Region available to core
#define FLASH_ROMSWMAP_SW2EN_M 0x00000030 // ROM SW Region 2 Availability
#define FLASH_ROMSWMAP_SW2EN_NOTVIS \
0x00000000 // Software region not available to
// the core
#define FLASH_ROMSWMAP_SW2EN_CORE \
0x00000010 // Region available to core
#define FLASH_ROMSWMAP_SW3EN_M 0x000000C0 // ROM SW Region 3 Availability
#define FLASH_ROMSWMAP_SW3EN_NOTVIS \
0x00000000 // Software region not available to
// the core
#define FLASH_ROMSWMAP_SW3EN_CORE \
0x00000040 // Region available to core
#define FLASH_ROMSWMAP_SW4EN_M 0x00000300 // ROM SW Region 4 Availability
#define FLASH_ROMSWMAP_SW4EN_NOTVIS \
0x00000000 // Software region not available to
// the core
#define FLASH_ROMSWMAP_SW4EN_CORE \
0x00000100 // Region available to core
#define FLASH_ROMSWMAP_SW5EN_M 0x00000C00 // ROM SW Region 5 Availability
#define FLASH_ROMSWMAP_SW5EN_NOTVIS \
0x00000000 // Software region not available to
// the core
#define FLASH_ROMSWMAP_SW5EN_CORE \
0x00000400 // Region available to core
#define FLASH_ROMSWMAP_SW6EN_M 0x00003000 // ROM SW Region 6 Availability
#define FLASH_ROMSWMAP_SW6EN_NOTVIS \
0x00000000 // Software region not available to
// the core
#define FLASH_ROMSWMAP_SW6EN_CORE \
0x00001000 // Region available to core
#define FLASH_ROMSWMAP_SW7EN_M 0x0000C000 // ROM SW Region 7 Availability
#define FLASH_ROMSWMAP_SW7EN_NOTVIS \
0x00000000 // Software region not available to
// the core
#define FLASH_ROMSWMAP_SW7EN_CORE \
0x00004000 // Region available to core
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_DMASZ register.
//
//*****************************************************************************
#define FLASH_DMASZ_SIZE_M 0x0003FFFF // uDMA-accessible Memory Size
#define FLASH_DMASZ_SIZE_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_DMAST register.
//
//*****************************************************************************
#define FLASH_DMAST_ADDR_M 0x1FFFF800 // Contains the starting address of
// the flash region accessible by
// uDMA if the FLASHPP register DFA
// bit is set
#define FLASH_DMAST_ADDR_S 11
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_RVP register.
//
//*****************************************************************************
#define FLASH_RVP_RV_M 0xFFFFFFFF // Reset Vector Pointer Address
#define FLASH_RVP_RV_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_RMCTL register.
//
//*****************************************************************************
#define FLASH_RMCTL_BA 0x00000001 // Boot Alias
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_BOOTCFG register.
//
//*****************************************************************************
#define FLASH_BOOTCFG_NW 0x80000000 // Not Written
#define FLASH_BOOTCFG_PORT_M 0x0000E000 // Boot GPIO Port
#define FLASH_BOOTCFG_PORT_A 0x00000000 // Port A
#define FLASH_BOOTCFG_PORT_B 0x00002000 // Port B
#define FLASH_BOOTCFG_PORT_C 0x00004000 // Port C
#define FLASH_BOOTCFG_PORT_D 0x00006000 // Port D
#define FLASH_BOOTCFG_PORT_E 0x00008000 // Port E
#define FLASH_BOOTCFG_PORT_F 0x0000A000 // Port F
#define FLASH_BOOTCFG_PORT_G 0x0000C000 // Port G
#define FLASH_BOOTCFG_PORT_H 0x0000E000 // Port H
#define FLASH_BOOTCFG_PIN_M 0x00001C00 // Boot GPIO Pin
#define FLASH_BOOTCFG_PIN_0 0x00000000 // Pin 0
#define FLASH_BOOTCFG_PIN_1 0x00000400 // Pin 1
#define FLASH_BOOTCFG_PIN_2 0x00000800 // Pin 2
#define FLASH_BOOTCFG_PIN_3 0x00000C00 // Pin 3
#define FLASH_BOOTCFG_PIN_4 0x00001000 // Pin 4
#define FLASH_BOOTCFG_PIN_5 0x00001400 // Pin 5
#define FLASH_BOOTCFG_PIN_6 0x00001800 // Pin 6
#define FLASH_BOOTCFG_PIN_7 0x00001C00 // Pin 7
#define FLASH_BOOTCFG_POL 0x00000200 // Boot GPIO Polarity
#define FLASH_BOOTCFG_EN 0x00000100 // Boot GPIO Enable
#define FLASH_BOOTCFG_KEY 0x00000010 // KEY Select
#define FLASH_BOOTCFG_DBG1 0x00000002 // Debug Control 1
#define FLASH_BOOTCFG_DBG0 0x00000001 // Debug Control 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_USERREG0 register.
//
//*****************************************************************************
#define FLASH_USERREG0_DATA_M 0xFFFFFFFF // User Data
#define FLASH_USERREG0_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_USERREG1 register.
//
//*****************************************************************************
#define FLASH_USERREG1_DATA_M 0xFFFFFFFF // User Data
#define FLASH_USERREG1_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_USERREG2 register.
//
//*****************************************************************************
#define FLASH_USERREG2_DATA_M 0xFFFFFFFF // User Data
#define FLASH_USERREG2_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_USERREG3 register.
//
//*****************************************************************************
#define FLASH_USERREG3_DATA_M 0xFFFFFFFF // User Data
#define FLASH_USERREG3_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FMPRE8 register.
//
//*****************************************************************************
#define FLASH_FMPRE8_READ_ENABLE_M \
0xFFFFFFFF // Flash Read Enable
#define FLASH_FMPRE8_READ_ENABLE_S \
0
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FMPRE9 register.
//
//*****************************************************************************
#define FLASH_FMPRE9_READ_ENABLE_M \
0xFFFFFFFF // Flash Read Enable
#define FLASH_FMPRE9_READ_ENABLE_S \
0
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FMPRE10 register.
//
//*****************************************************************************
#define FLASH_FMPRE10_READ_ENABLE_M \
0xFFFFFFFF // Flash Read Enable
#define FLASH_FMPRE10_READ_ENABLE_S \
0
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FMPRE11 register.
//
//*****************************************************************************
#define FLASH_FMPRE11_READ_ENABLE_M \
0xFFFFFFFF // Flash Read Enable
#define FLASH_FMPRE11_READ_ENABLE_S \
0
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FMPRE12 register.
//
//*****************************************************************************
#define FLASH_FMPRE12_READ_ENABLE_M \
0xFFFFFFFF // Flash Read Enable
#define FLASH_FMPRE12_READ_ENABLE_S \
0
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FMPRE13 register.
//
//*****************************************************************************
#define FLASH_FMPRE13_READ_ENABLE_M \
0xFFFFFFFF // Flash Read Enable
#define FLASH_FMPRE13_READ_ENABLE_S \
0
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FMPRE14 register.
//
//*****************************************************************************
#define FLASH_FMPRE14_READ_ENABLE_M \
0xFFFFFFFF // Flash Read Enable
#define FLASH_FMPRE14_READ_ENABLE_S \
0
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FMPRE15 register.
//
//*****************************************************************************
#define FLASH_FMPRE15_READ_ENABLE_M \
0xFFFFFFFF // Flash Read Enable
#define FLASH_FMPRE15_READ_ENABLE_S \
0
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FMPPE8 register.
//
//*****************************************************************************
#define FLASH_FMPPE8_PROG_ENABLE_M \
0xFFFFFFFF // Flash Programming Enable
#define FLASH_FMPPE8_PROG_ENABLE_S \
0
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FMPPE9 register.
//
//*****************************************************************************
#define FLASH_FMPPE9_PROG_ENABLE_M \
0xFFFFFFFF // Flash Programming Enable
#define FLASH_FMPPE9_PROG_ENABLE_S \
0
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FMPPE10 register.
//
//*****************************************************************************
#define FLASH_FMPPE10_PROG_ENABLE_M \
0xFFFFFFFF // Flash Programming Enable
#define FLASH_FMPPE10_PROG_ENABLE_S \
0
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FMPPE11 register.
//
//*****************************************************************************
#define FLASH_FMPPE11_PROG_ENABLE_M \
0xFFFFFFFF // Flash Programming Enable
#define FLASH_FMPPE11_PROG_ENABLE_S \
0
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FMPPE12 register.
//
//*****************************************************************************
#define FLASH_FMPPE12_PROG_ENABLE_M \
0xFFFFFFFF // Flash Programming Enable
#define FLASH_FMPPE12_PROG_ENABLE_S \
0
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FMPPE13 register.
//
//*****************************************************************************
#define FLASH_FMPPE13_PROG_ENABLE_M \
0xFFFFFFFF // Flash Programming Enable
#define FLASH_FMPPE13_PROG_ENABLE_S \
0
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FMPPE14 register.
//
//*****************************************************************************
#define FLASH_FMPPE14_PROG_ENABLE_M \
0xFFFFFFFF // Flash Programming Enable
#define FLASH_FMPPE14_PROG_ENABLE_S \
0
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FMPPE15 register.
//
//*****************************************************************************
#define FLASH_FMPPE15_PROG_ENABLE_M \
0xFFFFFFFF // Flash Programming Enable
#define FLASH_FMPPE15_PROG_ENABLE_S \
0
//*****************************************************************************
//
// The following are defines for the erase size of the FLASH block that is
// erased by an erase operation, and the protect size is the size of the FLASH
// block that is protected by each protection register.
//
//*****************************************************************************
#define FLASH_PROTECT_SIZE 0x00000800
#define FLASH_ERASE_SIZE 0x00000400
#endif // __HW_FLASH_H__

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@ -0,0 +1,213 @@
//*****************************************************************************
//
// hw_gpio.h - Defines and Macros for GPIO hardware.
//
// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_GPIO_H__
#define __HW_GPIO_H__
//*****************************************************************************
//
// The following are defines for the GPIO register offsets.
//
//*****************************************************************************
#define GPIO_O_DATA 0x00000000 // GPIO Data
#define GPIO_O_DIR 0x00000400 // GPIO Direction
#define GPIO_O_IS 0x00000404 // GPIO Interrupt Sense
#define GPIO_O_IBE 0x00000408 // GPIO Interrupt Both Edges
#define GPIO_O_IEV 0x0000040C // GPIO Interrupt Event
#define GPIO_O_IM 0x00000410 // GPIO Interrupt Mask
#define GPIO_O_RIS 0x00000414 // GPIO Raw Interrupt Status
#define GPIO_O_MIS 0x00000418 // GPIO Masked Interrupt Status
#define GPIO_O_ICR 0x0000041C // GPIO Interrupt Clear
#define GPIO_O_AFSEL 0x00000420 // GPIO Alternate Function Select
#define GPIO_O_DR2R 0x00000500 // GPIO 2-mA Drive Select
#define GPIO_O_DR4R 0x00000504 // GPIO 4-mA Drive Select
#define GPIO_O_DR8R 0x00000508 // GPIO 8-mA Drive Select
#define GPIO_O_ODR 0x0000050C // GPIO Open Drain Select
#define GPIO_O_PUR 0x00000510 // GPIO Pull-Up Select
#define GPIO_O_PDR 0x00000514 // GPIO Pull-Down Select
#define GPIO_O_SLR 0x00000518 // GPIO Slew Rate Control Select
#define GPIO_O_DEN 0x0000051C // GPIO Digital Enable
#define GPIO_O_LOCK 0x00000520 // GPIO Lock
#define GPIO_O_CR 0x00000524 // GPIO Commit
#define GPIO_O_AMSEL 0x00000528 // GPIO Analog Mode Select
#define GPIO_O_PCTL 0x0000052C // GPIO Port Control
#define GPIO_O_ADCCTL 0x00000530 // GPIO ADC Control
#define GPIO_O_DMACTL 0x00000534 // GPIO DMA Control
#define GPIO_O_SI 0x00000538 // GPIO Select Interrupt
#define GPIO_O_DR12R 0x0000053C // GPIO 12-mA Drive Select
#define GPIO_O_WAKEPEN 0x00000540 // GPIO Wake Pin Enable
#define GPIO_O_WAKELVL 0x00000544 // GPIO Wake Level
#define GPIO_O_WAKESTAT 0x00000548 // GPIO Wake Status
#define GPIO_O_PP 0x00000FC0 // GPIO Peripheral Property
#define GPIO_O_PC 0x00000FC4 // GPIO Peripheral Configuration
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_O_IM register.
//
//*****************************************************************************
#define GPIO_IM_DMAIME 0x00000100 // GPIO uDMA Done Interrupt Mask
// Enable
#define GPIO_IM_GPIO_M 0x000000FF // GPIO Interrupt Mask Enable
#define GPIO_IM_GPIO_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_O_RIS register.
//
//*****************************************************************************
#define GPIO_RIS_DMARIS 0x00000100 // GPIO uDMA Done Interrupt Raw
// Status
#define GPIO_RIS_GPIO_M 0x000000FF // GPIO Interrupt Raw Status
#define GPIO_RIS_GPIO_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_O_MIS register.
//
//*****************************************************************************
#define GPIO_MIS_DMAMIS 0x00000100 // GPIO uDMA Done Masked Interrupt
// Status
#define GPIO_MIS_GPIO_M 0x000000FF // GPIO Masked Interrupt Status
#define GPIO_MIS_GPIO_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_O_ICR register.
//
//*****************************************************************************
#define GPIO_ICR_DMAIC 0x00000100 // GPIO uDMA Interrupt Clear
#define GPIO_ICR_GPIO_M 0x000000FF // GPIO Interrupt Clear
#define GPIO_ICR_GPIO_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_O_LOCK register.
//
//*****************************************************************************
#define GPIO_LOCK_M 0xFFFFFFFF // GPIO Lock
#define GPIO_LOCK_UNLOCKED 0x00000000 // The GPIOCR register is unlocked
// and may be modified
#define GPIO_LOCK_LOCKED 0x00000001 // The GPIOCR register is locked
// and may not be modified
#define GPIO_LOCK_KEY 0x4C4F434B // Unlocks the GPIO_CR register
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_O_SI register.
//
//*****************************************************************************
#define GPIO_SI_SUM 0x00000001 // Summary Interrupt
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_O_DR12R register.
//
//*****************************************************************************
#define GPIO_DR12R_DRV12_M 0x000000FF // Output Pad 12-mA Drive Enable
#define GPIO_DR12R_DRV12_12MA 0x00000001 // The corresponding GPIO pin has
// 12-mA drive. This encoding is
// only valid if the GPIOPP EDE bit
// is set and the appropriate
// GPIOPC EDM bit field is
// programmed to 0x3
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_O_WAKEPEN register.
//
//*****************************************************************************
#define GPIO_WAKEPEN_WAKEP4 0x00000010 // P[4] Wake Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_O_WAKELVL register.
//
//*****************************************************************************
#define GPIO_WAKELVL_WAKELVL4 0x00000010 // P[4] Wake Level
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_O_WAKESTAT
// register.
//
//*****************************************************************************
#define GPIO_WAKESTAT_STAT4 0x00000010 // P[4] Wake Status
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_O_PP register.
//
//*****************************************************************************
#define GPIO_PP_EDE 0x00000001 // Extended Drive Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_O_PC register.
//
//*****************************************************************************
#define GPIO_PC_EDM7_M 0x0000C000 // Extended Drive Mode Bit 7
#define GPIO_PC_EDM6_M 0x00003000 // Extended Drive Mode Bit 6
#define GPIO_PC_EDM5_M 0x00000C00 // Extended Drive Mode Bit 5
#define GPIO_PC_EDM4_M 0x00000300 // Extended Drive Mode Bit 4
#define GPIO_PC_EDM3_M 0x000000C0 // Extended Drive Mode Bit 3
#define GPIO_PC_EDM2_M 0x00000030 // Extended Drive Mode Bit 2
#define GPIO_PC_EDM1_M 0x0000000C // Extended Drive Mode Bit 1
#define GPIO_PC_EDM0_M 0x00000003 // Extended Drive Mode Bit 0
#define GPIO_PC_EDM0_DISABLE 0x00000000 // Drive values of 2, 4 and 8 mA
// are maintained. GPIO n Drive
// Select (GPIODRnR) registers
// function as normal
#define GPIO_PC_EDM0_6MA 0x00000001 // An additional 6 mA option is
// provided
#define GPIO_PC_EDM0_PLUS2MA 0x00000003 // A 2 mA driver is always enabled;
// setting the corresponding
// GPIODR4R register bit adds 2 mA
// and setting the corresponding
// GPIODR8R of GPIODR12R register
// bit adds an additional 4 mA
#define GPIO_PC_EDM7_S 14
#define GPIO_PC_EDM6_S 12
#define GPIO_PC_EDM5_S 10
#define GPIO_PC_EDM4_S 8
#define GPIO_PC_EDM3_S 6
#define GPIO_PC_EDM2_S 4
#define GPIO_PC_EDM1_S 2
#endif // __HW_GPIO_H__

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//*****************************************************************************
//
// hw_hibernate.h - Defines and Macros for the Hibernation module.
//
// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_HIBERNATE_H__
#define __HW_HIBERNATE_H__
//*****************************************************************************
//
// The following are defines for the Hibernation module register addresses.
//
//*****************************************************************************
#define HIB_RTCC 0x400FC000 // Hibernation RTC Counter
#define HIB_RTCM0 0x400FC004 // Hibernation RTC Match 0
#define HIB_RTCLD 0x400FC00C // Hibernation RTC Load
#define HIB_CTL 0x400FC010 // Hibernation Control
#define HIB_IM 0x400FC014 // Hibernation Interrupt Mask
#define HIB_RIS 0x400FC018 // Hibernation Raw Interrupt Status
#define HIB_MIS 0x400FC01C // Hibernation Masked Interrupt
// Status
#define HIB_IC 0x400FC020 // Hibernation Interrupt Clear
#define HIB_RTCT 0x400FC024 // Hibernation RTC Trim
#define HIB_RTCSS 0x400FC028 // Hibernation RTC Sub Seconds
#define HIB_IO 0x400FC02C // Hibernation IO Configuration
#define HIB_DATA 0x400FC030 // Hibernation Data
#define HIB_CALCTL 0x400FC300 // Hibernation Calendar Control
#define HIB_CAL0 0x400FC310 // Hibernation Calendar 0
#define HIB_CAL1 0x400FC314 // Hibernation Calendar 1
#define HIB_CALLD0 0x400FC320 // Hibernation Calendar Load 0
#define HIB_CALLD1 0x400FC324 // Hibernation Calendar Load
#define HIB_CALM0 0x400FC330 // Hibernation Calendar Match 0
#define HIB_CALM1 0x400FC334 // Hibernation Calendar Match 1
#define HIB_LOCK 0x400FC360 // Hibernation Lock
#define HIB_TPCTL 0x400FC400 // HIB Tamper Control
#define HIB_TPSTAT 0x400FC404 // HIB Tamper Status
#define HIB_TPIO 0x400FC410 // HIB Tamper I/O Control
#define HIB_TPLOG0 0x400FC4E0 // HIB Tamper Log 0
#define HIB_TPLOG1 0x400FC4E4 // HIB Tamper Log 1
#define HIB_TPLOG2 0x400FC4E8 // HIB Tamper Log 2
#define HIB_TPLOG3 0x400FC4EC // HIB Tamper Log 3
#define HIB_TPLOG4 0x400FC4F0 // HIB Tamper Log 4
#define HIB_TPLOG5 0x400FC4F4 // HIB Tamper Log 5
#define HIB_TPLOG6 0x400FC4F8 // HIB Tamper Log 6
#define HIB_TPLOG7 0x400FC4FC // HIB Tamper Log 7
#define HIB_PP 0x400FCFC0 // Hibernation Peripheral
// Properties
#define HIB_CC 0x400FCFC8 // Hibernation Clock Control
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_RTCC register.
//
//*****************************************************************************
#define HIB_RTCC_M 0xFFFFFFFF // RTC Counter
#define HIB_RTCC_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_RTCM0 register.
//
//*****************************************************************************
#define HIB_RTCM0_M 0xFFFFFFFF // RTC Match 0
#define HIB_RTCM0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_RTCLD register.
//
//*****************************************************************************
#define HIB_RTCLD_M 0xFFFFFFFF // RTC Load
#define HIB_RTCLD_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_CTL register.
//
//*****************************************************************************
#define HIB_CTL_WRC 0x80000000 // Write Complete/Capable
#define HIB_CTL_RETCLR 0x40000000 // GPIO Retention/Clear
#define HIB_CTL_OSCSEL 0x00080000 // Oscillator Select
#define HIB_CTL_OSCDRV 0x00020000 // Oscillator Drive Capability
#define HIB_CTL_OSCBYP 0x00010000 // Oscillator Bypass
#define HIB_CTL_VBATSEL_M 0x00006000 // Select for Low-Battery
// Comparator
#define HIB_CTL_VBATSEL_1_9V 0x00000000 // 1.9 Volts
#define HIB_CTL_VBATSEL_2_1V 0x00002000 // 2.1 Volts (default)
#define HIB_CTL_VBATSEL_2_3V 0x00004000 // 2.3 Volts
#define HIB_CTL_VBATSEL_2_5V 0x00006000 // 2.5 Volts
#define HIB_CTL_BATCHK 0x00000400 // Check Battery Status
#define HIB_CTL_BATWKEN 0x00000200 // Wake on Low Battery
#define HIB_CTL_VDD3ON 0x00000100 // VDD Powered
#define HIB_CTL_VABORT 0x00000080 // Power Cut Abort Enable
#define HIB_CTL_CLK32EN 0x00000040 // Clocking Enable
#define HIB_CTL_PINWEN 0x00000010 // External Wake Pin Enable
#define HIB_CTL_RTCWEN 0x00000008 // RTC Wake-up Enable
#define HIB_CTL_HIBREQ 0x00000002 // Hibernation Request
#define HIB_CTL_RTCEN 0x00000001 // RTC Timer Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_IM register.
//
//*****************************************************************************
#define HIB_IM_VDDFAIL 0x00000080 // VDD Fail Interrupt Mask
#define HIB_IM_RSTWK 0x00000040 // Reset Pad I/O Wake-Up Interrupt
// Mask
#define HIB_IM_PADIOWK 0x00000020 // Pad I/O Wake-Up Interrupt Mask
#define HIB_IM_WC 0x00000010 // External Write Complete/Capable
// Interrupt Mask
#define HIB_IM_EXTW 0x00000008 // External Wake-Up Interrupt Mask
#define HIB_IM_LOWBAT 0x00000004 // Low Battery Voltage Interrupt
// Mask
#define HIB_IM_RTCALT0 0x00000001 // RTC Alert 0 Interrupt Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_RIS register.
//
//*****************************************************************************
#define HIB_RIS_VDDFAIL 0x00000080 // VDD Fail Raw Interrupt Status
#define HIB_RIS_RSTWK 0x00000040 // Reset Pad I/O Wake-Up Raw
// Interrupt Status
#define HIB_RIS_PADIOWK 0x00000020 // Pad I/O Wake-Up Raw Interrupt
// Status
#define HIB_RIS_WC 0x00000010 // Write Complete/Capable Raw
// Interrupt Status
#define HIB_RIS_EXTW 0x00000008 // External Wake-Up Raw Interrupt
// Status
#define HIB_RIS_LOWBAT 0x00000004 // Low Battery Voltage Raw
// Interrupt Status
#define HIB_RIS_RTCALT0 0x00000001 // RTC Alert 0 Raw Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_MIS register.
//
//*****************************************************************************
#define HIB_MIS_VDDFAIL 0x00000080 // VDD Fail Interrupt Mask
#define HIB_MIS_RSTWK 0x00000040 // Reset Pad I/O Wake-Up Interrupt
// Mask
#define HIB_MIS_PADIOWK 0x00000020 // Pad I/O Wake-Up Interrupt Mask
#define HIB_MIS_WC 0x00000010 // Write Complete/Capable Masked
// Interrupt Status
#define HIB_MIS_EXTW 0x00000008 // External Wake-Up Masked
// Interrupt Status
#define HIB_MIS_LOWBAT 0x00000004 // Low Battery Voltage Masked
// Interrupt Status
#define HIB_MIS_RTCALT0 0x00000001 // RTC Alert 0 Masked Interrupt
// Status
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_IC register.
//
//*****************************************************************************
#define HIB_IC_VDDFAIL 0x00000080 // VDD Fail Interrupt Clear
#define HIB_IC_RSTWK 0x00000040 // Reset Pad I/O Wake-Up Interrupt
// Clear
#define HIB_IC_PADIOWK 0x00000020 // Pad I/O Wake-Up Interrupt Clear
#define HIB_IC_WC 0x00000010 // Write Complete/Capable Interrupt
// Clear
#define HIB_IC_EXTW 0x00000008 // External Wake-Up Interrupt Clear
#define HIB_IC_LOWBAT 0x00000004 // Low Battery Voltage Interrupt
// Clear
#define HIB_IC_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt
// Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_RTCT register.
//
//*****************************************************************************
#define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value
#define HIB_RTCT_TRIM_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_RTCSS register.
//
//*****************************************************************************
#define HIB_RTCSS_RTCSSM_M 0x7FFF0000 // RTC Sub Seconds Match
#define HIB_RTCSS_RTCSSC_M 0x00007FFF // RTC Sub Seconds Count
#define HIB_RTCSS_RTCSSM_S 16
#define HIB_RTCSS_RTCSSC_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_IO register.
//
//*****************************************************************************
#define HIB_IO_IOWRC 0x80000000 // I/O Write Complete
#define HIB_IO_WURSTEN 0x00000010 // Reset Wake Source Enable
#define HIB_IO_WUUNLK 0x00000001 // I/O Wake Pad Configuration
// Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_DATA register.
//
//*****************************************************************************
#define HIB_DATA_RTD_M 0xFFFFFFFF // Hibernation Module NV Data
#define HIB_DATA_RTD_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_CALCTL register.
//
//*****************************************************************************
#define HIB_CALCTL_CAL24 0x00000004 // Calendar Mode
#define HIB_CALCTL_CALEN 0x00000001 // RTC Calendar/Counter Mode Select
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_CAL0 register.
//
//*****************************************************************************
#define HIB_CAL0_VALID 0x80000000 // Valid Calendar Load
#define HIB_CAL0_AMPM 0x00400000 // AM/PM Designation
#define HIB_CAL0_HR_M 0x001F0000 // Hours
#define HIB_CAL0_MIN_M 0x00003F00 // Minutes
#define HIB_CAL0_SEC_M 0x0000003F // Seconds
#define HIB_CAL0_HR_S 16
#define HIB_CAL0_MIN_S 8
#define HIB_CAL0_SEC_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_CAL1 register.
//
//*****************************************************************************
#define HIB_CAL1_VALID 0x80000000 // Valid Calendar Load
#define HIB_CAL1_DOW_M 0x07000000 // Day of Week
#define HIB_CAL1_YEAR_M 0x007F0000 // Year Value
#define HIB_CAL1_MON_M 0x00000F00 // Month
#define HIB_CAL1_DOM_M 0x0000001F // Day of Month
#define HIB_CAL1_DOW_S 24
#define HIB_CAL1_YEAR_S 16
#define HIB_CAL1_MON_S 8
#define HIB_CAL1_DOM_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_CALLD0 register.
//
//*****************************************************************************
#define HIB_CALLD0_AMPM 0x00400000 // AM/PM Designation
#define HIB_CALLD0_HR_M 0x001F0000 // Hours
#define HIB_CALLD0_MIN_M 0x00003F00 // Minutes
#define HIB_CALLD0_SEC_M 0x0000003F // Seconds
#define HIB_CALLD0_HR_S 16
#define HIB_CALLD0_MIN_S 8
#define HIB_CALLD0_SEC_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_CALLD1 register.
//
//*****************************************************************************
#define HIB_CALLD1_DOW_M 0x07000000 // Day of Week
#define HIB_CALLD1_YEAR_M 0x007F0000 // Year Value
#define HIB_CALLD1_MON_M 0x00000F00 // Month
#define HIB_CALLD1_DOM_M 0x0000001F // Day of Month
#define HIB_CALLD1_DOW_S 24
#define HIB_CALLD1_YEAR_S 16
#define HIB_CALLD1_MON_S 8
#define HIB_CALLD1_DOM_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_CALM0 register.
//
//*****************************************************************************
#define HIB_CALM0_AMPM 0x00400000 // AM/PM Designation
#define HIB_CALM0_HR_M 0x001F0000 // Hours
#define HIB_CALM0_MIN_M 0x00003F00 // Minutes
#define HIB_CALM0_SEC_M 0x0000003F // Seconds
#define HIB_CALM0_HR_S 16
#define HIB_CALM0_MIN_S 8
#define HIB_CALM0_SEC_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_CALM1 register.
//
//*****************************************************************************
#define HIB_CALM1_DOM_M 0x0000001F // Day of Month
#define HIB_CALM1_DOM_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_LOCK register.
//
//*****************************************************************************
#define HIB_LOCK_HIBLOCK_M 0xFFFFFFFF // HIbernate Lock
#define HIB_LOCK_HIBLOCK_KEY 0xA3359554 // Hibernate Lock Key
#define HIB_LOCK_HIBLOCK_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_TPCTL register.
//
//*****************************************************************************
#define HIB_TPCTL_WAKE 0x00000800 // Wake from Hibernate on a Tamper
// Event
#define HIB_TPCTL_MEMCLR_M 0x00000300 // HIB Memory Clear on Tamper Event
#define HIB_TPCTL_MEMCLR_NONE 0x00000000 // Do not Clear HIB memory on
// tamper event
#define HIB_TPCTL_MEMCLR_LOW32 0x00000100 // Clear Lower 32 Bytes of HIB
// memory on tamper event
#define HIB_TPCTL_MEMCLR_HIGH32 0x00000200 // Clear upper 32 Bytes of HIB
// memory on tamper event
#define HIB_TPCTL_MEMCLR_ALL 0x00000300 // Clear all HIB memory on tamper
// event
#define HIB_TPCTL_TPCLR 0x00000010 // Tamper Event Clear
#define HIB_TPCTL_TPEN 0x00000001 // Tamper Module Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_TPSTAT register.
//
//*****************************************************************************
#define HIB_TPSTAT_STATE_M 0x0000000C // Tamper Module Status
#define HIB_TPSTAT_STATE_DISABLED \
0x00000000 // Tamper disabled
#define HIB_TPSTAT_STATE_CONFIGED \
0x00000004 // Tamper configured
#define HIB_TPSTAT_STATE_ERROR 0x00000008 // Tamper pin event occurred
#define HIB_TPSTAT_XOSCST 0x00000002 // External Oscillator Status
#define HIB_TPSTAT_XOSCFAIL 0x00000001 // External Oscillator Failure
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_TPIO register.
//
//*****************************************************************************
#define HIB_TPIO_GFLTR3 0x08000000 // TMPR3 Glitch Filtering
#define HIB_TPIO_PUEN3 0x04000000 // TMPR3 Internal Weak Pull-up
// Enable
#define HIB_TPIO_LEV3 0x02000000 // TMPR3 Trigger Level
#define HIB_TPIO_EN3 0x01000000 // TMPR3 Enable
#define HIB_TPIO_GFLTR2 0x00080000 // TMPR2 Glitch Filtering
#define HIB_TPIO_PUEN2 0x00040000 // TMPR2 Internal Weak Pull-up
// Enable
#define HIB_TPIO_LEV2 0x00020000 // TMPR2 Trigger Level
#define HIB_TPIO_EN2 0x00010000 // TMPR2 Enable
#define HIB_TPIO_GFLTR1 0x00000800 // TMPR1 Glitch Filtering
#define HIB_TPIO_PUEN1 0x00000400 // TMPR1 Internal Weak Pull-up
// Enable
#define HIB_TPIO_LEV1 0x00000200 // TMPR1 Trigger Level
#define HIB_TPIO_EN1 0x00000100 // TMPR1Enable
#define HIB_TPIO_GFLTR0 0x00000008 // TMPR0 Glitch Filtering
#define HIB_TPIO_PUEN0 0x00000004 // TMPR0 Internal Weak Pull-up
// Enable
#define HIB_TPIO_LEV0 0x00000002 // TMPR0 Trigger Level
#define HIB_TPIO_EN0 0x00000001 // TMPR0 Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_TPLOG0 register.
//
//*****************************************************************************
#define HIB_TPLOG0_TIME_M 0xFFFFFFFF // Tamper Log Calendar Information
#define HIB_TPLOG0_TIME_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_TPLOG1 register.
//
//*****************************************************************************
#define HIB_TPLOG1_XOSC 0x00010000 // Status of external 32
#define HIB_TPLOG1_TRIG3 0x00000008 // Status of TMPR[3] Trigger
#define HIB_TPLOG1_TRIG2 0x00000004 // Status of TMPR[2] Trigger
#define HIB_TPLOG1_TRIG1 0x00000002 // Status of TMPR[1] Trigger
#define HIB_TPLOG1_TRIG0 0x00000001 // Status of TMPR[0] Trigger
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_TPLOG2 register.
//
//*****************************************************************************
#define HIB_TPLOG2_TIME_M 0xFFFFFFFF // Tamper Log Calendar Information
#define HIB_TPLOG2_TIME_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_TPLOG3 register.
//
//*****************************************************************************
#define HIB_TPLOG3_XOSC 0x00010000 // Status of external 32
#define HIB_TPLOG3_TRIG3 0x00000008 // Status of TMPR[3] Trigger
#define HIB_TPLOG3_TRIG2 0x00000004 // Status of TMPR[2] Trigger
#define HIB_TPLOG3_TRIG1 0x00000002 // Status of TMPR[1] Trigger
#define HIB_TPLOG3_TRIG0 0x00000001 // Status of TMPR[0] Trigger
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_TPLOG4 register.
//
//*****************************************************************************
#define HIB_TPLOG4_TIME_M 0xFFFFFFFF // Tamper Log Calendar Information
#define HIB_TPLOG4_TIME_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_TPLOG5 register.
//
//*****************************************************************************
#define HIB_TPLOG5_XOSC 0x00010000 // Status of external 32
#define HIB_TPLOG5_TRIG3 0x00000008 // Status of TMPR[3] Trigger
#define HIB_TPLOG5_TRIG2 0x00000004 // Status of TMPR[2] Trigger
#define HIB_TPLOG5_TRIG1 0x00000002 // Status of TMPR[1] Trigger
#define HIB_TPLOG5_TRIG0 0x00000001 // Status of TMPR[0] Trigger
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_TPLOG6 register.
//
//*****************************************************************************
#define HIB_TPLOG6_TIME_M 0xFFFFFFFF // Tamper Log Calendar Information
#define HIB_TPLOG6_TIME_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_TPLOG7 register.
//
//*****************************************************************************
#define HIB_TPLOG7_XOSC 0x00010000 // Status of external 32
#define HIB_TPLOG7_TRIG3 0x00000008 // Status of TMPR[3] Trigger
#define HIB_TPLOG7_TRIG2 0x00000004 // Status of TMPR[2] Trigger
#define HIB_TPLOG7_TRIG1 0x00000002 // Status of TMPR[1] Trigger
#define HIB_TPLOG7_TRIG0 0x00000001 // Status of TMPR[0] Trigger
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_PP register.
//
//*****************************************************************************
#define HIB_PP_TAMPER 0x00000002 // Tamper Pin Presence
#define HIB_PP_WAKENC 0x00000001 // Wake Pin Presence
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_CC register.
//
//*****************************************************************************
#define HIB_CC_SYSCLKEN 0x00000001 // RTCOSC to System Clock Enable
#endif // __HW_HIBERNATE_H__

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//*****************************************************************************
//
// hw_i2c.h - Macros used when accessing the I2C master and slave hardware.
//
// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_I2C_H__
#define __HW_I2C_H__
//*****************************************************************************
//
// The following are defines for the I2C register offsets.
//
//*****************************************************************************
#define I2C_O_MSA 0x00000000 // I2C Master Slave Address
#define I2C_O_MCS 0x00000004 // I2C Master Control/Status
#define I2C_O_MDR 0x00000008 // I2C Master Data
#define I2C_O_MTPR 0x0000000C // I2C Master Timer Period
#define I2C_O_MIMR 0x00000010 // I2C Master Interrupt Mask
#define I2C_O_MRIS 0x00000014 // I2C Master Raw Interrupt Status
#define I2C_O_MMIS 0x00000018 // I2C Master Masked Interrupt
// Status
#define I2C_O_MICR 0x0000001C // I2C Master Interrupt Clear
#define I2C_O_MCR 0x00000020 // I2C Master Configuration
#define I2C_O_MCLKOCNT 0x00000024 // I2C Master Clock Low Timeout
// Count
#define I2C_O_MBMON 0x0000002C // I2C Master Bus Monitor
#define I2C_O_MBLEN 0x00000030 // I2C Master Burst Length
#define I2C_O_MBCNT 0x00000034 // I2C Master Burst Count
#define I2C_O_MCR2 0x00000038 // I2C Master Configuration 2
#define I2C_O_SOAR 0x00000800 // I2C Slave Own Address
#define I2C_O_SCSR 0x00000804 // I2C Slave Control/Status
#define I2C_O_SDR 0x00000808 // I2C Slave Data
#define I2C_O_SIMR 0x0000080C // I2C Slave Interrupt Mask
#define I2C_O_SRIS 0x00000810 // I2C Slave Raw Interrupt Status
#define I2C_O_SMIS 0x00000814 // I2C Slave Masked Interrupt
// Status
#define I2C_O_SICR 0x00000818 // I2C Slave Interrupt Clear
#define I2C_O_SOAR2 0x0000081C // I2C Slave Own Address 2
#define I2C_O_SACKCTL 0x00000820 // I2C Slave ACK Control
#define I2C_O_FIFODATA 0x00000F00 // I2C FIFO Data
#define I2C_O_FIFOCTL 0x00000F04 // I2C FIFO Control
#define I2C_O_FIFOSTATUS 0x00000F08 // I2C FIFO Status
#define I2C_O_PP 0x00000FC0 // I2C Peripheral Properties
#define I2C_O_PC 0x00000FC4 // I2C Peripheral Configuration
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MSA register.
//
//*****************************************************************************
#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address
#define I2C_MSA_RS 0x00000001 // Receive not send
#define I2C_MSA_SA_S 1
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MCS register.
//
//*****************************************************************************
#define I2C_MCS_ACTDMARX 0x80000000 // DMA RX Active Status
#define I2C_MCS_ACTDMATX 0x40000000 // DMA TX Active Status
#define I2C_MCS_CLKTO 0x00000080 // Clock Timeout Error
#define I2C_MCS_BURST 0x00000040 // Burst Enable
#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy
#define I2C_MCS_IDLE 0x00000020 // I2C Idle
#define I2C_MCS_QCMD 0x00000020 // Quick Command
#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost
#define I2C_MCS_HS 0x00000010 // High-Speed Enable
#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable
#define I2C_MCS_DATACK 0x00000008 // Acknowledge Data
#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address
#define I2C_MCS_STOP 0x00000004 // Generate STOP
#define I2C_MCS_ERROR 0x00000002 // Error
#define I2C_MCS_START 0x00000002 // Generate START
#define I2C_MCS_RUN 0x00000001 // I2C Master Enable
#define I2C_MCS_BUSY 0x00000001 // I2C Busy
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MDR register.
//
//*****************************************************************************
#define I2C_MDR_DATA_M 0x000000FF // This byte contains the data
// transferred during a transaction
#define I2C_MDR_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MTPR register.
//
//*****************************************************************************
#define I2C_MTPR_PULSEL_M 0x00070000 // Glitch Suppression Pulse Width
#define I2C_MTPR_PULSEL_BYPASS 0x00000000 // Bypass
#define I2C_MTPR_PULSEL_1 0x00010000 // 1 clock
#define I2C_MTPR_PULSEL_2 0x00020000 // 2 clocks
#define I2C_MTPR_PULSEL_3 0x00030000 // 3 clocks
#define I2C_MTPR_PULSEL_4 0x00040000 // 4 clocks
#define I2C_MTPR_PULSEL_8 0x00050000 // 8 clocks
#define I2C_MTPR_PULSEL_16 0x00060000 // 16 clocks
#define I2C_MTPR_PULSEL_31 0x00070000 // 31 clocks
#define I2C_MTPR_HS 0x00000080 // High-Speed Enable
#define I2C_MTPR_TPR_M 0x0000007F // Timer Period
#define I2C_MTPR_TPR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MIMR register.
//
//*****************************************************************************
#define I2C_MIMR_RXFFIM 0x00000800 // Receive FIFO Full Interrupt Mask
#define I2C_MIMR_TXFEIM 0x00000400 // Transmit FIFO Empty Interrupt
// Mask
#define I2C_MIMR_RXIM 0x00000200 // Receive FIFO Request Interrupt
// Mask
#define I2C_MIMR_TXIM 0x00000100 // Transmit FIFO Request Interrupt
// Mask
#define I2C_MIMR_ARBLOSTIM 0x00000080 // Arbitration Lost Interrupt Mask
#define I2C_MIMR_STOPIM 0x00000040 // STOP Detection Interrupt Mask
#define I2C_MIMR_STARTIM 0x00000020 // START Detection Interrupt Mask
#define I2C_MIMR_NACKIM 0x00000010 // Address/Data NACK Interrupt Mask
#define I2C_MIMR_DMATXIM 0x00000008 // Transmit DMA Interrupt Mask
#define I2C_MIMR_DMARXIM 0x00000004 // Receive DMA Interrupt Mask
#define I2C_MIMR_CLKIM 0x00000002 // Clock Timeout Interrupt Mask
#define I2C_MIMR_IM 0x00000001 // Master Interrupt Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MRIS register.
//
//*****************************************************************************
#define I2C_MRIS_RXFFRIS 0x00000800 // Receive FIFO Full Raw Interrupt
// Status
#define I2C_MRIS_TXFERIS 0x00000400 // Transmit FIFO Empty Raw
// Interrupt Status
#define I2C_MRIS_RXRIS 0x00000200 // Receive FIFO Request Raw
// Interrupt Status
#define I2C_MRIS_TXRIS 0x00000100 // Transmit Request Raw Interrupt
// Status
#define I2C_MRIS_ARBLOSTRIS 0x00000080 // Arbitration Lost Raw Interrupt
// Status
#define I2C_MRIS_STOPRIS 0x00000040 // STOP Detection Raw Interrupt
// Status
#define I2C_MRIS_STARTRIS 0x00000020 // START Detection Raw Interrupt
// Status
#define I2C_MRIS_NACKRIS 0x00000010 // Address/Data NACK Raw Interrupt
// Status
#define I2C_MRIS_DMATXRIS 0x00000008 // Transmit DMA Raw Interrupt
// Status
#define I2C_MRIS_DMARXRIS 0x00000004 // Receive DMA Raw Interrupt Status
#define I2C_MRIS_CLKRIS 0x00000002 // Clock Timeout Raw Interrupt
// Status
#define I2C_MRIS_RIS 0x00000001 // Master Raw Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MMIS register.
//
//*****************************************************************************
#define I2C_MMIS_RXFFMIS 0x00000800 // Receive FIFO Full Interrupt Mask
#define I2C_MMIS_TXFEMIS 0x00000400 // Transmit FIFO Empty Interrupt
// Mask
#define I2C_MMIS_RXMIS 0x00000200 // Receive FIFO Request Interrupt
// Mask
#define I2C_MMIS_TXMIS 0x00000100 // Transmit Request Interrupt Mask
#define I2C_MMIS_ARBLOSTMIS 0x00000080 // Arbitration Lost Interrupt Mask
#define I2C_MMIS_STOPMIS 0x00000040 // STOP Detection Interrupt Mask
#define I2C_MMIS_STARTMIS 0x00000020 // START Detection Interrupt Mask
#define I2C_MMIS_NACKMIS 0x00000010 // Address/Data NACK Interrupt Mask
#define I2C_MMIS_DMATXMIS 0x00000008 // Transmit DMA Interrupt Status
#define I2C_MMIS_DMARXMIS 0x00000004 // Receive DMA Interrupt Status
#define I2C_MMIS_CLKMIS 0x00000002 // Clock Timeout Masked Interrupt
// Status
#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MICR register.
//
//*****************************************************************************
#define I2C_MICR_RXFFIC 0x00000800 // Receive FIFO Full Interrupt
// Clear
#define I2C_MICR_TXFEIC 0x00000400 // Transmit FIFO Empty Interrupt
// Clear
#define I2C_MICR_RXIC 0x00000200 // Receive FIFO Request Interrupt
// Clear
#define I2C_MICR_TXIC 0x00000100 // Transmit FIFO Request Interrupt
// Clear
#define I2C_MICR_ARBLOSTIC 0x00000080 // Arbitration Lost Interrupt Clear
#define I2C_MICR_STOPIC 0x00000040 // STOP Detection Interrupt Clear
#define I2C_MICR_STARTIC 0x00000020 // START Detection Interrupt Clear
#define I2C_MICR_NACKIC 0x00000010 // Address/Data NACK Interrupt
// Clear
#define I2C_MICR_DMATXIC 0x00000008 // Transmit DMA Interrupt Clear
#define I2C_MICR_DMARXIC 0x00000004 // Receive DMA Interrupt Clear
#define I2C_MICR_CLKIC 0x00000002 // Clock Timeout Interrupt Clear
#define I2C_MICR_IC 0x00000001 // Master Interrupt Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MCR register.
//
//*****************************************************************************
#define I2C_MCR_GFE 0x00000040 // I2C Glitch Filter Enable
#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable
#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable
#define I2C_MCR_LPBK 0x00000001 // I2C Loopback
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MCLKOCNT register.
//
//*****************************************************************************
#define I2C_MCLKOCNT_CNTL_M 0x000000FF // I2C Master Count
#define I2C_MCLKOCNT_CNTL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MBMON register.
//
//*****************************************************************************
#define I2C_MBMON_SDA 0x00000002 // I2C SDA Status
#define I2C_MBMON_SCL 0x00000001 // I2C SCL Status
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MBLEN register.
//
//*****************************************************************************
#define I2C_MBLEN_CNTL_M 0x000000FF // I2C Burst Length
#define I2C_MBLEN_CNTL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MBCNT register.
//
//*****************************************************************************
#define I2C_MBCNT_CNTL_M 0x000000FF // I2C Master Burst Count
#define I2C_MBCNT_CNTL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MCR2 register.
//
//*****************************************************************************
#define I2C_MCR2_GFPW_M 0x00000070 // I2C Glitch Filter Pulse Width
#define I2C_MCR2_GFPW_BYPASS 0x00000000 // Bypass
#define I2C_MCR2_GFPW_1 0x00000010 // 1 clock
#define I2C_MCR2_GFPW_2 0x00000020 // 2 clocks
#define I2C_MCR2_GFPW_3 0x00000030 // 3 clocks
#define I2C_MCR2_GFPW_4 0x00000040 // 4 clocks
#define I2C_MCR2_GFPW_8 0x00000050 // 8 clocks
#define I2C_MCR2_GFPW_16 0x00000060 // 16 clocks
#define I2C_MCR2_GFPW_31 0x00000070 // 31 clocks
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SOAR register.
//
//*****************************************************************************
#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address
#define I2C_SOAR_OAR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SCSR register.
//
//*****************************************************************************
#define I2C_SCSR_ACTDMARX 0x80000000 // DMA RX Active Status
#define I2C_SCSR_ACTDMATX 0x40000000 // DMA TX Active Status
#define I2C_SCSR_QCMDRW 0x00000020 // Quick Command Read / Write
#define I2C_SCSR_QCMDST 0x00000010 // Quick Command Status
#define I2C_SCSR_OAR2SEL 0x00000008 // OAR2 Address Matched
#define I2C_SCSR_FBR 0x00000004 // First Byte Received
#define I2C_SCSR_RXFIFO 0x00000004 // RX FIFO Enable
#define I2C_SCSR_TXFIFO 0x00000002 // TX FIFO Enable
#define I2C_SCSR_TREQ 0x00000002 // Transmit Request
#define I2C_SCSR_DA 0x00000001 // Device Active
#define I2C_SCSR_RREQ 0x00000001 // Receive Request
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SDR register.
//
//*****************************************************************************
#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer
#define I2C_SDR_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SIMR register.
//
//*****************************************************************************
#define I2C_SIMR_RXFFIM 0x00000100 // Receive FIFO Full Interrupt Mask
#define I2C_SIMR_TXFEIM 0x00000080 // Transmit FIFO Empty Interrupt
// Mask
#define I2C_SIMR_RXIM 0x00000040 // Receive FIFO Request Interrupt
// Mask
#define I2C_SIMR_TXIM 0x00000020 // Transmit FIFO Request Interrupt
// Mask
#define I2C_SIMR_DMATXIM 0x00000010 // Transmit DMA Interrupt Mask
#define I2C_SIMR_DMARXIM 0x00000008 // Receive DMA Interrupt Mask
#define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask
#define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask
#define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SRIS register.
//
//*****************************************************************************
#define I2C_SRIS_RXFFRIS 0x00000100 // Receive FIFO Full Raw Interrupt
// Status
#define I2C_SRIS_TXFERIS 0x00000080 // Transmit FIFO Empty Raw
// Interrupt Status
#define I2C_SRIS_RXRIS 0x00000040 // Receive FIFO Request Raw
// Interrupt Status
#define I2C_SRIS_TXRIS 0x00000020 // Transmit Request Raw Interrupt
// Status
#define I2C_SRIS_DMATXRIS 0x00000010 // Transmit DMA Raw Interrupt
// Status
#define I2C_SRIS_DMARXRIS 0x00000008 // Receive DMA Raw Interrupt Status
#define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt
// Status
#define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt
// Status
#define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SMIS register.
//
//*****************************************************************************
#define I2C_SMIS_RXFFMIS 0x00000100 // Receive FIFO Full Interrupt Mask
#define I2C_SMIS_TXFEMIS 0x00000080 // Transmit FIFO Empty Interrupt
// Mask
#define I2C_SMIS_RXMIS 0x00000040 // Receive FIFO Request Interrupt
// Mask
#define I2C_SMIS_TXMIS 0x00000020 // Transmit FIFO Request Interrupt
// Mask
#define I2C_SMIS_DMATXMIS 0x00000010 // Transmit DMA Masked Interrupt
// Status
#define I2C_SMIS_DMARXMIS 0x00000008 // Receive DMA Masked Interrupt
// Status
#define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt
// Status
#define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt
// Status
#define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SICR register.
//
//*****************************************************************************
#define I2C_SICR_RXFFIC 0x00000100 // Receive FIFO Full Interrupt Mask
#define I2C_SICR_TXFEIC 0x00000080 // Transmit FIFO Empty Interrupt
// Mask
#define I2C_SICR_RXIC 0x00000040 // Receive Request Interrupt Mask
#define I2C_SICR_TXIC 0x00000020 // Transmit Request Interrupt Mask
#define I2C_SICR_DMATXIC 0x00000010 // Transmit DMA Interrupt Clear
#define I2C_SICR_DMARXIC 0x00000008 // Receive DMA Interrupt Clear
#define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear
#define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear
#define I2C_SICR_DATAIC 0x00000001 // Data Interrupt Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SOAR2 register.
//
//*****************************************************************************
#define I2C_SOAR2_OAR2EN 0x00000080 // I2C Slave Own Address 2 Enable
#define I2C_SOAR2_OAR2_M 0x0000007F // I2C Slave Own Address 2
#define I2C_SOAR2_OAR2_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SACKCTL register.
//
//*****************************************************************************
#define I2C_SACKCTL_ACKOVAL 0x00000002 // I2C Slave ACK Override Value
#define I2C_SACKCTL_ACKOEN 0x00000001 // I2C Slave ACK Override Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_FIFODATA register.
//
//*****************************************************************************
#define I2C_FIFODATA_DATA_M 0x000000FF // I2C TX FIFO Write Data Byte
#define I2C_FIFODATA_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_FIFOCTL register.
//
//*****************************************************************************
#define I2C_FIFOCTL_RXASGNMT 0x80000000 // RX Control Assignment
#define I2C_FIFOCTL_RXFLUSH 0x40000000 // RX FIFO Flush
#define I2C_FIFOCTL_DMARXENA 0x20000000 // DMA RX Channel Enable
#define I2C_FIFOCTL_RXTRIG_M 0x00070000 // RX FIFO Trigger
#define I2C_FIFOCTL_TXASGNMT 0x00008000 // TX Control Assignment
#define I2C_FIFOCTL_TXFLUSH 0x00004000 // TX FIFO Flush
#define I2C_FIFOCTL_DMATXENA 0x00002000 // DMA TX Channel Enable
#define I2C_FIFOCTL_TXTRIG_M 0x00000007 // TX FIFO Trigger
#define I2C_FIFOCTL_RXTRIG_S 16
#define I2C_FIFOCTL_TXTRIG_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_FIFOSTATUS
// register.
//
//*****************************************************************************
#define I2C_FIFOSTATUS_RXABVTRIG \
0x00040000 // RX FIFO Above Trigger Level
#define I2C_FIFOSTATUS_RXFF 0x00020000 // RX FIFO Full
#define I2C_FIFOSTATUS_RXFE 0x00010000 // RX FIFO Empty
#define I2C_FIFOSTATUS_TXBLWTRIG \
0x00000004 // TX FIFO Below Trigger Level
#define I2C_FIFOSTATUS_TXFF 0x00000002 // TX FIFO Full
#define I2C_FIFOSTATUS_TXFE 0x00000001 // TX FIFO Empty
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_PP register.
//
//*****************************************************************************
#define I2C_PP_HS 0x00000001 // High-Speed Capable
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_PC register.
//
//*****************************************************************************
#define I2C_PC_HS 0x00000001 // High-Speed Capable
#endif // __HW_I2C_H__

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//*****************************************************************************
//
// hw_ints.h - Macros that define the interrupt assignment on Tiva C Series
// MCUs.
//
// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_INTS_H__
#define __HW_INTS_H__
//*****************************************************************************
//
// The following are defines for the fault assignments.
//
//*****************************************************************************
#define FAULT_NMI 2 // NMI fault
#define FAULT_HARD 3 // Hard fault
#define FAULT_MPU 4 // MPU fault
#define FAULT_BUS 5 // Bus fault
#define FAULT_USAGE 6 // Usage fault
#define FAULT_SVCALL 11 // SVCall
#define FAULT_DEBUG 12 // Debug monitor
#define FAULT_PENDSV 14 // PendSV
#define FAULT_SYSTICK 15 // System Tick
//*****************************************************************************
//
// TM4C123 Class Interrupts
//
//*****************************************************************************
#define INT_GPIOA_TM4C123 16 // GPIO Port A
#define INT_GPIOB_TM4C123 17 // GPIO Port B
#define INT_GPIOC_TM4C123 18 // GPIO Port C
#define INT_GPIOD_TM4C123 19 // GPIO Port D
#define INT_GPIOE_TM4C123 20 // GPIO Port E
#define INT_UART0_TM4C123 21 // UART0
#define INT_UART1_TM4C123 22 // UART1
#define INT_SSI0_TM4C123 23 // SSI0
#define INT_I2C0_TM4C123 24 // I2C0
#define INT_PWM0_FAULT_TM4C123 25 // PWM0 Fault
#define INT_PWM0_0_TM4C123 26 // PWM0 Generator 0
#define INT_PWM0_1_TM4C123 27 // PWM0 Generator 1
#define INT_PWM0_2_TM4C123 28 // PWM0 Generator 2
#define INT_QEI0_TM4C123 29 // QEI0
#define INT_ADC0SS0_TM4C123 30 // ADC0 Sequence 0
#define INT_ADC0SS1_TM4C123 31 // ADC0 Sequence 1
#define INT_ADC0SS2_TM4C123 32 // ADC0 Sequence 2
#define INT_ADC0SS3_TM4C123 33 // ADC0 Sequence 3
#define INT_WATCHDOG_TM4C123 34 // Watchdog Timers 0 and 1
#define INT_TIMER0A_TM4C123 35 // 16/32-Bit Timer 0A
#define INT_TIMER0B_TM4C123 36 // 16/32-Bit Timer 0B
#define INT_TIMER1A_TM4C123 37 // 16/32-Bit Timer 1A
#define INT_TIMER1B_TM4C123 38 // 16/32-Bit Timer 1B
#define INT_TIMER2A_TM4C123 39 // 16/32-Bit Timer 2A
#define INT_TIMER2B_TM4C123 40 // 16/32-Bit Timer 2B
#define INT_COMP0_TM4C123 41 // Analog Comparator 0
#define INT_COMP1_TM4C123 42 // Analog Comparator 1
#define INT_COMP2_TM4C123 43 // Analog Comparator 2
#define INT_SYSCTL_TM4C123 44 // System Control
#define INT_FLASH_TM4C123 45 // Flash Memory Control and EEPROM
// Control
#define INT_GPIOF_TM4C123 46 // GPIO Port F
#define INT_GPIOG_TM4C123 47 // GPIO Port G
#define INT_GPIOH_TM4C123 48 // GPIO Port H
#define INT_UART2_TM4C123 49 // UART2
#define INT_SSI1_TM4C123 50 // SSI1
#define INT_TIMER3A_TM4C123 51 // 16/32-Bit Timer 3A
#define INT_TIMER3B_TM4C123 52 // Timer 3B
#define INT_I2C1_TM4C123 53 // I2C1
#define INT_QEI1_TM4C123 54 // QEI1
#define INT_CAN0_TM4C123 55 // CAN0
#define INT_CAN1_TM4C123 56 // CAN1
#define INT_HIBERNATE_TM4C123 59 // Hibernation Module
#define INT_USB0_TM4C123 60 // USB
#define INT_PWM0_3_TM4C123 61 // PWM Generator 3
#define INT_UDMA_TM4C123 62 // uDMA Software
#define INT_UDMAERR_TM4C123 63 // uDMA Error
#define INT_ADC1SS0_TM4C123 64 // ADC1 Sequence 0
#define INT_ADC1SS1_TM4C123 65 // ADC1 Sequence 1
#define INT_ADC1SS2_TM4C123 66 // ADC1 Sequence 2
#define INT_ADC1SS3_TM4C123 67 // ADC1 Sequence 3
#define INT_GPIOJ_TM4C123 70 // GPIO Port J
#define INT_GPIOK_TM4C123 71 // GPIO Port K
#define INT_GPIOL_TM4C123 72 // GPIO Port L
#define INT_SSI2_TM4C123 73 // SSI2
#define INT_SSI3_TM4C123 74 // SSI3
#define INT_UART3_TM4C123 75 // UART3
#define INT_UART4_TM4C123 76 // UART4
#define INT_UART5_TM4C123 77 // UART5
#define INT_UART6_TM4C123 78 // UART6
#define INT_UART7_TM4C123 79 // UART7
#define INT_I2C2_TM4C123 84 // I2C2
#define INT_I2C3_TM4C123 85 // I2C3
#define INT_TIMER4A_TM4C123 86 // 16/32-Bit Timer 4A
#define INT_TIMER4B_TM4C123 87 // 16/32-Bit Timer 4B
#define INT_TIMER5A_TM4C123 108 // 16/32-Bit Timer 5A
#define INT_TIMER5B_TM4C123 109 // 16/32-Bit Timer 5B
#define INT_WTIMER0A_TM4C123 110 // 32/64-Bit Timer 0A
#define INT_WTIMER0B_TM4C123 111 // 32/64-Bit Timer 0B
#define INT_WTIMER1A_TM4C123 112 // 32/64-Bit Timer 1A
#define INT_WTIMER1B_TM4C123 113 // 32/64-Bit Timer 1B
#define INT_WTIMER2A_TM4C123 114 // 32/64-Bit Timer 2A
#define INT_WTIMER2B_TM4C123 115 // 32/64-Bit Timer 2B
#define INT_WTIMER3A_TM4C123 116 // 32/64-Bit Timer 3A
#define INT_WTIMER3B_TM4C123 117 // 32/64-Bit Timer 3B
#define INT_WTIMER4A_TM4C123 118 // 32/64-Bit Timer 4A
#define INT_WTIMER4B_TM4C123 119 // 32/64-Bit Timer 4B
#define INT_WTIMER5A_TM4C123 120 // 32/64-Bit Timer 5A
#define INT_WTIMER5B_TM4C123 121 // 32/64-Bit Timer 5B
#define INT_SYSEXC_TM4C123 122 // System Exception (imprecise)
#define INT_I2C4_TM4C123 125 // I2C4
#define INT_I2C5_TM4C123 126 // I2C5
#define INT_GPIOM_TM4C123 127 // GPIO Port M
#define INT_GPION_TM4C123 128 // GPIO Port N
#define INT_GPIOP0_TM4C123 132 // GPIO Port P (Summary or P0)
#define INT_GPIOP1_TM4C123 133 // GPIO Port P1
#define INT_GPIOP2_TM4C123 134 // GPIO Port P2
#define INT_GPIOP3_TM4C123 135 // GPIO Port P3
#define INT_GPIOP4_TM4C123 136 // GPIO Port P4
#define INT_GPIOP5_TM4C123 137 // GPIO Port P5
#define INT_GPIOP6_TM4C123 138 // GPIO Port P6
#define INT_GPIOP7_TM4C123 139 // GPIO Port P7
#define INT_GPIOQ0_TM4C123 140 // GPIO Port Q (Summary or Q0)
#define INT_GPIOQ1_TM4C123 141 // GPIO Port Q1
#define INT_GPIOQ2_TM4C123 142 // GPIO Port Q2
#define INT_GPIOQ3_TM4C123 143 // GPIO Port Q3
#define INT_GPIOQ4_TM4C123 144 // GPIO Port Q4
#define INT_GPIOQ5_TM4C123 145 // GPIO Port Q5
#define INT_GPIOQ6_TM4C123 146 // GPIO Port Q6
#define INT_GPIOQ7_TM4C123 147 // GPIO Port Q7
#define INT_PWM1_0_TM4C123 150 // PWM1 Generator 0
#define INT_PWM1_1_TM4C123 151 // PWM1 Generator 1
#define INT_PWM1_2_TM4C123 152 // PWM1 Generator 2
#define INT_PWM1_3_TM4C123 153 // PWM1 Generator 3
#define INT_PWM1_FAULT_TM4C123 154 // PWM1 Fault
#define NUM_INTERRUPTS_TM4C123 155
//*****************************************************************************
//
// TM4C129 Class Interrupts
//
//*****************************************************************************
#define INT_GPIOA_TM4C129 16 // GPIO Port A
#define INT_GPIOB_TM4C129 17 // GPIO Port B
#define INT_GPIOC_TM4C129 18 // GPIO Port C
#define INT_GPIOD_TM4C129 19 // GPIO Port D
#define INT_GPIOE_TM4C129 20 // GPIO Port E
#define INT_UART0_TM4C129 21 // UART0
#define INT_UART1_TM4C129 22 // UART1
#define INT_SSI0_TM4C129 23 // SSI0
#define INT_I2C0_TM4C129 24 // I2C0
#define INT_PWM0_FAULT_TM4C129 25 // PWM Fault
#define INT_PWM0_0_TM4C129 26 // PWM Generator 0
#define INT_PWM0_1_TM4C129 27 // PWM Generator 1
#define INT_PWM0_2_TM4C129 28 // PWM Generator 2
#define INT_QEI0_TM4C129 29 // QEI0
#define INT_ADC0SS0_TM4C129 30 // ADC0 Sequence 0
#define INT_ADC0SS1_TM4C129 31 // ADC0 Sequence 1
#define INT_ADC0SS2_TM4C129 32 // ADC0 Sequence 2
#define INT_ADC0SS3_TM4C129 33 // ADC0 Sequence 3
#define INT_WATCHDOG_TM4C129 34 // Watchdog Timers 0 and 1
#define INT_TIMER0A_TM4C129 35 // 16/32-Bit Timer 0A
#define INT_TIMER0B_TM4C129 36 // 16/32-Bit Timer 0B
#define INT_TIMER1A_TM4C129 37 // 16/32-Bit Timer 1A
#define INT_TIMER1B_TM4C129 38 // 16/32-Bit Timer 1B
#define INT_TIMER2A_TM4C129 39 // 16/32-Bit Timer 2A
#define INT_TIMER2B_TM4C129 40 // 16/32-Bit Timer 2B
#define INT_COMP0_TM4C129 41 // Analog Comparator 0
#define INT_COMP1_TM4C129 42 // Analog Comparator 1
#define INT_COMP2_TM4C129 43 // Analog Comparator 2
#define INT_SYSCTL_TM4C129 44 // System Control
#define INT_FLASH_TM4C129 45 // Flash Memory Control
#define INT_GPIOF_TM4C129 46 // GPIO Port F
#define INT_GPIOG_TM4C129 47 // GPIO Port G
#define INT_GPIOH_TM4C129 48 // GPIO Port H
#define INT_UART2_TM4C129 49 // UART2
#define INT_SSI1_TM4C129 50 // SSI1
#define INT_TIMER3A_TM4C129 51 // 16/32-Bit Timer 3A
#define INT_TIMER3B_TM4C129 52 // 16/32-Bit Timer 3B
#define INT_I2C1_TM4C129 53 // I2C1
#define INT_CAN0_TM4C129 54 // CAN 0
#define INT_CAN1_TM4C129 55 // CAN1
#define INT_EMAC0_TM4C129 56 // Ethernet MAC
#define INT_HIBERNATE_TM4C129 57 // HIB
#define INT_USB0_TM4C129 58 // USB MAC
#define INT_PWM0_3_TM4C129 59 // PWM Generator 3
#define INT_UDMA_TM4C129 60 // uDMA 0 Software
#define INT_UDMAERR_TM4C129 61 // uDMA 0 Error
#define INT_ADC1SS0_TM4C129 62 // ADC1 Sequence 0
#define INT_ADC1SS1_TM4C129 63 // ADC1 Sequence 1
#define INT_ADC1SS2_TM4C129 64 // ADC1 Sequence 2
#define INT_ADC1SS3_TM4C129 65 // ADC1 Sequence 3
#define INT_EPI0_TM4C129 66 // EPI 0
#define INT_GPIOJ_TM4C129 67 // GPIO Port J
#define INT_GPIOK_TM4C129 68 // GPIO Port K
#define INT_GPIOL_TM4C129 69 // GPIO Port L
#define INT_SSI2_TM4C129 70 // SSI 2
#define INT_SSI3_TM4C129 71 // SSI 3
#define INT_UART3_TM4C129 72 // UART 3
#define INT_UART4_TM4C129 73 // UART 4
#define INT_UART5_TM4C129 74 // UART 5
#define INT_UART6_TM4C129 75 // UART 6
#define INT_UART7_TM4C129 76 // UART 7
#define INT_I2C2_TM4C129 77 // I2C 2
#define INT_I2C3_TM4C129 78 // I2C 3
#define INT_TIMER4A_TM4C129 79 // Timer 4A
#define INT_TIMER4B_TM4C129 80 // Timer 4B
#define INT_TIMER5A_TM4C129 81 // Timer 5A
#define INT_TIMER5B_TM4C129 82 // Timer 5B
#define INT_SYSEXC_TM4C129 83 // Floating-Point Exception
// (imprecise)
#define INT_I2C4_TM4C129 86 // I2C 4
#define INT_I2C5_TM4C129 87 // I2C 5
#define INT_GPIOM_TM4C129 88 // GPIO Port M
#define INT_GPION_TM4C129 89 // GPIO Port N
#define INT_TAMPER0_TM4C129 91 // Tamper
#define INT_GPIOP0_TM4C129 92 // GPIO Port P (Summary or P0)
#define INT_GPIOP1_TM4C129 93 // GPIO Port P1
#define INT_GPIOP2_TM4C129 94 // GPIO Port P2
#define INT_GPIOP3_TM4C129 95 // GPIO Port P3
#define INT_GPIOP4_TM4C129 96 // GPIO Port P4
#define INT_GPIOP5_TM4C129 97 // GPIO Port P5
#define INT_GPIOP6_TM4C129 98 // GPIO Port P6
#define INT_GPIOP7_TM4C129 99 // GPIO Port P7
#define INT_GPIOQ0_TM4C129 100 // GPIO Port Q (Summary or Q0)
#define INT_GPIOQ1_TM4C129 101 // GPIO Port Q1
#define INT_GPIOQ2_TM4C129 102 // GPIO Port Q2
#define INT_GPIOQ3_TM4C129 103 // GPIO Port Q3
#define INT_GPIOQ4_TM4C129 104 // GPIO Port Q4
#define INT_GPIOQ5_TM4C129 105 // GPIO Port Q5
#define INT_GPIOQ6_TM4C129 106 // GPIO Port Q6
#define INT_GPIOQ7_TM4C129 107 // GPIO Port Q7
#define INT_GPIOR_TM4C129 108 // GPIO Port R
#define INT_GPIOS_TM4C129 109 // GPIO Port S
#define INT_SHA0_TM4C129 110 // SHA/MD5
#define INT_AES0_TM4C129 111 // AES
#define INT_DES0_TM4C129 112 // DES
#define INT_LCD0_TM4C129 113 // LCD
#define INT_TIMER6A_TM4C129 114 // 16/32-Bit Timer 6A
#define INT_TIMER6B_TM4C129 115 // 16/32-Bit Timer 6B
#define INT_TIMER7A_TM4C129 116 // 16/32-Bit Timer 7A
#define INT_TIMER7B_TM4C129 117 // 16/32-Bit Timer 7B
#define INT_I2C6_TM4C129 118 // I2C 6
#define INT_I2C7_TM4C129 119 // I2C 7
#define INT_ONEWIRE0_TM4C129 121 // 1-Wire
#define INT_I2C8_TM4C129 125 // I2C 8
#define INT_I2C9_TM4C129 126 // I2C 9
#define INT_GPIOT_TM4C129 127 // GPIO T
#define NUM_INTERRUPTS_TM4C129 129
//*****************************************************************************
//
// TM4C123 Interrupt Class Definition
//
//*****************************************************************************
#if defined(TARGET_IS_TM4C123_RA1) || defined(TARGET_IS_TM4C123_RA2) || \
defined(TARGET_IS_TM4C123_RA3) || defined(TARGET_IS_TM4C123_RB0) || \
defined(TARGET_IS_TM4C123_RB1) || defined(PART_TM4C1230C3PM) || \
defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) || \
defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || \
defined(PART_TM4C1231D5PM) || defined(PART_TM4C1231D5PZ) || \
defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) || \
defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) || \
defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || \
defined(PART_TM4C1232E6PM) || defined(PART_TM4C1232H6PM) || \
defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) || \
defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || \
defined(PART_TM4C1233E6PZ) || defined(PART_TM4C1233H6PM) || \
defined(PART_TM4C1233H6PZ) || defined(PART_TM4C1236D5PM) || \
defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) || \
defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || \
defined(PART_TM4C1237E6PM) || defined(PART_TM4C1237E6PZ) || \
defined(PART_TM4C1237H6PM) || defined(PART_TM4C1237H6PZ) || \
defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) || \
defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || \
defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || \
defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || \
defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GE6PZ) || \
defined(PART_TM4C123GH6PM) || defined(PART_TM4C123GH6PZ) || \
defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1233H6PGE) || \
defined(PART_TM4C1237H6PGE) || defined(PART_TM4C123BH6PGE) || \
defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123GH6PGE) || \
defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH6ZXR)
#define INT_RESOLVE(intname, class) intname##TM4C123
//*****************************************************************************
//
// TM4C129 Interrupt Class Definition
//
//*****************************************************************************
#elif defined(TARGET_IS_TM4C129_RA0) || defined(PART_TM4C1290NCPDT) || \
defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT) || \
defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || \
defined(PART_TM4C1294NCPDT) || defined(PART_TM4C1294NCZAD) || \
defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD) || \
defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || \
defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT) || \
defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT) || \
defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || \
defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD) || \
defined(PART_TM4C129XNCZAD)
#define INT_RESOLVE(intname, class) intname##TM4C129
#else
#define INT_DEVICE_CLASS "UNKNOWN"
#endif
//*****************************************************************************
//
// Macros to resolve the INT_PERIPH_CLASS name to a common INT_PERIPH name.
//
//*****************************************************************************
#define INT_CONCAT(intname, class) INT_RESOLVE(intname, class)
//*****************************************************************************
//
// The following are defines for the interrupt assignments.
//
//*****************************************************************************
#define INT_ADC0SS0 INT_CONCAT(INT_ADC0SS0_, INT_DEVICE_CLASS)
#define INT_ADC0SS1 INT_CONCAT(INT_ADC0SS1_, INT_DEVICE_CLASS)
#define INT_ADC0SS2 INT_CONCAT(INT_ADC0SS2_, INT_DEVICE_CLASS)
#define INT_ADC0SS3 INT_CONCAT(INT_ADC0SS3_, INT_DEVICE_CLASS)
#define INT_ADC1SS0 INT_CONCAT(INT_ADC1SS0_, INT_DEVICE_CLASS)
#define INT_ADC1SS1 INT_CONCAT(INT_ADC1SS1_, INT_DEVICE_CLASS)
#define INT_ADC1SS2 INT_CONCAT(INT_ADC1SS2_, INT_DEVICE_CLASS)
#define INT_ADC1SS3 INT_CONCAT(INT_ADC1SS3_, INT_DEVICE_CLASS)
#define INT_AES0 INT_CONCAT(INT_AES0_, INT_DEVICE_CLASS)
#define INT_CAN0 INT_CONCAT(INT_CAN0_, INT_DEVICE_CLASS)
#define INT_CAN1 INT_CONCAT(INT_CAN1_, INT_DEVICE_CLASS)
#define INT_COMP0 INT_CONCAT(INT_COMP0_, INT_DEVICE_CLASS)
#define INT_COMP1 INT_CONCAT(INT_COMP1_, INT_DEVICE_CLASS)
#define INT_COMP2 INT_CONCAT(INT_COMP2_, INT_DEVICE_CLASS)
#define INT_DES0 INT_CONCAT(INT_DES0_, INT_DEVICE_CLASS)
#define INT_EMAC0 INT_CONCAT(INT_EMAC0_, INT_DEVICE_CLASS)
#define INT_EPI0 INT_CONCAT(INT_EPI0_, INT_DEVICE_CLASS)
#define INT_FLASH INT_CONCAT(INT_FLASH_, INT_DEVICE_CLASS)
#define INT_GPIOA INT_CONCAT(INT_GPIOA_, INT_DEVICE_CLASS)
#define INT_GPIOB INT_CONCAT(INT_GPIOB_, INT_DEVICE_CLASS)
#define INT_GPIOC INT_CONCAT(INT_GPIOC_, INT_DEVICE_CLASS)
#define INT_GPIOD INT_CONCAT(INT_GPIOD_, INT_DEVICE_CLASS)
#define INT_GPIOE INT_CONCAT(INT_GPIOE_, INT_DEVICE_CLASS)
#define INT_GPIOF INT_CONCAT(INT_GPIOF_, INT_DEVICE_CLASS)
#define INT_GPIOG INT_CONCAT(INT_GPIOG_, INT_DEVICE_CLASS)
#define INT_GPIOH INT_CONCAT(INT_GPIOH_, INT_DEVICE_CLASS)
#define INT_GPIOJ INT_CONCAT(INT_GPIOJ_, INT_DEVICE_CLASS)
#define INT_GPIOK INT_CONCAT(INT_GPIOK_, INT_DEVICE_CLASS)
#define INT_GPIOL INT_CONCAT(INT_GPIOL_, INT_DEVICE_CLASS)
#define INT_GPIOM INT_CONCAT(INT_GPIOM_, INT_DEVICE_CLASS)
#define INT_GPION INT_CONCAT(INT_GPION_, INT_DEVICE_CLASS)
#define INT_GPIOP0 INT_CONCAT(INT_GPIOP0_, INT_DEVICE_CLASS)
#define INT_GPIOP1 INT_CONCAT(INT_GPIOP1_, INT_DEVICE_CLASS)
#define INT_GPIOP2 INT_CONCAT(INT_GPIOP2_, INT_DEVICE_CLASS)
#define INT_GPIOP3 INT_CONCAT(INT_GPIOP3_, INT_DEVICE_CLASS)
#define INT_GPIOP4 INT_CONCAT(INT_GPIOP4_, INT_DEVICE_CLASS)
#define INT_GPIOP5 INT_CONCAT(INT_GPIOP5_, INT_DEVICE_CLASS)
#define INT_GPIOP6 INT_CONCAT(INT_GPIOP6_, INT_DEVICE_CLASS)
#define INT_GPIOP7 INT_CONCAT(INT_GPIOP7_, INT_DEVICE_CLASS)
#define INT_GPIOQ0 INT_CONCAT(INT_GPIOQ0_, INT_DEVICE_CLASS)
#define INT_GPIOQ1 INT_CONCAT(INT_GPIOQ1_, INT_DEVICE_CLASS)
#define INT_GPIOQ2 INT_CONCAT(INT_GPIOQ2_, INT_DEVICE_CLASS)
#define INT_GPIOQ3 INT_CONCAT(INT_GPIOQ3_, INT_DEVICE_CLASS)
#define INT_GPIOQ4 INT_CONCAT(INT_GPIOQ4_, INT_DEVICE_CLASS)
#define INT_GPIOQ5 INT_CONCAT(INT_GPIOQ5_, INT_DEVICE_CLASS)
#define INT_GPIOQ6 INT_CONCAT(INT_GPIOQ6_, INT_DEVICE_CLASS)
#define INT_GPIOQ7 INT_CONCAT(INT_GPIOQ7_, INT_DEVICE_CLASS)
#define INT_GPIOR INT_CONCAT(INT_GPIOR_, INT_DEVICE_CLASS)
#define INT_GPIOS INT_CONCAT(INT_GPIOS_, INT_DEVICE_CLASS)
#define INT_GPIOT INT_CONCAT(INT_GPIOT_, INT_DEVICE_CLASS)
#define INT_HIBERNATE INT_CONCAT(INT_HIBERNATE_, INT_DEVICE_CLASS)
#define INT_I2C0 INT_CONCAT(INT_I2C0_, INT_DEVICE_CLASS)
#define INT_I2C1 INT_CONCAT(INT_I2C1_, INT_DEVICE_CLASS)
#define INT_I2C2 INT_CONCAT(INT_I2C2_, INT_DEVICE_CLASS)
#define INT_I2C3 INT_CONCAT(INT_I2C3_, INT_DEVICE_CLASS)
#define INT_I2C4 INT_CONCAT(INT_I2C4_, INT_DEVICE_CLASS)
#define INT_I2C5 INT_CONCAT(INT_I2C5_, INT_DEVICE_CLASS)
#define INT_I2C6 INT_CONCAT(INT_I2C6_, INT_DEVICE_CLASS)
#define INT_I2C7 INT_CONCAT(INT_I2C7_, INT_DEVICE_CLASS)
#define INT_I2C8 INT_CONCAT(INT_I2C8_, INT_DEVICE_CLASS)
#define INT_I2C9 INT_CONCAT(INT_I2C9_, INT_DEVICE_CLASS)
#define INT_LCD0 INT_CONCAT(INT_LCD0_, INT_DEVICE_CLASS)
#define INT_ONEWIRE0 INT_CONCAT(INT_ONEWIRE0_, INT_DEVICE_CLASS)
#define INT_PWM0_0 INT_CONCAT(INT_PWM0_0_, INT_DEVICE_CLASS)
#define INT_PWM0_1 INT_CONCAT(INT_PWM0_1_, INT_DEVICE_CLASS)
#define INT_PWM0_2 INT_CONCAT(INT_PWM0_2_, INT_DEVICE_CLASS)
#define INT_PWM0_3 INT_CONCAT(INT_PWM0_3_, INT_DEVICE_CLASS)
#define INT_PWM0_FAULT INT_CONCAT(INT_PWM0_FAULT_, INT_DEVICE_CLASS)
#define INT_PWM1_0 INT_CONCAT(INT_PWM1_0_, INT_DEVICE_CLASS)
#define INT_PWM1_1 INT_CONCAT(INT_PWM1_1_, INT_DEVICE_CLASS)
#define INT_PWM1_2 INT_CONCAT(INT_PWM1_2_, INT_DEVICE_CLASS)
#define INT_PWM1_3 INT_CONCAT(INT_PWM1_3_, INT_DEVICE_CLASS)
#define INT_PWM1_FAULT INT_CONCAT(INT_PWM1_FAULT_, INT_DEVICE_CLASS)
#define INT_QEI0 INT_CONCAT(INT_QEI0_, INT_DEVICE_CLASS)
#define INT_QEI1 INT_CONCAT(INT_QEI1_, INT_DEVICE_CLASS)
#define INT_SHA0 INT_CONCAT(INT_SHA0_, INT_DEVICE_CLASS)
#define INT_SSI0 INT_CONCAT(INT_SSI0_, INT_DEVICE_CLASS)
#define INT_SSI1 INT_CONCAT(INT_SSI1_, INT_DEVICE_CLASS)
#define INT_SSI2 INT_CONCAT(INT_SSI2_, INT_DEVICE_CLASS)
#define INT_SSI3 INT_CONCAT(INT_SSI3_, INT_DEVICE_CLASS)
#define INT_SYSCTL INT_CONCAT(INT_SYSCTL_, INT_DEVICE_CLASS)
#define INT_SYSEXC INT_CONCAT(INT_SYSEXC_, INT_DEVICE_CLASS)
#define INT_TAMPER0 INT_CONCAT(INT_TAMPER0_, INT_DEVICE_CLASS)
#define INT_TIMER0A INT_CONCAT(INT_TIMER0A_, INT_DEVICE_CLASS)
#define INT_TIMER0B INT_CONCAT(INT_TIMER0B_, INT_DEVICE_CLASS)
#define INT_TIMER1A INT_CONCAT(INT_TIMER1A_, INT_DEVICE_CLASS)
#define INT_TIMER1B INT_CONCAT(INT_TIMER1B_, INT_DEVICE_CLASS)
#define INT_TIMER2A INT_CONCAT(INT_TIMER2A_, INT_DEVICE_CLASS)
#define INT_TIMER2B INT_CONCAT(INT_TIMER2B_, INT_DEVICE_CLASS)
#define INT_TIMER3A INT_CONCAT(INT_TIMER3A_, INT_DEVICE_CLASS)
#define INT_TIMER3B INT_CONCAT(INT_TIMER3B_, INT_DEVICE_CLASS)
#define INT_TIMER4A INT_CONCAT(INT_TIMER4A_, INT_DEVICE_CLASS)
#define INT_TIMER4B INT_CONCAT(INT_TIMER4B_, INT_DEVICE_CLASS)
#define INT_TIMER5A INT_CONCAT(INT_TIMER5A_, INT_DEVICE_CLASS)
#define INT_TIMER5B INT_CONCAT(INT_TIMER5B_, INT_DEVICE_CLASS)
#define INT_TIMER6A INT_CONCAT(INT_TIMER6A_, INT_DEVICE_CLASS)
#define INT_TIMER6B INT_CONCAT(INT_TIMER6B_, INT_DEVICE_CLASS)
#define INT_TIMER7A INT_CONCAT(INT_TIMER7A_, INT_DEVICE_CLASS)
#define INT_TIMER7B INT_CONCAT(INT_TIMER7B_, INT_DEVICE_CLASS)
#define INT_UART0 INT_CONCAT(INT_UART0_, INT_DEVICE_CLASS)
#define INT_UART1 INT_CONCAT(INT_UART1_, INT_DEVICE_CLASS)
#define INT_UART2 INT_CONCAT(INT_UART2_, INT_DEVICE_CLASS)
#define INT_UART3 INT_CONCAT(INT_UART3_, INT_DEVICE_CLASS)
#define INT_UART4 INT_CONCAT(INT_UART4_, INT_DEVICE_CLASS)
#define INT_UART5 INT_CONCAT(INT_UART5_, INT_DEVICE_CLASS)
#define INT_UART6 INT_CONCAT(INT_UART6_, INT_DEVICE_CLASS)
#define INT_UART7 INT_CONCAT(INT_UART7_, INT_DEVICE_CLASS)
#define INT_UDMA INT_CONCAT(INT_UDMA_, INT_DEVICE_CLASS)
#define INT_UDMAERR INT_CONCAT(INT_UDMAERR_, INT_DEVICE_CLASS)
#define INT_USB0 INT_CONCAT(INT_USB0_, INT_DEVICE_CLASS)
#define INT_WATCHDOG INT_CONCAT(INT_WATCHDOG_, INT_DEVICE_CLASS)
#define INT_WTIMER0A INT_CONCAT(INT_WTIMER0A_, INT_DEVICE_CLASS)
#define INT_WTIMER0B INT_CONCAT(INT_WTIMER0B_, INT_DEVICE_CLASS)
#define INT_WTIMER1A INT_CONCAT(INT_WTIMER1A_, INT_DEVICE_CLASS)
#define INT_WTIMER1B INT_CONCAT(INT_WTIMER1B_, INT_DEVICE_CLASS)
#define INT_WTIMER2A INT_CONCAT(INT_WTIMER2A_, INT_DEVICE_CLASS)
#define INT_WTIMER2B INT_CONCAT(INT_WTIMER2B_, INT_DEVICE_CLASS)
#define INT_WTIMER3A INT_CONCAT(INT_WTIMER3A_, INT_DEVICE_CLASS)
#define INT_WTIMER3B INT_CONCAT(INT_WTIMER3B_, INT_DEVICE_CLASS)
#define INT_WTIMER4A INT_CONCAT(INT_WTIMER4A_, INT_DEVICE_CLASS)
#define INT_WTIMER4B INT_CONCAT(INT_WTIMER4B_, INT_DEVICE_CLASS)
#define INT_WTIMER5A INT_CONCAT(INT_WTIMER5A_, INT_DEVICE_CLASS)
#define INT_WTIMER5B INT_CONCAT(INT_WTIMER5B_, INT_DEVICE_CLASS)
//*****************************************************************************
//
// The following are defines for the total number of interrupts.
//
//*****************************************************************************
#define NUM_INTERRUPTS INT_CONCAT(NUM_INTERRUPTS_, INT_DEVICE_CLASS)
//*****************************************************************************
//
// The following are defines for the total number of priority levels.
//
//*****************************************************************************
#define NUM_PRIORITY 8
#define NUM_PRIORITY_BITS 3
#endif // __HW_INTS_H__

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//*****************************************************************************
//
// hw_lcd.h - Defines and macros used when accessing the LCD controller.
//
// Copyright (c) 2011-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_LCD_H__
#define __HW_LCD_H__
//*****************************************************************************
//
// The following are defines for the LCD register offsets.
//
//*****************************************************************************
#define LCD_O_PID 0x00000000 // LCD PID Register Format
#define LCD_O_CTL 0x00000004 // LCD Control
#define LCD_O_LIDDCTL 0x0000000C // LCD LIDD Control
#define LCD_O_LIDDCS0CFG 0x00000010 // LCD LIDD CS0 Configuration
#define LCD_O_LIDDCS0ADDR 0x00000014 // LIDD CS0 Read/Write Address
#define LCD_O_LIDDCS0DATA 0x00000018 // LIDD CS0 Data Read/Write
// Initiation
#define LCD_O_LIDDCS1CFG 0x0000001C // LIDD CS1 Configuration
#define LCD_O_LIDDCS1ADDR 0x00000020 // LIDD CS1 Address Read/Write
// Initiation
#define LCD_O_LIDDCS1DATA 0x00000024 // LIDD CS1 Data Read/Write
// Initiation
#define LCD_O_RASTRCTL 0x00000028 // LCD Raster Control
#define LCD_O_RASTRTIM0 0x0000002C // LCD Raster Timing 0
#define LCD_O_RASTRTIM1 0x00000030 // LCD Raster Timing 1
#define LCD_O_RASTRTIM2 0x00000034 // LCD Raster Timing 2
#define LCD_O_RASTRSUBP1 0x00000038 // LCD Raster Subpanel Display 1
#define LCD_O_RASTRSUBP2 0x0000003C // LCD Raster Subpanel Display 2
#define LCD_O_DMACTL 0x00000040 // LCD DMA Control
#define LCD_O_DMABAFB0 0x00000044 // LCD DMA Frame Buffer 0 Base
// Address
#define LCD_O_DMACAFB0 0x00000048 // LCD DMA Frame Buffer 0 Ceiling
// Address
#define LCD_O_DMABAFB1 0x0000004C // LCD DMA Frame Buffer 1 Base
// Address
#define LCD_O_DMACAFB1 0x00000050 // LCD DMA Frame Buffer 1 Ceiling
// Address
#define LCD_O_SYSCFG 0x00000054 // LCD System Configuration
// Register
#define LCD_O_RISSET 0x00000058 // LCD Interrupt Raw Status and Set
// Register
#define LCD_O_MISCLR 0x0000005C // LCD Interrupt Status and Clear
#define LCD_O_IM 0x00000060 // LCD Interrupt Mask
#define LCD_O_IENC 0x00000064 // LCD Interrupt Enable Clear
#define LCD_O_CLKEN 0x0000006C // LCD Clock Enable
#define LCD_O_CLKRESET 0x00000070 // LCD Clock Resets
//*****************************************************************************
//
// The following are defines for the bit fields in the LCD_O_PID register.
//
//*****************************************************************************
#define LCD_PID_MAJOR_M 0x00000700 // Major Release Number
#define LCD_PID_MINOR_M 0x0000003F // Minor Release Number
#define LCD_PID_MAJOR_S 8
#define LCD_PID_MINOR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the LCD_O_CTL register.
//
//*****************************************************************************
#define LCD_CTL_CLKDIV_M 0x0000FF00 // Clock Divisor
#define LCD_CTL_UFLOWRST 0x00000002 // Underflow Restart
#define LCD_CTL_LCDMODE 0x00000001 // LCD Mode Select
#define LCD_CTL_CLKDIV_S 8
//*****************************************************************************
//
// The following are defines for the bit fields in the LCD_O_LIDDCTL register.
//
//*****************************************************************************
#define LCD_LIDDCTL_DMACS 0x00000200 // CS0/CS1 Select for LIDD DMA
// Writes
#define LCD_LIDDCTL_DMAEN 0x00000100 // LIDD DMA Enable
#define LCD_LIDDCTL_CS1E1 0x00000080 // Chip Select 1 (CS1)/Enable 1(E1)
// Polarity Control
#define LCD_LIDDCTL_CS0E0 0x00000040 // Chip Select 0 (CS0)/Enable 0
// (E0) Polarity Control
#define LCD_LIDDCTL_WRDIRINV 0x00000020 // Write Strobe (WR) /Direction
// (DIR) Polarity Control
#define LCD_LIDDCTL_RDEN 0x00000010 // Read Strobe (RD) /Direct Enable
// (EN) Polarity Control
#define LCD_LIDDCTL_ALE 0x00000008 // Address Latch Enable (ALE)
// Polarity Control
#define LCD_LIDDCTL_MODE_M 0x00000007 // LIDD Mode Select
#define LCD_LIDDCTL_MODE_SYNCM68 \
0x00000000 // Synchronous Motorola 6800 Mode
#define LCD_LIDDCTL_MODE_ASYNCM68 \
0x00000001 // Asynchronous Motorola 6800 Mode
#define LCD_LIDDCTL_MODE_SYNCM80 \
0x00000002 // Synchronous Intel 8080 mode
#define LCD_LIDDCTL_MODE_ASYNCM80 \
0x00000003 // Asynchronous Intel 8080 mode
#define LCD_LIDDCTL_MODE_ASYNCHIT \
0x00000004 // Asynchronous Hitachi mode
//*****************************************************************************
//
// The following are defines for the bit fields in the LCD_O_LIDDCS0CFG
// register.
//
//*****************************************************************************
#define LCD_LIDDCS0CFG_WRSU_M 0xF8000000 // Write Strobe (WR) Set-Up Cycles
#define LCD_LIDDCS0CFG_WRDUR_M 0x07E00000 // Write Strobe (WR) Duration
// Cycles
#define LCD_LIDDCS0CFG_WRHOLD_M 0x001E0000 // Write Strobe (WR) Hold cycles
#define LCD_LIDDCS0CFG_RDSU_M 0x0001F000 // Read Strobe (RD) Set-Up cycles
#define LCD_LIDDCS0CFG_RDDUR_M 0x00000FC0 // Read Strobe (RD) Duration cycles
#define LCD_LIDDCS0CFG_RDHOLD_M 0x0000003C // Read Strobe (RD) Hold cycles
#define LCD_LIDDCS0CFG_GAP_M 0x00000003 // Field value defines the number
// of LCDMCLK cycles (GAP +1)
// between the end of one CS0
// (LCDAC) device access and the
// start of another CS0 (LCDAC)
// device access unless the two
// accesses are both reads
#define LCD_LIDDCS0CFG_WRSU_S 27
#define LCD_LIDDCS0CFG_WRDUR_S 21
#define LCD_LIDDCS0CFG_WRHOLD_S 17
#define LCD_LIDDCS0CFG_RDSU_S 12
#define LCD_LIDDCS0CFG_RDDUR_S 6
#define LCD_LIDDCS0CFG_RDHOLD_S 2
#define LCD_LIDDCS0CFG_GAP_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the LCD_O_LIDDCS0ADDR
// register.
//
//*****************************************************************************
#define LCD_LIDDCS0ADDR_CS0ADDR_M \
0x0000FFFF // LCD Address
#define LCD_LIDDCS0ADDR_CS0ADDR_S \
0
//*****************************************************************************
//
// The following are defines for the bit fields in the LCD_O_LIDDCS0DATA
// register.
//
//*****************************************************************************
#define LCD_LIDDCS0DATA_CS0DATA_M \
0x0000FFFF // LCD Data Read/Write
#define LCD_LIDDCS0DATA_CS0DATA_S \
0
//*****************************************************************************
//
// The following are defines for the bit fields in the LCD_O_LIDDCS1CFG
// register.
//
//*****************************************************************************
#define LCD_LIDDCS1CFG_WRSU_M 0xF8000000 // Write Strobe (WR) Set-Up Cycles
#define LCD_LIDDCS1CFG_WRDUR_M 0x07E00000 // Write Strobe (WR) Duration
// Cycles
#define LCD_LIDDCS1CFG_WRHOLD_M 0x001E0000 // Write Strobe (WR) Hold cycles
#define LCD_LIDDCS1CFG_RDSU_M 0x0001F000 // Read Strobe (RD) Set-Up cycles
#define LCD_LIDDCS1CFG_RDDUR_M 0x00000FC0 // Read Strobe (RD) Duration cycles
#define LCD_LIDDCS1CFG_RDHOLD_M 0x0000003C // Read Strobe (RD) Hold cycles
#define LCD_LIDDCS1CFG_GAP_M 0x00000003 // Field value defines the number
// of LCDMCLK cycles (GAP + 1)
// between the end of one CS1
// (LCDAC) device access and the
// start of another CS0 (LCDAC)
// device access unless the two
// accesses are both reads
#define LCD_LIDDCS1CFG_WRSU_S 27
#define LCD_LIDDCS1CFG_WRDUR_S 21
#define LCD_LIDDCS1CFG_WRHOLD_S 17
#define LCD_LIDDCS1CFG_RDSU_S 12
#define LCD_LIDDCS1CFG_RDDUR_S 6
#define LCD_LIDDCS1CFG_RDHOLD_S 2
#define LCD_LIDDCS1CFG_GAP_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the LCD_O_LIDDCS1ADDR
// register.
//
//*****************************************************************************
#define LCD_LIDDCS1ADDR_CS1ADDR_M \
0x0000FFFF // LCD Address Bus
#define LCD_LIDDCS1ADDR_CS1ADDR_S \
0
//*****************************************************************************
//
// The following are defines for the bit fields in the LCD_O_LIDDCS1DATA
// register.
//
//*****************************************************************************
#define LCD_LIDDCS1DATA_CS0DATA_M \
0x0000FFFF // LCD Data Read/Write Initiation
#define LCD_LIDDCS1DATA_CS0DATA_S \
0
//*****************************************************************************
//
// The following are defines for the bit fields in the LCD_O_RASTRCTL register.
//
//*****************************************************************************
#define LCD_RASTRCTL_TFT24UPCK 0x04000000 // 24-bit TFT Mode Packing
#define LCD_RASTRCTL_TFT24 0x02000000 // 24-Bit TFT Mode
#define LCD_RASTRCTL_FRMBUFSZ 0x01000000 // Frame Buffer Select
#define LCD_RASTRCTL_TFTMAP 0x00800000 // TFT Mode Alternate Signal
// Mapping for Palettized
// Framebuffer
#define LCD_RASTRCTL_NIBMODE 0x00400000 // Nibble Mode
#define LCD_RASTRCTL_PALMODE_M 0x00300000 // Pallette Loading Mode
#define LCD_RASTRCTL_PALMODE_PALDAT \
0x00000000 // Palette and data loading, reset
// value
#define LCD_RASTRCTL_PALMODE_PAL \
0x00100000 // Palette loading only
#define LCD_RASTRCTL_PALMODE_DAT \
0x00200000 // Data loading only
#define LCD_RASTRCTL_REQDLY_M 0x000FF000 // Palette Loading Delay
#define LCD_RASTRCTL_MONO8B 0x00000200 // Mono 8-Bit
#define LCD_RASTRCTL_RDORDER 0x00000100 // Raster Data Order Select
#define LCD_RASTRCTL_LCDTFT 0x00000080 // LCD TFT
#define LCD_RASTRCTL_LCDBW 0x00000002 // LCD Monochrome
#define LCD_RASTRCTL_LCDEN 0x00000001 // LCD Controller Enable for Raster
// Operations
#define LCD_RASTRCTL_REQDLY_S 12
//*****************************************************************************
//
// The following are defines for the bit fields in the LCD_O_RASTRTIM0
// register.
//
//*****************************************************************************
#define LCD_RASTRTIM0_HBP_M 0xFF000000 // Horizontal Back Porch Lowbits
#define LCD_RASTRTIM0_HFP_M 0x00FF0000 // Horizontal Front Porch Lowbits
#define LCD_RASTRTIM0_HSW_M 0x0000FC00 // Horizontal Sync Pulse Width
// Lowbits
#define LCD_RASTRTIM0_PPL_M 0x000003F0 // Pixels-per-line LSB[9:4]
#define LCD_RASTRTIM0_MSBPPL 0x00000008 // Pixels-per-line MSB[10]
#define LCD_RASTRTIM0_HBP_S 24
#define LCD_RASTRTIM0_HFP_S 16
#define LCD_RASTRTIM0_HSW_S 10
#define LCD_RASTRTIM0_PPL_S 4
#define LCD_RASTRTIM0_MSBPPL_S 3
//*****************************************************************************
//
// The following are defines for the bit fields in the LCD_O_RASTRTIM1
// register.
//
//*****************************************************************************
#define LCD_RASTRTIM1_VBP_M 0xFF000000 // Vertical Back Porch
#define LCD_RASTRTIM1_VFP_M 0x00FF0000 // Vertical Front Porch
#define LCD_RASTRTIM1_VSW_M 0x0000FC00 // Vertical Sync Width Pulse
#define LCD_RASTRTIM1_LPP_M 0x000003FF // Lines Per Panel
#define LCD_RASTRTIM1_VBP_S 24
#define LCD_RASTRTIM1_VFP_S 16
#define LCD_RASTRTIM1_VSW_S 10
#define LCD_RASTRTIM1_LPP_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the LCD_O_RASTRTIM2
// register.
//
//*****************************************************************************
#define LCD_RASTRTIM2_HSW_M 0x78000000 // Bits 9:6 of the horizontal sync
// width field
#define LCD_RASTRTIM2_MSBLPP 0x04000000 // MSB of Lines Per Panel
#define LCD_RASTRTIM2_PXLCLKCTL 0x02000000 // Hsync/Vsync Pixel Clock Control
// On/Off
#define LCD_RASTRTIM2_PSYNCRF 0x01000000 // Program HSYNC/VSYNC Rise or Fall
#define LCD_RASTRTIM2_INVOE 0x00800000 // Invert Output Enable
#define LCD_RASTRTIM2_INVPXLCLK 0x00400000 // Invert Pixel Clock
#define LCD_RASTRTIM2_IHS 0x00200000 // Invert Hysync
#define LCD_RASTRTIM2_IVS 0x00100000 // Invert Vsync
#define LCD_RASTRTIM2_ACBI_M 0x000F0000 // AC Bias Pins Transitions per
// Interrupt
#define LCD_RASTRTIM2_ACBF_M 0x0000FF00 // AC Bias Pin Frequency
#define LCD_RASTRTIM2_MSBHBP_M 0x00000030 // Bits 9:8 of the horizontal back
// porch field
#define LCD_RASTRTIM2_MSBHFP_M 0x00000003 // Bits 9:8 of the horizontal front
// porch field
#define LCD_RASTRTIM2_HSW_S 27
#define LCD_RASTRTIM2_MSBLPP_S 26
#define LCD_RASTRTIM2_ACBI_S 16
#define LCD_RASTRTIM2_ACBF_S 8
#define LCD_RASTRTIM2_MSBHBP_S 4
#define LCD_RASTRTIM2_MSBHFP_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the LCD_O_RASTRSUBP1
// register.
//
//*****************************************************************************
#define LCD_RASTRSUBP1_SPEN 0x80000000 // Sub Panel Enable
#define LCD_RASTRSUBP1_HOLS 0x20000000 // High or Low Signal
#define LCD_RASTRSUBP1_LPPT_M 0x03FF0000 // Line Per Panel Threshold
#define LCD_RASTRSUBP1_DPDLSB_M 0x0000FFFF // Default Pixel Data LSB[15:0]
#define LCD_RASTRSUBP1_LPPT_S 16
#define LCD_RASTRSUBP1_DPDLSB_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the LCD_O_RASTRSUBP2
// register.
//
//*****************************************************************************
#define LCD_RASTRSUBP2_LPPTMSB 0x00000100 // Lines Per Panel Threshold Bit 10
#define LCD_RASTRSUBP2_DPDMSB_M 0x000000FF // Default Pixel Data MSB [23:16]
#define LCD_RASTRSUBP2_DPDMSB_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the LCD_O_DMACTL register.
//
//*****************************************************************************
#define LCD_DMACTL_FIFORDY_M 0x00000700 // DMA FIFO threshold
#define LCD_DMACTL_FIFORDY_8 0x00000000 // 8 words
#define LCD_DMACTL_FIFORDY_16 0x00000100 // 16 words
#define LCD_DMACTL_FIFORDY_32 0x00000200 // 32 words
#define LCD_DMACTL_FIFORDY_64 0x00000300 // 64 words
#define LCD_DMACTL_FIFORDY_128 0x00000400 // 128 words
#define LCD_DMACTL_FIFORDY_256 0x00000500 // 256 words
#define LCD_DMACTL_FIFORDY_512 0x00000600 // 512 words
#define LCD_DMACTL_BURSTSZ_M 0x00000070 // Burst Size setting for DMA
// transfers (all DMA transfers are
// 32 bits wide):
#define LCD_DMACTL_BURSTSZ_4 0x00000020 // burst size of 4
#define LCD_DMACTL_BURSTSZ_8 0x00000030 // burst size of 8
#define LCD_DMACTL_BURSTSZ_16 0x00000040 // burst size of 16
#define LCD_DMACTL_BYTESWAP 0x00000008 // This bit controls the bytelane
// ordering of the data on the
// output of the DMA module
#define LCD_DMACTL_BIGDEND 0x00000002 // Big Endian Enable
#define LCD_DMACTL_FMODE 0x00000001 // Frame Mode
//*****************************************************************************
//
// The following are defines for the bit fields in the LCD_O_DMABAFB0 register.
//
//*****************************************************************************
#define LCD_DMABAFB0_FB0BA_M 0xFFFFFFFC // Frame Buffer 0 Base Address
// pointer
#define LCD_DMABAFB0_FB0BA_S 2
//*****************************************************************************
//
// The following are defines for the bit fields in the LCD_O_DMACAFB0 register.
//
//*****************************************************************************
#define LCD_DMACAFB0_FB0CA_M 0xFFFFFFFC // Frame Buffer 0 Ceiling Address
// pointer
#define LCD_DMACAFB0_FB0CA_S 2
//*****************************************************************************
//
// The following are defines for the bit fields in the LCD_O_DMABAFB1 register.
//
//*****************************************************************************
#define LCD_DMABAFB1_FB1BA_M 0xFFFFFFFC // Frame Buffer 1 Base Address
// pointer
#define LCD_DMABAFB1_FB1BA_S 2
//*****************************************************************************
//
// The following are defines for the bit fields in the LCD_O_DMACAFB1 register.
//
//*****************************************************************************
#define LCD_DMACAFB1_FB1CA_M 0xFFFFFFFC // Frame Buffer 1 Ceiling Address
// pointer
#define LCD_DMACAFB1_FB1CA_S 2
//*****************************************************************************
//
// The following are defines for the bit fields in the LCD_O_SYSCFG register.
//
//*****************************************************************************
#define LCD_SYSCFG_STDBY_M 0x00000030 // Standby Mode
#define LCD_SYSCFG_STDBY_FORCE 0x00000000 // Force-standby mode: local
// initiator is unconditionally
// placed in standby state. Backup
// mode, for debug only
#define LCD_SYSCFG_STDBY_NONE 0x00000010 // No-standby mode: local initiator
// is unconditionally placed out of
// standby state. Backup mode, for
// debug only
#define LCD_SYSCFG_STDBY_SMART 0x00000020 // Smart-standby mode: local
// initiator standby status depends
// on local conditions, that is,
// the module's functional
// requirement from the initiator.
// IP module shall not generate
// (initiator-related) wakeup
// events
#define LCD_SYSCFG_IDLEMODE_M 0x0000000C // Idle Mode
#define LCD_SYSCFG_IDLEMODE_FORCE \
0x00000000 // Force-idle mode: local target's
// idle state follows
// (acknowledges) the system's idle
// requests unconditionally, that
// is, regardless of the IP
// module's internal requirements.
// Backup mode, for debug only
#define LCD_SYSCFG_IDLEMODE_NONE \
0x00000004 // No-idle mode: local target never
// enters idle state. Backup mode,
// for debug only
#define LCD_SYSCFG_IDLEMODE_SMART \
0x00000008 // Smart-idle mode: local target's
// idle state eventually follows
// (acknowledges) the system's idle
// requests, depending on the IP
// module's internal requirements.
// IP module shall not generate
// (IRQ- or DMA-requestrelated)
// wakeup events
//*****************************************************************************
//
// The following are defines for the bit fields in the LCD_O_RISSET register.
//
//*****************************************************************************
#define LCD_RISSET_EOF1 0x00000200 // DMA End-of-Frame 1 Raw Interrupt
// Status and Set
#define LCD_RISSET_EOF0 0x00000100 // DMA End-of-Frame 0 Raw Interrupt
// Status and Set
#define LCD_RISSET_PALLOAD 0x00000040 // DMA Palette Loaded Raw Interrupt
// Status and Set
#define LCD_RISSET_FIFOU 0x00000020 // DMA FIFO Underflow Raw Interrupt
// Status and Set
#define LCD_RISSET_ACBS 0x00000008 // AC Bias Count Raw Interrupt
// Status and Set
#define LCD_RISSET_SYNCS 0x00000004 // Frame Synchronization Lost Raw
// Interrupt Status and Set
#define LCD_RISSET_RRASTRDONE 0x00000002 // Raster Mode Frame Done interrupt
#define LCD_RISSET_DONE 0x00000001 // Raster or LIDD Frame Done
// (shared, depends on whether
// Raster or LIDD mode enabled) Raw
// Interrupt Status and Set
//*****************************************************************************
//
// The following are defines for the bit fields in the LCD_O_MISCLR register.
//
//*****************************************************************************
#define LCD_MISCLR_EOF1 0x00000200 // DMA End-of-Frame 1 Enabled
// Interrupt and Clear
#define LCD_MISCLR_EOF0 0x00000100 // DMA End-of-Frame 0 Raw Interrupt
// and Clear
#define LCD_MISCLR_PALLOAD 0x00000040 // DMA Palette Loaded Enabled
// Interrupt and Clear
#define LCD_MISCLR_FIFOU 0x00000020 // DMA FIFO Underflow Enabled
// Interrupt and Clear
#define LCD_MISCLR_ACBS 0x00000008 // AC Bias Count Enabled Interrupt
// and Clear
#define LCD_MISCLR_SYNCS 0x00000004 // Frame Synchronization Lost
// Enabled Interrupt and Clear
#define LCD_MISCLR_RRASTRDONE 0x00000002 // Raster Mode Frame Done interrupt
#define LCD_MISCLR_DONE 0x00000001 // Raster or LIDD Frame Done
// (shared, depends on whether
// Raster or LIDD mode enabled)
// Enabled Interrupt and Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the LCD_O_IM register.
//
//*****************************************************************************
#define LCD_IM_EOF1 0x00000200 // DMA End-of-Frame 1 Interrupt
// Enable Set
#define LCD_IM_EOF0 0x00000100 // DMA End-of-Frame 0 Interrupt
// Enable Set
#define LCD_IM_PALLOAD 0x00000040 // DMA Palette Loaded Interrupt
// Enable Set
#define LCD_IM_FIFOU 0x00000020 // DMA FIFO Underflow Interrupt
// Enable Set
#define LCD_IM_ACBS 0x00000008 // AC Bias Count Interrupt Enable
// Set
#define LCD_IM_SYNCS 0x00000004 // Frame Synchronization Lost
// Interrupt Enable Set
#define LCD_IM_RRASTRDONE 0x00000002 // Raster Mode Frame Done Interrupt
// Enable Set
#define LCD_IM_DONE 0x00000001 // Raster or LIDD Frame Done
// (shared, depends on whether
// Raster or LIDD mode enabled)
// Interrupt Enable Set
//*****************************************************************************
//
// The following are defines for the bit fields in the LCD_O_IENC register.
//
//*****************************************************************************
#define LCD_IENC_EOF1 0x00000200 // DMA End-of-Frame 1 Interrupt
// Enable Clear
#define LCD_IENC_EOF0 0x00000100 // DMA End-of-Frame 0 Interrupt
// Enable Clear
#define LCD_IENC_PALLOAD 0x00000040 // DMA Palette Loaded Interrupt
// Enable Clear
#define LCD_IENC_FIFOU 0x00000020 // DMA FIFO Underflow Interrupt
// Enable Clear
#define LCD_IENC_ACBS 0x00000008 // AC Bias Count Interrupt Enable
// Clear
#define LCD_IENC_SYNCS 0x00000004 // Frame Synchronization Lost
// Interrupt Enable Clear
#define LCD_IENC_RRASTRDONE 0x00000002 // Raster Mode Frame Done Interrupt
// Enable Clear
#define LCD_IENC_DONE 0x00000001 // Raster or LIDD Frame Done
// (shared, depends on whether
// Raster or LIDD mode enabled)
// Interrupt Enable Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the LCD_O_CLKEN register.
//
//*****************************************************************************
#define LCD_CLKEN_DMA 0x00000004 // DMA Clock Enable
#define LCD_CLKEN_LIDD 0x00000002 // LIDD Submodule Clock Enable
#define LCD_CLKEN_CORE 0x00000001 // LCD Core Clock Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the LCD_O_CLKRESET register.
//
//*****************************************************************************
#define LCD_CLKRESET_MAIN 0x00000008 // Software Reset for the entire
// LCD module
#define LCD_CLKRESET_DMA 0x00000004 // Software Reset for the DMA
// submodule
#define LCD_CLKRESET_LIDD 0x00000002 // Software Reset for the LIDD
// submodule (character displays)
#define LCD_CLKRESET_CORE 0x00000001 // Software Reset for the Core,
// which encompasses the Raster
// Active Matrix and Passive Matrix
// logic
#endif // __HW_LCD_H__

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//*****************************************************************************
//
// hw_memmap.h - Macros defining the memory map of the device.
//
// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_MEMMAP_H__
#define __HW_MEMMAP_H__
//*****************************************************************************
//
// The following are defines for the base address of the memories and
// peripherals.
//
//*****************************************************************************
#define FLASH_BASE 0x00000000 // FLASH memory
#define SRAM_BASE 0x20000000 // SRAM memory
#define WATCHDOG0_BASE 0x40000000 // Watchdog0
#define WATCHDOG1_BASE 0x40001000 // Watchdog1
#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A
#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B
#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C
#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D
#define SSI0_BASE 0x40008000 // SSI0
#define SSI1_BASE 0x40009000 // SSI1
#define SSI2_BASE 0x4000A000 // SSI2
#define SSI3_BASE 0x4000B000 // SSI3
#define UART0_BASE 0x4000C000 // UART0
#define UART1_BASE 0x4000D000 // UART1
#define UART2_BASE 0x4000E000 // UART2
#define UART3_BASE 0x4000F000 // UART3
#define UART4_BASE 0x40010000 // UART4
#define UART5_BASE 0x40011000 // UART5
#define UART6_BASE 0x40012000 // UART6
#define UART7_BASE 0x40013000 // UART7
#define I2C0_BASE 0x40020000 // I2C0
#define I2C1_BASE 0x40021000 // I2C1
#define I2C2_BASE 0x40022000 // I2C2
#define I2C3_BASE 0x40023000 // I2C3
#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E
#define GPIO_PORTF_BASE 0x40025000 // GPIO Port F
#define GPIO_PORTG_BASE 0x40026000 // GPIO Port G
#define GPIO_PORTH_BASE 0x40027000 // GPIO Port H
#define PWM0_BASE 0x40028000 // Pulse Width Modulator (PWM)
#define PWM1_BASE 0x40029000 // Pulse Width Modulator (PWM)
#define QEI0_BASE 0x4002C000 // QEI0
#define QEI1_BASE 0x4002D000 // QEI1
#define TIMER0_BASE 0x40030000 // Timer0
#define TIMER1_BASE 0x40031000 // Timer1
#define TIMER2_BASE 0x40032000 // Timer2
#define TIMER3_BASE 0x40033000 // Timer3
#define TIMER4_BASE 0x40034000 // Timer4
#define TIMER5_BASE 0x40035000 // Timer5
#define WTIMER0_BASE 0x40036000 // Wide Timer0
#define WTIMER1_BASE 0x40037000 // Wide Timer1
#define ADC0_BASE 0x40038000 // ADC0
#define ADC1_BASE 0x40039000 // ADC1
#define COMP_BASE 0x4003C000 // Analog comparators
#define GPIO_PORTJ_BASE 0x4003D000 // GPIO Port J
#define CAN0_BASE 0x40040000 // CAN0
#define CAN1_BASE 0x40041000 // CAN1
#define WTIMER2_BASE 0x4004C000 // Wide Timer2
#define WTIMER3_BASE 0x4004D000 // Wide Timer3
#define WTIMER4_BASE 0x4004E000 // Wide Timer4
#define WTIMER5_BASE 0x4004F000 // Wide Timer5
#define USB0_BASE 0x40050000 // USB 0 Controller
#define GPIO_PORTA_AHB_BASE 0x40058000 // GPIO Port A (high speed)
#define GPIO_PORTB_AHB_BASE 0x40059000 // GPIO Port B (high speed)
#define GPIO_PORTC_AHB_BASE 0x4005A000 // GPIO Port C (high speed)
#define GPIO_PORTD_AHB_BASE 0x4005B000 // GPIO Port D (high speed)
#define GPIO_PORTE_AHB_BASE 0x4005C000 // GPIO Port E (high speed)
#define GPIO_PORTF_AHB_BASE 0x4005D000 // GPIO Port F (high speed)
#define GPIO_PORTG_AHB_BASE 0x4005E000 // GPIO Port G (high speed)
#define GPIO_PORTH_AHB_BASE 0x4005F000 // GPIO Port H (high speed)
#define GPIO_PORTJ_AHB_BASE 0x40060000 // GPIO Port J (high speed)
#define GPIO_PORTK_BASE 0x40061000 // GPIO Port K
#define GPIO_PORTL_BASE 0x40062000 // GPIO Port L
#define GPIO_PORTM_BASE 0x40063000 // GPIO Port M
#define GPIO_PORTN_BASE 0x40064000 // GPIO Port N
#define GPIO_PORTP_BASE 0x40065000 // GPIO Port P
#define GPIO_PORTQ_BASE 0x40066000 // GPIO Port Q
#define GPIO_PORTR_BASE 0x40067000 // General-Purpose Input/Outputs
// (GPIOs)
#define GPIO_PORTS_BASE 0x40068000 // General-Purpose Input/Outputs
// (GPIOs)
#define GPIO_PORTT_BASE 0x40069000 // General-Purpose Input/Outputs
// (GPIOs)
#define EEPROM_BASE 0x400AF000 // EEPROM memory
#define ONEWIRE0_BASE 0x400B6000 // 1-Wire Master Module
#define I2C8_BASE 0x400B8000 // I2C8
#define I2C9_BASE 0x400B9000 // I2C9
#define I2C4_BASE 0x400C0000 // I2C4
#define I2C5_BASE 0x400C1000 // I2C5
#define I2C6_BASE 0x400C2000 // I2C6
#define I2C7_BASE 0x400C3000 // I2C7
#define EPI0_BASE 0x400D0000 // EPI0
#define TIMER6_BASE 0x400E0000 // General-Purpose Timers
#define TIMER7_BASE 0x400E1000 // General-Purpose Timers
#define EMAC0_BASE 0x400EC000 // Ethernet Controller
#define SYSEXC_BASE 0x400F9000 // System Exception Module
#define HIB_BASE 0x400FC000 // Hibernation Module
#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller
#define SYSCTL_BASE 0x400FE000 // System Control
#define UDMA_BASE 0x400FF000 // uDMA Controller
#define CCM0_BASE 0x44030000 // Cyclical Redundancy Check (CRC)
#define SHAMD5_BASE 0x44034000 // SHA/MD5 Accelerator
#define AES_BASE 0x44036000 // Advance Encryption
// Hardware-Accelerated Module
#define DES_BASE 0x44038000 // Data Encryption Standard
// Accelerator (DES)
#define LCD0_BASE 0x44050000 // LCD Controller
#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell
#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace
#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint
#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl
#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit
#endif // __HW_MEMMAP_H__

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//*****************************************************************************
//
// hw_onewire.h - Macros used when accessing the One wire hardware.
//
// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_ONEWIRE_H__
#define __HW_ONEWIRE_H__
//*****************************************************************************
//
// The following are defines for the One wire register offsets.
//
//*****************************************************************************
#define ONEWIRE_O_CS 0x00000000 // 1-Wire Control and Status
#define ONEWIRE_O_TIM 0x00000004 // 1-Wire Timing Override
#define ONEWIRE_O_DATW 0x00000008 // 1-Wire Data Write
#define ONEWIRE_O_DATR 0x0000000C // 1-Wire Data Read
#define ONEWIRE_O_IM 0x00000100 // 1-Wire Interrupt Mask
#define ONEWIRE_O_RIS 0x00000104 // 1-Wire Raw Interrupt Status
#define ONEWIRE_O_MIS 0x00000108 // 1-Wire Masked Interrupt Status
#define ONEWIRE_O_ICR 0x0000010C // 1-Wire Interrupt Clear
#define ONEWIRE_O_DMA 0x00000120 // 1-Wire uDMA Control
#define ONEWIRE_O_PP 0x00000FC0 // 1-Wire Peripheral Properties
//*****************************************************************************
//
// The following are defines for the bit fields in the ONEWIRE_O_CS register.
//
//*****************************************************************************
#define ONEWIRE_CS_USEALT 0x80000000 // Two Wire Enable
#define ONEWIRE_CS_ALTP 0x40000000 // Alternate Polarity Enable
#define ONEWIRE_CS_BSIZE_M 0x00070000 // Last Byte Size
#define ONEWIRE_CS_BSIZE_8 0x00000000 // 8 bits (1 byte)
#define ONEWIRE_CS_BSIZE_1 0x00010000 // 1 bit
#define ONEWIRE_CS_BSIZE_2 0x00020000 // 2 bits
#define ONEWIRE_CS_BSIZE_3 0x00030000 // 3 bits
#define ONEWIRE_CS_BSIZE_4 0x00040000 // 4 bits
#define ONEWIRE_CS_BSIZE_5 0x00050000 // 5 bits
#define ONEWIRE_CS_BSIZE_6 0x00060000 // 6 bits
#define ONEWIRE_CS_BSIZE_7 0x00070000 // 7 bits
#define ONEWIRE_CS_STUCK 0x00000400 // STUCK Status
#define ONEWIRE_CS_NOATR 0x00000200 // Answer-to-Reset Status
#define ONEWIRE_CS_BUSY 0x00000100 // Busy Status
#define ONEWIRE_CS_SKATR 0x00000080 // Skip Answer-to-Reset Enable
#define ONEWIRE_CS_LSAM 0x00000040 // Late Sample Enable
#define ONEWIRE_CS_ODRV 0x00000020 // Overdrive Enable
#define ONEWIRE_CS_SZ_M 0x00000018 // Data Operation Size
#define ONEWIRE_CS_OP_M 0x00000006 // Operation Request
#define ONEWIRE_CS_OP_NONE 0x00000000 // No operation
#define ONEWIRE_CS_OP_RD 0x00000002 // Read
#define ONEWIRE_CS_OP_WR 0x00000004 // Write
#define ONEWIRE_CS_OP_WRRD 0x00000006 // Write/Read
#define ONEWIRE_CS_RST 0x00000001 // Reset Request
#define ONEWIRE_CS_SZ_S 3
//*****************************************************************************
//
// The following are defines for the bit fields in the ONEWIRE_O_TIM register.
//
//*****************************************************************************
#define ONEWIRE_TIM_W1TIM_M 0xF0000000 // Value '1' Timing
#define ONEWIRE_TIM_W0TIM_M 0x0F800000 // Value '0' Timing
#define ONEWIRE_TIM_W0REST_M 0x00780000 // Rest Time
#define ONEWIRE_TIM_W1SAM_M 0x00078000 // Sample Time
#define ONEWIRE_TIM_ATRSAM_M 0x00007800 // Answer-to-Reset Sample
#define ONEWIRE_TIM_ATRTIM_M 0x000007C0 // Answer-to-Reset/Rest Period
#define ONEWIRE_TIM_RSTTIM_M 0x0000003F // Reset Low Time
#define ONEWIRE_TIM_W1TIM_S 28
#define ONEWIRE_TIM_W0TIM_S 23
#define ONEWIRE_TIM_W0REST_S 19
#define ONEWIRE_TIM_W1SAM_S 15
#define ONEWIRE_TIM_ATRSAM_S 11
#define ONEWIRE_TIM_ATRTIM_S 6
#define ONEWIRE_TIM_RSTTIM_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the ONEWIRE_O_DATW register.
//
//*****************************************************************************
#define ONEWIRE_DATW_B3_M 0xFF000000 // Upper Data Byte
#define ONEWIRE_DATW_B2_M 0x00FF0000 // Upper Middle Data Byte
#define ONEWIRE_DATW_B1_M 0x0000FF00 // Lower Middle Data Byte
#define ONEWIRE_DATW_B0_M 0x000000FF // Lowest Data Byte
#define ONEWIRE_DATW_B3_S 24
#define ONEWIRE_DATW_B2_S 16
#define ONEWIRE_DATW_B1_S 8
#define ONEWIRE_DATW_B0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the ONEWIRE_O_DATR register.
//
//*****************************************************************************
#define ONEWIRE_DATR_B3_M 0xFF000000 // Upper Data Byte
#define ONEWIRE_DATR_B2_M 0x00FF0000 // Upper Middle Data Byte
#define ONEWIRE_DATR_B1_M 0x0000FF00 // Lower Middle Data Byte
#define ONEWIRE_DATR_B0_M 0x000000FF // Lowest Data Byte
#define ONEWIRE_DATR_B3_S 24
#define ONEWIRE_DATR_B2_S 16
#define ONEWIRE_DATR_B1_S 8
#define ONEWIRE_DATR_B0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the ONEWIRE_O_IM register.
//
//*****************************************************************************
#define ONEWIRE_IM_DMA 0x00000010 // DMA Done Interrupt Mask
#define ONEWIRE_IM_STUCK 0x00000008 // Stuck Status Interrupt Mask
#define ONEWIRE_IM_NOATR 0x00000004 // No Answer-to-Reset Interrupt
// Mask
#define ONEWIRE_IM_OPC 0x00000002 // Operation Complete Interrupt
// Mask
#define ONEWIRE_IM_RST 0x00000001 // Reset Interrupt Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the ONEWIRE_O_RIS register.
//
//*****************************************************************************
#define ONEWIRE_RIS_DMA 0x00000010 // DMA Done Raw Interrupt Status
#define ONEWIRE_RIS_STUCK 0x00000008 // Stuck Status Raw Interrupt
// Status
#define ONEWIRE_RIS_NOATR 0x00000004 // No Answer-to-Reset Raw Interrupt
// Status
#define ONEWIRE_RIS_OPC 0x00000002 // Operation Complete Raw Interrupt
// Status
#define ONEWIRE_RIS_RST 0x00000001 // Reset Raw Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the ONEWIRE_O_MIS register.
//
//*****************************************************************************
#define ONEWIRE_MIS_DMA 0x00000010 // DMA Done Masked Interrupt Status
#define ONEWIRE_MIS_STUCK 0x00000008 // Stuck Status Masked Interrupt
// Status
#define ONEWIRE_MIS_NOATR 0x00000004 // No Answer-to-Reset Masked
// Interrupt Status
#define ONEWIRE_MIS_OPC 0x00000002 // Operation Complete Masked
// Interrupt Status
#define ONEWIRE_MIS_RST 0x00000001 // Reset Interrupt Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the ONEWIRE_O_ICR register.
//
//*****************************************************************************
#define ONEWIRE_ICR_DMA 0x00000010 // DMA Done Interrupt Clear
#define ONEWIRE_ICR_STUCK 0x00000008 // Stuck Status Interrupt Clear
#define ONEWIRE_ICR_NOATR 0x00000004 // No Answer-to-Reset Interrupt
// Clear
#define ONEWIRE_ICR_OPC 0x00000002 // Operation Complete Interrupt
// Clear
#define ONEWIRE_ICR_RST 0x00000001 // Reset Interrupt Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the ONEWIRE_O_DMA register.
//
//*****************************************************************************
#define ONEWIRE_DMA_SG 0x00000008 // Scatter-Gather Enable
#define ONEWIRE_DMA_DMAOP_M 0x00000006 // uDMA Operation
#define ONEWIRE_DMA_DMAOP_DIS 0x00000000 // uDMA disabled
#define ONEWIRE_DMA_DMAOP_RDSNG 0x00000002 // uDMA single read: 1-Wire
// requests uDMA to read
// ONEWIREDATR register after each
// read transaction
#define ONEWIRE_DMA_DMAOP_WRMUL 0x00000004 // uDMA multiple write: 1-Wire
// requests uDMA to load whenever
// the ONEWIREDATW register is
// empty
#define ONEWIRE_DMA_DMAOP_RDMUL 0x00000006 // uDMA multiple read: An initial
// read occurs and subsequent reads
// start after uDMA has read the
// ONEWIREDATR register
#define ONEWIRE_DMA_RST 0x00000001 // uDMA Reset
//*****************************************************************************
//
// The following are defines for the bit fields in the ONEWIRE_O_PP register.
//
//*****************************************************************************
#define ONEWIRE_PP_DMAP 0x00000010 // uDMA Present
#define ONEWIRE_PP_CNT_M 0x00000003 // 1-Wire Bus Count
#define ONEWIRE_PP_CNT_S 0
#endif // __HW_ONEWIRE_H__

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//*****************************************************************************
//
// hw_qei.h - Macros used when accessing the QEI hardware.
//
// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_QEI_H__
#define __HW_QEI_H__
//*****************************************************************************
//
// The following are defines for the QEI register offsets.
//
//*****************************************************************************
#define QEI_O_CTL 0x00000000 // QEI Control
#define QEI_O_STAT 0x00000004 // QEI Status
#define QEI_O_POS 0x00000008 // QEI Position
#define QEI_O_MAXPOS 0x0000000C // QEI Maximum Position
#define QEI_O_LOAD 0x00000010 // QEI Timer Load
#define QEI_O_TIME 0x00000014 // QEI Timer
#define QEI_O_COUNT 0x00000018 // QEI Velocity Counter
#define QEI_O_SPEED 0x0000001C // QEI Velocity
#define QEI_O_INTEN 0x00000020 // QEI Interrupt Enable
#define QEI_O_RIS 0x00000024 // QEI Raw Interrupt Status
#define QEI_O_ISC 0x00000028 // QEI Interrupt Status and Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_O_CTL register.
//
//*****************************************************************************
#define QEI_CTL_FILTCNT_M 0x000F0000 // Input Filter Prescale Count
#define QEI_CTL_FILTEN 0x00002000 // Enable Input Filter
#define QEI_CTL_STALLEN 0x00001000 // Stall QEI
#define QEI_CTL_INVI 0x00000800 // Invert Index Pulse
#define QEI_CTL_INVB 0x00000400 // Invert PhB
#define QEI_CTL_INVA 0x00000200 // Invert PhA
#define QEI_CTL_VELDIV_M 0x000001C0 // Predivide Velocity
#define QEI_CTL_VELDIV_1 0x00000000 // QEI clock /1
#define QEI_CTL_VELDIV_2 0x00000040 // QEI clock /2
#define QEI_CTL_VELDIV_4 0x00000080 // QEI clock /4
#define QEI_CTL_VELDIV_8 0x000000C0 // QEI clock /8
#define QEI_CTL_VELDIV_16 0x00000100 // QEI clock /16
#define QEI_CTL_VELDIV_32 0x00000140 // QEI clock /32
#define QEI_CTL_VELDIV_64 0x00000180 // QEI clock /64
#define QEI_CTL_VELDIV_128 0x000001C0 // QEI clock /128
#define QEI_CTL_VELEN 0x00000020 // Capture Velocity
#define QEI_CTL_RESMODE 0x00000010 // Reset Mode
#define QEI_CTL_CAPMODE 0x00000008 // Capture Mode
#define QEI_CTL_SIGMODE 0x00000004 // Signal Mode
#define QEI_CTL_SWAP 0x00000002 // Swap Signals
#define QEI_CTL_ENABLE 0x00000001 // Enable QEI
#define QEI_CTL_FILTCNT_S 16
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_O_STAT register.
//
//*****************************************************************************
#define QEI_STAT_DIRECTION 0x00000002 // Direction of Rotation
#define QEI_STAT_ERROR 0x00000001 // Error Detected
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_O_POS register.
//
//*****************************************************************************
#define QEI_POS_M 0xFFFFFFFF // Current Position Integrator
// Value
#define QEI_POS_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_O_MAXPOS register.
//
//*****************************************************************************
#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum Position Integrator
// Value
#define QEI_MAXPOS_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_O_LOAD register.
//
//*****************************************************************************
#define QEI_LOAD_M 0xFFFFFFFF // Velocity Timer Load Value
#define QEI_LOAD_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_O_TIME register.
//
//*****************************************************************************
#define QEI_TIME_M 0xFFFFFFFF // Velocity Timer Current Value
#define QEI_TIME_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_O_COUNT register.
//
//*****************************************************************************
#define QEI_COUNT_M 0xFFFFFFFF // Velocity Pulse Count
#define QEI_COUNT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_O_SPEED register.
//
//*****************************************************************************
#define QEI_SPEED_M 0xFFFFFFFF // Velocity
#define QEI_SPEED_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_O_INTEN register.
//
//*****************************************************************************
#define QEI_INTEN_ERROR 0x00000008 // Phase Error Interrupt Enable
#define QEI_INTEN_DIR 0x00000004 // Direction Change Interrupt
// Enable
#define QEI_INTEN_TIMER 0x00000002 // Timer Expires Interrupt Enable
#define QEI_INTEN_INDEX 0x00000001 // Index Pulse Detected Interrupt
// Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_O_RIS register.
//
//*****************************************************************************
#define QEI_RIS_ERROR 0x00000008 // Phase Error Detected
#define QEI_RIS_DIR 0x00000004 // Direction Change Detected
#define QEI_RIS_TIMER 0x00000002 // Velocity Timer Expired
#define QEI_RIS_INDEX 0x00000001 // Index Pulse Asserted
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_O_ISC register.
//
//*****************************************************************************
#define QEI_ISC_ERROR 0x00000008 // Phase Error Interrupt
#define QEI_ISC_DIR 0x00000004 // Direction Change Interrupt
#define QEI_ISC_TIMER 0x00000002 // Velocity Timer Expired Interrupt
#define QEI_ISC_INDEX 0x00000001 // Index Pulse Interrupt
#endif // __HW_QEI_H__

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//*****************************************************************************
//
// hw_shamd5.h - Macros used when accessing the SHA/MD5 hardware.
//
// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_SHAMD5_H__
#define __HW_SHAMD5_H__
//*****************************************************************************
//
// The following are defines for the SHA/MD5 register offsets.
//
//*****************************************************************************
#define SHAMD5_O_ODIGEST_A 0x00000000 // SHA Outer Digest A
#define SHAMD5_O_ODIGEST_B 0x00000004 // SHA Outer Digest B
#define SHAMD5_O_ODIGEST_C 0x00000008 // SHA Outer Digest C
#define SHAMD5_O_ODIGEST_D 0x0000000C // SHA Outer Digest D
#define SHAMD5_O_ODIGEST_E 0x00000010 // SHA Outer Digest E
#define SHAMD5_O_ODIGEST_F 0x00000014 // SHA Outer Digest F
#define SHAMD5_O_ODIGEST_G 0x00000018 // SHA Outer Digest G
#define SHAMD5_O_ODIGEST_H 0x0000001C // SHA Outer Digest H
#define SHAMD5_O_IDIGEST_A 0x00000020 // SHA Inner Digest A
#define SHAMD5_O_IDIGEST_B 0x00000024 // SHA Inner Digest B
#define SHAMD5_O_IDIGEST_C 0x00000028 // SHA Inner Digest C
#define SHAMD5_O_IDIGEST_D 0x0000002C // SHA Inner Digest D
#define SHAMD5_O_IDIGEST_E 0x00000030 // SHA Inner Digest E
#define SHAMD5_O_IDIGEST_F 0x00000034 // SHA Inner Digest F
#define SHAMD5_O_IDIGEST_G 0x00000038 // SHA Inner Digest G
#define SHAMD5_O_IDIGEST_H 0x0000003C // SHA Inner Digest H
#define SHAMD5_O_DIGEST_COUNT 0x00000040 // SHA Digest Count
#define SHAMD5_O_MODE 0x00000044 // SHA Mode
#define SHAMD5_O_LENGTH 0x00000048 // SHA Length
#define SHAMD5_O_DATA_0_IN 0x00000080 // SHA Data 0 Input
#define SHAMD5_O_DATA_1_IN 0x00000084 // SHA Data 1 Input
#define SHAMD5_O_DATA_2_IN 0x00000088 // SHA Data 2 Input
#define SHAMD5_O_DATA_3_IN 0x0000008C // SHA Data 3 Input
#define SHAMD5_O_DATA_4_IN 0x00000090 // SHA Data 4 Input
#define SHAMD5_O_DATA_5_IN 0x00000094 // SHA Data 5 Input
#define SHAMD5_O_DATA_6_IN 0x00000098 // SHA Data 6 Input
#define SHAMD5_O_DATA_7_IN 0x0000009C // SHA Data 7 Input
#define SHAMD5_O_DATA_8_IN 0x000000A0 // SHA Data 8 Input
#define SHAMD5_O_DATA_9_IN 0x000000A4 // SHA Data 9 Input
#define SHAMD5_O_DATA_10_IN 0x000000A8 // SHA Data 10 Input
#define SHAMD5_O_DATA_11_IN 0x000000AC // SHA Data 11 Input
#define SHAMD5_O_DATA_12_IN 0x000000B0 // SHA Data 12 Input
#define SHAMD5_O_DATA_13_IN 0x000000B4 // SHA Data 13 Input
#define SHAMD5_O_DATA_14_IN 0x000000B8 // SHA Data 14 Input
#define SHAMD5_O_DATA_15_IN 0x000000BC // SHA Data 15 Input
#define SHAMD5_O_REVISION 0x00000100 // SHA Revision
#define SHAMD5_O_SYSCONFIG 0x00000110 // SHA System Configuration
#define SHAMD5_O_SYSSTATUS 0x00000114 // SHA System Status
#define SHAMD5_O_IRQSTATUS 0x00000118 // SHA Interrupt Status
#define SHAMD5_O_IRQENABLE 0x0000011C // SHA Interrupt Enable
#define SHAMD5_O_DMAIM 0xFFFFC010 // SHA DMA Interrupt Mask
#define SHAMD5_O_DMARIS 0xFFFFC014 // SHA DMA Raw Interrupt Status
#define SHAMD5_O_DMAMIS 0xFFFFC018 // SHA DMA Masked Interrupt Status
#define SHAMD5_O_DMAIC 0xFFFFC01C // SHA DMA Interrupt Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_A
// register.
//
//*****************************************************************************
#define SHAMD5_ODIGEST_A_DATA_M 0xFFFFFFFF // Digest/Key Data
#define SHAMD5_ODIGEST_A_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_B
// register.
//
//*****************************************************************************
#define SHAMD5_ODIGEST_B_DATA_M 0xFFFFFFFF // Digest/Key Data
#define SHAMD5_ODIGEST_B_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_C
// register.
//
//*****************************************************************************
#define SHAMD5_ODIGEST_C_DATA_M 0xFFFFFFFF // Digest/Key Data
#define SHAMD5_ODIGEST_C_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_D
// register.
//
//*****************************************************************************
#define SHAMD5_ODIGEST_D_DATA_M 0xFFFFFFFF // Digest/Key Data
#define SHAMD5_ODIGEST_D_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_E
// register.
//
//*****************************************************************************
#define SHAMD5_ODIGEST_E_DATA_M 0xFFFFFFFF // Digest/Key Data
#define SHAMD5_ODIGEST_E_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_F
// register.
//
//*****************************************************************************
#define SHAMD5_ODIGEST_F_DATA_M 0xFFFFFFFF // Digest/Key Data
#define SHAMD5_ODIGEST_F_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_G
// register.
//
//*****************************************************************************
#define SHAMD5_ODIGEST_G_DATA_M 0xFFFFFFFF // Digest/Key Data
#define SHAMD5_ODIGEST_G_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_H
// register.
//
//*****************************************************************************
#define SHAMD5_ODIGEST_H_DATA_M 0xFFFFFFFF // Digest/Key Data
#define SHAMD5_ODIGEST_H_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_A
// register.
//
//*****************************************************************************
#define SHAMD5_IDIGEST_A_DATA_M 0xFFFFFFFF // Digest/Key Data
#define SHAMD5_IDIGEST_A_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_B
// register.
//
//*****************************************************************************
#define SHAMD5_IDIGEST_B_DATA_M 0xFFFFFFFF // Digest/Key Data
#define SHAMD5_IDIGEST_B_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_C
// register.
//
//*****************************************************************************
#define SHAMD5_IDIGEST_C_DATA_M 0xFFFFFFFF // Digest/Key Data
#define SHAMD5_IDIGEST_C_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_D
// register.
//
//*****************************************************************************
#define SHAMD5_IDIGEST_D_DATA_M 0xFFFFFFFF // Digest/Key Data
#define SHAMD5_IDIGEST_D_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_E
// register.
//
//*****************************************************************************
#define SHAMD5_IDIGEST_E_DATA_M 0xFFFFFFFF // Digest/Key Data
#define SHAMD5_IDIGEST_E_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_F
// register.
//
//*****************************************************************************
#define SHAMD5_IDIGEST_F_DATA_M 0xFFFFFFFF // Digest/Key Data
#define SHAMD5_IDIGEST_F_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_G
// register.
//
//*****************************************************************************
#define SHAMD5_IDIGEST_G_DATA_M 0xFFFFFFFF // Digest/Key Data
#define SHAMD5_IDIGEST_G_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_H
// register.
//
//*****************************************************************************
#define SHAMD5_IDIGEST_H_DATA_M 0xFFFFFFFF // Digest/Key Data
#define SHAMD5_IDIGEST_H_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SHAMD5_O_DIGEST_COUNT
// register.
//
//*****************************************************************************
#define SHAMD5_DIGEST_COUNT_M 0xFFFFFFFF // Digest Count
#define SHAMD5_DIGEST_COUNT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SHAMD5_O_MODE register.
//
//*****************************************************************************
#define SHAMD5_MODE_HMAC_OUTER_HASH \
0x00000080 // HMAC Outer Hash Processing
// Enable
#define SHAMD5_MODE_HMAC_KEY_PROC \
0x00000020 // HMAC Key Processing Enable
#define SHAMD5_MODE_CLOSE_HASH 0x00000010 // Performs the padding, the
// Hash/HMAC will be 'closed' at
// the end of the block, as per
// MD5/SHA-1/SHA-2 specification
#define SHAMD5_MODE_ALGO_CONSTANT \
0x00000008 // The initial digest register will
// be overwritten with the
// algorithm constants for the
// selected algorithm when hashing
// and the initial digest count
// register will be reset to 0
#define SHAMD5_MODE_ALGO_M 0x00000007 // Hash Algorithm
#define SHAMD5_MODE_ALGO_MD5 0x00000000 // MD5
#define SHAMD5_MODE_ALGO_SHA1 0x00000002 // SHA-1
#define SHAMD5_MODE_ALGO_SHA224 0x00000004 // SHA-224
#define SHAMD5_MODE_ALGO_SHA256 0x00000006 // SHA-256
//*****************************************************************************
//
// The following are defines for the bit fields in the SHAMD5_O_LENGTH
// register.
//
//*****************************************************************************
#define SHAMD5_LENGTH_M 0xFFFFFFFF // Block Length/Remaining Byte
// Count
#define SHAMD5_LENGTH_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SHAMD5_O_DATA_0_IN
// register.
//
//*****************************************************************************
#define SHAMD5_DATA_0_IN_DATA_M 0xFFFFFFFF // Digest/Key Data
#define SHAMD5_DATA_0_IN_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SHAMD5_O_DATA_1_IN
// register.
//
//*****************************************************************************
#define SHAMD5_DATA_1_IN_DATA_M 0xFFFFFFFF // Digest/Key Data
#define SHAMD5_DATA_1_IN_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SHAMD5_O_DATA_2_IN
// register.
//
//*****************************************************************************
#define SHAMD5_DATA_2_IN_DATA_M 0xFFFFFFFF // Digest/Key Data
#define SHAMD5_DATA_2_IN_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SHAMD5_O_DATA_3_IN
// register.
//
//*****************************************************************************
#define SHAMD5_DATA_3_IN_DATA_M 0xFFFFFFFF // Digest/Key Data
#define SHAMD5_DATA_3_IN_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SHAMD5_O_DATA_4_IN
// register.
//
//*****************************************************************************
#define SHAMD5_DATA_4_IN_DATA_M 0xFFFFFFFF // Digest/Key Data
#define SHAMD5_DATA_4_IN_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SHAMD5_O_DATA_5_IN
// register.
//
//*****************************************************************************
#define SHAMD5_DATA_5_IN_DATA_M 0xFFFFFFFF // Digest/Key Data
#define SHAMD5_DATA_5_IN_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SHAMD5_O_DATA_6_IN
// register.
//
//*****************************************************************************
#define SHAMD5_DATA_6_IN_DATA_M 0xFFFFFFFF // Digest/Key Data
#define SHAMD5_DATA_6_IN_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SHAMD5_O_DATA_7_IN
// register.
//
//*****************************************************************************
#define SHAMD5_DATA_7_IN_DATA_M 0xFFFFFFFF // Digest/Key Data
#define SHAMD5_DATA_7_IN_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SHAMD5_O_DATA_8_IN
// register.
//
//*****************************************************************************
#define SHAMD5_DATA_8_IN_DATA_M 0xFFFFFFFF // Digest/Key Data
#define SHAMD5_DATA_8_IN_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SHAMD5_O_DATA_9_IN
// register.
//
//*****************************************************************************
#define SHAMD5_DATA_9_IN_DATA_M 0xFFFFFFFF // Digest/Key Data
#define SHAMD5_DATA_9_IN_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SHAMD5_O_DATA_10_IN
// register.
//
//*****************************************************************************
#define SHAMD5_DATA_10_IN_DATA_M \
0xFFFFFFFF // Digest/Key Data
#define SHAMD5_DATA_10_IN_DATA_S \
0
//*****************************************************************************
//
// The following are defines for the bit fields in the SHAMD5_O_DATA_11_IN
// register.
//
//*****************************************************************************
#define SHAMD5_DATA_11_IN_DATA_M \
0xFFFFFFFF // Digest/Key Data
#define SHAMD5_DATA_11_IN_DATA_S \
0
//*****************************************************************************
//
// The following are defines for the bit fields in the SHAMD5_O_DATA_12_IN
// register.
//
//*****************************************************************************
#define SHAMD5_DATA_12_IN_DATA_M \
0xFFFFFFFF // Digest/Key Data
#define SHAMD5_DATA_12_IN_DATA_S \
0
//*****************************************************************************
//
// The following are defines for the bit fields in the SHAMD5_O_DATA_13_IN
// register.
//
//*****************************************************************************
#define SHAMD5_DATA_13_IN_DATA_M \
0xFFFFFFFF // Digest/Key Data
#define SHAMD5_DATA_13_IN_DATA_S \
0
//*****************************************************************************
//
// The following are defines for the bit fields in the SHAMD5_O_DATA_14_IN
// register.
//
//*****************************************************************************
#define SHAMD5_DATA_14_IN_DATA_M \
0xFFFFFFFF // Digest/Key Data
#define SHAMD5_DATA_14_IN_DATA_S \
0
//*****************************************************************************
//
// The following are defines for the bit fields in the SHAMD5_O_DATA_15_IN
// register.
//
//*****************************************************************************
#define SHAMD5_DATA_15_IN_DATA_M \
0xFFFFFFFF // Digest/Key Data
#define SHAMD5_DATA_15_IN_DATA_S \
0
//*****************************************************************************
//
// The following are defines for the bit fields in the SHAMD5_O_REVISION
// register.
//
//*****************************************************************************
#define SHAMD5_REVISION_M 0xFFFFFFFF // Revision Number
#define SHAMD5_REVISION_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SHAMD5_O_SYSCONFIG
// register.
//
//*****************************************************************************
#define SHAMD5_SYSCONFIG_SADVANCED \
0x00000080 // Advanced Mode Enable
#define SHAMD5_SYSCONFIG_SIDLE_M \
0x00000030 // Sidle mode
#define SHAMD5_SYSCONFIG_SIDLE_FORCE \
0x00000000 // Force-idle mode
#define SHAMD5_SYSCONFIG_DMA_EN 0x00000008 // uDMA Request Enable
#define SHAMD5_SYSCONFIG_IT_EN 0x00000004 // Interrupt Enable
#define SHAMD5_SYSCONFIG_SOFTRESET \
0x00000002 // Soft reset
//*****************************************************************************
//
// The following are defines for the bit fields in the SHAMD5_O_SYSSTATUS
// register.
//
//*****************************************************************************
#define SHAMD5_SYSSTATUS_RESETDONE \
0x00000001 // Reset done status
//*****************************************************************************
//
// The following are defines for the bit fields in the SHAMD5_O_IRQSTATUS
// register.
//
//*****************************************************************************
#define SHAMD5_IRQSTATUS_CONTEXT_READY \
0x00000008 // Context Ready Status
#define SHAMD5_IRQSTATUS_INPUT_READY \
0x00000002 // Input Ready Status
#define SHAMD5_IRQSTATUS_OUTPUT_READY \
0x00000001 // Output Ready Status
//*****************************************************************************
//
// The following are defines for the bit fields in the SHAMD5_O_IRQENABLE
// register.
//
//*****************************************************************************
#define SHAMD5_IRQENABLE_CONTEXT_READY \
0x00000008 // Mask for context ready interrupt
#define SHAMD5_IRQENABLE_INPUT_READY \
0x00000002 // Mask for input ready interrupt
#define SHAMD5_IRQENABLE_OUTPUT_READY \
0x00000001 // Mask for output ready interrupt
//*****************************************************************************
//
// The following are defines for the bit fields in the SHAMD5_O_DMAIM register.
//
//*****************************************************************************
#define SHAMD5_DMAIM_COUT 0x00000004 // Context Out DMA Done Interrupt
// Mask
#define SHAMD5_DMAIM_DIN 0x00000002 // Data In DMA Done Interrupt Mask
#define SHAMD5_DMAIM_CIN 0x00000001 // Context In DMA Done Interrupt
// Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the SHAMD5_O_DMARIS
// register.
//
//*****************************************************************************
#define SHAMD5_DMARIS_COUT 0x00000004 // Context Out DMA Done Raw
// Interrupt Status
#define SHAMD5_DMARIS_DIN 0x00000002 // Data In DMA Done Raw Interrupt
// Status
#define SHAMD5_DMARIS_CIN 0x00000001 // Context In DMA Done Raw
// Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the SHAMD5_O_DMAMIS
// register.
//
//*****************************************************************************
#define SHAMD5_DMAMIS_COUT 0x00000004 // Context Out DMA Done Masked
// Interrupt Status
#define SHAMD5_DMAMIS_DIN 0x00000002 // Data In DMA Done Masked
// Interrupt Status
#define SHAMD5_DMAMIS_CIN 0x00000001 // Context In DMA Done Raw
// Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the SHAMD5_O_DMAIC register.
//
//*****************************************************************************
#define SHAMD5_DMAIC_COUT 0x00000004 // Context Out DMA Done Masked
// Interrupt Status
#define SHAMD5_DMAIC_DIN 0x00000002 // Data In DMA Done Interrupt Clear
#define SHAMD5_DMAIC_CIN 0x00000001 // Context In DMA Done Raw
// Interrupt Status
#endif // __HW_SHAMD5_H__

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bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/inc/hw_ssi.h Normal file
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@ -0,0 +1,237 @@
//*****************************************************************************
//
// hw_ssi.h - Macros used when accessing the SSI hardware.
//
// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_SSI_H__
#define __HW_SSI_H__
//*****************************************************************************
//
// The following are defines for the SSI register offsets.
//
//*****************************************************************************
#define SSI_O_CR0 0x00000000 // SSI Control 0
#define SSI_O_CR1 0x00000004 // SSI Control 1
#define SSI_O_DR 0x00000008 // SSI Data
#define SSI_O_SR 0x0000000C // SSI Status
#define SSI_O_CPSR 0x00000010 // SSI Clock Prescale
#define SSI_O_IM 0x00000014 // SSI Interrupt Mask
#define SSI_O_RIS 0x00000018 // SSI Raw Interrupt Status
#define SSI_O_MIS 0x0000001C // SSI Masked Interrupt Status
#define SSI_O_ICR 0x00000020 // SSI Interrupt Clear
#define SSI_O_DMACTL 0x00000024 // SSI DMA Control
#define SSI_O_PP 0x00000FC0 // SSI Peripheral Properties
#define SSI_O_CC 0x00000FC8 // SSI Clock Configuration
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_CR0 register.
//
//*****************************************************************************
#define SSI_CR0_SCR_M 0x0000FF00 // SSI Serial Clock Rate
#define SSI_CR0_SPH 0x00000080 // SSI Serial Clock Phase
#define SSI_CR0_SPO 0x00000040 // SSI Serial Clock Polarity
#define SSI_CR0_FRF_M 0x00000030 // SSI Frame Format Select
#define SSI_CR0_FRF_MOTO 0x00000000 // Freescale SPI Frame Format
#define SSI_CR0_FRF_TI 0x00000010 // Synchronous Serial Frame Format
#define SSI_CR0_FRF_NMW 0x00000020 // MICROWIRE Frame Format
#define SSI_CR0_DSS_M 0x0000000F // SSI Data Size Select
#define SSI_CR0_DSS_4 0x00000003 // 4-bit data
#define SSI_CR0_DSS_5 0x00000004 // 5-bit data
#define SSI_CR0_DSS_6 0x00000005 // 6-bit data
#define SSI_CR0_DSS_7 0x00000006 // 7-bit data
#define SSI_CR0_DSS_8 0x00000007 // 8-bit data
#define SSI_CR0_DSS_9 0x00000008 // 9-bit data
#define SSI_CR0_DSS_10 0x00000009 // 10-bit data
#define SSI_CR0_DSS_11 0x0000000A // 11-bit data
#define SSI_CR0_DSS_12 0x0000000B // 12-bit data
#define SSI_CR0_DSS_13 0x0000000C // 13-bit data
#define SSI_CR0_DSS_14 0x0000000D // 14-bit data
#define SSI_CR0_DSS_15 0x0000000E // 15-bit data
#define SSI_CR0_DSS_16 0x0000000F // 16-bit data
#define SSI_CR0_SCR_S 8
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_CR1 register.
//
//*****************************************************************************
#define SSI_CR1_EOM 0x00000800 // Stop Frame (End of Message)
#define SSI_CR1_FSSHLDFRM 0x00000400 // FSS Hold Frame
#define SSI_CR1_HSCLKEN 0x00000200 // High Speed Clock Enable
#define SSI_CR1_DIR 0x00000100 // SSI Direction of Operation
#define SSI_CR1_MODE_M 0x000000C0 // SSI Mode
#define SSI_CR1_MODE_LEGACY 0x00000000 // Legacy SSI mode
#define SSI_CR1_MODE_BI 0x00000040 // Bi-SSI mode
#define SSI_CR1_MODE_QUAD 0x00000080 // Quad-SSI Mode
#define SSI_CR1_MODE_ADVANCED 0x000000C0 // Advanced SSI Mode with 8-bit
// packet size
#define SSI_CR1_EOT 0x00000010 // End of Transmission
#define SSI_CR1_MS 0x00000004 // SSI Master/Slave Select
#define SSI_CR1_SSE 0x00000002 // SSI Synchronous Serial Port
// Enable
#define SSI_CR1_LBM 0x00000001 // SSI Loopback Mode
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_DR register.
//
//*****************************************************************************
#define SSI_DR_DATA_M 0x0000FFFF // SSI Receive/Transmit Data
#define SSI_DR_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_SR register.
//
//*****************************************************************************
#define SSI_SR_BSY 0x00000010 // SSI Busy Bit
#define SSI_SR_RFF 0x00000008 // SSI Receive FIFO Full
#define SSI_SR_RNE 0x00000004 // SSI Receive FIFO Not Empty
#define SSI_SR_TNF 0x00000002 // SSI Transmit FIFO Not Full
#define SSI_SR_TFE 0x00000001 // SSI Transmit FIFO Empty
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_CPSR register.
//
//*****************************************************************************
#define SSI_CPSR_CPSDVSR_M 0x000000FF // SSI Clock Prescale Divisor
#define SSI_CPSR_CPSDVSR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_IM register.
//
//*****************************************************************************
#define SSI_IM_EOTIM 0x00000040 // End of Transmit Interrupt Mask
#define SSI_IM_DMATXIM 0x00000020 // SSI Transmit DMA Interrupt Mask
#define SSI_IM_DMARXIM 0x00000010 // SSI Receive DMA Interrupt Mask
#define SSI_IM_TXIM 0x00000008 // SSI Transmit FIFO Interrupt Mask
#define SSI_IM_RXIM 0x00000004 // SSI Receive FIFO Interrupt Mask
#define SSI_IM_RTIM 0x00000002 // SSI Receive Time-Out Interrupt
// Mask
#define SSI_IM_RORIM 0x00000001 // SSI Receive Overrun Interrupt
// Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_RIS register.
//
//*****************************************************************************
#define SSI_RIS_EOTRIS 0x00000040 // End of Transmit Raw Interrupt
// Status
#define SSI_RIS_DMATXRIS 0x00000020 // SSI Transmit DMA Raw Interrupt
// Status
#define SSI_RIS_DMARXRIS 0x00000010 // SSI Receive DMA Raw Interrupt
// Status
#define SSI_RIS_TXRIS 0x00000008 // SSI Transmit FIFO Raw Interrupt
// Status
#define SSI_RIS_RXRIS 0x00000004 // SSI Receive FIFO Raw Interrupt
// Status
#define SSI_RIS_RTRIS 0x00000002 // SSI Receive Time-Out Raw
// Interrupt Status
#define SSI_RIS_RORRIS 0x00000001 // SSI Receive Overrun Raw
// Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_MIS register.
//
//*****************************************************************************
#define SSI_MIS_EOTMIS 0x00000040 // End of Transmit Masked Interrupt
// Status
#define SSI_MIS_DMATXMIS 0x00000020 // SSI Transmit DMA Masked
// Interrupt Status
#define SSI_MIS_DMARXMIS 0x00000010 // SSI Receive DMA Masked Interrupt
// Status
#define SSI_MIS_TXMIS 0x00000008 // SSI Transmit FIFO Masked
// Interrupt Status
#define SSI_MIS_RXMIS 0x00000004 // SSI Receive FIFO Masked
// Interrupt Status
#define SSI_MIS_RTMIS 0x00000002 // SSI Receive Time-Out Masked
// Interrupt Status
#define SSI_MIS_RORMIS 0x00000001 // SSI Receive Overrun Masked
// Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_ICR register.
//
//*****************************************************************************
#define SSI_ICR_EOTIC 0x00000040 // End of Transmit Interrupt Clear
#define SSI_ICR_DMATXIC 0x00000020 // SSI Transmit DMA Interrupt Clear
#define SSI_ICR_DMARXIC 0x00000010 // SSI Receive DMA Interrupt Clear
#define SSI_ICR_RTIC 0x00000002 // SSI Receive Time-Out Interrupt
// Clear
#define SSI_ICR_RORIC 0x00000001 // SSI Receive Overrun Interrupt
// Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_DMACTL register.
//
//*****************************************************************************
#define SSI_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable
#define SSI_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_PP register.
//
//*****************************************************************************
#define SSI_PP_FSSHLDFRM 0x00000008 // FSS Hold Frame Capability
#define SSI_PP_MODE_M 0x00000006 // Mode of Operation
#define SSI_PP_MODE_LEGACY 0x00000000 // Legacy SSI mode
#define SSI_PP_MODE_ADVBI 0x00000002 // Legacy mode, Advanced SSI mode
// and Bi-SSI mode enabled
#define SSI_PP_MODE_ADVBIQUAD 0x00000004 // Legacy mode, Advanced mode,
// Bi-SSI and Quad-SSI mode enabled
#define SSI_PP_HSCLK 0x00000001 // High Speed Capability
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_CC register.
//
//*****************************************************************************
#define SSI_CC_CS_M 0x0000000F // SSI Baud Clock Source
#define SSI_CC_CS_SYSPLL 0x00000000 // System clock (based on clock
// source and divisor factor)
#define SSI_CC_CS_PIOSC 0x00000005 // PIOSC
#endif // __HW_SSI_H__

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//*****************************************************************************
//
// hw_sysexc.h - Macros used when accessing the system exception module.
//
// Copyright (c) 2011-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_SYSEXC_H__
#define __HW_SYSEXC_H__
//*****************************************************************************
//
// The following are defines for the System Exception Module register
// addresses.
//
//*****************************************************************************
#define SYSEXC_RIS 0x400F9000 // System Exception Raw Interrupt
// Status
#define SYSEXC_IM 0x400F9004 // System Exception Interrupt Mask
#define SYSEXC_MIS 0x400F9008 // System Exception Masked
// Interrupt Status
#define SYSEXC_IC 0x400F900C // System Exception Interrupt Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSEXC_RIS register.
//
//*****************************************************************************
#define SYSEXC_RIS_FPIXCRIS 0x00000020 // Floating-Point Inexact Exception
// Raw Interrupt Status
#define SYSEXC_RIS_FPOFCRIS 0x00000010 // Floating-Point Overflow
// Exception Raw Interrupt Status
#define SYSEXC_RIS_FPUFCRIS 0x00000008 // Floating-Point Underflow
// Exception Raw Interrupt Status
#define SYSEXC_RIS_FPIOCRIS 0x00000004 // Floating-Point Invalid Operation
// Raw Interrupt Status
#define SYSEXC_RIS_FPDZCRIS 0x00000002 // Floating-Point Divide By 0
// Exception Raw Interrupt Status
#define SYSEXC_RIS_FPIDCRIS 0x00000001 // Floating-Point Input Denormal
// Exception Raw Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSEXC_IM register.
//
//*****************************************************************************
#define SYSEXC_IM_FPIXCIM 0x00000020 // Floating-Point Inexact Exception
// Interrupt Mask
#define SYSEXC_IM_FPOFCIM 0x00000010 // Floating-Point Overflow
// Exception Interrupt Mask
#define SYSEXC_IM_FPUFCIM 0x00000008 // Floating-Point Underflow
// Exception Interrupt Mask
#define SYSEXC_IM_FPIOCIM 0x00000004 // Floating-Point Invalid Operation
// Interrupt Mask
#define SYSEXC_IM_FPDZCIM 0x00000002 // Floating-Point Divide By 0
// Exception Interrupt Mask
#define SYSEXC_IM_FPIDCIM 0x00000001 // Floating-Point Input Denormal
// Exception Interrupt Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSEXC_MIS register.
//
//*****************************************************************************
#define SYSEXC_MIS_FPIXCMIS 0x00000020 // Floating-Point Inexact Exception
// Masked Interrupt Status
#define SYSEXC_MIS_FPOFCMIS 0x00000010 // Floating-Point Overflow
// Exception Masked Interrupt
// Status
#define SYSEXC_MIS_FPUFCMIS 0x00000008 // Floating-Point Underflow
// Exception Masked Interrupt
// Status
#define SYSEXC_MIS_FPIOCMIS 0x00000004 // Floating-Point Invalid Operation
// Masked Interrupt Status
#define SYSEXC_MIS_FPDZCMIS 0x00000002 // Floating-Point Divide By 0
// Exception Masked Interrupt
// Status
#define SYSEXC_MIS_FPIDCMIS 0x00000001 // Floating-Point Input Denormal
// Exception Masked Interrupt
// Status
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSEXC_IC register.
//
//*****************************************************************************
#define SYSEXC_IC_FPIXCIC 0x00000020 // Floating-Point Inexact Exception
// Interrupt Clear
#define SYSEXC_IC_FPOFCIC 0x00000010 // Floating-Point Overflow
// Exception Interrupt Clear
#define SYSEXC_IC_FPUFCIC 0x00000008 // Floating-Point Underflow
// Exception Interrupt Clear
#define SYSEXC_IC_FPIOCIC 0x00000004 // Floating-Point Invalid Operation
// Interrupt Clear
#define SYSEXC_IC_FPDZCIC 0x00000002 // Floating-Point Divide By 0
// Exception Interrupt Clear
#define SYSEXC_IC_FPIDCIC 0x00000001 // Floating-Point Input Denormal
// Exception Interrupt Clear
#endif // __HW_SYSEXC_H__

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//*****************************************************************************
//
// hw_timer.h - Defines and macros used when accessing the timer.
//
// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_TIMER_H__
#define __HW_TIMER_H__
//*****************************************************************************
//
// The following are defines for the Timer register offsets.
//
//*****************************************************************************
#define TIMER_O_CFG 0x00000000 // GPTM Configuration
#define TIMER_O_TAMR 0x00000004 // GPTM Timer A Mode
#define TIMER_O_TBMR 0x00000008 // GPTM Timer B Mode
#define TIMER_O_CTL 0x0000000C // GPTM Control
#define TIMER_O_SYNC 0x00000010 // GPTM Synchronize
#define TIMER_O_IMR 0x00000018 // GPTM Interrupt Mask
#define TIMER_O_RIS 0x0000001C // GPTM Raw Interrupt Status
#define TIMER_O_MIS 0x00000020 // GPTM Masked Interrupt Status
#define TIMER_O_ICR 0x00000024 // GPTM Interrupt Clear
#define TIMER_O_TAILR 0x00000028 // GPTM Timer A Interval Load
#define TIMER_O_TBILR 0x0000002C // GPTM Timer B Interval Load
#define TIMER_O_TAMATCHR 0x00000030 // GPTM Timer A Match
#define TIMER_O_TBMATCHR 0x00000034 // GPTM Timer B Match
#define TIMER_O_TAPR 0x00000038 // GPTM Timer A Prescale
#define TIMER_O_TBPR 0x0000003C // GPTM Timer B Prescale
#define TIMER_O_TAPMR 0x00000040 // GPTM TimerA Prescale Match
#define TIMER_O_TBPMR 0x00000044 // GPTM TimerB Prescale Match
#define TIMER_O_TAR 0x00000048 // GPTM Timer A
#define TIMER_O_TBR 0x0000004C // GPTM Timer B
#define TIMER_O_TAV 0x00000050 // GPTM Timer A Value
#define TIMER_O_TBV 0x00000054 // GPTM Timer B Value
#define TIMER_O_RTCPD 0x00000058 // GPTM RTC Predivide
#define TIMER_O_TAPS 0x0000005C // GPTM Timer A Prescale Snapshot
#define TIMER_O_TBPS 0x00000060 // GPTM Timer B Prescale Snapshot
#define TIMER_O_TAPV 0x00000064 // GPTM Timer A Prescale Value
#define TIMER_O_TBPV 0x00000068 // GPTM Timer B Prescale Value
#define TIMER_O_DMAEV 0x0000006C // GPTM DMA Event
#define TIMER_O_ADCEV 0x00000070 // GPTM ADC Event
#define TIMER_O_PP 0x00000FC0 // GPTM Peripheral Properties
#define TIMER_O_CC 0x00000FC8 // GPTM Clock Configuration
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_CFG register.
//
//*****************************************************************************
#define TIMER_CFG_M 0x00000007 // GPTM Configuration
#define TIMER_CFG_32_BIT_TIMER 0x00000000 // For a 16/32-bit timer, this
// value selects the 32-bit timer
// configuration
#define TIMER_CFG_32_BIT_RTC 0x00000001 // For a 16/32-bit timer, this
// value selects the 32-bit
// real-time clock (RTC) counter
// configuration
#define TIMER_CFG_16_BIT 0x00000004 // For a 16/32-bit timer, this
// value selects the 16-bit timer
// configuration
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAMR register.
//
//*****************************************************************************
#define TIMER_TAMR_TCACT_M 0x0000E000 // Timer Compare Action Select
#define TIMER_TAMR_TCACT_NONE 0x00000000 // Disable compare operations
#define TIMER_TAMR_TCACT_TOGGLE 0x00002000 // Toggle State on Time-Out
#define TIMER_TAMR_TCACT_CLRTO 0x00004000 // Clear CCP on Time-Out
#define TIMER_TAMR_TCACT_SETTO 0x00006000 // Set CCP on Time-Out
#define TIMER_TAMR_TCACT_SETTOGTO \
0x00008000 // Set CCP immediately and toggle
// on Time-Out
#define TIMER_TAMR_TCACT_CLRTOGTO \
0x0000A000 // Clear CCP immediately and toggle
// on Time-Out
#define TIMER_TAMR_TCACT_SETCLRTO \
0x0000C000 // Set CCP immediately and clear on
// Time-Out
#define TIMER_TAMR_TCACT_CLRSETTO \
0x0000E000 // Clear CCP immediately and set on
// Time-Out
#define TIMER_TAMR_TACINTD 0x00001000 // One-shot/Periodic Interrupt
// Disable
#define TIMER_TAMR_TAPLO 0x00000800 // GPTM Timer A PWM Legacy
// Operation
#define TIMER_TAMR_TAMRSU 0x00000400 // GPTM Timer A Match Register
// Update
#define TIMER_TAMR_TAPWMIE 0x00000200 // GPTM Timer A PWM Interrupt
// Enable
#define TIMER_TAMR_TAILD 0x00000100 // GPTM Timer A Interval Load Write
#define TIMER_TAMR_TASNAPS 0x00000080 // GPTM Timer A Snap-Shot Mode
#define TIMER_TAMR_TAWOT 0x00000040 // GPTM Timer A Wait-on-Trigger
#define TIMER_TAMR_TAMIE 0x00000020 // GPTM Timer A Match Interrupt
// Enable
#define TIMER_TAMR_TACDIR 0x00000010 // GPTM Timer A Count Direction
#define TIMER_TAMR_TAAMS 0x00000008 // GPTM Timer A Alternate Mode
// Select
#define TIMER_TAMR_TACMR 0x00000004 // GPTM Timer A Capture Mode
#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM Timer A Mode
#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode
#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode
#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBMR register.
//
//*****************************************************************************
#define TIMER_TBMR_TCACT_M 0x0000E000 // Timer Compare Action Select
#define TIMER_TBMR_TCACT_NONE 0x00000000 // Disable compare operations
#define TIMER_TBMR_TCACT_TOGGLE 0x00002000 // Toggle State on Time-Out
#define TIMER_TBMR_TCACT_CLRTO 0x00004000 // Clear CCP on Time-Out
#define TIMER_TBMR_TCACT_SETTO 0x00006000 // Set CCP on Time-Out
#define TIMER_TBMR_TCACT_SETTOGTO \
0x00008000 // Set CCP immediately and toggle
// on Time-Out
#define TIMER_TBMR_TCACT_CLRTOGTO \
0x0000A000 // Clear CCP immediately and toggle
// on Time-Out
#define TIMER_TBMR_TCACT_SETCLRTO \
0x0000C000 // Set CCP immediately and clear on
// Time-Out
#define TIMER_TBMR_TCACT_CLRSETTO \
0x0000E000 // Clear CCP immediately and set on
// Time-Out
#define TIMER_TBMR_TBCINTD 0x00001000 // One-Shot/Periodic Interrupt
// Disable
#define TIMER_TBMR_TBPLO 0x00000800 // GPTM Timer B PWM Legacy
// Operation
#define TIMER_TBMR_TBMRSU 0x00000400 // GPTM Timer B Match Register
// Update
#define TIMER_TBMR_TBPWMIE 0x00000200 // GPTM Timer B PWM Interrupt
// Enable
#define TIMER_TBMR_TBILD 0x00000100 // GPTM Timer B Interval Load Write
#define TIMER_TBMR_TBSNAPS 0x00000080 // GPTM Timer B Snap-Shot Mode
#define TIMER_TBMR_TBWOT 0x00000040 // GPTM Timer B Wait-on-Trigger
#define TIMER_TBMR_TBMIE 0x00000020 // GPTM Timer B Match Interrupt
// Enable
#define TIMER_TBMR_TBCDIR 0x00000010 // GPTM Timer B Count Direction
#define TIMER_TBMR_TBAMS 0x00000008 // GPTM Timer B Alternate Mode
// Select
#define TIMER_TBMR_TBCMR 0x00000004 // GPTM Timer B Capture Mode
#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM Timer B Mode
#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode
#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode
#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_CTL register.
//
//*****************************************************************************
#define TIMER_CTL_TBPWML 0x00004000 // GPTM Timer B PWM Output Level
#define TIMER_CTL_TBOTE 0x00002000 // GPTM Timer B Output Trigger
// Enable
#define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM Timer B Event Mode
#define TIMER_CTL_TBEVENT_POS 0x00000000 // Positive edge
#define TIMER_CTL_TBEVENT_NEG 0x00000400 // Negative edge
#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // Both edges
#define TIMER_CTL_TBSTALL 0x00000200 // GPTM Timer B Stall Enable
#define TIMER_CTL_TBEN 0x00000100 // GPTM Timer B Enable
#define TIMER_CTL_TAPWML 0x00000040 // GPTM Timer A PWM Output Level
#define TIMER_CTL_TAOTE 0x00000020 // GPTM Timer A Output Trigger
// Enable
#define TIMER_CTL_RTCEN 0x00000010 // GPTM RTC Stall Enable
#define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM Timer A Event Mode
#define TIMER_CTL_TAEVENT_POS 0x00000000 // Positive edge
#define TIMER_CTL_TAEVENT_NEG 0x00000004 // Negative edge
#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // Both edges
#define TIMER_CTL_TASTALL 0x00000002 // GPTM Timer A Stall Enable
#define TIMER_CTL_TAEN 0x00000001 // GPTM Timer A Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_SYNC register.
//
//*****************************************************************************
#define TIMER_SYNC_SYNCWT5_M 0x00C00000 // Synchronize GPTM 32/64-Bit Timer
// 5
#define TIMER_SYNC_SYNCWT5_NONE 0x00000000 // GPTM 32/64-Bit Timer 5 is not
// affected
#define TIMER_SYNC_SYNCWT5_TA 0x00400000 // A timeout event for Timer A of
// GPTM 32/64-Bit Timer 5 is
// triggered
#define TIMER_SYNC_SYNCWT5_TB 0x00800000 // A timeout event for Timer B of
// GPTM 32/64-Bit Timer 5 is
// triggered
#define TIMER_SYNC_SYNCWT5_TATB 0x00C00000 // A timeout event for both Timer A
// and Timer B of GPTM 32/64-Bit
// Timer 5 is triggered
#define TIMER_SYNC_SYNCWT4_M 0x00300000 // Synchronize GPTM 32/64-Bit Timer
// 4
#define TIMER_SYNC_SYNCWT4_NONE 0x00000000 // GPTM 32/64-Bit Timer 4 is not
// affected
#define TIMER_SYNC_SYNCWT4_TA 0x00100000 // A timeout event for Timer A of
// GPTM 32/64-Bit Timer 4 is
// triggered
#define TIMER_SYNC_SYNCWT4_TB 0x00200000 // A timeout event for Timer B of
// GPTM 32/64-Bit Timer 4 is
// triggered
#define TIMER_SYNC_SYNCWT4_TATB 0x00300000 // A timeout event for both Timer A
// and Timer B of GPTM 32/64-Bit
// Timer 4 is triggered
#define TIMER_SYNC_SYNCWT3_M 0x000C0000 // Synchronize GPTM 32/64-Bit Timer
// 3
#define TIMER_SYNC_SYNCWT3_NONE 0x00000000 // GPTM 32/64-Bit Timer 3 is not
// affected
#define TIMER_SYNC_SYNCWT3_TA 0x00040000 // A timeout event for Timer A of
// GPTM 32/64-Bit Timer 3 is
// triggered
#define TIMER_SYNC_SYNCWT3_TB 0x00080000 // A timeout event for Timer B of
// GPTM 32/64-Bit Timer 3 is
// triggered
#define TIMER_SYNC_SYNCWT3_TATB 0x000C0000 // A timeout event for both Timer A
// and Timer B of GPTM 32/64-Bit
// Timer 3 is triggered
#define TIMER_SYNC_SYNCWT2_M 0x00030000 // Synchronize GPTM 32/64-Bit Timer
// 2
#define TIMER_SYNC_SYNCWT2_NONE 0x00000000 // GPTM 32/64-Bit Timer 2 is not
// affected
#define TIMER_SYNC_SYNCWT2_TA 0x00010000 // A timeout event for Timer A of
// GPTM 32/64-Bit Timer 2 is
// triggered
#define TIMER_SYNC_SYNCWT2_TB 0x00020000 // A timeout event for Timer B of
// GPTM 32/64-Bit Timer 2 is
// triggered
#define TIMER_SYNC_SYNCWT2_TATB 0x00030000 // A timeout event for both Timer A
// and Timer B of GPTM 32/64-Bit
// Timer 2 is triggered
#define TIMER_SYNC_SYNCT7_M 0x0000C000 // Synchronize GPTM Timer 7
#define TIMER_SYNC_SYNCT7_NONE 0x00000000 // GPT7 is not affected
#define TIMER_SYNC_SYNCT7_TA 0x00004000 // A timeout event for Timer A of
// GPTM7 is triggered
#define TIMER_SYNC_SYNCT7_TB 0x00008000 // A timeout event for Timer B of
// GPTM7 is triggered
#define TIMER_SYNC_SYNCT7_TATB 0x0000C000 // A timeout event for both Timer A
// and Timer B of GPTM7 is
// triggered
#define TIMER_SYNC_SYNCWT1_M 0x0000C000 // Synchronize GPTM 32/64-Bit Timer
// 1
#define TIMER_SYNC_SYNCWT1_NONE 0x00000000 // GPTM 32/64-Bit Timer 1 is not
// affected
#define TIMER_SYNC_SYNCWT1_TA 0x00004000 // A timeout event for Timer A of
// GPTM 32/64-Bit Timer 1 is
// triggered
#define TIMER_SYNC_SYNCWT1_TB 0x00008000 // A timeout event for Timer B of
// GPTM 32/64-Bit Timer 1 is
// triggered
#define TIMER_SYNC_SYNCWT1_TATB 0x0000C000 // A timeout event for both Timer A
// and Timer B of GPTM 32/64-Bit
// Timer 1 is triggered
#define TIMER_SYNC_SYNCWT0_M 0x00003000 // Synchronize GPTM 32/64-Bit Timer
// 0
#define TIMER_SYNC_SYNCWT0_NONE 0x00000000 // GPTM 32/64-Bit Timer 0 is not
// affected
#define TIMER_SYNC_SYNCWT0_TA 0x00001000 // A timeout event for Timer A of
// GPTM 32/64-Bit Timer 0 is
// triggered
#define TIMER_SYNC_SYNCWT0_TB 0x00002000 // A timeout event for Timer B of
// GPTM 32/64-Bit Timer 0 is
// triggered
#define TIMER_SYNC_SYNCWT0_TATB 0x00003000 // A timeout event for both Timer A
// and Timer B of GPTM 32/64-Bit
// Timer 0 is triggered
#define TIMER_SYNC_SYNCT6_M 0x00003000 // Synchronize GPTM Timer 6
#define TIMER_SYNC_SYNCT6_NONE 0x00000000 // GPTM6 is not affected
#define TIMER_SYNC_SYNCT6_TA 0x00001000 // A timeout event for Timer A of
// GPTM6 is triggered
#define TIMER_SYNC_SYNCT6_TB 0x00002000 // A timeout event for Timer B of
// GPTM6 is triggered
#define TIMER_SYNC_SYNCT6_TATB 0x00003000 // A timeout event for both Timer A
// and Timer B of GPTM6 is
// triggered
#define TIMER_SYNC_SYNCT5_M 0x00000C00 // Synchronize GPTM Timer 5
#define TIMER_SYNC_SYNCT5_NONE 0x00000000 // GPTM5 is not affected
#define TIMER_SYNC_SYNCT5_TA 0x00000400 // A timeout event for Timer A of
// GPTM5 is triggered
#define TIMER_SYNC_SYNCT5_TB 0x00000800 // A timeout event for Timer B of
// GPTM5 is triggered
#define TIMER_SYNC_SYNCT5_TATB 0x00000C00 // A timeout event for both Timer A
// and Timer B of GPTM5 is
// triggered
#define TIMER_SYNC_SYNCT4_M 0x00000300 // Synchronize GPTM Timer 4
#define TIMER_SYNC_SYNCT4_NONE 0x00000000 // GPTM4 is not affected
#define TIMER_SYNC_SYNCT4_TA 0x00000100 // A timeout event for Timer A of
// GPTM4 is triggered
#define TIMER_SYNC_SYNCT4_TB 0x00000200 // A timeout event for Timer B of
// GPTM4 is triggered
#define TIMER_SYNC_SYNCT4_TATB 0x00000300 // A timeout event for both Timer A
// and Timer B of GPTM4 is
// triggered
#define TIMER_SYNC_SYNCT3_M 0x000000C0 // Synchronize GPTM Timer 3
#define TIMER_SYNC_SYNCT3_NONE 0x00000000 // GPTM3 is not affected
#define TIMER_SYNC_SYNCT3_TA 0x00000040 // A timeout event for Timer A of
// GPTM3 is triggered
#define TIMER_SYNC_SYNCT3_TB 0x00000080 // A timeout event for Timer B of
// GPTM3 is triggered
#define TIMER_SYNC_SYNCT3_TATB 0x000000C0 // A timeout event for both Timer A
// and Timer B of GPTM3 is
// triggered
#define TIMER_SYNC_SYNCT2_M 0x00000030 // Synchronize GPTM Timer 2
#define TIMER_SYNC_SYNCT2_NONE 0x00000000 // GPTM2 is not affected
#define TIMER_SYNC_SYNCT2_TA 0x00000010 // A timeout event for Timer A of
// GPTM2 is triggered
#define TIMER_SYNC_SYNCT2_TB 0x00000020 // A timeout event for Timer B of
// GPTM2 is triggered
#define TIMER_SYNC_SYNCT2_TATB 0x00000030 // A timeout event for both Timer A
// and Timer B of GPTM2 is
// triggered
#define TIMER_SYNC_SYNCT1_M 0x0000000C // Synchronize GPTM Timer 1
#define TIMER_SYNC_SYNCT1_NONE 0x00000000 // GPTM1 is not affected
#define TIMER_SYNC_SYNCT1_TA 0x00000004 // A timeout event for Timer A of
// GPTM1 is triggered
#define TIMER_SYNC_SYNCT1_TB 0x00000008 // A timeout event for Timer B of
// GPTM1 is triggered
#define TIMER_SYNC_SYNCT1_TATB 0x0000000C // A timeout event for both Timer A
// and Timer B of GPTM1 is
// triggered
#define TIMER_SYNC_SYNCT0_M 0x00000003 // Synchronize GPTM Timer 0
#define TIMER_SYNC_SYNCT0_NONE 0x00000000 // GPTM0 is not affected
#define TIMER_SYNC_SYNCT0_TA 0x00000001 // A timeout event for Timer A of
// GPTM0 is triggered
#define TIMER_SYNC_SYNCT0_TB 0x00000002 // A timeout event for Timer B of
// GPTM0 is triggered
#define TIMER_SYNC_SYNCT0_TATB 0x00000003 // A timeout event for both Timer A
// and Timer B of GPTM0 is
// triggered
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_IMR register.
//
//*****************************************************************************
#define TIMER_IMR_WUEIM 0x00010000 // 32/64-Bit Wide GPTM Write Update
// Error Interrupt Mask
#define TIMER_IMR_DMABIM 0x00002000 // GPTM Timer B DMA Done Interrupt
// Mask
#define TIMER_IMR_TBMIM 0x00000800 // GPTM Timer B Match Interrupt
// Mask
#define TIMER_IMR_CBEIM 0x00000400 // GPTM Timer B Capture Mode Event
// Interrupt Mask
#define TIMER_IMR_CBMIM 0x00000200 // GPTM Timer B Capture Mode Match
// Interrupt Mask
#define TIMER_IMR_TBTOIM 0x00000100 // GPTM Timer B Time-Out Interrupt
// Mask
#define TIMER_IMR_DMAAIM 0x00000020 // GPTM Timer A DMA Done Interrupt
// Mask
#define TIMER_IMR_TAMIM 0x00000010 // GPTM Timer A Match Interrupt
// Mask
#define TIMER_IMR_RTCIM 0x00000008 // GPTM RTC Interrupt Mask
#define TIMER_IMR_CAEIM 0x00000004 // GPTM Timer A Capture Mode Event
// Interrupt Mask
#define TIMER_IMR_CAMIM 0x00000002 // GPTM Timer A Capture Mode Match
// Interrupt Mask
#define TIMER_IMR_TATOIM 0x00000001 // GPTM Timer A Time-Out Interrupt
// Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_RIS register.
//
//*****************************************************************************
#define TIMER_RIS_WUERIS 0x00010000 // 32/64-Bit Wide GPTM Write Update
// Error Raw Interrupt Status
#define TIMER_RIS_DMABRIS 0x00002000 // GPTM Timer B DMA Done Raw
// Interrupt Status
#define TIMER_RIS_TBMRIS 0x00000800 // GPTM Timer B Match Raw Interrupt
#define TIMER_RIS_CBERIS 0x00000400 // GPTM Timer B Capture Mode Event
// Raw Interrupt
#define TIMER_RIS_CBMRIS 0x00000200 // GPTM Timer B Capture Mode Match
// Raw Interrupt
#define TIMER_RIS_TBTORIS 0x00000100 // GPTM Timer B Time-Out Raw
// Interrupt
#define TIMER_RIS_DMAARIS 0x00000020 // GPTM Timer A DMA Done Raw
// Interrupt Status
#define TIMER_RIS_TAMRIS 0x00000010 // GPTM Timer A Match Raw Interrupt
#define TIMER_RIS_RTCRIS 0x00000008 // GPTM RTC Raw Interrupt
#define TIMER_RIS_CAERIS 0x00000004 // GPTM Timer A Capture Mode Event
// Raw Interrupt
#define TIMER_RIS_CAMRIS 0x00000002 // GPTM Timer A Capture Mode Match
// Raw Interrupt
#define TIMER_RIS_TATORIS 0x00000001 // GPTM Timer A Time-Out Raw
// Interrupt
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_MIS register.
//
//*****************************************************************************
#define TIMER_MIS_WUEMIS 0x00010000 // 32/64-Bit Wide GPTM Write Update
// Error Masked Interrupt Status
#define TIMER_MIS_DMABMIS 0x00002000 // GPTM Timer B DMA Done Masked
// Interrupt
#define TIMER_MIS_TBMMIS 0x00000800 // GPTM Timer B Match Masked
// Interrupt
#define TIMER_MIS_CBEMIS 0x00000400 // GPTM Timer B Capture Mode Event
// Masked Interrupt
#define TIMER_MIS_CBMMIS 0x00000200 // GPTM Timer B Capture Mode Match
// Masked Interrupt
#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM Timer B Time-Out Masked
// Interrupt
#define TIMER_MIS_DMAAMIS 0x00000020 // GPTM Timer A DMA Done Masked
// Interrupt
#define TIMER_MIS_TAMMIS 0x00000010 // GPTM Timer A Match Masked
// Interrupt
#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt
#define TIMER_MIS_CAEMIS 0x00000004 // GPTM Timer A Capture Mode Event
// Masked Interrupt
#define TIMER_MIS_CAMMIS 0x00000002 // GPTM Timer A Capture Mode Match
// Masked Interrupt
#define TIMER_MIS_TATOMIS 0x00000001 // GPTM Timer A Time-Out Masked
// Interrupt
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_ICR register.
//
//*****************************************************************************
#define TIMER_ICR_WUECINT 0x00010000 // 32/64-Bit Wide GPTM Write Update
// Error Interrupt Clear
#define TIMER_ICR_DMABINT 0x00002000 // GPTM Timer B DMA Done Interrupt
// Clear
#define TIMER_ICR_TBMCINT 0x00000800 // GPTM Timer B Match Interrupt
// Clear
#define TIMER_ICR_CBECINT 0x00000400 // GPTM Timer B Capture Mode Event
// Interrupt Clear
#define TIMER_ICR_CBMCINT 0x00000200 // GPTM Timer B Capture Mode Match
// Interrupt Clear
#define TIMER_ICR_TBTOCINT 0x00000100 // GPTM Timer B Time-Out Interrupt
// Clear
#define TIMER_ICR_DMAAINT 0x00000020 // GPTM Timer A DMA Done Interrupt
// Clear
#define TIMER_ICR_TAMCINT 0x00000010 // GPTM Timer A Match Interrupt
// Clear
#define TIMER_ICR_RTCCINT 0x00000008 // GPTM RTC Interrupt Clear
#define TIMER_ICR_CAECINT 0x00000004 // GPTM Timer A Capture Mode Event
// Interrupt Clear
#define TIMER_ICR_CAMCINT 0x00000002 // GPTM Timer A Capture Mode Match
// Interrupt Clear
#define TIMER_ICR_TATOCINT 0x00000001 // GPTM Timer A Time-Out Raw
// Interrupt
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAILR register.
//
//*****************************************************************************
#define TIMER_TAILR_M 0xFFFFFFFF // GPTM Timer A Interval Load
// Register
#define TIMER_TAILR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBILR register.
//
//*****************************************************************************
#define TIMER_TBILR_M 0xFFFFFFFF // GPTM Timer B Interval Load
// Register
#define TIMER_TBILR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAMATCHR
// register.
//
//*****************************************************************************
#define TIMER_TAMATCHR_TAMR_M 0xFFFFFFFF // GPTM Timer A Match Register
#define TIMER_TAMATCHR_TAMR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBMATCHR
// register.
//
//*****************************************************************************
#define TIMER_TBMATCHR_TBMR_M 0xFFFFFFFF // GPTM Timer B Match Register
#define TIMER_TBMATCHR_TBMR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAPR register.
//
//*****************************************************************************
#define TIMER_TAPR_TAPSRH_M 0x0000FF00 // GPTM Timer A Prescale High Byte
#define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM Timer A Prescale
#define TIMER_TAPR_TAPSRH_S 8
#define TIMER_TAPR_TAPSR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBPR register.
//
//*****************************************************************************
#define TIMER_TBPR_TBPSRH_M 0x0000FF00 // GPTM Timer B Prescale High Byte
#define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM Timer B Prescale
#define TIMER_TBPR_TBPSRH_S 8
#define TIMER_TBPR_TBPSR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAPMR register.
//
//*****************************************************************************
#define TIMER_TAPMR_TAPSMRH_M 0x0000FF00 // GPTM Timer A Prescale Match High
// Byte
#define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match
#define TIMER_TAPMR_TAPSMRH_S 8
#define TIMER_TAPMR_TAPSMR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBPMR register.
//
//*****************************************************************************
#define TIMER_TBPMR_TBPSMRH_M 0x0000FF00 // GPTM Timer B Prescale Match High
// Byte
#define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match
#define TIMER_TBPMR_TBPSMRH_S 8
#define TIMER_TBPMR_TBPSMR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAR register.
//
//*****************************************************************************
#define TIMER_TAR_M 0xFFFFFFFF // GPTM Timer A Register
#define TIMER_TAR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBR register.
//
//*****************************************************************************
#define TIMER_TBR_M 0xFFFFFFFF // GPTM Timer B Register
#define TIMER_TBR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAV register.
//
//*****************************************************************************
#define TIMER_TAV_M 0xFFFFFFFF // GPTM Timer A Value
#define TIMER_TAV_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBV register.
//
//*****************************************************************************
#define TIMER_TBV_M 0xFFFFFFFF // GPTM Timer B Value
#define TIMER_TBV_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_RTCPD register.
//
//*****************************************************************************
#define TIMER_RTCPD_RTCPD_M 0x0000FFFF // RTC Predivide Counter Value
#define TIMER_RTCPD_RTCPD_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAPS register.
//
//*****************************************************************************
#define TIMER_TAPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Snapshot
#define TIMER_TAPS_PSS_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBPS register.
//
//*****************************************************************************
#define TIMER_TBPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Value
#define TIMER_TBPS_PSS_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAPV register.
//
//*****************************************************************************
#define TIMER_TAPV_PSV_M 0x0000FFFF // GPTM Timer A Prescaler Value
#define TIMER_TAPV_PSV_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBPV register.
//
//*****************************************************************************
#define TIMER_TBPV_PSV_M 0x0000FFFF // GPTM Timer B Prescaler Value
#define TIMER_TBPV_PSV_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_DMAEV register.
//
//*****************************************************************************
#define TIMER_DMAEV_TBMDMAEN 0x00000800 // GPTM B Mode Match Event DMA
// Trigger Enable
#define TIMER_DMAEV_CBEDMAEN 0x00000400 // GPTM B Capture Event DMA Trigger
// Enable
#define TIMER_DMAEV_CBMDMAEN 0x00000200 // GPTM B Capture Match Event DMA
// Trigger Enable
#define TIMER_DMAEV_TBTODMAEN 0x00000100 // GPTM B Time-Out Event DMA
// Trigger Enable
#define TIMER_DMAEV_TAMDMAEN 0x00000010 // GPTM A Mode Match Event DMA
// Trigger Enable
#define TIMER_DMAEV_RTCDMAEN 0x00000008 // GPTM A RTC Match Event DMA
// Trigger Enable
#define TIMER_DMAEV_CAEDMAEN 0x00000004 // GPTM A Capture Event DMA Trigger
// Enable
#define TIMER_DMAEV_CAMDMAEN 0x00000002 // GPTM A Capture Match Event DMA
// Trigger Enable
#define TIMER_DMAEV_TATODMAEN 0x00000001 // GPTM A Time-Out Event DMA
// Trigger Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_ADCEV register.
//
//*****************************************************************************
#define TIMER_ADCEV_TBMADCEN 0x00000800 // GPTM B Mode Match Event ADC
// Trigger Enable
#define TIMER_ADCEV_CBEADCEN 0x00000400 // GPTM B Capture Event ADC Trigger
// Enable
#define TIMER_ADCEV_CBMADCEN 0x00000200 // GPTM B Capture Match Event ADC
// Trigger Enable
#define TIMER_ADCEV_TBTOADCEN 0x00000100 // GPTM B Time-Out Event ADC
// Trigger Enable
#define TIMER_ADCEV_TAMADCEN 0x00000010 // GPTM A Mode Match Event ADC
// Trigger Enable
#define TIMER_ADCEV_RTCADCEN 0x00000008 // GPTM RTC Match Event ADC Trigger
// Enable
#define TIMER_ADCEV_CAEADCEN 0x00000004 // GPTM A Capture Event ADC Trigger
// Enable
#define TIMER_ADCEV_CAMADCEN 0x00000002 // GPTM A Capture Match Event ADC
// Trigger Enable
#define TIMER_ADCEV_TATOADCEN 0x00000001 // GPTM A Time-Out Event ADC
// Trigger Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_PP register.
//
//*****************************************************************************
#define TIMER_PP_ALTCLK 0x00000040 // Alternate Clock Source
#define TIMER_PP_SYNCCNT 0x00000020 // Synchronize Start
#define TIMER_PP_CHAIN 0x00000010 // Chain with Other Timers
#define TIMER_PP_SIZE_M 0x0000000F // Count Size
#define TIMER_PP_SIZE_16 0x00000000 // Timer A and Timer B counters are
// 16 bits each with an 8-bit
// prescale counter
#define TIMER_PP_SIZE_32 0x00000001 // Timer A and Timer B counters are
// 32 bits each with a 16-bit
// prescale counter
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_CC register.
//
//*****************************************************************************
#define TIMER_CC_ALTCLK 0x00000001 // Alternate Clock Source
#endif // __HW_TIMER_H__

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//*****************************************************************************
//
// hw_types.h - Common types and macros.
//
// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_TYPES_H__
#define __HW_TYPES_H__
//*****************************************************************************
//
// Macros for hardware access, both direct and via the bit-band region.
//
//*****************************************************************************
#define HWREG(x) \
(*((volatile uint32_t *)(x)))
#define HWREGH(x) \
(*((volatile uint16_t *)(x)))
#define HWREGB(x) \
(*((volatile uint8_t *)(x)))
#define HWREGBITW(x, b) \
HWREG(((uint32_t)(x) & 0xF0000000) | 0x02000000 | \
(((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2))
#define HWREGBITH(x, b) \
HWREGH(((uint32_t)(x) & 0xF0000000) | 0x02000000 | \
(((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2))
#define HWREGBITB(x, b) \
HWREGB(((uint32_t)(x) & 0xF0000000) | 0x02000000 | \
(((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2))
//*****************************************************************************
//
// Helper Macros for determining silicon revisions, etc.
//
// These macros will be used by Driverlib at "run-time" to create necessary
// conditional code blocks that will allow a single version of the Driverlib
// "binary" code to support multiple(all) Tiva silicon revisions.
//
// It is expected that these macros will be used inside of a standard 'C'
// conditional block of code, e.g.
//
// if(CLASS_IS_TM4C123)
// {
// do some TM4C123-class specific code here.
// }
//
// By default, these macros will be defined as run-time checks of the
// appropriate register(s) to allow creation of run-time conditional code
// blocks for a common DriverLib across the entire Tiva family.
//
// However, if code-space optimization is required, these macros can be "hard-
// coded" for a specific version of Tiva silicon. Many compilers will then
// detect the "hard-coded" conditionals, and appropriately optimize the code
// blocks, eliminating any "unreachable" code. This would result in a smaller
// Driverlib, thus producing a smaller final application size, but at the cost
// of limiting the Driverlib binary to a specific Tiva silicon revision.
//
//*****************************************************************************
#ifndef CLASS_IS_TM4C123
#define CLASS_IS_TM4C123 \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
(SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_TM4C123))
#endif
#ifndef CLASS_IS_TM4C129
#define CLASS_IS_TM4C129 \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
(SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_TM4C129))
#endif
#ifndef REVISION_IS_A0
#define REVISION_IS_A0 \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
(SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0))
#endif
#ifndef REVISION_IS_A1
#define REVISION_IS_A1 \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
(SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0))
#endif
#ifndef REVISION_IS_A2
#define REVISION_IS_A2 \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
(SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_2))
#endif
#ifndef REVISION_IS_B0
#define REVISION_IS_B0 \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
(SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_0))
#endif
#ifndef REVISION_IS_B1
#define REVISION_IS_B1 \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
(SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_1))
#endif
//*****************************************************************************
//
// For TivaWare 2.1, we removed all references to Tiva IC codenames from the
// source. To ensure that existing customer code doesn't break as a result
// of this change, make sure that the old definitions are still available at
// least for the time being.
//
//*****************************************************************************
#ifndef DEPRECATED
#define CLASS_IS_BLIZZARD CLASS_IS_TM4C123
#define CLASS_IS_SNOWFLAKE CLASS_IS_TM4C123
#endif
#endif // __HW_TYPES_H__

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//*****************************************************************************
//
// hw_uart.h - Macros and defines used when accessing the UART hardware.
//
// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_UART_H__
#define __HW_UART_H__
//*****************************************************************************
//
// The following are defines for the UART register offsets.
//
//*****************************************************************************
#define UART_O_DR 0x00000000 // UART Data
#define UART_O_RSR 0x00000004 // UART Receive Status/Error Clear
#define UART_O_ECR 0x00000004 // UART Receive Status/Error Clear
#define UART_O_FR 0x00000018 // UART Flag
#define UART_O_ILPR 0x00000020 // UART IrDA Low-Power Register
#define UART_O_IBRD 0x00000024 // UART Integer Baud-Rate Divisor
#define UART_O_FBRD 0x00000028 // UART Fractional Baud-Rate
// Divisor
#define UART_O_LCRH 0x0000002C // UART Line Control
#define UART_O_CTL 0x00000030 // UART Control
#define UART_O_IFLS 0x00000034 // UART Interrupt FIFO Level Select
#define UART_O_IM 0x00000038 // UART Interrupt Mask
#define UART_O_RIS 0x0000003C // UART Raw Interrupt Status
#define UART_O_MIS 0x00000040 // UART Masked Interrupt Status
#define UART_O_ICR 0x00000044 // UART Interrupt Clear
#define UART_O_DMACTL 0x00000048 // UART DMA Control
#define UART_O_9BITADDR 0x000000A4 // UART 9-Bit Self Address
#define UART_O_9BITAMASK 0x000000A8 // UART 9-Bit Self Address Mask
#define UART_O_PP 0x00000FC0 // UART Peripheral Properties
#define UART_O_CC 0x00000FC8 // UART Clock Configuration
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_DR register.
//
//*****************************************************************************
#define UART_DR_OE 0x00000800 // UART Overrun Error
#define UART_DR_BE 0x00000400 // UART Break Error
#define UART_DR_PE 0x00000200 // UART Parity Error
#define UART_DR_FE 0x00000100 // UART Framing Error
#define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received
#define UART_DR_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_RSR register.
//
//*****************************************************************************
#define UART_RSR_OE 0x00000008 // UART Overrun Error
#define UART_RSR_BE 0x00000004 // UART Break Error
#define UART_RSR_PE 0x00000002 // UART Parity Error
#define UART_RSR_FE 0x00000001 // UART Framing Error
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_ECR register.
//
//*****************************************************************************
#define UART_ECR_DATA_M 0x000000FF // Error Clear
#define UART_ECR_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_FR register.
//
//*****************************************************************************
#define UART_FR_RI 0x00000100 // Ring Indicator
#define UART_FR_TXFE 0x00000080 // UART Transmit FIFO Empty
#define UART_FR_RXFF 0x00000040 // UART Receive FIFO Full
#define UART_FR_TXFF 0x00000020 // UART Transmit FIFO Full
#define UART_FR_RXFE 0x00000010 // UART Receive FIFO Empty
#define UART_FR_BUSY 0x00000008 // UART Busy
#define UART_FR_DCD 0x00000004 // Data Carrier Detect
#define UART_FR_DSR 0x00000002 // Data Set Ready
#define UART_FR_CTS 0x00000001 // Clear To Send
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_ILPR register.
//
//*****************************************************************************
#define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor
#define UART_ILPR_ILPDVSR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_IBRD register.
//
//*****************************************************************************
#define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor
#define UART_IBRD_DIVINT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_FBRD register.
//
//*****************************************************************************
#define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor
#define UART_FBRD_DIVFRAC_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_LCRH register.
//
//*****************************************************************************
#define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select
#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length
#define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default)
#define UART_LCRH_WLEN_6 0x00000020 // 6 bits
#define UART_LCRH_WLEN_7 0x00000040 // 7 bits
#define UART_LCRH_WLEN_8 0x00000060 // 8 bits
#define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs
#define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select
#define UART_LCRH_EPS 0x00000004 // UART Even Parity Select
#define UART_LCRH_PEN 0x00000002 // UART Parity Enable
#define UART_LCRH_BRK 0x00000001 // UART Send Break
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_CTL register.
//
//*****************************************************************************
#define UART_CTL_CTSEN 0x00008000 // Enable Clear To Send
#define UART_CTL_RTSEN 0x00004000 // Enable Request to Send
#define UART_CTL_RTS 0x00000800 // Request to Send
#define UART_CTL_DTR 0x00000400 // Data Terminal Ready
#define UART_CTL_RXE 0x00000200 // UART Receive Enable
#define UART_CTL_TXE 0x00000100 // UART Transmit Enable
#define UART_CTL_LBE 0x00000080 // UART Loop Back Enable
#define UART_CTL_HSE 0x00000020 // High-Speed Enable
#define UART_CTL_EOT 0x00000010 // End of Transmission
#define UART_CTL_SMART 0x00000008 // ISO 7816 Smart Card Support
#define UART_CTL_SIRLP 0x00000004 // UART SIR Low-Power Mode
#define UART_CTL_SIREN 0x00000002 // UART SIR Enable
#define UART_CTL_UARTEN 0x00000001 // UART Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_IFLS register.
//
//*****************************************************************************
#define UART_IFLS_RX_M 0x00000038 // UART Receive Interrupt FIFO
// Level Select
#define UART_IFLS_RX1_8 0x00000000 // RX FIFO >= 1/8 full
#define UART_IFLS_RX2_8 0x00000008 // RX FIFO >= 1/4 full
#define UART_IFLS_RX4_8 0x00000010 // RX FIFO >= 1/2 full (default)
#define UART_IFLS_RX6_8 0x00000018 // RX FIFO >= 3/4 full
#define UART_IFLS_RX7_8 0x00000020 // RX FIFO >= 7/8 full
#define UART_IFLS_TX_M 0x00000007 // UART Transmit Interrupt FIFO
// Level Select
#define UART_IFLS_TX1_8 0x00000000 // TX FIFO <= 1/8 full
#define UART_IFLS_TX2_8 0x00000001 // TX FIFO <= 1/4 full
#define UART_IFLS_TX4_8 0x00000002 // TX FIFO <= 1/2 full (default)
#define UART_IFLS_TX6_8 0x00000003 // TX FIFO <= 3/4 full
#define UART_IFLS_TX7_8 0x00000004 // TX FIFO <= 7/8 full
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_IM register.
//
//*****************************************************************************
#define UART_IM_DMATXIM 0x00020000 // Transmit DMA Interrupt Mask
#define UART_IM_DMARXIM 0x00010000 // Receive DMA Interrupt Mask
#define UART_IM_9BITIM 0x00001000 // 9-Bit Mode Interrupt Mask
#define UART_IM_EOTIM 0x00000800 // End of Transmission Interrupt
// Mask
#define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt
// Mask
#define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask
#define UART_IM_PEIM 0x00000100 // UART Parity Error Interrupt Mask
#define UART_IM_FEIM 0x00000080 // UART Framing Error Interrupt
// Mask
#define UART_IM_RTIM 0x00000040 // UART Receive Time-Out Interrupt
// Mask
#define UART_IM_TXIM 0x00000020 // UART Transmit Interrupt Mask
#define UART_IM_RXIM 0x00000010 // UART Receive Interrupt Mask
#define UART_IM_DSRMIM 0x00000008 // UART Data Set Ready Modem
// Interrupt Mask
#define UART_IM_DCDMIM 0x00000004 // UART Data Carrier Detect Modem
// Interrupt Mask
#define UART_IM_CTSMIM 0x00000002 // UART Clear to Send Modem
// Interrupt Mask
#define UART_IM_RIMIM 0x00000001 // UART Ring Indicator Modem
// Interrupt Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_RIS register.
//
//*****************************************************************************
#define UART_RIS_DMATXRIS 0x00020000 // Transmit DMA Raw Interrupt
// Status
#define UART_RIS_DMARXRIS 0x00010000 // Receive DMA Raw Interrupt Status
#define UART_RIS_9BITRIS 0x00001000 // 9-Bit Mode Raw Interrupt Status
#define UART_RIS_EOTRIS 0x00000800 // End of Transmission Raw
// Interrupt Status
#define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt
// Status
#define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt
// Status
#define UART_RIS_PERIS 0x00000100 // UART Parity Error Raw Interrupt
// Status
#define UART_RIS_FERIS 0x00000080 // UART Framing Error Raw Interrupt
// Status
#define UART_RIS_RTRIS 0x00000040 // UART Receive Time-Out Raw
// Interrupt Status
#define UART_RIS_TXRIS 0x00000020 // UART Transmit Raw Interrupt
// Status
#define UART_RIS_RXRIS 0x00000010 // UART Receive Raw Interrupt
// Status
#define UART_RIS_DSRRIS 0x00000008 // UART Data Set Ready Modem Raw
// Interrupt Status
#define UART_RIS_DCDRIS 0x00000004 // UART Data Carrier Detect Modem
// Raw Interrupt Status
#define UART_RIS_CTSRIS 0x00000002 // UART Clear to Send Modem Raw
// Interrupt Status
#define UART_RIS_RIRIS 0x00000001 // UART Ring Indicator Modem Raw
// Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_MIS register.
//
//*****************************************************************************
#define UART_MIS_DMATXMIS 0x00020000 // Transmit DMA Masked Interrupt
// Status
#define UART_MIS_DMARXMIS 0x00010000 // Receive DMA Masked Interrupt
// Status
#define UART_MIS_9BITMIS 0x00001000 // 9-Bit Mode Masked Interrupt
// Status
#define UART_MIS_EOTMIS 0x00000800 // End of Transmission Masked
// Interrupt Status
#define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked
// Interrupt Status
#define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked
// Interrupt Status
#define UART_MIS_PEMIS 0x00000100 // UART Parity Error Masked
// Interrupt Status
#define UART_MIS_FEMIS 0x00000080 // UART Framing Error Masked
// Interrupt Status
#define UART_MIS_RTMIS 0x00000040 // UART Receive Time-Out Masked
// Interrupt Status
#define UART_MIS_TXMIS 0x00000020 // UART Transmit Masked Interrupt
// Status
#define UART_MIS_RXMIS 0x00000010 // UART Receive Masked Interrupt
// Status
#define UART_MIS_DSRMIS 0x00000008 // UART Data Set Ready Modem Masked
// Interrupt Status
#define UART_MIS_DCDMIS 0x00000004 // UART Data Carrier Detect Modem
// Masked Interrupt Status
#define UART_MIS_CTSMIS 0x00000002 // UART Clear to Send Modem Masked
// Interrupt Status
#define UART_MIS_RIMIS 0x00000001 // UART Ring Indicator Modem Masked
// Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_ICR register.
//
//*****************************************************************************
#define UART_ICR_DMATXIC 0x00020000 // Transmit DMA Interrupt Clear
#define UART_ICR_DMARXIC 0x00010000 // Receive DMA Interrupt Clear
#define UART_ICR_9BITIC 0x00001000 // 9-Bit Mode Interrupt Clear
#define UART_ICR_EOTIC 0x00000800 // End of Transmission Interrupt
// Clear
#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear
#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear
#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear
#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear
#define UART_ICR_RTIC 0x00000040 // Receive Time-Out Interrupt Clear
#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear
#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear
#define UART_ICR_DSRMIC 0x00000008 // UART Data Set Ready Modem
// Interrupt Clear
#define UART_ICR_DCDMIC 0x00000004 // UART Data Carrier Detect Modem
// Interrupt Clear
#define UART_ICR_CTSMIC 0x00000002 // UART Clear to Send Modem
// Interrupt Clear
#define UART_ICR_RIMIC 0x00000001 // UART Ring Indicator Modem
// Interrupt Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_DMACTL register.
//
//*****************************************************************************
#define UART_DMACTL_DMAERR 0x00000004 // DMA on Error
#define UART_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable
#define UART_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_9BITADDR
// register.
//
//*****************************************************************************
#define UART_9BITADDR_9BITEN 0x00008000 // Enable 9-Bit Mode
#define UART_9BITADDR_ADDR_M 0x000000FF // Self Address for 9-Bit Mode
#define UART_9BITADDR_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_9BITAMASK
// register.
//
//*****************************************************************************
#define UART_9BITAMASK_MASK_M 0x000000FF // Self Address Mask for 9-Bit Mode
#define UART_9BITAMASK_MASK_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_PP register.
//
//*****************************************************************************
#define UART_PP_MSE 0x00000008 // Modem Support Extended
#define UART_PP_MS 0x00000004 // Modem Support
#define UART_PP_NB 0x00000002 // 9-Bit Support
#define UART_PP_SC 0x00000001 // Smart Card Support
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_CC register.
//
//*****************************************************************************
#define UART_CC_CS_M 0x0000000F // UART Baud Clock Source
#define UART_CC_CS_SYSCLK 0x00000000 // System clock (based on clock
// source and divisor factor)
#define UART_CC_CS_PIOSC 0x00000005 // PIOSC
#endif // __HW_UART_H__

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//*****************************************************************************
//
// hw_udma.h - Macros for use in accessing the UDMA registers.
//
// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_UDMA_H__
#define __HW_UDMA_H__
//*****************************************************************************
//
// The following are defines for the Micro Direct Memory Access register
// addresses.
//
//*****************************************************************************
#define UDMA_STAT 0x400FF000 // DMA Status
#define UDMA_CFG 0x400FF004 // DMA Configuration
#define UDMA_CTLBASE 0x400FF008 // DMA Channel Control Base Pointer
#define UDMA_ALTBASE 0x400FF00C // DMA Alternate Channel Control
// Base Pointer
#define UDMA_WAITSTAT 0x400FF010 // DMA Channel Wait-on-Request
// Status
#define UDMA_SWREQ 0x400FF014 // DMA Channel Software Request
#define UDMA_USEBURSTSET 0x400FF018 // DMA Channel Useburst Set
#define UDMA_USEBURSTCLR 0x400FF01C // DMA Channel Useburst Clear
#define UDMA_REQMASKSET 0x400FF020 // DMA Channel Request Mask Set
#define UDMA_REQMASKCLR 0x400FF024 // DMA Channel Request Mask Clear
#define UDMA_ENASET 0x400FF028 // DMA Channel Enable Set
#define UDMA_ENACLR 0x400FF02C // DMA Channel Enable Clear
#define UDMA_ALTSET 0x400FF030 // DMA Channel Primary Alternate
// Set
#define UDMA_ALTCLR 0x400FF034 // DMA Channel Primary Alternate
// Clear
#define UDMA_PRIOSET 0x400FF038 // DMA Channel Priority Set
#define UDMA_PRIOCLR 0x400FF03C // DMA Channel Priority Clear
#define UDMA_ERRCLR 0x400FF04C // DMA Bus Error Clear
#define UDMA_CHASGN 0x400FF500 // DMA Channel Assignment
#define UDMA_CHIS 0x400FF504 // DMA Channel Interrupt Status
#define UDMA_CHMAP0 0x400FF510 // DMA Channel Map Select 0
#define UDMA_CHMAP1 0x400FF514 // DMA Channel Map Select 1
#define UDMA_CHMAP2 0x400FF518 // DMA Channel Map Select 2
#define UDMA_CHMAP3 0x400FF51C // DMA Channel Map Select 3
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_STAT register.
//
//*****************************************************************************
#define UDMA_STAT_DMACHANS_M 0x001F0000 // Available uDMA Channels Minus 1
#define UDMA_STAT_STATE_M 0x000000F0 // Control State Machine Status
#define UDMA_STAT_STATE_IDLE 0x00000000 // Idle
#define UDMA_STAT_STATE_RD_CTRL 0x00000010 // Reading channel controller data
#define UDMA_STAT_STATE_RD_SRCENDP \
0x00000020 // Reading source end pointer
#define UDMA_STAT_STATE_RD_DSTENDP \
0x00000030 // Reading destination end pointer
#define UDMA_STAT_STATE_RD_SRCDAT \
0x00000040 // Reading source data
#define UDMA_STAT_STATE_WR_DSTDAT \
0x00000050 // Writing destination data
#define UDMA_STAT_STATE_WAIT 0x00000060 // Waiting for uDMA request to
// clear
#define UDMA_STAT_STATE_WR_CTRL 0x00000070 // Writing channel controller data
#define UDMA_STAT_STATE_STALL 0x00000080 // Stalled
#define UDMA_STAT_STATE_DONE 0x00000090 // Done
#define UDMA_STAT_STATE_UNDEF 0x000000A0 // Undefined
#define UDMA_STAT_MASTEN 0x00000001 // Master Enable Status
#define UDMA_STAT_DMACHANS_S 16
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_CFG register.
//
//*****************************************************************************
#define UDMA_CFG_MASTEN 0x00000001 // Controller Master Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_CTLBASE register.
//
//*****************************************************************************
#define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 // Channel Control Base Address
#define UDMA_CTLBASE_ADDR_S 10
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_ALTBASE register.
//
//*****************************************************************************
#define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF // Alternate Channel Address
// Pointer
#define UDMA_ALTBASE_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_WAITSTAT register.
//
//*****************************************************************************
#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF // Channel [n] Wait Status
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_SWREQ register.
//
//*****************************************************************************
#define UDMA_SWREQ_M 0xFFFFFFFF // Channel [n] Software Request
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_USEBURSTSET
// register.
//
//*****************************************************************************
#define UDMA_USEBURSTSET_SET_M 0xFFFFFFFF // Channel [n] Useburst Set
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_USEBURSTCLR
// register.
//
//*****************************************************************************
#define UDMA_USEBURSTCLR_CLR_M 0xFFFFFFFF // Channel [n] Useburst Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_REQMASKSET
// register.
//
//*****************************************************************************
#define UDMA_REQMASKSET_SET_M 0xFFFFFFFF // Channel [n] Request Mask Set
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_REQMASKCLR
// register.
//
//*****************************************************************************
#define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF // Channel [n] Request Mask Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_ENASET register.
//
//*****************************************************************************
#define UDMA_ENASET_SET_M 0xFFFFFFFF // Channel [n] Enable Set
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_ENACLR register.
//
//*****************************************************************************
#define UDMA_ENACLR_CLR_M 0xFFFFFFFF // Clear Channel [n] Enable Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_ALTSET register.
//
//*****************************************************************************
#define UDMA_ALTSET_SET_M 0xFFFFFFFF // Channel [n] Alternate Set
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_ALTCLR register.
//
//*****************************************************************************
#define UDMA_ALTCLR_CLR_M 0xFFFFFFFF // Channel [n] Alternate Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_PRIOSET register.
//
//*****************************************************************************
#define UDMA_PRIOSET_SET_M 0xFFFFFFFF // Channel [n] Priority Set
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_PRIOCLR register.
//
//*****************************************************************************
#define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF // Channel [n] Priority Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_ERRCLR register.
//
//*****************************************************************************
#define UDMA_ERRCLR_ERRCLR 0x00000001 // uDMA Bus Error Status
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_CHASGN register.
//
//*****************************************************************************
#define UDMA_CHASGN_M 0xFFFFFFFF // Channel [n] Assignment Select
#define UDMA_CHASGN_PRIMARY 0x00000000 // Use the primary channel
// assignment
#define UDMA_CHASGN_SECONDARY 0x00000001 // Use the secondary channel
// assignment
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_CHIS register.
//
//*****************************************************************************
#define UDMA_CHIS_M 0xFFFFFFFF // Channel [n] Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_CHMAP0 register.
//
//*****************************************************************************
#define UDMA_CHMAP0_CH7SEL_M 0xF0000000 // uDMA Channel 7 Source Select
#define UDMA_CHMAP0_CH6SEL_M 0x0F000000 // uDMA Channel 6 Source Select
#define UDMA_CHMAP0_CH5SEL_M 0x00F00000 // uDMA Channel 5 Source Select
#define UDMA_CHMAP0_CH4SEL_M 0x000F0000 // uDMA Channel 4 Source Select
#define UDMA_CHMAP0_CH3SEL_M 0x0000F000 // uDMA Channel 3 Source Select
#define UDMA_CHMAP0_CH2SEL_M 0x00000F00 // uDMA Channel 2 Source Select
#define UDMA_CHMAP0_CH1SEL_M 0x000000F0 // uDMA Channel 1 Source Select
#define UDMA_CHMAP0_CH0SEL_M 0x0000000F // uDMA Channel 0 Source Select
#define UDMA_CHMAP0_CH7SEL_S 28
#define UDMA_CHMAP0_CH6SEL_S 24
#define UDMA_CHMAP0_CH5SEL_S 20
#define UDMA_CHMAP0_CH4SEL_S 16
#define UDMA_CHMAP0_CH3SEL_S 12
#define UDMA_CHMAP0_CH2SEL_S 8
#define UDMA_CHMAP0_CH1SEL_S 4
#define UDMA_CHMAP0_CH0SEL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_CHMAP1 register.
//
//*****************************************************************************
#define UDMA_CHMAP1_CH15SEL_M 0xF0000000 // uDMA Channel 15 Source Select
#define UDMA_CHMAP1_CH14SEL_M 0x0F000000 // uDMA Channel 14 Source Select
#define UDMA_CHMAP1_CH13SEL_M 0x00F00000 // uDMA Channel 13 Source Select
#define UDMA_CHMAP1_CH12SEL_M 0x000F0000 // uDMA Channel 12 Source Select
#define UDMA_CHMAP1_CH11SEL_M 0x0000F000 // uDMA Channel 11 Source Select
#define UDMA_CHMAP1_CH10SEL_M 0x00000F00 // uDMA Channel 10 Source Select
#define UDMA_CHMAP1_CH9SEL_M 0x000000F0 // uDMA Channel 9 Source Select
#define UDMA_CHMAP1_CH8SEL_M 0x0000000F // uDMA Channel 8 Source Select
#define UDMA_CHMAP1_CH15SEL_S 28
#define UDMA_CHMAP1_CH14SEL_S 24
#define UDMA_CHMAP1_CH13SEL_S 20
#define UDMA_CHMAP1_CH12SEL_S 16
#define UDMA_CHMAP1_CH11SEL_S 12
#define UDMA_CHMAP1_CH10SEL_S 8
#define UDMA_CHMAP1_CH9SEL_S 4
#define UDMA_CHMAP1_CH8SEL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_CHMAP2 register.
//
//*****************************************************************************
#define UDMA_CHMAP2_CH23SEL_M 0xF0000000 // uDMA Channel 23 Source Select
#define UDMA_CHMAP2_CH22SEL_M 0x0F000000 // uDMA Channel 22 Source Select
#define UDMA_CHMAP2_CH21SEL_M 0x00F00000 // uDMA Channel 21 Source Select
#define UDMA_CHMAP2_CH20SEL_M 0x000F0000 // uDMA Channel 20 Source Select
#define UDMA_CHMAP2_CH19SEL_M 0x0000F000 // uDMA Channel 19 Source Select
#define UDMA_CHMAP2_CH18SEL_M 0x00000F00 // uDMA Channel 18 Source Select
#define UDMA_CHMAP2_CH17SEL_M 0x000000F0 // uDMA Channel 17 Source Select
#define UDMA_CHMAP2_CH16SEL_M 0x0000000F // uDMA Channel 16 Source Select
#define UDMA_CHMAP2_CH23SEL_S 28
#define UDMA_CHMAP2_CH22SEL_S 24
#define UDMA_CHMAP2_CH21SEL_S 20
#define UDMA_CHMAP2_CH20SEL_S 16
#define UDMA_CHMAP2_CH19SEL_S 12
#define UDMA_CHMAP2_CH18SEL_S 8
#define UDMA_CHMAP2_CH17SEL_S 4
#define UDMA_CHMAP2_CH16SEL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_CHMAP3 register.
//
//*****************************************************************************
#define UDMA_CHMAP3_CH31SEL_M 0xF0000000 // uDMA Channel 31 Source Select
#define UDMA_CHMAP3_CH30SEL_M 0x0F000000 // uDMA Channel 30 Source Select
#define UDMA_CHMAP3_CH29SEL_M 0x00F00000 // uDMA Channel 29 Source Select
#define UDMA_CHMAP3_CH28SEL_M 0x000F0000 // uDMA Channel 28 Source Select
#define UDMA_CHMAP3_CH27SEL_M 0x0000F000 // uDMA Channel 27 Source Select
#define UDMA_CHMAP3_CH26SEL_M 0x00000F00 // uDMA Channel 26 Source Select
#define UDMA_CHMAP3_CH25SEL_M 0x000000F0 // uDMA Channel 25 Source Select
#define UDMA_CHMAP3_CH24SEL_M 0x0000000F // uDMA Channel 24 Source Select
#define UDMA_CHMAP3_CH31SEL_S 28
#define UDMA_CHMAP3_CH30SEL_S 24
#define UDMA_CHMAP3_CH29SEL_S 20
#define UDMA_CHMAP3_CH28SEL_S 16
#define UDMA_CHMAP3_CH27SEL_S 12
#define UDMA_CHMAP3_CH26SEL_S 8
#define UDMA_CHMAP3_CH25SEL_S 4
#define UDMA_CHMAP3_CH24SEL_S 0
//*****************************************************************************
//
// The following are defines for the Micro Direct Memory Access (uDMA) offsets.
//
//*****************************************************************************
#define UDMA_O_SRCENDP 0x00000000 // DMA Channel Source Address End
// Pointer
#define UDMA_O_DSTENDP 0x00000004 // DMA Channel Destination Address
// End Pointer
#define UDMA_O_CHCTL 0x00000008 // DMA Channel Control Word
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_SRCENDP register.
//
//*****************************************************************************
#define UDMA_SRCENDP_ADDR_M 0xFFFFFFFF // Source Address End Pointer
#define UDMA_SRCENDP_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_DSTENDP register.
//
//*****************************************************************************
#define UDMA_DSTENDP_ADDR_M 0xFFFFFFFF // Destination Address End Pointer
#define UDMA_DSTENDP_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_CHCTL register.
//
//*****************************************************************************
#define UDMA_CHCTL_DSTINC_M 0xC0000000 // Destination Address Increment
#define UDMA_CHCTL_DSTINC_8 0x00000000 // Byte
#define UDMA_CHCTL_DSTINC_16 0x40000000 // Half-word
#define UDMA_CHCTL_DSTINC_32 0x80000000 // Word
#define UDMA_CHCTL_DSTINC_NONE 0xC0000000 // No increment
#define UDMA_CHCTL_DSTSIZE_M 0x30000000 // Destination Data Size
#define UDMA_CHCTL_DSTSIZE_8 0x00000000 // Byte
#define UDMA_CHCTL_DSTSIZE_16 0x10000000 // Half-word
#define UDMA_CHCTL_DSTSIZE_32 0x20000000 // Word
#define UDMA_CHCTL_SRCINC_M 0x0C000000 // Source Address Increment
#define UDMA_CHCTL_SRCINC_8 0x00000000 // Byte
#define UDMA_CHCTL_SRCINC_16 0x04000000 // Half-word
#define UDMA_CHCTL_SRCINC_32 0x08000000 // Word
#define UDMA_CHCTL_SRCINC_NONE 0x0C000000 // No increment
#define UDMA_CHCTL_SRCSIZE_M 0x03000000 // Source Data Size
#define UDMA_CHCTL_SRCSIZE_8 0x00000000 // Byte
#define UDMA_CHCTL_SRCSIZE_16 0x01000000 // Half-word
#define UDMA_CHCTL_SRCSIZE_32 0x02000000 // Word
#define UDMA_CHCTL_DSTPROT0 0x00200000 // Destination Privilege Access
#define UDMA_CHCTL_SRCPROT0 0x00040000 // Source Privilege Access
#define UDMA_CHCTL_ARBSIZE_M 0x0003C000 // Arbitration Size
#define UDMA_CHCTL_ARBSIZE_1 0x00000000 // 1 Transfer
#define UDMA_CHCTL_ARBSIZE_2 0x00004000 // 2 Transfers
#define UDMA_CHCTL_ARBSIZE_4 0x00008000 // 4 Transfers
#define UDMA_CHCTL_ARBSIZE_8 0x0000C000 // 8 Transfers
#define UDMA_CHCTL_ARBSIZE_16 0x00010000 // 16 Transfers
#define UDMA_CHCTL_ARBSIZE_32 0x00014000 // 32 Transfers
#define UDMA_CHCTL_ARBSIZE_64 0x00018000 // 64 Transfers
#define UDMA_CHCTL_ARBSIZE_128 0x0001C000 // 128 Transfers
#define UDMA_CHCTL_ARBSIZE_256 0x00020000 // 256 Transfers
#define UDMA_CHCTL_ARBSIZE_512 0x00024000 // 512 Transfers
#define UDMA_CHCTL_ARBSIZE_1024 0x00028000 // 1024 Transfers
#define UDMA_CHCTL_XFERSIZE_M 0x00003FF0 // Transfer Size (minus 1)
#define UDMA_CHCTL_NXTUSEBURST 0x00000008 // Next Useburst
#define UDMA_CHCTL_XFERMODE_M 0x00000007 // uDMA Transfer Mode
#define UDMA_CHCTL_XFERMODE_STOP \
0x00000000 // Stop
#define UDMA_CHCTL_XFERMODE_BASIC \
0x00000001 // Basic
#define UDMA_CHCTL_XFERMODE_AUTO \
0x00000002 // Auto-Request
#define UDMA_CHCTL_XFERMODE_PINGPONG \
0x00000003 // Ping-Pong
#define UDMA_CHCTL_XFERMODE_MEM_SG \
0x00000004 // Memory Scatter-Gather
#define UDMA_CHCTL_XFERMODE_MEM_SGA \
0x00000005 // Alternate Memory Scatter-Gather
#define UDMA_CHCTL_XFERMODE_PER_SG \
0x00000006 // Peripheral Scatter-Gather
#define UDMA_CHCTL_XFERMODE_PER_SGA \
0x00000007 // Alternate Peripheral
// Scatter-Gather
#define UDMA_CHCTL_XFERSIZE_S 4
#endif // __HW_UDMA_H__

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//*****************************************************************************
//
// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware.
//
// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_WATCHDOG_H__
#define __HW_WATCHDOG_H__
//*****************************************************************************
//
// The following are defines for the Watchdog Timer register offsets.
//
//*****************************************************************************
#define WDT_O_LOAD 0x00000000 // Watchdog Load
#define WDT_O_VALUE 0x00000004 // Watchdog Value
#define WDT_O_CTL 0x00000008 // Watchdog Control
#define WDT_O_ICR 0x0000000C // Watchdog Interrupt Clear
#define WDT_O_RIS 0x00000010 // Watchdog Raw Interrupt Status
#define WDT_O_MIS 0x00000014 // Watchdog Masked Interrupt Status
#define WDT_O_TEST 0x00000418 // Watchdog Test
#define WDT_O_LOCK 0x00000C00 // Watchdog Lock
//*****************************************************************************
//
// The following are defines for the bit fields in the WDT_O_LOAD register.
//
//*****************************************************************************
#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value
#define WDT_LOAD_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the WDT_O_VALUE register.
//
//*****************************************************************************
#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value
#define WDT_VALUE_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the WDT_O_CTL register.
//
//*****************************************************************************
#define WDT_CTL_WRC 0x80000000 // Write Complete
#define WDT_CTL_INTTYPE 0x00000004 // Watchdog Interrupt Type
#define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable
#define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the WDT_O_ICR register.
//
//*****************************************************************************
#define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear
#define WDT_ICR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the WDT_O_RIS register.
//
//*****************************************************************************
#define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the WDT_O_MIS register.
//
//*****************************************************************************
#define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the WDT_O_TEST register.
//
//*****************************************************************************
#define WDT_TEST_STALL 0x00000100 // Watchdog Stall Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the WDT_O_LOCK register.
//
//*****************************************************************************
#define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock
#define WDT_LOCK_UNLOCKED 0x00000000 // Unlocked
#define WDT_LOCK_LOCKED 0x00000001 // Locked
#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer
#endif // __HW_WATCHDOG_H__

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//*****************************************************************************
//
// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver.
//
// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __DRIVERLIB_INTERRUPT_H__
#define __DRIVERLIB_INTERRUPT_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Macro to generate an interrupt priority mask based on the number of bits
// of priority supported by the hardware.
//
//*****************************************************************************
#define INT_PRIORITY_MASK ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF)
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern bool IntMasterEnable(void);
extern bool IntMasterDisable(void);
extern void IntRegister(uint32_t ui32Interrupt, void (*pfnHandler)(void));
extern void IntUnregister(uint32_t ui32Interrupt);
extern void IntPriorityGroupingSet(uint32_t ui32Bits);
extern uint32_t IntPriorityGroupingGet(void);
extern void IntPrioritySet(uint32_t ui32Interrupt,
uint8_t ui8Priority);
extern int32_t IntPriorityGet(uint32_t ui32Interrupt);
extern void IntEnable(uint32_t ui32Interrupt);
extern void IntDisable(uint32_t ui32Interrupt);
extern uint32_t IntIsEnabled(uint32_t ui32Interrupt);
extern void IntPendSet(uint32_t ui32Interrupt);
extern void IntPendClear(uint32_t ui32Interrupt);
extern void IntPriorityMaskSet(uint32_t ui32PriorityMask);
extern uint32_t IntPriorityMaskGet(void);
extern void IntTrigger(uint32_t ui32Interrupt);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_INTERRUPT_H__

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//*****************************************************************************
//
// lcd.h - Defines and Macros for the LCD Controller module.
//
// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __DRIVERLIB_LCD_H__
#define __DRIVERLIB_LCD_H__
//*****************************************************************************
//
//! \addtogroup lcd_api
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
//! This macro can be used to convert a 24-bit RGB color value as used by the
//! TivaWare Graphics Library into a 12-bit LCD controller color palette
//! entry.
//
//*****************************************************************************
#define PAL_FROM_RGB(ui32RGBColor) (((ui32RGBColor & 0xF0) >> 4) | \
((ui32RGBColor & 0xF000) >> 8) | \
((ui32RGBColor & 0xF00000) >> 12))
//*****************************************************************************
//
//! This macro can be used to convert from time in microseconds to periods of
//! the supplied clock in Hertz as required when setting up the LIDD and raster
//! timing structures. The calculation will round such that the number of
//! cycles returned represents no longer a time than specified in the
//! ui32Time_uS parameter. Values of ui32Time_uS less than or equal to
//! 4294967uS (4.29 seconds) are supported by the macro. Larger values will
//! cause arithmetic overflow and yield incorrect values. It is further
//! assumed that ui32ClockFreq is a non-zero multiple of 1000000 (1MHz).
//
//*****************************************************************************
#define CYCLES_FROM_TIME_US(ui32ClockFreq, ui32Time_uS) \
(((ui32Time_uS) == 0) ? 0 : \
(((ui32ClockFreq) / 1000000) * ((((ui32Time_uS) * 1000) - 1) / 1000)) + 1)
//*****************************************************************************
//
//! This macro can be used to convert from time in nanoseconds to periods of
//! the supplied clock in Hertz as required when setting up the LIDD and raster
//! timing structures. The calculation will round such that the number of
//! cycles returned represents no longer a time than specified in the
//! ui32Time_nS parameter. Values of ui32Time_nS less than or equal to
//! 35791394 (35.79 milliseconds) are supported by the macro. Larger values
//! will cause arithmetic overflow and yield incorrect values. It is further
//! assumed that ui32ClockFreq is a non-zero multiple of 1000000 (1MHz).
//
//*****************************************************************************
#define CYCLES_FROM_TIME_NS(ui32ClockFreq, ui32Time_nS) \
(((ui32Time_nS) == 0) ? 0 : \
((((((ui32ClockFreq) / 1000000) * ((ui32Time_nS) - 1)) / 1000)) + 1))
//*****************************************************************************
//
//! A structure containing timing parameters for the LIDD (LCD Interface
//! Display Driver) interface. This is used with the LCDIDDTimingSet function.
//
//*****************************************************************************
typedef struct
{
//
//! Write Strobe Set-Up cycles. When performing a write access, this
//! field defines the number of MCLK cycles that Data Bus/Pad Output
//! Enable, ALE, the Direction bit, and Chip Select have to be ready before
//! the Write Strobe is asserted. Valid values are from 0 to 31.
//
uint8_t ui8WSSetup;
//
//! Write Strobe Duration cycles. Field value defines the number of MCLK
//! cycles for which the Write Strobe is held active when performing a
//! write access. Valid values are from 1 to 63.
//
uint8_t ui8WSDuration;
//
//! Write Strobe Hold cycles. Field value defines the number of MCLK
//! cycles for which Data Bus/Pad Output Enable, ALE, the Direction bit,
//! and Chip Select are held after the Write Strobe is deasserted when
//! performing a write access. Valid values are from 1 to 15.
//
uint8_t ui8WSHold;
//
//! Read Strobe Set-Up cycles. When performing a read access, this field
//! defines the number of MCLK cycles that Data Bus/Pad Output Enable, ALE,
//! the Direction bit, and Chip Select have to be ready before the Read
//! Strobe is asserted. Valid values are from 0 to 31.
//
uint8_t ui8RSSetup;
//
//! Read Strobe Duration cycles. Field value defines the number of MCLK
//! cycles for which the Read Strobe is held active when performing a read
//! access. Valid values are from 1 to 63.
//
uint8_t ui8RSDuration;
//
//! Read Strobe Hold cycles. Field value defines the number of MCLK cycles
//! for which Data Bus/Pad Output Enable, ALE, the Direction bit, and Chip
//! Select are held after the Read Strobe is deasserted when performing a
//! read access. Valid values are from 1 to 15.
//
uint8_t ui8RSHold;
//
//! Field value defines the number of MCLK cycles between the end of one
//! device access and the start of another device access using the same
//! Chip Select unless the two accesses are both Reads. In this case,
//! this delay is not incurred. Valid vales are from 1 to 4.
//
uint8_t ui8DelayCycles;
}
tLCDIDDTiming;
//
// Values which can be ORed together within the ui32Flags field of the
// tLCDRasterTiming structure.
//
#define RASTER_TIMING_SYNCS_OPPOSITE_PIXCLK \
0x00000000
#define RASTER_TIMING_SYNCS_ON_RISING_PIXCLK \
0x02000000
#define RASTER_TIMING_SYNCS_ON_FALLING_PIXCLK \
0x03000000
#define RASTER_TIMING_ACTIVE_HIGH_OE \
0x00000000
#define RASTER_TIMING_ACTIVE_LOW_OE \
0x00800000
#define RASTER_TIMING_ACTIVE_HIGH_PIXCLK \
0x00000000
#define RASTER_TIMING_ACTIVE_LOW_PIXCLK \
0x00400000
#define RASTER_TIMING_ACTIVE_HIGH_HSYNC \
0x00000000
#define RASTER_TIMING_ACTIVE_LOW_HSYNC \
0x00200000
#define RASTER_TIMING_ACTIVE_HIGH_VSYNC \
0x00000000
#define RASTER_TIMING_ACTIVE_LOW_VSYNC \
0x00100000
//
//! A structure containing timing parameters for the raster interface. This is
//! used with the LCDRasterTimingSet function.
//
typedef struct
{
//
//! Flags configuring the polarity and active edges of the various signals
//! in the raster interface. This field is comprised of a logical OR of
//! the labels with prefix ``RASTER_TIMING_''.
//
uint32_t ui32Flags;
//
//! The number of pixels contained within each line on the LCD display.
//! Valid values are multiple of 16 less than or equal to 2048.
//
uint16_t ui16PanelWidth;
//
//! The number of lines on the LCD display. Valid values are from 1 to
//! 2048.
//
uint16_t ui16PanelHeight;
//
//! A value from 1 to 1024 that specifies the number of pixel clock periods
//! to add to the end of each line after active video has ended.
//
uint16_t ui16HFrontPorch;
//
//! A value from 1 to 1024 that specifies the number of pixel clock periods
//! to add to the beginning of a line before active video is asserted.
//
uint16_t ui16HBackPorch;
//
//! A value from 1 to 1024 that specifies the number of pixel clock periods
//! to pulse the line clock at the end of each line.
//
uint16_t ui16HSyncWidth;
//
//! A value from 0 to 255 that specifies the number of line clock periods
//! to add to the end of each frame after the last active line.
//
uint8_t ui8VFrontPorch;
//
//! A value from 0 to 255 that specifies the number of line clock periods
//! to add to the beginning of a frame before the first active line is
//! output to the display.
//
uint8_t ui8VBackPorch;
//
//! In active mode, a value from 1 to 64 that specifies the number of
//! line clock periods to set the lcd_fp pin active at the end of each
//! frame after the vertical front porch period elapses. The number of
//! The frame clock is used as the VSYNC signal in active mode.
//!
//! In passive mode, a value from 1 to 64 that specifies the number of
//! extra line clock periods to insert after the vertical front porch
//! period has elapsed. Note that the width of lcd_fp is not affected by
//! this value in passive mode.
//
uint8_t ui8VSyncWidth;
//
//! A value from 0 to 255 that specifies the number of line clocks to
//! count before transitioning the AC Bias pin. This pin is used to
//! periodically invert the polarity of the power supply to prevent DC
//! charge build-up within the display.
//
uint8_t ui8ACBiasLineCount;
}
tLCDRasterTiming;
//*****************************************************************************
//
// Possible values for the ui8Mode parameter to LCDModeSet(). The label
// LCD_MODE_AUTO_UFLOW_RESTART may be ORed with either of the other two.
//
//*****************************************************************************
#define LCD_MODE_LIDD ((uint8_t)0x00)
#define LCD_MODE_RASTER ((uint8_t)0x01)
#define LCD_MODE_AUTO_UFLOW_RESTART \
((uint8_t)0x02)
//*****************************************************************************
//
// Values used to construct the ui32Config parameter to LCDIDDConfigSet().
//
//*****************************************************************************
#define LIDD_CONFIG_SYNC_MPU68 0x00000000
#define LIDD_CONFIG_ASYNC_MPU68 0x00000001
#define LIDD_CONFIG_SYNC_MPU80 0x00000002
#define LIDD_CONFIG_ASYNC_MPU80 0x00000003
#define LIDD_CONFIG_ASYNC_HITACHI \
0x00000004
#define LIDD_CONFIG_INVERT_ALE 0x00000008
#define LIDD_CONFIG_INVERT_RS_EN \
0x00000010
#define LIDD_CONFIG_INVERT_WS_DIR \
0x00000020
#define LIDD_CONFIG_INVERT_CS0 0x00000040
#define LIDD_CONFIG_INVERT_CS1 0x00000080
//*****************************************************************************
//
// Values used to construct the ui32Config parameter to
// LCDRasterConfigSet(). Valid parameters contain one of the RASTER_FMT_xxx
// labels optionally ORed with the other flags. Only one of
// RASTER_LOAD_DATA_ONLY and RASTER_LOAD_PALETTE_ONLY may be specified (if
// neither is specified, the controller will load both palette and data when
// scanning out the frame buffer).
//
//*****************************************************************************
#define RASTER_FMT_ACTIVE_24BPP_PACKED \
0x02000080
#define RASTER_FMT_ACTIVE_24BPP_UNPACKED \
0x06000080
#define RASTER_FMT_ACTIVE_PALETTIZED_12BIT \
0x00000080
#define RASTER_FMT_ACTIVE_PALETTIZED_16BIT \
0x00800080
#define RASTER_FMT_PASSIVE_MONO_4PIX \
0x00000002
#define RASTER_FMT_PASSIVE_MONO_8PIX \
0x00000202
#define RASTER_FMT_PASSIVE_PALETTIZED \
0x00000000
#define RASTER_FMT_PASSIVE_COLOR_12BIT \
0x00000000
#define RASTER_FMT_PASSIVE_COLOR_16BIT \
0x01000000
#define RASTER_ACTVID_DURING_BLANK \
0x08000000
#define RASTER_NIBBLE_MODE_ENABLED \
0x00400000
#define RASTER_LOAD_DATA_ONLY 0x00200000
#define RASTER_LOAD_PALETTE_ONLY \
0x00100000
#define RASTER_READ_ORDER_REVERSED \
0x00000100
//*****************************************************************************
//
// Interrupt sources for the LCD controller. These may be ORed together and
// passed to LCDIntEnable(), LCDIntDisable() and LCDIntClear(). They are also
// returned by LCDIntStatus().
//
//*****************************************************************************
#define LCD_INT_DMA_DONE 0x00000001
#define LCD_INT_RASTER_FRAME_DONE \
0x00000002
#define LCD_INT_SYNC_LOST 0x00000004
#define LCD_INT_AC_BIAS_CNT 0x00000008
#define LCD_INT_UNDERFLOW 0x00000020
#define LCD_INT_PAL_LOAD 0x00000040
#define LCD_INT_EOF0 0x00000100
#define LCD_INT_EOF1 0x00000200
//*****************************************************************************
//
// Configuration values used with LCDDMAConfigSet().
//
//*****************************************************************************
#define LCD_DMA_FIFORDY_8_WORDS 0x00000000
#define LCD_DMA_FIFORDY_16_WORDS \
0x00000100
#define LCD_DMA_FIFORDY_32_WORDS \
0x00000200
#define LCD_DMA_FIFORDY_64_WORDS \
0x00000300
#define LCD_DMA_FIFORDY_128_WORDS \
0x00000400
#define LCD_DMA_FIFORDY_256_WORDS \
0x00000500
#define LCD_DMA_FIFORDY_512_WORDS \
0x00000600
#define LCD_DMA_BURST_1 0x00000010
#define LCD_DMA_BURST_2 0x00000010
#define LCD_DMA_BURST_4 0x00000020
#define LCD_DMA_BURST_8 0x00000030
#define LCD_DMA_BURST_16 0x00000040
#define LCD_DMA_BYTE_ORDER_0123 0x00000000
#define LCD_DMA_BYTE_ORDER_1023 0x00000008
#define LCD_DMA_BYTE_ORDER_3210 0x00000002
#define LCD_DMA_BYTE_ORDER_2301 0x0000000A
#define LCD_DMA_PING_PONG 0x00000001
//*****************************************************************************
//
// Type values used with LCDRasterPaletteSet().
//
//*****************************************************************************
#define LCD_PALETTE_TYPE_1BPP 0x00000000
#define LCD_PALETTE_TYPE_2BPP 0x00001000
#define LCD_PALETTE_TYPE_4BPP 0x00002000
#define LCD_PALETTE_TYPE_8BPP 0x00003000
#define LCD_PALETTE_TYPE_DIRECT 0x00004000
#define LCD_PALETTE_SRC_24BIT 0x80000000
//*****************************************************************************
//
// Flags used in the ui32Clocks parameter to LCDClockReset().
//
//*****************************************************************************
#define LCD_CLOCK_MAIN 0x00000008
#define LCD_CLOCK_DMA 0x00000004
#define LCD_CLOCK_LIDD 0x00000002
#define LCD_CLOCK_CORE 0x00000001
//*****************************************************************************
//
// Flags used in with LCDSubPanelConfigSet().
//
//*****************************************************************************
#define LCD_SUBPANEL_AT_TOP 0x20000000
#define LCD_SUBPANEL_AT_BOTTOM 0x00000000
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
//*****************************************************************************
//
// Function Prototypes.
//
//*****************************************************************************
extern uint32_t LCDModeSet(uint32_t ui32Base, uint8_t ui8Mode,
uint32_t ui32PixClk, uint32_t ui32SysClk);
extern void LCDClockReset(uint32_t ui32Base, uint32_t ui32Clocks);
extern void LCDIDDConfigSet(uint32_t ui32Base, uint32_t ui32Config);
extern void LCDIDDTimingSet(uint32_t ui32Base, uint32_t ui32CS,
const tLCDIDDTiming *pTiming);
extern void LCDIDDDMADisable(uint32_t ui32Base);
extern void LCDIDDCommandWrite(uint32_t ui32Base, uint32_t ui32CS,
uint16_t ui16Cmd);
extern void LCDIDDDataWrite(uint32_t ui32Base, uint32_t ui32CS,
uint16_t ui16Data);
extern void LCDIDDIndexedWrite(uint32_t ui32Base, uint32_t ui32CS,
uint16_t ui16Addr, uint16_t ui16Data);
extern uint16_t LCDIDDStatusRead(uint32_t ui32Base, uint32_t ui32CS);
extern uint16_t LCDIDDDataRead(uint32_t ui32Base, uint32_t ui32CS);
extern uint16_t LCDIDDIndexedRead(uint32_t ui32Base, uint32_t ui32CS,
uint16_t ui16Addr);
extern void LCDIDDDMAWrite(uint32_t ui32Base, uint32_t ui32CS,
const uint32_t *pui32Data, uint32_t ui32Count);
extern void LCDRasterConfigSet(uint32_t ui32Base, uint32_t ui32Config,
uint8_t ui8PalLoadDelay);
extern void LCDRasterTimingSet(uint32_t ui32Base,
const tLCDRasterTiming *pTiming);
extern void LCDRasterACBiasIntCountSet(uint32_t ui32Base, uint8_t ui8Count);
extern void LCDRasterEnable(uint32_t ui32Base);
extern bool LCDRasterEnabled(uint32_t ui32Base);
extern void LCDRasterDisable(uint32_t ui32Base);
extern void LCDRasterSubPanelConfigSet(uint32_t ui32Base, uint32_t ui32Flags,
uint32_t ui32BottomLines,
uint32_t ui32DefaultPixel);
extern void LCDRasterSubPanelEnable(uint32_t ui32Base);
extern void LCDRasterSubPanelDisable(uint32_t ui32Base);
extern void LCDDMAConfigSet(uint32_t ui32Base, uint32_t ui32Config);
extern void LCDRasterPaletteSet(uint32_t ui32Base, uint32_t ui32Type,
uint32_t *pui32PalAddr,
const uint32_t *pui32SrcColors,
uint32_t ui32Start,
uint32_t ui32Count);
extern void LCDRasterFrameBufferSet(uint32_t ui32Base, uint8_t ui8Buffer,
uint32_t *pui32Addr,
uint32_t ui32NumBytes);
extern void LCDIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void LCDIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
extern uint32_t LCDIntStatus(uint32_t ui32Base, bool bMasked);
extern void LCDIntClear(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void LCDIntRegister(uint32_t ui32Base, void (*pfnHandler)(void));
extern void LCDIntUnregister(uint32_t ui32Base);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_LCD_H__

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//*****************************************************************************
//
// mpu.h - Defines and Macros for the memory protection unit.
//
// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __DRIVERLIB_MPU_H__
#define __DRIVERLIB_MPU_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Flags that can be passed to MPUEnable.
//
//*****************************************************************************
#define MPU_CONFIG_PRIV_DEFAULT 4
#define MPU_CONFIG_HARDFLT_NMI 2
#define MPU_CONFIG_NONE 0
//*****************************************************************************
//
// Flags for the region size to be passed to MPURegionSet.
//
//*****************************************************************************
#define MPU_RGN_SIZE_32B (4 << 1)
#define MPU_RGN_SIZE_64B (5 << 1)
#define MPU_RGN_SIZE_128B (6 << 1)
#define MPU_RGN_SIZE_256B (7 << 1)
#define MPU_RGN_SIZE_512B (8 << 1)
#define MPU_RGN_SIZE_1K (9 << 1)
#define MPU_RGN_SIZE_2K (10 << 1)
#define MPU_RGN_SIZE_4K (11 << 1)
#define MPU_RGN_SIZE_8K (12 << 1)
#define MPU_RGN_SIZE_16K (13 << 1)
#define MPU_RGN_SIZE_32K (14 << 1)
#define MPU_RGN_SIZE_64K (15 << 1)
#define MPU_RGN_SIZE_128K (16 << 1)
#define MPU_RGN_SIZE_256K (17 << 1)
#define MPU_RGN_SIZE_512K (18 << 1)
#define MPU_RGN_SIZE_1M (19 << 1)
#define MPU_RGN_SIZE_2M (20 << 1)
#define MPU_RGN_SIZE_4M (21 << 1)
#define MPU_RGN_SIZE_8M (22 << 1)
#define MPU_RGN_SIZE_16M (23 << 1)
#define MPU_RGN_SIZE_32M (24 << 1)
#define MPU_RGN_SIZE_64M (25 << 1)
#define MPU_RGN_SIZE_128M (26 << 1)
#define MPU_RGN_SIZE_256M (27 << 1)
#define MPU_RGN_SIZE_512M (28 << 1)
#define MPU_RGN_SIZE_1G (29 << 1)
#define MPU_RGN_SIZE_2G (30 << 1)
#define MPU_RGN_SIZE_4G (31 << 1)
//*****************************************************************************
//
// Flags for the permissions to be passed to MPURegionSet.
//
//*****************************************************************************
#define MPU_RGN_PERM_EXEC 0x00000000
#define MPU_RGN_PERM_NOEXEC 0x10000000
#define MPU_RGN_PERM_PRV_NO_USR_NO 0x00000000
#define MPU_RGN_PERM_PRV_RW_USR_NO 0x01000000
#define MPU_RGN_PERM_PRV_RW_USR_RO 0x02000000
#define MPU_RGN_PERM_PRV_RW_USR_RW 0x03000000
#define MPU_RGN_PERM_PRV_RO_USR_NO 0x05000000
#define MPU_RGN_PERM_PRV_RO_USR_RO 0x06000000
//*****************************************************************************
//
// Flags for the sub-region to be passed to MPURegionSet.
//
//*****************************************************************************
#define MPU_SUB_RGN_DISABLE_0 0x00000100
#define MPU_SUB_RGN_DISABLE_1 0x00000200
#define MPU_SUB_RGN_DISABLE_2 0x00000400
#define MPU_SUB_RGN_DISABLE_3 0x00000800
#define MPU_SUB_RGN_DISABLE_4 0x00001000
#define MPU_SUB_RGN_DISABLE_5 0x00002000
#define MPU_SUB_RGN_DISABLE_6 0x00004000
#define MPU_SUB_RGN_DISABLE_7 0x00008000
//*****************************************************************************
//
// Flags to enable or disable a region, to be passed to MPURegionSet.
//
//*****************************************************************************
#define MPU_RGN_ENABLE 1
#define MPU_RGN_DISABLE 0
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void MPUEnable(uint32_t ui32MPUConfig);
extern void MPUDisable(void);
extern uint32_t MPURegionCountGet(void);
extern void MPURegionEnable(uint32_t ui32Region);
extern void MPURegionDisable(uint32_t ui32Region);
extern void MPURegionSet(uint32_t ui32Region, uint32_t ui32Addr,
uint32_t ui32Flags);
extern void MPURegionGet(uint32_t ui32Region, uint32_t *pui32Addr,
uint32_t *pui32Flags);
extern void MPUIntRegister(void (*pfnHandler)(void));
extern void MPUIntUnregister(void);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_MPU_H__

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//*****************************************************************************
//
// onewire.h - Prototypes for the OneWire Driver.
//
// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __DRIVERLIB_ONEWIRE_H__
#define __DRIVERLIB_ONEWIRE_H__
//*****************************************************************************
//
//! \addtogroup onewire_api
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Defines used in the OneWireInit() function call.
//
//*****************************************************************************
//
// This define is used in initialization to request standard speed bus
// timings. This is the default.
//
#define ONEWIRE_INIT_SPD_STD 0x00000000
//
// This define is used in initialization to request overdrive speed bus
// timings.
//
#define ONEWIRE_INIT_SPD_OD 0x00000020
//
// This define is used in initialization to request standard read sampling
// timing (2us for ONEWIRE_INIT_SPD_OD and 16us for ONEWIRE_INIT_SPD_STD).
// This is the default.
//
#define ONEWIRE_INIT_READ_STD 0x00000000
//
// This define is used in initialization to request late read sampling
// timing (7us for ONEWIRE_INIT_SPD_OD and 50us for ONEWIRE_INIT_SPD_STD).
//
#define ONEWIRE_INIT_READ_LATE 0x00000040
//
// This define is used in initialization to request a standard
// Answer-to-Reset (presence detect) monitor. This is the default.
//
#define ONEWIRE_INIT_ATR 0x00000000
//
// This define is used in initialization to request no Answer-to-Reset
// (presence detect) monitor. The module will delay operations after a bus
// reset for the expected presence detect period in this case.
//
#define ONEWIRE_INIT_NO_ATR 0x00000080
//
// This define is used in initialization to request standard signal polarity
// on the 1-Wire bus (pin is driven low to drive bus low). This is the
// default.
//
#define ONEWIRE_INIT_STD_POL 0x00000000
//
// This define is used in initialization to request alternate signal polarity
// on the 1-Wire bus (pin is driven high to drive bus low).
//
#define ONEWIRE_INIT_ALT_POL 0x40000000
//
// This define is used in initialization to request normal 1-Wire operational
// mode. This is the default.
//
#define ONEWIRE_INIT_1_WIRE_CFG 0x00000000
//
// This define is used in initialization to request a 2 pin operational
// mode where one pin is used exclusively for TX operations and the other
// for RX.
//
#define ONEWIRE_INIT_2_WIRE_CFG 0x80000000
//*****************************************************************************
//
// Defines for bus status conditions. These values can be returned by
// OneWireBusStatus().
//
//*****************************************************************************
//
// This will be set if the bus is busy handling a Read, Write or
// Reset activity.
//
#define ONEWIRE_BUS_STATUS_BUSY 0x00000100
//
// This will be set if the module did not detect any slave presence pulses
// after a bus reset.
//
#define ONEWIRE_BUS_STATUS_NO_SLAVE \
0x00000200
//
// This will be set if the bus is being held low outside of a normal Read,
// Write or Reset activity.
//
#define ONEWIRE_BUS_STATUS_STUCK \
0x00000400
//*****************************************************************************
//
// OneWire operation modes used with OneWireTransaction().
//
//*****************************************************************************
//
// This mode flag indicates a single reset should be issued prior to a write
// and/or read operation.
//
#define ONEWIRE_OP_RESET 0x00000001
//
// This mode flag indicates a read operation.
//
#define ONEWIRE_OP_READ 0x00000002
//
// This mode flag indicates a write operation.
//
#define ONEWIRE_OP_WRITE 0x00000004
//*****************************************************************************
//
// OneWire DMA used with OneWireDMAEnable().
//
//*****************************************************************************
//
// This indicates the DMA should issue a 1-Wire bus reset before starting.
//
#define ONEWIRE_DMA_BUS_RESET 0x00000001
//
// The DMA operation will be a single Read after each module transaction.
//
#define ONEWIRE_DMA_OP_READ 0x00000002
//
// The DMA will write values to the 1-Wire interface as each previous DMA
// write operation completes.
//
#define ONEWIRE_DMA_OP_MULTI_WRITE \
0x00000004
//
// The DMA will read values from the 1-Wire interface as each previous DMA
// read operation completes.
//
#define ONEWIRE_DMA_OP_MULTI_READ \
0x00000006
//
// This Scatter Gather DMA mode is paired with ONEWIRE_DMA_OP_READ to instruct
// the 1-Wire DMA to initiate an operation at the start of and then on each
// transition completion thereafter.
//
#define ONEWIRE_DMA_MODE_SG 0x00000008
//
// DMA expects a Read/Write bus operation size of 8 bits. This should match
// the uDMA channel setup.
//
#define ONEWIRE_DMA_OP_SZ_8 0x00000000
//
// DMA expects a Read/Write bus operation size of 16 bits. This should match
// the uDMA channel setup.
//
#define ONEWIRE_DMA_OP_SZ_16 0x00000800
//
// DMA expects a Read/Write bus operation size of 32 bits. This should match
// the uDMA channel setup.
//
#define ONEWIRE_DMA_OP_SZ_32 0x00001800
//*****************************************************************************
//
// OneWire interrupt defines. Use in calls to OneWireIntEnable(),
// OneWireIntDisable(), OneWireIntClear() and returned by OneWireIntStatus().
//
//*****************************************************************************
//
// This interrupt indicates a bus reset has just completed.
//
#define ONEWIRE_INT_RESET_DONE 0x00000001
//
// The interrupt indicates a Read or Write master initiated operation
// has just completed.
//
#define ONEWIRE_INT_OP_DONE 0x00000002
//
// This interrupt indicates that no presence detect was signaled by a slave
// on the bus after a reset.
//
#define ONEWIRE_INT_NO_SLAVE 0x00000004
//
// This interrupt indicates the bus is being held low outside of normal
// operations.
//
#define ONEWIRE_INT_STUCK 0x00000008
//
// This interrupt indicates a OneWire DMA operation has completed.
//
#define ONEWIRE_INT_DMA_DONE 0x00000010
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void OneWireBusReset(uint32_t ui32Base);
extern uint32_t OneWireBusStatus(uint32_t ui32Base);
extern void OneWireDataGet(uint32_t u3i2Base, uint32_t *pui32Data);
extern bool OneWireDataGetNonBlocking(uint32_t ui32Base, uint32_t *pui32Data);
extern void OneWireDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags);
extern void OneWireDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags);
extern void OneWireInit(uint32_t ui32Base, uint32_t ui32InitFlags);
extern void OneWireIntClear(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void OneWireIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void OneWireIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void OneWireIntRegister(uint32_t ui32Base, void (*pfnHandler)(void));
extern void OneWireIntUnregister(uint32_t ui32Base);
extern uint32_t OneWireIntStatus(uint32_t ui32Base, bool bMasked);
extern void OneWireTransaction(uint32_t ui32Base, uint32_t ui32OpFlags,
uint32_t ui32Data, uint32_t ui32BitCnt);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_ONEWIRE_H__

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//*****************************************************************************
//
// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports
//
// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __DRIVERLIB_PWM_H__
#define __DRIVERLIB_PWM_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following defines are passed to PWMGenConfigure() as the ui32Config
// parameter and specify the configuration of the PWM generator.
//
//*****************************************************************************
#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode
#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode
#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates
#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates
#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode
#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode
#define PWM_GEN_MODE_FAULT_LATCHED \
0x00040000 // Fault is latched
#define PWM_GEN_MODE_FAULT_UNLATCHED \
0x00000000 // Fault is not latched
#define PWM_GEN_MODE_FAULT_MINPER \
0x00020000 // Enable min fault period
#define PWM_GEN_MODE_FAULT_NO_MINPER \
0x00000000 // Disable min fault period
#define PWM_GEN_MODE_FAULT_EXT 0x00010000 // Enable extended fault support
#define PWM_GEN_MODE_FAULT_LEGACY \
0x00000000 // Disable extended fault support
#define PWM_GEN_MODE_DB_NO_SYNC 0x00000000 // Deadband updates occur
// immediately
#define PWM_GEN_MODE_DB_SYNC_LOCAL \
0x0000A800 // Deadband updates locally
// synchronized
#define PWM_GEN_MODE_DB_SYNC_GLOBAL \
0x0000FC00 // Deadband updates globally
// synchronized
#define PWM_GEN_MODE_GEN_NO_SYNC \
0x00000000 // Generator mode updates occur
// immediately
#define PWM_GEN_MODE_GEN_SYNC_LOCAL \
0x00000280 // Generator mode updates locally
// synchronized
#define PWM_GEN_MODE_GEN_SYNC_GLOBAL \
0x000003C0 // Generator mode updates globally
// synchronized
//*****************************************************************************
//
// Defines for enabling, disabling, and clearing PWM generator interrupts and
// triggers.
//
//*****************************************************************************
#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0
#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD
#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U
#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D
#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U
#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D
#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0
#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD
#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U
#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D
#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U
#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D
//*****************************************************************************
//
// Defines for enabling, disabling, and clearing PWM interrupts.
//
//*****************************************************************************
#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt
#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt
#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt
#define PWM_INT_GEN_3 0x00000008 // Generator 3 interrupt
#define PWM_INT_FAULT0 0x00010000 // Fault0 interrupt
#define PWM_INT_FAULT1 0x00020000 // Fault1 interrupt
#define PWM_INT_FAULT2 0x00040000 // Fault2 interrupt
#define PWM_INT_FAULT3 0x00080000 // Fault3 interrupt
#define PWM_INT_FAULT_M 0x000F0000 // Fault interrupt source mask
//*****************************************************************************
//
// Defines to identify the generators within a module.
//
//*****************************************************************************
#define PWM_GEN_0 0x00000040 // Offset address of Gen0
#define PWM_GEN_1 0x00000080 // Offset address of Gen1
#define PWM_GEN_2 0x000000C0 // Offset address of Gen2
#define PWM_GEN_3 0x00000100 // Offset address of Gen3
#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0
#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1
#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2
#define PWM_GEN_3_BIT 0x00000008 // Bit-wise ID for Gen3
#define PWM_GEN_EXT_0 0x00000800 // Offset of Gen0 ext address range
#define PWM_GEN_EXT_1 0x00000880 // Offset of Gen1 ext address range
#define PWM_GEN_EXT_2 0x00000900 // Offset of Gen2 ext address range
#define PWM_GEN_EXT_3 0x00000980 // Offset of Gen3 ext address range
//*****************************************************************************
//
// Defines to identify the outputs within a module.
//
//*****************************************************************************
#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0
#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1
#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2
#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3
#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4
#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5
#define PWM_OUT_6 0x00000106 // Encoded offset address of PWM6
#define PWM_OUT_7 0x00000107 // Encoded offset address of PWM7
#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0
#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1
#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2
#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3
#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4
#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5
#define PWM_OUT_6_BIT 0x00000040 // Bit-wise ID for PWM6
#define PWM_OUT_7_BIT 0x00000080 // Bit-wise ID for PWM7
//*****************************************************************************
//
// Defines to identify each of the possible fault trigger conditions in
// PWM_FAULT_GROUP_0.
//
//*****************************************************************************
#define PWM_FAULT_GROUP_0 0
#define PWM_FAULT_FAULT0 0x00000001
#define PWM_FAULT_FAULT1 0x00000002
#define PWM_FAULT_FAULT2 0x00000004
#define PWM_FAULT_FAULT3 0x00000008
#define PWM_FAULT_ACMP0 0x00010000
#define PWM_FAULT_ACMP1 0x00020000
#define PWM_FAULT_ACMP2 0x00040000
//*****************************************************************************
//
// Defines to identify each of the possible fault trigger conditions in
// PWM_FAULT_GROUP_1.
//
//*****************************************************************************
#define PWM_FAULT_GROUP_1 1
#define PWM_FAULT_DCMP0 0x00000001
#define PWM_FAULT_DCMP1 0x00000002
#define PWM_FAULT_DCMP2 0x00000004
#define PWM_FAULT_DCMP3 0x00000008
#define PWM_FAULT_DCMP4 0x00000010
#define PWM_FAULT_DCMP5 0x00000020
#define PWM_FAULT_DCMP6 0x00000040
#define PWM_FAULT_DCMP7 0x00000080
//*****************************************************************************
//
// Defines to identify the sense of each of the external FAULTn signals
//
//*****************************************************************************
#define PWM_FAULT0_SENSE_HIGH 0x00000000
#define PWM_FAULT0_SENSE_LOW 0x00000001
#define PWM_FAULT1_SENSE_HIGH 0x00000000
#define PWM_FAULT1_SENSE_LOW 0x00000002
#define PWM_FAULT2_SENSE_HIGH 0x00000000
#define PWM_FAULT2_SENSE_LOW 0x00000004
#define PWM_FAULT3_SENSE_HIGH 0x00000000
#define PWM_FAULT3_SENSE_LOW 0x00000008
//*****************************************************************************
//
// Defines that can be passed to the PWMClockSet() API as the ui32Config
// parameter, and can be returned by the PWMClockGet() API.
//
//*****************************************************************************
#define PWM_SYSCLK_DIV_1 0x00000000 // PWM clock is system clock
#define PWM_SYSCLK_DIV_2 0x00000100 // PWM clock is system clock /2
#define PWM_SYSCLK_DIV_4 0x00000101 // PWM clock is system clock /4
#define PWM_SYSCLK_DIV_8 0x00000102 // PWM clock is system clock /8
#define PWM_SYSCLK_DIV_16 0x00000103 // PWM clock is system clock /16
#define PWM_SYSCLK_DIV_32 0x00000104 // PWM clock is system clock /32
#define PWM_SYSCLK_DIV_64 0x00000105 // PWM clock is system clock /64
//*****************************************************************************
//
// Defines passed to PWMOutputUpdateMode() to identify the synchronization mode
// to use when enabling or disabling outputs using PWMOutputState().
//
//*****************************************************************************
#define PWM_OUTPUT_MODE_NO_SYNC 0x00000000 // Updates to occur immediately
#define PWM_OUTPUT_MODE_SYNC_LOCAL \
0x00000002 // Updates are locally synchronized
#define PWM_OUTPUT_MODE_SYNC_GLOBAL \
0x00000003 // Updates are globally synchronized
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void PWMGenConfigure(uint32_t ui32Base, uint32_t ui32Gen,
uint32_t ui32Config);
extern void PWMGenPeriodSet(uint32_t ui32Base, uint32_t ui32Gen,
uint32_t ui32Period);
extern uint32_t PWMGenPeriodGet(uint32_t ui32Base,
uint32_t ui32Gen);
extern void PWMGenEnable(uint32_t ui32Base, uint32_t ui32Gen);
extern void PWMGenDisable(uint32_t ui32Base, uint32_t ui32Gen);
extern void PWMPulseWidthSet(uint32_t ui32Base, uint32_t ui32PWMOut,
uint32_t ui32Width);
extern uint32_t PWMPulseWidthGet(uint32_t ui32Base,
uint32_t ui32PWMOut);
extern void PWMDeadBandEnable(uint32_t ui32Base, uint32_t ui32Gen,
uint16_t ui16Rise, uint16_t ui16Fall);
extern void PWMDeadBandDisable(uint32_t ui32Base, uint32_t ui32Gen);
extern void PWMSyncUpdate(uint32_t ui32Base, uint32_t ui32GenBits);
extern void PWMSyncTimeBase(uint32_t ui32Base, uint32_t ui32GenBits);
extern void PWMOutputState(uint32_t ui32Base, uint32_t ui32PWMOutBits,
bool bEnable);
extern void PWMOutputInvert(uint32_t ui32Base, uint32_t ui32PWMOutBits,
bool bInvert);
extern void PWMOutputFaultLevel(uint32_t ui32Base,
uint32_t ui32PWMOutBits,
bool bDriveHigh);
extern void PWMOutputFault(uint32_t ui32Base, uint32_t ui32PWMOutBits,
bool bFaultSuppress);
extern void PWMGenIntRegister(uint32_t ui32Base, uint32_t ui32Gen,
void (*pfnIntHandler)(void));
extern void PWMGenIntUnregister(uint32_t ui32Base, uint32_t ui32Gen);
extern void PWMFaultIntRegister(uint32_t ui32Base,
void (*pfnIntHandler)(void));
extern void PWMFaultIntUnregister(uint32_t ui32Base);
extern void PWMGenIntTrigEnable(uint32_t ui32Base, uint32_t ui32Gen,
uint32_t ui32IntTrig);
extern void PWMGenIntTrigDisable(uint32_t ui32Base, uint32_t ui32Gen,
uint32_t ui32IntTrig);
extern uint32_t PWMGenIntStatus(uint32_t ui32Base, uint32_t ui32Gen,
bool bMasked);
extern void PWMGenIntClear(uint32_t ui32Base, uint32_t ui32Gen,
uint32_t ui32Ints);
extern void PWMIntEnable(uint32_t ui32Base, uint32_t ui32GenFault);
extern void PWMIntDisable(uint32_t ui32Base, uint32_t ui32GenFault);
extern void PWMFaultIntClear(uint32_t ui32Base);
extern uint32_t PWMIntStatus(uint32_t ui32Base, bool bMasked);
extern void PWMFaultIntClearExt(uint32_t ui32Base,
uint32_t ui32FaultInts);
extern void PWMGenFaultConfigure(uint32_t ui32Base, uint32_t ui32Gen,
uint32_t ui32MinFaultPeriod,
uint32_t ui32FaultSenses);
extern void PWMGenFaultTriggerSet(uint32_t ui32Base, uint32_t ui32Gen,
uint32_t ui32Group,
uint32_t ui32FaultTriggers);
extern uint32_t PWMGenFaultTriggerGet(uint32_t ui32Base,
uint32_t ui32Gen,
uint32_t ui32Group);
extern uint32_t PWMGenFaultStatus(uint32_t ui32Base,
uint32_t ui32Gen,
uint32_t ui32Group);
extern void PWMGenFaultClear(uint32_t ui32Base, uint32_t ui32Gen,
uint32_t ui32Group,
uint32_t ui32FaultTriggers);
extern void PWMClockSet(uint32_t ui32Base, uint32_t ui32Config);
extern uint32_t PWMClockGet(uint32_t ui32Base);
extern void PWMOutputUpdateMode(uint32_t ui32Base,
uint32_t ui32PWMOutBits,
uint32_t ui32Mode);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_PWM_H__

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//*****************************************************************************
//
// qei.h - Prototypes for the Quadrature Encoder Driver.
//
// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __DRIVERLIB_QEI_H__
#define __DRIVERLIB_QEI_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to QEIConfigure as the ui32Config paramater.
//
//*****************************************************************************
#define QEI_CONFIG_CAPTURE_A 0x00000000 // Count on ChA edges only
#define QEI_CONFIG_CAPTURE_A_B 0x00000008 // Count on ChA and ChB edges
#define QEI_CONFIG_NO_RESET 0x00000000 // Do not reset on index pulse
#define QEI_CONFIG_RESET_IDX 0x00000010 // Reset position on index pulse
#define QEI_CONFIG_QUADRATURE 0x00000000 // ChA and ChB are quadrature
#define QEI_CONFIG_CLOCK_DIR 0x00000004 // ChA and ChB are clock and dir
#define QEI_CONFIG_NO_SWAP 0x00000000 // Do not swap ChA and ChB
#define QEI_CONFIG_SWAP 0x00000002 // Swap ChA and ChB
//*****************************************************************************
//
// Values that can be passed to QEIFilterConfigure as the ui32PreDiv
// parameter.
//
//*****************************************************************************
#define QEI_FILTCNT_2 0x00000000 // Filter Count of 2 System Clocks
#define QEI_FILTCNT_3 0x00010000 // Filter Count of 3 System Clocks
#define QEI_FILTCNT_4 0x00020000 // Filter Count of 4 System Clocks
#define QEI_FILTCNT_5 0x00030000 // Filter Count of 5 System Clocks
#define QEI_FILTCNT_6 0x00040000 // Filter Count of 6 System Clocks
#define QEI_FILTCNT_7 0x00050000 // Filter Count of 7 System Clocks
#define QEI_FILTCNT_8 0x00060000 // Filter Count of 8 System Clocks
#define QEI_FILTCNT_9 0x00070000 // Filter Count of 9 System Clocks
#define QEI_FILTCNT_10 0x00080000 // Filter Count of 10 System Clocks
#define QEI_FILTCNT_11 0x00090000 // Filter Count of 11 System Clocks
#define QEI_FILTCNT_12 0x000A0000 // Filter Count of 12 System Clocks
#define QEI_FILTCNT_13 0x000B0000 // Filter Count of 13 System Clocks
#define QEI_FILTCNT_14 0x000C0000 // Filter Count of 14 System Clocks
#define QEI_FILTCNT_15 0x000D0000 // Filter Count of 15 System Clocks
#define QEI_FILTCNT_16 0x000E0000 // Filter Count of 16 System Clocks
#define QEI_FILTCNT_17 0x000F0000 // Filter Count of 17 System Clocks
//*****************************************************************************
//
// Values that can be passed to QEIVelocityConfigure as the ui32PreDiv
// parameter.
//
//*****************************************************************************
#define QEI_VELDIV_1 0x00000000 // Predivide by 1
#define QEI_VELDIV_2 0x00000040 // Predivide by 2
#define QEI_VELDIV_4 0x00000080 // Predivide by 4
#define QEI_VELDIV_8 0x000000C0 // Predivide by 8
#define QEI_VELDIV_16 0x00000100 // Predivide by 16
#define QEI_VELDIV_32 0x00000140 // Predivide by 32
#define QEI_VELDIV_64 0x00000180 // Predivide by 64
#define QEI_VELDIV_128 0x000001C0 // Predivide by 128
//*****************************************************************************
//
// Values that can be passed to QEIEnableInts, QEIDisableInts, and QEIClearInts
// as the ui32IntFlags parameter, and returned by QEIGetIntStatus.
//
//*****************************************************************************
#define QEI_INTERROR 0x00000008 // Phase error detected
#define QEI_INTDIR 0x00000004 // Direction change
#define QEI_INTTIMER 0x00000002 // Velocity timer expired
#define QEI_INTINDEX 0x00000001 // Index pulse detected
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void QEIEnable(uint32_t ui32Base);
extern void QEIDisable(uint32_t ui32Base);
extern void QEIConfigure(uint32_t ui32Base, uint32_t ui32Config,
uint32_t ui32MaxPosition);
extern uint32_t QEIPositionGet(uint32_t ui32Base);
extern void QEIPositionSet(uint32_t ui32Base, uint32_t ui32Position);
extern int32_t QEIDirectionGet(uint32_t ui32Base);
extern bool QEIErrorGet(uint32_t ui32Base);
extern void QEIFilterEnable(uint32_t ui32Base);
extern void QEIFilterDisable(uint32_t ui32Base);
extern void QEIFilterConfigure(uint32_t ui32Base, uint32_t ui32FiltCnt);
extern void QEIVelocityEnable(uint32_t ui32Base);
extern void QEIVelocityDisable(uint32_t ui32Base);
extern void QEIVelocityConfigure(uint32_t ui32Base, uint32_t ui32PreDiv,
uint32_t ui32Period);
extern uint32_t QEIVelocityGet(uint32_t ui32Base);
extern void QEIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void));
extern void QEIIntUnregister(uint32_t ui32Base);
extern void QEIIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void QEIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
extern uint32_t QEIIntStatus(uint32_t ui32Base, bool bMasked);
extern void QEIIntClear(uint32_t ui32Base, uint32_t ui32IntFlags);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_QEI_H__

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//*****************************************************************************
//
// rtos_bindings.h - Macros intended to aid porting of TivaWare modules
// for use with an RTOS.
//
// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __DRIVERLIB_RTOS_BINDINGS_H__
#define __DRIVERLIB_RTOS_BINDINGS_H__
#ifdef USE_RTOS
//*****************************************************************************
//
// If an RTOS is in use, implement a header file called "tiva_rtos.h"
// which contains RTOS-specific versions of each of the macros defined below
// and make sure it appears on the include path set when you build your
// project.
//
// Note that there is no default implementation of this header file included
// in TivaWare - it is your responsibility to create it specifically for
// your RTOS.
//
//*****************************************************************************
#include "tiva_rtos.h"
#else
//*****************************************************************************
//
// When no RTOS is in use, the follow macros compile to either nothing or a
// minimal implementation that works in a bare-metal environment.
//
// Each of these macros must be redefined in tiva_rtos.h if you are using
// TivaWare under an RTOS.
//
//*****************************************************************************
//*****************************************************************************
//
// A simple macro used to yield within polling loops. In the default, non-RTOS
// implementation, this compiles to nothing.
//
//*****************************************************************************
#define OS_YIELD()
//*****************************************************************************
//
// A simple macro around the SysCtlDelay function. The parameter is the number
// of 3 cycle loops to wait before returning (as for SysCtlDelay). In an RTOS
// implementation, this could be replaced with an OS delay call with
// appropriate parameter scaling.
//
//*****************************************************************************
#define OS_DELAY(ul3Cycles) MAP_SysCtlDelay(ul3Cycles)
//*****************************************************************************
//
// Wrappers around low level interrupt control functions. For information
// on each of these functions, please see the appropriate API documentation
// for the DriverLib Interrupt driver.
//
// The macros defined here represent interrupt-control functions that may be
// called from within TivaWare code. It is expected that application
// code will use RTOS-specific functions to control interrupt priority, to
// pend interrupts and to perform runtime vector manipulation. As a result,
// no macros are defined to wrap any of these functions from interrupt.c.
//
//*****************************************************************************
#define OS_INT_MASTER_ENABLE() MAP_IntMasterEnable()
#define OS_INT_MASTER_DISABLE() MAP_IntMasterDisable()
#define OS_INT_DISABLE(ui32IntID) MAP_IntDisable(ui32IntID)
#define OS_INT_ENABLE(ui32IntID) MAP_IntEnable(ui32IntID)
#endif // USE_RTOS
#endif // __DRIVERLIB_RTOS_BINDINGS_H__

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//*****************************************************************************
//
// shamd5.h - Defines and Macros for the SHA/MD5.
//
// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __DRIVERLIB_SHAMD5_H__
#define __DRIVERLIB_SHAMD5_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following defines are used to specify the algorithm in use in the
// SHA/MD5 module.
//
//*****************************************************************************
#define SHAMD5_ALGO_MD5 0x00000018
#define SHAMD5_ALGO_SHA1 0x0000001a
#define SHAMD5_ALGO_SHA224 0x0000001c
#define SHAMD5_ALGO_SHA256 0x0000001e
#define SHAMD5_ALGO_HMAC_MD5 0x00000000
#define SHAMD5_ALGO_HMAC_SHA1 0x00000002
#define SHAMD5_ALGO_HMAC_SHA224 0x00000004
#define SHAMD5_ALGO_HMAC_SHA256 0x00000006
//*****************************************************************************
//
// The following defines are used to represent the different interrupt sources
// in SHAMD5IntEnable(), SHAMD5IntDisable(), SHAMD5GetIntStatus(), and
// SHAMD5BlockOnIntStatus() functions.
//
//*****************************************************************************
#define SHAMD5_INT_CONTEXT_READY \
0x00000008
#define SHAMD5_INT_PARTHASH_READY \
0x00000004
#define SHAMD5_INT_INPUT_READY 0x00000002
#define SHAMD5_INT_OUTPUT_READY 0x00000001
#define SHAMD5_INT_DMA_CONTEXT_IN \
0x00080000
#define SHAMD5_INT_DMA_DATA_IN 0x00020000
#define SHAMD5_INT_DMA_CONTEXT_OUT \
0x00010000
//*****************************************************************************
//
// Function prototypes
//
//*****************************************************************************
extern void SHAMD5ConfigSet(uint32_t ui32Base, uint32_t ui32Mode);
extern void SHAMD5DataProcess(uint32_t ui32Base, uint32_t *pui32DataSrc,
uint32_t ui32DataLength,
uint32_t *pui32HashResult);
extern void SHAMD5DataWrite(uint32_t ui32Base, uint32_t *pui32Src);
extern bool SHAMD5DataWriteNonBlocking(uint32_t ui32Base, uint32_t *pui32Src);
extern void SHAMD5DMADisable(uint32_t ui32Base);
extern void SHAMD5DMAEnable(uint32_t ui32Base);
extern void SHAMD5HashLengthSet(uint32_t ui32Base, uint32_t ui32Length);
extern void SHAMD5HMACKeySet(uint32_t ui32Base, uint32_t *pui32Src);
extern void SHAMD5HMACPPKeyGenerate(uint32_t ui32Base, uint32_t *pui32Key,
uint32_t *pui32PPKey);
extern void SHAMD5HMACPPKeySet(uint32_t ui32Base, uint32_t *pui32Src);
extern void SHAMD5HMACProcess(uint32_t ui32Base, uint32_t *pui32DataSrc,
uint32_t ui32DataLength,
uint32_t *pui32HashResult);
extern void SHAMD5IntClear(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void SHAMD5IntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void SHAMD5IntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void SHAMD5IntRegister(uint32_t ui32Base, void (*pfnHandler)(void));
extern uint32_t SHAMD5IntStatus(uint32_t ui32Base, bool bMasked);
extern void SHAMD5IntUnregister(uint32_t ui32Base);
extern void SHAMD5Reset(uint32_t ui32Base);
extern void SHAMD5ResultRead(uint32_t ui32Base, uint32_t *pui32Dest);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_SHAMD5_H__

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//*****************************************************************************
//
// ssi.h - Prototypes for the Synchronous Serial Interface Driver.
//
// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __DRIVERLIB_SSI_H__
#define __DRIVERLIB_SSI_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear
// as the ui32IntFlags parameter, and returned by SSIIntStatus.
//
//*****************************************************************************
#define SSI_TXEOT 0x00000040 // Transmit FIFO is empty
#define SSI_DMATX 0x00000020 // DMA Transmit complete
#define SSI_DMARX 0x00000010 // DMA Receive complete
#define SSI_TXFF 0x00000008 // TX FIFO half full or less
#define SSI_RXFF 0x00000004 // RX FIFO half full or more
#define SSI_RXTO 0x00000002 // RX timeout
#define SSI_RXOR 0x00000001 // RX overrun
//*****************************************************************************
//
// Values that can be passed to SSIConfigSetExpClk.
//
//*****************************************************************************
#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0
#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1
#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0
#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1
#define SSI_FRF_TI 0x00000010 // TI frame format
#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format
#define SSI_MODE_MASTER 0x00000000 // SSI master
#define SSI_MODE_SLAVE 0x00000001 // SSI slave
#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled
//*****************************************************************************
//
// Values that can be passed to SSIDMAEnable() and SSIDMADisable().
//
//*****************************************************************************
#define SSI_DMA_TX 0x00000002 // Enable DMA for transmit
#define SSI_DMA_RX 0x00000001 // Enable DMA for receive
//*****************************************************************************
//
// Values that can be passed to SSIClockSourceSet() or returned from
// SSIClockSourceGet().
//
//*****************************************************************************
#define SSI_CLOCK_SYSTEM 0x00000000
#define SSI_CLOCK_PIOSC 0x00000005
//*****************************************************************************
//
// Values that can be passed to SSIAdvModeSet().
//
//*****************************************************************************
#define SSI_ADV_MODE_LEGACY 0x00000000
#define SSI_ADV_MODE_READ_WRITE 0x000001c0
#define SSI_ADV_MODE_WRITE 0x000000c0
#define SSI_ADV_MODE_BI_READ 0x00000140
#define SSI_ADV_MODE_BI_WRITE 0x00000040
#define SSI_ADV_MODE_QUAD_READ 0x00000180
#define SSI_ADV_MODE_QUAD_WRITE 0x00000080
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void SSIConfigSetExpClk(uint32_t ui32Base, uint32_t ui32SSIClk,
uint32_t ui32Protocol, uint32_t ui32Mode,
uint32_t ui32BitRate,
uint32_t ui32DataWidth);
extern void SSIDataGet(uint32_t ui32Base, uint32_t *pui32Data);
extern int32_t SSIDataGetNonBlocking(uint32_t ui32Base,
uint32_t *pui32Data);
extern void SSIDataPut(uint32_t ui32Base, uint32_t ui32Data);
extern int32_t SSIDataPutNonBlocking(uint32_t ui32Base, uint32_t ui32Data);
extern void SSIDisable(uint32_t ui32Base);
extern void SSIEnable(uint32_t ui32Base);
extern void SSIIntClear(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void SSIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void SSIIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void SSIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void));
extern uint32_t SSIIntStatus(uint32_t ui32Base, bool bMasked);
extern void SSIIntUnregister(uint32_t ui32Base);
extern void SSIDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags);
extern void SSIDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags);
extern bool SSIBusy(uint32_t ui32Base);
extern void SSIClockSourceSet(uint32_t ui32Base, uint32_t ui32Source);
extern uint32_t SSIClockSourceGet(uint32_t ui32Base);
extern void SSIAdvModeSet(uint32_t ui32Base, uint32_t ui32Mode);
extern void SSIAdvDataPutFrameEnd(uint32_t ui32Base, uint32_t ui32Data);
extern int32_t SSIAdvDataPutFrameEndNonBlocking(uint32_t ui32Base,
uint32_t ui32Data);
extern void SSIAdvFrameHoldEnable(uint32_t ui32Base);
extern void SSIAdvFrameHoldDisable(uint32_t ui32Base);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_SSI_H__

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//*****************************************************************************
//
// sw_crc.h - Prototypes for the software CRC functions.
//
// Copyright (c) 2010-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __DRIVERLIB_SW_CRC_H__
#define __DRIVERLIB_SW_CRC_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Prototypes for the functions.
//
//*****************************************************************************
extern uint8_t Crc8CCITT(uint8_t ui8Crc, const uint8_t *pui8Data,
uint32_t ui32Count);
extern uint16_t Crc16(uint16_t ui16Crc, const uint8_t *pui8Data,
uint32_t ui32Count);
extern uint16_t Crc16Array(uint32_t ui32WordLen, const uint32_t *pui32Data);
extern void Crc16Array3(uint32_t ui32WordLen, const uint32_t *pui32Data,
uint16_t *pui16Crc3);
extern uint32_t Crc32(uint32_t ui32Crc, const uint8_t *pui8Data,
uint32_t ui32Count);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_SW_CRC_H__

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//*****************************************************************************
//
// sysctl.h - Prototypes for the system control driver.
//
// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __DRIVERLIB_SYSCTL_H__
#define __DRIVERLIB_SYSCTL_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following are values that can be passed to the
// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(),
// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the
// ui32Peripheral parameter. The peripherals in the fourth group (upper nibble
// is 3) can only be used with the SysCtlPeripheralPresent() API.
//
//*****************************************************************************
#define SYSCTL_PERIPH_ADC0 0xf0003800 // ADC 0
#define SYSCTL_PERIPH_ADC1 0xf0003801 // ADC 1
#define SYSCTL_PERIPH_CAN0 0xf0003400 // CAN 0
#define SYSCTL_PERIPH_CAN1 0xf0003401 // CAN 1
#define SYSCTL_PERIPH_COMP0 0xf0003c00 // Analog Comparator Module 0
#define SYSCTL_PERIPH_EMAC0 0xf0009c00 // Ethernet MAC0
#define SYSCTL_PERIPH_EPHY0 0xf0003000 // Ethernet PHY0
#define SYSCTL_PERIPH_EPI0 0xf0001000 // EPI0
#define SYSCTL_PERIPH_GPIOA 0xf0000800 // GPIO A
#define SYSCTL_PERIPH_GPIOB 0xf0000801 // GPIO B
#define SYSCTL_PERIPH_GPIOC 0xf0000802 // GPIO C
#define SYSCTL_PERIPH_GPIOD 0xf0000803 // GPIO D
#define SYSCTL_PERIPH_GPIOE 0xf0000804 // GPIO E
#define SYSCTL_PERIPH_GPIOF 0xf0000805 // GPIO F
#define SYSCTL_PERIPH_GPIOG 0xf0000806 // GPIO G
#define SYSCTL_PERIPH_GPIOH 0xf0000807 // GPIO H
#define SYSCTL_PERIPH_GPIOJ 0xf0000808 // GPIO J
#define SYSCTL_PERIPH_HIBERNATE 0xf0001400 // Hibernation module
#define SYSCTL_PERIPH_CCM0 0xf0007400 // CCM 0
#define SYSCTL_PERIPH_EEPROM0 0xf0005800 // EEPROM 0
#define SYSCTL_PERIPH_FAN0 0xf0005400 // FAN 0
#define SYSCTL_PERIPH_FAN1 0xf0005401 // FAN 1
#define SYSCTL_PERIPH_GPIOK 0xf0000809 // GPIO K
#define SYSCTL_PERIPH_GPIOL 0xf000080a // GPIO L
#define SYSCTL_PERIPH_GPIOM 0xf000080b // GPIO M
#define SYSCTL_PERIPH_GPION 0xf000080c // GPIO N
#define SYSCTL_PERIPH_GPIOP 0xf000080d // GPIO P
#define SYSCTL_PERIPH_GPIOQ 0xf000080e // GPIO Q
#define SYSCTL_PERIPH_GPIOR 0xf000080f // GPIO R
#define SYSCTL_PERIPH_GPIOS 0xf0000810 // GPIO S
#define SYSCTL_PERIPH_GPIOT 0xf0000811 // GPIO T
#define SYSCTL_PERIPH_I2C0 0xf0002000 // I2C 0
#define SYSCTL_PERIPH_I2C1 0xf0002001 // I2C 1
#define SYSCTL_PERIPH_I2C2 0xf0002002 // I2C 2
#define SYSCTL_PERIPH_I2C3 0xf0002003 // I2C 3
#define SYSCTL_PERIPH_I2C4 0xf0002004 // I2C 4
#define SYSCTL_PERIPH_I2C5 0xf0002005 // I2C 5
#define SYSCTL_PERIPH_I2C6 0xf0002006 // I2C 6
#define SYSCTL_PERIPH_I2C7 0xf0002007 // I2C 7
#define SYSCTL_PERIPH_I2C8 0xf0002008 // I2C 8
#define SYSCTL_PERIPH_I2C9 0xf0002009 // I2C 9
#define SYSCTL_PERIPH_LCD0 0xf0009000 // LCD 0
#define SYSCTL_PERIPH_ONEWIRE0 0xf0009800 // One Wire 0
#define SYSCTL_PERIPH_PWM0 0xf0004000 // PWM 0
#define SYSCTL_PERIPH_PWM1 0xf0004001 // PWM 1
#define SYSCTL_PERIPH_QEI0 0xf0004400 // QEI 0
#define SYSCTL_PERIPH_QEI1 0xf0004401 // QEI 1
#define SYSCTL_PERIPH_SSI0 0xf0001c00 // SSI 0
#define SYSCTL_PERIPH_SSI1 0xf0001c01 // SSI 1
#define SYSCTL_PERIPH_SSI2 0xf0001c02 // SSI 2
#define SYSCTL_PERIPH_SSI3 0xf0001c03 // SSI 3
#define SYSCTL_PERIPH_TIMER0 0xf0000400 // Timer 0
#define SYSCTL_PERIPH_TIMER1 0xf0000401 // Timer 1
#define SYSCTL_PERIPH_TIMER2 0xf0000402 // Timer 2
#define SYSCTL_PERIPH_TIMER3 0xf0000403 // Timer 3
#define SYSCTL_PERIPH_TIMER4 0xf0000404 // Timer 4
#define SYSCTL_PERIPH_TIMER5 0xf0000405 // Timer 5
#define SYSCTL_PERIPH_TIMER6 0xf0000406 // Timer 6
#define SYSCTL_PERIPH_TIMER7 0xf0000407 // Timer 7
#define SYSCTL_PERIPH_UART0 0xf0001800 // UART 0
#define SYSCTL_PERIPH_UART1 0xf0001801 // UART 1
#define SYSCTL_PERIPH_UART2 0xf0001802 // UART 2
#define SYSCTL_PERIPH_UART3 0xf0001803 // UART 3
#define SYSCTL_PERIPH_UART4 0xf0001804 // UART 4
#define SYSCTL_PERIPH_UART5 0xf0001805 // UART 5
#define SYSCTL_PERIPH_UART6 0xf0001806 // UART 6
#define SYSCTL_PERIPH_UART7 0xf0001807 // UART 7
#define SYSCTL_PERIPH_UDMA 0xf0000c00 // uDMA
#define SYSCTL_PERIPH_USB0 0xf0002800 // USB 0
#define SYSCTL_PERIPH_WDOG0 0xf0000000 // Watchdog 0
#define SYSCTL_PERIPH_WDOG1 0xf0000001 // Watchdog 1
#define SYSCTL_PERIPH_WTIMER0 0xf0005c00 // Wide Timer 0
#define SYSCTL_PERIPH_WTIMER1 0xf0005c01 // Wide Timer 1
#define SYSCTL_PERIPH_WTIMER2 0xf0005c02 // Wide Timer 2
#define SYSCTL_PERIPH_WTIMER3 0xf0005c03 // Wide Timer 3
#define SYSCTL_PERIPH_WTIMER4 0xf0005c04 // Wide Timer 4
#define SYSCTL_PERIPH_WTIMER5 0xf0005c05 // Wide Timer 5
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlLDOSleepSet() and
// SysCtlLDODeepSleepSet() APIs as the ui32Voltage value, or returned by the
// SysCtlLDOSleepGet() and SysCtlLDODeepSleepGet() APIs.
//
//*****************************************************************************
#define SYSCTL_LDO_0_90V 0x80000012 // LDO output of 0.90V
#define SYSCTL_LDO_0_95V 0x80000013 // LDO output of 0.95V
#define SYSCTL_LDO_1_00V 0x80000014 // LDO output of 1.00V
#define SYSCTL_LDO_1_05V 0x80000015 // LDO output of 1.05V
#define SYSCTL_LDO_1_10V 0x80000016 // LDO output of 1.10V
#define SYSCTL_LDO_1_15V 0x80000017 // LDO output of 1.15V
#define SYSCTL_LDO_1_20V 0x80000018 // LDO output of 1.20V
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlIntEnable(),
// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask
// by the SysCtlIntStatus() API.
//
//*****************************************************************************
#define SYSCTL_INT_BOR0 0x00000800 // VDD under BOR0
#define SYSCTL_INT_VDDA_OK 0x00000400 // VDDA Power OK
#define SYSCTL_INT_MOSC_PUP 0x00000100 // MOSC power-up interrupt
#define SYSCTL_INT_USBPLL_LOCK 0x00000080 // USB PLL lock interrupt
#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt
#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int
#define SYSCTL_INT_BOR1 0x00000002 // VDD under BOR1
#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlResetCauseClear()
// API or returned by the SysCtlResetCauseGet() API.
//
//*****************************************************************************
#define SYSCTL_CAUSE_HSRVREQ 0x00001000 // Hardware System Service Request
#define SYSCTL_CAUSE_HIB 0x00000040 // Hibernate reset
#define SYSCTL_CAUSE_WDOG1 0x00000020 // Watchdog 1 reset
#define SYSCTL_CAUSE_SW 0x00000010 // Software reset
#define SYSCTL_CAUSE_WDOG0 0x00000008 // Watchdog 0 reset
#ifndef DEPRECATED
#define SYSCTL_CAUSE_WDOG SYSCTL_CAUSE_WDOG0
// Watchdog reset(Deprecated)
#endif
#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset
#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset
#define SYSCTL_CAUSE_EXT 0x00000001 // External reset
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlBrownOutConfigSet()
// API as the ui32Config parameter.
//
//*****************************************************************************
#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting
#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlPWMClockSet() API
// as the ui32Config parameter, and can be returned by the SysCtlPWMClockGet()
// API.
//
//*****************************************************************************
#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1
#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2
#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4
#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8
#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16
#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32
#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlClockSet() API as
// the ui32Config parameter.
//
//*****************************************************************************
#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1
#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2
#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3
#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4
#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5
#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6
#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7
#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8
#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9
#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10
#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11
#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12
#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13
#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14
#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15
#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16
#define SYSCTL_SYSDIV_17 0x88400000 // Processor clock is osc/pll /17
#define SYSCTL_SYSDIV_18 0x88C00000 // Processor clock is osc/pll /18
#define SYSCTL_SYSDIV_19 0x89400000 // Processor clock is osc/pll /19
#define SYSCTL_SYSDIV_20 0x89C00000 // Processor clock is osc/pll /20
#define SYSCTL_SYSDIV_21 0x8A400000 // Processor clock is osc/pll /21
#define SYSCTL_SYSDIV_22 0x8AC00000 // Processor clock is osc/pll /22
#define SYSCTL_SYSDIV_23 0x8B400000 // Processor clock is osc/pll /23
#define SYSCTL_SYSDIV_24 0x8BC00000 // Processor clock is osc/pll /24
#define SYSCTL_SYSDIV_25 0x8C400000 // Processor clock is osc/pll /25
#define SYSCTL_SYSDIV_26 0x8CC00000 // Processor clock is osc/pll /26
#define SYSCTL_SYSDIV_27 0x8D400000 // Processor clock is osc/pll /27
#define SYSCTL_SYSDIV_28 0x8DC00000 // Processor clock is osc/pll /28
#define SYSCTL_SYSDIV_29 0x8E400000 // Processor clock is osc/pll /29
#define SYSCTL_SYSDIV_30 0x8EC00000 // Processor clock is osc/pll /30
#define SYSCTL_SYSDIV_31 0x8F400000 // Processor clock is osc/pll /31
#define SYSCTL_SYSDIV_32 0x8FC00000 // Processor clock is osc/pll /32
#define SYSCTL_SYSDIV_33 0x90400000 // Processor clock is osc/pll /33
#define SYSCTL_SYSDIV_34 0x90C00000 // Processor clock is osc/pll /34
#define SYSCTL_SYSDIV_35 0x91400000 // Processor clock is osc/pll /35
#define SYSCTL_SYSDIV_36 0x91C00000 // Processor clock is osc/pll /36
#define SYSCTL_SYSDIV_37 0x92400000 // Processor clock is osc/pll /37
#define SYSCTL_SYSDIV_38 0x92C00000 // Processor clock is osc/pll /38
#define SYSCTL_SYSDIV_39 0x93400000 // Processor clock is osc/pll /39
#define SYSCTL_SYSDIV_40 0x93C00000 // Processor clock is osc/pll /40
#define SYSCTL_SYSDIV_41 0x94400000 // Processor clock is osc/pll /41
#define SYSCTL_SYSDIV_42 0x94C00000 // Processor clock is osc/pll /42
#define SYSCTL_SYSDIV_43 0x95400000 // Processor clock is osc/pll /43
#define SYSCTL_SYSDIV_44 0x95C00000 // Processor clock is osc/pll /44
#define SYSCTL_SYSDIV_45 0x96400000 // Processor clock is osc/pll /45
#define SYSCTL_SYSDIV_46 0x96C00000 // Processor clock is osc/pll /46
#define SYSCTL_SYSDIV_47 0x97400000 // Processor clock is osc/pll /47
#define SYSCTL_SYSDIV_48 0x97C00000 // Processor clock is osc/pll /48
#define SYSCTL_SYSDIV_49 0x98400000 // Processor clock is osc/pll /49
#define SYSCTL_SYSDIV_50 0x98C00000 // Processor clock is osc/pll /50
#define SYSCTL_SYSDIV_51 0x99400000 // Processor clock is osc/pll /51
#define SYSCTL_SYSDIV_52 0x99C00000 // Processor clock is osc/pll /52
#define SYSCTL_SYSDIV_53 0x9A400000 // Processor clock is osc/pll /53
#define SYSCTL_SYSDIV_54 0x9AC00000 // Processor clock is osc/pll /54
#define SYSCTL_SYSDIV_55 0x9B400000 // Processor clock is osc/pll /55
#define SYSCTL_SYSDIV_56 0x9BC00000 // Processor clock is osc/pll /56
#define SYSCTL_SYSDIV_57 0x9C400000 // Processor clock is osc/pll /57
#define SYSCTL_SYSDIV_58 0x9CC00000 // Processor clock is osc/pll /58
#define SYSCTL_SYSDIV_59 0x9D400000 // Processor clock is osc/pll /59
#define SYSCTL_SYSDIV_60 0x9DC00000 // Processor clock is osc/pll /60
#define SYSCTL_SYSDIV_61 0x9E400000 // Processor clock is osc/pll /61
#define SYSCTL_SYSDIV_62 0x9EC00000 // Processor clock is osc/pll /62
#define SYSCTL_SYSDIV_63 0x9F400000 // Processor clock is osc/pll /63
#define SYSCTL_SYSDIV_64 0x9FC00000 // Processor clock is osc/pll /64
#define SYSCTL_SYSDIV_2_5 0xC1000000 // Processor clock is pll / 2.5
#define SYSCTL_SYSDIV_3_5 0xC1800000 // Processor clock is pll / 3.5
#define SYSCTL_SYSDIV_4_5 0xC2000000 // Processor clock is pll / 4.5
#define SYSCTL_SYSDIV_5_5 0xC2800000 // Processor clock is pll / 5.5
#define SYSCTL_SYSDIV_6_5 0xC3000000 // Processor clock is pll / 6.5
#define SYSCTL_SYSDIV_7_5 0xC3800000 // Processor clock is pll / 7.5
#define SYSCTL_SYSDIV_8_5 0xC4000000 // Processor clock is pll / 8.5
#define SYSCTL_SYSDIV_9_5 0xC4800000 // Processor clock is pll / 9.5
#define SYSCTL_SYSDIV_10_5 0xC5000000 // Processor clock is pll / 10.5
#define SYSCTL_SYSDIV_11_5 0xC5800000 // Processor clock is pll / 11.5
#define SYSCTL_SYSDIV_12_5 0xC6000000 // Processor clock is pll / 12.5
#define SYSCTL_SYSDIV_13_5 0xC6800000 // Processor clock is pll / 13.5
#define SYSCTL_SYSDIV_14_5 0xC7000000 // Processor clock is pll / 14.5
#define SYSCTL_SYSDIV_15_5 0xC7800000 // Processor clock is pll / 15.5
#define SYSCTL_SYSDIV_16_5 0xC8000000 // Processor clock is pll / 16.5
#define SYSCTL_SYSDIV_17_5 0xC8800000 // Processor clock is pll / 17.5
#define SYSCTL_SYSDIV_18_5 0xC9000000 // Processor clock is pll / 18.5
#define SYSCTL_SYSDIV_19_5 0xC9800000 // Processor clock is pll / 19.5
#define SYSCTL_SYSDIV_20_5 0xCA000000 // Processor clock is pll / 20.5
#define SYSCTL_SYSDIV_21_5 0xCA800000 // Processor clock is pll / 21.5
#define SYSCTL_SYSDIV_22_5 0xCB000000 // Processor clock is pll / 22.5
#define SYSCTL_SYSDIV_23_5 0xCB800000 // Processor clock is pll / 23.5
#define SYSCTL_SYSDIV_24_5 0xCC000000 // Processor clock is pll / 24.5
#define SYSCTL_SYSDIV_25_5 0xCC800000 // Processor clock is pll / 25.5
#define SYSCTL_SYSDIV_26_5 0xCD000000 // Processor clock is pll / 26.5
#define SYSCTL_SYSDIV_27_5 0xCD800000 // Processor clock is pll / 27.5
#define SYSCTL_SYSDIV_28_5 0xCE000000 // Processor clock is pll / 28.5
#define SYSCTL_SYSDIV_29_5 0xCE800000 // Processor clock is pll / 29.5
#define SYSCTL_SYSDIV_30_5 0xCF000000 // Processor clock is pll / 30.5
#define SYSCTL_SYSDIV_31_5 0xCF800000 // Processor clock is pll / 31.5
#define SYSCTL_SYSDIV_32_5 0xD0000000 // Processor clock is pll / 32.5
#define SYSCTL_SYSDIV_33_5 0xD0800000 // Processor clock is pll / 33.5
#define SYSCTL_SYSDIV_34_5 0xD1000000 // Processor clock is pll / 34.5
#define SYSCTL_SYSDIV_35_5 0xD1800000 // Processor clock is pll / 35.5
#define SYSCTL_SYSDIV_36_5 0xD2000000 // Processor clock is pll / 36.5
#define SYSCTL_SYSDIV_37_5 0xD2800000 // Processor clock is pll / 37.5
#define SYSCTL_SYSDIV_38_5 0xD3000000 // Processor clock is pll / 38.5
#define SYSCTL_SYSDIV_39_5 0xD3800000 // Processor clock is pll / 39.5
#define SYSCTL_SYSDIV_40_5 0xD4000000 // Processor clock is pll / 40.5
#define SYSCTL_SYSDIV_41_5 0xD4800000 // Processor clock is pll / 41.5
#define SYSCTL_SYSDIV_42_5 0xD5000000 // Processor clock is pll / 42.5
#define SYSCTL_SYSDIV_43_5 0xD5800000 // Processor clock is pll / 43.5
#define SYSCTL_SYSDIV_44_5 0xD6000000 // Processor clock is pll / 44.5
#define SYSCTL_SYSDIV_45_5 0xD6800000 // Processor clock is pll / 45.5
#define SYSCTL_SYSDIV_46_5 0xD7000000 // Processor clock is pll / 46.5
#define SYSCTL_SYSDIV_47_5 0xD7800000 // Processor clock is pll / 47.5
#define SYSCTL_SYSDIV_48_5 0xD8000000 // Processor clock is pll / 48.5
#define SYSCTL_SYSDIV_49_5 0xD8800000 // Processor clock is pll / 49.5
#define SYSCTL_SYSDIV_50_5 0xD9000000 // Processor clock is pll / 50.5
#define SYSCTL_SYSDIV_51_5 0xD9800000 // Processor clock is pll / 51.5
#define SYSCTL_SYSDIV_52_5 0xDA000000 // Processor clock is pll / 52.5
#define SYSCTL_SYSDIV_53_5 0xDA800000 // Processor clock is pll / 53.5
#define SYSCTL_SYSDIV_54_5 0xDB000000 // Processor clock is pll / 54.5
#define SYSCTL_SYSDIV_55_5 0xDB800000 // Processor clock is pll / 55.5
#define SYSCTL_SYSDIV_56_5 0xDC000000 // Processor clock is pll / 56.5
#define SYSCTL_SYSDIV_57_5 0xDC800000 // Processor clock is pll / 57.5
#define SYSCTL_SYSDIV_58_5 0xDD000000 // Processor clock is pll / 58.5
#define SYSCTL_SYSDIV_59_5 0xDD800000 // Processor clock is pll / 59.5
#define SYSCTL_SYSDIV_60_5 0xDE000000 // Processor clock is pll / 60.5
#define SYSCTL_SYSDIV_61_5 0xDE800000 // Processor clock is pll / 61.5
#define SYSCTL_SYSDIV_62_5 0xDF000000 // Processor clock is pll / 62.5
#define SYSCTL_SYSDIV_63_5 0xDF800000 // Processor clock is pll / 63.5
#define SYSCTL_CFG_VCO_480 0xF1000000 // VCO is 480 MHz
#define SYSCTL_CFG_VCO_320 0xF0000000 // VCO is 320 MHz
#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock
#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock
#define SYSCTL_XTAL_1MHZ 0x00000000 // External crystal is 1MHz
#define SYSCTL_XTAL_1_84MHZ 0x00000040 // External crystal is 1.8432MHz
#define SYSCTL_XTAL_2MHZ 0x00000080 // External crystal is 2MHz
#define SYSCTL_XTAL_2_45MHZ 0x000000C0 // External crystal is 2.4576MHz
#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz
#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz
#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz
#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz
#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz
#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz
#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz
#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz
#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz
#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz
#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz
#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz
#define SYSCTL_XTAL_10MHZ 0x00000400 // External crystal is 10 MHz
#define SYSCTL_XTAL_12MHZ 0x00000440 // External crystal is 12 MHz
#define SYSCTL_XTAL_12_2MHZ 0x00000480 // External crystal is 12.288 MHz
#define SYSCTL_XTAL_13_5MHZ 0x000004C0 // External crystal is 13.56 MHz
#define SYSCTL_XTAL_14_3MHZ 0x00000500 // External crystal is 14.31818 MHz
#define SYSCTL_XTAL_16MHZ 0x00000540 // External crystal is 16 MHz
#define SYSCTL_XTAL_16_3MHZ 0x00000580 // External crystal is 16.384 MHz
#define SYSCTL_XTAL_18MHZ 0x000005C0 // External crystal is 18.0 MHz
#define SYSCTL_XTAL_20MHZ 0x00000600 // External crystal is 20.0 MHz
#define SYSCTL_XTAL_24MHZ 0x00000640 // External crystal is 24.0 MHz
#define SYSCTL_XTAL_25MHZ 0x00000680 // External crystal is 25.0 MHz
#define SYSCTL_OSC_MAIN 0x00000000 // Osc source is main osc
#define SYSCTL_OSC_INT 0x00000010 // Osc source is int. osc
#define SYSCTL_OSC_INT4 0x00000020 // Osc source is int. osc /4
#define SYSCTL_OSC_INT30 0x00000030 // Osc source is int. 30 KHz
#define SYSCTL_OSC_EXT32 0x80000038 // Osc source is ext. 32 KHz
#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator
#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlDeepSleepClockSet()
// API as the ui32Config parameter.
//
//*****************************************************************************
#define SYSCTL_DSLP_DIV_1 0x00000000 // Deep-sleep clock is osc /1
#define SYSCTL_DSLP_DIV_2 0x00800000 // Deep-sleep clock is osc /2
#define SYSCTL_DSLP_DIV_3 0x01000000 // Deep-sleep clock is osc /3
#define SYSCTL_DSLP_DIV_4 0x01800000 // Deep-sleep clock is osc /4
#define SYSCTL_DSLP_DIV_5 0x02000000 // Deep-sleep clock is osc /5
#define SYSCTL_DSLP_DIV_6 0x02800000 // Deep-sleep clock is osc /6
#define SYSCTL_DSLP_DIV_7 0x03000000 // Deep-sleep clock is osc /7
#define SYSCTL_DSLP_DIV_8 0x03800000 // Deep-sleep clock is osc /8
#define SYSCTL_DSLP_DIV_9 0x04000000 // Deep-sleep clock is osc /9
#define SYSCTL_DSLP_DIV_10 0x04800000 // Deep-sleep clock is osc /10
#define SYSCTL_DSLP_DIV_11 0x05000000 // Deep-sleep clock is osc /11
#define SYSCTL_DSLP_DIV_12 0x05800000 // Deep-sleep clock is osc /12
#define SYSCTL_DSLP_DIV_13 0x06000000 // Deep-sleep clock is osc /13
#define SYSCTL_DSLP_DIV_14 0x06800000 // Deep-sleep clock is osc /14
#define SYSCTL_DSLP_DIV_15 0x07000000 // Deep-sleep clock is osc /15
#define SYSCTL_DSLP_DIV_16 0x07800000 // Deep-sleep clock is osc /16
#define SYSCTL_DSLP_DIV_17 0x08000000 // Deep-sleep clock is osc /17
#define SYSCTL_DSLP_DIV_18 0x08800000 // Deep-sleep clock is osc /18
#define SYSCTL_DSLP_DIV_19 0x09000000 // Deep-sleep clock is osc /19
#define SYSCTL_DSLP_DIV_20 0x09800000 // Deep-sleep clock is osc /20
#define SYSCTL_DSLP_DIV_21 0x0A000000 // Deep-sleep clock is osc /21
#define SYSCTL_DSLP_DIV_22 0x0A800000 // Deep-sleep clock is osc /22
#define SYSCTL_DSLP_DIV_23 0x0B000000 // Deep-sleep clock is osc /23
#define SYSCTL_DSLP_DIV_24 0x0B800000 // Deep-sleep clock is osc /24
#define SYSCTL_DSLP_DIV_25 0x0C000000 // Deep-sleep clock is osc /25
#define SYSCTL_DSLP_DIV_26 0x0C800000 // Deep-sleep clock is osc /26
#define SYSCTL_DSLP_DIV_27 0x0D000000 // Deep-sleep clock is osc /27
#define SYSCTL_DSLP_DIV_28 0x0D800000 // Deep-sleep clock is osc /28
#define SYSCTL_DSLP_DIV_29 0x0E000000 // Deep-sleep clock is osc /29
#define SYSCTL_DSLP_DIV_30 0x0E800000 // Deep-sleep clock is osc /30
#define SYSCTL_DSLP_DIV_31 0x0F000000 // Deep-sleep clock is osc /31
#define SYSCTL_DSLP_DIV_32 0x0F800000 // Deep-sleep clock is osc /32
#define SYSCTL_DSLP_DIV_33 0x10000000 // Deep-sleep clock is osc /33
#define SYSCTL_DSLP_DIV_34 0x10800000 // Deep-sleep clock is osc /34
#define SYSCTL_DSLP_DIV_35 0x11000000 // Deep-sleep clock is osc /35
#define SYSCTL_DSLP_DIV_36 0x11800000 // Deep-sleep clock is osc /36
#define SYSCTL_DSLP_DIV_37 0x12000000 // Deep-sleep clock is osc /37
#define SYSCTL_DSLP_DIV_38 0x12800000 // Deep-sleep clock is osc /38
#define SYSCTL_DSLP_DIV_39 0x13000000 // Deep-sleep clock is osc /39
#define SYSCTL_DSLP_DIV_40 0x13800000 // Deep-sleep clock is osc /40
#define SYSCTL_DSLP_DIV_41 0x14000000 // Deep-sleep clock is osc /41
#define SYSCTL_DSLP_DIV_42 0x14800000 // Deep-sleep clock is osc /42
#define SYSCTL_DSLP_DIV_43 0x15000000 // Deep-sleep clock is osc /43
#define SYSCTL_DSLP_DIV_44 0x15800000 // Deep-sleep clock is osc /44
#define SYSCTL_DSLP_DIV_45 0x16000000 // Deep-sleep clock is osc /45
#define SYSCTL_DSLP_DIV_46 0x16800000 // Deep-sleep clock is osc /46
#define SYSCTL_DSLP_DIV_47 0x17000000 // Deep-sleep clock is osc /47
#define SYSCTL_DSLP_DIV_48 0x17800000 // Deep-sleep clock is osc /48
#define SYSCTL_DSLP_DIV_49 0x18000000 // Deep-sleep clock is osc /49
#define SYSCTL_DSLP_DIV_50 0x18800000 // Deep-sleep clock is osc /50
#define SYSCTL_DSLP_DIV_51 0x19000000 // Deep-sleep clock is osc /51
#define SYSCTL_DSLP_DIV_52 0x19800000 // Deep-sleep clock is osc /52
#define SYSCTL_DSLP_DIV_53 0x1A000000 // Deep-sleep clock is osc /53
#define SYSCTL_DSLP_DIV_54 0x1A800000 // Deep-sleep clock is osc /54
#define SYSCTL_DSLP_DIV_55 0x1B000000 // Deep-sleep clock is osc /55
#define SYSCTL_DSLP_DIV_56 0x1B800000 // Deep-sleep clock is osc /56
#define SYSCTL_DSLP_DIV_57 0x1C000000 // Deep-sleep clock is osc /57
#define SYSCTL_DSLP_DIV_58 0x1C800000 // Deep-sleep clock is osc /58
#define SYSCTL_DSLP_DIV_59 0x1D000000 // Deep-sleep clock is osc /59
#define SYSCTL_DSLP_DIV_60 0x1D800000 // Deep-sleep clock is osc /60
#define SYSCTL_DSLP_DIV_61 0x1E000000 // Deep-sleep clock is osc /61
#define SYSCTL_DSLP_DIV_62 0x1E800000 // Deep-sleep clock is osc /62
#define SYSCTL_DSLP_DIV_63 0x1F000000 // Deep-sleep clock is osc /63
#define SYSCTL_DSLP_DIV_64 0x1F800000 // Deep-sleep clock is osc /64
#define SYSCTL_DSLP_OSC_MAIN 0x00000000 // Osc source is main osc
#define SYSCTL_DSLP_OSC_INT 0x00000010 // Osc source is int. osc
#define SYSCTL_DSLP_OSC_INT30 0x00000030 // Osc source is int. 30 KHz
#define SYSCTL_DSLP_OSC_EXT32 0x00000070 // Osc source is ext. 32 KHz
#define SYSCTL_DSLP_PIOSC_PD 0x00000002 // Power down PIOSC in deep-sleep
#define SYSCTL_DSLP_MOSC_PD 0x40000000 // Power down MOSC in deep-sleep
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlPIOSCCalibrate()
// API as the ui32Type parameter.
//
//*****************************************************************************
#define SYSCTL_PIOSC_CAL_AUTO 0x00000200 // Automatic calibration
#define SYSCTL_PIOSC_CAL_FACT 0x00000100 // Factory calibration
#define SYSCTL_PIOSC_CAL_USER 0x80000100 // User-supplied calibration
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlMOSCConfigSet() API
// as the ui32Config parameter.
//
//*****************************************************************************
#define SYSCTL_MOSC_VALIDATE 0x00000001 // Enable MOSC validation
#define SYSCTL_MOSC_INTERRUPT 0x00000002 // Generate interrupt on MOSC fail
#define SYSCTL_MOSC_NO_XTAL 0x00000004 // No crystal is attached to MOSC
#define SYSCTL_MOSC_PWR_DIS 0x00000008 // Power down the MOSC.
#define SYSCTL_MOSC_LOWFREQ 0x00000000 // MOSC is less than 10MHz
#define SYSCTL_MOSC_HIGHFREQ 0x00000010 // MOSC is greater than 10MHz
#define SYSCTL_MOSC_SESRC 0x00000020 // Singled ended oscillator source.
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlSleepPowerSet() and
// SysCtlDeepSleepPowerSet() APIs as the ui32Config parameter.
//
//*****************************************************************************
#define SYSCTL_LDO_SLEEP 0x00000200 // LDO in sleep mode
// (Deep Sleep Only)
#define SYSCTL_TEMP_LOW_POWER 0x00000100 // Temp sensor in low power mode
// (Deep Sleep Only)
#define SYSCTL_FLASH_NORMAL 0x00000000 // Flash in normal mode
#define SYSCTL_FLASH_LOW_POWER 0x00000020 // Flash in low power mode
#define SYSCTL_SRAM_NORMAL 0x00000000 // SRAM in normal mode
#define SYSCTL_SRAM_STANDBY 0x00000001 // SRAM in standby mode
#define SYSCTL_SRAM_LOW_POWER 0x00000003 // SRAM in low power mode
//*****************************************************************************
//
// Defines for the SysCtlResetBehaviorSet() and SysCtlResetBehaviorGet() APIs.
//
//*****************************************************************************
#define SYSCTL_ONRST_WDOG0_POR 0x00000030
#define SYSCTL_ONRST_WDOG0_SYS 0x00000020
#define SYSCTL_ONRST_WDOG1_POR 0x000000C0
#define SYSCTL_ONRST_WDOG1_SYS 0x00000080
#define SYSCTL_ONRST_BOR_POR 0x0000000C
#define SYSCTL_ONRST_BOR_SYS 0x00000008
#define SYSCTL_ONRST_EXT_POR 0x00000003
#define SYSCTL_ONRST_EXT_SYS 0x00000002
//*****************************************************************************
//
// Values used with the SysCtlVoltageEventConfig() API.
//
//*****************************************************************************
#define SYSCTL_VEVENT_VDDABO_NONE \
0x00000000
#define SYSCTL_VEVENT_VDDABO_INT \
0x00000100
#define SYSCTL_VEVENT_VDDABO_NMI \
0x00000200
#define SYSCTL_VEVENT_VDDABO_RST \
0x00000300
#define SYSCTL_VEVENT_VDDBO_NONE \
0x00000000
#define SYSCTL_VEVENT_VDDBO_INT 0x00000001
#define SYSCTL_VEVENT_VDDBO_NMI 0x00000002
#define SYSCTL_VEVENT_VDDBO_RST 0x00000003
//*****************************************************************************
//
// Values used with the SysCtlVoltageEventStatus() and
// SysCtlVoltageEventClear() APIs.
//
//*****************************************************************************
#define SYSCTL_VESTAT_VDDBOR 0x00000040
#define SYSCTL_VESTAT_VDDABOR 0x00000010
//*****************************************************************************
//
// Values used with the SysCtlNMIStatus() API.
//
//*****************************************************************************
#define SYSCTL_NMI_MOSCFAIL 0x00010000
#define SYSCTL_NMI_TAMPER 0x00000200
#define SYSCTL_NMI_WDT1 0x00000020
#define SYSCTL_NMI_WDT0 0x00000008
#define SYSCTL_NMI_POWER 0x00000004
#define SYSCTL_NMI_EXTERNAL 0x00000001
//*****************************************************************************
//
// The defines for the SysCtlClockOutConfig() API.
//
//*****************************************************************************
#define SYSCTL_CLKOUT_EN 0x80000000
#define SYSCTL_CLKOUT_DIS 0x00000000
#define SYSCTL_CLKOUT_SYSCLK 0x00000000
#define SYSCTL_CLKOUT_PIOSC 0x00010000
#define SYSCTL_CLKOUT_MOSC 0x00020000
//*****************************************************************************
//
// The following defines are used with the SysCtlAltClkConfig() function.
//
//*****************************************************************************
#define SYSCTL_ALTCLK_PIOSC 0x00000000
#define SYSCTL_ALTCLK_RTCOSC 0x00000003
#define SYSCTL_ALTCLK_LFIOSC 0x00000004
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern uint32_t SysCtlSRAMSizeGet(void);
extern uint32_t SysCtlFlashSizeGet(void);
extern uint32_t SysCtlFlashSectorSizeGet(void);
extern bool SysCtlPeripheralPresent(uint32_t ui32Peripheral);
extern bool SysCtlPeripheralReady(uint32_t ui32Peripheral);
extern void SysCtlPeripheralPowerOn(uint32_t ui32Peripheral);
extern void SysCtlPeripheralPowerOff(uint32_t ui32Peripheral);
extern void SysCtlPeripheralReset(uint32_t ui32Peripheral);
extern void SysCtlPeripheralEnable(uint32_t ui32Peripheral);
extern void SysCtlPeripheralDisable(uint32_t ui32Peripheral);
extern void SysCtlPeripheralSleepEnable(uint32_t ui32Peripheral);
extern void SysCtlPeripheralSleepDisable(uint32_t ui32Peripheral);
extern void SysCtlPeripheralDeepSleepEnable(uint32_t ui32Peripheral);
extern void SysCtlPeripheralDeepSleepDisable(uint32_t ui32Peripheral);
extern void SysCtlPeripheralClockGating(bool bEnable);
extern void SysCtlIntRegister(void (*pfnHandler)(void));
extern void SysCtlIntUnregister(void);
extern void SysCtlIntEnable(uint32_t ui32Ints);
extern void SysCtlIntDisable(uint32_t ui32Ints);
extern void SysCtlIntClear(uint32_t ui32Ints);
extern uint32_t SysCtlIntStatus(bool bMasked);
extern void SysCtlLDOSleepSet(uint32_t ui32Voltage);
extern uint32_t SysCtlLDOSleepGet(void);
extern void SysCtlLDODeepSleepSet(uint32_t ui32Voltage);
extern uint32_t SysCtlLDODeepSleepGet(void);
extern void SysCtlSleepPowerSet(uint32_t ui32Config);
extern void SysCtlDeepSleepPowerSet(uint32_t ui32Config);
extern void SysCtlReset(void);
extern void SysCtlSleep(void);
extern void SysCtlDeepSleep(void);
extern uint32_t SysCtlResetCauseGet(void);
extern void SysCtlResetCauseClear(uint32_t ui32Causes);
extern void SysCtlBrownOutConfigSet(uint32_t ui32Config,
uint32_t ui32Delay);
extern void SysCtlDelay(uint32_t ui32Count);
extern void SysCtlMOSCConfigSet(uint32_t ui32Config);
extern uint32_t SysCtlPIOSCCalibrate(uint32_t ui32Type);
extern void SysCtlClockSet(uint32_t ui32Config);
extern uint32_t SysCtlClockGet(void);
extern void SysCtlDeepSleepClockSet(uint32_t ui32Config);
extern void SysCtlDeepSleepClockConfigSet(uint32_t ui32Div,
uint32_t ui32Config);
extern void SysCtlPWMClockSet(uint32_t ui32Config);
extern uint32_t SysCtlPWMClockGet(void);
extern void SysCtlIOSCVerificationSet(bool bEnable);
extern void SysCtlMOSCVerificationSet(bool bEnable);
extern void SysCtlPLLVerificationSet(bool bEnable);
extern void SysCtlClkVerificationClear(void);
extern void SysCtlGPIOAHBEnable(uint32_t ui32GPIOPeripheral);
extern void SysCtlGPIOAHBDisable(uint32_t ui32GPIOPeripheral);
extern void SysCtlUSBPLLEnable(void);
extern void SysCtlUSBPLLDisable(void);
extern uint32_t SysCtlClockFreqSet(uint32_t ui32Config,
uint32_t ui32SysClock);
extern void SysCtlResetBehaviorSet(uint32_t ui32Behavior);
extern uint32_t SysCtlResetBehaviorGet(void);
extern void SysCtlClockOutConfig(uint32_t ui32Config, uint32_t ui32Div);
extern void SysCtlAltClkConfig(uint32_t ui32Config);
extern uint32_t SysCtlNMIStatus(void);
extern void SysCtlNMIClear(uint32_t ui32Status);
extern void SysCtlVoltageEventConfig(uint32_t ui32Config);
extern uint32_t SysCtlVoltageEventStatus(void);
extern void SysCtlVoltageEventClear(uint32_t ui32Status);
extern bool SysCtlVCOGet(uint32_t ui32Crystal, uint32_t *pui32VCOFrequency);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_SYSCTL_H__

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