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添加cpu复位函数 

RT_WEAK void rt_hw_cpu_reset(void)
This commit is contained in:
yufanyufan77 2018-12-14 08:58:40 +08:00
parent dcf7bce2cc
commit b40a8f816b
1 changed files with 19 additions and 0 deletions
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19
libcpu/arm/cortex-m0/cpuport.c
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@ -114,3 +114,22 @@ void rt_hw_hard_fault_exception(struct exception_stack_frame *contex)
while (1); while (1);
} }
#define SCB_CFSR (*(volatile const unsigned *)0xE000ED28) /* Configurable Fault Status Register */
#define SCB_HFSR (*(volatile const unsigned *)0xE000ED2C) /* HardFault Status Register */
#define SCB_MMAR (*(volatile const unsigned *)0xE000ED34) /* MemManage Fault Address register */
#define SCB_BFAR (*(volatile const unsigned *)0xE000ED38) /* Bus Fault Address Register */
#define SCB_AIRCR (*(volatile unsigned long *)0xE000ED00) /* Reset control Address Register */
#define SCB_RESET_VALUE 0x05FA0004 /* Reset value, write to SCB_AIRCR can reset cpu */
#define SCB_CFSR_MFSR (*(volatile const unsigned char*)0xE000ED28) /* Memory-management Fault Status Register */
#define SCB_CFSR_BFSR (*(volatile const unsigned char*)0xE000ED29) /* Bus Fault Status Register */
#define SCB_CFSR_UFSR (*(volatile const unsigned short*)0xE000ED2A) /* Usage Fault Status Register */
/**
* reset CPU
*/
RT_WEAK void rt_hw_cpu_reset(void)
{
SCB_AIRCR = SCB_RESET_VALUE;//((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |SCB_AIRCR_SYSRESETREQ_Msk);
}