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add GNU GCC support in LPC2478. 

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1333 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
bernard.xiong 2011-03-17 09:14:38 +00:00
parent 24dfbe437d
commit b5fbd46776
14 changed files with 516 additions and 382 deletions
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9
bsp/lpc2478/SConscript
View File

@ -3,15 +3,8 @@ Import('RTT_ROOT')
from building import * from building import *
src_bsp = ['application.c', 'startup.c', 'board.c'] src_bsp = ['application.c', 'startup.c', 'board.c']
src_drv = []
if GetDepend('RT_USING_DFS'): src = File(src_bsp)
src_drv += ['sd.c', 'spi.c']
if GetDepend('RT_USING_LWIP'):
src_drv += ['emac.c']
src = File(src_bsp + src_drv)
CPPPATH = [RTT_ROOT + '/bsp/lpc2478'] CPPPATH = [RTT_ROOT + '/bsp/lpc2478']
group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH) group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH)

11
bsp/lpc2478/SConstruct
View File

@ -6,7 +6,7 @@ RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
from building import * from building import *
TARGET = 'rtthread-lpc2478.' + rtconfig.TARGET_EXT TARGET = 'rtthread-lpc.' + rtconfig.TARGET_EXT
env = Environment(tools = ['mingw'], env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
@ -21,15 +21,6 @@ Export('rtconfig')
# prepare building environment # prepare building environment
objs = PrepareBuilding(env, RTT_ROOT) objs = PrepareBuilding(env, RTT_ROOT)
if GetDepend('RT_USING_WEBSERVER'):
objs = objs + SConscript(RTT_ROOT + '/components/net/webserver/SConscript', variant_dir='build/net/webserver', duplicate=0)
if GetDepend('RT_USING_RTGUI'):
objs = objs + SConscript(RTT_ROOT + '/examples/gui/SConscript', variant_dir='build/examples/gui', duplicate=0)
# libc testsuite
# objs = objs + SConscript(RTT_ROOT + '/examples/libc/SConscript', variant_dir='build/examples/libc', duplicate=0)
# build program # build program
env.Program(TARGET, objs) env.Program(TARGET, objs)

46
bsp/lpc2478/application.c
View File

@ -18,54 +18,8 @@
* @addtogroup LPC2478 * @addtogroup LPC2478
*/ */
/*@{*/ /*@{*/
char thread1_stack[512];
char thread2_stack[512];
struct rt_thread thread1;
struct rt_thread thread2;
void thread1_entry(void* parameter)
{
int i;
while (1)
{
for (i = 0; i < 10; i ++)
{
rt_kprintf("%d\n", i);
rt_thread_delay(100);
}
}
}
void thread2_entry(void* parameter)
{
int count = 0;
while (1)
{
rt_kprintf("Thread2 count:%d\n", count++);
rt_thread_delay(50);
}
}
int rt_application_init() int rt_application_init()
{ {
rt_thread_init(&thread1,
"thread1",
thread1_entry, RT_NULL,
&thread1_stack[0], sizeof(thread1_stack),
20, 10);
rt_thread_init(&thread2,
"thread2",
thread2_entry, RT_NULL,
&thread2_stack[0], sizeof(thread2_stack),
25, 8);
rt_thread_startup(&thread1);
rt_thread_startup(&thread2);
return 0; return 0;
} }

61
bsp/lpc2478/board.c
View File

@ -18,10 +18,10 @@
#include <LPC24xx.h> #include <LPC24xx.h>
#include "board.h" #include "board.h"
/* #define RT_BOARD_DEBUG */
#define DATA_COUNT 14400000/RT_TICK_PER_SECOND /* T0MR0 = delayInMs * (Fpclk / 1000); */ #define DATA_COUNT 14400000/RT_TICK_PER_SECOND /* T0MR0 = delayInMs * (Fpclk / 1000); */
extern void rt_hw_serial_init(void);
/** /**
* @addtogroup LPC2478 * @addtogroup LPC2478
*/ */
@ -29,69 +29,20 @@
void rt_timer_handler(int vector) void rt_timer_handler(int vector)
{ {
#ifdef BOARD_DEBUG
rt_kprintf("timer handler, increase a tick\n");
#endif
T0IR |= 0x01; /* clear interrupt flag */ T0IR |= 0x01; /* clear interrupt flag */
rt_tick_increase(); rt_tick_increase();
VICVectAddr = 0; /* Acknowledge Interrupt */ VICVectAddr = 0; /* Acknowledge Interrupt */
} }
/**
* This function is used to display a string on console, normally, it's
* invoked by rt_kprintf
*
* @param str the displayed string
*/
void rt_hw_console_output(const char* str)
{
while (*str)
{
if (*str=='\n')
{
while (!(U0LSR & 0x20));
U0THR = '\r';
}
while (!(U0LSR & 0x20));
U0THR = *str;
str ++;
}
}
#define BAUD_RATE 115200
#define U0PINS 0x50
void rt_hw_console_init()
{
rt_uint32_t fdiv;
/* Enable RxD and TxD pins */
PINSEL0 = U0PINS;
/* 8 bits, no Parity, 1 Stop bit */
U0LCR = 0x83;
/* Setup Baudrate */
fdiv = ( PCLK / 16 ) / BAUD_RATE ; /*baud rate */
U0DLM = fdiv / 256;
U0DLL = fdiv % 256;
U0FCR = 0x00; /* Enable and reset TX and RX FIFO. */
U0LCR = 0x03; /* DLAB = 0 */
/* DLAB = 0 */
U0LCR = 0x03;
}
/** /**
* This function will init LPC2478 board * This function will init LPC2478 board
*/ */
void rt_hw_board_init() void rt_hw_board_init()
{ {
/* init console for rt_kprintf function */ #if defined(RT_USING_DEVICE) && defined(RT_USING_UART1)
rt_hw_console_init(); rt_hw_serial_init();
rt_console_set_device("uart1");
#endif
T0IR = 0xff; T0IR = 0xff;
T0TC = 0; T0TC = 0;

0
bsp/lpc2478/lowlevel.S
View File

167
bsp/lpc2478/lpc2478_rom.lds
View File

@ -1,25 +1,29 @@
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") /*
OUTPUT_ARCH(arm) * linker script for LPC2478 with GNU ld
* bernard.xiong 2011-03-17
*/
/* Program Entry, set to mark it as "used" and avoid gc */
MEMORY
{
CODE (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000
DATA (rw) : ORIGIN = 0x40000000, LENGTH = 0x00010000
}
ENTRY(_start) ENTRY(_start)
SECTIONS SECTIONS
{ {
. = 0x00000000;
__text_start = .;
.text : .text :
{ {
*(.vectors) *(.init)
*(.text) *(.text)
*(.text.*) *(.text.*) /* remaining code */
} =0 *(.rodata) /* read-only data (constants) */
*(.rodata*)
*(.glue_7)
*(.glue_7t)
*(.gnu.linkonce.t*)
__text_end = .;
__rodata_start = .;
.rodata :
{
*(.rodata)
*(.rodata.*)
/* section information for finsh shell */ /* section information for finsh shell */
. = ALIGN(4); . = ALIGN(4);
__fsymtab_start = .; __fsymtab_start = .;
@ -30,67 +34,79 @@ SECTIONS
KEEP(*(VSymTab)) KEEP(*(VSymTab))
__vsymtab_end = .; __vsymtab_end = .;
. = ALIGN(4); . = ALIGN(4);
}
__rodata_end = .;
. = 0x40000000; /*Data in SRAM*/
__data_start = .;
. = ALIGN(4); . = ALIGN(4);
.data : _etext = .;
} > CODE = 0
. = ALIGN(4);
.ctors :
{ {
PROVIDE(__ctors_start__ = .);
KEEP(*(SORT(.ctors.*)))
KEEP(*(.ctors))
PROVIDE(__ctors_end__ = .);
} > CODE
.dtors :
{
PROVIDE(__dtors_start__ = .);
KEEP(*(SORT(.dtors.*)))
KEEP(*(.dtors))
PROVIDE(__dtors_end__ = .);
} > CODE
/* .ARM.exidx is sorted, so has to go in its own output section. */
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
/* This is used by the startup in order to initialize the .data secion */
_sidata = .;
} > CODE
__exidx_end = .;
/* .data section which is used for initialized data */
.data : AT (_sidata)
{
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_sdata = . ;
*(.data) *(.data)
*(.data.*) *(.data.*)
} *(.gnu.linkonce.d*)
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_edata = . ;
} >DATA
__data_end = .; __data_end = .;
. = ALIGN(4); .noinit :
__bss_start = __data_end; {
*(.bss.noinit)
} > DATA
__bss_start = .;
.bss : .bss :
{ {
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .;
*(.bss) *(.bss)
*(.bss.*)
*(COMMON) *(COMMON)
. = ALIGN(4); . = ALIGN(4);
} /* This is used by the startup in order to initialize the .bss secion */
. = ALIGN(4); _ebss = . ;
_estack = .;
} > DATA
__bss_end = .; __bss_end = .;
. = ALIGN(4); _end = .;
__UndStack_start = __bss_end;
.UndStack : { *(.UndStack) }
__UndStack_end = ( __UndStack_start + 0x00000100 );
. = ALIGN(4);
__IRQStack_start = __UndStack_end;
.IRQStack : { *(.IRQStack) }
__IRQStack_end = ( __IRQStack_start + 0x00000400 );
. = ALIGN(4);
__FIQStack_start = __IRQStack_end;
.FIQStack : { *(.FIQStack) }
__FIQStack_end = ( __FIQStack_start + 0x00000400 );
. = ALIGN(4);
__SVCStack_start = __FIQStack_end;
.SVCStack : { *(.SVCStack) }
__SVCStack_end = ( __SVCStack_start + 0x00000400 );
. = ALIGN(4);
__ABTStack_start = __SVCStack_end;
.ABTStack : { *(.ABTStack) }
__ABTStack_end = ( __ABTStack_start + 0x00000400 );
. = ALIGN(4);
__USRStack_start = __ABTStack_end;
.USRStack : { *(.USRStack) }
__USRStack_end = ( __USRStack_start + 0x00000400 );
. = ALIGN(4);
__Heap_start = __USRStack_end;
.Heap : { *(.Heap) }
__Heap_end = (__Heap_start + 0x00004000);
/* Stabs debugging sections. */ /* Stabs debugging sections. */
.stab 0 : { *(.stab) } .stab 0 : { *(.stab) }
@ -100,6 +116,29 @@ SECTIONS
.stab.index 0 : { *(.stab.index) } .stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) } .stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) } .comment 0 : { *(.comment) }
/* DWARF debug sections.
_end = .; * Symbols in the DWARF debugging sections are relative to the beginning
* of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
} }

143
bsp/lpc2478/project.Uv2 Normal file
View File

@ -0,0 +1,143 @@
### uVision2 Project, (C) Keil Software
### Do not modify !
Target (RT-Thread LPC2478), 0x0004 // Tools: 'ARM-ADS'
Group (Startup)
Group (Kernel)
Group (LPC24XX)
Group (finsh)
File 1,1,<.\application.c><application.c>
File 1,1,<.\startup.c><startup.c>
File 1,1,<.\board.c><board.c>
File 2,1,<..\..\src\clock.c><clock.c>
File 2,1,<..\..\src\device.c><device.c>
File 2,1,<..\..\src\idle.c><idle.c>
File 2,1,<..\..\src\ipc.c><ipc.c>
File 2,1,<..\..\src\irq.c><irq.c>
File 2,1,<..\..\src\kservice.c><kservice.c>
File 2,1,<..\..\src\mem.c><mem.c>
File 2,1,<..\..\src\mempool.c><mempool.c>
File 2,1,<..\..\src\module.c><module.c>
File 2,1,<..\..\src\object.c><object.c>
File 2,1,<..\..\src\rtm.c><rtm.c>
File 2,1,<..\..\src\scheduler.c><scheduler.c>
File 2,1,<..\..\src\slab.c><slab.c>
File 2,1,<..\..\src\thread.c><thread.c>
File 2,1,<..\..\src\timer.c><timer.c>
File 3,1,<..\..\libcpu\arm\lpc24xx\cpu.c><cpu.c>
File 3,1,<..\..\libcpu\arm\lpc24xx\interrupt.c><interrupt.c>
File 3,1,<..\..\libcpu\arm\lpc24xx\serial.c><serial.c>
File 3,1,<..\..\libcpu\arm\lpc24xx\stack.c><stack.c>
File 3,1,<..\..\libcpu\arm\lpc24xx\trap.c><trap.c>
File 3,2,<..\..\libcpu\arm\lpc24xx\context_rvds.S><context_rvds.S>
File 3,2,<..\..\libcpu\arm\lpc24xx\start_rvds.S><start_rvds.S>
File 3,1,<..\..\libcpu\arm\common\backtrace.c><backtrace.c>
File 3,1,<..\..\libcpu\arm\common\div0.c><div0.c>
File 3,1,<..\..\libcpu\arm\common\showmem.c><showmem.c>
File 4,1,<..\..\components\finsh\cmd.c><cmd.c>
File 4,1,<..\..\components\finsh\finsh_compiler.c><finsh_compiler.c>
File 4,1,<..\..\components\finsh\finsh_error.c><finsh_error.c>
File 4,1,<..\..\components\finsh\finsh_heap.c><finsh_heap.c>
File 4,1,<..\..\components\finsh\finsh_init.c><finsh_init.c>
File 4,1,<..\..\components\finsh\finsh_node.c><finsh_node.c>
File 4,1,<..\..\components\finsh\finsh_ops.c><finsh_ops.c>
File 4,1,<..\..\components\finsh\finsh_parser.c><finsh_parser.c>
File 4,1,<..\..\components\finsh\finsh_token.c><finsh_token.c>
File 4,1,<..\..\components\finsh\finsh_var.c><finsh_var.c>
File 4,1,<..\..\components\finsh\finsh_vm.c><finsh_vm.c>
File 4,1,<..\..\components\finsh\shell.c><shell.c>
File 4,1,<..\..\components\finsh\symbol.c><symbol.c>
Options 1,0,0 // Target 'RT-Thread LPC2478'
Device (LPC2478)
Vendor (NXP (founded by Philips))
Cpu (IRAM(0x40000000-0x4000FFFF) IRAM2(0x7FE00000-0x7FE03FFF) IROM(0-0x7FFFF) CLOCK(12000000) CPUTYPE(ARM7TDMI))
FlashUt (LPC210x_ISP.EXE ("#H" ^X $D COM1: 38400 1))
StupF ("STARTUP\Philips\LPC2400.s" ("Philips LPC2400 Startup Code"))
FlashDR (UL2ARM(-U268761108 -O7 -S0 -C0 -FO15 -FD40000000 -FC800 -FN1 -FF0LPC_IAP2_512 -FS00 -FL07E000))
DevID (4307)
Rgf (LPC23xx.H)
Mem ()
C ()
A ()
RL ()
OH ()
DBC_IFX ()
DBC_CMS ()
DBC_AMS ()
DBC_LMS ()
UseEnv=0
EnvBin ()
EnvInc ()
EnvLib ()
EnvReg (Philips\)
OrgReg (Philips\)
TgStat=16
OutDir (.\obj\)
OutName (rtthread-lpc)
GenApp=1
GenLib=0
GenHex=0
Debug=1
Browse=1
LstDir (.\obj\)
HexSel=1
MG32K=0
TGMORE=0
RunUsr 0 0 <>
RunUsr 1 0 <>
BrunUsr 0 0 <>
BrunUsr 1 0 <>
CrunUsr 0 0 <>
CrunUsr 1 0 <>
SVCSID <>
GLFLAGS=1790
ADSFLGA { 243,31,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
ACPUTYP (ARM7TDMI)
RVDEV ()
ADSTFLGA { 0,12,16,2,99,0,0,66,0,0,0,0,0,0,0,0,0,0,0,0 }
OCMADSOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
OCMADSIRAM { 0,0,0,0,64,0,0,1,0 }
OCMADSIROM { 1,0,0,0,0,0,0,8,0 }
OCMADSXRAM { 0,0,0,0,0,0,0,0,0 }
OCR_RVCT { 1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,8,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,64,0,0,1,0,0,0,0,224,127,0,64,0,0 }
RV_STAVEC ()
ADSCCFLG { 5,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
ADSCMISC ()
ADSCDEFN ()
ADSCUDEF ()
ADSCINCD (..\..\include;..\..\libcpu\arm\common;..\..\components\finsh;..\..\libcpu\arm\lpc24xx;.)
ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
ADSAMISC ()
ADSADEFN ()
ADSAUDEF ()
ADSAINCD ()
PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
IncBld=1
AlwaysBuild=0
GenAsm=0
AsmAsm=0
PublicsOnly=0
StopCode=3
CustArgs ()
LibMods ()
ADSLDFG { 17,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
ADSLDTA (0x00000000)
ADSLDDA (0x10000000)
ADSLDSC ()
ADSLDIB ()
ADSLDIC ()
ADSLDMC ( --keep __fsym_* --keep __vsym_*)
ADSLDIF ()
ADSLDDW ()
OPTDL (SARM.DLL)(-cLPC24xx)(DARMP.DLL)(-pLPC2478)(SARM.DLL)()(TARMP.DLL)(-pLPC2478)
OPTDBG 48125,7,()()()()()()()()()() (Segger\JL2CM3.dll)()()()
FLASH1 { 9,0,0,0,1,0,0,0,0,16,0,0,0,0,0,0,0,0,0,0 }
FLASH2 (BIN\UL2ARM.DLL)
FLASH3 ("LPC210x_ISP.EXE" ("#H" ^X $D COM1: 38400 1))
FLASH4 ()
EndOpt

9
bsp/lpc2478/rtconfig.h
View File

@ -67,6 +67,7 @@
#define RT_UART_RX_BUFFER_SIZE 64 #define RT_UART_RX_BUFFER_SIZE 64
/* SECTION: Console options */ /* SECTION: Console options */
#define RT_USING_CONSOLE
/* the buffer size of console*/ /* the buffer size of console*/
#define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLEBUF_SIZE 128
@ -77,14 +78,6 @@
#define FINSH_USING_SYMTAB #define FINSH_USING_SYMTAB
#define FINSH_USING_DESCRIPTION #define FINSH_USING_DESCRIPTION
/* SECTION: a mini libc */
/* Using mini libc library*/
/* #define RT_USING_MINILIBC */
/* SECTION: C++ support */
/* Using C++ support*/
/* #define RT_USING_CPLUSPLUS */
/* SECTION: lwip, a lighwight TCP/IP protocol stack */ /* SECTION: lwip, a lighwight TCP/IP protocol stack */
/* Using lighweight TCP/IP protocol stack*/ /* Using lighweight TCP/IP protocol stack*/
/* #define RT_USING_LWIP */ /* #define RT_USING_LWIP */

5
bsp/lpc2478/rtconfig.py
View File

@ -12,11 +12,6 @@ elif CROSS_TOOL == 'keil':
BUILD = 'debug' BUILD = 'debug'
if PLATFORM == 'gcc': if PLATFORM == 'gcc':
print "========================="
print "Can not support GNU GCC!!"
print "========================="
exit (0)
# toolchains # toolchains
PREFIX = 'arm-none-eabi-' PREFIX = 'arm-none-eabi-'
CC = PREFIX + 'gcc' CC = PREFIX + 'gcc'

12
bsp/lpc2478/startup.c
View File

@ -74,13 +74,6 @@ void rtthread_startup(void)
/* init scheduler system */ /* init scheduler system */
rt_system_scheduler_init(); rt_system_scheduler_init();
#ifdef RT_USING_DEVICE
/* init hardware serial device */
rt_hw_serial_init();
/*init all registed devices*/
rt_device_init_all();
#endif
/* init application */ /* init application */
rt_application_init(); rt_application_init();
@ -106,6 +99,11 @@ void rtthread_startup(void)
#ifdef __CC_ARM #ifdef __CC_ARM
int main(void) int main(void)
{ {
rt_uint32_t UNUSED level;
/* disable interrupt first */
level = rt_hw_interrupt_disable();
/* invoke rtthread_startup */ /* invoke rtthread_startup */
rtthread_startup(); rtthread_startup();

2
libcpu/arm/lpc24xx/interrupt.c
View File

@ -53,7 +53,6 @@ void rt_hw_interrupt_init()
*vect_cntl = 0xF; *vect_cntl = 0xF;
} }
/* init interrupt nest, and context in thread sp */ /* init interrupt nest, and context in thread sp */
rt_interrupt_nest = 0; rt_interrupt_nest = 0;
rt_interrupt_from_thread = 0; rt_interrupt_from_thread = 0;
@ -79,6 +78,7 @@ void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_ha
{ {
/* find first un-assigned VIC address for the handler */ /* find first un-assigned VIC address for the handler */
vect_addr = (rt_uint32_t *)(VIC_BASE_ADDR + 0x100 + vector*4); vect_addr = (rt_uint32_t *)(VIC_BASE_ADDR + 0x100 + vector*4);
if (old_handler != RT_NULL) *old_handler = *vect_addr; /* get old handler */
*vect_addr = (rt_uint32_t)new_handler; /* set interrupt vector */ *vect_addr = (rt_uint32_t)new_handler; /* set interrupt vector */
} }
} }

6
libcpu/arm/lpc24xx/serial.c
View File

@ -322,7 +322,7 @@ void rt_hw_serial_init(void)
lpc_serial->read_index = lpc_serial->save_index = 0; lpc_serial->read_index = lpc_serial->save_index = 0;
/* Enable UART0 RxD and TxD pins */ /* Enable UART0 RxD and TxD pins */
PINSEL0 |= 0x05; PINSEL0 |= 0x50;
/* 8 bits, no Parity, 1 Stop bit */ /* 8 bits, no Parity, 1 Stop bit */
UART_LCR(lpc_serial->hw_base) = 0x83; UART_LCR(lpc_serial->hw_base) = 0x83;
@ -334,6 +334,7 @@ void rt_hw_serial_init(void)
/* DLAB = 0 */ /* DLAB = 0 */
UART_LCR(lpc_serial->hw_base) = 0x03; UART_LCR(lpc_serial->hw_base) = 0x03;
lpc_serial->parent.type = RT_Device_Class_Char;
lpc_serial->parent.init = rt_serial_init; lpc_serial->parent.init = rt_serial_init;
lpc_serial->parent.open = rt_serial_open; lpc_serial->parent.open = rt_serial_open;
lpc_serial->parent.close = rt_serial_close; lpc_serial->parent.close = rt_serial_close;
@ -343,7 +344,7 @@ void rt_hw_serial_init(void)
lpc_serial->parent.user_data = RT_NULL; lpc_serial->parent.user_data = RT_NULL;
rt_device_register(&lpc_serial->parent, rt_device_register(&lpc_serial->parent,
"uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM);
#endif #endif
#ifdef RT_USING_UART2 #ifdef RT_USING_UART2
@ -371,6 +372,7 @@ void rt_hw_serial_init(void)
/* DLAB = 0 */ /* DLAB = 0 */
UART_LCR(lpc_serial->hw_base) = 0x03; UART_LCR(lpc_serial->hw_base) = 0x03;
lpc_serial->parent.type = RT_Device_Class_Char;
lpc_serial->parent.init = rt_serial_init; lpc_serial->parent.init = rt_serial_init;
lpc_serial->parent.open = rt_serial_open; lpc_serial->parent.open = rt_serial_open;
lpc_serial->parent.close = rt_serial_close; lpc_serial->parent.close = rt_serial_close;

179
libcpu/arm/lpc24xx/start_gcc.S
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@ -10,13 +10,10 @@
* Change Logs: * Change Logs:
* Date Author Notes * Date Author Notes
* 2008-12-11 XuXinming first version * 2008-12-11 XuXinming first version
* 2011-03-17 Bernard update to 0.4.x
*/ */
/** #define CONFIG_STACKSIZE 512
* @addtogroup LPC2478
*/
/*@{*/
#define WDMOD (0xE0000000 + 0x00) #define WDMOD (0xE0000000 + 0x00)
#define VICIntEnClr (0xFFFFF000 + 0x014) #define VICIntEnClr (0xFFFFF000 + 0x014)
#define VICVectAddr (0xFFFFF000 + 0xF00) #define VICVectAddr (0xFFFFF000 + 0xF00)
@ -32,9 +29,30 @@
#define MAMCR (0xE01FC000 + 0x000) #define MAMCR (0xE01FC000 + 0x000)
#define MAMTIM (0xE01FC000 + 0x004) #define MAMTIM (0xE01FC000 + 0x004)
/* stack memory */
.section .bss.noinit
.equ IRQ_STACK_SIZE, 0x00000200
.equ FIQ_STACK_SIZE, 0x00000100
.equ UDF_STACK_SIZE, 0x00000004
.equ ABT_STACK_SIZE, 0x00000004
.equ SVC_STACK_SIZE, 0x00000200
/*.section .init, "ax"*/ .space IRQ_STACK_SIZE
.section .vectors IRQ_STACK:
.space FIQ_STACK_SIZE
FIQ_STACK:
.space UDF_STACK_SIZE
UDF_STACK:
.space ABT_STACK_SIZE
ABT_STACK:
.space SVC_STACK_SIZE
SVC_STACK:
.section .init, "ax"
.code 32 .code 32
.globl _start .globl _start
_start: _start:
@ -55,6 +73,31 @@ _vector_resv: .word vector_resv
_vector_irq: .word vector_irq _vector_irq: .word vector_irq
_vector_fiq: .word vector_fiq _vector_fiq: .word vector_fiq
.balignl 16,0xdeadbeef
/*
* rtthread kernel start and end
* which are defined in linker script
*/
.globl _rtthread_start
_rtthread_start:
.word _start
.globl _rtthread_end
_rtthread_end:
.word _end
/*
* rtthread bss start and end which are defined in linker script
*/
.globl _bss_start
_bss_start:
.word __bss_start
.globl _bss_end
_bss_end:
.word __bss_end
.text .text
.code 32 .code 32
@ -84,7 +127,50 @@ reset:
/* setup stack */ /* setup stack */
bl stack_setup bl stack_setup
_rtthread_startup: .word rtthread_startup /* copy .data to SRAM */
ldr r1, =_sidata /* .data start in image */
ldr r2, =_edata /* .data end in image */
ldr r3, =_sdata /* sram data start */
data_loop:
ldr r0, [r1, #0]
str r0, [r3]
add r1, r1, #4
add r3, r3, #4
cmp r3, r2 /* check if data to clear */
blo data_loop /* loop until done */
/* clear .bss */
mov r0,#0 /* get a zero */
ldr r1,=__bss_start /* bss start */
ldr r2,=__bss_end /* bss end */
bss_loop:
cmp r1,r2 /* check if data to clear */
strlo r0,[r1],#4 /* clear 4 bytes */
blo bss_loop /* loop until done */
/* call C++ constructors of global objects */
ldr r0, =__ctors_start__
ldr r1, =__ctors_end__
ctor_loop:
cmp r0, r1
beq ctor_end
ldr r2, [r0], #4
stmfd sp!, {r0-r1}
mov lr, pc
bx r2
ldmfd sp!, {r0-r1}
b ctor_loop
ctor_end:
/* start RT-Thread Kernel */
ldr pc, _rtthread_startup
_rtthread_startup:
.word rtthread_startup
.equ USERMODE, 0x10 .equ USERMODE, 0x10
.equ FIQMODE, 0x11 .equ FIQMODE, 0x11
@ -113,7 +199,9 @@ vector_irq:
bl rt_hw_trap_irq bl rt_hw_trap_irq
bl rt_interrupt_leave bl rt_interrupt_leave
/* if rt_thread_switch_interrput_flag set, jump to _interrupt_thread_switch and don't return */ /* if rt_thread_switch_interrput_flag set,
* jump to _interrupt_thread_switch and don't return
*/
ldr r0, =rt_thread_switch_interrput_flag ldr r0, =rt_thread_switch_interrput_flag
ldr r1, [r0] ldr r1, [r0]
cmp r1, #1 cmp r1, #1
@ -130,85 +218,70 @@ vector_fiq:
subs pc,lr,#4 subs pc,lr,#4
_interrupt_thread_switch: _interrupt_thread_switch:
mov r1, #0 @ clear rt_thread_switch_interrput_flag mov r1, #0 /* clear rt_thread_switch_interrput_flag */
str r1, [r0] str r1, [r0]
ldmfd sp!, {r0-r12,lr} @ reload saved registers ldmfd sp!, {r0-r12,lr} /* reload saved registers */
stmfd sp!, {r0-r3} @ save r0-r3 stmfd sp!, {r0-r3} /* save r0-r3 */
mov r1, sp mov r1, sp
add sp, sp, #16 @ restore sp add sp, sp, #16 /* restore sp */
sub r2, lr, #4 @ save old task's pc to r2 sub r2, lr, #4 /* save old task's pc to r2 */
mrs r3, spsr @ disable interrupt mrs r3, spsr /* disable interrupt */
orr r0, r3, #NOINT orr r0, r3, #NOINT
msr spsr_c, r0 msr spsr_c, r0
ldr r0, =.+8 @ switch to interrupted task's stack ldr r0, =.+8 /* switch to interrupted task's stack */
movs pc, r0 movs pc, r0
stmfd sp!, {r2} @ push old task's pc stmfd sp!, {r2} /* push old task's pc */
stmfd sp!, {r4-r12,lr} @ push old task's lr,r12-r4 stmfd sp!, {r4-r12,lr} /* push old task's lr,r12-r4 */
mov r4, r1 @ Special optimised code below mov r4, r1 /* Special optimised code below */
mov r5, r3 mov r5, r3
ldmfd r4!, {r0-r3} ldmfd r4!, {r0-r3}
stmfd sp!, {r0-r3} @ push old task's r3-r0 stmfd sp!, {r0-r3} /* push old task's r3-r0 */
stmfd sp!, {r5} @ push old task's psr stmfd sp!, {r5} /* push old task's psr */
mrs r4, spsr mrs r4, spsr
stmfd sp!, {r4} @ push old task's spsr stmfd sp!, {r4} /* push old task's spsr */
ldr r4, =rt_interrupt_from_thread ldr r4, =rt_interrupt_from_thread
ldr r5, [r4] ldr r5, [r4]
str sp, [r5] @ store sp in preempted tasks's TCB str sp, [r5] /* store sp in preempted tasks's TCB */
ldr r6, =rt_interrupt_to_thread ldr r6, =rt_interrupt_to_thread
ldr r6, [r6] ldr r6, [r6]
ldr sp, [r6] @ get new task's stack pointer ldr sp, [r6] /* get new task's stack pointer */
ldmfd sp!, {r4} @ pop new task's spsr ldmfd sp!, {r4} /* pop new task's spsr */
msr SPSR_cxsf, r4 msr SPSR_cxsf, r4
ldmfd sp!, {r4} @ pop new task's psr ldmfd sp!, {r4} /* pop new task's psr */
msr CPSR_cxsf, r4 msr CPSR_cxsf, r4
ldmfd sp!, {r0-r12,lr,pc} @ pop new task's r0-r12,lr & pc ldmfd sp!, {r0-r12,lr,pc} /* pop new task's r0-r12,lr & pc */
/* each mode stack memory */
stack_setup: stack_setup:
mrs r0, cpsr mrs r0, cpsr
bic r0, r0, #MODEMASK bic r0, r0, #MODEMASK
orr r1, r0, #UNDEFMODE|NOINT orr r1, r0, #UNDEFMODE|NOINT
msr cpsr_cxsf, r1 @ undef mode msr cpsr_cxsf, r1 /* undef mode */
ldr sp, =__UndStack_end ldr sp, =UDF_STACK
mrs r0, cpsr
bic r0, r0, #MODEMASK
orr r1,r0,#ABORTMODE|NOINT orr r1,r0,#ABORTMODE|NOINT
msr cpsr_cxsf,r1 @ abort mode msr cpsr_cxsf,r1 /* abort mode */
ldr sp,=__ABTStack_end ldr sp, =ABT_STACK
mrs r0, cpsr
bic r0, r0, #MODEMASK
orr r1,r0,#IRQMODE|NOINT orr r1,r0,#IRQMODE|NOINT
msr cpsr_cxsf,r1 @ IRQ mode msr cpsr_cxsf,r1 /* IRQ mode */
ldr sp,=__IRQStack_end ldr sp, =IRQ_STACK
mrs r0, cpsr
bic r0, r0, #MODEMASK
orr r1,r0,#FIQMODE|NOINT orr r1,r0,#FIQMODE|NOINT
msr cpsr_cxsf,r1 @ FIQ mode msr cpsr_cxsf,r1 /* FIQ mode */
ldr sp,=__FIQStack_end ldr sp, =FIQ_STACK
mrs r0, cpsr
bic r0,r0,#MODEMASK bic r0,r0,#MODEMASK
orr r1,r0,#SVCMODE|NOINT orr r1,r0,#SVCMODE|NOINT
msr cpsr_cxsf,r1 @ SVC mode msr cpsr_cxsf,r1 /* SVC mode */
ldr sp,=__SVCStack_end ldr sp, =SVC_STACK
/* USER mode is not initialized. */ /* USER mode is not initialized. */
mrs r0, cpsr mov pc,lr /* The LR register may be not valid for the mode changes.*/
bic r0, r0, #MODEMASK|0x80 //IRQ enable and FIQ disable
orr r1,r0,#USERMODE
msr cpsr_cxsf,r1 @ usr mode
ldr sp,=__USRStack_end
ldr pc, _rtthread_startup

2
libcpu/arm/lpc24xx/trap.c
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@ -121,6 +121,8 @@ void rt_hw_trap_irq()
rt_isr_handler_t isr_func; rt_isr_handler_t isr_func;
isr_func = (rt_isr_handler_t) VICVectAddr; isr_func = (rt_isr_handler_t) VICVectAddr;
/* fixme, how to get interrupt number */
isr_func(0); isr_func(0);
} }