RT-Thread
/
rt-thread
mirror of https://github.com/RT-Thread/rt-thread
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

import RT-Thread RTOS 0.3.x to Google SVN 

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
bernard.xiong 2009-07-02 22:48:23 +00:00
parent 80c72e66de
commit bda4730a94
321 changed files with 116698 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

51
AUTHORS Normal file
View File

@ -0,0 +1,51 @@
Kernel Design & Implementation
- Bernard Xiong <bernard.xiong@gmail.com>
LwIP 1.3.0
- Porting
Qiu Yi
- Testing
Layer2, Bernard Xiong
Filesystem
- Porting and Add Virtual Filesystem
- Testing
Qiu Yi
RTGUI
- Design and Implemenation
Bernard Xiong
newlib
- Porting
Qiu Yi
BSP Porting
Bernard Xiong
- AMTEL AT91SAM7S64 & AT91SAM7X256 Porting
- STM32 Porting
- S3C4510 Porting
- LPC2148 Porting
- PXA270 Porting
- AT91RM9200 Porting
Aozima
- LPC 2148 Porting
Qiu Yi
- S3C2410 & S3C2440 Porting
- IA32 Porting
- PXA270 Porting
Xu Xinming
- S3C44b0 Porting
- LPC2478 Porting
Wang Gang
- NDS Porting
Trissel
- AT91RM9200 Porting
Layer2
- AT91RM9200 Porting

340
COPYING Normal file
View File

@ -0,0 +1,340 @@
GNU GENERAL PUBLIC LICENSE
Version 2, June 1991
Copyright (C) 1989, 1991 Free Software Foundation, Inc.
59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
Everyone is permitted to copy and distribute verbatim copies
of this license document, but changing it is not allowed.
Preamble
The licenses for most software are designed to take away your
freedom to share and change it. By contrast, the GNU General Public
License is intended to guarantee your freedom to share and change free
software--to make sure the software is free for all its users. This
General Public License applies to most of the Free Software
Foundation's software and to any other program whose authors commit to
using it. (Some other Free Software Foundation software is covered by
the GNU Library General Public License instead.) You can apply it to
your programs, too.
When we speak of free software, we are referring to freedom, not
price. Our General Public Licenses are designed to make sure that you
have the freedom to distribute copies of free software (and charge for
this service if you wish), that you receive source code or can get it
if you want it, that you can change the software or use pieces of it
in new free programs; and that you know you can do these things.
To protect your rights, we need to make restrictions that forbid
anyone to deny you these rights or to ask you to surrender the rights.
These restrictions translate to certain responsibilities for you if you
distribute copies of the software, or if you modify it.
For example, if you distribute copies of such a program, whether
gratis or for a fee, you must give the recipients all the rights that
you have. You must make sure that they, too, receive or can get the
source code. And you must show them these terms so they know their
rights.
We protect your rights with two steps: (1) copyright the software, and
(2) offer you this license which gives you legal permission to copy,
distribute and/or modify the software.
Also, for each author's protection and ours, we want to make certain
that everyone understands that there is no warranty for this free
software. If the software is modified by someone else and passed on, we
want its recipients to know that what they have is not the original, so
that any problems introduced by others will not reflect on the original
authors' reputations.
Finally, any free program is threatened constantly by software
patents. We wish to avoid the danger that redistributors of a free
program will individually obtain patent licenses, in effect making the
program proprietary. To prevent this, we have made it clear that any
patent must be licensed for everyone's free use or not licensed at all.
The precise terms and conditions for copying, distribution and
modification follow.
GNU GENERAL PUBLIC LICENSE
TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
0. This License applies to any program or other work which contains
a notice placed by the copyright holder saying it may be distributed
under the terms of this General Public License. The "Program", below,
refers to any such program or work, and a "work based on the Program"
means either the Program or any derivative work under copyright law:
that is to say, a work containing the Program or a portion of it,
either verbatim or with modifications and/or translated into another
language. (Hereinafter, translation is included without limitation in
the term "modification".) Each licensee is addressed as "you".
Activities other than copying, distribution and modification are not
covered by this License; they are outside its scope. The act of
running the Program is not restricted, and the output from the Program
is covered only if its contents constitute a work based on the
Program (independent of having been made by running the Program).
Whether that is true depends on what the Program does.
1. You may copy and distribute verbatim copies of the Program's
source code as you receive it, in any medium, provided that you
conspicuously and appropriately publish on each copy an appropriate
copyright notice and disclaimer of warranty; keep intact all the
notices that refer to this License and to the absence of any warranty;
and give any other recipients of the Program a copy of this License
along with the Program.
You may charge a fee for the physical act of transferring a copy, and
you may at your option offer warranty protection in exchange for a fee.
2. You may modify your copy or copies of the Program or any portion
of it, thus forming a work based on the Program, and copy and
distribute such modifications or work under the terms of Section 1
above, provided that you also meet all of these conditions:
a) You must cause the modified files to carry prominent notices
stating that you changed the files and the date of any change.
b) You must cause any work that you distribute or publish, that in
whole or in part contains or is derived from the Program or any
part thereof, to be licensed as a whole at no charge to all third
parties under the terms of this License.
c) If the modified program normally reads commands interactively
when run, you must cause it, when started running for such
interactive use in the most ordinary way, to print or display an
announcement including an appropriate copyright notice and a
notice that there is no warranty (or else, saying that you provide
a warranty) and that users may redistribute the program under
these conditions, and telling the user how to view a copy of this
License. (Exception: if the Program itself is interactive but
does not normally print such an announcement, your work based on
the Program is not required to print an announcement.)
These requirements apply to the modified work as a whole. If
identifiable sections of that work are not derived from the Program,
and can be reasonably considered independent and separate works in
themselves, then this License, and its terms, do not apply to those
sections when you distribute them as separate works. But when you
distribute the same sections as part of a whole which is a work based
on the Program, the distribution of the whole must be on the terms of
this License, whose permissions for other licensees extend to the
entire whole, and thus to each and every part regardless of who wrote it.
Thus, it is not the intent of this section to claim rights or contest
your rights to work written entirely by you; rather, the intent is to
exercise the right to control the distribution of derivative or
collective works based on the Program.
In addition, mere aggregation of another work not based on the Program
with the Program (or with a work based on the Program) on a volume of
a storage or distribution medium does not bring the other work under
the scope of this License.
3. You may copy and distribute the Program (or a work based on it,
under Section 2) in object code or executable form under the terms of
Sections 1 and 2 above provided that you also do one of the following:
a) Accompany it with the complete corresponding machine-readable
source code, which must be distributed under the terms of Sections
1 and 2 above on a medium customarily used for software interchange; or,
b) Accompany it with a written offer, valid for at least three
years, to give any third party, for a charge no more than your
cost of physically performing source distribution, a complete
machine-readable copy of the corresponding source code, to be
distributed under the terms of Sections 1 and 2 above on a medium
customarily used for software interchange; or,
c) Accompany it with the information you received as to the offer
to distribute corresponding source code. (This alternative is
allowed only for noncommercial distribution and only if you
received the program in object code or executable form with such
an offer, in accord with Subsection b above.)
The source code for a work means the preferred form of the work for
making modifications to it. For an executable work, complete source
code means all the source code for all modules it contains, plus any
associated interface definition files, plus the scripts used to
control compilation and installation of the executable. However, as a
special exception, the source code distributed need not include
anything that is normally distributed (in either source or binary
form) with the major components (compiler, kernel, and so on) of the
operating system on which the executable runs, unless that component
itself accompanies the executable.
If distribution of executable or object code is made by offering
access to copy from a designated place, then offering equivalent
access to copy the source code from the same place counts as
distribution of the source code, even though third parties are not
compelled to copy the source along with the object code.
4. You may not copy, modify, sublicense, or distribute the Program
except as expressly provided under this License. Any attempt
otherwise to copy, modify, sublicense or distribute the Program is
void, and will automatically terminate your rights under this License.
However, parties who have received copies, or rights, from you under
this License will not have their licenses terminated so long as such
parties remain in full compliance.
5. You are not required to accept this License, since you have not
signed it. However, nothing else grants you permission to modify or
distribute the Program or its derivative works. These actions are
prohibited by law if you do not accept this License. Therefore, by
modifying or distributing the Program (or any work based on the
Program), you indicate your acceptance of this License to do so, and
all its terms and conditions for copying, distributing or modifying
the Program or works based on it.
6. Each time you redistribute the Program (or any work based on the
Program), the recipient automatically receives a license from the
original licensor to copy, distribute or modify the Program subject to
these terms and conditions. You may not impose any further
restrictions on the recipients' exercise of the rights granted herein.
You are not responsible for enforcing compliance by third parties to
this License.
7. If, as a consequence of a court judgment or allegation of patent
infringement or for any other reason (not limited to patent issues),
conditions are imposed on you (whether by court order, agreement or
otherwise) that contradict the conditions of this License, they do not
excuse you from the conditions of this License. If you cannot
distribute so as to satisfy simultaneously your obligations under this
License and any other pertinent obligations, then as a consequence you
may not distribute the Program at all. For example, if a patent
license would not permit royalty-free redistribution of the Program by
all those who receive copies directly or indirectly through you, then
the only way you could satisfy both it and this License would be to
refrain entirely from distribution of the Program.
If any portion of this section is held invalid or unenforceable under
any particular circumstance, the balance of the section is intended to
apply and the section as a whole is intended to apply in other
circumstances.
It is not the purpose of this section to induce you to infringe any
patents or other property right claims or to contest validity of any
such claims; this section has the sole purpose of protecting the
integrity of the free software distribution system, which is
implemented by public license practices. Many people have made
generous contributions to the wide range of software distributed
through that system in reliance on consistent application of that
system; it is up to the author/donor to decide if he or she is willing
to distribute software through any other system and a licensee cannot
impose that choice.
This section is intended to make thoroughly clear what is believed to
be a consequence of the rest of this License.
8. If the distribution and/or use of the Program is restricted in
certain countries either by patents or by copyrighted interfaces, the
original copyright holder who places the Program under this License
may add an explicit geographical distribution limitation excluding
those countries, so that distribution is permitted only in or among
countries not thus excluded. In such case, this License incorporates
the limitation as if written in the body of this License.
9. The Free Software Foundation may publish revised and/or new versions
of the General Public License from time to time. Such new versions will
be similar in spirit to the present version, but may differ in detail to
address new problems or concerns.
Each version is given a distinguishing version number. If the Program
specifies a version number of this License which applies to it and "any
later version", you have the option of following the terms and conditions
either of that version or of any later version published by the Free
Software Foundation. If the Program does not specify a version number of
this License, you may choose any version ever published by the Free Software
Foundation.
10. If you wish to incorporate parts of the Program into other free
programs whose distribution conditions are different, write to the author
to ask for permission. For software which is copyrighted by the Free
Software Foundation, write to the Free Software Foundation; we sometimes
make exceptions for this. Our decision will be guided by the two goals
of preserving the free status of all derivatives of our free software and
of promoting the sharing and reuse of software generally.
NO WARRANTY
11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN
OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES
PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED
OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS
TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE
PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,
REPAIR OR CORRECTION.
12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR
REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,
INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING
OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED
TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY
YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER
PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES.
END OF TERMS AND CONDITIONS
How to Apply These Terms to Your New Programs
If you develop a new program, and you want it to be of the greatest
possible use to the public, the best way to achieve this is to make it
free software which everyone can redistribute and change under these terms.
To do so, attach the following notices to the program. It is safest
to attach them to the start of each source file to most effectively
convey the exclusion of warranty; and each file should have at least
the "copyright" line and a pointer to where the full notice is found.
<one line to give the program's name and a brief idea of what it does.>
Copyright (C) <year> <name of author>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
Also add information on how to contact you by electronic and paper mail.
If the program is interactive, make it output a short notice like this
when it starts in an interactive mode:
Gnomovision version 69, Copyright (C) year name of author
Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
The hypothetical commands `show w' and `show c' should show the appropriate
parts of the General Public License. Of course, the commands you use may
be called something other than `show w' and `show c'; they could even be
mouse-clicks or menu items--whatever suits your program.
You should also get your employer (if you work as a programmer) or your
school, if any, to sign a "copyright disclaimer" for the program, if
necessary. Here is a sample; alter the names:
Yoyodyne, Inc., hereby disclaims all copyright interest in the program
`Gnomovision' (which makes passes at compilers) written by James Hacker.
<signature of Ty Coon>, 1 April 1989
Ty Coon, President of Vice
This General Public License does not permit incorporating your program into
proprietary programs. If your program is a subroutine library, you may
consider it more useful to permit linking proprietary applications with the
library. If this is what you want to do, use the GNU Library General
Public License instead of this License.

57
bsp/stm32f103vb_lwip/application.c Normal file
View File

@ -0,0 +1,57 @@
/*
* File : app.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://openlab.rt-thread.com/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2009-05-24 Bernard Add lwip init
*/
/**
* @addtogroup STM32
*/
/*@{*/
#include <rtthread.h>
#ifdef RT_USING_LWIP
#include <lwip/sys.h>
#endif
/* thread phase init */
void rt_init_thread_entry(void *parameter)
{
/* LwIP Initialization */
#ifdef RT_USING_LWIP
{
extern void lwip_sys_init(void);
extern void httpd_init(void);
/* init lwip system */
lwip_sys_init();
rt_kprintf("TCP/IP initialized!\n");
httpd_init();
rt_kprintf("httpd initialized!\n");
}
#endif
}
int rt_application_init()
{
rt_thread_t init_thread;
init_thread = rt_thread_create("init",
rt_init_thread_entry, RT_NULL,
2048, 8, 20);
rt_thread_startup(init_thread);
return 0;
}
/*@}*/

230
bsp/stm32f103vb_lwip/board.c Normal file
View File

@ -0,0 +1,230 @@
/*
* File : board.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2009 RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://openlab.rt-thread.com/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2006-08-23 Bernard first implementation
*/
#include <rthw.h>
#include <rtthread.h>
#include "stm32f10x_lib.h"
static void rt_hw_console_init(void);
/**
* @addtogroup STM32
*/
/*@{*/
ErrorStatus HSEStartUpStatus;
/*******************************************************************************
* Function Name : RCC_Configuration
* Description : Configures the different system clocks.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void RCC_Configuration(void)
{
/* RCC system reset(for debug purpose) */
RCC_DeInit();
/* Enable HSE */
RCC_HSEConfig(RCC_HSE_ON);
/* Wait till HSE is ready */
HSEStartUpStatus = RCC_WaitForHSEStartUp();
if(HSEStartUpStatus == SUCCESS)
{
/* HCLK = SYSCLK */
RCC_HCLKConfig(RCC_SYSCLK_Div1);
/* PCLK2 = HCLK */
RCC_PCLK2Config(RCC_HCLK_Div1);
/* PCLK1 = HCLK/2 */
RCC_PCLK1Config(RCC_HCLK_Div2);
/* Flash 2 wait state */
FLASH_SetLatency(FLASH_Latency_2);
/* Enable Prefetch Buffer */
FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
/* PLLCLK = 8MHz * 9 = 72 MHz */
RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9);
/* Enable PLL */
RCC_PLLCmd(ENABLE);
/* Wait till PLL is ready */
while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) ;
/* Select PLL as system clock source */
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
/* Wait till PLL is used as system clock source */
while(RCC_GetSYSCLKSource() != 0x08) ;
}
}
/*******************************************************************************
* Function Name : NVIC_Configuration
* Description : Configures Vector Table base location.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void NVIC_Configuration(void)
{
#ifdef VECT_TAB_RAM
/* Set the Vector Table base location at 0x20000000 */
NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
#else /* VECT_TAB_FLASH */
/* Set the Vector Table base location at 0x08000000 */
NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
#endif
}
/*******************************************************************************
* Function Name : SysTick_Configuration
* Description : Configures the SysTick for OS tick.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void SysTick_Configuration(void)
{
RCC_ClocksTypeDef rcc_clocks;
rt_uint32_t cnts;
RCC_GetClocksFreq(&rcc_clocks);
cnts = (rt_uint32_t)rcc_clocks.HCLK_Frequency / RT_TICK_PER_SECOND;
SysTick_SetReload(cnts);
SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK);
SysTick_CounterCmd(SysTick_Counter_Enable);
SysTick_ITConfig(ENABLE);
}
extern void rt_hw_interrupt_thread_switch(void);
/**
* This is the timer interrupt service routine.
*
*/
void rt_hw_timer_handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
rt_tick_increase();
/* leave interrupt */
rt_interrupt_leave();
rt_hw_interrupt_thread_switch();
}
/**
* This function will initial STM32 board.
*/
void rt_hw_board_init()
{
/* Configure the system clocks */
RCC_Configuration();
/* NVIC Configuration */
NVIC_Configuration();
/* Configure the SysTick */
SysTick_Configuration();
rt_hw_console_init();
}
/* init console to support rt_kprintf */
static void rt_hw_console_init()
{
/* Enable USART1 and GPIOA clocks */
RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOA, ENABLE);
/* GPIO configuration */
{
GPIO_InitTypeDef GPIO_InitStructure;
/* Configure USART1 Tx (PA.09) as alternate function push-pull */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_Init(GPIOA, &GPIO_InitStructure);
/* Configure USART1 Rx (PA.10) as input floating */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_Init(GPIOA, &GPIO_InitStructure);
}
/* USART configuration */
{
USART_InitTypeDef USART_InitStructure;
/* USART1 configured as follow:
- BaudRate = 115200 baud
- Word Length = 8 Bits
- One Stop Bit
- No parity
- Hardware flow control disabled (RTS and CTS signals)
- Receive and transmit enabled
- USART Clock disabled
- USART CPOL: Clock is active low
- USART CPHA: Data is captured on the middle
- USART LastBit: The clock pulse of the last data bit is not output to
the SCLK pin
*/
USART_InitStructure.USART_BaudRate = 115200;
USART_InitStructure.USART_WordLength = USART_WordLength_8b;
USART_InitStructure.USART_StopBits = USART_StopBits_1;
USART_InitStructure.USART_Parity = USART_Parity_No;
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
USART_Init(USART1, &USART_InitStructure);
/* Enable USART1 */
USART_Cmd(USART1, ENABLE);
}
}
/* write one character to serial, must not trigger interrupt */
static void rt_hw_console_putc(const char c)
{
/*
to be polite with serial console add a line feed
to the carriage return character
*/
if (c=='\n')rt_hw_console_putc('\r');
while (!(USART1->SR & USART_FLAG_TXE));
USART1->DR = (c & 0x1FF);
}
/**
* This function is used by rt_kprintf to display a string on console.
*
* @param str the displayed string
*/
void rt_hw_console_output(const char* str)
{
while (*str)
{
rt_hw_console_putc (*str++);
}
}
/*@}*/

25
bsp/stm32f103vb_lwip/board.h Normal file
View File

@ -0,0 +1,25 @@
/*
* File : board.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://openlab.rt-thread.com/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2006-10-08 Bernard add board.h to this bsp
*/
#ifndef __BOARD_H__
#define __BOARD_H__
void rt_hw_board_led_on(int n);
void rt_hw_board_led_off(int n);
void rt_hw_board_init(void);
void rt_hw_usart_init(void);
void rt_hw_sdcard_init(void);
#endif

279
bsp/stm32f103vb_lwip/cortexm3_macro.s Normal file
View File

@ -0,0 +1,279 @@
;******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
;* File Name : cortexm3_macro.s
;* Author : MCD Application Team
;* Version : V1.1
;* Date : 11/26/2007
;* Description : Instruction wrappers for special Cortex-M3 instructions.
;*******************************************************************************
; THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
THUMB
REQUIRE8
PRESERVE8
AREA |.text|, CODE, READONLY, ALIGN=2
; Exported functions
EXPORT __WFI
EXPORT __WFE
EXPORT __SEV
EXPORT __ISB
EXPORT __DSB
EXPORT __DMB
EXPORT __SVC
EXPORT __MRS_CONTROL
EXPORT __MSR_CONTROL
EXPORT __MRS_PSP
EXPORT __MSR_PSP
EXPORT __MRS_MSP
EXPORT __MSR_MSP
EXPORT __SETPRIMASK
EXPORT __RESETPRIMASK
EXPORT __SETFAULTMASK
EXPORT __RESETFAULTMASK
EXPORT __BASEPRICONFIG
EXPORT __GetBASEPRI
EXPORT __REV_HalfWord
EXPORT __REV_Word
;*******************************************************************************
; Function Name : __WFI
; Description : Assembler function for the WFI instruction.
; Input : None
; Return : None
;*******************************************************************************
__WFI
WFI
BX r14
;*******************************************************************************
; Function Name : __WFE
; Description : Assembler function for the WFE instruction.
; Input : None
; Return : None
;*******************************************************************************
__WFE
WFE
BX r14
;*******************************************************************************
; Function Name : __SEV
; Description : Assembler function for the SEV instruction.
; Input : None
; Return : None
;*******************************************************************************
__SEV
SEV
BX r14
;*******************************************************************************
; Function Name : __ISB
; Description : Assembler function for the ISB instruction.
; Input : None
; Return : None
;*******************************************************************************
__ISB
ISB
BX r14
;*******************************************************************************
; Function Name : __DSB
; Description : Assembler function for the DSB instruction.
; Input : None
; Return : None
;*******************************************************************************
__DSB
DSB
BX r14
;*******************************************************************************
; Function Name : __DMB
; Description : Assembler function for the DMB instruction.
; Input : None
; Return : None
;*******************************************************************************
__DMB
DMB
BX r14
;*******************************************************************************
; Function Name : __SVC
; Description : Assembler function for the SVC instruction.
; Input : None
; Return : None
;*******************************************************************************
__SVC
SVC 0x01
BX r14
;*******************************************************************************
; Function Name : __MRS_CONTROL
; Description : Assembler function for the MRS instruction.
; Input : None
; Return : - r0 : Cortex-M3 CONTROL register value.
;*******************************************************************************
__MRS_CONTROL
MRS r0, CONTROL
BX r14
;*******************************************************************************
; Function Name : __MSR_CONTROL
; Description : Assembler function for the MSR instruction.
; Input : - r0 : Cortex-M3 CONTROL register new value.
; Return : None
;*******************************************************************************
__MSR_CONTROL
MSR CONTROL, r0
ISB
BX r14
;*******************************************************************************
; Function Name : __MRS_PSP
; Description : Assembler function for the MRS instruction.
; Input : None
; Return : - r0 : Process Stack value.
;*******************************************************************************
__MRS_PSP
MRS r0, PSP
BX r14
;*******************************************************************************
; Function Name : __MSR_PSP
; Description : Assembler function for the MSR instruction.
; Input : - r0 : Process Stack new value.
; Return : None
;*******************************************************************************
__MSR_PSP
MSR PSP, r0 ; set Process Stack value
BX r14
;*******************************************************************************
; Function Name : __MRS_MSP
; Description : Assembler function for the MRS instruction.
; Input : None
; Return : - r0 : Main Stack value.
;*******************************************************************************
__MRS_MSP
MRS r0, MSP
BX r14
;*******************************************************************************
; Function Name : __MSR_MSP
; Description : Assembler function for the MSR instruction.
; Input : - r0 : Main Stack new value.
; Return : None
;*******************************************************************************
__MSR_MSP
MSR MSP, r0 ; set Main Stack value
BX r14
;*******************************************************************************
; Function Name : __SETPRIMASK
; Description : Assembler function to set the PRIMASK.
; Input : None
; Return : None
;*******************************************************************************
__SETPRIMASK
CPSID i
BX r14
;*******************************************************************************
; Function Name : __RESETPRIMASK
; Description : Assembler function to reset the PRIMASK.
; Input : None
; Return : None
;*******************************************************************************
__RESETPRIMASK
CPSIE i
BX r14
;*******************************************************************************
; Function Name : __SETFAULTMASK
; Description : Assembler function to set the FAULTMASK.
; Input : None
; Return : None
;*******************************************************************************
__SETFAULTMASK
CPSID f
BX r14
;*******************************************************************************
; Function Name : __RESETFAULTMASK
; Description : Assembler function to reset the FAULTMASK.
; Input : None
; Return : None
;*******************************************************************************
__RESETFAULTMASK
CPSIE f
BX r14
;*******************************************************************************
; Function Name : __BASEPRICONFIG
; Description : Assembler function to set the Base Priority.
; Input : - r0 : Base Priority new value
; Return : None
;*******************************************************************************
__BASEPRICONFIG
MSR BASEPRI, r0
BX r14
;*******************************************************************************
; Function Name : __GetBASEPRI
; Description : Assembler function to get the Base Priority value.
; Input : None
; Return : - r0 : Base Priority value
;*******************************************************************************
__GetBASEPRI
MRS r0, BASEPRI_MAX
BX r14
;*******************************************************************************
; Function Name : __REV_HalfWord
; Description : Reverses the byte order in HalfWord(16-bit) input variable.
; Input : - r0 : specifies the input variable
; Return : - r0 : holds tve variable value after byte reversing.
;*******************************************************************************
__REV_HalfWord
REV16 r0, r0
BX r14
;*******************************************************************************
; Function Name : __REV_Word
; Description : Reverses the byte order in Word(32-bit) input variable.
; Input : - r0 : specifies the input variable
; Return : - r0 : holds tve variable value after byte reversing.
;*******************************************************************************
__REV_Word
REV r0, r0
BX r14
END
;******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE*****

725
bsp/stm32f103vb_lwip/enc28j60.c Normal file
View File

@ -0,0 +1,725 @@
#include "enc28j60.h"
#include <netif/ethernetif.h>
#include "lwipopts.h"
#include "stm32f10x_lib.h"
#define MAX_ADDR_LEN 6
#define CSACTIVE GPIO_ResetBits(GPIOA, GPIO_Pin_12);
#define CSPASSIVE GPIO_SetBits(GPIOA, GPIO_Pin_12);
struct net_device
{
/* inherit from ethernet device */
struct eth_device parent;
/* interface address info. */
rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */
};
static struct net_device enc28j60_dev_entry;
static struct net_device *enc28j60_dev =&enc28j60_dev_entry;
static rt_uint8_t Enc28j60Bank;
static rt_uint16_t NextPacketPtr;
static struct rt_semaphore tx_sem;
void _delay_us(rt_uint32_t us)
{
rt_uint32_t len;
for (;us > 0; us --)
for (len = 0; len < 20; len++ );
}
void delay_ms(rt_uint32_t ms)
{
rt_uint32_t len;
for (;ms > 0; ms --)
for (len = 0; len < 100; len++ );
}
rt_uint8_t spi_read_op(rt_uint8_t op, rt_uint8_t address)
{
int temp=0;
CSACTIVE;
SPI_I2S_SendData(SPI1, (op | (address & ADDR_MASK)));
while(SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_BSY)==SET);
SPI_I2S_ReceiveData(SPI1);
SPI_I2S_SendData(SPI1, 0x00);
while(SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_BSY)==SET);
// do dummy read if needed (for mac and mii, see datasheet page 29)
if(address & 0x80)
{
SPI_I2S_ReceiveData(SPI1);
SPI_I2S_SendData(SPI1, 0x00);
while(SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_BSY)==SET);
}
// release CS
temp=SPI_I2S_ReceiveData(SPI1);
// for(t=0;t<20;t++);
CSPASSIVE;
return (temp);
}
void spi_write_op(rt_uint8_t op, rt_uint8_t address, rt_uint8_t data)
{
rt_uint32_t level;
level = rt_hw_interrupt_disable();
CSACTIVE;
SPI_I2S_SendData(SPI1, op | (address & ADDR_MASK));
while(SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_BSY)==SET);
SPI_I2S_SendData(SPI1,data);
while(SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_BSY)==SET);
CSPASSIVE;
rt_hw_interrupt_enable(level);
}
void enc28j60_set_bank(rt_uint8_t address)
{
// set the bank (if needed)
if((address & BANK_MASK) != Enc28j60Bank)
{
// set the bank
spi_write_op(ENC28J60_BIT_FIELD_CLR, ECON1, (ECON1_BSEL1|ECON1_BSEL0));
spi_write_op(ENC28J60_BIT_FIELD_SET, ECON1, (address & BANK_MASK)>>5);
Enc28j60Bank = (address & BANK_MASK);
}
}
rt_uint8_t spi_read(rt_uint8_t address)
{
// set the bank
enc28j60_set_bank(address);
// do the read
return spi_read_op(ENC28J60_READ_CTRL_REG, address);
}
void spi_write(rt_uint8_t address, rt_uint8_t data)
{
// set the bank
enc28j60_set_bank(address);
// do the write
spi_write_op(ENC28J60_WRITE_CTRL_REG, address, data);
}
void enc28j60_phy_write(rt_uint8_t address, rt_uint16_t data)
{
// set the PHY register address
spi_write(MIREGADR, address);
// write the PHY data
spi_write(MIWRL, data);
spi_write(MIWRH, data>>8);
// wait until the PHY write completes
while(spi_read(MISTAT) & MISTAT_BUSY)
{
_delay_us(15);
}
}
// read upper 8 bits
rt_uint16_t enc28j60_phy_read(rt_uint8_t address)
{
// Set the right address and start the register read operation
spi_write(MIREGADR, address);
spi_write(MICMD, MICMD_MIIRD);
_delay_us(15);
// wait until the PHY read completes
while(spi_read(MISTAT) & MISTAT_BUSY);
// reset reading bit
spi_write(MICMD, 0x00);
return (spi_read(MIRDH));
}
void enc28j60_clkout(rt_uint8_t clk)
{
//setup clkout: 2 is 12.5MHz:
spi_write(ECOCON, clk & 0x7);
}
/*
* Access the PHY to determine link status
*/
static void enc28j60_check_link_status()
{
rt_uint16_t reg;
int duplex;
reg = enc28j60_phy_read(PHSTAT2);
duplex = reg & PHSTAT2_DPXSTAT;
if (reg & PHSTAT2_LSTAT)
{
/* on */
}
else
{
/* off */
}
}
#ifdef RT_USING_FINSH
#include <finsh.h>
/*
* Debug routine to dump useful register contents
*/
static void enc28j60(void)
{
rt_kprintf("-- enc28j60 registers:\n");
rt_kprintf("HwRevID: 0x%02x\n", spi_read(EREVID));
rt_kprintf("Cntrl: ECON1 ECON2 ESTAT EIR EIE\n");
rt_kprintf(" 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n",spi_read(ECON1), spi_read(ECON2), spi_read(ESTAT), spi_read(EIR), spi_read(EIE));
rt_kprintf("MAC : MACON1 MACON3 MACON4\n");
rt_kprintf(" 0x%02x 0x%02x 0x%02x\n", spi_read(MACON1), spi_read(MACON3), spi_read(MACON4));
rt_kprintf("Rx : ERXST ERXND ERXWRPT ERXRDPT ERXFCON EPKTCNT MAMXFL\n");
rt_kprintf(" 0x%04x 0x%04x 0x%04x 0x%04x ",
(spi_read(ERXSTH) << 8) | spi_read(ERXSTL),
(spi_read(ERXNDH) << 8) | spi_read(ERXNDL),
(spi_read(ERXWRPTH) << 8) | spi_read(ERXWRPTL),
(spi_read(ERXRDPTH) << 8) | spi_read(ERXRDPTL));
rt_kprintf("0x%02x 0x%02x 0x%04x\n", spi_read(ERXFCON), spi_read(EPKTCNT),
(spi_read(MAMXFLH) << 8) | spi_read(MAMXFLL));
rt_kprintf("Tx : ETXST ETXND MACLCON1 MACLCON2 MAPHSUP\n");
rt_kprintf(" 0x%04x 0x%04x 0x%02x 0x%02x 0x%02x\n",
(spi_read(ETXSTH) << 8) | spi_read(ETXSTL),
(spi_read(ETXNDH) << 8) | spi_read(ETXNDL),
spi_read(MACLCON1), spi_read(MACLCON2), spi_read(MAPHSUP));
}
FINSH_FUNCTION_EXPORT(enc28j60, dump enc28j60 registers)
#endif
/*
* RX handler
* ignore PKTIF because is unreliable! (look at the errata datasheet)
* check EPKTCNT is the suggested workaround.
* We don't need to clear interrupt flag, automatically done when
* enc28j60_hw_rx() decrements the packet counter.
* Returns how many packet processed.
*/
void enc28j60_isr()
{
/* Variable definitions can be made now. */
volatile rt_uint32_t eir, pk_counter;
volatile rt_bool_t rx_activiated;
rx_activiated = RT_FALSE;
/* get EIR */
eir = spi_read(EIR);
// rt_kprintf("eir: 0x%08x\n", eir);
do
{
/* errata #4, PKTIF does not reliable */
pk_counter = spi_read(EPKTCNT);
if (pk_counter)
{
rt_err_t result;
/* a frame has been received */
result = eth_device_ready((struct eth_device*)&(enc28j60_dev->parent));
RT_ASSERT(result == RT_EOK);
// switch to bank 0
enc28j60_set_bank(EIE);
// disable rx interrutps
spi_write_op(ENC28J60_BIT_FIELD_CLR, EIE, EIE_PKTIE);
}
/* clear PKTIF */
if (eir & EIR_PKTIF)
{
enc28j60_set_bank(EIR);
spi_write_op(ENC28J60_BIT_FIELD_CLR, EIR, EIR_PKTIF);
rx_activiated = RT_TRUE;
}
/* clear DMAIF */
if (eir & EIR_DMAIF)
{
enc28j60_set_bank(EIR);
spi_write_op(ENC28J60_BIT_FIELD_CLR, EIR, EIR_DMAIF);
}
/* LINK changed handler */
if ( eir & EIR_LINKIF)
{
enc28j60_check_link_status();
/* read PHIR to clear the flag */
enc28j60_phy_read(PHIR);
enc28j60_set_bank(EIR);
spi_write_op(ENC28J60_BIT_FIELD_CLR, EIR, EIR_LINKIF);
}
if (eir & EIR_TXIF)
{
/* A frame has been transmitted. */
rt_sem_release(&tx_sem);
enc28j60_set_bank(EIR);
spi_write_op(ENC28J60_BIT_FIELD_CLR, EIR, EIR_TXIF);
}
eir = spi_read(EIR);
// rt_kprintf("inner eir: 0x%08x\n", eir);
} while ((rx_activiated != RT_TRUE && eir != 0));
}
/* RT-Thread Device Interface */
/* initialize the interface */
rt_err_t enc28j60_init(rt_device_t dev)
{
CSPASSIVE;
// perform system reset
spi_write_op(ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
delay_ms(50);
NextPacketPtr = RXSTART_INIT;
// Rx start
spi_write(ERXSTL, RXSTART_INIT&0xFF);
spi_write(ERXSTH, RXSTART_INIT>>8);
// set receive pointer address
spi_write(ERXRDPTL, RXSTOP_INIT&0xFF);
spi_write(ERXRDPTH, RXSTOP_INIT>>8);
// RX end
spi_write(ERXNDL, RXSTOP_INIT&0xFF);
spi_write(ERXNDH, RXSTOP_INIT>>8);
// TX start
spi_write(ETXSTL, TXSTART_INIT&0xFF);
spi_write(ETXSTH, TXSTART_INIT>>8);
// set transmission pointer address
spi_write(EWRPTL, TXSTART_INIT&0xFF);
spi_write(EWRPTH, TXSTART_INIT>>8);
// TX end
spi_write(ETXNDL, TXSTOP_INIT&0xFF);
spi_write(ETXNDH, TXSTOP_INIT>>8);
// do bank 1 stuff, packet filter:
// For broadcast packets we allow only ARP packtets
// All other packets should be unicast only for our mac (MAADR)
//
// The pattern to match on is therefore
// Type ETH.DST
// ARP BROADCAST
// 06 08 -- ff ff ff ff ff ff -> ip checksum for theses bytes=f7f9
// in binary these poitions are:11 0000 0011 1111
// This is hex 303F->EPMM0=0x3f,EPMM1=0x30
spi_write(ERXFCON, ERXFCON_UCEN|ERXFCON_CRCEN|ERXFCON_BCEN);
// do bank 2 stuff
// enable MAC receive
spi_write(MACON1, MACON1_MARXEN|MACON1_TXPAUS|MACON1_RXPAUS);
// enable automatic padding to 60bytes and CRC operations
// spi_write_op(ENC28J60_BIT_FIELD_SET, MACON3, MACON3_PADCFG0|MACON3_TXCRCEN|MACON3_FRMLNEN);
spi_write_op(ENC28J60_BIT_FIELD_SET, MACON3, MACON3_PADCFG0 | MACON3_TXCRCEN | MACON3_FRMLNEN | MACON3_FULDPX);
// bring MAC out of reset
// set inter-frame gap (back-to-back)
// spi_write(MABBIPG, 0x12);
spi_write(MABBIPG, 0x15);
spi_write(MACON4, MACON4_DEFER);
spi_write(MACLCON2, 63);
// set inter-frame gap (non-back-to-back)
spi_write(MAIPGL, 0x12);
spi_write(MAIPGH, 0x0C);
// Set the maximum packet size which the controller will accept
// Do not send packets longer than MAX_FRAMELEN:
spi_write(MAMXFLL, MAX_FRAMELEN&0xFF);
spi_write(MAMXFLH, MAX_FRAMELEN>>8);
// do bank 3 stuff
// write MAC address
// NOTE: MAC address in ENC28J60 is byte-backward
spi_write(MAADR0, enc28j60_dev->dev_addr[5]);
spi_write(MAADR1, enc28j60_dev->dev_addr[4]);
spi_write(MAADR2, enc28j60_dev->dev_addr[3]);
spi_write(MAADR3, enc28j60_dev->dev_addr[2]);
spi_write(MAADR4, enc28j60_dev->dev_addr[1]);
spi_write(MAADR5, enc28j60_dev->dev_addr[0]);
/* output off */
spi_write(ECOCON, 0x00);
// enc28j60_phy_write(PHCON1, 0x00);
enc28j60_phy_write(PHCON1, PHCON1_PDPXMD); // full duplex
// no loopback of transmitted frames
enc28j60_phy_write(PHCON2, PHCON2_HDLDIS);
enc28j60_set_bank(ECON2);
spi_write_op(ENC28J60_BIT_FIELD_SET, ECON2, ECON2_AUTOINC);
// switch to bank 0
enc28j60_set_bank(ECON1);
// enable interrutps
spi_write_op(ENC28J60_BIT_FIELD_SET, EIE, EIE_INTIE|EIE_PKTIE|EIR_TXIF);
// enable packet reception
spi_write_op(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN);
/* clock out */
// enc28j60_clkout(2);
enc28j60_phy_write(PHLCON, 0xD76); //0x476
delay_ms(20);
rt_kprintf("enc28j60 init ok!\n");
return RT_EOK;
}
/* control the interface */
rt_err_t enc28j60_control(rt_device_t dev, rt_uint8_t cmd, void *args)
{
switch(cmd)
{
case NIOCTL_GADDR:
/* get mac address */
if(args) rt_memcpy(args, enc28j60_dev_entry.dev_addr, 6);
else return -RT_ERROR;
break;
default :
break;
}
return RT_EOK;
}
/* Open the ethernet interface */
rt_err_t enc28j60_open(rt_device_t dev, rt_uint16_t oflag)
{
return RT_EOK;
}
/* Close the interface */
rt_err_t enc28j60_close(rt_device_t dev)
{
return RT_EOK;
}
/* Read */
rt_size_t enc28j60_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
{
rt_set_errno(-RT_ENOSYS);
return 0;
}
/* Write */
rt_size_t enc28j60_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
{
rt_set_errno(-RT_ENOSYS);
return 0;
}
/* ethernet device interface */
/*
* Transmit packet.
*/
rt_err_t enc28j60_tx( rt_device_t dev, struct pbuf* p)
{
struct pbuf* q;
rt_uint32_t len;
rt_uint8_t* ptr;
// rt_kprintf("tx pbuf: 0x%08x\n", p);
/* lock tx operation */
rt_sem_take(&tx_sem, RT_WAITING_FOREVER);
// Set the write pointer to start of transmit buffer area
spi_write(EWRPTL, TXSTART_INIT&0xFF);
spi_write(EWRPTH, TXSTART_INIT>>8);
// Set the TXND pointer to correspond to the packet size given
spi_write(ETXNDL, (TXSTART_INIT+ p->tot_len + 1)&0xFF);
spi_write(ETXNDH, (TXSTART_INIT+ p->tot_len + 1)>>8);
// write per-packet control byte (0x00 means use macon3 settings)
spi_write_op(ENC28J60_WRITE_BUF_MEM, 0, 0x00);
for (q = p; q != NULL; q = q->next)
{
CSACTIVE;
SPI_I2S_SendData(SPI1, ENC28J60_WRITE_BUF_MEM);
while(SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_BSY)==SET);
len = q->len;
ptr = q->payload;
while(len)
{
SPI_I2S_SendData(SPI1,*ptr) ;
while(SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_BSY)==SET);;
ptr++;
len--;
}
CSPASSIVE;
}
// send the contents of the transmit buffer onto the network
spi_write_op(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_TXRTS);
// Reset the transmit logic problem. See Rev. B4 Silicon Errata point 12.
if( (spi_read(EIR) & EIR_TXERIF) )
{
spi_write_op(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_TXRTS);
}
// rt_kprintf("tx ok\n");
return RT_EOK;
}
struct pbuf *enc28j60_rx(rt_device_t dev)
{
struct pbuf* p;
rt_uint32_t len;
rt_uint16_t rxstat;
rt_uint32_t pk_counter;
p = RT_NULL;
pk_counter = spi_read(EPKTCNT);
if (pk_counter)
{
// Set the read pointer to the start of the received packet
spi_write(ERDPTL, (NextPacketPtr));
spi_write(ERDPTH, (NextPacketPtr)>>8);
// read the next packet pointer
NextPacketPtr = spi_read_op(ENC28J60_READ_BUF_MEM, 0);
NextPacketPtr |= spi_read_op(ENC28J60_READ_BUF_MEM, 0)<<8;
// read the packet length (see datasheet page 43)
len = spi_read_op(ENC28J60_READ_BUF_MEM, 0); //0x54
len |= spi_read_op(ENC28J60_READ_BUF_MEM, 0) <<8; //5554
len-=4; //remove the CRC count
// read the receive status (see datasheet page 43)
rxstat = spi_read_op(ENC28J60_READ_BUF_MEM, 0);
rxstat |= ((rt_uint16_t)spi_read_op(ENC28J60_READ_BUF_MEM, 0))<<8;
// check CRC and symbol errors (see datasheet page 44, table 7-3):
// The ERXFCON.CRCEN is set by default. Normally we should not
// need to check this.
if ((rxstat & 0x80)==0)
{
// invalid
len=0;
}
else
{
/* allocation pbuf */
p = pbuf_alloc(PBUF_LINK, len, PBUF_RAM);
if (p != RT_NULL)
{
rt_uint8_t* data;
struct pbuf* q;
for (q = p; q != RT_NULL; q= q->next)
{
data = q->payload;
len = q->len;
CSACTIVE;
SPI_I2S_SendData(SPI1,ENC28J60_READ_BUF_MEM);
while(SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_BSY)==SET);
SPI_I2S_ReceiveData(SPI1);
while(len)
{
len--;
SPI_I2S_SendData(SPI1,0x00) ;
while(SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_BSY)==SET);
*data= SPI_I2S_ReceiveData(SPI1);
data++;
}
CSPASSIVE;
}
}
}
// Move the RX read pointer to the start of the next received packet
// This frees the memory we just read out
spi_write(ERXRDPTL, (NextPacketPtr));
spi_write(ERXRDPTH, (NextPacketPtr)>>8);
// decrement the packet counter indicate we are done with this packet
spi_write_op(ENC28J60_BIT_FIELD_SET, ECON2, ECON2_PKTDEC);
}
else
{
rt_uint32_t level;
/* lock enc28j60 */
level = rt_hw_interrupt_disable();
// switch to bank 0
enc28j60_set_bank(EIE);
// enable interrutps
spi_write_op(ENC28J60_BIT_FIELD_SET, EIE, EIE_PKTIE);
// switch to bank 0
enc28j60_set_bank(ECON1);
// enable packet reception
spi_write_op(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN);
/* enable interrupt */
rt_hw_interrupt_enable(level);
}
return p;
}
static void RCC_Configuration(void)
{
/* enable spi1 clock */
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE);
/* enable gpioa port clock */
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOD | RCC_APB2Periph_AFIO, ENABLE);
}
static void NVIC_Configuration(void)
{
NVIC_InitTypeDef NVIC_InitStructure;
/* Configure one bit for preemption priority */
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);
/* Enable the EXTI0 Interrupt */
NVIC_InitStructure.NVIC_IRQChannel = EXTI9_5_IRQChannel;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
}
static void GPIO_Configuration()
{
GPIO_InitTypeDef GPIO_InitStructure;
EXTI_InitTypeDef EXTI_InitStructure;
/* configure PA8 as external interrupt */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_Init(GPIOA, &GPIO_InitStructure);
/* Configure SPI1 pins: SCK, MISO and MOSI ----------------------------*/
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_10MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOA, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
GPIO_Init(GPIOD, &GPIO_InitStructure);
/* Connect ENC28J60 EXTI Line to GPIOB Pin 0 */
GPIO_EXTILineConfig(GPIO_PortSourceGPIOA, GPIO_PinSource8);
/* Configure ENC28J60 EXTI Line to generate an interrupt on falling edge */
EXTI_InitStructure.EXTI_Line = EXTI_Line8;
EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
EXTI_InitStructure.EXTI_LineCmd = ENABLE;
EXTI_Init(&EXTI_InitStructure);
/* Clear the Key Button EXTI line pending bit */
EXTI_ClearITPendingBit(EXTI_Line8);
}
static void SetupSPI (void)
{
SPI_InitTypeDef SPI_InitStructure;
SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4;
SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
SPI_InitStructure.SPI_CRCPolynomial = 7;
SPI_Init(SPI1, &SPI_InitStructure);
SPI_Cmd(SPI1, ENABLE);
}
static rt_timer_t enc28j60_timer;
void rt_hw_enc28j60_timeout(void* parameter)
{
// switch to bank 0
enc28j60_set_bank(EIE);
// enable interrutps
spi_write_op(ENC28J60_BIT_FIELD_SET, EIE, EIE_PKTIE);
// switch to bank 0
enc28j60_set_bank(ECON1);
// enable packet reception
spi_write_op(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN);
enc28j60_isr();
}
int rt_hw_enc28j60_init()
{
rt_err_t result;
/* configuration PB5 as INT */
RCC_Configuration();
NVIC_Configuration();
GPIO_Configuration();
SetupSPI();
/* init rt-thread device interface */
enc28j60_dev_entry.parent.parent.init = enc28j60_init;
enc28j60_dev_entry.parent.parent.open = enc28j60_open;
enc28j60_dev_entry.parent.parent.close = enc28j60_close;
enc28j60_dev_entry.parent.parent.read = enc28j60_read;
enc28j60_dev_entry.parent.parent.write = enc28j60_write;
enc28j60_dev_entry.parent.parent.control = enc28j60_control;
enc28j60_dev_entry.parent.eth_rx = enc28j60_rx;
enc28j60_dev_entry.parent.eth_tx = enc28j60_tx;
/* Update MAC address */
enc28j60_dev_entry.dev_addr[0] = 0x1e;
enc28j60_dev_entry.dev_addr[1] = 0x30;
enc28j60_dev_entry.dev_addr[2] = 0x6c;
enc28j60_dev_entry.dev_addr[3] = 0xa2;
enc28j60_dev_entry.dev_addr[4] = 0x45;
enc28j60_dev_entry.dev_addr[5] = 0x5e;
rt_sem_init(&tx_sem, "emac", 1, RT_IPC_FLAG_FIFO);
result = eth_device_init(&(enc28j60_dev->parent), "E0");
/* workaround for enc28j60 interrupt */
enc28j60_timer = rt_timer_create("etimer",
rt_hw_enc28j60_timeout, RT_NULL,
50, RT_TIMER_FLAG_PERIODIC);
if (enc28j60_timer != RT_NULL)
rt_timer_start(enc28j60_timer);
return RT_EOK;
}

256
bsp/stm32f103vb_lwip/enc28j60.h Normal file
View File

@ -0,0 +1,256 @@
#ifndef __ENC28J60_H__
#define __ENC28J60_H__
#include <rtthread.h>
// ENC28J60 Control Registers
// Control register definitions are a combination of address,
// bank number, and Ethernet/MAC/PHY indicator bits.
// - Register address (bits 0-4)
// - Bank number (bits 5-6)
// - MAC/PHY indicator (bit 7)
#define ADDR_MASK 0x1F
#define BANK_MASK 0x60
#define SPRD_MASK 0x80
// All-bank registers
#define EIE 0x1B
#define EIR 0x1C
#define ESTAT 0x1D
#define ECON2 0x1E
#define ECON1 0x1F
// Bank 0 registers
#define ERDPTL (0x00|0x00)
#define ERDPTH (0x01|0x00)
#define EWRPTL (0x02|0x00)
#define EWRPTH (0x03|0x00)
#define ETXSTL (0x04|0x00)
#define ETXSTH (0x05|0x00)
#define ETXNDL (0x06|0x00)
#define ETXNDH (0x07|0x00)
#define ERXSTL (0x08|0x00)
#define ERXSTH (0x09|0x00)
#define ERXNDL (0x0A|0x00)
#define ERXNDH (0x0B|0x00)
#define ERXRDPTL (0x0C|0x00)
#define ERXRDPTH (0x0D|0x00)
#define ERXWRPTL (0x0E|0x00)
#define ERXWRPTH (0x0F|0x00)
#define EDMASTL (0x10|0x00)
#define EDMASTH (0x11|0x00)
#define EDMANDL (0x12|0x00)
#define EDMANDH (0x13|0x00)
#define EDMADSTL (0x14|0x00)
#define EDMADSTH (0x15|0x00)
#define EDMACSL (0x16|0x00)
#define EDMACSH (0x17|0x00)
// Bank 1 registers
#define EHT0 (0x00|0x20)
#define EHT1 (0x01|0x20)
#define EHT2 (0x02|0x20)
#define EHT3 (0x03|0x20)
#define EHT4 (0x04|0x20)
#define EHT5 (0x05|0x20)
#define EHT6 (0x06|0x20)
#define EHT7 (0x07|0x20)
#define EPMM0 (0x08|0x20)
#define EPMM1 (0x09|0x20)
#define EPMM2 (0x0A|0x20)
#define EPMM3 (0x0B|0x20)
#define EPMM4 (0x0C|0x20)
#define EPMM5 (0x0D|0x20)
#define EPMM6 (0x0E|0x20)
#define EPMM7 (0x0F|0x20)
#define EPMCSL (0x10|0x20)
#define EPMCSH (0x11|0x20)
#define EPMOL (0x14|0x20)
#define EPMOH (0x15|0x20)
#define EWOLIE (0x16|0x20)
#define EWOLIR (0x17|0x20)
#define ERXFCON (0x18|0x20)
#define EPKTCNT (0x19|0x20)
// Bank 2 registers
#define MACON1 (0x00|0x40|0x80)
#define MACON2 (0x01|0x40|0x80)
#define MACON3 (0x02|0x40|0x80)
#define MACON4 (0x03|0x40|0x80)
#define MABBIPG (0x04|0x40|0x80)
#define MAIPGL (0x06|0x40|0x80)
#define MAIPGH (0x07|0x40|0x80)
#define MACLCON1 (0x08|0x40|0x80)
#define MACLCON2 (0x09|0x40|0x80)
#define MAMXFLL (0x0A|0x40|0x80)
#define MAMXFLH (0x0B|0x40|0x80)
#define MAPHSUP (0x0D|0x40|0x80)
#define MICON (0x11|0x40|0x80)
#define MICMD (0x12|0x40|0x80)
#define MIREGADR (0x14|0x40|0x80)
#define MIWRL (0x16|0x40|0x80)
#define MIWRH (0x17|0x40|0x80)
#define MIRDL (0x18|0x40|0x80)
#define MIRDH (0x19|0x40|0x80)
// Bank 3 registers
#define MAADR1 (0x00|0x60|0x80)
#define MAADR0 (0x01|0x60|0x80)
#define MAADR3 (0x02|0x60|0x80)
#define MAADR2 (0x03|0x60|0x80)
#define MAADR5 (0x04|0x60|0x80)
#define MAADR4 (0x05|0x60|0x80)
#define EBSTSD (0x06|0x60)
#define EBSTCON (0x07|0x60)
#define EBSTCSL (0x08|0x60)
#define EBSTCSH (0x09|0x60)
#define MISTAT (0x0A|0x60|0x80)
#define EREVID (0x12|0x60)
#define ECOCON (0x15|0x60)
#define EFLOCON (0x17|0x60)
#define EPAUSL (0x18|0x60)
#define EPAUSH (0x19|0x60)
// PHY registers
#define PHCON1 0x00
#define PHSTAT1 0x01
#define PHHID1 0x02
#define PHHID2 0x03
#define PHCON2 0x10
#define PHSTAT2 0x11
#define PHIE 0x12
#define PHIR 0x13
#define PHLCON 0x14
// ENC28J60 ERXFCON Register Bit Definitions
#define ERXFCON_UCEN 0x80
#define ERXFCON_ANDOR 0x40
#define ERXFCON_CRCEN 0x20
#define ERXFCON_PMEN 0x10
#define ERXFCON_MPEN 0x08
#define ERXFCON_HTEN 0x04
#define ERXFCON_MCEN 0x02
#define ERXFCON_BCEN 0x01
// ENC28J60 EIE Register Bit Definitions
#define EIE_INTIE 0x80
#define EIE_PKTIE 0x40
#define EIE_DMAIE 0x20
#define EIE_LINKIE 0x10
#define EIE_TXIE 0x08
#define EIE_WOLIE 0x04
#define EIE_TXERIE 0x02
#define EIE_RXERIE 0x01
// ENC28J60 EIR Register Bit Definitions
#define EIR_PKTIF 0x40
#define EIR_DMAIF 0x20
#define EIR_LINKIF 0x10
#define EIR_TXIF 0x08
#define EIR_WOLIF 0x04
#define EIR_TXERIF 0x02
#define EIR_RXERIF 0x01
// ENC28J60 ESTAT Register Bit Definitions
#define ESTAT_INT 0x80
#define ESTAT_LATECOL 0x10
#define ESTAT_RXBUSY 0x04
#define ESTAT_TXABRT 0x02
#define ESTAT_CLKRDY 0x01
// ENC28J60 ECON2 Register Bit Definitions
#define ECON2_AUTOINC 0x80
#define ECON2_PKTDEC 0x40
#define ECON2_PWRSV 0x20
#define ECON2_VRPS 0x08
// ENC28J60 ECON1 Register Bit Definitions
#define ECON1_TXRST 0x80
#define ECON1_RXRST 0x40
#define ECON1_DMAST 0x20
#define ECON1_CSUMEN 0x10
#define ECON1_TXRTS 0x08
#define ECON1_RXEN 0x04
#define ECON1_BSEL1 0x02
#define ECON1_BSEL0 0x01
// ENC28J60 MACON1 Register Bit Definitions
#define MACON1_LOOPBK 0x10
#define MACON1_TXPAUS 0x08
#define MACON1_RXPAUS 0x04
#define MACON1_PASSALL 0x02
#define MACON1_MARXEN 0x01
// ENC28J60 MACON2 Register Bit Definitions
#define MACON2_MARST 0x80
#define MACON2_RNDRST 0x40
#define MACON2_MARXRST 0x08
#define MACON2_RFUNRST 0x04
#define MACON2_MATXRST 0x02
#define MACON2_TFUNRST 0x01
// ENC28J60 MACON3 Register Bit Definitions
#define MACON3_PADCFG2 0x80
#define MACON3_PADCFG1 0x40
#define MACON3_PADCFG0 0x20
#define MACON3_TXCRCEN 0x10
#define MACON3_PHDRLEN 0x08
#define MACON3_HFRMLEN 0x04
#define MACON3_FRMLNEN 0x02
#define MACON3_FULDPX 0x01
// ENC28J60 MACON4 Register Bit Definitions
#define MACON4_DEFER (1<<6)
#define MACON4_BPEN (1<<5)
#define MACON4_NOBKOFF (1<<4)
// ENC28J60 MICMD Register Bit Definitions
#define MICMD_MIISCAN 0x02
#define MICMD_MIIRD 0x01
// ENC28J60 MISTAT Register Bit Definitions
#define MISTAT_NVALID 0x04
#define MISTAT_SCAN 0x02
#define MISTAT_BUSY 0x01
// ENC28J60 PHY PHCON1 Register Bit Definitions
#define PHCON1_PRST 0x8000
#define PHCON1_PLOOPBK 0x4000
#define PHCON1_PPWRSV 0x0800
#define PHCON1_PDPXMD 0x0100
// ENC28J60 PHY PHSTAT1 Register Bit Definitions
#define PHSTAT1_PFDPX 0x1000
#define PHSTAT1_PHDPX 0x0800
#define PHSTAT1_LLSTAT 0x0004
#define PHSTAT1_JBSTAT 0x0002
/* ENC28J60 PHY PHSTAT2 Register Bit Definitions */
#define PHSTAT2_TXSTAT (1 << 13)
#define PHSTAT2_RXSTAT (1 << 12)
#define PHSTAT2_COLSTAT (1 << 11)
#define PHSTAT2_LSTAT (1 << 10)
#define PHSTAT2_DPXSTAT (1 << 9)
#define PHSTAT2_PLRITY (1 << 5)
// ENC28J60 PHY PHCON2 Register Bit Definitions
#define PHCON2_FRCLINK 0x4000
#define PHCON2_TXDIS 0x2000
#define PHCON2_JABBER 0x0400
#define PHCON2_HDLDIS 0x0100
// ENC28J60 Packet Control Byte Bit Definitions
#define PKTCTRL_PHUGEEN 0x08
#define PKTCTRL_PPADEN 0x04
#define PKTCTRL_PCRCEN 0x02
#define PKTCTRL_POVERRIDE 0x01
// SPI operation codes
#define ENC28J60_READ_CTRL_REG 0x00
#define ENC28J60_READ_BUF_MEM 0x3A
#define ENC28J60_WRITE_CTRL_REG 0x40
#define ENC28J60_WRITE_BUF_MEM 0x7A
#define ENC28J60_BIT_FIELD_SET 0x80
#define ENC28J60_BIT_FIELD_CLR 0xA0
#define ENC28J60_SOFT_RESET 0xFF
// The RXSTART_INIT should be zero. See Rev. B4 Silicon Errata
// buffer boundaries applied to internal 8K ram
// the entire available packet buffer space is allocated
//
// start with recbuf at 0/
#define RXSTART_INIT 0x0
// receive buffer end
#define RXSTOP_INIT (0x1FFF-0x0600) - 1
// start TX buffer at 0x1FFF-0x0600, pace for one full ethernet frame (~1500 bytes)
#define TXSTART_INIT (0x1FFF-0x0600)
// stp TX buffer at end of mem
#define TXSTOP_INIT 0x1FFF
// max frame length which the conroller will accept:
#define MAX_FRAMELEN 1518
int rt_hw_enc28j60_init(void);
#endif

75
bsp/stm32f103vb_lwip/httpserver-netconn.c Normal file
View File

@ -0,0 +1,75 @@
#include "lwip/opt.h"
#include "lwip/arch.h"
#include "lwip/api.h"
const static char http_html_hdr[] = "HTTP/1.1 200 OK\r\nContent-type: text/html\r\n\r\n";
const static char http_index_html[] = "<html><head><title>Congrats!</title></head><body><h1>Welcome to our lwIP HTTP server!</h1><p>This is a small test page.</body></html>";
void http_server_serve(struct netconn *conn) {
struct netbuf *inbuf;
char *buf;
u16_t buflen;
/* Read the data from the port, blocking if nothing yet there.
We assume the request (the part we care about) is in one netbuf */
inbuf = netconn_recv(conn);
if (netconn_err(conn) == ERR_OK) {
netbuf_data(inbuf, &buf, &buflen);
/* Is this an HTTP GET command? (only check the first 5 chars, since
there are other formats for GET, and we're keeping it very simple )*/
if (buflen>=5 &&
buf[0]=='G' &&
buf[1]=='E' &&
buf[2]=='T' &&
buf[3]==' ' &&
buf[4]=='/' ) {
/* Send the HTML header
* subtract 1 from the size, since we dont send the \0 in the string
* NETCONN_NOCOPY: our data is const static, so no need to copy it
*/
netconn_write(conn, http_html_hdr, sizeof(http_html_hdr)-1, NETCONN_NOCOPY);
/* Send our HTML page */
netconn_write(conn, http_index_html, sizeof(http_index_html)-1, NETCONN_NOCOPY);
}
}
/* Close the connection (server closes in HTTP) */
netconn_close(conn);
/* Delete the buffer (netconn_recv gives us ownership,
so we have to make sure to deallocate the buffer) */
netbuf_delete(inbuf);
}
void http_server(void* parameter) {
struct netconn *conn, *newconn;
/* Create a new TCP connection handle */
conn = netconn_new(NETCONN_TCP);
LWIP_ERROR("http_server: invalid conn", (conn != NULL), );
/* Bind to port 80 (HTTP) with default IP address */
netconn_bind(conn, NULL, 80);
/* Put the connection into LISTEN state */
netconn_listen(conn);
while(1) {
newconn = netconn_accept(conn);
http_server_serve(newconn);
netconn_delete(newconn);
}
}
void httpd_init()
{
rt_thread_t httpd = rt_thread_create("web",
http_server, RT_NULL,
1024, 20, 8);
if (httpd != RT_NULL)
rt_thread_startup(httpd);
}

53
bsp/stm32f103vb_lwip/library/inc/cortexm3_macro.h Normal file
View File

@ -0,0 +1,53 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : cortexm3_macro.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : Header file for cortexm3_macro.s.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __CORTEXM3_MACRO_H
#define __CORTEXM3_MACRO_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_type.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void __WFI(void);
void __WFE(void);
void __SEV(void);
void __ISB(void);
void __DSB(void);
void __DMB(void);
void __SVC(void);
u32 __MRS_CONTROL(void);
void __MSR_CONTROL(u32 Control);
u32 __MRS_PSP(void);
void __MSR_PSP(u32 TopOfProcessStack);
u32 __MRS_MSP(void);
void __MSR_MSP(u32 TopOfMainStack);
void __RESETPRIMASK(void);
void __SETPRIMASK(void);
u32 __READ_PRIMASK(void);
void __RESETFAULTMASK(void);
void __SETFAULTMASK(void);
u32 __READ_FAULTMASK(void);
void __BASEPRICONFIG(u32 NewPriority);
u32 __GetBASEPRI(void);
u16 __REV_HalfWord(u16 Data);
u32 __REV_Word(u32 Data);
#endif /* __CORTEXM3_MACRO_H */
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

300
bsp/stm32f103vb_lwip/library/inc/stm32f10x_adc.h Normal file
View File

@ -0,0 +1,300 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_adc.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the functions prototypes for the
* ADC firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_ADC_H
#define __STM32F10x_ADC_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
/* Exported types ------------------------------------------------------------*/
/* ADC Init structure definition */
typedef struct
{
u32 ADC_Mode;
FunctionalState ADC_ScanConvMode;
FunctionalState ADC_ContinuousConvMode;
u32 ADC_ExternalTrigConv;
u32 ADC_DataAlign;
u8 ADC_NbrOfChannel;
}ADC_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
#define IS_ADC_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == ADC1_BASE) || \
((*(u32*)&(PERIPH)) == ADC2_BASE) || \
((*(u32*)&(PERIPH)) == ADC3_BASE))
#define IS_ADC_DMA_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == ADC1_BASE) || \
((*(u32*)&(PERIPH)) == ADC3_BASE))
/* ADC dual mode -------------------------------------------------------------*/
#define ADC_Mode_Independent ((u32)0x00000000)
#define ADC_Mode_RegInjecSimult ((u32)0x00010000)
#define ADC_Mode_RegSimult_AlterTrig ((u32)0x00020000)
#define ADC_Mode_InjecSimult_FastInterl ((u32)0x00030000)
#define ADC_Mode_InjecSimult_SlowInterl ((u32)0x00040000)
#define ADC_Mode_InjecSimult ((u32)0x00050000)
#define ADC_Mode_RegSimult ((u32)0x00060000)
#define ADC_Mode_FastInterl ((u32)0x00070000)
#define ADC_Mode_SlowInterl ((u32)0x00080000)
#define ADC_Mode_AlterTrig ((u32)0x00090000)
#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
((MODE) == ADC_Mode_RegInjecSimult) || \
((MODE) == ADC_Mode_RegSimult_AlterTrig) || \
((MODE) == ADC_Mode_InjecSimult_FastInterl) || \
((MODE) == ADC_Mode_InjecSimult_SlowInterl) || \
((MODE) == ADC_Mode_InjecSimult) || \
((MODE) == ADC_Mode_RegSimult) || \
((MODE) == ADC_Mode_FastInterl) || \
((MODE) == ADC_Mode_SlowInterl) || \
((MODE) == ADC_Mode_AlterTrig))
/* ADC extrenal trigger sources for regular channels conversion --------------*/
/* for ADC1 and ADC2 */
#define ADC_ExternalTrigConv_T1_CC1 ((u32)0x00000000)
#define ADC_ExternalTrigConv_T1_CC2 ((u32)0x00020000)
#define ADC_ExternalTrigConv_T2_CC2 ((u32)0x00060000)
#define ADC_ExternalTrigConv_T3_TRGO ((u32)0x00080000)
#define ADC_ExternalTrigConv_T4_CC4 ((u32)0x000A0000)
#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((u32)0x000C0000)
/* for ADC1, ADC2 and ADC3 */
#define ADC_ExternalTrigConv_T1_CC3 ((u32)0x00040000)
#define ADC_ExternalTrigConv_None ((u32)0x000E0000)
/* for ADC3 */
#define ADC_ExternalTrigConv_T3_CC1 ((u32)0x00000000)
#define ADC_ExternalTrigConv_T2_CC3 ((u32)0x00020000)
#define ADC_ExternalTrigConv_T8_CC1 ((u32)0x00060000)
#define ADC_ExternalTrigConv_T8_TRGO ((u32)0x00080000)
#define ADC_ExternalTrigConv_T5_CC1 ((u32)0x000A0000)
#define ADC_ExternalTrigConv_T5_CC3 ((u32)0x000C0000)
#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \
((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \
((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \
((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \
((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \
((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO) || \
((REGTRIG) == ADC_ExternalTrigConv_None) || \
((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \
((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \
((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \
((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \
((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \
((REGTRIG) == ADC_ExternalTrigConv_T5_CC3))
/* ADC data align ------------------------------------------------------------*/
#define ADC_DataAlign_Right ((u32)0x00000000)
#define ADC_DataAlign_Left ((u32)0x00000800)
#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
((ALIGN) == ADC_DataAlign_Left))
/* ADC channels --------------------------------------------------------------*/
#define ADC_Channel_0 ((u8)0x00)
#define ADC_Channel_1 ((u8)0x01)
#define ADC_Channel_2 ((u8)0x02)
#define ADC_Channel_3 ((u8)0x03)
#define ADC_Channel_4 ((u8)0x04)
#define ADC_Channel_5 ((u8)0x05)
#define ADC_Channel_6 ((u8)0x06)
#define ADC_Channel_7 ((u8)0x07)
#define ADC_Channel_8 ((u8)0x08)
#define ADC_Channel_9 ((u8)0x09)
#define ADC_Channel_10 ((u8)0x0A)
#define ADC_Channel_11 ((u8)0x0B)
#define ADC_Channel_12 ((u8)0x0C)
#define ADC_Channel_13 ((u8)0x0D)
#define ADC_Channel_14 ((u8)0x0E)
#define ADC_Channel_15 ((u8)0x0F)
#define ADC_Channel_16 ((u8)0x10)
#define ADC_Channel_17 ((u8)0x11)
#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \
((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \
((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \
((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \
((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \
((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \
((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \
((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \
((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17))
/* ADC sampling times --------------------------------------------------------*/
#define ADC_SampleTime_1Cycles5 ((u8)0x00)
#define ADC_SampleTime_7Cycles5 ((u8)0x01)
#define ADC_SampleTime_13Cycles5 ((u8)0x02)
#define ADC_SampleTime_28Cycles5 ((u8)0x03)
#define ADC_SampleTime_41Cycles5 ((u8)0x04)
#define ADC_SampleTime_55Cycles5 ((u8)0x05)
#define ADC_SampleTime_71Cycles5 ((u8)0x06)
#define ADC_SampleTime_239Cycles5 ((u8)0x07)
#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \
((TIME) == ADC_SampleTime_7Cycles5) || \
((TIME) == ADC_SampleTime_13Cycles5) || \
((TIME) == ADC_SampleTime_28Cycles5) || \
((TIME) == ADC_SampleTime_41Cycles5) || \
((TIME) == ADC_SampleTime_55Cycles5) || \
((TIME) == ADC_SampleTime_71Cycles5) || \
((TIME) == ADC_SampleTime_239Cycles5))
/* ADC extrenal trigger sources for injected channels conversion -------------*/
/* For ADC1 and ADC2 */
#define ADC_ExternalTrigInjecConv_T2_TRGO ((u32)0x00002000)
#define ADC_ExternalTrigInjecConv_T2_CC1 ((u32)0x00003000)
#define ADC_ExternalTrigInjecConv_T3_CC4 ((u32)0x00004000)
#define ADC_ExternalTrigInjecConv_T4_TRGO ((u32)0x00005000)
#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((u32)0x00006000)
/* For ADC1, ADC2 and ADC3 */
#define ADC_ExternalTrigInjecConv_T1_TRGO ((u32)0x00000000)
#define ADC_ExternalTrigInjecConv_T1_CC4 ((u32)0x00001000)
#define ADC_ExternalTrigInjecConv_None ((u32)0x00007000)
/* For ADC3 */
#define ADC_ExternalTrigInjecConv_T4_CC3 ((u32)0x00002000)
#define ADC_ExternalTrigInjecConv_T8_CC2 ((u32)0x00003000)
#define ADC_ExternalTrigInjecConv_T8_CC4 ((u32)0x00004000)
#define ADC_ExternalTrigInjecConv_T5_TRGO ((u32)0x00005000)
#define ADC_ExternalTrigInjecConv_T5_CC4 ((u32)0x00006000)
#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_None) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4))
/* ADC injected channel selection --------------------------------------------*/
#define ADC_InjectedChannel_1 ((u8)0x14)
#define ADC_InjectedChannel_2 ((u8)0x18)
#define ADC_InjectedChannel_3 ((u8)0x1C)
#define ADC_InjectedChannel_4 ((u8)0x20)
#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
((CHANNEL) == ADC_InjectedChannel_2) || \
((CHANNEL) == ADC_InjectedChannel_3) || \
((CHANNEL) == ADC_InjectedChannel_4))
/* ADC analog watchdog selection ---------------------------------------------*/
#define ADC_AnalogWatchdog_SingleRegEnable ((u32)0x00800200)
#define ADC_AnalogWatchdog_SingleInjecEnable ((u32)0x00400200)
#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((u32)0x00C00200)
#define ADC_AnalogWatchdog_AllRegEnable ((u32)0x00800000)
#define ADC_AnalogWatchdog_AllInjecEnable ((u32)0x00400000)
#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((u32)0x00C00000)
#define ADC_AnalogWatchdog_None ((u32)0x00000000)
#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_None))
/* ADC interrupts definition -------------------------------------------------*/
#define ADC_IT_EOC ((u16)0x0220)
#define ADC_IT_AWD ((u16)0x0140)
#define ADC_IT_JEOC ((u16)0x0480)
#define IS_ADC_IT(IT) ((((IT) & (u16)0xF81F) == 0x00) && ((IT) != 0x00))
#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
((IT) == ADC_IT_JEOC))
/* ADC flags definition ------------------------------------------------------*/
#define ADC_FLAG_AWD ((u8)0x01)
#define ADC_FLAG_EOC ((u8)0x02)
#define ADC_FLAG_JEOC ((u8)0x04)
#define ADC_FLAG_JSTRT ((u8)0x08)
#define ADC_FLAG_STRT ((u8)0x10)
#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (u8)0xE0) == 0x00) && ((FLAG) != 0x00))
#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \
((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \
((FLAG) == ADC_FLAG_STRT))
/* ADC thresholds ------------------------------------------------------------*/
#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
/* ADC injected offset -------------------------------------------------------*/
#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
/* ADC injected length -------------------------------------------------------*/
#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
/* ADC injected rank ---------------------------------------------------------*/
#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
/* ADC regular length --------------------------------------------------------*/
#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
/* ADC regular rank ----------------------------------------------------------*/
#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
/* ADC regular discontinuous mode number -------------------------------------*/
#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void ADC_DeInit(ADC_TypeDef* ADCx);
void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_ITConfig(ADC_TypeDef* ADCx, u16 ADC_IT, FunctionalState NewState);
void ADC_ResetCalibration(ADC_TypeDef* ADCx);
FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx);
void ADC_StartCalibration(ADC_TypeDef* ADCx);
FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);
void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, u8 Number);
void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime);
void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
u16 ADC_GetConversionValue(ADC_TypeDef* ADCx);
u32 ADC_GetDualModeConversionValue(void);
void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, u32 ADC_ExternalTrigInjecConv);
void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime);
void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, u8 Length);
void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel, u16 Offset);
u16 ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel);
void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, u32 ADC_AnalogWatchdog);
void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, u16 HighThreshold, u16 LowThreshold);
void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel);
void ADC_TempSensorVrefintCmd(FunctionalState NewState);
FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, u8 ADC_FLAG);
void ADC_ClearFlag(ADC_TypeDef* ADCx, u8 ADC_FLAG);
ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, u16 ADC_IT);
void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, u16 ADC_IT);
#endif /*__STM32F10x_ADC_H */
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

122
bsp/stm32f103vb_lwip/library/inc/stm32f10x_bkp.h Normal file
View File

@ -0,0 +1,122 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_bkp.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the functions prototypes for the
* BKP firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_BKP_H
#define __STM32F10x_BKP_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Tamper Pin active level */
#define BKP_TamperPinLevel_High ((u16)0x0000)
#define BKP_TamperPinLevel_Low ((u16)0x0001)
#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \
((LEVEL) == BKP_TamperPinLevel_Low))
/* RTC output source to output on the Tamper pin */
#define BKP_RTCOutputSource_None ((u16)0x0000)
#define BKP_RTCOutputSource_CalibClock ((u16)0x0080)
#define BKP_RTCOutputSource_Alarm ((u16)0x0100)
#define BKP_RTCOutputSource_Second ((u16)0x0300)
#define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \
((SOURCE) == BKP_RTCOutputSource_CalibClock) || \
((SOURCE) == BKP_RTCOutputSource_Alarm) || \
((SOURCE) == BKP_RTCOutputSource_Second))
/* Data Backup Register */
#define BKP_DR1 ((u16)0x0004)
#define BKP_DR2 ((u16)0x0008)
#define BKP_DR3 ((u16)0x000C)
#define BKP_DR4 ((u16)0x0010)
#define BKP_DR5 ((u16)0x0014)
#define BKP_DR6 ((u16)0x0018)
#define BKP_DR7 ((u16)0x001C)
#define BKP_DR8 ((u16)0x0020)
#define BKP_DR9 ((u16)0x0024)
#define BKP_DR10 ((u16)0x0028)
#define BKP_DR11 ((u16)0x0040)
#define BKP_DR12 ((u16)0x0044)
#define BKP_DR13 ((u16)0x0048)
#define BKP_DR14 ((u16)0x004C)
#define BKP_DR15 ((u16)0x0050)
#define BKP_DR16 ((u16)0x0054)
#define BKP_DR17 ((u16)0x0058)
#define BKP_DR18 ((u16)0x005C)
#define BKP_DR19 ((u16)0x0060)
#define BKP_DR20 ((u16)0x0064)
#define BKP_DR21 ((u16)0x0068)
#define BKP_DR22 ((u16)0x006C)
#define BKP_DR23 ((u16)0x0070)
#define BKP_DR24 ((u16)0x0074)
#define BKP_DR25 ((u16)0x0078)
#define BKP_DR26 ((u16)0x007C)
#define BKP_DR27 ((u16)0x0080)
#define BKP_DR28 ((u16)0x0084)
#define BKP_DR29 ((u16)0x0088)
#define BKP_DR30 ((u16)0x008C)
#define BKP_DR31 ((u16)0x0090)
#define BKP_DR32 ((u16)0x0094)
#define BKP_DR33 ((u16)0x0098)
#define BKP_DR34 ((u16)0x009C)
#define BKP_DR35 ((u16)0x00A0)
#define BKP_DR36 ((u16)0x00A4)
#define BKP_DR37 ((u16)0x00A8)
#define BKP_DR38 ((u16)0x00AC)
#define BKP_DR39 ((u16)0x00B0)
#define BKP_DR40 ((u16)0x00B4)
#define BKP_DR41 ((u16)0x00B8)
#define BKP_DR42 ((u16)0x00BC)
#define IS_BKP_DR(DR) (((DR) == BKP_DR1) || ((DR) == BKP_DR2) || ((DR) == BKP_DR3) || \
((DR) == BKP_DR4) || ((DR) == BKP_DR5) || ((DR) == BKP_DR6) || \
((DR) == BKP_DR7) || ((DR) == BKP_DR8) || ((DR) == BKP_DR9) || \
((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \
((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \
((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \
((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \
((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \
((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \
((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \
((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \
((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \
((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \
((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42))
#define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F)
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void BKP_DeInit(void);
void BKP_TamperPinLevelConfig(u16 BKP_TamperPinLevel);
void BKP_TamperPinCmd(FunctionalState NewState);
void BKP_ITConfig(FunctionalState NewState);
void BKP_RTCOutputConfig(u16 BKP_RTCOutputSource);
void BKP_SetRTCCalibrationValue(u8 CalibrationValue);
void BKP_WriteBackupRegister(u16 BKP_DR, u16 Data);
u16 BKP_ReadBackupRegister(u16 BKP_DR);
FlagStatus BKP_GetFlagStatus(void);
void BKP_ClearFlag(void);
ITStatus BKP_GetITStatus(void);
void BKP_ClearITPendingBit(void);
#endif /* __STM32F10x_BKP_H */
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

263
bsp/stm32f103vb_lwip/library/inc/stm32f10x_can.h Normal file
View File

@ -0,0 +1,263 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_can.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the functions prototypes for the
* CAN firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_CAN_H
#define __STM32F10x_CAN_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
/* Exported types ------------------------------------------------------------*/
/* CAN init structure definition */
typedef struct
{
FunctionalState CAN_TTCM;
FunctionalState CAN_ABOM;
FunctionalState CAN_AWUM;
FunctionalState CAN_NART;
FunctionalState CAN_RFLM;
FunctionalState CAN_TXFP;
u8 CAN_Mode;
u8 CAN_SJW;
u8 CAN_BS1;
u8 CAN_BS2;
u16 CAN_Prescaler;
} CAN_InitTypeDef;
/* CAN filter init structure definition */
typedef struct
{
u8 CAN_FilterNumber;
u8 CAN_FilterMode;
u8 CAN_FilterScale;
u16 CAN_FilterIdHigh;
u16 CAN_FilterIdLow;
u16 CAN_FilterMaskIdHigh;
u16 CAN_FilterMaskIdLow;
u16 CAN_FilterFIFOAssignment;
FunctionalState CAN_FilterActivation;
} CAN_FilterInitTypeDef;
/* CAN Tx message structure definition */
typedef struct
{
u32 StdId;
u32 ExtId;
u8 IDE;
u8 RTR;
u8 DLC;
u8 Data[8];
} CanTxMsg;
/* CAN Rx message structure definition */
typedef struct
{
u32 StdId;
u32 ExtId;
u8 IDE;
u8 RTR;
u8 DLC;
u8 Data[8];
u8 FMI;
} CanRxMsg;
/* Exported constants --------------------------------------------------------*/
/* CAN sleep constants */
#define CANINITFAILED ((u8)0x00) /* CAN initialization failed */
#define CANINITOK ((u8)0x01) /* CAN initialization failed */
/* CAN operating mode */
#define CAN_Mode_Normal ((u8)0x00) /* normal mode */
#define CAN_Mode_LoopBack ((u8)0x01) /* loopback mode */
#define CAN_Mode_Silent ((u8)0x02) /* silent mode */
#define CAN_Mode_Silent_LoopBack ((u8)0x03) /* loopback combined with silent mode */
#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || ((MODE) == CAN_Mode_LoopBack)|| \
((MODE) == CAN_Mode_Silent) || ((MODE) == CAN_Mode_Silent_LoopBack))
/* CAN synchronisation jump width */
#define CAN_SJW_1tq ((u8)0x00) /* 1 time quantum */
#define CAN_SJW_2tq ((u8)0x01) /* 2 time quantum */
#define CAN_SJW_3tq ((u8)0x02) /* 3 time quantum */
#define CAN_SJW_4tq ((u8)0x03) /* 4 time quantum */
#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \
((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))
/* time quantum in bit segment 1 */
#define CAN_BS1_1tq ((u8)0x00) /* 1 time quantum */
#define CAN_BS1_2tq ((u8)0x01) /* 2 time quantum */
#define CAN_BS1_3tq ((u8)0x02) /* 3 time quantum */
#define CAN_BS1_4tq ((u8)0x03) /* 4 time quantum */
#define CAN_BS1_5tq ((u8)0x04) /* 5 time quantum */
#define CAN_BS1_6tq ((u8)0x05) /* 6 time quantum */
#define CAN_BS1_7tq ((u8)0x06) /* 7 time quantum */
#define CAN_BS1_8tq ((u8)0x07) /* 8 time quantum */
#define CAN_BS1_9tq ((u8)0x08) /* 9 time quantum */
#define CAN_BS1_10tq ((u8)0x09) /* 10 time quantum */
#define CAN_BS1_11tq ((u8)0x0A) /* 11 time quantum */
#define CAN_BS1_12tq ((u8)0x0B) /* 12 time quantum */
#define CAN_BS1_13tq ((u8)0x0C) /* 13 time quantum */
#define CAN_BS1_14tq ((u8)0x0D) /* 14 time quantum */
#define CAN_BS1_15tq ((u8)0x0E) /* 15 time quantum */
#define CAN_BS1_16tq ((u8)0x0F) /* 16 time quantum */
#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq)
/* time quantum in bit segment 2 */
#define CAN_BS2_1tq ((u8)0x00) /* 1 time quantum */
#define CAN_BS2_2tq ((u8)0x01) /* 2 time quantum */
#define CAN_BS2_3tq ((u8)0x02) /* 3 time quantum */
#define CAN_BS2_4tq ((u8)0x03) /* 4 time quantum */
#define CAN_BS2_5tq ((u8)0x04) /* 5 time quantum */
#define CAN_BS2_6tq ((u8)0x05) /* 6 time quantum */
#define CAN_BS2_7tq ((u8)0x06) /* 7 time quantum */
#define CAN_BS2_8tq ((u8)0x07) /* 8 time quantum */
#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq)
/* CAN clock prescaler */
#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
/* CAN filter number */
#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13)
/* CAN filter mode */
#define CAN_FilterMode_IdMask ((u8)0x00) /* id/mask mode */
#define CAN_FilterMode_IdList ((u8)0x01) /* identifier list mode */
#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \
((MODE) == CAN_FilterMode_IdList))
/* CAN filter scale */
#define CAN_FilterScale_16bit ((u8)0x00) /* 16-bit filter scale */
#define CAN_FilterScale_32bit ((u8)0x01) /* 2-bit filter scale */
#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \
((SCALE) == CAN_FilterScale_32bit))
/* CAN filter FIFO assignation */
#define CAN_FilterFIFO0 ((u8)0x00) /* Filter FIFO 0 assignment for filter x */
#define CAN_FilterFIFO1 ((u8)0x01) /* Filter FIFO 1 assignment for filter x */
#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \
((FIFO) == CAN_FilterFIFO1))
/* CAN Tx */
#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((u8)0x02))
#define IS_CAN_STDID(STDID) ((STDID) <= ((u32)0x7FF))
#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((u32)0x1FFFFFFF))
#define IS_CAN_DLC(DLC) ((DLC) <= ((u8)0x08))
/* CAN identifier type */
#define CAN_ID_STD ((u32)0x00000000) /* Standard Id */
#define CAN_ID_EXT ((u32)0x00000004) /* Extended Id */
#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || ((IDTYPE) == CAN_ID_EXT))
/* CAN remote transmission request */
#define CAN_RTR_DATA ((u32)0x00000000) /* Data frame */
#define CAN_RTR_REMOTE ((u32)0x00000002) /* Remote frame */
#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
/* CAN transmit constants */
#define CANTXFAILED ((u8)0x00) /* CAN transmission failed */
#define CANTXOK ((u8)0x01) /* CAN transmission succeeded */
#define CANTXPENDING ((u8)0x02) /* CAN transmission pending */
#define CAN_NO_MB ((u8)0x04) /* CAN cell did not provide an empty mailbox */
/* CAN receive FIFO number constants */
#define CAN_FIFO0 ((u8)0x00) /* CAN FIFO0 used to receive */
#define CAN_FIFO1 ((u8)0x01) /* CAN FIFO1 used to receive */
#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
/* CAN sleep constants */
#define CANSLEEPFAILED ((u8)0x00) /* CAN did not enter the sleep mode */
#define CANSLEEPOK ((u8)0x01) /* CAN entered the sleep mode */
/* CAN wake up constants */
#define CANWAKEUPFAILED ((u8)0x00) /* CAN did not leave the sleep mode */
#define CANWAKEUPOK ((u8)0x01) /* CAN leaved the sleep mode */
/* CAN flags */
#define CAN_FLAG_EWG ((u32)0x00000001) /* Error Warning Flag */
#define CAN_FLAG_EPV ((u32)0x00000002) /* Error Passive Flag */
#define CAN_FLAG_BOF ((u32)0x00000004) /* Bus-Off Flag */
#define IS_CAN_FLAG(FLAG) (((FLAG) == CAN_FLAG_EWG) || ((FLAG) == CAN_FLAG_EPV) ||\
((FLAG) == CAN_FLAG_BOF))
/* CAN interrupts */
#define CAN_IT_RQCP0 ((u32)0x00000005) /* Request completed mailbox 0 */
#define CAN_IT_RQCP1 ((u32)0x00000006) /* Request completed mailbox 1 */
#define CAN_IT_RQCP2 ((u32)0x00000007) /* Request completed mailbox 2 */
#define CAN_IT_TME ((u32)0x00000001) /* Transmit mailbox empty */
#define CAN_IT_FMP0 ((u32)0x00000002) /* FIFO 0 message pending */
#define CAN_IT_FF0 ((u32)0x00000004) /* FIFO 0 full */
#define CAN_IT_FOV0 ((u32)0x00000008) /* FIFO 0 overrun */
#define CAN_IT_FMP1 ((u32)0x00000010) /* FIFO 1 message pending */
#define CAN_IT_FF1 ((u32)0x00000020) /* FIFO 1 full */
#define CAN_IT_FOV1 ((u32)0x00000040) /* FIFO 1 overrun */
#define CAN_IT_EWG ((u32)0x00000100) /* Error warning */
#define CAN_IT_EPV ((u32)0x00000200) /* Error passive */
#define CAN_IT_BOF ((u32)0x00000400) /* Bus-off */
#define CAN_IT_LEC ((u32)0x00000800) /* Last error code */
#define CAN_IT_ERR ((u32)0x00008000) /* Error */
#define CAN_IT_WKU ((u32)0x00010000) /* Wake-up */
#define CAN_IT_SLK ((u32)0x00020000) /* Sleep */
#define IS_CAN_ITConfig(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\
((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\
((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\
((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
#define IS_CAN_ITStatus(IT) (((IT) == CAN_IT_RQCP0) || ((IT) == CAN_IT_RQCP1) ||\
((IT) == CAN_IT_RQCP2) || ((IT) == CAN_IT_FF0) ||\
((IT) == CAN_IT_FOV0) || ((IT) == CAN_IT_FF1) ||\
((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
/* Exported macro ------------------------------------------------------------*/
/* Exported function protypes ----------------------------------------------- */
void CAN_DeInit(void);
u8 CAN_Init(CAN_InitTypeDef* CAN_InitStruct);
void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
void CAN_ITConfig(u32 CAN_IT, FunctionalState NewState);
u8 CAN_Transmit(CanTxMsg* TxMessage);
u8 CAN_TransmitStatus(u8 TransmitMailbox);
void CAN_CancelTransmit(u8 Mailbox);
void CAN_FIFORelease(u8 FIFONumber);
u8 CAN_MessagePending(u8 FIFONumber);
void CAN_Receive(u8 FIFONumber, CanRxMsg* RxMessage);
u8 CAN_Sleep(void);
u8 CAN_WakeUp(void);
FlagStatus CAN_GetFlagStatus(u32 CAN_FLAG);
void CAN_ClearFlag(u32 CAN_FLAG);
ITStatus CAN_GetITStatus(u32 CAN_IT);
void CAN_ClearITPendingBit(u32 CAN_IT);
#endif /* __STM32F10x_CAN_H */
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

37
bsp/stm32f103vb_lwip/library/inc/stm32f10x_crc.h Normal file
View File

@ -0,0 +1,37 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_crc.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the functions prototypes for the
* CRC firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_CRC_H
#define __STM32F10x_CRC_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void CRC_ResetDR(void);
u32 CRC_CalcCRC(u32 Data);
u32 CRC_CalcBlockCRC(u32 pBuffer[], u32 BufferLength);
u32 CRC_GetCRC(void);
void CRC_SetIDRegister(u8 IDValue);
u8 CRC_GetIDRegister(void);
#endif /* __STM32F10x_CRC_H */
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

167
bsp/stm32f103vb_lwip/library/inc/stm32f10x_dac.h Normal file
View File

@ -0,0 +1,167 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_dac.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the functions prototypes for the
* DAC firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_DAC_H
#define __STM32F10x_DAC_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
/* Exported types ------------------------------------------------------------*/
/* DAC Init structure definition */
typedef struct
{
u32 DAC_Trigger;
u32 DAC_WaveGeneration;
u32 DAC_LFSRUnmask_TriangleAmplitude;
u32 DAC_OutputBuffer;
}DAC_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
/* DAC trigger selection */
#define DAC_Trigger_None ((u32)0x00000000)
#define DAC_Trigger_T6_TRGO ((u32)0x00000004)
#define DAC_Trigger_T8_TRGO ((u32)0x0000000C)
#define DAC_Trigger_T7_TRGO ((u32)0x00000014)
#define DAC_Trigger_T5_TRGO ((u32)0x0000001C)
#define DAC_Trigger_T2_TRGO ((u32)0x00000024)
#define DAC_Trigger_T4_TRGO ((u32)0x0000002C)
#define DAC_Trigger_Ext_IT9 ((u32)0x00000034)
#define DAC_Trigger_Software ((u32)0x0000003C)
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
((TRIGGER) == DAC_Trigger_T6_TRGO) || \
((TRIGGER) == DAC_Trigger_T8_TRGO) || \
((TRIGGER) == DAC_Trigger_T7_TRGO) || \
((TRIGGER) == DAC_Trigger_T5_TRGO) || \
((TRIGGER) == DAC_Trigger_T2_TRGO) || \
((TRIGGER) == DAC_Trigger_T4_TRGO) || \
((TRIGGER) == DAC_Trigger_Ext_IT9) || \
((TRIGGER) == DAC_Trigger_Software))
/* DAC wave generation */
#define DAC_WaveGeneration_None ((u32)0x00000000)
#define DAC_WaveGeneration_Noise ((u32)0x00000040)
#define DAC_WaveGeneration_Triangle ((u32)0x00000080)
#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
((WAVE) == DAC_WaveGeneration_Noise) || \
((WAVE) == DAC_WaveGeneration_Triangle))
/* DAC noise wave generation mask / triangle wave generation max amplitude */
#define DAC_LFSRUnmask_Bit0 ((u32)0x00000000)
#define DAC_LFSRUnmask_Bits1_0 ((u32)0x00000100)
#define DAC_LFSRUnmask_Bits2_0 ((u32)0x00000200)
#define DAC_LFSRUnmask_Bits3_0 ((u32)0x00000300)
#define DAC_LFSRUnmask_Bits4_0 ((u32)0x00000400)
#define DAC_LFSRUnmask_Bits5_0 ((u32)0x00000500)
#define DAC_LFSRUnmask_Bits6_0 ((u32)0x00000600)
#define DAC_LFSRUnmask_Bits7_0 ((u32)0x00000700)
#define DAC_LFSRUnmask_Bits8_0 ((u32)0x00000800)
#define DAC_LFSRUnmask_Bits9_0 ((u32)0x00000900)
#define DAC_LFSRUnmask_Bits10_0 ((u32)0x00000A00)
#define DAC_LFSRUnmask_Bits11_0 ((u32)0x00000B00)
#define DAC_TriangleAmplitude_1 ((u32)0x00000000)
#define DAC_TriangleAmplitude_3 ((u32)0x00000100)
#define DAC_TriangleAmplitude_7 ((u32)0x00000200)
#define DAC_TriangleAmplitude_15 ((u32)0x00000300)
#define DAC_TriangleAmplitude_31 ((u32)0x00000400)
#define DAC_TriangleAmplitude_63 ((u32)0x00000500)
#define DAC_TriangleAmplitude_127 ((u32)0x00000600)
#define DAC_TriangleAmplitude_255 ((u32)0x00000700)
#define DAC_TriangleAmplitude_511 ((u32)0x00000800)
#define DAC_TriangleAmplitude_1023 ((u32)0x00000900)
#define DAC_TriangleAmplitude_2047 ((u32)0x00000A00)
#define DAC_TriangleAmplitude_4095 ((u32)0x00000B00)
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
((VALUE) == DAC_TriangleAmplitude_1) || \
((VALUE) == DAC_TriangleAmplitude_3) || \
((VALUE) == DAC_TriangleAmplitude_7) || \
((VALUE) == DAC_TriangleAmplitude_15) || \
((VALUE) == DAC_TriangleAmplitude_31) || \
((VALUE) == DAC_TriangleAmplitude_63) || \
((VALUE) == DAC_TriangleAmplitude_127) || \
((VALUE) == DAC_TriangleAmplitude_255) || \
((VALUE) == DAC_TriangleAmplitude_511) || \
((VALUE) == DAC_TriangleAmplitude_1023) || \
((VALUE) == DAC_TriangleAmplitude_2047) || \
((VALUE) == DAC_TriangleAmplitude_4095))
/* DAC output buffer */
#define DAC_OutputBuffer_Enable ((u32)0x00000000)
#define DAC_OutputBuffer_Disable ((u32)0x00000002)
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
((STATE) == DAC_OutputBuffer_Disable))
/* DAC Channel selection */
#define DAC_Channel_1 ((u32)0x00000000)
#define DAC_Channel_2 ((u32)0x00000010)
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
((CHANNEL) == DAC_Channel_2))
/* DAC data alignement */
#define DAC_Align_12b_R ((u32)0x00000000)
#define DAC_Align_12b_L ((u32)0x00000004)
#define DAC_Align_8b_R ((u32)0x00000008)
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
((ALIGN) == DAC_Align_12b_L) || \
((ALIGN) == DAC_Align_8b_R))
/* DAC wave generation */
#define DAC_Wave_Noise ((u32)0x00000040)
#define DAC_Wave_Triangle ((u32)0x00000080)
#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
((WAVE) == DAC_Wave_Triangle))
/* DAC data ------------------------------------------------------------------*/
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
void DAC_DeInit(void);
void DAC_Init(u32 DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
void DAC_Cmd(u32 DAC_Channel, FunctionalState NewState);
void DAC_DMACmd(u32 DAC_Channel, FunctionalState NewState);
void DAC_SoftwareTriggerCmd(u32 DAC_Channel, FunctionalState NewState);
void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
void DAC_WaveGenerationCmd(u32 DAC_Channel, u32 DAC_Wave, FunctionalState NewState);
void DAC_SetChannel1Data(u32 DAC_Align, u16 Data);
void DAC_SetChannel2Data(u32 DAC_Align, u16 Data);
void DAC_SetDualChannelData(u32 DAC_Align, u16 Data2, u16 Data1);
u16 DAC_GetDataOutputValue(u32 DAC_Channel);
#endif /*__STM32F10x_DAC_H */
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

55
bsp/stm32f103vb_lwip/library/inc/stm32f10x_dbgmcu.h Normal file
View File

@ -0,0 +1,55 @@
/******************** (C) COPYRIGHT 2009 STMicroelectronics ********************
* File Name : stm32f10x_dbgmcu.h
* Author : MCD Application Team
* Version : V2.0.3Patch1
* Date : 04/06/2009
* Description : This file contains all the functions prototypes for the
* DBGMCU firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_DBGMCU_H
#define __STM32F10x_DBGMCU_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
#define DBGMCU_SLEEP ((u32)0x00000001)
#define DBGMCU_STOP ((u32)0x00000002)
#define DBGMCU_STANDBY ((u32)0x00000004)
#define DBGMCU_IWDG_STOP ((u32)0x00000100)
#define DBGMCU_WWDG_STOP ((u32)0x00000200)
#define DBGMCU_TIM1_STOP ((u32)0x00000400)
#define DBGMCU_TIM2_STOP ((u32)0x00000800)
#define DBGMCU_TIM3_STOP ((u32)0x00001000)
#define DBGMCU_TIM4_STOP ((u32)0x00002000)
#define DBGMCU_CAN_STOP ((u32)0x00004000)
#define DBGMCU_I2C1_SMBUS_TIMEOUT ((u32)0x00008000)
#define DBGMCU_I2C2_SMBUS_TIMEOUT ((u32)0x00010000)
#define DBGMCU_TIM8_STOP ((u32)0x00020000)
#define DBGMCU_TIM5_STOP ((u32)0x00040000)
#define DBGMCU_TIM6_STOP ((u32)0x00080000)
#define DBGMCU_TIM7_STOP ((u32)0x00100000)
#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFE000F8) == 0x00) && ((PERIPH) != 0x00))
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
u32 DBGMCU_GetREVID(void);
u32 DBGMCU_GetDEVID(void);
void DBGMCU_Config(u32 DBGMCU_Periph, FunctionalState NewState);
#endif /* __STM32F10x_DBGMCU_H */
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

297
bsp/stm32f103vb_lwip/library/inc/stm32f10x_dma.h Normal file
View File

@ -0,0 +1,297 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_dma.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the functions prototypes for the
* DMA firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_DMA_H
#define __STM32F10x_DMA_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
/* Exported types ------------------------------------------------------------*/
/* DMA Init structure definition */
typedef struct
{
u32 DMA_PeripheralBaseAddr;
u32 DMA_MemoryBaseAddr;
u32 DMA_DIR;
u32 DMA_BufferSize;
u32 DMA_PeripheralInc;
u32 DMA_MemoryInc;
u32 DMA_PeripheralDataSize;
u32 DMA_MemoryDataSize;
u32 DMA_Mode;
u32 DMA_Priority;
u32 DMA_M2M;
}DMA_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
#define IS_DMA_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == DMA1_Channel1_BASE) || \
((*(u32*)&(PERIPH)) == DMA1_Channel2_BASE) || \
((*(u32*)&(PERIPH)) == DMA1_Channel3_BASE) || \
((*(u32*)&(PERIPH)) == DMA1_Channel4_BASE) || \
((*(u32*)&(PERIPH)) == DMA1_Channel5_BASE) || \
((*(u32*)&(PERIPH)) == DMA1_Channel6_BASE) || \
((*(u32*)&(PERIPH)) == DMA1_Channel7_BASE) || \
((*(u32*)&(PERIPH)) == DMA2_Channel1_BASE) || \
((*(u32*)&(PERIPH)) == DMA2_Channel2_BASE) || \
((*(u32*)&(PERIPH)) == DMA2_Channel3_BASE) || \
((*(u32*)&(PERIPH)) == DMA2_Channel4_BASE) || \
((*(u32*)&(PERIPH)) == DMA2_Channel5_BASE))
/* DMA data transfer direction -----------------------------------------------*/
#define DMA_DIR_PeripheralDST ((u32)0x00000010)
#define DMA_DIR_PeripheralSRC ((u32)0x00000000)
#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \
((DIR) == DMA_DIR_PeripheralSRC))
/* DMA peripheral incremented mode -------------------------------------------*/
#define DMA_PeripheralInc_Enable ((u32)0x00000040)
#define DMA_PeripheralInc_Disable ((u32)0x00000000)
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
((STATE) == DMA_PeripheralInc_Disable))
/* DMA memory incremented mode -----------------------------------------------*/
#define DMA_MemoryInc_Enable ((u32)0x00000080)
#define DMA_MemoryInc_Disable ((u32)0x00000000)
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
((STATE) == DMA_MemoryInc_Disable))
/* DMA peripheral data size --------------------------------------------------*/
#define DMA_PeripheralDataSize_Byte ((u32)0x00000000)
#define DMA_PeripheralDataSize_HalfWord ((u32)0x00000100)
#define DMA_PeripheralDataSize_Word ((u32)0x00000200)
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
((SIZE) == DMA_PeripheralDataSize_Word))
/* DMA memory data size ------------------------------------------------------*/
#define DMA_MemoryDataSize_Byte ((u32)0x00000000)
#define DMA_MemoryDataSize_HalfWord ((u32)0x00000400)
#define DMA_MemoryDataSize_Word ((u32)0x00000800)
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
((SIZE) == DMA_MemoryDataSize_HalfWord) || \
((SIZE) == DMA_MemoryDataSize_Word))
/* DMA circular/normal mode --------------------------------------------------*/
#define DMA_Mode_Circular ((u32)0x00000020)
#define DMA_Mode_Normal ((u32)0x00000000)
#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))
/* DMA priority level --------------------------------------------------------*/
#define DMA_Priority_VeryHigh ((u32)0x00003000)
#define DMA_Priority_High ((u32)0x00002000)
#define DMA_Priority_Medium ((u32)0x00001000)
#define DMA_Priority_Low ((u32)0x00000000)
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
((PRIORITY) == DMA_Priority_High) || \
((PRIORITY) == DMA_Priority_Medium) || \
((PRIORITY) == DMA_Priority_Low))
/* DMA memory to memory ------------------------------------------------------*/
#define DMA_M2M_Enable ((u32)0x00004000)
#define DMA_M2M_Disable ((u32)0x00000000)
#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))
/* DMA interrupts definition -------------------------------------------------*/
#define DMA_IT_TC ((u32)0x00000002)
#define DMA_IT_HT ((u32)0x00000004)
#define DMA_IT_TE ((u32)0x00000008)
#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
/* For DMA1 */
#define DMA1_IT_GL1 ((u32)0x00000001)
#define DMA1_IT_TC1 ((u32)0x00000002)
#define DMA1_IT_HT1 ((u32)0x00000004)
#define DMA1_IT_TE1 ((u32)0x00000008)
#define DMA1_IT_GL2 ((u32)0x00000010)
#define DMA1_IT_TC2 ((u32)0x00000020)
#define DMA1_IT_HT2 ((u32)0x00000040)
#define DMA1_IT_TE2 ((u32)0x00000080)
#define DMA1_IT_GL3 ((u32)0x00000100)
#define DMA1_IT_TC3 ((u32)0x00000200)
#define DMA1_IT_HT3 ((u32)0x00000400)
#define DMA1_IT_TE3 ((u32)0x00000800)
#define DMA1_IT_GL4 ((u32)0x00001000)
#define DMA1_IT_TC4 ((u32)0x00002000)
#define DMA1_IT_HT4 ((u32)0x00004000)
#define DMA1_IT_TE4 ((u32)0x00008000)
#define DMA1_IT_GL5 ((u32)0x00010000)
#define DMA1_IT_TC5 ((u32)0x00020000)
#define DMA1_IT_HT5 ((u32)0x00040000)
#define DMA1_IT_TE5 ((u32)0x00080000)
#define DMA1_IT_GL6 ((u32)0x00100000)
#define DMA1_IT_TC6 ((u32)0x00200000)
#define DMA1_IT_HT6 ((u32)0x00400000)
#define DMA1_IT_TE6 ((u32)0x00800000)
#define DMA1_IT_GL7 ((u32)0x01000000)
#define DMA1_IT_TC7 ((u32)0x02000000)
#define DMA1_IT_HT7 ((u32)0x04000000)
#define DMA1_IT_TE7 ((u32)0x08000000)
/* For DMA2 */
#define DMA2_IT_GL1 ((u32)0x10000001)
#define DMA2_IT_TC1 ((u32)0x10000002)
#define DMA2_IT_HT1 ((u32)0x10000004)
#define DMA2_IT_TE1 ((u32)0x10000008)
#define DMA2_IT_GL2 ((u32)0x10000010)
#define DMA2_IT_TC2 ((u32)0x10000020)
#define DMA2_IT_HT2 ((u32)0x10000040)
#define DMA2_IT_TE2 ((u32)0x10000080)
#define DMA2_IT_GL3 ((u32)0x10000100)
#define DMA2_IT_TC3 ((u32)0x10000200)
#define DMA2_IT_HT3 ((u32)0x10000400)
#define DMA2_IT_TE3 ((u32)0x10000800)
#define DMA2_IT_GL4 ((u32)0x10001000)
#define DMA2_IT_TC4 ((u32)0x10002000)
#define DMA2_IT_HT4 ((u32)0x10004000)
#define DMA2_IT_TE4 ((u32)0x10008000)
#define DMA2_IT_GL5 ((u32)0x10010000)
#define DMA2_IT_TC5 ((u32)0x10020000)
#define DMA2_IT_HT5 ((u32)0x10040000)
#define DMA2_IT_TE5 ((u32)0x10080000)
#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \
((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \
((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \
((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \
((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \
((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \
((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \
((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \
((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))
/* DMA flags definition ------------------------------------------------------*/
/* For DMA1 */
#define DMA1_FLAG_GL1 ((u32)0x00000001)
#define DMA1_FLAG_TC1 ((u32)0x00000002)
#define DMA1_FLAG_HT1 ((u32)0x00000004)
#define DMA1_FLAG_TE1 ((u32)0x00000008)
#define DMA1_FLAG_GL2 ((u32)0x00000010)
#define DMA1_FLAG_TC2 ((u32)0x00000020)
#define DMA1_FLAG_HT2 ((u32)0x00000040)
#define DMA1_FLAG_TE2 ((u32)0x00000080)
#define DMA1_FLAG_GL3 ((u32)0x00000100)
#define DMA1_FLAG_TC3 ((u32)0x00000200)
#define DMA1_FLAG_HT3 ((u32)0x00000400)
#define DMA1_FLAG_TE3 ((u32)0x00000800)
#define DMA1_FLAG_GL4 ((u32)0x00001000)
#define DMA1_FLAG_TC4 ((u32)0x00002000)
#define DMA1_FLAG_HT4 ((u32)0x00004000)
#define DMA1_FLAG_TE4 ((u32)0x00008000)
#define DMA1_FLAG_GL5 ((u32)0x00010000)
#define DMA1_FLAG_TC5 ((u32)0x00020000)
#define DMA1_FLAG_HT5 ((u32)0x00040000)
#define DMA1_FLAG_TE5 ((u32)0x00080000)
#define DMA1_FLAG_GL6 ((u32)0x00100000)
#define DMA1_FLAG_TC6 ((u32)0x00200000)
#define DMA1_FLAG_HT6 ((u32)0x00400000)
#define DMA1_FLAG_TE6 ((u32)0x00800000)
#define DMA1_FLAG_GL7 ((u32)0x01000000)
#define DMA1_FLAG_TC7 ((u32)0x02000000)
#define DMA1_FLAG_HT7 ((u32)0x04000000)
#define DMA1_FLAG_TE7 ((u32)0x08000000)
/* For DMA2 */
#define DMA2_FLAG_GL1 ((u32)0x10000001)
#define DMA2_FLAG_TC1 ((u32)0x10000002)
#define DMA2_FLAG_HT1 ((u32)0x10000004)
#define DMA2_FLAG_TE1 ((u32)0x10000008)
#define DMA2_FLAG_GL2 ((u32)0x10000010)
#define DMA2_FLAG_TC2 ((u32)0x10000020)
#define DMA2_FLAG_HT2 ((u32)0x10000040)
#define DMA2_FLAG_TE2 ((u32)0x10000080)
#define DMA2_FLAG_GL3 ((u32)0x10000100)
#define DMA2_FLAG_TC3 ((u32)0x10000200)
#define DMA2_FLAG_HT3 ((u32)0x10000400)
#define DMA2_FLAG_TE3 ((u32)0x10000800)
#define DMA2_FLAG_GL4 ((u32)0x10001000)
#define DMA2_FLAG_TC4 ((u32)0x10002000)
#define DMA2_FLAG_HT4 ((u32)0x10004000)
#define DMA2_FLAG_TE4 ((u32)0x10008000)
#define DMA2_FLAG_GL5 ((u32)0x10010000)
#define DMA2_FLAG_TC5 ((u32)0x10020000)
#define DMA2_FLAG_HT5 ((u32)0x10040000)
#define DMA2_FLAG_TE5 ((u32)0x10080000)
#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \
((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \
((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \
((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \
((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))
/* DMA Buffer Size -----------------------------------------------------------*/
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, u32 DMA_IT, FunctionalState NewState);
u16 DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
FlagStatus DMA_GetFlagStatus(u32 DMA_FLAG);
void DMA_ClearFlag(u32 DMA_FLAG);
ITStatus DMA_GetITStatus(u32 DMA_IT);
void DMA_ClearITPendingBit(u32 DMA_IT);
#endif /*__STM32F10x_DMA_H */
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

107
bsp/stm32f103vb_lwip/library/inc/stm32f10x_exti.h Normal file
View File

@ -0,0 +1,107 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_exti.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the functions prototypes for the
* EXTI firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_EXTI_H
#define __STM32F10x_EXTI_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
/* Exported types ------------------------------------------------------------*/
/* EXTI mode enumeration -----------------------------------------------------*/
typedef enum
{
EXTI_Mode_Interrupt = 0x00,
EXTI_Mode_Event = 0x04
}EXTIMode_TypeDef;
#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
/* EXTI Trigger enumeration --------------------------------------------------*/
typedef enum
{
EXTI_Trigger_Rising = 0x08,
EXTI_Trigger_Falling = 0x0C,
EXTI_Trigger_Rising_Falling = 0x10
}EXTITrigger_TypeDef;
#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
((TRIGGER) == EXTI_Trigger_Falling) || \
((TRIGGER) == EXTI_Trigger_Rising_Falling))
/* EXTI Init Structure definition --------------------------------------------*/
typedef struct
{
u32 EXTI_Line;
EXTIMode_TypeDef EXTI_Mode;
EXTITrigger_TypeDef EXTI_Trigger;
FunctionalState EXTI_LineCmd;
}EXTI_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
/* EXTI Lines ----------------------------------------------------------------*/
#define EXTI_Line0 ((u32)0x00001) /* External interrupt line 0 */
#define EXTI_Line1 ((u32)0x00002) /* External interrupt line 1 */
#define EXTI_Line2 ((u32)0x00004) /* External interrupt line 2 */
#define EXTI_Line3 ((u32)0x00008) /* External interrupt line 3 */
#define EXTI_Line4 ((u32)0x00010) /* External interrupt line 4 */
#define EXTI_Line5 ((u32)0x00020) /* External interrupt line 5 */
#define EXTI_Line6 ((u32)0x00040) /* External interrupt line 6 */
#define EXTI_Line7 ((u32)0x00080) /* External interrupt line 7 */
#define EXTI_Line8 ((u32)0x00100) /* External interrupt line 8 */
#define EXTI_Line9 ((u32)0x00200) /* External interrupt line 9 */
#define EXTI_Line10 ((u32)0x00400) /* External interrupt line 10 */
#define EXTI_Line11 ((u32)0x00800) /* External interrupt line 11 */
#define EXTI_Line12 ((u32)0x01000) /* External interrupt line 12 */
#define EXTI_Line13 ((u32)0x02000) /* External interrupt line 13 */
#define EXTI_Line14 ((u32)0x04000) /* External interrupt line 14 */
#define EXTI_Line15 ((u32)0x08000) /* External interrupt line 15 */
#define EXTI_Line16 ((u32)0x10000) /* External interrupt line 16
Connected to the PVD Output */
#define EXTI_Line17 ((u32)0x20000) /* External interrupt line 17
Connected to the RTC Alarm event */
#define EXTI_Line18 ((u32)0x40000) /* External interrupt line 18
Connected to the USB Wakeup from
suspend event */
#define IS_EXTI_LINE(LINE) ((((LINE) & (u32)0xFFF80000) == 0x00) && ((LINE) != (u16)0x00))
#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
((LINE) == EXTI_Line18))
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void EXTI_DeInit(void);
void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
void EXTI_GenerateSWInterrupt(u32 EXTI_Line);
FlagStatus EXTI_GetFlagStatus(u32 EXTI_Line);
void EXTI_ClearFlag(u32 EXTI_Line);
ITStatus EXTI_GetITStatus(u32 EXTI_Line);
void EXTI_ClearITPendingBit(u32 EXTI_Line);
#endif /* __STM32F10x_EXTI_H */
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

208
bsp/stm32f103vb_lwip/library/inc/stm32f10x_flash.h Normal file
View File

@ -0,0 +1,208 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_flash.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the functions prototypes for the
* FLASH firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_FLASH_H
#define __STM32F10x_FLASH_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
/* Exported types ------------------------------------------------------------*/
#ifdef _FLASH_PROG
/* FLASH Status */
typedef enum
{
FLASH_BUSY = 1,
FLASH_ERROR_PG,
FLASH_ERROR_WRP,
FLASH_COMPLETE,
FLASH_TIMEOUT
}FLASH_Status;
#endif
/* Flash Latency -------------------------------------------------------------*/
#define FLASH_Latency_0 ((u32)0x00000000) /* FLASH Zero Latency cycle */
#define FLASH_Latency_1 ((u32)0x00000001) /* FLASH One Latency cycle */
#define FLASH_Latency_2 ((u32)0x00000002) /* FLASH Two Latency cycles */
#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
((LATENCY) == FLASH_Latency_1) || \
((LATENCY) == FLASH_Latency_2))
/* Half Cycle Enable/Disable -------------------------------------------------*/
#define FLASH_HalfCycleAccess_Enable ((u32)0x00000008) /* FLASH Half Cycle Enable */
#define FLASH_HalfCycleAccess_Disable ((u32)0x00000000) /* FLASH Half Cycle Disable */
#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \
((STATE) == FLASH_HalfCycleAccess_Disable))
/* Prefetch Buffer Enable/Disable --------------------------------------------*/
#define FLASH_PrefetchBuffer_Enable ((u32)0x00000010) /* FLASH Prefetch Buffer Enable */
#define FLASH_PrefetchBuffer_Disable ((u32)0x00000000) /* FLASH Prefetch Buffer Disable */
#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \
((STATE) == FLASH_PrefetchBuffer_Disable))
#ifdef _FLASH_PROG
/* Option Bytes Write Protection ---------------------------------------------*/
/* Values to be used with STM32F10Xxx Medium-density devices: FLASH memory density
ranges between 32 and 128 Kbytes with page size equal to 1 Kbytes */
#define FLASH_WRProt_Pages0to3 ((u32)0x00000001) /* Write protection of page 0 to 3 */
#define FLASH_WRProt_Pages4to7 ((u32)0x00000002) /* Write protection of page 4 to 7 */
#define FLASH_WRProt_Pages8to11 ((u32)0x00000004) /* Write protection of page 8 to 11 */
#define FLASH_WRProt_Pages12to15 ((u32)0x00000008) /* Write protection of page 12 to 15 */
#define FLASH_WRProt_Pages16to19 ((u32)0x00000010) /* Write protection of page 16 to 19 */
#define FLASH_WRProt_Pages20to23 ((u32)0x00000020) /* Write protection of page 20 to 23 */
#define FLASH_WRProt_Pages24to27 ((u32)0x00000040) /* Write protection of page 24 to 27 */
#define FLASH_WRProt_Pages28to31 ((u32)0x00000080) /* Write protection of page 28 to 31 */
#define FLASH_WRProt_Pages32to35 ((u32)0x00000100) /* Write protection of page 32 to 35 */
#define FLASH_WRProt_Pages36to39 ((u32)0x00000200) /* Write protection of page 36 to 39 */
#define FLASH_WRProt_Pages40to43 ((u32)0x00000400) /* Write protection of page 40 to 43 */
#define FLASH_WRProt_Pages44to47 ((u32)0x00000800) /* Write protection of page 44 to 47 */
#define FLASH_WRProt_Pages48to51 ((u32)0x00001000) /* Write protection of page 48 to 51 */
#define FLASH_WRProt_Pages52to55 ((u32)0x00002000) /* Write protection of page 52 to 55 */
#define FLASH_WRProt_Pages56to59 ((u32)0x00004000) /* Write protection of page 56 to 59 */
#define FLASH_WRProt_Pages60to63 ((u32)0x00008000) /* Write protection of page 60 to 63 */
#define FLASH_WRProt_Pages64to67 ((u32)0x00010000) /* Write protection of page 64 to 67 */
#define FLASH_WRProt_Pages68to71 ((u32)0x00020000) /* Write protection of page 68 to 71 */
#define FLASH_WRProt_Pages72to75 ((u32)0x00040000) /* Write protection of page 72 to 75 */
#define FLASH_WRProt_Pages76to79 ((u32)0x00080000) /* Write protection of page 76 to 79 */
#define FLASH_WRProt_Pages80to83 ((u32)0x00100000) /* Write protection of page 80 to 83 */
#define FLASH_WRProt_Pages84to87 ((u32)0x00200000) /* Write protection of page 84 to 87 */
#define FLASH_WRProt_Pages88to91 ((u32)0x00400000) /* Write protection of page 88 to 91 */
#define FLASH_WRProt_Pages92to95 ((u32)0x00800000) /* Write protection of page 92 to 95 */
#define FLASH_WRProt_Pages96to99 ((u32)0x01000000) /* Write protection of page 96 to 99 */
#define FLASH_WRProt_Pages100to103 ((u32)0x02000000) /* Write protection of page 100 to 103 */
#define FLASH_WRProt_Pages104to107 ((u32)0x04000000) /* Write protection of page 104 to 107 */
#define FLASH_WRProt_Pages108to111 ((u32)0x08000000) /* Write protection of page 108 to 111 */
#define FLASH_WRProt_Pages112to115 ((u32)0x10000000) /* Write protection of page 112 to 115 */
#define FLASH_WRProt_Pages116to119 ((u32)0x20000000) /* Write protection of page 115 to 119 */
#define FLASH_WRProt_Pages120to123 ((u32)0x40000000) /* Write protection of page 120 to 123 */
#define FLASH_WRProt_Pages124to127 ((u32)0x80000000) /* Write protection of page 124 to 127 */
/* Values to be used with STM32F10Xxx High-density devices: FLASH memory density
ranges between 256 and 512 Kbytes with page size equal to 2 Kbytes */
#define FLASH_WRProt_Pages0to1 ((u32)0x00000001) /* Write protection of page 0 to 1 */
#define FLASH_WRProt_Pages2to3 ((u32)0x00000002) /* Write protection of page 2 to 3 */
#define FLASH_WRProt_Pages4to5 ((u32)0x00000004) /* Write protection of page 4 to 5 */
#define FLASH_WRProt_Pages6to7 ((u32)0x00000008) /* Write protection of page 6 to 7 */
#define FLASH_WRProt_Pages8to9 ((u32)0x00000010) /* Write protection of page 8 to 9 */
#define FLASH_WRProt_Pages10to11 ((u32)0x00000020) /* Write protection of page 10 to 11 */
#define FLASH_WRProt_Pages12to13 ((u32)0x00000040) /* Write protection of page 12 to 13 */
#define FLASH_WRProt_Pages14to15 ((u32)0x00000080) /* Write protection of page 14 to 15 */
#define FLASH_WRProt_Pages16to17 ((u32)0x00000100) /* Write protection of page 16 to 17 */
#define FLASH_WRProt_Pages18to19 ((u32)0x00000200) /* Write protection of page 18 to 19 */
#define FLASH_WRProt_Pages20to21 ((u32)0x00000400) /* Write protection of page 20 to 21 */
#define FLASH_WRProt_Pages22to23 ((u32)0x00000800) /* Write protection of page 22 to 23 */
#define FLASH_WRProt_Pages24to25 ((u32)0x00001000) /* Write protection of page 24 to 25 */
#define FLASH_WRProt_Pages26to27 ((u32)0x00002000) /* Write protection of page 26 to 27 */
#define FLASH_WRProt_Pages28to29 ((u32)0x00004000) /* Write protection of page 28 to 29 */
#define FLASH_WRProt_Pages30to31 ((u32)0x00008000) /* Write protection of page 30 to 31 */
#define FLASH_WRProt_Pages32to33 ((u32)0x00010000) /* Write protection of page 32 to 33 */
#define FLASH_WRProt_Pages34to35 ((u32)0x00020000) /* Write protection of page 34 to 35 */
#define FLASH_WRProt_Pages36to37 ((u32)0x00040000) /* Write protection of page 36 to 37 */
#define FLASH_WRProt_Pages38to39 ((u32)0x00080000) /* Write protection of page 38 to 39 */
#define FLASH_WRProt_Pages40to41 ((u32)0x00100000) /* Write protection of page 40 to 41 */
#define FLASH_WRProt_Pages42to43 ((u32)0x00200000) /* Write protection of page 42 to 43 */
#define FLASH_WRProt_Pages44to45 ((u32)0x00400000) /* Write protection of page 44 to 45 */
#define FLASH_WRProt_Pages46to47 ((u32)0x00800000) /* Write protection of page 46 to 47 */
#define FLASH_WRProt_Pages48to49 ((u32)0x01000000) /* Write protection of page 48 to 49 */
#define FLASH_WRProt_Pages50to51 ((u32)0x02000000) /* Write protection of page 50 to 51 */
#define FLASH_WRProt_Pages52to53 ((u32)0x04000000) /* Write protection of page 52 to 53 */
#define FLASH_WRProt_Pages54to55 ((u32)0x08000000) /* Write protection of page 54 to 55 */
#define FLASH_WRProt_Pages56to57 ((u32)0x10000000) /* Write protection of page 56 to 57 */
#define FLASH_WRProt_Pages58to59 ((u32)0x20000000) /* Write protection of page 58 to 59 */
#define FLASH_WRProt_Pages60to61 ((u32)0x40000000) /* Write protection of page 60 to 61 */
#define FLASH_WRProt_Pages62to255 ((u32)0x80000000) /* Write protection of page 62 to 255 */
#define FLASH_WRProt_AllPages ((u32)0xFFFFFFFF) /* Write protection of all Pages */
#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000))
#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x0807FFFF))
#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))
/* Option Bytes IWatchdog ----------------------------------------------------*/
#define OB_IWDG_SW ((u16)0x0001) /* Software IWDG selected */
#define OB_IWDG_HW ((u16)0x0000) /* Hardware IWDG selected */
#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
/* Option Bytes nRST_STOP ----------------------------------------------------*/
#define OB_STOP_NoRST ((u16)0x0002) /* No reset generated when entering in STOP */
#define OB_STOP_RST ((u16)0x0000) /* Reset generated when entering in STOP */
#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
/* Option Bytes nRST_STDBY ---------------------------------------------------*/
#define OB_STDBY_NoRST ((u16)0x0004) /* No reset generated when entering in STANDBY */
#define OB_STDBY_RST ((u16)0x0000) /* Reset generated when entering in STANDBY */
#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
/* FLASH Interrupts ----------------------------------------------------------*/
#define FLASH_IT_ERROR ((u32)0x00000400) /* FPEC error interrupt source */
#define FLASH_IT_EOP ((u32)0x00001000) /* End of FLASH Operation Interrupt source */
#define IS_FLASH_IT(IT) ((((IT) & (u32)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
/* FLASH Flags ---------------------------------------------------------------*/
#define FLASH_FLAG_BSY ((u32)0x00000001) /* FLASH Busy flag */
#define FLASH_FLAG_EOP ((u32)0x00000020) /* FLASH End of Operation flag */
#define FLASH_FLAG_PGERR ((u32)0x00000004) /* FLASH Program error flag */
#define FLASH_FLAG_WRPRTERR ((u32)0x00000010) /* FLASH Write protected error flag */
#define FLASH_FLAG_OPTERR ((u32)0x00000001) /* FLASH Option Byte error flag */
#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (u32)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))
#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \
((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \
((FLAG) == FLASH_FLAG_OPTERR))
#endif
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void FLASH_SetLatency(u32 FLASH_Latency);
void FLASH_HalfCycleAccessCmd(u32 FLASH_HalfCycleAccess);
void FLASH_PrefetchBufferCmd(u32 FLASH_PrefetchBuffer);
#ifdef _FLASH_PROG
void FLASH_Unlock(void);
void FLASH_Lock(void);
FLASH_Status FLASH_ErasePage(u32 Page_Address);
FLASH_Status FLASH_EraseAllPages(void);
FLASH_Status FLASH_EraseOptionBytes(void);
FLASH_Status FLASH_ProgramWord(u32 Address, u32 Data);
FLASH_Status FLASH_ProgramHalfWord(u32 Address, u16 Data);
FLASH_Status FLASH_ProgramOptionByteData(u32 Address, u8 Data);
FLASH_Status FLASH_EnableWriteProtection(u32 FLASH_Pages);
FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState);
FLASH_Status FLASH_UserOptionByteConfig(u16 OB_IWDG, u16 OB_STOP, u16 OB_STDBY);
u32 FLASH_GetUserOptionByte(void);
u32 FLASH_GetWriteProtectionOptionByte(void);
FlagStatus FLASH_GetReadOutProtectionStatus(void);
FlagStatus FLASH_GetPrefetchBufferStatus(void);
void FLASH_ITConfig(u16 FLASH_IT, FunctionalState NewState);
FlagStatus FLASH_GetFlagStatus(u16 FLASH_FLAG);
void FLASH_ClearFlag(u16 FLASH_FLAG);
FLASH_Status FLASH_GetStatus(void);
FLASH_Status FLASH_WaitForLastOperation(u32 Timeout);
#endif
#endif /* __STM32F10x_FLASH_H */
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

337
bsp/stm32f103vb_lwip/library/inc/stm32f10x_fsmc.h Normal file
View File

@ -0,0 +1,337 @@
/******************** (C) COPYRIGHT 2009 STMicroelectronics ********************
* File Name : stm32f10x_fsmc.h
* Author : MCD Application Team
* Version : V2.0.3Patch1
* Date : 04/06/2009
* Description : This file contains all the functions prototypes for the
* FSMC firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_FSMC_H
#define __STM32F10x_FSMC_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
/* Exported types ------------------------------------------------------------*/
/* Timing parameters For NOR/SRAM Banks */
typedef struct
{
u32 FSMC_AddressSetupTime;
u32 FSMC_AddressHoldTime;
u32 FSMC_DataSetupTime;
u32 FSMC_BusTurnAroundDuration;
u32 FSMC_CLKDivision;
u32 FSMC_DataLatency;
u32 FSMC_AccessMode;
}FSMC_NORSRAMTimingInitTypeDef;
/* FSMC NOR/SRAM Init structure definition */
typedef struct
{
u32 FSMC_Bank;
u32 FSMC_DataAddressMux;
u32 FSMC_MemoryType;
u32 FSMC_MemoryDataWidth;
u32 FSMC_BurstAccessMode;
u32 FSMC_WaitSignalPolarity;
u32 FSMC_WrapMode;
u32 FSMC_WaitSignalActive;
u32 FSMC_WriteOperation;
u32 FSMC_WaitSignal;
u32 FSMC_ExtendedMode;
u32 FSMC_WriteBurst;
/* Timing Parameters for write and read access if the ExtendedMode is not used*/
FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct;
/* Timing Parameters for write access if the ExtendedMode is used*/
FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct;
}FSMC_NORSRAMInitTypeDef;
/* Timing parameters For FSMC NAND and PCCARD Banks */
typedef struct
{
u32 FSMC_SetupTime;
u32 FSMC_WaitSetupTime;
u32 FSMC_HoldSetupTime;
u32 FSMC_HiZSetupTime;
}FSMC_NAND_PCCARDTimingInitTypeDef;
/* FSMC NAND Init structure definition */
typedef struct
{
u32 FSMC_Bank;
u32 FSMC_Waitfeature;
u32 FSMC_MemoryDataWidth;
u32 FSMC_ECC;
u32 FSMC_ECCPageSize;
u32 FSMC_TCLRSetupTime;
u32 FSMC_TARSetupTime;
/* FSMC Common Space Timing */
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct;
/* FSMC Attribute Space Timing */
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct;
}FSMC_NANDInitTypeDef;
/* FSMC PCCARD Init structure definition */
typedef struct
{
u32 FSMC_Waitfeature;
u32 FSMC_TCLRSetupTime;
u32 FSMC_TARSetupTime;
/* FSMC Common Space Timing */
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct;
/* FSMC Attribute Space Timing */
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct;
/* FSMC IO Space Timing */
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct;
}FSMC_PCCARDInitTypeDef;
/* Exported constants --------------------------------------------------------*/
/*-------------------------------FSMC Banks definitions ----------------------*/
#define FSMC_Bank1_NORSRAM1 ((u32)0x00000000)
#define FSMC_Bank1_NORSRAM2 ((u32)0x00000002)
#define FSMC_Bank1_NORSRAM3 ((u32)0x00000004)
#define FSMC_Bank1_NORSRAM4 ((u32)0x00000006)
#define FSMC_Bank2_NAND ((u32)0x00000010)
#define FSMC_Bank3_NAND ((u32)0x00000100)
#define FSMC_Bank4_PCCARD ((u32)0x00001000)
#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
((BANK) == FSMC_Bank1_NORSRAM2) || \
((BANK) == FSMC_Bank1_NORSRAM3) || \
((BANK) == FSMC_Bank1_NORSRAM4))
#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
((BANK) == FSMC_Bank3_NAND))
#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
((BANK) == FSMC_Bank3_NAND) || \
((BANK) == FSMC_Bank4_PCCARD))
#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
((BANK) == FSMC_Bank3_NAND) || \
((BANK) == FSMC_Bank4_PCCARD))
/*------------------------------- NOR/SRAM Banks -----------------------------*/
/* FSMC Data/Address Bus Multiplexing ----------------------------------------*/
#define FSMC_DataAddressMux_Disable ((u32)0x00000000)
#define FSMC_DataAddressMux_Enable ((u32)0x00000002)
#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
((MUX) == FSMC_DataAddressMux_Enable))
/* FSMC Memory Type ----------------------------------------------------------*/
#define FSMC_MemoryType_SRAM ((u32)0x00000000)
#define FSMC_MemoryType_PSRAM ((u32)0x00000004)
#define FSMC_MemoryType_NOR ((u32)0x00000008)
#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
((MEMORY) == FSMC_MemoryType_PSRAM)|| \
((MEMORY) == FSMC_MemoryType_NOR))
/* FSMC Data Width ----------------------------------------------------------*/
#define FSMC_MemoryDataWidth_8b ((u32)0x00000000)
#define FSMC_MemoryDataWidth_16b ((u32)0x00000010)
#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
((WIDTH) == FSMC_MemoryDataWidth_16b))
/* FSMC Burst Access Mode ----------------------------------------------------*/
#define FSMC_BurstAccessMode_Disable ((u32)0x00000000)
#define FSMC_BurstAccessMode_Enable ((u32)0x00000100)
#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
((STATE) == FSMC_BurstAccessMode_Enable))
/* FSMC Wait Signal Polarity -------------------------------------------------*/
#define FSMC_WaitSignalPolarity_Low ((u32)0x00000000)
#define FSMC_WaitSignalPolarity_High ((u32)0x00000200)
#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
((POLARITY) == FSMC_WaitSignalPolarity_High))
/* FSMC Wrap Mode ------------------------------------------------------------*/
#define FSMC_WrapMode_Disable ((u32)0x00000000)
#define FSMC_WrapMode_Enable ((u32)0x00000400)
#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
((MODE) == FSMC_WrapMode_Enable))
/* FSMC Wait Timing ----------------------------------------------------------*/
#define FSMC_WaitSignalActive_BeforeWaitState ((u32)0x00000000)
#define FSMC_WaitSignalActive_DuringWaitState ((u32)0x00000800)
#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
/* FSMC Write Operation ------------------------------------------------------*/
#define FSMC_WriteOperation_Disable ((u32)0x00000000)
#define FSMC_WriteOperation_Enable ((u32)0x00001000)
#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
((OPERATION) == FSMC_WriteOperation_Enable))
/* FSMC Wait Signal ----------------------------------------------------------*/
#define FSMC_WaitSignal_Disable ((u32)0x00000000)
#define FSMC_WaitSignal_Enable ((u32)0x00002000)
#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
((SIGNAL) == FSMC_WaitSignal_Enable))
/* FSMC Extended Mode --------------------------------------------------------*/
#define FSMC_ExtendedMode_Disable ((u32)0x00000000)
#define FSMC_ExtendedMode_Enable ((u32)0x00004000)
#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
((MODE) == FSMC_ExtendedMode_Enable))
/* FSMC Write Burst ----------------------------------------------------------*/
#define FSMC_WriteBurst_Disable ((u32)0x00000000)
#define FSMC_WriteBurst_Enable ((u32)0x00080000)
#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
((BURST) == FSMC_WriteBurst_Enable))
/* FSMC Address Setup Time ---------------------------------------------------*/
#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
/* FSMC Address Hold Time ----------------------------------------------------*/
#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
/* FSMC Data Setup Time ------------------------------------------------------*/
#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
/* FSMC Bus Turn around Duration ---------------------------------------------*/
#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
/* FSMC CLK Division ---------------------------------------------------------*/
#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
/* FSMC Data Latency ---------------------------------------------------------*/
#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
/* FSMC Access Mode ----------------------------------------------------------*/
#define FSMC_AccessMode_A ((u32)0x00000000)
#define FSMC_AccessMode_B ((u32)0x10000000)
#define FSMC_AccessMode_C ((u32)0x20000000)
#define FSMC_AccessMode_D ((u32)0x30000000)
#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
((MODE) == FSMC_AccessMode_B) || \
((MODE) == FSMC_AccessMode_C) || \
((MODE) == FSMC_AccessMode_D))
/*----------------------------- NAND and PCCARD Banks ------------------------*/
/* FSMC Wait feature ---------------------------------------------------------*/
#define FSMC_Waitfeature_Disable ((u32)0x00000000)
#define FSMC_Waitfeature_Enable ((u32)0x00000002)
#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \
((FEATURE) == FSMC_Waitfeature_Enable))
/* FSMC Memory Data Width ----------------------------------------------------*/
#define FSMC_MemoryDataWidth_8b ((u32)0x00000000)
#define FSMC_MemoryDataWidth_16b ((u32)0x00000010)
#define IS_FSMC_DATA_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
((WIDTH) == FSMC_MemoryDataWidth_16b))
/* FSMC ECC ------------------------------------------------------------------*/
#define FSMC_ECC_Disable ((u32)0x00000000)
#define FSMC_ECC_Enable ((u32)0x00000040)
#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \
((STATE) == FSMC_ECC_Enable))
/* FSMC ECC Page Size --------------------------------------------------------*/
#define FSMC_ECCPageSize_256Bytes ((u32)0x00000000)
#define FSMC_ECCPageSize_512Bytes ((u32)0x00020000)
#define FSMC_ECCPageSize_1024Bytes ((u32)0x00040000)
#define FSMC_ECCPageSize_2048Bytes ((u32)0x00060000)
#define FSMC_ECCPageSize_4096Bytes ((u32)0x00080000)
#define FSMC_ECCPageSize_8192Bytes ((u32)0x000A0000)
#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \
((SIZE) == FSMC_ECCPageSize_512Bytes) || \
((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
((SIZE) == FSMC_ECCPageSize_8192Bytes))
/* FSMC TCLR Setup Time ------------------------------------------------------*/
#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
/* FSMC TAR Setup Time -------------------------------------------------------*/
#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
/* FSMC Setup Time ----------------------------------------------------*/
#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
/* FSMC Wait Setup Time -----------------------------------------------*/
#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
/* FSMC Hold Setup Time -----------------------------------------------*/
#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
/* FSMC HiZ Setup Time ------------------------------------------------*/
#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
/* FSMC Interrupt sources ----------------------------------------------------*/
#define FSMC_IT_RisingEdge ((u32)0x00000008)
#define FSMC_IT_Level ((u32)0x00000010)
#define FSMC_IT_FallingEdge ((u32)0x00000020)
#define IS_FSMC_IT(IT) ((((IT) & (u32)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \
((IT) == FSMC_IT_Level) || \
((IT) == FSMC_IT_FallingEdge))
/* FSMC Flags ----------------------------------------------------------------*/
#define FSMC_FLAG_RisingEdge ((u32)0x00000001)
#define FSMC_FLAG_Level ((u32)0x00000002)
#define FSMC_FLAG_FallingEdge ((u32)0x00000004)
#define FSMC_FLAG_FEMPT ((u32)0x00000040)
#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \
((FLAG) == FSMC_FLAG_Level) || \
((FLAG) == FSMC_FLAG_FallingEdge) || \
((FLAG) == FSMC_FLAG_FEMPT))
#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (u32)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void FSMC_NORSRAMDeInit(u32 FSMC_Bank);
void FSMC_NANDDeInit(u32 FSMC_Bank);
void FSMC_PCCARDDeInit(void);
void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
void FSMC_NORSRAMCmd(u32 FSMC_Bank, FunctionalState NewState);
void FSMC_NANDCmd(u32 FSMC_Bank, FunctionalState NewState);
void FSMC_PCCARDCmd(FunctionalState NewState);
void FSMC_NANDECCCmd(u32 FSMC_Bank, FunctionalState NewState);
u32 FSMC_GetECC(u32 FSMC_Bank);
void FSMC_ITConfig(u32 FSMC_Bank, u32 FSMC_IT, FunctionalState NewState);
FlagStatus FSMC_GetFlagStatus(u32 FSMC_Bank, u32 FSMC_FLAG);
void FSMC_ClearFlag(u32 FSMC_Bank, u32 FSMC_FLAG);
ITStatus FSMC_GetITStatus(u32 FSMC_Bank, u32 FSMC_IT);
void FSMC_ClearITPendingBit(u32 FSMC_Bank, u32 FSMC_IT);
#endif /*__STM32F10x_FSMC_H */
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

237
bsp/stm32f103vb_lwip/library/inc/stm32f10x_gpio.h Normal file
View File

@ -0,0 +1,237 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_gpio.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the functions prototypes for the
* GPIO firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_GPIO_H
#define __STM32F10x_GPIO_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
/* Exported types ------------------------------------------------------------*/
#define IS_GPIO_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == GPIOA_BASE) || \
((*(u32*)&(PERIPH)) == GPIOB_BASE) || \
((*(u32*)&(PERIPH)) == GPIOC_BASE) || \
((*(u32*)&(PERIPH)) == GPIOD_BASE) || \
((*(u32*)&(PERIPH)) == GPIOE_BASE) || \
((*(u32*)&(PERIPH)) == GPIOF_BASE) || \
((*(u32*)&(PERIPH)) == GPIOG_BASE))
/* Output Maximum frequency selection ----------------------------------------*/
typedef enum
{
GPIO_Speed_10MHz = 1,
GPIO_Speed_2MHz,
GPIO_Speed_50MHz
}GPIOSpeed_TypeDef;
#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \
((SPEED) == GPIO_Speed_50MHz))
/* Configuration Mode enumeration --------------------------------------------*/
typedef enum
{ GPIO_Mode_AIN = 0x0,
GPIO_Mode_IN_FLOATING = 0x04,
GPIO_Mode_IPD = 0x28,
GPIO_Mode_IPU = 0x48,
GPIO_Mode_Out_OD = 0x14,
GPIO_Mode_Out_PP = 0x10,
GPIO_Mode_AF_OD = 0x1C,
GPIO_Mode_AF_PP = 0x18
}GPIOMode_TypeDef;
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || \
((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \
((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \
((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP))
/* GPIO Init structure definition */
typedef struct
{
u16 GPIO_Pin;
GPIOSpeed_TypeDef GPIO_Speed;
GPIOMode_TypeDef GPIO_Mode;
}GPIO_InitTypeDef;
/* Bit_SET and Bit_RESET enumeration -----------------------------------------*/
typedef enum
{ Bit_RESET = 0,
Bit_SET
}BitAction;
#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
/* Exported constants --------------------------------------------------------*/
/* GPIO pins define ----------------------------------------------------------*/
#define GPIO_Pin_0 ((u16)0x0001) /* Pin 0 selected */
#define GPIO_Pin_1 ((u16)0x0002) /* Pin 1 selected */
#define GPIO_Pin_2 ((u16)0x0004) /* Pin 2 selected */
#define GPIO_Pin_3 ((u16)0x0008) /* Pin 3 selected */
#define GPIO_Pin_4 ((u16)0x0010) /* Pin 4 selected */
#define GPIO_Pin_5 ((u16)0x0020) /* Pin 5 selected */
#define GPIO_Pin_6 ((u16)0x0040) /* Pin 6 selected */
#define GPIO_Pin_7 ((u16)0x0080) /* Pin 7 selected */
#define GPIO_Pin_8 ((u16)0x0100) /* Pin 8 selected */
#define GPIO_Pin_9 ((u16)0x0200) /* Pin 9 selected */
#define GPIO_Pin_10 ((u16)0x0400) /* Pin 10 selected */
#define GPIO_Pin_11 ((u16)0x0800) /* Pin 11 selected */
#define GPIO_Pin_12 ((u16)0x1000) /* Pin 12 selected */
#define GPIO_Pin_13 ((u16)0x2000) /* Pin 13 selected */
#define GPIO_Pin_14 ((u16)0x4000) /* Pin 14 selected */
#define GPIO_Pin_15 ((u16)0x8000) /* Pin 15 selected */
#define GPIO_Pin_All ((u16)0xFFFF) /* All pins selected */
#define IS_GPIO_PIN(PIN) ((((PIN) & (u16)0x00) == 0x00) && ((PIN) != (u16)0x00))
#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
((PIN) == GPIO_Pin_1) || \
((PIN) == GPIO_Pin_2) || \
((PIN) == GPIO_Pin_3) || \
((PIN) == GPIO_Pin_4) || \
((PIN) == GPIO_Pin_5) || \
((PIN) == GPIO_Pin_6) || \
((PIN) == GPIO_Pin_7) || \
((PIN) == GPIO_Pin_8) || \
((PIN) == GPIO_Pin_9) || \
((PIN) == GPIO_Pin_10) || \
((PIN) == GPIO_Pin_11) || \
((PIN) == GPIO_Pin_12) || \
((PIN) == GPIO_Pin_13) || \
((PIN) == GPIO_Pin_14) || \
((PIN) == GPIO_Pin_15))
/* GPIO Remap define ---------------------------------------------------------*/
#define GPIO_Remap_SPI1 ((u32)0x00000001) /* SPI1 Alternate Function mapping */
#define GPIO_Remap_I2C1 ((u32)0x00000002) /* I2C1 Alternate Function mapping */
#define GPIO_Remap_USART1 ((u32)0x00000004) /* USART1 Alternate Function mapping */
#define GPIO_Remap_USART2 ((u32)0x00000008) /* USART2 Alternate Function mapping */
#define GPIO_PartialRemap_USART3 ((u32)0x00140010) /* USART3 Partial Alternate Function mapping */
#define GPIO_FullRemap_USART3 ((u32)0x00140030) /* USART3 Full Alternate Function mapping */
#define GPIO_PartialRemap_TIM1 ((u32)0x00160040) /* TIM1 Partial Alternate Function mapping */
#define GPIO_FullRemap_TIM1 ((u32)0x001600C0) /* TIM1 Full Alternate Function mapping */
#define GPIO_PartialRemap1_TIM2 ((u32)0x00180100) /* TIM2 Partial1 Alternate Function mapping */
#define GPIO_PartialRemap2_TIM2 ((u32)0x00180200) /* TIM2 Partial2 Alternate Function mapping */
#define GPIO_FullRemap_TIM2 ((u32)0x00180300) /* TIM2 Full Alternate Function mapping */
#define GPIO_PartialRemap_TIM3 ((u32)0x001A0800) /* TIM3 Partial Alternate Function mapping */
#define GPIO_FullRemap_TIM3 ((u32)0x001A0C00) /* TIM3 Full Alternate Function mapping */
#define GPIO_Remap_TIM4 ((u32)0x00001000) /* TIM4 Alternate Function mapping */
#define GPIO_Remap1_CAN ((u32)0x001D4000) /* CAN Alternate Function mapping */
#define GPIO_Remap2_CAN ((u32)0x001D6000) /* CAN Alternate Function mapping */
#define GPIO_Remap_PD01 ((u32)0x00008000) /* PD01 Alternate Function mapping */
#define GPIO_Remap_TIM5CH4_LSI ((u32)0x00200001) /* LSI connected to TIM5 Channel4 input capture for calibration */
#define GPIO_Remap_ADC1_ETRGINJ ((u32)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */
#define GPIO_Remap_ADC1_ETRGREG ((u32)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */
#define GPIO_Remap_ADC2_ETRGINJ ((u32)0x00200008) /* ADC2 External Trigger Injected Conversion remapping */
#define GPIO_Remap_ADC2_ETRGREG ((u32)0x00200010) /* ADC2 External Trigger Regular Conversion remapping */
#define GPIO_Remap_SWJ_NoJTRST ((u32)0x00300100) /* Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */
#define GPIO_Remap_SWJ_JTAGDisable ((u32)0x00300200) /* JTAG-DP Disabled and SW-DP Enabled */
#define GPIO_Remap_SWJ_Disable ((u32)0x00300400) /* Full SWJ Disabled (JTAG-DP + SW-DP) */
#define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \
((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || \
((REMAP) == GPIO_PartialRemap_USART3) || ((REMAP) == GPIO_FullRemap_USART3) || \
((REMAP) == GPIO_PartialRemap_TIM1) || ((REMAP) == GPIO_FullRemap_TIM1) || \
((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || \
((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || \
((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || \
((REMAP) == GPIO_Remap1_CAN) || ((REMAP) == GPIO_Remap2_CAN) || \
((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || \
((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \
((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || \
((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable)|| \
((REMAP) == GPIO_Remap_SWJ_Disable))
/* GPIO Port Sources ---------------------------------------------------------*/
#define GPIO_PortSourceGPIOA ((u8)0x00)
#define GPIO_PortSourceGPIOB ((u8)0x01)
#define GPIO_PortSourceGPIOC ((u8)0x02)
#define GPIO_PortSourceGPIOD ((u8)0x03)
#define GPIO_PortSourceGPIOE ((u8)0x04)
#define GPIO_PortSourceGPIOF ((u8)0x05)
#define GPIO_PortSourceGPIOG ((u8)0x06)
#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \
((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
((PORTSOURCE) == GPIO_PortSourceGPIOD) || \
((PORTSOURCE) == GPIO_PortSourceGPIOE))
#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \
((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
((PORTSOURCE) == GPIO_PortSourceGPIOD) || \
((PORTSOURCE) == GPIO_PortSourceGPIOE) || \
((PORTSOURCE) == GPIO_PortSourceGPIOF) || \
((PORTSOURCE) == GPIO_PortSourceGPIOG))
/* GPIO Pin sources ----------------------------------------------------------*/
#define GPIO_PinSource0 ((u8)0x00)
#define GPIO_PinSource1 ((u8)0x01)
#define GPIO_PinSource2 ((u8)0x02)
#define GPIO_PinSource3 ((u8)0x03)
#define GPIO_PinSource4 ((u8)0x04)
#define GPIO_PinSource5 ((u8)0x05)
#define GPIO_PinSource6 ((u8)0x06)
#define GPIO_PinSource7 ((u8)0x07)
#define GPIO_PinSource8 ((u8)0x08)
#define GPIO_PinSource9 ((u8)0x09)
#define GPIO_PinSource10 ((u8)0x0A)
#define GPIO_PinSource11 ((u8)0x0B)
#define GPIO_PinSource12 ((u8)0x0C)
#define GPIO_PinSource13 ((u8)0x0D)
#define GPIO_PinSource14 ((u8)0x0E)
#define GPIO_PinSource15 ((u8)0x0F)
#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
((PINSOURCE) == GPIO_PinSource1) || \
((PINSOURCE) == GPIO_PinSource2) || \
((PINSOURCE) == GPIO_PinSource3) || \
((PINSOURCE) == GPIO_PinSource4) || \
((PINSOURCE) == GPIO_PinSource5) || \
((PINSOURCE) == GPIO_PinSource6) || \
((PINSOURCE) == GPIO_PinSource7) || \
((PINSOURCE) == GPIO_PinSource8) || \
((PINSOURCE) == GPIO_PinSource9) || \
((PINSOURCE) == GPIO_PinSource10) || \
((PINSOURCE) == GPIO_PinSource11) || \
((PINSOURCE) == GPIO_PinSource12) || \
((PINSOURCE) == GPIO_PinSource13) || \
((PINSOURCE) == GPIO_PinSource14) || \
((PINSOURCE) == GPIO_PinSource15))
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void GPIO_DeInit(GPIO_TypeDef* GPIOx);
void GPIO_AFIODeInit(void);
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
u8 GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin);
u16 GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
u8 GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin);
u16 GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
void GPIO_SetBits(GPIO_TypeDef* GPIOx, u16 GPIO_Pin);
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, u16 GPIO_Pin);
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin, BitAction BitVal);
void GPIO_Write(GPIO_TypeDef* GPIOx, u16 PortVal);
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, u16 GPIO_Pin);
void GPIO_EventOutputConfig(u8 GPIO_PortSource, u8 GPIO_PinSource);
void GPIO_EventOutputCmd(FunctionalState NewState);
void GPIO_PinRemapConfig(u32 GPIO_Remap, FunctionalState NewState);
void GPIO_EXTILineConfig(u8 GPIO_PortSource, u8 GPIO_PinSource);
#endif /* __STM32F10x_GPIO_H */
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

285
bsp/stm32f103vb_lwip/library/inc/stm32f10x_i2c.h Normal file
View File

@ -0,0 +1,285 @@
/******************** (C) COPYRIGHT 2009 STMicroelectronics ********************
* File Name : stm32f10x_i2c.h
* Author : MCD Application Team
* Version : V2.0.3Patch1
* Date : 04/06/2009
* Description : This file contains all the functions prototypes for the
* I2C firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_I2C_H
#define __STM32F10x_I2C_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
/* Exported types ------------------------------------------------------------*/
/* I2C Init structure definition */
typedef struct
{
u16 I2C_Mode;
u16 I2C_DutyCycle;
u16 I2C_OwnAddress1;
u16 I2C_Ack;
u16 I2C_AcknowledgedAddress;
u32 I2C_ClockSpeed;
}I2C_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
#define IS_I2C_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == I2C1_BASE) || \
((*(u32*)&(PERIPH)) == I2C2_BASE))
/* I2C modes */
#define I2C_Mode_I2C ((u16)0x0000)
#define I2C_Mode_SMBusDevice ((u16)0x0002)
#define I2C_Mode_SMBusHost ((u16)0x000A)
#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
((MODE) == I2C_Mode_SMBusDevice) || \
((MODE) == I2C_Mode_SMBusHost))
/* I2C duty cycle in fast mode */
#define I2C_DutyCycle_16_9 ((u16)0x4000)
#define I2C_DutyCycle_2 ((u16)0xBFFF)
#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \
((CYCLE) == I2C_DutyCycle_2))
/* I2C cknowledgementy */
#define I2C_Ack_Enable ((u16)0x0400)
#define I2C_Ack_Disable ((u16)0x0000)
#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \
((STATE) == I2C_Ack_Disable))
/* I2C transfer direction */
#define I2C_Direction_Transmitter ((u8)0x00)
#define I2C_Direction_Receiver ((u8)0x01)
#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
((DIRECTION) == I2C_Direction_Receiver))
/* I2C acknowledged address defines */
#define I2C_AcknowledgedAddress_7bit ((u16)0x4000)
#define I2C_AcknowledgedAddress_10bit ((u16)0xC000)
#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
((ADDRESS) == I2C_AcknowledgedAddress_10bit))
/* I2C registers */
#define I2C_Register_CR1 ((u8)0x00)
#define I2C_Register_CR2 ((u8)0x04)
#define I2C_Register_OAR1 ((u8)0x08)
#define I2C_Register_OAR2 ((u8)0x0C)
#define I2C_Register_DR ((u8)0x10)
#define I2C_Register_SR1 ((u8)0x14)
#define I2C_Register_SR2 ((u8)0x18)
#define I2C_Register_CCR ((u8)0x1C)
#define I2C_Register_TRISE ((u8)0x20)
#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
((REGISTER) == I2C_Register_CR2) || \
((REGISTER) == I2C_Register_OAR1) || \
((REGISTER) == I2C_Register_OAR2) || \
((REGISTER) == I2C_Register_DR) || \
((REGISTER) == I2C_Register_SR1) || \
((REGISTER) == I2C_Register_SR2) || \
((REGISTER) == I2C_Register_CCR) || \
((REGISTER) == I2C_Register_TRISE))
/* I2C SMBus alert pin level */
#define I2C_SMBusAlert_Low ((u16)0x2000)
#define I2C_SMBusAlert_High ((u16)0xDFFF)
#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \
((ALERT) == I2C_SMBusAlert_High))
/* I2C PEC position */
#define I2C_PECPosition_Next ((u16)0x0800)
#define I2C_PECPosition_Current ((u16)0xF7FF)
#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \
((POSITION) == I2C_PECPosition_Current))
/* I2C interrupts definition */
#define I2C_IT_BUF ((u16)0x0400)
#define I2C_IT_EVT ((u16)0x0200)
#define I2C_IT_ERR ((u16)0x0100)
#define IS_I2C_CONFIG_IT(IT) ((((IT) & (u16)0xF8FF) == 0x00) && ((IT) != 0x00))
/* I2C interrupts definition */
#define I2C_IT_SMBALERT ((u32)0x01008000)
#define I2C_IT_TIMEOUT ((u32)0x01004000)
#define I2C_IT_PECERR ((u32)0x01001000)
#define I2C_IT_OVR ((u32)0x01000800)
#define I2C_IT_AF ((u32)0x01000400)
#define I2C_IT_ARLO ((u32)0x01000200)
#define I2C_IT_BERR ((u32)0x01000100)
#define I2C_IT_TXE ((u32)0x06000080)
#define I2C_IT_RXNE ((u32)0x06000040)
#define I2C_IT_STOPF ((u32)0x02000010)
#define I2C_IT_ADD10 ((u32)0x02000008)
#define I2C_IT_BTF ((u32)0x02000004)
#define I2C_IT_ADDR ((u32)0x02000002)
#define I2C_IT_SB ((u32)0x02000001)
#define IS_I2C_CLEAR_IT(IT) ((((IT) & (u16)0x20FF) == 0x00) && ((IT) != (u16)0x00))
#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \
((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \
((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \
((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \
((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \
((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \
((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))
/* I2C flags definition */
/* SR2 register flags */
#define I2C_FLAG_DUALF ((u32)0x00800000)
#define I2C_FLAG_SMBHOST ((u32)0x00400000)
#define I2C_FLAG_SMBDEFAULT ((u32)0x00200000)
#define I2C_FLAG_GENCALL ((u32)0x00100000)
#define I2C_FLAG_TRA ((u32)0x00040000)
#define I2C_FLAG_BUSY ((u32)0x00020000)
#define I2C_FLAG_MSL ((u32)0x00010000)
/* SR1 register flags */
#define I2C_FLAG_SMBALERT ((u32)0x10008000)
#define I2C_FLAG_TIMEOUT ((u32)0x10004000)
#define I2C_FLAG_PECERR ((u32)0x10001000)
#define I2C_FLAG_OVR ((u32)0x10000800)
#define I2C_FLAG_AF ((u32)0x10000400)
#define I2C_FLAG_ARLO ((u32)0x10000200)
#define I2C_FLAG_BERR ((u32)0x10000100)
#define I2C_FLAG_TXE ((u32)0x10000080)
#define I2C_FLAG_RXNE ((u32)0x10000040)
#define I2C_FLAG_STOPF ((u32)0x10000010)
#define I2C_FLAG_ADD10 ((u32)0x10000008)
#define I2C_FLAG_BTF ((u32)0x10000004)
#define I2C_FLAG_ADDR ((u32)0x10000002)
#define I2C_FLAG_SB ((u32)0x10000001)
#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (u16)0x20FF) == 0x00) && ((FLAG) != (u16)0x00))
#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \
((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \
((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \
((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \
((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \
((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \
((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \
((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \
((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \
((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \
((FLAG) == I2C_FLAG_SB))
/* I2C Events */
/* EV1 */
#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((u32)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((u32)0x00020002) /* BUSY and ADDR flags */
#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((u32)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((u32)0x00820000) /* DUALF and BUSY flags */
#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((u32)0x00120000) /* GENCALL and BUSY flags */
/* EV2 */
#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((u32)0x00020040) /* BUSY and RXNE flags */
/* EV3 */
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((u32)0x00060084) /* TRA, BUSY, TXE and BTF flags */
/* EV4 */
#define I2C_EVENT_SLAVE_STOP_DETECTED ((u32)0x00000010) /* STOPF flag */
/* EV5 */
#define I2C_EVENT_MASTER_MODE_SELECT ((u32)0x00030001) /* BUSY, MSL and SB flag */
/* EV6 */
#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((u32)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((u32)0x00030002) /* BUSY, MSL and ADDR flags */
/* EV7 */
#define I2C_EVENT_MASTER_BYTE_RECEIVED ((u32)0x00030040) /* BUSY, MSL and RXNE flags */
/* EV8 */
#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((u32)0x00070080) /* TRA, BUSY, MSL, TXE flags */
/* EV8_2 */
#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((u32)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
/* EV9 */
#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((u32)0x00030008) /* BUSY, MSL and ADD10 flags */
/* EV3_2 */
#define I2C_EVENT_SLAVE_ACK_FAILURE ((u32)0x00000400) /* AF flag */
#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \
((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \
((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \
((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \
((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))
/* I2C own address1 -----------------------------------------------------------*/
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
/* I2C clock speed ------------------------------------------------------------*/
#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void I2C_DeInit(I2C_TypeDef* I2Cx);
void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, u8 Address);
void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_ITConfig(I2C_TypeDef* I2Cx, u16 I2C_IT, FunctionalState NewState);
void I2C_SendData(I2C_TypeDef* I2Cx, u8 Data);
u8 I2C_ReceiveData(I2C_TypeDef* I2Cx);
void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, u8 Address, u8 I2C_Direction);
u16 I2C_ReadRegister(I2C_TypeDef* I2Cx, u8 I2C_Register);
void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, u16 I2C_SMBusAlert);
void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, u16 I2C_PECPosition);
void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
u8 I2C_GetPEC(I2C_TypeDef* I2Cx);
void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, u16 I2C_DutyCycle);
u32 I2C_GetLastEvent(I2C_TypeDef* I2Cx);
ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, u32 I2C_EVENT);
FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, u32 I2C_FLAG);
void I2C_ClearFlag(I2C_TypeDef* I2Cx, u32 I2C_FLAG);
ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, u32 I2C_IT);
void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, u32 I2C_IT);
#endif /*__STM32F10x_I2C_H */
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

69
bsp/stm32f103vb_lwip/library/inc/stm32f10x_iwdg.h Normal file
View File

@ -0,0 +1,69 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_iwdg.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the functions prototypes for the
* IWDG firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_IWDG_H
#define __STM32F10x_IWDG_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Write access to IWDG_PR and IWDG_RLR registers */
#define IWDG_WriteAccess_Enable ((u16)0x5555)
#define IWDG_WriteAccess_Disable ((u16)0x0000)
#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
((ACCESS) == IWDG_WriteAccess_Disable))
/* IWDG prescaler */
#define IWDG_Prescaler_4 ((u8)0x00)
#define IWDG_Prescaler_8 ((u8)0x01)
#define IWDG_Prescaler_16 ((u8)0x02)
#define IWDG_Prescaler_32 ((u8)0x03)
#define IWDG_Prescaler_64 ((u8)0x04)
#define IWDG_Prescaler_128 ((u8)0x05)
#define IWDG_Prescaler_256 ((u8)0x06)
#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \
((PRESCALER) == IWDG_Prescaler_8) || \
((PRESCALER) == IWDG_Prescaler_16) || \
((PRESCALER) == IWDG_Prescaler_32) || \
((PRESCALER) == IWDG_Prescaler_64) || \
((PRESCALER) == IWDG_Prescaler_128)|| \
((PRESCALER) == IWDG_Prescaler_256))
/* IWDG Flag */
#define IWDG_FLAG_PVU ((u16)0x0001)
#define IWDG_FLAG_RVU ((u16)0x0002)
#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))
#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void IWDG_WriteAccessCmd(u16 IWDG_WriteAccess);
void IWDG_SetPrescaler(u8 IWDG_Prescaler);
void IWDG_SetReload(u16 Reload);
void IWDG_ReloadCounter(void);
void IWDG_Enable(void);
FlagStatus IWDG_GetFlagStatus(u16 IWDG_FLAG);
#endif /* __STM32F10x_IWDG_H */
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

124
bsp/stm32f103vb_lwip/library/inc/stm32f10x_lib.h Normal file
View File

@ -0,0 +1,124 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_lib.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file includes the peripherals header files in the
* user application.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_LIB_H
#define __STM32F10x_LIB_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
#ifdef _ADC
#include "stm32f10x_adc.h"
#endif /*_ADC */
#ifdef _BKP
#include "stm32f10x_bkp.h"
#endif /*_BKP */
#ifdef _CAN
#include "stm32f10x_can.h"
#endif /*_CAN */
#ifdef _CRC
#include "stm32f10x_crc.h"
#endif /*_CRC */
#ifdef _DAC
#include "stm32f10x_dac.h"
#endif /*_DAC */
#ifdef _DBGMCU
#include "stm32f10x_dbgmcu.h"
#endif /*_DBGMCU */
#ifdef _DMA
#include "stm32f10x_dma.h"
#endif /*_DMA */
#ifdef _EXTI
#include "stm32f10x_exti.h"
#endif /*_EXTI */
#ifdef _FLASH
#include "stm32f10x_flash.h"
#endif /*_FLASH */
#ifdef _FSMC
#include "stm32f10x_fsmc.h"
#endif /*_FSMC */
#ifdef _GPIO
#include "stm32f10x_gpio.h"
#endif /*_GPIO */
#ifdef _I2C
#include "stm32f10x_i2c.h"
#endif /*_I2C */
#ifdef _IWDG
#include "stm32f10x_iwdg.h"
#endif /*_IWDG */
#ifdef _NVIC
#include "stm32f10x_nvic.h"
#endif /*_NVIC */
#ifdef _PWR
#include "stm32f10x_pwr.h"
#endif /*_PWR */
#ifdef _RCC
#include "stm32f10x_rcc.h"
#endif /*_RCC */
#ifdef _RTC
#include "stm32f10x_rtc.h"
#endif /*_RTC */
#ifdef _SDIO
#include "stm32f10x_sdio.h"
#endif /*_SDIO */
#ifdef _SPI
#include "stm32f10x_spi.h"
#endif /*_SPI */
#ifdef _SysTick
#include "stm32f10x_systick.h"
#endif /*_SysTick */
#ifdef _TIM
#include "stm32f10x_tim.h"
#endif /*_TIM */
#ifdef _USART
#include "stm32f10x_usart.h"
#endif /*_USART */
#ifdef _WWDG
#include "stm32f10x_wwdg.h"
#endif /*_WWDG */
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void debug(void);
#endif /* __STM32F10x_LIB_H */
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

7603
bsp/stm32f103vb_lwip/library/inc/stm32f10x_map.h Normal file
View File

File diff suppressed because it is too large Load Diff

287
bsp/stm32f103vb_lwip/library/inc/stm32f10x_nvic.h Normal file
View File

@ -0,0 +1,287 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_nvic.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the functions prototypes for the
* NVIC firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_NVIC_H
#define __STM32F10x_NVIC_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
/* Exported types ------------------------------------------------------------*/
/* NVIC Init Structure definition */
typedef struct
{
u8 NVIC_IRQChannel;
u8 NVIC_IRQChannelPreemptionPriority;
u8 NVIC_IRQChannelSubPriority;
FunctionalState NVIC_IRQChannelCmd;
} NVIC_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
/* IRQ Channels --------------------------------------------------------------*/
#define WWDG_IRQChannel ((u8)0x00) /* Window WatchDog Interrupt */
#define PVD_IRQChannel ((u8)0x01) /* PVD through EXTI Line detection Interrupt */
#define TAMPER_IRQChannel ((u8)0x02) /* Tamper Interrupt */
#define RTC_IRQChannel ((u8)0x03) /* RTC global Interrupt */
#define FLASH_IRQChannel ((u8)0x04) /* FLASH global Interrupt */
#define RCC_IRQChannel ((u8)0x05) /* RCC global Interrupt */
#define EXTI0_IRQChannel ((u8)0x06) /* EXTI Line0 Interrupt */
#define EXTI1_IRQChannel ((u8)0x07) /* EXTI Line1 Interrupt */
#define EXTI2_IRQChannel ((u8)0x08) /* EXTI Line2 Interrupt */
#define EXTI3_IRQChannel ((u8)0x09) /* EXTI Line3 Interrupt */
#define EXTI4_IRQChannel ((u8)0x0A) /* EXTI Line4 Interrupt */
#define DMA1_Channel1_IRQChannel ((u8)0x0B) /* DMA1 Channel 1 global Interrupt */
#define DMA1_Channel2_IRQChannel ((u8)0x0C) /* DMA1 Channel 2 global Interrupt */
#define DMA1_Channel3_IRQChannel ((u8)0x0D) /* DMA1 Channel 3 global Interrupt */
#define DMA1_Channel4_IRQChannel ((u8)0x0E) /* DMA1 Channel 4 global Interrupt */
#define DMA1_Channel5_IRQChannel ((u8)0x0F) /* DMA1 Channel 5 global Interrupt */
#define DMA1_Channel6_IRQChannel ((u8)0x10) /* DMA1 Channel 6 global Interrupt */
#define DMA1_Channel7_IRQChannel ((u8)0x11) /* DMA1 Channel 7 global Interrupt */
#define ADC1_2_IRQChannel ((u8)0x12) /* ADC1 et ADC2 global Interrupt */
#define USB_HP_CAN_TX_IRQChannel ((u8)0x13) /* USB High Priority or CAN TX Interrupts */
#define USB_LP_CAN_RX0_IRQChannel ((u8)0x14) /* USB Low Priority or CAN RX0 Interrupts */
#define CAN_RX1_IRQChannel ((u8)0x15) /* CAN RX1 Interrupt */
#define CAN_SCE_IRQChannel ((u8)0x16) /* CAN SCE Interrupt */
#define EXTI9_5_IRQChannel ((u8)0x17) /* External Line[9:5] Interrupts */
#define TIM1_BRK_IRQChannel ((u8)0x18) /* TIM1 Break Interrupt */
#define TIM1_UP_IRQChannel ((u8)0x19) /* TIM1 Update Interrupt */
#define TIM1_TRG_COM_IRQChannel ((u8)0x1A) /* TIM1 Trigger and Commutation Interrupt */
#define TIM1_CC_IRQChannel ((u8)0x1B) /* TIM1 Capture Compare Interrupt */
#define TIM2_IRQChannel ((u8)0x1C) /* TIM2 global Interrupt */
#define TIM3_IRQChannel ((u8)0x1D) /* TIM3 global Interrupt */
#define TIM4_IRQChannel ((u8)0x1E) /* TIM4 global Interrupt */
#define I2C1_EV_IRQChannel ((u8)0x1F) /* I2C1 Event Interrupt */
#define I2C1_ER_IRQChannel ((u8)0x20) /* I2C1 Error Interrupt */
#define I2C2_EV_IRQChannel ((u8)0x21) /* I2C2 Event Interrupt */
#define I2C2_ER_IRQChannel ((u8)0x22) /* I2C2 Error Interrupt */
#define SPI1_IRQChannel ((u8)0x23) /* SPI1 global Interrupt */
#define SPI2_IRQChannel ((u8)0x24) /* SPI2 global Interrupt */
#define USART1_IRQChannel ((u8)0x25) /* USART1 global Interrupt */
#define USART2_IRQChannel ((u8)0x26) /* USART2 global Interrupt */
#define USART3_IRQChannel ((u8)0x27) /* USART3 global Interrupt */
#define EXTI15_10_IRQChannel ((u8)0x28) /* External Line[15:10] Interrupts */
#define RTCAlarm_IRQChannel ((u8)0x29) /* RTC Alarm through EXTI Line Interrupt */
#define USBWakeUp_IRQChannel ((u8)0x2A) /* USB WakeUp from suspend through EXTI Line Interrupt */
#define TIM8_BRK_IRQChannel ((u8)0x2B) /* TIM8 Break Interrupt */
#define TIM8_UP_IRQChannel ((u8)0x2C) /* TIM8 Update Interrupt */
#define TIM8_TRG_COM_IRQChannel ((u8)0x2D) /* TIM8 Trigger and Commutation Interrupt */
#define TIM8_CC_IRQChannel ((u8)0x2E) /* TIM8 Capture Compare Interrupt */
#define ADC3_IRQChannel ((u8)0x2F) /* ADC3 global Interrupt */
#define FSMC_IRQChannel ((u8)0x30) /* FSMC global Interrupt */
#define SDIO_IRQChannel ((u8)0x31) /* SDIO global Interrupt */
#define TIM5_IRQChannel ((u8)0x32) /* TIM5 global Interrupt */
#define SPI3_IRQChannel ((u8)0x33) /* SPI3 global Interrupt */
#define UART4_IRQChannel ((u8)0x34) /* UART4 global Interrupt */
#define UART5_IRQChannel ((u8)0x35) /* UART5 global Interrupt */
#define TIM6_IRQChannel ((u8)0x36) /* TIM6 global Interrupt */
#define TIM7_IRQChannel ((u8)0x37) /* TIM7 global Interrupt */
#define DMA2_Channel1_IRQChannel ((u8)0x38) /* DMA2 Channel 1 global Interrupt */
#define DMA2_Channel2_IRQChannel ((u8)0x39) /* DMA2 Channel 2 global Interrupt */
#define DMA2_Channel3_IRQChannel ((u8)0x3A) /* DMA2 Channel 3 global Interrupt */
#define DMA2_Channel4_5_IRQChannel ((u8)0x3B) /* DMA2 Channel 4 and DMA2 Channel 5 global Interrupt */
#define IS_NVIC_IRQ_CHANNEL(CHANNEL) (((CHANNEL) == WWDG_IRQChannel) || \
((CHANNEL) == PVD_IRQChannel) || \
((CHANNEL) == TAMPER_IRQChannel) || \
((CHANNEL) == RTC_IRQChannel) || \
((CHANNEL) == FLASH_IRQChannel) || \
((CHANNEL) == RCC_IRQChannel) || \
((CHANNEL) == EXTI0_IRQChannel) || \
((CHANNEL) == EXTI1_IRQChannel) || \
((CHANNEL) == EXTI2_IRQChannel) || \
((CHANNEL) == EXTI3_IRQChannel) || \
((CHANNEL) == EXTI4_IRQChannel) || \
((CHANNEL) == DMA1_Channel1_IRQChannel) || \
((CHANNEL) == DMA1_Channel2_IRQChannel) || \
((CHANNEL) == DMA1_Channel3_IRQChannel) || \
((CHANNEL) == DMA1_Channel4_IRQChannel) || \
((CHANNEL) == DMA1_Channel5_IRQChannel) || \
((CHANNEL) == DMA1_Channel6_IRQChannel) || \
((CHANNEL) == DMA1_Channel7_IRQChannel) || \
((CHANNEL) == ADC1_2_IRQChannel) || \
((CHANNEL) == USB_HP_CAN_TX_IRQChannel) || \
((CHANNEL) == USB_LP_CAN_RX0_IRQChannel) || \
((CHANNEL) == CAN_RX1_IRQChannel) || \
((CHANNEL) == CAN_SCE_IRQChannel) || \
((CHANNEL) == EXTI9_5_IRQChannel) || \
((CHANNEL) == TIM1_BRK_IRQChannel) || \
((CHANNEL) == TIM1_UP_IRQChannel) || \
((CHANNEL) == TIM1_TRG_COM_IRQChannel) || \
((CHANNEL) == TIM1_CC_IRQChannel) || \
((CHANNEL) == TIM2_IRQChannel) || \
((CHANNEL) == TIM3_IRQChannel) || \
((CHANNEL) == TIM4_IRQChannel) || \
((CHANNEL) == I2C1_EV_IRQChannel) || \
((CHANNEL) == I2C1_ER_IRQChannel) || \
((CHANNEL) == I2C2_EV_IRQChannel) || \
((CHANNEL) == I2C2_ER_IRQChannel) || \
((CHANNEL) == SPI1_IRQChannel) || \
((CHANNEL) == SPI2_IRQChannel) || \
((CHANNEL) == USART1_IRQChannel) || \
((CHANNEL) == USART2_IRQChannel) || \
((CHANNEL) == USART3_IRQChannel) || \
((CHANNEL) == EXTI15_10_IRQChannel) || \
((CHANNEL) == RTCAlarm_IRQChannel) || \
((CHANNEL) == USBWakeUp_IRQChannel) || \
((CHANNEL) == TIM8_BRK_IRQChannel) || \
((CHANNEL) == TIM8_UP_IRQChannel) || \
((CHANNEL) == TIM8_TRG_COM_IRQChannel) || \
((CHANNEL) == TIM8_CC_IRQChannel) || \
((CHANNEL) == ADC3_IRQChannel) || \
((CHANNEL) == FSMC_IRQChannel) || \
((CHANNEL) == SDIO_IRQChannel) || \
((CHANNEL) == TIM5_IRQChannel) || \
((CHANNEL) == SPI3_IRQChannel) || \
((CHANNEL) == UART4_IRQChannel) || \
((CHANNEL) == UART5_IRQChannel) || \
((CHANNEL) == TIM6_IRQChannel) || \
((CHANNEL) == TIM7_IRQChannel) || \
((CHANNEL) == DMA2_Channel1_IRQChannel) || \
((CHANNEL) == DMA2_Channel2_IRQChannel) || \
((CHANNEL) == DMA2_Channel3_IRQChannel) || \
((CHANNEL) == DMA2_Channel4_5_IRQChannel))
/* System Handlers -----------------------------------------------------------*/
#define SystemHandler_NMI ((u32)0x00001F) /* NMI Handler */
#define SystemHandler_HardFault ((u32)0x000000) /* Hard Fault Handler */
#define SystemHandler_MemoryManage ((u32)0x043430) /* Memory Manage Handler */
#define SystemHandler_BusFault ((u32)0x547931) /* Bus Fault Handler */
#define SystemHandler_UsageFault ((u32)0x24C232) /* Usage Fault Handler */
#define SystemHandler_SVCall ((u32)0x01FF40) /* SVCall Handler */
#define SystemHandler_DebugMonitor ((u32)0x0A0080) /* Debug Monitor Handler */
#define SystemHandler_PSV ((u32)0x02829C) /* PSV Handler */
#define SystemHandler_SysTick ((u32)0x02C39A) /* SysTick Handler */
#define IS_CONFIG_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \
((HANDLER) == SystemHandler_BusFault) || \
((HANDLER) == SystemHandler_UsageFault))
#define IS_PRIORITY_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \
((HANDLER) == SystemHandler_BusFault) || \
((HANDLER) == SystemHandler_UsageFault) || \
((HANDLER) == SystemHandler_SVCall) || \
((HANDLER) == SystemHandler_DebugMonitor) || \
((HANDLER) == SystemHandler_PSV) || \
((HANDLER) == SystemHandler_SysTick))
#define IS_GET_PENDING_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \
((HANDLER) == SystemHandler_BusFault) || \
((HANDLER) == SystemHandler_SVCall))
#define IS_SET_PENDING_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_NMI) || \
((HANDLER) == SystemHandler_PSV) || \
((HANDLER) == SystemHandler_SysTick))
#define IS_CLEAR_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_PSV) || \
((HANDLER) == SystemHandler_SysTick))
#define IS_GET_ACTIVE_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \
((HANDLER) == SystemHandler_BusFault) || \
((HANDLER) == SystemHandler_UsageFault) || \
((HANDLER) == SystemHandler_SVCall) || \
((HANDLER) == SystemHandler_DebugMonitor) || \
((HANDLER) == SystemHandler_PSV) || \
((HANDLER) == SystemHandler_SysTick))
#define IS_FAULT_SOURCE_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_HardFault) || \
((HANDLER) == SystemHandler_MemoryManage) || \
((HANDLER) == SystemHandler_BusFault) || \
((HANDLER) == SystemHandler_UsageFault) || \
((HANDLER) == SystemHandler_DebugMonitor))
#define IS_FAULT_ADDRESS_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \
((HANDLER) == SystemHandler_BusFault))
/* Vector Table Base ---------------------------------------------------------*/
#define NVIC_VectTab_RAM ((u32)0x20000000)
#define NVIC_VectTab_FLASH ((u32)0x08000000)
#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
((VECTTAB) == NVIC_VectTab_FLASH))
/* System Low Power ----------------------------------------------------------*/
#define NVIC_LP_SEVONPEND ((u8)0x10)
#define NVIC_LP_SLEEPDEEP ((u8)0x04)
#define NVIC_LP_SLEEPONEXIT ((u8)0x02)
#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
((LP) == NVIC_LP_SLEEPDEEP) || \
((LP) == NVIC_LP_SLEEPONEXIT))
/* Preemption Priority Group -------------------------------------------------*/
#define NVIC_PriorityGroup_0 ((u32)0x700) /* 0 bits for pre-emption priority
4 bits for subpriority */
#define NVIC_PriorityGroup_1 ((u32)0x600) /* 1 bits for pre-emption priority
3 bits for subpriority */
#define NVIC_PriorityGroup_2 ((u32)0x500) /* 2 bits for pre-emption priority
2 bits for subpriority */
#define NVIC_PriorityGroup_3 ((u32)0x400) /* 3 bits for pre-emption priority
1 bits for subpriority */
#define NVIC_PriorityGroup_4 ((u32)0x300) /* 4 bits for pre-emption priority
0 bits for subpriority */
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
((GROUP) == NVIC_PriorityGroup_1) || \
((GROUP) == NVIC_PriorityGroup_2) || \
((GROUP) == NVIC_PriorityGroup_3) || \
((GROUP) == NVIC_PriorityGroup_4))
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x0007FFFF)
#define IS_NVIC_BASE_PRI(PRI) ((PRI) < 0x10)
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void NVIC_DeInit(void);
void NVIC_SCBDeInit(void);
void NVIC_PriorityGroupConfig(u32 NVIC_PriorityGroup);
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
void NVIC_StructInit(NVIC_InitTypeDef* NVIC_InitStruct);
void NVIC_SETPRIMASK(void);
void NVIC_RESETPRIMASK(void);
void NVIC_SETFAULTMASK(void);
void NVIC_RESETFAULTMASK(void);
void NVIC_BASEPRICONFIG(u32 NewPriority);
u32 NVIC_GetBASEPRI(void);
u16 NVIC_GetCurrentPendingIRQChannel(void);
ITStatus NVIC_GetIRQChannelPendingBitStatus(u8 NVIC_IRQChannel);
void NVIC_SetIRQChannelPendingBit(u8 NVIC_IRQChannel);
void NVIC_ClearIRQChannelPendingBit(u8 NVIC_IRQChannel);
u16 NVIC_GetCurrentActiveHandler(void);
ITStatus NVIC_GetIRQChannelActiveBitStatus(u8 NVIC_IRQChannel);
u32 NVIC_GetCPUID(void);
void NVIC_SetVectorTable(u32 NVIC_VectTab, u32 Offset);
void NVIC_GenerateSystemReset(void);
void NVIC_GenerateCoreReset(void);
void NVIC_SystemLPConfig(u8 LowPowerMode, FunctionalState NewState);
void NVIC_SystemHandlerConfig(u32 SystemHandler, FunctionalState NewState);
void NVIC_SystemHandlerPriorityConfig(u32 SystemHandler, u8 SystemHandlerPreemptionPriority,
u8 SystemHandlerSubPriority);
ITStatus NVIC_GetSystemHandlerPendingBitStatus(u32 SystemHandler);
void NVIC_SetSystemHandlerPendingBit(u32 SystemHandler);
void NVIC_ClearSystemHandlerPendingBit(u32 SystemHandler);
ITStatus NVIC_GetSystemHandlerActiveBitStatus(u32 SystemHandler);
u32 NVIC_GetFaultHandlerSources(u32 SystemHandler);
u32 NVIC_GetFaultAddress(u32 SystemHandler);
#endif /* __STM32F10x_NVIC_H */
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

77
bsp/stm32f103vb_lwip/library/inc/stm32f10x_pwr.h Normal file
View File

@ -0,0 +1,77 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_pwr.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the functions prototypes for the
* PWR firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_PWR_H
#define __STM32F10x_PWR_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* PVD detection level */
#define PWR_PVDLevel_2V2 ((u32)0x00000000)
#define PWR_PVDLevel_2V3 ((u32)0x00000020)
#define PWR_PVDLevel_2V4 ((u32)0x00000040)
#define PWR_PVDLevel_2V5 ((u32)0x00000060)
#define PWR_PVDLevel_2V6 ((u32)0x00000080)
#define PWR_PVDLevel_2V7 ((u32)0x000000A0)
#define PWR_PVDLevel_2V8 ((u32)0x000000C0)
#define PWR_PVDLevel_2V9 ((u32)0x000000E0)
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \
((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \
((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \
((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9))
/* Regulator state is STOP mode */
#define PWR_Regulator_ON ((u32)0x00000000)
#define PWR_Regulator_LowPower ((u32)0x00000001)
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
((REGULATOR) == PWR_Regulator_LowPower))
/* STOP mode entry */
#define PWR_STOPEntry_WFI ((u8)0x01)
#define PWR_STOPEntry_WFE ((u8)0x02)
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
/* PWR Flag */
#define PWR_FLAG_WU ((u32)0x00000001)
#define PWR_FLAG_SB ((u32)0x00000002)
#define PWR_FLAG_PVDO ((u32)0x00000004)
#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
((FLAG) == PWR_FLAG_PVDO))
#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void PWR_DeInit(void);
void PWR_BackupAccessCmd(FunctionalState NewState);
void PWR_PVDCmd(FunctionalState NewState);
void PWR_PVDLevelConfig(u32 PWR_PVDLevel);
void PWR_WakeUpPinCmd(FunctionalState NewState);
void PWR_EnterSTOPMode(u32 PWR_Regulator, u8 PWR_STOPEntry);
void PWR_EnterSTANDBYMode(void);
FlagStatus PWR_GetFlagStatus(u32 PWR_FLAG);
void PWR_ClearFlag(u32 PWR_FLAG);
#endif /* __STM32F10x_PWR_H */
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

288
bsp/stm32f103vb_lwip/library/inc/stm32f10x_rcc.h Normal file
View File

@ -0,0 +1,288 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_rcc.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the functions prototypes for the
* RCC firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_RCC_H
#define __STM32F10x_RCC_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
/* Exported types ------------------------------------------------------------*/
typedef struct
{
u32 SYSCLK_Frequency;
u32 HCLK_Frequency;
u32 PCLK1_Frequency;
u32 PCLK2_Frequency;
u32 ADCCLK_Frequency;
}RCC_ClocksTypeDef;
/* Exported constants --------------------------------------------------------*/
/* HSE configuration */
#define RCC_HSE_OFF ((u32)0x00000000)
#define RCC_HSE_ON ((u32)0x00010000)
#define RCC_HSE_Bypass ((u32)0x00040000)
#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
((HSE) == RCC_HSE_Bypass))
/* PLL entry clock source */
#define RCC_PLLSource_HSI_Div2 ((u32)0x00000000)
#define RCC_PLLSource_HSE_Div1 ((u32)0x00010000)
#define RCC_PLLSource_HSE_Div2 ((u32)0x00030000)
#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
((SOURCE) == RCC_PLLSource_HSE_Div1) || \
((SOURCE) == RCC_PLLSource_HSE_Div2))
/* PLL multiplication factor */
#define RCC_PLLMul_2 ((u32)0x00000000)
#define RCC_PLLMul_3 ((u32)0x00040000)
#define RCC_PLLMul_4 ((u32)0x00080000)
#define RCC_PLLMul_5 ((u32)0x000C0000)
#define RCC_PLLMul_6 ((u32)0x00100000)
#define RCC_PLLMul_7 ((u32)0x00140000)
#define RCC_PLLMul_8 ((u32)0x00180000)
#define RCC_PLLMul_9 ((u32)0x001C0000)
#define RCC_PLLMul_10 ((u32)0x00200000)
#define RCC_PLLMul_11 ((u32)0x00240000)
#define RCC_PLLMul_12 ((u32)0x00280000)
#define RCC_PLLMul_13 ((u32)0x002C0000)
#define RCC_PLLMul_14 ((u32)0x00300000)
#define RCC_PLLMul_15 ((u32)0x00340000)
#define RCC_PLLMul_16 ((u32)0x00380000)
#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \
((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
((MUL) == RCC_PLLMul_16))
/* System clock source */
#define RCC_SYSCLKSource_HSI ((u32)0x00000000)
#define RCC_SYSCLKSource_HSE ((u32)0x00000001)
#define RCC_SYSCLKSource_PLLCLK ((u32)0x00000002)
#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
((SOURCE) == RCC_SYSCLKSource_HSE) || \
((SOURCE) == RCC_SYSCLKSource_PLLCLK))
/* AHB clock source */
#define RCC_SYSCLK_Div1 ((u32)0x00000000)
#define RCC_SYSCLK_Div2 ((u32)0x00000080)
#define RCC_SYSCLK_Div4 ((u32)0x00000090)
#define RCC_SYSCLK_Div8 ((u32)0x000000A0)
#define RCC_SYSCLK_Div16 ((u32)0x000000B0)
#define RCC_SYSCLK_Div64 ((u32)0x000000C0)
#define RCC_SYSCLK_Div128 ((u32)0x000000D0)
#define RCC_SYSCLK_Div256 ((u32)0x000000E0)
#define RCC_SYSCLK_Div512 ((u32)0x000000F0)
#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
((HCLK) == RCC_SYSCLK_Div512))
/* APB1/APB2 clock source */
#define RCC_HCLK_Div1 ((u32)0x00000000)
#define RCC_HCLK_Div2 ((u32)0x00000400)
#define RCC_HCLK_Div4 ((u32)0x00000500)
#define RCC_HCLK_Div8 ((u32)0x00000600)
#define RCC_HCLK_Div16 ((u32)0x00000700)
#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
((PCLK) == RCC_HCLK_Div16))
/* RCC Interrupt source */
#define RCC_IT_LSIRDY ((u8)0x01)
#define RCC_IT_LSERDY ((u8)0x02)
#define RCC_IT_HSIRDY ((u8)0x04)
#define RCC_IT_HSERDY ((u8)0x08)
#define RCC_IT_PLLRDY ((u8)0x10)
#define RCC_IT_CSS ((u8)0x80)
#define IS_RCC_IT(IT) ((((IT) & (u8)0xE0) == 0x00) && ((IT) != 0x00))
#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS))
#define IS_RCC_CLEAR_IT(IT) ((((IT) & (u8)0x60) == 0x00) && ((IT) != 0x00))
/* USB clock source */
#define RCC_USBCLKSource_PLLCLK_1Div5 ((u8)0x00)
#define RCC_USBCLKSource_PLLCLK_Div1 ((u8)0x01)
#define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \
((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1))
/* ADC clock source */
#define RCC_PCLK2_Div2 ((u32)0x00000000)
#define RCC_PCLK2_Div4 ((u32)0x00004000)
#define RCC_PCLK2_Div6 ((u32)0x00008000)
#define RCC_PCLK2_Div8 ((u32)0x0000C000)
#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \
((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8))
/* LSE configuration */
#define RCC_LSE_OFF ((u8)0x00)
#define RCC_LSE_ON ((u8)0x01)
#define RCC_LSE_Bypass ((u8)0x04)
#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
((LSE) == RCC_LSE_Bypass))
/* RTC clock source */
#define RCC_RTCCLKSource_LSE ((u32)0x00000100)
#define RCC_RTCCLKSource_LSI ((u32)0x00000200)
#define RCC_RTCCLKSource_HSE_Div128 ((u32)0x00000300)
#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
((SOURCE) == RCC_RTCCLKSource_LSI) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div128))
/* AHB peripheral */
#define RCC_AHBPeriph_DMA1 ((u32)0x00000001)
#define RCC_AHBPeriph_DMA2 ((u32)0x00000002)
#define RCC_AHBPeriph_SRAM ((u32)0x00000004)
#define RCC_AHBPeriph_FLITF ((u32)0x00000010)
#define RCC_AHBPeriph_CRC ((u32)0x00000040)
#define RCC_AHBPeriph_FSMC ((u32)0x00000100)
#define RCC_AHBPeriph_SDIO ((u32)0x00000400)
#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00))
/* APB2 peripheral */
#define RCC_APB2Periph_AFIO ((u32)0x00000001)
#define RCC_APB2Periph_GPIOA ((u32)0x00000004)
#define RCC_APB2Periph_GPIOB ((u32)0x00000008)
#define RCC_APB2Periph_GPIOC ((u32)0x00000010)
#define RCC_APB2Periph_GPIOD ((u32)0x00000020)
#define RCC_APB2Periph_GPIOE ((u32)0x00000040)
#define RCC_APB2Periph_GPIOF ((u32)0x00000080)
#define RCC_APB2Periph_GPIOG ((u32)0x00000100)
#define RCC_APB2Periph_ADC1 ((u32)0x00000200)
#define RCC_APB2Periph_ADC2 ((u32)0x00000400)
#define RCC_APB2Periph_TIM1 ((u32)0x00000800)
#define RCC_APB2Periph_SPI1 ((u32)0x00001000)
#define RCC_APB2Periph_TIM8 ((u32)0x00002000)
#define RCC_APB2Periph_USART1 ((u32)0x00004000)
#define RCC_APB2Periph_ADC3 ((u32)0x00008000)
#define RCC_APB2Periph_ALL ((u32)0x0000FFFD)
#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFF0002) == 0x00) && ((PERIPH) != 0x00))
/* APB1 peripheral */
#define RCC_APB1Periph_TIM2 ((u32)0x00000001)
#define RCC_APB1Periph_TIM3 ((u32)0x00000002)
#define RCC_APB1Periph_TIM4 ((u32)0x00000004)
#define RCC_APB1Periph_TIM5 ((u32)0x00000008)
#define RCC_APB1Periph_TIM6 ((u32)0x00000010)
#define RCC_APB1Periph_TIM7 ((u32)0x00000020)
#define RCC_APB1Periph_WWDG ((u32)0x00000800)
#define RCC_APB1Periph_SPI2 ((u32)0x00004000)
#define RCC_APB1Periph_SPI3 ((u32)0x00008000)
#define RCC_APB1Periph_USART2 ((u32)0x00020000)
#define RCC_APB1Periph_USART3 ((u32)0x00040000)
#define RCC_APB1Periph_UART4 ((u32)0x00080000)
#define RCC_APB1Periph_UART5 ((u32)0x00100000)
#define RCC_APB1Periph_I2C1 ((u32)0x00200000)
#define RCC_APB1Periph_I2C2 ((u32)0x00400000)
#define RCC_APB1Periph_USB ((u32)0x00800000)
#define RCC_APB1Periph_CAN ((u32)0x02000000)
#define RCC_APB1Periph_BKP ((u32)0x08000000)
#define RCC_APB1Periph_PWR ((u32)0x10000000)
#define RCC_APB1Periph_DAC ((u32)0x20000000)
#define RCC_APB1Periph_ALL ((u32)0x3AFEC83F)
#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC50137C0) == 0x00) && ((PERIPH) != 0x00))
/* Clock source to output on MCO pin */
#define RCC_MCO_NoClock ((u8)0x00)
#define RCC_MCO_SYSCLK ((u8)0x04)
#define RCC_MCO_HSI ((u8)0x05)
#define RCC_MCO_HSE ((u8)0x06)
#define RCC_MCO_PLLCLK_Div2 ((u8)0x07)
#define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \
((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \
((MCO) == RCC_MCO_PLLCLK_Div2))
/* RCC Flag */
#define RCC_FLAG_HSIRDY ((u8)0x21)
#define RCC_FLAG_HSERDY ((u8)0x31)
#define RCC_FLAG_PLLRDY ((u8)0x39)
#define RCC_FLAG_LSERDY ((u8)0x41)
#define RCC_FLAG_LSIRDY ((u8)0x61)
#define RCC_FLAG_PINRST ((u8)0x7A)
#define RCC_FLAG_PORRST ((u8)0x7B)
#define RCC_FLAG_SFTRST ((u8)0x7C)
#define RCC_FLAG_IWDGRST ((u8)0x7D)
#define RCC_FLAG_WWDGRST ((u8)0x7E)
#define RCC_FLAG_LPWRRST ((u8)0x7F)
#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \
((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \
((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \
((FLAG) == RCC_FLAG_LPWRRST))
#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void RCC_DeInit(void);
void RCC_HSEConfig(u32 RCC_HSE);
ErrorStatus RCC_WaitForHSEStartUp(void);
void RCC_AdjustHSICalibrationValue(u8 HSICalibrationValue);
void RCC_HSICmd(FunctionalState NewState);
void RCC_PLLConfig(u32 RCC_PLLSource, u32 RCC_PLLMul);
void RCC_PLLCmd(FunctionalState NewState);
void RCC_SYSCLKConfig(u32 RCC_SYSCLKSource);
u8 RCC_GetSYSCLKSource(void);
void RCC_HCLKConfig(u32 RCC_SYSCLK);
void RCC_PCLK1Config(u32 RCC_HCLK);
void RCC_PCLK2Config(u32 RCC_HCLK);
void RCC_ITConfig(u8 RCC_IT, FunctionalState NewState);
void RCC_USBCLKConfig(u32 RCC_USBCLKSource);
void RCC_ADCCLKConfig(u32 RCC_PCLK2);
void RCC_LSEConfig(u8 RCC_LSE);
void RCC_LSICmd(FunctionalState NewState);
void RCC_RTCCLKConfig(u32 RCC_RTCCLKSource);
void RCC_RTCCLKCmd(FunctionalState NewState);
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
void RCC_AHBPeriphClockCmd(u32 RCC_AHBPeriph, FunctionalState NewState);
void RCC_APB2PeriphClockCmd(u32 RCC_APB2Periph, FunctionalState NewState);
void RCC_APB1PeriphClockCmd(u32 RCC_APB1Periph, FunctionalState NewState);
void RCC_APB2PeriphResetCmd(u32 RCC_APB2Periph, FunctionalState NewState);
void RCC_APB1PeriphResetCmd(u32 RCC_APB1Periph, FunctionalState NewState);
void RCC_BackupResetCmd(FunctionalState NewState);
void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
void RCC_MCOConfig(u8 RCC_MCO);
FlagStatus RCC_GetFlagStatus(u8 RCC_FLAG);
void RCC_ClearFlag(void);
ITStatus RCC_GetITStatus(u8 RCC_IT);
void RCC_ClearITPendingBit(u8 RCC_IT);
#endif /* __STM32F10x_RCC_H */
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

70
bsp/stm32f103vb_lwip/library/inc/stm32f10x_rtc.h Normal file
View File

@ -0,0 +1,70 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_rtc.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the functions prototypes for the
* RTC firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_RTC_H
#define __STM32F10x_RTC_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* RTC interrupts define -----------------------------------------------------*/
#define RTC_IT_OW ((u16)0x0004) /* Overflow interrupt */
#define RTC_IT_ALR ((u16)0x0002) /* Alarm interrupt */
#define RTC_IT_SEC ((u16)0x0001) /* Second interrupt */
#define IS_RTC_IT(IT) ((((IT) & (u16)0xFFF8) == 0x00) && ((IT) != 0x00))
#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || \
((IT) == RTC_IT_SEC))
/* RTC interrupts flags ------------------------------------------------------*/
#define RTC_FLAG_RTOFF ((u16)0x0020) /* RTC Operation OFF flag */
#define RTC_FLAG_RSF ((u16)0x0008) /* Registers Synchronized flag */
#define RTC_FLAG_OW ((u16)0x0004) /* Overflow flag */
#define RTC_FLAG_ALR ((u16)0x0002) /* Alarm flag */
#define RTC_FLAG_SEC ((u16)0x0001) /* Second flag */
#define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (u16)0xFFF0) == 0x00) && ((FLAG) != 0x00))
#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || \
((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || \
((FLAG) == RTC_FLAG_SEC))
#define IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF)
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void RTC_ITConfig(u16 RTC_IT, FunctionalState NewState);
void RTC_EnterConfigMode(void);
void RTC_ExitConfigMode(void);
u32 RTC_GetCounter(void);
void RTC_SetCounter(u32 CounterValue);
void RTC_SetPrescaler(u32 PrescalerValue);
void RTC_SetAlarm(u32 AlarmValue);
u32 RTC_GetDivider(void);
void RTC_WaitForLastTask(void);
void RTC_WaitForSynchro(void);
FlagStatus RTC_GetFlagStatus(u16 RTC_FLAG);
void RTC_ClearFlag(u16 RTC_FLAG);
ITStatus RTC_GetITStatus(u16 RTC_IT);
void RTC_ClearITPendingBit(u16 RTC_IT);
#endif /* __STM32F10x_RTC_H */
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

337
bsp/stm32f103vb_lwip/library/inc/stm32f10x_sdio.h Normal file
View File

@ -0,0 +1,337 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_sdio.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the functions prototypes for the
* SDIO firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_SDIO_H
#define __STM32F10x_SDIO_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
/* Exported types ------------------------------------------------------------*/
typedef struct
{
u8 SDIO_ClockDiv;
u32 SDIO_ClockEdge;
u32 SDIO_ClockBypass;
u32 SDIO_ClockPowerSave;
u32 SDIO_BusWide;
u32 SDIO_HardwareFlowControl;
} SDIO_InitTypeDef;
typedef struct
{
u32 SDIO_Argument;
u32 SDIO_CmdIndex;
u32 SDIO_Response;
u32 SDIO_Wait;
u32 SDIO_CPSM;
} SDIO_CmdInitTypeDef;
typedef struct
{
u32 SDIO_DataTimeOut;
u32 SDIO_DataLength;
u32 SDIO_DataBlockSize;
u32 SDIO_TransferDir;
u32 SDIO_TransferMode;
u32 SDIO_DPSM;
} SDIO_DataInitTypeDef;
/* Exported constants --------------------------------------------------------*/
/* SDIO Clock Edge -----------------------------------------------------------*/
#define SDIO_ClockEdge_Rising ((u32)0x00000000)
#define SDIO_ClockEdge_Falling ((u32)0x00002000)
#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \
((EDGE) == SDIO_ClockEdge_Falling))
/* SDIO Clock Bypass ----------------------------------------------------------*/
#define SDIO_ClockBypass_Disable ((u32)0x00000000)
#define SDIO_ClockBypass_Enable ((u32)0x00000400)
#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \
((BYPASS) == SDIO_ClockBypass_Enable))
/* SDIO Clock Power Save ----------------------------------------------------*/
#define SDIO_ClockPowerSave_Disable ((u32)0x00000000)
#define SDIO_ClockPowerSave_Enable ((u32)0x00000200)
#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \
((SAVE) == SDIO_ClockPowerSave_Enable))
/* SDIO Bus Wide -------------------------------------------------------------*/
#define SDIO_BusWide_1b ((u32)0x00000000)
#define SDIO_BusWide_4b ((u32)0x00000800)
#define SDIO_BusWide_8b ((u32)0x00001000)
#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \
((WIDE) == SDIO_BusWide_8b))
/* SDIO Hardware Flow Control -----------------------------------------------*/
#define SDIO_HardwareFlowControl_Disable ((u32)0x00000000)
#define SDIO_HardwareFlowControl_Enable ((u32)0x00004000)
#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \
((CONTROL) == SDIO_HardwareFlowControl_Enable))
/* SDIO Power State ----------------------------------------------------------*/
#define SDIO_PowerState_OFF ((u32)0x00000000)
#define SDIO_PowerState_ON ((u32)0x00000003)
#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON))
/* SDIO Interrupt soucres ----------------------------------------------------*/
#define SDIO_IT_CCRCFAIL ((u32)0x00000001)
#define SDIO_IT_DCRCFAIL ((u32)0x00000002)
#define SDIO_IT_CTIMEOUT ((u32)0x00000004)
#define SDIO_IT_DTIMEOUT ((u32)0x00000008)
#define SDIO_IT_TXUNDERR ((u32)0x00000010)
#define SDIO_IT_RXOVERR ((u32)0x00000020)
#define SDIO_IT_CMDREND ((u32)0x00000040)
#define SDIO_IT_CMDSENT ((u32)0x00000080)
#define SDIO_IT_DATAEND ((u32)0x00000100)
#define SDIO_IT_STBITERR ((u32)0x00000200)
#define SDIO_IT_DBCKEND ((u32)0x00000400)
#define SDIO_IT_CMDACT ((u32)0x00000800)
#define SDIO_IT_TXACT ((u32)0x00001000)
#define SDIO_IT_RXACT ((u32)0x00002000)
#define SDIO_IT_TXFIFOHE ((u32)0x00004000)
#define SDIO_IT_RXFIFOHF ((u32)0x00008000)
#define SDIO_IT_TXFIFOF ((u32)0x00010000)
#define SDIO_IT_RXFIFOF ((u32)0x00020000)
#define SDIO_IT_TXFIFOE ((u32)0x00040000)
#define SDIO_IT_RXFIFOE ((u32)0x00080000)
#define SDIO_IT_TXDAVL ((u32)0x00100000)
#define SDIO_IT_RXDAVL ((u32)0x00200000)
#define SDIO_IT_SDIOIT ((u32)0x00400000)
#define SDIO_IT_CEATAEND ((u32)0x00800000)
#define IS_SDIO_IT(IT) ((((IT) & (u32)0xFF000000) == 0x00) && ((IT) != (u32)0x00))
/* SDIO Command Index -------------------------------------------------------*/
#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
/* SDIO Response Type --------------------------------------------------------*/
#define SDIO_Response_No ((u32)0x00000000)
#define SDIO_Response_Short ((u32)0x00000040)
#define SDIO_Response_Long ((u32)0x000000C0)
#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \
((RESPONSE) == SDIO_Response_Short) || \
((RESPONSE) == SDIO_Response_Long))
/* SDIO Wait Interrupt State -------------------------------------------------*/
#define SDIO_Wait_No ((u32)0x00000000) /* SDIO No Wait, TimeOut is enabled */
#define SDIO_Wait_IT ((u32)0x00000100) /* SDIO Wait Interrupt Request */
#define SDIO_Wait_Pend ((u32)0x00000200) /* SDIO Wait End of transfer */
#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \
((WAIT) == SDIO_Wait_Pend))
/* SDIO CPSM State -----------------------------------------------------------*/
#define SDIO_CPSM_Disable ((u32)0x00000000)
#define SDIO_CPSM_Enable ((u32)0x00000400)
#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))
/* SDIO Response Registers ---------------------------------------------------*/
#define SDIO_RESP1 ((u32)0x00000000)
#define SDIO_RESP2 ((u32)0x00000004)
#define SDIO_RESP3 ((u32)0x00000008)
#define SDIO_RESP4 ((u32)0x0000000C)
#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \
((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))
/* SDIO Data Length ----------------------------------------------------------*/
#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
/* SDIO Data Block Size ------------------------------------------------------*/
#define SDIO_DataBlockSize_1b ((u32)0x00000000)
#define SDIO_DataBlockSize_2b ((u32)0x00000010)
#define SDIO_DataBlockSize_4b ((u32)0x00000020)
#define SDIO_DataBlockSize_8b ((u32)0x00000030)
#define SDIO_DataBlockSize_16b ((u32)0x00000040)
#define SDIO_DataBlockSize_32b ((u32)0x00000050)
#define SDIO_DataBlockSize_64b ((u32)0x00000060)
#define SDIO_DataBlockSize_128b ((u32)0x00000070)
#define SDIO_DataBlockSize_256b ((u32)0x00000080)
#define SDIO_DataBlockSize_512b ((u32)0x00000090)
#define SDIO_DataBlockSize_1024b ((u32)0x000000A0)
#define SDIO_DataBlockSize_2048b ((u32)0x000000B0)
#define SDIO_DataBlockSize_4096b ((u32)0x000000C0)
#define SDIO_DataBlockSize_8192b ((u32)0x000000D0)
#define SDIO_DataBlockSize_16384b ((u32)0x000000E0)
#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \
((SIZE) == SDIO_DataBlockSize_2b) || \
((SIZE) == SDIO_DataBlockSize_4b) || \
((SIZE) == SDIO_DataBlockSize_8b) || \
((SIZE) == SDIO_DataBlockSize_16b) || \
((SIZE) == SDIO_DataBlockSize_32b) || \
((SIZE) == SDIO_DataBlockSize_64b) || \
((SIZE) == SDIO_DataBlockSize_128b) || \
((SIZE) == SDIO_DataBlockSize_256b) || \
((SIZE) == SDIO_DataBlockSize_512b) || \
((SIZE) == SDIO_DataBlockSize_1024b) || \
((SIZE) == SDIO_DataBlockSize_2048b) || \
((SIZE) == SDIO_DataBlockSize_4096b) || \
((SIZE) == SDIO_DataBlockSize_8192b) || \
((SIZE) == SDIO_DataBlockSize_16384b))
/* SDIO Transfer Direction ---------------------------------------------------*/
#define SDIO_TransferDir_ToCard ((u32)0x00000000)
#define SDIO_TransferDir_ToSDIO ((u32)0x00000002)
#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \
((DIR) == SDIO_TransferDir_ToSDIO))
/* SDIO Transfer Type --------------------------------------------------------*/
#define SDIO_TransferMode_Block ((u32)0x00000000)
#define SDIO_TransferMode_Stream ((u32)0x00000004)
#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \
((MODE) == SDIO_TransferMode_Block))
/* SDIO DPSM State -----------------------------------------------------------*/
#define SDIO_DPSM_Disable ((u32)0x00000000)
#define SDIO_DPSM_Enable ((u32)0x00000001)
#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))
/* SDIO Flags ----------------------------------------------------------------*/
#define SDIO_FLAG_CCRCFAIL ((u32)0x00000001)
#define SDIO_FLAG_DCRCFAIL ((u32)0x00000002)
#define SDIO_FLAG_CTIMEOUT ((u32)0x00000004)
#define SDIO_FLAG_DTIMEOUT ((u32)0x00000008)
#define SDIO_FLAG_TXUNDERR ((u32)0x00000010)
#define SDIO_FLAG_RXOVERR ((u32)0x00000020)
#define SDIO_FLAG_CMDREND ((u32)0x00000040)
#define SDIO_FLAG_CMDSENT ((u32)0x00000080)
#define SDIO_FLAG_DATAEND ((u32)0x00000100)
#define SDIO_FLAG_STBITERR ((u32)0x00000200)
#define SDIO_FLAG_DBCKEND ((u32)0x00000400)
#define SDIO_FLAG_CMDACT ((u32)0x00000800)
#define SDIO_FLAG_TXACT ((u32)0x00001000)
#define SDIO_FLAG_RXACT ((u32)0x00002000)
#define SDIO_FLAG_TXFIFOHE ((u32)0x00004000)
#define SDIO_FLAG_RXFIFOHF ((u32)0x00008000)
#define SDIO_FLAG_TXFIFOF ((u32)0x00010000)
#define SDIO_FLAG_RXFIFOF ((u32)0x00020000)
#define SDIO_FLAG_TXFIFOE ((u32)0x00040000)
#define SDIO_FLAG_RXFIFOE ((u32)0x00080000)
#define SDIO_FLAG_TXDAVL ((u32)0x00100000)
#define SDIO_FLAG_RXDAVL ((u32)0x00200000)
#define SDIO_FLAG_SDIOIT ((u32)0x00400000)
#define SDIO_FLAG_CEATAEND ((u32)0x00800000)
#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \
((FLAG) == SDIO_FLAG_DCRCFAIL) || \
((FLAG) == SDIO_FLAG_CTIMEOUT) || \
((FLAG) == SDIO_FLAG_DTIMEOUT) || \
((FLAG) == SDIO_FLAG_TXUNDERR) || \
((FLAG) == SDIO_FLAG_RXOVERR) || \
((FLAG) == SDIO_FLAG_CMDREND) || \
((FLAG) == SDIO_FLAG_CMDSENT) || \
((FLAG) == SDIO_FLAG_DATAEND) || \
((FLAG) == SDIO_FLAG_STBITERR) || \
((FLAG) == SDIO_FLAG_DBCKEND) || \
((FLAG) == SDIO_FLAG_CMDACT) || \
((FLAG) == SDIO_FLAG_TXACT) || \
((FLAG) == SDIO_FLAG_RXACT) || \
((FLAG) == SDIO_FLAG_TXFIFOHE) || \
((FLAG) == SDIO_FLAG_RXFIFOHF) || \
((FLAG) == SDIO_FLAG_TXFIFOF) || \
((FLAG) == SDIO_FLAG_RXFIFOF) || \
((FLAG) == SDIO_FLAG_TXFIFOE) || \
((FLAG) == SDIO_FLAG_RXFIFOE) || \
((FLAG) == SDIO_FLAG_TXDAVL) || \
((FLAG) == SDIO_FLAG_RXDAVL) || \
((FLAG) == SDIO_FLAG_SDIOIT) || \
((FLAG) == SDIO_FLAG_CEATAEND))
#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (u32)0xFF3FF800) == 0x00) && ((FLAG) != (u32)0x00))
#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \
((IT) == SDIO_IT_DCRCFAIL) || \
((IT) == SDIO_IT_CTIMEOUT) || \
((IT) == SDIO_IT_DTIMEOUT) || \
((IT) == SDIO_IT_TXUNDERR) || \
((IT) == SDIO_IT_RXOVERR) || \
((IT) == SDIO_IT_CMDREND) || \
((IT) == SDIO_IT_CMDSENT) || \
((IT) == SDIO_IT_DATAEND) || \
((IT) == SDIO_IT_STBITERR) || \
((IT) == SDIO_IT_DBCKEND) || \
((IT) == SDIO_IT_CMDACT) || \
((IT) == SDIO_IT_TXACT) || \
((IT) == SDIO_IT_RXACT) || \
((IT) == SDIO_IT_TXFIFOHE) || \
((IT) == SDIO_IT_RXFIFOHF) || \
((IT) == SDIO_IT_TXFIFOF) || \
((IT) == SDIO_IT_RXFIFOF) || \
((IT) == SDIO_IT_TXFIFOE) || \
((IT) == SDIO_IT_RXFIFOE) || \
((IT) == SDIO_IT_TXDAVL) || \
((IT) == SDIO_IT_RXDAVL) || \
((IT) == SDIO_IT_SDIOIT) || \
((IT) == SDIO_IT_CEATAEND))
#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (u32)0xFF3FF800) == 0x00) && ((IT) != (u32)0x00))
/* SDIO Read Wait Mode -------------------------------------------------------*/
#define SDIO_ReadWaitMode_CLK ((u32)0x00000000)
#define SDIO_ReadWaitMode_DATA2 ((u32)0x00000001)
#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \
((MODE) == SDIO_ReadWaitMode_DATA2))
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void SDIO_DeInit(void);
void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);
void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
void SDIO_ClockCmd(FunctionalState NewState);
void SDIO_SetPowerState(u32 SDIO_PowerState);
u32 SDIO_GetPowerState(void);
void SDIO_ITConfig(u32 SDIO_IT, FunctionalState NewState);
void SDIO_DMACmd(FunctionalState NewState);
void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);
u8 SDIO_GetCommandResponse(void);
u32 SDIO_GetResponse(u32 SDIO_RESP);
void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
u32 SDIO_GetDataCounter(void);
u32 SDIO_ReadData(void);
void SDIO_WriteData(u32 Data);
u32 SDIO_GetFIFOCount(void);
void SDIO_StartSDIOReadWait(FunctionalState NewState);
void SDIO_StopSDIOReadWait(FunctionalState NewState);
void SDIO_SetSDIOReadWaitMode(u32 SDIO_ReadWaitMode);
void SDIO_SetSDIOOperation(FunctionalState NewState);
void SDIO_SendSDIOSuspendCmd(FunctionalState NewState);
void SDIO_CommandCompletionCmd(FunctionalState NewState);
void SDIO_CEATAITCmd(FunctionalState NewState);
void SDIO_SendCEATACmd(FunctionalState NewState);
FlagStatus SDIO_GetFlagStatus(u32 SDIO_FLAG);
void SDIO_ClearFlag(u32 SDIO_FLAG);
ITStatus SDIO_GetITStatus(u32 SDIO_IT);
void SDIO_ClearITPendingBit(u32 SDIO_IT);
#endif /* __STM32F10x_SDIO_H */
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

289
bsp/stm32f103vb_lwip/library/inc/stm32f10x_spi.h Normal file
View File

@ -0,0 +1,289 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_spi.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the functions prototypes for the
* SPI firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_SPI_H
#define __STM32F10x_SPI_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
/* Exported types ------------------------------------------------------------*/
/* SPI Init structure definition */
typedef struct
{
u16 SPI_Direction;
u16 SPI_Mode;
u16 SPI_DataSize;
u16 SPI_CPOL;
u16 SPI_CPHA;
u16 SPI_NSS;
u16 SPI_BaudRatePrescaler;
u16 SPI_FirstBit;
u16 SPI_CRCPolynomial;
}SPI_InitTypeDef;
/* I2S Init structure definition */
typedef struct
{
u16 I2S_Mode;
u16 I2S_Standard;
u16 I2S_DataFormat;
u16 I2S_MCLKOutput;
u16 I2S_AudioFreq;
u16 I2S_CPOL;
}I2S_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
#define IS_SPI_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == SPI1_BASE) || \
((*(u32*)&(PERIPH)) == SPI2_BASE) || \
((*(u32*)&(PERIPH)) == SPI3_BASE))
#define IS_SPI_23_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == SPI2_BASE) || \
((*(u32*)&(PERIPH)) == SPI3_BASE))
/* SPI data direction mode */
#define SPI_Direction_2Lines_FullDuplex ((u16)0x0000)
#define SPI_Direction_2Lines_RxOnly ((u16)0x0400)
#define SPI_Direction_1Line_Rx ((u16)0x8000)
#define SPI_Direction_1Line_Tx ((u16)0xC000)
#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
((MODE) == SPI_Direction_2Lines_RxOnly) || \
((MODE) == SPI_Direction_1Line_Rx) || \
((MODE) == SPI_Direction_1Line_Tx))
/* SPI master/slave mode */
#define SPI_Mode_Master ((u16)0x0104)
#define SPI_Mode_Slave ((u16)0x0000)
#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
((MODE) == SPI_Mode_Slave))
/* SPI data size */
#define SPI_DataSize_16b ((u16)0x0800)
#define SPI_DataSize_8b ((u16)0x0000)
#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \
((DATASIZE) == SPI_DataSize_8b))
/* SPI Clock Polarity */
#define SPI_CPOL_Low ((u16)0x0000)
#define SPI_CPOL_High ((u16)0x0002)
#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
((CPOL) == SPI_CPOL_High))
/* SPI Clock Phase */
#define SPI_CPHA_1Edge ((u16)0x0000)
#define SPI_CPHA_2Edge ((u16)0x0001)
#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
((CPHA) == SPI_CPHA_2Edge))
/* SPI Slave Select management */
#define SPI_NSS_Soft ((u16)0x0200)
#define SPI_NSS_Hard ((u16)0x0000)
#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
((NSS) == SPI_NSS_Hard))
/* SPI BaudRate Prescaler */
#define SPI_BaudRatePrescaler_2 ((u16)0x0000)
#define SPI_BaudRatePrescaler_4 ((u16)0x0008)
#define SPI_BaudRatePrescaler_8 ((u16)0x0010)
#define SPI_BaudRatePrescaler_16 ((u16)0x0018)
#define SPI_BaudRatePrescaler_32 ((u16)0x0020)
#define SPI_BaudRatePrescaler_64 ((u16)0x0028)
#define SPI_BaudRatePrescaler_128 ((u16)0x0030)
#define SPI_BaudRatePrescaler_256 ((u16)0x0038)
#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
((PRESCALER) == SPI_BaudRatePrescaler_4) || \
((PRESCALER) == SPI_BaudRatePrescaler_8) || \
((PRESCALER) == SPI_BaudRatePrescaler_16) || \
((PRESCALER) == SPI_BaudRatePrescaler_32) || \
((PRESCALER) == SPI_BaudRatePrescaler_64) || \
((PRESCALER) == SPI_BaudRatePrescaler_128) || \
((PRESCALER) == SPI_BaudRatePrescaler_256))
/* SPI MSB/LSB transmission */
#define SPI_FirstBit_MSB ((u16)0x0000)
#define SPI_FirstBit_LSB ((u16)0x0080)
#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
((BIT) == SPI_FirstBit_LSB))
/* I2S Mode */
#define I2S_Mode_SlaveTx ((u16)0x0000)
#define I2S_Mode_SlaveRx ((u16)0x0100)
#define I2S_Mode_MasterTx ((u16)0x0200)
#define I2S_Mode_MasterRx ((u16)0x0300)
#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
((MODE) == I2S_Mode_SlaveRx) || \
((MODE) == I2S_Mode_MasterTx) || \
((MODE) == I2S_Mode_MasterRx) )
/* I2S Standard */
#define I2S_Standard_Phillips ((u16)0x0000)
#define I2S_Standard_MSB ((u16)0x0010)
#define I2S_Standard_LSB ((u16)0x0020)
#define I2S_Standard_PCMShort ((u16)0x0030)
#define I2S_Standard_PCMLong ((u16)0x00B0)
#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
((STANDARD) == I2S_Standard_MSB) || \
((STANDARD) == I2S_Standard_LSB) || \
((STANDARD) == I2S_Standard_PCMShort) || \
((STANDARD) == I2S_Standard_PCMLong))
/* I2S Data Format */
#define I2S_DataFormat_16b ((u16)0x0000)
#define I2S_DataFormat_16bextended ((u16)0x0001)
#define I2S_DataFormat_24b ((u16)0x0003)
#define I2S_DataFormat_32b ((u16)0x0005)
#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
((FORMAT) == I2S_DataFormat_16bextended) || \
((FORMAT) == I2S_DataFormat_24b) || \
((FORMAT) == I2S_DataFormat_32b))
/* I2S MCLK Output */
#define I2S_MCLKOutput_Enable ((u16)0x0200)
#define I2S_MCLKOutput_Disable ((u16)0x0000)
#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
((OUTPUT) == I2S_MCLKOutput_Disable))
/* I2S Audio Frequency */
#define I2S_AudioFreq_48k ((u16)48000)
#define I2S_AudioFreq_44k ((u16)44100)
#define I2S_AudioFreq_22k ((u16)22050)
#define I2S_AudioFreq_16k ((u16)16000)
#define I2S_AudioFreq_8k ((u16)8000)
#define I2S_AudioFreq_Default ((u16)2)
#define IS_I2S_AUDIO_FREQ(FREQ) (((FREQ) == I2S_AudioFreq_48k) || \
((FREQ) == I2S_AudioFreq_44k) || \
((FREQ) == I2S_AudioFreq_22k) || \
((FREQ) == I2S_AudioFreq_16k) || \
((FREQ) == I2S_AudioFreq_8k) || \
((FREQ) == I2S_AudioFreq_Default))
/* I2S Clock Polarity */
#define I2S_CPOL_Low ((u16)0x0000)
#define I2S_CPOL_High ((u16)0x0008)
#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
((CPOL) == I2S_CPOL_High))
/* SPI_I2S DMA transfer requests */
#define SPI_I2S_DMAReq_Tx ((u16)0x0002)
#define SPI_I2S_DMAReq_Rx ((u16)0x0001)
#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (u16)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
/* SPI NSS internal software mangement */
#define SPI_NSSInternalSoft_Set ((u16)0x0100)
#define SPI_NSSInternalSoft_Reset ((u16)0xFEFF)
#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
((INTERNAL) == SPI_NSSInternalSoft_Reset))
/* SPI CRC Transmit/Receive */
#define SPI_CRC_Tx ((u8)0x00)
#define SPI_CRC_Rx ((u8)0x01)
#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
/* SPI direction transmit/receive */
#define SPI_Direction_Rx ((u16)0xBFFF)
#define SPI_Direction_Tx ((u16)0x4000)
#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
((DIRECTION) == SPI_Direction_Tx))
/* SPI_I2S interrupts definition */
#define SPI_I2S_IT_TXE ((u8)0x71)
#define SPI_I2S_IT_RXNE ((u8)0x60)
#define SPI_I2S_IT_ERR ((u8)0x50)
#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
((IT) == SPI_I2S_IT_RXNE) || \
((IT) == SPI_I2S_IT_ERR))
#define SPI_I2S_IT_OVR ((u8)0x56)
#define SPI_IT_MODF ((u8)0x55)
#define SPI_IT_CRCERR ((u8)0x54)
#define I2S_IT_UDR ((u8)0x53)
#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))
#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \
((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || \
((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR))
/* SPI_I2S flags definition */
#define SPI_I2S_FLAG_RXNE ((u16)0x0001)
#define SPI_I2S_FLAG_TXE ((u16)0x0002)
#define I2S_FLAG_CHSIDE ((u16)0x0004)
#define I2S_FLAG_UDR ((u16)0x0008)
#define SPI_FLAG_CRCERR ((u16)0x0010)
#define SPI_FLAG_MODF ((u16)0x0020)
#define SPI_I2S_FLAG_OVR ((u16)0x0040)
#define SPI_I2S_FLAG_BSY ((u16)0x0080)
#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \
((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE))
/* SPI CRC polynomial --------------------------------------------------------*/
#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, u8 SPI_I2S_IT, FunctionalState NewState);
void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, u16 SPI_I2S_DMAReq, FunctionalState NewState);
void SPI_I2S_SendData(SPI_TypeDef* SPIx, u16 Data);
u16 SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);
void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, u16 SPI_NSSInternalSoft);
void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
void SPI_DataSizeConfig(SPI_TypeDef* SPIx, u16 SPI_DataSize);
void SPI_TransmitCRC(SPI_TypeDef* SPIx);
void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
u16 SPI_GetCRC(SPI_TypeDef* SPIx, u8 SPI_CRC);
u16 SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, u16 SPI_Direction);
FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, u16 SPI_I2S_FLAG);
void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, u16 SPI_I2S_FLAG);
ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, u8 SPI_I2S_IT);
void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, u8 SPI_I2S_IT);
#endif /*__STM32F10x_SPI_H */
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

64
bsp/stm32f103vb_lwip/library/inc/stm32f10x_systick.h Normal file
View File

@ -0,0 +1,64 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_systick.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the functions prototypes for the
* SysTick firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_SYSTICK_H
#define __STM32F10x_SYSTICK_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* SysTick clock source */
#define SysTick_CLKSource_HCLK_Div8 ((u32)0xFFFFFFFB)
#define SysTick_CLKSource_HCLK ((u32)0x00000004)
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
((SOURCE) == SysTick_CLKSource_HCLK_Div8))
/* SysTick counter state */
#define SysTick_Counter_Disable ((u32)0xFFFFFFFE)
#define SysTick_Counter_Enable ((u32)0x00000001)
#define SysTick_Counter_Clear ((u32)0x00000000)
#define IS_SYSTICK_COUNTER(COUNTER) (((COUNTER) == SysTick_Counter_Disable) || \
((COUNTER) == SysTick_Counter_Enable) || \
((COUNTER) == SysTick_Counter_Clear))
/* SysTick Flag */
#define SysTick_FLAG_COUNT ((u32)0x00000010)
#define SysTick_FLAG_SKEW ((u32)0x0000001E)
#define SysTick_FLAG_NOREF ((u32)0x0000001F)
#define IS_SYSTICK_FLAG(FLAG) (((FLAG) == SysTick_FLAG_COUNT) || \
((FLAG) == SysTick_FLAG_SKEW) || \
((FLAG) == SysTick_FLAG_NOREF))
#define IS_SYSTICK_RELOAD(RELOAD) (((RELOAD) > 0) && ((RELOAD) <= 0xFFFFFF))
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void SysTick_CLKSourceConfig(u32 SysTick_CLKSource);
void SysTick_SetReload(u32 Reload);
void SysTick_CounterCmd(u32 SysTick_Counter);
void SysTick_ITConfig(FunctionalState NewState);
u32 SysTick_GetCounter(void);
FlagStatus SysTick_GetFlagStatus(u8 SysTick_FLAG);
#endif /* __STM32F10x_SYSTICK_H */
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

778
bsp/stm32f103vb_lwip/library/inc/stm32f10x_tim.h Normal file
View File

@ -0,0 +1,778 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_tim.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the functions prototypes for the
* TIM firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_TIM_H
#define __STM32F10x_TIM_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
/* Exported types ------------------------------------------------------------*/
/* TIM Time Base Init structure definition */
typedef struct
{
u16 TIM_Prescaler;
u16 TIM_CounterMode;
u16 TIM_Period;
u16 TIM_ClockDivision;
u8 TIM_RepetitionCounter;
} TIM_TimeBaseInitTypeDef;
/* TIM Output Compare Init structure definition */
typedef struct
{
u16 TIM_OCMode;
u16 TIM_OutputState;
u16 TIM_OutputNState;
u16 TIM_Pulse;
u16 TIM_OCPolarity;
u16 TIM_OCNPolarity;
u16 TIM_OCIdleState;
u16 TIM_OCNIdleState;
} TIM_OCInitTypeDef;
/* TIM Input Capture Init structure definition */
typedef struct
{
u16 TIM_Channel;
u16 TIM_ICPolarity;
u16 TIM_ICSelection;
u16 TIM_ICPrescaler;
u16 TIM_ICFilter;
} TIM_ICInitTypeDef;
/* BDTR structure definition */
typedef struct
{
u16 TIM_OSSRState;
u16 TIM_OSSIState;
u16 TIM_LOCKLevel;
u16 TIM_DeadTime;
u16 TIM_Break;
u16 TIM_BreakPolarity;
u16 TIM_AutomaticOutput;
} TIM_BDTRInitTypeDef;
/* Exported constants --------------------------------------------------------*/
#define IS_TIM_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == TIM1_BASE) || \
((*(u32*)&(PERIPH)) == TIM2_BASE) || \
((*(u32*)&(PERIPH)) == TIM3_BASE) || \
((*(u32*)&(PERIPH)) == TIM4_BASE) || \
((*(u32*)&(PERIPH)) == TIM5_BASE) || \
((*(u32*)&(PERIPH)) == TIM6_BASE) || \
((*(u32*)&(PERIPH)) == TIM7_BASE) || \
((*(u32*)&(PERIPH)) == TIM8_BASE))
#define IS_TIM_18_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == TIM1_BASE) || \
((*(u32*)&(PERIPH)) == TIM8_BASE))
#define IS_TIM_123458_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == TIM1_BASE) || \
((*(u32*)&(PERIPH)) == TIM2_BASE) || \
((*(u32*)&(PERIPH)) == TIM3_BASE) || \
((*(u32*)&(PERIPH)) == TIM4_BASE) || \
((*(u32*)&(PERIPH)) == TIM5_BASE) || \
((*(u32*)&(PERIPH)) == TIM8_BASE))
/* TIM Output Compare and PWM modes -----------------------------------------*/
#define TIM_OCMode_Timing ((u16)0x0000)
#define TIM_OCMode_Active ((u16)0x0010)
#define TIM_OCMode_Inactive ((u16)0x0020)
#define TIM_OCMode_Toggle ((u16)0x0030)
#define TIM_OCMode_PWM1 ((u16)0x0060)
#define TIM_OCMode_PWM2 ((u16)0x0070)
#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
((MODE) == TIM_OCMode_Active) || \
((MODE) == TIM_OCMode_Inactive) || \
((MODE) == TIM_OCMode_Toggle)|| \
((MODE) == TIM_OCMode_PWM1) || \
((MODE) == TIM_OCMode_PWM2))
#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
((MODE) == TIM_OCMode_Active) || \
((MODE) == TIM_OCMode_Inactive) || \
((MODE) == TIM_OCMode_Toggle)|| \
((MODE) == TIM_OCMode_PWM1) || \
((MODE) == TIM_OCMode_PWM2) || \
((MODE) == TIM_ForcedAction_Active) || \
((MODE) == TIM_ForcedAction_InActive))
/* TIM One Pulse Mode -------------------------------------------------------*/
#define TIM_OPMode_Single ((u16)0x0008)
#define TIM_OPMode_Repetitive ((u16)0x0000)
#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
((MODE) == TIM_OPMode_Repetitive))
/* TIM Channel -------------------------------------------------------------*/
#define TIM_Channel_1 ((u16)0x0000)
#define TIM_Channel_2 ((u16)0x0004)
#define TIM_Channel_3 ((u16)0x0008)
#define TIM_Channel_4 ((u16)0x000C)
#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
((CHANNEL) == TIM_Channel_2) || \
((CHANNEL) == TIM_Channel_3) || \
((CHANNEL) == TIM_Channel_4))
#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
((CHANNEL) == TIM_Channel_2))
#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
((CHANNEL) == TIM_Channel_2) || \
((CHANNEL) == TIM_Channel_3))
/* TIM Clock Division CKD --------------------------------------------------*/
#define TIM_CKD_DIV1 ((u16)0x0000)
#define TIM_CKD_DIV2 ((u16)0x0100)
#define TIM_CKD_DIV4 ((u16)0x0200)
#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \
((DIV) == TIM_CKD_DIV2) || \
((DIV) == TIM_CKD_DIV4))
/* TIM Counter Mode --------------------------------------------------------*/
#define TIM_CounterMode_Up ((u16)0x0000)
#define TIM_CounterMode_Down ((u16)0x0010)
#define TIM_CounterMode_CenterAligned1 ((u16)0x0020)
#define TIM_CounterMode_CenterAligned2 ((u16)0x0040)
#define TIM_CounterMode_CenterAligned3 ((u16)0x0060)
#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \
((MODE) == TIM_CounterMode_Down) || \
((MODE) == TIM_CounterMode_CenterAligned1) || \
((MODE) == TIM_CounterMode_CenterAligned2) || \
((MODE) == TIM_CounterMode_CenterAligned3))
/* TIM Output Compare Polarity ---------------------------------------------*/
#define TIM_OCPolarity_High ((u16)0x0000)
#define TIM_OCPolarity_Low ((u16)0x0002)
#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \
((POLARITY) == TIM_OCPolarity_Low))
/* TIM Output Compare N Polarity -------------------------------------------*/
#define TIM_OCNPolarity_High ((u16)0x0000)
#define TIM_OCNPolarity_Low ((u16)0x0008)
#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \
((POLARITY) == TIM_OCNPolarity_Low))
/* TIM Output Compare states -----------------------------------------------*/
#define TIM_OutputState_Disable ((u16)0x0000)
#define TIM_OutputState_Enable ((u16)0x0001)
#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \
((STATE) == TIM_OutputState_Enable))
/* TIM Output Compare N States ---------------------------------------------*/
#define TIM_OutputNState_Disable ((u16)0x0000)
#define TIM_OutputNState_Enable ((u16)0x0004)
#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \
((STATE) == TIM_OutputNState_Enable))
/* TIM Capture Compare States -----------------------------------------------*/
#define TIM_CCx_Enable ((u16)0x0001)
#define TIM_CCx_Disable ((u16)0x0000)
#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \
((CCX) == TIM_CCx_Disable))
/* TIM Capture Compare N States --------------------------------------------*/
#define TIM_CCxN_Enable ((u16)0x0004)
#define TIM_CCxN_Disable ((u16)0x0000)
#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \
((CCXN) == TIM_CCxN_Disable))
/* Break Input enable/disable -----------------------------------------------*/
#define TIM_Break_Enable ((u16)0x1000)
#define TIM_Break_Disable ((u16)0x0000)
#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \
((STATE) == TIM_Break_Disable))
/* Break Polarity -----------------------------------------------------------*/
#define TIM_BreakPolarity_Low ((u16)0x0000)
#define TIM_BreakPolarity_High ((u16)0x2000)
#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \
((POLARITY) == TIM_BreakPolarity_High))
/* TIM AOE Bit Set/Reset ---------------------------------------------------*/
#define TIM_AutomaticOutput_Enable ((u16)0x4000)
#define TIM_AutomaticOutput_Disable ((u16)0x0000)
#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \
((STATE) == TIM_AutomaticOutput_Disable))
/* Lock levels --------------------------------------------------------------*/
#define TIM_LOCKLevel_OFF ((u16)0x0000)
#define TIM_LOCKLevel_1 ((u16)0x0100)
#define TIM_LOCKLevel_2 ((u16)0x0200)
#define TIM_LOCKLevel_3 ((u16)0x0300)
#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \
((LEVEL) == TIM_LOCKLevel_1) || \
((LEVEL) == TIM_LOCKLevel_2) || \
((LEVEL) == TIM_LOCKLevel_3))
/* OSSI: Off-State Selection for Idle mode states ---------------------------*/
#define TIM_OSSIState_Enable ((u16)0x0400)
#define TIM_OSSIState_Disable ((u16)0x0000)
#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \
((STATE) == TIM_OSSIState_Disable))
/* OSSR: Off-State Selection for Run mode states ----------------------------*/
#define TIM_OSSRState_Enable ((u16)0x0800)
#define TIM_OSSRState_Disable ((u16)0x0000)
#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \
((STATE) == TIM_OSSRState_Disable))
/* TIM Output Compare Idle State -------------------------------------------*/
#define TIM_OCIdleState_Set ((u16)0x0100)
#define TIM_OCIdleState_Reset ((u16)0x0000)
#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \
((STATE) == TIM_OCIdleState_Reset))
/* TIM Output Compare N Idle State -----------------------------------------*/
#define TIM_OCNIdleState_Set ((u16)0x0200)
#define TIM_OCNIdleState_Reset ((u16)0x0000)
#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \
((STATE) == TIM_OCNIdleState_Reset))
/* TIM Input Capture Polarity ----------------------------------------------*/
#define TIM_ICPolarity_Rising ((u16)0x0000)
#define TIM_ICPolarity_Falling ((u16)0x0002)
#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
((POLARITY) == TIM_ICPolarity_Falling))
/* TIM Input Capture Selection ---------------------------------------------*/
#define TIM_ICSelection_DirectTI ((u16)0x0001)
#define TIM_ICSelection_IndirectTI ((u16)0x0002)
#define TIM_ICSelection_TRC ((u16)0x0003)
#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \
((SELECTION) == TIM_ICSelection_IndirectTI) || \
((SELECTION) == TIM_ICSelection_TRC))
/* TIM Input Capture Prescaler ---------------------------------------------*/
#define TIM_ICPSC_DIV1 ((u16)0x0000)
#define TIM_ICPSC_DIV2 ((u16)0x0004)
#define TIM_ICPSC_DIV4 ((u16)0x0008)
#define TIM_ICPSC_DIV8 ((u16)0x000C)
#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
((PRESCALER) == TIM_ICPSC_DIV2) || \
((PRESCALER) == TIM_ICPSC_DIV4) || \
((PRESCALER) == TIM_ICPSC_DIV8))
/* TIM interrupt sources ---------------------------------------------------*/
#define TIM_IT_Update ((u16)0x0001)
#define TIM_IT_CC1 ((u16)0x0002)
#define TIM_IT_CC2 ((u16)0x0004)
#define TIM_IT_CC3 ((u16)0x0008)
#define TIM_IT_CC4 ((u16)0x0010)
#define TIM_IT_COM ((u16)0x0020)
#define TIM_IT_Trigger ((u16)0x0040)
#define TIM_IT_Break ((u16)0x0080)
#define IS_TIM_IT(IT) ((((IT) & (u16)0xFF00) == 0x0000) && ((IT) != 0x0000))
#define IS_TIM_PERIPH_IT(PERIPH, TIM_IT) ((((((*(u32*)&(PERIPH)) == TIM2_BASE) || (((*(u32*)&(PERIPH)) == TIM3_BASE))||\
(((*(u32*)&(PERIPH)) == TIM4_BASE)) || (((*(u32*)&(PERIPH)) == TIM5_BASE))))&& \
(((TIM_IT) & (u16)0xFFA0) == 0x0000) && ((TIM_IT) != 0x0000)) ||\
(((((*(u32*)&(PERIPH)) == TIM1_BASE) || (((*(u32*)&(PERIPH)) == TIM8_BASE))))&& \
(((TIM_IT) & (u16)0xFF00) == 0x0000) && ((TIM_IT) != 0x0000)) ||\
(((((*(u32*)&(PERIPH)) == TIM6_BASE) || (((*(u32*)&(PERIPH)) == TIM7_BASE))))&& \
(((TIM_IT) & (u16)0xFFFE) == 0x0000) && ((TIM_IT) != 0x0000)))
#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
((IT) == TIM_IT_CC1) || \
((IT) == TIM_IT_CC2) || \
((IT) == TIM_IT_CC3) || \
((IT) == TIM_IT_CC4) || \
((IT) == TIM_IT_COM) || \
((IT) == TIM_IT_Trigger) || \
((IT) == TIM_IT_Break))
/* TIM DMA Base address ----------------------------------------------------*/
#define TIM_DMABase_CR1 ((u16)0x0000)
#define TIM_DMABase_CR2 ((u16)0x0001)
#define TIM_DMABase_SMCR ((u16)0x0002)
#define TIM_DMABase_DIER ((u16)0x0003)
#define TIM_DMABase_SR ((u16)0x0004)
#define TIM_DMABase_EGR ((u16)0x0005)
#define TIM_DMABase_CCMR1 ((u16)0x0006)
#define TIM_DMABase_CCMR2 ((u16)0x0007)
#define TIM_DMABase_CCER ((u16)0x0008)
#define TIM_DMABase_CNT ((u16)0x0009)
#define TIM_DMABase_PSC ((u16)0x000A)
#define TIM_DMABase_ARR ((u16)0x000B)
#define TIM_DMABase_RCR ((u16)0x000C)
#define TIM_DMABase_CCR1 ((u16)0x000D)
#define TIM_DMABase_CCR2 ((u16)0x000E)
#define TIM_DMABase_CCR3 ((u16)0x000F)
#define TIM_DMABase_CCR4 ((u16)0x0010)
#define TIM_DMABase_BDTR ((u16)0x0011)
#define TIM_DMABase_DCR ((u16)0x0012)
#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
((BASE) == TIM_DMABase_CR2) || \
((BASE) == TIM_DMABase_SMCR) || \
((BASE) == TIM_DMABase_DIER) || \
((BASE) == TIM_DMABase_SR) || \
((BASE) == TIM_DMABase_EGR) || \
((BASE) == TIM_DMABase_CCMR1) || \
((BASE) == TIM_DMABase_CCMR2) || \
((BASE) == TIM_DMABase_CCER) || \
((BASE) == TIM_DMABase_CNT) || \
((BASE) == TIM_DMABase_PSC) || \
((BASE) == TIM_DMABase_ARR) || \
((BASE) == TIM_DMABase_RCR) || \
((BASE) == TIM_DMABase_CCR1) || \
((BASE) == TIM_DMABase_CCR2) || \
((BASE) == TIM_DMABase_CCR3) || \
((BASE) == TIM_DMABase_CCR4) || \
((BASE) == TIM_DMABase_BDTR) || \
((BASE) == TIM_DMABase_DCR))
/* TIM DMA Burst Length ----------------------------------------------------*/
#define TIM_DMABurstLength_1Byte ((u16)0x0000)
#define TIM_DMABurstLength_2Bytes ((u16)0x0100)
#define TIM_DMABurstLength_3Bytes ((u16)0x0200)
#define TIM_DMABurstLength_4Bytes ((u16)0x0300)
#define TIM_DMABurstLength_5Bytes ((u16)0x0400)
#define TIM_DMABurstLength_6Bytes ((u16)0x0500)
#define TIM_DMABurstLength_7Bytes ((u16)0x0600)
#define TIM_DMABurstLength_8Bytes ((u16)0x0700)
#define TIM_DMABurstLength_9Bytes ((u16)0x0800)
#define TIM_DMABurstLength_10Bytes ((u16)0x0900)
#define TIM_DMABurstLength_11Bytes ((u16)0x0A00)
#define TIM_DMABurstLength_12Bytes ((u16)0x0B00)
#define TIM_DMABurstLength_13Bytes ((u16)0x0C00)
#define TIM_DMABurstLength_14Bytes ((u16)0x0D00)
#define TIM_DMABurstLength_15Bytes ((u16)0x0E00)
#define TIM_DMABurstLength_16Bytes ((u16)0x0F00)
#define TIM_DMABurstLength_17Bytes ((u16)0x1000)
#define TIM_DMABurstLength_18Bytes ((u16)0x1100)
#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Byte) || \
((LENGTH) == TIM_DMABurstLength_2Bytes) || \
((LENGTH) == TIM_DMABurstLength_3Bytes) || \
((LENGTH) == TIM_DMABurstLength_4Bytes) || \
((LENGTH) == TIM_DMABurstLength_5Bytes) || \
((LENGTH) == TIM_DMABurstLength_6Bytes) || \
((LENGTH) == TIM_DMABurstLength_7Bytes) || \
((LENGTH) == TIM_DMABurstLength_8Bytes) || \
((LENGTH) == TIM_DMABurstLength_9Bytes) || \
((LENGTH) == TIM_DMABurstLength_10Bytes) || \
((LENGTH) == TIM_DMABurstLength_11Bytes) || \
((LENGTH) == TIM_DMABurstLength_12Bytes) || \
((LENGTH) == TIM_DMABurstLength_13Bytes) || \
((LENGTH) == TIM_DMABurstLength_14Bytes) || \
((LENGTH) == TIM_DMABurstLength_15Bytes) || \
((LENGTH) == TIM_DMABurstLength_16Bytes) || \
((LENGTH) == TIM_DMABurstLength_17Bytes) || \
((LENGTH) == TIM_DMABurstLength_18Bytes))
/* TIM DMA sources ---------------------------------------------------------*/
#define TIM_DMA_Update ((u16)0x0100)
#define TIM_DMA_CC1 ((u16)0x0200)
#define TIM_DMA_CC2 ((u16)0x0400)
#define TIM_DMA_CC3 ((u16)0x0800)
#define TIM_DMA_CC4 ((u16)0x1000)
#define TIM_DMA_COM ((u16)0x2000)
#define TIM_DMA_Trigger ((u16)0x4000)
#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (u16)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
#define IS_TIM_PERIPH_DMA(PERIPH, SOURCE) ((((((*(u32*)&(PERIPH)) == TIM2_BASE) || (((*(u32*)&(PERIPH)) == TIM3_BASE))||\
(((*(u32*)&(PERIPH)) == TIM4_BASE)) || (((*(u32*)&(PERIPH)) == TIM5_BASE))))&& \
(((SOURCE) & (u16)0xA0FF) == 0x0000) && ((SOURCE) != 0x0000)) ||\
(((((*(u32*)&(PERIPH)) == TIM1_BASE) || (((*(u32*)&(PERIPH)) == TIM8_BASE))))&& \
(((SOURCE) & (u16)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) ||\
(((((*(u32*)&(PERIPH)) == TIM6_BASE) || (((*(u32*)&(PERIPH)) == TIM7_BASE))))&& \
(((SOURCE) & (u16)0xFEFF) == 0x0000) && ((SOURCE) != 0x0000)))
/* TIM External Trigger Prescaler ------------------------------------------*/
#define TIM_ExtTRGPSC_OFF ((u16)0x0000)
#define TIM_ExtTRGPSC_DIV2 ((u16)0x1000)
#define TIM_ExtTRGPSC_DIV4 ((u16)0x2000)
#define TIM_ExtTRGPSC_DIV8 ((u16)0x3000)
#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
((PRESCALER) == TIM_ExtTRGPSC_DIV8))
/* TIM Internal Trigger Selection ------------------------------------------*/
#define TIM_TS_ITR0 ((u16)0x0000)
#define TIM_TS_ITR1 ((u16)0x0010)
#define TIM_TS_ITR2 ((u16)0x0020)
#define TIM_TS_ITR3 ((u16)0x0030)
#define TIM_TS_TI1F_ED ((u16)0x0040)
#define TIM_TS_TI1FP1 ((u16)0x0050)
#define TIM_TS_TI2FP2 ((u16)0x0060)
#define TIM_TS_ETRF ((u16)0x0070)
#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
((SELECTION) == TIM_TS_ITR1) || \
((SELECTION) == TIM_TS_ITR2) || \
((SELECTION) == TIM_TS_ITR3) || \
((SELECTION) == TIM_TS_TI1F_ED) || \
((SELECTION) == TIM_TS_TI1FP1) || \
((SELECTION) == TIM_TS_TI2FP2) || \
((SELECTION) == TIM_TS_ETRF))
#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
((SELECTION) == TIM_TS_ITR1) || \
((SELECTION) == TIM_TS_ITR2) || \
((SELECTION) == TIM_TS_ITR3))
/* TIM TIx External Clock Source -------------------------------------------*/
#define TIM_TIxExternalCLK1Source_TI1 ((u16)0x0050)
#define TIM_TIxExternalCLK1Source_TI2 ((u16)0x0060)
#define TIM_TIxExternalCLK1Source_TI1ED ((u16)0x0040)
#define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || \
((SOURCE) == TIM_TIxExternalCLK1Source_TI2) || \
((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED))
/* TIM External Trigger Polarity -------------------------------------------*/
#define TIM_ExtTRGPolarity_Inverted ((u16)0x8000)
#define TIM_ExtTRGPolarity_NonInverted ((u16)0x0000)
#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
/* TIM Prescaler Reload Mode -----------------------------------------------*/
#define TIM_PSCReloadMode_Update ((u16)0x0000)
#define TIM_PSCReloadMode_Immediate ((u16)0x0001)
#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
((RELOAD) == TIM_PSCReloadMode_Immediate))
/* TIM Forced Action -------------------------------------------------------*/
#define TIM_ForcedAction_Active ((u16)0x0050)
#define TIM_ForcedAction_InActive ((u16)0x0040)
#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
((ACTION) == TIM_ForcedAction_InActive))
/* TIM Encoder Mode --------------------------------------------------------*/
#define TIM_EncoderMode_TI1 ((u16)0x0001)
#define TIM_EncoderMode_TI2 ((u16)0x0002)
#define TIM_EncoderMode_TI12 ((u16)0x0003)
#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
((MODE) == TIM_EncoderMode_TI2) || \
((MODE) == TIM_EncoderMode_TI12))
/* TIM Event Source --------------------------------------------------------*/
#define TIM_EventSource_Update ((u16)0x0001)
#define TIM_EventSource_CC1 ((u16)0x0002)
#define TIM_EventSource_CC2 ((u16)0x0004)
#define TIM_EventSource_CC3 ((u16)0x0008)
#define TIM_EventSource_CC4 ((u16)0x0010)
#define TIM_EventSource_COM ((u16)0x0020)
#define TIM_EventSource_Trigger ((u16)0x0040)
#define TIM_EventSource_Break ((u16)0x0080)
#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (u16)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
#define IS_TIM_PERIPH_EVENT(PERIPH, EVENT) ((((((*(u32*)&(PERIPH)) == TIM2_BASE) || (((*(u32*)&(PERIPH)) == TIM3_BASE))||\
(((*(u32*)&(PERIPH)) == TIM4_BASE)) || (((*(u32*)&(PERIPH)) == TIM5_BASE))))&& \
(((EVENT) & (u16)0xFFA0) == 0x0000) && ((EVENT) != 0x0000)) ||\
(((((*(u32*)&(PERIPH)) == TIM1_BASE) || (((*(u32*)&(PERIPH)) == TIM8_BASE))))&& \
(((EVENT) & (u16)0xFF00) == 0x0000) && ((EVENT) != 0x0000)) ||\
(((((*(u32*)&(PERIPH)) == TIM6_BASE) || (((*(u32*)&(PERIPH)) == TIM7_BASE))))&& \
(((EVENT) & (u16)0xFFFE) == 0x0000) && ((EVENT) != 0x0000)))
/* TIM Update Source --------------------------------------------------------*/
#define TIM_UpdateSource_Global ((u16)0x0000)
#define TIM_UpdateSource_Regular ((u16)0x0001)
#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
((SOURCE) == TIM_UpdateSource_Regular))
/* TIM Ouput Compare Preload State ------------------------------------------*/
#define TIM_OCPreload_Enable ((u16)0x0008)
#define TIM_OCPreload_Disable ((u16)0x0000)
#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
((STATE) == TIM_OCPreload_Disable))
/* TIM Ouput Compare Fast State ---------------------------------------------*/
#define TIM_OCFast_Enable ((u16)0x0004)
#define TIM_OCFast_Disable ((u16)0x0000)
#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
((STATE) == TIM_OCFast_Disable))
/* TIM Ouput Compare Clear State --------------------------------------------*/
#define TIM_OCClear_Enable ((u16)0x0080)
#define TIM_OCClear_Disable ((u16)0x0000)
#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
((STATE) == TIM_OCClear_Disable))
/* TIM Trigger Output Source ------------------------------------------------*/
#define TIM_TRGOSource_Reset ((u16)0x0000)
#define TIM_TRGOSource_Enable ((u16)0x0010)
#define TIM_TRGOSource_Update ((u16)0x0020)
#define TIM_TRGOSource_OC1 ((u16)0x0030)
#define TIM_TRGOSource_OC1Ref ((u16)0x0040)
#define TIM_TRGOSource_OC2Ref ((u16)0x0050)
#define TIM_TRGOSource_OC3Ref ((u16)0x0060)
#define TIM_TRGOSource_OC4Ref ((u16)0x0070)
#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
((SOURCE) == TIM_TRGOSource_Enable) || \
((SOURCE) == TIM_TRGOSource_Update) || \
((SOURCE) == TIM_TRGOSource_OC1) || \
((SOURCE) == TIM_TRGOSource_OC1Ref) || \
((SOURCE) == TIM_TRGOSource_OC2Ref) || \
((SOURCE) == TIM_TRGOSource_OC3Ref) || \
((SOURCE) == TIM_TRGOSource_OC4Ref))
#define IS_TIM_PERIPH_TRGO(PERIPH, TRGO) (((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\
(((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \
(((*(u32*)&(PERIPH)) == TIM6_BASE))||(((*(u32*)&(PERIPH)) == TIM7_BASE))|| \
(((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \
((TRGO) == TIM_TRGOSource_Reset)) ||\
((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\
(((*(u32*)&(PERIPH)) == TIM6_BASE))||(((*(u32*)&(PERIPH)) == TIM7_BASE))|| \
(((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \
(((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \
((TRGO) == TIM_TRGOSource_Enable)) ||\
((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\
(((*(u32*)&(PERIPH)) == TIM6_BASE))||(((*(u32*)&(PERIPH)) == TIM7_BASE))|| \
(((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \
(((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \
((TRGO) == TIM_TRGOSource_Update)) ||\
((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\
(((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \
(((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \
((TRGO) == TIM_TRGOSource_OC1)) ||\
((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\
(((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \
(((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \
((TRGO) == TIM_TRGOSource_OC1Ref)) ||\
((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\
(((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \
(((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \
((TRGO) == TIM_TRGOSource_OC2Ref)) ||\
((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\
(((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \
(((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \
((TRGO) == TIM_TRGOSource_OC3Ref)) ||\
((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\
(((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \
(((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \
((TRGO) == TIM_TRGOSource_OC4Ref)))
/* TIM Slave Mode ----------------------------------------------------------*/
#define TIM_SlaveMode_Reset ((u16)0x0004)
#define TIM_SlaveMode_Gated ((u16)0x0005)
#define TIM_SlaveMode_Trigger ((u16)0x0006)
#define TIM_SlaveMode_External1 ((u16)0x0007)
#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
((MODE) == TIM_SlaveMode_Gated) || \
((MODE) == TIM_SlaveMode_Trigger) || \
((MODE) == TIM_SlaveMode_External1))
/* TIM Master Slave Mode ---------------------------------------------------*/
#define TIM_MasterSlaveMode_Enable ((u16)0x0080)
#define TIM_MasterSlaveMode_Disable ((u16)0x0000)
#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
((STATE) == TIM_MasterSlaveMode_Disable))
/* TIM Flags ---------------------------------------------------------------*/
#define TIM_FLAG_Update ((u16)0x0001)
#define TIM_FLAG_CC1 ((u16)0x0002)
#define TIM_FLAG_CC2 ((u16)0x0004)
#define TIM_FLAG_CC3 ((u16)0x0008)
#define TIM_FLAG_CC4 ((u16)0x0010)
#define TIM_FLAG_COM ((u16)0x0020)
#define TIM_FLAG_Trigger ((u16)0x0040)
#define TIM_FLAG_Break ((u16)0x0080)
#define TIM_FLAG_CC1OF ((u16)0x0200)
#define TIM_FLAG_CC2OF ((u16)0x0400)
#define TIM_FLAG_CC3OF ((u16)0x0800)
#define TIM_FLAG_CC4OF ((u16)0x1000)
#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \
((FLAG) == TIM_FLAG_CC1) || \
((FLAG) == TIM_FLAG_CC2) || \
((FLAG) == TIM_FLAG_CC3) || \
((FLAG) == TIM_FLAG_CC4) || \
((FLAG) == TIM_FLAG_COM) || \
((FLAG) == TIM_FLAG_Trigger) || \
((FLAG) == TIM_FLAG_Break) || \
((FLAG) == TIM_FLAG_CC1OF) || \
((FLAG) == TIM_FLAG_CC2OF) || \
((FLAG) == TIM_FLAG_CC3OF) || \
((FLAG) == TIM_FLAG_CC4OF))
#define IS_TIM_CLEAR_FLAG(PERIPH, TIM_FLAG) ((((((*(u32*)&(PERIPH)) == TIM2_BASE) || (((*(u32*)&(PERIPH)) == TIM3_BASE))||\
(((*(u32*)&(PERIPH)) == TIM4_BASE)) || (((*(u32*)&(PERIPH)) == TIM5_BASE))))&& \
(((TIM_FLAG) & (u16)0xE1A0) == 0x0000) && ((TIM_FLAG) != 0x0000)) ||\
(((((*(u32*)&(PERIPH)) == TIM1_BASE) || (((*(u32*)&(PERIPH)) == TIM8_BASE))))&& \
(((TIM_FLAG) & (u16)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000)) ||\
(((((*(u32*)&(PERIPH)) == TIM6_BASE) || (((*(u32*)&(PERIPH)) == TIM7_BASE))))&& \
(((TIM_FLAG) & (u16)0xFFFE) == 0x0000) && ((TIM_FLAG) != 0x0000)))
#define IS_TIM_PERIPH_FLAG(PERIPH, TIM_FLAG) (((((*(u32*)&(PERIPH))==TIM2_BASE) || ((*(u32*)&(PERIPH)) == TIM3_BASE) ||\
((*(u32*)&(PERIPH)) == TIM4_BASE) || ((*(u32*)&(PERIPH))==TIM5_BASE) || \
((*(u32*)&(PERIPH))==TIM1_BASE) || ((*(u32*)&(PERIPH))==TIM8_BASE)) &&\
(((TIM_FLAG) == TIM_FLAG_CC1) || ((TIM_FLAG) == TIM_FLAG_CC2) ||\
((TIM_FLAG) == TIM_FLAG_CC3) || ((TIM_FLAG) == TIM_FLAG_CC4) || \
((TIM_FLAG) == TIM_FLAG_Trigger))) ||\
((((*(u32*)&(PERIPH))==TIM2_BASE) || ((*(u32*)&(PERIPH)) == TIM3_BASE) || \
((*(u32*)&(PERIPH)) == TIM4_BASE) || ((*(u32*)&(PERIPH))==TIM5_BASE) ||\
((*(u32*)&(PERIPH))==TIM1_BASE)|| ((*(u32*)&(PERIPH))==TIM8_BASE) || \
((*(u32*)&(PERIPH))==TIM7_BASE) || ((*(u32*)&(PERIPH))==TIM6_BASE)) && \
(((TIM_FLAG) == TIM_FLAG_Update))) ||\
((((*(u32*)&(PERIPH))==TIM1_BASE) || ((*(u32*)&(PERIPH)) == TIM8_BASE)) &&\
(((TIM_FLAG) == TIM_FLAG_COM) || ((TIM_FLAG) == TIM_FLAG_Break))) ||\
((((*(u32*)&(PERIPH))==TIM2_BASE) || ((*(u32*)&(PERIPH)) == TIM3_BASE) || \
((*(u32*)&(PERIPH)) == TIM4_BASE) || ((*(u32*)&(PERIPH))==TIM5_BASE) || \
((*(u32*)&(PERIPH))==TIM1_BASE) || ((*(u32*)&(PERIPH))==TIM8_BASE)) &&\
(((TIM_FLAG) == TIM_FLAG_CC1OF) || ((TIM_FLAG) == TIM_FLAG_CC2OF) ||\
((TIM_FLAG) == TIM_FLAG_CC3OF) || ((TIM_FLAG) == TIM_FLAG_CC4OF))))
/* TIM Input Capture Filer Value ---------------------------------------------*/
#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
/* TIM External Trigger Filter -----------------------------------------------*/
#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
void TIM_DeInit(TIM_TypeDef* TIMx);
void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
void TIM_ITConfig(TIM_TypeDef* TIMx, u16 TIM_IT, FunctionalState NewState);
void TIM_GenerateEvent(TIM_TypeDef* TIMx, u16 TIM_EventSource);
void TIM_DMAConfig(TIM_TypeDef* TIMx, u16 TIM_DMABase, u16 TIM_DMABurstLength);
void TIM_DMACmd(TIM_TypeDef* TIMx, u16 TIM_DMASource, FunctionalState NewState);
void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, u16 TIM_InputTriggerSource);
void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, u16 TIM_TIxExternalCLKSource,
u16 TIM_ICPolarity, u16 ICFilter);
void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, u16 TIM_ExtTRGPolarity,
u16 ExtTRGFilter);
void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler,
u16 TIM_ExtTRGPolarity, u16 ExtTRGFilter);
void TIM_ETRConfig(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, u16 TIM_ExtTRGPolarity,
u16 ExtTRGFilter);
void TIM_PrescalerConfig(TIM_TypeDef* TIMx, u16 Prescaler, u16 TIM_PSCReloadMode);
void TIM_CounterModeConfig(TIM_TypeDef* TIMx, u16 TIM_CounterMode);
void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, u16 TIM_InputTriggerSource);
void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, u16 TIM_EncoderMode,
u16 TIM_IC1Polarity, u16 TIM_IC2Polarity);
void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction);
void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction);
void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction);
void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction);
void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload);
void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload);
void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload);
void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload);
void TIM_OC1FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast);
void TIM_OC2FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast);
void TIM_OC3FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast);
void TIM_OC4FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast);
void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, u16 TIM_OCClear);
void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, u16 TIM_OCClear);
void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, u16 TIM_OCClear);
void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, u16 TIM_OCClear);
void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity);
void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCNPolarity);
void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity);
void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCNPolarity);
void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity);
void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCNPolarity);
void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity);
void TIM_CCxCmd(TIM_TypeDef* TIMx, u16 TIM_Channel, u16 TIM_CCx);
void TIM_CCxNCmd(TIM_TypeDef* TIMx, u16 TIM_Channel, u16 TIM_CCxN);
void TIM_SelectOCxM(TIM_TypeDef* TIMx, u16 TIM_Channel, u16 TIM_OCMode);
void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, u16 TIM_UpdateSource);
void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, u16 TIM_OPMode);
void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, u16 TIM_TRGOSource);
void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, u16 TIM_SlaveMode);
void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, u16 TIM_MasterSlaveMode);
void TIM_SetCounter(TIM_TypeDef* TIMx, u16 Counter);
void TIM_SetAutoreload(TIM_TypeDef* TIMx, u16 Autoreload);
void TIM_SetCompare1(TIM_TypeDef* TIMx, u16 Compare1);
void TIM_SetCompare2(TIM_TypeDef* TIMx, u16 Compare2);
void TIM_SetCompare3(TIM_TypeDef* TIMx, u16 Compare3);
void TIM_SetCompare4(TIM_TypeDef* TIMx, u16 Compare4);
void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, u16 TIM_ICPSC);
void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, u16 TIM_ICPSC);
void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, u16 TIM_ICPSC);
void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, u16 TIM_ICPSC);
void TIM_SetClockDivision(TIM_TypeDef* TIMx, u16 TIM_CKD);
u16 TIM_GetCapture1(TIM_TypeDef* TIMx);
u16 TIM_GetCapture2(TIM_TypeDef* TIMx);
u16 TIM_GetCapture3(TIM_TypeDef* TIMx);
u16 TIM_GetCapture4(TIM_TypeDef* TIMx);
u16 TIM_GetCounter(TIM_TypeDef* TIMx);
u16 TIM_GetPrescaler(TIM_TypeDef* TIMx);
FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, u16 TIM_FLAG);
void TIM_ClearFlag(TIM_TypeDef* TIMx, u16 TIM_FLAG);
ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, u16 TIM_IT);
void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, u16 TIM_IT);
#endif /*__STM32F10x_TIM_H */
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

80
bsp/stm32f103vb_lwip/library/inc/stm32f10x_type.h Normal file
View File

@ -0,0 +1,80 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_type.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the common data types used for the
* STM32F10x firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_TYPE_H
#define __STM32F10x_TYPE_H
/* Includes ------------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
typedef signed long s32;
typedef signed short s16;
typedef signed char s8;
typedef signed long const sc32; /* Read Only */
typedef signed short const sc16; /* Read Only */
typedef signed char const sc8; /* Read Only */
typedef volatile signed long vs32;
typedef volatile signed short vs16;
typedef volatile signed char vs8;
typedef volatile signed long const vsc32; /* Read Only */
typedef volatile signed short const vsc16; /* Read Only */
typedef volatile signed char const vsc8; /* Read Only */
typedef unsigned long u32;
typedef unsigned short u16;
typedef unsigned char u8;
typedef unsigned long const uc32; /* Read Only */
typedef unsigned short const uc16; /* Read Only */
typedef unsigned char const uc8; /* Read Only */
typedef volatile unsigned long vu32;
typedef volatile unsigned short vu16;
typedef volatile unsigned char vu8;
typedef volatile unsigned long const vuc32; /* Read Only */
typedef volatile unsigned short const vuc16; /* Read Only */
typedef volatile unsigned char const vuc8; /* Read Only */
typedef enum {FALSE = 0, TRUE = !FALSE} bool;
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
#define U8_MAX ((u8)255)
#define S8_MAX ((s8)127)
#define S8_MIN ((s8)-128)
#define U16_MAX ((u16)65535u)
#define S16_MAX ((s16)32767)
#define S16_MIN ((s16)-32768)
#define U32_MAX ((u32)4294967295uL)
#define S32_MAX ((s32)2147483647)
#define S32_MIN ((s32)-2147483648)
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
#endif /* __STM32F10x_TYPE_H */
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

253
bsp/stm32f103vb_lwip/library/inc/stm32f10x_usart.h Normal file
View File

@ -0,0 +1,253 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_usart.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the functions prototypes for the
* USART firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_USART_H
#define __STM32F10x_USART_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
/* Exported types ------------------------------------------------------------*/
/* USART Init Structure definition */
typedef struct
{
u32 USART_BaudRate;
u16 USART_WordLength;
u16 USART_StopBits;
u16 USART_Parity;
u16 USART_Mode;
u16 USART_HardwareFlowControl;
} USART_InitTypeDef;
/* USART Clock Init Structure definition */
typedef struct
{
u16 USART_Clock;
u16 USART_CPOL;
u16 USART_CPHA;
u16 USART_LastBit;
} USART_ClockInitTypeDef;
/* Exported constants --------------------------------------------------------*/
#define IS_USART_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == USART1_BASE) || \
((*(u32*)&(PERIPH)) == USART2_BASE) || \
((*(u32*)&(PERIPH)) == USART3_BASE) || \
((*(u32*)&(PERIPH)) == UART4_BASE) || \
((*(u32*)&(PERIPH)) == UART5_BASE))
#define IS_USART_123_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == USART1_BASE) || \
((*(u32*)&(PERIPH)) == USART2_BASE) || \
((*(u32*)&(PERIPH)) == USART3_BASE))
#define IS_USART_1234_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == USART1_BASE) || \
((*(u32*)&(PERIPH)) == USART2_BASE) || \
((*(u32*)&(PERIPH)) == USART3_BASE) || \
((*(u32*)&(PERIPH)) == UART4_BASE))
/* USART Word Length ---------------------------------------------------------*/
#define USART_WordLength_8b ((u16)0x0000)
#define USART_WordLength_9b ((u16)0x1000)
#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
((LENGTH) == USART_WordLength_9b))
/* USART Stop Bits -----------------------------------------------------------*/
#define USART_StopBits_1 ((u16)0x0000)
#define USART_StopBits_0_5 ((u16)0x1000)
#define USART_StopBits_2 ((u16)0x2000)
#define USART_StopBits_1_5 ((u16)0x3000)
#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
((STOPBITS) == USART_StopBits_0_5) || \
((STOPBITS) == USART_StopBits_2) || \
((STOPBITS) == USART_StopBits_1_5))
/* USART Parity --------------------------------------------------------------*/
#define USART_Parity_No ((u16)0x0000)
#define USART_Parity_Even ((u16)0x0400)
#define USART_Parity_Odd ((u16)0x0600)
#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
((PARITY) == USART_Parity_Even) || \
((PARITY) == USART_Parity_Odd))
/* USART Mode ----------------------------------------------------------------*/
#define USART_Mode_Rx ((u16)0x0004)
#define USART_Mode_Tx ((u16)0x0008)
#define IS_USART_MODE(MODE) ((((MODE) & (u16)0xFFF3) == 0x00) && ((MODE) != (u16)0x00))
/* USART Hardware Flow Control -----------------------------------------------*/
#define USART_HardwareFlowControl_None ((u16)0x0000)
#define USART_HardwareFlowControl_RTS ((u16)0x0100)
#define USART_HardwareFlowControl_CTS ((u16)0x0200)
#define USART_HardwareFlowControl_RTS_CTS ((u16)0x0300)
#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
(((CONTROL) == USART_HardwareFlowControl_None) || \
((CONTROL) == USART_HardwareFlowControl_RTS) || \
((CONTROL) == USART_HardwareFlowControl_CTS) || \
((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
#define IS_USART_PERIPH_HFC(PERIPH, HFC) ((((*(u32*)&(PERIPH)) != UART4_BASE) && \
((*(u32*)&(PERIPH)) != UART5_BASE)) \
|| ((HFC) == USART_HardwareFlowControl_None))
/* USART Clock ---------------------------------------------------------------*/
#define USART_Clock_Disable ((u16)0x0000)
#define USART_Clock_Enable ((u16)0x0800)
#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
((CLOCK) == USART_Clock_Enable))
/* USART Clock Polarity ------------------------------------------------------*/
#define USART_CPOL_Low ((u16)0x0000)
#define USART_CPOL_High ((u16)0x0400)
#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
/* USART Clock Phase ---------------------------------------------------------*/
#define USART_CPHA_1Edge ((u16)0x0000)
#define USART_CPHA_2Edge ((u16)0x0200)
#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
/* USART Last Bit ------------------------------------------------------------*/
#define USART_LastBit_Disable ((u16)0x0000)
#define USART_LastBit_Enable ((u16)0x0100)
#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
((LASTBIT) == USART_LastBit_Enable))
/* USART Interrupt definition ------------------------------------------------*/
#define USART_IT_PE ((u16)0x0028)
#define USART_IT_TXE ((u16)0x0727)
#define USART_IT_TC ((u16)0x0626)
#define USART_IT_RXNE ((u16)0x0525)
#define USART_IT_IDLE ((u16)0x0424)
#define USART_IT_LBD ((u16)0x0846)
#define USART_IT_CTS ((u16)0x096A)
#define USART_IT_ERR ((u16)0x0060)
#define USART_IT_ORE ((u16)0x0360)
#define USART_IT_NE ((u16)0x0260)
#define USART_IT_FE ((u16)0x0160)
#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))
#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
((IT) == USART_IT_NE) || ((IT) == USART_IT_FE))
#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))
#define IS_USART_PERIPH_IT(PERIPH, USART_IT) ((((*(u32*)&(PERIPH)) != UART4_BASE) && \
((*(u32*)&(PERIPH)) != UART5_BASE)) \
|| ((USART_IT) != USART_IT_CTS))
/* USART DMA Requests --------------------------------------------------------*/
#define USART_DMAReq_Tx ((u16)0x0080)
#define USART_DMAReq_Rx ((u16)0x0040)
#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (u16)0xFF3F) == 0x00) && ((DMAREQ) != (u16)0x00))
/* USART WakeUp methods ------------------------------------------------------*/
#define USART_WakeUp_IdleLine ((u16)0x0000)
#define USART_WakeUp_AddressMark ((u16)0x0800)
#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
((WAKEUP) == USART_WakeUp_AddressMark))
/* USART LIN Break Detection Length ------------------------------------------*/
#define USART_LINBreakDetectLength_10b ((u16)0x0000)
#define USART_LINBreakDetectLength_11b ((u16)0x0020)
#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
(((LENGTH) == USART_LINBreakDetectLength_10b) || \
((LENGTH) == USART_LINBreakDetectLength_11b))
/* USART IrDA Low Power ------------------------------------------------------*/
#define USART_IrDAMode_LowPower ((u16)0x0004)
#define USART_IrDAMode_Normal ((u16)0x0000)
#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
((MODE) == USART_IrDAMode_Normal))
/* USART Flags ---------------------------------------------------------------*/
#define USART_FLAG_CTS ((u16)0x0200)
#define USART_FLAG_LBD ((u16)0x0100)
#define USART_FLAG_TXE ((u16)0x0080)
#define USART_FLAG_TC ((u16)0x0040)
#define USART_FLAG_RXNE ((u16)0x0020)
#define USART_FLAG_IDLE ((u16)0x0010)
#define USART_FLAG_ORE ((u16)0x0008)
#define USART_FLAG_NE ((u16)0x0004)
#define USART_FLAG_FE ((u16)0x0002)
#define USART_FLAG_PE ((u16)0x0001)
#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))
#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (u16)0xFC9F) == 0x00) && ((FLAG) != (u16)0x00))
#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) ((((*(u32*)&(PERIPH)) != UART4_BASE) &&\
((*(u32*)&(PERIPH)) != UART5_BASE)) \
|| ((USART_FLAG) != USART_FLAG_CTS))
#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21))
#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void USART_DeInit(USART_TypeDef* USARTx);
void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_ITConfig(USART_TypeDef* USARTx, u16 USART_IT, FunctionalState NewState);
void USART_DMACmd(USART_TypeDef* USARTx, u16 USART_DMAReq, FunctionalState NewState);
void USART_SetAddress(USART_TypeDef* USARTx, u8 USART_Address);
void USART_WakeUpConfig(USART_TypeDef* USARTx, u16 USART_WakeUp);
void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, u16 USART_LINBreakDetectLength);
void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_SendData(USART_TypeDef* USARTx, u16 Data);
u16 USART_ReceiveData(USART_TypeDef* USARTx);
void USART_SendBreak(USART_TypeDef* USARTx);
void USART_SetGuardTime(USART_TypeDef* USARTx, u8 USART_GuardTime);
void USART_SetPrescaler(USART_TypeDef* USARTx, u8 USART_Prescaler);
void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_IrDAConfig(USART_TypeDef* USARTx, u16 USART_IrDAMode);
void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, u16 USART_FLAG);
void USART_ClearFlag(USART_TypeDef* USARTx, u16 USART_FLAG);
ITStatus USART_GetITStatus(USART_TypeDef* USARTx, u16 USART_IT);
void USART_ClearITPendingBit(USART_TypeDef* USARTx, u16 USART_IT);
#endif /* __STM32F10x_USART_H */
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

54
bsp/stm32f103vb_lwip/library/inc/stm32f10x_wwdg.h Normal file
View File

@ -0,0 +1,54 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_wwdg.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the functions prototypes for the
* WWDG firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_WWDG_H
#define __STM32F10x_WWDG_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* WWDG Prescaler */
#define WWDG_Prescaler_1 ((u32)0x00000000)
#define WWDG_Prescaler_2 ((u32)0x00000080)
#define WWDG_Prescaler_4 ((u32)0x00000100)
#define WWDG_Prescaler_8 ((u32)0x00000180)
#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
((PRESCALER) == WWDG_Prescaler_2) || \
((PRESCALER) == WWDG_Prescaler_4) || \
((PRESCALER) == WWDG_Prescaler_8))
#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void WWDG_DeInit(void);
void WWDG_SetPrescaler(u32 WWDG_Prescaler);
void WWDG_SetWindowValue(u8 WindowValue);
void WWDG_EnableIT(void);
void WWDG_SetCounter(u8 Counter);
void WWDG_Enable(u8 Counter);
FlagStatus WWDG_GetFlagStatus(void);
void WWDG_ClearFlag(void);
#endif /* __STM32F10x_WWDG_H */
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

1402
bsp/stm32f103vb_lwip/library/src/stm32f10x_adc.c Normal file
View File

File diff suppressed because it is too large Load Diff

272
bsp/stm32f103vb_lwip/library/src/stm32f10x_bkp.c Normal file
View File

@ -0,0 +1,272 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_bkp.c
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file provides all the BKP firmware functions.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_bkp.h"
#include "stm32f10x_rcc.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* ------------ BKP registers bit address in the alias region ----------- */
#define BKP_OFFSET (BKP_BASE - PERIPH_BASE)
/* --- CR Register ---*/
/* Alias word address of TPAL bit */
#define CR_OFFSET (BKP_OFFSET + 0x30)
#define TPAL_BitNumber 0x01
#define CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4))
/* Alias word address of TPE bit */
#define TPE_BitNumber 0x00
#define CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4))
/* --- CSR Register ---*/
/* Alias word address of TPIE bit */
#define CSR_OFFSET (BKP_OFFSET + 0x34)
#define TPIE_BitNumber 0x02
#define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4))
/* Alias word address of TIF bit */
#define TIF_BitNumber 0x09
#define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4))
/* Alias word address of TEF bit */
#define TEF_BitNumber 0x08
#define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4))
/* ---------------------- BKP registers bit mask ------------------------ */
/* RTCCR register bit mask */
#define RTCCR_CAL_Mask ((u16)0xFF80)
#define RTCCR_Mask ((u16)0xFC7F)
/* CSR register bit mask */
#define CSR_CTE_Set ((u16)0x0001)
#define CSR_CTI_Set ((u16)0x0002)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : BKP_DeInit
* Description : Deinitializes the BKP peripheral registers to their default
* reset values.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void BKP_DeInit(void)
{
RCC_BackupResetCmd(ENABLE);
RCC_BackupResetCmd(DISABLE);
}
/*******************************************************************************
* Function Name : BKP_TamperPinLevelConfig
* Description : Configures the Tamper Pin active level.
* Input : - BKP_TamperPinLevel: specifies the Tamper Pin active level.
* This parameter can be one of the following values:
* - BKP_TamperPinLevel_High: Tamper pin active on high level
* - BKP_TamperPinLevel_Low: Tamper pin active on low level
* Output : None
* Return : None
*******************************************************************************/
void BKP_TamperPinLevelConfig(u16 BKP_TamperPinLevel)
{
/* Check the parameters */
assert_param(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel));
*(vu32 *) CR_TPAL_BB = BKP_TamperPinLevel;
}
/*******************************************************************************
* Function Name : BKP_TamperPinCmd
* Description : Enables or disables the Tamper Pin activation.
* Input : - NewState: new state of the Tamper Pin activation.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void BKP_TamperPinCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(vu32 *) CR_TPE_BB = (u32)NewState;
}
/*******************************************************************************
* Function Name : BKP_ITConfig
* Description : Enables or disables the Tamper Pin Interrupt.
* Input : - NewState: new state of the Tamper Pin Interrupt.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void BKP_ITConfig(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(vu32 *) CSR_TPIE_BB = (u32)NewState;
}
/*******************************************************************************
* Function Name : BKP_RTCOutputConfig
* Description : Select the RTC output source to output on the Tamper pin.
* Input : - BKP_RTCOutputSource: specifies the RTC output source.
* This parameter can be one of the following values:
* - BKP_RTCOutputSource_None: no RTC output on the Tamper pin.
* - BKP_RTCOutputSource_CalibClock: output the RTC clock
* with frequency divided by 64 on the Tamper pin.
* - BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse
* signal on the Tamper pin.
* - BKP_RTCOutputSource_Second: output the RTC Second pulse
* signal on the Tamper pin.
* Output : None
* Return : None
*******************************************************************************/
void BKP_RTCOutputConfig(u16 BKP_RTCOutputSource)
{
u16 tmpreg = 0;
/* Check the parameters */
assert_param(IS_BKP_RTC_OUTPUT_SOURCE(BKP_RTCOutputSource));
tmpreg = BKP->RTCCR;
/* Clear CCO, ASOE and ASOS bits */
tmpreg &= RTCCR_Mask;
/* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */
tmpreg |= BKP_RTCOutputSource;
/* Store the new value */
BKP->RTCCR = tmpreg;
}
/*******************************************************************************
* Function Name : BKP_SetRTCCalibrationValue
* Description : Sets RTC Clock Calibration value.
* Input : - CalibrationValue: specifies the RTC Clock Calibration value.
* This parameter must be a number between 0 and 0x7F.
* Output : None
* Return : None
*******************************************************************************/
void BKP_SetRTCCalibrationValue(u8 CalibrationValue)
{
u16 tmpreg = 0;
/* Check the parameters */
assert_param(IS_BKP_CALIBRATION_VALUE(CalibrationValue));
tmpreg = BKP->RTCCR;
/* Clear CAL[6:0] bits */
tmpreg &= RTCCR_CAL_Mask;
/* Set CAL[6:0] bits according to CalibrationValue value */
tmpreg |= CalibrationValue;
/* Store the new value */
BKP->RTCCR = tmpreg;
}
/*******************************************************************************
* Function Name : BKP_WriteBackupRegister
* Description : Writes user data to the specified Data Backup Register.
* Input : - BKP_DR: specifies the Data Backup Register.
* This parameter can be BKP_DRx where x:[1, 42]
* - Data: data to write
* Output : None
* Return : None
*******************************************************************************/
void BKP_WriteBackupRegister(u16 BKP_DR, u16 Data)
{
/* Check the parameters */
assert_param(IS_BKP_DR(BKP_DR));
*(vu16 *) (BKP_BASE + BKP_DR) = Data;
}
/*******************************************************************************
* Function Name : BKP_ReadBackupRegister
* Description : Reads data from the specified Data Backup Register.
* Input : - BKP_DR: specifies the Data Backup Register.
* This parameter can be BKP_DRx where x:[1, 42]
* Output : None
* Return : The content of the specified Data Backup Register
*******************************************************************************/
u16 BKP_ReadBackupRegister(u16 BKP_DR)
{
/* Check the parameters */
assert_param(IS_BKP_DR(BKP_DR));
return (*(vu16 *) (BKP_BASE + BKP_DR));
}
/*******************************************************************************
* Function Name : BKP_GetFlagStatus
* Description : Checks whether the Tamper Pin Event flag is set or not.
* Input : None
* Output : None
* Return : The new state of the Tamper Pin Event flag (SET or RESET).
*******************************************************************************/
FlagStatus BKP_GetFlagStatus(void)
{
return (FlagStatus)(*(vu32 *) CSR_TEF_BB);
}
/*******************************************************************************
* Function Name : BKP_ClearFlag
* Description : Clears Tamper Pin Event pending flag.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void BKP_ClearFlag(void)
{
/* Set CTE bit to clear Tamper Pin Event flag */
BKP->CSR |= CSR_CTE_Set;
}
/*******************************************************************************
* Function Name : BKP_GetITStatus
* Description : Checks whether the Tamper Pin Interrupt has occurred or not.
* Input : None
* Output : None
* Return : The new state of the Tamper Pin Interrupt (SET or RESET).
*******************************************************************************/
ITStatus BKP_GetITStatus(void)
{
return (ITStatus)(*(vu32 *) CSR_TIF_BB);
}
/*******************************************************************************
* Function Name : BKP_ClearITPendingBit
* Description : Clears Tamper Pin Interrupt pending bit.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void BKP_ClearITPendingBit(void)
{
/* Set CTI bit to clear Tamper Pin Interrupt pending bit */
BKP->CSR |= CSR_CTI_Set;
}
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

907
bsp/stm32f103vb_lwip/library/src/stm32f10x_can.c Normal file
View File

@ -0,0 +1,907 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_can.c
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file provides all the CAN firmware functions.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_can.h"
#include "stm32f10x_rcc.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* CAN Master Control Register bits */
#define MCR_INRQ ((u32)0x00000001) /* Initialization request */
#define MCR_SLEEP ((u32)0x00000002) /* Sleep mode request */
#define MCR_TXFP ((u32)0x00000004) /* Transmit FIFO priority */
#define MCR_RFLM ((u32)0x00000008) /* Receive FIFO locked mode */
#define MCR_NART ((u32)0x00000010) /* No automatic retransmission */
#define MCR_AWUM ((u32)0x00000020) /* Automatic wake up mode */
#define MCR_ABOM ((u32)0x00000040) /* Automatic bus-off management */
#define MCR_TTCM ((u32)0x00000080) /* time triggered communication */
/* CAN Master Status Register bits */
#define MSR_INAK ((u32)0x00000001) /* Initialization acknowledge */
#define MSR_WKUI ((u32)0x00000008) /* Wake-up interrupt */
#define MSR_SLAKI ((u32)0x00000010) /* Sleep acknowledge interrupt */
/* CAN Transmit Status Register bits */
#define TSR_RQCP0 ((u32)0x00000001) /* Request completed mailbox0 */
#define TSR_TXOK0 ((u32)0x00000002) /* Transmission OK of mailbox0 */
#define TSR_ABRQ0 ((u32)0x00000080) /* Abort request for mailbox0 */
#define TSR_RQCP1 ((u32)0x00000100) /* Request completed mailbox1 */
#define TSR_TXOK1 ((u32)0x00000200) /* Transmission OK of mailbox1 */
#define TSR_ABRQ1 ((u32)0x00008000) /* Abort request for mailbox1 */
#define TSR_RQCP2 ((u32)0x00010000) /* Request completed mailbox2 */
#define TSR_TXOK2 ((u32)0x00020000) /* Transmission OK of mailbox2 */
#define TSR_ABRQ2 ((u32)0x00800000) /* Abort request for mailbox2 */
#define TSR_TME0 ((u32)0x04000000) /* Transmit mailbox 0 empty */
#define TSR_TME1 ((u32)0x08000000) /* Transmit mailbox 1 empty */
#define TSR_TME2 ((u32)0x10000000) /* Transmit mailbox 2 empty */
/* CAN Receive FIFO 0 Register bits */
#define RF0R_FULL0 ((u32)0x00000008) /* FIFO 0 full */
#define RF0R_FOVR0 ((u32)0x00000010) /* FIFO 0 overrun */
#define RF0R_RFOM0 ((u32)0x00000020) /* Release FIFO 0 output mailbox */
/* CAN Receive FIFO 1 Register bits */
#define RF1R_FULL1 ((u32)0x00000008) /* FIFO 1 full */
#define RF1R_FOVR1 ((u32)0x00000010) /* FIFO 1 overrun */
#define RF1R_RFOM1 ((u32)0x00000020) /* Release FIFO 1 output mailbox */
/* CAN Error Status Register bits */
#define ESR_EWGF ((u32)0x00000001) /* Error warning flag */
#define ESR_EPVF ((u32)0x00000002) /* Error passive flag */
#define ESR_BOFF ((u32)0x00000004) /* Bus-off flag */
/* CAN Mailbox Transmit Request */
#define TMIDxR_TXRQ ((u32)0x00000001) /* Transmit mailbox request */
/* CAN Filter Master Register bits */
#define FMR_FINIT ((u32)0x00000001) /* Filter init mode */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
static ITStatus CheckITStatus(u32 CAN_Reg, u32 It_Bit);
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : CAN_DeInit
* Description : Deinitializes the CAN peripheral registers to their default
* reset values.
* Input : None.
* Output : None.
* Return : None.
*******************************************************************************/
void CAN_DeInit(void)
{
/* Enable CAN reset state */
RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN, ENABLE);
/* Release CAN from reset state */
RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN, DISABLE);
}
/*******************************************************************************
* Function Name : CAN_Init
* Description : Initializes the CAN peripheral according to the specified
* parameters in the CAN_InitStruct.
* Input : CAN_InitStruct: pointer to a CAN_InitTypeDef structure that
contains the configuration information for the CAN peripheral.
* Output : None.
* Return : Constant indicates initialization succeed which will be
* CANINITFAILED or CANINITOK.
*******************************************************************************/
u8 CAN_Init(CAN_InitTypeDef* CAN_InitStruct)
{
u8 InitStatus = 0;
u16 WaitAck = 0;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM));
assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM));
assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM));
assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART));
assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM));
assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP));
assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode));
assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW));
assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1));
assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2));
assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler));
/* Request initialisation */
CAN->MCR = MCR_INRQ;
/* ...and check acknowledged */
if ((CAN->MSR & MSR_INAK) == 0)
{
InitStatus = CANINITFAILED;
}
else
{
/* Set the time triggered communication mode */
if (CAN_InitStruct->CAN_TTCM == ENABLE)
{
CAN->MCR |= MCR_TTCM;
}
else
{
CAN->MCR &= ~MCR_TTCM;
}
/* Set the automatic bus-off management */
if (CAN_InitStruct->CAN_ABOM == ENABLE)
{
CAN->MCR |= MCR_ABOM;
}
else
{
CAN->MCR &= ~MCR_ABOM;
}
/* Set the automatic wake-up mode */
if (CAN_InitStruct->CAN_AWUM == ENABLE)
{
CAN->MCR |= MCR_AWUM;
}
else
{
CAN->MCR &= ~MCR_AWUM;
}
/* Set the no automatic retransmission */
if (CAN_InitStruct->CAN_NART == ENABLE)
{
CAN->MCR |= MCR_NART;
}
else
{
CAN->MCR &= ~MCR_NART;
}
/* Set the receive FIFO locked mode */
if (CAN_InitStruct->CAN_RFLM == ENABLE)
{
CAN->MCR |= MCR_RFLM;
}
else
{
CAN->MCR &= ~MCR_RFLM;
}
/* Set the transmit FIFO priority */
if (CAN_InitStruct->CAN_TXFP == ENABLE)
{
CAN->MCR |= MCR_TXFP;
}
else
{
CAN->MCR &= ~MCR_TXFP;
}
/* Set the bit timing register */
CAN->BTR = (u32)((u32)CAN_InitStruct->CAN_Mode << 30) | ((u32)CAN_InitStruct->CAN_SJW << 24) |
((u32)CAN_InitStruct->CAN_BS1 << 16) | ((u32)CAN_InitStruct->CAN_BS2 << 20) |
((u32)CAN_InitStruct->CAN_Prescaler - 1);
InitStatus = CANINITOK;
/* Request leave initialisation */
CAN->MCR &= ~MCR_INRQ;
/* Wait the acknowledge */
for(WaitAck = 0x400; WaitAck > 0x0; WaitAck--)
{
}
/* ...and check acknowledged */
if ((CAN->MSR & MSR_INAK) == MSR_INAK)
{
InitStatus = CANINITFAILED;
}
}
/* At this step, return the status of initialization */
return InitStatus;
}
/*******************************************************************************
* Function Name : CAN_FilterInit
* Description : Initializes the CAN peripheral according to the specified
* parameters in the CAN_FilterInitStruct.
* Input : CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef
* structure that contains the configuration information.
* Output : None.
* Return : None.
*******************************************************************************/
void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct)
{
u16 FilterNumber_BitPos = 0;
/* Check the parameters */
assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber));
assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode));
assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale));
assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment));
assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation));
FilterNumber_BitPos =
(u16)(((u16)0x0001) << ((u16)CAN_FilterInitStruct->CAN_FilterNumber));
/* Initialisation mode for the filter */
CAN->FMR |= FMR_FINIT;
/* Filter Deactivation */
CAN->FA1R &= ~(u32)FilterNumber_BitPos;
/* Filter Scale */
if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit)
{
/* 16-bit scale for the filter */
CAN->FS1R &= ~(u32)FilterNumber_BitPos;
/* First 16-bit identifier and First 16-bit mask */
/* Or First 16-bit identifier and Second 16-bit identifier */
CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 =
((u32)((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) |
((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterIdLow);
/* Second 16-bit identifier and Second 16-bit mask */
/* Or Third 16-bit identifier and Fourth 16-bit identifier */
CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 =
((u32)((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterIdHigh);
}
if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit)
{
/* 32-bit scale for the filter */
CAN->FS1R |= FilterNumber_BitPos;
/* 32-bit identifier or First 32-bit identifier */
CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 =
((u32)((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) |
((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterIdLow);
/* 32-bit mask or Second 32-bit identifier */
CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 =
((u32)((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterMaskIdLow);
}
/* Filter Mode */
if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask)
{
/*Id/Mask mode for the filter*/
CAN->FM1R &= ~(u32)FilterNumber_BitPos;
}
else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
{
/*Identifier list mode for the filter*/
CAN->FM1R |= (u32)FilterNumber_BitPos;
}
/* Filter FIFO assignment */
if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO0)
{
/* FIFO 0 assignation for the filter */
CAN->FFA1R &= ~(u32)FilterNumber_BitPos;
}
if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO1)
{
/* FIFO 1 assignation for the filter */
CAN->FFA1R |= (u32)FilterNumber_BitPos;
}
/* Filter activation */
if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE)
{
CAN->FA1R |= FilterNumber_BitPos;
}
/* Leave the initialisation mode for the filter */
CAN->FMR &= ~FMR_FINIT;
}
/*******************************************************************************
* Function Name : CAN_StructInit
* Description : Fills each CAN_InitStruct member with its default value.
* Input : CAN_InitStruct: pointer to a CAN_InitTypeDef structure which
* will be initialized.
* Output : None.
* Return : None.
*******************************************************************************/
void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct)
{
/* Reset CAN init structure parameters values */
/* Initialize the time triggered communication mode */
CAN_InitStruct->CAN_TTCM = DISABLE;
/* Initialize the automatic bus-off management */
CAN_InitStruct->CAN_ABOM = DISABLE;
/* Initialize the automatic wake-up mode */
CAN_InitStruct->CAN_AWUM = DISABLE;
/* Initialize the no automatic retransmission */
CAN_InitStruct->CAN_NART = DISABLE;
/* Initialize the receive FIFO locked mode */
CAN_InitStruct->CAN_RFLM = DISABLE;
/* Initialize the transmit FIFO priority */
CAN_InitStruct->CAN_TXFP = DISABLE;
/* Initialize the CAN_Mode member */
CAN_InitStruct->CAN_Mode = CAN_Mode_Normal;
/* Initialize the CAN_SJW member */
CAN_InitStruct->CAN_SJW = CAN_SJW_1tq;
/* Initialize the CAN_BS1 member */
CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq;
/* Initialize the CAN_BS2 member */
CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq;
/* Initialize the CAN_Prescaler member */
CAN_InitStruct->CAN_Prescaler = 1;
}
/*******************************************************************************
* Function Name : CAN_ITConfig
* Description : Enables or disables the specified CAN interrupts.
* Input : - CAN_IT: specifies the CAN interrupt sources to be enabled or
* disabled.
* This parameter can be: CAN_IT_TME, CAN_IT_FMP0, CAN_IT_FF0,
* CAN_IT_FOV0, CAN_IT_FMP1, CAN_IT_FF1,
* CAN_IT_FOV1, CAN_IT_EWG, CAN_IT_EPV,
* CAN_IT_LEC, CAN_IT_ERR, CAN_IT_WKU or
* CAN_IT_SLK.
* - NewState: new state of the CAN interrupts.
* This parameter can be: ENABLE or DISABLE.
* Output : None.
* Return : None.
*******************************************************************************/
void CAN_ITConfig(u32 CAN_IT, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_CAN_ITConfig(CAN_IT));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected CAN interrupt */
CAN->IER |= CAN_IT;
}
else
{
/* Disable the selected CAN interrupt */
CAN->IER &= ~CAN_IT;
}
}
/*******************************************************************************
* Function Name : CAN_Transmit
* Description : Initiates the transmission of a message.
* Input : TxMessage: pointer to a structure which contains CAN Id, CAN
* DLC and CAN datas.
* Output : None.
* Return : The number of the mailbox that is used for transmission
* or CAN_NO_MB if there is no empty mailbox.
*******************************************************************************/
u8 CAN_Transmit(CanTxMsg* TxMessage)
{
u8 TransmitMailbox = 0;
/* Check the parameters */
assert_param(IS_CAN_STDID(TxMessage->StdId));
assert_param(IS_CAN_EXTID(TxMessage->StdId));
assert_param(IS_CAN_IDTYPE(TxMessage->IDE));
assert_param(IS_CAN_RTR(TxMessage->RTR));
assert_param(IS_CAN_DLC(TxMessage->DLC));
/* Select one empty transmit mailbox */
if ((CAN->TSR&TSR_TME0) == TSR_TME0)
{
TransmitMailbox = 0;
}
else if ((CAN->TSR&TSR_TME1) == TSR_TME1)
{
TransmitMailbox = 1;
}
else if ((CAN->TSR&TSR_TME2) == TSR_TME2)
{
TransmitMailbox = 2;
}
else
{
TransmitMailbox = CAN_NO_MB;
}
if (TransmitMailbox != CAN_NO_MB)
{
/* Set up the Id */
CAN->sTxMailBox[TransmitMailbox].TIR &= TMIDxR_TXRQ;
if (TxMessage->IDE == CAN_ID_STD)
{
TxMessage->StdId &= (u32)0x000007FF;
TxMessage->StdId = TxMessage->StdId << 21;
CAN->sTxMailBox[TransmitMailbox].TIR |= (TxMessage->StdId | TxMessage->IDE |
TxMessage->RTR);
}
else
{
TxMessage->ExtId &= (u32)0x1FFFFFFF;
TxMessage->ExtId <<= 3;
CAN->sTxMailBox[TransmitMailbox].TIR |= (TxMessage->ExtId | TxMessage->IDE |
TxMessage->RTR);
}
/* Set up the DLC */
TxMessage->DLC &= (u8)0x0000000F;
CAN->sTxMailBox[TransmitMailbox].TDTR &= (u32)0xFFFFFFF0;
CAN->sTxMailBox[TransmitMailbox].TDTR |= TxMessage->DLC;
/* Set up the data field */
CAN->sTxMailBox[TransmitMailbox].TDLR = (((u32)TxMessage->Data[3] << 24) |
((u32)TxMessage->Data[2] << 16) |
((u32)TxMessage->Data[1] << 8) |
((u32)TxMessage->Data[0]));
CAN->sTxMailBox[TransmitMailbox].TDHR = (((u32)TxMessage->Data[7] << 24) |
((u32)TxMessage->Data[6] << 16) |
((u32)TxMessage->Data[5] << 8) |
((u32)TxMessage->Data[4]));
/* Request transmission */
CAN->sTxMailBox[TransmitMailbox].TIR |= TMIDxR_TXRQ;
}
return TransmitMailbox;
}
/*******************************************************************************
* Function Name : CAN_TransmitStatus
* Description : Checks the transmission of a message.
* Input : TransmitMailbox: the number of the mailbox that is used for
* transmission.
* Output : None.
* Return : CANTXOK if the CAN driver transmits the message, CANTXFAILED
* in an other case.
*******************************************************************************/
u8 CAN_TransmitStatus(u8 TransmitMailbox)
{
/* RQCP, TXOK and TME bits */
u8 State = 0;
/* Check the parameters */
assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox));
switch (TransmitMailbox)
{
case (0): State |= (u8)((CAN->TSR & TSR_RQCP0) << 2);
State |= (u8)((CAN->TSR & TSR_TXOK0) >> 0);
State |= (u8)((CAN->TSR & TSR_TME0) >> 26);
break;
case (1): State |= (u8)((CAN->TSR & TSR_RQCP1) >> 6);
State |= (u8)((CAN->TSR & TSR_TXOK1) >> 8);
State |= (u8)((CAN->TSR & TSR_TME1) >> 27);
break;
case (2): State |= (u8)((CAN->TSR & TSR_RQCP2) >> 14);
State |= (u8)((CAN->TSR & TSR_TXOK2) >> 16);
State |= (u8)((CAN->TSR & TSR_TME2) >> 28);
break;
default:
State = CANTXFAILED;
break;
}
switch (State)
{
/* transmit pending */
case (0x0): State = CANTXPENDING;
break;
/* transmit failed */
case (0x5): State = CANTXFAILED;
break;
/* transmit succedeed */
case (0x7): State = CANTXOK;
break;
default:
State = CANTXFAILED;
break;
}
return State;
}
/*******************************************************************************
* Function Name : CAN_CancelTransmit
* Description : Cancels a transmit request.
* Input : Mailbox number.
* Output : None.
* Return : None.
*******************************************************************************/
void CAN_CancelTransmit(u8 Mailbox)
{
/* Check the parameters */
assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox));
/* abort transmission */
switch (Mailbox)
{
case (0): CAN->TSR |= TSR_ABRQ0;
break;
case (1): CAN->TSR |= TSR_ABRQ1;
break;
case (2): CAN->TSR |= TSR_ABRQ2;
break;
default:
break;
}
}
/*******************************************************************************
* Function Name : CAN_FIFORelease
* Description : Releases a FIFO.
* Input : FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1.
* Output : None.
* Return : None.
*******************************************************************************/
void CAN_FIFORelease(u8 FIFONumber)
{
/* Check the parameters */
assert_param(IS_CAN_FIFO(FIFONumber));
/* Release FIFO0 */
if (FIFONumber == CAN_FIFO0)
{
CAN->RF0R = RF0R_RFOM0;
}
/* Release FIFO1 */
else /* FIFONumber == CAN_FIFO1 */
{
CAN->RF1R = RF1R_RFOM1;
}
}
/*******************************************************************************
* Function Name : CAN_MessagePending
* Description : Returns the number of pending messages.
* Input : FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
* Output : None.
* Return : NbMessage which is the number of pending message.
*******************************************************************************/
u8 CAN_MessagePending(u8 FIFONumber)
{
u8 MessagePending=0;
/* Check the parameters */
assert_param(IS_CAN_FIFO(FIFONumber));
if (FIFONumber == CAN_FIFO0)
{
MessagePending = (u8)(CAN->RF0R&(u32)0x03);
}
else if (FIFONumber == CAN_FIFO1)
{
MessagePending = (u8)(CAN->RF1R&(u32)0x03);
}
else
{
MessagePending = 0;
}
return MessagePending;
}
/*******************************************************************************
* Function Name : CAN_Receive
* Description : Receives a message.
* Input : FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
* Output : RxMessage: pointer to a structure which contains CAN Id,
* CAN DLC, CAN datas and FMI number.
* Return : None.
*******************************************************************************/
void CAN_Receive(u8 FIFONumber, CanRxMsg* RxMessage)
{
/* Check the parameters */
assert_param(IS_CAN_FIFO(FIFONumber));
/* Get the Id */
RxMessage->IDE = (u8)0x04 & CAN->sFIFOMailBox[FIFONumber].RIR;
if (RxMessage->IDE == CAN_ID_STD)
{
RxMessage->StdId = (u32)0x000007FF & (CAN->sFIFOMailBox[FIFONumber].RIR >> 21);
}
else
{
RxMessage->ExtId = (u32)0x1FFFFFFF & (CAN->sFIFOMailBox[FIFONumber].RIR >> 3);
}
RxMessage->RTR = (u8)0x02 & CAN->sFIFOMailBox[FIFONumber].RIR;
/* Get the DLC */
RxMessage->DLC = (u8)0x0F & CAN->sFIFOMailBox[FIFONumber].RDTR;
/* Get the FMI */
RxMessage->FMI = (u8)0xFF & (CAN->sFIFOMailBox[FIFONumber].RDTR >> 8);
/* Get the data field */
RxMessage->Data[0] = (u8)0xFF & CAN->sFIFOMailBox[FIFONumber].RDLR;
RxMessage->Data[1] = (u8)0xFF & (CAN->sFIFOMailBox[FIFONumber].RDLR >> 8);
RxMessage->Data[2] = (u8)0xFF & (CAN->sFIFOMailBox[FIFONumber].RDLR >> 16);
RxMessage->Data[3] = (u8)0xFF & (CAN->sFIFOMailBox[FIFONumber].RDLR >> 24);
RxMessage->Data[4] = (u8)0xFF & CAN->sFIFOMailBox[FIFONumber].RDHR;
RxMessage->Data[5] = (u8)0xFF & (CAN->sFIFOMailBox[FIFONumber].RDHR >> 8);
RxMessage->Data[6] = (u8)0xFF & (CAN->sFIFOMailBox[FIFONumber].RDHR >> 16);
RxMessage->Data[7] = (u8)0xFF & (CAN->sFIFOMailBox[FIFONumber].RDHR >> 24);
/* Release the FIFO */
CAN_FIFORelease(FIFONumber);
}
/*******************************************************************************
* Function Name : CAN_Sleep
* Description : Enters the low power mode.
* Input : None.
* Output : None.
* Return : CANSLEEPOK if sleep entered, CANSLEEPFAILED in an other case.
*******************************************************************************/
u8 CAN_Sleep(void)
{
u8 SleepStatus = 0;
/* Sleep mode entering request */
CAN->MCR |= MCR_SLEEP;
SleepStatus = CANSLEEPOK;
/* Sleep mode status */
if ((CAN->MCR&MCR_SLEEP) == 0)
{
/* Sleep mode not entered */
SleepStatus = CANSLEEPFAILED;
}
/* At this step, sleep mode status */
return SleepStatus;
}
/*******************************************************************************
* Function Name : CAN_WakeUp
* Description : Wakes the CAN up.
* Input : None.
* Output : None.
* Return : CANWAKEUPOK if sleep mode left, CANWAKEUPFAILED in an other
* case.
*******************************************************************************/
u8 CAN_WakeUp(void)
{
u8 WakeUpStatus = 0;
/* Wake up request */
CAN->MCR &= ~MCR_SLEEP;
WakeUpStatus = CANWAKEUPFAILED;
/* Sleep mode status */
if ((CAN->MCR&MCR_SLEEP) == 0)
{
/* Sleep mode exited */
WakeUpStatus = CANWAKEUPOK;
}
/* At this step, sleep mode status */
return WakeUpStatus;
}
/*******************************************************************************
* Function Name : CAN_GetFlagStatus
* Description : Checks whether the specified CAN flag is set or not.
* Input : CAN_FLAG: specifies the flag to check.
* This parameter can be: CAN_FLAG_EWG, CAN_FLAG_EPV or
* CAN_FLAG_BOF.
* Output : None.
* Return : The new state of CAN_FLAG (SET or RESET).
*******************************************************************************/
FlagStatus CAN_GetFlagStatus(u32 CAN_FLAG)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_CAN_FLAG(CAN_FLAG));
/* Check the status of the specified CAN flag */
if ((CAN->ESR & CAN_FLAG) != (u32)RESET)
{
/* CAN_FLAG is set */
bitstatus = SET;
}
else
{
/* CAN_FLAG is reset */
bitstatus = RESET;
}
/* Return the CAN_FLAG status */
return bitstatus;
}
/*******************************************************************************
* Function Name : CAN_ClearFlag
* Description : Clears the CAN's pending flags.
* Input : CAN_FLAG: specifies the flag to clear.
* Output : None.
* Return : None.
*******************************************************************************/
void CAN_ClearFlag(u32 CAN_FLAG)
{
/* Check the parameters */
assert_param(IS_CAN_FLAG(CAN_FLAG));
/* Clear the selected CAN flags */
CAN->ESR &= ~CAN_FLAG;
}
/*******************************************************************************
* Function Name : CAN_GetITStatus
* Description : Checks whether the specified CAN interrupt has occurred or
* not.
* Input : CAN_IT: specifies the CAN interrupt source to check.
* This parameter can be: CAN_IT_RQCP0, CAN_IT_RQCP1, CAN_IT_RQCP2,
* CAN_IT_FF0, CAN_IT_FOV0, CAN_IT_FF1,
* CAN_IT_FOV1, CAN_IT_EWG, CAN_IT_EPV,
* CAN_IT_BOF, CAN_IT_WKU or CAN_IT_SLK.
* Output : None.
* Return : The new state of CAN_IT (SET or RESET).
*******************************************************************************/
ITStatus CAN_GetITStatus(u32 CAN_IT)
{
ITStatus pendingbitstatus = RESET;
/* Check the parameters */
assert_param(IS_CAN_ITStatus(CAN_IT));
switch (CAN_IT)
{
case CAN_IT_RQCP0:
pendingbitstatus = CheckITStatus(CAN->TSR, TSR_RQCP0);
break;
case CAN_IT_RQCP1:
pendingbitstatus = CheckITStatus(CAN->TSR, TSR_RQCP1);
break;
case CAN_IT_RQCP2:
pendingbitstatus = CheckITStatus(CAN->TSR, TSR_RQCP2);
break;
case CAN_IT_FF0:
pendingbitstatus = CheckITStatus(CAN->RF0R, RF0R_FULL0);
break;
case CAN_IT_FOV0:
pendingbitstatus = CheckITStatus(CAN->RF0R, RF0R_FOVR0);
break;
case CAN_IT_FF1:
pendingbitstatus = CheckITStatus(CAN->RF1R, RF1R_FULL1);
break;
case CAN_IT_FOV1:
pendingbitstatus = CheckITStatus(CAN->RF1R, RF1R_FOVR1);
break;
case CAN_IT_EWG:
pendingbitstatus = CheckITStatus(CAN->ESR, ESR_EWGF);
break;
case CAN_IT_EPV:
pendingbitstatus = CheckITStatus(CAN->ESR, ESR_EPVF);
break;
case CAN_IT_BOF:
pendingbitstatus = CheckITStatus(CAN->ESR, ESR_BOFF);
break;
case CAN_IT_SLK:
pendingbitstatus = CheckITStatus(CAN->MSR, MSR_SLAKI);
break;
case CAN_IT_WKU:
pendingbitstatus = CheckITStatus(CAN->MSR, MSR_WKUI);
break;
default :
pendingbitstatus = RESET;
break;
}
/* Return the CAN_IT status */
return pendingbitstatus;
}
/*******************************************************************************
* Function Name : CAN_ClearITPendingBit
* Description : Clears the CAN’s interrupt pending bits.
* Input : CAN_IT: specifies the interrupt pending bit to clear.
* Output : None.
* Return : None.
*******************************************************************************/
void CAN_ClearITPendingBit(u32 CAN_IT)
{
/* Check the parameters */
assert_param(IS_CAN_ITStatus(CAN_IT));
switch (CAN_IT)
{
case CAN_IT_RQCP0:
CAN->TSR = TSR_RQCP0; /* rc_w1*/
break;
case CAN_IT_RQCP1:
CAN->TSR = TSR_RQCP1; /* rc_w1*/
break;
case CAN_IT_RQCP2:
CAN->TSR = TSR_RQCP2; /* rc_w1*/
break;
case CAN_IT_FF0:
CAN->RF0R = RF0R_FULL0; /* rc_w1*/
break;
case CAN_IT_FOV0:
CAN->RF0R = RF0R_FOVR0; /* rc_w1*/
break;
case CAN_IT_FF1:
CAN->RF1R = RF1R_FULL1; /* rc_w1*/
break;
case CAN_IT_FOV1:
CAN->RF1R = RF1R_FOVR1; /* rc_w1*/
break;
case CAN_IT_EWG:
CAN->ESR &= ~ ESR_EWGF; /* rw */
break;
case CAN_IT_EPV:
CAN->ESR &= ~ ESR_EPVF; /* rw */
break;
case CAN_IT_BOF:
CAN->ESR &= ~ ESR_BOFF; /* rw */
break;
case CAN_IT_WKU:
CAN->MSR = MSR_WKUI; /* rc_w1*/
break;
case CAN_IT_SLK:
CAN->MSR = MSR_SLAKI; /* rc_w1*/
break;
default :
break;
}
}
/*******************************************************************************
* Function Name : CheckITStatus
* Description : Checks whether the CAN interrupt has occurred or not.
* Input : CAN_Reg: specifies the CAN interrupt register to check.
* It_Bit: specifies the interrupt source bit to check.
* Output : None.
* Return : The new state of the CAN Interrupt (SET or RESET).
*******************************************************************************/
static ITStatus CheckITStatus(u32 CAN_Reg, u32 It_Bit)
{
ITStatus pendingbitstatus = RESET;
if ((CAN_Reg & It_Bit) != (u32)RESET)
{
/* CAN_IT is set */
pendingbitstatus = SET;
}
else
{
/* CAN_IT is reset */
pendingbitstatus = RESET;
}
return pendingbitstatus;
}
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

114
bsp/stm32f103vb_lwip/library/src/stm32f10x_crc.c Normal file
View File

@ -0,0 +1,114 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_crc.c
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file provides all the CRC firmware functions.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_crc.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* CR register bit mask */
#define CR_RESET_Set ((u32)0x00000001)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : CRC_ResetDR
* Description : Resets the CRC Data register (DR).
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void CRC_ResetDR(void)
{
/* Reset CRC generator */
CRC->CR = CR_RESET_Set;
}
/*******************************************************************************
* Function Name : CRC_CalcCRC
* Description : Computes the 32-bit CRC of a given data word(32-bit).
* Input : - Data: data word(32-bit) to compute its CRC
* Output : None
* Return : 32-bit CRC
*******************************************************************************/
u32 CRC_CalcCRC(u32 Data)
{
CRC->DR = Data;
return (CRC->DR);
}
/*******************************************************************************
* Function Name : CRC_CalcBlockCRC
* Description : Computes the 32-bit CRC of a given buffer of data word(32-bit).
* Input : - pBuffer: pointer to the buffer containing the data to be
* computed
* - BufferLength: length of the buffer to be computed
* Output : None
* Return : 32-bit CRC
*******************************************************************************/
u32 CRC_CalcBlockCRC(u32 pBuffer[], u32 BufferLength)
{
u32 index = 0;
for(index = 0; index < BufferLength; index++)
{
CRC->DR = pBuffer[index];
}
return (CRC->DR);
}
/*******************************************************************************
* Function Name : CRC_GetCRC
* Description : Returns the current CRC value.
* Input : None
* Output : None
* Return : 32-bit CRC
*******************************************************************************/
u32 CRC_GetCRC(void)
{
return (CRC->DR);
}
/*******************************************************************************
* Function Name : CRC_SetIDRegister
* Description : Stores a 8-bit data in the Independent Data(ID) register.
* Input : - IDValue: 8-bit value to be stored in the ID register
* Output : None
* Return : None
*******************************************************************************/
void CRC_SetIDRegister(u8 IDValue)
{
CRC->IDR = IDValue;
}
/*******************************************************************************
* Function Name : CRC_GetIDRegister
* Description : Returns the 8-bit data stored in the Independent Data(ID) register
* Input : None
* Output : None
* Return : 8-bit value of the ID register
*******************************************************************************/
u8 CRC_GetIDRegister(void)
{
return (CRC->IDR);
}
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

389
bsp/stm32f103vb_lwip/library/src/stm32f10x_dac.c Normal file
View File

@ -0,0 +1,389 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_dac.c
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file provides all the DAC firmware functions.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_dac.h"
#include "stm32f10x_rcc.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* DAC EN mask */
#define CR_EN_Set ((u32)0x00000001)
/* DAC DMAEN mask */
#define CR_DMAEN_Set ((u32)0x00001000)
/* CR register Mask */
#define CR_CLEAR_Mask ((u32)0x00000FFE)
/* DAC SWTRIG mask */
#define SWTRIGR_SWTRIG_Set ((u32)0x00000001)
/* DAC Dual Channels SWTRIG masks */
#define DUAL_SWTRIG_Set ((u32)0x00000003)
#define DUAL_SWTRIG_Reset ((u32)0xFFFFFFFC)
/* DHR registers offsets */
#define DHR12R1_Offset ((u32)0x00000008)
#define DHR12R2_Offset ((u32)0x00000014)
#define DHR12RD_Offset ((u32)0x00000020)
/* DOR register offset */
#define DOR_Offset ((u32)0x0000002C)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : DAC_DeInit
* Description : Deinitializes the DAC peripheral registers to their default
* reset values.
* Input : None.
* Output : None
* Return : None
*******************************************************************************/
void DAC_DeInit(void)
{
/* Enable DAC reset state */
RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);
/* Release DAC from reset state */
RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);
}
/*******************************************************************************
* Function Name : DAC_Init
* Description : Initializes the DAC peripheral according to the specified
* parameters in the DAC_InitStruct.
* Input : - DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* - DAC_Channel_1: DAC Channel1 selected
* - DAC_Channel_2: DAC Channel2 selected
* - DAC_InitStruct: pointer to a DAC_InitTypeDef structure that
* contains the configuration information for the specified
* DAC channel.
* Output : None
* Return : None
*******************************************************************************/
void DAC_Init(u32 DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
{
u32 tmpreg1 = 0, tmpreg2 = 0;
/* Check the DAC parameters */
assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));
/*---------------------------- DAC CR Configuration --------------------------*/
/* Get the DAC CR value */
tmpreg1 = DAC->CR;
/* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
tmpreg1 &= ~(CR_CLEAR_Mask << DAC_Channel);
/* Configure for the selected DAC channel: buffer output, trigger, wave genration,
mask/amplitude for wave genration */
/* Set TSELx and TENx bits according to DAC_Trigger value */
/* Set WAVEx bits according to DAC_WaveGeneration value */
/* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */
/* Set BOFFx bit according to DAC_OutputBuffer value */
tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);
/* Calculate CR register value depending on DAC_Channel */
tmpreg1 |= tmpreg2 << DAC_Channel;
/* Write to DAC CR */
DAC->CR = tmpreg1;
}
/*******************************************************************************
* Function Name : DAC_StructInit
* Description : Fills each DAC_InitStruct member with its default value.
* Input : - DAC_InitStruct : pointer to a DAC_InitTypeDef structure
* which will be initialized.
* Output : None
* Return : None
*******************************************************************************/
void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
{
/*--------------- Reset DAC init structure parameters values -----------------*/
/* Initialize the DAC_Trigger member */
DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
/* Initialize the DAC_WaveGeneration member */
DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
/* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
/* Initialize the DAC_OutputBuffer member */
DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
}
/*******************************************************************************
* Function Name : DAC_Cmd
* Description : Enables or disables the specified DAC channel.
* Input - DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* - DAC_Channel_1: DAC Channel1 selected
* - DAC_Channel_2: DAC Channel2 selected
* - NewState: new state of the DAC channel.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void DAC_Cmd(u32 DAC_Channel, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected DAC channel */
DAC->CR |= CR_EN_Set << DAC_Channel;
}
else
{
/* Disable the selected DAC channel */
DAC->CR &= ~(CR_EN_Set << DAC_Channel);
}
}
/*******************************************************************************
* Function Name : DAC_DMACmd
* Description : Enables or disables the specified DAC channel DMA request.
* Input - DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* - DAC_Channel_1: DAC Channel1 selected
* - DAC_Channel_2: DAC Channel2 selected
* - NewState: new state of the selected DAC channel DMA request.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void DAC_DMACmd(u32 DAC_Channel, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected DAC channel DMA request */
DAC->CR |= CR_DMAEN_Set << DAC_Channel;
}
else
{
/* Disable the selected DAC channel DMA request */
DAC->CR &= ~(CR_DMAEN_Set << DAC_Channel);
}
}
/*******************************************************************************
* Function Name : DAC_SoftwareTriggerCmd
* Description : Enables or disables the selected DAC channel software trigger.
* Input - DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* - DAC_Channel_1: DAC Channel1 selected
* - DAC_Channel_2: DAC Channel2 selected
* - NewState: new state of the selected DAC channel software trigger.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void DAC_SoftwareTriggerCmd(u32 DAC_Channel, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable software trigger for the selected DAC channel */
DAC->SWTRIGR |= SWTRIGR_SWTRIG_Set << (DAC_Channel >> 4);
}
else
{
/* Disable software trigger for the selected DAC channel */
DAC->SWTRIGR &= ~(SWTRIGR_SWTRIG_Set << (DAC_Channel >> 4));
}
}
/*******************************************************************************
* Function Name : DAC_DualSoftwareTriggerCmd
* Description : Enables or disables simultaneously the two DAC channels software
* triggers.
* Input - NewState: new state of the DAC channels software triggers.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable software trigger for both DAC channels */
DAC->SWTRIGR |= DUAL_SWTRIG_Set ;
}
else
{
/* Disable software trigger for both DAC channels */
DAC->SWTRIGR &= DUAL_SWTRIG_Reset;
}
}
/*******************************************************************************
* Function Name : DAC_WaveGenerationCmd
* Description : Enables or disables the selected DAC channel wave generation.
* Input - DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* - DAC_Channel_1: DAC Channel1 selected
* - DAC_Channel_2: DAC Channel2 selected
* - DAC_Wave: Specifies the wave type to enable or disable.
* This parameter can be one of the following values:
* - DAC_Wave_Noise: noise wave generation
* - DAC_Wave_Triangle: triangle wave generation
* - NewState: new state of the selected DAC channel wave generation.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void DAC_WaveGenerationCmd(u32 DAC_Channel, u32 DAC_Wave, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_DAC_WAVE(DAC_Wave));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected wave generation for the selected DAC channel */
DAC->CR |= DAC_Wave << DAC_Channel;
}
else
{
/* Disable the selected wave generation for the selected DAC channel */
DAC->CR &= ~(DAC_Wave << DAC_Channel);
}
}
/*******************************************************************************
* Function Name : DAC_SetChannel1Data
* Description : Set the specified data holding register value for DAC channel1.
* Input : - DAC_Align: Specifies the data alignement for DAC channel1.
* This parameter can be one of the following values:
* - DAC_Align_8b_R: 8bit right data alignement selected
* - DAC_Align_12b_L: 12bit left data alignement selected
* - DAC_Align_12b_R: 12bit right data alignement selected
* - Data : Data to be loaded in the selected data holding
* register.
* Output : None
* Return : None
*******************************************************************************/
void DAC_SetChannel1Data(u32 DAC_Align, u16 Data)
{
/* Check the parameters */
assert_param(IS_DAC_ALIGN(DAC_Align));
assert_param(IS_DAC_DATA(Data));
/* Set the DAC channel1 selected data holding register */
*((vu32 *)(DAC_BASE + DHR12R1_Offset + DAC_Align)) = (u32)Data;
}
/*******************************************************************************
* Function Name : DAC_SetChannel2Data
* Description : Set the specified data holding register value for DAC channel2.
* Input : - DAC_Align: Specifies the data alignement for DAC channel2.
* This parameter can be one of the following values:
* - DAC_Align_8b_R: 8bit right data alignement selected
* - DAC_Align_12b_L: 12bit left data alignement selected
* - DAC_Align_12b_R: 12bit right data alignement selected
* - Data : Data to be loaded in the selected data holding
* register.
* Output : None
* Return : None
*******************************************************************************/
void DAC_SetChannel2Data(u32 DAC_Align, u16 Data)
{
/* Check the parameters */
assert_param(IS_DAC_ALIGN(DAC_Align));
assert_param(IS_DAC_DATA(Data));
/* Set the DAC channel2 selected data holding register */
*((vu32 *)(DAC_BASE + DHR12R2_Offset + DAC_Align)) = (u32)Data;
}
/*******************************************************************************
* Function Name : DAC_SetDualChannelData
* Description : Set the specified data holding register value for dual channel
* DAC.
* Input : - DAC_Align: Specifies the data alignement for dual channel DAC.
* This parameter can be one of the following values:
* - DAC_Align_8b_R: 8bit right data alignement selected
* - DAC_Align_12b_L: 12bit left data alignement selected
* - DAC_Align_12b_R: 12bit right data alignement selected
* - Data2: Data for DAC Channel2 to be loaded in the selected data
* holding register.
* - Data1: Data for DAC Channel1 to be loaded in the selected data
* holding register.
* Output : None
* Return : None
*******************************************************************************/
void DAC_SetDualChannelData(u32 DAC_Align, u16 Data2, u16 Data1)
{
u32 data = 0;
/* Check the parameters */
assert_param(IS_DAC_ALIGN(DAC_Align));
assert_param(IS_DAC_DATA(Data1));
assert_param(IS_DAC_DATA(Data2));
/* Calculate and set dual DAC data holding register value */
if (DAC_Align == DAC_Align_8b_R)
{
data = ((u32)Data2 << 8) | Data1;
}
else
{
data = ((u32)Data2 << 16) | Data1;
}
/* Set the dual DAC selected data holding register */
*((vu32 *)(DAC_BASE + DHR12RD_Offset + DAC_Align)) = data;
}
/*******************************************************************************
* Function Name : DAC_GetDataOutputValue
* Description : Returns the last data output value of the selected DAC cahnnel.
* Input - DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* - DAC_Channel_1: DAC Channel1 selected
* - DAC_Channel_2: DAC Channel2 selected
* Output : None
* Return : The selected DAC channel data output value.
*******************************************************************************/
u16 DAC_GetDataOutputValue(u32 DAC_Channel)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
/* Returns the DAC channel data output register value */
return (u16) (*(vu32*)(DAC_BASE + DOR_Offset + ((u32)DAC_Channel >> 2)));
}
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

97
bsp/stm32f103vb_lwip/library/src/stm32f10x_dbgmcu.c Normal file
View File

@ -0,0 +1,97 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_dbgmcu.c
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file provides all the DBGMCU firmware functions.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_dbgmcu.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define IDCODE_DEVID_Mask ((u32)0x00000FFF)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : DBGMCU_GetREVID
* Description : Returns the device revision identifier.
* Input : None
* Output : None
* Return : Device revision identifier
*******************************************************************************/
u32 DBGMCU_GetREVID(void)
{
return(DBGMCU->IDCODE >> 16);
}
/*******************************************************************************
* Function Name : DBGMCU_GetDEVID
* Description : Returns the device identifier.
* Input : None
* Output : None
* Return : Device identifier
*******************************************************************************/
u32 DBGMCU_GetDEVID(void)
{
return(DBGMCU->IDCODE & IDCODE_DEVID_Mask);
}
/*******************************************************************************
* Function Name : DBGMCU_Config
* Description : Configures the specified peripheral and low power mode behavior
* when the MCU under Debug mode.
* Input : - DBGMCU_Periph: specifies the peripheral and low power mode.
* This parameter can be any combination of the following values:
* - DBGMCU_SLEEP: Keep debugger connection during SLEEP mode
* - DBGMCU_STOP: Keep debugger connection during STOP mode
* - DBGMCU_STANDBY: Keep debugger connection during STANDBY mode
* - DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted
* - DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted
* - DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted
* - DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted
* - DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted
* - DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted
* - DBGMCU_CAN_STOP: Debug CAN stopped when Core is halted
* - DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped
* when Core is halted
* - DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped
* when Core is halted
* - DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted
* - DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted
* - DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted
* - DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted
* - NewState: new state of the specified peripheral in Debug mode.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void DBGMCU_Config(u32 DBGMCU_Periph, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
DBGMCU->CR |= DBGMCU_Periph;
}
else
{
DBGMCU->CR &= ~DBGMCU_Periph;
}
}
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

678
bsp/stm32f103vb_lwip/library/src/stm32f10x_dma.c Normal file
View File

@ -0,0 +1,678 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_dma.c
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file provides all the DMA firmware functions.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_dma.h"
#include "stm32f10x_rcc.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* DMA ENABLE mask */
#define CCR_ENABLE_Set ((u32)0x00000001)
#define CCR_ENABLE_Reset ((u32)0xFFFFFFFE)
/* DMA1 Channelx interrupt pending bit masks */
#define DMA1_Channel1_IT_Mask ((u32)0x0000000F)
#define DMA1_Channel2_IT_Mask ((u32)0x000000F0)
#define DMA1_Channel3_IT_Mask ((u32)0x00000F00)
#define DMA1_Channel4_IT_Mask ((u32)0x0000F000)
#define DMA1_Channel5_IT_Mask ((u32)0x000F0000)
#define DMA1_Channel6_IT_Mask ((u32)0x00F00000)
#define DMA1_Channel7_IT_Mask ((u32)0x0F000000)
/* DMA2 Channelx interrupt pending bit masks */
#define DMA2_Channel1_IT_Mask ((u32)0x0000000F)
#define DMA2_Channel2_IT_Mask ((u32)0x000000F0)
#define DMA2_Channel3_IT_Mask ((u32)0x00000F00)
#define DMA2_Channel4_IT_Mask ((u32)0x0000F000)
#define DMA2_Channel5_IT_Mask ((u32)0x000F0000)
/* DMA2 FLAG mask */
#define FLAG_Mask ((u32)0x10000000)
/* DMA registers Masks */
#define CCR_CLEAR_Mask ((u32)0xFFFF800F)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : DMA_DeInit
* Description : Deinitializes the DMAy Channelx registers to their default reset
* values.
* Input : - DMAy_Channelx: where y can be 1 or 2 to select the DMA and
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the
* DMA Channel.
* Output : None
* Return : None
*******************************************************************************/
void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
/* Disable the selected DMAy Channelx */
DMAy_Channelx->CCR &= CCR_ENABLE_Reset;
/* Reset DMAy Channelx control register */
DMAy_Channelx->CCR = 0;
/* Reset DMAy Channelx remaining bytes register */
DMAy_Channelx->CNDTR = 0;
/* Reset DMAy Channelx peripheral address register */
DMAy_Channelx->CPAR = 0;
/* Reset DMAy Channelx memory address register */
DMAy_Channelx->CMAR = 0;
switch (*(u32*)&DMAy_Channelx)
{
case DMA1_Channel1_BASE:
/* Reset interrupt pending bits for DMA1 Channel1 */
DMA1->IFCR |= DMA1_Channel1_IT_Mask;
break;
case DMA1_Channel2_BASE:
/* Reset interrupt pending bits for DMA1 Channel2 */
DMA1->IFCR |= DMA1_Channel2_IT_Mask;
break;
case DMA1_Channel3_BASE:
/* Reset interrupt pending bits for DMA1 Channel3 */
DMA1->IFCR |= DMA1_Channel3_IT_Mask;
break;
case DMA1_Channel4_BASE:
/* Reset interrupt pending bits for DMA1 Channel4 */
DMA1->IFCR |= DMA1_Channel4_IT_Mask;
break;
case DMA1_Channel5_BASE:
/* Reset interrupt pending bits for DMA1 Channel5 */
DMA1->IFCR |= DMA1_Channel5_IT_Mask;
break;
case DMA1_Channel6_BASE:
/* Reset interrupt pending bits for DMA1 Channel6 */
DMA1->IFCR |= DMA1_Channel6_IT_Mask;
break;
case DMA1_Channel7_BASE:
/* Reset interrupt pending bits for DMA1 Channel7 */
DMA1->IFCR |= DMA1_Channel7_IT_Mask;
break;
case DMA2_Channel1_BASE:
/* Reset interrupt pending bits for DMA2 Channel1 */
DMA2->IFCR |= DMA2_Channel1_IT_Mask;
break;
case DMA2_Channel2_BASE:
/* Reset interrupt pending bits for DMA2 Channel2 */
DMA2->IFCR |= DMA2_Channel2_IT_Mask;
break;
case DMA2_Channel3_BASE:
/* Reset interrupt pending bits for DMA2 Channel3 */
DMA2->IFCR |= DMA2_Channel3_IT_Mask;
break;
case DMA2_Channel4_BASE:
/* Reset interrupt pending bits for DMA2 Channel4 */
DMA2->IFCR |= DMA2_Channel4_IT_Mask;
break;
case DMA2_Channel5_BASE:
/* Reset interrupt pending bits for DMA2 Channel5 */
DMA2->IFCR |= DMA2_Channel5_IT_Mask;
break;
default:
break;
}
}
/*******************************************************************************
* Function Name : DMA_Init
* Description : Initializes the DMAy Channelx according to the specified
* parameters in the DMA_InitStruct.
* Input : - DMAy_Channelx: where y can be 1 or 2 to select the DMA and
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the
* DMA Channel.
* - DMA_InitStruct: pointer to a DMA_InitTypeDef structure that
* contains the configuration information for the specified
* DMA Channel.
* Output : None
* Return : None
******************************************************************************/
void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
{
u32 tmpreg = 0;
/* Check the parameters */
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
/*--------------------------- DMAy Channelx CCR Configuration -----------------*/
/* Get the DMAy_Channelx CCR value */
tmpreg = DMAy_Channelx->CCR;
/* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
tmpreg &= CCR_CLEAR_Mask;
/* Configure DMAy Channelx: data transfer, data size, priority level and mode */
/* Set DIR bit according to DMA_DIR value */
/* Set CIRC bit according to DMA_Mode value */
/* Set PINC bit according to DMA_PeripheralInc value */
/* Set MINC bit according to DMA_MemoryInc value */
/* Set PSIZE bits according to DMA_PeripheralDataSize value */
/* Set MSIZE bits according to DMA_MemoryDataSize value */
/* Set PL bits according to DMA_Priority value */
/* Set the MEM2MEM bit according to DMA_M2M value */
tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
/* Write to DMAy Channelx CCR */
DMAy_Channelx->CCR = tmpreg;
/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
/* Write to DMAy Channelx CNDTR */
DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/
/* Write to DMAy Channelx CPAR */
DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/
/* Write to DMAy Channelx CMAR */
DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
}
/*******************************************************************************
* Function Name : DMA_StructInit
* Description : Fills each DMA_InitStruct member with its default value.
* Input : - DMA_InitStruct : pointer to a DMA_InitTypeDef structure
* which will be initialized.
* Output : None
* Return : None
*******************************************************************************/
void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
{
/*-------------- Reset DMA init structure parameters values ------------------*/
/* Initialize the DMA_PeripheralBaseAddr member */
DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
/* Initialize the DMA_MemoryBaseAddr member */
DMA_InitStruct->DMA_MemoryBaseAddr = 0;
/* Initialize the DMA_DIR member */
DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
/* Initialize the DMA_BufferSize member */
DMA_InitStruct->DMA_BufferSize = 0;
/* Initialize the DMA_PeripheralInc member */
DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
/* Initialize the DMA_MemoryInc member */
DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
/* Initialize the DMA_PeripheralDataSize member */
DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
/* Initialize the DMA_MemoryDataSize member */
DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
/* Initialize the DMA_Mode member */
DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
/* Initialize the DMA_Priority member */
DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
/* Initialize the DMA_M2M member */
DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
}
/*******************************************************************************
* Function Name : DMA_Cmd
* Description : Enables or disables the specified DMAy Channelx.
* Input : - DMAy_Channelx: where y can be 1 or 2 to select the DMA and
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the
* DMA Channel.
* - NewState: new state of the DMAy Channelx.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected DMAy Channelx */
DMAy_Channelx->CCR |= CCR_ENABLE_Set;
}
else
{
/* Disable the selected DMAy Channelx */
DMAy_Channelx->CCR &= CCR_ENABLE_Reset;
}
}
/*******************************************************************************
* Function Name : DMA_ITConfig
* Description : Enables or disables the specified DMAy Channelx interrupts.
* Input : - DMAy_Channelx: where y can be 1 or 2 to select the DMA and
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the
* DMA Channel.
* - DMA_IT: specifies the DMA interrupts sources to be enabled
* or disabled.
* This parameter can be any combination of the following values:
* - DMA_IT_TC: Transfer complete interrupt mask
* - DMA_IT_HT: Half transfer interrupt mask
* - DMA_IT_TE: Transfer error interrupt mask
* - NewState: new state of the specified DMA interrupts.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, u32 DMA_IT, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
assert_param(IS_DMA_CONFIG_IT(DMA_IT));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected DMA interrupts */
DMAy_Channelx->CCR |= DMA_IT;
}
else
{
/* Disable the selected DMA interrupts */
DMAy_Channelx->CCR &= ~DMA_IT;
}
}
/*******************************************************************************
* Function Name : DMA_GetCurrDataCounter
* Description : Returns the number of remaining data units in the current
* DMAy Channelx transfer.
* Input : - DMAy_Channelx: where y can be 1 or 2 to select the DMA and
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the
* DMA Channel.
* Output : None
* Return : The number of remaining data units in the current DMAy Channelx
* transfer.
*******************************************************************************/
u16 DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
/* Return the number of remaining data units for DMAy Channelx */
return ((u16)(DMAy_Channelx->CNDTR));
}
/*******************************************************************************
* Function Name : DMA_GetFlagStatus
* Description : Checks whether the specified DMAy Channelx flag is set or not.
* Input : - DMA_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* - DMA1_FLAG_GL1: DMA1 Channel1 global flag.
* - DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
* - DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
* - DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
* - DMA1_FLAG_GL2: DMA1 Channel2 global flag.
* - DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
* - DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
* - DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
* - DMA1_FLAG_GL3: DMA1 Channel3 global flag.
* - DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
* - DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
* - DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
* - DMA1_FLAG_GL4: DMA1 Channel4 global flag.
* - DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
* - DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
* - DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
* - DMA1_FLAG_GL5: DMA1 Channel5 global flag.
* - DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
* - DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
* - DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
* - DMA1_FLAG_GL6: DMA1 Channel6 global flag.
* - DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
* - DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
* - DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
* - DMA1_FLAG_GL7: DMA1 Channel7 global flag.
* - DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
* - DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
* - DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
* - DMA2_FLAG_GL1: DMA2 Channel1 global flag.
* - DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
* - DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
* - DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
* - DMA2_FLAG_GL2: DMA2 Channel2 global flag.
* - DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
* - DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
* - DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
* - DMA2_FLAG_GL3: DMA2 Channel3 global flag.
* - DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
* - DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
* - DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
* - DMA2_FLAG_GL4: DMA2 Channel4 global flag.
* - DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
* - DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
* - DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
* - DMA2_FLAG_GL5: DMA2 Channel5 global flag.
* - DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
* - DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
* - DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
* Output : None
* Return : The new state of DMA_FLAG (SET or RESET).
*******************************************************************************/
FlagStatus DMA_GetFlagStatus(u32 DMA_FLAG)
{
FlagStatus bitstatus = RESET;
u32 tmpreg = 0;
/* Check the parameters */
assert_param(IS_DMA_GET_FLAG(DMA_FLAG));
/* Calculate the used DMA */
if ((DMA_FLAG & FLAG_Mask) != (u32)RESET)
{
/* Get DMA2 ISR register value */
tmpreg = DMA2->ISR ;
}
else
{
/* Get DMA1 ISR register value */
tmpreg = DMA1->ISR ;
}
/* Check the status of the specified DMA flag */
if ((tmpreg & DMA_FLAG) != (u32)RESET)
{
/* DMA_FLAG is set */
bitstatus = SET;
}
else
{
/* DMA_FLAG is reset */
bitstatus = RESET;
}
/* Return the DMA_FLAG status */
return bitstatus;
}
/*******************************************************************************
* Function Name : DMA_ClearFlag
* Description : Clears the DMAy Channelx's pending flags.
* Input : - DMA_FLAG: specifies the flag to clear.
* This parameter can be any combination (for the same DMA) of
* the following values:
* - DMA1_FLAG_GL1: DMA1 Channel1 global flag.
* - DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
* - DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
* - DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
* - DMA1_FLAG_GL2: DMA1 Channel2 global flag.
* - DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
* - DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
* - DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
* - DMA1_FLAG_GL3: DMA1 Channel3 global flag.
* - DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
* - DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
* - DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
* - DMA1_FLAG_GL4: DMA1 Channel4 global flag.
* - DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
* - DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
* - DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
* - DMA1_FLAG_GL5: DMA1 Channel5 global flag.
* - DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
* - DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
* - DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
* - DMA1_FLAG_GL6: DMA1 Channel6 global flag.
* - DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
* - DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
* - DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
* - DMA1_FLAG_GL7: DMA1 Channel7 global flag.
* - DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
* - DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
* - DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
* - DMA2_FLAG_GL1: DMA2 Channel1 global flag.
* - DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
* - DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
* - DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
* - DMA2_FLAG_GL2: DMA2 Channel2 global flag.
* - DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
* - DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
* - DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
* - DMA2_FLAG_GL3: DMA2 Channel3 global flag.
* - DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
* - DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
* - DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
* - DMA2_FLAG_GL4: DMA2 Channel4 global flag.
* - DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
* - DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
* - DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
* - DMA2_FLAG_GL5: DMA2 Channel5 global flag.
* - DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
* - DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
* - DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
* Output : None
* Return : None
*******************************************************************************/
void DMA_ClearFlag(u32 DMA_FLAG)
{
/* Check the parameters */
assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));
/* Calculate the used DMA */
if ((DMA_FLAG & FLAG_Mask) != (u32)RESET)
{
/* Clear the selected DMA flags */
DMA2->IFCR = DMA_FLAG;
}
else
{
/* Clear the selected DMA flags */
DMA1->IFCR = DMA_FLAG;
}
}
/*******************************************************************************
* Function Name : DMA_GetITStatus
* Description : Checks whether the specified DMAy Channelx interrupt has
* occurred or not.
* Input : - DMA_IT: specifies the DMA interrupt source to check.
* This parameter can be one of the following values:
* - DMA1_IT_GL1: DMA1 Channel1 global interrupt.
* - DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
* - DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
* - DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
* - DMA1_IT_GL2: DMA1 Channel2 global interrupt.
* - DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
* - DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
* - DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
* - DMA1_IT_GL3: DMA1 Channel3 global interrupt.
* - DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
* - DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
* - DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
* - DMA1_IT_GL4: DMA1 Channel4 global interrupt.
* - DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
* - DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
* - DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
* - DMA1_IT_GL5: DMA1 Channel5 global interrupt.
* - DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
* - DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
* - DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
* - DMA1_IT_GL6: DMA1 Channel6 global interrupt.
* - DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
* - DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
* - DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
* - DMA1_IT_GL7: DMA1 Channel7 global interrupt.
* - DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
* - DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
* - DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
* - DMA2_IT_GL1: DMA2 Channel1 global interrupt.
* - DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
* - DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
* - DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
* - DMA2_IT_GL2: DMA2 Channel2 global interrupt.
* - DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
* - DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
* - DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
* - DMA2_IT_GL3: DMA2 Channel3 global interrupt.
* - DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
* - DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
* - DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
* - DMA2_IT_GL4: DMA2 Channel4 global interrupt.
* - DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
* - DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
* - DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
* - DMA2_IT_GL5: DMA2 Channel5 global interrupt.
* - DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
* - DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
* - DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
* Output : None
* Return : The new state of DMA_IT (SET or RESET).
*******************************************************************************/
ITStatus DMA_GetITStatus(u32 DMA_IT)
{
ITStatus bitstatus = RESET;
u32 tmpreg = 0;
/* Check the parameters */
assert_param(IS_DMA_GET_IT(DMA_IT));
/* Calculate the used DMA */
if ((DMA_IT & FLAG_Mask) != (u32)RESET)
{
/* Get DMA2 ISR register value */
tmpreg = DMA2->ISR ;
}
else
{
/* Get DMA1 ISR register value */
tmpreg = DMA1->ISR ;
}
/* Check the status of the specified DMA interrupt */
if ((tmpreg & DMA_IT) != (u32)RESET)
{
/* DMA_IT is set */
bitstatus = SET;
}
else
{
/* DMA_IT is reset */
bitstatus = RESET;
}
/* Return the DMA_IT status */
return bitstatus;
}
/*******************************************************************************
* Function Name : DMA_ClearITPendingBit
* Description : Clears the DMAy Channelx’s interrupt pending bits.
* Input : - DMA_IT: specifies the DMA interrupt pending bit to clear.
* This parameter can be any combination (for the same DMA) of
* the following values:
* - DMA1_IT_GL1: DMA1 Channel1 global interrupt.
* - DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
* - DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
* - DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
* - DMA1_IT_GL2: DMA1 Channel2 global interrupt.
* - DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
* - DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
* - DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
* - DMA1_IT_GL3: DMA1 Channel3 global interrupt.
* - DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
* - DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
* - DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
* - DMA1_IT_GL4: DMA1 Channel4 global interrupt.
* - DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
* - DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
* - DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
* - DMA1_IT_GL5: DMA1 Channel5 global interrupt.
* - DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
* - DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
* - DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
* - DMA1_IT_GL6: DMA1 Channel6 global interrupt.
* - DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
* - DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
* - DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
* - DMA1_IT_GL7: DMA1 Channel7 global interrupt.
* - DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
* - DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
* - DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
* - DMA2_IT_GL1: DMA2 Channel1 global interrupt.
* - DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
* - DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
* - DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
* - DMA2_IT_GL2: DMA2 Channel2 global interrupt.
* - DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
* - DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
* - DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
* - DMA2_IT_GL3: DMA2 Channel3 global interrupt.
* - DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
* - DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
* - DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
* - DMA2_IT_GL4: DMA2 Channel4 global interrupt.
* - DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
* - DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
* - DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
* - DMA2_IT_GL5: DMA2 Channel5 global interrupt.
* - DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
* - DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
* - DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
* Output : None
* Return : None
*******************************************************************************/
void DMA_ClearITPendingBit(u32 DMA_IT)
{
/* Check the parameters */
assert_param(IS_DMA_CLEAR_IT(DMA_IT));
/* Calculate the used DMA */
if ((DMA_IT & FLAG_Mask) != (u32)RESET)
{
/* Clear the selected DMA interrupt pending bits */
DMA2->IFCR = DMA_IT;
}
else
{
/* Clear the selected DMA interrupt pending bits */
DMA1->IFCR = DMA_IT;
}
}
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

219
bsp/stm32f103vb_lwip/library/src/stm32f10x_exti.c Normal file
View File

@ -0,0 +1,219 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_exti.c
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file provides all the EXTI firmware functions.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_exti.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define EXTI_LineNone ((u32)0x00000) /* No interrupt selected */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : EXTI_DeInit
* Description : Deinitializes the EXTI peripheral registers to their default
* reset values.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void EXTI_DeInit(void)
{
EXTI->IMR = 0x00000000;
EXTI->EMR = 0x00000000;
EXTI->RTSR = 0x00000000;
EXTI->FTSR = 0x00000000;
EXTI->PR = 0x0007FFFF;
}
/*******************************************************************************
* Function Name : EXTI_Init
* Description : Initializes the EXTI peripheral according to the specified
* parameters in the EXTI_InitStruct.
* Input : - EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
* that contains the configuration information for the EXTI
* peripheral.
* Output : None
* Return : None
*******************************************************************************/
void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
{
/* Check the parameters */
assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));
assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
{
/* Clear EXTI line configuration */
EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;
EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
*(vu32 *)(EXTI_BASE + (u32)EXTI_InitStruct->EXTI_Mode)|= EXTI_InitStruct->EXTI_Line;
/* Clear Rising Falling edge configuration */
EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
/* Select the trigger for the selected external interrupts */
if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
{
/* Rising Falling edge */
EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
}
else
{
*(vu32 *)(EXTI_BASE + (u32)EXTI_InitStruct->EXTI_Trigger)|= EXTI_InitStruct->EXTI_Line;
}
}
else
{
/* Disable the selected external lines */
*(vu32 *)(EXTI_BASE + (u32)EXTI_InitStruct->EXTI_Mode)&= ~EXTI_InitStruct->EXTI_Line;
}
}
/*******************************************************************************
* Function Name : EXTI_StructInit
* Description : Fills each EXTI_InitStruct member with its reset value.
* Input : - EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
* which will be initialized.
* Output : None
* Return : None
*******************************************************************************/
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
{
EXTI_InitStruct->EXTI_Line = EXTI_LineNone;
EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
EXTI_InitStruct->EXTI_LineCmd = DISABLE;
}
/*******************************************************************************
* Function Name : EXTI_GenerateSWInterrupt
* Description : Generates a Software interrupt.
* Input : - EXTI_Line: specifies the EXTI lines to be enabled or
* disabled.
* This parameter can be any combination of EXTI_Linex where
* x can be (0..18).
* Output : None
* Return : None
*******************************************************************************/
void EXTI_GenerateSWInterrupt(u32 EXTI_Line)
{
/* Check the parameters */
assert_param(IS_EXTI_LINE(EXTI_Line));
EXTI->SWIER |= EXTI_Line;
}
/*******************************************************************************
* Function Name : EXTI_GetFlagStatus
* Description : Checks whether the specified EXTI line flag is set or not.
* Input : - EXTI_Line: specifies the EXTI line flag to check.
* This parameter can be:
* - EXTI_Linex: External interrupt line x where x(0..18)
* Output : None
* Return : The new state of EXTI_Line (SET or RESET).
*******************************************************************************/
FlagStatus EXTI_GetFlagStatus(u32 EXTI_Line)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_GET_EXTI_LINE(EXTI_Line));
if ((EXTI->PR & EXTI_Line) != (u32)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*******************************************************************************
* Function Name : EXTI_ClearFlag
* Description : Clears the EXTI’s line pending flags.
* Input : - EXTI_Line: specifies the EXTI lines flags to clear.
* This parameter can be any combination of EXTI_Linex where
* x can be (0..18).
* Output : None
* Return : None
*******************************************************************************/
void EXTI_ClearFlag(u32 EXTI_Line)
{
/* Check the parameters */
assert_param(IS_EXTI_LINE(EXTI_Line));
EXTI->PR = EXTI_Line;
}
/*******************************************************************************
* Function Name : EXTI_GetITStatus
* Description : Checks whether the specified EXTI line is asserted or not.
* Input : - EXTI_Line: specifies the EXTI line to check.
* This parameter can be:
* - EXTI_Linex: External interrupt line x where x(0..18)
* Output : None
* Return : The new state of EXTI_Line (SET or RESET).
*******************************************************************************/
ITStatus EXTI_GetITStatus(u32 EXTI_Line)
{
ITStatus bitstatus = RESET;
u32 enablestatus = 0;
/* Check the parameters */
assert_param(IS_GET_EXTI_LINE(EXTI_Line));
enablestatus = EXTI->IMR & EXTI_Line;
if (((EXTI->PR & EXTI_Line) != (u32)RESET) && (enablestatus != (u32)RESET))
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*******************************************************************************
* Function Name : EXTI_ClearITPendingBit
* Description : Clears the EXTI’s line pending bits.
* Input : - EXTI_Line: specifies the EXTI lines to clear.
* This parameter can be any combination of EXTI_Linex where
* x can be (0..18).
* Output : None
* Return : None
*******************************************************************************/
void EXTI_ClearITPendingBit(u32 EXTI_Line)
{
/* Check the parameters */
assert_param(IS_EXTI_LINE(EXTI_Line));
EXTI->PR = EXTI_Line;
}
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

919
bsp/stm32f103vb_lwip/library/src/stm32f10x_flash.c Normal file
View File

@ -0,0 +1,919 @@
/******************** (C) COPYRIGHT 2009 STMicroelectronics ********************
* File Name : stm32f10x_flash.c
* Author : MCD Application Team
* Version : V2.0.3Patch1
* Date : 04/06/2009
* Description : This file provides all the FLASH firmware functions.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_flash.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Flash Access Control Register bits */
#define ACR_LATENCY_Mask ((u32)0x00000038)
#define ACR_HLFCYA_Mask ((u32)0xFFFFFFF7)
#define ACR_PRFTBE_Mask ((u32)0xFFFFFFEF)
#ifdef _FLASH_PROG
/* Flash Access Control Register bits */
#define ACR_PRFTBS_Mask ((u32)0x00000020)
/* Flash Control Register bits */
#define CR_PG_Set ((u32)0x00000001)
#define CR_PG_Reset ((u32)0x00001FFE)
#define CR_PER_Set ((u32)0x00000002)
#define CR_PER_Reset ((u32)0x00001FFD)
#define CR_MER_Set ((u32)0x00000004)
#define CR_MER_Reset ((u32)0x00001FFB)
#define CR_OPTPG_Set ((u32)0x00000010)
#define CR_OPTPG_Reset ((u32)0x00001FEF)
#define CR_OPTER_Set ((u32)0x00000020)
#define CR_OPTER_Reset ((u32)0x00001FDF)
#define CR_STRT_Set ((u32)0x00000040)
#define CR_LOCK_Set ((u32)0x00000080)
/* FLASH Mask */
#define RDPRT_Mask ((u32)0x00000002)
#define WRP0_Mask ((u32)0x000000FF)
#define WRP1_Mask ((u32)0x0000FF00)
#define WRP2_Mask ((u32)0x00FF0000)
#define WRP3_Mask ((u32)0xFF000000)
/* FLASH Keys */
#define RDP_Key ((u16)0x00A5)
#define FLASH_KEY1 ((u32)0x45670123)
#define FLASH_KEY2 ((u32)0xCDEF89AB)
/* Delay definition */
#define EraseTimeout ((u32)0x00000FFF)
#define ProgramTimeout ((u32)0x0000000F)
#endif
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
#ifdef _FLASH_PROG
static void delay(void);
#endif
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : FLASH_SetLatency
* Description : Sets the code latency value.
* Input : - FLASH_Latency: specifies the FLASH Latency value.
* This parameter can be one of the following values:
* - FLASH_Latency_0: FLASH Zero Latency cycle
* - FLASH_Latency_1: FLASH One Latency cycle
* - FLASH_Latency_2: FLASH Two Latency cycles
* Output : None
* Return : None
*******************************************************************************/
void FLASH_SetLatency(u32 FLASH_Latency)
{
u32 tmpreg = 0;
/* Check the parameters */
assert_param(IS_FLASH_LATENCY(FLASH_Latency));
/* Read the ACR register */
tmpreg = FLASH->ACR;
/* Sets the Latency value */
tmpreg &= ACR_LATENCY_Mask;
tmpreg |= FLASH_Latency;
/* Write the ACR register */
FLASH->ACR = tmpreg;
}
/*******************************************************************************
* Function Name : FLASH_HalfCycleAccessCmd
* Description : Enables or disables the Half cycle flash access.
* Input : - FLASH_HalfCycle: specifies the FLASH Half cycle Access mode.
* This parameter can be one of the following values:
* - FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable
* - FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable
* Output : None
* Return : None
*******************************************************************************/
void FLASH_HalfCycleAccessCmd(u32 FLASH_HalfCycleAccess)
{
/* Check the parameters */
assert_param(IS_FLASH_HALFCYCLEACCESS_STATE(FLASH_HalfCycleAccess));
/* Enable or disable the Half cycle access */
FLASH->ACR &= ACR_HLFCYA_Mask;
FLASH->ACR |= FLASH_HalfCycleAccess;
}
/*******************************************************************************
* Function Name : FLASH_PrefetchBufferCmd
* Description : Enables or disables the Prefetch Buffer.
* Input : - FLASH_PrefetchBuffer: specifies the Prefetch buffer status.
* This parameter can be one of the following values:
* - FLASH_PrefetchBuffer_Enable: FLASH Prefetch Buffer Enable
* - FLASH_PrefetchBuffer_Disable: FLASH Prefetch Buffer Disable
* Output : None
* Return : None
*******************************************************************************/
void FLASH_PrefetchBufferCmd(u32 FLASH_PrefetchBuffer)
{
/* Check the parameters */
assert_param(IS_FLASH_PREFETCHBUFFER_STATE(FLASH_PrefetchBuffer));
/* Enable or disable the Prefetch Buffer */
FLASH->ACR &= ACR_PRFTBE_Mask;
FLASH->ACR |= FLASH_PrefetchBuffer;
}
#ifdef _FLASH_PROG
/*******************************************************************************
* Function Name : FLASH_Unlock
* Description : Unlocks the FLASH Program Erase Controller.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void FLASH_Unlock(void)
{
/* Authorize the FPEC Access */
FLASH->KEYR = FLASH_KEY1;
FLASH->KEYR = FLASH_KEY2;
}
/*******************************************************************************
* Function Name : FLASH_Lock
* Description : Locks the FLASH Program Erase Controller.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void FLASH_Lock(void)
{
/* Set the Lock Bit to lock the FPEC and the FCR */
FLASH->CR |= CR_LOCK_Set;
}
/*******************************************************************************
* Function Name : FLASH_ErasePage
* Description : Erases a specified FLASH page.
* Input : - Page_Address: The page address to be erased.
* Output : None
* Return : FLASH Status: The returned value can be: FLASH_BUSY,
* FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or
* FLASH_TIMEOUT.
*******************************************************************************/
FLASH_Status FLASH_ErasePage(u32 Page_Address)
{
FLASH_Status status = FLASH_COMPLETE;
/* Check the parameters */
assert_param(IS_FLASH_ADDRESS(Page_Address));
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(EraseTimeout);
if(status == FLASH_COMPLETE)
{
/* if the previous operation is completed, proceed to erase the page */
FLASH->CR|= CR_PER_Set;
FLASH->AR = Page_Address;
FLASH->CR|= CR_STRT_Set;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(EraseTimeout);
if(status != FLASH_BUSY)
{
/* if the erase operation is completed, disable the PER Bit */
FLASH->CR &= CR_PER_Reset;
}
}
/* Return the Erase Status */
return status;
}
/*******************************************************************************
* Function Name : FLASH_EraseAllPages
* Description : Erases all FLASH pages.
* Input : None
* Output : None
* Return : FLASH Status: The returned value can be: FLASH_BUSY,
* FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or
* FLASH_TIMEOUT.
*******************************************************************************/
FLASH_Status FLASH_EraseAllPages(void)
{
FLASH_Status status = FLASH_COMPLETE;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(EraseTimeout);
if(status == FLASH_COMPLETE)
{
/* if the previous operation is completed, proceed to erase all pages */
FLASH->CR |= CR_MER_Set;
FLASH->CR |= CR_STRT_Set;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(EraseTimeout);
if(status != FLASH_BUSY)
{
/* if the erase operation is completed, disable the MER Bit */
FLASH->CR &= CR_MER_Reset;
}
}
/* Return the Erase Status */
return status;
}
/*******************************************************************************
* Function Name : FLASH_EraseOptionBytes
* Description : Erases the FLASH option bytes.
* Input : None
* Output : None
* Return : FLASH Status: The returned value can be: FLASH_BUSY,
* FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or
* FLASH_TIMEOUT.
*******************************************************************************/
FLASH_Status FLASH_EraseOptionBytes(void)
{
FLASH_Status status = FLASH_COMPLETE;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(EraseTimeout);
if(status == FLASH_COMPLETE)
{
/* Authorize the small information block programming */
FLASH->OPTKEYR = FLASH_KEY1;
FLASH->OPTKEYR = FLASH_KEY2;
/* if the previous operation is completed, proceed to erase the option bytes */
FLASH->CR |= CR_OPTER_Set;
FLASH->CR |= CR_STRT_Set;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(EraseTimeout);
if(status == FLASH_COMPLETE)
{
/* if the erase operation is completed, disable the OPTER Bit */
FLASH->CR &= CR_OPTER_Reset;
/* Enable the Option Bytes Programming operation */
FLASH->CR |= CR_OPTPG_Set;
/* Enable the readout access */
OB->RDP= RDP_Key;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(ProgramTimeout);
if(status != FLASH_BUSY)
{
/* if the program operation is completed, disable the OPTPG Bit */
FLASH->CR &= CR_OPTPG_Reset;
}
}
else
{
if (status != FLASH_BUSY)
{
/* Disable the OPTPG Bit */
FLASH->CR &= CR_OPTPG_Reset;
}
}
}
/* Return the erase status */
return status;
}
/*******************************************************************************
* Function Name : FLASH_ProgramWord
* Description : Programs a word at a specified address.
* Input : - Address: specifies the address to be programmed.
* - Data: specifies the data to be programmed.
* Output : None
* Return : FLASH Status: The returned value can be: FLASH_BUSY,
* FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or
* FLASH_TIMEOUT.
*******************************************************************************/
FLASH_Status FLASH_ProgramWord(u32 Address, u32 Data)
{
FLASH_Status status = FLASH_COMPLETE;
/* Check the parameters */
assert_param(IS_FLASH_ADDRESS(Address));
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(ProgramTimeout);
if(status == FLASH_COMPLETE)
{
/* if the previous operation is completed, proceed to program the new first
half word */
FLASH->CR |= CR_PG_Set;
*(vu16*)Address = (u16)Data;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(ProgramTimeout);
if(status == FLASH_COMPLETE)
{
/* if the previous operation is completed, proceed to program the new second
half word */
*(vu16*)(Address + 2) = Data >> 16;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(ProgramTimeout);
if(status != FLASH_BUSY)
{
/* Disable the PG Bit */
FLASH->CR &= CR_PG_Reset;
}
}
else
{
if (status != FLASH_BUSY)
{
/* Disable the PG Bit */
FLASH->CR &= CR_PG_Reset;
}
}
}
/* Return the Program Status */
return status;
}
/*******************************************************************************
* Function Name : FLASH_ProgramHalfWord
* Description : Programs a half word at a specified address.
* Input : - Address: specifies the address to be programmed.
* - Data: specifies the data to be programmed.
* Output : None
* Return : FLASH Status: The returned value can be: FLASH_BUSY,
* FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or
* FLASH_TIMEOUT.
*******************************************************************************/
FLASH_Status FLASH_ProgramHalfWord(u32 Address, u16 Data)
{
FLASH_Status status = FLASH_COMPLETE;
/* Check the parameters */
assert_param(IS_FLASH_ADDRESS(Address));
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(ProgramTimeout);
if(status == FLASH_COMPLETE)
{
/* if the previous operation is completed, proceed to program the new data */
FLASH->CR |= CR_PG_Set;
*(vu16*)Address = Data;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(ProgramTimeout);
if(status != FLASH_BUSY)
{
/* if the program operation is completed, disable the PG Bit */
FLASH->CR &= CR_PG_Reset;
}
}
/* Return the Program Status */
return status;
}
/*******************************************************************************
* Function Name : FLASH_ProgramOptionByteData
* Description : Programs a half word at a specified Option Byte Data address.
* Input : - Address: specifies the address to be programmed.
* This parameter can be 0x1FFFF804 or 0x1FFFF806.
* - Data: specifies the data to be programmed.
* Output : None
* Return : FLASH Status: The returned value can be: FLASH_BUSY,
* FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or
* FLASH_TIMEOUT.
*******************************************************************************/
FLASH_Status FLASH_ProgramOptionByteData(u32 Address, u8 Data)
{
FLASH_Status status = FLASH_COMPLETE;
/* Check the parameters */
assert_param(IS_OB_DATA_ADDRESS(Address));
status = FLASH_WaitForLastOperation(ProgramTimeout);
if(status == FLASH_COMPLETE)
{
/* Authorize the small information block programming */
FLASH->OPTKEYR = FLASH_KEY1;
FLASH->OPTKEYR = FLASH_KEY2;
/* Enables the Option Bytes Programming operation */
FLASH->CR |= CR_OPTPG_Set;
*(vu16*)Address = Data;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(ProgramTimeout);
if(status != FLASH_BUSY)
{
/* if the program operation is completed, disable the OPTPG Bit */
FLASH->CR &= CR_OPTPG_Reset;
}
}
/* Return the Option Byte Data Program Status */
return status;
}
/*******************************************************************************
* Function Name : FLASH_EnableWriteProtection
* Description : Write protects the desired pages
* Input : - FLASH_Pages: specifies the address of the pages to be
* write protected. This parameter can be:
* - For STM32F10Xxx Medium-density devices (FLASH page size equal to 1 KB)
* - A value between FLASH_WRProt_Pages0to3 and
* FLASH_WRProt_Pages124to127
* - For STM32F10Xxx High-density devices (FLASH page size equal to 2 KB)
* - A value between FLASH_WRProt_Pages0to1 and
* FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to255
* - FLASH_WRProt_AllPages
* Output : None
* Return : FLASH Status: The returned value can be: FLASH_BUSY,
* FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or
* FLASH_TIMEOUT.
*******************************************************************************/
FLASH_Status FLASH_EnableWriteProtection(u32 FLASH_Pages)
{
u16 WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;
FLASH_Status status = FLASH_COMPLETE;
/* Check the parameters */
assert_param(IS_FLASH_WRPROT_PAGE(FLASH_Pages));
FLASH_Pages = (u32)(~FLASH_Pages);
WRP0_Data = (vu16)(FLASH_Pages & WRP0_Mask);
WRP1_Data = (vu16)((FLASH_Pages & WRP1_Mask) >> 8);
WRP2_Data = (vu16)((FLASH_Pages & WRP2_Mask) >> 16);
WRP3_Data = (vu16)((FLASH_Pages & WRP3_Mask) >> 24);
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(ProgramTimeout);
if(status == FLASH_COMPLETE)
{
/* Authorizes the small information block programming */
FLASH->OPTKEYR = FLASH_KEY1;
FLASH->OPTKEYR = FLASH_KEY2;
FLASH->CR |= CR_OPTPG_Set;
if(WRP0_Data != 0xFF)
{
OB->WRP0 = WRP0_Data;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(ProgramTimeout);
}
if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF))
{
OB->WRP1 = WRP1_Data;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(ProgramTimeout);
}
if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF))
{
OB->WRP2 = WRP2_Data;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(ProgramTimeout);
}
if((status == FLASH_COMPLETE)&& (WRP3_Data != 0xFF))
{
OB->WRP3 = WRP3_Data;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(ProgramTimeout);
}
if(status != FLASH_BUSY)
{
/* if the program operation is completed, disable the OPTPG Bit */
FLASH->CR &= CR_OPTPG_Reset;
}
}
/* Return the write protection operation Status */
return status;
}
/*******************************************************************************
* Function Name : FLASH_ReadOutProtection
* Description : Enables or disables the read out protection.
* If the user has already programmed the other option bytes before
* calling this function, he must re-program them since this
* function erases all option bytes.
* Input : - Newstate: new state of the ReadOut Protection.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : FLASH Status: The returned value can be: FLASH_BUSY,
* FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or
* FLASH_TIMEOUT.
*******************************************************************************/
FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState)
{
FLASH_Status status = FLASH_COMPLETE;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
status = FLASH_WaitForLastOperation(EraseTimeout);
if(status == FLASH_COMPLETE)
{
/* Authorizes the small information block programming */
FLASH->OPTKEYR = FLASH_KEY1;
FLASH->OPTKEYR = FLASH_KEY2;
FLASH->CR |= CR_OPTER_Set;
FLASH->CR |= CR_STRT_Set;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(EraseTimeout);
if(status == FLASH_COMPLETE)
{
/* if the erase operation is completed, disable the OPTER Bit */
FLASH->CR &= CR_OPTER_Reset;
/* Enable the Option Bytes Programming operation */
FLASH->CR |= CR_OPTPG_Set;
if(NewState != DISABLE)
{
OB->RDP = 0x00;
}
else
{
OB->RDP = RDP_Key;
}
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(EraseTimeout);
if(status != FLASH_BUSY)
{
/* if the program operation is completed, disable the OPTPG Bit */
FLASH->CR &= CR_OPTPG_Reset;
}
}
else
{
if(status != FLASH_BUSY)
{
/* Disable the OPTER Bit */
FLASH->CR &= CR_OPTER_Reset;
}
}
}
/* Return the protection operation Status */
return status;
}
/*******************************************************************************
* Function Name : FLASH_UserOptionByteConfig
* Description : Programs the FLASH User Option Byte: IWDG_SW / RST_STOP /
* RST_STDBY.
* Input : - OB_IWDG: Selects the IWDG mode
* This parameter can be one of the following values:
* - OB_IWDG_SW: Software IWDG selected
* - OB_IWDG_HW: Hardware IWDG selected
* - OB_STOP: Reset event when entering STOP mode.
* This parameter can be one of the following values:
* - OB_STOP_NoRST: No reset generated when entering in STOP
* - OB_STOP_RST: Reset generated when entering in STOP
* - OB_STDBY: Reset event when entering Standby mode.
* This parameter can be one of the following values:
* - OB_STDBY_NoRST: No reset generated when entering in STANDBY
* - OB_STDBY_RST: Reset generated when entering in STANDBY
* Output : None
* Return : FLASH Status: The returned value can be: FLASH_BUSY,
* FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or
* FLASH_TIMEOUT.
*******************************************************************************/
FLASH_Status FLASH_UserOptionByteConfig(u16 OB_IWDG, u16 OB_STOP, u16 OB_STDBY)
{
FLASH_Status status = FLASH_COMPLETE;
/* Check the parameters */
assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
assert_param(IS_OB_STOP_SOURCE(OB_STOP));
assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
/* Authorize the small information block programming */
FLASH->OPTKEYR = FLASH_KEY1;
FLASH->OPTKEYR = FLASH_KEY2;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(ProgramTimeout);
if(status == FLASH_COMPLETE)
{
/* Enable the Option Bytes Programming operation */
FLASH->CR |= CR_OPTPG_Set;
OB->USER = ( OB_IWDG | OB_STOP |OB_STDBY) | (u16)0xF8;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(ProgramTimeout);
if(status != FLASH_BUSY)
{
/* if the program operation is completed, disable the OPTPG Bit */
FLASH->CR &= CR_OPTPG_Reset;
}
}
/* Return the Option Byte program Status */
return status;
}
/*******************************************************************************
* Function Name : FLASH_GetUserOptionByte
* Description : Returns the FLASH User Option Bytes values.
* Input : None
* Output : None
* Return : The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1)
* and RST_STDBY(Bit2).
*******************************************************************************/
u32 FLASH_GetUserOptionByte(void)
{
/* Return the User Option Byte */
return (u32)(FLASH->OBR >> 2);
}
/*******************************************************************************
* Function Name : FLASH_GetWriteProtectionOptionByte
* Description : Returns the FLASH Write Protection Option Bytes Register value.
* Input : None
* Output : None
* Return : The FLASH Write Protection Option Bytes Register value
*******************************************************************************/
u32 FLASH_GetWriteProtectionOptionByte(void)
{
/* Return the Falsh write protection Register value */
return (u32)(FLASH->WRPR);
}
/*******************************************************************************
* Function Name : FLASH_GetReadOutProtectionStatus
* Description : Checks whether the FLASH Read Out Protection Status is set
* or not.
* Input : None
* Output : None
* Return : FLASH ReadOut Protection Status(SET or RESET)
*******************************************************************************/
FlagStatus FLASH_GetReadOutProtectionStatus(void)
{
FlagStatus readoutstatus = RESET;
if ((FLASH->OBR & RDPRT_Mask) != (u32)RESET)
{
readoutstatus = SET;
}
else
{
readoutstatus = RESET;
}
return readoutstatus;
}
/*******************************************************************************
* Function Name : FLASH_GetPrefetchBufferStatus
* Description : Checks whether the FLASH Prefetch Buffer status is set or not.
* Input : None
* Output : None
* Return : FLASH Prefetch Buffer Status (SET or RESET).
*******************************************************************************/
FlagStatus FLASH_GetPrefetchBufferStatus(void)
{
FlagStatus bitstatus = RESET;
if ((FLASH->ACR & ACR_PRFTBS_Mask) != (u32)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
/* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */
return bitstatus;
}
/*******************************************************************************
* Function Name : FLASH_ITConfig
* Description : Enables or disables the specified FLASH interrupts.
* Input : - FLASH_IT: specifies the FLASH interrupt sources to be
* enabled or disabled.
* This parameter can be any combination of the following values:
* - FLASH_IT_ERROR: FLASH Error Interrupt
* - FLASH_IT_EOP: FLASH end of operation Interrupt
* Output : None
* Return : None
*******************************************************************************/
void FLASH_ITConfig(u16 FLASH_IT, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FLASH_IT(FLASH_IT));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if(NewState != DISABLE)
{
/* Enable the interrupt sources */
FLASH->CR |= FLASH_IT;
}
else
{
/* Disable the interrupt sources */
FLASH->CR &= ~(u32)FLASH_IT;
}
}
/*******************************************************************************
* Function Name : FLASH_GetFlagStatus
* Description : Checks whether the specified FLASH flag is set or not.
* Input : - FLASH_FLAG: specifies the FLASH flag to check.
* This parameter can be one of the following values:
* - FLASH_FLAG_BSY: FLASH Busy flag
* - FLASH_FLAG_PGERR: FLASH Program error flag
* - FLASH_FLAG_WRPRTERR: FLASH Write protected error flag
* - FLASH_FLAG_EOP: FLASH End of Operation flag
* - FLASH_FLAG_OPTERR: FLASH Option Byte error flag
* Output : None
* Return : The new state of FLASH_FLAG (SET or RESET).
*******************************************************************************/
FlagStatus FLASH_GetFlagStatus(u16 FLASH_FLAG)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ;
if(FLASH_FLAG == FLASH_FLAG_OPTERR)
{
if((FLASH->OBR & FLASH_FLAG_OPTERR) != (u32)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
}
else
{
if((FLASH->SR & FLASH_FLAG) != (u32)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
}
/* Return the new state of FLASH_FLAG (SET or RESET) */
return bitstatus;
}
/*******************************************************************************
* Function Name : FLASH_ClearFlag
* Description : Clears the FLASH’s pending flags.
* Input : - FLASH_FLAG: specifies the FLASH flags to clear.
* This parameter can be any combination of the following values:
* - FLASH_FLAG_BSY: FLASH Busy flag
* - FLASH_FLAG_PGERR: FLASH Program error flag
* - FLASH_FLAG_WRPRTERR: FLASH Write protected error flag
* - FLASH_FLAG_EOP: FLASH End of Operation flag
* Output : None
* Return : None
*******************************************************************************/
void FLASH_ClearFlag(u16 FLASH_FLAG)
{
/* Check the parameters */
assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ;
/* Clear the flags */
FLASH->SR = FLASH_FLAG;
}
/*******************************************************************************
* Function Name : FLASH_GetStatus
* Description : Returns the FLASH Status.
* Input : None
* Output : None
* Return : FLASH Status: The returned value can be: FLASH_BUSY,
* FLASH_ERROR_PG, FLASH_ERROR_WRP or FLASH_COMPLETE
*******************************************************************************/
FLASH_Status FLASH_GetStatus(void)
{
FLASH_Status flashstatus = FLASH_COMPLETE;
if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY)
{
flashstatus = FLASH_BUSY;
}
else
{
if(FLASH->SR & FLASH_FLAG_PGERR)
{
flashstatus = FLASH_ERROR_PG;
}
else
{
if(FLASH->SR & FLASH_FLAG_WRPRTERR)
{
flashstatus = FLASH_ERROR_WRP;
}
else
{
flashstatus = FLASH_COMPLETE;
}
}
}
/* Return the Flash Status */
return flashstatus;
}
/*******************************************************************************
* Function Name : FLASH_WaitForLastOperation
* Description : Waits for a Flash operation to complete or a TIMEOUT to occur.
* Input : - Timeout: FLASH progamming Timeout
* Output : None
* Return : FLASH Status: The returned value can be: FLASH_BUSY,
* FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or
* FLASH_TIMEOUT.
*******************************************************************************/
FLASH_Status FLASH_WaitForLastOperation(u32 Timeout)
{
FLASH_Status status = FLASH_COMPLETE;
/* Check for the Flash Status */
status = FLASH_GetStatus();
/* Wait for a Flash operation to complete or a TIMEOUT to occur */
while((status == FLASH_BUSY) && (Timeout != 0x00))
{
delay();
status = FLASH_GetStatus();
Timeout--;
}
if(Timeout == 0x00 )
{
status = FLASH_TIMEOUT;
}
/* Return the operation status */
return status;
}
/*******************************************************************************
* Function Name : delay
* Description : Inserts a time delay.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
static void delay(void)
{
vu32 i = 0;
for(i = 0xFF; i != 0; i--)
{
}
}
#endif
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

851
bsp/stm32f103vb_lwip/library/src/stm32f10x_fsmc.c Normal file
View File

@ -0,0 +1,851 @@
/******************** (C) COPYRIGHT 2009 STMicroelectronics ********************
* File Name : stm32f10x_fsmc.c
* Author : MCD Application Team
* Version : V2.0.3Patch1
* Date : 04/06/2009
* Description : This file provides all the FSMC firmware functions.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_fsmc.h"
#include "stm32f10x_rcc.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* --------------------- FSMC registers bit mask ---------------------------- */
/* FSMC BCRx Mask */
#define BCR_MBKEN_Set ((u32)0x00000001)
#define BCR_MBKEN_Reset ((u32)0x000FFFFE)
#define BCR_FACCEN_Set ((u32)0x00000040)
/* FSMC PCRx Mask */
#define PCR_PBKEN_Set ((u32)0x00000004)
#define PCR_PBKEN_Reset ((u32)0x000FFFFB)
#define PCR_ECCEN_Set ((u32)0x00000040)
#define PCR_ECCEN_Reset ((u32)0x000FFFBF)
#define PCR_MemoryType_NAND ((u32)0x00000008)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : FSMC_NORSRAMDeInit
* Description : Deinitializes the FSMC NOR/SRAM Banks registers to their default
* reset values.
* Input : - FSMC_Bank: specifies the FSMC Bank to be used
* This parameter can be one of the following values:
* - FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
* - FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
* - FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
* - FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
* Output : None
* Return : None
*******************************************************************************/
void FSMC_NORSRAMDeInit(u32 FSMC_Bank)
{
/* Check the parameter */
assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
/* FSMC_Bank1_NORSRAM1 */
if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
{
FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;
}
/* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */
else
{
FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2;
}
FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;
}
/*******************************************************************************
* Function Name : FSMC_NANDDeInit
* Description : Deinitializes the FSMC NAND Banks registers to their default
* reset values.
* Input : - FSMC_Bank: specifies the FSMC Bank to be used
* This parameter can be one of the following values:
* - FSMC_Bank2_NAND: FSMC Bank2 NAND
* - FSMC_Bank3_NAND: FSMC Bank3 NAND
* Output : None
* Return : None
*******************************************************************************/
void FSMC_NANDDeInit(u32 FSMC_Bank)
{
/* Check the parameter */
assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
if(FSMC_Bank == FSMC_Bank2_NAND)
{
/* Set the FSMC_Bank2 registers to their reset values */
FSMC_Bank2->PCR2 = 0x00000018;
FSMC_Bank2->SR2 = 0x00000040;
FSMC_Bank2->PMEM2 = 0xFCFCFCFC;
FSMC_Bank2->PATT2 = 0xFCFCFCFC;
}
/* FSMC_Bank3_NAND */
else
{
/* Set the FSMC_Bank3 registers to their reset values */
FSMC_Bank3->PCR3 = 0x00000018;
FSMC_Bank3->SR3 = 0x00000040;
FSMC_Bank3->PMEM3 = 0xFCFCFCFC;
FSMC_Bank3->PATT3 = 0xFCFCFCFC;
}
}
/*******************************************************************************
* Function Name : FSMC_PCCARDDeInit
* Description : Deinitializes the FSMC PCCARD Bank registers to their default
* reset values.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void FSMC_PCCARDDeInit(void)
{
/* Set the FSMC_Bank4 registers to their reset values */
FSMC_Bank4->PCR4 = 0x00000018;
FSMC_Bank4->SR4 = 0x00000000;
FSMC_Bank4->PMEM4 = 0xFCFCFCFC;
FSMC_Bank4->PATT4 = 0xFCFCFCFC;
FSMC_Bank4->PIO4 = 0xFCFCFCFC;
}
/*******************************************************************************
* Function Name : FSMC_NORSRAMInit
* Description : Initializes the FSMC NOR/SRAM Banks according to the
* specified parameters in the FSMC_NORSRAMInitStruct.
* Input : - FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef
* structure that contains the configuration information for
* the FSMC NOR/SRAM specified Banks.
* Output : None
* Return : None
*******************************************************************************/
void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
{
/* Check the parameters */
assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));
assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode));
/* Bank1 NOR/SRAM control register configuration */
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
(u32)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
FSMC_NORSRAMInitStruct->FSMC_MemoryType |
FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
FSMC_NORSRAMInitStruct->FSMC_WrapMode |
FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
{
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (u32)BCR_FACCEN_Set;
}
/* Bank1 NOR/SRAM timing register configuration */
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] =
(u32)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
/* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
{
assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
(u32)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
}
else
{
FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
}
}
/*******************************************************************************
* Function Name : FSMC_NANDInit
* Description : Initializes the FSMC NAND Banks according to the specified
* parameters in the FSMC_NANDInitStruct.
* Input : - FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef
* structure that contains the configuration information for
* the FSMC NAND specified Banks.
* Output : None
* Return : None
*******************************************************************************/
void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
{
u32 tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
/* Check the parameters */
assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));
assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));
assert_param( IS_FSMC_DATA_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));
assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));
assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));
assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));
assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));
assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
/* Set the tmppcr value according to FSMC_NANDInitStruct parameters */
tmppcr = (u32)FSMC_NANDInitStruct->FSMC_Waitfeature |
PCR_MemoryType_NAND |
FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
FSMC_NANDInitStruct->FSMC_ECC |
FSMC_NANDInitStruct->FSMC_ECCPageSize |
(FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|
(FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
/* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */
tmppmem = (u32)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
/* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */
tmppatt = (u32)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
{
/* FSMC_Bank2_NAND registers configuration */
FSMC_Bank2->PCR2 = tmppcr;
FSMC_Bank2->PMEM2 = tmppmem;
FSMC_Bank2->PATT2 = tmppatt;
}
else
{
/* FSMC_Bank3_NAND registers configuration */
FSMC_Bank3->PCR3 = tmppcr;
FSMC_Bank3->PMEM3 = tmppmem;
FSMC_Bank3->PATT3 = tmppatt;
}
}
/*******************************************************************************
* Function Name : FSMC_PCCARDInit
* Description : Initializes the FSMC PCCARD Bank according to the specified
* parameters in the FSMC_PCCARDInitStruct.
* Input : - FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef
* structure that contains the configuration information for
* the FSMC PCCARD Bank.
* Output : None
* Return : None
*******************************************************************************/
void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
{
/* Check the parameters */
assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));
assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));
assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));
assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime));
assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime));
assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));
assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));
/* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */
FSMC_Bank4->PCR4 = (u32)FSMC_PCCARDInitStruct->FSMC_Waitfeature |
FSMC_MemoryDataWidth_16b |
(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |
(FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);
/* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */
FSMC_Bank4->PMEM4 = (u32)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
/* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */
FSMC_Bank4->PATT4 = (u32)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
/* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */
FSMC_Bank4->PIO4 = (u32)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |
(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24);
}
/*******************************************************************************
* Function Name : FSMC_NORSRAMStructInit
* Description : Fills each FSMC_NORSRAMInitStruct member with its default value.
* Input : - FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef
* structure which will be initialized.
* Output : None
* Return : None
*******************************************************************************/
void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
{
/* Reset NOR/SRAM Init structure parameters values */
FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
}
/*******************************************************************************
* Function Name : FSMC_NANDStructInit
* Description : Fills each FSMC_NANDInitStruct member with its default value.
* Input : - FSMC_NORSRAMInitStruct: pointer to a FSMC_NANDInitTypeDef
* structure which will be initialized.
* Output : None
* Return : None
*******************************************************************************/
void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
{
/* Reset NAND Init structure parameters values */
FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;
FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;
FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;
FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;
FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;
FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
}
/*******************************************************************************
* Function Name : FSMC_PCCARDStructInit
* Description : Fills each FSMC_PCCARDInitStruct member with its default value.
* Input : - FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef
* structure which will be initialized.
* Output : None
* Return : None
*******************************************************************************/
void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
{
/* Reset PCCARD Init structure parameters values */
FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;
FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;
FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;
FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
}
/*******************************************************************************
* Function Name : FSMC_NORSRAMCmd
* Description : Enables or disables the specified NOR/SRAM Memory Bank.
* Input : - FSMC_Bank: specifies the FSMC Bank to be used
* This parameter can be one of the following values:
* - FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
* - FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
* - FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
* - FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
* : - NewState: new state of the FSMC_Bank.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void FSMC_NORSRAMCmd(u32 FSMC_Bank, FunctionalState NewState)
{
assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set;
}
else
{
/* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset;
}
}
/*******************************************************************************
* Function Name : FSMC_NANDCmd
* Description : Enables or disables the specified NAND Memory Bank.
* Input : - FSMC_Bank: specifies the FSMC Bank to be used
* This parameter can be one of the following values:
* - FSMC_Bank2_NAND: FSMC Bank2 NAND
* - FSMC_Bank3_NAND: FSMC Bank3 NAND
* : - NewState: new state of the FSMC_Bank.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void FSMC_NANDCmd(u32 FSMC_Bank, FunctionalState NewState)
{
assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
if(FSMC_Bank == FSMC_Bank2_NAND)
{
FSMC_Bank2->PCR2 |= PCR_PBKEN_Set;
}
else
{
FSMC_Bank3->PCR3 |= PCR_PBKEN_Set;
}
}
else
{
/* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
if(FSMC_Bank == FSMC_Bank2_NAND)
{
FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset;
}
else
{
FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset;
}
}
}
/*******************************************************************************
* Function Name : FSMC_PCCARDCmd
* Description : Enables or disables the PCCARD Memory Bank.
* Input : - NewState: new state of the PCCARD Memory Bank.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void FSMC_PCCARDCmd(FunctionalState NewState)
{
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */
FSMC_Bank4->PCR4 |= PCR_PBKEN_Set;
}
else
{
/* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */
FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset;
}
}
/*******************************************************************************
* Function Name : FSMC_NANDECCCmd
* Description : Enables or disables the FSMC NAND ECC feature.
* Input : - FSMC_Bank: specifies the FSMC Bank to be used
* This parameter can be one of the following values:
* - FSMC_Bank2_NAND: FSMC Bank2 NAND
* - FSMC_Bank3_NAND: FSMC Bank3 NAND
* : - NewState: new state of the FSMC NAND ECC feature.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void FSMC_NANDECCCmd(u32 FSMC_Bank, FunctionalState NewState)
{
assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
if(FSMC_Bank == FSMC_Bank2_NAND)
{
FSMC_Bank2->PCR2 |= PCR_ECCEN_Set;
}
else
{
FSMC_Bank3->PCR3 |= PCR_ECCEN_Set;
}
}
else
{
/* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
if(FSMC_Bank == FSMC_Bank2_NAND)
{
FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset;
}
else
{
FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset;
}
}
}
/*******************************************************************************
* Function Name : FSMC_GetECC
* Description : Returns the error correction code register value.
* Input : - FSMC_Bank: specifies the FSMC Bank to be used
* This parameter can be one of the following values:
* - FSMC_Bank2_NAND: FSMC Bank2 NAND
* - FSMC_Bank3_NAND: FSMC Bank3 NAND
* Output : None
* Return : The Error Correction Code (ECC) value.
*******************************************************************************/
u32 FSMC_GetECC(u32 FSMC_Bank)
{
u32 eccval = 0x00000000;
if(FSMC_Bank == FSMC_Bank2_NAND)
{
/* Get the ECCR2 register value */
eccval = FSMC_Bank2->ECCR2;
}
else
{
/* Get the ECCR3 register value */
eccval = FSMC_Bank3->ECCR3;
}
/* Return the error correction code value */
return(eccval);
}
/*******************************************************************************
* Function Name : FSMC_ITConfig
* Description : Enables or disables the specified FSMC interrupts.
* Input : - FSMC_Bank: specifies the FSMC Bank to be used
* This parameter can be one of the following values:
* - FSMC_Bank2_NAND: FSMC Bank2 NAND
* - FSMC_Bank3_NAND: FSMC Bank3 NAND
* - FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
* - FSMC_IT: specifies the FSMC interrupt sources to be
* enabled or disabled.
* This parameter can be any combination of the following values:
* - FSMC_IT_RisingEdge: Rising edge detection interrupt.
* - FSMC_IT_Level: Level edge detection interrupt.
* - FSMC_IT_FallingEdge: Falling edge detection interrupt.
* - NewState: new state of the specified FSMC interrupts.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void FSMC_ITConfig(u32 FSMC_Bank, u32 FSMC_IT, FunctionalState NewState)
{
assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
assert_param(IS_FSMC_IT(FSMC_IT));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected FSMC_Bank2 interrupts */
if(FSMC_Bank == FSMC_Bank2_NAND)
{
FSMC_Bank2->SR2 |= FSMC_IT;
}
/* Enable the selected FSMC_Bank3 interrupts */
else if (FSMC_Bank == FSMC_Bank3_NAND)
{
FSMC_Bank3->SR3 |= FSMC_IT;
}
/* Enable the selected FSMC_Bank4 interrupts */
else
{
FSMC_Bank4->SR4 |= FSMC_IT;
}
}
else
{
/* Disable the selected FSMC_Bank2 interrupts */
if(FSMC_Bank == FSMC_Bank2_NAND)
{
FSMC_Bank2->SR2 &= (u32)~FSMC_IT;
}
/* Disable the selected FSMC_Bank3 interrupts */
else if (FSMC_Bank == FSMC_Bank3_NAND)
{
FSMC_Bank3->SR3 &= (u32)~FSMC_IT;
}
/* Disable the selected FSMC_Bank4 interrupts */
else
{
FSMC_Bank4->SR4 &= (u32)~FSMC_IT;
}
}
}
/*******************************************************************************
* Function Name : FSMC_GetFlagStatus
* Description : Checks whether the specified FSMC flag is set or not.
* Input : - FSMC_Bank: specifies the FSMC Bank to be used
* This parameter can be one of the following values:
* - FSMC_Bank2_NAND: FSMC Bank2 NAND
* - FSMC_Bank3_NAND: FSMC Bank3 NAND
* - FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
* - FSMC_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* - FSMC_FLAG_RisingEdge: Rising egde detection Flag.
* - FSMC_FLAG_Level: Level detection Flag.
* - FSMC_FLAG_FallingEdge: Falling egde detection Flag.
* - FSMC_FLAG_FEMPT: Fifo empty Flag.
* Output : None
* Return : The new state of FSMC_FLAG (SET or RESET).
*******************************************************************************/
FlagStatus FSMC_GetFlagStatus(u32 FSMC_Bank, u32 FSMC_FLAG)
{
FlagStatus bitstatus = RESET;
u32 tmpsr = 0x00000000;
/* Check the parameters */
assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG));
if(FSMC_Bank == FSMC_Bank2_NAND)
{
tmpsr = FSMC_Bank2->SR2;
}
else if(FSMC_Bank == FSMC_Bank3_NAND)
{
tmpsr = FSMC_Bank3->SR3;
}
/* FSMC_Bank4_PCCARD*/
else
{
tmpsr = FSMC_Bank4->SR4;
}
/* Get the flag status */
if ((tmpsr & FSMC_FLAG) != (u16)RESET )
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
/* Return the flag status */
return bitstatus;
}
/*******************************************************************************
* Function Name : FSMC_ClearFlag
* Description : Clears the FSMC’s pending flags.
* Input : - FSMC_Bank: specifies the FSMC Bank to be used
* This parameter can be one of the following values:
* - FSMC_Bank2_NAND: FSMC Bank2 NAND
* - FSMC_Bank3_NAND: FSMC Bank3 NAND
* - FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
* - FSMC_FLAG: specifies the flag to clear.
* This parameter can be any combination of the following values:
* - FSMC_FLAG_RisingEdge: Rising egde detection Flag.
* - FSMC_FLAG_Level: Level detection Flag.
* - FSMC_FLAG_FallingEdge: Falling egde detection Flag.
* Output : None
* Return : None
*******************************************************************************/
void FSMC_ClearFlag(u32 FSMC_Bank, u32 FSMC_FLAG)
{
/* Check the parameters */
assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ;
if(FSMC_Bank == FSMC_Bank2_NAND)
{
FSMC_Bank2->SR2 &= ~FSMC_FLAG;
}
else if(FSMC_Bank == FSMC_Bank3_NAND)
{
FSMC_Bank3->SR3 &= ~FSMC_FLAG;
}
/* FSMC_Bank4_PCCARD*/
else
{
FSMC_Bank4->SR4 &= ~FSMC_FLAG;
}
}
/*******************************************************************************
* Function Name : FSMC_GetITStatus
* Description : Checks whether the specified FSMC interrupt has occurred or not.
* Input : - FSMC_Bank: specifies the FSMC Bank to be used
* This parameter can be one of the following values:
* - FSMC_Bank2_NAND: FSMC Bank2 NAND
* - FSMC_Bank3_NAND: FSMC Bank3 NAND
* - FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
* - FSMC_IT: specifies the FSMC interrupt source to check.
* This parameter can be one of the following values:
* - FSMC_IT_RisingEdge: Rising edge detection interrupt.
* - FSMC_IT_Level: Level edge detection interrupt.
* - FSMC_IT_FallingEdge: Falling edge detection interrupt.
* Output : None
* Return : The new state of FSMC_IT (SET or RESET).
*******************************************************************************/
ITStatus FSMC_GetITStatus(u32 FSMC_Bank, u32 FSMC_IT)
{
ITStatus bitstatus = RESET;
u32 tmpsr = 0x0, itstatus = 0x0, itenable = 0x0;
/* Check the parameters */
assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
assert_param(IS_FSMC_GET_IT(FSMC_IT));
if(FSMC_Bank == FSMC_Bank2_NAND)
{
tmpsr = FSMC_Bank2->SR2;
}
else if(FSMC_Bank == FSMC_Bank3_NAND)
{
tmpsr = FSMC_Bank3->SR3;
}
/* FSMC_Bank4_PCCARD*/
else
{
tmpsr = FSMC_Bank4->SR4;
}
itstatus = tmpsr & FSMC_IT;
itenable = tmpsr & (FSMC_IT >> 3);
if ((itstatus != (u32)RESET) && (itenable != (u32)RESET))
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*******************************************************************************
* Function Name : FSMC_ClearITPendingBit
* Description : Clears the FSMC’s interrupt pending bits.
* Input : - FSMC_Bank: specifies the FSMC Bank to be used
* This parameter can be one of the following values:
* - FSMC_Bank2_NAND: FSMC Bank2 NAND
* - FSMC_Bank3_NAND: FSMC Bank3 NAND
* - FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
* - FSMC_IT: specifies the interrupt pending bit to clear.
* This parameter can be any combination of the following values:
* - FSMC_IT_RisingEdge: Rising edge detection interrupt.
* - FSMC_IT_Level: Level edge detection interrupt.
* - FSMC_IT_FallingEdge: Falling edge detection interrupt.
* Output : None
* Return : None
*******************************************************************************/
void FSMC_ClearITPendingBit(u32 FSMC_Bank, u32 FSMC_IT)
{
/* Check the parameters */
assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
assert_param(IS_FSMC_IT(FSMC_IT));
if(FSMC_Bank == FSMC_Bank2_NAND)
{
FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3);
}
else if(FSMC_Bank == FSMC_Bank3_NAND)
{
FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3);
}
/* FSMC_Bank4_PCCARD*/
else
{
FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3);
}
}
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

583
bsp/stm32f103vb_lwip/library/src/stm32f10x_gpio.c Normal file
View File

@ -0,0 +1,583 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_gpio.c
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file provides all the GPIO firmware functions.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_gpio.h"
#include "stm32f10x_rcc.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* ------------ RCC registers bit address in the alias region ----------- */
#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE)
/* --- EVENTCR Register ---*/
/* Alias word address of EVOE bit */
#define EVCR_OFFSET (AFIO_OFFSET + 0x00)
#define EVOE_BitNumber ((u8)0x07)
#define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4))
#define EVCR_PORTPINCONFIG_MASK ((u16)0xFF80)
#define LSB_MASK ((u16)0xFFFF)
#define DBGAFR_POSITION_MASK ((u32)0x000F0000)
#define DBGAFR_SWJCFG_MASK ((u32)0xF0FFFFFF)
#define DBGAFR_LOCATION_MASK ((u32)0x00200000)
#define DBGAFR_NUMBITS_MASK ((u32)0x00100000)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : GPIO_DeInit
* Description : Deinitializes the GPIOx peripheral registers to their default
* reset values.
* Input : - GPIOx: where x can be (A..G) to select the GPIO peripheral.
* Output : None
* Return : None
*******************************************************************************/
void GPIO_DeInit(GPIO_TypeDef* GPIOx)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
switch (*(u32*)&GPIOx)
{
case GPIOA_BASE:
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);
break;
case GPIOB_BASE:
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);
break;
case GPIOC_BASE:
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);
break;
case GPIOD_BASE:
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);
break;
case GPIOE_BASE:
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE);
break;
case GPIOF_BASE:
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE);
break;
case GPIOG_BASE:
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE);
break;
default:
break;
}
}
/*******************************************************************************
* Function Name : GPIO_AFIODeInit
* Description : Deinitializes the Alternate Functions (remap, event control
* and EXTI configuration) registers to their default reset
* values.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void GPIO_AFIODeInit(void)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE);
}
/*******************************************************************************
* Function Name : GPIO_Init
* Description : Initializes the GPIOx peripheral according to the specified
* parameters in the GPIO_InitStruct.
* Input : - GPIOx: where x can be (A..G) to select the GPIO peripheral.
* - GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that
* contains the configuration information for the specified GPIO
* peripheral.
* Output : None
* Return : None
*******************************************************************************/
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
{
u32 currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
u32 tmpreg = 0x00, pinmask = 0x00;
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
/*---------------------------- GPIO Mode Configuration -----------------------*/
currentmode = ((u32)GPIO_InitStruct->GPIO_Mode) & ((u32)0x0F);
if ((((u32)GPIO_InitStruct->GPIO_Mode) & ((u32)0x10)) != 0x00)
{
/* Check the parameters */
assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
/* Output mode */
currentmode |= (u32)GPIO_InitStruct->GPIO_Speed;
}
/*---------------------------- GPIO CRL Configuration ------------------------*/
/* Configure the eight low port pins */
if (((u32)GPIO_InitStruct->GPIO_Pin & ((u32)0x00FF)) != 0x00)
{
tmpreg = GPIOx->CRL;
for (pinpos = 0x00; pinpos < 0x08; pinpos++)
{
pos = ((u32)0x01) << pinpos;
/* Get the port pins position */
currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
if (currentpin == pos)
{
pos = pinpos << 2;
/* Clear the corresponding low control register bits */
pinmask = ((u32)0x0F) << pos;
tmpreg &= ~pinmask;
/* Write the mode configuration in the corresponding bits */
tmpreg |= (currentmode << pos);
/* Reset the corresponding ODR bit */
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
{
GPIOx->BRR = (((u32)0x01) << pinpos);
}
else
{
/* Set the corresponding ODR bit */
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
{
GPIOx->BSRR = (((u32)0x01) << pinpos);
}
}
}
}
GPIOx->CRL = tmpreg;
}
/*---------------------------- GPIO CRH Configuration ------------------------*/
/* Configure the eight high port pins */
if (GPIO_InitStruct->GPIO_Pin > 0x00FF)
{
tmpreg = GPIOx->CRH;
for (pinpos = 0x00; pinpos < 0x08; pinpos++)
{
pos = (((u32)0x01) << (pinpos + 0x08));
/* Get the port pins position */
currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);
if (currentpin == pos)
{
pos = pinpos << 2;
/* Clear the corresponding high control register bits */
pinmask = ((u32)0x0F) << pos;
tmpreg &= ~pinmask;
/* Write the mode configuration in the corresponding bits */
tmpreg |= (currentmode << pos);
/* Reset the corresponding ODR bit */
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
{
GPIOx->BRR = (((u32)0x01) << (pinpos + 0x08));
}
/* Set the corresponding ODR bit */
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
{
GPIOx->BSRR = (((u32)0x01) << (pinpos + 0x08));
}
}
}
GPIOx->CRH = tmpreg;
}
}
/*******************************************************************************
* Function Name : GPIO_StructInit
* Description : Fills each GPIO_InitStruct member with its default value.
* Input : - GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure
* which will be initialized.
* Output : None
* Return : None
*******************************************************************************/
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
{
/* Reset GPIO init structure parameters values */
GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;
}
/*******************************************************************************
* Function Name : GPIO_ReadInputDataBit
* Description : Reads the specified input port pin.
* Input : - GPIOx: where x can be (A..G) to select the GPIO peripheral.
* : - GPIO_Pin: specifies the port bit to read.
* This parameter can be GPIO_Pin_x where x can be (0..15).
* Output : None
* Return : The input port pin value.
*******************************************************************************/
u8 GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin)
{
u8 bitstatus = 0x00;
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
if ((GPIOx->IDR & GPIO_Pin) != (u32)Bit_RESET)
{
bitstatus = (u8)Bit_SET;
}
else
{
bitstatus = (u8)Bit_RESET;
}
return bitstatus;
}
/*******************************************************************************
* Function Name : GPIO_ReadInputData
* Description : Reads the specified GPIO input data port.
* Input : - GPIOx: where x can be (A..G) to select the GPIO peripheral.
* Output : None
* Return : GPIO input data port value.
*******************************************************************************/
u16 GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
return ((u16)GPIOx->IDR);
}
/*******************************************************************************
* Function Name : GPIO_ReadOutputDataBit
* Description : Reads the specified output data port bit.
* Input : - GPIOx: where x can be (A..G) to select the GPIO peripheral.
* : - GPIO_Pin: specifies the port bit to read.
* This parameter can be GPIO_Pin_x where x can be (0..15).
* Output : None
* Return : The output port pin value.
*******************************************************************************/
u8 GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin)
{
u8 bitstatus = 0x00;
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
if ((GPIOx->ODR & GPIO_Pin) != (u32)Bit_RESET)
{
bitstatus = (u8)Bit_SET;
}
else
{
bitstatus = (u8)Bit_RESET;
}
return bitstatus;
}
/*******************************************************************************
* Function Name : GPIO_ReadOutputData
* Description : Reads the specified GPIO output data port.
* Input : - GPIOx: where x can be (A..G) to select the GPIO peripheral.
* Output : None
* Return : GPIO output data port value.
*******************************************************************************/
u16 GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
return ((u16)GPIOx->ODR);
}
/*******************************************************************************
* Function Name : GPIO_SetBits
* Description : Sets the selected data port bits.
* Input : - GPIOx: where x can be (A..G) to select the GPIO peripheral.
* - GPIO_Pin: specifies the port bits to be written.
* This parameter can be any combination of GPIO_Pin_x where
* x can be (0..15).
* Output : None
* Return : None
*******************************************************************************/
void GPIO_SetBits(GPIO_TypeDef* GPIOx, u16 GPIO_Pin)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Pin));
GPIOx->BSRR = GPIO_Pin;
}
/*******************************************************************************
* Function Name : GPIO_ResetBits
* Description : Clears the selected data port bits.
* Input : - GPIOx: where x can be (A..G) to select the GPIO peripheral.
* - GPIO_Pin: specifies the port bits to be written.
* This parameter can be any combination of GPIO_Pin_x where
* x can be (0..15).
* Output : None
* Return : None
*******************************************************************************/
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, u16 GPIO_Pin)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Pin));
GPIOx->BRR = GPIO_Pin;
}
/*******************************************************************************
* Function Name : GPIO_WriteBit
* Description : Sets or clears the selected data port bit.
* Input : - GPIOx: where x can be (A..G) to select the GPIO peripheral.
* - GPIO_Pin: specifies the port bit to be written.
* This parameter can be one of GPIO_Pin_x where x can be (0..15).
* - BitVal: specifies the value to be written to the selected bit.
* This parameter can be one of the BitAction enum values:
* - Bit_RESET: to clear the port pin
* - Bit_SET: to set the port pin
* Output : None
* Return : None
*******************************************************************************/
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin, BitAction BitVal)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_BIT_ACTION(BitVal));
if (BitVal != Bit_RESET)
{
GPIOx->BSRR = GPIO_Pin;
}
else
{
GPIOx->BRR = GPIO_Pin;
}
}
/*******************************************************************************
* Function Name : GPIO_Write
* Description : Writes data to the specified GPIO data port.
* Input : - GPIOx: where x can be (A..G) to select the GPIO peripheral.
* - PortVal: specifies the value to be written to the port output
* data register.
* Output : None
* Return : None
*******************************************************************************/
void GPIO_Write(GPIO_TypeDef* GPIOx, u16 PortVal)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
GPIOx->ODR = PortVal;
}
/*******************************************************************************
* Function Name : GPIO_PinLockConfig
* Description : Locks GPIO Pins configuration registers.
* Input : - GPIOx: where x can be (A..G) to select the GPIO peripheral.
* - GPIO_Pin: specifies the port bit to be written.
* This parameter can be any combination of GPIO_Pin_x where
* x can be (0..15).
* Output : None
* Return : None
*******************************************************************************/
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, u16 GPIO_Pin)
{
u32 tmp = 0x00010000;
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Pin));
tmp |= GPIO_Pin;
/* Set LCKK bit */
GPIOx->LCKR = tmp;
/* Reset LCKK bit */
GPIOx->LCKR = GPIO_Pin;
/* Set LCKK bit */
GPIOx->LCKR = tmp;
/* Read LCKK bit*/
tmp = GPIOx->LCKR;
/* Read LCKK bit*/
tmp = GPIOx->LCKR;
}
/*******************************************************************************
* Function Name : GPIO_EventOutputConfig
* Description : Selects the GPIO pin used as Event output.
* Input : - GPIO_PortSource: selects the GPIO port to be used as source
* for Event output.
* This parameter can be GPIO_PortSourceGPIOx where x can be
* (A..E).
* - GPIO_PinSource: specifies the pin for the Event output.
* This parameter can be GPIO_PinSourcex where x can be (0..15).
* Output : None
* Return : None
*******************************************************************************/
void GPIO_EventOutputConfig(u8 GPIO_PortSource, u8 GPIO_PinSource)
{
u32 tmpreg = 0x00;
/* Check the parameters */
assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(GPIO_PortSource));
assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
tmpreg = AFIO->EVCR;
/* Clear the PORT[6:4] and PIN[3:0] bits */
tmpreg &= EVCR_PORTPINCONFIG_MASK;
tmpreg |= (u32)GPIO_PortSource << 0x04;
tmpreg |= GPIO_PinSource;
AFIO->EVCR = tmpreg;
}
/*******************************************************************************
* Function Name : GPIO_EventOutputCmd
* Description : Enables or disables the Event Output.
* Input : - NewState: new state of the Event output.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void GPIO_EventOutputCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(vu32 *) EVCR_EVOE_BB = (u32)NewState;
}
/*******************************************************************************
* Function Name : GPIO_PinRemapConfig
* Description : Changes the mapping of the specified pin.
* Input : - GPIO_Remap: selects the pin to remap.
* This parameter can be one of the following values:
* - GPIO_Remap_SPI1
* - GPIO_Remap_I2C1
* - GPIO_Remap_USART1
* - GPIO_Remap_USART2
* - GPIO_PartialRemap_USART3
* - GPIO_FullRemap_USART3
* - GPIO_PartialRemap_TIM1
* - GPIO_FullRemap_TIM1
* - GPIO_PartialRemap1_TIM2
* - GPIO_PartialRemap2_TIM2
* - GPIO_FullRemap_TIM2
* - GPIO_PartialRemap_TIM3
* - GPIO_FullRemap_TIM3
* - GPIO_Remap_TIM4
* - GPIO_Remap1_CAN
* - GPIO_Remap2_CAN
* - GPIO_Remap_PD01
* - GPIO_Remap_TIM5CH4_LSI
* - GPIO_Remap_ADC1_ETRGINJ
* - GPIO_Remap_ADC1_ETRGREG
* - GPIO_Remap_ADC2_ETRGINJ
* - GPIO_Remap_ADC2_ETRGREG
* - GPIO_Remap_SWJ_NoJTRST
* - GPIO_Remap_SWJ_JTAGDisable
* - GPIO_Remap_SWJ_Disable
* - NewState: new state of the port pin remapping.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void GPIO_PinRemapConfig(u32 GPIO_Remap, FunctionalState NewState)
{
u32 tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00;
/* Check the parameters */
assert_param(IS_GPIO_REMAP(GPIO_Remap));
assert_param(IS_FUNCTIONAL_STATE(NewState));
tmpreg = AFIO->MAPR;
tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10;
tmp = GPIO_Remap & LSB_MASK;
if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK))
{
tmpreg &= DBGAFR_SWJCFG_MASK;
AFIO->MAPR &= DBGAFR_SWJCFG_MASK;
}
else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK)
{
tmp1 = ((u32)0x03) << tmpmask;
tmpreg &= ~tmp1;
tmpreg |= ~DBGAFR_SWJCFG_MASK;
}
else
{
tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15)*0x10));
tmpreg |= ~DBGAFR_SWJCFG_MASK;
}
if (NewState != DISABLE)
{
tmpreg |= (tmp << ((GPIO_Remap >> 0x15)*0x10));
}
AFIO->MAPR = tmpreg;
}
/*******************************************************************************
* Function Name : GPIO_EXTILineConfig
* Description : Selects the GPIO pin used as EXTI Line.
* Input : - GPIO_PortSource: selects the GPIO port to be used as
* source for EXTI lines.
* This parameter can be GPIO_PortSourceGPIOx where x can be
* (A..G).
* - GPIO_PinSource: specifies the EXTI line to be configured.
* This parameter can be GPIO_PinSourcex where x can be (0..15).
* Output : None
* Return : None
*******************************************************************************/
void GPIO_EXTILineConfig(u8 GPIO_PortSource, u8 GPIO_PinSource)
{
u32 tmp = 0x00;
/* Check the parameters */
assert_param(IS_GPIO_EXTI_PORT_SOURCE(GPIO_PortSource));
assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
tmp = ((u32)0x0F) << (0x04 * (GPIO_PinSource & (u8)0x03));
AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp;
AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((u32)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (u8)0x03)));
}
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

1216
bsp/stm32f103vb_lwip/library/src/stm32f10x_i2c.c Normal file
View File

File diff suppressed because it is too large Load Diff

148
bsp/stm32f103vb_lwip/library/src/stm32f10x_iwdg.c Normal file
View File

@ -0,0 +1,148 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_iwdg.c
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file provides all the IWDG firmware functions.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_iwdg.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* ---------------------- IWDG registers bit mask ------------------------ */
/* KR register bit mask */
#define KR_KEY_Reload ((u16)0xAAAA)
#define KR_KEY_Enable ((u16)0xCCCC)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : IWDG_WriteAccessCmd
* Description : Enables or disables write access to IWDG_PR and IWDG_RLR
* registers.
* Input : - IWDG_WriteAccess: new state of write access to IWDG_PR and
* IWDG_RLR registers.
* This parameter can be one of the following values:
* - IWDG_WriteAccess_Enable: Enable write access to
* IWDG_PR and IWDG_RLR registers
* - IWDG_WriteAccess_Disable: Disable write access to
* IWDG_PR and IWDG_RLR registers
* Output : None
* Return : None
*******************************************************************************/
void IWDG_WriteAccessCmd(u16 IWDG_WriteAccess)
{
/* Check the parameters */
assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
IWDG->KR = IWDG_WriteAccess;
}
/*******************************************************************************
* Function Name : IWDG_SetPrescaler
* Description : Sets IWDG Prescaler value.
* Input : - IWDG_Prescaler: specifies the IWDG Prescaler value.
* This parameter can be one of the following values:
* - IWDG_Prescaler_4: IWDG prescaler set to 4
* - IWDG_Prescaler_8: IWDG prescaler set to 8
* - IWDG_Prescaler_16: IWDG prescaler set to 16
* - IWDG_Prescaler_32: IWDG prescaler set to 32
* - IWDG_Prescaler_64: IWDG prescaler set to 64
* - IWDG_Prescaler_128: IWDG prescaler set to 128
* - IWDG_Prescaler_256: IWDG prescaler set to 256
* Output : None
* Return : None
*******************************************************************************/
void IWDG_SetPrescaler(u8 IWDG_Prescaler)
{
/* Check the parameters */
assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
IWDG->PR = IWDG_Prescaler;
}
/*******************************************************************************
* Function Name : IWDG_SetReload
* Description : Sets IWDG Reload value.
* Input : - Reload: specifies the IWDG Reload value.
* This parameter must be a number between 0 and 0x0FFF.
* Output : None
* Return : None
*******************************************************************************/
void IWDG_SetReload(u16 Reload)
{
/* Check the parameters */
assert_param(IS_IWDG_RELOAD(Reload));
IWDG->RLR = Reload;
}
/*******************************************************************************
* Function Name : IWDG_ReloadCounter
* Description : Reloads IWDG counter with value defined in the reload register
* (write access to IWDG_PR and IWDG_RLR registers disabled).
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void IWDG_ReloadCounter(void)
{
IWDG->KR = KR_KEY_Reload;
}
/*******************************************************************************
* Function Name : IWDG_Enable
* Description : Enables IWDG (write access to IWDG_PR and IWDG_RLR registers
* disabled).
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void IWDG_Enable(void)
{
IWDG->KR = KR_KEY_Enable;
}
/*******************************************************************************
* Function Name : IWDG_GetFlagStatus
* Description : Checks whether the specified IWDG flag is set or not.
* Input : - IWDG_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* - IWDG_FLAG_PVU: Prescaler Value Update on going
* - IWDG_FLAG_RVU: Reload Value Update on going
* Output : None
* Return : The new state of IWDG_FLAG (SET or RESET).
*******************************************************************************/
FlagStatus IWDG_GetFlagStatus(u16 IWDG_FLAG)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_IWDG_FLAG(IWDG_FLAG));
if ((IWDG->SR & IWDG_FLAG) != (u32)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
/* Return the flag status */
return bitstatus;
}
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

303
bsp/stm32f103vb_lwip/library/src/stm32f10x_lib.c Normal file
View File

@ -0,0 +1,303 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_lib.c
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file provides all peripherals pointers initialization.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
#define EXT
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_lib.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
#ifdef DEBUG
/*******************************************************************************
* Function Name : debug
* Description : This function initialize peripherals pointers.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void debug(void)
{
/************************************* ADC ************************************/
#ifdef _ADC1
ADC1 = (ADC_TypeDef *) ADC1_BASE;
#endif /*_ADC1 */
#ifdef _ADC2
ADC2 = (ADC_TypeDef *) ADC2_BASE;
#endif /*_ADC2 */
#ifdef _ADC3
ADC3 = (ADC_TypeDef *) ADC3_BASE;
#endif /*_ADC3 */
/************************************* BKP ************************************/
#ifdef _BKP
BKP = (BKP_TypeDef *) BKP_BASE;
#endif /*_BKP */
/************************************* CAN ************************************/
#ifdef _CAN
CAN = (CAN_TypeDef *) CAN_BASE;
#endif /*_CAN */
/************************************* CRC ************************************/
#ifdef _CRC
CRC = (CRC_TypeDef *) CRC_BASE;
#endif /*_CRC */
/************************************* DAC ************************************/
#ifdef _DAC
DAC = (DAC_TypeDef *) DAC_BASE;
#endif /*_DAC */
/************************************* DBGMCU**********************************/
#ifdef _DBGMCU
DBGMCU = (DBGMCU_TypeDef *) DBGMCU_BASE;
#endif /*_DBGMCU */
/************************************* DMA ************************************/
#ifdef _DMA
DMA1 = (DMA_TypeDef *) DMA1_BASE;
DMA2 = (DMA_TypeDef *) DMA2_BASE;
#endif /*_DMA */
#ifdef _DMA1_Channel1
DMA1_Channel1 = (DMA_Channel_TypeDef *) DMA1_Channel1_BASE;
#endif /*_DMA1_Channel1 */
#ifdef _DMA1_Channel2
DMA1_Channel2 = (DMA_Channel_TypeDef *) DMA1_Channel2_BASE;
#endif /*_DMA1_Channel2 */
#ifdef _DMA1_Channel3
DMA1_Channel3 = (DMA_Channel_TypeDef *) DMA1_Channel3_BASE;
#endif /*_DMA1_Channel3 */
#ifdef _DMA1_Channel4
DMA1_Channel4 = (DMA_Channel_TypeDef *) DMA1_Channel4_BASE;
#endif /*_DMA1_Channel4 */
#ifdef _DMA1_Channel5
DMA1_Channel5 = (DMA_Channel_TypeDef *) DMA1_Channel5_BASE;
#endif /*_DMA1_Channel5 */
#ifdef _DMA1_Channel6
DMA1_Channel6 = (DMA_Channel_TypeDef *) DMA1_Channel6_BASE;
#endif /*_DMA1_Channel6 */
#ifdef _DMA1_Channel7
DMA1_Channel7 = (DMA_Channel_TypeDef *) DMA1_Channel7_BASE;
#endif /*_DMA1_Channel7 */
#ifdef _DMA2_Channel1
DMA2_Channel1 = (DMA_Channel_TypeDef *) DMA2_Channel1_BASE;
#endif /*_DMA2_Channel1 */
#ifdef _DMA2_Channel2
DMA2_Channel2 = (DMA_Channel_TypeDef *) DMA2_Channel2_BASE;
#endif /*_DMA2_Channel2 */
#ifdef _DMA2_Channel3
DMA2_Channel3 = (DMA_Channel_TypeDef *) DMA2_Channel3_BASE;
#endif /*_DMA2_Channel3 */
#ifdef _DMA2_Channel4
DMA2_Channel4 = (DMA_Channel_TypeDef *) DMA2_Channel4_BASE;
#endif /*_DMA2_Channel4 */
#ifdef _DMA2_Channel5
DMA2_Channel5 = (DMA_Channel_TypeDef *) DMA2_Channel5_BASE;
#endif /*_DMA2_Channel5 */
/************************************* EXTI ***********************************/
#ifdef _EXTI
EXTI = (EXTI_TypeDef *) EXTI_BASE;
#endif /*_EXTI */
/************************************* FLASH and Option Bytes *****************/
#ifdef _FLASH
FLASH = (FLASH_TypeDef *) FLASH_R_BASE;
OB = (OB_TypeDef *) OB_BASE;
#endif /*_FLASH */
/************************************* FSMC ***********************************/
#ifdef _FSMC
FSMC_Bank1 = (FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE;
FSMC_Bank1E = (FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE;
FSMC_Bank2 = (FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE;
FSMC_Bank3 = (FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE;
FSMC_Bank4 = (FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE;
#endif /*_FSMC */
/************************************* GPIO ***********************************/
#ifdef _GPIOA
GPIOA = (GPIO_TypeDef *) GPIOA_BASE;
#endif /*_GPIOA */
#ifdef _GPIOB
GPIOB = (GPIO_TypeDef *) GPIOB_BASE;
#endif /*_GPIOB */
#ifdef _GPIOC
GPIOC = (GPIO_TypeDef *) GPIOC_BASE;
#endif /*_GPIOC */
#ifdef _GPIOD
GPIOD = (GPIO_TypeDef *) GPIOD_BASE;
#endif /*_GPIOD */
#ifdef _GPIOE
GPIOE = (GPIO_TypeDef *) GPIOE_BASE;
#endif /*_GPIOE */
#ifdef _GPIOF
GPIOF = (GPIO_TypeDef *) GPIOF_BASE;
#endif /*_GPIOF */
#ifdef _GPIOG
GPIOG = (GPIO_TypeDef *) GPIOG_BASE;
#endif /*_GPIOG */
#ifdef _AFIO
AFIO = (AFIO_TypeDef *) AFIO_BASE;
#endif /*_AFIO */
/************************************* I2C ************************************/
#ifdef _I2C1
I2C1 = (I2C_TypeDef *) I2C1_BASE;
#endif /*_I2C1 */
#ifdef _I2C2
I2C2 = (I2C_TypeDef *) I2C2_BASE;
#endif /*_I2C2 */
/************************************* IWDG ***********************************/
#ifdef _IWDG
IWDG = (IWDG_TypeDef *) IWDG_BASE;
#endif /*_IWDG */
/************************************* NVIC ***********************************/
#ifdef _NVIC
NVIC = (NVIC_TypeDef *) NVIC_BASE;
SCB = (SCB_TypeDef *) SCB_BASE;
#endif /*_NVIC */
/************************************* PWR ************************************/
#ifdef _PWR
PWR = (PWR_TypeDef *) PWR_BASE;
#endif /*_PWR */
/************************************* RCC ************************************/
#ifdef _RCC
RCC = (RCC_TypeDef *) RCC_BASE;
#endif /*_RCC */
/************************************* RTC ************************************/
#ifdef _RTC
RTC = (RTC_TypeDef *) RTC_BASE;
#endif /*_RTC */
/************************************* SDIO ***********************************/
#ifdef _SDIO
SDIO = (SDIO_TypeDef *) SDIO_BASE;
#endif /*_SDIO */
/************************************* SPI ************************************/
#ifdef _SPI1
SPI1 = (SPI_TypeDef *) SPI1_BASE;
#endif /*_SPI1 */
#ifdef _SPI2
SPI2 = (SPI_TypeDef *) SPI2_BASE;
#endif /*_SPI2 */
#ifdef _SPI3
SPI3 = (SPI_TypeDef *) SPI3_BASE;
#endif /*_SPI3 */
/************************************* SysTick ********************************/
#ifdef _SysTick
SysTick = (SysTick_TypeDef *) SysTick_BASE;
#endif /*_SysTick */
/************************************* TIM ************************************/
#ifdef _TIM1
TIM1 = (TIM_TypeDef *) TIM1_BASE;
#endif /*_TIM1 */
#ifdef _TIM2
TIM2 = (TIM_TypeDef *) TIM2_BASE;
#endif /*_TIM2 */
#ifdef _TIM3
TIM3 = (TIM_TypeDef *) TIM3_BASE;
#endif /*_TIM3 */
#ifdef _TIM4
TIM4 = (TIM_TypeDef *) TIM4_BASE;
#endif /*_TIM4 */
#ifdef _TIM5
TIM5 = (TIM_TypeDef *) TIM5_BASE;
#endif /*_TIM5 */
#ifdef _TIM6
TIM6 = (TIM_TypeDef *) TIM6_BASE;
#endif /*_TIM6 */
#ifdef _TIM7
TIM7 = (TIM_TypeDef *) TIM7_BASE;
#endif /*_TIM7 */
#ifdef _TIM8
TIM8 = (TIM_TypeDef *) TIM8_BASE;
#endif /*_TIM8 */
/************************************* USART **********************************/
#ifdef _USART1
USART1 = (USART_TypeDef *) USART1_BASE;
#endif /*_USART1 */
#ifdef _USART2
USART2 = (USART_TypeDef *) USART2_BASE;
#endif /*_USART2 */
#ifdef _USART3
USART3 = (USART_TypeDef *) USART3_BASE;
#endif /*_USART3 */
#ifdef _UART4
UART4 = (USART_TypeDef *) UART4_BASE;
#endif /*_UART4 */
#ifdef _UART5
UART5 = (USART_TypeDef *) UART5_BASE;
#endif /*_UART5 */
/************************************* WWDG ***********************************/
#ifdef _WWDG
WWDG = (WWDG_TypeDef *) WWDG_BASE;
#endif /*_WWDG */
}
#endif /* DEBUG*/
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

751
bsp/stm32f103vb_lwip/library/src/stm32f10x_nvic.c Normal file
View File

@ -0,0 +1,751 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_nvic.c
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file provides all the NVIC firmware functions.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_nvic.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define AIRCR_VECTKEY_MASK ((u32)0x05FA0000)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : NVIC_DeInit
* Description : Deinitializes the NVIC peripheral registers to their default
* reset values.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void NVIC_DeInit(void)
{
u32 index = 0;
NVIC->ICER[0] = 0xFFFFFFFF;
NVIC->ICER[1] = 0x0FFFFFFF;
NVIC->ICPR[0] = 0xFFFFFFFF;
NVIC->ICPR[1] = 0x0FFFFFFF;
for(index = 0; index < 0x0F; index++)
{
NVIC->IPR[index] = 0x00000000;
}
}
/*******************************************************************************
* Function Name : NVIC_SCBDeInit
* Description : Deinitializes the SCB peripheral registers to their default
* reset values.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void NVIC_SCBDeInit(void)
{
u32 index = 0x00;
SCB->ICSR = 0x0A000000;
SCB->VTOR = 0x00000000;
SCB->AIRCR = AIRCR_VECTKEY_MASK;
SCB->SCR = 0x00000000;
SCB->CCR = 0x00000000;
for(index = 0; index < 0x03; index++)
{
SCB->SHPR[index] = 0;
}
SCB->SHCSR = 0x00000000;
SCB->CFSR = 0xFFFFFFFF;
SCB->HFSR = 0xFFFFFFFF;
SCB->DFSR = 0xFFFFFFFF;
}
/*******************************************************************************
* Function Name : NVIC_PriorityGroupConfig
* Description : Configures the priority grouping: pre-emption priority
* and subpriority.
* Input : - NVIC_PriorityGroup: specifies the priority grouping bits
* length. This parameter can be one of the following values:
* - NVIC_PriorityGroup_0: 0 bits for pre-emption priority
* 4 bits for subpriority
* - NVIC_PriorityGroup_1: 1 bits for pre-emption priority
* 3 bits for subpriority
* - NVIC_PriorityGroup_2: 2 bits for pre-emption priority
* 2 bits for subpriority
* - NVIC_PriorityGroup_3: 3 bits for pre-emption priority
* 1 bits for subpriority
* - NVIC_PriorityGroup_4: 4 bits for pre-emption priority
* 0 bits for subpriority
* Output : None
* Return : None
*******************************************************************************/
void NVIC_PriorityGroupConfig(u32 NVIC_PriorityGroup)
{
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
}
/*******************************************************************************
* Function Name : NVIC_Init
* Description : Initializes the NVIC peripheral according to the specified
* parameters in the NVIC_InitStruct.
* Input : - NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure
* that contains the configuration information for the
* specified NVIC peripheral.
* Output : None
* Return : None
*******************************************************************************/
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
{
u32 tmppriority = 0x00, tmpreg = 0x00, tmpmask = 0x00;
u32 tmppre = 0, tmpsub = 0x0F;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
assert_param(IS_NVIC_IRQ_CHANNEL(NVIC_InitStruct->NVIC_IRQChannel));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
{
/* Compute the Corresponding IRQ Priority --------------------------------*/
tmppriority = (0x700 - (SCB->AIRCR & (u32)0x700))>> 0x08;
tmppre = (0x4 - tmppriority);
tmpsub = tmpsub >> tmppriority;
tmppriority = (u32)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
tmppriority = tmppriority << 0x04;
tmppriority = ((u32)tmppriority) << ((NVIC_InitStruct->NVIC_IRQChannel & (u8)0x03) * 0x08);
tmpreg = NVIC->IPR[(NVIC_InitStruct->NVIC_IRQChannel >> 0x02)];
tmpmask = (u32)0xFF << ((NVIC_InitStruct->NVIC_IRQChannel & (u8)0x03) * 0x08);
tmpreg &= ~tmpmask;
tmppriority &= tmpmask;
tmpreg |= tmppriority;
NVIC->IPR[(NVIC_InitStruct->NVIC_IRQChannel >> 0x02)] = tmpreg;
/* Enable the Selected IRQ Channels --------------------------------------*/
NVIC->ISER[(NVIC_InitStruct->NVIC_IRQChannel >> 0x05)] =
(u32)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (u8)0x1F);
}
else
{
/* Disable the Selected IRQ Channels -------------------------------------*/
NVIC->ICER[(NVIC_InitStruct->NVIC_IRQChannel >> 0x05)] =
(u32)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (u8)0x1F);
}
}
/*******************************************************************************
* Function Name : NVIC_StructInit
* Description : Fills each NVIC_InitStruct member with its default value.
* Input : - NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure which
* will be initialized.
* Output : None
* Return : None
*******************************************************************************/
void NVIC_StructInit(NVIC_InitTypeDef* NVIC_InitStruct)
{
/* NVIC_InitStruct members default value */
NVIC_InitStruct->NVIC_IRQChannel = 0x00;
NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority = 0x00;
NVIC_InitStruct->NVIC_IRQChannelSubPriority = 0x00;
NVIC_InitStruct->NVIC_IRQChannelCmd = DISABLE;
}
/*******************************************************************************
* Function Name : NVIC_SETPRIMASK
* Description : Enables the PRIMASK priority: Raises the execution priority to 0.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void NVIC_SETPRIMASK(void)
{
__SETPRIMASK();
}
/*******************************************************************************
* Function Name : NVIC_RESETPRIMASK
* Description : Disables the PRIMASK priority.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void NVIC_RESETPRIMASK(void)
{
__RESETPRIMASK();
}
/*******************************************************************************
* Function Name : NVIC_SETFAULTMASK
* Description : Enables the FAULTMASK priority: Raises the execution priority to -1.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void NVIC_SETFAULTMASK(void)
{
__SETFAULTMASK();
}
/*******************************************************************************
* Function Name : NVIC_RESETFAULTMASK
* Description : Disables the FAULTMASK priority.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void NVIC_RESETFAULTMASK(void)
{
__RESETFAULTMASK();
}
/*******************************************************************************
* Function Name : NVIC_BASEPRICONFIG
* Description : The execution priority can be changed from 15 (lowest
configurable priority) to 1. Writing a zero value will disable
* the mask of execution priority.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void NVIC_BASEPRICONFIG(u32 NewPriority)
{
/* Check the parameters */
assert_param(IS_NVIC_BASE_PRI(NewPriority));
__BASEPRICONFIG(NewPriority << 0x04);
}
/*******************************************************************************
* Function Name : NVIC_GetBASEPRI
* Description : Returns the BASEPRI mask value.
* Input : None
* Output : None
* Return : BASEPRI register value
*******************************************************************************/
u32 NVIC_GetBASEPRI(void)
{
return (__GetBASEPRI());
}
/*******************************************************************************
* Function Name : NVIC_GetCurrentPendingIRQChannel
* Description : Returns the current pending IRQ channel identifier.
* Input : None
* Output : None
* Return : Pending IRQ Channel Identifier.
*******************************************************************************/
u16 NVIC_GetCurrentPendingIRQChannel(void)
{
return ((u16)((SCB->ICSR & (u32)0x003FF000) >> 0x0C));
}
/*******************************************************************************
* Function Name : NVIC_GetIRQChannelPendingBitStatus
* Description : Checks whether the specified IRQ Channel pending bit is set
* or not.
* Input : - NVIC_IRQChannel: specifies the interrupt pending bit to check.
* Output : None
* Return : The new state of IRQ Channel pending bit(SET or RESET).
*******************************************************************************/
ITStatus NVIC_GetIRQChannelPendingBitStatus(u8 NVIC_IRQChannel)
{
ITStatus pendingirqstatus = RESET;
u32 tmp = 0x00;
/* Check the parameters */
assert_param(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel));
tmp = ((u32)0x01 << (NVIC_IRQChannel & (u32)0x1F));
if (((NVIC->ISPR[(NVIC_IRQChannel >> 0x05)]) & tmp) == tmp)
{
pendingirqstatus = SET;
}
else
{
pendingirqstatus = RESET;
}
return pendingirqstatus;
}
/*******************************************************************************
* Function Name : NVIC_SetIRQChannelPendingBit
* Description : Sets the NVIC’s interrupt pending bit.
* Input : - NVIC_IRQChannel: specifies the interrupt pending bit to Set.
* Output : None
* Return : None
*******************************************************************************/
void NVIC_SetIRQChannelPendingBit(u8 NVIC_IRQChannel)
{
/* Check the parameters */
assert_param(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel));
*(vu32*) 0xE000EF00 = (u32)NVIC_IRQChannel;
}
/*******************************************************************************
* Function Name : NVIC_ClearIRQChannelPendingBit
* Description : Clears the NVIC’s interrupt pending bit.
* Input : - NVIC_IRQChannel: specifies the interrupt pending bit to clear.
* Output : None
* Return : None
*******************************************************************************/
void NVIC_ClearIRQChannelPendingBit(u8 NVIC_IRQChannel)
{
/* Check the parameters */
assert_param(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel));
NVIC->ICPR[(NVIC_IRQChannel >> 0x05)] = (u32)0x01 << (NVIC_IRQChannel & (u32)0x1F);
}
/*******************************************************************************
* Function Name : NVIC_GetCurrentActiveHandler
* Description : Returns the current active Handler (IRQ Channel and
* SystemHandler) identifier.
* Input : None
* Output : None
* Return : Active Handler Identifier.
*******************************************************************************/
u16 NVIC_GetCurrentActiveHandler(void)
{
return ((u16)(SCB->ICSR & (u32)0x3FF));
}
/*******************************************************************************
* Function Name : NVIC_GetIRQChannelActiveBitStatus
* Description : Checks whether the specified IRQ Channel active bit is set
* or not.
* Input : - NVIC_IRQChannel: specifies the interrupt active bit to check.
* Output : None
* Return : The new state of IRQ Channel active bit(SET or RESET).
*******************************************************************************/
ITStatus NVIC_GetIRQChannelActiveBitStatus(u8 NVIC_IRQChannel)
{
ITStatus activeirqstatus = RESET;
u32 tmp = 0x00;
/* Check the parameters */
assert_param(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel));
tmp = ((u32)0x01 << (NVIC_IRQChannel & (u32)0x1F));
if (((NVIC->IABR[(NVIC_IRQChannel >> 0x05)]) & tmp) == tmp )
{
activeirqstatus = SET;
}
else
{
activeirqstatus = RESET;
}
return activeirqstatus;
}
/*******************************************************************************
* Function Name : NVIC_GetCPUID
* Description : Returns the ID number, the version number and the implementation
* details of the Cortex-M3 core.
* Input : None
* Output : None
* Return : CPU ID.
*******************************************************************************/
u32 NVIC_GetCPUID(void)
{
return (SCB->CPUID);
}
/*******************************************************************************
* Function Name : NVIC_SetVectorTable
* Description : Sets the vector table location and Offset.
* Input : - NVIC_VectTab: specifies if the vector table is in RAM or
* FLASH memory.
* This parameter can be one of the following values:
* - NVIC_VectTab_RAM
* - NVIC_VectTab_FLASH
* - Offset: Vector Table base offset field.
* This value must be a multiple of 0x100.
* Output : None
* Return : None
*******************************************************************************/
void NVIC_SetVectorTable(u32 NVIC_VectTab, u32 Offset)
{
/* Check the parameters */
assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
assert_param(IS_NVIC_OFFSET(Offset));
SCB->VTOR = NVIC_VectTab | (Offset & (u32)0x1FFFFF80);
}
/*******************************************************************************
* Function Name : NVIC_GenerateSystemReset
* Description : Generates a system reset.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void NVIC_GenerateSystemReset(void)
{
SCB->AIRCR = AIRCR_VECTKEY_MASK | (u32)0x04;
}
/*******************************************************************************
* Function Name : NVIC_GenerateCoreReset
* Description : Generates a Core (Core + NVIC) reset.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void NVIC_GenerateCoreReset(void)
{
SCB->AIRCR = AIRCR_VECTKEY_MASK | (u32)0x01;
}
/*******************************************************************************
* Function Name : NVIC_SystemLPConfig
* Description : Selects the condition for the system to enter low power mode.
* Input : - LowPowerMode: Specifies the new mode for the system to enter
* low power mode.
* This parameter can be one of the following values:
* - NVIC_LP_SEVONPEND
* - NVIC_LP_SLEEPDEEP
* - NVIC_LP_SLEEPONEXIT
* - NewState: new state of LP condition.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void NVIC_SystemLPConfig(u8 LowPowerMode, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_NVIC_LP(LowPowerMode));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
SCB->SCR |= LowPowerMode;
}
else
{
SCB->SCR &= (u32)(~(u32)LowPowerMode);
}
}
/*******************************************************************************
* Function Name : NVIC_SystemHandlerConfig
* Description : Enables or disables the specified System Handlers.
* Input : - SystemHandler: specifies the system handler to be enabled
* or disabled.
* This parameter can be one of the following values:
* - SystemHandler_MemoryManage
* - SystemHandler_BusFault
* - SystemHandler_UsageFault
* - NewState: new state of specified System Handlers.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void NVIC_SystemHandlerConfig(u32 SystemHandler, FunctionalState NewState)
{
u32 tmpreg = 0x00;
/* Check the parameters */
assert_param(IS_CONFIG_SYSTEM_HANDLER(SystemHandler));
assert_param(IS_FUNCTIONAL_STATE(NewState));
tmpreg = (u32)0x01 << (SystemHandler & (u32)0x1F);
if (NewState != DISABLE)
{
SCB->SHCSR |= tmpreg;
}
else
{
SCB->SHCSR &= ~tmpreg;
}
}
/*******************************************************************************
* Function Name : NVIC_SystemHandlerPriorityConfig
* Description : Configures the specified System Handlers priority.
* Input : - SystemHandler: specifies the system handler to be
* enabled or disabled.
* This parameter can be one of the following values:
* - SystemHandler_MemoryManage
* - SystemHandler_BusFault
* - SystemHandler_UsageFault
* - SystemHandler_SVCall
* - SystemHandler_DebugMonitor
* - SystemHandler_PSV
* - SystemHandler_SysTick
* - SystemHandlerPreemptionPriority: new priority group of the
* specified system handlers.
* - SystemHandlerSubPriority: new sub priority of the specified
* system handlers.
* Output : None
* Return : None
*******************************************************************************/
void NVIC_SystemHandlerPriorityConfig(u32 SystemHandler, u8 SystemHandlerPreemptionPriority,
u8 SystemHandlerSubPriority)
{
u32 tmp1 = 0x00, tmp2 = 0xFF, handlermask = 0x00;
u32 tmppriority = 0x00;
/* Check the parameters */
assert_param(IS_PRIORITY_SYSTEM_HANDLER(SystemHandler));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(SystemHandlerPreemptionPriority));
assert_param(IS_NVIC_SUB_PRIORITY(SystemHandlerSubPriority));
tmppriority = (0x700 - (SCB->AIRCR & (u32)0x700))>> 0x08;
tmp1 = (0x4 - tmppriority);
tmp2 = tmp2 >> tmppriority;
tmppriority = (u32)SystemHandlerPreemptionPriority << tmp1;
tmppriority |= SystemHandlerSubPriority & tmp2;
tmppriority = tmppriority << 0x04;
tmp1 = SystemHandler & (u32)0xC0;
tmp1 = tmp1 >> 0x06;
tmp2 = (SystemHandler >> 0x08) & (u32)0x03;
tmppriority = tmppriority << (tmp2 * 0x08);
handlermask = (u32)0xFF << (tmp2 * 0x08);
SCB->SHPR[tmp1] &= ~handlermask;
SCB->SHPR[tmp1] |= tmppriority;
}
/*******************************************************************************
* Function Name : NVIC_GetSystemHandlerPendingBitStatus
* Description : Checks whether the specified System handlers pending bit is
* set or not.
* Input : - SystemHandler: specifies the system handler pending bit to
* check.
* This parameter can be one of the following values:
* - SystemHandler_MemoryManage
* - SystemHandler_BusFault
* - SystemHandler_SVCall
* Output : None
* Return : The new state of System Handler pending bit(SET or RESET).
*******************************************************************************/
ITStatus NVIC_GetSystemHandlerPendingBitStatus(u32 SystemHandler)
{
ITStatus bitstatus = RESET;
u32 tmp = 0x00, tmppos = 0x00;
/* Check the parameters */
assert_param(IS_GET_PENDING_SYSTEM_HANDLER(SystemHandler));
tmppos = (SystemHandler >> 0x0A);
tmppos &= (u32)0x0F;
tmppos = (u32)0x01 << tmppos;
tmp = SCB->SHCSR & tmppos;
if (tmp == tmppos)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*******************************************************************************
* Function Name : NVIC_SetSystemHandlerPendingBit
* Description : Sets System Handler pending bit.
* Input : - SystemHandler: specifies the system handler pending bit
* to be set.
* This parameter can be one of the following values:
* - SystemHandler_NMI
* - SystemHandler_PSV
* - SystemHandler_SysTick
* Output : None
* Return : None
*******************************************************************************/
void NVIC_SetSystemHandlerPendingBit(u32 SystemHandler)
{
u32 tmp = 0x00;
/* Check the parameters */
assert_param(IS_SET_PENDING_SYSTEM_HANDLER(SystemHandler));
/* Get the System Handler pending bit position */
tmp = SystemHandler & (u32)0x1F;
/* Set the corresponding System Handler pending bit */
SCB->ICSR |= ((u32)0x01 << tmp);
}
/*******************************************************************************
* Function Name : NVIC_ClearSystemHandlerPendingBit
* Description : Clears System Handler pending bit.
* Input : - SystemHandler: specifies the system handler pending bit to
* be clear.
* This parameter can be one of the following values:
* - SystemHandler_PSV
* - SystemHandler_SysTick
* Output : None
* Return : None
*******************************************************************************/
void NVIC_ClearSystemHandlerPendingBit(u32 SystemHandler)
{
u32 tmp = 0x00;
/* Check the parameters */
assert_param(IS_CLEAR_SYSTEM_HANDLER(SystemHandler));
/* Get the System Handler pending bit position */
tmp = SystemHandler & (u32)0x1F;
/* Clear the corresponding System Handler pending bit */
SCB->ICSR |= ((u32)0x01 << (tmp - 0x01));
}
/*******************************************************************************
* Function Name : NVIC_GetSystemHandlerActiveBitStatus
* Description : Checks whether the specified System handlers active bit is
* set or not.
* Input : - SystemHandler: specifies the system handler active bit to
* check.
* This parameter can be one of the following values:
* - SystemHandler_MemoryManage
* - SystemHandler_BusFault
* - SystemHandler_UsageFault
* - SystemHandler_SVCall
* - SystemHandler_DebugMonitor
* - SystemHandler_PSV
* - SystemHandler_SysTick
* Output : None
* Return : The new state of System Handler active bit(SET or RESET).
*******************************************************************************/
ITStatus NVIC_GetSystemHandlerActiveBitStatus(u32 SystemHandler)
{
ITStatus bitstatus = RESET;
u32 tmp = 0x00, tmppos = 0x00;
/* Check the parameters */
assert_param(IS_GET_ACTIVE_SYSTEM_HANDLER(SystemHandler));
tmppos = (SystemHandler >> 0x0E) & (u32)0x0F;
tmppos = (u32)0x01 << tmppos;
tmp = SCB->SHCSR & tmppos;
if (tmp == tmppos)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*******************************************************************************
* Function Name : NVIC_GetFaultHandlerSources
* Description : Returns the system fault handlers sources.
* Input : - SystemHandler: specifies the system handler to get its fault
* sources.
* This parameter can be one of the following values:
* - SystemHandler_HardFault
* - SystemHandler_MemoryManage
* - SystemHandler_BusFault
* - SystemHandler_UsageFault
* - SystemHandler_DebugMonitor
* Output : None
* Return : Source of the fault handler.
*******************************************************************************/
u32 NVIC_GetFaultHandlerSources(u32 SystemHandler)
{
u32 faultsources = 0x00;
u32 tmpreg = 0x00, tmppos = 0x00;
/* Check the parameters */
assert_param(IS_FAULT_SOURCE_SYSTEM_HANDLER(SystemHandler));
tmpreg = (SystemHandler >> 0x12) & (u32)0x03;
tmppos = (SystemHandler >> 0x14) & (u32)0x03;
if (tmpreg == 0x00)
{
faultsources = SCB->HFSR;
}
else if (tmpreg == 0x01)
{
faultsources = SCB->CFSR >> (tmppos * 0x08);
if (tmppos != 0x02)
{
faultsources &= (u32)0x0F;
}
else
{
faultsources &= (u32)0xFF;
}
}
else
{
faultsources = SCB->DFSR;
}
return faultsources;
}
/*******************************************************************************
* Function Name : NVIC_GetFaultAddress
* Description : Returns the address of the location that generated a fault
* handler.
* Input : - SystemHandler: specifies the system handler to get its
* fault address.
* This parameter can be one of the following values:
* - SystemHandler_MemoryManage
* - SystemHandler_BusFault
* Output : None
* Return : Fault address.
*******************************************************************************/
u32 NVIC_GetFaultAddress(u32 SystemHandler)
{
u32 faultaddress = 0x00;
u32 tmp = 0x00;
/* Check the parameters */
assert_param(IS_FAULT_ADDRESS_SYSTEM_HANDLER(SystemHandler));
tmp = (SystemHandler >> 0x16) & (u32)0x01;
if (tmp == 0x00)
{
faultaddress = SCB->MMFAR;
}
else
{
faultaddress = SCB->BFAR;
}
return faultaddress;
}
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

280
bsp/stm32f103vb_lwip/library/src/stm32f10x_pwr.c Normal file
View File

@ -0,0 +1,280 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_pwr.c
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file provides all the PWR firmware functions.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_pwr.h"
#include "stm32f10x_rcc.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* --------- PWR registers bit address in the alias region ---------- */
#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
/* --- CR Register ---*/
/* Alias word address of DBP bit */
#define CR_OFFSET (PWR_OFFSET + 0x00)
#define DBP_BitNumber 0x08
#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
/* Alias word address of PVDE bit */
#define PVDE_BitNumber 0x04
#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
/* --- CSR Register ---*/
/* Alias word address of EWUP bit */
#define CSR_OFFSET (PWR_OFFSET + 0x04)
#define EWUP_BitNumber 0x08
#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
/* ------------------ PWR registers bit mask ------------------------ */
/* CR register bit mask */
#define CR_PDDS_Set ((u32)0x00000002)
#define CR_DS_Mask ((u32)0xFFFFFFFC)
#define CR_CWUF_Set ((u32)0x00000004)
#define CR_PLS_Mask ((u32)0xFFFFFF1F)
/* --------- Cortex System Control register bit mask ---------------- */
/* Cortex System Control register address */
#define SCB_SysCtrl ((u32)0xE000ED10)
/* SLEEPDEEP bit mask */
#define SysCtrl_SLEEPDEEP_Set ((u32)0x00000004)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : PWR_DeInit
* Description : Deinitializes the PWR peripheral registers to their default
* reset values.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void PWR_DeInit(void)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
}
/*******************************************************************************
* Function Name : PWR_BackupAccessCmd
* Description : Enables or disables access to the RTC and backup registers.
* Input : - NewState: new state of the access to the RTC and backup
* registers. This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void PWR_BackupAccessCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(vu32 *) CR_DBP_BB = (u32)NewState;
}
/*******************************************************************************
* Function Name : PWR_PVDCmd
* Description : Enables or disables the Power Voltage Detector(PVD).
* Input : - NewState: new state of the PVD.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void PWR_PVDCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(vu32 *) CR_PVDE_BB = (u32)NewState;
}
/*******************************************************************************
* Function Name : PWR_PVDLevelConfig
* Description : Configures the voltage threshold detected by the Power Voltage
* Detector(PVD).
* Input : - PWR_PVDLevel: specifies the PVD detection level
* This parameter can be one of the following values:
* - PWR_PVDLevel_2V2: PVD detection level set to 2.2V
* - PWR_PVDLevel_2V3: PVD detection level set to 2.3V
* - PWR_PVDLevel_2V4: PVD detection level set to 2.4V
* - PWR_PVDLevel_2V5: PVD detection level set to 2.5V
* - PWR_PVDLevel_2V6: PVD detection level set to 2.6V
* - PWR_PVDLevel_2V7: PVD detection level set to 2.7V
* - PWR_PVDLevel_2V8: PVD detection level set to 2.8V
* - PWR_PVDLevel_2V9: PVD detection level set to 2.9V
* Output : None
* Return : None
*******************************************************************************/
void PWR_PVDLevelConfig(u32 PWR_PVDLevel)
{
u32 tmpreg = 0;
/* Check the parameters */
assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
tmpreg = PWR->CR;
/* Clear PLS[7:5] bits */
tmpreg &= CR_PLS_Mask;
/* Set PLS[7:5] bits according to PWR_PVDLevel value */
tmpreg |= PWR_PVDLevel;
/* Store the new value */
PWR->CR = tmpreg;
}
/*******************************************************************************
* Function Name : PWR_WakeUpPinCmd
* Description : Enables or disables the WakeUp Pin functionality.
* Input : - NewState: new state of the WakeUp Pin functionality.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void PWR_WakeUpPinCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(vu32 *) CSR_EWUP_BB = (u32)NewState;
}
/*******************************************************************************
* Function Name : PWR_EnterSTOPMode
* Description : Enters STOP mode.
* Input : - PWR_Regulator: specifies the regulator state in STOP mode.
* This parameter can be one of the following values:
* - PWR_Regulator_ON: STOP mode with regulator ON
* - PWR_Regulator_LowPower: STOP mode with
* regulator in low power mode
* - PWR_STOPEntry: specifies if STOP mode in entered with WFI or
* WFE instruction.
* This parameter can be one of the following values:
* - PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
* - PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
* Output : None
* Return : None
*******************************************************************************/
void PWR_EnterSTOPMode(u32 PWR_Regulator, u8 PWR_STOPEntry)
{
u32 tmpreg = 0;
/* Check the parameters */
assert_param(IS_PWR_REGULATOR(PWR_Regulator));
assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
/* Select the regulator state in STOP mode ---------------------------------*/
tmpreg = PWR->CR;
/* Clear PDDS and LPDS bits */
tmpreg &= CR_DS_Mask;
/* Set LPDS bit according to PWR_Regulator value */
tmpreg |= PWR_Regulator;
/* Store the new value */
PWR->CR = tmpreg;
/* Set SLEEPDEEP bit of Cortex System Control Register */
*(vu32 *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set;
/* Select STOP mode entry --------------------------------------------------*/
if(PWR_STOPEntry == PWR_STOPEntry_WFI)
{
/* Request Wait For Interrupt */
__WFI();
}
else
{
/* Request Wait For Event */
__WFE();
}
}
/*******************************************************************************
* Function Name : PWR_EnterSTANDBYMode
* Description : Enters STANDBY mode.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void PWR_EnterSTANDBYMode(void)
{
/* Clear Wake-up flag */
PWR->CR |= CR_CWUF_Set;
/* Select STANDBY mode */
PWR->CR |= CR_PDDS_Set;
/* Set SLEEPDEEP bit of Cortex System Control Register */
*(vu32 *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set;
/* Request Wait For Interrupt */
__WFI();
}
/*******************************************************************************
* Function Name : PWR_GetFlagStatus
* Description : Checks whether the specified PWR flag is set or not.
* Input : - PWR_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* - PWR_FLAG_WU: Wake Up flag
* - PWR_FLAG_SB: StandBy flag
* - PWR_FLAG_PVDO: PVD Output
* Output : None
* Return : The new state of PWR_FLAG (SET or RESET).
*******************************************************************************/
FlagStatus PWR_GetFlagStatus(u32 PWR_FLAG)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
if ((PWR->CSR & PWR_FLAG) != (u32)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
/* Return the flag status */
return bitstatus;
}
/*******************************************************************************
* Function Name : PWR_ClearFlag
* Description : Clears the PWR's pending flags.
* Input : - PWR_FLAG: specifies the flag to clear.
* This parameter can be one of the following values:
* - PWR_FLAG_WU: Wake Up flag
* - PWR_FLAG_SB: StandBy flag
* Output : None
* Return : None
*******************************************************************************/
void PWR_ClearFlag(u32 PWR_FLAG)
{
/* Check the parameters */
assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
PWR->CR |= PWR_FLAG << 2;
}
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

1105
bsp/stm32f103vb_lwip/library/src/stm32f10x_rcc.c Normal file
View File

File diff suppressed because it is too large Load Diff

320
bsp/stm32f103vb_lwip/library/src/stm32f10x_rtc.c Normal file
View File

@ -0,0 +1,320 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_rtc.c
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file provides all the RTC firmware functions.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_rtc.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define CRL_CNF_Set ((u16)0x0010) /* Configuration Flag Enable Mask */
#define CRL_CNF_Reset ((u16)0xFFEF) /* Configuration Flag Disable Mask */
#define RTC_LSB_Mask ((u32)0x0000FFFF) /* RTC LSB Mask */
#define PRLH_MSB_Mask ((u32)0x000F0000) /* RTC Prescaler MSB Mask */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : RTC_ITConfig
* Description : Enables or disables the specified RTC interrupts.
* Input : - RTC_IT: specifies the RTC interrupts sources to be enabled
* or disabled.
* This parameter can be any combination of the following values:
* - RTC_IT_OW: Overflow interrupt
* - RTC_IT_ALR: Alarm interrupt
* - RTC_IT_SEC: Second interrupt
* - NewState: new state of the specified RTC interrupts.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void RTC_ITConfig(u16 RTC_IT, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_RTC_IT(RTC_IT));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
RTC->CRH |= RTC_IT;
}
else
{
RTC->CRH &= (u16)~RTC_IT;
}
}
/*******************************************************************************
* Function Name : RTC_EnterConfigMode
* Description : Enters the RTC configuration mode.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void RTC_EnterConfigMode(void)
{
/* Set the CNF flag to enter in the Configuration Mode */
RTC->CRL |= CRL_CNF_Set;
}
/*******************************************************************************
* Function Name : RTC_ExitConfigMode
* Description : Exits from the RTC configuration mode.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void RTC_ExitConfigMode(void)
{
/* Reset the CNF flag to exit from the Configuration Mode */
RTC->CRL &= CRL_CNF_Reset;
}
/*******************************************************************************
* Function Name : RTC_GetCounter
* Description : Gets the RTC counter value.
* Input : None
* Output : None
* Return : RTC counter value.
*******************************************************************************/
u32 RTC_GetCounter(void)
{
u16 tmp = 0;
tmp = RTC->CNTL;
return (((u32)RTC->CNTH << 16 ) | tmp) ;
}
/*******************************************************************************
* Function Name : RTC_SetCounter
* Description : Sets the RTC counter value.
* Input : - CounterValue: RTC counter new value.
* Output : None
* Return : None
*******************************************************************************/
void RTC_SetCounter(u32 CounterValue)
{
RTC_EnterConfigMode();
/* Set RTC COUNTER MSB word */
RTC->CNTH = CounterValue >> 16;
/* Set RTC COUNTER LSB word */
RTC->CNTL = (CounterValue & RTC_LSB_Mask);
RTC_ExitConfigMode();
}
/*******************************************************************************
* Function Name : RTC_SetPrescaler
* Description : Sets the RTC prescaler value.
* Input : - PrescalerValue: RTC prescaler new value.
* Output : None
* Return : None
*******************************************************************************/
void RTC_SetPrescaler(u32 PrescalerValue)
{
/* Check the parameters */
assert_param(IS_RTC_PRESCALER(PrescalerValue));
RTC_EnterConfigMode();
/* Set RTC PRESCALER MSB word */
RTC->PRLH = (PrescalerValue & PRLH_MSB_Mask) >> 16;
/* Set RTC PRESCALER LSB word */
RTC->PRLL = (PrescalerValue & RTC_LSB_Mask);
RTC_ExitConfigMode();
}
/*******************************************************************************
* Function Name : RTC_SetAlarm
* Description : Sets the RTC alarm value.
* Input : - AlarmValue: RTC alarm new value.
* Output : None
* Return : None
*******************************************************************************/
void RTC_SetAlarm(u32 AlarmValue)
{
RTC_EnterConfigMode();
/* Set the ALARM MSB word */
RTC->ALRH = AlarmValue >> 16;
/* Set the ALARM LSB word */
RTC->ALRL = (AlarmValue & RTC_LSB_Mask);
RTC_ExitConfigMode();
}
/*******************************************************************************
* Function Name : RTC_GetDivider
* Description : Gets the RTC divider value.
* Input : None
* Output : None
* Return : RTC Divider value.
*******************************************************************************/
u32 RTC_GetDivider(void)
{
u32 tmp = 0x00;
tmp = ((u32)RTC->DIVH & (u32)0x000F) << 16;
tmp |= RTC->DIVL;
return tmp;
}
/*******************************************************************************
* Function Name : RTC_WaitForLastTask
* Description : Waits until last write operation on RTC registers has finished.
* This function must be called before any write to RTC registers.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void RTC_WaitForLastTask(void)
{
/* Loop until RTOFF flag is set */
while ((RTC->CRL & RTC_FLAG_RTOFF) == (u16)RESET)
{
}
}
/*******************************************************************************
* Function Name : RTC_WaitForSynchro
* Description : Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL)
* are synchronized with RTC APB clock.
* This function must be called before any read operation after
* an APB reset or an APB clock stop.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void RTC_WaitForSynchro(void)
{
/* Clear RSF flag */
RTC->CRL &= (u16)~RTC_FLAG_RSF;
/* Loop until RSF flag is set */
while ((RTC->CRL & RTC_FLAG_RSF) == (u16)RESET)
{
}
}
/*******************************************************************************
* Function Name : RTC_GetFlagStatus
* Description : Checks whether the specified RTC flag is set or not.
* Input : - RTC_FLAG: specifies the flag to check.
* This parameter can be one the following values:
* - RTC_FLAG_RTOFF: RTC Operation OFF flag
* - RTC_FLAG_RSF: Registers Synchronized flag
* - RTC_FLAG_OW: Overflow flag
* - RTC_FLAG_ALR: Alarm flag
* - RTC_FLAG_SEC: Second flag
* Output : None
* Return : The new state of RTC_FLAG (SET or RESET).
*******************************************************************************/
FlagStatus RTC_GetFlagStatus(u16 RTC_FLAG)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_RTC_GET_FLAG(RTC_FLAG));
if ((RTC->CRL & RTC_FLAG) != (u16)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*******************************************************************************
* Function Name : RTC_ClearFlag
* Description : Clears the RTC’s pending flags.
* Input : - RTC_FLAG: specifies the flag to clear.
* This parameter can be any combination of the following values:
* - RTC_FLAG_RSF: Registers Synchronized flag. This flag
* is cleared only after an APB reset or an APB Clock stop.
* - RTC_FLAG_OW: Overflow flag
* - RTC_FLAG_ALR: Alarm flag
* - RTC_FLAG_SEC: Second flag
* Output : None
* Return : None
*******************************************************************************/
void RTC_ClearFlag(u16 RTC_FLAG)
{
/* Check the parameters */
assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG));
/* Clear the coressponding RTC flag */
RTC->CRL &= (u16)~RTC_FLAG;
}
/*******************************************************************************
* Function Name : RTC_GetITStatus
* Description : Checks whether the specified RTC interrupt has occured or not.
* Input : - RTC_IT: specifies the RTC interrupts sources to check.
* This parameter can be one of the following values:
* - RTC_IT_OW: Overflow interrupt
* - RTC_IT_ALR: Alarm interrupt
* - RTC_IT_SEC: Second interrupt
* Output : None
* Return : The new state of the RTC_IT (SET or RESET).
*******************************************************************************/
ITStatus RTC_GetITStatus(u16 RTC_IT)
{
ITStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_RTC_GET_IT(RTC_IT));
bitstatus = (ITStatus)(RTC->CRL & RTC_IT);
if (((RTC->CRH & RTC_IT) != (u16)RESET) && (bitstatus != (u16)RESET))
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*******************************************************************************
* Function Name : RTC_ClearITPendingBit
* Description : Clears the RTC’s interrupt pending bits.
* Input : - RTC_IT: specifies the interrupt pending bit to clear.
* This parameter can be any combination of the following values:
* - RTC_IT_OW: Overflow interrupt
* - RTC_IT_ALR: Alarm interrupt
* - RTC_IT_SEC: Second interrupt
* Output : None
* Return : None
*******************************************************************************/
void RTC_ClearITPendingBit(u16 RTC_IT)
{
/* Check the parameters */
assert_param(IS_RTC_IT(RTC_IT));
/* Clear the coressponding RTC pending bit */
RTC->CRL &= (u16)~RTC_IT;
}
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

832
bsp/stm32f103vb_lwip/library/src/stm32f10x_sdio.c Normal file
View File

@ -0,0 +1,832 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_sdio.c
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file provides all the SDIO firmware functions.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_sdio.h"
#include "stm32f10x_rcc.h"
/* Private typedef -----------------------------------------------------------*/
/* ------------ SDIO registers bit address in the alias region ----------- */
#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
/* --- CLKCR Register ---*/
/* Alias word address of CLKEN bit */
#define CLKCR_OFFSET (SDIO_OFFSET + 0x04)
#define CLKEN_BitNumber 0x08
#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
/* --- CMD Register ---*/
/* Alias word address of SDIOSUSPEND bit */
#define CMD_OFFSET (SDIO_OFFSET + 0x0C)
#define SDIOSUSPEND_BitNumber 0x0B
#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
/* Alias word address of ENCMDCOMPL bit */
#define ENCMDCOMPL_BitNumber 0x0C
#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
/* Alias word address of NIEN bit */
#define NIEN_BitNumber 0x0D
#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
/* Alias word address of ATACMD bit */
#define ATACMD_BitNumber 0x0E
#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
/* --- DCTRL Register ---*/
/* Alias word address of DMAEN bit */
#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
#define DMAEN_BitNumber 0x03
#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
/* Alias word address of RWSTART bit */
#define RWSTART_BitNumber 0x08
#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
/* Alias word address of RWSTOP bit */
#define RWSTOP_BitNumber 0x09
#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
/* Alias word address of RWMOD bit */
#define RWMOD_BitNumber 0x0A
#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
/* Alias word address of SDIOEN bit */
#define SDIOEN_BitNumber 0x0B
#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
/* ---------------------- SDIO registers bit mask ------------------------ */
/* --- CLKCR Register ---*/
/* CLKCR register clear mask */
#define CLKCR_CLEAR_MASK ((u32)0xFFFF8100)
/* --- PWRCTRL Register ---*/
/* SDIO PWRCTRL Mask */
#define PWR_PWRCTRL_MASK ((u32)0xFFFFFFFC)
/* --- DCTRL Register ---*/
/* SDIO DCTRL Clear Mask */
#define DCTRL_CLEAR_MASK ((u32)0xFFFFFF08)
/* --- CMD Register ---*/
/* CMD Register clear mask */
#define CMD_CLEAR_MASK ((u32)0xFFFFF800)
/* SDIO RESP Registers Address */
#define SDIO_RESP_ADDR ((u32)(SDIO_BASE + 0x14))
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : SDIO_DeInit
* Description : Deinitializes the SDIO peripheral registers to their default
* reset values.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void SDIO_DeInit(void)
{
SDIO->POWER = 0x00000000;
SDIO->CLKCR = 0x00000000;
SDIO->ARG = 0x00000000;
SDIO->CMD = 0x00000000;
SDIO->DTIMER = 0x00000000;
SDIO->DLEN = 0x00000000;
SDIO->DCTRL = 0x00000000;
SDIO->ICR = 0x00C007FF;
SDIO->MASK = 0x00000000;
}
/*******************************************************************************
* Function Name : SDIO_Init
* Description : Initializes the SDIO peripheral according to the specified
* parameters in the SDIO_InitStruct.
* Input : SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure
* that contains the configuration information for the SDIO
* peripheral.
* Output : None
* Return : None
*******************************************************************************/
void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)
{
u32 tmpreg = 0;
/* Check the parameters */
assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge));
assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass));
assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave));
assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide));
assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl));
/*---------------------------- SDIO CLKCR Configuration ------------------------*/
/* Get the SDIO CLKCR value */
tmpreg = SDIO->CLKCR;
/* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */
tmpreg &= CLKCR_CLEAR_MASK;
/* Set CLKDIV bits according to SDIO_ClockDiv value */
/* Set PWRSAV bit according to SDIO_ClockPowerSave value */
/* Set BYPASS bit according to SDIO_ClockBypass value */
/* Set WIDBUS bits according to SDIO_BusWide value */
/* Set NEGEDGE bits according to SDIO_ClockEdge value */
/* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */
tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave |
SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide |
SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl);
/* Write to SDIO CLKCR */
SDIO->CLKCR = tmpreg;
}
/*******************************************************************************
* Function Name : SDIO_StructInit
* Description : Fills each SDIO_InitStruct member with its default value.
* Input : SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which
* will be initialized.
* Output : None
* Return : None
*******************************************************************************/
void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct)
{
/* SDIO_InitStruct members default value */
SDIO_InitStruct->SDIO_ClockDiv = 0x00;
SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising;
SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable;
SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b;
SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
}
/*******************************************************************************
* Function Name : SDIO_ClockCmd
* Description : Enables or disables the SDIO Clock.
* Input : NewState: new state of the SDIO Clock.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void SDIO_ClockCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(vu32 *) CLKCR_CLKEN_BB = (u32)NewState;
}
/*******************************************************************************
* Function Name : SDIO_SetPowerState
* Description : Sets the power status of the controller.
* Input : SDIO_PowerState: new state of the Power state.
* This parameter can be one of the following values:
* - SDIO_PowerState_OFF
* - SDIO_PowerState_ON
* Output : None
* Return : None
*******************************************************************************/
void SDIO_SetPowerState(u32 SDIO_PowerState)
{
/* Check the parameters */
assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState));
SDIO->POWER &= PWR_PWRCTRL_MASK;
SDIO->POWER |= SDIO_PowerState;
}
/*******************************************************************************
* Function Name : SDIO_GetPowerState
* Description : Gets the power status of the controller.
* Input : None
* Output : None
* Return : Power status of the controller. The returned value can
* be one of the following:
* - 0x00: Power OFF
* - 0x02: Power UP
* - 0x03: Power ON
*******************************************************************************/
u32 SDIO_GetPowerState(void)
{
return (SDIO->POWER & (~PWR_PWRCTRL_MASK));
}
/*******************************************************************************
* Function Name : SDIO_ITConfig
* Description : Enables or disables the SDIO interrupts.
* Input : - SDIO_IT: specifies the SDIO interrupt sources to be
* enabled or disabled.
* This parameter can be one or a combination of the following
* values:
* - SDIO_IT_CCRCFAIL: Command response received (CRC check
* failed) interrupt
* - SDIO_IT_DCRCFAIL: Data block sent/received (CRC check
* failed) interrupt
* - SDIO_IT_CTIMEOUT: Command response timeout interrupt
* - SDIO_IT_DTIMEOUT: Data timeout interrupt
* - SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
* - SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
* - SDIO_IT_CMDREND: Command response received (CRC check
* passed) interrupt
* - SDIO_IT_CMDSENT: Command sent (no response required)
* interrupt
* - SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is
* zero) interrupt
* - SDIO_IT_STBITERR: Start bit not detected on all data
* signals in wide bus mode interrupt
* - SDIO_IT_DBCKEND: Data block sent/received (CRC check
* passed) interrupt
* - SDIO_IT_CMDACT: Command transfer in progress interrupt
* - SDIO_IT_TXACT: Data transmit in progress interrupt
* - SDIO_IT_RXACT: Data receive in progress interrupt
* - SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
* - SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
* - SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
* - SDIO_IT_RXFIFOF: Receive FIFO full interrupt
* - SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
* - SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
* - SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
* - SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
* - SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
* - SDIO_IT_CEATAEND: CE-ATA command completion signal
* received for CMD61 interrupt
* - NewState: new state of the specified SDIO interrupts.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void SDIO_ITConfig(u32 SDIO_IT, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_SDIO_IT(SDIO_IT));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the SDIO interrupts */
SDIO->MASK |= SDIO_IT;
}
else
{
/* Disable the SDIO interrupts */
SDIO->MASK &= ~SDIO_IT;
}
}
/*******************************************************************************
* Function Name : SDIO_DMACmd
* Description : Enables or disables the SDIO DMA request.
* Input : NewState: new state of the selected SDIO DMA request.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void SDIO_DMACmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(vu32 *) DCTRL_DMAEN_BB = (u32)NewState;
}
/*******************************************************************************
* Function Name : SDIO_SendCommand
* Description : Initializes the SDIO Command according to the specified
* parameters in the SDIO_CmdInitStruct and send the command.
* Input : SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef
* structure that contains the configuration information
* for the SDIO command.
* Output : None
* Return : None
*******************************************************************************/
void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
{
u32 tmpreg = 0;
/* Check the parameters */
assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex));
assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response));
assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait));
assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM));
/*---------------------------- SDIO ARG Configuration ------------------------*/
/* Set the SDIO Argument value */
SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument;
/*---------------------------- SDIO CMD Configuration ------------------------*/
/* Get the SDIO CMD value */
tmpreg = SDIO->CMD;
/* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */
tmpreg &= CMD_CLEAR_MASK;
/* Set CMDINDEX bits according to SDIO_CmdIndex value */
/* Set WAITRESP bits according to SDIO_Response value */
/* Set WAITINT and WAITPEND bits according to SDIO_Wait value */
/* Set CPSMEN bits according to SDIO_CPSM value */
tmpreg |= (u32)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response
| SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM;
/* Write to SDIO CMD */
SDIO->CMD = tmpreg;
}
/*******************************************************************************
* Function Name : SDIO_CmdStructInit
* Description : Fills each SDIO_CmdInitStruct member with its default value.
* Input : SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef
* structure which will be initialized.
* Output : None
* Return : None
*******************************************************************************/
void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct)
{
/* SDIO_CmdInitStruct members default value */
SDIO_CmdInitStruct->SDIO_Argument = 0x00;
SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00;
SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No;
SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;
SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;
}
/*******************************************************************************
* Function Name : SDIO_GetCommandResponse
* Description : Returns command index of last command for which response
* received.
* Input : None
* Output : None
* Return : Returns the command index of the last command response received.
*******************************************************************************/
u8 SDIO_GetCommandResponse(void)
{
return (u8)(SDIO->RESPCMD);
}
/*******************************************************************************
* Function Name : SDIO_GetResponse
* Description : Returns response received from the card for the last command.
* Input : - SDIO_RESP: Specifies the SDIO response register.
* This parameter can be one of the following values:
* - SDIO_RESP1: Response Register 1
* - SDIO_RESP2: Response Register 2
* - SDIO_RESP3: Response Register 3
* - SDIO_RESP4: Response Register 4
* Output : None
* Return : The Corresponding response register value.
*******************************************************************************/
u32 SDIO_GetResponse(u32 SDIO_RESP)
{
/* Check the parameters */
assert_param(IS_SDIO_RESP(SDIO_RESP));
return (*(vu32 *)(SDIO_RESP_ADDR + SDIO_RESP));
}
/*******************************************************************************
* Function Name : SDIO_DataConfig
* Description : Initializes the SDIO data path according to the specified
* parameters in the SDIO_DataInitStruct.
* Input : SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef
* structure that contains the configuration information
* for the SDIO command.
* Output : None
* Return : None
*******************************************************************************/
void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
{
u32 tmpreg = 0;
/* Check the parameters */
assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength));
assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize));
assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir));
assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode));
assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM));
/*---------------------------- SDIO DTIMER Configuration ---------------------*/
/* Set the SDIO Data TimeOut value */
SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut;
/*---------------------------- SDIO DLEN Configuration -----------------------*/
/* Set the SDIO DataLength value */
SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength;
/*---------------------------- SDIO DCTRL Configuration ----------------------*/
/* Get the SDIO DCTRL value */
tmpreg = SDIO->DCTRL;
/* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */
tmpreg &= DCTRL_CLEAR_MASK;
/* Set DEN bit according to SDIO_DPSM value */
/* Set DTMODE bit according to SDIO_TransferMode value */
/* Set DTDIR bit according to SDIO_TransferDir value */
/* Set DBCKSIZE bits according to SDIO_DataBlockSize value */
tmpreg |= (u32)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir
| SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM;
/* Write to SDIO DCTRL */
SDIO->DCTRL = tmpreg;
}
/*******************************************************************************
* Function Name : SDIO_DataStructInit
* Description : Fills each SDIO_DataInitStruct member with its default value.
* Input : SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef
* structure which will be initialized.
* Output : None
* Return : None
*******************************************************************************/
void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
{
/* SDIO_DataInitStruct members default value */
SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF;
SDIO_DataInitStruct->SDIO_DataLength = 0x00;
SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b;
SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard;
SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block;
SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable;
}
/*******************************************************************************
* Function Name : SDIO_GetDataCounter
* Description : Returns number of remaining data bytes to be transferred.
* Input : None
* Output : None
* Return : Number of remaining data bytes to be transferred
*******************************************************************************/
u32 SDIO_GetDataCounter(void)
{
return SDIO->DCOUNT;
}
/*******************************************************************************
* Function Name : SDIO_ReadData
* Description : Read one data word from Rx FIFO.
* Input : None
* Output : None
* Return : Data received
*******************************************************************************/
u32 SDIO_ReadData(void)
{
return SDIO->FIFO;
}
/*******************************************************************************
* Function Name : SDIO_WriteData
* Description : Write one data word to Tx FIFO.
* Input : Data: 32-bit data word to write.
* Output : None
* Return : None
*******************************************************************************/
void SDIO_WriteData(u32 Data)
{
SDIO->FIFO = Data;
}
/*******************************************************************************
* Function Name : SDIO_GetFIFOCount
* Description : Returns the number of words left to be written to or read
* from FIFO.
* Input : None
* Output : None
* Return : Remaining number of words.
*******************************************************************************/
u32 SDIO_GetFIFOCount(void)
{
return SDIO->FIFOCNT;
}
/*******************************************************************************
* Function Name : SDIO_StartSDIOReadWait
* Description : Starts the SD I/O Read Wait operation.
* Input : NewState: new state of the Start SDIO Read Wait operation.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void SDIO_StartSDIOReadWait(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(vu32 *) DCTRL_RWSTART_BB = (u32) NewState;
}
/*******************************************************************************
* Function Name : SDIO_StopSDIOReadWait
* Description : Stops the SD I/O Read Wait operation.
* Input : NewState: new state of the Stop SDIO Read Wait operation.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void SDIO_StopSDIOReadWait(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(vu32 *) DCTRL_RWSTOP_BB = (u32) NewState;
}
/*******************************************************************************
* Function Name : SDIO_SetSDIOReadWaitMode
* Description : Sets one of the two options of inserting read wait interval.
* Input : SDIOReadWaitMode: SD I/O Read Wait operation mode.
* This parametre can be:
* - SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK
* - SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2
* Output : None
* Return : None
*******************************************************************************/
void SDIO_SetSDIOReadWaitMode(u32 SDIO_ReadWaitMode)
{
/* Check the parameters */
assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));
*(vu32 *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode;
}
/*******************************************************************************
* Function Name : SDIO_SetSDIOOperation
* Description : Enables or disables the SD I/O Mode Operation.
* Input : NewState: new state of SDIO specific operation.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void SDIO_SetSDIOOperation(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(vu32 *) DCTRL_SDIOEN_BB = (u32)NewState;
}
/*******************************************************************************
* Function Name : SDIO_SendSDIOSuspendCmd
* Description : Enables or disables the SD I/O Mode suspend command sending.
* Input : NewState: new state of the SD I/O Mode suspend command.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void SDIO_SendSDIOSuspendCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(vu32 *) CMD_SDIOSUSPEND_BB = (u32)NewState;
}
/*******************************************************************************
* Function Name : SDIO_CommandCompletionCmd
* Description : Enables or disables the command completion signal.
* Input : NewState: new state of command completion signal.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void SDIO_CommandCompletionCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(vu32 *) CMD_ENCMDCOMPL_BB = (u32)NewState;
}
/*******************************************************************************
* Function Name : SDIO_CEATAITCmd
* Description : Enables or disables the CE-ATA interrupt.
* Input : NewState: new state of CE-ATA interrupt.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void SDIO_CEATAITCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(vu32 *) CMD_NIEN_BB = (u32)((~((u32)NewState)) & ((u32)0x1));
}
/*******************************************************************************
* Function Name : SDIO_SendCEATACmd
* Description : Sends CE-ATA command (CMD61).
* Input : NewState: new state of CE-ATA command.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void SDIO_SendCEATACmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(vu32 *) CMD_ATACMD_BB = (u32)NewState;
}
/*******************************************************************************
* Function Name : SDIO_GetFlagStatus
* Description : Checks whether the specified SDIO flag is set or not.
* Input : SDIO_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* - SDIO_FLAG_CCRCFAIL: Command response received (CRC check
* failed)
* - SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check
* failed)
* - SDIO_FLAG_CTIMEOUT: Command response timeout
* - SDIO_FLAG_DTIMEOUT: Data timeou
* - SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
* - SDIO_FLAG_RXOVERR: Received FIFO overrun error
* - SDIO_FLAG_CMDREND: Command response received (CRC check
* passed)
* - SDIO_FLAG_CMDSENT: Command sent (no response required)
* - SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is
* zero)
* - SDIO_FLAG_STBITERR: Start bit not detected on all data
* signals in wide bus mode
* - SDIO_FLAG_DBCKEND: Data block sent/received (CRC check
* passed)
* - SDIO_FLAG_CMDACT: Command transfer in progress
* - SDIO_FLAG_TXACT: Data transmit in progress
* - SDIO_FLAG_RXACT: Data receive in progress
* - SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
* - SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
* - SDIO_FLAG_TXFIFOF: Transmit FIFO full
* - SDIO_FLAG_RXFIFOF: Receive FIFO full
* - SDIO_FLAG_TXFIFOE: Transmit FIFO empty
* - SDIO_FLAG_RXFIFOE: Receive FIFO empty
* - SDIO_FLAG_TXDAVL: Data available in transmit FIFO
* - SDIO_FLAG_RXDAVL: Data available in receive FIFO
* - SDIO_FLAG_SDIOIT: SD I/O interrupt received
* - SDIO_FLAG_CEATAEND: CE-ATA command completion signal
* received for CMD61
* Output : None
* Return : The new state of SDIO_FLAG (SET or RESET).
*******************************************************************************/
FlagStatus SDIO_GetFlagStatus(u32 SDIO_FLAG)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_SDIO_FLAG(SDIO_FLAG));
if ((SDIO->STA & SDIO_FLAG) != (u32)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*******************************************************************************
* Function Name : SDIO_ClearFlag
* Description : Clears the SDIO's pending flags.
* Input : SDIO_FLAG: specifies the flag to clear.
* This parameter can be one or a combination of the following
* values:
* - SDIO_FLAG_CCRCFAIL: Command response received (CRC check
* failed)
* - SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check
* failed)
* - SDIO_FLAG_CTIMEOUT: Command response timeout
* - SDIO_FLAG_DTIMEOUT: Data timeou
* - SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
* - SDIO_FLAG_RXOVERR: Received FIFO overrun error
* - SDIO_FLAG_CMDREND: Command response received (CRC check
* passed)
* - SDIO_FLAG_CMDSENT: Command sent (no response required)
* - SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is
* zero)
* - SDIO_FLAG_STBITERR: Start bit not detected on all data
* signals in wide bus mode
* - SDIO_FLAG_DBCKEND: Data block sent/received (CRC check
* passed)
* - SDIO_FLAG_SDIOIT: SD I/O interrupt received
* - SDIO_FLAG_CEATAEND: CE-ATA command completion signal
* received for CMD61
* Output : None
* Return : None
*******************************************************************************/
void SDIO_ClearFlag(u32 SDIO_FLAG)
{
/* Check the parameters */
assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG));
SDIO->ICR = SDIO_FLAG;
}
/*******************************************************************************
* Function Name : SDIO_GetITStatus
* Description : Checks whether the specified SDIO interrupt has occurred or not.
* Input : SDIO_IT: specifies the SDIO interrupt source to check.
* This parameter can be one of the following values:
* - SDIO_IT_CCRCFAIL: Command response received (CRC check
* failed) interrupt
* - SDIO_IT_DCRCFAIL: Data block sent/received (CRC check
* failed) interrupt
* - SDIO_IT_CTIMEOUT: Command response timeout interrupt
* - SDIO_IT_DTIMEOUT: Data timeout interrupt
* - SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
* - SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
* - SDIO_IT_CMDREND: Command response received (CRC check
* passed) interrupt
* - SDIO_IT_CMDSENT: Command sent (no response required)
* interrupt
* - SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is
* zero) interrupt
* - SDIO_IT_STBITERR: Start bit not detected on all data
* signals in wide bus mode interrupt
* - SDIO_IT_DBCKEND: Data block sent/received (CRC check
* passed) interrupt
* - SDIO_IT_CMDACT: Command transfer in progress interrupt
* - SDIO_IT_TXACT: Data transmit in progress interrupt
* - SDIO_IT_RXACT: Data receive in progress interrupt
* - SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
* - SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
* - SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
* - SDIO_IT_RXFIFOF: Receive FIFO full interrupt
* - SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
* - SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
* - SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
* - SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
* - SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
* - SDIO_IT_CEATAEND: CE-ATA command completion signal
* received for CMD61 interrupt
* Output : None
* Return : The new state of SDIO_IT (SET or RESET).
*******************************************************************************/
ITStatus SDIO_GetITStatus(u32 SDIO_IT)
{
ITStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_SDIO_GET_IT(SDIO_IT));
if ((SDIO->STA & SDIO_IT) != (u32)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*******************************************************************************
* Function Name : SDIO_ClearITPendingBit
* Description : Clears the SDIO’s interrupt pending bits.
* Input : SDIO_IT: specifies the interrupt pending bit to clear.
* This parameter can be one or a combination of the following
* values:
* - SDIO_IT_CCRCFAIL: Command response received (CRC check
* failed) interrupt
* - SDIO_IT_DCRCFAIL: Data block sent/received (CRC check
* failed) interrupt
* - SDIO_IT_CTIMEOUT: Command response timeout interrupt
* - SDIO_IT_DTIMEOUT: Data timeout interrupt
* - SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
* - SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
* - SDIO_IT_CMDREND: Command response received (CRC check
* passed) interrupt
* - SDIO_IT_CMDSENT: Command sent (no response required)
* interrupt
* - SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is
* zero) interrupt
* - SDIO_IT_STBITERR: Start bit not detected on all data
* signals in wide bus mode interrupt
* - SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
* - SDIO_IT_CEATAEND: CE-ATA command completion signal
* received for CMD61
* Output : None
* Return : None
*******************************************************************************/
void SDIO_ClearITPendingBit(u32 SDIO_IT)
{
/* Check the parameters */
assert_param(IS_SDIO_CLEAR_IT(SDIO_IT));
SDIO->ICR = SDIO_IT;
}
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

863
bsp/stm32f103vb_lwip/library/src/stm32f10x_spi.c Normal file
View File

@ -0,0 +1,863 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_spi.c
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file provides all the SPI firmware functions.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_spi.h"
#include "stm32f10x_rcc.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* SPI SPE mask */
#define CR1_SPE_Set ((u16)0x0040)
#define CR1_SPE_Reset ((u16)0xFFBF)
/* I2S I2SE mask */
#define I2SCFGR_I2SE_Set ((u16)0x0400)
#define I2SCFGR_I2SE_Reset ((u16)0xFBFF)
/* SPI CRCNext mask */
#define CR1_CRCNext_Set ((u16)0x1000)
/* SPI CRCEN mask */
#define CR1_CRCEN_Set ((u16)0x2000)
#define CR1_CRCEN_Reset ((u16)0xDFFF)
/* SPI SSOE mask */
#define CR2_SSOE_Set ((u16)0x0004)
#define CR2_SSOE_Reset ((u16)0xFFFB)
/* SPI registers Masks */
#define CR1_CLEAR_Mask ((u16)0x3040)
#define I2SCFGR_CLEAR_Mask ((u16)0xF040)
/* SPI or I2S mode selection masks */
#define SPI_Mode_Select ((u16)0xF7FF)
#define I2S_Mode_Select ((u16)0x0800)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : SPI_I2S_DeInit
* Description : Deinitializes the SPIx peripheral registers to their default
* reset values (Affects also the I2Ss).
* Input : - SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
* Output : None
* Return : None
*******************************************************************************/
void SPI_I2S_DeInit(SPI_TypeDef* SPIx)
{
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
switch (*(u32*)&SPIx)
{
case SPI1_BASE:
/* Enable SPI1 reset state */
RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
/* Release SPI1 from reset state */
RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
break;
case SPI2_BASE:
/* Enable SPI2 reset state */
RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
/* Release SPI2 from reset state */
RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
break;
case SPI3_BASE:
/* Enable SPI3 reset state */
RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
/* Release SPI3 from reset state */
RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);
break;
default:
break;
}
}
/*******************************************************************************
* Function Name : SPI_Init
* Description : Initializes the SPIx peripheral according to the specified
* parameters in the SPI_InitStruct.
* Input : - SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
* - SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
* contains the configuration information for the specified
* SPI peripheral.
* Output : None
* Return : None
******************************************************************************/
void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
{
u16 tmpreg = 0;
/* check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
/* Check the SPI parameters */
assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));
assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));
/*---------------------------- SPIx CR1 Configuration ------------------------*/
/* Get the SPIx CR1 value */
tmpreg = SPIx->CR1;
/* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
tmpreg &= CR1_CLEAR_Mask;
/* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
master/salve mode, CPOL and CPHA */
/* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
/* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
/* Set LSBFirst bit according to SPI_FirstBit value */
/* Set BR bits according to SPI_BaudRatePrescaler value */
/* Set CPOL bit according to SPI_CPOL value */
/* Set CPHA bit according to SPI_CPHA value */
tmpreg |= (u16)((u32)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |
SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |
SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |
SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);
/* Write to SPIx CR1 */
SPIx->CR1 = tmpreg;
/* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
SPIx->I2SCFGR &= SPI_Mode_Select;
/*---------------------------- SPIx CRCPOLY Configuration --------------------*/
/* Write to SPIx CRCPOLY */
SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
}
/*******************************************************************************
* Function Name : I2S_Init
* Description : Initializes the SPIx peripheral according to the specified
* parameters in the I2S_InitStruct.
* Input : - SPIx: where x can be 2 or 3 to select the SPI peripheral
* (configured in I2S mode).
* - I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
* contains the configuration information for the specified
* SPI peripheral configured in I2S mode.
* Output : None
* Return : None
******************************************************************************/
void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
{
u16 tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
u32 tmp = 0;
RCC_ClocksTypeDef RCC_Clocks;
/* Check the I2S parameters */
assert_param(IS_SPI_23_PERIPH(SPIx));
assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));
assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));
assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));
/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
/* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask;
SPIx->I2SPR = 0x0002;
/* Get the I2SCFGR register value */
tmpreg = SPIx->I2SCFGR;
/* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
{
i2sodd = (u16)0;
i2sdiv = (u16)2;
}
/* If the requested audio frequency is not the default, compute the prescaler */
else
{
/* Check the frame length (For the Prescaler computing) */
if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
{
/* Packet length is 16 bits */
packetlength = 1;
}
else
{
/* Packet length is 32 bits */
packetlength = 2;
}
/* Get System Clock frequency */
RCC_GetClocksFreq(&RCC_Clocks);
/* Compute the Real divider depending on the MCLK output state with a flaoting point */
if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
{
/* MCLK output is enabled */
tmp = (u16)(((10 * RCC_Clocks.SYSCLK_Frequency) / (256 * I2S_InitStruct->I2S_AudioFreq)) + 5);
}
else
{
/* MCLK output is disabled */
tmp = (u16)(((10 * RCC_Clocks.SYSCLK_Frequency) / (32 * packetlength * I2S_InitStruct->I2S_AudioFreq)) + 5);
}
/* Remove the flaoting point */
tmp = tmp/10;
/* Check the parity of the divider */
i2sodd = (u16)(tmp & (u16)0x0001);
/* Compute the i2sdiv prescaler */
i2sdiv = (u16)((tmp - i2sodd) / 2);
/* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
i2sodd = (u16) (i2sodd << 8);
}
/* Test if the divider is 1 or 0 */
if ((i2sdiv < 2) || (i2sdiv > 0xFF))
{
/* Set the default values */
i2sdiv = 2;
i2sodd = 0;
}
/* Write to SPIx I2SPR register the computed value */
SPIx->I2SPR = (u16)(i2sdiv | i2sodd | I2S_InitStruct->I2S_MCLKOutput);
/* Configure the I2S with the SPI_InitStruct values */
tmpreg |= (u16)(I2S_Mode_Select | I2S_InitStruct->I2S_Mode | \
I2S_InitStruct->I2S_Standard | I2S_InitStruct->I2S_DataFormat | \
I2S_InitStruct->I2S_CPOL);
/* Write to SPIx I2SCFGR */
SPIx->I2SCFGR = tmpreg;
}
/*******************************************************************************
* Function Name : SPI_StructInit
* Description : Fills each SPI_InitStruct member with its default value.
* Input : - SPI_InitStruct : pointer to a SPI_InitTypeDef structure
* which will be initialized.
* Output : None
* Return : None
*******************************************************************************/
void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
{
/*--------------- Reset SPI init structure parameters values -----------------*/
/* Initialize the SPI_Direction member */
SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
/* initialize the SPI_Mode member */
SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
/* initialize the SPI_DataSize member */
SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
/* Initialize the SPI_CPOL member */
SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
/* Initialize the SPI_CPHA member */
SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
/* Initialize the SPI_NSS member */
SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;
/* Initialize the SPI_BaudRatePrescaler member */
SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
/* Initialize the SPI_FirstBit member */
SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
/* Initialize the SPI_CRCPolynomial member */
SPI_InitStruct->SPI_CRCPolynomial = 7;
}
/*******************************************************************************
* Function Name : I2S_StructInit
* Description : Fills each I2S_InitStruct member with its default value.
* Input : - I2S_InitStruct : pointer to a I2S_InitTypeDef structure
* which will be initialized.
* Output : None
* Return : None
*******************************************************************************/
void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)
{
/*--------------- Reset I2S init structure parameters values -----------------*/
/* Initialize the I2S_Mode member */
I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
/* Initialize the I2S_Standard member */
I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
/* Initialize the I2S_DataFormat member */
I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
/* Initialize the I2S_MCLKOutput member */
I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
/* Initialize the I2S_AudioFreq member */
I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
/* Initialize the I2S_CPOL member */
I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
}
/*******************************************************************************
* Function Name : SPI_Cmd
* Description : Enables or disables the specified SPI peripheral.
* Input : - SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
* - NewState: new state of the SPIx peripheral.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected SPI peripheral */
SPIx->CR1 |= CR1_SPE_Set;
}
else
{
/* Disable the selected SPI peripheral */
SPIx->CR1 &= CR1_SPE_Reset;
}
}
/*******************************************************************************
* Function Name : I2S_Cmd
* Description : Enables or disables the specified SPI peripheral (in I2S mode).
* Input : - SPIx: where x can be 2 or 3 to select the SPI peripheral.
* - NewState: new state of the SPIx peripheral.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_SPI_23_PERIPH(SPIx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected SPI peripheral (in I2S mode) */
SPIx->I2SCFGR |= I2SCFGR_I2SE_Set;
}
else
{
/* Disable the selected SPI peripheral (in I2S mode) */
SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset;
}
}
/*******************************************************************************
* Function Name : SPI_I2S_ITConfig
* Description : Enables or disables the specified SPI/I2S interrupts.
* Input : - SPIx: where x can be :
* - 1, 2 or 3 in SPI mode
* - 2 or 3 in I2S mode
* - SPI_I2S_IT: specifies the SPI/I2S interrupt source to be
* enabled or disabled.
* This parameter can be one of the following values:
* - SPI_I2S_IT_TXE: Tx buffer empty interrupt mask
* - SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask
* - SPI_I2S_IT_ERR: Error interrupt mask
* - NewState: new state of the specified SPI/I2S interrupt.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, u8 SPI_I2S_IT, FunctionalState NewState)
{
u16 itpos = 0, itmask = 0 ;
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));
/* Get the SPI/I2S IT index */
itpos = SPI_I2S_IT >> 4;
/* Set the IT mask */
itmask = (u16)((u16)1 << itpos);
if (NewState != DISABLE)
{
/* Enable the selected SPI/I2S interrupt */
SPIx->CR2 |= itmask;
}
else
{
/* Disable the selected SPI/I2S interrupt */
SPIx->CR2 &= (u16)~itmask;
}
}
/*******************************************************************************
* Function Name : SPI_I2S_DMACmd
* Description : Enables or disables the SPIx/I2Sx DMA interface.
* Input : - SPIx: where x can be :
* - 1, 2 or 3 in SPI mode
* - 2 or 3 in I2S mode
* - SPI_I2S_DMAReq: specifies the SPI/I2S DMA transfer request
* to be enabled or disabled.
* This parameter can be any combination of the following values:
* - SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request
* - SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request
* - NewState: new state of the selected SPI/I2S DMA transfer
* request.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, u16 SPI_I2S_DMAReq, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq));
if (NewState != DISABLE)
{
/* Enable the selected SPI/I2S DMA requests */
SPIx->CR2 |= SPI_I2S_DMAReq;
}
else
{
/* Disable the selected SPI/I2S DMA requests */
SPIx->CR2 &= (u16)~SPI_I2S_DMAReq;
}
}
/*******************************************************************************
* Function Name : SPI_I2S_SendData
* Description : Transmits a Data through the SPIx/I2Sx peripheral.
* Input : - SPIx: where x can be :
* - 1, 2 or 3 in SPI mode
* - 2 or 3 in I2S mode
* - Data : Data to be transmitted..
* Output : None
* Return : None
*******************************************************************************/
void SPI_I2S_SendData(SPI_TypeDef* SPIx, u16 Data)
{
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
/* Write in the DR register the data to be sent */
SPIx->DR = Data;
}
/*******************************************************************************
* Function Name : SPI_I2S_ReceiveData
* Description : Returns the most recent received data by the SPIx/I2Sx peripheral.
* Input : - SPIx: where x can be :
* - 1, 2 or 3 in SPI mode
* - 2 or 3 in I2S mode
* Output : None
* Return : The value of the received data.
*******************************************************************************/
u16 SPI_I2S_ReceiveData(SPI_TypeDef* SPIx)
{
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
/* Return the data in the DR register */
return SPIx->DR;
}
/*******************************************************************************
* Function Name : SPI_NSSInternalSoftwareConfig
* Description : Configures internally by software the NSS pin for the selected
* SPI.
* Input : - SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
* - SPI_NSSInternalSoft: specifies the SPI NSS internal state.
* This parameter can be one of the following values:
* - SPI_NSSInternalSoft_Set: Set NSS pin internally
* - SPI_NSSInternalSoft_Reset: Reset NSS pin internally
* Output : None
* Return : None
*******************************************************************************/
void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, u16 SPI_NSSInternalSoft)
{
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));
if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
{
/* Set NSS pin internally by software */
SPIx->CR1 |= SPI_NSSInternalSoft_Set;
}
else
{
/* Reset NSS pin internally by software */
SPIx->CR1 &= SPI_NSSInternalSoft_Reset;
}
}
/*******************************************************************************
* Function Name : SPI_SSOutputCmd
* Description : Enables or disables the SS output for the selected SPI.
* Input : - SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
* - NewState: new state of the SPIx SS output.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected SPI SS output */
SPIx->CR2 |= CR2_SSOE_Set;
}
else
{
/* Disable the selected SPI SS output */
SPIx->CR2 &= CR2_SSOE_Reset;
}
}
/*******************************************************************************
* Function Name : SPI_DataSizeConfig
* Description : Configures the data size for the selected SPI.
* Input : - SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
* - SPI_DataSize: specifies the SPI data size.
* This parameter can be one of the following values:
* - SPI_DataSize_16b: Set data frame format to 16bit
* - SPI_DataSize_8b: Set data frame format to 8bit
* Output : None
* Return : None
*******************************************************************************/
void SPI_DataSizeConfig(SPI_TypeDef* SPIx, u16 SPI_DataSize)
{
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
assert_param(IS_SPI_DATASIZE(SPI_DataSize));
/* Clear DFF bit */
SPIx->CR1 &= (u16)~SPI_DataSize_16b;
/* Set new DFF bit value */
SPIx->CR1 |= SPI_DataSize;
}
/*******************************************************************************
* Function Name : SPI_TransmitCRC
* Description : Transmit the SPIx CRC value.
* Input : - SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
* Output : None
* Return : None
*******************************************************************************/
void SPI_TransmitCRC(SPI_TypeDef* SPIx)
{
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
/* Enable the selected SPI CRC transmission */
SPIx->CR1 |= CR1_CRCNext_Set;
}
/*******************************************************************************
* Function Name : SPI_CalculateCRC
* Description : Enables or disables the CRC value calculation of the
* transfered bytes.
* Input : - SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
* - NewState: new state of the SPIx CRC value calculation.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected SPI CRC calculation */
SPIx->CR1 |= CR1_CRCEN_Set;
}
else
{
/* Disable the selected SPI CRC calculation */
SPIx->CR1 &= CR1_CRCEN_Reset;
}
}
/*******************************************************************************
* Function Name : SPI_GetCRC
* Description : Returns the transmit or the receive CRC register value for
* the specified SPI.
* Input : - SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
* - SPI_CRC: specifies the CRC register to be read.
* This parameter can be one of the following values:
* - SPI_CRC_Tx: Selects Tx CRC register
* - SPI_CRC_Rx: Selects Rx CRC register
* Output : None
* Return : The selected CRC register value..
*******************************************************************************/
u16 SPI_GetCRC(SPI_TypeDef* SPIx, u8 SPI_CRC)
{
u16 crcreg = 0;
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
assert_param(IS_SPI_CRC(SPI_CRC));
if (SPI_CRC != SPI_CRC_Rx)
{
/* Get the Tx CRC register */
crcreg = SPIx->TXCRCR;
}
else
{
/* Get the Rx CRC register */
crcreg = SPIx->RXCRCR;
}
/* Return the selected CRC register */
return crcreg;
}
/*******************************************************************************
* Function Name : SPI_GetCRCPolynomial
* Description : Returns the CRC Polynomial register value for the specified SPI.
* Input : - SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
* Output : None
* Return : The CRC Polynomial register value.
*******************************************************************************/
u16 SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
{
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
/* Return the CRC polynomial register */
return SPIx->CRCPR;
}
/*******************************************************************************
* Function Name : SPI_BiDirectionalLineConfig
* Description : Selects the data transfer direction in bi-directional mode
* for the specified SPI.
* Input : - SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
* - SPI_Direction: specifies the data transfer direction in
* bi-directional mode.
* This parameter can be one of the following values:
* - SPI_Direction_Tx: Selects Tx transmission direction
* - SPI_Direction_Rx: Selects Rx receive direction
* Output : None
* Return : None
*******************************************************************************/
void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, u16 SPI_Direction)
{
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
assert_param(IS_SPI_DIRECTION(SPI_Direction));
if (SPI_Direction == SPI_Direction_Tx)
{
/* Set the Tx only mode */
SPIx->CR1 |= SPI_Direction_Tx;
}
else
{
/* Set the Rx only mode */
SPIx->CR1 &= SPI_Direction_Rx;
}
}
/*******************************************************************************
* Function Name : SPI_I2S_GetFlagStatus
* Description : Checks whether the specified SPI/I2S flag is set or not.
* Input : - SPIx: where x can be :
* - 1, 2 or 3 in SPI mode
* - 2 or 3 in I2S mode
* - SPI_I2S_FLAG: specifies the SPI/I2S flag to check.
* This parameter can be one of the following values:
* - SPI_I2S_FLAG_TXE: Transmit buffer empty flag.
* - SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.
* - SPI_I2S_FLAG_BSY: Busy flag.
* - SPI_I2S_FLAG_OVR: Overrun flag.
* - SPI_FLAG_MODF: Mode Fault flag.
* - SPI_FLAG_CRCERR: CRC Error flag.
* - I2S_FLAG_UDR: Underrun Error flag.
* - I2S_FLAG_CHSIDE: Channel Side flag.
* Output : None
* Return : The new state of SPI_I2S_FLAG (SET or RESET).
*******************************************************************************/
FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, u16 SPI_I2S_FLAG)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
/* Check the status of the specified SPI/I2S flag */
if ((SPIx->SR & SPI_I2S_FLAG) != (u16)RESET)
{
/* SPI_I2S_FLAG is set */
bitstatus = SET;
}
else
{
/* SPI_I2S_FLAG is reset */
bitstatus = RESET;
}
/* Return the SPI_I2S_FLAG status */
return bitstatus;
}
/*******************************************************************************
* Function Name : SPI_I2S_ClearFlag
* Description : Clears the SPIx CRC Error (CRCERR) flag.
* Input : - SPIx: where x can be :
* - 1, 2 or 3 in SPI mode
* - SPI_I2S_FLAG: specifies the SPI flag to clear.
* This function clears only CRCERR flag.
* Notes:
* - OVR (OverRun error) flag is cleared by software
* sequence: a read operation to SPI_DR register
* (SPI_I2S_ReceiveData()) followed by a read operation
* to SPI_SR register (SPI_I2S_GetFlagStatus()).
* - UDR (UnderRun error) flag is cleared by a read
* operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
* - MODF (Mode Fault) flag is cleared by software sequence:
* a read/write operation to SPI_SR register
* (SPI_I2S_GetFlagStatus()) followed by a write
* operation to SPI_CR1 register (SPI_Cmd() to enable
* the SPI).
* Output : None
* Return : None
*******************************************************************************/
void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, u16 SPI_I2S_FLAG)
{
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG));
/* Clear the selected SPI CRC Error (CRCERR) flag */
SPIx->SR = (u16)~SPI_I2S_FLAG;
}
/*******************************************************************************
* Function Name : SPI_I2S_GetITStatus
* Description : Checks whether the specified SPI/I2S interrupt has occurred or not.
* Input : - SPIx: where x can be :
* - 1, 2 or 3 in SPI mode
* - 2 or 3 in I2S mode
* - SPI_I2S_IT: specifies the SPI/I2S interrupt source to check.
* This parameter can be one of the following values:
* - SPI_I2S_IT_TXE: Transmit buffer empty interrupt.
* - SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.
* - SPI_I2S_IT_OVR: Overrun interrupt.
* - SPI_IT_MODF: Mode Fault interrupt.
* - SPI_IT_CRCERR: CRC Error interrupt.
* - I2S_IT_UDR: Underrun Error interrupt.
* Output : None
* Return : The new state of SPI_I2S_IT (SET or RESET).
*******************************************************************************/
ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, u8 SPI_I2S_IT)
{
ITStatus bitstatus = RESET;
u16 itpos = 0, itmask = 0, enablestatus = 0;
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));
/* Get the SPI/I2S IT index */
itpos = (u16)((u16)0x01 << (SPI_I2S_IT & (u8)0x0F));
/* Get the SPI/I2S IT mask */
itmask = SPI_I2S_IT >> 4;
/* Set the IT mask */
itmask = (u16)((u16)0x01 << itmask);
/* Get the SPI_I2S_IT enable bit status */
enablestatus = (SPIx->CR2 & itmask) ;
/* Check the status of the specified SPI/I2S interrupt */
if (((SPIx->SR & itpos) != (u16)RESET) && enablestatus)
{
/* SPI_I2S_IT is set */
bitstatus = SET;
}
else
{
/* SPI_I2S_IT is reset */
bitstatus = RESET;
}
/* Return the SPI_I2S_IT status */
return bitstatus;
}
/*******************************************************************************
* Function Name : SPI_I2S_ClearITPendingBit
* Description : Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
* Input : - SPIx: where x can be :
* - 1, 2 or 3 in SPI mode
* - SPI_I2S_IT: specifies the SPI interrupt pending bit to clear.
* This function clears only CRCERR intetrrupt pending bit.
* Notes:
* - OVR (OverRun Error) interrupt pending bit is cleared
* by software sequence: a read operation to SPI_DR
* register (SPI_I2S_ReceiveData()) followed by a read
* operation to SPI_SR register (SPI_I2S_GetITStatus()).
* - UDR (UnderRun Error) interrupt pending bit is cleared
* by a read operation to SPI_SR register
* (SPI_I2S_GetITStatus()).
* - MODF (Mode Fault) interrupt pending bit is cleared by
* software sequence: a read/write operation to SPI_SR
* register (SPI_I2S_GetITStatus()) followed by a write
* operation to SPI_CR1 register (SPI_Cmd() to enable the
* SPI).
* Output : None
* Return : None
*******************************************************************************/
void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, u8 SPI_I2S_IT)
{
u16 itpos = 0;
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT));
/* Get the SPI IT index */
itpos = (u16)((u16)0x01 << (SPI_I2S_IT & (u8)0x0F));
/* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */
SPIx->SR = (u16)~itpos;
}
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

181
bsp/stm32f103vb_lwip/library/src/stm32f10x_systick.c Normal file
View File

@ -0,0 +1,181 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_systick.c
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file provides all the SysTick firmware functions.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_systick.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* ---------------------- SysTick registers bit mask -------------------- */
/* CTRL TICKINT Mask */
#define CTRL_TICKINT_Set ((u32)0x00000002)
#define CTRL_TICKINT_Reset ((u32)0xFFFFFFFD)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : SysTick_CLKSourceConfig
* Description : Configures the SysTick clock source.
* Input : - SysTick_CLKSource: specifies the SysTick clock source.
* This parameter can be one of the following values:
* - SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8
* selected as SysTick clock source.
* - SysTick_CLKSource_HCLK: AHB clock selected as
* SysTick clock source.
* Output : None
* Return : None
*******************************************************************************/
void SysTick_CLKSourceConfig(u32 SysTick_CLKSource)
{
/* Check the parameters */
assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
{
SysTick->CTRL |= SysTick_CLKSource_HCLK;
}
else
{
SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
}
}
/*******************************************************************************
* Function Name : SysTick_SetReload
* Description : Sets SysTick Reload value.
* Input : - Reload: SysTick Reload new value.
* This parameter must be a number between 1 and 0xFFFFFF.
* Output : None
* Return : None
*******************************************************************************/
void SysTick_SetReload(u32 Reload)
{
/* Check the parameters */
assert_param(IS_SYSTICK_RELOAD(Reload));
SysTick->LOAD = Reload;
}
/*******************************************************************************
* Function Name : SysTick_CounterCmd
* Description : Enables or disables the SysTick counter.
* Input : - SysTick_Counter: new state of the SysTick counter.
* This parameter can be one of the following values:
* - SysTick_Counter_Disable: Disable counter
* - SysTick_Counter_Enable: Enable counter
* - SysTick_Counter_Clear: Clear counter value to 0
* Output : None
* Return : None
*******************************************************************************/
void SysTick_CounterCmd(u32 SysTick_Counter)
{
/* Check the parameters */
assert_param(IS_SYSTICK_COUNTER(SysTick_Counter));
if (SysTick_Counter == SysTick_Counter_Enable)
{
SysTick->CTRL |= SysTick_Counter_Enable;
}
else if (SysTick_Counter == SysTick_Counter_Disable)
{
SysTick->CTRL &= SysTick_Counter_Disable;
}
else /* SysTick_Counter == SysTick_Counter_Clear */
{
SysTick->VAL = SysTick_Counter_Clear;
}
}
/*******************************************************************************
* Function Name : SysTick_ITConfig
* Description : Enables or disables the SysTick Interrupt.
* Input : - NewState: new state of the SysTick Interrupt.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void SysTick_ITConfig(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
SysTick->CTRL |= CTRL_TICKINT_Set;
}
else
{
SysTick->CTRL &= CTRL_TICKINT_Reset;
}
}
/*******************************************************************************
* Function Name : SysTick_GetCounter
* Description : Gets SysTick counter value.
* Input : None
* Output : None
* Return : SysTick current value
*******************************************************************************/
u32 SysTick_GetCounter(void)
{
return(SysTick->VAL);
}
/*******************************************************************************
* Function Name : SysTick_GetFlagStatus
* Description : Checks whether the specified SysTick flag is set or not.
* Input : - SysTick_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* - SysTick_FLAG_COUNT
* - SysTick_FLAG_SKEW
* - SysTick_FLAG_NOREF
* Output : None
* Return : None
*******************************************************************************/
FlagStatus SysTick_GetFlagStatus(u8 SysTick_FLAG)
{
u32 statusreg = 0, tmp = 0 ;
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_SYSTICK_FLAG(SysTick_FLAG));
/* Get the SysTick register index */
tmp = SysTick_FLAG >> 3;
if (tmp == 2) /* The flag to check is in CTRL register */
{
statusreg = SysTick->CTRL;
}
else /* The flag to check is in CALIB register */
{
statusreg = SysTick->CALIB;
}
if ((statusreg & ((u32)1 << SysTick_FLAG)) != (u32)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

3219
bsp/stm32f103vb_lwip/library/src/stm32f10x_tim.c Normal file
View File

File diff suppressed because it is too large Load Diff

1001
bsp/stm32f103vb_lwip/library/src/stm32f10x_usart.c Normal file
View File

File diff suppressed because it is too large Load Diff

185
bsp/stm32f103vb_lwip/library/src/stm32f10x_wwdg.c Normal file
View File

@ -0,0 +1,185 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_wwdg.c
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file provides all the WWDG firmware functions.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_wwdg.h"
#include "stm32f10x_rcc.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* ----------- WWDG registers bit address in the alias region ----------- */
#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE)
/* Alias word address of EWI bit */
#define CFR_OFFSET (WWDG_OFFSET + 0x04)
#define EWI_BitNumber 0x09
#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))
/* --------------------- WWDG registers bit mask ------------------------ */
/* CR register bit mask */
#define CR_WDGA_Set ((u32)0x00000080)
/* CFR register bit mask */
#define CFR_WDGTB_Mask ((u32)0xFFFFFE7F)
#define CFR_W_Mask ((u32)0xFFFFFF80)
#define BIT_Mask ((u8)0x7F)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : WWDG_DeInit
* Description : Deinitializes the WWDG peripheral registers to their default
* reset values.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void WWDG_DeInit(void)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
}
/*******************************************************************************
* Function Name : WWDG_SetPrescaler
* Description : Sets the WWDG Prescaler.
* Input : - WWDG_Prescaler: specifies the WWDG Prescaler.
* This parameter can be one of the following values:
* - WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
* - WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
* - WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
* - WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
* Output : None
* Return : None
*******************************************************************************/
void WWDG_SetPrescaler(u32 WWDG_Prescaler)
{
u32 tmpreg = 0;
/* Check the parameters */
assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));
/* Clear WDGTB[1:0] bits */
tmpreg = WWDG->CFR & CFR_WDGTB_Mask;
/* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
tmpreg |= WWDG_Prescaler;
/* Store the new value */
WWDG->CFR = tmpreg;
}
/*******************************************************************************
* Function Name : WWDG_SetWindowValue
* Description : Sets the WWDG window value.
* Input : - WindowValue: specifies the window value to be compared to
* the downcounter.
* This parameter value must be lower than 0x80.
* Output : None
* Return : None
*******************************************************************************/
void WWDG_SetWindowValue(u8 WindowValue)
{
u32 tmpreg = 0;
/* Check the parameters */
assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));
/* Clear W[6:0] bits */
tmpreg = WWDG->CFR & CFR_W_Mask;
/* Set W[6:0] bits according to WindowValue value */
tmpreg |= WindowValue & BIT_Mask;
/* Store the new value */
WWDG->CFR = tmpreg;
}
/*******************************************************************************
* Function Name : WWDG_EnableIT
* Description : Enables the WWDG Early Wakeup interrupt(EWI).
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void WWDG_EnableIT(void)
{
*(vu32 *) CFR_EWI_BB = (u32)ENABLE;
}
/*******************************************************************************
* Function Name : WWDG_SetCounter
* Description : Sets the WWDG counter value.
* Input : - Counter: specifies the watchdog counter value.
* This parameter must be a number between 0x40 and 0x7F.
* Output : None
* Return : None
*******************************************************************************/
void WWDG_SetCounter(u8 Counter)
{
/* Check the parameters */
assert_param(IS_WWDG_COUNTER(Counter));
/* Write to T[6:0] bits to configure the counter value, no need to do
a read-modify-write; writing a 0 to WDGA bit does nothing */
WWDG->CR = Counter & BIT_Mask;
}
/*******************************************************************************
* Function Name : WWDG_Enable
* Description : Enables WWDG and load the counter value.
* - Counter: specifies the watchdog counter value.
* This parameter must be a number between 0x40 and 0x7F.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void WWDG_Enable(u8 Counter)
{
/* Check the parameters */
assert_param(IS_WWDG_COUNTER(Counter));
WWDG->CR = CR_WDGA_Set | Counter;
}
/*******************************************************************************
* Function Name : WWDG_GetFlagStatus
* Description : Checks whether the Early Wakeup interrupt flag is set or not.
* Input : None
* Output : None
* Return : The new state of the Early Wakeup interrupt flag (SET or RESET)
*******************************************************************************/
FlagStatus WWDG_GetFlagStatus(void)
{
return (FlagStatus)(WWDG->SR);
}
/*******************************************************************************
* Function Name : WWDG_ClearFlag
* Description : Clears Early Wakeup interrupt flag.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void WWDG_ClearFlag(void)
{
WWDG->SR = (u32)RESET;
}
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

937
bsp/stm32f103vb_lwip/msd.c Normal file
View File

@ -0,0 +1,937 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : msd.c
* Author : MCD Application Team
* Version : V2.1
* Date : 05/30/2008
* Description : MSD card driver source file.
* Pin assignment:
* ----------------------------------------------
* | STM32F10x | MSD Pin |
* ----------------------------------------------
* | P0.4 | ChipSelect 1 |
* | P0.1 / MOSI | DataIn 2 |
* | | GND 3 (0 V) |
* | | VDD 4 (3.3 V) |
* | P0.2 / SCLK | Clock 5 |
* | | GND 6 (0 V) |
* | P0.0 / MISO | DataOut 7 |
* -----------------------------------------------
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
* FOR MORE INFORMATION PLEASE CAREFULLY READ THE LICENSE AGREEMENT FILE LOCATED
* IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "msd.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Select MSD Card: ChipSelect pin low */
#define MSD_CS_LOW() GPIO_ResetBits(GPIOD, GPIO_Pin_9)
/* Deselect MSD Card: ChipSelect pin high */
#define MSD_CS_HIGH() GPIO_SetBits(GPIOD, GPIO_Pin_9)
/* Private function prototypes -----------------------------------------------*/
static void SPI_Config(void);
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : MSD_Init
* Description : Initializes the MSD/SD communication.
* Input : None
* Output : None
* Return : The MSD Response: - MSD_RESPONSE_FAILURE: Sequence failed
* - MSD_RESPONSE_NO_ERROR: Sequence succeed
*******************************************************************************/
u8 MSD_Init(void)
{
u32 i = 0;
/* Initialize SPI1 */
SPI_Config();
/* MSD chip select high */
MSD_CS_HIGH();
/* Send dummy byte 0xFF, 10 times with CS high*/
/* rise CS and MOSI for 80 clocks cycles */
for (i = 0; i <= 9; i++)
{
/* Send dummy byte 0xFF */
MSD_WriteByte(DUMMY);
}
/*------------Put MSD in SPI mode--------------*/
/* MSD initialized and set to SPI mode properly */
return (MSD_GoIdleState());
}
/*******************************************************************************
* Function Name : MSD_WriteBlock
* Description : Writes a block on the MSD
* Input : - pBuffer : pointer to the buffer containing the data to be
* written on the MSD.
* - WriteAddr : address to write on.
* - NumByteToWrite: number of data to write
* Output : None
* Return : The MSD Response: - MSD_RESPONSE_FAILURE: Sequence failed
* - MSD_RESPONSE_NO_ERROR: Sequence succeed
*******************************************************************************/
u8 MSD_WriteBlock(u8* pBuffer, u32 WriteAddr, u16 NumByteToWrite)
{
u32 i = 0;
u8 rvalue = MSD_RESPONSE_FAILURE;
/* MSD chip select low */
MSD_CS_LOW();
/* Send CMD24 (MSD_WRITE_BLOCK) to write multiple block */
MSD_SendCmd(MSD_WRITE_BLOCK, WriteAddr, 0xFF);
/* Check if the MSD acknowledged the write block command: R1 response (0x00: no errors) */
if (!MSD_GetResponse(MSD_RESPONSE_NO_ERROR))
{
/* Send a dummy byte */
MSD_WriteByte(DUMMY);
/* Send the data token to signify the start of the data */
MSD_WriteByte(0xFE);
/* Write the block data to MSD : write count data by block */
for (i = 0; i < NumByteToWrite; i++)
{
/* Send the pointed byte */
MSD_WriteByte(*pBuffer);
/* Point to the next location where the byte read will be saved */
pBuffer++;
}
/* Put CRC bytes (not really needed by us, but required by MSD) */
MSD_ReadByte();
MSD_ReadByte();
/* Read data response */
if (MSD_GetDataResponse() == MSD_DATA_OK)
{
rvalue = MSD_RESPONSE_NO_ERROR;
}
}
/* MSD chip select high */
MSD_CS_HIGH();
/* Send dummy byte: 8 Clock pulses of delay */
MSD_WriteByte(DUMMY);
/* Returns the reponse */
return rvalue;
}
/*******************************************************************************
* Function Name : MSD_ReadBlock
* Description : Reads a block of data from the MSD.
* Input : - pBuffer : pointer to the buffer that receives the data read
* from the MSD.
* - ReadAddr : MSD's internal address to read from.
* - NumByteToRead : number of bytes to read from the MSD.
* Output : None
* Return : The MSD Response: - MSD_RESPONSE_FAILURE: Sequence failed
* - MSD_RESPONSE_NO_ERROR: Sequence succeed
*******************************************************************************/
u8 MSD_ReadBlock(u8* pBuffer, u32 ReadAddr, u16 NumByteToRead)
{
u32 i = 0;
u8 rvalue = MSD_RESPONSE_FAILURE;
/* MSD chip select low */
MSD_CS_LOW();
/* Send CMD17 (MSD_READ_SINGLE_BLOCK) to read one block */
MSD_SendCmd(MSD_READ_SINGLE_BLOCK, ReadAddr, 0xFF);
/* Check if the MSD acknowledged the read block command: R1 response (0x00: no errors) */
if (!MSD_GetResponse(MSD_RESPONSE_NO_ERROR))
{
/* Now look for the data token to signify the start of the data */
if (!MSD_GetResponse(MSD_START_DATA_SINGLE_BLOCK_READ))
{
/* Read the MSD block data : read NumByteToRead data */
for (i = 0; i < NumByteToRead; i++)
{
/* Save the received data */
*pBuffer = MSD_ReadByte();
/* Point to the next location where the byte read will be saved */
pBuffer++;
}
/* Get CRC bytes (not really needed by us, but required by MSD) */
MSD_ReadByte();
MSD_ReadByte();
/* Set response value to success */
rvalue = MSD_RESPONSE_NO_ERROR;
}
}
/* MSD chip select high */
MSD_CS_HIGH();
/* Send dummy byte: 8 Clock pulses of delay */
MSD_WriteByte(DUMMY);
/* Returns the reponse */
return rvalue;
}
/*******************************************************************************
* Function Name : MSD_WriteBuffer
* Description : Writes many blocks on the MSD
* Input : - pBuffer : pointer to the buffer containing the data to be
* written on the MSD.
* - WriteAddr : address to write on.
* - NumByteToWrite: number of data to write
* Output : None
* Return : The MSD Response: - MSD_RESPONSE_FAILURE: Sequence failed
* - MSD_RESPONSE_NO_ERROR: Sequence succeed
*******************************************************************************/
u8 MSD_WriteBuffer(u8* pBuffer, u32 WriteAddr, u32 NumByteToWrite)
{
u32 i = 0, NbrOfBlock = 0, Offset = 0;
u8 rvalue = MSD_RESPONSE_FAILURE;
/* Calculate number of blocks to write */
NbrOfBlock = NumByteToWrite / BLOCK_SIZE;
/* MSD chip select low */
MSD_CS_LOW();
/* Data transfer */
while (NbrOfBlock --)
{
/* Send CMD24 (MSD_WRITE_BLOCK) to write blocks */
MSD_SendCmd(MSD_WRITE_BLOCK, WriteAddr + Offset, 0xFF);
/* Check if the MSD acknowledged the write block command: R1 response (0x00: no errors) */
if (MSD_GetResponse(MSD_RESPONSE_NO_ERROR))
{
return MSD_RESPONSE_FAILURE;
}
/* Send dummy byte */
MSD_WriteByte(DUMMY);
/* Send the data token to signify the start of the data */
MSD_WriteByte(MSD_START_DATA_SINGLE_BLOCK_WRITE);
/* Write the block data to MSD : write count data by block */
for (i = 0; i < BLOCK_SIZE; i++)
{
/* Send the pointed byte */
MSD_WriteByte(*pBuffer);
/* Point to the next location where the byte read will be saved */
pBuffer++;
}
/* Set next write address */
Offset += 512;
/* Put CRC bytes (not really needed by us, but required by MSD) */
MSD_ReadByte();
MSD_ReadByte();
/* Read data response */
if (MSD_GetDataResponse() == MSD_DATA_OK)
{
/* Set response value to success */
rvalue = MSD_RESPONSE_NO_ERROR;
}
else
{
/* Set response value to failure */
rvalue = MSD_RESPONSE_FAILURE;
}
}
/* MSD chip select high */
MSD_CS_HIGH();
/* Send dummy byte: 8 Clock pulses of delay */
MSD_WriteByte(DUMMY);
/* Returns the reponse */
return rvalue;
}
/*******************************************************************************
* Function Name : MSD_ReadBuffer
* Description : Reads multiple block of data from the MSD.
* Input : - pBuffer : pointer to the buffer that receives the data read
* from the MSD.
* - ReadAddr : MSD's internal address to read from.
* - NumByteToRead : number of bytes to read from the MSD.
* Output : None
* Return : The MSD Response: - MSD_RESPONSE_FAILURE: Sequence failed
* - MSD_RESPONSE_NO_ERROR: Sequence succeed
*******************************************************************************/
u8 MSD_ReadBuffer(u8* pBuffer, u32 ReadAddr, u32 NumByteToRead)
{
u32 i = 0, NbrOfBlock = 0, Offset = 0;
u8 rvalue = MSD_RESPONSE_FAILURE;
/* Calculate number of blocks to read */
NbrOfBlock = NumByteToRead / BLOCK_SIZE;
/* MSD chip select low */
MSD_CS_LOW();
/* Data transfer */
while (NbrOfBlock --)
{
/* Send CMD17 (MSD_READ_SINGLE_BLOCK) to read one block */
MSD_SendCmd (MSD_READ_SINGLE_BLOCK, ReadAddr + Offset, 0xFF);
/* Check if the MSD acknowledged the read block command: R1 response (0x00: no errors) */
if (MSD_GetResponse(MSD_RESPONSE_NO_ERROR))
{
return MSD_RESPONSE_FAILURE;
}
/* Now look for the data token to signify the start of the data */
if (!MSD_GetResponse(MSD_START_DATA_SINGLE_BLOCK_READ))
{
/* Read the MSD block data : read NumByteToRead data */
for (i = 0; i < BLOCK_SIZE; i++)
{
/* Read the pointed data */
*pBuffer = MSD_ReadByte();
/* Point to the next location where the byte read will be saved */
pBuffer++;
}
/* Set next read address*/
Offset += 512;
/* get CRC bytes (not really needed by us, but required by MSD) */
MSD_ReadByte();
MSD_ReadByte();
/* Set response value to success */
rvalue = MSD_RESPONSE_NO_ERROR;
}
else
{
/* Set response value to failure */
rvalue = MSD_RESPONSE_FAILURE;
}
}
/* MSD chip select high */
MSD_CS_HIGH();
/* Send dummy byte: 8 Clock pulses of delay */
MSD_WriteByte(DUMMY);
/* Returns the reponse */
return rvalue;
}
/*******************************************************************************
* Function Name : MSD_GetCSDRegister
* Description : Read the CSD card register.
* Reading the contents of the CSD register in SPI mode
* is a simple read-block transaction.
* Input : - MSD_csd: pointer on an SCD register structure
* Output : None
* Return : The MSD Response: - MSD_RESPONSE_FAILURE: Sequence failed
* - MSD_RESPONSE_NO_ERROR: Sequence succeed
*******************************************************************************/
u8 MSD_GetCSDRegister(sMSD_CSD* MSD_csd)
{
u32 i = 0;
u8 rvalue = MSD_RESPONSE_FAILURE;
u8 CSD_Tab[16];
/* MSD chip select low */
MSD_CS_LOW();
/* Send CMD9 (CSD register) or CMD10(CSD register) */
MSD_SendCmd(MSD_SEND_CSD, 0, 0xFF);
/* Wait for response in the R1 format (0x00 is no errors) */
if (!MSD_GetResponse(MSD_RESPONSE_NO_ERROR))
{
if (!MSD_GetResponse(MSD_START_DATA_SINGLE_BLOCK_READ))
{
for (i = 0; i < 16; i++)
{
/* Store CSD register value on CSD_Tab */
CSD_Tab[i] = MSD_ReadByte();
}
}
/* Get CRC bytes (not really needed by us, but required by MSD) */
MSD_WriteByte(DUMMY);
MSD_WriteByte(DUMMY);
/* Set response value to success */
rvalue = MSD_RESPONSE_NO_ERROR;
}
/* MSD chip select high */
MSD_CS_HIGH();
/* Send dummy byte: 8 Clock pulses of delay */
MSD_WriteByte(DUMMY);
/* Byte 0 */
MSD_csd->CSDStruct = (CSD_Tab[0] & 0xC0) >> 6;
MSD_csd->SysSpecVersion = (CSD_Tab[0] & 0x3C) >> 2;
MSD_csd->Reserved1 = CSD_Tab[0] & 0x03;
/* Byte 1 */
MSD_csd->TAAC = CSD_Tab[1] ;
/* Byte 2 */
MSD_csd->NSAC = CSD_Tab[2];
/* Byte 3 */
MSD_csd->MaxBusClkFrec = CSD_Tab[3];
/* Byte 4 */
MSD_csd->CardComdClasses = CSD_Tab[4] << 4;
/* Byte 5 */
MSD_csd->CardComdClasses |= (CSD_Tab[5] & 0xF0) >> 4;
MSD_csd->RdBlockLen = CSD_Tab[5] & 0x0F;
/* Byte 6 */
MSD_csd->PartBlockRead = (CSD_Tab[6] & 0x80) >> 7;
MSD_csd->WrBlockMisalign = (CSD_Tab[6] & 0x40) >> 6;
MSD_csd->RdBlockMisalign = (CSD_Tab[6] & 0x20) >> 5;
MSD_csd->DSRImpl = (CSD_Tab[6] & 0x10) >> 4;
MSD_csd->Reserved2 = 0; /* Reserved */
MSD_csd->DeviceSize = (CSD_Tab[6] & 0x03) << 10;
/* Byte 7 */
MSD_csd->DeviceSize |= (CSD_Tab[7]) << 2;
/* Byte 8 */
MSD_csd->DeviceSize |= (CSD_Tab[8] & 0xC0) >> 6;
MSD_csd->MaxRdCurrentVDDMin = (CSD_Tab[8] & 0x38) >> 3;
MSD_csd->MaxRdCurrentVDDMax = (CSD_Tab[8] & 0x07);
/* Byte 9 */
MSD_csd->MaxWrCurrentVDDMin = (CSD_Tab[9] & 0xE0) >> 5;
MSD_csd->MaxWrCurrentVDDMax = (CSD_Tab[9] & 0x1C) >> 2;
MSD_csd->DeviceSizeMul = (CSD_Tab[9] & 0x03) << 1;
/* Byte 10 */
MSD_csd->DeviceSizeMul |= (CSD_Tab[10] & 0x80) >> 7;
MSD_csd->EraseGrSize = (CSD_Tab[10] & 0x7C) >> 2;
MSD_csd->EraseGrMul = (CSD_Tab[10] & 0x03) << 3;
/* Byte 11 */
MSD_csd->EraseGrMul |= (CSD_Tab[11] & 0xE0) >> 5;
MSD_csd->WrProtectGrSize = (CSD_Tab[11] & 0x1F);
/* Byte 12 */
MSD_csd->WrProtectGrEnable = (CSD_Tab[12] & 0x80) >> 7;
MSD_csd->ManDeflECC = (CSD_Tab[12] & 0x60) >> 5;
MSD_csd->WrSpeedFact = (CSD_Tab[12] & 0x1C) >> 2;
MSD_csd->MaxWrBlockLen = (CSD_Tab[12] & 0x03) << 2;
/* Byte 13 */
MSD_csd->MaxWrBlockLen |= (CSD_Tab[13] & 0xc0) >> 6;
MSD_csd->WriteBlockPaPartial = (CSD_Tab[13] & 0x20) >> 5;
MSD_csd->Reserved3 = 0;
MSD_csd->ContentProtectAppli = (CSD_Tab[13] & 0x01);
/* Byte 14 */
MSD_csd->FileFormatGrouop = (CSD_Tab[14] & 0x80) >> 7;
MSD_csd->CopyFlag = (CSD_Tab[14] & 0x40) >> 6;
MSD_csd->PermWrProtect = (CSD_Tab[14] & 0x20) >> 5;
MSD_csd->TempWrProtect = (CSD_Tab[14] & 0x10) >> 4;
MSD_csd->FileFormat = (CSD_Tab[14] & 0x0C) >> 2;
MSD_csd->ECC = (CSD_Tab[14] & 0x03);
/* Byte 15 */
MSD_csd->msd_CRC = (CSD_Tab[15] & 0xFE) >> 1;
MSD_csd->Reserved4 = 1;
/* Return the reponse */
return rvalue;
}
/*******************************************************************************
* Function Name : MSD_GetCIDRegister
* Description : Read the CID card register.
* Reading the contents of the CID register in SPI mode
* is a simple read-block transaction.
* Input : - MSD_cid: pointer on an CID register structure
* Output : None
* Return : The MSD Response: - MSD_RESPONSE_FAILURE: Sequence failed
* - MSD_RESPONSE_NO_ERROR: Sequence succeed
*******************************************************************************/
u8 MSD_GetCIDRegister(sMSD_CID* MSD_cid)
{
u32 i = 0;
u8 rvalue = MSD_RESPONSE_FAILURE;
u8 CID_Tab[16];
/* MSD chip select low */
MSD_CS_LOW();
/* Send CMD10 (CID register) */
MSD_SendCmd(MSD_SEND_CID, 0, 0xFF);
/* Wait for response in the R1 format (0x00 is no errors) */
if (!MSD_GetResponse(MSD_RESPONSE_NO_ERROR))
{
if (!MSD_GetResponse(MSD_START_DATA_SINGLE_BLOCK_READ))
{
/* Store CID register value on CID_Tab */
for (i = 0; i < 16; i++)
{
CID_Tab[i] = MSD_ReadByte();
}
}
/* Get CRC bytes (not really needed by us, but required by MSD) */
MSD_WriteByte(DUMMY);
MSD_WriteByte(DUMMY);
/* Set response value to success */
rvalue = MSD_RESPONSE_NO_ERROR;
}
/* MSD chip select high */
MSD_CS_HIGH();
/* Send dummy byte: 8 Clock pulses of delay */
MSD_WriteByte(DUMMY);
/* Byte 0 */
MSD_cid->ManufacturerID = CID_Tab[0];
/* Byte 1 */
MSD_cid->OEM_AppliID = CID_Tab[1] << 8;
/* Byte 2 */
MSD_cid->OEM_AppliID |= CID_Tab[2];
/* Byte 3 */
MSD_cid->ProdName1 = CID_Tab[3] << 24;
/* Byte 4 */
MSD_cid->ProdName1 |= CID_Tab[4] << 16;
/* Byte 5 */
MSD_cid->ProdName1 |= CID_Tab[5] << 8;
/* Byte 6 */
MSD_cid->ProdName1 |= CID_Tab[6];
/* Byte 7 */
MSD_cid->ProdName2 = CID_Tab[7];
/* Byte 8 */
MSD_cid->ProdRev = CID_Tab[8];
/* Byte 9 */
MSD_cid->ProdSN = CID_Tab[9] << 24;
/* Byte 10 */
MSD_cid->ProdSN |= CID_Tab[10] << 16;
/* Byte 11 */
MSD_cid->ProdSN |= CID_Tab[11] << 8;
/* Byte 12 */
MSD_cid->ProdSN |= CID_Tab[12];
/* Byte 13 */
MSD_cid->Reserved1 |= (CID_Tab[13] & 0xF0) >> 4;
/* Byte 14 */
MSD_cid->ManufactDate = (CID_Tab[13] & 0x0F) << 8;
/* Byte 15 */
MSD_cid->ManufactDate |= CID_Tab[14];
/* Byte 16 */
MSD_cid->msd_CRC = (CID_Tab[15] & 0xFE) >> 1;
MSD_cid->Reserved2 = 1;
/* Return the reponse */
return rvalue;
}
/*******************************************************************************
* Function Name : MSD_SendCmd
* Description : Send 5 bytes command to the MSD card.
* Input : - Cmd: the user expected command to send to MSD card
* - Arg: the command argument
* - Crc: the CRC
* Output : None
* Return : None
*******************************************************************************/
void MSD_SendCmd(u8 Cmd, u32 Arg, u8 Crc)
{
u32 i = 0x00;
u8 Frame[6];
/* Construct byte1 */
Frame[0] = (Cmd | 0x40);
/* Construct byte2 */
Frame[1] = (u8)(Arg >> 24);
/* Construct byte3 */
Frame[2] = (u8)(Arg >> 16);
/* Construct byte4 */
Frame[3] = (u8)(Arg >> 8);
/* Construct byte5 */
Frame[4] = (u8)(Arg);
/* Construct CRC: byte6 */
Frame[5] = (Crc);
/* Send the Cmd bytes */
for (i = 0; i < 6; i++)
{
MSD_WriteByte(Frame[i]);
}
}
/*******************************************************************************
* Function Name : MSD_GetDataResponse
* Description : Get MSD card data response.
* Input : None
* Output : None
* Return : The MSD status: Read data response xxx0<status>1
* - status 010: Data accecpted
* - status 101: Data rejected due to a crc error
* - status 110: Data rejected due to a Write error.
* - status 111: Data rejected due to other error.
*******************************************************************************/
u8 MSD_GetDataResponse(void)
{
u32 i = 0;
u8 response, rvalue;
while (i <= 64)
{
/* Read resonse */
response = MSD_ReadByte();
/* Mask unused bits */
response &= 0x1F;
switch (response)
{
case MSD_DATA_OK:
{
rvalue = MSD_DATA_OK;
break;
}
case MSD_DATA_CRC_ERROR:
return MSD_DATA_CRC_ERROR;
case MSD_DATA_WRITE_ERROR:
return MSD_DATA_WRITE_ERROR;
default:
{
rvalue = MSD_DATA_OTHER_ERROR;
break;
}
}
/* Exit loop in case of data ok */
if (rvalue == MSD_DATA_OK)
break;
/* Increment loop counter */
i++;
}
/* Wait null data */
while (MSD_ReadByte() == 0);
/* Return response */
return response;
}
/*******************************************************************************
* Function Name : MSD_GetResponse
* Description : Returns the MSD response.
* Input : None
* Output : None
* Return : The MSD Response: - MSD_RESPONSE_FAILURE: Sequence failed
* - MSD_RESPONSE_NO_ERROR: Sequence succeed
*******************************************************************************/
u8 MSD_GetResponse(u8 Response)
{
u32 Count = 0xFFF;
/* Check if response is got or a timeout is happen */
while ((MSD_ReadByte() != Response) && Count)
{
Count--;
}
if (Count == 0)
{
/* After time out */
return MSD_RESPONSE_FAILURE;
}
else
{
/* Right response got */
return MSD_RESPONSE_NO_ERROR;
}
}
/*******************************************************************************
* Function Name : MSD_GetStatus
* Description : Returns the MSD status.
* Input : None
* Output : None
* Return : The MSD status.
*******************************************************************************/
u16 MSD_GetStatus(void)
{
u16 Status = 0;
/* MSD chip select low */
MSD_CS_LOW();
/* Send CMD13 (MSD_SEND_STATUS) to get MSD status */
MSD_SendCmd(MSD_SEND_STATUS, 0, 0xFF);
Status = MSD_ReadByte();
Status |= (u16)(MSD_ReadByte() << 8);
/* MSD chip select high */
MSD_CS_HIGH();
/* Send dummy byte 0xFF */
MSD_WriteByte(DUMMY);
return Status;
}
/*******************************************************************************
* Function Name : MSD_GoIdleState
* Description : Put MSD in Idle state.
* Input : None
* Output : None
* Return : The MSD Response: - MSD_RESPONSE_FAILURE: Sequence failed
* - MSD_RESPONSE_NO_ERROR: Sequence succeed
*******************************************************************************/
u8 MSD_GoIdleState(void)
{
/* MSD chip select low */
MSD_CS_LOW();
/* Send CMD0 (GO_IDLE_STATE) to put MSD in SPI mode */
MSD_SendCmd(MSD_GO_IDLE_STATE, 0, 0x95);
/* Wait for In Idle State Response (R1 Format) equal to 0x01 */
if (MSD_GetResponse(MSD_IN_IDLE_STATE))
{
/* No Idle State Response: return response failue */
return MSD_RESPONSE_FAILURE;
}
/*----------Activates the card initialization process-----------*/
do
{
/* MSD chip select high */
MSD_CS_HIGH();
/* Send Dummy byte 0xFF */
MSD_WriteByte(DUMMY);
/* MSD chip select low */
MSD_CS_LOW();
/* Send CMD1 (Activates the card process) until response equal to 0x0 */
MSD_SendCmd(MSD_SEND_OP_COND, 0, 0xFF);
/* Wait for no error Response (R1 Format) equal to 0x00 */
}
while (MSD_GetResponse(MSD_RESPONSE_NO_ERROR));
/* MSD chip select high */
MSD_CS_HIGH();
/* Send dummy byte 0xFF */
MSD_WriteByte(DUMMY);
return MSD_RESPONSE_NO_ERROR;
}
/*******************************************************************************
* Function Name : MSD_WriteByte
* Description : Write a byte on the MSD.
* Input : Data: byte to send.
* Output : None
* Return : None.
*******************************************************************************/
void MSD_WriteByte(u8 Data)
{
/* Wait until the transmit buffer is empty */
while (SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_TXE) == RESET);
/* Send the byte */
SPI_I2S_SendData(SPI1, Data);
}
/*******************************************************************************
* Function Name : MSD_ReadByte
* Description : Read a byte from the MSD.
* Input : None.
* Output : None
* Return : The received byte.
*******************************************************************************/
u8 MSD_ReadByte(void)
{
u8 Data = 0;
/* Wait until the transmit buffer is empty */
while (SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_TXE) == RESET);
/* Send the byte */
SPI_I2S_SendData(SPI1, DUMMY);
/* Wait until a data is received */
while (SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_RXNE) == RESET);
/* Get the received data */
Data = SPI_I2S_ReceiveData(SPI1);
/* Return the shifted data */
return Data;
}
/*******************************************************************************
* Function Name : SPI_Config
* Description : Initializes the SPI1 and CS pins.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void SPI_Config(void)
{
u16 i, j;
GPIO_InitTypeDef GPIO_InitStructure;
SPI_InitTypeDef SPI_InitStructure;
/* GPIOA and GPIOC Periph clock enable */
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOD, ENABLE);
/* SPI1 Periph clock enable */
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE);
/* Configure SPI1 pins: SCK, MISO and MOSI */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOA, &GPIO_InitStructure);
/* Configure PD9 pin: CS pin ,PD10 : SD Power */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9|GPIO_Pin_10;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
GPIO_Init(GPIOD, &GPIO_InitStructure);
/* SPI1 Config */
SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;
SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4;
SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
SPI_InitStructure.SPI_CRCPolynomial = 7;
SPI_Init(SPI1, &SPI_InitStructure);
/* SPI1 enable */
SPI_Cmd(SPI1, ENABLE);
/* active SD card */
GPIO_ResetBits(GPIOD, GPIO_Pin_10);
for(i=0;i<65530;i++)
{
for(j=0;j<5000;j++)
;
}
}
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
/*
* RT-Thread SD Card Driver
* 20090417 Bernard
*/
#include <rtthread.h>
#include <dfs_fs.h>
struct rt_device sdcard_device;
struct dfs_partition part;
#define SECTOR_SIZE 512
/* RT-Thread Device Driver Interface */
static rt_err_t rt_sdcard_init(rt_device_t dev)
{
sMSD_CSD MSD_csd;
MSD_GetCSDRegister(&MSD_csd);
return RT_EOK;
}
static rt_err_t rt_sdcard_open(rt_device_t dev, rt_uint16_t oflag)
{
return RT_EOK;
}
static rt_err_t rt_sdcard_close(rt_device_t dev)
{
return RT_EOK;
}
static rt_size_t rt_sdcard_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
{
rt_uint8_t status;
rt_uint32_t i;
status = MSD_RESPONSE_NO_ERROR;
rt_kprintf("read: 0x%x, size %d\n", pos, size);
/* read all sectors */
for (i = 0; i < size / SECTOR_SIZE; i ++)
{
status = MSD_ReadBlock((rt_uint8_t*)((rt_uint8_t*)buffer + i * SECTOR_SIZE),
(part.offset + i)* SECTOR_SIZE + pos,
SECTOR_SIZE);
if (status != MSD_RESPONSE_NO_ERROR)
{
rt_kprintf("sd card read failed\n");
return 0;
}
}
if (status == MSD_RESPONSE_NO_ERROR) return size;
rt_kprintf("read failed: %d\n", status);
return 0;
}
static rt_size_t rt_sdcard_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
{
rt_uint8_t status;
rt_uint32_t i;
status = MSD_RESPONSE_NO_ERROR;
rt_kprintf("write: 0x%x, size %d\n", pos, size);
/* read all sectors */
for (i = 0; i < size / SECTOR_SIZE; i ++)
{
status = MSD_WriteBuffer((rt_uint8_t*)((rt_uint8_t*)buffer + i * SECTOR_SIZE),
(part.offset + i)* SECTOR_SIZE + pos,
SECTOR_SIZE);
if (status != MSD_RESPONSE_NO_ERROR)
{
rt_kprintf("sd card write failed\n");
return 0;
}
}
if (status == MSD_RESPONSE_NO_ERROR) return size;
rt_kprintf("write failed: %d\n", status);
return 0;
}
static rt_err_t rt_sdcard_control(rt_device_t dev, rt_uint8_t cmd, void *args)
{
return RT_EOK;
}
void rt_hw_sdcard_init()
{
if (MSD_Init() == MSD_RESPONSE_NO_ERROR)
{
rt_uint8_t status;
rt_uint8_t *sector;
/* register sdcard device */
sdcard_device.init = rt_sdcard_init;
sdcard_device.open = rt_sdcard_open;
sdcard_device.close = rt_sdcard_close;
sdcard_device.read = rt_sdcard_read;
sdcard_device.write = rt_sdcard_write;
sdcard_device.control = rt_sdcard_control;
/* no private */
sdcard_device.private = RT_NULL;
/* get the first sector to read partition table */
sector = (rt_uint8_t*) rt_malloc (512);
if (sector == RT_NULL)
{
rt_kprintf("allocate partition sector buffer failed\n");
return;
}
status = MSD_ReadBlock(sector, 0, 512);
if (status == MSD_RESPONSE_NO_ERROR)
{
/* get the first partition */
status = dfs_filesystem_get_partition(&part, sector, 0);
if (status != RT_EOK)
{
/* there is no partition table */
part.offset = 0;
part.size = 0;
}
}
else
{
/* there is no partition table */
part.offset = 0;
part.size = 0;
}
/* release sector buffer */
rt_free(sector);
rt_device_register(&sdcard_device, "sd0",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE);
}
else
{
rt_kprintf("sdcard init failed\n");
}
}

173
bsp/stm32f103vb_lwip/msd.h Normal file
View File

@ -0,0 +1,173 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : msd.h
* Author : MCD Application Team
* Version : V2.1
* Date : 05/30/2008
* Description : Header for msd.c file.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
* FOR MORE INFORMATION PLEASE CAREFULLY READ THE LICENSE AGREEMENT FILE LOCATED
* IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __MSD_H
#define __MSD_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_lib.h"
/* Private define ------------------------------------------------------------*/
/* Block Size */
#define BLOCK_SIZE 512
/* Dummy byte */
#define DUMMY 0xFF
/* Start Data tokens */
/* Tokens (necessary because at nop/idle (and CS active) only 0xff is on the data/command line) */
#define MSD_START_DATA_SINGLE_BLOCK_READ 0xFE /* Data token start byte, Start Single Block Read */
#define MSD_START_DATA_MULTIPLE_BLOCK_READ 0xFE /* Data token start byte, Start Multiple Block Read */
#define MSD_START_DATA_SINGLE_BLOCK_WRITE 0xFE /* Data token start byte, Start Single Block Write */
#define MSD_START_DATA_MULTIPLE_BLOCK_WRITE 0xFD /* Data token start byte, Start Multiple Block Write */
#define MSD_STOP_DATA_MULTIPLE_BLOCK_WRITE 0xFD /* Data toke stop byte, Stop Multiple Block Write */
/* MSD functions return */
#define MSD_SUCCESS 0x00
#define MSD_FAIL 0xFF
/* MSD reponses and error flags */
#define MSD_RESPONSE_NO_ERROR 0x00
#define MSD_IN_IDLE_STATE 0x01
#define MSD_ERASE_RESET 0x02
#define MSD_ILLEGAL_COMMAND 0x04
#define MSD_COM_CRC_ERROR 0x08
#define MSD_ERASE_SEQUENCE_ERROR 0x10
#define MSD_ADDRESS_ERROR 0x20
#define MSD_PARAMETER_ERROR 0x40
#define MSD_RESPONSE_FAILURE 0xFF
/* Data response error */
#define MSD_DATA_OK 0x05
#define MSD_DATA_CRC_ERROR 0x0B
#define MSD_DATA_WRITE_ERROR 0x0D
#define MSD_DATA_OTHER_ERROR 0xFF
/* Commands: CMDxx = CMD-number | 0x40 */
#define MSD_GO_IDLE_STATE 0 /* CMD0=0x40 */
#define MSD_SEND_OP_COND 1 /* CMD1=0x41 */
#define MSD_SEND_CSD 9 /* CMD9=0x49 */
#define MSD_SEND_CID 10 /* CMD10=0x4A */
#define MSD_STOP_TRANSMISSION 12 /* CMD12=0x4C */
#define MSD_SEND_STATUS 13 /* CMD13=0x4D */
#define MSD_SET_BLOCKLEN 16 /* CMD16=0x50 */
#define MSD_READ_SINGLE_BLOCK 17 /* CMD17=0x51 */
#define MSD_READ_MULTIPLE_BLOCK 18 /* CMD18=0x52 */
#define MSD_SET_BLOCK_COUNT 23 /* CMD23=0x57 */
#define MSD_WRITE_BLOCK 24 /* CMD24=0x58 */
#define MSD_WRITE_MULTIPLE_BLOCK 25 /* CMD25=0x59 */
#define MSD_PROGRAM_CSD 27 /* CMD27=0x5B */
#define MSD_SET_WRITE_PROT 28 /* CMD28=0x5C */
#define MSD_CLR_WRITE_PROT 29 /* CMD29=0x5D */
#define MSD_SEND_WRITE_PROT 30 /* CMD30=0x5E */
#define MSD_TAG_SECTOR_START 32 /* CMD32=0x60 */
#define MSD_TAG_SECTOR_END 33 /* CMD33=0x61 */
#define MSD_UNTAG_SECTOR 34 /* CMD34=0x62 */
#define MSD_TAG_ERASE_GROUP_START 35 /* CMD35=0x63 */
#define MSD_TAG_ERASE_GROUP_END 36 /* CMD36=0x64 */
#define MSD_UNTAG_ERASE_GROUP 37 /* CMD37=0x65 */
#define MSD_ERASE 38 /* CMD38=0x66 */
#define MSD_READ_OCR 39 /* CMD39=0x67 */
#define MSD_CRC_ON_OFF 40 /* CMD40=0x68 */
/* Exported types ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
typedef struct _MSD_CSD /*Card Specific Data*/
{
vu8 CSDStruct; /* CSD structure */
vu8 SysSpecVersion; /* System specification version */
vu8 Reserved1; /* Reserved */
vu8 TAAC; /* Data read access-time 1 */
vu8 NSAC; /* Data read access-time 2 in CLK cycles */
vu8 MaxBusClkFrec; /* Max. bus clock frequency */
vu16 CardComdClasses; /* Card command classes */
vu8 RdBlockLen; /* Max. read data block length */
vu8 PartBlockRead; /* Partial blocks for read allowed */
vu8 WrBlockMisalign; /* Write block misalignment */
vu8 RdBlockMisalign; /* Read block misalignment */
vu8 DSRImpl; /* DSR implemented */
vu8 Reserved2; /* Reserved */
vu16 DeviceSize; /* Device Size */
vu8 MaxRdCurrentVDDMin; /* Max. read current @ VDD min */
vu8 MaxRdCurrentVDDMax; /* Max. read current @ VDD max */
vu8 MaxWrCurrentVDDMin; /* Max. write current @ VDD min */
vu8 MaxWrCurrentVDDMax; /* Max. write current @ VDD max */
vu8 DeviceSizeMul; /* Device size multiplier */
vu8 EraseGrSize; /* Erase group size */
vu8 EraseGrMul; /* Erase group size multiplier */
vu8 WrProtectGrSize; /* Write protect group size */
vu8 WrProtectGrEnable; /* Write protect group enable */
vu8 ManDeflECC; /* Manufacturer default ECC */
vu8 WrSpeedFact; /* Write speed factor */
vu8 MaxWrBlockLen; /* Max. write data block length */
vu8 WriteBlockPaPartial; /* Partial blocks for write allowed */
vu8 Reserved3; /* Reserded */
vu8 ContentProtectAppli; /* Content protection application */
vu8 FileFormatGrouop; /* File format group */
vu8 CopyFlag; /* Copy flag (OTP) */
vu8 PermWrProtect; /* Permanent write protection */
vu8 TempWrProtect; /* Temporary write protection */
vu8 FileFormat; /* File Format */
vu8 ECC; /* ECC code */
vu8 msd_CRC; /* CRC */
vu8 Reserved4; /* always 1*/
}
sMSD_CSD;
typedef struct _MSD_CID /*Card Identification Data*/
{
vu8 ManufacturerID; /* ManufacturerID */
vu16 OEM_AppliID; /* OEM/Application ID */
vu32 ProdName1; /* Product Name part1 */
vu8 ProdName2; /* Product Name part2*/
vu8 ProdRev; /* Product Revision */
vu32 ProdSN; /* Product Serial Number */
vu8 Reserved1; /* Reserved1 */
vu16 ManufactDate; /* Manufacturing Date */
vu8 msd_CRC; /* CRC */
vu8 Reserved2; /* always 1*/
}
sMSD_CID;
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/*----- High layer function -----*/
u8 MSD_Init(void);
u8 MSD_WriteBlock(u8* pBuffer, u32 WriteAddr, u16 NumByteToWrite);
u8 MSD_ReadBlock(u8* pBuffer, u32 ReadAddr, u16 NumByteToRead);
u8 MSD_WriteBuffer(u8* pBuffer, u32 WriteAddr, u32 NumByteToWrite);
u8 MSD_ReadBuffer(u8* pBuffer, u32 ReadAddr, u32 NumByteToRead);
u8 MSD_GetCSDRegister(sMSD_CSD* MSD_csd);
u8 MSD_GetCIDRegister(sMSD_CID* MSD_cid);
/*----- Medium layer function -----*/
void MSD_SendCmd(u8 Cmd, u32 Arg, u8 Crc);
u8 MSD_GetResponse(u8 Response);
u8 MSD_GetDataResponse(void);
u8 MSD_GoIdleState(void);
u16 MSD_GetStatus(void);
/*----- Low layer function -----*/
void MSD_WriteByte(u8 byte);
u8 MSD_ReadByte(void);
#endif /* __MSD_H */
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

158
bsp/stm32f103vb_lwip/project.Opt Normal file
View File

@ -0,0 +1,158 @@
### uVision2 Project, (C) Keil Software
### Do not modify !
cExt (*.c)
aExt (*.s*; *.src; *.a*)
oExt (*.obj)
lExt (*.lib)
tExt (*.txt; *.h; *.inc)
pExt (*.plm)
CppX (*.cpp)
DaveTm { 0,0,0,0,0,0,0,0 }
Target (RT-Thread/STM32), 0x0004 // Tools: 'ARM-ADS'
GRPOPT 1,(Startup),1,0,0
GRPOPT 2,(Library),0,0,0
GRPOPT 3,(Kernel),0,0,0
GRPOPT 4,(STM32),0,0,0
GRPOPT 5,(LwIP),0,0,0
GRPOPT 6,(finsh),0,0,0
GRPOPT 7,(Filesystem),0,0,0
OPTFFF 1,1,1,0,0,0,0,0,<.\application.c><application.c>
OPTFFF 1,2,1,0,0,0,0,0,<.\board.c><board.c>
OPTFFF 1,3,1,0,0,0,0,0,<.\startup.c><startup.c>
OPTFFF 1,4,2,234881024,0,0,0,0,<.\cortexm3_macro.s><cortexm3_macro.s>
OPTFFF 1,5,1,0,0,0,0,0,<.\stm32f10x_it.c><stm32f10x_it.c>
OPTFFF 1,6,5,0,0,0,0,0,<.\stm32f10x_conf.h><stm32f10x_conf.h>
OPTFFF 1,7,5,0,0,0,0,0,<.\rtconfig.h><rtconfig.h>
OPTFFF 1,8,1,0,0,0,0,0,<.\usart.c><usart.c>
OPTFFF 1,9,1,0,0,0,0,0,<.\enc28j60.c><enc28j60.c>
OPTFFF 1,10,1,0,0,0,0,0,<.\httpserver-netconn.c><httpserver-netconn.c>
OPTFFF 1,11,1,0,0,0,0,0,<.\rtc.c><rtc.c>
OPTFFF 1,12,1,0,0,0,0,0,<.\msd.c><msd.c>
OPTFFF 2,13,1,0,0,0,0,0,<.\library\src\stm32f10x_wwdg.c><stm32f10x_wwdg.c>
OPTFFF 2,14,1,0,0,0,0,0,<.\library\src\stm32f10x_adc.c><stm32f10x_adc.c>
OPTFFF 2,15,1,0,0,0,0,0,<.\library\src\stm32f10x_bkp.c><stm32f10x_bkp.c>
OPTFFF 2,16,1,0,0,0,0,0,<.\library\src\stm32f10x_can.c><stm32f10x_can.c>
OPTFFF 2,17,1,0,0,0,0,0,<.\library\src\stm32f10x_crc.c><stm32f10x_crc.c>
OPTFFF 2,18,1,0,0,0,0,0,<.\library\src\stm32f10x_dac.c><stm32f10x_dac.c>
OPTFFF 2,19,1,0,0,0,0,0,<.\library\src\stm32f10x_dbgmcu.c><stm32f10x_dbgmcu.c>
OPTFFF 2,20,1,0,0,0,0,0,<.\library\src\stm32f10x_dma.c><stm32f10x_dma.c>
OPTFFF 2,21,1,0,0,0,0,0,<.\library\src\stm32f10x_exti.c><stm32f10x_exti.c>
OPTFFF 2,22,1,0,0,0,0,0,<.\library\src\stm32f10x_flash.c><stm32f10x_flash.c>
OPTFFF 2,23,1,0,0,0,0,0,<.\library\src\stm32f10x_gpio.c><stm32f10x_gpio.c>
OPTFFF 2,24,1,0,0,0,0,0,<.\library\src\stm32f10x_i2c.c><stm32f10x_i2c.c>
OPTFFF 2,25,1,0,0,0,0,0,<.\library\src\stm32f10x_iwdg.c><stm32f10x_iwdg.c>
OPTFFF 2,26,1,0,0,0,0,0,<.\library\src\stm32f10x_lib.c><stm32f10x_lib.c>
OPTFFF 2,27,1,0,0,0,0,0,<.\library\src\stm32f10x_nvic.c><stm32f10x_nvic.c>
OPTFFF 2,28,1,0,0,0,0,0,<.\library\src\stm32f10x_pwr.c><stm32f10x_pwr.c>
OPTFFF 2,29,1,0,0,0,0,0,<.\library\src\stm32f10x_rcc.c><stm32f10x_rcc.c>
OPTFFF 2,30,1,0,0,0,0,0,<.\library\src\stm32f10x_rtc.c><stm32f10x_rtc.c>
OPTFFF 2,31,1,0,0,0,0,0,<.\library\src\stm32f10x_spi.c><stm32f10x_spi.c>
OPTFFF 2,32,1,0,0,0,0,0,<.\library\src\stm32f10x_systick.c><stm32f10x_systick.c>
OPTFFF 2,33,1,0,0,0,0,0,<.\library\src\stm32f10x_tim.c><stm32f10x_tim.c>
OPTFFF 2,34,1,0,0,0,0,0,<.\library\src\stm32f10x_usart.c><stm32f10x_usart.c>
OPTFFF 3,35,1,0,0,0,0,0,<..\..\src\clock.c><clock.c>
OPTFFF 3,36,1,0,0,0,0,0,<..\..\src\idle.c><idle.c>
OPTFFF 3,37,1,0,0,0,0,0,<..\..\src\ipc.c><ipc.c>
OPTFFF 3,38,1,0,0,0,0,0,<..\..\src\mem.c><mem.c>
OPTFFF 3,39,1,0,0,0,0,0,<..\..\src\mempool.c><mempool.c>
OPTFFF 3,40,1,0,0,0,0,0,<..\..\src\object.c><object.c>
OPTFFF 3,41,1,0,0,0,0,0,<..\..\src\scheduler.c><scheduler.c>
OPTFFF 3,42,1,201326592,0,0,0,0,<..\..\src\thread.c><thread.c>
OPTFFF 3,43,1,0,0,0,0,0,<..\..\src\timer.c><timer.c>
OPTFFF 3,44,1,0,0,0,0,0,<..\..\src\irq.c><irq.c>
OPTFFF 3,45,1,0,0,0,0,0,<..\..\src\kservice.c><kservice.c>
OPTFFF 3,46,1,0,0,0,0,0,<..\..\src\device.c><device.c>
OPTFFF 3,47,1,0,0,0,0,0,<..\..\src\slab.c><slab.c>
OPTFFF 4,48,1,0,0,0,0,0,<..\..\libcpu\arm\stm32\stack.c><stack.c>
OPTFFF 4,49,1,0,0,0,0,0,<..\..\libcpu\arm\stm32\interrupt.c><interrupt.c>
OPTFFF 4,50,1,0,0,0,0,0,<..\..\libcpu\arm\stm32\cpu.c><cpu.c>
OPTFFF 4,51,1,0,0,0,0,0,<..\..\libcpu\arm\stm32\serial.c><serial.c>
OPTFFF 4,52,2,0,0,0,0,0,<..\..\libcpu\arm\stm32\context_rvds.S><context_rvds.S>
OPTFFF 4,53,2,0,0,0,0,0,<..\..\libcpu\arm\stm32\start_rvds.s><start_rvds.s>
OPTFFF 4,54,2,0,0,0,0,0,<..\..\libcpu\arm\stm32\fault_rvds.S><fault_rvds.S>
OPTFFF 4,55,1,0,0,0,0,0,<..\..\libcpu\arm\stm32\fault.c><fault.c>
OPTFFF 5,56,1,0,0,0,0,0,<..\..\net\lwip\src\core\dhcp.c><dhcp.c>
OPTFFF 5,57,1,0,0,0,0,0,<..\..\net\lwip\src\core\dns.c><dns.c>
OPTFFF 5,58,1,0,0,0,0,0,<..\..\net\lwip\src\core\init.c><init.c>
OPTFFF 5,59,1,0,0,0,0,0,<..\..\net\lwip\src\core\memp_tiny.c><memp_tiny.c>
OPTFFF 5,60,1,0,0,0,0,0,<..\..\net\lwip\src\core\netif.c><netif.c>
OPTFFF 5,61,1,0,0,0,0,0,<..\..\net\lwip\src\core\pbuf.c><pbuf.c>
OPTFFF 5,62,1,0,0,0,0,0,<..\..\net\lwip\src\core\raw.c><raw.c>
OPTFFF 5,63,1,0,0,0,0,0,<..\..\net\lwip\src\core\stats.c><stats.c>
OPTFFF 5,64,1,0,0,0,0,0,<..\..\net\lwip\src\core\sys.c><sys.c>
OPTFFF 5,65,1,0,0,0,0,0,<..\..\net\lwip\src\core\tcp.c><tcp.c>
OPTFFF 5,66,1,0,0,0,0,0,<..\..\net\lwip\src\core\tcp_in.c><tcp_in.c>
OPTFFF 5,67,1,0,0,0,0,0,<..\..\net\lwip\src\core\tcp_out.c><tcp_out.c>
OPTFFF 5,68,1,0,0,0,0,0,<..\..\net\lwip\src\core\udp.c><udp.c>
OPTFFF 5,69,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\ip_frag.c><ip_frag.c>
OPTFFF 5,70,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\autoip.c><autoip.c>
OPTFFF 5,71,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\icmp.c><icmp.c>
OPTFFF 5,72,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\igmp.c><igmp.c>
OPTFFF 5,73,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\inet.c><inet.c>
OPTFFF 5,74,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\inet_chksum.c><inet_chksum.c>
OPTFFF 5,75,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\ip.c><ip.c>
OPTFFF 5,76,1,0,0,0,0,0,<..\..\net\lwip\src\core\ipv4\ip_addr.c><ip_addr.c>
OPTFFF 5,77,1,0,0,0,0,0,<..\..\net\lwip\src\netif\ethernetif.c><ethernetif.c>
OPTFFF 5,78,1,0,0,0,0,0,<..\..\net\lwip\src\netif\etharp.c><etharp.c>
OPTFFF 5,79,1,0,0,0,0,0,<..\..\net\lwip\src\arch\sys_arch_init.c><sys_arch_init.c>
OPTFFF 5,80,1,0,0,0,0,0,<..\..\net\lwip\src\arch\sys_arch.c><sys_arch.c>
OPTFFF 5,81,1,0,0,0,0,0,<..\..\net\lwip\src\api\tcpip.c><tcpip.c>
OPTFFF 5,82,1,0,0,0,0,0,<..\..\net\lwip\src\api\api_lib.c><api_lib.c>
OPTFFF 5,83,1,0,0,0,0,0,<..\..\net\lwip\src\api\api_msg.c><api_msg.c>
OPTFFF 5,84,1,0,0,0,0,0,<..\..\net\lwip\src\api\err.c><err.c>
OPTFFF 5,85,1,0,0,0,0,0,<..\..\net\lwip\src\api\netbuf.c><netbuf.c>
OPTFFF 5,86,1,0,0,0,0,0,<..\..\net\lwip\src\api\netdb.c><netdb.c>
OPTFFF 5,87,1,0,0,0,0,0,<..\..\net\lwip\src\api\netifapi.c><netifapi.c>
OPTFFF 5,88,1,150994944,0,0,0,0,<..\..\net\lwip\src\api\sockets.c><sockets.c>
OPTFFF 6,89,1,0,0,0,0,0,<..\..\finsh\cmd.c><cmd.c>
OPTFFF 6,90,1,0,0,0,0,0,<..\..\finsh\finsh_compiler.c><finsh_compiler.c>
OPTFFF 6,91,1,0,0,0,0,0,<..\..\finsh\finsh_error.c><finsh_error.c>
OPTFFF 6,92,1,0,0,0,0,0,<..\..\finsh\finsh_heap.c><finsh_heap.c>
OPTFFF 6,93,1,0,0,0,0,0,<..\..\finsh\finsh_init.c><finsh_init.c>
OPTFFF 6,94,1,0,0,0,0,0,<..\..\finsh\finsh_node.c><finsh_node.c>
OPTFFF 6,95,1,0,0,0,0,0,<..\..\finsh\finsh_ops.c><finsh_ops.c>
OPTFFF 6,96,1,0,0,0,0,0,<..\..\finsh\finsh_parser.c><finsh_parser.c>
OPTFFF 6,97,1,0,0,0,0,0,<..\..\finsh\finsh_token.c><finsh_token.c>
OPTFFF 6,98,1,0,0,0,0,0,<..\..\finsh\finsh_var.c><finsh_var.c>
OPTFFF 6,99,1,0,0,0,0,0,<..\..\finsh\finsh_vm.c><finsh_vm.c>
OPTFFF 6,100,1,0,0,0,0,0,<..\..\finsh\shell.c><shell.c>
OPTFFF 6,101,1,0,0,0,0,0,<..\..\finsh\symbol.c><symbol.c>
OPTFFF 7,102,1,0,0,0,0,0,<..\..\filesystem\dfs\src\dfs_cache.c><dfs_cache.c>
OPTFFF 7,103,1,0,0,0,0,0,<..\..\filesystem\dfs\src\dfs_fs.c><dfs_fs.c>
OPTFFF 7,104,1,0,0,0,0,0,<..\..\filesystem\dfs\src\dfs_init.c><dfs_init.c>
OPTFFF 7,105,1,268435456,0,0,0,0,<..\..\filesystem\dfs\src\dfs_posix.c><dfs_posix.c>
OPTFFF 7,106,1,0,0,0,0,0,<..\..\filesystem\dfs\src\dfs_raw.c><dfs_raw.c>
OPTFFF 7,107,1,0,0,0,0,0,<..\..\filesystem\dfs\src\dfs_util.c><dfs_util.c>
OPTFFF 7,108,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\base\efs.c><efs.c>
OPTFFF 7,109,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\base\extract.c><extract.c>
OPTFFF 7,110,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\base\partition.c><partition.c>
OPTFFF 7,111,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\base\plibc.c><plibc.c>
OPTFFF 7,112,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\dir.c><dir.c>
OPTFFF 7,113,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\fat.c><fat.c>
OPTFFF 7,114,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\file.c><file.c>
OPTFFF 7,115,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\fs.c><fs.c>
OPTFFF 7,116,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\ls.c><ls.c>
OPTFFF 7,117,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\time.c><time.c>
OPTFFF 7,118,1,0,0,0,0,0,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\ui.c><ui.c>
TARGOPT 1, (RT-Thread/STM32)
ADSCLK=8000000
OPTTT 1,1,1,0
OPTHX 1,65535,0,0,0
OPTLX 79,66,8,<.\obj\>
OPTOX 16
OPTLT 1,1,1,0,1,1,0,1,0,0,0,0
OPTXL 1,1,1,1,1,1,1,0,0
OPTFL 1,0,1
OPTAX 0
OPTDL (SARMCM3.DLL)()(DARMSTM.DLL)(-pSTM32F103VB)(SARMCM3.DLL)()(TARMSTM.DLL)(-pSTM32F103VB)
OPTDBG 49149,6,()()()()()()()()()() (Segger\JLTAgdi.dll)()()()
OPTDF 0x0
OPTLE <>
OPTLC <>
EndOpt

223
bsp/stm32f103vb_lwip/project.Uv2 Normal file
View File

@ -0,0 +1,223 @@
### uVision2 Project, (C) Keil Software
### Do not modify !
Target (RT-Thread/STM32), 0x0004 // Tools: 'ARM-ADS'
Group (Startup)
Group (Library)
Group (Kernel)
Group (STM32)
Group (LwIP)
Group (finsh)
Group (Filesystem)
File 1,1,<.\application.c><application.c>
File 1,1,<.\board.c><board.c>
File 1,1,<.\startup.c><startup.c>
File 1,2,<.\cortexm3_macro.s><cortexm3_macro.s>
File 1,1,<.\stm32f10x_it.c><stm32f10x_it.c>
File 1,5,<.\stm32f10x_conf.h><stm32f10x_conf.h>
File 1,5,<.\rtconfig.h><rtconfig.h>
File 1,1,<.\usart.c><usart.c>
File 1,1,<.\enc28j60.c><enc28j60.c>
File 1,1,<.\httpserver-netconn.c><httpserver-netconn.c>
File 1,1,<.\rtc.c><rtc.c>
File 1,1,<.\msd.c><msd.c>
File 2,1,<.\library\src\stm32f10x_wwdg.c><stm32f10x_wwdg.c>
File 2,1,<.\library\src\stm32f10x_adc.c><stm32f10x_adc.c>
File 2,1,<.\library\src\stm32f10x_bkp.c><stm32f10x_bkp.c>
File 2,1,<.\library\src\stm32f10x_can.c><stm32f10x_can.c>
File 2,1,<.\library\src\stm32f10x_crc.c><stm32f10x_crc.c>
File 2,1,<.\library\src\stm32f10x_dac.c><stm32f10x_dac.c>
File 2,1,<.\library\src\stm32f10x_dbgmcu.c><stm32f10x_dbgmcu.c>
File 2,1,<.\library\src\stm32f10x_dma.c><stm32f10x_dma.c>
File 2,1,<.\library\src\stm32f10x_exti.c><stm32f10x_exti.c>
File 2,1,<.\library\src\stm32f10x_flash.c><stm32f10x_flash.c>
File 2,1,<.\library\src\stm32f10x_gpio.c><stm32f10x_gpio.c>
File 2,1,<.\library\src\stm32f10x_i2c.c><stm32f10x_i2c.c>
File 2,1,<.\library\src\stm32f10x_iwdg.c><stm32f10x_iwdg.c>
File 2,1,<.\library\src\stm32f10x_lib.c><stm32f10x_lib.c>
File 2,1,<.\library\src\stm32f10x_nvic.c><stm32f10x_nvic.c>
File 2,1,<.\library\src\stm32f10x_pwr.c><stm32f10x_pwr.c>
File 2,1,<.\library\src\stm32f10x_rcc.c><stm32f10x_rcc.c>
File 2,1,<.\library\src\stm32f10x_rtc.c><stm32f10x_rtc.c>
File 2,1,<.\library\src\stm32f10x_spi.c><stm32f10x_spi.c>
File 2,1,<.\library\src\stm32f10x_systick.c><stm32f10x_systick.c>
File 2,1,<.\library\src\stm32f10x_tim.c><stm32f10x_tim.c>
File 2,1,<.\library\src\stm32f10x_usart.c><stm32f10x_usart.c>
File 3,1,<..\..\src\clock.c><clock.c>
File 3,1,<..\..\src\idle.c><idle.c>
File 3,1,<..\..\src\ipc.c><ipc.c>
File 3,1,<..\..\src\mem.c><mem.c>
File 3,1,<..\..\src\mempool.c><mempool.c>
File 3,1,<..\..\src\object.c><object.c>
File 3,1,<..\..\src\scheduler.c><scheduler.c>
File 3,1,<..\..\src\thread.c><thread.c>
File 3,1,<..\..\src\timer.c><timer.c>
File 3,1,<..\..\src\irq.c><irq.c>
File 3,1,<..\..\src\kservice.c><kservice.c>
File 3,1,<..\..\src\device.c><device.c>
File 3,1,<..\..\src\slab.c><slab.c>
File 4,1,<..\..\libcpu\arm\stm32\stack.c><stack.c>
File 4,1,<..\..\libcpu\arm\stm32\interrupt.c><interrupt.c>
File 4,1,<..\..\libcpu\arm\stm32\cpu.c><cpu.c>
File 4,1,<..\..\libcpu\arm\stm32\serial.c><serial.c>
File 4,2,<..\..\libcpu\arm\stm32\context_rvds.S><context_rvds.S>
File 4,2,<..\..\libcpu\arm\stm32\start_rvds.s><start_rvds.s>
File 4,2,<..\..\libcpu\arm\stm32\fault_rvds.S><fault_rvds.S>
File 4,1,<..\..\libcpu\arm\stm32\fault.c><fault.c>
File 5,1,<..\..\net\lwip\src\core\dhcp.c><dhcp.c>
File 5,1,<..\..\net\lwip\src\core\dns.c><dns.c>
File 5,1,<..\..\net\lwip\src\core\init.c><init.c>
File 5,1,<..\..\net\lwip\src\core\memp_tiny.c><memp_tiny.c>
File 5,1,<..\..\net\lwip\src\core\netif.c><netif.c>
File 5,1,<..\..\net\lwip\src\core\pbuf.c><pbuf.c>
File 5,1,<..\..\net\lwip\src\core\raw.c><raw.c>
File 5,1,<..\..\net\lwip\src\core\stats.c><stats.c>
File 5,1,<..\..\net\lwip\src\core\sys.c><sys.c>
File 5,1,<..\..\net\lwip\src\core\tcp.c><tcp.c>
File 5,1,<..\..\net\lwip\src\core\tcp_in.c><tcp_in.c>
File 5,1,<..\..\net\lwip\src\core\tcp_out.c><tcp_out.c>
File 5,1,<..\..\net\lwip\src\core\udp.c><udp.c>
File 5,1,<..\..\net\lwip\src\core\ipv4\ip_frag.c><ip_frag.c>
File 5,1,<..\..\net\lwip\src\core\ipv4\autoip.c><autoip.c>
File 5,1,<..\..\net\lwip\src\core\ipv4\icmp.c><icmp.c>
File 5,1,<..\..\net\lwip\src\core\ipv4\igmp.c><igmp.c>
File 5,1,<..\..\net\lwip\src\core\ipv4\inet.c><inet.c>
File 5,1,<..\..\net\lwip\src\core\ipv4\inet_chksum.c><inet_chksum.c>
File 5,1,<..\..\net\lwip\src\core\ipv4\ip.c><ip.c>
File 5,1,<..\..\net\lwip\src\core\ipv4\ip_addr.c><ip_addr.c>
File 5,1,<..\..\net\lwip\src\netif\ethernetif.c><ethernetif.c>
File 5,1,<..\..\net\lwip\src\netif\etharp.c><etharp.c>
File 5,1,<..\..\net\lwip\src\arch\sys_arch_init.c><sys_arch_init.c>
File 5,1,<..\..\net\lwip\src\arch\sys_arch.c><sys_arch.c>
File 5,1,<..\..\net\lwip\src\api\tcpip.c><tcpip.c>
File 5,1,<..\..\net\lwip\src\api\api_lib.c><api_lib.c>
File 5,1,<..\..\net\lwip\src\api\api_msg.c><api_msg.c>
File 5,1,<..\..\net\lwip\src\api\err.c><err.c>
File 5,1,<..\..\net\lwip\src\api\netbuf.c><netbuf.c>
File 5,1,<..\..\net\lwip\src\api\netdb.c><netdb.c>
File 5,1,<..\..\net\lwip\src\api\netifapi.c><netifapi.c>
File 5,1,<..\..\net\lwip\src\api\sockets.c><sockets.c>
File 6,1,<..\..\finsh\cmd.c><cmd.c>
File 6,1,<..\..\finsh\finsh_compiler.c><finsh_compiler.c>
File 6,1,<..\..\finsh\finsh_error.c><finsh_error.c>
File 6,1,<..\..\finsh\finsh_heap.c><finsh_heap.c>
File 6,1,<..\..\finsh\finsh_init.c><finsh_init.c>
File 6,1,<..\..\finsh\finsh_node.c><finsh_node.c>
File 6,1,<..\..\finsh\finsh_ops.c><finsh_ops.c>
File 6,1,<..\..\finsh\finsh_parser.c><finsh_parser.c>
File 6,1,<..\..\finsh\finsh_token.c><finsh_token.c>
File 6,1,<..\..\finsh\finsh_var.c><finsh_var.c>
File 6,1,<..\..\finsh\finsh_vm.c><finsh_vm.c>
File 6,1,<..\..\finsh\shell.c><shell.c>
File 6,1,<..\..\finsh\symbol.c><symbol.c>
File 7,1,<..\..\filesystem\dfs\src\dfs_cache.c><dfs_cache.c>
File 7,1,<..\..\filesystem\dfs\src\dfs_fs.c><dfs_fs.c>
File 7,1,<..\..\filesystem\dfs\src\dfs_init.c><dfs_init.c>
File 7,1,<..\..\filesystem\dfs\src\dfs_posix.c><dfs_posix.c>
File 7,1,<..\..\filesystem\dfs\src\dfs_raw.c><dfs_raw.c>
File 7,1,<..\..\filesystem\dfs\src\dfs_util.c><dfs_util.c>
File 7,1,<..\..\filesystem\dfs\filesystems\efsl\src\base\efs.c><efs.c>
File 7,1,<..\..\filesystem\dfs\filesystems\efsl\src\base\extract.c><extract.c>
File 7,1,<..\..\filesystem\dfs\filesystems\efsl\src\base\partition.c><partition.c>
File 7,1,<..\..\filesystem\dfs\filesystems\efsl\src\base\plibc.c><plibc.c>
File 7,1,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\dir.c><dir.c>
File 7,1,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\fat.c><fat.c>
File 7,1,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\file.c><file.c>
File 7,1,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\fs.c><fs.c>
File 7,1,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\ls.c><ls.c>
File 7,1,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\time.c><time.c>
File 7,1,<..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\ui.c><ui.c>
Options 1,0,0 // Target 'RT-Thread/STM32'
Device (STM32F103VB)
Vendor (STMicroelectronics)
Cpu (IRAM(0x20000000-0x20004FFF) IROM(0x8000000-0x801FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3"))
FlashUt ()
StupF ("STARTUP\ST\STM32F10x.s" ("STM32 Startup Code"))
FlashDR (UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000))
DevID (4223)
Rgf (stm32f10x_lib.h)
Mem ()
C ()
A ()
RL ()
OH ()
DBC_IFX ()
DBC_CMS ()
DBC_AMS ()
DBC_LMS ()
UseEnv=0
EnvBin ()
EnvInc ()
EnvLib ()
EnvReg (ÿST\STM32F10x\)
OrgReg (ÿST\STM32F10x\)
TgStat=16
OutDir (.\obj\)
OutName (rtthread-stm32)
GenApp=1
GenLib=0
GenHex=0
Debug=1
Browse=1
LstDir (.\obj\)
HexSel=1
MG32K=0
TGMORE=0
RunUsr 0 0 <>
RunUsr 1 0 <>
BrunUsr 0 0 <>
BrunUsr 1 0 <>
CrunUsr 0 0 <>
CrunUsr 1 0 <>
SVCSID <>
GLFLAGS=1790
ADSFLGA { 243,31,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
ACPUTYP ("Cortex-M3")
RVDEV ()
ADSTFLGA { 0,12,0,2,99,0,1,66,0,0,0,0,0,0,0,0,0,0,0,0 }
OCMADSOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
OCMADSIRAM { 0,0,0,0,32,0,80,0,0 }
OCMADSIROM { 1,0,0,0,8,0,0,2,0 }
OCMADSXRAM { 0,0,0,0,0,0,0,0,0 }
OCR_RVCT { 1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,8,0,0,2,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,80,0,0,0,0,0,0,0,0,0,0,0 }
RV_STAVEC ()
ADSCCFLG { 17,0,0,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
ADSCMISC ()
ADSCDEFN ()
ADSCUDEF ()
ADSCINCD (.;.\library\inc;..\..\include;..\..\finsh;..\..\libcpu\arm\stm32;..\..\net\lwip\src;..\..\net\lwip\src\include;..\..\net\lwip\src\arch\include;..\..\net\lwip\src\include\ipv4;..\..\filesystem\dfs;..\..\filesystem\dfs\include;..\..\filesystem\dfs\filesystems\efsl\src\include;..\..\filesystem\dfs\filesystems\efsl\src\base\include;..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\include)
ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
ADSAMISC ()
ADSADEFN ()
ADSAUDEF ()
ADSAINCD ()
PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
IncBld=1
AlwaysBuild=0
GenAsm=0
AsmAsm=0
PublicsOnly=0
StopCode=3
CustArgs ()
LibMods ()
ADSLDFG { 17,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
ADSLDTA (0x08000000)
ADSLDDA (0x20000000)
ADSLDSC ()
ADSLDIB ()
ADSLDIC ()
ADSLDMC (--keep __fsym_* --keep __vsym_*)
ADSLDIF ()
ADSLDDW ()
OPTDL (SARMCM3.DLL)()(DARMSTM.DLL)(-pSTM32F103VB)(SARMCM3.DLL)()(TARMSTM.DLL)(-pSTM32F103VB)
OPTDBG 49149,6,()()()()()()()()()() (Segger\JLTAgdi.dll)()()()
FLASH1 { 9,0,0,0,1,0,0,0,4,16,0,0,0,0,0,0,0,0,0,0 }
FLASH2 (Segger\JLTAgdi.dll)
FLASH3 ("" ())
FLASH4 ()
EndOpt

217
bsp/stm32f103vb_lwip/rtc.c Normal file
View File

@ -0,0 +1,217 @@
#include <rtthread.h>
#include "stm32f10x_lib.h"
static struct rt_device rtc;
static rt_err_t rt_rtc_open(rt_device_t dev, rt_uint16_t oflag)
{
if (dev->rx_indicate != RT_NULL)
{
/* Open Interrupt */
}
return RT_EOK;
}
static rt_size_t rt_rtc_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
{
return 0;
}
static rt_err_t rt_rtc_control(rt_device_t dev, rt_uint8_t cmd, void *args)
{
rt_time_t *time;
RT_ASSERT(dev != RT_NULL);
switch (cmd)
{
case RT_DEVICE_CTRL_RTC_GET_TIME:
time = (rt_time_t *)args;
/* read device */
*time = RTC_GetCounter();
break;
case RT_DEVICE_CTRL_RTC_SET_TIME:
{
time = (rt_time_t *)args;
/* Enable PWR and BKP clocks */
RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE);
/* Allow access to BKP Domain */
PWR_BackupAccessCmd(ENABLE);
/* Wait until last write operation on RTC registers has finished */
RTC_WaitForLastTask();
/* Change the current time */
RTC_SetCounter(*time);
/* Wait until last write operation on RTC registers has finished */
RTC_WaitForLastTask();
BKP_WriteBackupRegister(BKP_DR1, 0xA5A5);
}
break;
}
return RT_EOK;
}
/*******************************************************************************
* Function Name : RTC_Configuration
* Description : Configures the RTC.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void RTC_Configuration(void)
{
/* Enable PWR and BKP clocks */
RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE);
/* Allow access to BKP Domain */
PWR_BackupAccessCmd(ENABLE);
/* Reset Backup Domain */
BKP_DeInit();
/* Enable LSE */
RCC_LSEConfig(RCC_LSE_ON);
/* Wait till LSE is ready */
while (RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET)
{
}
/* Select LSE as RTC Clock Source */
RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE);
/* Enable RTC Clock */
RCC_RTCCLKCmd(ENABLE);
/* Wait for RTC registers synchronization */
RTC_WaitForSynchro();
/* Wait until last write operation on RTC registers has finished */
RTC_WaitForLastTask();
/* Set RTC prescaler: set RTC period to 1sec */
RTC_SetPrescaler(32767); /* RTC period = RTCCLK/RTC_PR = (32.768 KHz)/(32767+1) */
/* Wait until last write operation on RTC registers has finished */
RTC_WaitForLastTask();
}
void rt_hw_rtc_init(void)
{
rtc.type = RT_Device_Class_RTC;
if (BKP_ReadBackupRegister(BKP_DR1) != 0xA5A5)
{
rt_kprintf("rtc is not configured\n");
rt_kprintf("please configure with set_date and set_time\n");
RTC_Configuration();
}
else
{
/* Wait for RTC registers synchronization */
RTC_WaitForSynchro();
}
/* register rtc device */
rtc.init = RT_NULL;
rtc.open = rt_rtc_open;
rtc.close = RT_NULL;
rtc.read = rt_rtc_read;
rtc.write = RT_NULL;
rtc.control = rt_rtc_control;
/* no private */
rtc.private = RT_NULL;
rt_device_register(&rtc, "rtc", RT_DEVICE_FLAG_RDWR);
return;
}
#ifdef RT_USING_FINSH
#include <finsh.h>
#include <time.h>
time_t time(time_t* t)
{
rt_device_t device;
time_t time;
device = rt_device_find("rtc");
if (device != RT_NULL)
{
rt_device_control(device, RT_DEVICE_CTRL_RTC_GET_TIME, &time);
if (t != RT_NULL) *t = time;
}
return time;
}
void set_date(rt_uint32_t year, rt_uint32_t month, rt_uint32_t day)
{
time_t now;
struct tm* ti;
rt_device_t device;
ti = RT_NULL;
/* get current time */
time(&now);
ti = localtime(&now);
if (ti != RT_NULL)
{
ti->tm_year = year - 1900;
ti->tm_mon = month;
ti->tm_mday = day;
}
now = mktime(ti);
device = rt_device_find("rtc");
if (device != RT_NULL)
{
rt_rtc_control(device, RT_DEVICE_CTRL_RTC_SET_TIME, &now);
}
}
FINSH_FUNCTION_EXPORT(set_date, set date)
void set_time(rt_uint32_t hour, rt_uint32_t minute, rt_uint32_t second)
{
time_t now;
struct tm* ti;
rt_device_t device;
ti = RT_NULL;
/* get current time */
time(&now);
ti = localtime(&now);
if (ti != RT_NULL)
{
ti->tm_hour = hour;
ti->tm_min = minute;
ti->tm_sec = second;
}
now = mktime(ti);
device = rt_device_find("rtc");
if (device != RT_NULL)
{
rt_rtc_control(device, RT_DEVICE_CTRL_RTC_SET_TIME, &now);
}
}
FINSH_FUNCTION_EXPORT(set_time, set second)
void list_date()
{
time_t now;
time(&now);
rt_kprintf("%s\n", ctime(&now));
}
FINSH_FUNCTION_EXPORT(list_date, set date)
#endif

6
bsp/stm32f103vb_lwip/rtc.h Normal file
View File

@ -0,0 +1,6 @@
#ifndef __RTC_H__
#define __RTC_H__
void rt_hw_rtc_init(void);
#endif

145
bsp/stm32f103vb_lwip/rtconfig.h Normal file
View File

@ -0,0 +1,145 @@
/* RT-Thread config file */
#ifndef __RTTHREAD_CFG_H__
#define __RTTHREAD_CFG_H__
/* RT_NAME_MAX*/
#define RT_NAME_MAX 8
/* RT_ALIGN_SIZE*/
#define RT_ALIGN_SIZE 4
/* PRIORITY_MAX*/
#define RT_THREAD_PRIORITY_MAX 32
/* Tick per Second*/
#define RT_TICK_PER_SECOND 100
/* SECTION: RT_DEBUG */
/* Thread Debug*/
/* #define RT_DEBUG */
/* #define RT_THREAD_DEBUG */
/* Using Hook*/
#define RT_USING_HOOK
/* SECTION: IPC */
/* Using Semaphore*/
#define RT_USING_SEMAPHORE
/* Using Mutex*/
#define RT_USING_MUTEX
/* Using Event*/
#define RT_USING_EVENT
/* Using Faset Event*/
/* #define RT_USING_FASTEVENT */
/* Using MailBox*/
#define RT_USING_MAILBOX
/* Using Message Queue*/
#define RT_USING_MESSAGEQUEUE
/* SECTION: Memory Management */
/* Using Memory Pool Management*/
#define RT_USING_MEMPOOL
/* Using Dynamic Heap Management*/
#define RT_USING_HEAP
/* Using Small MM*/
#define RT_USING_SMALL_MEM
/* Using SLAB Allocator*/
/* #define RT_USING_SLAB */
/* SECTION: Device System */
/* Using Device System*/
#define RT_USING_DEVICE
#define RT_USING_UART1
/* #define RT_USING_UART2 */
/* #define RT_USING_UART3 */
/* SECTION: Console options */
/* the buffer size of console*/
#define RT_CONSOLEBUF_SIZE 128
/* SECTION: FinSH shell options */
/* Using FinSH as Shell*/
#define RT_USING_FINSH
/* Using symbol table */
#define FINSH_USING_SYMTAB
#define FINSH_USING_DESCRIPTION
/* SECTION: a mini libc */
/* Using mini libc library*/
/* #define RT_USING_MINILIBC */
/* SECTION: C++ support */
/* Using C++ support*/
/* #define RT_USING_CPLUSPLUS */
/* SECTION: DFS options */
#define RT_USING_DFS
/* the max number of mounted filesystem */
#define DFS_FILESYSTEMS_MAX 1
/* the max number of opened files */
#define DFS_FD_MAX 2
/* the max number of cached sector */
#define DFS_CACHE_MAX_NUM 4
/* SECTION: lwip, a lighwight TCP/IP protocol stack */
/* Using lighweight TCP/IP protocol stack*/
/* #define RT_USING_LWIP */
/* Trace LwIP protocol*/
/* #define RT_LWIP_DEBUG */
/* Enable ICMP protocol*/
#define RT_LWIP_ICMP
/* Enable IGMP protocol*/
#define RT_LWIP_IGMP
/* Enable UDP protocol*/
#define RT_LWIP_UDP
/* Enable TCP protocol*/
#define RT_LWIP_TCP
/* Enable SNMP protocol*/
/* #define RT_LWIP_SNMP */
/* Using DHCP*/
/* #define RT_LWIP_DHCP */
/* ip address of target*/
#define RT_LWIP_IPADDR0 192
#define RT_LWIP_IPADDR1 168
#define RT_LWIP_IPADDR2 1
#define RT_LWIP_IPADDR3 30
/* gateway address of target*/
#define RT_LWIP_GWADDR0 192
#define RT_LWIP_GWADDR1 168
#define RT_LWIP_GWADDR2 1
#define RT_LWIP_GWADDR3 1
/* mask address of target*/
#define RT_LWIP_MSKADDR0 255
#define RT_LWIP_MSKADDR1 255
#define RT_LWIP_MSKADDR2 255
#define RT_LWIP_MSKADDR3 0
/* tcp thread options */
#define RT_LWIP_TCPTHREAD_PRIORITY 12
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 4
#define RT_LWIP_TCPTHREAD_STACKSIZE 1024
/* ethernet if thread options */
#define RT_LWIP_ETHTHREAD_PRIORITY 15
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 4
#define RT_LWIP_ETHTHREAD_STACKSIZE 1024
#endif

147
bsp/stm32f103vb_lwip/startup.c Normal file
View File

@ -0,0 +1,147 @@
/*
* File : startup.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://openlab.rt-thread.com/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2006-08-31 Bernard first implementation
*/
#include <rthw.h>
#include <rtthread.h>
#include "board.h"
#include "rtc.h"
#ifdef RT_USING_LWIP
#include <netif/ethernetif.h>
#include "enc28j60.h"
#endif
/**
* @addtogroup STM32
*/
/*@{*/
#ifdef RT_USING_FINSH
extern void finsh_system_init(void);
extern void finsh_set_device(char* device);
#endif
extern int rt_application_init(void);
#ifdef __CC_ARM
extern int Image$$RW_IRAM1$$ZI$$Limit;
#elif __ICCARM__
#pragma section="HEAP"
#else
extern int __bss_end;
#endif
#ifdef DEBUG
/*******************************************************************************
* Function Name : assert_failed
* Description : Reports the name of the source file and the source line number
* where the assert error has occurred.
* Input : - file: pointer to the source file name
* - line: assert error line source number
* Output : None
* Return : None
*******************************************************************************/
void assert_failed(u8* file, u32 line)
{
rt_kprintf("\n\r Wrong parameter value detected on\r\n");
rt_kprintf(" file %s\r\n", file);
rt_kprintf(" line %d\r\n", line);
while (1) ;
}
#endif
/**
* This function will startup RT-Thread RTOS.
*/
void rtthread_startup(void)
{
/* init board */
rt_hw_board_init();
/* show version */
rt_show_version();
/* init tick */
rt_system_tick_init();
/* init kernel object */
rt_system_object_init();
/* init timer system */
rt_system_timer_init();
#ifdef RT_USING_HEAP
#ifdef __CC_ARM
rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x20005000);
#elif __ICCARM__
rt_system_heap_init(__segment_end("HEAP"), (void*)0x20005000);
#else
/* init memory system */
rt_system_heap_init((void*)&__bss_end, (void*)0x20005000);
#endif
#endif
/* init scheduler system */
rt_system_scheduler_init();
#ifdef RT_USING_LWIP
eth_system_device_init();
/* register ethernetif device */
rt_hw_enc28j60_init();
#endif
rt_hw_rtc_init();
/* init hardware serial device */
rt_hw_usart_init();
#ifdef RT_USING_DFS
rt_hw_sdcard_init();
#endif
/* init all device */
rt_device_init_all();
/* init application */
rt_application_init();
#ifdef RT_USING_FINSH
/* init finsh */
finsh_system_init();
finsh_set_device("uart1");
#endif
/* init idle thread */
rt_thread_idle_init();
/* start scheduler */
rt_system_scheduler_start();
/* never reach here */
return ;
}
int main(void)
{
rt_uint32_t UNUSED level;
/* disable interrupt first */
level = rt_hw_interrupt_disable();
rtthread_startup();
return 0;
}
/*@}*/

154
bsp/stm32f103vb_lwip/stm32f10x_conf.h Normal file
View File

@ -0,0 +1,154 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_conf.h
* Author : MCD Application Team
* Version : V1.1.2
* Date : 09/22/2008
* Description : Library configuration file.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_CONF_H
#define __STM32F10x_CONF_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_type.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Uncomment the line below to compile the library in DEBUG mode, this will expanse
the "assert_param" macro in the firmware library code (see "Exported macro"
section below) */
/* #define DEBUG 1*/
/* Comment the line below to disable the specific peripheral inclusion */
/************************************* ADC ************************************/
#define _ADC
#define _ADC1
/************************************* BKP ************************************/
#define _BKP
/************************************* CAN ************************************/
#define _CAN
/************************************* CRC ************************************/
#define _CRC
/************************************* DAC ************************************/
#define _DAC
/************************************* DBGMCU *********************************/
#define _DBGMCU
/************************************* DMA ************************************/
#define _DMA
#define _DMA1_Channel1
#define _DMA1_Channel2
#define _DMA1_Channel3
#define _DMA1_Channel4
#define _DMA1_Channel5
#define _DMA1_Channel6
#define _DMA1_Channel7
/************************************* EXTI ***********************************/
#define _EXTI
/************************************* FLASH and Option Bytes *****************/
#define _FLASH
/* Uncomment the line below to enable FLASH program/erase/protections functions,
otherwise only FLASH configuration (latency, prefetch, half cycle) functions
are enabled */
/* #define _FLASH_PROG */
/************************************* GPIO ***********************************/
#define _GPIO
#define _GPIOA
#define _GPIOB
#define _GPIOC
#define _GPIOD
#define _GPIOE
#define _GPIOF
#define _GPIOG
#define _AFIO
/************************************* I2C ************************************/
#define _I2C
#define _I2C1
#define _I2C2
/************************************* IWDG ***********************************/
#define _IWDG
/************************************* NVIC ***********************************/
#define _NVIC
/************************************* PWR ************************************/
#define _PWR
/************************************* RCC ************************************/
#define _RCC
/************************************* RTC ************************************/
#define _RTC
/************************************* SPI ************************************/
#define _SPI
#define _SPI1
#define _SPI2
/************************************* SysTick ********************************/
#define _SysTick
/************************************* TIM ************************************/
#define _TIM
#define _TIM1
#define _TIM2
#define _TIM3
#define _TIM4
/************************************* USART **********************************/
#define _USART
#define _USART1
#define _USART2
#define _USART3
/************************************* WWDG ***********************************/
#define _WWDG
/* In the following line adjust the value of External High Speed oscillator (HSE)
used in your application */
#define HSE_Value ((u32)8000000) /* Value of the External oscillator in Hz*/
/* In the following line adjust the External High Speed oscillator (HSE) Startup
Timeout value */
#define HSEStartUp_TimeOut ((u16)0x0500) /* Time out for HSE start up */
/* Exported macro ------------------------------------------------------------*/
#ifdef DEBUG
/*******************************************************************************
* Macro Name : assert_param
* Description : The assert_param macro is used for function's parameters check.
* It is used only if the library is compiled in DEBUG mode.
* Input : - expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* Return : None
*******************************************************************************/
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((u8 *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(u8* file, u32 line);
#else
#define assert_param(expr) ((void)0)
#endif /* DEBUG */
#endif /* __STM32F10x_CONF_H */
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

906
bsp/stm32f103vb_lwip/stm32f10x_it.c Normal file
View File

@ -0,0 +1,906 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_it.c
* Author : MCD Application Team
* Version : V1.1.2
* Date : 09/22/2008
* Description : Main Interrupt Service Routines.
* This file provides template for all exceptions handler
* and peripherals interrupt service routine.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include <rtthread.h>
#include <serial.h>
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
extern void rt_hw_timer_handler(void);
extern void rt_hw_interrupt_thread_switch(void);
/*******************************************************************************
* Function Name : NMIException
* Description : This function handles NMI exception.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void NMIException(void)
{
}
/*******************************************************************************
* Function Name : HardFaultException
* Description : This function handles Hard Fault exception.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void HardFaultException(void)
{
/* Go to infinite loop when Hard Fault exception occurs */
rt_kprintf("hard fault exception\n");
while (1)
{
}
}
/*******************************************************************************
* Function Name : MemManageException
* Description : This function handles Memory Manage exception.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void MemManageException(void)
{
/* Go to infinite loop when Memory Manage exception occurs */
rt_kprintf("memory manage exception\n");
while (1)
{
}
}
/*******************************************************************************
* Function Name : BusFaultException
* Description : This function handles Bus Fault exception.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void BusFaultException(void)
{
/* Go to infinite loop when Bus Fault exception occurs */
rt_kprintf("bus fault exception\n");
while (1)
{
}
}
/*******************************************************************************
* Function Name : UsageFaultException
* Description : This function handles Usage Fault exception.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void UsageFaultException(void)
{
/* Go to infinite loop when Usage Fault exception occurs */
rt_kprintf("usage fault exception\n");
while (1)
{
}
}
/*******************************************************************************
* Function Name : DebugMonitor
* Description : This function handles Debug Monitor exception.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void DebugMonitor(void)
{
}
/*******************************************************************************
* Function Name : SVCHandler
* Description : This function handles SVCall exception.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void SVCHandler(void)
{
}
/*******************************************************************************
* Function Name : SysTickHandler
* Description : This function handles SysTick Handler.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void SysTickHandler(void)
{
/* handle os tick */
rt_hw_timer_handler();
}
/*******************************************************************************
* Function Name : WWDG_IRQHandler
* Description : This function handles WWDG interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void WWDG_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : PVD_IRQHandler
* Description : This function handles PVD interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void PVD_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : TAMPER_IRQHandler
* Description : This function handles Tamper interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void TAMPER_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : RTC_IRQHandler
* Description : This function handles RTC global interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void RTC_IRQHandler(void)
{
if (RTC_GetITStatus(RTC_IT_SEC) != RESET)
{
/* Clear the RTC Second interrupt */
RTC_ClearITPendingBit(RTC_IT_SEC);
/* Wait until last write operation on RTC registers has finished */
RTC_WaitForLastTask();
/* Reset RTC Counter when Time is 23:59:59 */
if (RTC_GetCounter() == 0x00015180)
{
RTC_SetCounter(0x0);
/* Wait until last write operation on RTC registers has finished */
RTC_WaitForLastTask();
}
}
}
/*******************************************************************************
* Function Name : FLASH_IRQHandler
* Description : This function handles Flash interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void FLASH_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : RCC_IRQHandler
* Description : This function handles RCC interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void RCC_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : EXTI0_IRQHandler
* Description : This function handles External interrupt Line 0 request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void EXTI0_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : EXTI1_IRQHandler
* Description : This function handles External interrupt Line 1 request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void EXTI1_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : EXTI2_IRQHandler
* Description : This function handles External interrupt Line 2 request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void EXTI2_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : EXTI3_IRQHandler
* Description : This function handles External interrupt Line 3 request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void EXTI3_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : EXTI4_IRQHandler
* Description : This function handles External interrupt Line 4 request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void EXTI4_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : DMA1_Channel1_IRQHandler
* Description : This function handles DMA1 Channel 1 interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void DMA1_Channel1_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : DMA1_Channel2_IRQHandler
* Description : This function handles DMA1 Channel 2 interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void DMA1_Channel2_IRQHandler(void)
{
#ifdef RT_USING_UART3
extern struct rt_device uart3_device;
/* enter interrupt */
rt_interrupt_enter();
if (DMA_GetITStatus(DMA1_IT_TC2))
{
/* transmission complete, invoke serial dma tx isr */
rt_hw_serial_dma_tx_isr(&uart3_device);
}
/* clear DMA flag */
DMA_ClearFlag(DMA1_FLAG_TC2 | DMA1_FLAG_TE2);
/* leave interrupt */
rt_interrupt_leave();
rt_hw_interrupt_thread_switch();
#endif
}
/*******************************************************************************
* Function Name : DMA1_Channel3_IRQHandler
* Description : This function handles DMA1 Channel 3 interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void DMA1_Channel3_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : DMA1_Channel4_IRQHandler
* Description : This function handles DMA1 Channel 4 interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void DMA1_Channel4_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : DMA1_Channel5_IRQHandler
* Description : This function handles DMA1 Channel 5 interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void DMA1_Channel5_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : DMA1_Channel6_IRQHandler
* Description : This function handles DMA1 Channel 6 interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void DMA1_Channel6_IRQHandler(void)
{
#ifdef RT_USING_UART2
extern struct rt_device uart2_device;
/* enter interrupt */
rt_interrupt_enter();
/* clear DMA flag */
DMA_ClearFlag(DMA1_FLAG_TC6 | DMA1_FLAG_TE6);
rt_hw_serial_dma_rx_isr(&uart2_device);
/* leave interrupt */
rt_interrupt_leave();
rt_hw_interrupt_thread_switch();
#endif
}
/*******************************************************************************
* Function Name : DMA1_Channel7_IRQHandler
* Description : This function handles DMA1 Channel 7 interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void DMA1_Channel7_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : ADC1_2_IRQHandler
* Description : This function handles ADC1 and ADC2 global interrupts requests.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void ADC1_2_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : USB_HP_CAN_TX_IRQHandler
* Description : This function handles USB High Priority or CAN TX interrupts
* requests.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void USB_HP_CAN_TX_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : USB_LP_CAN_RX0_IRQHandler
* Description : This function handles USB Low Priority or CAN RX0 interrupts
* requests.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void USB_LP_CAN_RX0_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : CAN_RX1_IRQHandler
* Description : This function handles CAN RX1 interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void CAN_RX1_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : CAN_SCE_IRQHandler
* Description : This function handles CAN SCE interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void CAN_SCE_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : EXTI9_5_IRQHandler
* Description : This function handles External lines 9 to 5 interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void EXTI9_5_IRQHandler(void)
{
extern void enc28j60_isr(void);
/* enter interrupt */
rt_interrupt_enter();
enc28j60_isr();
/* Clear the Key Button EXTI line pending bit */
EXTI_ClearITPendingBit(EXTI_Line8);
/* leave interrupt */
rt_interrupt_leave();
rt_hw_interrupt_thread_switch();
}
/*******************************************************************************
* Function Name : TIM1_BRK_IRQHandler
* Description : This function handles TIM1 Break interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void TIM1_BRK_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : TIM1_UP_IRQHandler
* Description : This function handles TIM1 overflow and update interrupt
* request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void TIM1_UP_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : TIM1_TRG_COM_IRQHandler
* Description : This function handles TIM1 Trigger and commutation interrupts
* requests.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void TIM1_TRG_COM_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : TIM1_CC_IRQHandler
* Description : This function handles TIM1 capture compare interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void TIM1_CC_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : TIM2_IRQHandler
* Description : This function handles TIM2 global interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void TIM2_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : TIM3_IRQHandler
* Description : This function handles TIM3 global interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void TIM3_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : TIM4_IRQHandler
* Description : This function handles TIM4 global interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void TIM4_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : I2C1_EV_IRQHandler
* Description : This function handles I2C1 Event interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void I2C1_EV_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : I2C1_ER_IRQHandler
* Description : This function handles I2C1 Error interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void I2C1_ER_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : I2C2_EV_IRQHandler
* Description : This function handles I2C2 Event interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void I2C2_EV_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : I2C2_ER_IRQHandler
* Description : This function handles I2C2 Error interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void I2C2_ER_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : SPI1_IRQHandler
* Description : This function handles SPI1 global interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void SPI1_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : SPI2_IRQHandler
* Description : This function handles SPI2 global interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void SPI2_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : USART1_IRQHandler
* Description : This function handles USART1 global interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void USART1_IRQHandler(void)
{
#ifdef RT_USING_UART1
extern struct rt_device uart1_device;
/* enter interrupt */
rt_interrupt_enter();
rt_hw_serial_isr(&uart1_device);
/* leave interrupt */
rt_interrupt_leave();
rt_hw_interrupt_thread_switch();
#endif
}
/*******************************************************************************
* Function Name : USART2_IRQHandler
* Description : This function handles USART2 global interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void USART2_IRQHandler(void)
{
#ifdef RT_USING_UART2
extern struct rt_device uart2_device;
/* enter interrupt */
rt_interrupt_enter();
rt_hw_serial_isr(&uart2_device);
/* leave interrupt */
rt_interrupt_leave();
rt_hw_interrupt_thread_switch();
#endif
}
/*******************************************************************************
* Function Name : USART3_IRQHandler
* Description : This function handles USART3 global interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void USART3_IRQHandler(void)
{
#ifdef RT_USING_UART3
extern struct rt_device uart3_device;
/* enter interrupt */
rt_interrupt_enter();
rt_hw_serial_isr(&uart3_device);
/* leave interrupt */
rt_interrupt_leave();
rt_hw_interrupt_thread_switch();
#endif
}
/*******************************************************************************
* Function Name : EXTI15_10_IRQHandler
* Description : This function handles External lines 15 to 10 interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void EXTI15_10_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : RTCAlarm_IRQHandler
* Description : This function handles RTC Alarm interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void RTCAlarm_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : USBWakeUp_IRQHandler
* Description : This function handles USB WakeUp interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void USBWakeUp_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : TIM8_BRK_IRQHandler
* Description : This function handles TIM8 Break interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void TIM8_BRK_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : TIM8_UP_IRQHandler
* Description : This function handles TIM8 overflow and update interrupt
* request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void TIM8_UP_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : TIM8_TRG_COM_IRQHandler
* Description : This function handles TIM8 Trigger and commutation interrupts
* requests.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void TIM8_TRG_COM_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : TIM8_CC_IRQHandler
* Description : This function handles TIM8 capture compare interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void TIM8_CC_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : ADC3_IRQHandler
* Description : This function handles ADC3 global interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void ADC3_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : FSMC_IRQHandler
* Description : This function handles FSMC global interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void FSMC_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : SDIO_IRQHandler
* Description : This function handles SDIO global interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void SDIO_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : TIM5_IRQHandler
* Description : This function handles TIM5 global interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void TIM5_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : SPI3_IRQHandler
* Description : This function handles SPI3 global interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void SPI3_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : UART4_IRQHandler
* Description : This function handles UART4 global interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void UART4_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : UART5_IRQHandler
* Description : This function handles UART5 global interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void UART5_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : TIM6_IRQHandler
* Description : This function handles TIM6 global interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void TIM6_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : TIM7_IRQHandler
* Description : This function handles TIM7 global interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void TIM7_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : DMA2_Channel1_IRQHandler
* Description : This function handles DMA2 Channel 1 interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void DMA2_Channel1_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : DMA2_Channel2_IRQHandler
* Description : This function handles DMA2 Channel 2 interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void DMA2_Channel2_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : DMA2_Channel3_IRQHandler
* Description : This function handles DMA2 Channel 3 interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void DMA2_Channel3_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : DMA2_Channel4_5_IRQHandler
* Description : This function handles DMA2 Channel 4 and DMA2 Channel 5
* interrupt request.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void DMA2_Channel4_5_IRQHandler(void)
{
}
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

100
bsp/stm32f103vb_lwip/stm32f10x_it.h Normal file
View File

@ -0,0 +1,100 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_it.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains the headers of the interrupt handlers.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_IT_H
#define __STM32F10x_IT_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_lib.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void NMIException(void);
void HardFaultException(void);
void MemManageException(void);
void BusFaultException(void);
void UsageFaultException(void);
void DebugMonitor(void);
void SVCHandler(void);
void rt_hw_pend_sv(void);
void SysTickHandler(void);
void WWDG_IRQHandler(void);
void PVD_IRQHandler(void);
void TAMPER_IRQHandler(void);
void RTC_IRQHandler(void);
void FLASH_IRQHandler(void);
void RCC_IRQHandler(void);
void EXTI0_IRQHandler(void);
void EXTI1_IRQHandler(void);
void EXTI2_IRQHandler(void);
void EXTI3_IRQHandler(void);
void EXTI4_IRQHandler(void);
void DMA1_Channel1_IRQHandler(void);
void DMA1_Channel2_IRQHandler(void);
void DMA1_Channel3_IRQHandler(void);
void DMA1_Channel4_IRQHandler(void);
void DMA1_Channel5_IRQHandler(void);
void DMA1_Channel6_IRQHandler(void);
void DMA1_Channel7_IRQHandler(void);
void ADC1_2_IRQHandler(void);
void USB_HP_CAN_TX_IRQHandler(void);
void USB_LP_CAN_RX0_IRQHandler(void);
void CAN_RX1_IRQHandler(void);
void CAN_SCE_IRQHandler(void);
void EXTI9_5_IRQHandler(void);
void TIM1_BRK_IRQHandler(void);
void TIM1_UP_IRQHandler(void);
void TIM1_TRG_COM_IRQHandler(void);
void TIM1_CC_IRQHandler(void);
void TIM2_IRQHandler(void);
void TIM3_IRQHandler(void);
void TIM4_IRQHandler(void);
void I2C1_EV_IRQHandler(void);
void I2C1_ER_IRQHandler(void);
void I2C2_EV_IRQHandler(void);
void I2C2_ER_IRQHandler(void);
void SPI1_IRQHandler(void);
void SPI2_IRQHandler(void);
void USART1_IRQHandler(void);
void USART2_IRQHandler(void);
void USART3_IRQHandler(void);
void EXTI15_10_IRQHandler(void);
void RTCAlarm_IRQHandler(void);
void USBWakeUp_IRQHandler(void);
void TIM8_BRK_IRQHandler(void);
void TIM8_UP_IRQHandler(void);
void TIM8_TRG_COM_IRQHandler(void);
void TIM8_CC_IRQHandler(void);
void ADC3_IRQHandler(void);
void FSMC_IRQHandler(void);
void SDIO_IRQHandler(void);
void TIM5_IRQHandler(void);
void SPI3_IRQHandler(void);
void UART4_IRQHandler(void);
void UART5_IRQHandler(void);
void TIM6_IRQHandler(void);
void TIM7_IRQHandler(void);
void DMA2_Channel1_IRQHandler(void);
void DMA2_Channel2_IRQHandler(void);
void DMA2_Channel3_IRQHandler(void);
void DMA2_Channel4_5_IRQHandler(void);
#endif /* __STM32F10x_IT_H */
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

342
bsp/stm32f103vb_lwip/usart.c Normal file
View File

@ -0,0 +1,342 @@
#include "usart.h"
#include <serial.h>
#include <stm32f10x_lib.h>
#include <stm32f10x_map.h>
/*
* Use UART1 as console output and finsh input
* interrupt Rx and poll Tx (stream mode)
*
* Use UART2 with DMA Rx and poll Tx -- DMA channel 6
* Use UART3 with DMA Tx and interrupt Rx -- DMA channel 2
*
* USART DMA setting on STM32
* USART1 Tx --> DMA Channel 4
* USART1 Rx --> DMA Channel 5
* USART2 Tx --> DMA Channel 7
* USART2 Rx --> DMA Channel 6
* USART3 Tx --> DMA Channel 2
* USART3 Rx --> DMA Channel 3
*/
#ifdef RT_USING_UART1
struct stm32_serial_int_rx uart1_int_rx;
struct stm32_serial_device uart1 =
{
USART1,
&uart1_int_rx,
RT_NULL,
RT_NULL,
RT_NULL
};
struct rt_device uart1_device;
#endif
#ifdef RT_USING_UART2
struct stm32_serial_int_rx uart2_int_rx;
struct stm32_serial_dma_rx uart2_dma_rx;
struct stm32_serial_device uart2 =
{
USART2,
&uart2_int_rx,
&uart2_dma_rx,
RT_NULL,
RT_NULL
};
struct rt_device uart2_device;
#endif
#ifdef RT_USING_UART3
struct stm32_serial_int_rx uart3_int_rx;
struct stm32_serial_dma_tx uart3_dma_tx;
struct stm32_serial_device uart3 =
{
USART3,
&uart3_int_rx,
RT_NULL,
RT_NULL,
&uart3_dma_tx
};
struct rt_device uart3_device;
#endif
#define USART1_DR_Base 0x40013804
#define USART2_DR_Base 0x40004404
#define USART3_DR_Base 0x40004804
/* USART1_REMAP = 0 */
#define UART1_GPIO_TX GPIO_Pin_9
#define UART1_GPIO_RX GPIO_Pin_10
#define UART1_GPIO GPIOA
#define RCC_APBPeriph_UART1 RCC_APB2Periph_USART1
#define UART1_TX_DMA DMA1_Channel4
#define UART1_RX_DMA DMA1_Channel5
/* USART2_REMAP = 1 */
#define UART2_GPIO_TX GPIO_Pin_5
#define UART2_GPIO_RX GPIO_Pin_6
#define UART2_GPIO GPIOD
#define RCC_APBPeriph_UART2 RCC_APB1Periph_USART2
#define UART2_TX_DMA DMA1_Channel7
#define UART2_RX_DMA DMA1_Channel6
/* USART3_REMAP[1:0] = 00 */
#define UART3_GPIO_RX GPIO_Pin_11
#define UART3_GPIO_TX GPIO_Pin_10
#define UART3_GPIO GPIOB
#define RCC_APBPeriph_UART3 RCC_APB1Periph_USART3
#define UART3_TX_DMA DMA1_Channel2
#define UART3_RX_DMA DMA1_Channel3
static void RCC_Configuration(void)
{
RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
#ifdef RT_USING_UART1
/* Enable USART1 and GPIOA clocks */
RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOA, ENABLE);
#endif
#ifdef RT_USING_UART2
/* Enable GPIOD clocks */
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD, ENABLE);
/* Enable USART2 clock */
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
#endif
#ifdef RT_USING_UART3
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
/* Enable USART3 clock */
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);
#endif
#if defined (RT_USING_UART2) || defined (RT_USING_UART3)
/* DMA clock enable */
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
#endif
}
static void GPIO_Configuration(void)
{
GPIO_InitTypeDef GPIO_InitStructure;
#ifdef RT_USING_UART1
/* Configure USART1 Rx (PA.10) as input floating */
GPIO_InitStructure.GPIO_Pin = UART1_GPIO_RX;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_Init(UART1_GPIO, &GPIO_InitStructure);
/* Configure USART1 Tx (PA.09) as alternate function push-pull */
GPIO_InitStructure.GPIO_Pin = UART1_GPIO_TX;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(UART1_GPIO, &GPIO_InitStructure);
#endif
#ifdef RT_USING_UART2
/* Enable the USART2 Pins Software Remapping */
GPIO_PinRemapConfig(GPIO_Remap_USART2, ENABLE);
/* Configure USART2 Rx as input floating */
GPIO_InitStructure.GPIO_Pin = UART2_GPIO_RX;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_Init(UART2_GPIO, &GPIO_InitStructure);
/* Configure USART2 Tx as alternate function push-pull */
GPIO_InitStructure.GPIO_Pin = UART2_GPIO_TX;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_Init(UART2_GPIO, &GPIO_InitStructure);
#endif
#ifdef RT_USING_UART3
/* Configure USART3 Rx as input floating */
GPIO_InitStructure.GPIO_Pin = UART3_GPIO_RX;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_Init(UART3_GPIO, &GPIO_InitStructure);
/* Configure USART3 Tx as alternate function push-pull */
GPIO_InitStructure.GPIO_Pin = UART3_GPIO_TX;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_Init(UART3_GPIO, &GPIO_InitStructure);
#endif
}
static void NVIC_Configuration(void)
{
NVIC_InitTypeDef NVIC_InitStructure;
/* Configure the NVIC Preemption Priority Bits */
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_0);
#ifdef RT_USING_UART1
/* Enable the USART1 Interrupt */
NVIC_InitStructure.NVIC_IRQChannel = USART1_IRQChannel;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
#endif
#ifdef RT_USING_UART2
/* Enable the USART2 Interrupt */
NVIC_InitStructure.NVIC_IRQChannel = USART2_IRQChannel;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
/* Enable the DMA1 Channel6 Interrupt */
NVIC_InitStructure.NVIC_IRQChannel = DMA1_Channel6_IRQChannel;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
#endif
#ifdef RT_USING_UART3
/* Enable the USART3 Interrupt */
NVIC_InitStructure.NVIC_IRQChannel = USART3_IRQChannel;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
/* Enable the DMA1 Channel2 Interrupt */
NVIC_InitStructure.NVIC_IRQChannel = DMA1_Channel2_IRQChannel;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
#endif
}
static void DMA_Configuration(void)
{
DMA_InitTypeDef DMA_InitStructure;
/* fill init structure */
DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
#ifdef RT_USING_UART2
/* DMA1 Channel4 (triggered by USART2 Rx event) Config */
DMA_DeInit(UART2_RX_DMA);
DMA_InitStructure.DMA_PeripheralBaseAddr = USART2_DR_Base;
DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
DMA_InitStructure.DMA_MemoryBaseAddr = (u32)0;
DMA_InitStructure.DMA_BufferSize = 0;
DMA_Init(UART2_RX_DMA, &DMA_InitStructure);
DMA_ITConfig(UART2_RX_DMA, DMA_IT_TC | DMA_IT_TE, ENABLE);
DMA_ClearFlag(DMA1_FLAG_TC4);
#endif
#ifdef RT_USING_UART3
/* DMA1 Channel5 (triggered by USART3 Tx event) Config */
DMA_DeInit(UART3_TX_DMA);
DMA_InitStructure.DMA_PeripheralBaseAddr = USART3_DR_Base;
DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
DMA_InitStructure.DMA_MemoryBaseAddr = (u32)0;
DMA_InitStructure.DMA_BufferSize = 0;
DMA_Init(UART3_TX_DMA, &DMA_InitStructure);
DMA_ITConfig(UART3_TX_DMA, DMA_IT_TC | DMA_IT_TE, ENABLE);
DMA_ClearFlag(DMA1_FLAG_TC5);
#endif
}
/*
* Init all related hardware in here
* rt_hw_serial_init() will register all supported USART device
*/
void rt_hw_usart_init()
{
USART_InitTypeDef USART_InitStructure;
USART_ClockInitTypeDef USART_ClockInitStructure;
RCC_Configuration();
GPIO_Configuration();
NVIC_Configuration();
DMA_Configuration();
/* uart init */
#ifdef RT_USING_UART1
USART_InitStructure.USART_BaudRate = 115200;
USART_InitStructure.USART_WordLength = USART_WordLength_8b;
USART_InitStructure.USART_StopBits = USART_StopBits_1;
USART_InitStructure.USART_Parity = USART_Parity_No;
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
USART_ClockInitStructure.USART_Clock = USART_Clock_Disable;
USART_ClockInitStructure.USART_CPOL = USART_CPOL_Low;
USART_ClockInitStructure.USART_CPHA = USART_CPHA_2Edge;
USART_ClockInitStructure.USART_LastBit = USART_LastBit_Disable;
USART_Init(USART1, &USART_InitStructure);
USART_ClockInit(USART1, &USART_ClockInitStructure);
/* register uart1 */
rt_hw_serial_register(&uart1_device, "uart1",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
&uart1);
/* enable interrupt */
USART_ITConfig(USART1, USART_IT_RXNE, ENABLE);
#endif
#ifdef RT_USING_UART2
USART_InitStructure.USART_BaudRate = 115200;
USART_InitStructure.USART_WordLength = USART_WordLength_8b;
USART_InitStructure.USART_StopBits = USART_StopBits_1;
USART_InitStructure.USART_Parity = USART_Parity_No;
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
USART_ClockInitStructure.USART_Clock = USART_Clock_Disable;
USART_ClockInitStructure.USART_CPOL = USART_CPOL_Low;
USART_ClockInitStructure.USART_CPHA = USART_CPHA_2Edge;
USART_ClockInitStructure.USART_LastBit = USART_LastBit_Disable;
USART_Init(USART2, &USART_InitStructure);
USART_ClockInit(USART2, &USART_ClockInitStructure);
uart2_dma_rx.dma_channel= UART2_RX_DMA;
/* register uart2 */
rt_hw_serial_register(&uart2_device, "uart2",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_DMA_RX,
&uart2);
/* Enable USART2 DMA Rx request */
USART_DMACmd(USART2, USART_DMAReq_Rx , ENABLE);
#endif
#ifdef RT_USING_UART3
USART_InitStructure.USART_BaudRate = 115200;
USART_InitStructure.USART_WordLength = USART_WordLength_8b;
USART_InitStructure.USART_StopBits = USART_StopBits_1;
USART_InitStructure.USART_Parity = USART_Parity_No;
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
USART_ClockInitStructure.USART_Clock = USART_Clock_Disable;
USART_ClockInitStructure.USART_CPOL = USART_CPOL_Low;
USART_ClockInitStructure.USART_CPHA = USART_CPHA_2Edge;
USART_ClockInitStructure.USART_LastBit = USART_LastBit_Disable;
USART_Init(USART3, &USART_InitStructure);
USART_ClockInit(USART3, &USART_ClockInitStructure);
uart3_dma_tx.dma_channel= UART3_TX_DMA;
/* register uart3 */
rt_hw_serial_register(&uart3_device, "uart3",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_DMA_TX,
&uart3);
/* Enable USART3 DMA Tx request */
USART_DMACmd(USART3, USART_DMAReq_Tx , ENABLE);
/* enable interrupt */
USART_ITConfig(USART3, USART_IT_RXNE, ENABLE);
#endif
}

9
bsp/stm32f103vb_lwip/usart.h Normal file
View File

@ -0,0 +1,9 @@
#ifndef __USART_H__
#define __USART_H__
#include <rthw.h>
#include <rtthread.h>
void rt_hw_usart_init(void);
#endif

40
filesystem/dfs/config.mk Normal file
View File

@ -0,0 +1,40 @@
#+------------------------------------------------------------------------------
#| Device FileSystem
#+------------------------------------------------------------------------------
#| Copyright 2004, 2005 www.fayfayspace.org.
#| All rights reserved.
#+------------------------------------------------------------------------------
#| File : config.mk, the configuration of makefile
#+------------------------------------------------------------------------------
#| Chang Logs:
#| Date Author notes
#| 2005-01-22 ffxz The first version.
#+------------------------------------------------------------------------------
KERNEL_ROOT=$(DFS_ROOT_DIR)/../..
include $(KERNEL_ROOT)/config.mk
CFLAGS +=-I$(KERNEL_ROOT)/include -I$(DFS_ROOT_DIR)/include -I.
# Source and objects
DFS_SRC = $(DFS_ROOT_DIR)/src/dfs_fs.c $(DFS_ROOT_DIR)/src/dfs_init.c \
$(DFS_ROOT_DIR)/src/dfs_util.c $(DFS_ROOT_DIR)/src/dfs_raw.c \
$(DFS_ROOT_DIR)/src/dfs_api.c $(DFS_ROOT_DIR)/src/dfs_task.c \
$(DFS_ROOT_DIR)/src/dfs_cache.c
ifneq ($(RT_USING_NEWLIB), 1)
DFS_SRC += $(DFS_ROOT_DIR)/src/dfs_posix.c
endif
DFS_OBJS= $(DFS_SRC:.c=.o)
FAT_SRC = $(DFS_ROOT_DIR)/filesystems/fatfs/fatfs_init.c \
$(DFS_ROOT_DIR)/filesystems/fatfs/fatfs_mount.c \
$(DFS_ROOT_DIR)/filesystems/fatfs/fatfs_fat.c \
$(DFS_ROOT_DIR)/filesystems/fatfs/fatfs_misc.c \
$(DFS_ROOT_DIR)/filesystems/fatfs/fatfs_file.c \
$(DFS_ROOT_DIR)/filesystems/fatfs/fatfs_cache.c \
$(DFS_ROOT_DIR)/filesystems/fatfs/fatfs_filename.c \
$(DFS_ROOT_DIR)/filesystems/fatfs/fatfs_direntry.c \
$(DFS_ROOT_DIR)/filesystems/fatfs/fatfs_mkfs.c
FAT_OBJS = $(FAT_SRC:.c=.o)

100
filesystem/dfs/dfs_config.h Normal file
View File

@ -0,0 +1,100 @@
/*
+------------------------------------------------------------------------------
| Project : Device Filesystem
+------------------------------------------------------------------------------
| Copyright 2004, 2005 www.fayfayspace.org.
| All rights reserved.
|------------------------------------------------------------------------------
| File : dfs_opts.h, the option definitions of Device FileSystem
|------------------------------------------------------------------------------
| Chang Logs:
| Date Author Notes
| 2005-01-22 ffxz The first version.
+------------------------------------------------------------------------------
*/
#ifndef __DFS_CONFIG_H__
#define __DFS_CONFIG_H__
/*
+------------------------------------------------------------------------------
| Device Manager options
+------------------------------------------------------------------------------
*/
/* Device Options parameters */
#define DEVICES_MAX 8
#define DEVICE_NAME_MAX 8
/*
+------------------------------------------------------------------------------
| Device Filesystem options
+------------------------------------------------------------------------------
*/
/* the max length of filesystem name */
#define DFS_FS_NAME_MAX 4
/* the max type of filesystem */
#define DFS_FILESYSTEM_TYPES_MAX 2
/* the max length of path name */
#define DFS_PATH_MAX 256
/* the max length of file name */
#define DFS_FILE_MAX 256
/* options for server task */
#define DFS_MBOX_NUMBER 32
#define DFS_SERVER_STACK 1024
#define DFS_SERVER_PRI 110
#define DFS_SERVER_SLICE 20
/*
+------------------------------------------------------------------------------
| FAT filesystem options
+------------------------------------------------------------------------------
*/
/* file name max length */
#define FAT_NAME_MAX 256
/* max number of FAT filesystem */
#define FATFS_MAX 2
/* the size of sector */
#define SECTOR_SIZE 512
/* FAT table sector cache options */
#define FAT_CACHE_SIZE 0x10 /* config parameter */
#define FAT_CACHE_MASK (FAT_CACHE_SIZE-1)
#define GET16(x) (*(x)) | (*((x)+1) << 8)
#define GET32(x) (*(x)) | (*((x)+1) << 8) | (*((x)+2) << 16) | (*((x)+3) << 24)
#define SET16(x, v) \
do \
{ \
*(x) = (v) & 0x00ff; \
(*((x)+1)) = (v) >> 8; \
} while ( 0 )
#define SET32(x, v) \
do \
{ \
*(x) = (v) & 0x000000ff; \
(*((x)+1)) = ((v) >> 8) & 0x000000ff; \
(*((x)+2)) = ((v) >> 16) & 0x000000ff; \
(*((x)+3)) = ((v) >> 24); \
} while ( 0 )
#define DFS_DEBUG_INFO 0x01
#define DFS_DEBUG_WARNING 0x02
#define DFS_DEBUG_ERROR 0x04
#define DFS_DEBUG_LEVEL (DFS_DEBUG_INFO | DFS_DEBUG_WARNING | DFS_DEBUG_ERROR)
/* #define DFS_DEBUG */
#ifdef DFS_DEBUG
#define dfs_log(level, x) do { if (level & DFS_DEBUG_LEVEL) \
{rt_kprintf("DFS %s, %d:", __FILE__, __LINE__); rt_kprintf x; \
rt_kprintf ("\n");}}while (0)
#else
#define dfs_log(level, x)
#endif
#endif

39
filesystem/dfs/filesystems/efsl/CHANGELOG Normal file
View File

@ -0,0 +1,39 @@
CHANGEFILE
----------
This is the Changefile for the development 0.3 branch of EFSL.
Recording began with EFSL-0.3.3
0.3.5
-----
* Added warning in documentation that it is outdated
* Changed structure definitions
* Implemnted full-feature cp
* Renamed some efsl-functions (all starting with EFSL_)
* Added another example for AVR.
* Updated docs on getting started on AVR.
0.3.4
-----
* Fixed avr support
* Created new avr example + makefile
* Some more work on new fsutils
0.3.3
-----
* Renamed src/core to src/base
* Implemented new hwInterface structure
Support for multiple hwEndpoints in one project
* Modified SD_SPI to work as a general protocol
* Modified Linuxfile to the new hwInterface model
* Created a new efs_configger, now supports every
combination of partitions/disc
* Implemented full support for little and big endian
machines, as well as for little and big endian
filesystems
* Created new build system, for multiple platforms,
configurable from one file
* Changes cpo to use the new library functions
* Broke both dsp & atmega support

3
filesystem/dfs/filesystems/efsl/VERSION Normal file
View File

@ -0,0 +1,3 @@
efsl-0.3.6
[Embedded Filesystems Library]

182
filesystem/dfs/filesystems/efsl/src/base/debug.c Normal file
View File

@ -0,0 +1,182 @@
/*****************************************************************************\
* EFSL - Embedded Filesystems Library *
* ----------------------------------- *
* *
* Filename : debug.c *
* Release : 0.3 - devel *
* Description : These functions are used for debugging output on different *
* environments *
* *
* This program is free software; you can redistribute it and/or *
* modify it under the terms of the GNU General Public License *
* as published by the Free Software Foundation; version 2 *
* of the License. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* As a special exception, if other files instantiate templates or *
* use macros or inline functions from this file, or you compile this *
* file and link it with other works to produce a work based on this file, *
* this file does not by itself cause the resulting work to be covered *
* by the GNU General Public License. However the source code for this *
* file must still be made available in accordance with section (3) of *
* the GNU General Public License. *
* *
* This exception does not invalidate any other reasons why a work based *
* on this file might be covered by the GNU General Public License. *
* *
* (c)2006 Lennart Yseboodt *
* (c)2006 Michael De Nil *
\*****************************************************************************/
/* COMMENT REGARDING FUNCTION COMMENTS IN THIS FILE
* Only the linuxfile debug functions are commented since all functions
* perform the same logical task.
*/
/*****************************************************************************/
#include "debug.h"
/*****************************************************************************/
/*****************************************************************************/
#ifdef DEBUG
#ifdef HW_ENDPOINT_LINUX_ALL
/*****************************************************************************/
/* ****************************************************************************
* void debug(const eint8 *format, ...)
* Description: This function prints debug output to the screen (target dependant)
* and if DO_FUNC_DEBUG is defined also to a localfile.
* Return value: void
*/
void debug(const eint8 *format, ...)
{
va_list ap;
#ifdef DO_FUNC_DEBUG
euint8 c;
extern FILE* debugfile;
extern volatile euint8 tw;
#endif
va_start(ap, format);
vprintf(format,ap);
#ifdef DO_FUNC_DEBUG
for(c=0;c<tw+1;c++)
{
fprintf(debugfile," ");
}
vfprintf(debugfile,format,ap);
#endif
va_end(ap);
}
/*****************************************************************************/
/* ****************************************************************************
* void debug_funcin(const eint8 *format, ...)
* Description: This function marks the entrance of a function, which
* increments a tabfieldcounter. A tree like structure can the be found in the
* debugging file.
* Return value: void
*/
void debug_funcin(const eint8 *format, ...)
{
#ifdef DO_FUNC_DEBUG
eint8 c;
va_list ap;
extern FILE* debugfile;
extern volatile unsigned char tw;
if(debugfile==RT_NULL)return;
for(c=0;c<tw;c++){
fprintf(debugfile," ");
}
va_start(ap, format);
vfprintf(debugfile,format,ap);
va_end(ap);
fprintf(debugfile,"\n");
tw++;
#endif
}
/*****************************************************************************/
/* ****************************************************************************
* void debug_funcout(const eint8 *format, ...)
* Description: Decrements the tabfieldcounter. This function is called everywhere
* a function is left.
* Return value: void
*/
void debug_funcout(const eint8 *format, ...)
{
#ifdef DO_FUNC_DEBUG
eint8 c;
va_list ap;
extern FILE* debugfile;
extern volatile euint8 tw;
if(debugfile==RT_NULL)return;
if(tw>0)tw--;
for(c=0;c<tw;c++){
fprintf(debugfile," ");
}
va_start(ap, format);
vfprintf(debugfile,format,ap);
va_end(ap);
fprintf(debugfile,"\n");
#endif
}
/*****************************************************************************/
/* ****************************************************************************
* void debug_init()
* Description: This function optionally opens the debugfile, or does any other
* initialisation to enable debugoutput.
* Return value: void
*/
void debug_init()
{
#ifdef DO_FUNC_DEBUG
extern FILE* debugfile;
extern volatile unsigned char tw;
debugfile=RT_NULL;
tw=0;
debugfile=fopen("DBG.OUT","w");
#endif
}
/*****************************************************************************/
/* ****************************************************************************
* void debug_end()
* Description: This function closes the debugfile.
* Return value: void
*/
void debug_end()
{
#ifdef DO_FUNC_DEBUG
extern FILE* debugfile;
fflush(debugfile);
fclose(debugfile);
#endif
}
/*****************************************************************************/
/*****************************************************************************/
#endif
#endif
/*****************************************************************************/

489
filesystem/dfs/filesystems/efsl/src/base/efs.c Normal file
View File

@ -0,0 +1,489 @@
/*
* File : efs.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, 2007, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://openlab.rt-thread.com/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2008-08-16 Yi.Qiu The first version.
*/
#include "efs.h"
#include "ls.h"
#include "ui.h"
#include "fat.h"
#include <string.h>
#define EFS_MAX 2
struct dfs_filesystem_operation efs;
/**
* This function will initialize efsl to DFS interface.
*
* @return 0 on succesful
*/
int efsl_init()
{
/* init EFS filesystem operations */
efs.name[0] = 'e';
efs.name[1] = 'f';
efs.name[2] = 's';
efs.name[3] = '\0';
efs.mount = efs_mount;
efs.unmount = efs_unmount;
efs.open = efs_open;
efs.close = efs_close;
efs.ioctl = efs_ioctl;
efs.read = efs_read;
efs.write = efs_write;
efs.lseek = efs_lseek;
efs.getdents= efs_getdents;
efs.unlink = efs_unlink;
efs.stat = efs_stat;
efs.rename = efs_rename;
/* register EFS file system */
dfs_register(&efs);
return 0;
}
/**
* This function will set a hook function, which will be invoked when a memory
* block is allocated from heap memory.
*
* @param hook the hook function
*/
int efs_mount(struct dfs_filesystem* fs)
{
efsl_fs* efsfs;
int result;
/* allocate an EFS filesystem entry */
efsfs = (efsl_fs*) rt_malloc (sizeof(efsl_fs));
/* init efs filesystem struct */
efsfs->partition.ioman = rt_malloc(sizeof(IOManager));
efsfs->partition.ioman->device = fs->dev_id;
part_initPartition(&efsfs->partition);
ioman_init(efsfs->partition.ioman);
result = fs_initFs(&efsfs->filesystem ,&efsfs->partition);
/* set to DFS filesystem user data */
fs->data = efsfs;
return result;
}
/**
* This function will set a hook function, which will be invoked when a memory
* block is allocated from heap memory.
*
* @param hook the hook function
*/
int efs_unmount(struct dfs_filesystem* fs)
{
efsl_fs* efsfs;
efsfs = (efsl_fs*) fs->data;
if ( efsfs == RT_NULL ) return -DFS_STATUS_EINVAL;
fs_flushFs(&efsfs->filesystem);
rt_free(efsfs->partition.ioman);
rt_free(efsfs);
fs->data = RT_NULL;
return 0;
}
/**
* This function will set a hook function, which will be invoked when a memory
* block is allocated from heap memory.
*
* @param hook the hook function
*/
int efs_open(struct dfs_fd* file)
{
File* efsfile;
DirList* efsdir;
efsl_fs* efsfs = (efsl_fs*)(file->fs->data);
int result = 0;
/* parameter check */
if ( file == RT_NULL || file->fs == RT_NULL ||
file->fs->data == RT_NULL )
{
dfs_log(DFS_DEBUG_INFO, ("Invalid argument"));
return -DFS_STATUS_EINVAL;
}
/* open directory */
if(file->flags & DFS_O_DIRECTORY)
{
/* write directory is not supported */
if(file->flags & DFS_O_WRONLY || file->flags & DFS_O_RDWR)
{
dfs_log(DFS_DEBUG_INFO, ("write directory isn't supported"));
return -DFS_STATUS_EISDIR;
}
/* create directory */
if(file->flags & DFS_O_CREAT)
{
dfs_log(DFS_DEBUG_INFO, ("create directory"));
result = mk_dir(&efsfs->filesystem, file->path);
if(result < 0)
{
dfs_log(DFS_DEBUG_INFO, ("directory %s has existed", file->path));
return -DFS_STATUS_EEXIST;
}
}
efsdir = (DirList*)rt_malloc(sizeof(DirList));
if(efsdir == RT_NULL)
{
dfs_log(DFS_DEBUG_INFO, ("memory alloc failed"));
return -DFS_STATUS_ENOMEM;
}
result = ls_openDir(efsdir, &efsfs->filesystem, file->path);
if(result < 0)
{
dfs_log(DFS_DEBUG_INFO, ("open directory %s failed", file->path));
rt_free(efsdir);
}
else
{
file->data = efsdir;
}
}
/* open file */
else
{
efsfile = (File *)rt_malloc(sizeof(File));
if (efsfile == RT_NULL)
{
dfs_log(DFS_DEBUG_INFO, ("memory alloc failed"));
return -DFS_STATUS_ENOMEM;
}
result = file_fopen(efsfile, &efsfs->filesystem, file->path, file->flags);
if(result < 0)
{
dfs_log(DFS_DEBUG_INFO, ("open file %s failed", file->path));
rt_free(efsfile);
}
else
{
file->pos = efsfile->FilePtr;
file->size = efsfile->FileSize;
file->data = efsfile;
}
}
return result;
}
/**
* This function will set a hook function, which will be invoked when a memory
* block is allocated from heap memory.
*
* @param hook the hook function
*/
int efs_close(struct dfs_fd* file)
{
int result = 0;
if (!file || !(file->flags & DFS_F_OPEN)) return -DFS_STATUS_EBADF;
if(!(file->flags & DFS_F_DIRECTORY))
result = file_fclose((File *)file->data);
else
{
dfs_log(DFS_DEBUG_INFO, ("close a directory, %s", file->path));
}
dfs_log(DFS_DEBUG_INFO, ("close a file, %s", file->path));
/* free directory or file */
rt_free(file->data);
file->data = RT_NULL;
return result;
}
/**
* This function will set a hook function, which will be invoked when a memory
* block is allocated from heap memory.
*
* @param hook the hook function
*/
int efs_ioctl(struct dfs_fd* file, int cmd, void* args)
{
return 0;
}
/**
* This function will set a hook function, which will be invoked when a memory
* block is allocated from heap memory.
*
* @param hook the hook function
*/
int efs_read(struct dfs_fd* file, void* buf, rt_size_t len)
{
File* efsfile = file->data;
int result = 0;
/* parameter check */
RT_ASSERT(efsfile != RT_NULL);
result = file_read(efsfile, len, buf);
file->pos = efsfile->FilePtr;
dfs_log(DFS_DEBUG_INFO, ("read file %s %d bytes", file->path, result));
return result;
}
/**
* This function will set a hook function, which will be invoked when a memory
* block is allocated from heap memory.
*
* @param hook the hook function
*/
int efs_write(struct dfs_fd* file, const void* buf, rt_size_t len)
{
File* efsfile = file->data;
int result = 0;
/* parameter check */
RT_ASSERT(efsfile != RT_NULL);
result = file_write(efsfile, len, (euint8 *)buf);
file->pos = efsfile->FilePtr;
file->size = efsfile->FileSize;
dfs_log(DFS_DEBUG_INFO, ("write file %s %d bytes", file->path, result));
return result;
}
/**
* This function will set a hook function, which will be invoked when a memory
* block is allocated from heap memory.
*
* @param hook the hook function
*/
int efs_lseek(struct dfs_fd* file, rt_off_t offset)
{
int result = 0;
DirList* efsdir;
efsl_fs* efsfs = (efsl_fs *)file->fs->data;
/* parameter check */
RT_ASSERT(efsfs != RT_NULL);
/* seek directory */
if(file->flags & DFS_O_DIRECTORY)
{
efsdir = (DirList*)file->data;
/* only support offset equels zero */
if(offset == 0)
{
result = ls_openDir(efsdir, &efsfs->filesystem, file->path);
if(result < 0)
{
dfs_log(DFS_DEBUG_INFO, ("open directory %s failed", file->path));
}
}
/* should implement in future version */
else
{
dfs_log(DFS_DEBUG_INFO, ("not implement"));
}
}
/* seek file */
else
{
File* efsfile = file->data;
/* parameter check */
if ( efsfile == RT_NULL) return -DFS_STATUS_EBADF;
result = file_setpos(efsfile, offset);
}
return result;
}
/**
* This function will set a hook function, which will be invoked when a memory
* block is allocated from heap memory.
*
* @param hook the hook function
*/
int efs_getdents(struct dfs_fd* file, struct dfs_dirent* dirp, rt_uint32_t count)
{
DirList* efsdir = (DirList*)file->data;
struct dfs_dirent* d;
int result = 0;
/* fd check */
if ( efsdir == RT_NULL) return -DFS_STATUS_EBADF;
/* flags check */
if(!(file->flags & DFS_F_DIRECTORY)) return -DFS_STATUS_EBADF;
/* make integer count */
count = (count / sizeof(struct dfs_dirent)) * sizeof(struct dfs_dirent);
if ( count == 0 ) return -DFS_STATUS_EINVAL;
while(1)
{
/* it's the end of file */
if(ls_getNext(efsdir) < 0) return 0;
d = dirp + result;
/* copy dirent name */
fat_ShortnameToString(efsdir->currentEntry.FileName, d->d_name);
d->d_reclen = (euint16)sizeof(struct dfs_dirent);
/* set type */
d->d_type = DFS_DT_UNKNOWN;
if (efsdir->currentEntry.Attribute & ATTR_DIRECTORY ) d->d_type &= DFS_DT_DIR;
else d->d_type &= DFS_DT_REG;
result ++;
/* is it enough? */
if ( result * sizeof(struct dfs_dirent) >= count )
break;
}
return result * sizeof(struct dfs_dirent);
}
/**
* This function will set a hook function, which will be invoked when a memory
* block is allocated from heap memory.
*
* @param hook the hook function
*/
int efs_unlink(struct dfs_filesystem* fs, const char* path)
{
efsl_fs* efsfs;
RT_ASSERT(fs != RT_NULL);
efsfs = (efsl_fs *)fs->data;
RT_ASSERT(path != RT_NULL);
RT_ASSERT(efsfs != RT_NULL);
return un_link(&efsfs->filesystem, (euint8 *)path);
}
/**
* This function will set a hook function, which will be invoked when a memory
* block is allocated from heap memory.
*
* @param hook the hook function
*/
int efs_stat(struct dfs_filesystem* fs, const char *path, struct dfs_stat *st)
{
FileRecord entry;
FileLocation loc;
efsl_fs* efsfs = (efsl_fs*)(fs->data);
/* parameter check */
RT_ASSERT(efsfs != RT_NULL);
/* file does not exist */
if(fs_findFile(&efsfs->filesystem, (char *)path, &loc, 0) == 0)
{
dfs_log(DFS_DEBUG_ERROR, ("can't find direntry"));
return -DFS_STATUS_ENOENT;
}
dir_getFileStructure(&efsfs->filesystem, &entry, &loc);
st->st_dev = fs->dev_id;
st->st_mode = DFS_S_IFREG | DFS_S_IRUSR | DFS_S_IRGRP | DFS_S_IROTH |
DFS_S_IWUSR | DFS_S_IWGRP | DFS_S_IWOTH;
if ( entry.Attribute & ATTR_DIRECTORY )
{
st->st_mode &= ~DFS_S_IFREG;
st->st_mode |= DFS_S_IFDIR | DFS_S_IXUSR | DFS_S_IXGRP | DFS_S_IXOTH;
}
if ( entry.Attribute & ATTR_READ_ONLY )
st->st_mode &= ~(DFS_S_IWUSR | DFS_S_IWGRP | DFS_S_IWOTH);
st->st_size = entry.FileSize;
st->st_mtime = entry.WriteTime;
return 0;
}
/**
* This function will set a hook function, which will be invoked when a memory
* block is allocated from heap memory.
*
* @param hook the hook function
*/
int efs_rename(struct dfs_filesystem* fs, const char* oldpath, const char* newpath)
{
FileRecord old_entry, new_entry;
FileLocation old_loc, new_loc;
efsl_fs* efsfs;
eint8 fatfilename[11];
efsfs = (efsl_fs*) fs->data ;
RT_ASSERT(efsfs != RT_NULL);
dir_getFatFileName((eint8 *)newpath, &fatfilename[0]);
/* parameters check */
if (strlen(oldpath) > DFS_PATH_MAX ||
strlen(newpath) > DFS_PATH_MAX ||
/* old path is a directory that contains newpath */
strncmp(oldpath, newpath, strlen(newpath)) == 0)
{
dfs_log(DFS_DEBUG_ERROR, ("old path is a directory that contains newpath"));
return -DFS_STATUS_EINVAL;
}
/* if can't find old direntry */
if(fs_findFile(&efsfs->filesystem, (eint8 *)oldpath, &old_loc, 0) == 0)
{
dfs_log(DFS_DEBUG_ERROR, ("can't find old direntry"));
return -DFS_STATUS_ENOENT;
}
dir_getFileStructure(&efsfs->filesystem, &old_entry, &old_loc);
/* if the new direntry exist */
if(fs_findFile(&efsfs->filesystem, (eint8 *)newpath, &new_loc, 0) > 0)
{
dfs_log(DFS_DEBUG_ERROR, ("new direntry existed"));
return -DFS_STATUS_ENOENT;
}
if(fs_findFreeFile(&efsfs->filesystem, (eint8 *)newpath, &new_loc, 0))
{
memCpy(&old_entry, &new_entry, sizeof(FileRecord));
memCpy(fatfilename, new_entry.FileName, 11);
dir_createDirectoryEntry(&efsfs->filesystem, &new_entry, &new_loc);
}
/* delete the old direntry */
old_entry.FileName[0] = 0xe5;
dir_updateDirectoryEntry(&efsfs->filesystem, &old_entry, &old_loc);
return 0;
}

57
filesystem/dfs/filesystems/efsl/src/base/extract.c Normal file
View File

@ -0,0 +1,57 @@
/*****************************************************************************\
* EFSL - Embedded Filesystems Library *
* ----------------------------------- *
* *
* Filename : extract.c *
* Release : 0.3 - devel *
* Description : This file contains functions to copy structures that get *
* corrupted when using direct memory copy *
* *
* This program is free software; you can redistribute it and/or *
* modify it under the terms of the GNU General Public License *
* as published by the Free Software Foundation; version 2 *
* of the License. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* As a special exception, if other files instantiate templates or *
* use macros or inline functions from this file, or you compile this *
* file and link it with other works to produce a work based on this file, *
* this file does not by itself cause the resulting work to be covered *
* by the GNU General Public License. However the source code for this *
* file must still be made available in accordance with section (3) of *
* the GNU General Public License. *
* *
* This exception does not invalidate any other reasons why a work based *
* on this file might be covered by the GNU General Public License. *
* *
* (c)2006 Lennart Yseboodt *
* (c)2006 Michael De Nil *
\*****************************************************************************/
/*****************************************************************************/
#include "extract.h"
/*****************************************************************************/
#if !(defined(BYTE_ALIGNMENT))
#warning "Compiling f_setbxx"
void ex_setb16(euint8* buf,euint16 data)
{
buf[1] = data>>8;
buf[0] = data>>0;
}
void ex_setb32(euint8* buf,euint32 data)
{
buf[3] = data>>24;
buf[2] = data>>16;
buf[1] = data>>8;
buf[0] = data>>0;
}
#endif

68
filesystem/dfs/filesystems/efsl/src/base/include/debug.h Normal file
View File

@ -0,0 +1,68 @@
/*****************************************************************************\
* EFSL - Embedded Filesystems Library *
* ----------------------------------- *
* *
* Filename : debug.h *
* Release : 0.3 - devel *
* Description : These functions are used for debugging output on different *
* environments *
* *
* This program is free software; you can redistribute it and/or *
* modify it under the terms of the GNU General Public License *
* as published by the Free Software Foundation; version 2 *
* of the License. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* As a special exception, if other files instantiate templates or *
* use macros or inline functions from this file, or you compile this *
* file and link it with other works to produce a work based on this file, *
* this file does not by itself cause the resulting work to be covered *
* by the GNU General Public License. However the source code for this *
* file must still be made available in accordance with section (3) of *
* the GNU General Public License. *
* *
* This exception does not invalidate any other reasons why a work based *
* on this file might be covered by the GNU General Public License. *
* *
* (c)2006 Lennart Yseboodt *
* (c)2006 Michael De Nil *
\*****************************************************************************/
#ifndef __DEBUG_H__
#define __DEBUG_H__
/*****************************************************************************/
#include "types.h"
#include "config.h"
/*****************************************************************************/
#ifndef DEBUG
#define TXT(x) ;
#define DBG(x) ;
#define FUNC_IN(x) ;
#define FUNC_OUT(x) ;
#endif
#ifdef DEBUG
#ifdef HW_ENDPOINT_LINUX
#include <stdio.h>
#include <stdarg.h>
#define TXT(x) x
#define DBG(x) debug x
#define FUNC_IN(x) debug_funcin(x)
#define FUNC_OUT(x) debug_funcout(x)
#endif
void debug(const eint8 *format, ...);
void debug_init();
void debug_end();
#endif
#endif

89
filesystem/dfs/filesystems/efsl/src/base/include/efs.h Normal file
View File

@ -0,0 +1,89 @@
/*****************************************************************************\
* EFSL - Embedded Filesystems Library *
* ----------------------------------- *
* *
* Filename : efs.c *
* Release : 0.3 - devel *
* Description : This should become the wrapper around efs. It will contain *
* functions like efs_init etc. *
* *
* This program is free software; you can redistribute it and/or *
* modify it under the terms of the GNU General Public License *
* as published by the Free Software Foundation; version 2 *
* of the License. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* As a special exception, if other files instantiate templates or *
* use macros or inline functions from this file, or you compile this *
* file and link it with other works to produce a work based on this file, *
* this file does not by itself cause the resulting work to be covered *
* by the GNU General Public License. However the source code for this *
* file must still be made available in accordance with section (3) of *
* the GNU General Public License. *
* *
* This exception does not invalidate any other reasons why a work based *
* on this file might be covered by the GNU General Public License. *
* *
* (c)2006 Lennart Yseboodt *
* (c)2006 Michael De Nil *
\*****************************************************************************/
#ifndef __EFS_H__
#define __EFS_H__
/*****************************************************************************/
#include <dfs_fs.h>
#include "types.h"
#include "config.h"
#include "extract.h"
#include "partition.h"
/* WARNING !!!!
* These includes DO NOT BELONG HERE,
* remove them when the VFS layer is implemented !!!!
*/
#include "fs.h"
#include "file.h"
#include "tm.h"
#include "ui.h"
/*****************************************************************************/
#define LINUX_FILE_CONFIG 0x00
#define AVR_SD_CONFIG 0x01
/*****************************************************************************/
#define efs_read_sectors(device, start, count, buf) rt_device_read(device, \
(start) * SECTOR_SIZE, (buf), (count) * SECTOR_SIZE) / SECTOR_SIZE
#define efs_write_sectors(device, start, count, buf) rt_device_write(device, \
(start) * SECTOR_SIZE, (buf), (count) * SECTOR_SIZE) / SECTOR_SIZE
struct _efsl_fs {
Partition partition;
FileSystem filesystem;
};
typedef struct _efsl_fs efsl_fs;
/* EFS filesystem file operations */
int efs_mount(struct dfs_filesystem* fs);
int efs_unmount(struct dfs_filesystem* fs);
int efs_open(struct dfs_fd* file);
int efs_close(struct dfs_fd* file);
int efs_ioctl(struct dfs_fd* file, int cmd, void* args);
int efs_read(struct dfs_fd* file, void* buf, rt_size_t len);
int efs_write(struct dfs_fd* file, const void* buf, rt_size_t len);
int efs_lseek(struct dfs_fd* file, rt_off_t offset);
int efs_getdents(struct dfs_fd* file, struct dfs_dirent* dirp, rt_uint32_t count);
int efs_unlink(struct dfs_filesystem* fs, const char* path);
int efs_stat(struct dfs_filesystem* fs, const char *path, struct dfs_stat *st);
int efs_rename(struct dfs_filesystem* fs, const char* oldpath, const char* newpath);
/*****************************************************************************/
int efsl_init(void);
#endif

101
filesystem/dfs/filesystems/efsl/src/base/include/extract.h Normal file
View File

@ -0,0 +1,101 @@
/*****************************************************************************\
* EFSL - Embedded Filesystems Library *
* ----------------------------------- *
* *
* Filename : extract.h *
* Release : 0.3 - devel *
* Description : This file contains functions to copy structures that get *
* corrupted when using direct memory copy *
* *
* This program is free software; you can redistribute it and/or *
* modify it under the terms of the GNU General Public License *
* as published by the Free Software Foundation; version 2 *
* of the License. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* As a special exception, if other files instantiate templates or *
* use macros or inline functions from this file, or you compile this *
* file and link it with other works to produce a work based on this file, *
* this file does not by itself cause the resulting work to be covered *
* by the GNU General Public License. However the source code for this *
* file must still be made available in accordance with section (3) of *
* the GNU General Public License. *
* *
* This exception does not invalidate any other reasons why a work based *
* on this file might be covered by the GNU General Public License. *
* *
* (c)2006 Lennart Yseboodt *
* (c)2006 Michael De Nil *
\*****************************************************************************/
#ifndef __EXTRACT_H_
#define __EXTRACT_H_
/*****************************************************************************/
#include "config.h"
#include "types.h"
/*****************************************************************************/
#if !(defined(HOST_LITTLE_ENDIAN)) && !(defined(HOST_BIG_ENDIAN))
#error Endianess undefined, see config.h
#elif defined(HOST_LITTLE_ENDIAN) && (defined(HOST_BIG_ENDIAN))
#error Endianess defined as little and big, see config.h
#endif
/*****************************************************************************/
#define end_conv16(x) ((((euint16)(x) & 0xff00) >> 8) | \
(((euint16)(x) & 0x00ff) << 8))
#define end_conv32(x) ((((euint32)(x) & 0xff000000) >> 24) | \
(((euint32)(x) & 0x00ff0000) >> 8) | \
(((euint32)(x) & 0x0000ff00) << 8) | \
(((euint32)(x) & 0x000000ff) << 24))
/*****************************************************************************/
#if defined(BYTE_ALIGNMENT)
#define ex_getb16(buf) (*((euint16*)(buf)))
#define ex_setb16(buf,data) *((euint16*)(buf))=(data)
#define ex_getb32(buf) (*((euint32*)(buf)))
#define ex_setb32(buf,data) *((euint32*)(buf))=(data)
#else
#define ex_getb16(buf) \
((euint16)(*((euint8*)(buf)+1)<<8) + \
(euint16)(*((euint8*)(buf)+0)<<0))
void ex_setb16(euint8* buf,euint16 data);
#define ex_getb32(buf) \
((euint32)(*((euint8*)(buf)+3)<<24) + \
(euint32)(*((euint8*)(buf)+2)<<16) + \
(euint32)(*((euint8*)(buf)+1)<<8) + \
(euint32)(*((euint8*)(buf)+0)<<0))
void ex_setb32(euint8* buf,euint32 data);
#endif
#if defined(HOST_LITTLE_ENDIAN)
#define ex_lth16(buf) ex_getb16(buf)
#define ex_lth32(buf) ex_getb32(buf)
#define ex_bth16(buf) end_conv16(ex_getb16(buf))
#define ex_bth32(buf) end_conv32(ex_getb32(buf))
#define ex_htl16(buf) ex_setb16(buf)
#define ex_htl32(buf) ex_setb32(buf)
#define ex_htb16(buf) ex_setb16(end_conv16(buf))
#define ex_htb32(buf) ex_setb32(end_conv32(buf))
#elif defined(HOST_BIG_ENDIAN)
#define ex_lth16(buf) end_conv16(ex_getb16(buf))
#define ex_lth32(buf) end_conv32(ex_getb32(buf))
#define ex_bth16(buf) ex_getb16(buf)
#define ex_bth32(buf) ex_getb32(buf)
#define ex_htl16(buf) ex_setb16(end_conv16(buf))
#define ex_htl32(buf) ex_setb32(end_conv32(buf))
#define ex_htb16(buf) ex_setb16(buf)
#define ex_htb32(buf) ex_setb32(buf)
#endif
#endif

140
filesystem/dfs/filesystems/efsl/src/base/include/ioman.h Normal file
View File

@ -0,0 +1,140 @@
/*****************************************************************************\
* EFSL - Embedded Filesystems Library *
* ----------------------------------- *
* *
* Filename : ioman.c *
* Release : 0.3 - devel *
* Description : The IO Manager receives all requests for sectors in a central *
* allowing it to make smart decision regarding caching. *
* The IOMAN_NUMBUFFER parameter determines how many sectors *
* ioman can cache. ioman also supports overallocating and *
* backtracking sectors. *
* *
* This program is free software; you can redistribute it and/or *
* modify it under the terms of the GNU General Public License *
* as published by the Free Software Foundation; version 2 *
* of the License. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* As a special exception, if other files instantiate templates or *
* use macros or inline functions from this file, or you compile this *
* file and link it with other works to produce a work based on this file, *
* this file does not by itself cause the resulting work to be covered *
* by the GNU General Public License. However the source code for this *
* file must still be made available in accordance with section (3) of *
* the GNU General Public License. *
* *
* This exception does not invalidate any other reasons why a work based *
* on this file might be covered by the GNU General Public License. *
* *
* (c)2006 Lennart Yseboodt *
* (c)2006 Michael De Nil *
\*****************************************************************************/
#ifndef __IOMAN_H__
#define __IOMAN_H__
/*****************************************************************************/
#include <rtthread.h>
#include "error.h"
#include "plibc.h"
#include "debug.h"
#include "types.h"
#include "config.h"
/*****************************************************************************/
#define IOMAN_STATUS_ATTR_VALIDDATA 0
#define IOMAN_STATUS_ATTR_USERBUFFER 1
#define IOMAN_STATUS_ATTR_WRITE 2
#define IOM_MODE_READONLY 1
#define IOM_MODE_READWRITE 2
#define IOM_MODE_EXP_REQ 4
struct _IOManStack{
euint32 sector;
euint8 status;
euint8 usage;
};
typedef struct _IOManStack IOManStack;
struct _IOManager{
rt_device_t device;
euint8 *bufptr;
euint16 numbuf;
euint16 numit;
IOMAN_ERR_EUINT8
IOManStack stack[IOMAN_NUMBUFFER][IOMAN_NUMITERATIONS];
euint32 sector[IOMAN_NUMBUFFER];
euint8 status[IOMAN_NUMBUFFER];
euint8 usage[IOMAN_NUMBUFFER];
euint8 reference[IOMAN_NUMBUFFER];
euint8 itptr[IOMAN_NUMBUFFER];
#ifdef IOMAN_DO_MEMALLOC
euint8 cache_mem[IOMAN_NUMBUFFER * 512];
#endif
};
typedef struct _IOManager IOManager;
#define IOBJ ioman
#define ioman_isValid(bp) ioman_getAttr(IOBJ,bp,IOMAN_STATUS_ATTR_VALIDDATA)
#define ioman_isUserBuf(bp) ioman_getAttr(IOBJ,bp,IOMAN_STATUS_ATTR_USERBUFFER)
#define ioman_isWritable(bp) ioman_getAttr(IOBJ,bp,IOMAN_STATUS_ATTR_WRITE)
#define ioman_setValid(bp) ioman_setAttr(IOBJ,bp,IOMAN_STATUS_ATTR_VALIDDATA,1)
#define ioman_setUserBuf(bp) ioman_setAttr(IOBJ,bp,IOMAN_STATUS_ATTR_USERBUFFER,1)
#define ioman_setWritable(bp) ioman_setAttr(IOBJ,bp,IOMAN_STATUS_ATTR_WRITE,1)
#define ioman_setNotValid(bp) ioman_setAttr(IOBJ,bp,IOMAN_STATUS_ATTR_VALIDDATA,0)
#define ioman_setNotUserBuf(bp) ioman_setAttr(IOBJ,bp,IOMAN_STATUS_ATTR_USERBUFFER,0)
#define ioman_setNotWritable(bp) ioman_setAttr(IOBJ,bp,IOMAN_STATUS_ATTR_WRITE,0)
#define ioman_isReqRo(mode) ((mode)&(IOM_MODE_READONLY))
#define ioman_isReqRw(mode) ((mode)&(IOM_MODE_READWRITE))
#define ioman_isReqExp(mode) ((mode)&(IOM_MODE_EXP_REQ))
esint8 ioman_init(IOManager *ioman, euint8* bufferarea);
void ioman_reset(IOManager *ioman);
euint8* ioman_getBuffer(IOManager *ioman,euint8* bufferarea);
void ioman_setAttr(IOManager *ioman,euint16 bufplace,euint8 attribute,euint8 val);
euint8 ioman_getAttr(IOManager *ioman,euint16 bufplace,euint8 attribute);
euint8 ioman_getUseCnt(IOManager *ioman,euint16 bufplace);
void ioman_incUseCnt(IOManager *ioman,euint16 bufplace);
void ioman_decUseCnt(IOManager *ioman,euint16 bufplace);
void ioman_resetUseCnt(IOManager *ioman,euint16 bufplace);
euint8 ioman_getRefCnt(IOManager *ioman,euint16 bufplace);
void ioman_incRefCnt(IOManager *ioman,euint16 bufplace);
void ioman_decRefCnt(IOManager *ioman,euint16 bufplace);
void ioman_resetRefCnt(IOManager *ioman,euint16 bufplace);
esint8 ioman_pop(IOManager *ioman,euint16 bufplace);
esint8 ioman_push(IOManager *ioman,euint16 bufplace);
euint8* ioman_getPtr(IOManager *ioman,euint16 bufplace);
esint16 ioman_getBp(IOManager *ioman,euint8* buf);
esint8 ioman_readSector(IOManager *ioman,euint32 address,euint8* buf);
esint8 ioman_writeSector(IOManager *ioman, euint32 address, euint8* buf);
void ioman_resetCacheItem(IOManager *ioman,euint16 bufplace);
esint32 ioman_findSectorInCache(IOManager *ioman, euint32 address);
esint32 ioman_findFreeSpot(IOManager *ioman);
esint32 ioman_findUnusedSpot(IOManager *ioman);
esint32 ioman_findOverallocableSpot(IOManager *ioman);
esint8 ioman_putSectorInCache(IOManager *ioman,euint32 address, euint16 bufplace);
esint8 ioman_flushSector(IOManager *ioman, euint16 bufplace);
euint8* ioman_getSector(IOManager *ioman,euint32 address, euint8 mode);
esint8 ioman_releaseSector(IOManager *ioman,euint8* buf);
esint8 ioman_directSectorRead(IOManager *ioman,euint32 address, euint8* buf);
esint8 ioman_directSectorWrite(IOManager *ioman,euint32 address, euint8* buf);
esint8 ioman_flushRange(IOManager *ioman,euint32 address_low, euint32 address_high);
esint8 ioman_flushAll(IOManager *ioman);
void ioman_printStatus(IOManager *ioman);
#endif

93
filesystem/dfs/filesystems/efsl/src/base/include/ioman_small.h Normal file
View File

@ -0,0 +1,93 @@
/*****************************************************************************\
* EFSL - Embedded Filesystems Library *
* ----------------------------------- *
* *
* Filename : ioman_small.c *
* Release : 0.3 - devel *
* Description : The IO Manager receives all requests for sectors in a central *
* allowing it to make smart decision regarding caching. *
* The IOMAN_NUMBUFFER parameter determines how many sectors *
* ioman can cache. ioman also supports overallocating and *
* backtracking sectors. *
* This is the small version of IOMan, for systems with limited *
* resources. It features only one fixed buffer, and has *
* simplified operation *
* *
* This program is free software; you can redistribute it and/or *
* modify it under the terms of the GNU General Public License *
* as published by the Free Software Foundation; version 2 *
* of the License. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* As a special exception, if other files instantiate templates or *
* use macros or inline functions from this file, or you compile this *
* file and link it with other works to produce a work based on this file, *
* this file does not by itself cause the resulting work to be covered *
* by the GNU General Public License. However the source code for this *
* file must still be made available in accordance with section (3) of *
* the GNU General Public License. *
* *
* This exception does not invalidate any other reasons why a work based *
* on this file might be covered by the GNU General Public License. *
* *
* (c)2006 Lennart Yseboodt *
* (c)2006 Michael De Nil *
\*****************************************************************************/
#include "error.h"
#include "plibc.h"
#include "debug.h"
#include "types.h"
#include "config.h"
#define IOMAN_STATUS_ATTR_VALIDDATA 0
#define IOMAN_STATUS_ATTR_USERBUFFER 1
#define IOMAN_STATUS_ATTR_WRITE 2
#define IOM_MODE_READONLY 1
#define IOM_MODE_READWRITE 2
#define IOM_MODE_EXP_REQ 4
struct _IOManStack{
euint32 sector;
euint8 status;
};
typedef struct _IOManStack IOManStack;
struct _IOManager{
rt_device_t device; /* device handler */
euint8 bufptr[512];
IOMAN_ERR_EUINT8
euint32 sector;
euint8 status;
euint8 itptr;
IOManStack stack;
};
typedef struct _IOManager IOManager;
#define IOBJ ioman
#define ioman_isValid() ioman_getAttr(IOBJ,IOMAN_STATUS_ATTR_VALIDDATA)
#define ioman_isUserBuf() ioman_getAttr(IOBJ,IOMAN_STATUS_ATTR_USERBUFFER)
#define ioman_isWritable() ioman_getAttr(IOBJ,IOMAN_STATUS_ATTR_WRITE)
#define ioman_setValid() ioman_setAttr(IOBJ,IOMAN_STATUS_ATTR_VALIDDATA,1)
#define ioman_setUserBuf() ioman_setAttr(IOBJ,IOMAN_STATUS_ATTR_USERBUFFER,1)
#define ioman_setWritable() ioman_setAttr(IOBJ,IOMAN_STATUS_ATTR_WRITE,1)
#define ioman_setNotValid() ioman_setAttr(IOBJ,IOMAN_STATUS_ATTR_VALIDDATA,0)
#define ioman_setNotUserBuf() ioman_setAttr(IOBJ,IOMAN_STATUS_ATTR_USERBUFFER,0)
#define ioman_setNotWritable() ioman_setAttr(IOBJ,IOMAN_STATUS_ATTR_WRITE,0)
#define ioman_isReqRo(mode) ((mode)&(IOM_MODE_READONLY))
#define ioman_isReqRw(mode) ((mode)&(IOM_MODE_READWRITE))
#define ioman_isReqExp(mode) ((mode)&(IOM_MODE_EXP_REQ))
esint8 ioman_init(IOManager *ioman, euint8* bufferarea);
void ioman_reset(IOManager *ioman);
void ioman_setAttr(IOManager *ioman,euint8 attribute,euint8 val);
euint8 ioman_getAttr(IOManager *ioman,euint8 attribute);

73
filesystem/dfs/filesystems/efsl/src/base/include/partition.h Normal file
View File

@ -0,0 +1,73 @@
/*****************************************************************************\
* EFSL - Embedded Filesystems Library *
* ----------------------------------- *
* *
* Filename : partition.c *
* Release : 0.3 - devel *
* Description : These functions are partition specific. Searching FAT type *
* partitions and read/write functions to partitions. *
* *
* This program is free software; you can redistribute it and/or *
* modify it under the terms of the GNU General Public License *
* as published by the Free Software Foundation; version 2 *
* of the License. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* As a special exception, if other files instantiate templates or *
* use macros or inline functions from this file, or you compile this *
* file and link it with other works to produce a work based on this file, *
* this file does not by itself cause the resulting work to be covered *
* by the GNU General Public License. However the source code for this *
* file must still be made available in accordance with section (3) of *
* the GNU General Public License. *
* *
* This exception does not invalidate any other reasons why a work based *
* on this file might be covered by the GNU General Public License. *
* *
* (c)2006 Lennart Yseboodt *
* (c)2006 Michael De Nil *
\*****************************************************************************/
#ifndef __PARTITION_H__
#define __PARTITION_H__
/*****************************************************************************/
#include "config.h"
#include "error.h"
#include "types.h"
// #include "ioman.h"
#include <dfs_cache.h>
/*****************************************************************************/
#define PT_FAT12 0x01
#define PT_FAT16A 0x04
#define PT_FAT16 0x06
#define PT_FAT32 0x0B
#define PT_FAT32A 0x5C
#define PT_FAT16B 0x5E
struct _Partition{
IOManager *ioman;
};
typedef struct _Partition Partition;
void part_initPartition(Partition *part);
eint16 part_isFatPart(euint8 type);
esint8 part_readBuf(Partition *part, euint32 address, euint8* buf);
esint8 part_readPartBuf(Partition *part, euint32 address, euint8* buf, euint32 offset, euint16 len);
eint16 part_writeBuf(Partition *part,euint32 address,euint8* buf);
euint8* part_getSect(Partition *part, euint32 address,euint8 mode);
esint8 part_relSect(Partition *part, euint8* buf);
esint8 part_flushPart(Partition *part,euint32 addr_l, euint32 addr_h);
esint8 part_directSectorRead(Partition *part, euint32 address, euint8* buf, euint32 numsector);
esint8 part_directSectorWrite(Partition *part, euint32 address, euint8* buf, euint32 numsector);
#include "extract.h"
#endif

49
filesystem/dfs/filesystems/efsl/src/base/include/plibc.h Normal file
View File

@ -0,0 +1,49 @@
/*****************************************************************************\
* EFSL - Embedded Filesystems Library *
* ----------------------------------- *
* *
* Filename : plibc.c *
* Release : 0.3 - devel *
* Description : This file contains replacements of common c library functions *
* *
* This program is free software; you can redistribute it and/or *
* modify it under the terms of the GNU General Public License *
* as published by the Free Software Foundation; version 2 *
* of the License. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* As a special exception, if other files instantiate templates or *
* use macros or inline functions from this file, or you compile this *
* file and link it with other works to produce a work based on this file, *
* this file does not by itself cause the resulting work to be covered *
* by the GNU General Public License. However the source code for this *
* file must still be made available in accordance with section (3) of *
* the GNU General Public License. *
* *
* This exception does not invalidate any other reasons why a work based *
* on this file might be covered by the GNU General Public License. *
* *
* (c)2006 Lennart Yseboodt *
* (c)2006 Michael De Nil *
\*****************************************************************************/
#ifndef __PLIBC_H__
#define __PLIBC_H__
/*****************************************************************************/
#include "debug.h"
#include "types.h"
#include "config.h"
/*****************************************************************************/
euint16 strMatch(eint8* bufa, eint8*bufb,euint32 n);
void memCpy(void* psrc, void* pdest, euint32 size);
void memClr(void *pdest,euint32 size);
void memSet(void *pdest,euint32 size,euint8 data);
#endif

600
filesystem/dfs/filesystems/efsl/src/base/ioman.c Normal file
View File

@ -0,0 +1,600 @@
/*****************************************************************************\
* EFSL - Embedded Filesystems Library *
* ----------------------------------- *
* *
* Filename : ioman.c *
* Release : 0.3 - devel *
* Description : The IO Manager receives all requests for sectors in a central *
* allowing it to make smart decision regarding caching. *
* The IOMAN_NUMBUFFER parameter determines how many sectors *
* ioman can cache. ioman also supports overallocating and *
* backtracking sectors. *
* *
* This program is free software; you can redistribute it and/or *
* modify it under the terms of the GNU General Public License *
* as published by the Free Software Foundation; version 2 *
* of the License. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* As a special exception, if other files instantiate templates or *
* use macros or inline functions from this file, or you compile this *
* file and link it with other works to produce a work based on this file, *
* this file does not by itself cause the resulting work to be covered *
* by the GNU General Public License. However the source code for this *
* file must still be made available in accordance with section (3) of *
* the GNU General Public License. *
* *
* This exception does not invalidate any other reasons why a work based *
* on this file might be covered by the GNU General Public License. *
* *
* (c)2006 Lennart Yseboodt *
* (c)2006 Michael De Nil *
\*****************************************************************************/
/*****************************************************************************/
#include "ioman.h"
#include "efs.h"
/*****************************************************************************/
esint8 ioman_init(IOManager *ioman, euint8* bufferarea)
{
ioman->bufptr = ioman_getBuffer(ioman,bufferarea);
ioman->numbuf = IOMAN_NUMBUFFER;
ioman->numit = IOMAN_NUMITERATIONS;
ioman_reset(ioman);
return(0);
}
/*****************************************************************************/
void ioman_reset(IOManager *ioman)
{
euint16 nb,ni;
memClr(ioman->sector,sizeof(euint32)*ioman->numbuf);
memClr(ioman->status,sizeof(euint8) *ioman->numbuf);
memClr(ioman->usage ,sizeof(euint8) *ioman->numbuf);
memClr(ioman->itptr ,sizeof(euint8) *ioman->numbuf);
ioman_setError(ioman,IOMAN_NOERROR);
for(nb=0;nb<ioman->numbuf;nb++){
for(ni=0;ni<ioman->numit;ni++){
ioman->stack[nb][ni].sector=0;
ioman->stack[nb][ni].status=0;
ioman->stack[nb][ni].usage =0;
}
}
}
/*****************************************************************************/
euint8* ioman_getBuffer(IOManager *ioman,euint8* bufferarea)
{
#ifdef IOMAN_DO_MEMALLOC
return(ioman->cache_mem);
#else
return(bufferarea);
#endif
}
/*****************************************************************************/
void ioman_setAttr(IOManager *ioman,euint16 bufplace,euint8 attribute,euint8 val)
{
if(bufplace>=ioman->numbuf){
ioman_setError(ioman,IOMAN_ERR_SETATTROUTOFBOUNDS);
return; /* Out of bounds */
}
if(val){
ioman->status[bufplace]|=1<<attribute;
}else{
ioman->status[bufplace]&=~(1<<attribute);
}
}
/*****************************************************************************/
euint8 ioman_getAttr(IOManager *ioman,euint16 bufplace,euint8 attribute)
{
if(bufplace>=ioman->numbuf){
ioman_setError(ioman,IOMAN_ERR_GETATTROUTOFBOUNDS);
return(0xFF); /* Out of bounds */
}
return(ioman->status[bufplace]&(1<<attribute));
}
/*****************************************************************************/
euint8 ioman_getUseCnt(IOManager *ioman,euint16 bufplace)
{
if(bufplace>=ioman->numbuf){
ioman_setError(ioman,IOMAN_ERR_OPOUTOFBOUNDS);
return(0x00);
}
return(ioman->usage[bufplace]);
}
/*****************************************************************************/
void ioman_incUseCnt(IOManager *ioman,euint16 bufplace)
{
if(bufplace>=ioman->numbuf){
ioman_setError(ioman,IOMAN_ERR_OPOUTOFBOUNDS);
return;
}
if(ioman->usage[bufplace]==0xFF)return;
else ioman->usage[bufplace]++;
}
/*****************************************************************************/
void ioman_decUseCnt(IOManager *ioman,euint16 bufplace)
{
if(bufplace>=ioman->numbuf){
ioman_setError(ioman,IOMAN_ERR_OPOUTOFBOUNDS);
return;
}
if(ioman->usage[bufplace]==0x0)return;
else ioman->usage[bufplace]--;
}
/*****************************************************************************/
void ioman_resetUseCnt(IOManager *ioman,euint16 bufplace)
{
if(bufplace>=ioman->numbuf){
ioman_setError(ioman,IOMAN_ERR_OPOUTOFBOUNDS);
return;
}
ioman->usage[bufplace]=0x00;
}
/*****************************************************************************/
euint8 ioman_getRefCnt(IOManager *ioman,euint16 bufplace)
{
if(bufplace>=ioman->numbuf){
ioman_setError(ioman,IOMAN_ERR_OPOUTOFBOUNDS);
return(0x00);
}
return(ioman->reference[bufplace]);
}
/*****************************************************************************/
void ioman_incRefCnt(IOManager *ioman,euint16 bufplace)
{
if(bufplace>=ioman->numbuf){
ioman_setError(ioman,IOMAN_ERR_OPOUTOFBOUNDS);
return;
}
if(ioman->reference[bufplace]==0xFF)return;
else ioman->reference[bufplace]++;
}
/*****************************************************************************/
void ioman_decRefCnt(IOManager *ioman,euint16 bufplace)
{
if(bufplace>=ioman->numbuf){
ioman_setError(ioman,IOMAN_ERR_OPOUTOFBOUNDS);
return;
}
if(ioman->reference[bufplace]==0x00)return;
else ioman->reference[bufplace]--;
}
/*****************************************************************************/
void ioman_resetRefCnt(IOManager *ioman,euint16 bufplace)
{
if(bufplace>=ioman->numbuf){
ioman_setError(ioman,IOMAN_ERR_OPOUTOFBOUNDS);
return;
}
ioman->reference[bufplace]=0x00;
}
/*****************************************************************************/
esint8 ioman_pop(IOManager *ioman,euint16 bufplace)
{
if(bufplace>=ioman->numbuf){
ioman_setError(ioman,IOMAN_ERR_POPEMPTYSTACK);
return(-1);
}
if(ioman->itptr[bufplace]==0 || ioman->itptr[bufplace]>IOMAN_NUMITERATIONS)return(-1);
ioman->itptr[bufplace]--;
ioman->sector[bufplace] = ioman->stack[bufplace][ioman->itptr[bufplace]].sector;
ioman->status[bufplace] = ioman->stack[bufplace][ioman->itptr[bufplace]].status;
ioman->usage[bufplace] = ioman->stack[bufplace][ioman->itptr[bufplace]].usage;
return(0);
}
/*****************************************************************************/
esint8 ioman_push(IOManager *ioman,euint16 bufplace)
{
if(bufplace>=ioman->numbuf){
ioman_setError(ioman,IOMAN_ERR_OPOUTOFBOUNDS);
return(-1);
}
if(ioman->itptr[bufplace]>=IOMAN_NUMITERATIONS){
ioman_setError(ioman,IOMAN_ERR_PUSHBEYONDSTACK);
return(-1);
}
ioman->stack[bufplace][ioman->itptr[bufplace]].sector = ioman->sector[bufplace];
ioman->stack[bufplace][ioman->itptr[bufplace]].status = ioman->status[bufplace];
ioman->stack[bufplace][ioman->itptr[bufplace]].usage = ioman->usage[bufplace];
ioman->itptr[bufplace]++;
return(0);
}
/*****************************************************************************/
euint8* ioman_getPtr(IOManager *ioman,euint16 bufplace)
{
if(bufplace>=ioman->numbuf){
ioman_setError(ioman,IOMAN_ERR_OPOUTOFBOUNDS);
return(0);
}
return(ioman->bufptr+bufplace*512);
}
/*****************************************************************************/
esint16 ioman_getBp(IOManager *ioman,euint8* buf)
{
if(buf<(ioman->bufptr) || buf>=( ioman->bufptr+(ioman->numbuf*512) )){
ioman_setError(ioman,IOMAN_ERR_CACHEPTROUTOFRANGE);
return(-1);
}
return((buf-(ioman->bufptr))/512);
}
/*****************************************************************************/
esint8 ioman_readSector(IOManager *ioman,euint32 address,euint8* buf)
{
esint8 r;
if(buf==0){
return(-1);
}
r = efs_read_sectors(ioman->device, address, 1, buf);
if(r!=1){
ioman_setError(ioman,IOMAN_ERR_READFAIL);
return(-1);
}
return(0);
}
/*****************************************************************************/
esint8 ioman_writeSector(IOManager *ioman, euint32 address, euint8* buf)
{
esint8 r;
if(buf==0)return(-1);
r = efs_write_sectors(ioman->device, address, 1, buf);
if(r!=1){
ioman_setError(ioman,IOMAN_ERR_WRITEFAIL);
return(-1);
}
return(0);
}
/*****************************************************************************/
void ioman_resetCacheItem(IOManager *ioman,euint16 bufplace)
{
if(bufplace>=ioman->numbuf){
ioman_setError(ioman,IOMAN_ERR_OPOUTOFBOUNDS);
return;
}
ioman->sector[bufplace] = 0;
ioman->status[bufplace] = 0;
ioman->usage[bufplace] = 0;
ioman->reference[bufplace] = 0;
}
/*****************************************************************************/
esint32 ioman_findSectorInCache(IOManager *ioman, euint32 address)
{
euint16 c;
for(c=0;c<ioman->numbuf;c++){
if(ioman_isValid(c) && ioman->sector[c] == address)return(c);
}
return(-1);
}
/*****************************************************************************/
esint32 ioman_findFreeSpot(IOManager *ioman)
{
euint16 c;
for(c=0;c<ioman->numbuf;c++){
if(!ioman_isValid(c))return(c);
}
return(-1);
}
/*****************************************************************************/
esint32 ioman_findUnusedSpot(IOManager *ioman)
{
esint32 r=-1;
euint16 c;
euint8 fr=0,lr=0xFF;
for(c=0;c<ioman->numbuf;c++){
if(ioman_getUseCnt(ioman,c)==0){
if(!ioman_isWritable(c) && !fr){
fr=1;
lr=0xFF;
r=-1;
}
if(ioman_isWritable(c) && !fr){
if(ioman_getRefCnt(ioman,c)<=lr){
r=c;
lr=ioman_getRefCnt(ioman,c);
}
}
if(fr && !ioman_isWritable(c)){
if(ioman_getRefCnt(ioman,c)<=lr){
r=c;
lr=ioman_getRefCnt(ioman,c);
}
}
}
}
return(r);
}
/*****************************************************************************/
esint32 ioman_findOverallocableSpot(IOManager *ioman)
{
euint8 points,lp=0xFF;
euint16 c;
esint32 r=-1;
for(c=0;c<ioman->numbuf;c++){
if(ioman->itptr[c]<ioman->numit){
points = 0;
if(ioman_isWritable(c))points+=0x7F;
points += ((euint16)(ioman->itptr[c]*0x4D))/(ioman->numit);
points += ((euint16)(ioman_getRefCnt(ioman,c)*0x33))/0xFF;
if(points<lp){
lp=points;
r=c;
}
}
}
return(r);
}
/*****************************************************************************/
esint8 ioman_putSectorInCache(IOManager *ioman, euint32 address, euint16 bufplace)
{
euint8* buf;
if((buf = ioman_getPtr(ioman,bufplace))==0){
ioman_setError(ioman,IOMAN_ERR_CACHEPTROUTOFRANGE);
return(-1);
}
if((ioman_readSector(ioman,address,buf))){
ioman_setError(ioman,IOMAN_ERR_READFAIL);
return(-1);
}
ioman_setValid(bufplace);
ioman->sector[bufplace]=address;
return(0);
}
/***************** if(bufplace>=ioman->numbuf)return;
************************************************************/
esint8 ioman_flushSector(IOManager *ioman, euint16 bufplace)
{
euint8* buf;
if((buf = ioman_getPtr(ioman,bufplace))==0){
ioman_setError(ioman,IOMAN_ERR_CACHEPTROUTOFRANGE);
return(-1);
}
if(!ioman_isWritable(bufplace)){
ioman_setError(ioman,IOMAN_ERR_WRITEREADONLYSECTOR);
return(-1);
}
if(ioman_writeSector(ioman,ioman->sector[bufplace],buf)){ /* ERROR HERE STILL TO BE FIXED -> ! must be removed! */
ioman_setError(ioman,IOMAN_ERR_WRITEFAIL);
return(-1);
}
if(ioman->usage[bufplace]==0)ioman_setNotWritable(bufplace);
return(0);
}
/*****************************************************************************/
esint8 ioman_flushRange(IOManager *ioman,euint32 address_low, euint32 address_high)
{
euint32 c;
if(address_low>address_high){
c=address_low; address_low=address_high;address_high=c;
}
for(c=0;c<ioman->numbuf;c++){
if((ioman->sector[c]>=address_low) && (ioman->sector[c]<=address_high) && (ioman_isWritable(c))){
if(ioman_flushSector(ioman,c)){
return(-1);
}
if(ioman->usage[c]==0)ioman_setNotWritable(c);
}
}
return(0);
}
/*****************************************************************************/
esint8 ioman_flushAll(IOManager *ioman)
{
euint16 c;
for(c=0;c<ioman->numbuf;c++){
if(ioman_isWritable(c)){
if(ioman_flushSector(ioman,c)){
return(-1);
}
if(ioman->usage[c]==0)ioman_setNotWritable(c);
}
}
return(0);
}
/*****************************************************************************/
euint8* ioman_getSector(IOManager *ioman,euint32 address, euint8 mode)
{
esint32 bp;
if((bp=ioman_findSectorInCache(ioman,address))!=-1){
if(ioman_isReqRw(mode)){
ioman_setWritable(bp);
}
ioman_incUseCnt(ioman,bp);
if(!ioman_isReqExp(mode))ioman_incRefCnt(ioman,bp);
return(ioman_getPtr(ioman,bp));
}
if((bp=ioman_findFreeSpot(ioman))==-1){
if(((bp=ioman_findUnusedSpot(ioman))!=-1)&&(ioman_isWritable(bp))){
ioman_flushSector(ioman,bp);
}
}
if(bp!=-1){
ioman_resetCacheItem(ioman,bp);
if((ioman_putSectorInCache(ioman,address,bp))){
return(0);
}
if(ioman_isReqRw(mode)){
ioman_setWritable(bp);
}
ioman_incUseCnt(ioman,bp);
if(!ioman_isReqExp(mode))ioman_incRefCnt(ioman,bp);
return(ioman_getPtr(ioman,bp));
}
if((bp=ioman_findOverallocableSpot(ioman))!=-1){
if(ioman_isWritable(bp)){
ioman_flushSector(ioman,bp);
}
if(ioman_push(ioman,bp)){
return(0);
}
ioman_resetCacheItem(ioman,bp);
if((ioman_putSectorInCache(ioman,address,bp))){
return(0);
}
if(ioman_isReqRw(mode)){
ioman_setWritable(bp);
}
ioman_incUseCnt(ioman,bp);
if(!ioman_isReqExp(mode))ioman_incRefCnt(ioman,bp);
return(ioman_getPtr(ioman,bp));
}
ioman_setError(ioman,IOMAN_ERR_NOMEMORY);
return(0);
}
/*****************************************************************************/
esint8 ioman_releaseSector(IOManager *ioman,euint8* buf)
{
euint16 bp;
bp=ioman_getBp(ioman,buf);
ioman_decUseCnt(ioman,bp);
if(ioman_getUseCnt(ioman,bp)==0)
{
if(ioman_isWritable(bp))
{
ioman_flushSector(ioman,bp);
}
if(ioman->itptr[bp]!=0)
{
ioman_pop(ioman,bp);
ioman_putSectorInCache(ioman,ioman->sector[bp],bp);
}
}
return(0);
}
/*****************************************************************************/
esint8 ioman_directSectorRead(IOManager *ioman,euint32 address, euint8* buf)
{
euint8* ibuf;
esint16 bp;
if((bp=ioman_findSectorInCache(ioman,address))!=-1){
ibuf=ioman_getPtr(ioman,bp);
memCpy(ibuf,buf,512);
return(0);
}
if((bp=ioman_findFreeSpot(ioman))!=-1){
if((ioman_putSectorInCache(ioman,address,bp))){
return(-1);
}
ibuf=ioman_getPtr(ioman,bp);
memCpy(ibuf,buf,512);
return(0);
}
if(ioman_readSector(ioman,address,buf)){
return(-1);
}
return(0);
}
/*****************************************************************************/
esint8 ioman_directSectorWrite(IOManager *ioman,euint32 address, euint8* buf)
{
euint8* ibuf;
esint16 bp;
if((bp=ioman_findSectorInCache(ioman,address))!=-1){
ibuf=ioman_getPtr(ioman,bp);
memCpy(buf,ibuf,512);
ioman_setWritable(bp);
return(0);
}
if((bp=ioman_findFreeSpot(ioman))!=-1){
ibuf=ioman_getPtr(ioman,bp);
memCpy(buf,ibuf,512);
ioman_resetCacheItem(ioman,bp);
ioman->sector[bp]=address;
ioman_setWritable(bp);
ioman_setValid(bp);
return(0);
}
if(ioman_writeSector(ioman,address,buf)){
return(-1);
}
return(0);
}
/*****************************************************************************/
void ioman_printStatus(IOManager *ioman)
{
euint16 c;
DBG((TXT("IO-Manager -- Report\n====================\n")));
DBG((TXT("Buffer is %i sectors, from %p to %p\n"),
ioman->numbuf,ioman->bufptr,ioman->bufptr+(ioman->numbuf*512)));
for(c=0;c<ioman->numbuf;c++){
if(ioman_isValid(c)){
DBG((TXT("BP %3i\t SC %8li\t\t US %i\t RF %i\t %s %s\n"),
c,ioman->sector[c],ioman_getUseCnt(ioman,c),ioman_getRefCnt(ioman,c),
ioman_isUserBuf(c) ? "USRBUF" : " ",
ioman_isWritable(c) ? "WRITABLE" : "READONLY"));
}
}
}
/*****************************************************************************/

120
filesystem/dfs/filesystems/efsl/src/base/ioman_small.c Normal file
View File

@ -0,0 +1,120 @@
/*****************************************************************************\
* EFSL - Embedded Filesystems Library *
* ----------------------------------- *
* *
* Filename : ioman_small.c *
* Release : 0.3 - devel *
* Description : The IO Manager receives all requests for sectors in a central *
* allowing it to make smart decision regarding caching. *
* The IOMAN_NUMBUFFER parameter determines how many sectors *
* ioman can cache. ioman also supports overallocating and *
* backtracking sectors. *
* This is the small version of IOMan, for systems with limited *
* resources. It features only one fixed buffer, and has *
* simplified operation *
* *
* This program is free software; you can redistribute it and/or *
* modify it under the terms of the GNU General Public License *
* as published by the Free Software Foundation; version 2 *
* of the License. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* As a special exception, if other files instantiate templates or *
* use macros or inline functions from this file, or you compile this *
* file and link it with other works to produce a work based on this file, *
* this file does not by itself cause the resulting work to be covered *
* by the GNU General Public License. However the source code for this *
* file must still be made available in accordance with section (3) of *
* the GNU General Public License. *
* *
* This exception does not invalidate any other reasons why a work based *
* on this file might be covered by the GNU General Public License. *
* *
* (c)2006 Lennart Yseboodt *
* (c)2006 Michael De Nil *
\*****************************************************************************/
#include "ioman_small.h"
esint8 ioman_init(IOManager *ioman, euint8* bufferarea)
{
ioman_reset(ioman);
return(0);
}
/*****************************************************************************/
void ioman_reset(IOManager *ioman)
{
ioman->sector=ioman->status=ioman->itptr=0;
ioman->stack.sector=ioman->stack.status=0;
ioman_setError(ioman,IOMAN_NOERROR);
}
/*****************************************************************************/
void ioman_setAttr(IOManager *ioman,euint8 attribute,euint8 val)
{
if(val){
ioman->status|=1<<attribute;
}else{
ioman->status&=~(1<<attribute);
}
}
/*****************************************************************************/
euint8 ioman_getAttr(IOManager *ioman,euint8 attribute)
{
return(ioman->status&(1<<attribute));
}
/*****************************************************************************/
euint8* ioman_getSector(IOManager *ioman,euint32 address, euint8 mode)
{
if(address==ioman->sector){
if(mode==IOM_MODE_READWRITE)ioman_setWritable();
return(ioman->bufptr);
}
}
esint8 ioman_readSector(IOManager *ioman,euint32 address,euint8* buf)
{
esint8 r;
if(buf==0){
return(-1);
}
//r=if_readBuf(ioman->iface,address,buf);
r = efs_read_sectors(ioman->device, address, 1, buf);
if(r!=0){
ioman_setError(ioman,IOMAN_ERR_READFAIL);
return(-1);
}
return(0);
}
/*****************************************************************************/
esint8 ioman_writeSector(IOManager *ioman, euint32 address, euint8* buf)
{
esint8 r;
if(buf==0)return(-1);
//r=if_writeBuf(ioman->iface,address,buf);
r = efs_write_sectors(ioman->device, address, 1, buf);
if(r<=0){
ioman_setError(ioman,IOMAN_ERR_WRITEFAIL);
return(-1);
}
return(0);
}
/*****************************************************************************/

125
filesystem/dfs/filesystems/efsl/src/base/partition.c Normal file
View File

@ -0,0 +1,125 @@
/*****************************************************************************\
* EFSL - Embedded Filesystems Library *
* ----------------------------------- *
* *
* Filename : partition.c *
* Release : 0.3 - devel *
* Description : These functions are partition specific. Searching FAT type *
* partitions and read/write functions to partitions. *
* *
* This program is free software; you can redistribute it and/or *
* modify it under the terms of the GNU General Public License *
* as published by the Free Software Foundation; version 2 *
* of the License. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* As a special exception, if other files instantiate templates or *
* use macros or inline functions from this file, or you compile this *
* file and link it with other works to produce a work based on this file, *
* this file does not by itself cause the resulting work to be covered *
* by the GNU General Public License. However the source code for this *
* file must still be made available in accordance with section (3) of *
* the GNU General Public License. *
* *
* This exception does not invalidate any other reasons why a work based *
* on this file might be covered by the GNU General Public License. *
* *
* (c)2006 Lennart Yseboodt *
* (c)2006 Michael De Nil *
\*****************************************************************************/
/*****************************************************************************/
#include "partition.h"
#include "efs.h"
/*****************************************************************************/
/* ****************************************************************************
* void part_initPartition(Partition *part,Disc* refDisc)
* Description: This function searches the 4 partitions for a FAT class partition
* and marks the first one found as the active to be used partition.
*/
void part_initPartition(Partition *part)
{
part_setError(part,PART_NOERROR);
}
/*****************************************************************************/
/* ****************************************************************************
* eint16 part_isFatPart(euint8 type)
* Description: This functions checks if a partitiontype (eint8) is of the FAT
* type in the broadest sense. I
* Return value: If it is FAT, returns 1, otherwise 0.
*/
eint16 part_isFatPart(euint8 type)
{
if(type == PT_FAT12 ||
type == PT_FAT16A ||
type == PT_FAT16 ||
type == PT_FAT32 ||
type == PT_FAT32A ||
type == PT_FAT16B )
{
return(1);
}
return(0);
}
/*****************************************************************************/
esint8 part_readBuf(Partition *part, euint32 address, euint8* buf)
{
return efs_read_sectors(part->ioman->device, address, 1, buf);
}
/* ****************************************************************************
* eint16 part_writeBuf(Partition *part,euint32 address,euint8* buf)
* Description: This function writes 512 bytes, from buf. It's offset is address
* sectors from the beginning of the partition.
* Return value: It returns whatever the hardware function returns. (-1=error)
*/
eint16 part_writeBuf(Partition *part,euint32 address,euint8* buf)
{
/*DBG((TXT("part_writeBuf :: %li\n"),address));*/
return efs_write_sectors(part->ioman->device, address, 1, buf);
}
/*****************************************************************************/
/* ****************************************************************************
* euint8* part_getSect(Partition *part, euint32 address, euint8 mode)
* Description: This function calls ioman_getSector, but recalculates the sector
* address to be partition relative.
* Return value: Whatever getSector returns. (pointer or 0)
*/
euint8* part_getSect(Partition *part, euint32 address, euint8 mode)
{
return(ioman_getSector(part->ioman,address,mode));
}
/* ****************************************************************************
* esint8 part_relSect(Partition *part, euint8* buf)
* Description: This function calls ioman_releaseSector.
* Return value: Whatever releaseSector returns.
*/
esint8 part_relSect(Partition *part, euint8* buf)
{
return(ioman_releaseSector(part->ioman,buf));
}
esint8 part_flushPart(Partition *part,euint32 addr_l, euint32 addr_h)
{
return ioman_flushRange(part->ioman,addr_l,addr_h);
}
esint8 part_directSectorRead(Partition *part, euint32 address, euint8* buf, euint32 numsector)
{
return ioman_directSectorRead(part->ioman, address, buf, numsector);
}
esint8 part_directSectorWrite(Partition *part,euint32 address, euint8* buf, euint32 numsector)
{
return ioman_directSectorWrite(part->ioman, address, buf, numsector);
}

83
filesystem/dfs/filesystems/efsl/src/base/plibc.c Normal file
View File

@ -0,0 +1,83 @@
/*****************************************************************************\
* EFSL - Embedded Filesystems Library *
* ----------------------------------- *
* *
* Filename : plibc.c *
* Release : 0.3 - devel *
* Description : This file contains replacements of common c library functions *
* *
* This program is free software; you can redistribute it and/or *
* modify it under the terms of the GNU General Public License *
* as published by the Free Software Foundation; version 2 *
* of the License. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* As a special exception, if other files instantiate templates or *
* use macros or inline functions from this file, or you compile this *
* file and link it with other works to produce a work based on this file, *
* this file does not by itself cause the resulting work to be covered *
* by the GNU General Public License. However the source code for this *
* file must still be made available in accordance with section (3) of *
* the GNU General Public License. *
* *
* This exception does not invalidate any other reasons why a work based *
* on this file might be covered by the GNU General Public License. *
* *
* (c)2006 Lennart Yseboodt *
* (c)2006 Michael De Nil *
\*****************************************************************************/
/*****************************************************************************/
#include "plibc.h"
/*****************************************************************************/
/* ****************************************************************************
* unsigned short strMatch(char* bufa, char*bufb, unsigned long n)
* Description: Compares bufa and bufb for a length of n bytes.
* Return value: Returns the number of character NOT matching.
*/
euint16 strMatch(eint8* bufa, eint8*bufb,euint32 n)
{
euint32 c;
euint16 res=0;
for(c=0;c<n;c++)if(bufa[c]!=bufb[c])res++;
return(res);
}
/*****************************************************************************/
/* ****************************************************************************
* void memCpy(void* psrc, void* pdest, unsigned long size)
* Description: Copies the contents of psrc into pdest on a byte per byte basis.
* The total number of bytes copies is size.
*/
void memCpy(void* psrc, void* pdest, euint32 size)
{
while(size>0){
*((eint8*)pdest+size-1)=*((eint8*)psrc+size-1);
size--;
}
}
/*****************************************************************************/
void memClr(void *pdest,euint32 size)
{
while(size>0){
*(((eint8*)pdest)+size-1)=0x00;
size--;
}
}
void memSet(void *pdest,euint32 size,euint8 data)
{
while(size>0){
*(((eint8*)pdest)+size-1)=data;
size--;
}
}

365
filesystem/dfs/filesystems/efsl/src/fs/vfat/dir.c Normal file
View File

@ -0,0 +1,365 @@
/*****************************************************************************\
* EFSL - Embedded Filesystems Library *
* ----------------------------------- *
* *
* Filename : dir.c *
* Release : 0.3 - devel *
* Description : The functions of dir.c are part of fs.c, they deal with all *
* the directory specific stuff. *
* *
* This program is free software; you can redistribute it and/or *
* modify it under the terms of the GNU General Public License *
* as published by the Free Software Foundation; version 2 *
* of the License. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* As a special exception, if other files instantiate templates or *
* use macros or inline functions from this file, or you compile this *
* file and link it with other works to produce a work based on this file, *
* this file does not by itself cause the resulting work to be covered *
* by the GNU General Public License. However the source code for this *
* file must still be made available in accordance with section (3) of *
* the GNU General Public License. *
* *
* This exception does not invalidate any other reasons why a work based *
* on this file might be covered by the GNU General Public License. *
* *
* (c)2006 Lennart Yseboodt *
* (c)2006 Michael De Nil *
\*****************************************************************************/
/*****************************************************************************/
#include "dir.h"
/*****************************************************************************/
/* ****************************************************************************
* void dir_getFileStructure(FileSystem *fs,FileRecord *filerec,FileLocation *loc)
* Description: This function stores the filerecord located at loc in filerec.
* It fetches the required sector for this.
* Return value: void
*/
void dir_getFileStructure(FileSystem *fs,FileRecord *filerec,FileLocation *loc)
{
euint8 *buf;
buf=part_getSect(fs->part,loc->Sector,IOM_MODE_READONLY);
*filerec=*(((FileRecord*)buf)+loc->Offset);
part_relSect(fs->part,buf);
}
/*****************************************************************************/
/* ****************************************************************************
* void dir_createDirectoryEntry(FileSystem *fs,FileRecord *filerec,FileLocation *loc)
* Description: This function writes the filerecord stored in filerec to disc at
* location loc.
* Return value: void
*/
void dir_createDirectoryEntry(FileSystem *fs,FileRecord *filerec,FileLocation *loc)
{
euint8 *buf;
buf = part_getSect(fs->part,loc->Sector,IOM_MODE_READWRITE);
memCpy(filerec,buf+(loc->Offset*sizeof(*filerec)),sizeof(*filerec));
part_relSect(fs->part,buf);
}
/*****************************************************************************/
/* ****************************************************************************
* void dir_createDefaultEntry(FileSystem *fs,FileRecord *filerec,eint8* fatfilename)
* Description: This function fills in a filerecord with safe default values, and
* a given fatfilename. If your system has a means of knowing time, here is an
* excellent place to apply it to the filerecord.
* Return value: void
*/
void dir_createDefaultEntry(FileSystem *fs,FileRecord *filerec,eint8* fatfilename)
{
memCpy(fatfilename,filerec->FileName,11);
filerec->Attribute=0x00;
filerec->NTReserved=0x00;
filerec->MilliSecTimeStamp=0x00;
filerec->CreatedTime=time_getTime();
filerec->CreatedDate=time_getDate();
filerec->AccessDate=filerec->CreatedDate;
filerec->FirstClusterHigh=0x0000;
filerec->WriteTime=filerec->CreatedTime;
filerec->WriteDate=filerec->CreatedDate;
filerec->FirstClusterLow=0x0000;
filerec->FileSize=0x00000000;
}
/*****************************************************************************/
/* ****************************************************************************
* void dir_setFirstCluster(File *file,euint32 cluster_addr)
* Description: This function requires modification to release it from
* depending on the file object.
* Return value:
*/
void dir_setFirstCluster(FileSystem *fs,FileLocation *loc,euint32 cluster_addr)
{
euint8 *buf;
buf = part_getSect(fs->part,loc->Sector,IOM_MODE_READWRITE);
(((FileRecord*)buf)+loc->Offset)->FirstClusterHigh=cluster_addr>>16;
(((FileRecord*)buf)+loc->Offset)->FirstClusterLow=cluster_addr&0xFFFF;
part_relSect(fs->part,buf);
}
/*****************************************************************************/
/* ****************************************************************************
* void dir_setFileSize(FileSystem *fs, FileLocation *loc,euint32 numbytes)
* Description: This function changes the filesize recorded at loc->Sector
* to 'numbytes'.
* Return value: void
*/
void dir_setFileSize(FileSystem *fs, FileLocation *loc,euint32 numbytes)
{
euint8 *buf;
buf = part_getSect(fs->part,loc->Sector,IOM_MODE_READWRITE);
(((FileRecord*)buf)+loc->Offset)->FileSize=numbytes;
part_relSect(fs->part,buf);
}
/*****************************************************************************/
/* ****************************************************************************
* esint8 dir_updateDirectoryEntry(FileSystem *fs,FileRecord *entry,FileLocation *loc))
* This function changes the entire entity stores at loc to the data recorded
* in entry. This is for custom updates to the directoryentry.
* Return value: 0 on success, -1 on failure
*/
esint8 dir_updateDirectoryEntry(FileSystem *fs,FileRecord *entry,FileLocation *loc)
{
euint8 *buf;
buf = part_getSect(fs->part,loc->Sector,IOM_MODE_READWRITE);
memCpy(entry,buf+(loc->Offset*sizeof(*entry)),sizeof(*entry));
part_relSect(fs->part,buf);
return(0);
}
/* ****************************************************************************
* euint32 dir_findFileinBuf(euint8 *buf, eint8 *fatname, FileLocation *loc)
* This function searches for a given fatfilename in the buffer provided.
* It will iterate through the 16 direntry's in the buffer and searches
* for the fatfilename. If found, it will store the offset and attribute
* entry of the directoryrecord in the loc structure.
* If loc is 0, then it's members are not touched.
* Return value: This function returns 0 when it cannot find the file,
* if it can find the file it will return the first cluster number.
*/
euint32 dir_findFileinBuf(euint8 *buf, eint8 *fatname, FileLocation *loc)
{
FileRecord fileEntry;
euint8 c;
for(c=0; c<16; c++)
{
fileEntry = *(((FileRecord*)buf) + c);
/* Check if the entry is for short filenames */
if( !( (fileEntry.Attribute & 0x0F) == 0x0F ) )
{
if( strMatch((eint8*)fileEntry.FileName,fatname,11) == 0 )
{
/* The entry has been found, return the location in the dir */
if(loc)loc->Offset = c;
if(loc)loc->attrib = fileEntry.Attribute;
if((((euint32 )fileEntry.FirstClusterHigh)<<16)+ fileEntry.FirstClusterLow==0){
return(1); /* Lie about cluster, 0 means not found! */
}else{
return
(
(((euint32 )fileEntry.FirstClusterHigh)<<16)
+ fileEntry.FirstClusterLow
);
}
}
}
}
return(0);
}
/* ****************************************************************************
* euint32 dir_findFreeEntryinBuf(euint8* buf, FileLocation *loc)
* This function searches for a free entry in a given sector 'buf'.
* It will put the offset into the loc->Offset field, given that loc is not 0.
* Return value: 1 when it found a free spot, 0 if it hasn't.
*/
euint32 dir_findFreeEntryinBuf(euint8* buf, FileLocation *loc)
{
FileRecord fileEntry;
euint8 c;
for(c=0;c<16;c++){
fileEntry = *(((FileRecord*)buf) + c);
if( !( (fileEntry.Attribute & 0x0F) == 0x0F ) ){
if(fileEntry.FileName[0] == 0x00 ||
fileEntry.FileName[0] == 0xE5 ){
if(loc)loc->Offset=c;
return(1);
}
}
}
return(0);
}
/* ****************************************************************************
* euint32 dir_findinBuf(euint8 *buf, eint8 *fatname, FileLocation *loc)
* Description: This function searches for a given fatfilename in a buffer.
* Return value: Returns 0 on not found, and the firstcluster when the name is found.
*/
euint32 dir_findinBuf(euint8 *buf, eint8 *fatname, FileLocation *loc, euint8 mode)
{
switch(mode){
case DIRFIND_FILE:
return(dir_findFileinBuf(buf,fatname,loc));
break;
case DIRFIND_FREE:
return(dir_findFreeEntryinBuf(buf,loc));
break;
default:
return(0);
break;
}
return(0);
}
/*****************************************************************************/
/* ****************************************************************************
* euint32 dir_findinCluster(FileSystem *fs,euint32 cluster,eint8 *fatname, FileLocation *loc, euint8 mode)
* This function will search for an existing (fatname) or free directory entry
* in a full cluster.
* Return value: 0 on failure, firstcluster on finding file, and 1 on finding free spot.
*/
euint32 dir_findinCluster(FileSystem *fs,euint32 cluster,eint8 *fatname, FileLocation *loc, euint8 mode)
{
euint8 c,*buf=0;
euint32 fclus;
for(c=0;c<fs->volumeId.SectorsPerCluster;c++){
buf = part_getSect(fs->part,fs_clusterToSector(fs,cluster)+c,IOM_MODE_READONLY);
fclus=dir_findinBuf(buf,fatname,loc,mode);
if(fclus)
{
if(loc)loc->Sector=fs_clusterToSector(fs,cluster)+c;
part_relSect(fs->part,buf);
return(fclus);
}
part_relSect(fs->part,buf);
}
part_relSect(fs->part,buf);
return(0);
}
/* ****************************************************************************
* euint32 dir_findinDir(FileSystem *fs, eint8* fatname,euint32 firstcluster, FileLocation *loc, euint8 mode)
* This function will search for an existing (fatname) or free directory entry
* in a directory, following the clusterchains.
* Return value: 0 on failure, firstcluster on finding file, and 1 on finding free spot.
*/
euint32 dir_findinDir(FileSystem *fs, eint8* fatname,euint32 firstcluster, FileLocation *loc, euint8 mode)
{
euint32 c=0,cluster;
ClusterChain Cache;
Cache.DiscCluster = Cache.FirstCluster = firstcluster;
Cache.LogicCluster = Cache.LastCluster = Cache.Linear = 0;
if(firstcluster <= 1){
return(dir_findinRootArea(fs,fatname,loc,mode));
}
while(!fat_LogicToDiscCluster(fs,&Cache,c++)){
if((cluster=dir_findinCluster(fs,Cache.DiscCluster,fatname,loc,mode))){
return(cluster);
}
}
return(0);
}
/* ****************************************************************************
* euint32 dir_findinDir(FileSystem *fs, eint8* fatname,euint32 firstcluster, FileLocation *loc, euint8 mode)
* This function will search for an existing (fatname) or free directory entry
* in the rootdirectory-area of a FAT12/FAT16 filesystem.
* Return value: 0 on failure, firstcluster on finding file, and 1 on finding free spot.
*/
euint32 dir_findinRootArea(FileSystem *fs,eint8* fatname, FileLocation *loc, euint8 mode)
{
euint32 c,fclus;
euint8 *buf=0;
if((fs->type != FAT12) && (fs->type != FAT16))return(0);
for(c=fs->FirstSectorRootDir;c<(fs->FirstSectorRootDir+fs->volumeId.RootEntryCount/32);c++){
buf = part_getSect(fs->part,c,IOM_MODE_READONLY);
if((fclus=dir_findinBuf(buf,fatname,loc,mode))){
if(loc)loc->Sector=c;
part_relSect(fs->part,buf);
return(fclus);
}
part_relSect(fs->part,buf);
}
part_relSect(fs->part,buf);
return(0);
}
/* ****************************************************************************
* esint8 dir_getFatFileName(eint8* filename, eint8* fatfilename)
* This function will take a full directory path, and strip off all leading
* dirs and characters, leaving you with the MS-DOS notation of the actual filename.
* Return value: 1 on success, 0 on not being able to produca a filename
*/
esint8 dir_getFatFileName(eint8* filename, eint8* fatfilename)
{
eint8 ffnamec[11],*next,nn=0;
memClr(ffnamec,11); memClr(fatfilename,11);
next = filename;
if(*filename=='/')next++;
while((next=file_normalToFatName(next,ffnamec))){
memCpy(ffnamec,fatfilename,11);
nn++;
}
if(nn)return(1);
return(0);
}
/* ****************************************************************************
* esint8 dir_addCluster(FileSystem *fs,euint32 firstCluster)
* This function extends a directory by 1 cluster + optional the number of
* clusters you want pre-allocated. It will also delete the contents of that
* cluster. (or clusters)
* Return value: 0 on success, -1 on fail
*/
esint8 dir_addCluster(FileSystem *fs,euint32 firstCluster)
{
euint32 lastc,logicalc;
ClusterChain cache;
fs_initClusterChain(fs,&cache,firstCluster);
if(fat_allocClusterChain(fs,&cache,1)){
return(-1);
}
lastc = fs_getLastCluster(fs,&cache);
if(CLUSTER_PREALLOC_DIRECTORY){
if(fat_allocClusterChain(fs,&cache,CLUSTER_PREALLOC_DIRECTORY)){
return(-1);
}
logicalc = fat_DiscToLogicCluster(fs,firstCluster,lastc);
while(!fat_LogicToDiscCluster(fs,&cache,++logicalc)){
fs_clearCluster(fs,cache.DiscCluster);
}
}else{
fs_clearCluster(fs,lastc);
}
return(0);
}

577
filesystem/dfs/filesystems/efsl/src/fs/vfat/fat.c Normal file
View File

@ -0,0 +1,577 @@
/*****************************************************************************\
* EFSL - Embedded Filesystems Library *
* ----------------------------------- *
* *
* Filename : fat.c *
* Release : 0.3 - devel *
* Description : This file contains all the functions dealing with the FAT *
* in a Microsoft FAT filesystem. It belongs under fs.c *
* *
* This program is free software; you can redistribute it and/or *
* modify it under the terms of the GNU General Public License *
* as published by the Free Software Foundation; version 2 *
* of the License. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* As a special exception, if other files instantiate templates or *
* use macros or inline functions from this file, or you compile this *
* file and link it with other works to produce a work based on this file, *
* this file does not by itself cause the resulting work to be covered *
* by the GNU General Public License. However the source code for this *
* file must still be made available in accordance with section (3) of *
* the GNU General Public License. *
* *
* This exception does not invalidate any other reasons why a work based *
* on this file might be covered by the GNU General Public License. *
* *
* (c)2006 Lennart Yseboodt *
* (c)2006 Michael De Nil *
\*****************************************************************************/
/*****************************************************************************/
#include "fs.h"
/*****************************************************************************/
/* ****************************************************************************
* unsigned long fat_getSectorAddressFatEntry(FileSystem *fs,unsigned long cluster_addr)
* Description: Returns the sectornumber that holds the fat entry for cluster cluster_addr.
* This works for all FAT types.
* Return value: Sectornumber, or 0. Warning, no boundary check.
*/
euint32 fat_getSectorAddressFatEntry(FileSystem *fs,euint32 cluster_addr)
{
euint32 base = fs->volumeId.ReservedSectorCount,res;
switch(fs->type){
case FAT12:
res=(cluster_addr*3/1024);
if(res>=fs->FatSectorCount){
return(0);
}else{
return(base+res);
}
break;
case FAT16:
res=cluster_addr/256;
if(res>=fs->FatSectorCount){
return(0);
}else{
return(base+res);
}
break;
case FAT32:
res=cluster_addr/128;
if(res>=fs->FatSectorCount){
return(0);
}else{
return(base+res);
}
break;
}
return(0);
}
/*****************************************************************************/
/* ****************************************************************************
* unsigned long fat_getNextClusterAddress(FileSystem *fs,unsigned long cluster_addr
* Description: This function loads the sector of the fat which contains the entry
* for cluster_addr. It then fetches and (if required) calculates it's value.
* This value is the EoC marker -or- the number of the next cluster in the chain.
* Return value: Clusternumber or EoC
*/
euint32 fat_getNextClusterAddress(FileSystem *fs,euint32 cluster_addr,euint16 *linear)
{
euint8 *buf;
euint8 hb,lb;
euint16 offset;
euint32 sector;
euint32 nextcluster=0;
sector=fat_getSectorAddressFatEntry(fs,cluster_addr);
if( (fs->FatSectorCount <= (sector-fs->volumeId.ReservedSectorCount)) || sector==0 )
{
return(0);
}
buf=part_getSect(fs->part,sector,IOM_MODE_READONLY);
switch(fs->type)
{
case FAT12:
offset = ((cluster_addr%1024)*3/2)%512;
hb = buf[offset];
if(offset == 511){
part_relSect(fs->part,buf);
buf=part_getSect(fs->part,sector+1,IOM_MODE_READONLY);
lb = buf[0];
}else{
lb = buf[offset + 1];
}
if(cluster_addr%2==0){
nextcluster = ( ((lb&0x0F)<<8) + (hb) );
}else{
nextcluster = ( (lb<<4) + (hb>>4) );
}
break;
case FAT16:
offset=cluster_addr%256;
nextcluster = *((euint16 *)buf + offset);
break;
case FAT32:
offset=cluster_addr%128;
nextcluster = *((euint32 *)buf + offset);
break;
}
part_relSect(fs->part,buf);
return(nextcluster);
}
/*****************************************************************************/
/* ****************************************************************************
* void fat_setNextClusterAddress(FileSystem *fs,unsigned long cluster_addr,unsigned long next_cluster_addr)
* Description: This function makes an entry in the fattable for cluster_addr. The value it puts there
* is next_cluster_addr.
*/
void fat_setNextClusterAddress(FileSystem *fs,euint32 cluster_addr,euint32 next_cluster_addr)
{
euint8 *buf,*buf2;
euint16 offset;
euint32 sector;
sector=fat_getSectorAddressFatEntry(fs,cluster_addr);
if(fs->FatSectorCount<sector){
DBG((TXT("HARDERROR:::fat_getNextClusterAddress READ PAST FAT BOUNDARY\n")));
return;
}
buf=part_getSect(fs->part,sector,IOM_MODE_READWRITE);
switch(fs->type){
case FAT12:
offset = ((cluster_addr%1024)*3/2)%512;
if(offset == 511){
if(cluster_addr%2==0){
buf[offset]=next_cluster_addr&0xFF;
}else{
buf[offset]=(buf[offset]&0xF)+((next_cluster_addr<<4)&0xF0);
}
buf2=part_getSect(fs->part,fat_getSectorAddressFatEntry(fs,cluster_addr)+1,IOM_MODE_READWRITE);
if(cluster_addr%2==0){
buf2[0]=(buf2[0]&0xF0)+((next_cluster_addr>>8)&0xF);
}else{
buf2[0]=(next_cluster_addr>>4)&0xFF;
}
part_relSect(fs->part,buf2);
}else{
if(cluster_addr%2==0){
buf[offset]=next_cluster_addr&0xFF;
buf[offset+1]=(buf[offset+1]&0xF0)+((next_cluster_addr>>8)&0xF);
}else{
buf[offset]=(buf[offset]&0xF)+((next_cluster_addr<<4)&0xF0);
buf[offset+1]=(next_cluster_addr>>4)&0xFF;
}
}
part_relSect(fs->part,buf);
break;
case FAT16:
offset=cluster_addr%256;
*((euint16*)buf+offset)=next_cluster_addr;
part_relSect(fs->part,buf);
break;
case FAT32:
offset=cluster_addr%128;
*((euint32*)buf+offset)=next_cluster_addr;
part_relSect(fs->part,buf);
break;
}
}
/*****************************************************************************/
/* ****************************************************************************
* short fat_isEocMarker(FileSystem *fs,unsigned long fat_entry)
* Description: Checks if a certain value is the EoC marker for the filesystem
* noted in fs->type.
* Return value: Returns 0 when it is the EoC marker, and 1 otherwise.
*/
eint16 fat_isEocMarker(FileSystem *fs,euint32 fat_entry)
{
switch(fs->type){
case FAT12:
if(fat_entry<0xFF8){
return(0);
}
break;
case FAT16:
if(fat_entry<0xFFF8){
return(0);
}
break;
case FAT32:
if((fat_entry&0x0FFFFFFF)<0xFFFFFF8){
return(0);
}
break;
}
return(1);
}
/*****************************************************************************/
/* ****************************************************************************
* unsigned long fat_giveEocMarker(FileSystem *fs)
* Description: Returns an EoC markernumber valid for the filesystem noted in
* fs->type.
* Note, for FAT32, the upper 4 bits are set to zero, although they should be un
* touched according to MicroSoft specifications. I didn't care.
* Return value: The EoC marker cast to an ulong.
*/
euint32 fat_giveEocMarker(FileSystem *fs)
{
switch(fs->type)
{
case FAT12:
return(0xFFF);
break;
case FAT16:
return(0xFFFF);
break;
case FAT32:
return(0x0FFFFFFF);
break;
}
return(0);
}
/*****************************************************************************/
/* ****************************************************************************
* euint32 fat_getNextClusterAddressWBuf(FileSystem *fs,euint32 cluster_addr, euint8* buf)
* Description: This function retrieves the contents of a FAT field. It does not fetch
* it's own buffer, it is given as a parameter. (ioman makes this function rather obsolete)
* Only in the case of a FAT12 crosssector data entry a sector is retrieved here.
* Return value: The value of the clusterfield is returned.
*/
euint32 fat_getNextClusterAddressWBuf(FileSystem *fs,euint32 cluster_addr, euint8* buf)
{
euint8 *buf2; /* For FAT12 fallover only */
euint8 hb,lb;
euint16 offset;
euint32 nextcluster=0;
switch(fs->type)
{
case FAT12:
offset = ((cluster_addr%1024)*3/2)%512;
hb = buf[offset];
if(offset == 511){
buf2=part_getSect(fs->part,fat_getSectorAddressFatEntry(fs,cluster_addr)+1,IOM_MODE_READONLY);
lb = buf2[0];
part_relSect(fs->part,buf2);
}else{
lb = buf[offset + 1];
}
if(cluster_addr%2==0){
nextcluster = ( ((lb&0x0F)<<8) + (hb) );
}else{
nextcluster = ( (lb<<4) + (hb>>4) );
}
break;
case FAT16:
offset=cluster_addr%256;
nextcluster = *((euint16*)buf + offset);
break;
case FAT32:
offset=cluster_addr%128;
nextcluster = *((euint32*)buf + offset);
break;
}
return(nextcluster);
}
/*****************************************************************************/
/* ****************************************************************************
* void fat_setNextClusterAddressWBuf(FileSystem *fs,euint32 cluster_addr,euint32 next_cluster_addr,euint8* buf)
* Description: This function fills in a fat entry. The entry is cluster_addr and the
* data entered is next_cluster_addr. This function is also given a *buf, so it does
* not write the data itself, except in the case of FAT 12 cross sector data, where
* the second sector is handled by this function.
* Return value:
*/
void fat_setNextClusterAddressWBuf(FileSystem *fs,euint32 cluster_addr,euint32 next_cluster_addr,euint8* buf)
{
euint16 offset;
euint8 *buf2;
switch(fs->type)
{
case FAT12:
offset = ((cluster_addr%1024)*3/2)%512;
if(offset == 511){
if(cluster_addr%2==0){
buf[offset]=next_cluster_addr&0xFF;
}else{
buf[offset]=(buf[offset]&0xF)+((next_cluster_addr<<4)&0xF0);
}
buf2=part_getSect(fs->part,fat_getSectorAddressFatEntry(fs,cluster_addr)+1,IOM_MODE_READWRITE);
if(cluster_addr%2==0){
buf2[0]=(buf2[0]&0xF0)+((next_cluster_addr>>8)&0xF);
}else{
buf2[0]=(next_cluster_addr>>4)&0xFF;
}
part_relSect(fs->part,buf2);
}else{
if(cluster_addr%2==0){
buf[offset]=next_cluster_addr&0xFF;
buf[offset+1]=(buf[offset+1]&0xF0)+((next_cluster_addr>>8)&0xF);
}else{
buf[offset]=(buf[offset]&0xF)+((next_cluster_addr<<4)&0xF0);
buf[offset+1]=(next_cluster_addr>>4)&0xFF;
}
}
break;
case FAT16:
offset=cluster_addr%256;
*((euint16*)buf+offset)=next_cluster_addr;
break;
case FAT32:
offset=cluster_addr%128;
*((euint32*)buf+offset)=next_cluster_addr;
break;
}
}
/*****************************************************************************/
/* ****************************************************************************
* esint16 fat_getNextClusterChain(FileSystem *fs, ClusterChain *Cache)
* Description: This function is to advance the clusterchain of a Cache.
* First, the function verifies if the Cache is valid. It could correct it if it
* is not, but this is not done at the time. If the cachen is valid, the next step is
* to see what the next cluster is, if this is the End of Clustermark, the cache is
* updated to know the lastcluster but will remain untouched otherwise. -1 is returned.
* If there are more clusters the function scans the rest of the chain until the next
* cluster is no longer lineair, or until it has run out of fat data (only 1 sector) is
* examined, namely the one fetched to check for EoC.
* With lineair is meant that logical cluster n+1 should be 1 more than logical cluster n
* at the disc level.
* Return value: 0 on success, or -1 when EoC.
*/
esint16 fat_getNextClusterChain(FileSystem *fs, ClusterChain *Cache)
{
euint32 sect,lr,nlr,dc;
esint16 lin=0;
euint8 *buf;
if(Cache->DiscCluster==0)
{
return(-1);
}
sect=fat_getSectorAddressFatEntry(fs,Cache->DiscCluster);
buf=part_getSect(fs->part,sect,IOM_MODE_READONLY);
dc=fat_getNextClusterAddressWBuf(fs,Cache->DiscCluster,buf);
if(fat_isEocMarker(fs,dc))
{
Cache->LastCluster=Cache->DiscCluster;
part_relSect(fs->part,buf);
return(-1);
}
Cache->DiscCluster=dc;
Cache->LogicCluster++;
lr=Cache->DiscCluster-1;
nlr=lr+1;
while(nlr-1==lr && fat_getSectorAddressFatEntry(fs,nlr)==sect)
{
lr=nlr;
nlr=fat_getNextClusterAddressWBuf(fs,lr,buf);
lin++;
}
Cache->Linear=lin-1<0?0:lin-1;
part_relSect(fs->part,buf);
return(0);
}
/*****************************************************************************/
/* ****************************************************************************
* esint16 fat_LogicToDiscCluster(FileSystem *fs, ClusterChain *Cache,euint32 logiccluster)
* Description: This function is used to follow clusterchains. When called it will convert
* a logical cluster, to a disc cluster, using a Cache object. All it does is call
* getNextClusterChain in the proper manner, and rewind clusterchains if required.
* It is NOT recommended to go backwards in clusterchains, since this will require
* scanning the entire chain every time.
* Return value: 0 on success and -1 on failure (meaning out of bounds).
*/
esint16 fat_LogicToDiscCluster(FileSystem *fs, ClusterChain *Cache,euint32 logiccluster)
{
if(logiccluster<Cache->LogicCluster || Cache->DiscCluster==0){
Cache->LogicCluster=0;
Cache->DiscCluster=Cache->FirstCluster;
Cache->Linear=0;
}
if(Cache->LogicCluster==logiccluster){
return(0);
}
while(Cache->LogicCluster!=logiccluster)
{
if(Cache->Linear!=0)
{
Cache->Linear--;
Cache->LogicCluster++;
Cache->DiscCluster++;
}
else
{
if((fat_getNextClusterChain(fs,Cache))!=0){
return(-1);
}
}
}
return(0);
}
/*****************************************************************************/
/* ****************************************************************************
* eint16 fat_allocClusterChain(FileSystem *fs,ClusterChain *Cache,euint32 num_clusters)
* Description: This function extends a clusterchain by num_clusters. It returns the
* number of clusters it *failed* to allocate.
* Return value: 0 on success, all other values are the number of clusters it could
* not allocate.
*/
eint16 fat_allocClusterChain(FileSystem *fs,ClusterChain *Cache,euint32 num_clusters)
{
euint32 cc,ncl=num_clusters,lc;
euint8 *bufa=0,*bufb=0;
euint8 overflow=0;
if(Cache->FirstCluster<=1)return(num_clusters);
lc=fs_getLastCluster(fs,Cache);
cc=lc;
while(ncl > 0){
cc++;
if(cc>=fs->DataClusterCount+1){
if(overflow){
bufa=part_getSect(fs->part,fat_getSectorAddressFatEntry(fs,lc),IOM_MODE_READWRITE);
fat_setNextClusterAddressWBuf(fs,lc,fat_giveEocMarker(fs),bufa);
Cache->LastCluster=lc;
part_relSect(fs->part,bufa);
return(num_clusters-ncl);
}
cc=2;
overflow++;
}
bufa=part_getSect(fs->part,fat_getSectorAddressFatEntry(fs,cc),IOM_MODE_READONLY);
if(fat_getNextClusterAddressWBuf(fs,cc,bufa)==0){
bufb=part_getSect(fs->part,fat_getSectorAddressFatEntry(fs,lc),IOM_MODE_READWRITE);
fat_setNextClusterAddressWBuf(fs,lc,cc,bufb);
part_relSect(fs->part,bufb);
ncl--;
lc=cc;
}
part_relSect(fs->part,bufa);
if(ncl==0){
bufa=part_getSect(fs->part,fat_getSectorAddressFatEntry(fs,lc),IOM_MODE_READWRITE);
fat_setNextClusterAddressWBuf(fs,lc,fat_giveEocMarker(fs),bufa);
Cache->LastCluster=lc;
part_relSect(fs->part,bufa);
}
}
return(0);
}
/* ****************************************************************************
* eint16 fat_unlinkClusterChain(FileSystem *fs,ClusterChain *Cache)
* Description: This function removes a clusterchain. Starting at FirstCluster
* it follows the chain until the end, resetting all values to 0.
* Return value: 0 on success.
*/
eint16 fat_unlinkClusterChain(FileSystem *fs,ClusterChain *Cache)
{
euint32 c,tbd=0;
Cache->LogicCluster=0;
Cache->DiscCluster=Cache->FirstCluster;
c=0;
while(!fat_LogicToDiscCluster(fs,Cache,c++)){
if(tbd!=0){
fat_setNextClusterAddress(fs,tbd,0);
}
tbd=Cache->DiscCluster;
}
fat_setNextClusterAddress(fs,Cache->DiscCluster,0);
return(0);
}
euint32 fat_countClustersInChain(FileSystem *fs,euint32 firstcluster)
{
ClusterChain cache;
euint32 c=0;
if(firstcluster<=1)return(0);
cache.DiscCluster = cache.LogicCluster = cache.LastCluster = cache.Linear = 0;
cache.FirstCluster = firstcluster;
while(!(fat_LogicToDiscCluster(fs,&cache,c++)));
return(c-1);
}
euint32 fat_DiscToLogicCluster(FileSystem *fs,euint32 firstcluster,euint32 disccluster)
{
ClusterChain cache;
euint32 c=0,r=0;
cache.DiscCluster = cache.LogicCluster = cache.LastCluster = cache.Linear = 0;
cache.FirstCluster = firstcluster;
while(!(fat_LogicToDiscCluster(fs,&cache,c++)) && !r){
if(cache.DiscCluster == disccluster){
r = cache.LogicCluster;
}
}
return(r);
}
void fat_ShortnameToString(const euint8* src, eint8* nm)
{
register eint32 i;
i = 8;
while (i-- && *src != ' ')
{
*nm++ = *src++;
}
src += i + 1;
if (*src > ' ')
{
*nm++ = '.';
i = 3;
while (i-- && *src != ' ')
{
*nm++ = *src++;
}
}
*nm = '\0';
}

551
filesystem/dfs/filesystems/efsl/src/fs/vfat/file.c Normal file
View File

@ -0,0 +1,551 @@
/*****************************************************************************\
* EFSL - Embedded Filesystems Library *
* ----------------------------------- *
* *
* Filename : file.c *
* Release : 0.3 - devel *
* Description : This file contains functions dealing with files such as: *
* fopen, fread and fwrite. *
* *
* This program is free software; you can redistribute it and/or *
* modify it under the terms of the GNU General Public License *
* as published by the Free Software Foundation; version 2 *
* of the License. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* As a special exception, if other files instantiate templates or *
* use macros or inline functions from this file, or you compile this *
* file and link it with other works to produce a work based on this file, *
* this file does not by itself cause the resulting work to be covered *
* by the GNU General Public License. However the source code for this *
* file must still be made available in accordance with section (3) of *
* the GNU General Public License. *
* *
* This exception does not invalidate any other reasons why a work based *
* on this file might be covered by the GNU General Public License. *
* *
* (c)2006 Lennart Yseboodt *
* (c)2006 Michael De Nil *
\*****************************************************************************/
/*****************************************************************************/
#include <dfs_fs.h>
#include "file.h"
#include "ui.h"
/*****************************************************************************/
/* ****************************************************************************
* euint32 file_fread(File *file,euint32 offset, euint32 size,euint8 *buf)
* Description: This function reads 'size' bytes from 'file' starting at
* 'offset' and puts the result in '*buf'.
* Return value: amount of bytes actually read (can differ from the given
* size when the file was smaller
*/
euint32 file_fread(File *file,euint32 offset, euint32 size,euint8 *buf)
{
euint32 bytes_read=0,size_left=size,coffset=offset;
euint32 cclus,csec,cbyte;
euint32 rclus,rsec;
euint32 btr;
euint8 *tbuf;
if(!file_getAttr(file,FILE_STATUS_OPEN))return(0);
if(offset>=file->FileSize)
size_left=0; /* Offset check */
if( (offset+size > file->FileSize) && size_left!=0)
size_left=file->FileSize-offset;
while(size_left>0)
{
cclus = coffset/(512*file->fs->volumeId.SectorsPerCluster);
csec = (coffset/(512))%file->fs->volumeId.SectorsPerCluster;
cbyte = coffset%512;
if ((size_left > 512 * file->fs->volumeId.SectorsPerCluster) &&
(csec == 0) && (cbyte == 0))
{
/* read whole cluster */
btr = 512 * file->fs->volumeId.SectorsPerCluster;
}
else if(cbyte!=0 || size_left<512)
{
btr = 512-(coffset%512) >= size_left? size_left:512-(coffset%512);
}
else
{
/* whole sector */
btr = 512;
}
if((fat_LogicToDiscCluster(file->fs,&(file->Cache),cclus))!=0){
return(0);
}
rclus = file->Cache.DiscCluster;
rsec = fs_clusterToSector(file->fs,rclus);
if(btr > 512)
{
part_directSectorRead(file->fs->part, rsec + csec, buf + bytes_read, btr / 512);
}
else
{
tbuf = part_getSect(file->fs->part,rsec+csec,IOM_MODE_READONLY);
memCpy(tbuf+(coffset%512),buf+bytes_read,btr);
part_relSect(file->fs->part,tbuf);
}
coffset+=btr;
bytes_read+=btr;
size_left-=btr;
}
return(bytes_read);
}
/*****************************************************************************/
/* ****************************************************************************
* euint32 file_read (File *file,euint32 size,euint8 *buf)
* Description: This function reads from a file, taking the FilePtr into account
* and advancing it according to the freadcall.
* Return value: Value obtained from fread
*/
euint32 file_read(File *file,euint32 size,euint8 *buf)
{
euint32 r;
r=file_fread(file,file->FilePtr,size,buf);
file->FilePtr+=r;
return(r);
}
/*****************************************************************************/
/* ****************************************************************************
* euint32 file_write(File *file, euint32 size,euint8 *buf)
* Description: This function writes to a file, taking FilePtr into account
* and advancing it according to the fwritecall.
* Return value: Value obtained from fread
*/
euint32 file_write(File *file, euint32 size,euint8 *buf)
{
euint32 r;
r=file_fwrite(file,file->FilePtr,size,buf);
file->FilePtr+=r;
return(r);
}
/*****************************************************************************/
/* ****************************************************************************
* esint32 file_setpos(File *file,euint32 pos)
* Description: This function does a sanity check on the requested position
* and changes the fileptr accordingly.
* Return value: 0 on success and -1 on failure.
*/
esint32 file_setpos(File *file,euint32 pos)
{
if(pos<=file->FileSize){
file->FilePtr=pos;
return(pos);
}
return(-1);
}
/*****************************************************************************/
/* ****************************************************************************
* euint32 file_fwrite(File* file,euint32 offset,euint32 size,euint8* buf)
* Description: This function writes to a file, at offset 'offset' and size 'size'.
* It also updates the FileSize in the object, and discstructure.
* Return value: Bytes actually written.
*/
euint32 file_fwrite(File* file,euint32 offset,euint32 size,euint8* buf)
{
euint32 need_cluster;
euint32 cclus,csec,cbyte;
euint32 size_left=size,bytes_written=0;
euint32 rclus,rsec;
euint32 coffset=offset;
euint16 btr;
euint8 *tbuf;
if(!file_getAttr(file,FILE_STATUS_OPEN) || !file_getAttr(file,FILE_STATUS_WRITE))return(0);
if(offset>file->FileSize){
offset=file->FileSize;
}
need_cluster = file_requiredCluster(file,offset,size);
if(need_cluster){
if(fat_allocClusterChain(file->fs,&(file->Cache),need_cluster+CLUSTER_PREALLOC_FILE)!=0){
return(0);
}
}
while(size_left>0){
cclus = coffset/(512*file->fs->volumeId.SectorsPerCluster);
csec = (coffset/(512))%file->fs->volumeId.SectorsPerCluster;
cbyte = coffset%512;
if ((size_left > 512 * file->fs->volumeId.SectorsPerCluster) &&
(csec == 0) && (cbyte == 0))
{
/* write whole cluster */
btr = 512 * file->fs->volumeId.SectorsPerCluster;
}
else if(cbyte!=0 || size_left<512)
{
btr = 512- (coffset%512) >= size_left? size_left:512-(coffset%512);
}
else
{
/* whole sector */
btr = 512;
}
if((fat_LogicToDiscCluster(file->fs,&(file->Cache),cclus))!=0){
file->FileSize+=bytes_written;
dir_setFileSize(file->fs,&(file->Location),file->FileSize);
return(bytes_written);
}
rclus=file->Cache.DiscCluster;
rsec=fs_clusterToSector(file->fs,rclus);
if(btr > 512)
{
part_directSectorWrite(file->fs->part, rsec + csec, buf + bytes_written, btr / 512);
}
else
{
tbuf = part_getSect(file->fs->part,rsec+csec,IOM_MODE_READWRITE);
memCpy(buf+bytes_written, tbuf+(coffset%512), btr);
part_relSect(file->fs->part,tbuf);
}
coffset+=btr;
bytes_written+=btr;
size_left-=btr;
}
if(bytes_written>file->FileSize-offset){
file->FileSize+=bytes_written-(file->FileSize-offset);
}
return(bytes_written);
}
/* ****************************************************************************
* esint8 file_fclose(File *file)
* Description: This function closes a file, by clearing the object.
* Return value: 0 on success.
*/
esint8 file_fclose(File *file)
{
if(fs_hasTimeSupport()){
file->DirEntry.AccessDate = time_getDate();
if(file_getAttr(file,FILE_STATUS_WRITE)){
file->DirEntry.FileSize = file->FileSize;
file->DirEntry.WriteDate = file->DirEntry.AccessDate;
file->DirEntry.WriteTime = time_getTime();
}
dir_updateDirectoryEntry(file->fs,&(file->DirEntry),&(file->Location));
}else{
if(file_getAttr(file,FILE_STATUS_WRITE)){
dir_setFileSize(file->fs,&(file->Location),file->FileSize);
}
}
memClr(file,sizeof(*file));
file_setAttr(file,FILE_STATUS_OPEN,0);
file_setAttr(file,FILE_STATUS_WRITE,0);
return(0);
}
/* ****************************************************************************
* void file_initFile(File *file, FileSystem *fs, FileLocation *loc)
* Description: This function initialises a new file object, by filling in
* the fs pointer, filesize (note, that DirEntry must already be filled in)
* and known cache parameters.
* Return value: void
*/
void file_initFile(File *file, FileSystem *fs, FileLocation *loc)
{
file->fs=fs;
file->FileSize=file->DirEntry.FileSize;
file->FilePtr=0;
file->Location.Sector=loc->Sector;
file->Location.Offset=loc->Offset;
file->Cache.Linear=0;
file->Cache.FirstCluster=(((euint32)file->DirEntry.FirstClusterHigh)<<16)+
file->DirEntry.FirstClusterLow;
file->Cache.LastCluster=0;
file->Cache.LogicCluster=0;
file->Cache.DiscCluster=file->Cache.FirstCluster;
}
/*****************************************************************************/
/* ****************************************************************************
* euint8* file_normalToFatName(eint8* filename,eint8* fatfilename)
* Description: This function converts a human readable filename (limited to
* 8.3 eint8 character) to a valid FAT (not VFAT) filename. Invalid characters are
* changed to capital X and only the first 11 characters are used.
* Furthermore all letters are capitalised.
* Return value: pointer after the filename
*/
eint8* file_normalToFatName(eint8* filename,eint8* fatfilename)
{
euint8 c,dot=0,vc=0;
for(c=0;c<11;c++)fatfilename[c]=' ';
c=0;
if(*filename == '.'){
fatfilename[0]='.';
vc++;
if(*(filename+1) == '.'){
fatfilename[1]='.';
filename+=2;
}else{
filename++;
}
}else{
while(*filename != '\0' && *filename != ' ' && *filename != '/'){
if(*filename=='.' && !dot){
dot=1;
c=8;
}else{
if(dot){
if(c<=10){
fatfilename[c]=file_validateChar(*filename);
c++;
}
}else{
if(c<=7){
fatfilename[c]=file_validateChar(*filename);
c++; vc++;
}
}
}
filename++;
}
}
if(vc>0){
if(*filename=='\0'){
return(filename);
}else{
return(filename+1);
}
}else{
return(0);
}
}
/*****************************************************************************/
/* ****************************************************************************
*
* Description: This function takes the character c, and if it is not a *
* valid FAT Filename character returns X. If it is a lowercase letter the *
* uppercase equivalent is returned. The remaining characters are returned *
* as they are.
* Return value: The validated char
*/
euint8 file_validateChar(euint8 c)
{
if( (c<0x20) || (c>0x20&&c<0x30&&c!='-') || (c>0x39&&c<0x41) || (c>0x5A&&c<0x61&&c!='_') || (c>0x7A&&c!='~') )
return(0x58);
if( c>=0x61 && c<=0x7A )
return(c-32);
return(c);
}
/*****************************************************************************/
/* ****************************************************************************
* void ioman_setAttr(IOManager *ioman,euint16 bufplace,euint8 attribute,euint8 val)
* Description: This sets the attribute of 'bufplace' to the given value (binary).
*
* Return value: void
*/
void file_setAttr(File* file,euint8 attribute,euint8 val)
{
if(val){
file->FileStatus|=1<<attribute;
}else{
file->FileStatus&=~(1<<attribute);
}
}
/*****************************************************************************/
/* ****************************************************************************
* euint8 ioman_getAttr(IOManager *ioman,euint16 bufplace,euint8 attribute)
* Description: This function retrieves an attribute from the bufstat array.
* It returns nonzero when it attribute is true and 0 when it is false.
* Please note, I said "nonzero", not 1.
* Return value: Attribute.
*/
euint8 file_getAttr(File* file,euint8 attribute)
{
return(file->FileStatus&(1<<attribute));
}
/*****************************************************************************/
euint32 file_requiredCluster(File *file,euint32 offset, euint32 size)
{
euint32 clusters_required,clustersize;
euint32 hc;
if((offset+size)>file->FileSize){
hc = fat_countClustersInChain(file->fs,file->Cache.FirstCluster);
clustersize = file->fs->volumeId.BytesPerSector * file->fs->volumeId.SectorsPerCluster;
if((size-file->FileSize+offset)>
((hc-((file->FileSize+clustersize-1)/clustersize))*clustersize)){
clusters_required = (((offset+size)-(hc*clustersize))+clustersize-1)/clustersize;
}else{
clusters_required = 0;
}
}else{
clusters_required = 0;
}
return(clusters_required);
}
esint8 file_fopen(File* file,FileSystem *fs,eint8* filename,eint32 mode)
{
FileLocation loc;
FileRecord wtmp;
eint8 fatfilename[11];
euint32 sec;
dir_getFatFileName(filename,fatfilename);
/* create */
if(mode & DFS_O_CREAT)
{
/* file does not exist */
if(fs_findFile(fs,filename,&loc,0) == 0)
{
if(fs_findFreeFile(fs,filename,&loc,0))
{
dir_createDefaultEntry(fs,&wtmp,fatfilename);
dir_createDirectoryEntry(fs,&wtmp,&loc);
memCpy(&wtmp,&(file->DirEntry),sizeof(wtmp));
file_initFile(file,fs,&loc);
sec=fs_getNextFreeCluster(file->fs,fs_giveFreeClusterHint(file->fs));
dir_setFirstCluster(file->fs,&(file->Location),sec);
fs_setFirstClusterInDirEntry(&(file->DirEntry),sec);
fs_initClusterChain(fs,&(file->Cache),sec);
fat_setNextClusterAddress(fs,sec,fat_giveEocMarker(fs));
if (mode & DFS_O_APPEND)
file_setpos(file,file->FileSize);
}
else
{
dfs_log(DFS_DEBUG_INFO, ("no space left on device"));
return -DFS_STATUS_ENOSPC;
}
}
else if ( mode & DFS_O_EXCL)
{
dfs_log(DFS_DEBUG_INFO, ("file has existed"));
return -DFS_STATUS_EEXIST;
}
/*file exist*/
else
{
dir_getFileStructure(fs,&(file->DirEntry), &loc);
file_initFile(file,fs,&loc);
}
file_setAttr(file,FILE_STATUS_OPEN,1);
file_setAttr(file,FILE_STATUS_WRITE,1);
}
/* write */
else if(mode & DFS_O_WRONLY || mode & DFS_O_RDWR)
{
/* file does not exist */
if(fs_findFile(fs,filename,&loc,0) == 0)
{
if(fs_findFreeFile(fs,filename,&loc,0))
{
dir_createDefaultEntry(fs,&wtmp,fatfilename);
dir_createDirectoryEntry(fs,&wtmp,&loc);
memCpy(&wtmp,&(file->DirEntry),sizeof(wtmp));
file_initFile(file,fs,&loc);
sec=fs_getNextFreeCluster(file->fs,fs_giveFreeClusterHint(file->fs));
dir_setFirstCluster(file->fs,&(file->Location),sec);
fs_setFirstClusterInDirEntry(&(file->DirEntry),sec);
fs_initClusterChain(fs,&(file->Cache),sec);
fat_setNextClusterAddress(fs,sec,fat_giveEocMarker(fs));
if (mode & DFS_O_APPEND)
file_setpos(file,file->FileSize);
}
else
{
dfs_log(DFS_DEBUG_INFO, ("no space left on device"));
return -DFS_STATUS_ENOSPC;
}
}
else
{
if (mode & DFS_O_APPEND)
{
dir_getFileStructure(fs,&(file->DirEntry), &loc);
file_initFile(file,fs,&loc);
if(file->Cache.FirstCluster==0)
{
sec=fs_getNextFreeCluster(file->fs,fs_giveFreeClusterHint(file->fs));
dir_setFirstCluster(file->fs,&(file->Location),sec);
fs_setFirstClusterInDirEntry(&(file->DirEntry),sec);
fat_setNextClusterAddress(fs,sec,fat_giveEocMarker(fs));
file_initFile(file,fs,&loc);
file_setpos(file,file->FileSize);
}
}
else
{
dir_getFileStructure(fs,&(file->DirEntry), &loc);
file_initFile(file,fs,&loc);
}
}
file_setAttr(file,FILE_STATUS_OPEN,1);
file_setAttr(file,FILE_STATUS_WRITE,1);
}
/* read */
else
{
/* file does not exist */
if(fs_findFile(fs,filename,&loc,0) == 0)
{
dfs_log(DFS_DEBUG_INFO, ("file doesn't exist"));
return -DFS_STATUS_ENOENT;
}
else
{
dir_getFileStructure(fs,&(file->DirEntry), &loc);
file_initFile(file,fs,&loc);
file_setAttr(file,FILE_STATUS_OPEN,1);
file_setAttr(file,FILE_STATUS_WRITE,0);
}
}
return 0;
}

503
filesystem/dfs/filesystems/efsl/src/fs/vfat/fs.c Normal file
View File

@ -0,0 +1,503 @@
/*****************************************************************************\
* EFSL - Embedded Filesystems Library *
* ----------------------------------- *
* *
* Filename : fs.c *
* Release : 0.3 - devel *
* Description : These are general filesystem functions, supported by the *
* functions of dir.c and fat.c file.c uses these functions *
* heavily, but is not used by fs.c (not true anymore) *
* *
* This program is free software; you can redistribute it and/or *
* modify it under the terms of the GNU General Public License *
* as published by the Free Software Foundation; version 2 *
* of the License. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* As a special exception, if other files instantiate templates or *
* use macros or inline functions from this file, or you compile this *
* file and link it with other works to produce a work based on this file, *
* this file does not by itself cause the resulting work to be covered *
* by the GNU General Public License. However the source code for this *
* file must still be made available in accordance with section (3) of *
* the GNU General Public License. *
* *
* This exception does not invalidate any other reasons why a work based *
* on this file might be covered by the GNU General Public License. *
* *
* (c)2006 Lennart Yseboodt *
* (c)2006 Michael De Nil *
\*****************************************************************************/
/*****************************************************************************/
#include "fs.h"
#include "fat.h"
#include "dir.h"
/*****************************************************************************/
/* ****************************************************************************
* eint16 fs_initFs(FileSystem *fs,Partition *part)
* Description: This functions glues the initialisation of the filesystem together.
* It loads the volumeID, computes the FS type and searches for the rootsector.
* Return value: Returns 0 on succes and -1 on error (if magic code is wrong)
*/
eint16 fs_initFs(FileSystem *fs,Partition *part)
{
if(!fs_isValidFat(part)){
return(-1);
}
fs->part=part;
fs_loadVolumeId(fs,part);
if(!fs_verifySanity(fs))return(-2);
fs_countDataSectors(fs);
fs_determineFatType(fs);
fs_findFirstSectorRootDir(fs);
fs_initCurrentDir(fs);
return(0);
}
/*****************************************************************************/
/* ****************************************************************************
* eint16 fs_isValidFat(Partition *part)
* Description: This functions loads the volumeID and checks if the magic
* value is present.
* Return value: returns 0 when magic code is missing, 1 if it is there.
*/
eint16 fs_isValidFat(Partition *part)
{
euint8 *buf;
buf=part_getSect(part,0,IOM_MODE_READONLY|IOM_MODE_EXP_REQ); /* Load Volume label */
if( ex_getb16(buf+0x1FE) != 0xAA55 ){
return (0);
}
part_relSect(part,buf);
return(1);
}
/*****************************************************************************/
/* ****************************************************************************
* void fs_loadVolumeId(FileSystem *fs, Partition *part)
* Description: This function loads all relevant fields from the volumeid.
*/
void fs_loadVolumeId(FileSystem *fs, Partition *part)
{
euint8 *buf;
buf=part_getSect(part,0,IOM_MODE_READONLY|IOM_MODE_EXP_REQ);
fs->volumeId.BytesPerSector=ex_getb16(buf+0x0B);
fs->volumeId.SectorsPerCluster=*((eint8*)(buf+0x0D));
fs->volumeId.ReservedSectorCount=ex_getb16(buf+0x0E);
fs->volumeId.NumberOfFats=*((eint8*)(buf+0x10));
fs->volumeId.RootEntryCount=ex_getb16(buf+0x11);
fs->volumeId.SectorCount16=ex_getb16(buf+0x13);
fs->volumeId.FatSectorCount16=ex_getb16(buf+0x16);
fs->volumeId.SectorCount32=ex_getb32(buf+0x20);
fs->volumeId.FatSectorCount32=ex_getb32(buf+0x24);
fs->volumeId.RootCluster=ex_getb32(buf+0x2C);
part_relSect(part,buf);
}
/*****************************************************************************/
/* ****************************************************************************
* esint16 fs_verifySanity(FileSystem *fs)
* Description: Does some sanity calculations.
* Return value: 1 on success, 0 when discrepancies were found.
*/
esint16 fs_verifySanity(FileSystem *fs)
{
esint16 sane=1; /* Sane until proven otherwise */
/* First check, BPS, we only support 512 */
if(fs->volumeId.BytesPerSector!=512)sane=0;
/* Check is SPC is valid (multiple of 2, and clustersize >=32KB */
if(!((fs->volumeId.SectorsPerCluster == 1 ) |
(fs->volumeId.SectorsPerCluster == 2 ) |
(fs->volumeId.SectorsPerCluster == 4 ) |
(fs->volumeId.SectorsPerCluster == 8 ) |
(fs->volumeId.SectorsPerCluster == 16) |
(fs->volumeId.SectorsPerCluster == 32) |
(fs->volumeId.SectorsPerCluster == 64) ))sane=0;
/* Any number of FAT's should be supported... (untested) */
/* There should be at least 1 reserved sector */
if(fs->volumeId.ReservedSectorCount==0)sane=0;
return(sane);
}
/*****************************************************************************/
/* ****************************************************************************
* void fs_countDataSectors(FileSystem *fs)
* Description: This functions calculates the sectorcounts, fatsectorcounts and
* dataclustercounts. It fills in the general fields.
*/
void fs_countDataSectors(FileSystem *fs)
{
euint32 rootDirSectors,dataSectorCount;
rootDirSectors=((fs->volumeId.RootEntryCount*32) +
(fs->volumeId.BytesPerSector - 1)) /
fs->volumeId.BytesPerSector;
if(fs->volumeId.FatSectorCount16 != 0)
{
fs->FatSectorCount=fs->volumeId.FatSectorCount16;
fs->volumeId.FatSectorCount32=0;
}
else
{
fs->FatSectorCount=fs->volumeId.FatSectorCount32;
fs->volumeId.FatSectorCount16=0;
}
if(fs->volumeId.SectorCount16!=0)
{
fs->SectorCount=fs->volumeId.SectorCount16;
fs->volumeId.SectorCount32=0;
}
else
{
fs->SectorCount=fs->volumeId.SectorCount32;
fs->volumeId.SectorCount16=0;
}
dataSectorCount=fs->SectorCount - (
fs->volumeId.ReservedSectorCount +
(fs->volumeId.NumberOfFats * fs->FatSectorCount) +
rootDirSectors);
fs->DataClusterCount=dataSectorCount/fs->volumeId.SectorsPerCluster;
}
/*****************************************************************************/
/* ****************************************************************************
* void fs_determineFatType(FileSystem *fs)
* Description: This function looks af the Dataclustercount and determines the
* FAT type. It fills in fs->type.
*/
void fs_determineFatType(FileSystem *fs)
{
if(fs->DataClusterCount < 4085)
{
fs->type=FAT12;
fs->volumeId.RootCluster=0;
}
else if(fs->DataClusterCount < 65525)
{
fs->type=FAT16;
fs->volumeId.RootCluster=0;
}
else
{
fs->type=FAT32;
}
}
/*****************************************************************************/
/* ****************************************************************************
* void fs_findFirstSectorRootDir(FileSystem *fs)
* Description: This functions fills in the fs->FirstSectorRootDir field, even
* for FAT32, although that is not necessary (because you have FirstClusterRootDir).
*/
void fs_findFirstSectorRootDir(FileSystem *fs)
{
if(fs->type==FAT32)
fs->FirstSectorRootDir = fs->volumeId.ReservedSectorCount +
(fs->volumeId.NumberOfFats*fs->volumeId.FatSectorCount32) +
(fs->volumeId.RootCluster-2)*fs->volumeId.SectorsPerCluster;
else
fs->FirstSectorRootDir = fs->volumeId.ReservedSectorCount +
(fs->volumeId.NumberOfFats*fs->volumeId.FatSectorCount16);
}
/*****************************************************************************/
void fs_initCurrentDir(FileSystem *fs)
{
fs->FirstClusterCurrentDir = fs_getFirstClusterRootDir(fs);
}
/*****************************************************************************/
/* ****************************************************************************
* long fs_clusterToSector(FileSystem *fs,euint32 cluster)
* Description: This function converts a clusternumber in the effective sector
* number where this cluster starts. Boundary check is not implemented
* Return value: A long is returned representing the sectornumber.
*/
euint32 fs_clusterToSector(FileSystem *fs,euint32 cluster)
{
eint32 base;
if(fs->type==FAT32)
{
base=
fs->volumeId.ReservedSectorCount+
fs->FatSectorCount*fs->volumeId.NumberOfFats;
}
else
{
base=
fs->volumeId.ReservedSectorCount+
fs->FatSectorCount*fs->volumeId.NumberOfFats+
fs->volumeId.RootEntryCount/16;
}
return( base + (cluster-2)*fs->volumeId.SectorsPerCluster );
}
/*****************************************************************************/
/* Function is unused, but may be usefull */
euint32 fs_sectorToCluster(FileSystem *fs,euint32 sector)
{
eint32 base;
if(fs->type==FAT32)
{
base=
fs->volumeId.ReservedSectorCount+
fs->FatSectorCount*fs->volumeId.NumberOfFats;
}
else
{
base=
fs->volumeId.ReservedSectorCount+
fs->FatSectorCount*fs->volumeId.NumberOfFats+
fs->volumeId.RootEntryCount/16;
}
return(((sector-base)-((sector-base)%fs->volumeId.SectorsPerCluster))/fs->volumeId.SectorsPerCluster+2 );
}
/*****************************************************************************/
/* ****************************************************************************
* euint32 fs_getNextFreeCluster(FileSystem *fs,euint32 startingcluster)
* Description: This functions searches for a free cluster, starting it's search at
* cluster startingcluster. This allow to speed up searches and try to avoid
* fragmentation. Implementing rollover search is still to be done.
* Return value: If a free cluster is found it's number is returned. If none is
* found 0 is returned.
*/
euint32 fs_getNextFreeCluster(FileSystem *fs,euint32 startingcluster)
{
euint32 r;
while(startingcluster<fs->DataClusterCount){
r=fat_getNextClusterAddress(fs,startingcluster,0);
if(r==0){
return(startingcluster);
}
startingcluster++;
}
return(0);
}
/*****************************************************************************/
/* ****************************************************************************
* euint32 fs_giveFreeClusterHint(FileSystem *fs)
*
* Description: This function should return a clusternumber that is free or
* lies close before free clusters. The result MUST be checked to see if
* it is free! Implementationhint: search the largest clusternumber in the
* files in the rootdirectory.
*
* Return value: Returns it's best guess.
*/
euint32 fs_giveFreeClusterHint(FileSystem *fs)
{
return(2); /* Now THIS is a hint ;) */
}
/*****************************************************************************/
/* ****************************************************************************
* esint8 fs_findFile(FileSystem *fs,eint8* filename,FileLocation *loc,euint32 *lastDir)
*
* Description: This function looks if the given filename is on the given fs
* and, if found, fills in its location in loc.
* The function will first check if the pathname starts with a slash. If so it will
* set the starting directory to the rootdirectory. Else, it will take the firstcluster-
* currentdir (That you can change with chdir()) as startingpoint.
* The lastdir pointer will be the first cluster of the last directory fs_findfile
* enters. It starts out at the root/current dir and then traverses the path along with
* fs_findFile.
* It is set to 0 in case of errors (like dir/dir/dir/file/dir/dir...)
* Return value: Returns 0 when nothing was found, 1 when the thing found
* was a file and 2 if the thing found was a directory.
*/
esint8 fs_findFile(FileSystem *fs,eint8* filename,FileLocation *loc,euint32 *lastDir)
{
euint32 fccd,tmpclus;
eint8 ffname[11],*next,it=0,filefound=0;
if(*filename=='/'){
fccd = fs_getFirstClusterRootDir(fs);
filename++;
if(!*filename){
if(lastDir)*lastDir=fccd;
return(2);
}
}else{
fccd = fs->FirstClusterCurrentDir;
}
if(lastDir)*lastDir=fccd;
while((next=file_normalToFatName(filename,ffname))!=0){
if((tmpclus=dir_findinDir(fs,ffname,fccd,loc,DIRFIND_FILE))==0)return(0);
it++;
if(loc->attrib&ATTR_DIRECTORY){
fccd = tmpclus;
filename = next;
if(lastDir)*lastDir=fccd;
if(filefound)*lastDir=0;
}else{
filefound=1;
if((file_normalToFatName(next,ffname))!=0){
return(0);
}else{
filename=next;
}
}
}
if(it==0)return(0);
if(loc->attrib&ATTR_DIRECTORY || !filefound)return(2);
return(1);
}
/*****************************************************************************/
esint16 fs_findFreeFile(FileSystem *fs,eint8* filename,FileLocation *loc,euint8 mode)
{
euint32 targetdir=0;
eint8 ffname[11];
if(fs_findFile(fs,filename,loc,&targetdir))return(0);
if(!dir_getFatFileName(filename,ffname))return(0);
if(dir_findinDir(fs,ffname,targetdir,loc,DIRFIND_FREE)){
return(1);
}else{
if(dir_addCluster(fs,targetdir)){
return(0);
}else{
if(dir_findinDir(fs,ffname,targetdir,loc,DIRFIND_FREE)){
return(1);
}
}
}
return(0);
}
/*****************************************************************************/
/* ****************************************************************************
* euint32 fs_getLastCluster(FileSystem *fs,ClusterChain *Cache)
* Description: This function searches the last cluster of a chain.
* Return value: The LastCluster (also stored in cache);
*/
euint32 fs_getLastCluster(FileSystem *fs,ClusterChain *Cache)
{
if(Cache->DiscCluster==0){
Cache->DiscCluster=Cache->FirstCluster;
Cache->LogicCluster=0;
}
if(Cache->LastCluster==0)
{
while(fat_getNextClusterChain(fs, Cache)==0)
{
Cache->LogicCluster+=Cache->Linear;
Cache->DiscCluster+=Cache->Linear;
Cache->Linear=0;
}
}
return(Cache->LastCluster);
}
/*****************************************************************************/
euint32 fs_getFirstClusterRootDir(FileSystem *fs)
{
if (fs->type == FAT32)
return fs->volumeId.RootCluster;
return 1;
}
/*****************************************************************************/
void fs_initClusterChain(FileSystem *fs,ClusterChain *cache,euint32 cluster_addr)
{
cache->FirstCluster=cluster_addr;
cache->DiscCluster=cluster_addr;
cache->LogicCluster=0;
cache->LastCluster=0; /* Warning flag here */
cache->Linear=0;
}
/*****************************************************************************/
void fs_setFirstClusterInDirEntry(FileRecord *rec,euint32 cluster_addr)
{
rec->FirstClusterHigh=cluster_addr>>16;
rec->FirstClusterLow=cluster_addr&0xFFFF;
}
/*****************************************************************************/
esint8 fs_flushFs(FileSystem *fs)
{
return(part_flushPart(fs->part,0,fs->SectorCount));
}
/*****************************************************************************/
esint8 fs_umount(FileSystem *fs)
{
return(fs_flushFs(fs));
}
/*****************************************************************************/
esint8 fs_clearCluster(FileSystem *fs,euint32 cluster)
{
euint16 c;
euint8* buf;
for(c=0;c<(fs->volumeId.SectorsPerCluster);c++){
buf = part_getSect(fs->part,fs_clusterToSector(fs,cluster)+c,IOM_MODE_READWRITE);
memClr(buf,512);
part_relSect(fs->part,buf);
}
return(0);
}
esint8 fs_getFsInfo(FileSystem *fs)
{
euint8 *buf;
if(!fs->type==FAT32)return(0);
buf = part_getSect(fs->part,FS_INFO_SECTOR,IOM_MODE_READONLY);
if(ex_getb32(buf+0)!=FSINFO_MAGIC_BEGIN || ex_getb32(buf+508)!=FSINFO_MAGIC_END){
part_relSect(fs->part,buf);
return(-1);
}
fs->FreeClusterCount = ex_getb32(buf+488);
fs->NextFreeCluster = ex_getb32(buf+492);
part_relSect(fs->part,buf);
return(0);
}
esint8 fs_setFsInfo(FileSystem *fs)
{
euint8* buf;
if(!fs->type==FAT32)return(0);
buf = part_getSect(fs->part,FS_INFO_SECTOR,IOM_MODE_READWRITE);
if(ex_getb32(buf+0)!=FSINFO_MAGIC_BEGIN || ex_getb32(buf+508)!=FSINFO_MAGIC_END){
part_relSect(fs->part,buf);
return(-1);
}
ex_setb32(buf+488,fs->FreeClusterCount);
ex_setb32(buf+492,fs->NextFreeCluster);
part_relSect(fs->part,buf);
return(0);
}

86
filesystem/dfs/filesystems/efsl/src/fs/vfat/include/dir.h Normal file
View File

@ -0,0 +1,86 @@
/*****************************************************************************\
* EFSL - Embedded Filesystems Library *
* ----------------------------------- *
* *
* Filename : dir.h *
* Release : 0.3 - devel *
* Description : The functions of dir.c are part of fs.c, they deal with all *
* the directory specific stuff. *
* *
* This program is free software; you can redistribute it and/or *
* modify it under the terms of the GNU General Public License *
* as published by the Free Software Foundation; version 2 *
* of the License. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* As a special exception, if other files instantiate templates or *
* use macros or inline functions from this file, or you compile this *
* file and link it with other works to produce a work based on this file, *
* this file does not by itself cause the resulting work to be covered *
* by the GNU General Public License. However the source code for this *
* file must still be made available in accordance with section (3) of *
* the GNU General Public License. *
* *
* This exception does not invalidate any other reasons why a work based *
* on this file might be covered by the GNU General Public License. *
* *
* (c)2006 Lennart Yseboodt *
* (c)2006 Michael De Nil *
\*****************************************************************************/
#ifndef __DDIR_H__
#define __DDIR_H__
/*****************************************************************************/
#include "config.h"
#include "error.h"
#include "fat.h"
#include "plibc.h"
#include "types.h"
// #include "ioman.h"
#include "tm.h"
#include "fs.h"
#include <dfs_cache.h>
/*****************************************************************************/
#define ATTR_READ_ONLY 0x01
#define ATTR_HIDDEN 0x02
#define ATTR_SYSTEM 0x04
#define ATTR_VOLUME_ID 0x08
#define ATTR_DIRECTORY 0x10
#define ATTR_ARCHIVE 0x20
#define OFFSET_DE_FILENAME 0
#define OFFSET_DE_ATTRIBUTE 11
#define OFFSET_DE_NTRESERVED 12
#define OFFSET_DE_CRTIMETNT 13
#define OFFSET_DE_CREATETIME 14
#define OFFSET_DE_CREATEDATE 16
#define OFFSET_DE_LASTACCESSDATE 18
#define OFFSET_DE_FIRSTCLUSTERHIGH 20
#define OFFSET_DE_WRITETIME 22
#define OFFSET_DE_WRITEDATE 24
#define OFFSET_DE_FIRSTCLUSTERLOW 26
#define OFFSET_DE_FILESIZE 28
#define DIRFIND_FILE 0
#define DIRFIND_FREE 1
void dir_getFileStructure(FileSystem *fs,FileRecord *filerec,FileLocation *loc);
void dir_createDirectoryEntry(FileSystem *fs,FileRecord *filerec,FileLocation *loc);
void dir_createDefaultEntry(FileSystem *fs,FileRecord *filerec,eint8* fatfilename);
void dir_setFirstCluster(FileSystem *fs,FileLocation *loc,euint32 cluster_addr);
void dir_setFileSize(FileSystem *fs,FileLocation *loc,euint32 numbytes);
euint32 dir_findinRoot(FileSystem *fs,eint8 * fatname, FileLocation *loc);
euint32 dir_findinDir(FileSystem *fs, eint8 * fatname, euint32 startCluster, FileLocation *loc, euint8 mode);
euint32 dir_findinBuf(euint8 *buf,eint8 *fatname, FileLocation *loc, euint8 mode);
euint32 dir_findinCluster(FileSystem *fs,euint32 cluster,eint8 *fatname, FileLocation *loc, euint8 mode);
euint32 dir_findinRootArea(FileSystem *fs,eint8* fatname, FileLocation *loc, euint8 mode);
esint8 dir_getFatFileName(eint8* filename, eint8* fatfilename);
esint8 dir_updateDirectoryEntry(FileSystem *fs,FileRecord *entry,FileLocation *loc);
esint8 dir_addCluster(FileSystem *fs,euint32 firstCluster);
#endif

64
filesystem/dfs/filesystems/efsl/src/fs/vfat/include/fat.h Normal file
View File

@ -0,0 +1,64 @@
/*****************************************************************************\
* EFSL - Embedded Filesystems Library *
* ----------------------------------- *
* *
* Filename : fat.h *
* Release : 0.3 - devel *
* Description : This file contains all the functions dealing with the FAT *
* in a Microsoft FAT filesystem. It belongs under fs.c *
* *
* This program is free software; you can redistribute it and/or *
* modify it under the terms of the GNU General Public License *
* as published by the Free Software Foundation; version 2 *
* of the License. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* As a special exception, if other files instantiate templates or *
* use macros or inline functions from this file, or you compile this *
* file and link it with other works to produce a work based on this file, *
* this file does not by itself cause the resulting work to be covered *
* by the GNU General Public License. However the source code for this *
* file must still be made available in accordance with section (3) of *
* the GNU General Public License. *
* *
* This exception does not invalidate any other reasons why a work based *
* on this file might be covered by the GNU General Public License. *
* *
* (c)2006 Lennart Yseboodt *
* (c)2006 Michael De Nil *
\*****************************************************************************/
#ifndef __FAT_H_
#define __FAT_H_
/*****************************************************************************/
#include "config.h"
#include "error.h"
#include "file.h"
#include "debug.h"
#include "types.h"
/*****************************************************************************/
euint32 fat_getSectorAddressFatEntry(FileSystem *fs,euint32 cluster_addr);
euint32 fat_getNextClusterAddress(FileSystem *fs, euint32 cluster_addr, euint16 *linear);
void fat_setNextClusterAddress(FileSystem *fs,euint32 cluster_addr,euint32 next_cluster_addr);
eint16 fat_isEocMarker(FileSystem *fs,euint32 fat_entry);
euint32 fat_giveEocMarker(FileSystem *fs);
euint32 fat_findClusterAddress(FileSystem *fs,euint32 cluster,euint32 offset, euint8 *linear);
euint32 fat_getNextClusterAddressWBuf(FileSystem *fs,euint32 cluster_addr, euint8 * buf);
void fat_setNextClusterAddressWBuf(FileSystem *fs,euint32 cluster_addr,euint32 next_cluster_addr,euint8 * buf);
esint16 fat_getNextClusterChain(FileSystem *fs, ClusterChain *Cache);
void fat_bogus(void);
esint16 fat_LogicToDiscCluster(FileSystem *fs, ClusterChain *Cache,euint32 logiccluster);
eint16 fat_allocClusterChain(FileSystem *fs,ClusterChain *Cache,euint32 num_clusters);
eint16 fat_unlinkClusterChain(FileSystem *fs,ClusterChain *Cache);
euint32 fat_countClustersInChain(FileSystem *fs,euint32 firstcluster);
euint32 fat_DiscToLogicCluster(FileSystem *fs,euint32 firstcluster,euint32 disccluster);
void fat_ShortnameToString(const euint8* src, eint8* nm);
#endif

100
filesystem/dfs/filesystems/efsl/src/fs/vfat/include/file.h Normal file
View File

@ -0,0 +1,100 @@
/*****************************************************************************\
* EFSL - Embedded Filesystems Library *
* ----------------------------------- *
* *
* Filename : file.h *
* Release : 0.3 - devel *
* Description : This file contains functions dealing with files such as: *
* fopen, fread and fwrite. *
* *
* This program is free software; you can redistribute it and/or *
* modify it under the terms of the GNU General Public License *
* as published by the Free Software Foundation; version 2 *
* of the License. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* As a special exception, if other files instantiate templates or *
* use macros or inline functions from this file, or you compile this *
* file and link it with other works to produce a work based on this file, *
* this file does not by itself cause the resulting work to be covered *
* by the GNU General Public License. However the source code for this *
* file must still be made available in accordance with section (3) of *
* the GNU General Public License. *
* *
* This exception does not invalidate any other reasons why a work based *
* on this file might be covered by the GNU General Public License. *
* *
* (c)2006 Lennart Yseboodt *
* (c)2006 Michael De Nil *
\*****************************************************************************/
#ifndef __FILE_H_
#define __FILE_H_
/*****************************************************************************/
#include "config.h"
#include "error.h"
#include "tm.h"
#include "fs.h"
#include "dir.h"
#include "plibc.h"
#include "debug.h"
#include "types.h"
#include "fat.h"
/*****************************************************************************/
/* Operation flags */
#define EFSL_O_RDONLY 0
#define EFSL_O_WRONLY 1
#define EFSL_O_RDWR 2
#define EFSL_O_APPEND 8
#define FILE_STATUS_OPEN 0
#define FILE_STATUS_WRITE 1
/*****************************************************************************\
* File
* ------
* FileRecord DirEntry Copy of the FileRecord for this file
* FileLocation Location Location of the direntry
* FileSystem *fs Pointer to the filesystem this file is on
* FileCache Cache Pointer to the cache object of the file
* euint8 FileStatus Contains bitfield regarding filestatus
* euint32 FilePtr Offsetpointer for fread/fwrite functions
* euint32 FileSize Working copy of the filesize, always use this,
it is more up to date than DirEntry->FileSize,
which is only updated when flushing to disc.
\*****************************************************************************/
struct _File{
FileRecord DirEntry;
FileLocation Location; /* Location in directory!! */
FileSystem *fs;
ClusterChain Cache;
euint8 FileStatus;
euint32 FilePtr;
euint32 FileSize;
euint32 ref_count; /* Descriptor reference count */
};
typedef struct _File File;
esint8 file_fopen(File *file, FileSystem *fs,eint8 *filename, eint32 mode);
esint8 file_fclose(File *file);
esint32 file_setpos(File *file,euint32 pos);
euint32 file_fread(File *file,euint32 offset, euint32 size,euint8 *buf);
euint32 file_read (File *file,euint32 size,euint8 *buf);
euint32 file_fwrite(File* file,euint32 offset,euint32 size,euint8* buf);
euint32 file_write (File* file,euint32 size,euint8* buf);
eint8* file_normalToFatName(eint8* filename,eint8* fatfilename);
euint8 file_validateChar(euint8 c);
void file_initFile(File *file, FileSystem *fs, FileLocation *loc);
eint16 file_allocClusterChain(File *file,euint32 num_clusters);
void file_setAttr(File* file,euint8 attribute,euint8 val);
euint8 file_getAttr(File* file,euint8 attribute);
euint32 file_requiredCluster(File *file,euint32 offset, euint32 size);
#endif

201
filesystem/dfs/filesystems/efsl/src/fs/vfat/include/fs.h Normal file
View File

@ -0,0 +1,201 @@
/*****************************************************************************\
* EFSL - Embedded Filesystems Library *
* ----------------------------------- *
* *
* Filename : fs.h *
* Release : 0.3 - devel *
* Description : These are general filesystem functions, supported by the *
* functions of dir.c and fat.c file.c uses these functions *
* heavily, but is not used by fs.c (not true anymore) *
* *
* This program is free software; you can redistribute it and/or *
* modify it under the terms of the GNU General Public License *
* as published by the Free Software Foundation; version 2 *
* of the License. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* As a special exception, if other files instantiate templates or *
* use macros or inline functions from this file, or you compile this *
* file and link it with other works to produce a work based on this file, *
* this file does not by itself cause the resulting work to be covered *
* by the GNU General Public License. However the source code for this *
* file must still be made available in accordance with section (3) of *
* the GNU General Public License. *
* *
* This exception does not invalidate any other reasons why a work based *
* on this file might be covered by the GNU General Public License. *
* *
* (c)2006 Lennart Yseboodt *
* (c)2006 Michael De Nil *
\*****************************************************************************/
#ifndef __FS_H_
#define __FS_H_
/*****************************************************************************/
#include "config.h"
#include "types.h"
#include "error.h"
#include "partition.h"
#include "debug.h"
#include "tm.h"
#include "extract.h"
/*****************************************************************************/
#define FAT12 1
#define FAT16 2
#define FAT32 3
#define FS_INFO_SECTOR 1
#define FSINFO_MAGIC_BEGIN 0x41615252
#define FSINFO_MAGIC_END 0xAA550000
/*****************************************************************************************\
VolumeId
------
* ushort BytesPerSector Must be 512 or shit happens.
* uchar SectorsPerCluster Must be multiple of 2 (1,2,4,8,16 or 32)
* ushort ReservedSectorCount Number of sectors after which the first FAT begins.
* uchar NumberOfFats Should be 2
* ushort RootEntryCount Number of filerecords the Rootdir can contain. NOT for FAT32
* ushort SectorCount16 Number of Sectors for 12/16 bit FAT
* ushort FatSectorCount16 Number of Sectors for 1 FAT on FAT12/16 bit FAT's
* ulong SectorCount32 Number of Sectors for 32 bit FAT
* ulong FatSectorCount32 Number of Sectors for 1 FAT on FAT32
* ulong RootCluster Clusternumber of the first cluster of the RootDir on FAT 32
This is NOT a complete volumeId copy, no direct I/O is possible.
\*****************************************************************************************/
struct _VolumeId{
euint16 BytesPerSector;
euint8 SectorsPerCluster;
euint16 ReservedSectorCount;
euint8 NumberOfFats;
euint16 RootEntryCount;
euint16 SectorCount16;
euint16 FatSectorCount16;
euint32 SectorCount32;
euint32 FatSectorCount32;
euint32 RootCluster;
};
typedef struct _VolumeId VolumeId;
/**************************************************************************************************\
FileSystem
--------
* Partition* part Pointer to partition on which this FS resides.
* VolumeId volumeId Contains important FS info.
* ulong DataClusterCount Number of dataclusters. This number determines the FATType.
* ulong FatSectorCount Number of sectors for 1 FAT, regardless of FATType
* ulong SectorCount Number of sectors, regardless of FATType
* ulong FirstSectorRootDir First sector of the RootDir.
* uchar type Determines FATType (FAT12 FAT16 or FAT32 are defined)
\**************************************************************************************************/
struct _FileSystem{
Partition *part;
VolumeId volumeId;
euint32 DataClusterCount;
euint32 FatSectorCount;
euint32 SectorCount;
euint32 FirstSectorRootDir;
euint32 FirstClusterCurrentDir;
euint32 FreeClusterCount;
euint32 NextFreeCluster;
euint8 type;
};
typedef struct _FileSystem FileSystem;
/**************************************************************************************************\
FileLocation
----------
* euint32 Sector Sector where the directoryentry of the file/directory can be found.
* euint8 Offset Offset (in 32byte segments) where in the sector the entry is.
\**************************************************************************************************/
struct _FileLocation{
euint32 Sector;
euint8 Offset;
euint8 attrib;
};
typedef struct _FileLocation FileLocation;
/*****************************************************************************\
* FileCache
* -----------
* This struct acts as cache for the current file. It contains the current
* FATPointer (next location in the FAT table), LogicCluster
* (the last part of the file that was read) and DataCluster
* (the last cluster that was read).
* euint8 Linear For how many more clusters the file is nonfragmented
* euint32 LogicCluster This field determines the n'th cluster of the file as current
* euint32 DiscCluster If this field is 0, it means the cache is invalid. Otherwise
it is the clusternumber corresponding with
logic(FirstCluster+LogicCluster).
* euint32 FirstCluster First cluster of the chain. Zero or one are invalid.
* euint32 LastCluster Last cluster of the chain (is not always filled in)
\*****************************************************************************/
struct _ClusterChain{
euint8 Linear;
esint32 LogicCluster;
euint32 DiscCluster;
euint32 FirstCluster;
euint32 LastCluster;
};
typedef struct _ClusterChain ClusterChain;
/*****************************************************************************\
* FileRecord *
* ------------ *
* This struct represents a 32 byte file entry as it occurs in the data area *
* of the filesystem. Direct I/O is possible. *
\*****************************************************************************/
struct _FileRecord{
euint8 FileName[11];
euint8 Attribute;
euint8 NTReserved;
euint8 MilliSecTimeStamp;
euint16 CreatedTime;
euint16 CreatedDate;
euint16 AccessDate;
euint16 FirstClusterHigh;
euint16 WriteTime;
euint16 WriteDate;
euint16 FirstClusterLow;
euint32 FileSize;
};
typedef struct _FileRecord FileRecord;
eint16 fs_initFs(FileSystem *fs,Partition *part);
eint16 fs_isValidFat(Partition *part);
void fs_loadVolumeId(FileSystem *fs, Partition *part);
esint16 fs_verifySanity(FileSystem *fs);
void fs_countDataSectors(FileSystem *fs);
void fs_determineFatType(FileSystem *fs);
void fs_findFirstSectorRootDir(FileSystem *fs);
void fs_initCurrentDir(FileSystem *fs);
euint32 fs_getSectorAddressRootDir(FileSystem *fs,euint32 secref);
euint32 fs_clusterToSector(FileSystem *fs,euint32 cluster);
euint32 fs_sectorToCluster(FileSystem *fs,euint32 sector);
euint32 fs_getNextFreeCluster(FileSystem *fs,euint32 startingcluster);
euint32 fs_giveFreeClusterHint(FileSystem *fs);
esint16 fs_findFreeFile(FileSystem *fs,eint8* filename,FileLocation *loc,euint8 mode);
esint8 fs_findFile(FileSystem *fs,eint8* filename,FileLocation *loc,euint32 *lastDir);
esint8 fs_findFile_broken(FileSystem *fs,eint8* filename,FileLocation *loc);
euint32 fs_getLastCluster(FileSystem *fs,ClusterChain *Cache);
euint32 fs_getFirstClusterRootDir(FileSystem *fs);
euint16 fs_makeDate(void);
euint16 fs_makeTime(void);
void fs_setFirstClusterInDirEntry(FileRecord *rec,euint32 cluster_addr);
void fs_initClusterChain(FileSystem *fs,ClusterChain *cache,euint32 cluster_addr);
esint8 fs_flushFs(FileSystem *fs);
esint8 fs_umount(FileSystem *fs);
esint8 fs_clearCluster(FileSystem *fs,euint32 cluster);
esint8 fs_getFsInfo(FileSystem *fs);
esint8 fs_setFsInfo(FileSystem *fs);
#endif

69
filesystem/dfs/filesystems/efsl/src/fs/vfat/include/ls.h Normal file
View File

@ -0,0 +1,69 @@
/*****************************************************************************\
* EFSL - Embedded Filesystems Library *
* ----------------------------------- *
* *
* Filename : ls.h *
* Release : 0.3 - devel *
* Description : This file contains functions to list the files in a directory *
* *
* This program is free software; you can redistribute it and/or *
* modify it under the terms of the GNU General Public License *
* as published by the Free Software Foundation; version 2 *
* of the License. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* As a special exception, if other files instantiate templates or *
* use macros or inline functions from this file, or you compile this *
* file and link it with other works to produce a work based on this file, *
* this file does not by itself cause the resulting work to be covered *
* by the GNU General Public License. However the source code for this *
* file must still be made available in accordance with section (3) of *
* the GNU General Public License. *
* *
* This exception does not invalidate any other reasons why a work based *
* on this file might be covered by the GNU General Public License. *
* *
* (c)2006 Lennart Yseboodt *
* (c)2006 Michael De Nil *
\*****************************************************************************/
#ifndef __LS_H__
#define __LS_H__
/*****************************************************************************/
#include "config.h"
#include "fs.h"
#include "dir.h"
#include "fat.h"
/*****************************************************************************/
struct _ListDirEntry{
euint8 FileName[LIST_MAXLENFILENAME];
euint32 FileSize;
euint8 Attribute;
};
typedef struct _ListDirEntry ListDirEntry;
struct _DirList{
FileSystem *fs;
euint16 cEntry,rEntry;
/*FileRecord currentEntry;*/
ListDirEntry currentEntry;
ClusterChain Cache;
};
typedef struct _DirList DirList;
esint8 ls_openDir(DirList *dlist,FileSystem *fs,eint8* dirname);
esint8 ls_getNext(DirList *dlist);
esint8 ls_getDirEntry(DirList *dlist);
esint8 ls_getRealDirEntry(DirList *dlist);
esint8 ls_getRootAreaEntry(DirList *dlist);
esint8 ls_isValidFileEntry(ListDirEntry *entry);
void ls_fileEntryToDirListEntry(DirList *dlist, euint8* buf, euint16 offset);
#endif

Some files were not shown because too many files have changed in this diff Show More