mirror of https://github.com/RT-Thread/rt-thread
bsp/stm32：Separate STM32WL HAL drivers (#10218)
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commit
c210588db9
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@ -98,6 +98,7 @@ config SOC_SERIES_STM32WL
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bool
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bool
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select ARCH_ARM_CORTEX_M4
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select ARCH_ARM_CORTEX_M4
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select SOC_FAMILY_STM32
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select SOC_FAMILY_STM32
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select PKG_USING_STM32WL_HAL_DRIVER
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config SOC_SERIES_STM32WB
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config SOC_SERIES_STM32WB
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bool
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bool
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@ -1,282 +0,0 @@
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/**
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******************************************************************************
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* @file stm32wlxx.h
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* @author MCD Application Team
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* @brief CMSIS STM32WLxx Device Peripheral Access Layer Header File.
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*
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* The file is the unique include file that the application programmer
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* is using in the C source code, usually in main.c. This file contains:
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* - Configuration section that allows to select:
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* - The STM32WLxx device used in the target application
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* - To use or not the peripheral’s drivers in application code(i.e.
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* code will be based on direct access to peripheral’s registers
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* rather than drivers API), this option is controlled by
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* "#define USE_HAL_DRIVER"
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*
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2020(-2021) STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup stm32wlxx
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* @{
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*/
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#ifndef __STM32WLxx_H
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#define __STM32WLxx_H
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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/** @addtogroup Library_configuration_section
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* @{
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*/
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/**
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* @brief STM32 Family
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*/
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#if !defined (STM32WL)
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#define STM32WL
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#endif /* STM32WL */
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/* Uncomment the line below according to the target STM32WL device used in your
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application
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*/
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#if !defined (STM32WL55xx) && !defined (STM32WL54xx) && !defined (STM32WLE5xx) && !defined (STM32WLE4xx)
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/* #define STM32WL55xx */ /*!< STM32WL55xx Devices */
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/* #define STM32WL54xx */ /*!< STM32WL54xx Devices */
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/* #define STM32WLE5xx */ /*!< STM32WLE5xx Devices */
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/* #define STM32WLE4xx */ /*!< STM32WLE4xx Devices */
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#endif
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/* Tip: To avoid modifying this file each time you need to switch between these
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devices, you can define the device in your toolchain compiler preprocessor.
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*/
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#if !defined (USE_HAL_DRIVER)
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/**
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* @brief Comment the line below if you will not use the peripherals drivers.
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In this case, these drivers will not be included and the application code will
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be based on direct access to peripherals registers
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*/
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/*#define USE_HAL_DRIVER */
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#endif /* USE_HAL_DRIVER */
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/**
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* @brief CMSIS Device version number
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*/
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#define __STM32WLxx_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */
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#define __STM32WLxx_CMSIS_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */
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#define __STM32WLxx_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
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#define __STM32WLxx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
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#define __STM32WLxx_CMSIS_DEVICE_VERSION ((__STM32WLxx_CMSIS_VERSION_MAIN << 24)\
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|(__STM32WLxx_CMSIS_VERSION_SUB1 << 16)\
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|(__STM32WLxx_CMSIS_VERSION_SUB2 << 8 )\
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|(__STM32WLxx_CMSIS_VERSION_RC))
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/**
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* @}
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*/
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/** @addtogroup Device_Included
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* @{
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*/
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#if defined(STM32WL55xx)
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#include "stm32wl55xx.h"
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#elif defined(STM32WLE5xx)
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#include "stm32wle5xx.h"
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#elif defined(STM32WL54xx)
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#include "stm32wl54xx.h"
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#elif defined(STM32WLE4xx)
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#include "stm32wle4xx.h"
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#else
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#error "Please select first the target STM32WLxx device used in your application, for instance xxx (in stm32wlxx.h file)"
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#endif
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/**
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* @}
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*/
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/** @addtogroup Exported_types
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* @{
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*/
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typedef enum
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{
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RESET = 0,
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SET = !RESET
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} FlagStatus, ITStatus;
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typedef enum
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{
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DISABLE = 0,
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ENABLE = !DISABLE
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} FunctionalState;
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#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
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typedef enum
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{
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ERROR = 0,
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SUCCESS = !ERROR
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} ErrorStatus;
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/**
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* @}
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*/
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/** @addtogroup Exported_macros
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* @{
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*/
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#define SET_BIT(REG, BIT) ((REG) |= (BIT))
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#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
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#define READ_BIT(REG, BIT) ((REG) & (BIT))
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#define CLEAR_REG(REG) ((REG) = (0x0))
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#define WRITE_REG(REG, VAL) ((REG) = (VAL))
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#define READ_REG(REG) ((REG))
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#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
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#if defined(CORE_CM0PLUS)
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/* Use of interrupt control for register exclusive access (privileged mode only) */
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/* Atomic 32-bit register access macro to set one or several bits */
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#define ATOMIC_SET_BIT(REG, BIT) \
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do { \
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uint32_t primask; \
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primask = __get_PRIMASK(); \
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__set_PRIMASK(1); \
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SET_BIT((REG), (BIT)); \
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__set_PRIMASK(primask); \
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} while(0)
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/* Atomic 32-bit register access macro to clear one or several bits */
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#define ATOMIC_CLEAR_BIT(REG, BIT) \
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do { \
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uint32_t primask; \
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primask = __get_PRIMASK(); \
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__set_PRIMASK(1); \
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CLEAR_BIT((REG), (BIT)); \
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__set_PRIMASK(primask); \
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} while(0)
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/* Atomic 32-bit register access macro to clear and set one or several bits */
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#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
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do { \
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uint32_t primask; \
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primask = __get_PRIMASK(); \
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__set_PRIMASK(1); \
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MODIFY_REG((REG), (CLEARMSK), (SETMASK)); \
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__set_PRIMASK(primask); \
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} while(0)
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/* Atomic 16-bit register access macro to set one or several bits */
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#define ATOMIC_SETH_BIT(REG, BIT) ATOMIC_SET_BIT(REG, BIT)
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/* Atomic 16-bit register access macro to clear one or several bits */
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#define ATOMIC_CLEARH_BIT(REG, BIT) ATOMIC_CLEAR_BIT(REG, BIT)
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/* Atomic 16-bit register access macro to clear and set one or several bits */
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#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK)
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#else
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/* Use of CMSIS compiler intrinsics for register exclusive access */
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/* Atomic 32-bit register access macro to set one or several bits */
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#define ATOMIC_SET_BIT(REG, BIT) \
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do { \
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uint32_t val; \
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do { \
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val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \
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} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
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} while(0)
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/* Atomic 32-bit register access macro to clear one or several bits */
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#define ATOMIC_CLEAR_BIT(REG, BIT) \
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do { \
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uint32_t val; \
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do { \
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val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \
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} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
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} while(0)
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/* Atomic 32-bit register access macro to clear and set one or several bits */
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#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
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do { \
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uint32_t val; \
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do { \
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val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
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} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
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} while(0)
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/* Atomic 16-bit register access macro to set one or several bits */
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#define ATOMIC_SETH_BIT(REG, BIT) \
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do { \
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uint16_t val; \
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do { \
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val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \
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} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
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} while(0)
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/* Atomic 16-bit register access macro to clear one or several bits */
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#define ATOMIC_CLEARH_BIT(REG, BIT) \
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do { \
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uint16_t val; \
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do { \
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val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \
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} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
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} while(0)
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/* Atomic 16-bit register access macro to clear and set one or several bits */
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#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \
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do { \
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uint16_t val; \
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do { \
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val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
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} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
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} while(0)
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#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
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#endif /* CORE_CM0PLUS */
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/**
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* @}
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*/
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#if defined (USE_HAL_DRIVER)
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#include "stm32wlxx_hal.h"
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#endif /* USE_HAL_DRIVER */
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* __STM32WLxx_H */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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@ -1,106 +0,0 @@
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/**
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******************************************************************************
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* @file system_stm32wlxx.h
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* @author MCD Application Team
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* @brief CMSIS Cortex Device System Source File for STM32WLxx devices.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2020(-2021) STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup stm32wlxx_system
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* @{
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*/
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/**
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* @brief Define to prevent recursive inclusion
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*/
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#ifndef __SYSTEM_STM32WLXX_H
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#define __SYSTEM_STM32WLXX_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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/** @addtogroup STM32WLxx_System_Includes
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32WLxx_System_Exported_types
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* @{
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*/
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/* The SystemCoreClock variable is updated in three ways:
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1) from within HAL_Init()
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2) by calling CMSIS function SystemCoreClockUpdate()
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3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
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*/
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extern uint32_t SystemCoreClock; /*!< System Clock Frequency */
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extern const uint32_t AHBPrescTable[16]; /*!< AHB prescalers table values */
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extern const uint32_t APBPrescTable[8]; /*!< APB prescalers table values */
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extern const uint32_t MSIRangeTable[16]; /*!< MSI ranges table values */
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/**
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* @}
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*/
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/** @addtogroup STM32WLxx_System_Exported_Constants
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32WLxx_System_Exported_Macros
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32WLxx_System_Exported_Functions
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* @{
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*/
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extern void SystemInit(void);
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extern void SystemCoreClockUpdate(void);
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /*__SYSTEM_STM32WLXX_H */
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/**
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* @}
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*/
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/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,97 +0,0 @@
|
||||||
<!DOCTYPE html>
|
|
||||||
<html xmlns="http://www.w3.org/1999/xhtml" lang="en" xml:lang="en">
|
|
||||||
<head>
|
|
||||||
<meta charset="utf-8" />
|
|
||||||
<meta name="generator" content="pandoc" />
|
|
||||||
<meta name="viewport" content="width=device-width, initial-scale=1.0, user-scalable=yes" />
|
|
||||||
<title>Release Notes for STM32WLxx CMSIS</title>
|
|
||||||
<style type="text/css">
|
|
||||||
code{white-space: pre-wrap;}
|
|
||||||
span.smallcaps{font-variant: small-caps;}
|
|
||||||
span.underline{text-decoration: underline;}
|
|
||||||
div.column{display: inline-block; vertical-align: top; width: 50%;}
|
|
||||||
</style>
|
|
||||||
<link rel="stylesheet" href="_htmresc/mini-st_2020.css" />
|
|
||||||
<!--[if lt IE 9]>
|
|
||||||
<script src="//cdnjs.cloudflare.com/ajax/libs/html5shiv/3.7.3/html5shiv-printshiv.min.js"></script>
|
|
||||||
<![endif]-->
|
|
||||||
<link rel="icon" type="image/x-icon" href="_htmresc/favicon.png" />
|
|
||||||
</head>
|
|
||||||
<body>
|
|
||||||
<div class="row">
|
|
||||||
<div class="col-sm-12 col-lg-4">
|
|
||||||
<center>
|
|
||||||
<h1 id="release-notes-for">Release Notes for</h1>
|
|
||||||
<h1 id="stm32wlxx-cmsis"><mark>STM32WLxx CMSIS</mark></h1>
|
|
||||||
<p>Copyright © 2020 STMicroelectronics<br />
|
|
||||||
</p>
|
|
||||||
<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo_2020.png" alt="ST logo" /></a>
|
|
||||||
</center>
|
|
||||||
<h1 id="purpose">Purpose</h1>
|
|
||||||
<p>This driver provides the CMSIS device for the stm32WLxx products. This covers</p>
|
|
||||||
<ul>
|
|
||||||
<li>STM32WL55xx devices</li>
|
|
||||||
<li>STM32WL54xx devices</li>
|
|
||||||
<li>STM32WLE5xx devices</li>
|
|
||||||
<li>STM32WLE4xx devices</li>
|
|
||||||
</ul>
|
|
||||||
<p>This driver is composed of the descriptions of the registers under “Include” directory.</p>
|
|
||||||
<p>Various template file are provided to easily build an application. They can be adapted to fit applications requirements.</p>
|
|
||||||
<ul>
|
|
||||||
<li>Templates/system_stm32WLxx.c contains the initialization code referred as SystemInit.</li>
|
|
||||||
<li>Startup files are provided as example for IAR©, KEIL© and STM32CubeIDE©.</li>
|
|
||||||
<li>Linker files are provided as example for IAR©, KEIL© and STM32CubeIDE©.</li>
|
|
||||||
</ul>
|
|
||||||
</div>
|
|
||||||
<div class="col-sm-12 col-lg-8">
|
|
||||||
<h1 id="update-history">Update History</h1>
|
|
||||||
<div class="collapse">
|
|
||||||
<input type="checkbox" id="collapse-section2" checked aria-hidden="true"> <label for="collapse-section2" aria-hidden="true"><strong>V1.1.0 / 16-June-2021</strong></label>
|
|
||||||
<div>
|
|
||||||
<h2 id="main-changes">Main Changes</h2>
|
|
||||||
<ul>
|
|
||||||
<li>Add atomic register access services:
|
|
||||||
<ul>
|
|
||||||
<li>32-bit register access: ATOMIC_SET_BIT(), ATOMIC_CLEAR_BIT(), ATOMIC_MODIFY_REG()</li>
|
|
||||||
<li>16-bit register access: ATOMIC_SETH_BIT(), ATOMIC_CLEARH_BIT(), ATOMIC_MODIFYH_BIT()</li>
|
|
||||||
</ul></li>
|
|
||||||
<li>Add define LSI_STARTUP_TIME used in default IWDG timeout calculation (HAL_IWDG_DEFAULT_TIMEOUT)</li>
|
|
||||||
<li>Add reference to user manual for customization of CubeIDE linker files</li>
|
|
||||||
</ul>
|
|
||||||
<h2 id="known-limitations">Known Limitations</h2>
|
|
||||||
<p>None</p>
|
|
||||||
<h2 id="dependencies">Dependencies</h2>
|
|
||||||
<p>None</p>
|
|
||||||
<h2 id="notes">Notes</h2>
|
|
||||||
<p>None</p>
|
|
||||||
</div>
|
|
||||||
</div>
|
|
||||||
<div class="collapse">
|
|
||||||
<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 / 28-October-2020</strong></label>
|
|
||||||
<div>
|
|
||||||
<h2 id="main-changes-1">Main Changes</h2>
|
|
||||||
<p><strong>First Official Release</strong></p>
|
|
||||||
<h2 id="contents">Contents</h2>
|
|
||||||
<p>First official release of CMSIS drivers for STM32WLxx lines</p>
|
|
||||||
<h2 id="known-limitations-1">Known Limitations</h2>
|
|
||||||
<p>None</p>
|
|
||||||
<h2 id="dependencies-1">Dependencies</h2>
|
|
||||||
<p>None</p>
|
|
||||||
<h2 id="notes-1">Notes</h2>
|
|
||||||
<p>None</p>
|
|
||||||
</div>
|
|
||||||
</div>
|
|
||||||
</div>
|
|
||||||
</div>
|
|
||||||
<footer class="sticky">
|
|
||||||
<div class="columns">
|
|
||||||
<div class="column" style="width:95%;">
|
|
||||||
<p>For complete documentation on STM32WLxx, visit: <a href="http://www.st.com/stm32wl">www.st.com/stm32wl</a></p>
|
|
||||||
<p><em>This release note uses up to date web standards and, for this reason, should not be opened with Internet Explorer but preferably with popular browsers such as Google Chrome, Mozilla Firefox, Opera or Microsoft Edge.</em></p>
|
|
||||||
</div><div class="column" style="width:5%;">
|
|
||||||
<p><abbr title="Based on template cx566953 version 2.0">Info</abbr></p>
|
|
||||||
</div>
|
|
||||||
</div>
|
|
||||||
</footer>
|
|
||||||
</body>
|
|
||||||
</html>
|
|
||||||
|
|
@ -1,19 +0,0 @@
|
||||||
; *************************************************************
|
|
||||||
; *** Scatter-Loading Description File generated by uVision ***
|
|
||||||
; *************************************************************
|
|
||||||
|
|
||||||
LR_IROM1 0x08020000 0x00020000 { ; load region size_region
|
|
||||||
; FLASH part dedicated to M0+
|
|
||||||
ER_IROM1 0x08020000 0x00020000 { ; load address = execution address
|
|
||||||
*.o (RESET, +First)
|
|
||||||
*(InRoot$$Sections)
|
|
||||||
.ANY (+RO)
|
|
||||||
}
|
|
||||||
; Non-backup SRAM1 dedicated to M0+
|
|
||||||
RW_IRAM1 0x20004000 0x00004000 { ; RW data
|
|
||||||
.ANY (+RW +ZI)
|
|
||||||
}
|
|
||||||
; Backup SRAM2 dedicated to M0+
|
|
||||||
RW_IRAM2 0x2000C000 EMPTY 0x00004000 { ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
@ -1,19 +0,0 @@
|
||||||
; *************************************************************
|
|
||||||
; *** Scatter-Loading Description File generated by uVision ***
|
|
||||||
; *************************************************************
|
|
||||||
|
|
||||||
LR_IROM1 0x08000000 0x00020000 { ; load region size_region
|
|
||||||
; FLASH part dedicated to M4
|
|
||||||
ER_IROM1 0x08000000 0x00020000 { ; load address = execution address
|
|
||||||
*.o (RESET, +First)
|
|
||||||
*(InRoot$$Sections)
|
|
||||||
.ANY (+RO)
|
|
||||||
}
|
|
||||||
; Non-backup SRAM1 dedicated to M4
|
|
||||||
RW_IRAM1 0x20000000 0x00004000 { ; RW data
|
|
||||||
.ANY (+RW +ZI)
|
|
||||||
}
|
|
||||||
; Backup SRAM2 dedicated to M4
|
|
||||||
RW_IRAM2 0x20008000 EMPTY 0x00004000 { ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
@ -1,19 +0,0 @@
|
||||||
; *************************************************************
|
|
||||||
; *** Scatter-Loading Description File generated by uVision ***
|
|
||||||
; *************************************************************
|
|
||||||
|
|
||||||
LR_IROM1 0x08020000 0x00020000 { ; load region size_region
|
|
||||||
; FLASH part dedicated to M0+
|
|
||||||
ER_IROM1 0x08020000 0x00020000 { ; load address = execution address
|
|
||||||
*.o (RESET, +First)
|
|
||||||
*(InRoot$$Sections)
|
|
||||||
.ANY (+RO)
|
|
||||||
}
|
|
||||||
; Non-backup SRAM1 dedicated to M0+
|
|
||||||
RW_IRAM1 0x20004000 0x00004000 { ; RW data
|
|
||||||
.ANY (+RW +ZI)
|
|
||||||
}
|
|
||||||
; Backup SRAM2 dedicated to M0+
|
|
||||||
RW_IRAM2 0x2000C000 EMPTY 0x00004000 { ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
@ -1,19 +0,0 @@
|
||||||
; *************************************************************
|
|
||||||
; *** Scatter-Loading Description File generated by uVision ***
|
|
||||||
; *************************************************************
|
|
||||||
|
|
||||||
LR_IROM1 0x08000000 0x00020000 { ; load region size_region
|
|
||||||
; FLASH part dedicated to M4
|
|
||||||
ER_IROM1 0x08000000 0x00020000 { ; load address = execution address
|
|
||||||
*.o (RESET, +First)
|
|
||||||
*(InRoot$$Sections)
|
|
||||||
.ANY (+RO)
|
|
||||||
}
|
|
||||||
; Non-backup SRAM1 dedicated to M4
|
|
||||||
RW_IRAM1 0x20000000 0x00004000 { ; RW data
|
|
||||||
.ANY (+RW +ZI)
|
|
||||||
}
|
|
||||||
; Backup SRAM2 dedicated to M4
|
|
||||||
RW_IRAM2 0x20008000 EMPTY 0x00004000 { ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
@ -1,19 +0,0 @@
|
||||||
; *************************************************************
|
|
||||||
; *** Scatter-Loading Description File generated by uVision ***
|
|
||||||
; *************************************************************
|
|
||||||
|
|
||||||
LR_IROM1 0x08000000 0x00040000 { ; load region size_region
|
|
||||||
; FLASH
|
|
||||||
ER_IROM1 0x08000000 0x00040000 { ; load address = execution address
|
|
||||||
*.o (RESET, +First)
|
|
||||||
*(InRoot$$Sections)
|
|
||||||
.ANY (+RO)
|
|
||||||
}
|
|
||||||
; Non-backup SRAM1
|
|
||||||
RW_IRAM1 0x20000000 0x00008000 { ; RW data
|
|
||||||
.ANY (+RW +ZI)
|
|
||||||
}
|
|
||||||
; Backup SRAM2
|
|
||||||
RW_IRAM2 0x20008000 EMPTY 0x00008000 { ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
@ -1,19 +0,0 @@
|
||||||
; *************************************************************
|
|
||||||
; *** Scatter-Loading Description File generated by uVision ***
|
|
||||||
; *************************************************************
|
|
||||||
|
|
||||||
LR_IROM1 0x08000000 0x00040000 { ; load region size_region
|
|
||||||
; FLASH
|
|
||||||
ER_IROM1 0x08000000 0x00040000 { ; load address = execution address
|
|
||||||
*.o (RESET, +First)
|
|
||||||
*(InRoot$$Sections)
|
|
||||||
.ANY (+RO)
|
|
||||||
}
|
|
||||||
; Non-backup SRAM1
|
|
||||||
RW_IRAM1 0x20000000 0x00008000 { ; RW data
|
|
||||||
.ANY (+RW +ZI)
|
|
||||||
}
|
|
||||||
; Backup SRAM2
|
|
||||||
RW_IRAM2 0x20008000 EMPTY 0x00008000 { ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
@ -1,253 +0,0 @@
|
||||||
;******************************************************************************
|
|
||||||
;* File Name : startup_stm32wl54xx_cm0plus.s
|
|
||||||
;* Author : MCD Application Team
|
|
||||||
;* Description : STM32WL54xx devices vector table for MDK-ARM toolchain.
|
|
||||||
;* This module performs:
|
|
||||||
;* - Set the initial SP
|
|
||||||
;* - Set the initial PC == Reset_Handler
|
|
||||||
;* - Set the vector table entries with the exceptions ISR address
|
|
||||||
;* - Branches to __main in the C library (which eventually
|
|
||||||
;* calls main()).
|
|
||||||
;* After Reset the Cortex-M0+ processor is in Thread mode,
|
|
||||||
;* priority is Privileged, and the Stack is set to Main.
|
|
||||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
|
||||||
;******************************************************************************
|
|
||||||
;* @attention
|
|
||||||
;*
|
|
||||||
;* Copyright (c) 2020(2021) STMicroelectronics.
|
|
||||||
;* All rights reserved.
|
|
||||||
;*
|
|
||||||
;* This software is licensed under terms that can be found in the LICENSE file
|
|
||||||
;* in the root directory of this software component.
|
|
||||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
|
||||||
;*
|
|
||||||
;******************************************************************************
|
|
||||||
|
|
||||||
; Amount of memory (in bytes) allocated for Stack
|
|
||||||
; Tailor this value to your application needs
|
|
||||||
; <h> Stack Configuration
|
|
||||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
|
||||||
; </h>
|
|
||||||
|
|
||||||
Stack_Size EQU 0x00000400
|
|
||||||
|
|
||||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
|
||||||
Stack_Mem SPACE Stack_Size
|
|
||||||
__initial_sp
|
|
||||||
|
|
||||||
|
|
||||||
; <h> Heap Configuration
|
|
||||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
|
||||||
; </h>
|
|
||||||
|
|
||||||
Heap_Size EQU 0x00000000
|
|
||||||
|
|
||||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
|
||||||
__heap_base
|
|
||||||
Heap_Mem SPACE Heap_Size
|
|
||||||
__heap_limit
|
|
||||||
|
|
||||||
PRESERVE8
|
|
||||||
THUMB
|
|
||||||
|
|
||||||
|
|
||||||
; Vector Table Mapped to Address 0 at Reset
|
|
||||||
AREA RESET, DATA, READONLY
|
|
||||||
EXPORT __Vectors
|
|
||||||
EXPORT __Vectors_End
|
|
||||||
EXPORT __Vectors_Size
|
|
||||||
|
|
||||||
__Vectors DCD __initial_sp ; Top of Stack
|
|
||||||
DCD Reset_Handler ; Reset Handler
|
|
||||||
DCD NMI_Handler ; NMI Handler
|
|
||||||
DCD HardFault_Handler ; Hard Fault Handler
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD SVC_Handler ; SVCall Handler
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD PendSV_Handler ; PendSV Handler
|
|
||||||
DCD SysTick_Handler ; SysTick Handler
|
|
||||||
|
|
||||||
; External Interrupts
|
|
||||||
DCD TZIC_ILA_IRQHandler ; Security Interrupt controller illegal access Interrupts
|
|
||||||
DCD PVD_PVM_IRQHandler ; PVD and PVM detector
|
|
||||||
DCD RTC_LSECSS_IRQHandler ; RTC Wakeup + RTC Tamper and TimeStamp + RTC Alarms (A & B) + SSR Underflow and LSECSS Interrupts
|
|
||||||
DCD RCC_FLASH_C1SEV_IRQHandler ; RCC1 and FLASH and CPU1 M4 SEV Interrupts
|
|
||||||
DCD EXTI1_0_IRQHandler ; EXTI Line 1:0 Interrupts
|
|
||||||
DCD EXTI3_2_IRQHandler ; XTI Line 3:2 Interrupts
|
|
||||||
DCD EXTI15_4_IRQHandler ; EXTI Line 15:4 interrupts
|
|
||||||
DCD ADC_COMP_DAC_IRQHandler ; ADC, COMP1, COMP2, DAC Interrupts
|
|
||||||
DCD DMA1_Channel1_2_3_IRQHandler ; DMA1 Channel 1 to 3 Interrupts
|
|
||||||
DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channels 4, 5, 6, 7 Interrupts
|
|
||||||
DCD DMA2_DMAMUX1_OVR_IRQHandler ; DMA2 Channels[1..7] and DMAMUX Overrun Interrupts
|
|
||||||
DCD LPTIM1_IRQHandler ; LPTIM1 global Interrupt
|
|
||||||
DCD LPTIM2_IRQHandler ; LPTIM2 global Interrupt
|
|
||||||
DCD LPTIM3_IRQHandler ; LPTIM3 global Interrupt
|
|
||||||
DCD TIM1_IRQHandler ; TIM1 Interrupt
|
|
||||||
DCD TIM2_IRQHandler ; TIM2 Interrupt
|
|
||||||
DCD TIM16_IRQHandler ; TIM16 Interrupt
|
|
||||||
DCD TIM17_IRQHandler ; TIM17 Interrupt
|
|
||||||
DCD IPCC_C2_RX_C2_TX_IRQHandler ; IPCC RX Occupied and TX Free Interrupt Interrupts
|
|
||||||
DCD HSEM_IRQHandler ; Semaphore Interrupt
|
|
||||||
DCD RNG_IRQHandler ; RNG Interrupt
|
|
||||||
DCD AES_PKA_IRQHandler ; AES and PKA Interrupts
|
|
||||||
DCD I2C1_IRQHandler ; I2C1 Event and Error Interrupt
|
|
||||||
DCD I2C2_IRQHandler ; I2C2 Event and Error Interrupt
|
|
||||||
DCD I2C3_IRQHandler ; I2C3 Event and Error Interrupt
|
|
||||||
DCD SPI1_IRQHandler ; SPI1 Interrupts
|
|
||||||
DCD SPI2_IRQHandler ; SPI2 Interrupt
|
|
||||||
DCD USART1_IRQHandler ; USART1 Interrupt
|
|
||||||
DCD USART2_IRQHandler ; USART2 Interrupt
|
|
||||||
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
|
|
||||||
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
|
|
||||||
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
|
|
||||||
__Vectors_End
|
|
||||||
|
|
||||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
|
||||||
|
|
||||||
AREA |.text|, CODE, READONLY
|
|
||||||
|
|
||||||
; Reset handler
|
|
||||||
Reset_Handler PROC
|
|
||||||
EXPORT Reset_Handler [WEAK]
|
|
||||||
IMPORT SystemInit
|
|
||||||
IMPORT __main
|
|
||||||
|
|
||||||
LDR R0, =SystemInit
|
|
||||||
BLX R0
|
|
||||||
LDR R0, =__main
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
|
||||||
|
|
||||||
NMI_Handler PROC
|
|
||||||
EXPORT NMI_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
HardFault_Handler\
|
|
||||||
PROC
|
|
||||||
EXPORT HardFault_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
SVC_Handler PROC
|
|
||||||
EXPORT SVC_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
PendSV_Handler PROC
|
|
||||||
EXPORT PendSV_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
SysTick_Handler PROC
|
|
||||||
EXPORT SysTick_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
Default_Handler PROC
|
|
||||||
EXPORT TZIC_ILA_IRQHandler [WEAK]
|
|
||||||
EXPORT PVD_PVM_IRQHandler [WEAK]
|
|
||||||
EXPORT RTC_LSECSS_IRQHandler [WEAK]
|
|
||||||
EXPORT RCC_FLASH_C1SEV_IRQHandler [WEAK]
|
|
||||||
EXPORT EXTI1_0_IRQHandler [WEAK]
|
|
||||||
EXPORT EXTI3_2_IRQHandler [WEAK]
|
|
||||||
EXPORT EXTI15_4_IRQHandler [WEAK]
|
|
||||||
EXPORT ADC_COMP_DAC_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA1_Channel1_2_3_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA1_Channel4_5_6_7_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA2_DMAMUX1_OVR_IRQHandler [WEAK]
|
|
||||||
EXPORT LPTIM1_IRQHandler [WEAK]
|
|
||||||
EXPORT LPTIM2_IRQHandler [WEAK]
|
|
||||||
EXPORT LPTIM3_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM1_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM2_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM16_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM17_IRQHandler [WEAK]
|
|
||||||
EXPORT IPCC_C2_RX_C2_TX_IRQHandler [WEAK]
|
|
||||||
EXPORT HSEM_IRQHandler [WEAK]
|
|
||||||
EXPORT RNG_IRQHandler [WEAK]
|
|
||||||
EXPORT AES_PKA_IRQHandler [WEAK]
|
|
||||||
EXPORT I2C1_IRQHandler [WEAK]
|
|
||||||
EXPORT I2C2_IRQHandler [WEAK]
|
|
||||||
EXPORT I2C3_IRQHandler [WEAK]
|
|
||||||
EXPORT SPI1_IRQHandler [WEAK]
|
|
||||||
EXPORT SPI2_IRQHandler [WEAK]
|
|
||||||
EXPORT USART1_IRQHandler [WEAK]
|
|
||||||
EXPORT USART2_IRQHandler [WEAK]
|
|
||||||
EXPORT LPUART1_IRQHandler [WEAK]
|
|
||||||
EXPORT SUBGHZSPI_IRQHandler [WEAK]
|
|
||||||
EXPORT SUBGHZ_Radio_IRQHandler [WEAK]
|
|
||||||
|
|
||||||
TZIC_ILA_IRQHandler
|
|
||||||
PVD_PVM_IRQHandler
|
|
||||||
RTC_LSECSS_IRQHandler
|
|
||||||
RCC_FLASH_C1SEV_IRQHandler
|
|
||||||
EXTI1_0_IRQHandler
|
|
||||||
EXTI3_2_IRQHandler
|
|
||||||
EXTI15_4_IRQHandler
|
|
||||||
ADC_COMP_DAC_IRQHandler
|
|
||||||
DMA1_Channel1_2_3_IRQHandler
|
|
||||||
DMA1_Channel4_5_6_7_IRQHandler
|
|
||||||
DMA2_DMAMUX1_OVR_IRQHandler
|
|
||||||
LPTIM1_IRQHandler
|
|
||||||
LPTIM2_IRQHandler
|
|
||||||
LPTIM3_IRQHandler
|
|
||||||
TIM1_IRQHandler
|
|
||||||
TIM2_IRQHandler
|
|
||||||
TIM16_IRQHandler
|
|
||||||
TIM17_IRQHandler
|
|
||||||
IPCC_C2_RX_C2_TX_IRQHandler
|
|
||||||
HSEM_IRQHandler
|
|
||||||
RNG_IRQHandler
|
|
||||||
AES_PKA_IRQHandler
|
|
||||||
I2C1_IRQHandler
|
|
||||||
I2C2_IRQHandler
|
|
||||||
I2C3_IRQHandler
|
|
||||||
SPI1_IRQHandler
|
|
||||||
SPI2_IRQHandler
|
|
||||||
USART1_IRQHandler
|
|
||||||
USART2_IRQHandler
|
|
||||||
LPUART1_IRQHandler
|
|
||||||
SUBGHZSPI_IRQHandler
|
|
||||||
SUBGHZ_Radio_IRQHandler
|
|
||||||
|
|
||||||
B .
|
|
||||||
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
ALIGN
|
|
||||||
|
|
||||||
;*******************************************************************************
|
|
||||||
; User Stack and Heap initialization
|
|
||||||
;*******************************************************************************
|
|
||||||
IF :DEF:__MICROLIB
|
|
||||||
|
|
||||||
EXPORT __initial_sp
|
|
||||||
EXPORT __heap_base
|
|
||||||
EXPORT __heap_limit
|
|
||||||
|
|
||||||
ELSE
|
|
||||||
|
|
||||||
IMPORT __use_two_region_memory
|
|
||||||
EXPORT __user_initial_stackheap
|
|
||||||
|
|
||||||
__user_initial_stackheap
|
|
||||||
|
|
||||||
LDR R0, = Heap_Mem
|
|
||||||
LDR R1, =(Stack_Mem + Stack_Size)
|
|
||||||
LDR R2, = (Heap_Mem + Heap_Size)
|
|
||||||
LDR R3, = Stack_Mem
|
|
||||||
BX LR
|
|
||||||
|
|
||||||
ALIGN
|
|
||||||
|
|
||||||
ENDIF
|
|
||||||
|
|
||||||
END
|
|
||||||
|
|
||||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
|
||||||
|
|
@ -1,365 +0,0 @@
|
||||||
;******************************************************************************
|
|
||||||
;* File Name : startup_stm32wl54xx_cm4.s
|
|
||||||
;* Author : MCD Application Team
|
|
||||||
;* Description : STM32WL54xx devices vector table for MDK-ARM toolchain.
|
|
||||||
;* This module performs:
|
|
||||||
;* - Set the initial SP
|
|
||||||
;* - Set the initial PC == Reset_Handler
|
|
||||||
;* - Set the vector table entries with the exceptions ISR address
|
|
||||||
;* - Branches to __main in the C library (which eventually
|
|
||||||
;* calls main()).
|
|
||||||
;* After Reset the CortexM4 processor is in Thread mode,
|
|
||||||
;* priority is Privileged, and the Stack is set to Main.
|
|
||||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
|
||||||
;******************************************************************************
|
|
||||||
;* @attention
|
|
||||||
;*
|
|
||||||
;* Copyright (c) 2020(2021) STMicroelectronics.
|
|
||||||
;* All rights reserved.
|
|
||||||
;*
|
|
||||||
;* This software is licensed under terms that can be found in the LICENSE file
|
|
||||||
;* in the root directory of this software component.
|
|
||||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
|
||||||
;*
|
|
||||||
;******************************************************************************
|
|
||||||
|
|
||||||
; Amount of memory (in bytes) allocated for Stack
|
|
||||||
; Tailor this value to your application needs
|
|
||||||
; <h> Stack Configuration
|
|
||||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
|
||||||
; </h>
|
|
||||||
|
|
||||||
Stack_Size EQU 0x00000400
|
|
||||||
|
|
||||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
|
||||||
Stack_Mem SPACE Stack_Size
|
|
||||||
__initial_sp
|
|
||||||
|
|
||||||
|
|
||||||
; <h> Heap Configuration
|
|
||||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
|
||||||
; </h>
|
|
||||||
|
|
||||||
Heap_Size EQU 0x00000000
|
|
||||||
|
|
||||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
|
||||||
__heap_base
|
|
||||||
Heap_Mem SPACE Heap_Size
|
|
||||||
__heap_limit
|
|
||||||
|
|
||||||
PRESERVE8
|
|
||||||
THUMB
|
|
||||||
|
|
||||||
|
|
||||||
; Vector Table Mapped to Address 0 at Reset
|
|
||||||
AREA RESET, DATA, READONLY
|
|
||||||
EXPORT __Vectors
|
|
||||||
EXPORT __Vectors_End
|
|
||||||
EXPORT __Vectors_Size
|
|
||||||
|
|
||||||
__Vectors DCD __initial_sp ; Top of Stack
|
|
||||||
DCD Reset_Handler ; Reset Handler
|
|
||||||
DCD NMI_Handler ; NMI Handler
|
|
||||||
DCD HardFault_Handler ; Hard Fault Handler
|
|
||||||
DCD MemManage_Handler ; MPU Fault Handler
|
|
||||||
DCD BusFault_Handler ; Bus Fault Handler
|
|
||||||
DCD UsageFault_Handler ; Usage Fault Handler
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD SVC_Handler ; SVCall Handler
|
|
||||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD PendSV_Handler ; PendSV Handler
|
|
||||||
DCD SysTick_Handler ; SysTick Handler
|
|
||||||
|
|
||||||
; External Interrupts
|
|
||||||
DCD WWDG_IRQHandler ; Window WatchDog
|
|
||||||
DCD PVD_PVM_IRQHandler ; PVD and PVM detector
|
|
||||||
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSR Underflow Interrupts
|
|
||||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
|
|
||||||
DCD FLASH_IRQHandler ; FLASH global Interrupt
|
|
||||||
DCD RCC_IRQHandler ; RCC Interrupt
|
|
||||||
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
|
|
||||||
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
|
|
||||||
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
|
|
||||||
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup
|
|
||||||
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
|
|
||||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
|
|
||||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
|
|
||||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
|
|
||||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
|
|
||||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
|
|
||||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
|
|
||||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
|
|
||||||
DCD ADC_IRQHandler ; ADC Interrupt
|
|
||||||
DCD DAC_IRQHandler ; DAC Interrupt
|
|
||||||
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV and PWR CPU M0+ HOLD wakeup Interrupt
|
|
||||||
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
|
|
||||||
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
|
|
||||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
|
|
||||||
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupts
|
|
||||||
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
|
|
||||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
|
|
||||||
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
|
|
||||||
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
|
|
||||||
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
|
|
||||||
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
|
|
||||||
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
|
|
||||||
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
|
|
||||||
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
|
|
||||||
DCD SPI1_IRQHandler ; SPI1 Interrupt
|
|
||||||
DCD SPI2_IRQHandler ; SPI2 Interrupt
|
|
||||||
DCD USART1_IRQHandler ; USART1 Interrupt
|
|
||||||
DCD USART2_IRQHandler ; USART2 Interrupt
|
|
||||||
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
|
|
||||||
DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
|
|
||||||
DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
|
|
||||||
DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
|
|
||||||
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
|
|
||||||
DCD LPTIM3_IRQHandler ; LPTIM3 Interrupt
|
|
||||||
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
|
|
||||||
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
|
|
||||||
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
|
|
||||||
DCD HSEM_IRQHandler ; HSEM0 Interrupt
|
|
||||||
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
|
|
||||||
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
|
|
||||||
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
|
|
||||||
DCD AES_IRQHandler ; AES Interrupt
|
|
||||||
DCD RNG_IRQHandler ; RNG1 Interrupt
|
|
||||||
DCD PKA_IRQHandler ; PKA Interrupt
|
|
||||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
|
|
||||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
|
|
||||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
|
|
||||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
|
|
||||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
|
|
||||||
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
|
|
||||||
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
|
|
||||||
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
|
|
||||||
|
|
||||||
__Vectors_End
|
|
||||||
|
|
||||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
|
||||||
|
|
||||||
AREA |.text|, CODE, READONLY
|
|
||||||
|
|
||||||
; Reset handler
|
|
||||||
Reset_Handler PROC
|
|
||||||
EXPORT Reset_Handler [WEAK]
|
|
||||||
IMPORT SystemInit
|
|
||||||
IMPORT __main
|
|
||||||
|
|
||||||
LDR R0, =SystemInit
|
|
||||||
BLX R0
|
|
||||||
LDR R0, =__main
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
|
||||||
|
|
||||||
NMI_Handler PROC
|
|
||||||
EXPORT NMI_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
HardFault_Handler\
|
|
||||||
PROC
|
|
||||||
EXPORT HardFault_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
MemManage_Handler\
|
|
||||||
PROC
|
|
||||||
EXPORT MemManage_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
BusFault_Handler\
|
|
||||||
PROC
|
|
||||||
EXPORT BusFault_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
UsageFault_Handler\
|
|
||||||
PROC
|
|
||||||
EXPORT UsageFault_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
SVC_Handler PROC
|
|
||||||
EXPORT SVC_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
DebugMon_Handler\
|
|
||||||
PROC
|
|
||||||
EXPORT DebugMon_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
PendSV_Handler PROC
|
|
||||||
EXPORT PendSV_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
SysTick_Handler PROC
|
|
||||||
EXPORT SysTick_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
Default_Handler PROC
|
|
||||||
|
|
||||||
EXPORT WWDG_IRQHandler [WEAK]
|
|
||||||
EXPORT PVD_PVM_IRQHandler [WEAK]
|
|
||||||
EXPORT TAMP_STAMP_LSECSS_SSRU_IRQHandler [WEAK]
|
|
||||||
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
|
||||||
EXPORT FLASH_IRQHandler [WEAK]
|
|
||||||
EXPORT RCC_IRQHandler [WEAK]
|
|
||||||
EXPORT EXTI0_IRQHandler [WEAK]
|
|
||||||
EXPORT EXTI1_IRQHandler [WEAK]
|
|
||||||
EXPORT EXTI2_IRQHandler [WEAK]
|
|
||||||
EXPORT EXTI3_IRQHandler [WEAK]
|
|
||||||
EXPORT EXTI4_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
|
||||||
EXPORT ADC_IRQHandler [WEAK]
|
|
||||||
EXPORT DAC_IRQHandler [WEAK]
|
|
||||||
EXPORT C2SEV_PWR_C2H_IRQHandler [WEAK]
|
|
||||||
EXPORT COMP_IRQHandler [WEAK]
|
|
||||||
EXPORT EXTI9_5_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM1_BRK_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM1_UP_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM1_CC_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM2_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM16_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM17_IRQHandler [WEAK]
|
|
||||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
|
||||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
|
||||||
EXPORT I2C2_EV_IRQHandler [WEAK]
|
|
||||||
EXPORT I2C2_ER_IRQHandler [WEAK]
|
|
||||||
EXPORT SPI1_IRQHandler [WEAK]
|
|
||||||
EXPORT SPI2_IRQHandler [WEAK]
|
|
||||||
EXPORT USART1_IRQHandler [WEAK]
|
|
||||||
EXPORT USART2_IRQHandler [WEAK]
|
|
||||||
EXPORT LPUART1_IRQHandler [WEAK]
|
|
||||||
EXPORT LPTIM1_IRQHandler [WEAK]
|
|
||||||
EXPORT LPTIM2_IRQHandler [WEAK]
|
|
||||||
EXPORT EXTI15_10_IRQHandler [WEAK]
|
|
||||||
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
|
||||||
EXPORT LPTIM3_IRQHandler [WEAK]
|
|
||||||
EXPORT SUBGHZSPI_IRQHandler [WEAK]
|
|
||||||
EXPORT IPCC_C1_RX_IRQHandler [WEAK]
|
|
||||||
EXPORT IPCC_C1_TX_IRQHandler [WEAK]
|
|
||||||
EXPORT HSEM_IRQHandler [WEAK]
|
|
||||||
EXPORT I2C3_EV_IRQHandler [WEAK]
|
|
||||||
EXPORT I2C3_ER_IRQHandler [WEAK]
|
|
||||||
EXPORT SUBGHZ_Radio_IRQHandler [WEAK]
|
|
||||||
EXPORT AES_IRQHandler [WEAK]
|
|
||||||
EXPORT RNG_IRQHandler [WEAK]
|
|
||||||
EXPORT PKA_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA2_Channel1_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA2_Channel2_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA2_Channel3_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA2_Channel4_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA2_Channel5_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA2_Channel6_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA2_Channel7_IRQHandler [WEAK]
|
|
||||||
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
|
|
||||||
|
|
||||||
WWDG_IRQHandler
|
|
||||||
PVD_PVM_IRQHandler
|
|
||||||
TAMP_STAMP_LSECSS_SSRU_IRQHandler
|
|
||||||
RTC_WKUP_IRQHandler
|
|
||||||
FLASH_IRQHandler
|
|
||||||
RCC_IRQHandler
|
|
||||||
EXTI0_IRQHandler
|
|
||||||
EXTI1_IRQHandler
|
|
||||||
EXTI2_IRQHandler
|
|
||||||
EXTI3_IRQHandler
|
|
||||||
EXTI4_IRQHandler
|
|
||||||
DMA1_Channel1_IRQHandler
|
|
||||||
DMA1_Channel2_IRQHandler
|
|
||||||
DMA1_Channel3_IRQHandler
|
|
||||||
DMA1_Channel4_IRQHandler
|
|
||||||
DMA1_Channel5_IRQHandler
|
|
||||||
DMA1_Channel6_IRQHandler
|
|
||||||
DMA1_Channel7_IRQHandler
|
|
||||||
ADC_IRQHandler
|
|
||||||
DAC_IRQHandler
|
|
||||||
C2SEV_PWR_C2H_IRQHandler
|
|
||||||
COMP_IRQHandler
|
|
||||||
EXTI9_5_IRQHandler
|
|
||||||
TIM1_BRK_IRQHandler
|
|
||||||
TIM1_UP_IRQHandler
|
|
||||||
TIM1_TRG_COM_IRQHandler
|
|
||||||
TIM1_CC_IRQHandler
|
|
||||||
TIM2_IRQHandler
|
|
||||||
TIM16_IRQHandler
|
|
||||||
TIM17_IRQHandler
|
|
||||||
I2C1_EV_IRQHandler
|
|
||||||
I2C1_ER_IRQHandler
|
|
||||||
I2C2_EV_IRQHandler
|
|
||||||
I2C2_ER_IRQHandler
|
|
||||||
SPI1_IRQHandler
|
|
||||||
SPI2_IRQHandler
|
|
||||||
USART1_IRQHandler
|
|
||||||
USART2_IRQHandler
|
|
||||||
LPUART1_IRQHandler
|
|
||||||
LPTIM1_IRQHandler
|
|
||||||
LPTIM2_IRQHandler
|
|
||||||
EXTI15_10_IRQHandler
|
|
||||||
RTC_Alarm_IRQHandler
|
|
||||||
LPTIM3_IRQHandler
|
|
||||||
SUBGHZSPI_IRQHandler
|
|
||||||
IPCC_C1_RX_IRQHandler
|
|
||||||
IPCC_C1_TX_IRQHandler
|
|
||||||
HSEM_IRQHandler
|
|
||||||
I2C3_EV_IRQHandler
|
|
||||||
I2C3_ER_IRQHandler
|
|
||||||
SUBGHZ_Radio_IRQHandler
|
|
||||||
AES_IRQHandler
|
|
||||||
RNG_IRQHandler
|
|
||||||
PKA_IRQHandler
|
|
||||||
DMA2_Channel1_IRQHandler
|
|
||||||
DMA2_Channel2_IRQHandler
|
|
||||||
DMA2_Channel3_IRQHandler
|
|
||||||
DMA2_Channel4_IRQHandler
|
|
||||||
DMA2_Channel5_IRQHandler
|
|
||||||
DMA2_Channel6_IRQHandler
|
|
||||||
DMA2_Channel7_IRQHandler
|
|
||||||
DMAMUX1_OVR_IRQHandler
|
|
||||||
|
|
||||||
B .
|
|
||||||
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
ALIGN
|
|
||||||
|
|
||||||
;*******************************************************************************
|
|
||||||
; User Stack and Heap initialization
|
|
||||||
;*******************************************************************************
|
|
||||||
IF :DEF:__MICROLIB
|
|
||||||
|
|
||||||
EXPORT __initial_sp
|
|
||||||
EXPORT __heap_base
|
|
||||||
EXPORT __heap_limit
|
|
||||||
|
|
||||||
ELSE
|
|
||||||
|
|
||||||
IMPORT __use_two_region_memory
|
|
||||||
EXPORT __user_initial_stackheap
|
|
||||||
|
|
||||||
__user_initial_stackheap
|
|
||||||
|
|
||||||
LDR R0, = Heap_Mem
|
|
||||||
LDR R1, =(Stack_Mem + Stack_Size)
|
|
||||||
LDR R2, = (Heap_Mem + Heap_Size)
|
|
||||||
LDR R3, = Stack_Mem
|
|
||||||
BX LR
|
|
||||||
|
|
||||||
ALIGN
|
|
||||||
|
|
||||||
ENDIF
|
|
||||||
|
|
||||||
END
|
|
||||||
|
|
||||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
|
||||||
|
|
@ -1,253 +0,0 @@
|
||||||
;******************************************************************************
|
|
||||||
;* File Name : startup_stm32wl55xx_cm0plus.s
|
|
||||||
;* Author : MCD Application Team
|
|
||||||
;* Description : STM32WL55xx devices vector table for MDK-ARM toolchain.
|
|
||||||
;* This module performs:
|
|
||||||
;* - Set the initial SP
|
|
||||||
;* - Set the initial PC == Reset_Handler
|
|
||||||
;* - Set the vector table entries with the exceptions ISR address
|
|
||||||
;* - Branches to __main in the C library (which eventually
|
|
||||||
;* calls main()).
|
|
||||||
;* After Reset the Cortex-M0+ processor is in Thread mode,
|
|
||||||
;* priority is Privileged, and the Stack is set to Main.
|
|
||||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
|
||||||
;******************************************************************************
|
|
||||||
;* @attention
|
|
||||||
;*
|
|
||||||
;* Copyright (c) 2020(2021) STMicroelectronics.
|
|
||||||
;* All rights reserved.
|
|
||||||
;*
|
|
||||||
;* This software is licensed under terms that can be found in the LICENSE file
|
|
||||||
;* in the root directory of this software component.
|
|
||||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
|
||||||
;*
|
|
||||||
;******************************************************************************
|
|
||||||
|
|
||||||
; Amount of memory (in bytes) allocated for Stack
|
|
||||||
; Tailor this value to your application needs
|
|
||||||
; <h> Stack Configuration
|
|
||||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
|
||||||
; </h>
|
|
||||||
|
|
||||||
Stack_Size EQU 0x00000400
|
|
||||||
|
|
||||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
|
||||||
Stack_Mem SPACE Stack_Size
|
|
||||||
__initial_sp
|
|
||||||
|
|
||||||
|
|
||||||
; <h> Heap Configuration
|
|
||||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
|
||||||
; </h>
|
|
||||||
|
|
||||||
Heap_Size EQU 0x00000000
|
|
||||||
|
|
||||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
|
||||||
__heap_base
|
|
||||||
Heap_Mem SPACE Heap_Size
|
|
||||||
__heap_limit
|
|
||||||
|
|
||||||
PRESERVE8
|
|
||||||
THUMB
|
|
||||||
|
|
||||||
|
|
||||||
; Vector Table Mapped to Address 0 at Reset
|
|
||||||
AREA RESET, DATA, READONLY
|
|
||||||
EXPORT __Vectors
|
|
||||||
EXPORT __Vectors_End
|
|
||||||
EXPORT __Vectors_Size
|
|
||||||
|
|
||||||
__Vectors DCD __initial_sp ; Top of Stack
|
|
||||||
DCD Reset_Handler ; Reset Handler
|
|
||||||
DCD NMI_Handler ; NMI Handler
|
|
||||||
DCD HardFault_Handler ; Hard Fault Handler
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD SVC_Handler ; SVCall Handler
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD PendSV_Handler ; PendSV Handler
|
|
||||||
DCD SysTick_Handler ; SysTick Handler
|
|
||||||
|
|
||||||
; External Interrupts
|
|
||||||
DCD TZIC_ILA_IRQHandler ; Security Interrupt controller illegal access Interrupts
|
|
||||||
DCD PVD_PVM_IRQHandler ; PVD and PVM detector
|
|
||||||
DCD RTC_LSECSS_IRQHandler ; RTC Wakeup + RTC Tamper and TimeStamp + RTC Alarms (A & B) + SSR Underflow and LSECSS Interrupts
|
|
||||||
DCD RCC_FLASH_C1SEV_IRQHandler ; RCC1 and FLASH and CPU1 M4 SEV Interrupts
|
|
||||||
DCD EXTI1_0_IRQHandler ; EXTI Line 1:0 Interrupts
|
|
||||||
DCD EXTI3_2_IRQHandler ; XTI Line 3:2 Interrupts
|
|
||||||
DCD EXTI15_4_IRQHandler ; EXTI Line 15:4 interrupts
|
|
||||||
DCD ADC_COMP_DAC_IRQHandler ; ADC, COMP1, COMP2, DAC Interrupts
|
|
||||||
DCD DMA1_Channel1_2_3_IRQHandler ; DMA1 Channel 1 to 3 Interrupts
|
|
||||||
DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channels 4, 5, 6, 7 Interrupts
|
|
||||||
DCD DMA2_DMAMUX1_OVR_IRQHandler ; DMA2 Channels[1..7] and DMAMUX Overrun Interrupts
|
|
||||||
DCD LPTIM1_IRQHandler ; LPTIM1 global Interrupt
|
|
||||||
DCD LPTIM2_IRQHandler ; LPTIM2 global Interrupt
|
|
||||||
DCD LPTIM3_IRQHandler ; LPTIM3 global Interrupt
|
|
||||||
DCD TIM1_IRQHandler ; TIM1 Interrupt
|
|
||||||
DCD TIM2_IRQHandler ; TIM2 Interrupt
|
|
||||||
DCD TIM16_IRQHandler ; TIM16 Interrupt
|
|
||||||
DCD TIM17_IRQHandler ; TIM17 Interrupt
|
|
||||||
DCD IPCC_C2_RX_C2_TX_IRQHandler ; IPCC RX Occupied and TX Free Interrupt Interrupts
|
|
||||||
DCD HSEM_IRQHandler ; Semaphore Interrupt
|
|
||||||
DCD RNG_IRQHandler ; RNG Interrupt
|
|
||||||
DCD AES_PKA_IRQHandler ; AES and PKA Interrupts
|
|
||||||
DCD I2C1_IRQHandler ; I2C1 Event and Error Interrupt
|
|
||||||
DCD I2C2_IRQHandler ; I2C2 Event and Error Interrupt
|
|
||||||
DCD I2C3_IRQHandler ; I2C3 Event and Error Interrupt
|
|
||||||
DCD SPI1_IRQHandler ; SPI1 Interrupts
|
|
||||||
DCD SPI2_IRQHandler ; SPI2 Interrupt
|
|
||||||
DCD USART1_IRQHandler ; USART1 Interrupt
|
|
||||||
DCD USART2_IRQHandler ; USART2 Interrupt
|
|
||||||
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
|
|
||||||
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
|
|
||||||
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
|
|
||||||
__Vectors_End
|
|
||||||
|
|
||||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
|
||||||
|
|
||||||
AREA |.text|, CODE, READONLY
|
|
||||||
|
|
||||||
; Reset handler
|
|
||||||
Reset_Handler PROC
|
|
||||||
EXPORT Reset_Handler [WEAK]
|
|
||||||
IMPORT SystemInit
|
|
||||||
IMPORT __main
|
|
||||||
|
|
||||||
LDR R0, =SystemInit
|
|
||||||
BLX R0
|
|
||||||
LDR R0, =__main
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
|
||||||
|
|
||||||
NMI_Handler PROC
|
|
||||||
EXPORT NMI_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
HardFault_Handler\
|
|
||||||
PROC
|
|
||||||
EXPORT HardFault_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
SVC_Handler PROC
|
|
||||||
EXPORT SVC_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
PendSV_Handler PROC
|
|
||||||
EXPORT PendSV_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
SysTick_Handler PROC
|
|
||||||
EXPORT SysTick_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
Default_Handler PROC
|
|
||||||
EXPORT TZIC_ILA_IRQHandler [WEAK]
|
|
||||||
EXPORT PVD_PVM_IRQHandler [WEAK]
|
|
||||||
EXPORT RTC_LSECSS_IRQHandler [WEAK]
|
|
||||||
EXPORT RCC_FLASH_C1SEV_IRQHandler [WEAK]
|
|
||||||
EXPORT EXTI1_0_IRQHandler [WEAK]
|
|
||||||
EXPORT EXTI3_2_IRQHandler [WEAK]
|
|
||||||
EXPORT EXTI15_4_IRQHandler [WEAK]
|
|
||||||
EXPORT ADC_COMP_DAC_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA1_Channel1_2_3_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA1_Channel4_5_6_7_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA2_DMAMUX1_OVR_IRQHandler [WEAK]
|
|
||||||
EXPORT LPTIM1_IRQHandler [WEAK]
|
|
||||||
EXPORT LPTIM2_IRQHandler [WEAK]
|
|
||||||
EXPORT LPTIM3_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM1_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM2_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM16_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM17_IRQHandler [WEAK]
|
|
||||||
EXPORT IPCC_C2_RX_C2_TX_IRQHandler [WEAK]
|
|
||||||
EXPORT HSEM_IRQHandler [WEAK]
|
|
||||||
EXPORT RNG_IRQHandler [WEAK]
|
|
||||||
EXPORT AES_PKA_IRQHandler [WEAK]
|
|
||||||
EXPORT I2C1_IRQHandler [WEAK]
|
|
||||||
EXPORT I2C2_IRQHandler [WEAK]
|
|
||||||
EXPORT I2C3_IRQHandler [WEAK]
|
|
||||||
EXPORT SPI1_IRQHandler [WEAK]
|
|
||||||
EXPORT SPI2_IRQHandler [WEAK]
|
|
||||||
EXPORT USART1_IRQHandler [WEAK]
|
|
||||||
EXPORT USART2_IRQHandler [WEAK]
|
|
||||||
EXPORT LPUART1_IRQHandler [WEAK]
|
|
||||||
EXPORT SUBGHZSPI_IRQHandler [WEAK]
|
|
||||||
EXPORT SUBGHZ_Radio_IRQHandler [WEAK]
|
|
||||||
|
|
||||||
TZIC_ILA_IRQHandler
|
|
||||||
PVD_PVM_IRQHandler
|
|
||||||
RTC_LSECSS_IRQHandler
|
|
||||||
RCC_FLASH_C1SEV_IRQHandler
|
|
||||||
EXTI1_0_IRQHandler
|
|
||||||
EXTI3_2_IRQHandler
|
|
||||||
EXTI15_4_IRQHandler
|
|
||||||
ADC_COMP_DAC_IRQHandler
|
|
||||||
DMA1_Channel1_2_3_IRQHandler
|
|
||||||
DMA1_Channel4_5_6_7_IRQHandler
|
|
||||||
DMA2_DMAMUX1_OVR_IRQHandler
|
|
||||||
LPTIM1_IRQHandler
|
|
||||||
LPTIM2_IRQHandler
|
|
||||||
LPTIM3_IRQHandler
|
|
||||||
TIM1_IRQHandler
|
|
||||||
TIM2_IRQHandler
|
|
||||||
TIM16_IRQHandler
|
|
||||||
TIM17_IRQHandler
|
|
||||||
IPCC_C2_RX_C2_TX_IRQHandler
|
|
||||||
HSEM_IRQHandler
|
|
||||||
RNG_IRQHandler
|
|
||||||
AES_PKA_IRQHandler
|
|
||||||
I2C1_IRQHandler
|
|
||||||
I2C2_IRQHandler
|
|
||||||
I2C3_IRQHandler
|
|
||||||
SPI1_IRQHandler
|
|
||||||
SPI2_IRQHandler
|
|
||||||
USART1_IRQHandler
|
|
||||||
USART2_IRQHandler
|
|
||||||
LPUART1_IRQHandler
|
|
||||||
SUBGHZSPI_IRQHandler
|
|
||||||
SUBGHZ_Radio_IRQHandler
|
|
||||||
|
|
||||||
B .
|
|
||||||
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
ALIGN
|
|
||||||
|
|
||||||
;*******************************************************************************
|
|
||||||
; User Stack and Heap initialization
|
|
||||||
;*******************************************************************************
|
|
||||||
IF :DEF:__MICROLIB
|
|
||||||
|
|
||||||
EXPORT __initial_sp
|
|
||||||
EXPORT __heap_base
|
|
||||||
EXPORT __heap_limit
|
|
||||||
|
|
||||||
ELSE
|
|
||||||
|
|
||||||
IMPORT __use_two_region_memory
|
|
||||||
EXPORT __user_initial_stackheap
|
|
||||||
|
|
||||||
__user_initial_stackheap
|
|
||||||
|
|
||||||
LDR R0, = Heap_Mem
|
|
||||||
LDR R1, =(Stack_Mem + Stack_Size)
|
|
||||||
LDR R2, = (Heap_Mem + Heap_Size)
|
|
||||||
LDR R3, = Stack_Mem
|
|
||||||
BX LR
|
|
||||||
|
|
||||||
ALIGN
|
|
||||||
|
|
||||||
ENDIF
|
|
||||||
|
|
||||||
END
|
|
||||||
|
|
||||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
|
||||||
|
|
@ -1,365 +0,0 @@
|
||||||
;******************************************************************************
|
|
||||||
;* File Name : startup_stm32wl55xx_cm4.s
|
|
||||||
;* Author : MCD Application Team
|
|
||||||
;* Description : STM32WL55xx devices vector table for MDK-ARM toolchain.
|
|
||||||
;* This module performs:
|
|
||||||
;* - Set the initial SP
|
|
||||||
;* - Set the initial PC == Reset_Handler
|
|
||||||
;* - Set the vector table entries with the exceptions ISR address
|
|
||||||
;* - Branches to __main in the C library (which eventually
|
|
||||||
;* calls main()).
|
|
||||||
;* After Reset the CortexM4 processor is in Thread mode,
|
|
||||||
;* priority is Privileged, and the Stack is set to Main.
|
|
||||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
|
||||||
;******************************************************************************
|
|
||||||
;* @attention
|
|
||||||
;*
|
|
||||||
;* Copyright (c) 2020(2021) STMicroelectronics.
|
|
||||||
;* All rights reserved.
|
|
||||||
;*
|
|
||||||
;* This software is licensed under terms that can be found in the LICENSE file
|
|
||||||
;* in the root directory of this software component.
|
|
||||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
|
||||||
;*
|
|
||||||
;******************************************************************************
|
|
||||||
|
|
||||||
; Amount of memory (in bytes) allocated for Stack
|
|
||||||
; Tailor this value to your application needs
|
|
||||||
; <h> Stack Configuration
|
|
||||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
|
||||||
; </h>
|
|
||||||
|
|
||||||
Stack_Size EQU 0x00000400
|
|
||||||
|
|
||||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
|
||||||
Stack_Mem SPACE Stack_Size
|
|
||||||
__initial_sp
|
|
||||||
|
|
||||||
|
|
||||||
; <h> Heap Configuration
|
|
||||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
|
||||||
; </h>
|
|
||||||
|
|
||||||
Heap_Size EQU 0x00000000
|
|
||||||
|
|
||||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
|
||||||
__heap_base
|
|
||||||
Heap_Mem SPACE Heap_Size
|
|
||||||
__heap_limit
|
|
||||||
|
|
||||||
PRESERVE8
|
|
||||||
THUMB
|
|
||||||
|
|
||||||
|
|
||||||
; Vector Table Mapped to Address 0 at Reset
|
|
||||||
AREA RESET, DATA, READONLY
|
|
||||||
EXPORT __Vectors
|
|
||||||
EXPORT __Vectors_End
|
|
||||||
EXPORT __Vectors_Size
|
|
||||||
|
|
||||||
__Vectors DCD __initial_sp ; Top of Stack
|
|
||||||
DCD Reset_Handler ; Reset Handler
|
|
||||||
DCD NMI_Handler ; NMI Handler
|
|
||||||
DCD HardFault_Handler ; Hard Fault Handler
|
|
||||||
DCD MemManage_Handler ; MPU Fault Handler
|
|
||||||
DCD BusFault_Handler ; Bus Fault Handler
|
|
||||||
DCD UsageFault_Handler ; Usage Fault Handler
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD SVC_Handler ; SVCall Handler
|
|
||||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD PendSV_Handler ; PendSV Handler
|
|
||||||
DCD SysTick_Handler ; SysTick Handler
|
|
||||||
|
|
||||||
; External Interrupts
|
|
||||||
DCD WWDG_IRQHandler ; Window WatchDog
|
|
||||||
DCD PVD_PVM_IRQHandler ; PVD and PVM detector
|
|
||||||
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSR Underflow Interrupts
|
|
||||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
|
|
||||||
DCD FLASH_IRQHandler ; FLASH global Interrupt
|
|
||||||
DCD RCC_IRQHandler ; RCC Interrupt
|
|
||||||
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
|
|
||||||
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
|
|
||||||
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
|
|
||||||
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup
|
|
||||||
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
|
|
||||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
|
|
||||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
|
|
||||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
|
|
||||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
|
|
||||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
|
|
||||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
|
|
||||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
|
|
||||||
DCD ADC_IRQHandler ; ADC Interrupt
|
|
||||||
DCD DAC_IRQHandler ; DAC Interrupt
|
|
||||||
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV and PWR CPU M0+ HOLD wakeup Interrupt
|
|
||||||
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
|
|
||||||
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
|
|
||||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
|
|
||||||
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupts
|
|
||||||
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
|
|
||||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
|
|
||||||
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
|
|
||||||
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
|
|
||||||
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
|
|
||||||
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
|
|
||||||
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
|
|
||||||
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
|
|
||||||
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
|
|
||||||
DCD SPI1_IRQHandler ; SPI1 Interrupt
|
|
||||||
DCD SPI2_IRQHandler ; SPI2 Interrupt
|
|
||||||
DCD USART1_IRQHandler ; USART1 Interrupt
|
|
||||||
DCD USART2_IRQHandler ; USART2 Interrupt
|
|
||||||
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
|
|
||||||
DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
|
|
||||||
DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
|
|
||||||
DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
|
|
||||||
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
|
|
||||||
DCD LPTIM3_IRQHandler ; LPTIM3 Interrupt
|
|
||||||
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
|
|
||||||
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
|
|
||||||
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
|
|
||||||
DCD HSEM_IRQHandler ; HSEM0 Interrupt
|
|
||||||
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
|
|
||||||
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
|
|
||||||
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
|
|
||||||
DCD AES_IRQHandler ; AES Interrupt
|
|
||||||
DCD RNG_IRQHandler ; RNG1 Interrupt
|
|
||||||
DCD PKA_IRQHandler ; PKA Interrupt
|
|
||||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
|
|
||||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
|
|
||||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
|
|
||||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
|
|
||||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
|
|
||||||
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
|
|
||||||
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
|
|
||||||
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
|
|
||||||
|
|
||||||
__Vectors_End
|
|
||||||
|
|
||||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
|
||||||
|
|
||||||
AREA |.text|, CODE, READONLY
|
|
||||||
|
|
||||||
; Reset handler
|
|
||||||
Reset_Handler PROC
|
|
||||||
EXPORT Reset_Handler [WEAK]
|
|
||||||
IMPORT SystemInit
|
|
||||||
IMPORT __main
|
|
||||||
|
|
||||||
LDR R0, =SystemInit
|
|
||||||
BLX R0
|
|
||||||
LDR R0, =__main
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
|
||||||
|
|
||||||
NMI_Handler PROC
|
|
||||||
EXPORT NMI_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
HardFault_Handler\
|
|
||||||
PROC
|
|
||||||
EXPORT HardFault_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
MemManage_Handler\
|
|
||||||
PROC
|
|
||||||
EXPORT MemManage_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
BusFault_Handler\
|
|
||||||
PROC
|
|
||||||
EXPORT BusFault_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
UsageFault_Handler\
|
|
||||||
PROC
|
|
||||||
EXPORT UsageFault_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
SVC_Handler PROC
|
|
||||||
EXPORT SVC_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
DebugMon_Handler\
|
|
||||||
PROC
|
|
||||||
EXPORT DebugMon_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
PendSV_Handler PROC
|
|
||||||
EXPORT PendSV_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
SysTick_Handler PROC
|
|
||||||
EXPORT SysTick_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
Default_Handler PROC
|
|
||||||
|
|
||||||
EXPORT WWDG_IRQHandler [WEAK]
|
|
||||||
EXPORT PVD_PVM_IRQHandler [WEAK]
|
|
||||||
EXPORT TAMP_STAMP_LSECSS_SSRU_IRQHandler [WEAK]
|
|
||||||
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
|
||||||
EXPORT FLASH_IRQHandler [WEAK]
|
|
||||||
EXPORT RCC_IRQHandler [WEAK]
|
|
||||||
EXPORT EXTI0_IRQHandler [WEAK]
|
|
||||||
EXPORT EXTI1_IRQHandler [WEAK]
|
|
||||||
EXPORT EXTI2_IRQHandler [WEAK]
|
|
||||||
EXPORT EXTI3_IRQHandler [WEAK]
|
|
||||||
EXPORT EXTI4_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
|
||||||
EXPORT ADC_IRQHandler [WEAK]
|
|
||||||
EXPORT DAC_IRQHandler [WEAK]
|
|
||||||
EXPORT C2SEV_PWR_C2H_IRQHandler [WEAK]
|
|
||||||
EXPORT COMP_IRQHandler [WEAK]
|
|
||||||
EXPORT EXTI9_5_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM1_BRK_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM1_UP_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM1_CC_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM2_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM16_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM17_IRQHandler [WEAK]
|
|
||||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
|
||||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
|
||||||
EXPORT I2C2_EV_IRQHandler [WEAK]
|
|
||||||
EXPORT I2C2_ER_IRQHandler [WEAK]
|
|
||||||
EXPORT SPI1_IRQHandler [WEAK]
|
|
||||||
EXPORT SPI2_IRQHandler [WEAK]
|
|
||||||
EXPORT USART1_IRQHandler [WEAK]
|
|
||||||
EXPORT USART2_IRQHandler [WEAK]
|
|
||||||
EXPORT LPUART1_IRQHandler [WEAK]
|
|
||||||
EXPORT LPTIM1_IRQHandler [WEAK]
|
|
||||||
EXPORT LPTIM2_IRQHandler [WEAK]
|
|
||||||
EXPORT EXTI15_10_IRQHandler [WEAK]
|
|
||||||
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
|
||||||
EXPORT LPTIM3_IRQHandler [WEAK]
|
|
||||||
EXPORT SUBGHZSPI_IRQHandler [WEAK]
|
|
||||||
EXPORT IPCC_C1_RX_IRQHandler [WEAK]
|
|
||||||
EXPORT IPCC_C1_TX_IRQHandler [WEAK]
|
|
||||||
EXPORT HSEM_IRQHandler [WEAK]
|
|
||||||
EXPORT I2C3_EV_IRQHandler [WEAK]
|
|
||||||
EXPORT I2C3_ER_IRQHandler [WEAK]
|
|
||||||
EXPORT SUBGHZ_Radio_IRQHandler [WEAK]
|
|
||||||
EXPORT AES_IRQHandler [WEAK]
|
|
||||||
EXPORT RNG_IRQHandler [WEAK]
|
|
||||||
EXPORT PKA_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA2_Channel1_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA2_Channel2_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA2_Channel3_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA2_Channel4_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA2_Channel5_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA2_Channel6_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA2_Channel7_IRQHandler [WEAK]
|
|
||||||
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
|
|
||||||
|
|
||||||
WWDG_IRQHandler
|
|
||||||
PVD_PVM_IRQHandler
|
|
||||||
TAMP_STAMP_LSECSS_SSRU_IRQHandler
|
|
||||||
RTC_WKUP_IRQHandler
|
|
||||||
FLASH_IRQHandler
|
|
||||||
RCC_IRQHandler
|
|
||||||
EXTI0_IRQHandler
|
|
||||||
EXTI1_IRQHandler
|
|
||||||
EXTI2_IRQHandler
|
|
||||||
EXTI3_IRQHandler
|
|
||||||
EXTI4_IRQHandler
|
|
||||||
DMA1_Channel1_IRQHandler
|
|
||||||
DMA1_Channel2_IRQHandler
|
|
||||||
DMA1_Channel3_IRQHandler
|
|
||||||
DMA1_Channel4_IRQHandler
|
|
||||||
DMA1_Channel5_IRQHandler
|
|
||||||
DMA1_Channel6_IRQHandler
|
|
||||||
DMA1_Channel7_IRQHandler
|
|
||||||
ADC_IRQHandler
|
|
||||||
DAC_IRQHandler
|
|
||||||
C2SEV_PWR_C2H_IRQHandler
|
|
||||||
COMP_IRQHandler
|
|
||||||
EXTI9_5_IRQHandler
|
|
||||||
TIM1_BRK_IRQHandler
|
|
||||||
TIM1_UP_IRQHandler
|
|
||||||
TIM1_TRG_COM_IRQHandler
|
|
||||||
TIM1_CC_IRQHandler
|
|
||||||
TIM2_IRQHandler
|
|
||||||
TIM16_IRQHandler
|
|
||||||
TIM17_IRQHandler
|
|
||||||
I2C1_EV_IRQHandler
|
|
||||||
I2C1_ER_IRQHandler
|
|
||||||
I2C2_EV_IRQHandler
|
|
||||||
I2C2_ER_IRQHandler
|
|
||||||
SPI1_IRQHandler
|
|
||||||
SPI2_IRQHandler
|
|
||||||
USART1_IRQHandler
|
|
||||||
USART2_IRQHandler
|
|
||||||
LPUART1_IRQHandler
|
|
||||||
LPTIM1_IRQHandler
|
|
||||||
LPTIM2_IRQHandler
|
|
||||||
EXTI15_10_IRQHandler
|
|
||||||
RTC_Alarm_IRQHandler
|
|
||||||
LPTIM3_IRQHandler
|
|
||||||
SUBGHZSPI_IRQHandler
|
|
||||||
IPCC_C1_RX_IRQHandler
|
|
||||||
IPCC_C1_TX_IRQHandler
|
|
||||||
HSEM_IRQHandler
|
|
||||||
I2C3_EV_IRQHandler
|
|
||||||
I2C3_ER_IRQHandler
|
|
||||||
SUBGHZ_Radio_IRQHandler
|
|
||||||
AES_IRQHandler
|
|
||||||
RNG_IRQHandler
|
|
||||||
PKA_IRQHandler
|
|
||||||
DMA2_Channel1_IRQHandler
|
|
||||||
DMA2_Channel2_IRQHandler
|
|
||||||
DMA2_Channel3_IRQHandler
|
|
||||||
DMA2_Channel4_IRQHandler
|
|
||||||
DMA2_Channel5_IRQHandler
|
|
||||||
DMA2_Channel6_IRQHandler
|
|
||||||
DMA2_Channel7_IRQHandler
|
|
||||||
DMAMUX1_OVR_IRQHandler
|
|
||||||
|
|
||||||
B .
|
|
||||||
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
ALIGN
|
|
||||||
|
|
||||||
;*******************************************************************************
|
|
||||||
; User Stack and Heap initialization
|
|
||||||
;*******************************************************************************
|
|
||||||
IF :DEF:__MICROLIB
|
|
||||||
|
|
||||||
EXPORT __initial_sp
|
|
||||||
EXPORT __heap_base
|
|
||||||
EXPORT __heap_limit
|
|
||||||
|
|
||||||
ELSE
|
|
||||||
|
|
||||||
IMPORT __use_two_region_memory
|
|
||||||
EXPORT __user_initial_stackheap
|
|
||||||
|
|
||||||
__user_initial_stackheap
|
|
||||||
|
|
||||||
LDR R0, = Heap_Mem
|
|
||||||
LDR R1, =(Stack_Mem + Stack_Size)
|
|
||||||
LDR R2, = (Heap_Mem + Heap_Size)
|
|
||||||
LDR R3, = Stack_Mem
|
|
||||||
BX LR
|
|
||||||
|
|
||||||
ALIGN
|
|
||||||
|
|
||||||
ENDIF
|
|
||||||
|
|
||||||
END
|
|
||||||
|
|
||||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
|
||||||
|
|
@ -1,359 +0,0 @@
|
||||||
;******************************************************************************
|
|
||||||
;* File Name : startup_stm32wle4xx.s
|
|
||||||
;* Author : MCD Application Team
|
|
||||||
;* Description : STM32WLE4xx devices vector table for MDK-ARM toolchain.
|
|
||||||
;* This module performs:
|
|
||||||
;* - Set the initial SP
|
|
||||||
;* - Set the initial PC == Reset_Handler
|
|
||||||
;* - Set the vector table entries with the exceptions ISR address
|
|
||||||
;* - Branches to __main in the C library (which eventually
|
|
||||||
;* calls main()).
|
|
||||||
;* After Reset the CortexM4 processor is in Thread mode,
|
|
||||||
;* priority is Privileged, and the Stack is set to Main.
|
|
||||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
|
||||||
;******************************************************************************
|
|
||||||
;* @attention
|
|
||||||
;*
|
|
||||||
;* Copyright (c) 2020(2021) STMicroelectronics.
|
|
||||||
;* All rights reserved.
|
|
||||||
;*
|
|
||||||
;* This software is licensed under terms that can be found in the LICENSE file
|
|
||||||
;* in the root directory of this software component.
|
|
||||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
|
||||||
;*
|
|
||||||
;******************************************************************************
|
|
||||||
|
|
||||||
; Amount of memory (in bytes) allocated for Stack
|
|
||||||
; Tailor this value to your application needs
|
|
||||||
; <h> Stack Configuration
|
|
||||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
|
||||||
; </h>
|
|
||||||
|
|
||||||
Stack_Size EQU 0x00000400
|
|
||||||
|
|
||||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
|
||||||
Stack_Mem SPACE Stack_Size
|
|
||||||
__initial_sp
|
|
||||||
|
|
||||||
|
|
||||||
; <h> Heap Configuration
|
|
||||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
|
||||||
; </h>
|
|
||||||
|
|
||||||
Heap_Size EQU 0x00000000
|
|
||||||
|
|
||||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
|
||||||
__heap_base
|
|
||||||
Heap_Mem SPACE Heap_Size
|
|
||||||
__heap_limit
|
|
||||||
|
|
||||||
PRESERVE8
|
|
||||||
THUMB
|
|
||||||
|
|
||||||
|
|
||||||
; Vector Table Mapped to Address 0 at Reset
|
|
||||||
AREA RESET, DATA, READONLY
|
|
||||||
EXPORT __Vectors
|
|
||||||
EXPORT __Vectors_End
|
|
||||||
EXPORT __Vectors_Size
|
|
||||||
|
|
||||||
__Vectors DCD __initial_sp ; Top of Stack
|
|
||||||
DCD Reset_Handler ; Reset Handler
|
|
||||||
DCD NMI_Handler ; NMI Handler
|
|
||||||
DCD HardFault_Handler ; Hard Fault Handler
|
|
||||||
DCD MemManage_Handler ; MPU Fault Handler
|
|
||||||
DCD BusFault_Handler ; Bus Fault Handler
|
|
||||||
DCD UsageFault_Handler ; Usage Fault Handler
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD SVC_Handler ; SVCall Handler
|
|
||||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD PendSV_Handler ; PendSV Handler
|
|
||||||
DCD SysTick_Handler ; SysTick Handler
|
|
||||||
|
|
||||||
; External Interrupts
|
|
||||||
DCD WWDG_IRQHandler ; Window WatchDog
|
|
||||||
DCD PVD_PVM_IRQHandler ; PVD and PVM detector
|
|
||||||
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSR Underflow Interrupts
|
|
||||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
|
|
||||||
DCD FLASH_IRQHandler ; FLASH global Interrupt
|
|
||||||
DCD RCC_IRQHandler ; RCC Interrupt
|
|
||||||
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
|
|
||||||
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
|
|
||||||
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
|
|
||||||
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup
|
|
||||||
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
|
|
||||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
|
|
||||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
|
|
||||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
|
|
||||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
|
|
||||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
|
|
||||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
|
|
||||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
|
|
||||||
DCD ADC_IRQHandler ; ADC Interrupt
|
|
||||||
DCD DAC_IRQHandler ; DAC Interrupt
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
|
|
||||||
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
|
|
||||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
|
|
||||||
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupts
|
|
||||||
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
|
|
||||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
|
|
||||||
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
|
|
||||||
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
|
|
||||||
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
|
|
||||||
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
|
|
||||||
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
|
|
||||||
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
|
|
||||||
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
|
|
||||||
DCD SPI1_IRQHandler ; SPI1 Interrupt
|
|
||||||
DCD SPI2_IRQHandler ; SPI2 Interrupt
|
|
||||||
DCD USART1_IRQHandler ; USART1 Interrupt
|
|
||||||
DCD USART2_IRQHandler ; USART2 Interrupt
|
|
||||||
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
|
|
||||||
DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
|
|
||||||
DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
|
|
||||||
DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
|
|
||||||
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
|
|
||||||
DCD LPTIM3_IRQHandler ; LPTIM3 Interrupt
|
|
||||||
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD HSEM_IRQHandler ; HSEM0 Interrupt
|
|
||||||
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
|
|
||||||
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
|
|
||||||
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
|
|
||||||
DCD AES_IRQHandler ; AES Interrupt
|
|
||||||
DCD RNG_IRQHandler ; RNG1 Interrupt
|
|
||||||
DCD PKA_IRQHandler ; PKA Interrupt
|
|
||||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
|
|
||||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
|
|
||||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
|
|
||||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
|
|
||||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
|
|
||||||
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
|
|
||||||
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
|
|
||||||
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
|
|
||||||
|
|
||||||
__Vectors_End
|
|
||||||
|
|
||||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
|
||||||
|
|
||||||
AREA |.text|, CODE, READONLY
|
|
||||||
|
|
||||||
; Reset handler
|
|
||||||
Reset_Handler PROC
|
|
||||||
EXPORT Reset_Handler [WEAK]
|
|
||||||
IMPORT SystemInit
|
|
||||||
IMPORT __main
|
|
||||||
|
|
||||||
LDR R0, =SystemInit
|
|
||||||
BLX R0
|
|
||||||
LDR R0, =__main
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
|
||||||
|
|
||||||
NMI_Handler PROC
|
|
||||||
EXPORT NMI_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
HardFault_Handler\
|
|
||||||
PROC
|
|
||||||
EXPORT HardFault_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
MemManage_Handler\
|
|
||||||
PROC
|
|
||||||
EXPORT MemManage_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
BusFault_Handler\
|
|
||||||
PROC
|
|
||||||
EXPORT BusFault_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
UsageFault_Handler\
|
|
||||||
PROC
|
|
||||||
EXPORT UsageFault_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
SVC_Handler PROC
|
|
||||||
EXPORT SVC_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
DebugMon_Handler\
|
|
||||||
PROC
|
|
||||||
EXPORT DebugMon_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
PendSV_Handler PROC
|
|
||||||
EXPORT PendSV_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
SysTick_Handler PROC
|
|
||||||
EXPORT SysTick_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
Default_Handler PROC
|
|
||||||
|
|
||||||
EXPORT WWDG_IRQHandler [WEAK]
|
|
||||||
EXPORT PVD_PVM_IRQHandler [WEAK]
|
|
||||||
EXPORT TAMP_STAMP_LSECSS_SSRU_IRQHandler [WEAK]
|
|
||||||
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
|
||||||
EXPORT FLASH_IRQHandler [WEAK]
|
|
||||||
EXPORT RCC_IRQHandler [WEAK]
|
|
||||||
EXPORT EXTI0_IRQHandler [WEAK]
|
|
||||||
EXPORT EXTI1_IRQHandler [WEAK]
|
|
||||||
EXPORT EXTI2_IRQHandler [WEAK]
|
|
||||||
EXPORT EXTI3_IRQHandler [WEAK]
|
|
||||||
EXPORT EXTI4_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
|
||||||
EXPORT ADC_IRQHandler [WEAK]
|
|
||||||
EXPORT DAC_IRQHandler [WEAK]
|
|
||||||
EXPORT COMP_IRQHandler [WEAK]
|
|
||||||
EXPORT EXTI9_5_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM1_BRK_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM1_UP_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM1_CC_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM2_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM16_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM17_IRQHandler [WEAK]
|
|
||||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
|
||||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
|
||||||
EXPORT I2C2_EV_IRQHandler [WEAK]
|
|
||||||
EXPORT I2C2_ER_IRQHandler [WEAK]
|
|
||||||
EXPORT SPI1_IRQHandler [WEAK]
|
|
||||||
EXPORT SPI2_IRQHandler [WEAK]
|
|
||||||
EXPORT USART1_IRQHandler [WEAK]
|
|
||||||
EXPORT USART2_IRQHandler [WEAK]
|
|
||||||
EXPORT LPUART1_IRQHandler [WEAK]
|
|
||||||
EXPORT LPTIM1_IRQHandler [WEAK]
|
|
||||||
EXPORT LPTIM2_IRQHandler [WEAK]
|
|
||||||
EXPORT EXTI15_10_IRQHandler [WEAK]
|
|
||||||
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
|
||||||
EXPORT LPTIM3_IRQHandler [WEAK]
|
|
||||||
EXPORT SUBGHZSPI_IRQHandler [WEAK]
|
|
||||||
EXPORT HSEM_IRQHandler [WEAK]
|
|
||||||
EXPORT I2C3_EV_IRQHandler [WEAK]
|
|
||||||
EXPORT I2C3_ER_IRQHandler [WEAK]
|
|
||||||
EXPORT SUBGHZ_Radio_IRQHandler [WEAK]
|
|
||||||
EXPORT AES_IRQHandler [WEAK]
|
|
||||||
EXPORT RNG_IRQHandler [WEAK]
|
|
||||||
EXPORT PKA_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA2_Channel1_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA2_Channel2_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA2_Channel3_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA2_Channel4_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA2_Channel5_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA2_Channel6_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA2_Channel7_IRQHandler [WEAK]
|
|
||||||
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
|
|
||||||
|
|
||||||
WWDG_IRQHandler
|
|
||||||
PVD_PVM_IRQHandler
|
|
||||||
TAMP_STAMP_LSECSS_SSRU_IRQHandler
|
|
||||||
RTC_WKUP_IRQHandler
|
|
||||||
FLASH_IRQHandler
|
|
||||||
RCC_IRQHandler
|
|
||||||
EXTI0_IRQHandler
|
|
||||||
EXTI1_IRQHandler
|
|
||||||
EXTI2_IRQHandler
|
|
||||||
EXTI3_IRQHandler
|
|
||||||
EXTI4_IRQHandler
|
|
||||||
DMA1_Channel1_IRQHandler
|
|
||||||
DMA1_Channel2_IRQHandler
|
|
||||||
DMA1_Channel3_IRQHandler
|
|
||||||
DMA1_Channel4_IRQHandler
|
|
||||||
DMA1_Channel5_IRQHandler
|
|
||||||
DMA1_Channel6_IRQHandler
|
|
||||||
DMA1_Channel7_IRQHandler
|
|
||||||
ADC_IRQHandler
|
|
||||||
DAC_IRQHandler
|
|
||||||
COMP_IRQHandler
|
|
||||||
EXTI9_5_IRQHandler
|
|
||||||
TIM1_BRK_IRQHandler
|
|
||||||
TIM1_UP_IRQHandler
|
|
||||||
TIM1_TRG_COM_IRQHandler
|
|
||||||
TIM1_CC_IRQHandler
|
|
||||||
TIM2_IRQHandler
|
|
||||||
TIM16_IRQHandler
|
|
||||||
TIM17_IRQHandler
|
|
||||||
I2C1_EV_IRQHandler
|
|
||||||
I2C1_ER_IRQHandler
|
|
||||||
I2C2_EV_IRQHandler
|
|
||||||
I2C2_ER_IRQHandler
|
|
||||||
SPI1_IRQHandler
|
|
||||||
SPI2_IRQHandler
|
|
||||||
USART1_IRQHandler
|
|
||||||
USART2_IRQHandler
|
|
||||||
LPUART1_IRQHandler
|
|
||||||
LPTIM1_IRQHandler
|
|
||||||
LPTIM2_IRQHandler
|
|
||||||
EXTI15_10_IRQHandler
|
|
||||||
RTC_Alarm_IRQHandler
|
|
||||||
LPTIM3_IRQHandler
|
|
||||||
SUBGHZSPI_IRQHandler
|
|
||||||
HSEM_IRQHandler
|
|
||||||
I2C3_EV_IRQHandler
|
|
||||||
I2C3_ER_IRQHandler
|
|
||||||
SUBGHZ_Radio_IRQHandler
|
|
||||||
AES_IRQHandler
|
|
||||||
RNG_IRQHandler
|
|
||||||
PKA_IRQHandler
|
|
||||||
DMA2_Channel1_IRQHandler
|
|
||||||
DMA2_Channel2_IRQHandler
|
|
||||||
DMA2_Channel3_IRQHandler
|
|
||||||
DMA2_Channel4_IRQHandler
|
|
||||||
DMA2_Channel5_IRQHandler
|
|
||||||
DMA2_Channel6_IRQHandler
|
|
||||||
DMA2_Channel7_IRQHandler
|
|
||||||
DMAMUX1_OVR_IRQHandler
|
|
||||||
|
|
||||||
B .
|
|
||||||
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
ALIGN
|
|
||||||
|
|
||||||
;*******************************************************************************
|
|
||||||
; User Stack and Heap initialization
|
|
||||||
;*******************************************************************************
|
|
||||||
IF :DEF:__MICROLIB
|
|
||||||
|
|
||||||
EXPORT __initial_sp
|
|
||||||
EXPORT __heap_base
|
|
||||||
EXPORT __heap_limit
|
|
||||||
|
|
||||||
ELSE
|
|
||||||
|
|
||||||
IMPORT __use_two_region_memory
|
|
||||||
EXPORT __user_initial_stackheap
|
|
||||||
|
|
||||||
__user_initial_stackheap
|
|
||||||
|
|
||||||
LDR R0, = Heap_Mem
|
|
||||||
LDR R1, =(Stack_Mem + Stack_Size)
|
|
||||||
LDR R2, = (Heap_Mem + Heap_Size)
|
|
||||||
LDR R3, = Stack_Mem
|
|
||||||
BX LR
|
|
||||||
|
|
||||||
ALIGN
|
|
||||||
|
|
||||||
ENDIF
|
|
||||||
|
|
||||||
END
|
|
||||||
|
|
||||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
|
||||||
|
|
@ -1,359 +0,0 @@
|
||||||
;******************************************************************************
|
|
||||||
;* File Name : startup_stm32wle5xx.s
|
|
||||||
;* Author : MCD Application Team
|
|
||||||
;* Description : STM32WLE5xx devices vector table for MDK-ARM toolchain.
|
|
||||||
;* This module performs:
|
|
||||||
;* - Set the initial SP
|
|
||||||
;* - Set the initial PC == Reset_Handler
|
|
||||||
;* - Set the vector table entries with the exceptions ISR address
|
|
||||||
;* - Branches to __main in the C library (which eventually
|
|
||||||
;* calls main()).
|
|
||||||
;* After Reset the CortexM4 processor is in Thread mode,
|
|
||||||
;* priority is Privileged, and the Stack is set to Main.
|
|
||||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
|
||||||
;******************************************************************************
|
|
||||||
;* @attention
|
|
||||||
;*
|
|
||||||
;* Copyright (c) 2020(2021) STMicroelectronics.
|
|
||||||
;* All rights reserved.
|
|
||||||
;*
|
|
||||||
;* This software is licensed under terms that can be found in the LICENSE file
|
|
||||||
;* in the root directory of this software component.
|
|
||||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
|
||||||
;*
|
|
||||||
;******************************************************************************
|
|
||||||
|
|
||||||
; Amount of memory (in bytes) allocated for Stack
|
|
||||||
; Tailor this value to your application needs
|
|
||||||
; <h> Stack Configuration
|
|
||||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
|
||||||
; </h>
|
|
||||||
|
|
||||||
Stack_Size EQU 0x00000400
|
|
||||||
|
|
||||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
|
||||||
Stack_Mem SPACE Stack_Size
|
|
||||||
__initial_sp
|
|
||||||
|
|
||||||
|
|
||||||
; <h> Heap Configuration
|
|
||||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
|
||||||
; </h>
|
|
||||||
|
|
||||||
Heap_Size EQU 0x00000000
|
|
||||||
|
|
||||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
|
||||||
__heap_base
|
|
||||||
Heap_Mem SPACE Heap_Size
|
|
||||||
__heap_limit
|
|
||||||
|
|
||||||
PRESERVE8
|
|
||||||
THUMB
|
|
||||||
|
|
||||||
|
|
||||||
; Vector Table Mapped to Address 0 at Reset
|
|
||||||
AREA RESET, DATA, READONLY
|
|
||||||
EXPORT __Vectors
|
|
||||||
EXPORT __Vectors_End
|
|
||||||
EXPORT __Vectors_Size
|
|
||||||
|
|
||||||
__Vectors DCD __initial_sp ; Top of Stack
|
|
||||||
DCD Reset_Handler ; Reset Handler
|
|
||||||
DCD NMI_Handler ; NMI Handler
|
|
||||||
DCD HardFault_Handler ; Hard Fault Handler
|
|
||||||
DCD MemManage_Handler ; MPU Fault Handler
|
|
||||||
DCD BusFault_Handler ; Bus Fault Handler
|
|
||||||
DCD UsageFault_Handler ; Usage Fault Handler
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD SVC_Handler ; SVCall Handler
|
|
||||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD PendSV_Handler ; PendSV Handler
|
|
||||||
DCD SysTick_Handler ; SysTick Handler
|
|
||||||
|
|
||||||
; External Interrupts
|
|
||||||
DCD WWDG_IRQHandler ; Window WatchDog
|
|
||||||
DCD PVD_PVM_IRQHandler ; PVD and PVM detector
|
|
||||||
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSR Underflow Interrupts
|
|
||||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
|
|
||||||
DCD FLASH_IRQHandler ; FLASH global Interrupt
|
|
||||||
DCD RCC_IRQHandler ; RCC Interrupt
|
|
||||||
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
|
|
||||||
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
|
|
||||||
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
|
|
||||||
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup
|
|
||||||
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
|
|
||||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
|
|
||||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
|
|
||||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
|
|
||||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
|
|
||||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
|
|
||||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
|
|
||||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
|
|
||||||
DCD ADC_IRQHandler ; ADC Interrupt
|
|
||||||
DCD DAC_IRQHandler ; DAC Interrupt
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
|
|
||||||
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
|
|
||||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
|
|
||||||
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupts
|
|
||||||
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
|
|
||||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
|
|
||||||
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
|
|
||||||
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
|
|
||||||
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
|
|
||||||
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
|
|
||||||
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
|
|
||||||
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
|
|
||||||
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
|
|
||||||
DCD SPI1_IRQHandler ; SPI1 Interrupt
|
|
||||||
DCD SPI2_IRQHandler ; SPI2 Interrupt
|
|
||||||
DCD USART1_IRQHandler ; USART1 Interrupt
|
|
||||||
DCD USART2_IRQHandler ; USART2 Interrupt
|
|
||||||
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
|
|
||||||
DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
|
|
||||||
DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
|
|
||||||
DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
|
|
||||||
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
|
|
||||||
DCD LPTIM3_IRQHandler ; LPTIM3 Interrupt
|
|
||||||
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD HSEM_IRQHandler ; HSEM0 Interrupt
|
|
||||||
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
|
|
||||||
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
|
|
||||||
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
|
|
||||||
DCD AES_IRQHandler ; AES Interrupt
|
|
||||||
DCD RNG_IRQHandler ; RNG1 Interrupt
|
|
||||||
DCD PKA_IRQHandler ; PKA Interrupt
|
|
||||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
|
|
||||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
|
|
||||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
|
|
||||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
|
|
||||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
|
|
||||||
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
|
|
||||||
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
|
|
||||||
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
|
|
||||||
|
|
||||||
__Vectors_End
|
|
||||||
|
|
||||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
|
||||||
|
|
||||||
AREA |.text|, CODE, READONLY
|
|
||||||
|
|
||||||
; Reset handler
|
|
||||||
Reset_Handler PROC
|
|
||||||
EXPORT Reset_Handler [WEAK]
|
|
||||||
IMPORT SystemInit
|
|
||||||
IMPORT __main
|
|
||||||
|
|
||||||
LDR R0, =SystemInit
|
|
||||||
BLX R0
|
|
||||||
LDR R0, =__main
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
|
||||||
|
|
||||||
NMI_Handler PROC
|
|
||||||
EXPORT NMI_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
HardFault_Handler\
|
|
||||||
PROC
|
|
||||||
EXPORT HardFault_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
MemManage_Handler\
|
|
||||||
PROC
|
|
||||||
EXPORT MemManage_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
BusFault_Handler\
|
|
||||||
PROC
|
|
||||||
EXPORT BusFault_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
UsageFault_Handler\
|
|
||||||
PROC
|
|
||||||
EXPORT UsageFault_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
SVC_Handler PROC
|
|
||||||
EXPORT SVC_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
DebugMon_Handler\
|
|
||||||
PROC
|
|
||||||
EXPORT DebugMon_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
PendSV_Handler PROC
|
|
||||||
EXPORT PendSV_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
SysTick_Handler PROC
|
|
||||||
EXPORT SysTick_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
Default_Handler PROC
|
|
||||||
|
|
||||||
EXPORT WWDG_IRQHandler [WEAK]
|
|
||||||
EXPORT PVD_PVM_IRQHandler [WEAK]
|
|
||||||
EXPORT TAMP_STAMP_LSECSS_SSRU_IRQHandler [WEAK]
|
|
||||||
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
|
||||||
EXPORT FLASH_IRQHandler [WEAK]
|
|
||||||
EXPORT RCC_IRQHandler [WEAK]
|
|
||||||
EXPORT EXTI0_IRQHandler [WEAK]
|
|
||||||
EXPORT EXTI1_IRQHandler [WEAK]
|
|
||||||
EXPORT EXTI2_IRQHandler [WEAK]
|
|
||||||
EXPORT EXTI3_IRQHandler [WEAK]
|
|
||||||
EXPORT EXTI4_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
|
||||||
EXPORT ADC_IRQHandler [WEAK]
|
|
||||||
EXPORT DAC_IRQHandler [WEAK]
|
|
||||||
EXPORT COMP_IRQHandler [WEAK]
|
|
||||||
EXPORT EXTI9_5_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM1_BRK_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM1_UP_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM1_CC_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM2_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM16_IRQHandler [WEAK]
|
|
||||||
EXPORT TIM17_IRQHandler [WEAK]
|
|
||||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
|
||||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
|
||||||
EXPORT I2C2_EV_IRQHandler [WEAK]
|
|
||||||
EXPORT I2C2_ER_IRQHandler [WEAK]
|
|
||||||
EXPORT SPI1_IRQHandler [WEAK]
|
|
||||||
EXPORT SPI2_IRQHandler [WEAK]
|
|
||||||
EXPORT USART1_IRQHandler [WEAK]
|
|
||||||
EXPORT USART2_IRQHandler [WEAK]
|
|
||||||
EXPORT LPUART1_IRQHandler [WEAK]
|
|
||||||
EXPORT LPTIM1_IRQHandler [WEAK]
|
|
||||||
EXPORT LPTIM2_IRQHandler [WEAK]
|
|
||||||
EXPORT EXTI15_10_IRQHandler [WEAK]
|
|
||||||
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
|
||||||
EXPORT LPTIM3_IRQHandler [WEAK]
|
|
||||||
EXPORT SUBGHZSPI_IRQHandler [WEAK]
|
|
||||||
EXPORT HSEM_IRQHandler [WEAK]
|
|
||||||
EXPORT I2C3_EV_IRQHandler [WEAK]
|
|
||||||
EXPORT I2C3_ER_IRQHandler [WEAK]
|
|
||||||
EXPORT SUBGHZ_Radio_IRQHandler [WEAK]
|
|
||||||
EXPORT AES_IRQHandler [WEAK]
|
|
||||||
EXPORT RNG_IRQHandler [WEAK]
|
|
||||||
EXPORT PKA_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA2_Channel1_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA2_Channel2_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA2_Channel3_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA2_Channel4_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA2_Channel5_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA2_Channel6_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA2_Channel7_IRQHandler [WEAK]
|
|
||||||
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
|
|
||||||
|
|
||||||
WWDG_IRQHandler
|
|
||||||
PVD_PVM_IRQHandler
|
|
||||||
TAMP_STAMP_LSECSS_SSRU_IRQHandler
|
|
||||||
RTC_WKUP_IRQHandler
|
|
||||||
FLASH_IRQHandler
|
|
||||||
RCC_IRQHandler
|
|
||||||
EXTI0_IRQHandler
|
|
||||||
EXTI1_IRQHandler
|
|
||||||
EXTI2_IRQHandler
|
|
||||||
EXTI3_IRQHandler
|
|
||||||
EXTI4_IRQHandler
|
|
||||||
DMA1_Channel1_IRQHandler
|
|
||||||
DMA1_Channel2_IRQHandler
|
|
||||||
DMA1_Channel3_IRQHandler
|
|
||||||
DMA1_Channel4_IRQHandler
|
|
||||||
DMA1_Channel5_IRQHandler
|
|
||||||
DMA1_Channel6_IRQHandler
|
|
||||||
DMA1_Channel7_IRQHandler
|
|
||||||
ADC_IRQHandler
|
|
||||||
DAC_IRQHandler
|
|
||||||
COMP_IRQHandler
|
|
||||||
EXTI9_5_IRQHandler
|
|
||||||
TIM1_BRK_IRQHandler
|
|
||||||
TIM1_UP_IRQHandler
|
|
||||||
TIM1_TRG_COM_IRQHandler
|
|
||||||
TIM1_CC_IRQHandler
|
|
||||||
TIM2_IRQHandler
|
|
||||||
TIM16_IRQHandler
|
|
||||||
TIM17_IRQHandler
|
|
||||||
I2C1_EV_IRQHandler
|
|
||||||
I2C1_ER_IRQHandler
|
|
||||||
I2C2_EV_IRQHandler
|
|
||||||
I2C2_ER_IRQHandler
|
|
||||||
SPI1_IRQHandler
|
|
||||||
SPI2_IRQHandler
|
|
||||||
USART1_IRQHandler
|
|
||||||
USART2_IRQHandler
|
|
||||||
LPUART1_IRQHandler
|
|
||||||
LPTIM1_IRQHandler
|
|
||||||
LPTIM2_IRQHandler
|
|
||||||
EXTI15_10_IRQHandler
|
|
||||||
RTC_Alarm_IRQHandler
|
|
||||||
LPTIM3_IRQHandler
|
|
||||||
SUBGHZSPI_IRQHandler
|
|
||||||
HSEM_IRQHandler
|
|
||||||
I2C3_EV_IRQHandler
|
|
||||||
I2C3_ER_IRQHandler
|
|
||||||
SUBGHZ_Radio_IRQHandler
|
|
||||||
AES_IRQHandler
|
|
||||||
RNG_IRQHandler
|
|
||||||
PKA_IRQHandler
|
|
||||||
DMA2_Channel1_IRQHandler
|
|
||||||
DMA2_Channel2_IRQHandler
|
|
||||||
DMA2_Channel3_IRQHandler
|
|
||||||
DMA2_Channel4_IRQHandler
|
|
||||||
DMA2_Channel5_IRQHandler
|
|
||||||
DMA2_Channel6_IRQHandler
|
|
||||||
DMA2_Channel7_IRQHandler
|
|
||||||
DMAMUX1_OVR_IRQHandler
|
|
||||||
|
|
||||||
B .
|
|
||||||
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
ALIGN
|
|
||||||
|
|
||||||
;*******************************************************************************
|
|
||||||
; User Stack and Heap initialization
|
|
||||||
;*******************************************************************************
|
|
||||||
IF :DEF:__MICROLIB
|
|
||||||
|
|
||||||
EXPORT __initial_sp
|
|
||||||
EXPORT __heap_base
|
|
||||||
EXPORT __heap_limit
|
|
||||||
|
|
||||||
ELSE
|
|
||||||
|
|
||||||
IMPORT __use_two_region_memory
|
|
||||||
EXPORT __user_initial_stackheap
|
|
||||||
|
|
||||||
__user_initial_stackheap
|
|
||||||
|
|
||||||
LDR R0, = Heap_Mem
|
|
||||||
LDR R1, =(Stack_Mem + Stack_Size)
|
|
||||||
LDR R2, = (Heap_Mem + Heap_Size)
|
|
||||||
LDR R3, = Stack_Mem
|
|
||||||
BX LR
|
|
||||||
|
|
||||||
ALIGN
|
|
||||||
|
|
||||||
ENDIF
|
|
||||||
|
|
||||||
END
|
|
||||||
|
|
||||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
|
||||||
|
|
@ -1,178 +0,0 @@
|
||||||
/*
|
|
||||||
** LinkerScript
|
|
||||||
** Note: For specific memory allocation, linker and startup files must be customized.
|
|
||||||
** Refer to STM32CubeIDE user guide (UM2609), chapter "Modify the linker script".
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Entry Point */
|
|
||||||
ENTRY(Reset_Handler)
|
|
||||||
|
|
||||||
/* Highest address of the user mode stack */
|
|
||||||
_estack = ORIGIN(RAM1) + LENGTH(RAM1); /* end of "SRAM1" Ram type memory */
|
|
||||||
|
|
||||||
_Min_Heap_Size = 0x200; /* required amount of heap */
|
|
||||||
_Min_Stack_Size = 0x400; /* required amount of stack */
|
|
||||||
|
|
||||||
/* Memories definition */
|
|
||||||
MEMORY
|
|
||||||
{
|
|
||||||
ROM (rx) : ORIGIN = 0x08020000, LENGTH = 128K /* Flash memory dedicated to CM0+ */
|
|
||||||
RAM1 (xrw) : ORIGIN = 0x20004000, LENGTH = 16K /* Non-backup SRAM1 dedicated to CM0+ */
|
|
||||||
RAM2 (xrw) : ORIGIN = 0x2000C000, LENGTH = 16K /* Backup SRAM2 dedicated to CM0+ */
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Sections */
|
|
||||||
SECTIONS
|
|
||||||
{
|
|
||||||
/* The startup code into "ROM" Rom type memory */
|
|
||||||
.isr_vector :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
KEEP(*(.isr_vector)) /* Startup code */
|
|
||||||
. = ALIGN(8);
|
|
||||||
} >ROM
|
|
||||||
|
|
||||||
/* The program code and other data into "ROM" Rom type memory */
|
|
||||||
.text :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
*(.text) /* .text sections (code) */
|
|
||||||
*(.text*) /* .text* sections (code) */
|
|
||||||
*(.glue_7) /* glue arm to thumb code */
|
|
||||||
*(.glue_7t) /* glue thumb to arm code */
|
|
||||||
*(.eh_frame)
|
|
||||||
|
|
||||||
KEEP (*(.init))
|
|
||||||
KEEP (*(.fini))
|
|
||||||
|
|
||||||
. = ALIGN(8);
|
|
||||||
_etext = .; /* define a global symbols at end of code */
|
|
||||||
} >ROM
|
|
||||||
|
|
||||||
/* Constant data into "ROM" Rom type memory */
|
|
||||||
.rodata :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
|
||||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
|
||||||
. = ALIGN(8);
|
|
||||||
} >ROM
|
|
||||||
|
|
||||||
.ARM.extab : {
|
|
||||||
. = ALIGN(8);
|
|
||||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
|
||||||
. = ALIGN(8);
|
|
||||||
} >ROM
|
|
||||||
|
|
||||||
.ARM : {
|
|
||||||
. = ALIGN(8);
|
|
||||||
__exidx_start = .;
|
|
||||||
*(.ARM.exidx*)
|
|
||||||
__exidx_end = .;
|
|
||||||
. = ALIGN(8);
|
|
||||||
} >ROM
|
|
||||||
|
|
||||||
.preinit_array :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
|
||||||
KEEP (*(.preinit_array*))
|
|
||||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
|
||||||
. = ALIGN(8);
|
|
||||||
} >ROM
|
|
||||||
|
|
||||||
.init_array :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
PROVIDE_HIDDEN (__init_array_start = .);
|
|
||||||
KEEP (*(SORT(.init_array.*)))
|
|
||||||
KEEP (*(.init_array*))
|
|
||||||
PROVIDE_HIDDEN (__init_array_end = .);
|
|
||||||
. = ALIGN(8);
|
|
||||||
} >ROM
|
|
||||||
|
|
||||||
.fini_array :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
|
||||||
KEEP (*(SORT(.fini_array.*)))
|
|
||||||
KEEP (*(.fini_array*))
|
|
||||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
|
||||||
. = ALIGN(8);
|
|
||||||
} >ROM
|
|
||||||
|
|
||||||
/* Used by the startup to initialize data */
|
|
||||||
_sidata = LOADADDR(.data);
|
|
||||||
|
|
||||||
/* Initialized data sections into "SRAM1" Ram type memory */
|
|
||||||
.data :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
_sdata = .; /* create a global symbol at data start */
|
|
||||||
*(.data) /* .data sections */
|
|
||||||
*(.data*) /* .data* sections */
|
|
||||||
|
|
||||||
. = ALIGN(8);
|
|
||||||
_edata = .; /* define a global symbol at data end */
|
|
||||||
|
|
||||||
} >RAM1 AT> ROM
|
|
||||||
|
|
||||||
/* Uninitialized data section into "SRAM1" Ram type memory */
|
|
||||||
. = ALIGN(8);
|
|
||||||
.bss :
|
|
||||||
{
|
|
||||||
/* This is used by the startup in order to initialize the .bss section */
|
|
||||||
_sbss = .; /* define a global symbol at bss start */
|
|
||||||
__bss_start__ = _sbss;
|
|
||||||
*(.bss)
|
|
||||||
*(.bss*)
|
|
||||||
*(COMMON)
|
|
||||||
|
|
||||||
. = ALIGN(8);
|
|
||||||
_ebss = .; /* define a global symbol at bss end */
|
|
||||||
__bss_end__ = _ebss;
|
|
||||||
} >RAM1
|
|
||||||
|
|
||||||
/* Data section into "SRAM1" Ram type memory: Non-backup SRAM1 dedicated to CM0+ */
|
|
||||||
. = ALIGN(8);
|
|
||||||
RAM1_region :
|
|
||||||
{
|
|
||||||
_sRAM1_region = .; /* define a global symbol at section start */
|
|
||||||
*(.RAM1_region)
|
|
||||||
|
|
||||||
. = ALIGN(8);
|
|
||||||
_eRAM1_region = .; /* define a global symbol at section end */
|
|
||||||
} >RAM1
|
|
||||||
|
|
||||||
/* Data section into "SRAM2" Ram type memory: Backup SRAM2 dedicated to CM0+ */
|
|
||||||
. = ALIGN(8);
|
|
||||||
RAM2_region :
|
|
||||||
{
|
|
||||||
_sRAM2_region = .; /* define a global symbol at section start */
|
|
||||||
*(.RAM2_region)
|
|
||||||
|
|
||||||
. = ALIGN(8);
|
|
||||||
_eRAM2_region = .; /* define a global symbol at section end */
|
|
||||||
} >RAM2
|
|
||||||
|
|
||||||
/* User_heap_stack section, used to check that there is enough "SRAM1" Ram type memory left */
|
|
||||||
._user_heap_stack :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
PROVIDE ( end = . );
|
|
||||||
PROVIDE ( _end = . );
|
|
||||||
. = . + _Min_Heap_Size;
|
|
||||||
. = . + _Min_Stack_Size;
|
|
||||||
. = ALIGN(8);
|
|
||||||
} >RAM1
|
|
||||||
|
|
||||||
/* Remove information from the compiler libraries */
|
|
||||||
/DISCARD/ :
|
|
||||||
{
|
|
||||||
libc.a ( * )
|
|
||||||
libm.a ( * )
|
|
||||||
libgcc.a ( * )
|
|
||||||
}
|
|
||||||
|
|
||||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
|
||||||
}
|
|
||||||
|
|
@ -1,178 +0,0 @@
|
||||||
/*
|
|
||||||
** LinkerScript
|
|
||||||
** Note: For specific memory allocation, linker and startup files must be customized.
|
|
||||||
** Refer to STM32CubeIDE user guide (UM2609), chapter "Modify the linker script".
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Entry Point */
|
|
||||||
ENTRY(Reset_Handler)
|
|
||||||
|
|
||||||
/* Highest address of the user mode stack */
|
|
||||||
_estack = ORIGIN(RAM1) + LENGTH(RAM1); /* end of "SRAM1" Ram type memory */
|
|
||||||
|
|
||||||
_Min_Heap_Size = 0x200; /* required amount of heap */
|
|
||||||
_Min_Stack_Size = 0x400; /* required amount of stack */
|
|
||||||
|
|
||||||
/* Memories definition */
|
|
||||||
MEMORY
|
|
||||||
{
|
|
||||||
ROM (rx) : ORIGIN = 0x08000000, LENGTH = 128K /* Flash memory dedicated to CM4 */
|
|
||||||
RAM1 (xrw) : ORIGIN = 0x20000000, LENGTH = 16K /* Non-backup SRAM1 dedicated to CM4 */
|
|
||||||
RAM2 (xrw) : ORIGIN = 0x20008000, LENGTH = 16K /* Backup SRAM2 dedicated to CM4 */
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Sections */
|
|
||||||
SECTIONS
|
|
||||||
{
|
|
||||||
/* The startup code into "ROM" Rom type memory */
|
|
||||||
.isr_vector :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
KEEP(*(.isr_vector)) /* Startup code */
|
|
||||||
. = ALIGN(8);
|
|
||||||
} >ROM
|
|
||||||
|
|
||||||
/* The program code and other data into "ROM" Rom type memory */
|
|
||||||
.text :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
*(.text) /* .text sections (code) */
|
|
||||||
*(.text*) /* .text* sections (code) */
|
|
||||||
*(.glue_7) /* glue arm to thumb code */
|
|
||||||
*(.glue_7t) /* glue thumb to arm code */
|
|
||||||
*(.eh_frame)
|
|
||||||
|
|
||||||
KEEP (*(.init))
|
|
||||||
KEEP (*(.fini))
|
|
||||||
|
|
||||||
. = ALIGN(8);
|
|
||||||
_etext = .; /* define a global symbols at end of code */
|
|
||||||
} >ROM
|
|
||||||
|
|
||||||
/* Constant data into "ROM" Rom type memory */
|
|
||||||
.rodata :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
|
||||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
|
||||||
. = ALIGN(8);
|
|
||||||
} >ROM
|
|
||||||
|
|
||||||
.ARM.extab : {
|
|
||||||
. = ALIGN(8);
|
|
||||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
|
||||||
. = ALIGN(8);
|
|
||||||
} >ROM
|
|
||||||
|
|
||||||
.ARM : {
|
|
||||||
. = ALIGN(8);
|
|
||||||
__exidx_start = .;
|
|
||||||
*(.ARM.exidx*)
|
|
||||||
__exidx_end = .;
|
|
||||||
. = ALIGN(8);
|
|
||||||
} >ROM
|
|
||||||
|
|
||||||
.preinit_array :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
|
||||||
KEEP (*(.preinit_array*))
|
|
||||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
|
||||||
. = ALIGN(8);
|
|
||||||
} >ROM
|
|
||||||
|
|
||||||
.init_array :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
PROVIDE_HIDDEN (__init_array_start = .);
|
|
||||||
KEEP (*(SORT(.init_array.*)))
|
|
||||||
KEEP (*(.init_array*))
|
|
||||||
PROVIDE_HIDDEN (__init_array_end = .);
|
|
||||||
. = ALIGN(8);
|
|
||||||
} >ROM
|
|
||||||
|
|
||||||
.fini_array :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
|
||||||
KEEP (*(SORT(.fini_array.*)))
|
|
||||||
KEEP (*(.fini_array*))
|
|
||||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
|
||||||
. = ALIGN(8);
|
|
||||||
} >ROM
|
|
||||||
|
|
||||||
/* Used by the startup to initialize data */
|
|
||||||
_sidata = LOADADDR(.data);
|
|
||||||
|
|
||||||
/* Initialized data sections into "SRAM1" Ram type memory */
|
|
||||||
.data :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
_sdata = .; /* create a global symbol at data start */
|
|
||||||
*(.data) /* .data sections */
|
|
||||||
*(.data*) /* .data* sections */
|
|
||||||
|
|
||||||
. = ALIGN(8);
|
|
||||||
_edata = .; /* define a global symbol at data end */
|
|
||||||
|
|
||||||
} >RAM1 AT> ROM
|
|
||||||
|
|
||||||
/* Uninitialized data section into "SRAM1" Ram type memory */
|
|
||||||
. = ALIGN(8);
|
|
||||||
.bss :
|
|
||||||
{
|
|
||||||
/* This is used by the startup in order to initialize the .bss section */
|
|
||||||
_sbss = .; /* define a global symbol at bss start */
|
|
||||||
__bss_start__ = _sbss;
|
|
||||||
*(.bss)
|
|
||||||
*(.bss*)
|
|
||||||
*(COMMON)
|
|
||||||
|
|
||||||
. = ALIGN(8);
|
|
||||||
_ebss = .; /* define a global symbol at bss end */
|
|
||||||
__bss_end__ = _ebss;
|
|
||||||
} >RAM1
|
|
||||||
|
|
||||||
/* Data section into "SRAM1" Ram type memory: Non-backup SRAM1 dedicated to CM4 */
|
|
||||||
. = ALIGN(8);
|
|
||||||
RAM1_region :
|
|
||||||
{
|
|
||||||
_sRAM1_region = .; /* define a global symbol at section start */
|
|
||||||
*(.RAM1_region)
|
|
||||||
|
|
||||||
. = ALIGN(8);
|
|
||||||
_eRAM1_region = .; /* define a global symbol at section end */
|
|
||||||
} >RAM1
|
|
||||||
|
|
||||||
/* Data section into "SRAM2" Ram type memory: Backup SRAM2 dedicated to CM4 */
|
|
||||||
. = ALIGN(8);
|
|
||||||
RAM2_region :
|
|
||||||
{
|
|
||||||
_sRAM2_region = .; /* define a global symbol at section start */
|
|
||||||
*(.RAM2_region)
|
|
||||||
|
|
||||||
. = ALIGN(8);
|
|
||||||
_eRAM2_region = .; /* define a global symbol at section end */
|
|
||||||
} >RAM2
|
|
||||||
|
|
||||||
/* User_heap_stack section, used to check that there is enough "SRAM1" Ram type memory left */
|
|
||||||
._user_heap_stack :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
PROVIDE ( end = . );
|
|
||||||
PROVIDE ( _end = . );
|
|
||||||
. = . + _Min_Heap_Size;
|
|
||||||
. = . + _Min_Stack_Size;
|
|
||||||
. = ALIGN(8);
|
|
||||||
} >RAM1
|
|
||||||
|
|
||||||
/* Remove information from the compiler libraries */
|
|
||||||
/DISCARD/ :
|
|
||||||
{
|
|
||||||
libc.a ( * )
|
|
||||||
libm.a ( * )
|
|
||||||
libgcc.a ( * )
|
|
||||||
}
|
|
||||||
|
|
||||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
|
||||||
}
|
|
||||||
|
|
@ -1,178 +0,0 @@
|
||||||
/*
|
|
||||||
** LinkerScript
|
|
||||||
** Note: For specific memory allocation, linker and startup files must be customized.
|
|
||||||
** Refer to STM32CubeIDE user guide (UM2609), chapter "Modify the linker script".
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Entry Point */
|
|
||||||
ENTRY(Reset_Handler)
|
|
||||||
|
|
||||||
/* Highest address of the user mode stack */
|
|
||||||
_estack = ORIGIN(RAM1) + LENGTH(RAM1); /* end of "SRAM1" Ram type memory */
|
|
||||||
|
|
||||||
_Min_Heap_Size = 0x200; /* required amount of heap */
|
|
||||||
_Min_Stack_Size = 0x400; /* required amount of stack */
|
|
||||||
|
|
||||||
/* Memories definition */
|
|
||||||
MEMORY
|
|
||||||
{
|
|
||||||
ROM (rx) : ORIGIN = 0x08020000, LENGTH = 128K /* Flash memory dedicated to CM0+ */
|
|
||||||
RAM1 (xrw) : ORIGIN = 0x20004000, LENGTH = 16K /* Non-backup SRAM1 dedicated to CM0+ */
|
|
||||||
RAM2 (xrw) : ORIGIN = 0x2000C000, LENGTH = 16K /* Backup SRAM2 dedicated to CM0+ */
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Sections */
|
|
||||||
SECTIONS
|
|
||||||
{
|
|
||||||
/* The startup code into "ROM" Rom type memory */
|
|
||||||
.isr_vector :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
KEEP(*(.isr_vector)) /* Startup code */
|
|
||||||
. = ALIGN(8);
|
|
||||||
} >ROM
|
|
||||||
|
|
||||||
/* The program code and other data into "ROM" Rom type memory */
|
|
||||||
.text :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
*(.text) /* .text sections (code) */
|
|
||||||
*(.text*) /* .text* sections (code) */
|
|
||||||
*(.glue_7) /* glue arm to thumb code */
|
|
||||||
*(.glue_7t) /* glue thumb to arm code */
|
|
||||||
*(.eh_frame)
|
|
||||||
|
|
||||||
KEEP (*(.init))
|
|
||||||
KEEP (*(.fini))
|
|
||||||
|
|
||||||
. = ALIGN(8);
|
|
||||||
_etext = .; /* define a global symbols at end of code */
|
|
||||||
} >ROM
|
|
||||||
|
|
||||||
/* Constant data into "ROM" Rom type memory */
|
|
||||||
.rodata :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
|
||||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
|
||||||
. = ALIGN(8);
|
|
||||||
} >ROM
|
|
||||||
|
|
||||||
.ARM.extab : {
|
|
||||||
. = ALIGN(8);
|
|
||||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
|
||||||
. = ALIGN(8);
|
|
||||||
} >ROM
|
|
||||||
|
|
||||||
.ARM : {
|
|
||||||
. = ALIGN(8);
|
|
||||||
__exidx_start = .;
|
|
||||||
*(.ARM.exidx*)
|
|
||||||
__exidx_end = .;
|
|
||||||
. = ALIGN(8);
|
|
||||||
} >ROM
|
|
||||||
|
|
||||||
.preinit_array :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
|
||||||
KEEP (*(.preinit_array*))
|
|
||||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
|
||||||
. = ALIGN(8);
|
|
||||||
} >ROM
|
|
||||||
|
|
||||||
.init_array :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
PROVIDE_HIDDEN (__init_array_start = .);
|
|
||||||
KEEP (*(SORT(.init_array.*)))
|
|
||||||
KEEP (*(.init_array*))
|
|
||||||
PROVIDE_HIDDEN (__init_array_end = .);
|
|
||||||
. = ALIGN(8);
|
|
||||||
} >ROM
|
|
||||||
|
|
||||||
.fini_array :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
|
||||||
KEEP (*(SORT(.fini_array.*)))
|
|
||||||
KEEP (*(.fini_array*))
|
|
||||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
|
||||||
. = ALIGN(8);
|
|
||||||
} >ROM
|
|
||||||
|
|
||||||
/* Used by the startup to initialize data */
|
|
||||||
_sidata = LOADADDR(.data);
|
|
||||||
|
|
||||||
/* Initialized data sections into "SRAM1" Ram type memory */
|
|
||||||
.data :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
_sdata = .; /* create a global symbol at data start */
|
|
||||||
*(.data) /* .data sections */
|
|
||||||
*(.data*) /* .data* sections */
|
|
||||||
|
|
||||||
. = ALIGN(8);
|
|
||||||
_edata = .; /* define a global symbol at data end */
|
|
||||||
|
|
||||||
} >RAM1 AT> ROM
|
|
||||||
|
|
||||||
/* Uninitialized data section into "SRAM1" Ram type memory */
|
|
||||||
. = ALIGN(8);
|
|
||||||
.bss :
|
|
||||||
{
|
|
||||||
/* This is used by the startup in order to initialize the .bss section */
|
|
||||||
_sbss = .; /* define a global symbol at bss start */
|
|
||||||
__bss_start__ = _sbss;
|
|
||||||
*(.bss)
|
|
||||||
*(.bss*)
|
|
||||||
*(COMMON)
|
|
||||||
|
|
||||||
. = ALIGN(8);
|
|
||||||
_ebss = .; /* define a global symbol at bss end */
|
|
||||||
__bss_end__ = _ebss;
|
|
||||||
} >RAM1
|
|
||||||
|
|
||||||
/* Data section into "SRAM1" Ram type memory: Non-backup SRAM1 dedicated to CM0+ */
|
|
||||||
. = ALIGN(8);
|
|
||||||
RAM1_region :
|
|
||||||
{
|
|
||||||
_sRAM1_region = .; /* define a global symbol at section start */
|
|
||||||
*(.RAM1_region)
|
|
||||||
|
|
||||||
. = ALIGN(8);
|
|
||||||
_eRAM1_region = .; /* define a global symbol at section end */
|
|
||||||
} >RAM1
|
|
||||||
|
|
||||||
/* Data section into "SRAM2" Ram type memory: Backup SRAM2 dedicated to CM0+ */
|
|
||||||
. = ALIGN(8);
|
|
||||||
RAM2_region :
|
|
||||||
{
|
|
||||||
_sRAM2_region = .; /* define a global symbol at section start */
|
|
||||||
*(.RAM2_region)
|
|
||||||
|
|
||||||
. = ALIGN(8);
|
|
||||||
_eRAM2_region = .; /* define a global symbol at section end */
|
|
||||||
} >RAM2
|
|
||||||
|
|
||||||
/* User_heap_stack section, used to check that there is enough "SRAM1" Ram type memory left */
|
|
||||||
._user_heap_stack :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
PROVIDE ( end = . );
|
|
||||||
PROVIDE ( _end = . );
|
|
||||||
. = . + _Min_Heap_Size;
|
|
||||||
. = . + _Min_Stack_Size;
|
|
||||||
. = ALIGN(8);
|
|
||||||
} >RAM1
|
|
||||||
|
|
||||||
/* Remove information from the compiler libraries */
|
|
||||||
/DISCARD/ :
|
|
||||||
{
|
|
||||||
libc.a ( * )
|
|
||||||
libm.a ( * )
|
|
||||||
libgcc.a ( * )
|
|
||||||
}
|
|
||||||
|
|
||||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
|
||||||
}
|
|
||||||
|
|
@ -1,178 +0,0 @@
|
||||||
/*
|
|
||||||
** LinkerScript
|
|
||||||
** Note: For specific memory allocation, linker and startup files must be customized.
|
|
||||||
** Refer to STM32CubeIDE user guide (UM2609), chapter "Modify the linker script".
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Entry Point */
|
|
||||||
ENTRY(Reset_Handler)
|
|
||||||
|
|
||||||
/* Highest address of the user mode stack */
|
|
||||||
_estack = ORIGIN(RAM1) + LENGTH(RAM1); /* end of "SRAM1" Ram type memory */
|
|
||||||
|
|
||||||
_Min_Heap_Size = 0x200; /* required amount of heap */
|
|
||||||
_Min_Stack_Size = 0x400; /* required amount of stack */
|
|
||||||
|
|
||||||
/* Memories definition */
|
|
||||||
MEMORY
|
|
||||||
{
|
|
||||||
ROM (rx) : ORIGIN = 0x08000000, LENGTH = 128K /* Flash memory dedicated to CM4 */
|
|
||||||
RAM1 (xrw) : ORIGIN = 0x20000000, LENGTH = 16K /* Non-backup SRAM1 dedicated to CM4 */
|
|
||||||
RAM2 (xrw) : ORIGIN = 0x20008000, LENGTH = 16K /* Backup SRAM2 dedicated to CM4 */
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Sections */
|
|
||||||
SECTIONS
|
|
||||||
{
|
|
||||||
/* The startup code into "ROM" Rom type memory */
|
|
||||||
.isr_vector :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
KEEP(*(.isr_vector)) /* Startup code */
|
|
||||||
. = ALIGN(8);
|
|
||||||
} >ROM
|
|
||||||
|
|
||||||
/* The program code and other data into "ROM" Rom type memory */
|
|
||||||
.text :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
*(.text) /* .text sections (code) */
|
|
||||||
*(.text*) /* .text* sections (code) */
|
|
||||||
*(.glue_7) /* glue arm to thumb code */
|
|
||||||
*(.glue_7t) /* glue thumb to arm code */
|
|
||||||
*(.eh_frame)
|
|
||||||
|
|
||||||
KEEP (*(.init))
|
|
||||||
KEEP (*(.fini))
|
|
||||||
|
|
||||||
. = ALIGN(8);
|
|
||||||
_etext = .; /* define a global symbols at end of code */
|
|
||||||
} >ROM
|
|
||||||
|
|
||||||
/* Constant data into "ROM" Rom type memory */
|
|
||||||
.rodata :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
|
||||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
|
||||||
. = ALIGN(8);
|
|
||||||
} >ROM
|
|
||||||
|
|
||||||
.ARM.extab : {
|
|
||||||
. = ALIGN(8);
|
|
||||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
|
||||||
. = ALIGN(8);
|
|
||||||
} >ROM
|
|
||||||
|
|
||||||
.ARM : {
|
|
||||||
. = ALIGN(8);
|
|
||||||
__exidx_start = .;
|
|
||||||
*(.ARM.exidx*)
|
|
||||||
__exidx_end = .;
|
|
||||||
. = ALIGN(8);
|
|
||||||
} >ROM
|
|
||||||
|
|
||||||
.preinit_array :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
|
||||||
KEEP (*(.preinit_array*))
|
|
||||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
|
||||||
. = ALIGN(8);
|
|
||||||
} >ROM
|
|
||||||
|
|
||||||
.init_array :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
PROVIDE_HIDDEN (__init_array_start = .);
|
|
||||||
KEEP (*(SORT(.init_array.*)))
|
|
||||||
KEEP (*(.init_array*))
|
|
||||||
PROVIDE_HIDDEN (__init_array_end = .);
|
|
||||||
. = ALIGN(8);
|
|
||||||
} >ROM
|
|
||||||
|
|
||||||
.fini_array :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
|
||||||
KEEP (*(SORT(.fini_array.*)))
|
|
||||||
KEEP (*(.fini_array*))
|
|
||||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
|
||||||
. = ALIGN(8);
|
|
||||||
} >ROM
|
|
||||||
|
|
||||||
/* Used by the startup to initialize data */
|
|
||||||
_sidata = LOADADDR(.data);
|
|
||||||
|
|
||||||
/* Initialized data sections into "SRAM1" Ram type memory */
|
|
||||||
.data :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
_sdata = .; /* create a global symbol at data start */
|
|
||||||
*(.data) /* .data sections */
|
|
||||||
*(.data*) /* .data* sections */
|
|
||||||
|
|
||||||
. = ALIGN(8);
|
|
||||||
_edata = .; /* define a global symbol at data end */
|
|
||||||
|
|
||||||
} >RAM1 AT> ROM
|
|
||||||
|
|
||||||
/* Uninitialized data section into "SRAM1" Ram type memory */
|
|
||||||
. = ALIGN(8);
|
|
||||||
.bss :
|
|
||||||
{
|
|
||||||
/* This is used by the startup in order to initialize the .bss section */
|
|
||||||
_sbss = .; /* define a global symbol at bss start */
|
|
||||||
__bss_start__ = _sbss;
|
|
||||||
*(.bss)
|
|
||||||
*(.bss*)
|
|
||||||
*(COMMON)
|
|
||||||
|
|
||||||
. = ALIGN(8);
|
|
||||||
_ebss = .; /* define a global symbol at bss end */
|
|
||||||
__bss_end__ = _ebss;
|
|
||||||
} >RAM1
|
|
||||||
|
|
||||||
/* Data section into "SRAM1" Ram type memory: Non-backup SRAM1 dedicated to CM4 */
|
|
||||||
. = ALIGN(8);
|
|
||||||
RAM1_region :
|
|
||||||
{
|
|
||||||
_sRAM1_region = .; /* define a global symbol at section start */
|
|
||||||
*(.RAM1_region)
|
|
||||||
|
|
||||||
. = ALIGN(8);
|
|
||||||
_eRAM1_region = .; /* define a global symbol at section end */
|
|
||||||
} >RAM1
|
|
||||||
|
|
||||||
/* Data section into "SRAM2" Ram type memory: Backup SRAM2 dedicated to CM4 */
|
|
||||||
. = ALIGN(8);
|
|
||||||
RAM2_region :
|
|
||||||
{
|
|
||||||
_sRAM2_region = .; /* define a global symbol at section start */
|
|
||||||
*(.RAM2_region)
|
|
||||||
|
|
||||||
. = ALIGN(8);
|
|
||||||
_eRAM2_region = .; /* define a global symbol at section end */
|
|
||||||
} >RAM2
|
|
||||||
|
|
||||||
/* User_heap_stack section, used to check that there is enough "SRAM1" Ram type memory left */
|
|
||||||
._user_heap_stack :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
PROVIDE ( end = . );
|
|
||||||
PROVIDE ( _end = . );
|
|
||||||
. = . + _Min_Heap_Size;
|
|
||||||
. = . + _Min_Stack_Size;
|
|
||||||
. = ALIGN(8);
|
|
||||||
} >RAM1
|
|
||||||
|
|
||||||
/* Remove information from the compiler libraries */
|
|
||||||
/DISCARD/ :
|
|
||||||
{
|
|
||||||
libc.a ( * )
|
|
||||||
libm.a ( * )
|
|
||||||
libgcc.a ( * )
|
|
||||||
}
|
|
||||||
|
|
||||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
|
||||||
}
|
|
||||||
|
|
@ -1,178 +0,0 @@
|
||||||
/*
|
|
||||||
** LinkerScript
|
|
||||||
** Note: For specific memory allocation, linker and startup files must be customized.
|
|
||||||
** Refer to STM32CubeIDE user guide (UM2609), chapter "Modify the linker script".
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Entry Point */
|
|
||||||
ENTRY(Reset_Handler)
|
|
||||||
|
|
||||||
/* Highest address of the user mode stack */
|
|
||||||
_estack = ORIGIN(RAM1) + LENGTH(RAM1); /* end of "SRAM1" Ram type memory */
|
|
||||||
|
|
||||||
_Min_Heap_Size = 0x200; /* required amount of heap */
|
|
||||||
_Min_Stack_Size = 0x400; /* required amount of stack */
|
|
||||||
|
|
||||||
/* Memories definition */
|
|
||||||
MEMORY
|
|
||||||
{
|
|
||||||
ROM (rx) : ORIGIN = 0x08000000, LENGTH = 256K
|
|
||||||
RAM1 (xrw) : ORIGIN = 0x20000000, LENGTH = 32K /* Non-backup SRAM1 */
|
|
||||||
RAM2 (xrw) : ORIGIN = 0x20008000, LENGTH = 32K /* Backup SRAM2 */
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Sections */
|
|
||||||
SECTIONS
|
|
||||||
{
|
|
||||||
/* The startup code into "ROM" Rom type memory */
|
|
||||||
.isr_vector :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
KEEP(*(.isr_vector)) /* Startup code */
|
|
||||||
. = ALIGN(8);
|
|
||||||
} >ROM
|
|
||||||
|
|
||||||
/* The program code and other data into "ROM" Rom type memory */
|
|
||||||
.text :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
*(.text) /* .text sections (code) */
|
|
||||||
*(.text*) /* .text* sections (code) */
|
|
||||||
*(.glue_7) /* glue arm to thumb code */
|
|
||||||
*(.glue_7t) /* glue thumb to arm code */
|
|
||||||
*(.eh_frame)
|
|
||||||
|
|
||||||
KEEP (*(.init))
|
|
||||||
KEEP (*(.fini))
|
|
||||||
|
|
||||||
. = ALIGN(8);
|
|
||||||
_etext = .; /* define a global symbols at end of code */
|
|
||||||
} >ROM
|
|
||||||
|
|
||||||
/* Constant data into "ROM" Rom type memory */
|
|
||||||
.rodata :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
|
||||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
|
||||||
. = ALIGN(8);
|
|
||||||
} >ROM
|
|
||||||
|
|
||||||
.ARM.extab : {
|
|
||||||
. = ALIGN(8);
|
|
||||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
|
||||||
. = ALIGN(8);
|
|
||||||
} >ROM
|
|
||||||
|
|
||||||
.ARM : {
|
|
||||||
. = ALIGN(8);
|
|
||||||
__exidx_start = .;
|
|
||||||
*(.ARM.exidx*)
|
|
||||||
__exidx_end = .;
|
|
||||||
. = ALIGN(8);
|
|
||||||
} >ROM
|
|
||||||
|
|
||||||
.preinit_array :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
|
||||||
KEEP (*(.preinit_array*))
|
|
||||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
|
||||||
. = ALIGN(8);
|
|
||||||
} >ROM
|
|
||||||
|
|
||||||
.init_array :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
PROVIDE_HIDDEN (__init_array_start = .);
|
|
||||||
KEEP (*(SORT(.init_array.*)))
|
|
||||||
KEEP (*(.init_array*))
|
|
||||||
PROVIDE_HIDDEN (__init_array_end = .);
|
|
||||||
. = ALIGN(8);
|
|
||||||
} >ROM
|
|
||||||
|
|
||||||
.fini_array :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
|
||||||
KEEP (*(SORT(.fini_array.*)))
|
|
||||||
KEEP (*(.fini_array*))
|
|
||||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
|
||||||
. = ALIGN(8);
|
|
||||||
} >ROM
|
|
||||||
|
|
||||||
/* Used by the startup to initialize data */
|
|
||||||
_sidata = LOADADDR(.data);
|
|
||||||
|
|
||||||
/* Initialized data sections into "SRAM1" Ram type memory */
|
|
||||||
.data :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
_sdata = .; /* create a global symbol at data start */
|
|
||||||
*(.data) /* .data sections */
|
|
||||||
*(.data*) /* .data* sections */
|
|
||||||
|
|
||||||
. = ALIGN(8);
|
|
||||||
_edata = .; /* define a global symbol at data end */
|
|
||||||
|
|
||||||
} >RAM1 AT> ROM
|
|
||||||
|
|
||||||
/* Uninitialized data section into "SRAM1" Ram type memory */
|
|
||||||
. = ALIGN(8);
|
|
||||||
.bss :
|
|
||||||
{
|
|
||||||
/* This is used by the startup in order to initialize the .bss section */
|
|
||||||
_sbss = .; /* define a global symbol at bss start */
|
|
||||||
__bss_start__ = _sbss;
|
|
||||||
*(.bss)
|
|
||||||
*(.bss*)
|
|
||||||
*(COMMON)
|
|
||||||
|
|
||||||
. = ALIGN(8);
|
|
||||||
_ebss = .; /* define a global symbol at bss end */
|
|
||||||
__bss_end__ = _ebss;
|
|
||||||
} >RAM1
|
|
||||||
|
|
||||||
/* Data section into "SRAM1" Ram type memory: Non-backup SRAM1 dedicated to CM4 */
|
|
||||||
. = ALIGN(8);
|
|
||||||
RAM1_region :
|
|
||||||
{
|
|
||||||
_sRAM1_region = .; /* define a global symbol at section start */
|
|
||||||
*(.RAM1_region)
|
|
||||||
|
|
||||||
. = ALIGN(8);
|
|
||||||
_eRAM1_region = .; /* define a global symbol at section end */
|
|
||||||
} >RAM1
|
|
||||||
|
|
||||||
/* Data section into "SRAM2" Ram type memory: Backup SRAM2 dedicated to CM4 */
|
|
||||||
. = ALIGN(8);
|
|
||||||
RAM2_region :
|
|
||||||
{
|
|
||||||
_sRAM2_region = .; /* define a global symbol at section start */
|
|
||||||
*(.RAM2_region)
|
|
||||||
|
|
||||||
. = ALIGN(8);
|
|
||||||
_eRAM2_region = .; /* define a global symbol at section end */
|
|
||||||
} >RAM2
|
|
||||||
|
|
||||||
/* User_heap_stack section, used to check that there is enough "SRAM1" Ram type memory left */
|
|
||||||
._user_heap_stack :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
PROVIDE ( end = . );
|
|
||||||
PROVIDE ( _end = . );
|
|
||||||
. = . + _Min_Heap_Size;
|
|
||||||
. = . + _Min_Stack_Size;
|
|
||||||
. = ALIGN(8);
|
|
||||||
} >RAM1
|
|
||||||
|
|
||||||
/* Remove information from the compiler libraries */
|
|
||||||
/DISCARD/ :
|
|
||||||
{
|
|
||||||
libc.a ( * )
|
|
||||||
libm.a ( * )
|
|
||||||
libgcc.a ( * )
|
|
||||||
}
|
|
||||||
|
|
||||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
|
||||||
}
|
|
||||||
|
|
@ -1,178 +0,0 @@
|
||||||
/*
|
|
||||||
** LinkerScript
|
|
||||||
** Note: For specific memory allocation, linker and startup files must be customized.
|
|
||||||
** Refer to STM32CubeIDE user guide (UM2609), chapter "Modify the linker script".
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Entry Point */
|
|
||||||
ENTRY(Reset_Handler)
|
|
||||||
|
|
||||||
/* Highest address of the user mode stack */
|
|
||||||
_estack = ORIGIN(RAM1) + LENGTH(RAM1); /* end of "SRAM1" Ram type memory */
|
|
||||||
|
|
||||||
_Min_Heap_Size = 0x200; /* required amount of heap */
|
|
||||||
_Min_Stack_Size = 0x400; /* required amount of stack */
|
|
||||||
|
|
||||||
/* Memories definition */
|
|
||||||
MEMORY
|
|
||||||
{
|
|
||||||
ROM (rx) : ORIGIN = 0x08000000, LENGTH = 256K
|
|
||||||
RAM1 (xrw) : ORIGIN = 0x20000000, LENGTH = 32K /* Non-backup SRAM1 */
|
|
||||||
RAM2 (xrw) : ORIGIN = 0x20008000, LENGTH = 32K /* Backup SRAM2 */
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Sections */
|
|
||||||
SECTIONS
|
|
||||||
{
|
|
||||||
/* The startup code into "ROM" Rom type memory */
|
|
||||||
.isr_vector :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
KEEP(*(.isr_vector)) /* Startup code */
|
|
||||||
. = ALIGN(8);
|
|
||||||
} >ROM
|
|
||||||
|
|
||||||
/* The program code and other data into "ROM" Rom type memory */
|
|
||||||
.text :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
*(.text) /* .text sections (code) */
|
|
||||||
*(.text*) /* .text* sections (code) */
|
|
||||||
*(.glue_7) /* glue arm to thumb code */
|
|
||||||
*(.glue_7t) /* glue thumb to arm code */
|
|
||||||
*(.eh_frame)
|
|
||||||
|
|
||||||
KEEP (*(.init))
|
|
||||||
KEEP (*(.fini))
|
|
||||||
|
|
||||||
. = ALIGN(8);
|
|
||||||
_etext = .; /* define a global symbols at end of code */
|
|
||||||
} >ROM
|
|
||||||
|
|
||||||
/* Constant data into "ROM" Rom type memory */
|
|
||||||
.rodata :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
|
||||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
|
||||||
. = ALIGN(8);
|
|
||||||
} >ROM
|
|
||||||
|
|
||||||
.ARM.extab : {
|
|
||||||
. = ALIGN(8);
|
|
||||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
|
||||||
. = ALIGN(8);
|
|
||||||
} >ROM
|
|
||||||
|
|
||||||
.ARM : {
|
|
||||||
. = ALIGN(8);
|
|
||||||
__exidx_start = .;
|
|
||||||
*(.ARM.exidx*)
|
|
||||||
__exidx_end = .;
|
|
||||||
. = ALIGN(8);
|
|
||||||
} >ROM
|
|
||||||
|
|
||||||
.preinit_array :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
|
||||||
KEEP (*(.preinit_array*))
|
|
||||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
|
||||||
. = ALIGN(8);
|
|
||||||
} >ROM
|
|
||||||
|
|
||||||
.init_array :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
PROVIDE_HIDDEN (__init_array_start = .);
|
|
||||||
KEEP (*(SORT(.init_array.*)))
|
|
||||||
KEEP (*(.init_array*))
|
|
||||||
PROVIDE_HIDDEN (__init_array_end = .);
|
|
||||||
. = ALIGN(8);
|
|
||||||
} >ROM
|
|
||||||
|
|
||||||
.fini_array :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
|
||||||
KEEP (*(SORT(.fini_array.*)))
|
|
||||||
KEEP (*(.fini_array*))
|
|
||||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
|
||||||
. = ALIGN(8);
|
|
||||||
} >ROM
|
|
||||||
|
|
||||||
/* Used by the startup to initialize data */
|
|
||||||
_sidata = LOADADDR(.data);
|
|
||||||
|
|
||||||
/* Initialized data sections into "SRAM1" Ram type memory */
|
|
||||||
.data :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
_sdata = .; /* create a global symbol at data start */
|
|
||||||
*(.data) /* .data sections */
|
|
||||||
*(.data*) /* .data* sections */
|
|
||||||
|
|
||||||
. = ALIGN(8);
|
|
||||||
_edata = .; /* define a global symbol at data end */
|
|
||||||
|
|
||||||
} >RAM1 AT> ROM
|
|
||||||
|
|
||||||
/* Uninitialized data section into "SRAM1" Ram type memory */
|
|
||||||
. = ALIGN(8);
|
|
||||||
.bss :
|
|
||||||
{
|
|
||||||
/* This is used by the startup in order to initialize the .bss section */
|
|
||||||
_sbss = .; /* define a global symbol at bss start */
|
|
||||||
__bss_start__ = _sbss;
|
|
||||||
*(.bss)
|
|
||||||
*(.bss*)
|
|
||||||
*(COMMON)
|
|
||||||
|
|
||||||
. = ALIGN(8);
|
|
||||||
_ebss = .; /* define a global symbol at bss end */
|
|
||||||
__bss_end__ = _ebss;
|
|
||||||
} >RAM1
|
|
||||||
|
|
||||||
/* Data section into "SRAM1" Ram type memory: Non-backup SRAM1 dedicated to CM4 */
|
|
||||||
. = ALIGN(8);
|
|
||||||
RAM1_region :
|
|
||||||
{
|
|
||||||
_sRAM1_region = .; /* define a global symbol at section start */
|
|
||||||
*(.RAM1_region)
|
|
||||||
|
|
||||||
. = ALIGN(8);
|
|
||||||
_eRAM1_region = .; /* define a global symbol at section end */
|
|
||||||
} >RAM1
|
|
||||||
|
|
||||||
/* Data section into "SRAM2" Ram type memory: Backup SRAM2 dedicated to CM4 */
|
|
||||||
. = ALIGN(8);
|
|
||||||
RAM2_region :
|
|
||||||
{
|
|
||||||
_sRAM2_region = .; /* define a global symbol at section start */
|
|
||||||
*(.RAM2_region)
|
|
||||||
|
|
||||||
. = ALIGN(8);
|
|
||||||
_eRAM2_region = .; /* define a global symbol at section end */
|
|
||||||
} >RAM2
|
|
||||||
|
|
||||||
/* User_heap_stack section, used to check that there is enough "SRAM1" Ram type memory left */
|
|
||||||
._user_heap_stack :
|
|
||||||
{
|
|
||||||
. = ALIGN(8);
|
|
||||||
PROVIDE ( end = . );
|
|
||||||
PROVIDE ( _end = . );
|
|
||||||
. = . + _Min_Heap_Size;
|
|
||||||
. = . + _Min_Stack_Size;
|
|
||||||
. = ALIGN(8);
|
|
||||||
} >RAM1
|
|
||||||
|
|
||||||
/* Remove information from the compiler libraries */
|
|
||||||
/DISCARD/ :
|
|
||||||
{
|
|
||||||
libc.a ( * )
|
|
||||||
libm.a ( * )
|
|
||||||
libgcc.a ( * )
|
|
||||||
}
|
|
||||||
|
|
||||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
|
||||||
}
|
|
||||||
|
|
@ -1,303 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file startup_stm32wl54xx_cm0plus.s
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief STM32WL54xx devices Cortex-M0+ vector table for GCC toolchain.
|
|
||||||
* This module performs:
|
|
||||||
* - Set the initial SP
|
|
||||||
* - Set the initial PC == Reset_Handler,
|
|
||||||
* - Set the vector table entries with the exceptions ISR address,
|
|
||||||
* - Branches to main in the C library (which eventually
|
|
||||||
* calls main()).
|
|
||||||
* After Reset the Cortex-M0+ processor is in Thread mode,
|
|
||||||
* priority is Privileged, and the Stack is set to Main.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* Copyright (c) 2020(-2021) STMicroelectronics.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* This software is licensed under terms that can be found in the LICENSE file
|
|
||||||
* in the root directory of this software component.
|
|
||||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
.syntax unified
|
|
||||||
.cpu cortex-m0plus
|
|
||||||
.fpu softvfp
|
|
||||||
.thumb
|
|
||||||
|
|
||||||
.global g_pfnVectors
|
|
||||||
.global Default_Handler
|
|
||||||
|
|
||||||
/* start address for the initialization values of the .data section.
|
|
||||||
defined in linker script */
|
|
||||||
.word _sidata
|
|
||||||
/* start address for the .data section. defined in linker script */
|
|
||||||
.word _sdata
|
|
||||||
/* end address for the .data section. defined in linker script */
|
|
||||||
.word _edata
|
|
||||||
/* start address for the .bss section. defined in linker script */
|
|
||||||
.word _sbss
|
|
||||||
/* end address for the .bss section. defined in linker script */
|
|
||||||
.word _ebss
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief This is the code that gets called when the processor first
|
|
||||||
* starts execution following a reset event. Only the absolutely
|
|
||||||
* necessary set is performed, after which the application
|
|
||||||
* supplied main() routine is called.
|
|
||||||
* @param None
|
|
||||||
* @retval : None
|
|
||||||
*/
|
|
||||||
|
|
||||||
.section .text.Reset_Handler
|
|
||||||
.weak Reset_Handler
|
|
||||||
.type Reset_Handler, %function
|
|
||||||
Reset_Handler:
|
|
||||||
ldr r0, =_estack
|
|
||||||
mov sp, r0 /* set stack pointer */
|
|
||||||
|
|
||||||
/* Call the clock system initialization function.*/
|
|
||||||
bl SystemInit
|
|
||||||
|
|
||||||
/* Copy the data segment initializers from flash to SRAM */
|
|
||||||
ldr r0, =_sdata
|
|
||||||
ldr r1, =_edata
|
|
||||||
ldr r2, =_sidata
|
|
||||||
movs r3, #0
|
|
||||||
b LoopCopyDataInit
|
|
||||||
|
|
||||||
CopyDataInit:
|
|
||||||
ldr r4, [r2, r3]
|
|
||||||
str r4, [r0, r3]
|
|
||||||
adds r3, r3, #4
|
|
||||||
|
|
||||||
LoopCopyDataInit:
|
|
||||||
adds r4, r0, r3
|
|
||||||
cmp r4, r1
|
|
||||||
bcc CopyDataInit
|
|
||||||
|
|
||||||
/* Zero fill the bss segment. */
|
|
||||||
ldr r2, =_sbss
|
|
||||||
ldr r4, =_ebss
|
|
||||||
movs r3, #0
|
|
||||||
b LoopFillZerobss
|
|
||||||
|
|
||||||
FillZerobss:
|
|
||||||
str r3, [r2]
|
|
||||||
adds r2, r2, #4
|
|
||||||
|
|
||||||
LoopFillZerobss:
|
|
||||||
cmp r2, r4
|
|
||||||
bcc FillZerobss
|
|
||||||
|
|
||||||
/* Call static constructors */
|
|
||||||
bl __libc_init_array
|
|
||||||
/* Call the application's entry point.*/
|
|
||||||
bl entry
|
|
||||||
|
|
||||||
LoopForever:
|
|
||||||
b LoopForever
|
|
||||||
|
|
||||||
.size Reset_Handler, .-Reset_Handler
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief This is the code that gets called when the processor receives an
|
|
||||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
|
||||||
* the system state for examination by a debugger.
|
|
||||||
*
|
|
||||||
* @param None
|
|
||||||
* @retval : None
|
|
||||||
*/
|
|
||||||
.section .text.Default_Handler,"ax",%progbits
|
|
||||||
Default_Handler:
|
|
||||||
Infinite_Loop:
|
|
||||||
b Infinite_Loop
|
|
||||||
.size Default_Handler, .-Default_Handler
|
|
||||||
|
|
||||||
/******************************************************************************
|
|
||||||
*
|
|
||||||
* The STM32WL54xx Cortex-M0+ vector table. Note that the proper constructs
|
|
||||||
* must be placed on this to ensure that it ends up at physical address
|
|
||||||
* 0x0000.0000.
|
|
||||||
*
|
|
||||||
******************************************************************************/
|
|
||||||
.section .isr_vector,"a",%progbits
|
|
||||||
.type g_pfnVectors, %object
|
|
||||||
.size g_pfnVectors, .-g_pfnVectors
|
|
||||||
|
|
||||||
g_pfnVectors:
|
|
||||||
.word _estack
|
|
||||||
.word Reset_Handler
|
|
||||||
.word NMI_Handler
|
|
||||||
.word HardFault_Handler
|
|
||||||
.word 0
|
|
||||||
.word 0
|
|
||||||
.word 0
|
|
||||||
.word 0
|
|
||||||
.word 0
|
|
||||||
.word 0
|
|
||||||
.word 0
|
|
||||||
.word SVC_Handler
|
|
||||||
.word 0
|
|
||||||
.word 0
|
|
||||||
.word PendSV_Handler
|
|
||||||
.word SysTick_Handler
|
|
||||||
.word TZIC_ILA_IRQHandler /* TZIC ILA Interrupt */
|
|
||||||
.word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */
|
|
||||||
.word RTC_LSECSS_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
|
|
||||||
.word RCC_FLASH_C1SEV_IRQHandler /* RCC and FLASH and CPU1 M4 SEV Interrupt */
|
|
||||||
.word EXTI1_0_IRQHandler /* EXTI Line 1:0 Interrupt */
|
|
||||||
.word EXTI3_2_IRQHandler /* EXTI Line 3:2 Interrupt */
|
|
||||||
.word EXTI15_4_IRQHandler /* EXTI Line 15:4 interrupt */
|
|
||||||
.word ADC_COMP_DAC_IRQHandler /* ADC, COMP1, COMP2, DAC Interrupt */
|
|
||||||
.word DMA1_Channel1_2_3_IRQHandler /* DMA1 Channel 1 to 3 Interrupt */
|
|
||||||
.word DMA1_Channel4_5_6_7_IRQHandler /* DMA1 Channels 4,5,6,7 Interrupt */
|
|
||||||
.word DMA2_DMAMUX1_OVR_IRQHandler /* DMA2 Channels[1..7] and DMAMUX Overrun Interrupts */
|
|
||||||
.word LPTIM1_IRQHandler /* LPTIM1 Global Interrupt */
|
|
||||||
.word LPTIM2_IRQHandler /* LPTIM2 Global Interrupt */
|
|
||||||
.word LPTIM3_IRQHandler /* LPTIM3 Global Interrupt */
|
|
||||||
.word TIM1_IRQHandler /* TIM1 Global Interrupt */
|
|
||||||
.word TIM2_IRQHandler /* TIM2 Global Interrupt */
|
|
||||||
.word TIM16_IRQHandler /* TIM16 Global Interrupt */
|
|
||||||
.word TIM17_IRQHandler /* TIM17 Global Interrupt */
|
|
||||||
.word IPCC_C2_RX_C2_TX_IRQHandler /* IPCC RX Occupied and TX Free Interrupt Interrupt */
|
|
||||||
.word HSEM_IRQHandler /* Semaphore Interrupt */
|
|
||||||
.word RNG_IRQHandler /* RNG Interrupt */
|
|
||||||
.word AES_PKA_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */
|
|
||||||
.word I2C1_IRQHandler /* I2C1 Event and Error Interrupt */
|
|
||||||
.word I2C2_IRQHandler /* I2C2 Event and Error Interrupt */
|
|
||||||
.word I2C3_IRQHandler /* I2C3 Event and Error Interrupt */
|
|
||||||
.word SPI1_IRQHandler /* SPI1 Interrupt */
|
|
||||||
.word SPI2_IRQHandler /* SPI2 Interrupt */
|
|
||||||
.word USART1_IRQHandler /* USART1 Interrupt */
|
|
||||||
.word USART2_IRQHandler /* USART2 Interrupt */
|
|
||||||
.word LPUART1_IRQHandler /* LPUART1 Interrupt */
|
|
||||||
.word SUBGHZSPI_IRQHandler /* SUBGHZSPI Interrupt */
|
|
||||||
.word SUBGHZ_Radio_IRQHandler /* SUBGHZ Radio Interrupt */
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
*
|
|
||||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
|
||||||
* As they are weak aliases, any function with the same name will override
|
|
||||||
* this definition.
|
|
||||||
*
|
|
||||||
*******************************************************************************/
|
|
||||||
|
|
||||||
.weak NMI_Handler
|
|
||||||
.thumb_set NMI_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak HardFault_Handler
|
|
||||||
.thumb_set HardFault_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak SVC_Handler
|
|
||||||
.thumb_set SVC_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak PendSV_Handler
|
|
||||||
.thumb_set PendSV_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak SysTick_Handler
|
|
||||||
.thumb_set SysTick_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak TZIC_ILA_IRQHandler
|
|
||||||
.thumb_set TZIC_ILA_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak PVD_PVM_IRQHandler
|
|
||||||
.thumb_set PVD_PVM_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak RTC_LSECSS_IRQHandler
|
|
||||||
.thumb_set RTC_LSECSS_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak RCC_FLASH_C1SEV_IRQHandler
|
|
||||||
.thumb_set RCC_FLASH_C1SEV_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak EXTI1_0_IRQHandler
|
|
||||||
.thumb_set EXTI1_0_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak EXTI3_2_IRQHandler
|
|
||||||
.thumb_set EXTI3_2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak EXTI15_4_IRQHandler
|
|
||||||
.thumb_set EXTI15_4_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak ADC_COMP_DAC_IRQHandler
|
|
||||||
.thumb_set ADC_COMP_DAC_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Channel1_2_3_IRQHandler
|
|
||||||
.thumb_set DMA1_Channel1_2_3_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Channel4_5_6_7_IRQHandler
|
|
||||||
.thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA2_DMAMUX1_OVR_IRQHandler
|
|
||||||
.thumb_set DMA2_DMAMUX1_OVR_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak LPTIM1_IRQHandler
|
|
||||||
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak LPTIM2_IRQHandler
|
|
||||||
.thumb_set LPTIM2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak LPTIM3_IRQHandler
|
|
||||||
.thumb_set LPTIM3_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM1_IRQHandler
|
|
||||||
.thumb_set TIM1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM2_IRQHandler
|
|
||||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM16_IRQHandler
|
|
||||||
.thumb_set TIM16_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM17_IRQHandler
|
|
||||||
.thumb_set TIM17_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak IPCC_C2_RX_C2_TX_IRQHandler
|
|
||||||
.thumb_set IPCC_C2_RX_C2_TX_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak HSEM_IRQHandler
|
|
||||||
.thumb_set HSEM_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak RNG_IRQHandler
|
|
||||||
.thumb_set RNG_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak AES_PKA_IRQHandler
|
|
||||||
.thumb_set AES_PKA_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak I2C1_IRQHandler
|
|
||||||
.thumb_set I2C1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak I2C2_IRQHandler
|
|
||||||
.thumb_set I2C2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak I2C3_IRQHandler
|
|
||||||
.thumb_set I2C3_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak SPI1_IRQHandler
|
|
||||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak SPI2_IRQHandler
|
|
||||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak USART1_IRQHandler
|
|
||||||
.thumb_set USART1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak USART2_IRQHandler
|
|
||||||
.thumb_set USART2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak LPUART1_IRQHandler
|
|
||||||
.thumb_set LPUART1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak SUBGHZSPI_IRQHandler
|
|
||||||
.thumb_set SUBGHZSPI_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak SUBGHZ_Radio_IRQHandler
|
|
||||||
.thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak SystemInit
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectonics *****END OF FILE****/
|
|
||||||
|
|
@ -1,435 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file startup_stm32wl54xx_cm4.s
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief STM32WL54xx devices Cortex-M4 vector table for GCC toolchain.
|
|
||||||
* This module performs:
|
|
||||||
* - Set the initial SP
|
|
||||||
* - Set the initial PC == Reset_Handler,
|
|
||||||
* - Set the vector table entries with the exceptions ISR address,
|
|
||||||
* - Branches to main in the C library (which eventually
|
|
||||||
* calls main()).
|
|
||||||
* After Reset the Cortex-M4 processor is in Thread mode,
|
|
||||||
* priority is Privileged, and the Stack is set to Main.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* Copyright (c) 2020(-2021) STMicroelectronics.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* This software is licensed under terms that can be found in the LICENSE file
|
|
||||||
* in the root directory of this software component.
|
|
||||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
.syntax unified
|
|
||||||
.cpu cortex-m4
|
|
||||||
.fpu softvfp
|
|
||||||
.thumb
|
|
||||||
|
|
||||||
.global g_pfnVectors
|
|
||||||
.global Default_Handler
|
|
||||||
|
|
||||||
/* start address for the initialization values of the .data section.
|
|
||||||
defined in linker script */
|
|
||||||
.word _sidata
|
|
||||||
/* start address for the .data section. defined in linker script */
|
|
||||||
.word _sdata
|
|
||||||
/* end address for the .data section. defined in linker script */
|
|
||||||
.word _edata
|
|
||||||
/* start address for the .bss section. defined in linker script */
|
|
||||||
.word _sbss
|
|
||||||
/* end address for the .bss section. defined in linker script */
|
|
||||||
.word _ebss
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief This is the code that gets called when the processor first
|
|
||||||
* starts execution following a reset event. Only the absolutely
|
|
||||||
* necessary set is performed, after which the application
|
|
||||||
* supplied main() routine is called.
|
|
||||||
* @param None
|
|
||||||
* @retval : None
|
|
||||||
*/
|
|
||||||
|
|
||||||
.section .text.Reset_Handler
|
|
||||||
.weak Reset_Handler
|
|
||||||
.type Reset_Handler, %function
|
|
||||||
Reset_Handler:
|
|
||||||
ldr r0, =_estack
|
|
||||||
mov sp, r0 /* set stack pointer */
|
|
||||||
|
|
||||||
/* Call the clock system initialization function.*/
|
|
||||||
bl SystemInit
|
|
||||||
|
|
||||||
/* Copy the data segment initializers from flash to SRAM */
|
|
||||||
ldr r0, =_sdata
|
|
||||||
ldr r1, =_edata
|
|
||||||
ldr r2, =_sidata
|
|
||||||
movs r3, #0
|
|
||||||
b LoopCopyDataInit
|
|
||||||
|
|
||||||
CopyDataInit:
|
|
||||||
ldr r4, [r2, r3]
|
|
||||||
str r4, [r0, r3]
|
|
||||||
adds r3, r3, #4
|
|
||||||
|
|
||||||
LoopCopyDataInit:
|
|
||||||
adds r4, r0, r3
|
|
||||||
cmp r4, r1
|
|
||||||
bcc CopyDataInit
|
|
||||||
|
|
||||||
/* Zero fill the bss segment. */
|
|
||||||
ldr r2, =_sbss
|
|
||||||
ldr r4, =_ebss
|
|
||||||
movs r3, #0
|
|
||||||
b LoopFillZerobss
|
|
||||||
|
|
||||||
FillZerobss:
|
|
||||||
str r3, [r2]
|
|
||||||
adds r2, r2, #4
|
|
||||||
|
|
||||||
LoopFillZerobss:
|
|
||||||
cmp r2, r4
|
|
||||||
bcc FillZerobss
|
|
||||||
|
|
||||||
/* Call static constructors */
|
|
||||||
bl __libc_init_array
|
|
||||||
/* Call the application's entry point.*/
|
|
||||||
bl entry
|
|
||||||
|
|
||||||
LoopForever:
|
|
||||||
b LoopForever
|
|
||||||
|
|
||||||
.size Reset_Handler, .-Reset_Handler
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief This is the code that gets called when the processor receives an
|
|
||||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
|
||||||
* the system state for examination by a debugger.
|
|
||||||
*
|
|
||||||
* @param None
|
|
||||||
* @retval : None
|
|
||||||
*/
|
|
||||||
.section .text.Default_Handler,"ax",%progbits
|
|
||||||
Default_Handler:
|
|
||||||
Infinite_Loop:
|
|
||||||
b Infinite_Loop
|
|
||||||
.size Default_Handler, .-Default_Handler
|
|
||||||
|
|
||||||
/******************************************************************************
|
|
||||||
*
|
|
||||||
* The STM32WL54xx Cortex-M4 vector table. Note that the proper constructs
|
|
||||||
* must be placed on this to ensure that it ends up at physical address
|
|
||||||
* 0x0000.0000.
|
|
||||||
*
|
|
||||||
******************************************************************************/
|
|
||||||
.section .isr_vector,"a",%progbits
|
|
||||||
.type g_pfnVectors, %object
|
|
||||||
.size g_pfnVectors, .-g_pfnVectors
|
|
||||||
|
|
||||||
g_pfnVectors:
|
|
||||||
.word _estack
|
|
||||||
.word Reset_Handler
|
|
||||||
.word NMI_Handler
|
|
||||||
.word HardFault_Handler
|
|
||||||
.word MemManage_Handler
|
|
||||||
.word BusFault_Handler
|
|
||||||
.word UsageFault_Handler
|
|
||||||
.word 0
|
|
||||||
.word 0
|
|
||||||
.word 0
|
|
||||||
.word 0
|
|
||||||
.word SVC_Handler
|
|
||||||
.word DebugMon_Handler
|
|
||||||
.word 0
|
|
||||||
.word PendSV_Handler
|
|
||||||
.word SysTick_Handler
|
|
||||||
.word WWDG_IRQHandler /* Window Watchdog interrupt */
|
|
||||||
.word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */
|
|
||||||
.word TAMP_STAMP_LSECSS_SSRU_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
|
|
||||||
.word RTC_WKUP_IRQHandler /* RTC wakeup interrupt through EXTI[19] */
|
|
||||||
.word FLASH_IRQHandler /* Flash memory global interrupt and Flash memory ECC */
|
|
||||||
.word RCC_IRQHandler /* RCC global interrupt */
|
|
||||||
.word EXTI0_IRQHandler /* EXTI line 0 interrupt */
|
|
||||||
.word EXTI1_IRQHandler /* EXTI line 1 interrupt */
|
|
||||||
.word EXTI2_IRQHandler /* EXTI line 2 interrupt */
|
|
||||||
.word EXTI3_IRQHandler /* EXTI line 3 interrupt */
|
|
||||||
.word EXTI4_IRQHandler /* EXTI line 4 interrupt */
|
|
||||||
.word DMA1_Channel1_IRQHandler /* DMA1 channel 1 interrupt */
|
|
||||||
.word DMA1_Channel2_IRQHandler /* DMA1 channel 2 interrupt */
|
|
||||||
.word DMA1_Channel3_IRQHandler /* DMA1 channel 3 interrupt */
|
|
||||||
.word DMA1_Channel4_IRQHandler /* DMA1 channel 4 interrupt */
|
|
||||||
.word DMA1_Channel5_IRQHandler /* DMA1 channel 5 interrupt */
|
|
||||||
.word DMA1_Channel6_IRQHandler /* DMA1 channel 6 interrupt */
|
|
||||||
.word DMA1_Channel7_IRQHandler /* DMA1 channel 7 interrupt */
|
|
||||||
.word ADC_IRQHandler /* ADC interrupt */
|
|
||||||
.word DAC_IRQHandler /* DAC interrupt */
|
|
||||||
.word C2SEV_PWR_C2H_IRQHandler /* CPU M0+ SEV Interrupt */
|
|
||||||
.word COMP_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */
|
|
||||||
.word EXTI9_5_IRQHandler /* EXTI line 9_5 interrupt */
|
|
||||||
.word TIM1_BRK_IRQHandler /* Timer 1 break interrupt */
|
|
||||||
.word TIM1_UP_IRQHandler /* Timer 1 Update */
|
|
||||||
.word TIM1_TRG_COM_IRQHandler /* Timer 1 trigger and communication */
|
|
||||||
.word TIM1_CC_IRQHandler /* Timer 1 capture compare interrupt */
|
|
||||||
.word TIM2_IRQHandler /* TIM2 global interrupt */
|
|
||||||
.word TIM16_IRQHandler /* Timer 16 global interrupt */
|
|
||||||
.word TIM17_IRQHandler /* Timer 17 global interrupt */
|
|
||||||
.word I2C1_EV_IRQHandler /* I2C1 event interrupt */
|
|
||||||
.word I2C1_ER_IRQHandler /* I2C1 event interrupt */
|
|
||||||
.word I2C2_EV_IRQHandler /* I2C2 error interrupt */
|
|
||||||
.word I2C2_ER_IRQHandler /* I2C2 error interrupt */
|
|
||||||
.word SPI1_IRQHandler /* SPI1 global interrupt */
|
|
||||||
.word SPI2_IRQHandler /* SPI2 global interrupt */
|
|
||||||
.word USART1_IRQHandler /* USART1 global interrupt */
|
|
||||||
.word USART2_IRQHandler /* USART2 global interrupt */
|
|
||||||
.word LPUART1_IRQHandler /* LPUART1 global interrupt */
|
|
||||||
.word LPTIM1_IRQHandler /* LPtimer 1 global interrupt */
|
|
||||||
.word LPTIM2_IRQHandler /* LPtimer 2 global interrupt */
|
|
||||||
.word EXTI15_10_IRQHandler /* EXTI line 15_10] interrupt through EXTI */
|
|
||||||
.word RTC_Alarm_IRQHandler /* RTC Alarms A & B interrupt */
|
|
||||||
.word LPTIM3_IRQHandler /* LPtimer 3 global interrupt */
|
|
||||||
.word SUBGHZSPI_IRQHandler /* SUBGHZSPI global interrupt */
|
|
||||||
.word IPCC_C1_RX_IRQHandler /* IPCC CPU1 RX occupied interrupt */
|
|
||||||
.word IPCC_C1_TX_IRQHandler /* IPCC CPU1 RX free interrupt */
|
|
||||||
.word HSEM_IRQHandler /* Semaphore interrupt 0 to CPU1 */
|
|
||||||
.word I2C3_EV_IRQHandler /* I2C3 event interrupt */
|
|
||||||
.word I2C3_ER_IRQHandler /* I2C3 error interrupt */
|
|
||||||
.word SUBGHZ_Radio_IRQHandler /* Radio IRQs RFBUSY interrupt through EXTI */
|
|
||||||
.word AES_IRQHandler /* AES global interrupt */
|
|
||||||
.word RNG_IRQHandler /* RNG interrupt */
|
|
||||||
.word PKA_IRQHandler /* PKA interrupt */
|
|
||||||
.word DMA2_Channel1_IRQHandler /* DMA2 channel 1 interrupt */
|
|
||||||
.word DMA2_Channel2_IRQHandler /* DMA2 channel 2 interrupt */
|
|
||||||
.word DMA2_Channel3_IRQHandler /* DMA2 channel 3 interrupt */
|
|
||||||
.word DMA2_Channel4_IRQHandler /* DMA2 channel 4 interrupt */
|
|
||||||
.word DMA2_Channel5_IRQHandler /* DMA2 channel 5 interrupt */
|
|
||||||
.word DMA2_Channel6_IRQHandler /* DMA2 channel 6 interrupt */
|
|
||||||
.word DMA2_Channel7_IRQHandler /* DMA2 channel 7 interrupt */
|
|
||||||
.word DMAMUX1_OVR_IRQHandler /* DMAMUX overrun interrupt */
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
*
|
|
||||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
|
||||||
* As they are weak aliases, any function with the same name will override
|
|
||||||
* this definition.
|
|
||||||
*
|
|
||||||
*******************************************************************************/
|
|
||||||
|
|
||||||
.weak NMI_Handler
|
|
||||||
.thumb_set NMI_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak HardFault_Handler
|
|
||||||
.thumb_set HardFault_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak MemManage_Handler
|
|
||||||
.thumb_set MemManage_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak BusFault_Handler
|
|
||||||
.thumb_set BusFault_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak UsageFault_Handler
|
|
||||||
.thumb_set UsageFault_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak SVC_Handler
|
|
||||||
.thumb_set SVC_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak DebugMon_Handler
|
|
||||||
.thumb_set DebugMon_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak PendSV_Handler
|
|
||||||
.thumb_set PendSV_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak SysTick_Handler
|
|
||||||
.thumb_set SysTick_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak WWDG_IRQHandler
|
|
||||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak PVD_PVM_IRQHandler
|
|
||||||
.thumb_set PVD_PVM_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TAMP_STAMP_LSECSS_SSRU_IRQHandler
|
|
||||||
.thumb_set TAMP_STAMP_LSECSS_SSRU_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak RTC_WKUP_IRQHandler
|
|
||||||
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak FLASH_IRQHandler
|
|
||||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak RCC_IRQHandler
|
|
||||||
.thumb_set RCC_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak EXTI0_IRQHandler
|
|
||||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak EXTI1_IRQHandler
|
|
||||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak EXTI2_IRQHandler
|
|
||||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak EXTI3_IRQHandler
|
|
||||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak EXTI4_IRQHandler
|
|
||||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Channel1_IRQHandler
|
|
||||||
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Channel2_IRQHandler
|
|
||||||
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Channel3_IRQHandler
|
|
||||||
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Channel4_IRQHandler
|
|
||||||
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Channel5_IRQHandler
|
|
||||||
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Channel6_IRQHandler
|
|
||||||
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Channel7_IRQHandler
|
|
||||||
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak ADC_IRQHandler
|
|
||||||
.thumb_set ADC_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DAC_IRQHandler
|
|
||||||
.thumb_set DAC_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak C2SEV_PWR_C2H_IRQHandler
|
|
||||||
.thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak COMP_IRQHandler
|
|
||||||
.thumb_set COMP_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak EXTI9_5_IRQHandler
|
|
||||||
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM1_BRK_IRQHandler
|
|
||||||
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM1_UP_IRQHandler
|
|
||||||
.thumb_set TIM1_UP_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM1_TRG_COM_IRQHandler
|
|
||||||
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM1_CC_IRQHandler
|
|
||||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM2_IRQHandler
|
|
||||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM16_IRQHandler
|
|
||||||
.thumb_set TIM16_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM17_IRQHandler
|
|
||||||
.thumb_set TIM17_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak I2C1_EV_IRQHandler
|
|
||||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak I2C1_ER_IRQHandler
|
|
||||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak I2C2_EV_IRQHandler
|
|
||||||
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak I2C2_ER_IRQHandler
|
|
||||||
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak SPI1_IRQHandler
|
|
||||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak SPI2_IRQHandler
|
|
||||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak USART1_IRQHandler
|
|
||||||
.thumb_set USART1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak USART2_IRQHandler
|
|
||||||
.thumb_set USART2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak LPUART1_IRQHandler
|
|
||||||
.thumb_set LPUART1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak LPTIM1_IRQHandler
|
|
||||||
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak LPTIM2_IRQHandler
|
|
||||||
.thumb_set LPTIM2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak EXTI15_10_IRQHandler
|
|
||||||
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak RTC_Alarm_IRQHandler
|
|
||||||
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak LPTIM3_IRQHandler
|
|
||||||
.thumb_set LPTIM3_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak SUBGHZSPI_IRQHandler
|
|
||||||
.thumb_set SUBGHZSPI_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak IPCC_C1_RX_IRQHandler
|
|
||||||
.thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak IPCC_C1_TX_IRQHandler
|
|
||||||
.thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak HSEM_IRQHandler
|
|
||||||
.thumb_set HSEM_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak I2C3_EV_IRQHandler
|
|
||||||
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak I2C3_ER_IRQHandler
|
|
||||||
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak SUBGHZ_Radio_IRQHandler
|
|
||||||
.thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak AES_IRQHandler
|
|
||||||
.thumb_set AES_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak RNG_IRQHandler
|
|
||||||
.thumb_set RNG_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak PKA_IRQHandler
|
|
||||||
.thumb_set PKA_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA2_Channel1_IRQHandler
|
|
||||||
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA2_Channel2_IRQHandler
|
|
||||||
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA2_Channel3_IRQHandler
|
|
||||||
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA2_Channel4_IRQHandler
|
|
||||||
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA2_Channel5_IRQHandler
|
|
||||||
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA2_Channel6_IRQHandler
|
|
||||||
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA2_Channel7_IRQHandler
|
|
||||||
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMAMUX1_OVR_IRQHandler
|
|
||||||
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak SystemInit
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectonics *****END OF FILE****/
|
|
||||||
|
|
@ -1,303 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file startup_stm32wl55xx_cm0plus.s
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief STM32WL55xx devices Cortex-M0+ vector table for GCC toolchain.
|
|
||||||
* This module performs:
|
|
||||||
* - Set the initial SP
|
|
||||||
* - Set the initial PC == Reset_Handler,
|
|
||||||
* - Set the vector table entries with the exceptions ISR address,
|
|
||||||
* - Branches to main in the C library (which eventually
|
|
||||||
* calls main()).
|
|
||||||
* After Reset the Cortex-M0+ processor is in Thread mode,
|
|
||||||
* priority is Privileged, and the Stack is set to Main.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* Copyright (c) 2020(-2021) STMicroelectronics.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* This software is licensed under terms that can be found in the LICENSE file
|
|
||||||
* in the root directory of this software component.
|
|
||||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
.syntax unified
|
|
||||||
.cpu cortex-m0plus
|
|
||||||
.fpu softvfp
|
|
||||||
.thumb
|
|
||||||
|
|
||||||
.global g_pfnVectors
|
|
||||||
.global Default_Handler
|
|
||||||
|
|
||||||
/* start address for the initialization values of the .data section.
|
|
||||||
defined in linker script */
|
|
||||||
.word _sidata
|
|
||||||
/* start address for the .data section. defined in linker script */
|
|
||||||
.word _sdata
|
|
||||||
/* end address for the .data section. defined in linker script */
|
|
||||||
.word _edata
|
|
||||||
/* start address for the .bss section. defined in linker script */
|
|
||||||
.word _sbss
|
|
||||||
/* end address for the .bss section. defined in linker script */
|
|
||||||
.word _ebss
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief This is the code that gets called when the processor first
|
|
||||||
* starts execution following a reset event. Only the absolutely
|
|
||||||
* necessary set is performed, after which the application
|
|
||||||
* supplied main() routine is called.
|
|
||||||
* @param None
|
|
||||||
* @retval : None
|
|
||||||
*/
|
|
||||||
|
|
||||||
.section .text.Reset_Handler
|
|
||||||
.weak Reset_Handler
|
|
||||||
.type Reset_Handler, %function
|
|
||||||
Reset_Handler:
|
|
||||||
ldr r0, =_estack
|
|
||||||
mov sp, r0 /* set stack pointer */
|
|
||||||
|
|
||||||
/* Call the clock system initialization function.*/
|
|
||||||
bl SystemInit
|
|
||||||
|
|
||||||
/* Copy the data segment initializers from flash to SRAM */
|
|
||||||
ldr r0, =_sdata
|
|
||||||
ldr r1, =_edata
|
|
||||||
ldr r2, =_sidata
|
|
||||||
movs r3, #0
|
|
||||||
b LoopCopyDataInit
|
|
||||||
|
|
||||||
CopyDataInit:
|
|
||||||
ldr r4, [r2, r3]
|
|
||||||
str r4, [r0, r3]
|
|
||||||
adds r3, r3, #4
|
|
||||||
|
|
||||||
LoopCopyDataInit:
|
|
||||||
adds r4, r0, r3
|
|
||||||
cmp r4, r1
|
|
||||||
bcc CopyDataInit
|
|
||||||
|
|
||||||
/* Zero fill the bss segment. */
|
|
||||||
ldr r2, =_sbss
|
|
||||||
ldr r4, =_ebss
|
|
||||||
movs r3, #0
|
|
||||||
b LoopFillZerobss
|
|
||||||
|
|
||||||
FillZerobss:
|
|
||||||
str r3, [r2]
|
|
||||||
adds r2, r2, #4
|
|
||||||
|
|
||||||
LoopFillZerobss:
|
|
||||||
cmp r2, r4
|
|
||||||
bcc FillZerobss
|
|
||||||
|
|
||||||
/* Call static constructors */
|
|
||||||
bl __libc_init_array
|
|
||||||
/* Call the application's entry point.*/
|
|
||||||
bl entry
|
|
||||||
|
|
||||||
LoopForever:
|
|
||||||
b LoopForever
|
|
||||||
|
|
||||||
.size Reset_Handler, .-Reset_Handler
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief This is the code that gets called when the processor receives an
|
|
||||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
|
||||||
* the system state for examination by a debugger.
|
|
||||||
*
|
|
||||||
* @param None
|
|
||||||
* @retval : None
|
|
||||||
*/
|
|
||||||
.section .text.Default_Handler,"ax",%progbits
|
|
||||||
Default_Handler:
|
|
||||||
Infinite_Loop:
|
|
||||||
b Infinite_Loop
|
|
||||||
.size Default_Handler, .-Default_Handler
|
|
||||||
|
|
||||||
/******************************************************************************
|
|
||||||
*
|
|
||||||
* The STM32WL55xx Cortex-M0+ vector table. Note that the proper constructs
|
|
||||||
* must be placed on this to ensure that it ends up at physical address
|
|
||||||
* 0x0000.0000.
|
|
||||||
*
|
|
||||||
******************************************************************************/
|
|
||||||
.section .isr_vector,"a",%progbits
|
|
||||||
.type g_pfnVectors, %object
|
|
||||||
.size g_pfnVectors, .-g_pfnVectors
|
|
||||||
|
|
||||||
g_pfnVectors:
|
|
||||||
.word _estack
|
|
||||||
.word Reset_Handler
|
|
||||||
.word NMI_Handler
|
|
||||||
.word HardFault_Handler
|
|
||||||
.word 0
|
|
||||||
.word 0
|
|
||||||
.word 0
|
|
||||||
.word 0
|
|
||||||
.word 0
|
|
||||||
.word 0
|
|
||||||
.word 0
|
|
||||||
.word SVC_Handler
|
|
||||||
.word 0
|
|
||||||
.word 0
|
|
||||||
.word PendSV_Handler
|
|
||||||
.word SysTick_Handler
|
|
||||||
.word TZIC_ILA_IRQHandler /* TZIC ILA Interrupt */
|
|
||||||
.word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */
|
|
||||||
.word RTC_LSECSS_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
|
|
||||||
.word RCC_FLASH_C1SEV_IRQHandler /* RCC and FLASH and CPU1 M4 SEV Interrupt */
|
|
||||||
.word EXTI1_0_IRQHandler /* EXTI Line 1:0 Interrupt */
|
|
||||||
.word EXTI3_2_IRQHandler /* EXTI Line 3:2 Interrupt */
|
|
||||||
.word EXTI15_4_IRQHandler /* EXTI Line 15:4 interrupt */
|
|
||||||
.word ADC_COMP_DAC_IRQHandler /* ADC, COMP1, COMP2, DAC Interrupt */
|
|
||||||
.word DMA1_Channel1_2_3_IRQHandler /* DMA1 Channel 1 to 3 Interrupt */
|
|
||||||
.word DMA1_Channel4_5_6_7_IRQHandler /* DMA1 Channels 4,5,6,7 Interrupt */
|
|
||||||
.word DMA2_DMAMUX1_OVR_IRQHandler /* DMA2 Channels[1..7] and DMAMUX Overrun Interrupts */
|
|
||||||
.word LPTIM1_IRQHandler /* LPTIM1 Global Interrupt */
|
|
||||||
.word LPTIM2_IRQHandler /* LPTIM2 Global Interrupt */
|
|
||||||
.word LPTIM3_IRQHandler /* LPTIM3 Global Interrupt */
|
|
||||||
.word TIM1_IRQHandler /* TIM1 Global Interrupt */
|
|
||||||
.word TIM2_IRQHandler /* TIM2 Global Interrupt */
|
|
||||||
.word TIM16_IRQHandler /* TIM16 Global Interrupt */
|
|
||||||
.word TIM17_IRQHandler /* TIM17 Global Interrupt */
|
|
||||||
.word IPCC_C2_RX_C2_TX_IRQHandler /* IPCC RX Occupied and TX Free Interrupt Interrupt */
|
|
||||||
.word HSEM_IRQHandler /* Semaphore Interrupt */
|
|
||||||
.word RNG_IRQHandler /* RNG Interrupt */
|
|
||||||
.word AES_PKA_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */
|
|
||||||
.word I2C1_IRQHandler /* I2C1 Event and Error Interrupt */
|
|
||||||
.word I2C2_IRQHandler /* I2C2 Event and Error Interrupt */
|
|
||||||
.word I2C3_IRQHandler /* I2C3 Event and Error Interrupt */
|
|
||||||
.word SPI1_IRQHandler /* SPI1 Interrupt */
|
|
||||||
.word SPI2_IRQHandler /* SPI2 Interrupt */
|
|
||||||
.word USART1_IRQHandler /* USART1 Interrupt */
|
|
||||||
.word USART2_IRQHandler /* USART2 Interrupt */
|
|
||||||
.word LPUART1_IRQHandler /* LPUART1 Interrupt */
|
|
||||||
.word SUBGHZSPI_IRQHandler /* SUBGHZSPI Interrupt */
|
|
||||||
.word SUBGHZ_Radio_IRQHandler /* SUBGHZ Radio Interrupt */
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
*
|
|
||||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
|
||||||
* As they are weak aliases, any function with the same name will override
|
|
||||||
* this definition.
|
|
||||||
*
|
|
||||||
*******************************************************************************/
|
|
||||||
|
|
||||||
.weak NMI_Handler
|
|
||||||
.thumb_set NMI_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak HardFault_Handler
|
|
||||||
.thumb_set HardFault_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak SVC_Handler
|
|
||||||
.thumb_set SVC_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak PendSV_Handler
|
|
||||||
.thumb_set PendSV_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak SysTick_Handler
|
|
||||||
.thumb_set SysTick_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak TZIC_ILA_IRQHandler
|
|
||||||
.thumb_set TZIC_ILA_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak PVD_PVM_IRQHandler
|
|
||||||
.thumb_set PVD_PVM_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak RTC_LSECSS_IRQHandler
|
|
||||||
.thumb_set RTC_LSECSS_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak RCC_FLASH_C1SEV_IRQHandler
|
|
||||||
.thumb_set RCC_FLASH_C1SEV_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak EXTI1_0_IRQHandler
|
|
||||||
.thumb_set EXTI1_0_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak EXTI3_2_IRQHandler
|
|
||||||
.thumb_set EXTI3_2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak EXTI15_4_IRQHandler
|
|
||||||
.thumb_set EXTI15_4_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak ADC_COMP_DAC_IRQHandler
|
|
||||||
.thumb_set ADC_COMP_DAC_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Channel1_2_3_IRQHandler
|
|
||||||
.thumb_set DMA1_Channel1_2_3_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Channel4_5_6_7_IRQHandler
|
|
||||||
.thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA2_DMAMUX1_OVR_IRQHandler
|
|
||||||
.thumb_set DMA2_DMAMUX1_OVR_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak LPTIM1_IRQHandler
|
|
||||||
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak LPTIM2_IRQHandler
|
|
||||||
.thumb_set LPTIM2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak LPTIM3_IRQHandler
|
|
||||||
.thumb_set LPTIM3_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM1_IRQHandler
|
|
||||||
.thumb_set TIM1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM2_IRQHandler
|
|
||||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM16_IRQHandler
|
|
||||||
.thumb_set TIM16_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM17_IRQHandler
|
|
||||||
.thumb_set TIM17_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak IPCC_C2_RX_C2_TX_IRQHandler
|
|
||||||
.thumb_set IPCC_C2_RX_C2_TX_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak HSEM_IRQHandler
|
|
||||||
.thumb_set HSEM_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak RNG_IRQHandler
|
|
||||||
.thumb_set RNG_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak AES_PKA_IRQHandler
|
|
||||||
.thumb_set AES_PKA_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak I2C1_IRQHandler
|
|
||||||
.thumb_set I2C1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak I2C2_IRQHandler
|
|
||||||
.thumb_set I2C2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak I2C3_IRQHandler
|
|
||||||
.thumb_set I2C3_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak SPI1_IRQHandler
|
|
||||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak SPI2_IRQHandler
|
|
||||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak USART1_IRQHandler
|
|
||||||
.thumb_set USART1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak USART2_IRQHandler
|
|
||||||
.thumb_set USART2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak LPUART1_IRQHandler
|
|
||||||
.thumb_set LPUART1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak SUBGHZSPI_IRQHandler
|
|
||||||
.thumb_set SUBGHZSPI_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak SUBGHZ_Radio_IRQHandler
|
|
||||||
.thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak SystemInit
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectonics *****END OF FILE****/
|
|
||||||
|
|
@ -1,435 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file startup_stm32wl55xx_cm4.s
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief STM32WL55xx devices Cortex-M4 vector table for GCC toolchain.
|
|
||||||
* This module performs:
|
|
||||||
* - Set the initial SP
|
|
||||||
* - Set the initial PC == Reset_Handler,
|
|
||||||
* - Set the vector table entries with the exceptions ISR address,
|
|
||||||
* - Branches to main in the C library (which eventually
|
|
||||||
* calls main()).
|
|
||||||
* After Reset the Cortex-M4 processor is in Thread mode,
|
|
||||||
* priority is Privileged, and the Stack is set to Main.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* Copyright (c) 2020(-2021) STMicroelectronics.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* This software is licensed under terms that can be found in the LICENSE file
|
|
||||||
* in the root directory of this software component.
|
|
||||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
.syntax unified
|
|
||||||
.cpu cortex-m4
|
|
||||||
.fpu softvfp
|
|
||||||
.thumb
|
|
||||||
|
|
||||||
.global g_pfnVectors
|
|
||||||
.global Default_Handler
|
|
||||||
|
|
||||||
/* start address for the initialization values of the .data section.
|
|
||||||
defined in linker script */
|
|
||||||
.word _sidata
|
|
||||||
/* start address for the .data section. defined in linker script */
|
|
||||||
.word _sdata
|
|
||||||
/* end address for the .data section. defined in linker script */
|
|
||||||
.word _edata
|
|
||||||
/* start address for the .bss section. defined in linker script */
|
|
||||||
.word _sbss
|
|
||||||
/* end address for the .bss section. defined in linker script */
|
|
||||||
.word _ebss
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief This is the code that gets called when the processor first
|
|
||||||
* starts execution following a reset event. Only the absolutely
|
|
||||||
* necessary set is performed, after which the application
|
|
||||||
* supplied main() routine is called.
|
|
||||||
* @param None
|
|
||||||
* @retval : None
|
|
||||||
*/
|
|
||||||
|
|
||||||
.section .text.Reset_Handler
|
|
||||||
.weak Reset_Handler
|
|
||||||
.type Reset_Handler, %function
|
|
||||||
Reset_Handler:
|
|
||||||
ldr r0, =_estack
|
|
||||||
mov sp, r0 /* set stack pointer */
|
|
||||||
|
|
||||||
/* Call the clock system initialization function.*/
|
|
||||||
bl SystemInit
|
|
||||||
|
|
||||||
/* Copy the data segment initializers from flash to SRAM */
|
|
||||||
ldr r0, =_sdata
|
|
||||||
ldr r1, =_edata
|
|
||||||
ldr r2, =_sidata
|
|
||||||
movs r3, #0
|
|
||||||
b LoopCopyDataInit
|
|
||||||
|
|
||||||
CopyDataInit:
|
|
||||||
ldr r4, [r2, r3]
|
|
||||||
str r4, [r0, r3]
|
|
||||||
adds r3, r3, #4
|
|
||||||
|
|
||||||
LoopCopyDataInit:
|
|
||||||
adds r4, r0, r3
|
|
||||||
cmp r4, r1
|
|
||||||
bcc CopyDataInit
|
|
||||||
|
|
||||||
/* Zero fill the bss segment. */
|
|
||||||
ldr r2, =_sbss
|
|
||||||
ldr r4, =_ebss
|
|
||||||
movs r3, #0
|
|
||||||
b LoopFillZerobss
|
|
||||||
|
|
||||||
FillZerobss:
|
|
||||||
str r3, [r2]
|
|
||||||
adds r2, r2, #4
|
|
||||||
|
|
||||||
LoopFillZerobss:
|
|
||||||
cmp r2, r4
|
|
||||||
bcc FillZerobss
|
|
||||||
|
|
||||||
/* Call static constructors */
|
|
||||||
bl __libc_init_array
|
|
||||||
/* Call the application's entry point.*/
|
|
||||||
bl entry
|
|
||||||
|
|
||||||
LoopForever:
|
|
||||||
b LoopForever
|
|
||||||
|
|
||||||
.size Reset_Handler, .-Reset_Handler
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief This is the code that gets called when the processor receives an
|
|
||||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
|
||||||
* the system state for examination by a debugger.
|
|
||||||
*
|
|
||||||
* @param None
|
|
||||||
* @retval : None
|
|
||||||
*/
|
|
||||||
.section .text.Default_Handler,"ax",%progbits
|
|
||||||
Default_Handler:
|
|
||||||
Infinite_Loop:
|
|
||||||
b Infinite_Loop
|
|
||||||
.size Default_Handler, .-Default_Handler
|
|
||||||
|
|
||||||
/******************************************************************************
|
|
||||||
*
|
|
||||||
* The STM32WL55xx Cortex-M4 vector table. Note that the proper constructs
|
|
||||||
* must be placed on this to ensure that it ends up at physical address
|
|
||||||
* 0x0000.0000.
|
|
||||||
*
|
|
||||||
******************************************************************************/
|
|
||||||
.section .isr_vector,"a",%progbits
|
|
||||||
.type g_pfnVectors, %object
|
|
||||||
.size g_pfnVectors, .-g_pfnVectors
|
|
||||||
|
|
||||||
g_pfnVectors:
|
|
||||||
.word _estack
|
|
||||||
.word Reset_Handler
|
|
||||||
.word NMI_Handler
|
|
||||||
.word HardFault_Handler
|
|
||||||
.word MemManage_Handler
|
|
||||||
.word BusFault_Handler
|
|
||||||
.word UsageFault_Handler
|
|
||||||
.word 0
|
|
||||||
.word 0
|
|
||||||
.word 0
|
|
||||||
.word 0
|
|
||||||
.word SVC_Handler
|
|
||||||
.word DebugMon_Handler
|
|
||||||
.word 0
|
|
||||||
.word PendSV_Handler
|
|
||||||
.word SysTick_Handler
|
|
||||||
.word WWDG_IRQHandler /* Window Watchdog interrupt */
|
|
||||||
.word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */
|
|
||||||
.word TAMP_STAMP_LSECSS_SSRU_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
|
|
||||||
.word RTC_WKUP_IRQHandler /* RTC wakeup interrupt through EXTI[19] */
|
|
||||||
.word FLASH_IRQHandler /* Flash memory global interrupt and Flash memory ECC */
|
|
||||||
.word RCC_IRQHandler /* RCC global interrupt */
|
|
||||||
.word EXTI0_IRQHandler /* EXTI line 0 interrupt */
|
|
||||||
.word EXTI1_IRQHandler /* EXTI line 1 interrupt */
|
|
||||||
.word EXTI2_IRQHandler /* EXTI line 2 interrupt */
|
|
||||||
.word EXTI3_IRQHandler /* EXTI line 3 interrupt */
|
|
||||||
.word EXTI4_IRQHandler /* EXTI line 4 interrupt */
|
|
||||||
.word DMA1_Channel1_IRQHandler /* DMA1 channel 1 interrupt */
|
|
||||||
.word DMA1_Channel2_IRQHandler /* DMA1 channel 2 interrupt */
|
|
||||||
.word DMA1_Channel3_IRQHandler /* DMA1 channel 3 interrupt */
|
|
||||||
.word DMA1_Channel4_IRQHandler /* DMA1 channel 4 interrupt */
|
|
||||||
.word DMA1_Channel5_IRQHandler /* DMA1 channel 5 interrupt */
|
|
||||||
.word DMA1_Channel6_IRQHandler /* DMA1 channel 6 interrupt */
|
|
||||||
.word DMA1_Channel7_IRQHandler /* DMA1 channel 7 interrupt */
|
|
||||||
.word ADC_IRQHandler /* ADC interrupt */
|
|
||||||
.word DAC_IRQHandler /* DAC interrupt */
|
|
||||||
.word C2SEV_PWR_C2H_IRQHandler /* CPU M0+ SEV Interrupt */
|
|
||||||
.word COMP_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */
|
|
||||||
.word EXTI9_5_IRQHandler /* EXTI line 9_5 interrupt */
|
|
||||||
.word TIM1_BRK_IRQHandler /* Timer 1 break interrupt */
|
|
||||||
.word TIM1_UP_IRQHandler /* Timer 1 Update */
|
|
||||||
.word TIM1_TRG_COM_IRQHandler /* Timer 1 trigger and communication */
|
|
||||||
.word TIM1_CC_IRQHandler /* Timer 1 capture compare interrupt */
|
|
||||||
.word TIM2_IRQHandler /* TIM2 global interrupt */
|
|
||||||
.word TIM16_IRQHandler /* Timer 16 global interrupt */
|
|
||||||
.word TIM17_IRQHandler /* Timer 17 global interrupt */
|
|
||||||
.word I2C1_EV_IRQHandler /* I2C1 event interrupt */
|
|
||||||
.word I2C1_ER_IRQHandler /* I2C1 event interrupt */
|
|
||||||
.word I2C2_EV_IRQHandler /* I2C2 error interrupt */
|
|
||||||
.word I2C2_ER_IRQHandler /* I2C2 error interrupt */
|
|
||||||
.word SPI1_IRQHandler /* SPI1 global interrupt */
|
|
||||||
.word SPI2_IRQHandler /* SPI2 global interrupt */
|
|
||||||
.word USART1_IRQHandler /* USART1 global interrupt */
|
|
||||||
.word USART2_IRQHandler /* USART2 global interrupt */
|
|
||||||
.word LPUART1_IRQHandler /* LPUART1 global interrupt */
|
|
||||||
.word LPTIM1_IRQHandler /* LPtimer 1 global interrupt */
|
|
||||||
.word LPTIM2_IRQHandler /* LPtimer 2 global interrupt */
|
|
||||||
.word EXTI15_10_IRQHandler /* EXTI line 15_10] interrupt through EXTI */
|
|
||||||
.word RTC_Alarm_IRQHandler /* RTC Alarms A & B interrupt */
|
|
||||||
.word LPTIM3_IRQHandler /* LPtimer 3 global interrupt */
|
|
||||||
.word SUBGHZSPI_IRQHandler /* SUBGHZSPI global interrupt */
|
|
||||||
.word IPCC_C1_RX_IRQHandler /* IPCC CPU1 RX occupied interrupt */
|
|
||||||
.word IPCC_C1_TX_IRQHandler /* IPCC CPU1 RX free interrupt */
|
|
||||||
.word HSEM_IRQHandler /* Semaphore interrupt 0 to CPU1 */
|
|
||||||
.word I2C3_EV_IRQHandler /* I2C3 event interrupt */
|
|
||||||
.word I2C3_ER_IRQHandler /* I2C3 error interrupt */
|
|
||||||
.word SUBGHZ_Radio_IRQHandler /* Radio IRQs RFBUSY interrupt through EXTI */
|
|
||||||
.word AES_IRQHandler /* AES global interrupt */
|
|
||||||
.word RNG_IRQHandler /* RNG interrupt */
|
|
||||||
.word PKA_IRQHandler /* PKA interrupt */
|
|
||||||
.word DMA2_Channel1_IRQHandler /* DMA2 channel 1 interrupt */
|
|
||||||
.word DMA2_Channel2_IRQHandler /* DMA2 channel 2 interrupt */
|
|
||||||
.word DMA2_Channel3_IRQHandler /* DMA2 channel 3 interrupt */
|
|
||||||
.word DMA2_Channel4_IRQHandler /* DMA2 channel 4 interrupt */
|
|
||||||
.word DMA2_Channel5_IRQHandler /* DMA2 channel 5 interrupt */
|
|
||||||
.word DMA2_Channel6_IRQHandler /* DMA2 channel 6 interrupt */
|
|
||||||
.word DMA2_Channel7_IRQHandler /* DMA2 channel 7 interrupt */
|
|
||||||
.word DMAMUX1_OVR_IRQHandler /* DMAMUX overrun interrupt */
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
*
|
|
||||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
|
||||||
* As they are weak aliases, any function with the same name will override
|
|
||||||
* this definition.
|
|
||||||
*
|
|
||||||
*******************************************************************************/
|
|
||||||
|
|
||||||
.weak NMI_Handler
|
|
||||||
.thumb_set NMI_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak HardFault_Handler
|
|
||||||
.thumb_set HardFault_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak MemManage_Handler
|
|
||||||
.thumb_set MemManage_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak BusFault_Handler
|
|
||||||
.thumb_set BusFault_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak UsageFault_Handler
|
|
||||||
.thumb_set UsageFault_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak SVC_Handler
|
|
||||||
.thumb_set SVC_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak DebugMon_Handler
|
|
||||||
.thumb_set DebugMon_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak PendSV_Handler
|
|
||||||
.thumb_set PendSV_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak SysTick_Handler
|
|
||||||
.thumb_set SysTick_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak WWDG_IRQHandler
|
|
||||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak PVD_PVM_IRQHandler
|
|
||||||
.thumb_set PVD_PVM_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TAMP_STAMP_LSECSS_SSRU_IRQHandler
|
|
||||||
.thumb_set TAMP_STAMP_LSECSS_SSRU_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak RTC_WKUP_IRQHandler
|
|
||||||
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak FLASH_IRQHandler
|
|
||||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak RCC_IRQHandler
|
|
||||||
.thumb_set RCC_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak EXTI0_IRQHandler
|
|
||||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak EXTI1_IRQHandler
|
|
||||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak EXTI2_IRQHandler
|
|
||||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak EXTI3_IRQHandler
|
|
||||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak EXTI4_IRQHandler
|
|
||||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Channel1_IRQHandler
|
|
||||||
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Channel2_IRQHandler
|
|
||||||
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Channel3_IRQHandler
|
|
||||||
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Channel4_IRQHandler
|
|
||||||
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Channel5_IRQHandler
|
|
||||||
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Channel6_IRQHandler
|
|
||||||
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Channel7_IRQHandler
|
|
||||||
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak ADC_IRQHandler
|
|
||||||
.thumb_set ADC_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DAC_IRQHandler
|
|
||||||
.thumb_set DAC_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak C2SEV_PWR_C2H_IRQHandler
|
|
||||||
.thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak COMP_IRQHandler
|
|
||||||
.thumb_set COMP_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak EXTI9_5_IRQHandler
|
|
||||||
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM1_BRK_IRQHandler
|
|
||||||
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM1_UP_IRQHandler
|
|
||||||
.thumb_set TIM1_UP_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM1_TRG_COM_IRQHandler
|
|
||||||
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM1_CC_IRQHandler
|
|
||||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM2_IRQHandler
|
|
||||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM16_IRQHandler
|
|
||||||
.thumb_set TIM16_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM17_IRQHandler
|
|
||||||
.thumb_set TIM17_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak I2C1_EV_IRQHandler
|
|
||||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak I2C1_ER_IRQHandler
|
|
||||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak I2C2_EV_IRQHandler
|
|
||||||
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak I2C2_ER_IRQHandler
|
|
||||||
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak SPI1_IRQHandler
|
|
||||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak SPI2_IRQHandler
|
|
||||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak USART1_IRQHandler
|
|
||||||
.thumb_set USART1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak USART2_IRQHandler
|
|
||||||
.thumb_set USART2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak LPUART1_IRQHandler
|
|
||||||
.thumb_set LPUART1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak LPTIM1_IRQHandler
|
|
||||||
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak LPTIM2_IRQHandler
|
|
||||||
.thumb_set LPTIM2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak EXTI15_10_IRQHandler
|
|
||||||
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak RTC_Alarm_IRQHandler
|
|
||||||
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak LPTIM3_IRQHandler
|
|
||||||
.thumb_set LPTIM3_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak SUBGHZSPI_IRQHandler
|
|
||||||
.thumb_set SUBGHZSPI_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak IPCC_C1_RX_IRQHandler
|
|
||||||
.thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak IPCC_C1_TX_IRQHandler
|
|
||||||
.thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak HSEM_IRQHandler
|
|
||||||
.thumb_set HSEM_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak I2C3_EV_IRQHandler
|
|
||||||
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak I2C3_ER_IRQHandler
|
|
||||||
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak SUBGHZ_Radio_IRQHandler
|
|
||||||
.thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak AES_IRQHandler
|
|
||||||
.thumb_set AES_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak RNG_IRQHandler
|
|
||||||
.thumb_set RNG_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak PKA_IRQHandler
|
|
||||||
.thumb_set PKA_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA2_Channel1_IRQHandler
|
|
||||||
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA2_Channel2_IRQHandler
|
|
||||||
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA2_Channel3_IRQHandler
|
|
||||||
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA2_Channel4_IRQHandler
|
|
||||||
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA2_Channel5_IRQHandler
|
|
||||||
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA2_Channel6_IRQHandler
|
|
||||||
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA2_Channel7_IRQHandler
|
|
||||||
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMAMUX1_OVR_IRQHandler
|
|
||||||
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak SystemInit
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectonics *****END OF FILE****/
|
|
||||||
|
|
@ -1,426 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file startup_stm32wle4xx.s
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief STM32WLE4xx devices vector table for GCC toolchain.
|
|
||||||
* This module performs:
|
|
||||||
* - Set the initial SP
|
|
||||||
* - Set the initial PC == Reset_Handler,
|
|
||||||
* - Set the vector table entries with the exceptions ISR address,
|
|
||||||
* - Branches to main in the C library (which eventually
|
|
||||||
* calls main()).
|
|
||||||
* After Reset the Cortex-M4 processor is in Thread mode,
|
|
||||||
* priority is Privileged, and the Stack is set to Main.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* Copyright (c) 2020(-2021) STMicroelectronics.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* This software is licensed under terms that can be found in the LICENSE file
|
|
||||||
* in the root directory of this software component.
|
|
||||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
.syntax unified
|
|
||||||
.cpu cortex-m4
|
|
||||||
.fpu softvfp
|
|
||||||
.thumb
|
|
||||||
|
|
||||||
.global g_pfnVectors
|
|
||||||
.global Default_Handler
|
|
||||||
|
|
||||||
/* start address for the initialization values of the .data section.
|
|
||||||
defined in linker script */
|
|
||||||
.word _sidata
|
|
||||||
/* start address for the .data section. defined in linker script */
|
|
||||||
.word _sdata
|
|
||||||
/* end address for the .data section. defined in linker script */
|
|
||||||
.word _edata
|
|
||||||
/* start address for the .bss section. defined in linker script */
|
|
||||||
.word _sbss
|
|
||||||
/* end address for the .bss section. defined in linker script */
|
|
||||||
.word _ebss
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief This is the code that gets called when the processor first
|
|
||||||
* starts execution following a reset event. Only the absolutely
|
|
||||||
* necessary set is performed, after which the application
|
|
||||||
* supplied main() routine is called.
|
|
||||||
* @param None
|
|
||||||
* @retval : None
|
|
||||||
*/
|
|
||||||
|
|
||||||
.section .text.Reset_Handler
|
|
||||||
.weak Reset_Handler
|
|
||||||
.type Reset_Handler, %function
|
|
||||||
Reset_Handler:
|
|
||||||
ldr r0, =_estack
|
|
||||||
mov sp, r0 /* set stack pointer */
|
|
||||||
|
|
||||||
/* Call the clock system initialization function.*/
|
|
||||||
bl SystemInit
|
|
||||||
|
|
||||||
/* Copy the data segment initializers from flash to SRAM */
|
|
||||||
ldr r0, =_sdata
|
|
||||||
ldr r1, =_edata
|
|
||||||
ldr r2, =_sidata
|
|
||||||
movs r3, #0
|
|
||||||
b LoopCopyDataInit
|
|
||||||
|
|
||||||
CopyDataInit:
|
|
||||||
ldr r4, [r2, r3]
|
|
||||||
str r4, [r0, r3]
|
|
||||||
adds r3, r3, #4
|
|
||||||
|
|
||||||
LoopCopyDataInit:
|
|
||||||
adds r4, r0, r3
|
|
||||||
cmp r4, r1
|
|
||||||
bcc CopyDataInit
|
|
||||||
|
|
||||||
/* Zero fill the bss segment. */
|
|
||||||
ldr r2, =_sbss
|
|
||||||
ldr r4, =_ebss
|
|
||||||
movs r3, #0
|
|
||||||
b LoopFillZerobss
|
|
||||||
|
|
||||||
FillZerobss:
|
|
||||||
str r3, [r2]
|
|
||||||
adds r2, r2, #4
|
|
||||||
|
|
||||||
LoopFillZerobss:
|
|
||||||
cmp r2, r4
|
|
||||||
bcc FillZerobss
|
|
||||||
|
|
||||||
/* Call static constructors */
|
|
||||||
bl __libc_init_array
|
|
||||||
/* Call the application's entry point.*/
|
|
||||||
bl entry
|
|
||||||
|
|
||||||
LoopForever:
|
|
||||||
b LoopForever
|
|
||||||
|
|
||||||
.size Reset_Handler, .-Reset_Handler
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief This is the code that gets called when the processor receives an
|
|
||||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
|
||||||
* the system state for examination by a debugger.
|
|
||||||
*
|
|
||||||
* @param None
|
|
||||||
* @retval : None
|
|
||||||
*/
|
|
||||||
.section .text.Default_Handler,"ax",%progbits
|
|
||||||
Default_Handler:
|
|
||||||
Infinite_Loop:
|
|
||||||
b Infinite_Loop
|
|
||||||
.size Default_Handler, .-Default_Handler
|
|
||||||
|
|
||||||
/******************************************************************************
|
|
||||||
*
|
|
||||||
* The STM32WLE4xx vector table. Note that the proper constructs
|
|
||||||
* must be placed on this to ensure that it ends up at physical address
|
|
||||||
* 0x0000.0000.
|
|
||||||
*
|
|
||||||
******************************************************************************/
|
|
||||||
.section .isr_vector,"a",%progbits
|
|
||||||
.type g_pfnVectors, %object
|
|
||||||
.size g_pfnVectors, .-g_pfnVectors
|
|
||||||
|
|
||||||
g_pfnVectors:
|
|
||||||
.word _estack
|
|
||||||
.word Reset_Handler
|
|
||||||
.word NMI_Handler
|
|
||||||
.word HardFault_Handler
|
|
||||||
.word MemManage_Handler
|
|
||||||
.word BusFault_Handler
|
|
||||||
.word UsageFault_Handler
|
|
||||||
.word 0
|
|
||||||
.word 0
|
|
||||||
.word 0
|
|
||||||
.word 0
|
|
||||||
.word SVC_Handler
|
|
||||||
.word DebugMon_Handler
|
|
||||||
.word 0
|
|
||||||
.word PendSV_Handler
|
|
||||||
.word SysTick_Handler
|
|
||||||
.word WWDG_IRQHandler /* Window Watchdog interrupt */
|
|
||||||
.word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */
|
|
||||||
.word TAMP_STAMP_LSECSS_SSRU_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
|
|
||||||
.word RTC_WKUP_IRQHandler /* RTC wakeup interrupt through EXTI[19] */
|
|
||||||
.word FLASH_IRQHandler /* Flash memory global interrupt and Flash memory ECC */
|
|
||||||
.word RCC_IRQHandler /* RCC global interrupt */
|
|
||||||
.word EXTI0_IRQHandler /* EXTI line 0 interrupt */
|
|
||||||
.word EXTI1_IRQHandler /* EXTI line 1 interrupt */
|
|
||||||
.word EXTI2_IRQHandler /* EXTI line 2 interrupt */
|
|
||||||
.word EXTI3_IRQHandler /* EXTI line 3 interrupt */
|
|
||||||
.word EXTI4_IRQHandler /* EXTI line 4 interrupt */
|
|
||||||
.word DMA1_Channel1_IRQHandler /* DMA1 channel 1 interrupt */
|
|
||||||
.word DMA1_Channel2_IRQHandler /* DMA1 channel 2 interrupt */
|
|
||||||
.word DMA1_Channel3_IRQHandler /* DMA1 channel 3 interrupt */
|
|
||||||
.word DMA1_Channel4_IRQHandler /* DMA1 channel 4 interrupt */
|
|
||||||
.word DMA1_Channel5_IRQHandler /* DMA1 channel 5 interrupt */
|
|
||||||
.word DMA1_Channel6_IRQHandler /* DMA1 channel 6 interrupt */
|
|
||||||
.word DMA1_Channel7_IRQHandler /* DMA1 channel 7 interrupt */
|
|
||||||
.word ADC_IRQHandler /* ADC interrupt */
|
|
||||||
.word DAC_IRQHandler /* DAC interrupt */
|
|
||||||
.word 0 /* Reserved */
|
|
||||||
.word COMP_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */
|
|
||||||
.word EXTI9_5_IRQHandler /* EXTI line 9_5 interrupt */
|
|
||||||
.word TIM1_BRK_IRQHandler /* Timer 1 break interrupt */
|
|
||||||
.word TIM1_UP_IRQHandler /* Timer 1 Update */
|
|
||||||
.word TIM1_TRG_COM_IRQHandler /* Timer 1 trigger and communication */
|
|
||||||
.word TIM1_CC_IRQHandler /* Timer 1 capture compare interrupt */
|
|
||||||
.word TIM2_IRQHandler /* TIM2 global interrupt */
|
|
||||||
.word TIM16_IRQHandler /* Timer 16 global interrupt */
|
|
||||||
.word TIM17_IRQHandler /* Timer 17 global interrupt */
|
|
||||||
.word I2C1_EV_IRQHandler /* I2C1 event interrupt */
|
|
||||||
.word I2C1_ER_IRQHandler /* I2C1 event interrupt */
|
|
||||||
.word I2C2_EV_IRQHandler /* I2C2 error interrupt */
|
|
||||||
.word I2C2_ER_IRQHandler /* I2C2 error interrupt */
|
|
||||||
.word SPI1_IRQHandler /* SPI1 global interrupt */
|
|
||||||
.word SPI2_IRQHandler /* SPI2 global interrupt */
|
|
||||||
.word USART1_IRQHandler /* USART1 global interrupt */
|
|
||||||
.word USART2_IRQHandler /* USART2 global interrupt */
|
|
||||||
.word LPUART1_IRQHandler /* LPUART1 global interrupt */
|
|
||||||
.word LPTIM1_IRQHandler /* LPtimer 1 global interrupt */
|
|
||||||
.word LPTIM2_IRQHandler /* LPtimer 2 global interrupt */
|
|
||||||
.word EXTI15_10_IRQHandler /* EXTI line 15_10] interrupt through EXTI */
|
|
||||||
.word RTC_Alarm_IRQHandler /* RTC Alarms A & B interrupt */
|
|
||||||
.word LPTIM3_IRQHandler /* LPtimer 3 global interrupt */
|
|
||||||
.word SUBGHZSPI_IRQHandler /* SUBGHZSPI global interrupt */
|
|
||||||
.word 0 /* Reserved */
|
|
||||||
.word 0 /* Reserved */
|
|
||||||
.word HSEM_IRQHandler /* Semaphore interrupt 0 to CPU1 */
|
|
||||||
.word I2C3_EV_IRQHandler /* I2C3 event interrupt */
|
|
||||||
.word I2C3_ER_IRQHandler /* I2C3 error interrupt */
|
|
||||||
.word SUBGHZ_Radio_IRQHandler /* Radio IRQs RFBUSY interrupt through EXTI */
|
|
||||||
.word AES_IRQHandler /* AES global interrupt */
|
|
||||||
.word RNG_IRQHandler /* RNG interrupt */
|
|
||||||
.word PKA_IRQHandler /* PKA interrupt */
|
|
||||||
.word DMA2_Channel1_IRQHandler /* DMA2 channel 1 interrupt */
|
|
||||||
.word DMA2_Channel2_IRQHandler /* DMA2 channel 2 interrupt */
|
|
||||||
.word DMA2_Channel3_IRQHandler /* DMA2 channel 3 interrupt */
|
|
||||||
.word DMA2_Channel4_IRQHandler /* DMA2 channel 4 interrupt */
|
|
||||||
.word DMA2_Channel5_IRQHandler /* DMA2 channel 5 interrupt */
|
|
||||||
.word DMA2_Channel6_IRQHandler /* DMA2 channel 6 interrupt */
|
|
||||||
.word DMA2_Channel7_IRQHandler /* DMA2 channel 7 interrupt */
|
|
||||||
.word DMAMUX1_OVR_IRQHandler /* DMAMUX overrun interrupt */
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
*
|
|
||||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
|
||||||
* As they are weak aliases, any function with the same name will override
|
|
||||||
* this definition.
|
|
||||||
*
|
|
||||||
*******************************************************************************/
|
|
||||||
|
|
||||||
.weak NMI_Handler
|
|
||||||
.thumb_set NMI_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak HardFault_Handler
|
|
||||||
.thumb_set HardFault_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak MemManage_Handler
|
|
||||||
.thumb_set MemManage_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak BusFault_Handler
|
|
||||||
.thumb_set BusFault_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak UsageFault_Handler
|
|
||||||
.thumb_set UsageFault_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak SVC_Handler
|
|
||||||
.thumb_set SVC_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak DebugMon_Handler
|
|
||||||
.thumb_set DebugMon_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak PendSV_Handler
|
|
||||||
.thumb_set PendSV_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak SysTick_Handler
|
|
||||||
.thumb_set SysTick_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak WWDG_IRQHandler
|
|
||||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak PVD_PVM_IRQHandler
|
|
||||||
.thumb_set PVD_PVM_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TAMP_STAMP_LSECSS_SSRU_IRQHandler
|
|
||||||
.thumb_set TAMP_STAMP_LSECSS_SSRU_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak RTC_WKUP_IRQHandler
|
|
||||||
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak FLASH_IRQHandler
|
|
||||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak RCC_IRQHandler
|
|
||||||
.thumb_set RCC_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak EXTI0_IRQHandler
|
|
||||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak EXTI1_IRQHandler
|
|
||||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak EXTI2_IRQHandler
|
|
||||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak EXTI3_IRQHandler
|
|
||||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak EXTI4_IRQHandler
|
|
||||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Channel1_IRQHandler
|
|
||||||
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Channel2_IRQHandler
|
|
||||||
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Channel3_IRQHandler
|
|
||||||
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Channel4_IRQHandler
|
|
||||||
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Channel5_IRQHandler
|
|
||||||
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Channel6_IRQHandler
|
|
||||||
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Channel7_IRQHandler
|
|
||||||
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak ADC_IRQHandler
|
|
||||||
.thumb_set ADC_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DAC_IRQHandler
|
|
||||||
.thumb_set DAC_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak COMP_IRQHandler
|
|
||||||
.thumb_set COMP_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak EXTI9_5_IRQHandler
|
|
||||||
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM1_BRK_IRQHandler
|
|
||||||
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM1_UP_IRQHandler
|
|
||||||
.thumb_set TIM1_UP_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM1_TRG_COM_IRQHandler
|
|
||||||
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM1_CC_IRQHandler
|
|
||||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM2_IRQHandler
|
|
||||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM16_IRQHandler
|
|
||||||
.thumb_set TIM16_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM17_IRQHandler
|
|
||||||
.thumb_set TIM17_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak I2C1_EV_IRQHandler
|
|
||||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak I2C1_ER_IRQHandler
|
|
||||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak I2C2_EV_IRQHandler
|
|
||||||
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak I2C2_ER_IRQHandler
|
|
||||||
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak SPI1_IRQHandler
|
|
||||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak SPI2_IRQHandler
|
|
||||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak USART1_IRQHandler
|
|
||||||
.thumb_set USART1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak USART2_IRQHandler
|
|
||||||
.thumb_set USART2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak LPUART1_IRQHandler
|
|
||||||
.thumb_set LPUART1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak LPTIM1_IRQHandler
|
|
||||||
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak LPTIM2_IRQHandler
|
|
||||||
.thumb_set LPTIM2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak EXTI15_10_IRQHandler
|
|
||||||
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak RTC_Alarm_IRQHandler
|
|
||||||
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak LPTIM3_IRQHandler
|
|
||||||
.thumb_set LPTIM3_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak SUBGHZSPI_IRQHandler
|
|
||||||
.thumb_set SUBGHZSPI_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak HSEM_IRQHandler
|
|
||||||
.thumb_set HSEM_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak I2C3_EV_IRQHandler
|
|
||||||
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak I2C3_ER_IRQHandler
|
|
||||||
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak SUBGHZ_Radio_IRQHandler
|
|
||||||
.thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak AES_IRQHandler
|
|
||||||
.thumb_set AES_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak RNG_IRQHandler
|
|
||||||
.thumb_set RNG_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak PKA_IRQHandler
|
|
||||||
.thumb_set PKA_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA2_Channel1_IRQHandler
|
|
||||||
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA2_Channel2_IRQHandler
|
|
||||||
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA2_Channel3_IRQHandler
|
|
||||||
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA2_Channel4_IRQHandler
|
|
||||||
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA2_Channel5_IRQHandler
|
|
||||||
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA2_Channel6_IRQHandler
|
|
||||||
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA2_Channel7_IRQHandler
|
|
||||||
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMAMUX1_OVR_IRQHandler
|
|
||||||
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak SystemInit
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectonics *****END OF FILE****/
|
|
||||||
|
|
@ -1,426 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file startup_stm32wle5xx.s
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief STM32WLE5xx devices vector table for GCC toolchain.
|
|
||||||
* This module performs:
|
|
||||||
* - Set the initial SP
|
|
||||||
* - Set the initial PC == Reset_Handler,
|
|
||||||
* - Set the vector table entries with the exceptions ISR address,
|
|
||||||
* - Branches to main in the C library (which eventually
|
|
||||||
* calls main()).
|
|
||||||
* After Reset the Cortex-M4 processor is in Thread mode,
|
|
||||||
* priority is Privileged, and the Stack is set to Main.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* Copyright (c) 2020(-2021) STMicroelectronics.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* This software is licensed under terms that can be found in the LICENSE file
|
|
||||||
* in the root directory of this software component.
|
|
||||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
.syntax unified
|
|
||||||
.cpu cortex-m4
|
|
||||||
.fpu softvfp
|
|
||||||
.thumb
|
|
||||||
|
|
||||||
.global g_pfnVectors
|
|
||||||
.global Default_Handler
|
|
||||||
|
|
||||||
/* start address for the initialization values of the .data section.
|
|
||||||
defined in linker script */
|
|
||||||
.word _sidata
|
|
||||||
/* start address for the .data section. defined in linker script */
|
|
||||||
.word _sdata
|
|
||||||
/* end address for the .data section. defined in linker script */
|
|
||||||
.word _edata
|
|
||||||
/* start address for the .bss section. defined in linker script */
|
|
||||||
.word _sbss
|
|
||||||
/* end address for the .bss section. defined in linker script */
|
|
||||||
.word _ebss
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief This is the code that gets called when the processor first
|
|
||||||
* starts execution following a reset event. Only the absolutely
|
|
||||||
* necessary set is performed, after which the application
|
|
||||||
* supplied main() routine is called.
|
|
||||||
* @param None
|
|
||||||
* @retval : None
|
|
||||||
*/
|
|
||||||
|
|
||||||
.section .text.Reset_Handler
|
|
||||||
.weak Reset_Handler
|
|
||||||
.type Reset_Handler, %function
|
|
||||||
Reset_Handler:
|
|
||||||
ldr r0, =_estack
|
|
||||||
mov sp, r0 /* set stack pointer */
|
|
||||||
|
|
||||||
/* Call the clock system initialization function.*/
|
|
||||||
bl SystemInit
|
|
||||||
|
|
||||||
/* Copy the data segment initializers from flash to SRAM */
|
|
||||||
ldr r0, =_sdata
|
|
||||||
ldr r1, =_edata
|
|
||||||
ldr r2, =_sidata
|
|
||||||
movs r3, #0
|
|
||||||
b LoopCopyDataInit
|
|
||||||
|
|
||||||
CopyDataInit:
|
|
||||||
ldr r4, [r2, r3]
|
|
||||||
str r4, [r0, r3]
|
|
||||||
adds r3, r3, #4
|
|
||||||
|
|
||||||
LoopCopyDataInit:
|
|
||||||
adds r4, r0, r3
|
|
||||||
cmp r4, r1
|
|
||||||
bcc CopyDataInit
|
|
||||||
|
|
||||||
/* Zero fill the bss segment. */
|
|
||||||
ldr r2, =_sbss
|
|
||||||
ldr r4, =_ebss
|
|
||||||
movs r3, #0
|
|
||||||
b LoopFillZerobss
|
|
||||||
|
|
||||||
FillZerobss:
|
|
||||||
str r3, [r2]
|
|
||||||
adds r2, r2, #4
|
|
||||||
|
|
||||||
LoopFillZerobss:
|
|
||||||
cmp r2, r4
|
|
||||||
bcc FillZerobss
|
|
||||||
|
|
||||||
/* Call static constructors */
|
|
||||||
bl __libc_init_array
|
|
||||||
/* Call the application's entry point.*/
|
|
||||||
bl entry
|
|
||||||
|
|
||||||
LoopForever:
|
|
||||||
b LoopForever
|
|
||||||
|
|
||||||
.size Reset_Handler, .-Reset_Handler
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief This is the code that gets called when the processor receives an
|
|
||||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
|
||||||
* the system state for examination by a debugger.
|
|
||||||
*
|
|
||||||
* @param None
|
|
||||||
* @retval : None
|
|
||||||
*/
|
|
||||||
.section .text.Default_Handler,"ax",%progbits
|
|
||||||
Default_Handler:
|
|
||||||
Infinite_Loop:
|
|
||||||
b Infinite_Loop
|
|
||||||
.size Default_Handler, .-Default_Handler
|
|
||||||
|
|
||||||
/******************************************************************************
|
|
||||||
*
|
|
||||||
* The STM32WLE5xx vector table. Note that the proper constructs
|
|
||||||
* must be placed on this to ensure that it ends up at physical address
|
|
||||||
* 0x0000.0000.
|
|
||||||
*
|
|
||||||
******************************************************************************/
|
|
||||||
.section .isr_vector,"a",%progbits
|
|
||||||
.type g_pfnVectors, %object
|
|
||||||
.size g_pfnVectors, .-g_pfnVectors
|
|
||||||
|
|
||||||
g_pfnVectors:
|
|
||||||
.word _estack
|
|
||||||
.word Reset_Handler
|
|
||||||
.word NMI_Handler
|
|
||||||
.word HardFault_Handler
|
|
||||||
.word MemManage_Handler
|
|
||||||
.word BusFault_Handler
|
|
||||||
.word UsageFault_Handler
|
|
||||||
.word 0
|
|
||||||
.word 0
|
|
||||||
.word 0
|
|
||||||
.word 0
|
|
||||||
.word SVC_Handler
|
|
||||||
.word DebugMon_Handler
|
|
||||||
.word 0
|
|
||||||
.word PendSV_Handler
|
|
||||||
.word SysTick_Handler
|
|
||||||
.word WWDG_IRQHandler /* Window Watchdog interrupt */
|
|
||||||
.word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */
|
|
||||||
.word TAMP_STAMP_LSECSS_SSRU_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
|
|
||||||
.word RTC_WKUP_IRQHandler /* RTC wakeup interrupt through EXTI[19] */
|
|
||||||
.word FLASH_IRQHandler /* Flash memory global interrupt and Flash memory ECC */
|
|
||||||
.word RCC_IRQHandler /* RCC global interrupt */
|
|
||||||
.word EXTI0_IRQHandler /* EXTI line 0 interrupt */
|
|
||||||
.word EXTI1_IRQHandler /* EXTI line 1 interrupt */
|
|
||||||
.word EXTI2_IRQHandler /* EXTI line 2 interrupt */
|
|
||||||
.word EXTI3_IRQHandler /* EXTI line 3 interrupt */
|
|
||||||
.word EXTI4_IRQHandler /* EXTI line 4 interrupt */
|
|
||||||
.word DMA1_Channel1_IRQHandler /* DMA1 channel 1 interrupt */
|
|
||||||
.word DMA1_Channel2_IRQHandler /* DMA1 channel 2 interrupt */
|
|
||||||
.word DMA1_Channel3_IRQHandler /* DMA1 channel 3 interrupt */
|
|
||||||
.word DMA1_Channel4_IRQHandler /* DMA1 channel 4 interrupt */
|
|
||||||
.word DMA1_Channel5_IRQHandler /* DMA1 channel 5 interrupt */
|
|
||||||
.word DMA1_Channel6_IRQHandler /* DMA1 channel 6 interrupt */
|
|
||||||
.word DMA1_Channel7_IRQHandler /* DMA1 channel 7 interrupt */
|
|
||||||
.word ADC_IRQHandler /* ADC interrupt */
|
|
||||||
.word DAC_IRQHandler /* DAC interrupt */
|
|
||||||
.word 0 /* Reserved */
|
|
||||||
.word COMP_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */
|
|
||||||
.word EXTI9_5_IRQHandler /* EXTI line 9_5 interrupt */
|
|
||||||
.word TIM1_BRK_IRQHandler /* Timer 1 break interrupt */
|
|
||||||
.word TIM1_UP_IRQHandler /* Timer 1 Update */
|
|
||||||
.word TIM1_TRG_COM_IRQHandler /* Timer 1 trigger and communication */
|
|
||||||
.word TIM1_CC_IRQHandler /* Timer 1 capture compare interrupt */
|
|
||||||
.word TIM2_IRQHandler /* TIM2 global interrupt */
|
|
||||||
.word TIM16_IRQHandler /* Timer 16 global interrupt */
|
|
||||||
.word TIM17_IRQHandler /* Timer 17 global interrupt */
|
|
||||||
.word I2C1_EV_IRQHandler /* I2C1 event interrupt */
|
|
||||||
.word I2C1_ER_IRQHandler /* I2C1 event interrupt */
|
|
||||||
.word I2C2_EV_IRQHandler /* I2C2 error interrupt */
|
|
||||||
.word I2C2_ER_IRQHandler /* I2C2 error interrupt */
|
|
||||||
.word SPI1_IRQHandler /* SPI1 global interrupt */
|
|
||||||
.word SPI2_IRQHandler /* SPI2 global interrupt */
|
|
||||||
.word USART1_IRQHandler /* USART1 global interrupt */
|
|
||||||
.word USART2_IRQHandler /* USART2 global interrupt */
|
|
||||||
.word LPUART1_IRQHandler /* LPUART1 global interrupt */
|
|
||||||
.word LPTIM1_IRQHandler /* LPtimer 1 global interrupt */
|
|
||||||
.word LPTIM2_IRQHandler /* LPtimer 2 global interrupt */
|
|
||||||
.word EXTI15_10_IRQHandler /* EXTI line 15_10] interrupt through EXTI */
|
|
||||||
.word RTC_Alarm_IRQHandler /* RTC Alarms A & B interrupt */
|
|
||||||
.word LPTIM3_IRQHandler /* LPtimer 3 global interrupt */
|
|
||||||
.word SUBGHZSPI_IRQHandler /* SUBGHZSPI global interrupt */
|
|
||||||
.word 0 /* Reserved */
|
|
||||||
.word 0 /* Reserved */
|
|
||||||
.word HSEM_IRQHandler /* Semaphore interrupt 0 to CPU1 */
|
|
||||||
.word I2C3_EV_IRQHandler /* I2C3 event interrupt */
|
|
||||||
.word I2C3_ER_IRQHandler /* I2C3 error interrupt */
|
|
||||||
.word SUBGHZ_Radio_IRQHandler /* Radio IRQs RFBUSY interrupt through EXTI */
|
|
||||||
.word AES_IRQHandler /* AES global interrupt */
|
|
||||||
.word RNG_IRQHandler /* RNG interrupt */
|
|
||||||
.word PKA_IRQHandler /* PKA interrupt */
|
|
||||||
.word DMA2_Channel1_IRQHandler /* DMA2 channel 1 interrupt */
|
|
||||||
.word DMA2_Channel2_IRQHandler /* DMA2 channel 2 interrupt */
|
|
||||||
.word DMA2_Channel3_IRQHandler /* DMA2 channel 3 interrupt */
|
|
||||||
.word DMA2_Channel4_IRQHandler /* DMA2 channel 4 interrupt */
|
|
||||||
.word DMA2_Channel5_IRQHandler /* DMA2 channel 5 interrupt */
|
|
||||||
.word DMA2_Channel6_IRQHandler /* DMA2 channel 6 interrupt */
|
|
||||||
.word DMA2_Channel7_IRQHandler /* DMA2 channel 7 interrupt */
|
|
||||||
.word DMAMUX1_OVR_IRQHandler /* DMAMUX overrun interrupt */
|
|
||||||
|
|
||||||
/*******************************************************************************
|
|
||||||
*
|
|
||||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
|
||||||
* As they are weak aliases, any function with the same name will override
|
|
||||||
* this definition.
|
|
||||||
*
|
|
||||||
*******************************************************************************/
|
|
||||||
|
|
||||||
.weak NMI_Handler
|
|
||||||
.thumb_set NMI_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak HardFault_Handler
|
|
||||||
.thumb_set HardFault_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak MemManage_Handler
|
|
||||||
.thumb_set MemManage_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak BusFault_Handler
|
|
||||||
.thumb_set BusFault_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak UsageFault_Handler
|
|
||||||
.thumb_set UsageFault_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak SVC_Handler
|
|
||||||
.thumb_set SVC_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak DebugMon_Handler
|
|
||||||
.thumb_set DebugMon_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak PendSV_Handler
|
|
||||||
.thumb_set PendSV_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak SysTick_Handler
|
|
||||||
.thumb_set SysTick_Handler,Default_Handler
|
|
||||||
|
|
||||||
.weak WWDG_IRQHandler
|
|
||||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak PVD_PVM_IRQHandler
|
|
||||||
.thumb_set PVD_PVM_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TAMP_STAMP_LSECSS_SSRU_IRQHandler
|
|
||||||
.thumb_set TAMP_STAMP_LSECSS_SSRU_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak RTC_WKUP_IRQHandler
|
|
||||||
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak FLASH_IRQHandler
|
|
||||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak RCC_IRQHandler
|
|
||||||
.thumb_set RCC_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak EXTI0_IRQHandler
|
|
||||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak EXTI1_IRQHandler
|
|
||||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak EXTI2_IRQHandler
|
|
||||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak EXTI3_IRQHandler
|
|
||||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak EXTI4_IRQHandler
|
|
||||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Channel1_IRQHandler
|
|
||||||
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Channel2_IRQHandler
|
|
||||||
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Channel3_IRQHandler
|
|
||||||
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Channel4_IRQHandler
|
|
||||||
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Channel5_IRQHandler
|
|
||||||
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Channel6_IRQHandler
|
|
||||||
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Channel7_IRQHandler
|
|
||||||
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak ADC_IRQHandler
|
|
||||||
.thumb_set ADC_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DAC_IRQHandler
|
|
||||||
.thumb_set DAC_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak COMP_IRQHandler
|
|
||||||
.thumb_set COMP_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak EXTI9_5_IRQHandler
|
|
||||||
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM1_BRK_IRQHandler
|
|
||||||
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM1_UP_IRQHandler
|
|
||||||
.thumb_set TIM1_UP_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM1_TRG_COM_IRQHandler
|
|
||||||
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM1_CC_IRQHandler
|
|
||||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM2_IRQHandler
|
|
||||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM16_IRQHandler
|
|
||||||
.thumb_set TIM16_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM17_IRQHandler
|
|
||||||
.thumb_set TIM17_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak I2C1_EV_IRQHandler
|
|
||||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak I2C1_ER_IRQHandler
|
|
||||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak I2C2_EV_IRQHandler
|
|
||||||
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak I2C2_ER_IRQHandler
|
|
||||||
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak SPI1_IRQHandler
|
|
||||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak SPI2_IRQHandler
|
|
||||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak USART1_IRQHandler
|
|
||||||
.thumb_set USART1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak USART2_IRQHandler
|
|
||||||
.thumb_set USART2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak LPUART1_IRQHandler
|
|
||||||
.thumb_set LPUART1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak LPTIM1_IRQHandler
|
|
||||||
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak LPTIM2_IRQHandler
|
|
||||||
.thumb_set LPTIM2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak EXTI15_10_IRQHandler
|
|
||||||
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak RTC_Alarm_IRQHandler
|
|
||||||
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak LPTIM3_IRQHandler
|
|
||||||
.thumb_set LPTIM3_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak SUBGHZSPI_IRQHandler
|
|
||||||
.thumb_set SUBGHZSPI_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak HSEM_IRQHandler
|
|
||||||
.thumb_set HSEM_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak I2C3_EV_IRQHandler
|
|
||||||
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak I2C3_ER_IRQHandler
|
|
||||||
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak SUBGHZ_Radio_IRQHandler
|
|
||||||
.thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak AES_IRQHandler
|
|
||||||
.thumb_set AES_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak RNG_IRQHandler
|
|
||||||
.thumb_set RNG_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak PKA_IRQHandler
|
|
||||||
.thumb_set PKA_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA2_Channel1_IRQHandler
|
|
||||||
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA2_Channel2_IRQHandler
|
|
||||||
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA2_Channel3_IRQHandler
|
|
||||||
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA2_Channel4_IRQHandler
|
|
||||||
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA2_Channel5_IRQHandler
|
|
||||||
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA2_Channel6_IRQHandler
|
|
||||||
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA2_Channel7_IRQHandler
|
|
||||||
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMAMUX1_OVR_IRQHandler
|
|
||||||
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak SystemInit
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectonics *****END OF FILE****/
|
|
||||||
|
|
@ -1,40 +0,0 @@
|
||||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
|
||||||
/*-Editor annotation file-*/
|
|
||||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
|
||||||
/*-Specials-*/
|
|
||||||
define symbol __ICFEDIT_intvec_start__ = 0x08020000;
|
|
||||||
|
|
||||||
/*-Memory Regions-*/
|
|
||||||
/***** FLASH part dedicated to M0+ *****/
|
|
||||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08020000;
|
|
||||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF;
|
|
||||||
/***** Non-backup SRAM1 dedicated to M0+ *****/
|
|
||||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20004000;
|
|
||||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
|
|
||||||
/***** Backup SRAM2 dedicated to M0+ *****/
|
|
||||||
define symbol __ICFEDIT_region_RAM2_start__ = 0x2000C000;
|
|
||||||
define symbol __ICFEDIT_region_RAM2_end__ = 0x2000FFFF;
|
|
||||||
|
|
||||||
/*-Sizes-*/
|
|
||||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
|
||||||
define symbol __ICFEDIT_size_heap__ = 0x000;
|
|
||||||
/**** End of ICF editor section. ###ICF###*/
|
|
||||||
|
|
||||||
|
|
||||||
define memory mem with size = 4G;
|
|
||||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
|
||||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
|
||||||
define region RAM2_region = mem:[from __ICFEDIT_region_RAM2_start__ to __ICFEDIT_region_RAM2_end__];
|
|
||||||
|
|
||||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
|
||||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
|
||||||
|
|
||||||
initialize by copy { readwrite };
|
|
||||||
do not initialize { section .noinit };
|
|
||||||
|
|
||||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
|
||||||
|
|
||||||
place in ROM_region { readonly };
|
|
||||||
place in RAM_region { readwrite,
|
|
||||||
block CSTACK, block HEAP };
|
|
||||||
place in RAM2_region { };
|
|
||||||
|
|
@ -1,40 +0,0 @@
|
||||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
|
||||||
/*-Editor annotation file-*/
|
|
||||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
|
||||||
/*-Specials-*/
|
|
||||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
|
||||||
|
|
||||||
/*-Memory Regions-*/
|
|
||||||
/***** FLASH part dedicated to M4 *****/
|
|
||||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
|
||||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF;
|
|
||||||
/***** Non-backup SRAM1 dedicated to M4 *****/
|
|
||||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
|
||||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF;
|
|
||||||
/***** Backup SRAM2 dedicated to M4 *****/
|
|
||||||
define symbol __ICFEDIT_region_RAM2_start__ = 0x20008000;
|
|
||||||
define symbol __ICFEDIT_region_RAM2_end__ = 0x2000BFFF;
|
|
||||||
|
|
||||||
/*-Sizes-*/
|
|
||||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
|
||||||
define symbol __ICFEDIT_size_heap__ = 0x000;
|
|
||||||
/**** End of ICF editor section. ###ICF###*/
|
|
||||||
|
|
||||||
|
|
||||||
define memory mem with size = 4G;
|
|
||||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
|
||||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
|
||||||
define region RAM2_region = mem:[from __ICFEDIT_region_RAM2_start__ to __ICFEDIT_region_RAM2_end__];
|
|
||||||
|
|
||||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
|
||||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
|
||||||
|
|
||||||
initialize by copy { readwrite };
|
|
||||||
do not initialize { section .noinit };
|
|
||||||
|
|
||||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
|
||||||
|
|
||||||
place in ROM_region { readonly };
|
|
||||||
place in RAM_region { readwrite,
|
|
||||||
block CSTACK, block HEAP };
|
|
||||||
place in RAM2_region { };
|
|
||||||
|
|
@ -1,35 +0,0 @@
|
||||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
|
||||||
/*-Editor annotation file-*/
|
|
||||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
|
||||||
/*-Specials-*/
|
|
||||||
define symbol __ICFEDIT_intvec_start__ = 0x2000C000;
|
|
||||||
|
|
||||||
/*-Memory Regions-*/
|
|
||||||
/***** Non-backup SRAM1 dedicated to M0+ code *****/
|
|
||||||
define symbol __ICFEDIT_region_ROM_start__ = 0x2000C000;
|
|
||||||
define symbol __ICFEDIT_region_ROM_end__ = 0x2000FFFF;
|
|
||||||
/***** Backup SRAM2 dedicated to M0+ data *****/
|
|
||||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20004000;
|
|
||||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
|
|
||||||
|
|
||||||
/*-Sizes-*/
|
|
||||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
|
||||||
define symbol __ICFEDIT_size_heap__ = 0x000;
|
|
||||||
/**** End of ICF editor section. ###ICF###*/
|
|
||||||
|
|
||||||
|
|
||||||
define memory mem with size = 4G;
|
|
||||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
|
||||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
|
||||||
|
|
||||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
|
||||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
|
||||||
|
|
||||||
initialize by copy { readwrite };
|
|
||||||
do not initialize { section .noinit };
|
|
||||||
|
|
||||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
|
||||||
|
|
||||||
place in ROM_region { readonly };
|
|
||||||
place in RAM_region { readwrite,
|
|
||||||
block CSTACK, block HEAP };
|
|
||||||
|
|
@ -1,34 +0,0 @@
|
||||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
|
||||||
/*-Editor annotation file-*/
|
|
||||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
|
||||||
/*-Specials-*/
|
|
||||||
define symbol __ICFEDIT_intvec_start__ = 0x20008000;
|
|
||||||
/*-Memory Regions-*/
|
|
||||||
/***** Non-backup SRAM1 dedicated to M4 code *****/
|
|
||||||
define symbol __ICFEDIT_region_ROM_start__ = 0x20008000;
|
|
||||||
define symbol __ICFEDIT_region_ROM_end__ = 0x2000BFFF;
|
|
||||||
/***** Backup SRAM2 dedicated to M4 data *****/
|
|
||||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
|
||||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF;
|
|
||||||
|
|
||||||
/*-Sizes-*/
|
|
||||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
|
||||||
define symbol __ICFEDIT_size_heap__ = 0x000;
|
|
||||||
/**** End of ICF editor section. ###ICF###*/
|
|
||||||
|
|
||||||
|
|
||||||
define memory mem with size = 4G;
|
|
||||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
|
||||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
|
||||||
|
|
||||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
|
||||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
|
||||||
|
|
||||||
initialize by copy { readwrite };
|
|
||||||
do not initialize { section .noinit };
|
|
||||||
|
|
||||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
|
||||||
|
|
||||||
place in ROM_region { readonly };
|
|
||||||
place in RAM_region { readwrite,
|
|
||||||
block CSTACK, block HEAP };
|
|
||||||
|
|
@ -1,40 +0,0 @@
|
||||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
|
||||||
/*-Editor annotation file-*/
|
|
||||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
|
||||||
/*-Specials-*/
|
|
||||||
define symbol __ICFEDIT_intvec_start__ = 0x08020000;
|
|
||||||
|
|
||||||
/*-Memory Regions-*/
|
|
||||||
/***** FLASH part dedicated to M0+ *****/
|
|
||||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08020000;
|
|
||||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF;
|
|
||||||
/***** SRAM1 dedicated to M0+ *****/
|
|
||||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20004000;
|
|
||||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
|
|
||||||
/***** SRAM2 dedicated to M0+ *****/
|
|
||||||
define symbol __ICFEDIT_region_RAM2_start__ = 0x2000C000;
|
|
||||||
define symbol __ICFEDIT_region_RAM2_end__ = 0x2000FFFF;
|
|
||||||
|
|
||||||
/*-Sizes-*/
|
|
||||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
|
||||||
define symbol __ICFEDIT_size_heap__ = 0x000;
|
|
||||||
/**** End of ICF editor section. ###ICF###*/
|
|
||||||
|
|
||||||
|
|
||||||
define memory mem with size = 4G;
|
|
||||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
|
||||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
|
||||||
define region RAM2_region = mem:[from __ICFEDIT_region_RAM2_start__ to __ICFEDIT_region_RAM2_end__];
|
|
||||||
|
|
||||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
|
||||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
|
||||||
|
|
||||||
initialize by copy { readwrite };
|
|
||||||
do not initialize { section .noinit };
|
|
||||||
|
|
||||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
|
||||||
|
|
||||||
place in ROM_region { readonly };
|
|
||||||
place in RAM_region { readwrite,
|
|
||||||
block CSTACK, block HEAP };
|
|
||||||
place in RAM2_region { };
|
|
||||||
|
|
@ -1,40 +0,0 @@
|
||||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
|
||||||
/*-Editor annotation file-*/
|
|
||||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
|
||||||
/*-Specials-*/
|
|
||||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
|
||||||
|
|
||||||
/*-Memory Regions-*/
|
|
||||||
/***** FLASH part dedicated to M4 *****/
|
|
||||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
|
||||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF;
|
|
||||||
/***** Non-backup SRAM1 dedicated to M4 *****/
|
|
||||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
|
||||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF;
|
|
||||||
/***** Backup SRAM2 dedicated to M4 *****/
|
|
||||||
define symbol __ICFEDIT_region_RAM2_start__ = 0x20008000;
|
|
||||||
define symbol __ICFEDIT_region_RAM2_end__ = 0x2000BFFF;
|
|
||||||
|
|
||||||
/*-Sizes-*/
|
|
||||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
|
||||||
define symbol __ICFEDIT_size_heap__ = 0x000;
|
|
||||||
/**** End of ICF editor section. ###ICF###*/
|
|
||||||
|
|
||||||
|
|
||||||
define memory mem with size = 4G;
|
|
||||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
|
||||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
|
||||||
define region RAM2_region = mem:[from __ICFEDIT_region_RAM2_start__ to __ICFEDIT_region_RAM2_end__];
|
|
||||||
|
|
||||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
|
||||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
|
||||||
|
|
||||||
initialize by copy { readwrite };
|
|
||||||
do not initialize { section .noinit };
|
|
||||||
|
|
||||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
|
||||||
|
|
||||||
place in ROM_region { readonly };
|
|
||||||
place in RAM_region { readwrite,
|
|
||||||
block CSTACK, block HEAP };
|
|
||||||
place in RAM2_region { };
|
|
||||||
|
|
@ -1,35 +0,0 @@
|
||||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
|
||||||
/*-Editor annotation file-*/
|
|
||||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
|
||||||
/*-Specials-*/
|
|
||||||
define symbol __ICFEDIT_intvec_start__ = 0x2000C000;
|
|
||||||
|
|
||||||
/*-Memory Regions-*/
|
|
||||||
/***** Non-backup SRAM1 dedicated to M0+ code *****/
|
|
||||||
define symbol __ICFEDIT_region_ROM_start__ = 0x2000C000;
|
|
||||||
define symbol __ICFEDIT_region_ROM_end__ = 0x2000FFFF;
|
|
||||||
/***** Backup SRAM2 dedicated to M0+ data *****/
|
|
||||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20004000;
|
|
||||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
|
|
||||||
|
|
||||||
/*-Sizes-*/
|
|
||||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
|
||||||
define symbol __ICFEDIT_size_heap__ = 0x000;
|
|
||||||
/**** End of ICF editor section. ###ICF###*/
|
|
||||||
|
|
||||||
|
|
||||||
define memory mem with size = 4G;
|
|
||||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
|
||||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
|
||||||
|
|
||||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
|
||||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
|
||||||
|
|
||||||
initialize by copy { readwrite };
|
|
||||||
do not initialize { section .noinit };
|
|
||||||
|
|
||||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
|
||||||
|
|
||||||
place in ROM_region { readonly };
|
|
||||||
place in RAM_region { readwrite,
|
|
||||||
block CSTACK, block HEAP };
|
|
||||||
|
|
@ -1,35 +0,0 @@
|
||||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
|
||||||
/*-Editor annotation file-*/
|
|
||||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
|
||||||
/*-Specials-*/
|
|
||||||
define symbol __ICFEDIT_intvec_start__ = 0x20008000;
|
|
||||||
|
|
||||||
/*-Memory Regions-*/
|
|
||||||
/***** Non-backup SRAM1 dedicated to M4 code *****/
|
|
||||||
define symbol __ICFEDIT_region_ROM_start__ = 0x20008000;
|
|
||||||
define symbol __ICFEDIT_region_ROM_end__ = 0x2000BFFF;
|
|
||||||
/***** Backup SRAM2 dedicated to M4 data *****/
|
|
||||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
|
||||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF;
|
|
||||||
|
|
||||||
/*-Sizes-*/
|
|
||||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
|
||||||
define symbol __ICFEDIT_size_heap__ = 0x000;
|
|
||||||
/**** End of ICF editor section. ###ICF###*/
|
|
||||||
|
|
||||||
|
|
||||||
define memory mem with size = 4G;
|
|
||||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
|
||||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
|
||||||
|
|
||||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
|
||||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
|
||||||
|
|
||||||
initialize by copy { readwrite };
|
|
||||||
do not initialize { section .noinit };
|
|
||||||
|
|
||||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
|
||||||
|
|
||||||
place in ROM_region { readonly };
|
|
||||||
place in RAM_region { readwrite,
|
|
||||||
block CSTACK, block HEAP };
|
|
||||||
|
|
@ -1,40 +0,0 @@
|
||||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
|
||||||
/*-Editor annotation file-*/
|
|
||||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
|
||||||
/*-Specials-*/
|
|
||||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
|
||||||
|
|
||||||
/*-Memory Regions-*/
|
|
||||||
/***** FLASH *****/
|
|
||||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
|
||||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF;
|
|
||||||
/***** Non-backup SRAM1 *****/
|
|
||||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
|
||||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
|
|
||||||
/***** Backup SRAM2 *****/
|
|
||||||
define symbol __ICFEDIT_region_RAM2_start__ = 0x20008000;
|
|
||||||
define symbol __ICFEDIT_region_RAM2_end__ = 0x2000FFFF;
|
|
||||||
|
|
||||||
/*-Sizes-*/
|
|
||||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
|
||||||
define symbol __ICFEDIT_size_heap__ = 0x000;
|
|
||||||
/**** End of ICF editor section. ###ICF###*/
|
|
||||||
|
|
||||||
|
|
||||||
define memory mem with size = 4G;
|
|
||||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
|
||||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
|
||||||
define region RAM2_region = mem:[from __ICFEDIT_region_RAM2_start__ to __ICFEDIT_region_RAM2_end__];
|
|
||||||
|
|
||||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
|
||||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
|
||||||
|
|
||||||
initialize by copy { readwrite };
|
|
||||||
do not initialize { section .noinit };
|
|
||||||
|
|
||||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
|
||||||
|
|
||||||
place in ROM_region { readonly };
|
|
||||||
place in RAM_region { readwrite,
|
|
||||||
block CSTACK, block HEAP };
|
|
||||||
place in RAM2_region { };
|
|
||||||
|
|
@ -1,35 +0,0 @@
|
||||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
|
||||||
/*-Editor annotation file-*/
|
|
||||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
|
||||||
/*-Specials-*/
|
|
||||||
define symbol __ICFEDIT_intvec_start__ = 0x20000000;
|
|
||||||
|
|
||||||
/*-Memory Regions-*/
|
|
||||||
/***** Non-backup SRAM1 dedicated to code *****/
|
|
||||||
define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
|
|
||||||
define symbol __ICFEDIT_region_ROM_end__ = 0x20007FFF;
|
|
||||||
/***** Backup SRAM2 dedicated to data *****/
|
|
||||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20008000;
|
|
||||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF;
|
|
||||||
|
|
||||||
/*-Sizes-*/
|
|
||||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
|
||||||
define symbol __ICFEDIT_size_heap__ = 0x000;
|
|
||||||
/**** End of ICF editor section. ###ICF###*/
|
|
||||||
|
|
||||||
|
|
||||||
define memory mem with size = 4G;
|
|
||||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
|
||||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
|
||||||
|
|
||||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
|
||||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
|
||||||
|
|
||||||
initialize by copy { readwrite };
|
|
||||||
do not initialize { section .noinit };
|
|
||||||
|
|
||||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
|
||||||
|
|
||||||
place in ROM_region { readonly };
|
|
||||||
place in RAM_region { readwrite,
|
|
||||||
block CSTACK, block HEAP };
|
|
||||||
|
|
@ -1,40 +0,0 @@
|
||||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
|
||||||
/*-Editor annotation file-*/
|
|
||||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
|
||||||
/*-Specials-*/
|
|
||||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
|
||||||
|
|
||||||
/*-Memory Regions-*/
|
|
||||||
/***** FLASH *****/
|
|
||||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
|
||||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF;
|
|
||||||
/***** Non-backup SRAM1 *****/
|
|
||||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
|
||||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
|
|
||||||
/***** Backup SRAM2 *****/
|
|
||||||
define symbol __ICFEDIT_region_RAM2_start__ = 0x20008000;
|
|
||||||
define symbol __ICFEDIT_region_RAM2_end__ = 0x2000FFFF;
|
|
||||||
|
|
||||||
/*-Sizes-*/
|
|
||||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
|
||||||
define symbol __ICFEDIT_size_heap__ = 0x000;
|
|
||||||
/**** End of ICF editor section. ###ICF###*/
|
|
||||||
|
|
||||||
|
|
||||||
define memory mem with size = 4G;
|
|
||||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
|
||||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
|
||||||
define region RAM2_region = mem:[from __ICFEDIT_region_RAM2_start__ to __ICFEDIT_region_RAM2_end__];
|
|
||||||
|
|
||||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
|
||||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
|
||||||
|
|
||||||
initialize by copy { readwrite };
|
|
||||||
do not initialize { section .noinit };
|
|
||||||
|
|
||||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
|
||||||
|
|
||||||
place in ROM_region { readonly };
|
|
||||||
place in RAM_region { readwrite,
|
|
||||||
block CSTACK, block HEAP };
|
|
||||||
place in RAM2_region { };
|
|
||||||
|
|
@ -1,35 +0,0 @@
|
||||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
|
||||||
/*-Editor annotation file-*/
|
|
||||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
|
||||||
/*-Specials-*/
|
|
||||||
define symbol __ICFEDIT_intvec_start__ = 0x20000000;
|
|
||||||
|
|
||||||
/*-Memory Regions-*/
|
|
||||||
/***** Non-backup SRAM1 dedicated to code *****/
|
|
||||||
define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
|
|
||||||
define symbol __ICFEDIT_region_ROM_end__ = 0x20007FFF;
|
|
||||||
/***** Backup SRAM2 dedicated to data *****/
|
|
||||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20008000;
|
|
||||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF;
|
|
||||||
|
|
||||||
/*-Sizes-*/
|
|
||||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
|
||||||
define symbol __ICFEDIT_size_heap__ = 0x000;
|
|
||||||
/**** End of ICF editor section. ###ICF###*/
|
|
||||||
|
|
||||||
|
|
||||||
define memory mem with size = 4G;
|
|
||||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
|
||||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
|
||||||
|
|
||||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
|
||||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
|
||||||
|
|
||||||
initialize by copy { readwrite };
|
|
||||||
do not initialize { section .noinit };
|
|
||||||
|
|
||||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
|
||||||
|
|
||||||
place in ROM_region { readonly };
|
|
||||||
place in RAM_region { readwrite,
|
|
||||||
block CSTACK, block HEAP };
|
|
||||||
|
|
@ -1,316 +0,0 @@
|
||||||
;********************************************************************************
|
|
||||||
;* File Name : startup_stm32wl54xx_cm0plus.s
|
|
||||||
;* Author : MCD Application Team
|
|
||||||
;* Description : MO+ core vector table of the STM32WLxxxx devices for the
|
|
||||||
;* IAR (EWARM) toolchain.
|
|
||||||
;*
|
|
||||||
;* This module performs:
|
|
||||||
;* - Set the initial SP
|
|
||||||
;* - Set the initial PC == _iar_program_start,
|
|
||||||
;* - Set the vector table entries with the exceptions ISR
|
|
||||||
;* address.
|
|
||||||
;* - Branches to main in the C library (which eventually
|
|
||||||
;* calls main()).
|
|
||||||
;* After Reset the Cortex-M0+ processor is in Thread mode,
|
|
||||||
;* priority is Privileged, and the Stack is set to Main.
|
|
||||||
;********************************************************************************
|
|
||||||
;*
|
|
||||||
;* Copyright (c) 2020(2021) STMicroelectronics.
|
|
||||||
;* All rights reserved.
|
|
||||||
;*
|
|
||||||
;* This software is licensed under terms that can be found in the LICENSE file
|
|
||||||
;* in the root directory of this software component.
|
|
||||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
|
||||||
;
|
|
||||||
;*******************************************************************************
|
|
||||||
;
|
|
||||||
;
|
|
||||||
; The modules in this file are included in the libraries, and may be replaced
|
|
||||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
|
||||||
; a user defined start symbol.
|
|
||||||
; To override the cstartup defined in the library, simply add your modified
|
|
||||||
; version to the workbench project.
|
|
||||||
;
|
|
||||||
; The vector table is normally located at address 0.
|
|
||||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
|
||||||
; The name "__vector_table" has special meaning for C-SPY:
|
|
||||||
; it is where the SP start value is found, and the NVIC vector
|
|
||||||
; table register (VTOR) is initialized to this address if != 0.
|
|
||||||
;
|
|
||||||
; Cortex-M version
|
|
||||||
;
|
|
||||||
|
|
||||||
MODULE ?cstartup
|
|
||||||
|
|
||||||
;; Forward declaration of sections.
|
|
||||||
SECTION CSTACK:DATA:NOROOT(3)
|
|
||||||
|
|
||||||
SECTION .intvec:CODE:NOROOT(2)
|
|
||||||
|
|
||||||
EXTERN __iar_program_start
|
|
||||||
EXTERN SystemInit
|
|
||||||
PUBLIC __vector_table
|
|
||||||
|
|
||||||
DATA
|
|
||||||
__vector_table
|
|
||||||
DCD sfe(CSTACK)
|
|
||||||
DCD Reset_Handler ; Reset Handler
|
|
||||||
|
|
||||||
DCD NMI_Handler ; NMI Handler
|
|
||||||
DCD HardFault_Handler ; Hard Fault Handler
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD SVC_Handler ; SVCall Handler
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD PendSV_Handler ; PendSV Handler
|
|
||||||
DCD SysTick_Handler ; SysTick Handler
|
|
||||||
|
|
||||||
; External Interrupts
|
|
||||||
DCD TZIC_ILA_IRQHandler ; TZIC ILA Interrupt
|
|
||||||
DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
|
|
||||||
DCD RTC_LSECSS_IRQHandler ; RTC Wakeup, Tamper, TimeStamp, RTC Alarms (A & B) and RTC SSRU Interrupts and LSECSS Interrupts
|
|
||||||
DCD RCC_FLASH_C1SEV_IRQHandler ; RCC and FLASH and CPU1 M4 SEV Interrupt
|
|
||||||
DCD EXTI1_0_IRQHandler ; EXTI Line 1:0 Interrupt
|
|
||||||
DCD EXTI3_2_IRQHandler ; EXTI Line 3:2 Interrupt
|
|
||||||
DCD EXTI15_4_IRQHandler ; EXTI Line 15:4 interrupt
|
|
||||||
DCD ADC_COMP_DAC_IRQHandler ; ADC, COMP1, COMP2, DAC Interrupt
|
|
||||||
DCD DMA1_Channel1_2_3_IRQHandler ; DMA1 Channel 1 to 3 Interrupt
|
|
||||||
DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channels 4,5,6,7 Interrupt
|
|
||||||
DCD DMA2_DMAMUX1_OVR_IRQHandler ; DMA2 Channels[1..7] and DMAMUX Overrun Interrupts
|
|
||||||
|
|
||||||
DCD LPTIM1_IRQHandler ; LPTIM1 Global Interrupt
|
|
||||||
DCD LPTIM2_IRQHandler ; LPTIM2 Global Interrupt
|
|
||||||
DCD LPTIM3_IRQHandler ; LPTIM3 Global Interrupt
|
|
||||||
|
|
||||||
DCD TIM1_IRQHandler ; TIM1 Global Interrupt
|
|
||||||
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
|
|
||||||
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
|
|
||||||
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
|
|
||||||
DCD IPCC_C2_RX_C2_TX_IRQHandler ; IPCC RX Occupied and TX Free Interrupt Interrupt
|
|
||||||
DCD HSEM_IRQHandler ; Semaphore Interrupt
|
|
||||||
DCD RNG_IRQHandler ; RNG Interrupt
|
|
||||||
DCD AES_PKA_IRQHandler ; AES and PKA Interrupt
|
|
||||||
DCD I2C1_IRQHandler ; I2C1 Event and Error Interrupt
|
|
||||||
DCD I2C2_IRQHandler ; I2C2 Event and Error Interrupt
|
|
||||||
DCD I2C3_IRQHandler ; I2C3 Event and Error Interrupt
|
|
||||||
DCD SPI1_IRQHandler ; SPI1 Interrupt
|
|
||||||
DCD SPI2_IRQHandler ; SPI2 Interrupt
|
|
||||||
DCD USART1_IRQHandler ; USART1 Interrupt
|
|
||||||
DCD USART2_IRQHandler ; USART2 Interrupt
|
|
||||||
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
|
|
||||||
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
|
|
||||||
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
|
|
||||||
|
|
||||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
||||||
;;
|
|
||||||
;; Default interrupt handlers.
|
|
||||||
;;
|
|
||||||
THUMB
|
|
||||||
|
|
||||||
PUBWEAK Reset_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
|
||||||
Reset_Handler
|
|
||||||
LDR R0, =SystemInit
|
|
||||||
BLX R0
|
|
||||||
LDR R0, =__iar_program_start
|
|
||||||
BX R0
|
|
||||||
|
|
||||||
PUBWEAK NMI_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
NMI_Handler
|
|
||||||
B NMI_Handler
|
|
||||||
|
|
||||||
PUBWEAK HardFault_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
HardFault_Handler
|
|
||||||
B HardFault_Handler
|
|
||||||
|
|
||||||
PUBWEAK SVC_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
SVC_Handler
|
|
||||||
B SVC_Handler
|
|
||||||
|
|
||||||
PUBWEAK PendSV_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
PendSV_Handler
|
|
||||||
B PendSV_Handler
|
|
||||||
|
|
||||||
PUBWEAK SysTick_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
SysTick_Handler
|
|
||||||
B SysTick_Handler
|
|
||||||
|
|
||||||
PUBWEAK TZIC_ILA_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
TZIC_ILA_IRQHandler
|
|
||||||
B TZIC_ILA_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK PVD_PVM_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
PVD_PVM_IRQHandler
|
|
||||||
B PVD_PVM_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK RTC_LSECSS_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
RTC_LSECSS_IRQHandler
|
|
||||||
B RTC_LSECSS_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK RCC_FLASH_C1SEV_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
RCC_FLASH_C1SEV_IRQHandler
|
|
||||||
B RCC_FLASH_C1SEV_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK EXTI1_0_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
EXTI1_0_IRQHandler
|
|
||||||
B EXTI1_0_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK EXTI3_2_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
EXTI3_2_IRQHandler
|
|
||||||
B EXTI3_2_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK EXTI15_4_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
EXTI15_4_IRQHandler
|
|
||||||
B EXTI15_4_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK ADC_COMP_DAC_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
ADC_COMP_DAC_IRQHandler
|
|
||||||
B ADC_COMP_DAC_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA1_Channel1_2_3_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA1_Channel1_2_3_IRQHandler
|
|
||||||
B DMA1_Channel1_2_3_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA1_Channel4_5_6_7_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA1_Channel4_5_6_7_IRQHandler
|
|
||||||
B DMA1_Channel4_5_6_7_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA2_DMAMUX1_OVR_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA2_DMAMUX1_OVR_IRQHandler
|
|
||||||
B DMA2_DMAMUX1_OVR_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK LPTIM1_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
LPTIM1_IRQHandler
|
|
||||||
B LPTIM1_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK LPTIM2_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
LPTIM2_IRQHandler
|
|
||||||
B LPTIM2_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK LPTIM3_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
LPTIM3_IRQHandler
|
|
||||||
B LPTIM3_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK TIM1_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
TIM1_IRQHandler
|
|
||||||
B TIM1_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK TIM2_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
TIM2_IRQHandler
|
|
||||||
B TIM2_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK TIM16_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
TIM16_IRQHandler
|
|
||||||
B TIM16_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK TIM17_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
TIM17_IRQHandler
|
|
||||||
B TIM17_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK IPCC_C2_RX_C2_TX_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
IPCC_C2_RX_C2_TX_IRQHandler
|
|
||||||
B IPCC_C2_RX_C2_TX_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK HSEM_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
HSEM_IRQHandler
|
|
||||||
B HSEM_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK RNG_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
RNG_IRQHandler
|
|
||||||
B RNG_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK AES_PKA_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
AES_PKA_IRQHandler
|
|
||||||
B AES_PKA_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK LCD_802_1_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
LCD_802_1_IRQHandler
|
|
||||||
B LCD_802_1_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK I2C1_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
I2C1_IRQHandler
|
|
||||||
B I2C1_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK I2C2_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
I2C2_IRQHandler
|
|
||||||
B I2C2_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK I2C3_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
I2C3_IRQHandler
|
|
||||||
B I2C3_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK SPI1_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
SPI1_IRQHandler
|
|
||||||
B SPI1_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK SPI2_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
SPI2_IRQHandler
|
|
||||||
B SPI2_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK USART1_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
USART1_IRQHandler
|
|
||||||
B USART1_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK USART2_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
USART2_IRQHandler
|
|
||||||
B USART2_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK LPUART1_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
LPUART1_IRQHandler
|
|
||||||
B LPUART1_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK SUBGHZSPI_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
SUBGHZSPI_IRQHandler
|
|
||||||
B SUBGHZSPI_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK SUBGHZ_Radio_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
SUBGHZ_Radio_IRQHandler
|
|
||||||
B SUBGHZ_Radio_IRQHandler
|
|
||||||
|
|
||||||
END
|
|
||||||
|
|
||||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
|
||||||
|
|
@ -1,509 +0,0 @@
|
||||||
;********************************************************************************
|
|
||||||
;* File Name : startup_stm32wl54xx_cm4.s
|
|
||||||
;* Author : MCD Application Team
|
|
||||||
;* Description : M4 core vector table of the STM32WLxxxx devices for the
|
|
||||||
;* IAR (EWARM) toolchain.
|
|
||||||
;*
|
|
||||||
;* This module performs:
|
|
||||||
;* - Set the initial SP
|
|
||||||
;* - Set the initial PC == _iar_program_start,
|
|
||||||
;* - Set the vector table entries with the exceptions ISR
|
|
||||||
;* address.
|
|
||||||
;* - Branches to main in the C library (which eventually
|
|
||||||
;* calls main()).
|
|
||||||
;* After Reset the Cortex-M4 processor is in Thread mode,
|
|
||||||
;* priority is Privileged, and the Stack is set to Main.
|
|
||||||
;********************************************************************************
|
|
||||||
;*
|
|
||||||
;* Copyright (c) 2020(2021) STMicroelectronics.
|
|
||||||
;* All rights reserved.
|
|
||||||
;*
|
|
||||||
;* This software is licensed under terms that can be found in the LICENSE file
|
|
||||||
;* in the root directory of this software component.
|
|
||||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
|
||||||
;
|
|
||||||
;*******************************************************************************
|
|
||||||
;
|
|
||||||
;
|
|
||||||
; The modules in this file are included in the libraries, and may be replaced
|
|
||||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
|
||||||
; a user defined start symbol.
|
|
||||||
; To override the cstartup defined in the library, simply add your modified
|
|
||||||
; version to the workbench project.
|
|
||||||
;
|
|
||||||
; The vector table is normally located at address 0.
|
|
||||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
|
||||||
; The name "__vector_table" has special meaning for C-SPY:
|
|
||||||
; it is where the SP start value is found, and the NVIC vector
|
|
||||||
; table register (VTOR) is initialized to this address if != 0.
|
|
||||||
;
|
|
||||||
; Cortex-M version
|
|
||||||
;
|
|
||||||
|
|
||||||
MODULE ?cstartup
|
|
||||||
|
|
||||||
;; Forward declaration of sections.
|
|
||||||
SECTION CSTACK:DATA:NOROOT(3)
|
|
||||||
|
|
||||||
SECTION .intvec:CODE:NOROOT(2)
|
|
||||||
|
|
||||||
EXTERN __iar_program_start
|
|
||||||
EXTERN SystemInit
|
|
||||||
PUBLIC __vector_table
|
|
||||||
|
|
||||||
DATA
|
|
||||||
__vector_table
|
|
||||||
DCD sfe(CSTACK)
|
|
||||||
DCD Reset_Handler ; Reset Handler
|
|
||||||
|
|
||||||
DCD NMI_Handler ; NMI Handler
|
|
||||||
DCD HardFault_Handler ; Hard Fault Handler
|
|
||||||
DCD MemManage_Handler ; MPU Fault Handler
|
|
||||||
DCD BusFault_Handler ; Bus Fault Handler
|
|
||||||
DCD UsageFault_Handler ; Usage Fault Handler
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD SVC_Handler ; SVCall Handler
|
|
||||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD PendSV_Handler ; PendSV Handler
|
|
||||||
DCD SysTick_Handler ; SysTick Handler
|
|
||||||
|
|
||||||
; External Interrupts
|
|
||||||
DCD WWDG_IRQHandler ; Window WatchDog
|
|
||||||
DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
|
|
||||||
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts
|
|
||||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
|
|
||||||
DCD FLASH_IRQHandler ; FLASH global Interrupt
|
|
||||||
DCD RCC_IRQHandler ; RCC Interrupt
|
|
||||||
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
|
|
||||||
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
|
|
||||||
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
|
|
||||||
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
|
|
||||||
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
|
|
||||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
|
|
||||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
|
|
||||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
|
|
||||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
|
|
||||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
|
|
||||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
|
|
||||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
|
|
||||||
DCD ADC_IRQHandler ; ADC Interrupt
|
|
||||||
DCD DAC_IRQHandler ; DAC Interrupt
|
|
||||||
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt
|
|
||||||
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
|
|
||||||
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
|
|
||||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
|
|
||||||
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
|
|
||||||
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
|
|
||||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
|
|
||||||
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
|
|
||||||
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
|
|
||||||
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
|
|
||||||
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
|
|
||||||
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
|
|
||||||
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
|
|
||||||
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
|
|
||||||
DCD SPI1_IRQHandler ; SPI1 Interrupt
|
|
||||||
DCD SPI2_IRQHandler ; SPI2 Interrupt
|
|
||||||
DCD USART1_IRQHandler ; USART1 Interrupt
|
|
||||||
DCD USART2_IRQHandler ; USART2 Interrupt
|
|
||||||
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
|
|
||||||
DCD LPTIM1_IRQHandler ; LPTIM1 Global Interrupt
|
|
||||||
DCD LPTIM2_IRQHandler ; LPTIM2 Global Interrupt
|
|
||||||
DCD EXTI15_10_IRQHandler ; EXTI Lines [15:10] Interrupt
|
|
||||||
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
|
|
||||||
DCD LPTIM3_IRQHandler ; LPTIM3 Global Interrupt
|
|
||||||
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
|
|
||||||
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
|
|
||||||
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
|
|
||||||
DCD HSEM_IRQHandler ; HSEM0 Interrupt
|
|
||||||
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
|
|
||||||
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
|
|
||||||
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
|
|
||||||
DCD AES_IRQHandler ; AES Interrupt
|
|
||||||
DCD RNG_IRQHandler ; RNG1 Interrupt
|
|
||||||
DCD PKA_IRQHandler ; PKA Interrupt
|
|
||||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
|
|
||||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
|
|
||||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
|
|
||||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
|
|
||||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
|
|
||||||
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
|
|
||||||
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
|
|
||||||
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
|
|
||||||
|
|
||||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
||||||
;;
|
|
||||||
;; Default interrupt handlers.
|
|
||||||
;;
|
|
||||||
THUMB
|
|
||||||
|
|
||||||
PUBWEAK Reset_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
|
||||||
Reset_Handler
|
|
||||||
LDR R0, =SystemInit
|
|
||||||
BLX R0
|
|
||||||
LDR R0, =__iar_program_start
|
|
||||||
BX R0
|
|
||||||
|
|
||||||
PUBWEAK NMI_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
NMI_Handler
|
|
||||||
B NMI_Handler
|
|
||||||
|
|
||||||
PUBWEAK HardFault_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
HardFault_Handler
|
|
||||||
B HardFault_Handler
|
|
||||||
|
|
||||||
PUBWEAK MemManage_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
MemManage_Handler
|
|
||||||
B MemManage_Handler
|
|
||||||
|
|
||||||
PUBWEAK BusFault_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
BusFault_Handler
|
|
||||||
B BusFault_Handler
|
|
||||||
|
|
||||||
PUBWEAK UsageFault_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
UsageFault_Handler
|
|
||||||
B UsageFault_Handler
|
|
||||||
|
|
||||||
PUBWEAK SVC_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
SVC_Handler
|
|
||||||
B SVC_Handler
|
|
||||||
|
|
||||||
PUBWEAK DebugMon_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DebugMon_Handler
|
|
||||||
B DebugMon_Handler
|
|
||||||
|
|
||||||
PUBWEAK PendSV_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
PendSV_Handler
|
|
||||||
B PendSV_Handler
|
|
||||||
|
|
||||||
PUBWEAK SysTick_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
SysTick_Handler
|
|
||||||
B SysTick_Handler
|
|
||||||
|
|
||||||
PUBWEAK WWDG_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
WWDG_IRQHandler
|
|
||||||
B WWDG_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK PVD_PVM_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
PVD_PVM_IRQHandler
|
|
||||||
B PVD_PVM_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK TAMP_STAMP_LSECSS_SSRU_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
TAMP_STAMP_LSECSS_SSRU_IRQHandler
|
|
||||||
B TAMP_STAMP_LSECSS_SSRU_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK RTC_WKUP_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
RTC_WKUP_IRQHandler
|
|
||||||
B RTC_WKUP_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK FLASH_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
FLASH_IRQHandler
|
|
||||||
B FLASH_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK RCC_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
RCC_IRQHandler
|
|
||||||
B RCC_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK EXTI0_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
EXTI0_IRQHandler
|
|
||||||
B EXTI0_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK EXTI1_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
EXTI1_IRQHandler
|
|
||||||
B EXTI1_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK EXTI2_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
EXTI2_IRQHandler
|
|
||||||
B EXTI2_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK EXTI3_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
EXTI3_IRQHandler
|
|
||||||
B EXTI3_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK EXTI4_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
EXTI4_IRQHandler
|
|
||||||
B EXTI4_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA1_Channel1_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA1_Channel1_IRQHandler
|
|
||||||
B DMA1_Channel1_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA1_Channel2_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA1_Channel2_IRQHandler
|
|
||||||
B DMA1_Channel2_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA1_Channel3_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA1_Channel3_IRQHandler
|
|
||||||
B DMA1_Channel3_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA1_Channel4_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA1_Channel4_IRQHandler
|
|
||||||
B DMA1_Channel4_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA1_Channel5_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA1_Channel5_IRQHandler
|
|
||||||
B DMA1_Channel5_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA1_Channel6_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA1_Channel6_IRQHandler
|
|
||||||
B DMA1_Channel6_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA1_Channel7_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA1_Channel7_IRQHandler
|
|
||||||
B DMA1_Channel7_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK ADC_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
ADC_IRQHandler
|
|
||||||
B ADC_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DAC_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DAC_IRQHandler
|
|
||||||
B DAC_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK C2SEV_PWR_C2H_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
C2SEV_PWR_C2H_IRQHandler
|
|
||||||
B C2SEV_PWR_C2H_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK COMP_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
COMP_IRQHandler
|
|
||||||
B COMP_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK EXTI9_5_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
EXTI9_5_IRQHandler
|
|
||||||
B EXTI9_5_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK TIM1_BRK_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
TIM1_BRK_IRQHandler
|
|
||||||
B TIM1_BRK_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK TIM1_UP_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
TIM1_UP_IRQHandler
|
|
||||||
B TIM1_UP_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK TIM1_TRG_COM_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
TIM1_TRG_COM_IRQHandler
|
|
||||||
B TIM1_TRG_COM_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK TIM1_CC_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
TIM1_CC_IRQHandler
|
|
||||||
B TIM1_CC_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK TIM2_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
TIM2_IRQHandler
|
|
||||||
B TIM2_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK TIM16_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
TIM16_IRQHandler
|
|
||||||
B TIM16_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK TIM17_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
TIM17_IRQHandler
|
|
||||||
B TIM17_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK I2C1_EV_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
I2C1_EV_IRQHandler
|
|
||||||
B I2C1_EV_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK I2C1_ER_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
I2C1_ER_IRQHandler
|
|
||||||
B I2C1_ER_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK I2C2_EV_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
I2C2_EV_IRQHandler
|
|
||||||
B I2C2_EV_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK I2C2_ER_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
I2C2_ER_IRQHandler
|
|
||||||
B I2C2_ER_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK SPI1_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
SPI1_IRQHandler
|
|
||||||
B SPI1_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK SPI2_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
SPI2_IRQHandler
|
|
||||||
B SPI2_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK USART1_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
USART1_IRQHandler
|
|
||||||
B USART1_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK USART2_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
USART2_IRQHandler
|
|
||||||
B USART2_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK LPUART1_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
LPUART1_IRQHandler
|
|
||||||
B LPUART1_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK LPTIM1_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
LPTIM1_IRQHandler
|
|
||||||
B LPTIM1_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK LPTIM2_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
LPTIM2_IRQHandler
|
|
||||||
B LPTIM2_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK EXTI15_10_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
EXTI15_10_IRQHandler
|
|
||||||
B EXTI15_10_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK RTC_Alarm_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
RTC_Alarm_IRQHandler
|
|
||||||
B RTC_Alarm_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK LPTIM3_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
LPTIM3_IRQHandler
|
|
||||||
B LPTIM3_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK SUBGHZSPI_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
SUBGHZSPI_IRQHandler
|
|
||||||
B SUBGHZSPI_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK IPCC_C1_RX_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
IPCC_C1_RX_IRQHandler
|
|
||||||
B IPCC_C1_RX_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK IPCC_C1_TX_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
IPCC_C1_TX_IRQHandler
|
|
||||||
B IPCC_C1_TX_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK HSEM_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
HSEM_IRQHandler
|
|
||||||
B HSEM_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK I2C3_EV_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
I2C3_EV_IRQHandler
|
|
||||||
B I2C3_EV_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK I2C3_ER_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
I2C3_ER_IRQHandler
|
|
||||||
B I2C3_ER_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK SUBGHZ_Radio_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
SUBGHZ_Radio_IRQHandler
|
|
||||||
B SUBGHZ_Radio_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK AES_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
AES_IRQHandler
|
|
||||||
B AES_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK RNG_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
RNG_IRQHandler
|
|
||||||
B RNG_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK PKA_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
PKA_IRQHandler
|
|
||||||
B PKA_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA2_Channel1_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA2_Channel1_IRQHandler
|
|
||||||
B DMA2_Channel1_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA2_Channel2_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA2_Channel2_IRQHandler
|
|
||||||
B DMA2_Channel2_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA2_Channel3_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA2_Channel3_IRQHandler
|
|
||||||
B DMA2_Channel3_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA2_Channel4_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA2_Channel4_IRQHandler
|
|
||||||
B DMA2_Channel4_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA2_Channel5_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA2_Channel5_IRQHandler
|
|
||||||
B DMA2_Channel5_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA2_Channel6_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA2_Channel6_IRQHandler
|
|
||||||
B DMA2_Channel6_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA2_Channel7_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA2_Channel7_IRQHandler
|
|
||||||
B DMA2_Channel7_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMAMUX1_OVR_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMAMUX1_OVR_IRQHandler
|
|
||||||
B DMAMUX1_OVR_IRQHandler
|
|
||||||
|
|
||||||
END
|
|
||||||
|
|
||||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
|
||||||
|
|
@ -1,316 +0,0 @@
|
||||||
;********************************************************************************
|
|
||||||
;* File Name : startup_stm32wl55xx_cm0plus.s
|
|
||||||
;* Author : MCD Application Team
|
|
||||||
;* Description : MO+ core vector table of the STM32WLxxxx devices for the
|
|
||||||
;* IAR (EWARM) toolchain.
|
|
||||||
;*
|
|
||||||
;* This module performs:
|
|
||||||
;* - Set the initial SP
|
|
||||||
;* - Set the initial PC == _iar_program_start,
|
|
||||||
;* - Set the vector table entries with the exceptions ISR
|
|
||||||
;* address.
|
|
||||||
;* - Branches to main in the C library (which eventually
|
|
||||||
;* calls main()).
|
|
||||||
;* After Reset the Cortex-M0+ processor is in Thread mode,
|
|
||||||
;* priority is Privileged, and the Stack is set to Main.
|
|
||||||
;********************************************************************************
|
|
||||||
;*
|
|
||||||
;* Copyright (c) 2020(2021) STMicroelectronics.
|
|
||||||
;* All rights reserved.
|
|
||||||
;*
|
|
||||||
;* This software is licensed under terms that can be found in the LICENSE file
|
|
||||||
;* in the root directory of this software component.
|
|
||||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
|
||||||
;
|
|
||||||
;*******************************************************************************
|
|
||||||
;
|
|
||||||
;
|
|
||||||
; The modules in this file are included in the libraries, and may be replaced
|
|
||||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
|
||||||
; a user defined start symbol.
|
|
||||||
; To override the cstartup defined in the library, simply add your modified
|
|
||||||
; version to the workbench project.
|
|
||||||
;
|
|
||||||
; The vector table is normally located at address 0.
|
|
||||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
|
||||||
; The name "__vector_table" has special meaning for C-SPY:
|
|
||||||
; it is where the SP start value is found, and the NVIC vector
|
|
||||||
; table register (VTOR) is initialized to this address if != 0.
|
|
||||||
;
|
|
||||||
; Cortex-M version
|
|
||||||
;
|
|
||||||
|
|
||||||
MODULE ?cstartup
|
|
||||||
|
|
||||||
;; Forward declaration of sections.
|
|
||||||
SECTION CSTACK:DATA:NOROOT(3)
|
|
||||||
|
|
||||||
SECTION .intvec:CODE:NOROOT(2)
|
|
||||||
|
|
||||||
EXTERN __iar_program_start
|
|
||||||
EXTERN SystemInit
|
|
||||||
PUBLIC __vector_table
|
|
||||||
|
|
||||||
DATA
|
|
||||||
__vector_table
|
|
||||||
DCD sfe(CSTACK)
|
|
||||||
DCD Reset_Handler ; Reset Handler
|
|
||||||
|
|
||||||
DCD NMI_Handler ; NMI Handler
|
|
||||||
DCD HardFault_Handler ; Hard Fault Handler
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD SVC_Handler ; SVCall Handler
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD PendSV_Handler ; PendSV Handler
|
|
||||||
DCD SysTick_Handler ; SysTick Handler
|
|
||||||
|
|
||||||
; External Interrupts
|
|
||||||
DCD TZIC_ILA_IRQHandler ; TZIC ILA Interrupt
|
|
||||||
DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
|
|
||||||
DCD RTC_LSECSS_IRQHandler ; RTC Wakeup, Tamper, TimeStamp, RTC Alarms (A & B) and RTC SSRU Interrupts and LSECSS Interrupts
|
|
||||||
DCD RCC_FLASH_C1SEV_IRQHandler ; RCC and FLASH and CPU1 M4 SEV Interrupt
|
|
||||||
DCD EXTI1_0_IRQHandler ; EXTI Line 1:0 Interrupt
|
|
||||||
DCD EXTI3_2_IRQHandler ; EXTI Line 3:2 Interrupt
|
|
||||||
DCD EXTI15_4_IRQHandler ; EXTI Line 15:4 interrupt
|
|
||||||
DCD ADC_COMP_DAC_IRQHandler ; ADC, COMP1, COMP2, DAC Interrupt
|
|
||||||
DCD DMA1_Channel1_2_3_IRQHandler ; DMA1 Channel 1 to 3 Interrupt
|
|
||||||
DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channels 4,5,6,7 Interrupt
|
|
||||||
DCD DMA2_DMAMUX1_OVR_IRQHandler ; DMA2 Channels[1..7] and DMAMUX Overrun Interrupts
|
|
||||||
|
|
||||||
DCD LPTIM1_IRQHandler ; LPTIM1 Global Interrupt
|
|
||||||
DCD LPTIM2_IRQHandler ; LPTIM2 Global Interrupt
|
|
||||||
DCD LPTIM3_IRQHandler ; LPTIM3 Global Interrupt
|
|
||||||
|
|
||||||
DCD TIM1_IRQHandler ; TIM1 Global Interrupt
|
|
||||||
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
|
|
||||||
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
|
|
||||||
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
|
|
||||||
DCD IPCC_C2_RX_C2_TX_IRQHandler ; IPCC RX Occupied and TX Free Interrupt Interrupt
|
|
||||||
DCD HSEM_IRQHandler ; Semaphore Interrupt
|
|
||||||
DCD RNG_IRQHandler ; RNG Interrupt
|
|
||||||
DCD AES_PKA_IRQHandler ; AES and PKA Interrupt
|
|
||||||
DCD I2C1_IRQHandler ; I2C1 Event and Error Interrupt
|
|
||||||
DCD I2C2_IRQHandler ; I2C2 Event and Error Interrupt
|
|
||||||
DCD I2C3_IRQHandler ; I2C3 Event and Error Interrupt
|
|
||||||
DCD SPI1_IRQHandler ; SPI1 Interrupt
|
|
||||||
DCD SPI2_IRQHandler ; SPI2 Interrupt
|
|
||||||
DCD USART1_IRQHandler ; USART1 Interrupt
|
|
||||||
DCD USART2_IRQHandler ; USART2 Interrupt
|
|
||||||
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
|
|
||||||
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
|
|
||||||
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
|
|
||||||
|
|
||||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
||||||
;;
|
|
||||||
;; Default interrupt handlers.
|
|
||||||
;;
|
|
||||||
THUMB
|
|
||||||
|
|
||||||
PUBWEAK Reset_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
|
||||||
Reset_Handler
|
|
||||||
LDR R0, =SystemInit
|
|
||||||
BLX R0
|
|
||||||
LDR R0, =__iar_program_start
|
|
||||||
BX R0
|
|
||||||
|
|
||||||
PUBWEAK NMI_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
NMI_Handler
|
|
||||||
B NMI_Handler
|
|
||||||
|
|
||||||
PUBWEAK HardFault_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
HardFault_Handler
|
|
||||||
B HardFault_Handler
|
|
||||||
|
|
||||||
PUBWEAK SVC_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
SVC_Handler
|
|
||||||
B SVC_Handler
|
|
||||||
|
|
||||||
PUBWEAK PendSV_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
PendSV_Handler
|
|
||||||
B PendSV_Handler
|
|
||||||
|
|
||||||
PUBWEAK SysTick_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
SysTick_Handler
|
|
||||||
B SysTick_Handler
|
|
||||||
|
|
||||||
PUBWEAK TZIC_ILA_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
TZIC_ILA_IRQHandler
|
|
||||||
B TZIC_ILA_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK PVD_PVM_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
PVD_PVM_IRQHandler
|
|
||||||
B PVD_PVM_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK RTC_LSECSS_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
RTC_LSECSS_IRQHandler
|
|
||||||
B RTC_LSECSS_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK RCC_FLASH_C1SEV_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
RCC_FLASH_C1SEV_IRQHandler
|
|
||||||
B RCC_FLASH_C1SEV_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK EXTI1_0_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
EXTI1_0_IRQHandler
|
|
||||||
B EXTI1_0_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK EXTI3_2_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
EXTI3_2_IRQHandler
|
|
||||||
B EXTI3_2_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK EXTI15_4_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
EXTI15_4_IRQHandler
|
|
||||||
B EXTI15_4_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK ADC_COMP_DAC_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
ADC_COMP_DAC_IRQHandler
|
|
||||||
B ADC_COMP_DAC_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA1_Channel1_2_3_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA1_Channel1_2_3_IRQHandler
|
|
||||||
B DMA1_Channel1_2_3_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA1_Channel4_5_6_7_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA1_Channel4_5_6_7_IRQHandler
|
|
||||||
B DMA1_Channel4_5_6_7_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA2_DMAMUX1_OVR_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA2_DMAMUX1_OVR_IRQHandler
|
|
||||||
B DMA2_DMAMUX1_OVR_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK LPTIM1_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
LPTIM1_IRQHandler
|
|
||||||
B LPTIM1_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK LPTIM2_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
LPTIM2_IRQHandler
|
|
||||||
B LPTIM2_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK LPTIM3_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
LPTIM3_IRQHandler
|
|
||||||
B LPTIM3_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK TIM1_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
TIM1_IRQHandler
|
|
||||||
B TIM1_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK TIM2_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
TIM2_IRQHandler
|
|
||||||
B TIM2_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK TIM16_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
TIM16_IRQHandler
|
|
||||||
B TIM16_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK TIM17_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
TIM17_IRQHandler
|
|
||||||
B TIM17_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK IPCC_C2_RX_C2_TX_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
IPCC_C2_RX_C2_TX_IRQHandler
|
|
||||||
B IPCC_C2_RX_C2_TX_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK HSEM_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
HSEM_IRQHandler
|
|
||||||
B HSEM_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK RNG_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
RNG_IRQHandler
|
|
||||||
B RNG_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK AES_PKA_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
AES_PKA_IRQHandler
|
|
||||||
B AES_PKA_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK LCD_802_1_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
LCD_802_1_IRQHandler
|
|
||||||
B LCD_802_1_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK I2C1_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
I2C1_IRQHandler
|
|
||||||
B I2C1_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK I2C2_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
I2C2_IRQHandler
|
|
||||||
B I2C2_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK I2C3_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
I2C3_IRQHandler
|
|
||||||
B I2C3_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK SPI1_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
SPI1_IRQHandler
|
|
||||||
B SPI1_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK SPI2_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
SPI2_IRQHandler
|
|
||||||
B SPI2_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK USART1_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
USART1_IRQHandler
|
|
||||||
B USART1_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK USART2_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
USART2_IRQHandler
|
|
||||||
B USART2_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK LPUART1_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
LPUART1_IRQHandler
|
|
||||||
B LPUART1_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK SUBGHZSPI_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
SUBGHZSPI_IRQHandler
|
|
||||||
B SUBGHZSPI_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK SUBGHZ_Radio_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
SUBGHZ_Radio_IRQHandler
|
|
||||||
B SUBGHZ_Radio_IRQHandler
|
|
||||||
|
|
||||||
END
|
|
||||||
|
|
||||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
|
||||||
|
|
@ -1,509 +0,0 @@
|
||||||
;********************************************************************************
|
|
||||||
;* File Name : startup_stm32wl55xx_cm4.s
|
|
||||||
;* Author : MCD Application Team
|
|
||||||
;* Description : M4 core vector table of the STM32WLxxxx devices for the
|
|
||||||
;* IAR (EWARM) toolchain.
|
|
||||||
;*
|
|
||||||
;* This module performs:
|
|
||||||
;* - Set the initial SP
|
|
||||||
;* - Set the initial PC == _iar_program_start,
|
|
||||||
;* - Set the vector table entries with the exceptions ISR
|
|
||||||
;* address.
|
|
||||||
;* - Branches to main in the C library (which eventually
|
|
||||||
;* calls main()).
|
|
||||||
;* After Reset the Cortex-M4 processor is in Thread mode,
|
|
||||||
;* priority is Privileged, and the Stack is set to Main.
|
|
||||||
;********************************************************************************
|
|
||||||
;*
|
|
||||||
;* Copyright (c) 2020(2021) STMicroelectronics.
|
|
||||||
;* All rights reserved.
|
|
||||||
;*
|
|
||||||
;* This software is licensed under terms that can be found in the LICENSE file
|
|
||||||
;* in the root directory of this software component.
|
|
||||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
|
||||||
;
|
|
||||||
;*******************************************************************************
|
|
||||||
;
|
|
||||||
;
|
|
||||||
; The modules in this file are included in the libraries, and may be replaced
|
|
||||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
|
||||||
; a user defined start symbol.
|
|
||||||
; To override the cstartup defined in the library, simply add your modified
|
|
||||||
; version to the workbench project.
|
|
||||||
;
|
|
||||||
; The vector table is normally located at address 0.
|
|
||||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
|
||||||
; The name "__vector_table" has special meaning for C-SPY:
|
|
||||||
; it is where the SP start value is found, and the NVIC vector
|
|
||||||
; table register (VTOR) is initialized to this address if != 0.
|
|
||||||
;
|
|
||||||
; Cortex-M version
|
|
||||||
;
|
|
||||||
|
|
||||||
MODULE ?cstartup
|
|
||||||
|
|
||||||
;; Forward declaration of sections.
|
|
||||||
SECTION CSTACK:DATA:NOROOT(3)
|
|
||||||
|
|
||||||
SECTION .intvec:CODE:NOROOT(2)
|
|
||||||
|
|
||||||
EXTERN __iar_program_start
|
|
||||||
EXTERN SystemInit
|
|
||||||
PUBLIC __vector_table
|
|
||||||
|
|
||||||
DATA
|
|
||||||
__vector_table
|
|
||||||
DCD sfe(CSTACK)
|
|
||||||
DCD Reset_Handler ; Reset Handler
|
|
||||||
|
|
||||||
DCD NMI_Handler ; NMI Handler
|
|
||||||
DCD HardFault_Handler ; Hard Fault Handler
|
|
||||||
DCD MemManage_Handler ; MPU Fault Handler
|
|
||||||
DCD BusFault_Handler ; Bus Fault Handler
|
|
||||||
DCD UsageFault_Handler ; Usage Fault Handler
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD SVC_Handler ; SVCall Handler
|
|
||||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD PendSV_Handler ; PendSV Handler
|
|
||||||
DCD SysTick_Handler ; SysTick Handler
|
|
||||||
|
|
||||||
; External Interrupts
|
|
||||||
DCD WWDG_IRQHandler ; Window WatchDog
|
|
||||||
DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
|
|
||||||
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts
|
|
||||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
|
|
||||||
DCD FLASH_IRQHandler ; FLASH global Interrupt
|
|
||||||
DCD RCC_IRQHandler ; RCC Interrupt
|
|
||||||
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
|
|
||||||
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
|
|
||||||
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
|
|
||||||
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
|
|
||||||
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
|
|
||||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
|
|
||||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
|
|
||||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
|
|
||||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
|
|
||||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
|
|
||||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
|
|
||||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
|
|
||||||
DCD ADC_IRQHandler ; ADC Interrupt
|
|
||||||
DCD DAC_IRQHandler ; DAC Interrupt
|
|
||||||
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt
|
|
||||||
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
|
|
||||||
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
|
|
||||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
|
|
||||||
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
|
|
||||||
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
|
|
||||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
|
|
||||||
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
|
|
||||||
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
|
|
||||||
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
|
|
||||||
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
|
|
||||||
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
|
|
||||||
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
|
|
||||||
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
|
|
||||||
DCD SPI1_IRQHandler ; SPI1 Interrupt
|
|
||||||
DCD SPI2_IRQHandler ; SPI2 Interrupt
|
|
||||||
DCD USART1_IRQHandler ; USART1 Interrupt
|
|
||||||
DCD USART2_IRQHandler ; USART2 Interrupt
|
|
||||||
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
|
|
||||||
DCD LPTIM1_IRQHandler ; LPTIM1 Global Interrupt
|
|
||||||
DCD LPTIM2_IRQHandler ; LPTIM2 Global Interrupt
|
|
||||||
DCD EXTI15_10_IRQHandler ; EXTI Lines [15:10] Interrupt
|
|
||||||
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
|
|
||||||
DCD LPTIM3_IRQHandler ; LPTIM3 Global Interrupt
|
|
||||||
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
|
|
||||||
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
|
|
||||||
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
|
|
||||||
DCD HSEM_IRQHandler ; HSEM0 Interrupt
|
|
||||||
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
|
|
||||||
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
|
|
||||||
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
|
|
||||||
DCD AES_IRQHandler ; AES Interrupt
|
|
||||||
DCD RNG_IRQHandler ; RNG1 Interrupt
|
|
||||||
DCD PKA_IRQHandler ; PKA Interrupt
|
|
||||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
|
|
||||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
|
|
||||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
|
|
||||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
|
|
||||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
|
|
||||||
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
|
|
||||||
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
|
|
||||||
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
|
|
||||||
|
|
||||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
||||||
;;
|
|
||||||
;; Default interrupt handlers.
|
|
||||||
;;
|
|
||||||
THUMB
|
|
||||||
|
|
||||||
PUBWEAK Reset_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
|
||||||
Reset_Handler
|
|
||||||
LDR R0, =SystemInit
|
|
||||||
BLX R0
|
|
||||||
LDR R0, =__iar_program_start
|
|
||||||
BX R0
|
|
||||||
|
|
||||||
PUBWEAK NMI_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
NMI_Handler
|
|
||||||
B NMI_Handler
|
|
||||||
|
|
||||||
PUBWEAK HardFault_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
HardFault_Handler
|
|
||||||
B HardFault_Handler
|
|
||||||
|
|
||||||
PUBWEAK MemManage_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
MemManage_Handler
|
|
||||||
B MemManage_Handler
|
|
||||||
|
|
||||||
PUBWEAK BusFault_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
BusFault_Handler
|
|
||||||
B BusFault_Handler
|
|
||||||
|
|
||||||
PUBWEAK UsageFault_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
UsageFault_Handler
|
|
||||||
B UsageFault_Handler
|
|
||||||
|
|
||||||
PUBWEAK SVC_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
SVC_Handler
|
|
||||||
B SVC_Handler
|
|
||||||
|
|
||||||
PUBWEAK DebugMon_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DebugMon_Handler
|
|
||||||
B DebugMon_Handler
|
|
||||||
|
|
||||||
PUBWEAK PendSV_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
PendSV_Handler
|
|
||||||
B PendSV_Handler
|
|
||||||
|
|
||||||
PUBWEAK SysTick_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
SysTick_Handler
|
|
||||||
B SysTick_Handler
|
|
||||||
|
|
||||||
PUBWEAK WWDG_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
WWDG_IRQHandler
|
|
||||||
B WWDG_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK PVD_PVM_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
PVD_PVM_IRQHandler
|
|
||||||
B PVD_PVM_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK TAMP_STAMP_LSECSS_SSRU_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
TAMP_STAMP_LSECSS_SSRU_IRQHandler
|
|
||||||
B TAMP_STAMP_LSECSS_SSRU_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK RTC_WKUP_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
RTC_WKUP_IRQHandler
|
|
||||||
B RTC_WKUP_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK FLASH_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
FLASH_IRQHandler
|
|
||||||
B FLASH_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK RCC_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
RCC_IRQHandler
|
|
||||||
B RCC_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK EXTI0_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
EXTI0_IRQHandler
|
|
||||||
B EXTI0_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK EXTI1_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
EXTI1_IRQHandler
|
|
||||||
B EXTI1_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK EXTI2_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
EXTI2_IRQHandler
|
|
||||||
B EXTI2_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK EXTI3_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
EXTI3_IRQHandler
|
|
||||||
B EXTI3_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK EXTI4_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
EXTI4_IRQHandler
|
|
||||||
B EXTI4_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA1_Channel1_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA1_Channel1_IRQHandler
|
|
||||||
B DMA1_Channel1_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA1_Channel2_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA1_Channel2_IRQHandler
|
|
||||||
B DMA1_Channel2_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA1_Channel3_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA1_Channel3_IRQHandler
|
|
||||||
B DMA1_Channel3_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA1_Channel4_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA1_Channel4_IRQHandler
|
|
||||||
B DMA1_Channel4_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA1_Channel5_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA1_Channel5_IRQHandler
|
|
||||||
B DMA1_Channel5_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA1_Channel6_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA1_Channel6_IRQHandler
|
|
||||||
B DMA1_Channel6_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA1_Channel7_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA1_Channel7_IRQHandler
|
|
||||||
B DMA1_Channel7_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK ADC_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
ADC_IRQHandler
|
|
||||||
B ADC_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DAC_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DAC_IRQHandler
|
|
||||||
B DAC_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK C2SEV_PWR_C2H_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
C2SEV_PWR_C2H_IRQHandler
|
|
||||||
B C2SEV_PWR_C2H_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK COMP_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
COMP_IRQHandler
|
|
||||||
B COMP_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK EXTI9_5_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
EXTI9_5_IRQHandler
|
|
||||||
B EXTI9_5_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK TIM1_BRK_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
TIM1_BRK_IRQHandler
|
|
||||||
B TIM1_BRK_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK TIM1_UP_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
TIM1_UP_IRQHandler
|
|
||||||
B TIM1_UP_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK TIM1_TRG_COM_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
TIM1_TRG_COM_IRQHandler
|
|
||||||
B TIM1_TRG_COM_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK TIM1_CC_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
TIM1_CC_IRQHandler
|
|
||||||
B TIM1_CC_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK TIM2_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
TIM2_IRQHandler
|
|
||||||
B TIM2_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK TIM16_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
TIM16_IRQHandler
|
|
||||||
B TIM16_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK TIM17_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
TIM17_IRQHandler
|
|
||||||
B TIM17_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK I2C1_EV_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
I2C1_EV_IRQHandler
|
|
||||||
B I2C1_EV_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK I2C1_ER_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
I2C1_ER_IRQHandler
|
|
||||||
B I2C1_ER_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK I2C2_EV_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
I2C2_EV_IRQHandler
|
|
||||||
B I2C2_EV_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK I2C2_ER_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
I2C2_ER_IRQHandler
|
|
||||||
B I2C2_ER_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK SPI1_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
SPI1_IRQHandler
|
|
||||||
B SPI1_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK SPI2_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
SPI2_IRQHandler
|
|
||||||
B SPI2_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK USART1_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
USART1_IRQHandler
|
|
||||||
B USART1_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK USART2_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
USART2_IRQHandler
|
|
||||||
B USART2_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK LPUART1_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
LPUART1_IRQHandler
|
|
||||||
B LPUART1_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK LPTIM1_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
LPTIM1_IRQHandler
|
|
||||||
B LPTIM1_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK LPTIM2_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
LPTIM2_IRQHandler
|
|
||||||
B LPTIM2_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK EXTI15_10_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
EXTI15_10_IRQHandler
|
|
||||||
B EXTI15_10_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK RTC_Alarm_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
RTC_Alarm_IRQHandler
|
|
||||||
B RTC_Alarm_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK LPTIM3_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
LPTIM3_IRQHandler
|
|
||||||
B LPTIM3_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK SUBGHZSPI_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
SUBGHZSPI_IRQHandler
|
|
||||||
B SUBGHZSPI_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK IPCC_C1_RX_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
IPCC_C1_RX_IRQHandler
|
|
||||||
B IPCC_C1_RX_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK IPCC_C1_TX_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
IPCC_C1_TX_IRQHandler
|
|
||||||
B IPCC_C1_TX_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK HSEM_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
HSEM_IRQHandler
|
|
||||||
B HSEM_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK I2C3_EV_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
I2C3_EV_IRQHandler
|
|
||||||
B I2C3_EV_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK I2C3_ER_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
I2C3_ER_IRQHandler
|
|
||||||
B I2C3_ER_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK SUBGHZ_Radio_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
SUBGHZ_Radio_IRQHandler
|
|
||||||
B SUBGHZ_Radio_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK AES_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
AES_IRQHandler
|
|
||||||
B AES_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK RNG_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
RNG_IRQHandler
|
|
||||||
B RNG_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK PKA_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
PKA_IRQHandler
|
|
||||||
B PKA_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA2_Channel1_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA2_Channel1_IRQHandler
|
|
||||||
B DMA2_Channel1_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA2_Channel2_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA2_Channel2_IRQHandler
|
|
||||||
B DMA2_Channel2_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA2_Channel3_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA2_Channel3_IRQHandler
|
|
||||||
B DMA2_Channel3_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA2_Channel4_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA2_Channel4_IRQHandler
|
|
||||||
B DMA2_Channel4_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA2_Channel5_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA2_Channel5_IRQHandler
|
|
||||||
B DMA2_Channel5_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA2_Channel6_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA2_Channel6_IRQHandler
|
|
||||||
B DMA2_Channel6_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA2_Channel7_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA2_Channel7_IRQHandler
|
|
||||||
B DMA2_Channel7_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMAMUX1_OVR_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMAMUX1_OVR_IRQHandler
|
|
||||||
B DMAMUX1_OVR_IRQHandler
|
|
||||||
|
|
||||||
END
|
|
||||||
|
|
||||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
|
||||||
|
|
@ -1,494 +0,0 @@
|
||||||
;********************************************************************************
|
|
||||||
;* File Name : startup_stm32wle4xx.s
|
|
||||||
;* Author : MCD Application Team
|
|
||||||
;* Description : M4 core vector table of the STM32WLxxxx devices for the
|
|
||||||
;* IAR (EWARM) toolchain.
|
|
||||||
;*
|
|
||||||
;* This module performs:
|
|
||||||
;* - Set the initial SP
|
|
||||||
;* - Set the initial PC == _iar_program_start,
|
|
||||||
;* - Set the vector table entries with the exceptions ISR
|
|
||||||
;* address.
|
|
||||||
;* - Branches to main in the C library (which eventually
|
|
||||||
;* calls main()).
|
|
||||||
;* After Reset the Cortex-M4 processor is in Thread mode,
|
|
||||||
;* priority is Privileged, and the Stack is set to Main.
|
|
||||||
;********************************************************************************
|
|
||||||
;*
|
|
||||||
;* Copyright (c) 2020(2021) STMicroelectronics.
|
|
||||||
;* All rights reserved.
|
|
||||||
;*
|
|
||||||
;* This software is licensed under terms that can be found in the LICENSE file
|
|
||||||
;* in the root directory of this software component.
|
|
||||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
|
||||||
;
|
|
||||||
;*******************************************************************************
|
|
||||||
;
|
|
||||||
;
|
|
||||||
; The modules in this file are included in the libraries, and may be replaced
|
|
||||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
|
||||||
; a user defined start symbol.
|
|
||||||
; To override the cstartup defined in the library, simply add your modified
|
|
||||||
; version to the workbench project.
|
|
||||||
;
|
|
||||||
; The vector table is normally located at address 0.
|
|
||||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
|
||||||
; The name "__vector_table" has special meaning for C-SPY:
|
|
||||||
; it is where the SP start value is found, and the NVIC vector
|
|
||||||
; table register (VTOR) is initialized to this address if != 0.
|
|
||||||
;
|
|
||||||
; Cortex-M version
|
|
||||||
;
|
|
||||||
|
|
||||||
MODULE ?cstartup
|
|
||||||
|
|
||||||
;; Forward declaration of sections.
|
|
||||||
SECTION CSTACK:DATA:NOROOT(3)
|
|
||||||
|
|
||||||
SECTION .intvec:CODE:NOROOT(2)
|
|
||||||
|
|
||||||
EXTERN __iar_program_start
|
|
||||||
EXTERN SystemInit
|
|
||||||
PUBLIC __vector_table
|
|
||||||
|
|
||||||
DATA
|
|
||||||
__vector_table
|
|
||||||
DCD sfe(CSTACK)
|
|
||||||
DCD Reset_Handler ; Reset Handler
|
|
||||||
|
|
||||||
DCD NMI_Handler ; NMI Handler
|
|
||||||
DCD HardFault_Handler ; Hard Fault Handler
|
|
||||||
DCD MemManage_Handler ; MPU Fault Handler
|
|
||||||
DCD BusFault_Handler ; Bus Fault Handler
|
|
||||||
DCD UsageFault_Handler ; Usage Fault Handler
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD SVC_Handler ; SVCall Handler
|
|
||||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD PendSV_Handler ; PendSV Handler
|
|
||||||
DCD SysTick_Handler ; SysTick Handler
|
|
||||||
|
|
||||||
; External Interrupts
|
|
||||||
DCD WWDG_IRQHandler ; Window WatchDog
|
|
||||||
DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
|
|
||||||
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts
|
|
||||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
|
|
||||||
DCD FLASH_IRQHandler ; FLASH global Interrupt
|
|
||||||
DCD RCC_IRQHandler ; RCC Interrupt
|
|
||||||
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
|
|
||||||
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
|
|
||||||
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
|
|
||||||
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
|
|
||||||
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
|
|
||||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
|
|
||||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
|
|
||||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
|
|
||||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
|
|
||||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
|
|
||||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
|
|
||||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
|
|
||||||
DCD ADC_IRQHandler ; ADC Interrupt
|
|
||||||
DCD DAC_IRQHandler ; DAC Interrupt
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
|
|
||||||
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
|
|
||||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
|
|
||||||
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
|
|
||||||
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
|
|
||||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
|
|
||||||
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
|
|
||||||
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
|
|
||||||
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
|
|
||||||
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
|
|
||||||
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
|
|
||||||
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
|
|
||||||
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
|
|
||||||
DCD SPI1_IRQHandler ; SPI1 Interrupt
|
|
||||||
DCD SPI2_IRQHandler ; SPI2 Interrupt
|
|
||||||
DCD USART1_IRQHandler ; USART1 Interrupt
|
|
||||||
DCD USART2_IRQHandler ; USART2 Interrupt
|
|
||||||
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
|
|
||||||
DCD LPTIM1_IRQHandler ; LPTIM1 Global Interrupt
|
|
||||||
DCD LPTIM2_IRQHandler ; LPTIM2 Global Interrupt
|
|
||||||
DCD EXTI15_10_IRQHandler ; EXTI Lines [15:10] Interrupt
|
|
||||||
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
|
|
||||||
DCD LPTIM3_IRQHandler ; LPTIM3 Global Interrupt
|
|
||||||
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD HSEM_IRQHandler ; HSEM0 Interrupt
|
|
||||||
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
|
|
||||||
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
|
|
||||||
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
|
|
||||||
DCD AES_IRQHandler ; AES Interrupt
|
|
||||||
DCD RNG_IRQHandler ; RNG1 Interrupt
|
|
||||||
DCD PKA_IRQHandler ; PKA Interrupt
|
|
||||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
|
|
||||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
|
|
||||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
|
|
||||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
|
|
||||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
|
|
||||||
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
|
|
||||||
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
|
|
||||||
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
|
|
||||||
|
|
||||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
||||||
;;
|
|
||||||
;; Default interrupt handlers.
|
|
||||||
;;
|
|
||||||
THUMB
|
|
||||||
|
|
||||||
PUBWEAK Reset_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
|
||||||
Reset_Handler
|
|
||||||
LDR R0, =SystemInit
|
|
||||||
BLX R0
|
|
||||||
LDR R0, =__iar_program_start
|
|
||||||
BX R0
|
|
||||||
|
|
||||||
PUBWEAK NMI_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
NMI_Handler
|
|
||||||
B NMI_Handler
|
|
||||||
|
|
||||||
PUBWEAK HardFault_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
HardFault_Handler
|
|
||||||
B HardFault_Handler
|
|
||||||
|
|
||||||
PUBWEAK MemManage_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
MemManage_Handler
|
|
||||||
B MemManage_Handler
|
|
||||||
|
|
||||||
PUBWEAK BusFault_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
BusFault_Handler
|
|
||||||
B BusFault_Handler
|
|
||||||
|
|
||||||
PUBWEAK UsageFault_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
UsageFault_Handler
|
|
||||||
B UsageFault_Handler
|
|
||||||
|
|
||||||
PUBWEAK SVC_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
SVC_Handler
|
|
||||||
B SVC_Handler
|
|
||||||
|
|
||||||
PUBWEAK DebugMon_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DebugMon_Handler
|
|
||||||
B DebugMon_Handler
|
|
||||||
|
|
||||||
PUBWEAK PendSV_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
PendSV_Handler
|
|
||||||
B PendSV_Handler
|
|
||||||
|
|
||||||
PUBWEAK SysTick_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
SysTick_Handler
|
|
||||||
B SysTick_Handler
|
|
||||||
|
|
||||||
PUBWEAK WWDG_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
WWDG_IRQHandler
|
|
||||||
B WWDG_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK PVD_PVM_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
PVD_PVM_IRQHandler
|
|
||||||
B PVD_PVM_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK TAMP_STAMP_LSECSS_SSRU_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
TAMP_STAMP_LSECSS_SSRU_IRQHandler
|
|
||||||
B TAMP_STAMP_LSECSS_SSRU_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK RTC_WKUP_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
RTC_WKUP_IRQHandler
|
|
||||||
B RTC_WKUP_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK FLASH_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
FLASH_IRQHandler
|
|
||||||
B FLASH_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK RCC_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
RCC_IRQHandler
|
|
||||||
B RCC_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK EXTI0_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
EXTI0_IRQHandler
|
|
||||||
B EXTI0_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK EXTI1_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
EXTI1_IRQHandler
|
|
||||||
B EXTI1_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK EXTI2_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
EXTI2_IRQHandler
|
|
||||||
B EXTI2_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK EXTI3_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
EXTI3_IRQHandler
|
|
||||||
B EXTI3_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK EXTI4_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
EXTI4_IRQHandler
|
|
||||||
B EXTI4_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA1_Channel1_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA1_Channel1_IRQHandler
|
|
||||||
B DMA1_Channel1_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA1_Channel2_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA1_Channel2_IRQHandler
|
|
||||||
B DMA1_Channel2_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA1_Channel3_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA1_Channel3_IRQHandler
|
|
||||||
B DMA1_Channel3_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA1_Channel4_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA1_Channel4_IRQHandler
|
|
||||||
B DMA1_Channel4_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA1_Channel5_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA1_Channel5_IRQHandler
|
|
||||||
B DMA1_Channel5_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA1_Channel6_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA1_Channel6_IRQHandler
|
|
||||||
B DMA1_Channel6_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA1_Channel7_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA1_Channel7_IRQHandler
|
|
||||||
B DMA1_Channel7_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK ADC_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
ADC_IRQHandler
|
|
||||||
B ADC_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DAC_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DAC_IRQHandler
|
|
||||||
B DAC_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK COMP_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
COMP_IRQHandler
|
|
||||||
B COMP_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK EXTI9_5_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
EXTI9_5_IRQHandler
|
|
||||||
B EXTI9_5_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK TIM1_BRK_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
TIM1_BRK_IRQHandler
|
|
||||||
B TIM1_BRK_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK TIM1_UP_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
TIM1_UP_IRQHandler
|
|
||||||
B TIM1_UP_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK TIM1_TRG_COM_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
TIM1_TRG_COM_IRQHandler
|
|
||||||
B TIM1_TRG_COM_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK TIM1_CC_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
TIM1_CC_IRQHandler
|
|
||||||
B TIM1_CC_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK TIM2_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
TIM2_IRQHandler
|
|
||||||
B TIM2_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK TIM16_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
TIM16_IRQHandler
|
|
||||||
B TIM16_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK TIM17_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
TIM17_IRQHandler
|
|
||||||
B TIM17_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK I2C1_EV_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
I2C1_EV_IRQHandler
|
|
||||||
B I2C1_EV_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK I2C1_ER_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
I2C1_ER_IRQHandler
|
|
||||||
B I2C1_ER_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK I2C2_EV_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
I2C2_EV_IRQHandler
|
|
||||||
B I2C2_EV_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK I2C2_ER_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
I2C2_ER_IRQHandler
|
|
||||||
B I2C2_ER_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK SPI1_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
SPI1_IRQHandler
|
|
||||||
B SPI1_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK SPI2_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
SPI2_IRQHandler
|
|
||||||
B SPI2_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK USART1_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
USART1_IRQHandler
|
|
||||||
B USART1_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK USART2_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
USART2_IRQHandler
|
|
||||||
B USART2_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK LPUART1_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
LPUART1_IRQHandler
|
|
||||||
B LPUART1_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK LPTIM1_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
LPTIM1_IRQHandler
|
|
||||||
B LPTIM1_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK LPTIM2_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
LPTIM2_IRQHandler
|
|
||||||
B LPTIM2_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK EXTI15_10_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
EXTI15_10_IRQHandler
|
|
||||||
B EXTI15_10_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK RTC_Alarm_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
RTC_Alarm_IRQHandler
|
|
||||||
B RTC_Alarm_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK LPTIM3_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
LPTIM3_IRQHandler
|
|
||||||
B LPTIM3_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK SUBGHZSPI_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
SUBGHZSPI_IRQHandler
|
|
||||||
B SUBGHZSPI_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK HSEM_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
HSEM_IRQHandler
|
|
||||||
B HSEM_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK I2C3_EV_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
I2C3_EV_IRQHandler
|
|
||||||
B I2C3_EV_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK I2C3_ER_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
I2C3_ER_IRQHandler
|
|
||||||
B I2C3_ER_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK SUBGHZ_Radio_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
SUBGHZ_Radio_IRQHandler
|
|
||||||
B SUBGHZ_Radio_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK AES_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
AES_IRQHandler
|
|
||||||
B AES_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK RNG_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
RNG_IRQHandler
|
|
||||||
B RNG_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK PKA_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
PKA_IRQHandler
|
|
||||||
B PKA_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA2_Channel1_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA2_Channel1_IRQHandler
|
|
||||||
B DMA2_Channel1_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA2_Channel2_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA2_Channel2_IRQHandler
|
|
||||||
B DMA2_Channel2_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA2_Channel3_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA2_Channel3_IRQHandler
|
|
||||||
B DMA2_Channel3_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA2_Channel4_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA2_Channel4_IRQHandler
|
|
||||||
B DMA2_Channel4_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA2_Channel5_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA2_Channel5_IRQHandler
|
|
||||||
B DMA2_Channel5_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA2_Channel6_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA2_Channel6_IRQHandler
|
|
||||||
B DMA2_Channel6_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA2_Channel7_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA2_Channel7_IRQHandler
|
|
||||||
B DMA2_Channel7_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMAMUX1_OVR_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMAMUX1_OVR_IRQHandler
|
|
||||||
B DMAMUX1_OVR_IRQHandler
|
|
||||||
|
|
||||||
END
|
|
||||||
|
|
||||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
|
||||||
|
|
@ -1,494 +0,0 @@
|
||||||
;********************************************************************************
|
|
||||||
;* File Name : startup_stm32wle5xx.s
|
|
||||||
;* Author : MCD Application Team
|
|
||||||
;* Description : M4 core vector table of the STM32WLxxxx devices for the
|
|
||||||
;* IAR (EWARM) toolchain.
|
|
||||||
;*
|
|
||||||
;* This module performs:
|
|
||||||
;* - Set the initial SP
|
|
||||||
;* - Set the initial PC == _iar_program_start,
|
|
||||||
;* - Set the vector table entries with the exceptions ISR
|
|
||||||
;* address.
|
|
||||||
;* - Branches to main in the C library (which eventually
|
|
||||||
;* calls main()).
|
|
||||||
;* After Reset the Cortex-M4 processor is in Thread mode,
|
|
||||||
;* priority is Privileged, and the Stack is set to Main.
|
|
||||||
;********************************************************************************
|
|
||||||
;*
|
|
||||||
;* Copyright (c) 2020(2021) STMicroelectronics.
|
|
||||||
;* All rights reserved.
|
|
||||||
;*
|
|
||||||
;* This software is licensed under terms that can be found in the LICENSE file
|
|
||||||
;* in the root directory of this software component.
|
|
||||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
|
||||||
;
|
|
||||||
;*******************************************************************************
|
|
||||||
;
|
|
||||||
;
|
|
||||||
; The modules in this file are included in the libraries, and may be replaced
|
|
||||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
|
||||||
; a user defined start symbol.
|
|
||||||
; To override the cstartup defined in the library, simply add your modified
|
|
||||||
; version to the workbench project.
|
|
||||||
;
|
|
||||||
; The vector table is normally located at address 0.
|
|
||||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
|
||||||
; The name "__vector_table" has special meaning for C-SPY:
|
|
||||||
; it is where the SP start value is found, and the NVIC vector
|
|
||||||
; table register (VTOR) is initialized to this address if != 0.
|
|
||||||
;
|
|
||||||
; Cortex-M version
|
|
||||||
;
|
|
||||||
|
|
||||||
MODULE ?cstartup
|
|
||||||
|
|
||||||
;; Forward declaration of sections.
|
|
||||||
SECTION CSTACK:DATA:NOROOT(3)
|
|
||||||
|
|
||||||
SECTION .intvec:CODE:NOROOT(2)
|
|
||||||
|
|
||||||
EXTERN __iar_program_start
|
|
||||||
EXTERN SystemInit
|
|
||||||
PUBLIC __vector_table
|
|
||||||
|
|
||||||
DATA
|
|
||||||
__vector_table
|
|
||||||
DCD sfe(CSTACK)
|
|
||||||
DCD Reset_Handler ; Reset Handler
|
|
||||||
|
|
||||||
DCD NMI_Handler ; NMI Handler
|
|
||||||
DCD HardFault_Handler ; Hard Fault Handler
|
|
||||||
DCD MemManage_Handler ; MPU Fault Handler
|
|
||||||
DCD BusFault_Handler ; Bus Fault Handler
|
|
||||||
DCD UsageFault_Handler ; Usage Fault Handler
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD SVC_Handler ; SVCall Handler
|
|
||||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD PendSV_Handler ; PendSV Handler
|
|
||||||
DCD SysTick_Handler ; SysTick Handler
|
|
||||||
|
|
||||||
; External Interrupts
|
|
||||||
DCD WWDG_IRQHandler ; Window WatchDog
|
|
||||||
DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
|
|
||||||
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts
|
|
||||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
|
|
||||||
DCD FLASH_IRQHandler ; FLASH global Interrupt
|
|
||||||
DCD RCC_IRQHandler ; RCC Interrupt
|
|
||||||
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
|
|
||||||
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
|
|
||||||
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
|
|
||||||
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
|
|
||||||
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
|
|
||||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
|
|
||||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
|
|
||||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
|
|
||||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
|
|
||||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
|
|
||||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
|
|
||||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
|
|
||||||
DCD ADC_IRQHandler ; ADC Interrupt
|
|
||||||
DCD DAC_IRQHandler ; DAC Interrupt
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
|
|
||||||
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
|
|
||||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
|
|
||||||
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
|
|
||||||
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
|
|
||||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
|
|
||||||
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
|
|
||||||
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
|
|
||||||
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
|
|
||||||
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
|
|
||||||
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
|
|
||||||
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
|
|
||||||
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
|
|
||||||
DCD SPI1_IRQHandler ; SPI1 Interrupt
|
|
||||||
DCD SPI2_IRQHandler ; SPI2 Interrupt
|
|
||||||
DCD USART1_IRQHandler ; USART1 Interrupt
|
|
||||||
DCD USART2_IRQHandler ; USART2 Interrupt
|
|
||||||
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
|
|
||||||
DCD LPTIM1_IRQHandler ; LPTIM1 Global Interrupt
|
|
||||||
DCD LPTIM2_IRQHandler ; LPTIM2 Global Interrupt
|
|
||||||
DCD EXTI15_10_IRQHandler ; EXTI Lines [15:10] Interrupt
|
|
||||||
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
|
|
||||||
DCD LPTIM3_IRQHandler ; LPTIM3 Global Interrupt
|
|
||||||
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD HSEM_IRQHandler ; HSEM0 Interrupt
|
|
||||||
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
|
|
||||||
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
|
|
||||||
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
|
|
||||||
DCD AES_IRQHandler ; AES Interrupt
|
|
||||||
DCD RNG_IRQHandler ; RNG1 Interrupt
|
|
||||||
DCD PKA_IRQHandler ; PKA Interrupt
|
|
||||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
|
|
||||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
|
|
||||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
|
|
||||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
|
|
||||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
|
|
||||||
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
|
|
||||||
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
|
|
||||||
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
|
|
||||||
|
|
||||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
||||||
;;
|
|
||||||
;; Default interrupt handlers.
|
|
||||||
;;
|
|
||||||
THUMB
|
|
||||||
|
|
||||||
PUBWEAK Reset_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
|
||||||
Reset_Handler
|
|
||||||
LDR R0, =SystemInit
|
|
||||||
BLX R0
|
|
||||||
LDR R0, =__iar_program_start
|
|
||||||
BX R0
|
|
||||||
|
|
||||||
PUBWEAK NMI_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
NMI_Handler
|
|
||||||
B NMI_Handler
|
|
||||||
|
|
||||||
PUBWEAK HardFault_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
HardFault_Handler
|
|
||||||
B HardFault_Handler
|
|
||||||
|
|
||||||
PUBWEAK MemManage_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
MemManage_Handler
|
|
||||||
B MemManage_Handler
|
|
||||||
|
|
||||||
PUBWEAK BusFault_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
BusFault_Handler
|
|
||||||
B BusFault_Handler
|
|
||||||
|
|
||||||
PUBWEAK UsageFault_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
UsageFault_Handler
|
|
||||||
B UsageFault_Handler
|
|
||||||
|
|
||||||
PUBWEAK SVC_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
SVC_Handler
|
|
||||||
B SVC_Handler
|
|
||||||
|
|
||||||
PUBWEAK DebugMon_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DebugMon_Handler
|
|
||||||
B DebugMon_Handler
|
|
||||||
|
|
||||||
PUBWEAK PendSV_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
PendSV_Handler
|
|
||||||
B PendSV_Handler
|
|
||||||
|
|
||||||
PUBWEAK SysTick_Handler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
SysTick_Handler
|
|
||||||
B SysTick_Handler
|
|
||||||
|
|
||||||
PUBWEAK WWDG_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
WWDG_IRQHandler
|
|
||||||
B WWDG_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK PVD_PVM_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
PVD_PVM_IRQHandler
|
|
||||||
B PVD_PVM_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK TAMP_STAMP_LSECSS_SSRU_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
TAMP_STAMP_LSECSS_SSRU_IRQHandler
|
|
||||||
B TAMP_STAMP_LSECSS_SSRU_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK RTC_WKUP_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
RTC_WKUP_IRQHandler
|
|
||||||
B RTC_WKUP_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK FLASH_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
FLASH_IRQHandler
|
|
||||||
B FLASH_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK RCC_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
RCC_IRQHandler
|
|
||||||
B RCC_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK EXTI0_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
EXTI0_IRQHandler
|
|
||||||
B EXTI0_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK EXTI1_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
EXTI1_IRQHandler
|
|
||||||
B EXTI1_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK EXTI2_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
EXTI2_IRQHandler
|
|
||||||
B EXTI2_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK EXTI3_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
EXTI3_IRQHandler
|
|
||||||
B EXTI3_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK EXTI4_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
EXTI4_IRQHandler
|
|
||||||
B EXTI4_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA1_Channel1_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA1_Channel1_IRQHandler
|
|
||||||
B DMA1_Channel1_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA1_Channel2_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA1_Channel2_IRQHandler
|
|
||||||
B DMA1_Channel2_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA1_Channel3_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA1_Channel3_IRQHandler
|
|
||||||
B DMA1_Channel3_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA1_Channel4_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA1_Channel4_IRQHandler
|
|
||||||
B DMA1_Channel4_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA1_Channel5_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA1_Channel5_IRQHandler
|
|
||||||
B DMA1_Channel5_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA1_Channel6_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA1_Channel6_IRQHandler
|
|
||||||
B DMA1_Channel6_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA1_Channel7_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA1_Channel7_IRQHandler
|
|
||||||
B DMA1_Channel7_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK ADC_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
ADC_IRQHandler
|
|
||||||
B ADC_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DAC_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DAC_IRQHandler
|
|
||||||
B DAC_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK COMP_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
COMP_IRQHandler
|
|
||||||
B COMP_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK EXTI9_5_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
EXTI9_5_IRQHandler
|
|
||||||
B EXTI9_5_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK TIM1_BRK_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
TIM1_BRK_IRQHandler
|
|
||||||
B TIM1_BRK_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK TIM1_UP_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
TIM1_UP_IRQHandler
|
|
||||||
B TIM1_UP_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK TIM1_TRG_COM_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
TIM1_TRG_COM_IRQHandler
|
|
||||||
B TIM1_TRG_COM_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK TIM1_CC_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
TIM1_CC_IRQHandler
|
|
||||||
B TIM1_CC_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK TIM2_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
TIM2_IRQHandler
|
|
||||||
B TIM2_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK TIM16_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
TIM16_IRQHandler
|
|
||||||
B TIM16_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK TIM17_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
TIM17_IRQHandler
|
|
||||||
B TIM17_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK I2C1_EV_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
I2C1_EV_IRQHandler
|
|
||||||
B I2C1_EV_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK I2C1_ER_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
I2C1_ER_IRQHandler
|
|
||||||
B I2C1_ER_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK I2C2_EV_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
I2C2_EV_IRQHandler
|
|
||||||
B I2C2_EV_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK I2C2_ER_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
I2C2_ER_IRQHandler
|
|
||||||
B I2C2_ER_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK SPI1_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
SPI1_IRQHandler
|
|
||||||
B SPI1_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK SPI2_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
SPI2_IRQHandler
|
|
||||||
B SPI2_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK USART1_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
USART1_IRQHandler
|
|
||||||
B USART1_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK USART2_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
USART2_IRQHandler
|
|
||||||
B USART2_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK LPUART1_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
LPUART1_IRQHandler
|
|
||||||
B LPUART1_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK LPTIM1_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
LPTIM1_IRQHandler
|
|
||||||
B LPTIM1_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK LPTIM2_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
LPTIM2_IRQHandler
|
|
||||||
B LPTIM2_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK EXTI15_10_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
EXTI15_10_IRQHandler
|
|
||||||
B EXTI15_10_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK RTC_Alarm_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
RTC_Alarm_IRQHandler
|
|
||||||
B RTC_Alarm_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK LPTIM3_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
LPTIM3_IRQHandler
|
|
||||||
B LPTIM3_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK SUBGHZSPI_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
SUBGHZSPI_IRQHandler
|
|
||||||
B SUBGHZSPI_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK HSEM_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
HSEM_IRQHandler
|
|
||||||
B HSEM_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK I2C3_EV_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
I2C3_EV_IRQHandler
|
|
||||||
B I2C3_EV_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK I2C3_ER_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
I2C3_ER_IRQHandler
|
|
||||||
B I2C3_ER_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK SUBGHZ_Radio_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
SUBGHZ_Radio_IRQHandler
|
|
||||||
B SUBGHZ_Radio_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK AES_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
AES_IRQHandler
|
|
||||||
B AES_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK RNG_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
RNG_IRQHandler
|
|
||||||
B RNG_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK PKA_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
PKA_IRQHandler
|
|
||||||
B PKA_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA2_Channel1_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA2_Channel1_IRQHandler
|
|
||||||
B DMA2_Channel1_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA2_Channel2_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA2_Channel2_IRQHandler
|
|
||||||
B DMA2_Channel2_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA2_Channel3_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA2_Channel3_IRQHandler
|
|
||||||
B DMA2_Channel3_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA2_Channel4_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA2_Channel4_IRQHandler
|
|
||||||
B DMA2_Channel4_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA2_Channel5_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA2_Channel5_IRQHandler
|
|
||||||
B DMA2_Channel5_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA2_Channel6_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA2_Channel6_IRQHandler
|
|
||||||
B DMA2_Channel6_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA2_Channel7_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMA2_Channel7_IRQHandler
|
|
||||||
B DMA2_Channel7_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMAMUX1_OVR_IRQHandler
|
|
||||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
|
||||||
DMAMUX1_OVR_IRQHandler
|
|
||||||
B DMAMUX1_OVR_IRQHandler
|
|
||||||
|
|
||||||
END
|
|
||||||
|
|
||||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
|
||||||
|
|
@ -1,359 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file system_stm32wlxx.c
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief CMSIS Cortex Device Peripheral Access Layer System Source File
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* Copyright (c) 2020(-2021) STMicroelectronics.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* This software is licensed under terms that can be found in the LICENSE file
|
|
||||||
* in the root directory of this software component.
|
|
||||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
* This file provides two functions and one global variable to be called from
|
|
||||||
* user application:
|
|
||||||
* - SystemInit(): This function is called at startup just after reset and
|
|
||||||
* before branch to main program. This call is made inside
|
|
||||||
* the "startup_stm32wlxx.s" file.
|
|
||||||
*
|
|
||||||
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
|
|
||||||
* by the user application to setup the SysTick
|
|
||||||
* timer or configure other parameters.
|
|
||||||
*
|
|
||||||
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
|
|
||||||
* be called whenever the core clock is changed
|
|
||||||
* during program execution.
|
|
||||||
*
|
|
||||||
* After each device reset the MSI (4 MHz) is used as system clock source.
|
|
||||||
* Then SystemInit() function is called, in "startup_stm32wlxx.s" file, to
|
|
||||||
* configure the system clock before to branch to main program.
|
|
||||||
*
|
|
||||||
* This file configures the system clock as follows:
|
|
||||||
*=============================================================================
|
|
||||||
*-----------------------------------------------------------------------------
|
|
||||||
* System Clock source | MSI
|
|
||||||
*-----------------------------------------------------------------------------
|
|
||||||
* SYSCLK(Hz) | 4000000
|
|
||||||
*-----------------------------------------------------------------------------
|
|
||||||
* HCLK(Hz) | 4000000
|
|
||||||
*-----------------------------------------------------------------------------
|
|
||||||
* AHB Prescaler | 1
|
|
||||||
*-----------------------------------------------------------------------------
|
|
||||||
* APB1 Prescaler | 1
|
|
||||||
*-----------------------------------------------------------------------------
|
|
||||||
* APB2 Prescaler | 1
|
|
||||||
*-----------------------------------------------------------------------------
|
|
||||||
* PLL_M | 1
|
|
||||||
*-----------------------------------------------------------------------------
|
|
||||||
* PLL_N | 8
|
|
||||||
*-----------------------------------------------------------------------------
|
|
||||||
* PLL_P | 7
|
|
||||||
*-----------------------------------------------------------------------------
|
|
||||||
* PLL_Q | 2
|
|
||||||
*-----------------------------------------------------------------------------
|
|
||||||
* PLL_R | 2
|
|
||||||
*-----------------------------------------------------------------------------
|
|
||||||
* PLLSAI1_P | NA
|
|
||||||
*-----------------------------------------------------------------------------
|
|
||||||
* PLLSAI1_Q | NA
|
|
||||||
*-----------------------------------------------------------------------------
|
|
||||||
* PLLSAI1_R | NA
|
|
||||||
*-----------------------------------------------------------------------------
|
|
||||||
* Require 48MHz for USB OTG FS, | Disabled
|
|
||||||
* SDIO and RNG clock |
|
|
||||||
*-----------------------------------------------------------------------------
|
|
||||||
*=============================================================================
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup CMSIS
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup stm32WLxx_system
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup stm32WLxx_System_Private_Includes
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include "stm32wlxx.h"
|
|
||||||
|
|
||||||
#if !defined (HSE_VALUE)
|
|
||||||
#define HSE_VALUE (32000000UL) /*!< Value of the External oscillator in Hz */
|
|
||||||
#endif /* HSE_VALUE */
|
|
||||||
|
|
||||||
#if !defined (MSI_VALUE)
|
|
||||||
#define MSI_VALUE (4000000UL) /*!< Value of the Internal oscillator in Hz*/
|
|
||||||
#endif /* MSI_VALUE */
|
|
||||||
|
|
||||||
#if !defined (HSI_VALUE)
|
|
||||||
#define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/
|
|
||||||
#endif /* HSI_VALUE */
|
|
||||||
|
|
||||||
#if !defined (LSI_VALUE)
|
|
||||||
#define LSI_VALUE (32000UL) /*!< Value of LSI in Hz*/
|
|
||||||
#endif /* LSI_VALUE */
|
|
||||||
|
|
||||||
#if !defined (LSE_VALUE)
|
|
||||||
#define LSE_VALUE (32768UL) /*!< Value of LSE in Hz*/
|
|
||||||
#endif /* LSE_VALUE */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup STM32WLxx_System_Private_TypesDefinitions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup STM32WLxx_System_Private_Defines
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Note: Following vector table addresses must be defined in line with linker
|
|
||||||
configuration. */
|
|
||||||
/*!< Uncomment the following line if you need to relocate CPU1 CM4 and/or CPU2
|
|
||||||
CM0+ vector table anywhere in Sram or Flash. Else vector table will be kept
|
|
||||||
at address 0x00 which correspond to automatic remap of boot address selected */
|
|
||||||
/* #define USER_VECT_TAB_ADDRESS */
|
|
||||||
#if defined(USER_VECT_TAB_ADDRESS)
|
|
||||||
#ifdef CORE_CM0PLUS
|
|
||||||
/*!< Uncomment this line for user vector table remap in Sram else user remap
|
|
||||||
will be done in Flash. */
|
|
||||||
/* #define VECT_TAB_SRAM */
|
|
||||||
#if defined(VECT_TAB_SRAM)
|
|
||||||
#define VECT_TAB_BASE_ADDRESS SRAM2_BASE /*!< Vector Table base address field.
|
|
||||||
This value must be a multiple of 0x100. */
|
|
||||||
#define VECT_TAB_OFFSET 0x00008000U /*!< Vector Table base offset field.
|
|
||||||
This value must be a multiple of 0x100. */
|
|
||||||
#else
|
|
||||||
#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
|
|
||||||
This value must be a multiple of 0x100. */
|
|
||||||
#define VECT_TAB_OFFSET 0x00020000U /*!< Vector Table base offset field.
|
|
||||||
This value must be a multiple of 0x100. */
|
|
||||||
#endif
|
|
||||||
#else /* CORE_CM4 */
|
|
||||||
/*!< Uncomment this line for user vector table remap in Sram else user remap
|
|
||||||
will be done in Flash. */
|
|
||||||
/* #define VECT_TAB_SRAM */
|
|
||||||
#if defined(VECT_TAB_SRAM)
|
|
||||||
#define VECT_TAB_BASE_ADDRESS SRAM1_BASE /*!< Vector Table base address field.
|
|
||||||
This value must be a multiple of 0x200. */
|
|
||||||
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
|
|
||||||
This value must be a multiple of 0x200. */
|
|
||||||
#else
|
|
||||||
#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
|
|
||||||
This value must be a multiple of 0x200. */
|
|
||||||
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
|
|
||||||
This value must be a multiple of 0x200. */
|
|
||||||
#endif
|
|
||||||
#endif
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup STM32WLxx_System_Private_Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup STM32WLxx_System_Private_Variables
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* The SystemCoreClock variable is updated in three ways:
|
|
||||||
1) from within HAL_Init()
|
|
||||||
2) by calling CMSIS function SystemCoreClockUpdate()
|
|
||||||
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
|
|
||||||
*/
|
|
||||||
uint32_t SystemCoreClock = 4000000UL; /*CPU1: M4 on MSI clock after startup (4MHz)*/
|
|
||||||
|
|
||||||
const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
|
|
||||||
|
|
||||||
const uint32_t APBPrescTable[8UL] = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
|
|
||||||
|
|
||||||
const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
|
|
||||||
4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup STM32WLxx_System_Private_FunctionPrototypes
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup STM32WLxx_System_Private_Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Setup the microcontroller system.
|
|
||||||
* @param None
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void SystemInit(void)
|
|
||||||
{
|
|
||||||
#if defined(USER_VECT_TAB_ADDRESS)
|
|
||||||
/* Configure the Vector Table location add offset address ------------------*/
|
|
||||||
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* FPU settings ------------------------------------------------------------*/
|
|
||||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
|
||||||
SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL))); /* set CP10 and CP11 Full Access */
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
|
||||||
* The SystemCoreClock variable contains the core clock (HCLK), it can
|
|
||||||
* be used by the user application to setup the SysTick timer or configure
|
|
||||||
* other parameters.
|
|
||||||
*
|
|
||||||
* @note Each time the core clock (HCLK) changes, this function must be called
|
|
||||||
* to update SystemCoreClock variable value. Otherwise, any configuration
|
|
||||||
* based on this variable will be incorrect.
|
|
||||||
*
|
|
||||||
* @note - The system frequency computed by this function is not the real
|
|
||||||
* frequency in the chip. It is calculated based on the predefined
|
|
||||||
* constant and the selected clock source:
|
|
||||||
*
|
|
||||||
* - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
|
|
||||||
*
|
|
||||||
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
|
|
||||||
*
|
|
||||||
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
|
|
||||||
*
|
|
||||||
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
|
|
||||||
* or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
|
|
||||||
*
|
|
||||||
* (*) MSI_VALUE is a constant defined in stm32wlxx_hal.h file (default value
|
|
||||||
* 4 MHz) but the real value may vary depending on the variations
|
|
||||||
* in voltage and temperature.
|
|
||||||
*
|
|
||||||
* (**) HSI_VALUE is a constant defined in stm32wlxx_hal_conf.h file (default value
|
|
||||||
* 16 MHz) but the real value may vary depending on the variations
|
|
||||||
* in voltage and temperature.
|
|
||||||
*
|
|
||||||
* (***) HSE_VALUE is a constant defined in stm32wlxx_hal_conf.h file (default value
|
|
||||||
* 32 MHz), user has to ensure that HSE_VALUE is same as the real
|
|
||||||
* frequency of the crystal used. Otherwise, this function may
|
|
||||||
* have wrong result.
|
|
||||||
*
|
|
||||||
* - The result of this function could be not correct when using fractional
|
|
||||||
* value for HSE crystal.
|
|
||||||
*
|
|
||||||
* @param None
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void SystemCoreClockUpdate(void)
|
|
||||||
{
|
|
||||||
uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
|
|
||||||
|
|
||||||
/* Get MSI Range frequency--------------------------------------------------*/
|
|
||||||
|
|
||||||
/* Get MSI Range frequency--------------------------------------------------*/
|
|
||||||
if((RCC->CR & RCC_CR_MSIRGSEL) == 0U)
|
|
||||||
{ /* MSISRANGE from RCC_CSR applies */
|
|
||||||
msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{ /* MSIRANGE from RCC_CR applies */
|
|
||||||
msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U;
|
|
||||||
}
|
|
||||||
/*MSI frequency range in HZ*/
|
|
||||||
msirange = MSIRangeTable[msirange];
|
|
||||||
|
|
||||||
|
|
||||||
/*SystemCoreClock=HAL_RCC_GetSysClockFreq();*/
|
|
||||||
/* Get SYSCLK source -------------------------------------------------------*/
|
|
||||||
switch (RCC->CFGR & RCC_CFGR_SWS)
|
|
||||||
{
|
|
||||||
case 0x00: /* MSI used as system clock source */
|
|
||||||
SystemCoreClock = msirange;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case 0x04: /* HSI used as system clock source */
|
|
||||||
/* HSI used as system clock source */
|
|
||||||
SystemCoreClock = HSI_VALUE;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case 0x08: /* HSE used as system clock source */
|
|
||||||
SystemCoreClock = HSE_VALUE;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case 0x0C: /* PLL used as system clock source */
|
|
||||||
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
|
|
||||||
SYSCLK = PLL_VCO / PLLR
|
|
||||||
*/
|
|
||||||
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
|
|
||||||
pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
|
|
||||||
|
|
||||||
switch (pllsource)
|
|
||||||
{
|
|
||||||
case 0x02: /* HSI used as PLL clock source */
|
|
||||||
pllvco = (HSI_VALUE / pllm);
|
|
||||||
break;
|
|
||||||
|
|
||||||
case 0x03: /* HSE used as PLL clock source */
|
|
||||||
pllvco = (HSE_VALUE / pllm);
|
|
||||||
break;
|
|
||||||
|
|
||||||
default: /* MSI used as PLL clock source */
|
|
||||||
pllvco = (msirange / pllm);
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
|
|
||||||
pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
|
|
||||||
|
|
||||||
SystemCoreClock = pllvco/pllr;
|
|
||||||
break;
|
|
||||||
|
|
||||||
default:
|
|
||||||
SystemCoreClock = msirange;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Compute HCLK clock frequency --------------------------------------------*/
|
|
||||||
#if defined(DUAL_CORE) && defined(CORE_CM0PLUS)
|
|
||||||
/* Get HCLK2 prescaler */
|
|
||||||
tmp = AHBPrescTable[((RCC->EXTCFGR & RCC_EXTCFGR_C2HPRE) >> RCC_EXTCFGR_C2HPRE_Pos)];
|
|
||||||
#else
|
|
||||||
/* Get HCLK1 prescaler */
|
|
||||||
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Core clock frequency */
|
|
||||||
SystemCoreClock = SystemCoreClock / tmp;
|
|
||||||
}
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,77 +0,0 @@
|
||||||
import rtconfig
|
|
||||||
from building import *
|
|
||||||
|
|
||||||
# get current directory
|
|
||||||
cwd = GetCurrentDir()
|
|
||||||
|
|
||||||
# The set of source files associated with this SConscript file.
|
|
||||||
|
|
||||||
src = Split('''
|
|
||||||
CMSIS/Device/ST/STM32WLxx/Source/Templates/system_stm32wlxx.c
|
|
||||||
STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c
|
|
||||||
STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_comp.c
|
|
||||||
STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c
|
|
||||||
STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_crc.c
|
|
||||||
STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_crc_ex.c
|
|
||||||
STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cryp.c
|
|
||||||
STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cryp_ex.c
|
|
||||||
STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c
|
|
||||||
STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.c
|
|
||||||
STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c
|
|
||||||
STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c
|
|
||||||
STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c
|
|
||||||
STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c
|
|
||||||
STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c
|
|
||||||
STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rng.c
|
|
||||||
STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c
|
|
||||||
''')
|
|
||||||
|
|
||||||
if GetDepend(['RT_USING_SERIAL']) or GetDepend(['RT_USING_NANO', 'RT_USING_CONSOLE']):
|
|
||||||
src += ['STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c']
|
|
||||||
src += ['STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c']
|
|
||||||
src += ['STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_usart.c']
|
|
||||||
src += ['STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_usart_ex.c']
|
|
||||||
|
|
||||||
if GetDepend(['RT_USING_I2C']):
|
|
||||||
src += ['STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_i2c.c']
|
|
||||||
src += ['STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_i2c_ex.c']
|
|
||||||
|
|
||||||
if GetDepend(['RT_USING_SPI']):
|
|
||||||
src += ['STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_spi.c']
|
|
||||||
src += ['STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_spi_ex.c']
|
|
||||||
|
|
||||||
if GetDepend(['RT_USING_HWTIMER']) or GetDepend(['RT_USING_PWM']):
|
|
||||||
src += ['STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_lptim.c']
|
|
||||||
src += ['STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim.c']
|
|
||||||
src += ['STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim_ex.c']
|
|
||||||
|
|
||||||
if GetDepend(['RT_USING_ADC']):
|
|
||||||
src += ['STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c']
|
|
||||||
src += ['STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc_ex.c']
|
|
||||||
|
|
||||||
if GetDepend(['BSP_USING_ONCHIP_RTC']):
|
|
||||||
src += ['STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c']
|
|
||||||
src += ['STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c']
|
|
||||||
|
|
||||||
if GetDepend(['RT_USING_WDT']):
|
|
||||||
src += ['STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_iwdg.c']
|
|
||||||
src += ['STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_wwdg.c']
|
|
||||||
|
|
||||||
if GetDepend(['RT_USING_PM']):
|
|
||||||
src += ['STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_lptim.c']
|
|
||||||
|
|
||||||
if GetDepend(['BSP_USING_ON_CHIP_FLASH']):
|
|
||||||
src += ['STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c']
|
|
||||||
src += ['STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c']
|
|
||||||
src += ['STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ramfunc.c']
|
|
||||||
|
|
||||||
if GetDepend(['BSP_USING_SUBGHZ']):
|
|
||||||
src += ['STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c']
|
|
||||||
|
|
||||||
path = [cwd + '/STM32WLxx_HAL_Driver/Inc',
|
|
||||||
cwd + '/CMSIS/Device/ST/STM32WLxx/Include']
|
|
||||||
|
|
||||||
CPPDEFINES = ['USE_HAL_DRIVER']
|
|
||||||
group = DefineGroup('STM32_HAL', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
|
|
||||||
|
|
||||||
Return('group')
|
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,57 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32_assert.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief STM32 assert template file.
|
|
||||||
* This file should be copied to the application folder and renamed
|
|
||||||
* to stm32_assert.h.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
|
||||||
* All rights reserved.</center></h2>
|
|
||||||
*
|
|
||||||
* This software component is licensed by ST under BSD 3-Clause license,
|
|
||||||
* the "License"; You may not use this file except in compliance with the
|
|
||||||
* License. You may obtain a copy of the License at:
|
|
||||||
* opensource.org/licenses/BSD-3-Clause
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef __STM32_ASSERT_H
|
|
||||||
#define __STM32_ASSERT_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
/* Exported macro ------------------------------------------------------------*/
|
|
||||||
#ifdef USE_FULL_ASSERT
|
|
||||||
/**
|
|
||||||
* @brief The assert_param macro is used for function's parameters check.
|
|
||||||
* @param expr If expr is false, it calls assert_failed function
|
|
||||||
* which reports the name of the source file and the source
|
|
||||||
* line number of the call that failed.
|
|
||||||
* If expr is true, it returns no value.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
|
|
||||||
/* Exported functions ------------------------------------------------------- */
|
|
||||||
void assert_failed(uint8_t* file, uint32_t line);
|
|
||||||
#else
|
|
||||||
#define assert_param(expr) ((void)0U)
|
|
||||||
#endif /* USE_FULL_ASSERT */
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* __STM32_ASSERT_H */
|
|
||||||
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,796 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32wlxx_hal.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief This file contains all the functions prototypes for the HAL
|
|
||||||
* module driver.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
|
||||||
* All rights reserved.</center></h2>
|
|
||||||
*
|
|
||||||
* This software component is licensed by ST under BSD 3-Clause license,
|
|
||||||
* the "License"; You may not use this file except in compliance with the
|
|
||||||
* License. You may obtain a copy of the License at:
|
|
||||||
* opensource.org/licenses/BSD-3-Clause
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef __STM32WLxx_HAL_H
|
|
||||||
#define __STM32WLxx_HAL_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32wlxx_hal_conf.h"
|
|
||||||
#include "stm32wlxx_ll_system.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32WLxx_HAL_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup HAL HAL
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
/** @defgroup HAL_Exported_Structures HAL Exported Structures
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup HAL_TICK_FREQ Tick Frequency
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
HAL_TICK_FREQ_10HZ = 100U,
|
|
||||||
HAL_TICK_FREQ_100HZ = 10U,
|
|
||||||
HAL_TICK_FREQ_1KHZ = 1U,
|
|
||||||
HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
|
|
||||||
} HAL_TickFreqTypeDef;
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#if defined(DUAL_CORE)
|
|
||||||
/** @defgroup HAL_SYSCFG_IM HAL SYSCFG Interrupt Mask
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/**
|
|
||||||
* @brief SYSCFG Interrupt Mask structure definition
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t InterruptMask1; /*!< The SYSCFG Interrupt Mask to be configured.
|
|
||||||
This parameter can be a combination of @ref SYSCFG_IM_GRP1 */
|
|
||||||
uint32_t InterruptMask2; /*!< The SYSCFG Interrupt Mask to be configured.
|
|
||||||
This parameter can be a combination of @ref SYSCFG_IM_GRP2 */
|
|
||||||
} SYSCFG_InterruptTypeDef;
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
|
||||||
/** @defgroup HAL_Exported_Constants HAL Exported Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SYSCFG_BootMode BOOT Mode
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SYSCFG_BOOT_MAINFLASH LL_SYSCFG_REMAP_FLASH /*!< Main Flash memory mapped at 0x00000000 */
|
|
||||||
#define SYSCFG_BOOT_SYSTEMFLASH LL_SYSCFG_REMAP_SYSTEMFLASH /*!< System Flash memory mapped at 0x00000000 */
|
|
||||||
#define SYSCFG_BOOT_SRAM LL_SYSCFG_REMAP_SRAM /*!< SRAM1 mapped at 0x00000000 */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SYSCFG_SRAM2WRP SRAM2 Page Write protection (0 to 31)
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SYSCFG_SRAM2WRP_PAGE0 LL_SYSCFG_SRAM2WRP_PAGE0 /*!< SRAM2 Write protection page 0 */
|
|
||||||
#define SYSCFG_SRAM2WRP_PAGE1 LL_SYSCFG_SRAM2WRP_PAGE1 /*!< SRAM2 Write protection page 1 */
|
|
||||||
#define SYSCFG_SRAM2WRP_PAGE2 LL_SYSCFG_SRAM2WRP_PAGE2 /*!< SRAM2 Write protection page 2 */
|
|
||||||
#define SYSCFG_SRAM2WRP_PAGE3 LL_SYSCFG_SRAM2WRP_PAGE3 /*!< SRAM2 Write protection page 3 */
|
|
||||||
#define SYSCFG_SRAM2WRP_PAGE4 LL_SYSCFG_SRAM2WRP_PAGE4 /*!< SRAM2 Write protection page 4 */
|
|
||||||
#define SYSCFG_SRAM2WRP_PAGE5 LL_SYSCFG_SRAM2WRP_PAGE5 /*!< SRAM2 Write protection page 5 */
|
|
||||||
#define SYSCFG_SRAM2WRP_PAGE6 LL_SYSCFG_SRAM2WRP_PAGE6 /*!< SRAM2 Write protection page 6 */
|
|
||||||
#define SYSCFG_SRAM2WRP_PAGE7 LL_SYSCFG_SRAM2WRP_PAGE7 /*!< SRAM2 Write protection page 7 */
|
|
||||||
#define SYSCFG_SRAM2WRP_PAGE8 LL_SYSCFG_SRAM2WRP_PAGE8 /*!< SRAM2 Write protection page 8 */
|
|
||||||
#define SYSCFG_SRAM2WRP_PAGE9 LL_SYSCFG_SRAM2WRP_PAGE9 /*!< SRAM2 Write protection page 9 */
|
|
||||||
#define SYSCFG_SRAM2WRP_PAGE10 LL_SYSCFG_SRAM2WRP_PAGE10 /*!< SRAM2 Write protection page 10 */
|
|
||||||
#define SYSCFG_SRAM2WRP_PAGE11 LL_SYSCFG_SRAM2WRP_PAGE11 /*!< SRAM2 Write protection page 11 */
|
|
||||||
#define SYSCFG_SRAM2WRP_PAGE12 LL_SYSCFG_SRAM2WRP_PAGE12 /*!< SRAM2 Write protection page 12 */
|
|
||||||
#define SYSCFG_SRAM2WRP_PAGE13 LL_SYSCFG_SRAM2WRP_PAGE13 /*!< SRAM2 Write protection page 13 */
|
|
||||||
#define SYSCFG_SRAM2WRP_PAGE14 LL_SYSCFG_SRAM2WRP_PAGE14 /*!< SRAM2 Write protection page 14 */
|
|
||||||
#define SYSCFG_SRAM2WRP_PAGE15 LL_SYSCFG_SRAM2WRP_PAGE15 /*!< SRAM2 Write protection page 15 */
|
|
||||||
#define SYSCFG_SRAM2WRP_PAGE16 LL_SYSCFG_SRAM2WRP_PAGE16 /*!< SRAM2 Write protection page 16 */
|
|
||||||
#define SYSCFG_SRAM2WRP_PAGE17 LL_SYSCFG_SRAM2WRP_PAGE17 /*!< SRAM2 Write protection page 17 */
|
|
||||||
#define SYSCFG_SRAM2WRP_PAGE18 LL_SYSCFG_SRAM2WRP_PAGE18 /*!< SRAM2 Write protection page 18 */
|
|
||||||
#define SYSCFG_SRAM2WRP_PAGE19 LL_SYSCFG_SRAM2WRP_PAGE19 /*!< SRAM2 Write protection page 19 */
|
|
||||||
#define SYSCFG_SRAM2WRP_PAGE20 LL_SYSCFG_SRAM2WRP_PAGE20 /*!< SRAM2 Write protection page 20 */
|
|
||||||
#define SYSCFG_SRAM2WRP_PAGE21 LL_SYSCFG_SRAM2WRP_PAGE21 /*!< SRAM2 Write protection page 21 */
|
|
||||||
#define SYSCFG_SRAM2WRP_PAGE22 LL_SYSCFG_SRAM2WRP_PAGE22 /*!< SRAM2 Write protection page 22 */
|
|
||||||
#define SYSCFG_SRAM2WRP_PAGE23 LL_SYSCFG_SRAM2WRP_PAGE23 /*!< SRAM2 Write protection page 23 */
|
|
||||||
#define SYSCFG_SRAM2WRP_PAGE24 LL_SYSCFG_SRAM2WRP_PAGE24 /*!< SRAM2 Write protection page 24 */
|
|
||||||
#define SYSCFG_SRAM2WRP_PAGE25 LL_SYSCFG_SRAM2WRP_PAGE25 /*!< SRAM2 Write protection page 25 */
|
|
||||||
#define SYSCFG_SRAM2WRP_PAGE26 LL_SYSCFG_SRAM2WRP_PAGE26 /*!< SRAM2 Write protection page 26 */
|
|
||||||
#define SYSCFG_SRAM2WRP_PAGE27 LL_SYSCFG_SRAM2WRP_PAGE27 /*!< SRAM2 Write protection page 27 */
|
|
||||||
#define SYSCFG_SRAM2WRP_PAGE28 LL_SYSCFG_SRAM2WRP_PAGE28 /*!< SRAM2 Write protection page 28 */
|
|
||||||
#define SYSCFG_SRAM2WRP_PAGE29 LL_SYSCFG_SRAM2WRP_PAGE29 /*!< SRAM2 Write protection page 29 */
|
|
||||||
#define SYSCFG_SRAM2WRP_PAGE30 LL_SYSCFG_SRAM2WRP_PAGE30 /*!< SRAM2 Write protection page 30 */
|
|
||||||
#define SYSCFG_SRAM2WRP_PAGE31 LL_SYSCFG_SRAM2WRP_PAGE31 /*!< SRAM2 Write protection page 31 */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#if defined(VREFBUF)
|
|
||||||
/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 LL_VREFBUF_VOLTAGE_SCALE0 /*!< Voltage reference scale 0 (VREF_OUT1) */
|
|
||||||
#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 LL_VREFBUF_VOLTAGE_SCALE1 /*!< Voltage reference scale 1 (VREF_OUT2) */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE 0x00000000U /*!< VREF_plus pin is internally connected to Voltage reference buffer output */
|
|
||||||
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
#endif /* VREFBUF */
|
|
||||||
|
|
||||||
/** @defgroup SYSCFG_SRAM_flags_definition SRAM Flags
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define SYSCFG_FLAG_SRAM2_PE SYSCFG_CFGR2_SPF /*!< SRAM2 parity error */
|
|
||||||
#define SYSCFG_FLAG_SRAM_BUSY SYSCFG_SCSR_SRAMBSY /*!< SRAM1 or SRAM2 erase operation is ongoing */
|
|
||||||
#define SYSCFG_FLAG_PKASRAM_BUSY SYSCFG_SCSR_PKASRAMBSY /*!< PKA SRAM busy by erase operation */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @brief Fast-mode Plus driving capability on a specific GPIO
|
|
||||||
*/
|
|
||||||
#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */
|
|
||||||
#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */
|
|
||||||
#define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */
|
|
||||||
#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#if defined(DUAL_CORE)
|
|
||||||
/** @defgroup SYSCFG_IM_GRP1 SYSCFG INTERRUPT MASK GROUP1
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define HAL_SYSCFG_GRP1_RESERVED 0x00U /*!< Define user to differentiate Group1 to Group 2 */
|
|
||||||
|
|
||||||
#if defined(CORE_CM0PLUS)
|
|
||||||
/** @brief Interrupt mask related to CPU2 NVIC
|
|
||||||
*/
|
|
||||||
#define HAL_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS (LL_C2_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from RTC TimeStamp, RTC Tampers
|
|
||||||
and LSE Clock Security System to CPU2 */
|
|
||||||
#define HAL_SYSCFG_GRP1_RTCALARM (LL_C2_SYSCFG_GRP1_RTCALARM | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from RTC Alarms to CPU2 */
|
|
||||||
#define HAL_SYSCFG_GRP1_RTCSSRU (LL_C2_SYSCFG_GRP1_RTCSSRU | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from RTC SSRU to CPU2 */
|
|
||||||
#define HAL_SYSCFG_GRP1_RTCWKUP (LL_C2_SYSCFG_GRP1_RTCWKUP | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from RTC Wakeup to CPU2 */
|
|
||||||
#define HAL_SYSCFG_GRP1_RCC (LL_C2_SYSCFG_GRP1_RCC | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from RCC to CPU2 */
|
|
||||||
#define HAL_SYSCFG_GRP1_FLASH (LL_C2_SYSCFG_GRP1_FLASH | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from FLASH to CPU2 */
|
|
||||||
#define HAL_SYSCFG_GRP1_PKA (LL_C2_SYSCFG_GRP1_PKA | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from PKA to CPU2 */
|
|
||||||
#define HAL_SYSCFG_GRP1_AES (LL_C2_SYSCFG_GRP1_AES | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from AES to CPU2 */
|
|
||||||
#define HAL_SYSCFG_GRP1_COMP (LL_C2_SYSCFG_GRP1_COMP | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from Comparator to CPU2 */
|
|
||||||
#define HAL_SYSCFG_GRP1_ADC (LL_C2_SYSCFG_GRP1_ADC | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from Analog Digital Converter to CPU2 */
|
|
||||||
#define HAL_SYSCFG_GRP1_DAC (LL_C2_SYSCFG_GRP1_DAC | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from Digital Analog Converter to CPU2 */
|
|
||||||
|
|
||||||
#define HAL_SYSCFG_GRP1_EXTI0 (LL_C2_SYSCFG_GRP1_EXTI0 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 0 to CPU2 */
|
|
||||||
#define HAL_SYSCFG_GRP1_EXTI1 (LL_C2_SYSCFG_GRP1_EXTI1 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 1 to CPU2 */
|
|
||||||
#define HAL_SYSCFG_GRP1_EXTI2 (LL_C2_SYSCFG_GRP1_EXTI2 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 2 to CPU2 */
|
|
||||||
#define HAL_SYSCFG_GRP1_EXTI3 (LL_C2_SYSCFG_GRP1_EXTI3 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 3 to CPU2 */
|
|
||||||
#define HAL_SYSCFG_GRP1_EXTI4 (LL_C2_SYSCFG_GRP1_EXTI4 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 4 to CPU2 */
|
|
||||||
#define HAL_SYSCFG_GRP1_EXTI5 (LL_C2_SYSCFG_GRP1_EXTI5 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 5 to CPU2 */
|
|
||||||
#define HAL_SYSCFG_GRP1_EXTI6 (LL_C2_SYSCFG_GRP1_EXTI6 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 6 to CPU2 */
|
|
||||||
#define HAL_SYSCFG_GRP1_EXTI7 (LL_C2_SYSCFG_GRP1_EXTI7 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 7 to CPU2 */
|
|
||||||
#define HAL_SYSCFG_GRP1_EXTI8 (LL_C2_SYSCFG_GRP1_EXTI8 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 8 to CPU2 */
|
|
||||||
#define HAL_SYSCFG_GRP1_EXTI9 (LL_C2_SYSCFG_GRP1_EXTI9 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 9 to CPU2 */
|
|
||||||
#define HAL_SYSCFG_GRP1_EXTI10 (LL_C2_SYSCFG_GRP1_EXTI10 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 10 to CPU2 */
|
|
||||||
#define HAL_SYSCFG_GRP1_EXTI11 (LL_C2_SYSCFG_GRP1_EXTI11 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 11 to CPU2 */
|
|
||||||
#define HAL_SYSCFG_GRP1_EXTI12 (LL_C2_SYSCFG_GRP1_EXTI12 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 12 to CPU2 */
|
|
||||||
#define HAL_SYSCFG_GRP1_EXTI13 (LL_C2_SYSCFG_GRP1_EXTI13 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 13 to CPU2 */
|
|
||||||
#define HAL_SYSCFG_GRP1_EXTI14 (LL_C2_SYSCFG_GRP1_EXTI14 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 14 to CPU2 */
|
|
||||||
#define HAL_SYSCFG_GRP1_EXTI15 (LL_C2_SYSCFG_GRP1_EXTI15 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 15 to CPU2 */
|
|
||||||
|
|
||||||
#else
|
|
||||||
|
|
||||||
/** @brief Interrupt mask related to CPU1 NVIC
|
|
||||||
*/
|
|
||||||
#define HAL_SYSCFG_GRP1_RTCSTAMPTAMPLSECSS (LL_SYSCFG_GRP1_RTCSTAMPTAMPLSECSS | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from RTCSTAMPTAMPLSECSS to CPU1 */
|
|
||||||
#define HAL_SYSCFG_GRP1_RTCSSRU (LL_SYSCFG_GRP1_RTCSSRU | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from RTC SSRU to CPU1 */
|
|
||||||
#define HAL_SYSCFG_GRP1_EXTI5 (LL_SYSCFG_GRP1_EXTI5 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 5 to CPU1 */
|
|
||||||
#define HAL_SYSCFG_GRP1_EXTI6 (LL_SYSCFG_GRP1_EXTI6 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 6 to CPU1 */
|
|
||||||
#define HAL_SYSCFG_GRP1_EXTI7 (LL_SYSCFG_GRP1_EXTI7 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 7 to CPU1 */
|
|
||||||
#define HAL_SYSCFG_GRP1_EXTI8 (LL_SYSCFG_GRP1_EXTI8 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 8 to CPU1 */
|
|
||||||
#define HAL_SYSCFG_GRP1_EXTI9 (LL_SYSCFG_GRP1_EXTI9 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 9 to CPU1 */
|
|
||||||
#define HAL_SYSCFG_GRP1_EXTI10 (LL_SYSCFG_GRP1_EXTI10 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 10 to CPU1 */
|
|
||||||
#define HAL_SYSCFG_GRP1_EXTI11 (LL_SYSCFG_GRP1_EXTI11 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 11 to CPU1 */
|
|
||||||
#define HAL_SYSCFG_GRP1_EXTI12 (LL_SYSCFG_GRP1_EXTI12 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 12 to CPU1 */
|
|
||||||
#define HAL_SYSCFG_GRP1_EXTI13 (LL_SYSCFG_GRP1_EXTI13 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 13 to CPU1 */
|
|
||||||
#define HAL_SYSCFG_GRP1_EXTI14 (LL_SYSCFG_GRP1_EXTI14 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 14 to CPU1 */
|
|
||||||
#define HAL_SYSCFG_GRP1_EXTI15 (LL_SYSCFG_GRP1_EXTI15 | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 15 to CPU1 */
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SYSCFG_IM_GRP2 SYSCFG INTERRUPT MASK GROUP2
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define HAL_SYSCFG_GRP2_RESERVED 0x80U /*!< Define user to differentiate Group1 to Group 2 */
|
|
||||||
|
|
||||||
#if defined(CORE_CM0PLUS)
|
|
||||||
/** @brief Interrupt mask related to CPU2 NVIC
|
|
||||||
*/
|
|
||||||
#define HAL_SYSCFG_GRP2_DMA1CH1 (LL_C2_SYSCFG_GRP2_DMA1CH1 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA1 Channel 1 to CPU2 */
|
|
||||||
#define HAL_SYSCFG_GRP2_DMA1CH2 (LL_C2_SYSCFG_GRP2_DMA1CH2 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA1 Channel 2 to CPU2 */
|
|
||||||
#define HAL_SYSCFG_GRP2_DMA1CH3 (LL_C2_SYSCFG_GRP2_DMA1CH3 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA1 Channel 3 to CPU2 */
|
|
||||||
#define HAL_SYSCFG_GRP2_DMA1CH4 (LL_C2_SYSCFG_GRP2_DMA1CH4 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA1 Channel 4 to CPU2 */
|
|
||||||
#define HAL_SYSCFG_GRP2_DMA1CH5 (LL_C2_SYSCFG_GRP2_DMA1CH5 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA1 Channel 5 to CPU2 */
|
|
||||||
#define HAL_SYSCFG_GRP2_DMA1CH6 (LL_C2_SYSCFG_GRP2_DMA1CH6 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA1 Channel 6 to CPU2 */
|
|
||||||
#define HAL_SYSCFG_GRP2_DMA1CH7 (LL_C2_SYSCFG_GRP2_DMA1CH7 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA1 Channel 7 to CPU2 */
|
|
||||||
|
|
||||||
#define HAL_SYSCFG_GRP2_DMA2CH1 (LL_C2_SYSCFG_GRP2_DMA2CH1 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA2 Channel 1 to CPU2 */
|
|
||||||
#define HAL_SYSCFG_GRP2_DMA2CH2 (LL_C2_SYSCFG_GRP2_DMA2CH2 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA2 Channel 2 to CPU2 */
|
|
||||||
#define HAL_SYSCFG_GRP2_DMA2CH3 (LL_C2_SYSCFG_GRP2_DMA2CH3 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA2 Channel 3 to CPU2 */
|
|
||||||
#define HAL_SYSCFG_GRP2_DMA2CH4 (LL_C2_SYSCFG_GRP2_DMA2CH4 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA2 Channel 4 to CPU2 */
|
|
||||||
#define HAL_SYSCFG_GRP2_DMA2CH5 (LL_C2_SYSCFG_GRP2_DMA2CH5 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA2 Channel 5 to CPU2 */
|
|
||||||
#define HAL_SYSCFG_GRP2_DMA2CH6 (LL_C2_SYSCFG_GRP2_DMA2CH6 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA2 Channel 6 to CPU2 */
|
|
||||||
#define HAL_SYSCFG_GRP2_DMA2CH7 (LL_C2_SYSCFG_GRP2_DMA2CH7 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA2 Channel 7 to CPU2 */
|
|
||||||
|
|
||||||
#define HAL_SYSCFG_GRP2_DMAMUX1 (LL_C2_SYSCFG_GRP2_DMAMUX1 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMAMUX1 to CPU2 */
|
|
||||||
|
|
||||||
#define HAL_SYSCFG_GRP2_PVM3 (LL_C2_SYSCFG_GRP2_PVM3 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from Power Voltage Monitoring 3 to CPU2 */
|
|
||||||
#define HAL_SYSCFG_GRP2_PVD (LL_C2_SYSCFG_GRP2_PVD | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from Power Voltage Detector to CPU2 */
|
|
||||||
|
|
||||||
#else
|
|
||||||
|
|
||||||
/** @brief Interrupt mask related to CPU1 NVIC
|
|
||||||
*/
|
|
||||||
#define HAL_SYSCFG_GRP2_PVM3 (LL_SYSCFG_GRP2_PVM3 | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from Power Voltage Monitoring 3 to CPU1 */
|
|
||||||
#define HAL_SYSCFG_GRP2_PVD (LL_SYSCFG_GRP2_PVD | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from Power Voltage Detector to CPU1 */
|
|
||||||
|
|
||||||
#endif
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
#endif /* DUAL_CORE */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported macros -----------------------------------------------------------*/
|
|
||||||
/** @defgroup HAL_Exported_Macros HAL Exported Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @brief Freeze and Unfreeze Peripherals in Debug mode
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DBGMCU_APBx_GRPx_STOP_IP DBGMCU CPU1 APBx GRPx STOP IP
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#if defined(LL_DBGMCU_APB1_GRP1_TIM2_STOP)
|
|
||||||
#define __HAL_DBGMCU_FREEZE_TIM2() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_TIM2_STOP)
|
|
||||||
#define __HAL_DBGMCU_UNFREEZE_TIM2() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_TIM2_STOP)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(LL_DBGMCU_APB1_GRP1_RTC_STOP)
|
|
||||||
#define __HAL_DBGMCU_FREEZE_RTC() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_RTC_STOP)
|
|
||||||
#define __HAL_DBGMCU_UNFREEZE_RTC() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_RTC_STOP)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(LL_DBGMCU_APB1_GRP1_WWDG_STOP)
|
|
||||||
#define __HAL_DBGMCU_FREEZE_WWDG() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_WWDG_STOP)
|
|
||||||
#define __HAL_DBGMCU_UNFREEZE_WWDG() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_WWDG_STOP)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(LL_DBGMCU_APB1_GRP1_IWDG_STOP)
|
|
||||||
#define __HAL_DBGMCU_FREEZE_IWDG() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_IWDG_STOP)
|
|
||||||
#define __HAL_DBGMCU_UNFREEZE_IWDG() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_IWDG_STOP)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(LL_DBGMCU_APB1_GRP1_I2C1_STOP)
|
|
||||||
#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_I2C1_STOP)
|
|
||||||
#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_I2C1_STOP)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(LL_DBGMCU_APB1_GRP1_I2C2_STOP)
|
|
||||||
#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_I2C2_STOP)
|
|
||||||
#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_I2C2_STOP)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(LL_DBGMCU_APB1_GRP1_I2C3_STOP)
|
|
||||||
#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_I2C3_STOP)
|
|
||||||
#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_I2C3_STOP)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP)
|
|
||||||
#define __HAL_DBGMCU_FREEZE_LPTIM1() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP)
|
|
||||||
#define __HAL_DBGMCU_UNFREEZE_LPTIM1() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(LL_DBGMCU_APB1_GRP2_LPTIM2_STOP)
|
|
||||||
#define __HAL_DBGMCU_FREEZE_LPTIM2() LL_DBGMCU_APB1_GRP2_FreezePeriph(LL_DBGMCU_APB1_GRP2_LPTIM2_STOP)
|
|
||||||
#define __HAL_DBGMCU_UNFREEZE_LPTIM2() LL_DBGMCU_APB1_GRP2_UnFreezePeriph(LL_DBGMCU_APB1_GRP2_LPTIM2_STOP)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(LL_DBGMCU_APB1_GRP2_LPTIM3_STOP)
|
|
||||||
#define __HAL_DBGMCU_FREEZE_LPTIM3() LL_DBGMCU_APB1_GRP2_FreezePeriph(LL_DBGMCU_APB1_GRP2_LPTIM3_STOP)
|
|
||||||
#define __HAL_DBGMCU_UNFREEZE_LPTIM3() LL_DBGMCU_APB1_GRP2_UnFreezePeriph(LL_DBGMCU_APB1_GRP2_LPTIM3_STOP)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(LL_DBGMCU_APB2_GRP1_TIM1_STOP)
|
|
||||||
#define __HAL_DBGMCU_FREEZE_TIM1() LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM1_STOP)
|
|
||||||
#define __HAL_DBGMCU_UNFREEZE_TIM1() LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_APB2_GRP1_TIM1_STOP)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(LL_DBGMCU_APB2_GRP1_TIM16_STOP)
|
|
||||||
#define __HAL_DBGMCU_FREEZE_TIM16() LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM16_STOP)
|
|
||||||
#define __HAL_DBGMCU_UNFREEZE_TIM16() LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_APB2_GRP1_TIM16_STOP)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(LL_DBGMCU_APB2_GRP1_TIM17_STOP)
|
|
||||||
#define __HAL_DBGMCU_FREEZE_TIM17() LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM17_STOP)
|
|
||||||
#define __HAL_DBGMCU_UNFREEZE_TIM17() LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_APB2_GRP1_TIM17_STOP)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DBGMCU_C2_APBx_GRPx_STOP_IP DBGMCU CPU2 APBx GRPx STOP IP
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#if defined(LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP)
|
|
||||||
#define __HAL_C2_DBGMCU_FREEZE_TIM2() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP)
|
|
||||||
#define __HAL_C2_DBGMCU_UNFREEZE_TIM2() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(LL_C2_DBGMCU_APB1_GRP1_RTC_STOP)
|
|
||||||
#define __HAL_C2_DBGMCU_FREEZE_RTC() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_RTC_STOP)
|
|
||||||
#define __HAL_C2_DBGMCU_UNFREEZE_RTC() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_RTC_STOP)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP)
|
|
||||||
#define __HAL_C2_DBGMCU_FREEZE_IWDG() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP)
|
|
||||||
#define __HAL_C2_DBGMCU_UNFREEZE_IWDG() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP)
|
|
||||||
#define __HAL_C2_DBGMCU_FREEZE_I2C1_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP)
|
|
||||||
#define __HAL_C2_DBGMCU_UNFREEZE_I2C1_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(LL_C2_DBGMCU_APB1_GRP1_I2C2_STOP)
|
|
||||||
#define __HAL_C2_DBGMCU_FREEZE_I2C2_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C2_STOP)
|
|
||||||
#define __HAL_C2_DBGMCU_UNFREEZE_I2C2_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C2_STOP)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP)
|
|
||||||
#define __HAL_C2_DBGMCU_FREEZE_I2C3_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP)
|
|
||||||
#define __HAL_C2_DBGMCU_UNFREEZE_I2C3_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP)
|
|
||||||
#define __HAL_C2_DBGMCU_FREEZE_LPTIM1() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP)
|
|
||||||
#define __HAL_C2_DBGMCU_UNFREEZE_LPTIM1() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP)
|
|
||||||
#define __HAL_C2_DBGMCU_FREEZE_LPTIM2() LL_C2_DBGMCU_APB1_GRP2_FreezePeriph(LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP)
|
|
||||||
#define __HAL_C2_DBGMCU_UNFREEZE_LPTIM2() LL_C2_DBGMCU_APB1_GRP2_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(LL_C2_DBGMCU_APB1_GRP2_LPTIM3_STOP)
|
|
||||||
#define __HAL_C2_DBGMCU_FREEZE_LPTIM3() LL_C2_DBGMCU_APB1_GRP2_FreezePeriph(LL_C2_DBGMCU_APB1_GRP2_LPTIM3_STOP)
|
|
||||||
#define __HAL_C2_DBGMCU_UNFREEZE_LPTIM3() LL_C2_DBGMCU_APB1_GRP2_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP2_LPTIM3_STOP)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP)
|
|
||||||
#define __HAL_C2_DBGMCU_FREEZE_TIM1() LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP)
|
|
||||||
#define __HAL_C2_DBGMCU_UNFREEZE_TIM1() LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP)
|
|
||||||
#define __HAL_C2_DBGMCU_FREEZE_TIM16() LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP)
|
|
||||||
#define __HAL_C2_DBGMCU_UNFREEZE_TIM16() LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP)
|
|
||||||
#define __HAL_C2_DBGMCU_FREEZE_TIM17() LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP)
|
|
||||||
#define __HAL_C2_DBGMCU_UNFREEZE_TIM17() LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @brief Main Flash memory mapped at 0x00000000
|
|
||||||
*/
|
|
||||||
#define __HAL_SYSCFG_REMAPMEMORY_FLASH() LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_FLASH)
|
|
||||||
|
|
||||||
/** @brief System Flash memory mapped at 0x00000000
|
|
||||||
*/
|
|
||||||
#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_SYSTEMFLASH)
|
|
||||||
|
|
||||||
/** @brief Embedded SRAM mapped at 0x00000000
|
|
||||||
*/
|
|
||||||
#define __HAL_SYSCFG_REMAPMEMORY_SRAM() LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_SRAM)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Return the boot mode as configured by user.
|
|
||||||
* @retval The boot mode as configured by user. The returned value can be one
|
|
||||||
* of the following values:
|
|
||||||
* @arg @ref SYSCFG_BOOT_MAINFLASH
|
|
||||||
* @arg @ref SYSCFG_BOOT_SYSTEMFLASH
|
|
||||||
* @arg @ref SYSCFG_BOOT_SRAM
|
|
||||||
*/
|
|
||||||
#define __HAL_SYSCFG_GET_BOOT_MODE() LL_SYSCFG_GetRemapMemory()
|
|
||||||
|
|
||||||
/** @brief SRAM2 page 0 to 31 write protection enable macro
|
|
||||||
* @param __SRAM2WRP__ This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP
|
|
||||||
* @note Write protection can only be disabled by a system reset
|
|
||||||
*/
|
|
||||||
/* Legacy define */
|
|
||||||
#define __HAL_SYSCFG_SRAM2_WRP_1_31_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
|
|
||||||
#define __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\
|
|
||||||
LL_SYSCFG_EnableSRAM2PageWRP_0_31(__SRAM2WRP__);\
|
|
||||||
}while(0)
|
|
||||||
|
|
||||||
/** @brief SRAM2 page write protection unlock prior to erase
|
|
||||||
* @note Writing a wrong key reactivates the write protection
|
|
||||||
*/
|
|
||||||
#define __HAL_SYSCFG_SRAM2_WRP_UNLOCK() LL_SYSCFG_UnlockSRAM2WRP()
|
|
||||||
|
|
||||||
/** @brief SRAM2 erase
|
|
||||||
* @note __SYSCFG_GET_FLAG(SYSCFG_FLAG_SRAM_BUSY) may be used to check end of erase
|
|
||||||
*/
|
|
||||||
#define __HAL_SYSCFG_SRAM2_ERASE() LL_SYSCFG_EnableSRAM2Erase()
|
|
||||||
|
|
||||||
/** @brief SYSCFG Break ECC lock.
|
|
||||||
* Enable and lock the connection of Flash ECC error connection to TIM1/16/17 Break input.
|
|
||||||
* @note The selected configuration is locked and can be unlocked only by system reset.
|
|
||||||
*/
|
|
||||||
#define __HAL_SYSCFG_BREAK_ECC_LOCK() LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_ECC)
|
|
||||||
|
|
||||||
/** @brief SYSCFG Break Cortex-M4 Lockup lock.
|
|
||||||
* Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/16/17 Break input.
|
|
||||||
* @note The selected configuration is locked and can be unlocked only by system reset.
|
|
||||||
*/
|
|
||||||
#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_LOCKUP)
|
|
||||||
|
|
||||||
/** @brief SYSCFG Break PVD lock.
|
|
||||||
* Enable and lock the PVD connection to Timer1/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register.
|
|
||||||
* @note The selected configuration is locked and can be unlocked only by system reset.
|
|
||||||
*/
|
|
||||||
#define __HAL_SYSCFG_BREAK_PVD_LOCK() LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_PVD)
|
|
||||||
|
|
||||||
/** @brief SYSCFG Break SRAM2 parity lock.
|
|
||||||
* Enable and lock the SRAM2 parity error signal connection to TIM1/16/17 Break input.
|
|
||||||
* @note The selected configuration is locked and can be unlocked by system reset.
|
|
||||||
*/
|
|
||||||
#define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_SRAM2_PARITY)
|
|
||||||
|
|
||||||
/** @brief Check SYSCFG flag is set or not.
|
|
||||||
* @param __FLAG__ specifies the flag to check.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg @ref SYSCFG_FLAG_SRAM2_PE SRAM2 Parity Error Flag
|
|
||||||
* @arg @ref SYSCFG_FLAG_SRAM_BUSY SRAM2 Erase Ongoing
|
|
||||||
* @arg @ref SYSCFG_FLAG_PKASRAM_BUSY PKA SRAM Erase Ongoing
|
|
||||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
|
||||||
*/
|
|
||||||
#define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_FLAG_SRAM2_PE)? SYSCFG->CFGR2 : SYSCFG->SCSR) & (__FLAG__))!= 0) ? 1 : 0)
|
|
||||||
|
|
||||||
/** @brief Set the SPF bit to clear the SRAM Parity Error Flag.
|
|
||||||
*/
|
|
||||||
#define __HAL_SYSCFG_CLEAR_FLAG() LL_SYSCFG_ClearFlag_SP()
|
|
||||||
|
|
||||||
/** @brief Fast mode Plus driving capability enable/disable macros
|
|
||||||
* @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO
|
|
||||||
*/
|
|
||||||
#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \
|
|
||||||
LL_SYSCFG_EnableFastModePlus(__FASTMODEPLUS__); \
|
|
||||||
}while(0)
|
|
||||||
|
|
||||||
#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \
|
|
||||||
LL_SYSCFG_DisableFastModePlus(__FASTMODEPLUS__); \
|
|
||||||
}while(0)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private macros ------------------------------------------------------------*/
|
|
||||||
/** @defgroup HAL_Private_Macros HAL Private Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFFFFFU))
|
|
||||||
|
|
||||||
#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
|
|
||||||
((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1))
|
|
||||||
|
|
||||||
#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
|
|
||||||
((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))
|
|
||||||
|
|
||||||
#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
|
|
||||||
|
|
||||||
#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
|
|
||||||
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
|
|
||||||
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
|
|
||||||
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
|
|
||||||
|
|
||||||
|
|
||||||
#if defined(DUAL_CORE)
|
|
||||||
#if defined(CORE_CM0PLUS)
|
|
||||||
#define IS_SYSCFG_IM_GRP1(__VALUE__) ((((__VALUE__) & 0x80U) == HAL_SYSCFG_GRP1_RESERVED) && \
|
|
||||||
((((__VALUE__) & HAL_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS) == HAL_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP1_RTCALARM ) == HAL_SYSCFG_GRP1_RTCALARM ) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP1_RTCSSRU ) == HAL_SYSCFG_GRP1_RTCSSRU ) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP1_RTCWKUP ) == HAL_SYSCFG_GRP1_RTCWKUP ) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP1_RCC ) == HAL_SYSCFG_GRP1_RCC ) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP1_FLASH ) == HAL_SYSCFG_GRP1_FLASH ) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP1_PKA ) == HAL_SYSCFG_GRP1_PKA ) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP1_AES ) == HAL_SYSCFG_GRP1_AES ) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP1_COMP ) == HAL_SYSCFG_GRP1_COMP ) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP1_ADC ) == HAL_SYSCFG_GRP1_ADC ) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP1_DAC ) == HAL_SYSCFG_GRP1_DAC ) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP1_EXTI0 ) == HAL_SYSCFG_GRP1_EXTI0 ) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP1_EXTI1 ) == HAL_SYSCFG_GRP1_EXTI1 ) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP1_EXTI2 ) == HAL_SYSCFG_GRP1_EXTI2 ) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP1_EXTI3 ) == HAL_SYSCFG_GRP1_EXTI3 ) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP1_EXTI4 ) == HAL_SYSCFG_GRP1_EXTI4 ) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP1_EXTI5 ) == HAL_SYSCFG_GRP1_EXTI5 ) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP1_EXTI6 ) == HAL_SYSCFG_GRP1_EXTI6 ) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP1_EXTI7 ) == HAL_SYSCFG_GRP1_EXTI7 ) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP1_EXTI8 ) == HAL_SYSCFG_GRP1_EXTI8 ) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP1_EXTI9 ) == HAL_SYSCFG_GRP1_EXTI9 ) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP1_EXTI10 ) == HAL_SYSCFG_GRP1_EXTI10 ) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP1_EXTI11 ) == HAL_SYSCFG_GRP1_EXTI11 ) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP1_EXTI12 ) == HAL_SYSCFG_GRP1_EXTI12 ) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP1_EXTI13 ) == HAL_SYSCFG_GRP1_EXTI13 ) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP1_EXTI14 ) == HAL_SYSCFG_GRP1_EXTI14 ) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP1_EXTI15 ) == HAL_SYSCFG_GRP1_EXTI15 )))
|
|
||||||
|
|
||||||
#define IS_SYSCFG_IM_GRP2(__VALUE__) ((((__VALUE__) & 0x80U) == HAL_SYSCFG_GRP2_RESERVED) && \
|
|
||||||
((((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH1) == HAL_SYSCFG_GRP2_DMA1CH1) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH2) == HAL_SYSCFG_GRP2_DMA1CH2) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH3) == HAL_SYSCFG_GRP2_DMA1CH3) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH4) == HAL_SYSCFG_GRP2_DMA1CH4) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH5) == HAL_SYSCFG_GRP2_DMA1CH5) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH6) == HAL_SYSCFG_GRP2_DMA1CH6) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH7) == HAL_SYSCFG_GRP2_DMA1CH7) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH1) == HAL_SYSCFG_GRP2_DMA2CH1) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH2) == HAL_SYSCFG_GRP2_DMA2CH2) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH3) == HAL_SYSCFG_GRP2_DMA2CH3) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH4) == HAL_SYSCFG_GRP2_DMA2CH4) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH5) == HAL_SYSCFG_GRP2_DMA2CH5) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH6) == HAL_SYSCFG_GRP2_DMA2CH6) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH7) == HAL_SYSCFG_GRP2_DMA2CH7) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP2_DMAMUX1) == HAL_SYSCFG_GRP2_DMAMUX1) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP2_PVM3 ) == HAL_SYSCFG_GRP2_PVM3 ) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP2_PVD ) == HAL_SYSCFG_GRP2_PVD )))
|
|
||||||
|
|
||||||
#else /* !CORE_CM0PLUS */
|
|
||||||
|
|
||||||
#define IS_SYSCFG_IM_GRP1(__VALUE__) ((((__VALUE__) & 0x80U) == HAL_SYSCFG_GRP1_RESERVED) && \
|
|
||||||
((((__VALUE__) & HAL_SYSCFG_GRP1_RTCSTAMPTAMPLSECSS) == HAL_SYSCFG_GRP1_RTCSTAMPTAMPLSECSS) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP1_RTCSSRU ) == HAL_SYSCFG_GRP1_RTCSSRU ) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP1_EXTI5 ) == HAL_SYSCFG_GRP1_EXTI5 ) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP1_EXTI6 ) == HAL_SYSCFG_GRP1_EXTI6 ) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP1_EXTI7 ) == HAL_SYSCFG_GRP1_EXTI7 ) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP1_EXTI8 ) == HAL_SYSCFG_GRP1_EXTI8 ) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP1_EXTI9 ) == HAL_SYSCFG_GRP1_EXTI9 ) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP1_EXTI10 ) == HAL_SYSCFG_GRP1_EXTI10 ) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP1_EXTI11 ) == HAL_SYSCFG_GRP1_EXTI11 ) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP1_EXTI12 ) == HAL_SYSCFG_GRP1_EXTI12 ) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP1_EXTI13 ) == HAL_SYSCFG_GRP1_EXTI13 ) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP1_EXTI14 ) == HAL_SYSCFG_GRP1_EXTI14 ) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP1_EXTI15 ) == HAL_SYSCFG_GRP1_EXTI15 )))
|
|
||||||
|
|
||||||
#define IS_SYSCFG_IM_GRP2(__VALUE__) ((((__VALUE__) & 0x80U) == HAL_SYSCFG_GRP2_RESERVED) && \
|
|
||||||
((((__VALUE__) & HAL_SYSCFG_GRP2_PVM3) == HAL_SYSCFG_GRP2_PVM3) || \
|
|
||||||
(((__VALUE__) & HAL_SYSCFG_GRP2_PVD ) == HAL_SYSCFG_GRP2_PVD )))
|
|
||||||
|
|
||||||
#endif /* CORE_CM0PLUS */
|
|
||||||
#endif /* DUAL_CORE */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup HAL_Private_Macros HAL Private Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \
|
|
||||||
((FREQ) == HAL_TICK_FREQ_100HZ) || \
|
|
||||||
((FREQ) == HAL_TICK_FREQ_1KHZ))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/* Exported functions --------------------------------------------------------*/
|
|
||||||
|
|
||||||
/** @defgroup HAL_Exported_Functions HAL Exported Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup HAL_Exported_Functions_Group1 HAL Initialization and Configuration functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Initialization and Configuration functions ******************************/
|
|
||||||
HAL_StatusTypeDef HAL_Init(void);
|
|
||||||
HAL_StatusTypeDef HAL_DeInit(void);
|
|
||||||
void HAL_MspInit(void);
|
|
||||||
void HAL_MspDeInit(void);
|
|
||||||
|
|
||||||
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported variables ---------------------------------------------------------*/
|
|
||||||
/** @addtogroup HAL_Exported_Variables
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
extern __IO uint32_t uwTick;
|
|
||||||
extern uint32_t uwTickPrio;
|
|
||||||
extern HAL_TickFreqTypeDef uwTickFreq;
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Peripheral Control functions ************************************************/
|
|
||||||
void HAL_IncTick(void);
|
|
||||||
void HAL_Delay(uint32_t Delay);
|
|
||||||
uint32_t HAL_GetTick(void);
|
|
||||||
uint32_t HAL_GetTickPrio(void);
|
|
||||||
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
|
|
||||||
HAL_TickFreqTypeDef HAL_GetTickFreq(void);
|
|
||||||
void HAL_SuspendTick(void);
|
|
||||||
void HAL_ResumeTick(void);
|
|
||||||
uint32_t HAL_GetHalVersion(void);
|
|
||||||
uint32_t HAL_GetREVID(void);
|
|
||||||
uint32_t HAL_GetDEVID(void);
|
|
||||||
uint32_t HAL_GetUIDw0(void);
|
|
||||||
uint32_t HAL_GetUIDw1(void);
|
|
||||||
uint32_t HAL_GetUIDw2(void);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup HAL_Exported_Functions_Group3 HAL Debug functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* DBGMCU Peripheral Control functions *****************************************/
|
|
||||||
void HAL_DBGMCU_EnableDBGSleepMode(void);
|
|
||||||
void HAL_DBGMCU_DisableDBGSleepMode(void);
|
|
||||||
void HAL_DBGMCU_EnableDBGStopMode(void);
|
|
||||||
void HAL_DBGMCU_DisableDBGStopMode(void);
|
|
||||||
void HAL_DBGMCU_EnableDBGStandbyMode(void);
|
|
||||||
void HAL_DBGMCU_DisableDBGStandbyMode(void);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup HAL_Exported_Functions_Group4 HAL System Configuration functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* SYSCFG Control functions ****************************************************/
|
|
||||||
void HAL_SYSCFG_SRAM2Erase(void);
|
|
||||||
|
|
||||||
void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
|
|
||||||
void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
|
|
||||||
void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
|
|
||||||
HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
|
|
||||||
void HAL_SYSCFG_DisableVREFBUF(void);
|
|
||||||
|
|
||||||
void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void);
|
|
||||||
void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void);
|
|
||||||
|
|
||||||
#if defined(DUAL_CORE)
|
|
||||||
void HAL_SYSCFG_EnableIT(SYSCFG_InterruptTypeDef *Interrupt);
|
|
||||||
void HAL_SYSCFG_DisableIT(SYSCFG_InterruptTypeDef *Interrupt);
|
|
||||||
#endif
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* __STM32WLxx_HAL_H */
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,189 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32wlxx_hal_adc_ex.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief Header file of ADC HAL extended module.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
|
||||||
* All rights reserved.</center></h2>
|
|
||||||
*
|
|
||||||
* This software component is licensed by ST under BSD 3-Clause license,
|
|
||||||
* the "License"; You may not use this file except in compliance with the
|
|
||||||
* License. You may obtain a copy of the License at:
|
|
||||||
* opensource.org/licenses/BSD-3-Clause
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef STM32WLxx_HAL_ADC_EX_H
|
|
||||||
#define STM32WLxx_HAL_ADC_EX_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32wlxx_hal_def.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32WLxx_HAL_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup ADCEx
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
/** @defgroup ADCEx_Exported_Types ADC Extended Exported Types
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
|
||||||
|
|
||||||
/** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on all STM32 devices) */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported macros -----------------------------------------------------------*/
|
|
||||||
|
|
||||||
/* Private macros ------------------------------------------------------------*/
|
|
||||||
|
|
||||||
/** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Macro reserved for internal HAL driver usage, not intended to be used in */
|
|
||||||
/* code of final user. */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Check whether or not ADC is independent.
|
|
||||||
* @param __HANDLE__ ADC handle.
|
|
||||||
* @note When multimode feature is not available, the macro always returns SET.
|
|
||||||
* @retval SET (ADC is independent) or RESET (ADC is not).
|
|
||||||
*/
|
|
||||||
#define ADC_IS_INDEPENDENT(__HANDLE__) (SET)
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Calibration factor size verification (7 bits maximum).
|
|
||||||
* @param __CALIBRATION_FACTOR__ Calibration factor value.
|
|
||||||
* @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large)
|
|
||||||
*/
|
|
||||||
#define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Verify the ADC oversampling ratio.
|
|
||||||
* @param __RATIO__ programmed ADC oversampling ratio.
|
|
||||||
* @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid)
|
|
||||||
*/
|
|
||||||
#define IS_ADC_OVERSAMPLING_RATIO(__RATIO__) (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2 ) || \
|
|
||||||
((__RATIO__) == ADC_OVERSAMPLING_RATIO_4 ) || \
|
|
||||||
((__RATIO__) == ADC_OVERSAMPLING_RATIO_8 ) || \
|
|
||||||
((__RATIO__) == ADC_OVERSAMPLING_RATIO_16 ) || \
|
|
||||||
((__RATIO__) == ADC_OVERSAMPLING_RATIO_32 ) || \
|
|
||||||
((__RATIO__) == ADC_OVERSAMPLING_RATIO_64 ) || \
|
|
||||||
((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) || \
|
|
||||||
((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 ))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Verify the ADC oversampling shift.
|
|
||||||
* @param __SHIFT__ programmed ADC oversampling shift.
|
|
||||||
* @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid)
|
|
||||||
*/
|
|
||||||
#define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \
|
|
||||||
((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) || \
|
|
||||||
((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) || \
|
|
||||||
((__SHIFT__) == ADC_RIGHTBITSHIFT_3 ) || \
|
|
||||||
((__SHIFT__) == ADC_RIGHTBITSHIFT_4 ) || \
|
|
||||||
((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) || \
|
|
||||||
((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) || \
|
|
||||||
((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \
|
|
||||||
((__SHIFT__) == ADC_RIGHTBITSHIFT_8 ))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Verify the ADC oversampling triggered mode.
|
|
||||||
* @param __MODE__ programmed ADC oversampling triggered mode.
|
|
||||||
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
|
|
||||||
*/
|
|
||||||
#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
|
|
||||||
((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/* Exported functions --------------------------------------------------------*/
|
|
||||||
/** @addtogroup ADCEx_Exported_Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup ADCEx_Exported_Functions_Group1
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* IO operation functions *****************************************************/
|
|
||||||
|
|
||||||
/* ADC calibration */
|
|
||||||
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc);
|
|
||||||
uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc);
|
|
||||||
HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t CalibrationFactor);
|
|
||||||
|
|
||||||
/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
|
|
||||||
void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc);
|
|
||||||
void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc);
|
|
||||||
void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc);
|
|
||||||
void HAL_ADCEx_ChannelConfigReadyCallback(ADC_HandleTypeDef *hadc);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup ADCEx_Exported_Functions_Group2
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Peripheral Control functions ***********************************************/
|
|
||||||
HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* STM32WLxx_HAL_ADC_EX_H */
|
|
||||||
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,730 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32wlxx_hal_comp.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief Header file of COMP HAL module.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
|
||||||
* All rights reserved.</center></h2>
|
|
||||||
*
|
|
||||||
* This software component is licensed by ST under BSD 3-Clause license,
|
|
||||||
* the "License"; You may not use this file except in compliance with the
|
|
||||||
* License. You may obtain a copy of the License at:
|
|
||||||
* opensource.org/licenses/BSD-3-Clause
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef STM32WLxx_HAL_COMP_H
|
|
||||||
#define STM32WLxx_HAL_COMP_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32wlxx_hal_def.h"
|
|
||||||
#include "stm32wlxx_ll_exti.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32WLxx_HAL_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/** @addtogroup COMP
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
/** @defgroup COMP_Exported_Types COMP Exported Types
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief COMP Init structure definition
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
|
|
||||||
uint32_t WindowMode; /*!< Set window mode of a pair of comparators instances
|
|
||||||
(2 consecutive instances odd and even COMP<x> and COMP<x+1>).
|
|
||||||
Note: HAL COMP driver allows to set window mode from any COMP instance of the pair of COMP instances composing window mode.
|
|
||||||
This parameter can be a value of @ref COMP_WindowMode */
|
|
||||||
|
|
||||||
uint32_t Mode; /*!< Set comparator operating mode to adjust power and speed.
|
|
||||||
Note: For the characteristics of comparator power modes
|
|
||||||
(propagation delay and power consumption), refer to device datasheet.
|
|
||||||
This parameter can be a value of @ref COMP_PowerMode */
|
|
||||||
|
|
||||||
uint32_t InputPlus; /*!< Set comparator input plus (non-inverting input).
|
|
||||||
This parameter can be a value of @ref COMP_InputPlus */
|
|
||||||
|
|
||||||
uint32_t InputMinus; /*!< Set comparator input minus (inverting input).
|
|
||||||
This parameter can be a value of @ref COMP_InputMinus */
|
|
||||||
|
|
||||||
uint32_t Hysteresis; /*!< Set comparator hysteresis mode of the input minus.
|
|
||||||
This parameter can be a value of @ref COMP_Hysteresis */
|
|
||||||
|
|
||||||
uint32_t OutputPol; /*!< Set comparator output polarity.
|
|
||||||
This parameter can be a value of @ref COMP_OutputPolarity */
|
|
||||||
|
|
||||||
uint32_t BlankingSrce; /*!< Set comparator blanking source.
|
|
||||||
This parameter can be a value of @ref COMP_BlankingSrce */
|
|
||||||
|
|
||||||
uint32_t TriggerMode; /*!< Set the comparator output triggering External Interrupt Line (EXTI).
|
|
||||||
This parameter can be a value of @ref COMP_EXTI_TriggerMode */
|
|
||||||
|
|
||||||
} COMP_InitTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief HAL COMP state machine: HAL COMP states definition
|
|
||||||
*/
|
|
||||||
#define COMP_STATE_BITFIELD_LOCK (0x10U)
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
HAL_COMP_STATE_RESET = 0x00U, /*!< COMP not yet initialized */
|
|
||||||
HAL_COMP_STATE_RESET_LOCKED = (HAL_COMP_STATE_RESET | COMP_STATE_BITFIELD_LOCK), /*!< COMP not yet initialized and configuration is locked */
|
|
||||||
HAL_COMP_STATE_READY = 0x01U, /*!< COMP initialized and ready for use */
|
|
||||||
HAL_COMP_STATE_READY_LOCKED = (HAL_COMP_STATE_READY | COMP_STATE_BITFIELD_LOCK), /*!< COMP initialized but configuration is locked */
|
|
||||||
HAL_COMP_STATE_BUSY = 0x02U, /*!< COMP is running */
|
|
||||||
HAL_COMP_STATE_BUSY_LOCKED = (HAL_COMP_STATE_BUSY | COMP_STATE_BITFIELD_LOCK) /*!< COMP is running and configuration is locked */
|
|
||||||
} HAL_COMP_StateTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief COMP Handle Structure definition
|
|
||||||
*/
|
|
||||||
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
|
|
||||||
typedef struct __COMP_HandleTypeDef
|
|
||||||
#else
|
|
||||||
typedef struct
|
|
||||||
#endif
|
|
||||||
{
|
|
||||||
COMP_TypeDef *Instance; /*!< Register base address */
|
|
||||||
COMP_InitTypeDef Init; /*!< COMP required parameters */
|
|
||||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
|
||||||
__IO HAL_COMP_StateTypeDef State; /*!< COMP communication state */
|
|
||||||
__IO uint32_t ErrorCode; /*!< COMP error code */
|
|
||||||
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
|
|
||||||
void (* TriggerCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP trigger callback */
|
|
||||||
void (* MspInitCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP Msp Init callback */
|
|
||||||
void (* MspDeInitCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP Msp DeInit callback */
|
|
||||||
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
|
|
||||||
} COMP_HandleTypeDef;
|
|
||||||
|
|
||||||
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
|
|
||||||
/**
|
|
||||||
* @brief HAL COMP Callback ID enumeration definition
|
|
||||||
*/
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
HAL_COMP_TRIGGER_CB_ID = 0x00U, /*!< COMP trigger callback ID */
|
|
||||||
HAL_COMP_MSPINIT_CB_ID = 0x01U, /*!< COMP Msp Init callback ID */
|
|
||||||
HAL_COMP_MSPDEINIT_CB_ID = 0x02U /*!< COMP Msp DeInit callback ID */
|
|
||||||
} HAL_COMP_CallbackIDTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief HAL COMP Callback pointer definition
|
|
||||||
*/
|
|
||||||
typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer to a COMP callback function */
|
|
||||||
|
|
||||||
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
|
||||||
/** @defgroup COMP_Exported_Constants COMP Exported Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup COMP_Error_Code COMP Error Code
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define HAL_COMP_ERROR_NONE (0x00UL) /*!< No error */
|
|
||||||
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
|
|
||||||
#define HAL_COMP_ERROR_INVALID_CALLBACK (0x01UL) /*!< Invalid Callback error */
|
|
||||||
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup COMP_WindowMode COMP Window Mode
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define COMP_WINDOWMODE_DISABLE (0x00000000UL) /*!< Window mode disable: Comparators instances pair COMP1 and COMP2 are independent */
|
|
||||||
#define COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE) /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup COMP_PowerMode COMP power mode
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Note: For the characteristics of comparator power modes */
|
|
||||||
/* (propagation delay and power consumption), */
|
|
||||||
/* refer to device datasheet. */
|
|
||||||
#define COMP_POWERMODE_HIGHSPEED (0x00000000UL) /*!< High Speed */
|
|
||||||
#define COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_PWRMODE_0) /*!< Medium Speed */
|
|
||||||
#define COMP_POWERMODE_ULTRALOWPOWER (COMP_CSR_PWRMODE) /*!< Ultra-low power mode */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup COMP_InputPlus COMP input plus (non-inverting input)
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define COMP_INPUT_PLUS_IO1 (0x00000000UL) /*!< Comparator input plus connected to IO1 (pin PB4 for COMP1, pin PB4 for COMP2) */
|
|
||||||
#define COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL_0) /*!< Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PB1 for COMP2) */
|
|
||||||
#define COMP_INPUT_PLUS_IO3 (COMP_CSR_INPSEL_1) /*!< Comparator input plus connected to IO3 (not applicable for COMP1, pin PA15 for COMP2) */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup COMP_InputMinus COMP input minus (inverting input)
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define COMP_INPUT_MINUS_1_4VREFINT ( COMP_CSR_SCALEN | COMP_CSR_BRGEN) /*!< Comparator input minus connected to 1/4 VrefInt */
|
|
||||||
#define COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN | COMP_CSR_BRGEN) /*!< Comparator input minus connected to 1/2 VrefInt */
|
|
||||||
#define COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_SCALEN | COMP_CSR_BRGEN) /*!< Comparator input minus connected to 3/4 VrefInt */
|
|
||||||
#define COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN ) /*!< Comparator input minus connected to VrefInt */
|
|
||||||
#define COMP_INPUT_MINUS_DAC_CH1 (COMP_CSR_INMSEL_2 ) /*!< Comparator input minus connected to DAC channel 1 (DAC_OUT1) */
|
|
||||||
#define COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PB3 for COMP1, pin PB3 for COMP2) */
|
|
||||||
#define COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO2 (pin PA10 for COMP1, pin PB2 for COMP2) */
|
|
||||||
#define COMP_INPUT_MINUS_IO3 ( COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO3 (pin PA11 for COMP1, pin PA10 for COMP2) */
|
|
||||||
#define COMP_INPUT_MINUS_IO4 (COMP_CSR_INMESEL_1 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO4 (pin PA15 for COMP1, pin PA11 for COMP2) */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup COMP_Hysteresis COMP hysteresis
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define COMP_HYSTERESIS_NONE (0x00000000UL) /*!< No hysteresis */
|
|
||||||
#define COMP_HYSTERESIS_LOW ( COMP_CSR_HYST_0) /*!< Hysteresis level low */
|
|
||||||
#define COMP_HYSTERESIS_MEDIUM (COMP_CSR_HYST_1 ) /*!< Hysteresis level medium */
|
|
||||||
#define COMP_HYSTERESIS_HIGH (COMP_CSR_HYST_1 | COMP_CSR_HYST_0) /*!< Hysteresis level high */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup COMP_OutputPolarity COMP output Polarity
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define COMP_OUTPUTPOL_NONINVERTED (0x00000000UL) /*!< COMP output level is not inverted (comparator output is high when the input plus is at a higher voltage than the input minus) */
|
|
||||||
#define COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY) /*!< COMP output level is inverted (comparator output is low when the input plus is at a higher voltage than the input minus) */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup COMP_BlankingSrce COMP blanking source
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define COMP_BLANKINGSRC_NONE (0x00000000UL) /*!<Comparator output without blanking */
|
|
||||||
/* Note: Output blanking source common to all COMP instances */
|
|
||||||
#define COMP_BLANKINGSRC_TIM1_OC5 (COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM1 OC5 (common to all COMP instances: COMP1, COMP2) */
|
|
||||||
#define COMP_BLANKINGSRC_TIM2_OC3 (COMP_CSR_BLANKING_1) /*!< Comparator output blanking source TIM2 OC3 (common to all COMP instances: COMP1, COMP2) */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup COMP_OutputLevel COMP Output Level
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Note: Comparator output level values are fixed to "0" and "1", */
|
|
||||||
/* corresponding COMP register bit is managed by HAL function to match */
|
|
||||||
/* with these values (independently of bit position in register). */
|
|
||||||
|
|
||||||
/* When output polarity is not inverted, comparator output is low when
|
|
||||||
the input plus is at a lower voltage than the input minus */
|
|
||||||
#define COMP_OUTPUT_LEVEL_LOW (0x00000000UL)
|
|
||||||
/* When output polarity is not inverted, comparator output is high when
|
|
||||||
the input plus is at a higher voltage than the input minus */
|
|
||||||
#define COMP_OUTPUT_LEVEL_HIGH (0x00000001UL)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup COMP_EXTI_TriggerMode COMP output to EXTI
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define COMP_TRIGGERMODE_NONE (0x00000000UL) /*!< Comparator output triggering no External Interrupt Line */
|
|
||||||
#define COMP_TRIGGERMODE_IT_RISING (COMP_EXTI_IT | COMP_EXTI_RISING) /*!< Comparator output triggering External Interrupt Line event with interruption, on rising edge */
|
|
||||||
#define COMP_TRIGGERMODE_IT_FALLING (COMP_EXTI_IT | COMP_EXTI_FALLING) /*!< Comparator output triggering External Interrupt Line event with interruption, on falling edge */
|
|
||||||
#define COMP_TRIGGERMODE_IT_RISING_FALLING (COMP_EXTI_IT | COMP_EXTI_RISING | COMP_EXTI_FALLING) /*!< Comparator output triggering External Interrupt Line event with interruption, on both rising and falling edges */
|
|
||||||
#define COMP_TRIGGERMODE_EVENT_RISING (COMP_EXTI_EVENT | COMP_EXTI_RISING) /*!< Comparator output triggering External Interrupt Line event only (without interruption), on rising edge */
|
|
||||||
#define COMP_TRIGGERMODE_EVENT_FALLING (COMP_EXTI_EVENT | COMP_EXTI_FALLING) /*!< Comparator output triggering External Interrupt Line event only (without interruption), on falling edge */
|
|
||||||
#define COMP_TRIGGERMODE_EVENT_RISING_FALLING (COMP_EXTI_EVENT | COMP_EXTI_RISING | COMP_EXTI_FALLING) /*!< Comparator output triggering External Interrupt Line event only (without interruption), on both rising and falling edges */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported macro ------------------------------------------------------------*/
|
|
||||||
/** @defgroup COMP_Exported_Macros COMP Exported Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup COMP_Handle_Management COMP Handle Management
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @brief Reset COMP handle state.
|
|
||||||
* @param __HANDLE__ COMP handle
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
|
|
||||||
#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
|
||||||
(__HANDLE__)->State = HAL_COMP_STATE_RESET; \
|
|
||||||
(__HANDLE__)->MspInitCallback = NULL; \
|
|
||||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
|
||||||
} while(0)
|
|
||||||
#else
|
|
||||||
#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Clear COMP error code (set it to no error code "HAL_COMP_ERROR_NONE").
|
|
||||||
* @param __HANDLE__ COMP handle
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define COMP_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the specified comparator.
|
|
||||||
* @param __HANDLE__ COMP handle
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_COMP_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the specified comparator.
|
|
||||||
* @param __HANDLE__ COMP handle
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_COMP_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Lock the specified comparator configuration.
|
|
||||||
* @note Using this macro induce HAL COMP handle state machine being no
|
|
||||||
* more in line with COMP instance state.
|
|
||||||
* To keep HAL COMP handle state machine updated, it is recommended
|
|
||||||
* to use function "HAL_COMP_Lock')".
|
|
||||||
* @param __HANDLE__ COMP handle
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_COMP_LOCK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Check whether the specified comparator is locked.
|
|
||||||
* @param __HANDLE__ COMP handle
|
|
||||||
* @retval Value 0 if COMP instance is not locked, value 1 if COMP instance is locked
|
|
||||||
*/
|
|
||||||
#define __HAL_COMP_IS_LOCKED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) == COMP_CSR_LOCK)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup COMP_Exti_Management COMP external interrupt line management
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the COMP1 EXTI line rising edge trigger.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the COMP1 EXTI line rising edge trigger.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the COMP1 EXTI line falling edge trigger.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the COMP1 EXTI line falling edge trigger.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the COMP1 EXTI line rising & falling edge trigger.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
|
|
||||||
LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \
|
|
||||||
LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \
|
|
||||||
} while(0)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the COMP1 EXTI line rising & falling edge trigger.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
|
|
||||||
LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \
|
|
||||||
LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \
|
|
||||||
} while(0)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the COMP1 EXTI line in interrupt mode.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#if defined(CORE_CM0PLUS)
|
|
||||||
#define __HAL_COMP_COMP1_EXTI_ENABLE_IT() LL_C2_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP1)
|
|
||||||
#else
|
|
||||||
#define __HAL_COMP_COMP1_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP1)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the COMP1 EXTI line in interrupt mode.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#if defined(CORE_CM0PLUS)
|
|
||||||
#define __HAL_COMP_COMP1_EXTI_DISABLE_IT() LL_C2_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP1)
|
|
||||||
#else
|
|
||||||
#define __HAL_COMP_COMP1_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP1)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Generate a software interrupt on the COMP1 EXTI line.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP1)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the COMP1 EXTI line in event mode.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#if defined(CORE_CM0PLUS)
|
|
||||||
#define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT() LL_C2_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP1)
|
|
||||||
#else
|
|
||||||
#define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP1)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the COMP1 EXTI line in event mode.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#if defined(CORE_CM0PLUS)
|
|
||||||
#define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT() LL_C2_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP1)
|
|
||||||
#else
|
|
||||||
#define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP1)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Check whether the COMP1 EXTI line flag is set.
|
|
||||||
* @retval RESET or SET
|
|
||||||
*/
|
|
||||||
#define __HAL_COMP_COMP1_EXTI_GET_FLAG() LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP1)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Clear the COMP1 EXTI flag.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP1)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the COMP2 EXTI line rising edge trigger.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the COMP2 EXTI line rising edge trigger.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the COMP2 EXTI line falling edge trigger.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the COMP2 EXTI line falling edge trigger.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the COMP2 EXTI line rising & falling edge trigger.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
|
|
||||||
LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \
|
|
||||||
LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2); \
|
|
||||||
} while(0)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the COMP2 EXTI line rising & falling edge trigger.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
|
|
||||||
LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \
|
|
||||||
LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2); \
|
|
||||||
} while(0)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the COMP2 EXTI line in interrupt mode.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_COMP_COMP2_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP2)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the COMP2 EXTI line in interrupt mode.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_COMP_COMP2_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP2)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Generate a software interrupt on the COMP2 EXTI line.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP2)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the COMP2 EXTI line in event mode.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_COMP_COMP2_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP2)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the COMP2 EXTI line in event mode.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP2)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Check whether the COMP2 EXTI line flag is set.
|
|
||||||
* @retval RESET or SET
|
|
||||||
*/
|
|
||||||
#define __HAL_COMP_COMP2_EXTI_GET_FLAG() LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP2)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Clear the COMP2 EXTI flag.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP2)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/* Private types -------------------------------------------------------------*/
|
|
||||||
/* Private constants ---------------------------------------------------------*/
|
|
||||||
/** @defgroup COMP_Private_Constants COMP Private Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup COMP_ExtiLine COMP EXTI Lines
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define COMP_EXTI_LINE_COMP1 (LL_EXTI_LINE_21) /*!< EXTI line 21 connected to COMP1 output */
|
|
||||||
#define COMP_EXTI_LINE_COMP2 (LL_EXTI_LINE_22) /*!< EXTI line 22 connected to COMP2 output */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup COMP_ExtiLine COMP EXTI Lines
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define COMP_EXTI_IT (0x00000001UL) /*!< EXTI line event with interruption */
|
|
||||||
#define COMP_EXTI_EVENT (0x00000002UL) /*!< EXTI line event only (without interruption) */
|
|
||||||
#define COMP_EXTI_RISING (0x00000010UL) /*!< EXTI line event on rising edge */
|
|
||||||
#define COMP_EXTI_FALLING (0x00000020UL) /*!< EXTI line event on falling edge */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private macros ------------------------------------------------------------*/
|
|
||||||
/** @defgroup COMP_Private_Macros COMP Private Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup COMP_GET_EXTI_LINE COMP private macros to get EXTI line associated with comparators
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/**
|
|
||||||
* @brief Get the specified EXTI line for a comparator instance.
|
|
||||||
* @param __INSTANCE__ specifies the COMP instance.
|
|
||||||
* @retval value of @ref COMP_ExtiLine
|
|
||||||
*/
|
|
||||||
#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 \
|
|
||||||
: COMP_EXTI_LINE_COMP2)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup COMP_IS_COMP_Private_Definitions COMP private macros to check input parameters
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define IS_COMP_WINDOWMODE(__WINDOWMODE__) (((__WINDOWMODE__) == COMP_WINDOWMODE_DISABLE) || \
|
|
||||||
((__WINDOWMODE__) == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON) )
|
|
||||||
|
|
||||||
#define IS_COMP_POWERMODE(__POWERMODE__) (((__POWERMODE__) == COMP_POWERMODE_HIGHSPEED) || \
|
|
||||||
((__POWERMODE__) == COMP_POWERMODE_MEDIUMSPEED) || \
|
|
||||||
((__POWERMODE__) == COMP_POWERMODE_ULTRALOWPOWER) )
|
|
||||||
|
|
||||||
#define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) ((__COMP_INSTANCE__ == COMP1) \
|
|
||||||
? (((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) || \
|
|
||||||
((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2) ) \
|
|
||||||
: \
|
|
||||||
(((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) || \
|
|
||||||
((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2) || \
|
|
||||||
((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO3) ) \
|
|
||||||
)
|
|
||||||
|
|
||||||
/* Note: On this STM32 series, comparator input minus parameters are */
|
|
||||||
/* the same on all COMP instances. */
|
|
||||||
/* However, comparator instance kept as macro parameter for */
|
|
||||||
/* compatibility with other STM32 families. */
|
|
||||||
#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) || \
|
|
||||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) || \
|
|
||||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) || \
|
|
||||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) || \
|
|
||||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC_CH1) || \
|
|
||||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) || \
|
|
||||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2) || \
|
|
||||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO3) || \
|
|
||||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO4))
|
|
||||||
|
|
||||||
#define IS_COMP_HYSTERESIS(__HYSTERESIS__) (((__HYSTERESIS__) == COMP_HYSTERESIS_NONE) || \
|
|
||||||
((__HYSTERESIS__) == COMP_HYSTERESIS_LOW) || \
|
|
||||||
((__HYSTERESIS__) == COMP_HYSTERESIS_MEDIUM) || \
|
|
||||||
((__HYSTERESIS__) == COMP_HYSTERESIS_HIGH))
|
|
||||||
|
|
||||||
#define IS_COMP_OUTPUTPOL(__POL__) (((__POL__) == COMP_OUTPUTPOL_NONINVERTED) || \
|
|
||||||
((__POL__) == COMP_OUTPUTPOL_INVERTED))
|
|
||||||
|
|
||||||
#define IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__) \
|
|
||||||
( ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) \
|
|
||||||
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5) \
|
|
||||||
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3) \
|
|
||||||
)
|
|
||||||
|
|
||||||
/* Note: Output blanking source common to all COMP instances */
|
|
||||||
/* Macro kept for compatibility with other STM32 series */
|
|
||||||
#define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \
|
|
||||||
(IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__))
|
|
||||||
|
|
||||||
|
|
||||||
#define IS_COMP_TRIGGERMODE(__MODE__) (((__MODE__) == COMP_TRIGGERMODE_NONE) || \
|
|
||||||
((__MODE__) == COMP_TRIGGERMODE_IT_RISING) || \
|
|
||||||
((__MODE__) == COMP_TRIGGERMODE_IT_FALLING) || \
|
|
||||||
((__MODE__) == COMP_TRIGGERMODE_IT_RISING_FALLING) || \
|
|
||||||
((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING) || \
|
|
||||||
((__MODE__) == COMP_TRIGGERMODE_EVENT_FALLING) || \
|
|
||||||
((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING_FALLING))
|
|
||||||
|
|
||||||
#define IS_COMP_OUTPUT_LEVEL(__OUTPUT_LEVEL__) (((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_LOW) || \
|
|
||||||
((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_HIGH))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/* Exported functions --------------------------------------------------------*/
|
|
||||||
/** @addtogroup COMP_Exported_Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup COMP_Exported_Functions_Group1
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Initialization and de-initialization functions **********************************/
|
|
||||||
HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp);
|
|
||||||
HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp);
|
|
||||||
void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp);
|
|
||||||
void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp);
|
|
||||||
|
|
||||||
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
|
|
||||||
/* Callbacks Register/UnRegister functions ***********************************/
|
|
||||||
HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID,
|
|
||||||
pCOMP_CallbackTypeDef pCallback);
|
|
||||||
HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID);
|
|
||||||
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* IO operation functions *****************************************************/
|
|
||||||
/** @addtogroup COMP_Exported_Functions_Group2
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp);
|
|
||||||
HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp);
|
|
||||||
void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Peripheral Control functions ************************************************/
|
|
||||||
/** @addtogroup COMP_Exported_Functions_Group3
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp);
|
|
||||||
uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp);
|
|
||||||
/* Callback in interrupt mode */
|
|
||||||
void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Peripheral State functions **************************************************/
|
|
||||||
/** @addtogroup COMP_Exported_Functions_Group4
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp);
|
|
||||||
uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* STM32WLxx_HAL_COMP_H */
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,340 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32wlxx_hal_conf.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief HAL configuration file.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
|
||||||
* All rights reserved.</center></h2>
|
|
||||||
*
|
|
||||||
* This software component is licensed by ST under BSD 3-Clause license,
|
|
||||||
* the "License"; You may not use this file except in compliance with the
|
|
||||||
* License. You may obtain a copy of the License at:
|
|
||||||
* opensource.org/licenses/BSD-3-Clause
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef STM32WLxx_HAL_CONF_H
|
|
||||||
#define STM32WLxx_HAL_CONF_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
|
||||||
|
|
||||||
/* ########################## Module Selection ############################## */
|
|
||||||
/**
|
|
||||||
* @brief This is the list of modules to be used in the HAL driver
|
|
||||||
*/
|
|
||||||
#define HAL_MODULE_ENABLED
|
|
||||||
#define HAL_ADC_MODULE_ENABLED
|
|
||||||
#define HAL_COMP_MODULE_ENABLED
|
|
||||||
#define HAL_CRC_MODULE_ENABLED
|
|
||||||
#define HAL_CRYP_MODULE_ENABLED
|
|
||||||
#define HAL_DAC_MODULE_ENABLED
|
|
||||||
#define HAL_GTZC_MODULE_ENABLED
|
|
||||||
#define HAL_HSEM_MODULE_ENABLED
|
|
||||||
#define HAL_I2C_MODULE_ENABLED
|
|
||||||
#define HAL_I2S_MODULE_ENABLED
|
|
||||||
#define HAL_IPCC_MODULE_ENABLED
|
|
||||||
#define HAL_IRDA_MODULE_ENABLED
|
|
||||||
#define HAL_IWDG_MODULE_ENABLED
|
|
||||||
#define HAL_LPTIM_MODULE_ENABLED
|
|
||||||
#define HAL_PKA_MODULE_ENABLED
|
|
||||||
#define HAL_RNG_MODULE_ENABLED
|
|
||||||
#define HAL_RTC_MODULE_ENABLED
|
|
||||||
#define HAL_SMARTCARD_MODULE_ENABLED
|
|
||||||
#define HAL_SMBUS_MODULE_ENABLED
|
|
||||||
#define HAL_SPI_MODULE_ENABLED
|
|
||||||
#define HAL_SUBGHZ_MODULE_ENABLED
|
|
||||||
#define HAL_TIM_MODULE_ENABLED
|
|
||||||
#define HAL_UART_MODULE_ENABLED
|
|
||||||
#define HAL_USART_MODULE_ENABLED
|
|
||||||
#define HAL_WWDG_MODULE_ENABLED
|
|
||||||
#define HAL_EXTI_MODULE_ENABLED
|
|
||||||
#define HAL_CORTEX_MODULE_ENABLED
|
|
||||||
#define HAL_DMA_MODULE_ENABLED
|
|
||||||
#define HAL_FLASH_MODULE_ENABLED
|
|
||||||
#define HAL_GPIO_MODULE_ENABLED
|
|
||||||
#define HAL_PWR_MODULE_ENABLED
|
|
||||||
#define HAL_RCC_MODULE_ENABLED
|
|
||||||
|
|
||||||
/* ########################## Register Callbacks selection ############################## */
|
|
||||||
/**
|
|
||||||
* @brief This is the list of modules where register callback can be used
|
|
||||||
*/
|
|
||||||
#define USE_HAL_ADC_REGISTER_CALLBACKS 0u
|
|
||||||
#define USE_HAL_COMP_REGISTER_CALLBACKS 0u
|
|
||||||
#define USE_HAL_CRYP_REGISTER_CALLBACKS 0u
|
|
||||||
#define USE_HAL_DAC_REGISTER_CALLBACKS 0u
|
|
||||||
#define USE_HAL_I2C_REGISTER_CALLBACKS 0u
|
|
||||||
#define USE_HAL_I2S_REGISTER_CALLBACKS 0u
|
|
||||||
#define USE_HAL_IRDA_REGISTER_CALLBACKS 0u
|
|
||||||
#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0u
|
|
||||||
#define USE_HAL_PKA_REGISTER_CALLBACKS 0u
|
|
||||||
#define USE_HAL_RNG_REGISTER_CALLBACKS 0u
|
|
||||||
#define USE_HAL_RTC_REGISTER_CALLBACKS 0u
|
|
||||||
#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
|
|
||||||
#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0u
|
|
||||||
#define USE_HAL_SPI_REGISTER_CALLBACKS 0u
|
|
||||||
#define USE_HAL_SUBGHZ_REGISTER_CALLBACKS 0u
|
|
||||||
#define USE_HAL_TIM_REGISTER_CALLBACKS 0u
|
|
||||||
#define USE_HAL_UART_REGISTER_CALLBACKS 0u
|
|
||||||
#define USE_HAL_USART_REGISTER_CALLBACKS 0u
|
|
||||||
#define USE_HAL_WWDG_REGISTER_CALLBACKS 0u
|
|
||||||
|
|
||||||
/* ########################## Oscillator Values adaptation ####################*/
|
|
||||||
/**
|
|
||||||
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
|
|
||||||
* This value is used by the RCC HAL module to compute the system frequency
|
|
||||||
* (when HSE is used as system clock source, directly or through the PLL).
|
|
||||||
*/
|
|
||||||
|
|
||||||
#if !defined (HSE_VALUE)
|
|
||||||
#define HSE_VALUE 32000000UL /*!< Value of the External oscillator in Hz */
|
|
||||||
#endif /* HSE_VALUE */
|
|
||||||
|
|
||||||
#if !defined (HSE_STARTUP_TIMEOUT)
|
|
||||||
#define HSE_STARTUP_TIMEOUT 100UL /*!< Time out for HSE start up, in ms */
|
|
||||||
#endif /* HSE_STARTUP_TIMEOUT */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Internal Multiple Speed oscillator (MSI) default value.
|
|
||||||
* This value is the default MSI range value after Reset.
|
|
||||||
*/
|
|
||||||
#if !defined (MSI_VALUE)
|
|
||||||
#define MSI_VALUE 4000000UL /*!< Value of the Internal oscillator in Hz*/
|
|
||||||
#endif /* MSI_VALUE */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Internal High Speed oscillator (HSI) value.
|
|
||||||
* This value is used by the RCC HAL module to compute the system frequency
|
|
||||||
* (when HSI is used as system clock source, directly or through the PLL).
|
|
||||||
*/
|
|
||||||
#if !defined (HSI_VALUE)
|
|
||||||
#define HSI_VALUE 16000000UL /*!< Value of the Internal oscillator in Hz*/
|
|
||||||
#endif /* HSI_VALUE */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Internal Low Speed oscillator (LSI) value.
|
|
||||||
*/
|
|
||||||
#if !defined (LSI_VALUE)
|
|
||||||
#define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz*/
|
|
||||||
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
|
|
||||||
The real value may vary depending on the variations
|
|
||||||
in voltage and temperature. */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief External Low Speed oscillator (LSE) value.
|
|
||||||
* This value is used by the UART, RTC HAL module to compute the system frequency
|
|
||||||
*/
|
|
||||||
#if !defined (LSE_VALUE)
|
|
||||||
#define LSE_VALUE 32768UL /*!< Value of the External oscillator in Hz*/
|
|
||||||
#endif /* LSE_VALUE */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Internal Multiple Speed oscillator (HSI48) default value.
|
|
||||||
* This value is the default HSI48 range value after Reset.
|
|
||||||
*/
|
|
||||||
#if !defined (HSI48_VALUE)
|
|
||||||
#define HSI48_VALUE 48000000UL /*!< Value of the Internal oscillator in Hz*/
|
|
||||||
#endif /* HSI48_VALUE */
|
|
||||||
|
|
||||||
#if !defined (LSE_STARTUP_TIMEOUT)
|
|
||||||
#define LSE_STARTUP_TIMEOUT 5000UL /*!< Time out for LSE start up, in ms */
|
|
||||||
#endif /* LSE_STARTUP_TIMEOUT */
|
|
||||||
|
|
||||||
|
|
||||||
/* Tip: To avoid modifying this file each time you need to use different HSE,
|
|
||||||
=== you can define the HSE value in your toolchain compiler preprocessor. */
|
|
||||||
|
|
||||||
/* ########################### System Configuration ######################### */
|
|
||||||
/**
|
|
||||||
* @brief This is the HAL system configuration section
|
|
||||||
*/
|
|
||||||
#define VDD_VALUE 3300U /*!< Value of VDD in mv */
|
|
||||||
#define TICK_INT_PRIORITY ((1uL <<__NVIC_PRIO_BITS) - 1uL) /*!< tick interrupt priority (lowest by default) */
|
|
||||||
#define USE_RTOS 0U
|
|
||||||
#define PREFETCH_ENABLE 0U
|
|
||||||
#define INSTRUCTION_CACHE_ENABLE 1U
|
|
||||||
#define DATA_CACHE_ENABLE 1U
|
|
||||||
|
|
||||||
/* ########################## Assert Selection ############################## */
|
|
||||||
/**
|
|
||||||
* @brief Uncomment the line below to expanse the "assert_param" macro in the
|
|
||||||
* HAL drivers code
|
|
||||||
*/
|
|
||||||
/* #define USE_FULL_ASSERT 1 */
|
|
||||||
|
|
||||||
/* ################## SPI peripheral configuration ########################## */
|
|
||||||
|
|
||||||
/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
|
|
||||||
* Activated: CRC code is present inside driver
|
|
||||||
* Deactivated: CRC code cleaned from driver
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define USE_SPI_CRC 1U
|
|
||||||
|
|
||||||
/* ################## CRYP peripheral configuration ########################## */
|
|
||||||
|
|
||||||
#define USE_HAL_CRYP_SUSPEND_RESUME 1U
|
|
||||||
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
/**
|
|
||||||
* @brief Include module's header file
|
|
||||||
*/
|
|
||||||
#ifdef HAL_DMA_MODULE_ENABLED
|
|
||||||
#include "stm32wlxx_hal_dma.h"
|
|
||||||
#endif /* HAL_DMA_MODULE_ENABLED */
|
|
||||||
|
|
||||||
#ifdef HAL_ADC_MODULE_ENABLED
|
|
||||||
#include "stm32wlxx_hal_adc.h"
|
|
||||||
#endif /* HAL_ADC_MODULE_ENABLED */
|
|
||||||
|
|
||||||
#ifdef HAL_COMP_MODULE_ENABLED
|
|
||||||
#include "stm32wlxx_hal_comp.h"
|
|
||||||
#endif /* HAL_COMP_MODULE_ENABLED */
|
|
||||||
|
|
||||||
#ifdef HAL_CORTEX_MODULE_ENABLED
|
|
||||||
#include "stm32wlxx_hal_cortex.h"
|
|
||||||
#endif /* HAL_CORTEX_MODULE_ENABLED */
|
|
||||||
|
|
||||||
#ifdef HAL_CRC_MODULE_ENABLED
|
|
||||||
#include "stm32wlxx_hal_crc.h"
|
|
||||||
#endif /* HAL_CRC_MODULE_ENABLED */
|
|
||||||
|
|
||||||
#ifdef HAL_CRYP_MODULE_ENABLED
|
|
||||||
#include "stm32wlxx_hal_cryp.h"
|
|
||||||
#endif /* HAL_CRYP_MODULE_ENABLED */
|
|
||||||
|
|
||||||
#ifdef HAL_DAC_MODULE_ENABLED
|
|
||||||
#include "stm32wlxx_hal_dac.h"
|
|
||||||
#endif /* HAL_DAC_MODULE_ENABLED */
|
|
||||||
|
|
||||||
#ifdef HAL_EXTI_MODULE_ENABLED
|
|
||||||
#include "stm32wlxx_hal_exti.h"
|
|
||||||
#endif /* HAL_EXTI_MODULE_ENABLED */
|
|
||||||
|
|
||||||
#ifdef HAL_FLASH_MODULE_ENABLED
|
|
||||||
#include "stm32wlxx_hal_flash.h"
|
|
||||||
#endif /* HAL_FLASH_MODULE_ENABLED */
|
|
||||||
|
|
||||||
#ifdef HAL_GPIO_MODULE_ENABLED
|
|
||||||
#include "stm32wlxx_hal_gpio.h"
|
|
||||||
#endif /* HAL_GPIO_MODULE_ENABLED */
|
|
||||||
|
|
||||||
#ifdef HAL_GTZC_MODULE_ENABLED
|
|
||||||
#include "stm32wlxx_hal_gtzc.h"
|
|
||||||
#endif /* HAL_GTZC_MODULE_ENABLED */
|
|
||||||
|
|
||||||
#ifdef HAL_HSEM_MODULE_ENABLED
|
|
||||||
#include "stm32wlxx_hal_hsem.h"
|
|
||||||
#endif /* HAL_HSEM_MODULE_ENABLED */
|
|
||||||
|
|
||||||
#ifdef HAL_I2C_MODULE_ENABLED
|
|
||||||
#include "stm32wlxx_hal_i2c.h"
|
|
||||||
#endif /* HAL_I2C_MODULE_ENABLED */
|
|
||||||
|
|
||||||
#ifdef HAL_I2S_MODULE_ENABLED
|
|
||||||
#include "stm32wlxx_hal_i2s.h"
|
|
||||||
#endif /* HAL_I2S_MODULE_ENABLED */
|
|
||||||
|
|
||||||
#ifdef HAL_IPCC_MODULE_ENABLED
|
|
||||||
#include "stm32wlxx_hal_ipcc.h"
|
|
||||||
#endif /* HAL_IPCC_MODULE_ENABLED */
|
|
||||||
|
|
||||||
#ifdef HAL_IRDA_MODULE_ENABLED
|
|
||||||
#include "stm32wlxx_hal_irda.h"
|
|
||||||
#endif /* HAL_IRDA_MODULE_ENABLED */
|
|
||||||
|
|
||||||
#ifdef HAL_IWDG_MODULE_ENABLED
|
|
||||||
#include "stm32wlxx_hal_iwdg.h"
|
|
||||||
#endif /* HAL_IWDG_MODULE_ENABLED */
|
|
||||||
|
|
||||||
#ifdef HAL_LPTIM_MODULE_ENABLED
|
|
||||||
#include "stm32wlxx_hal_lptim.h"
|
|
||||||
#endif /* HAL_LPTIM_MODULE_ENABLED */
|
|
||||||
|
|
||||||
#ifdef HAL_PKA_MODULE_ENABLED
|
|
||||||
#include "stm32wlxx_hal_pka.h"
|
|
||||||
#endif /* HAL_PKA_MODULE_ENABLED */
|
|
||||||
|
|
||||||
#ifdef HAL_PWR_MODULE_ENABLED
|
|
||||||
#include "stm32wlxx_hal_pwr.h"
|
|
||||||
#endif /* HAL_PWR_MODULE_ENABLED */
|
|
||||||
|
|
||||||
#ifdef HAL_RCC_MODULE_ENABLED
|
|
||||||
#include "stm32wlxx_hal_rcc.h"
|
|
||||||
#endif /* HAL_RCC_MODULE_ENABLED */
|
|
||||||
|
|
||||||
#ifdef HAL_RNG_MODULE_ENABLED
|
|
||||||
#include "stm32wlxx_hal_rng.h"
|
|
||||||
#endif /* HAL_RNG_MODULE_ENABLED */
|
|
||||||
|
|
||||||
#ifdef HAL_RTC_MODULE_ENABLED
|
|
||||||
#include "stm32wlxx_hal_rtc.h"
|
|
||||||
#endif /* HAL_RTC_MODULE_ENABLED */
|
|
||||||
|
|
||||||
#ifdef HAL_SMARTCARD_MODULE_ENABLED
|
|
||||||
#include "stm32wlxx_hal_smartcard.h"
|
|
||||||
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
|
|
||||||
|
|
||||||
#ifdef HAL_SMBUS_MODULE_ENABLED
|
|
||||||
#include "stm32wlxx_hal_smbus.h"
|
|
||||||
#endif /* HAL_SMBUS_MODULE_ENABLED */
|
|
||||||
|
|
||||||
#ifdef HAL_SPI_MODULE_ENABLED
|
|
||||||
#include "stm32wlxx_hal_spi.h"
|
|
||||||
#endif /* HAL_SPI_MODULE_ENABLED */
|
|
||||||
|
|
||||||
#ifdef HAL_SUBGHZ_MODULE_ENABLED
|
|
||||||
#include "stm32wlxx_hal_subghz.h"
|
|
||||||
#endif /* HAL_SUBGHZ_MODULE_ENABLED */
|
|
||||||
|
|
||||||
#ifdef HAL_TIM_MODULE_ENABLED
|
|
||||||
#include "stm32wlxx_hal_tim.h"
|
|
||||||
#endif /* HAL_TIM_MODULE_ENABLED */
|
|
||||||
|
|
||||||
#ifdef HAL_UART_MODULE_ENABLED
|
|
||||||
#include "stm32wlxx_hal_uart.h"
|
|
||||||
#endif /* HAL_UART_MODULE_ENABLED */
|
|
||||||
|
|
||||||
#ifdef HAL_USART_MODULE_ENABLED
|
|
||||||
#include "stm32wlxx_hal_usart.h"
|
|
||||||
#endif /* HAL_USART_MODULE_ENABLED */
|
|
||||||
|
|
||||||
#ifdef HAL_WWDG_MODULE_ENABLED
|
|
||||||
#include "stm32wlxx_hal_wwdg.h"
|
|
||||||
#endif /* HAL_WWDG_MODULE_ENABLED */
|
|
||||||
|
|
||||||
/* Exported macro ------------------------------------------------------------*/
|
|
||||||
#ifdef USE_FULL_ASSERT
|
|
||||||
/**
|
|
||||||
* @brief The assert_param macro is used for function's parameters check.
|
|
||||||
* @param expr If expr is false, it calls assert_failed function
|
|
||||||
* which reports the name of the source file and the source
|
|
||||||
* line number of the call that failed.
|
|
||||||
* If expr is true, it returns no value.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
|
|
||||||
/* Exported functions ------------------------------------------------------- */
|
|
||||||
void assert_failed(uint8_t* file, uint32_t line);
|
|
||||||
#else
|
|
||||||
#define assert_param(expr) ((void)0U)
|
|
||||||
#endif /* USE_FULL_ASSERT */
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* STM32WLxx_HAL_CONF_H */
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,466 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32wlxx_hal_cortex.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief Header file of CORTEX HAL module.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
|
||||||
* All rights reserved.</center></h2>
|
|
||||||
*
|
|
||||||
* This software component is licensed by ST under BSD 3-Clause license,
|
|
||||||
* the "License"; You may not use this file except in compliance with the
|
|
||||||
* License. You may obtain a copy of the License at:
|
|
||||||
* opensource.org/licenses/BSD-3-Clause
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef __STM32WLxx_HAL_CORTEX_H
|
|
||||||
#define __STM32WLxx_HAL_CORTEX_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32wlxx_hal_def.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32WLxx_HAL_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup CORTEX CORTEX
|
|
||||||
* @brief CORTEX HAL module driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
/** @defgroup CORTEX_Exported_Types CORTEX Exported Types
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#if (__MPU_PRESENT == 1)
|
|
||||||
/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
|
|
||||||
* @brief MPU Region initialization structure
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint8_t Enable; /*!< Specifies the status of the region.
|
|
||||||
This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
|
|
||||||
uint8_t Number; /*!< Specifies the number of the region to protect.
|
|
||||||
This parameter can be a value of @ref CORTEX_MPU_Region_Number */
|
|
||||||
uint32_t BaseAddress; /*!< Specifies the base address of the region to protect.
|
|
||||||
*/
|
|
||||||
uint8_t Size; /*!< Specifies the size of the region to protect.
|
|
||||||
This parameter can be a value of @ref CORTEX_MPU_Region_Size */
|
|
||||||
uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
|
|
||||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
|
|
||||||
uint8_t TypeExtField; /*!< Specifies the TEX field level.
|
|
||||||
This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
|
|
||||||
uint8_t AccessPermission; /*!< Specifies the region access permission type.
|
|
||||||
This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
|
|
||||||
uint8_t DisableExec; /*!< Specifies the instruction access status.
|
|
||||||
This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
|
|
||||||
uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
|
|
||||||
This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
|
|
||||||
uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
|
|
||||||
This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
|
|
||||||
uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
|
|
||||||
This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
|
|
||||||
} MPU_Region_InitTypeDef;
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
#endif /* __MPU_PRESENT */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
|
||||||
|
|
||||||
/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#ifdef CORE_CM0PLUS
|
|
||||||
#else
|
|
||||||
/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define NVIC_PRIORITYGROUP_0 (0x00000007U) /*!< 0 bit for pre-emption priority,
|
|
||||||
4 bits for subpriority */
|
|
||||||
#define NVIC_PRIORITYGROUP_1 (0x00000006U) /*!< 1 bit for pre-emption priority,
|
|
||||||
3 bits for subpriority */
|
|
||||||
#define NVIC_PRIORITYGROUP_2 (0x00000005U) /*!< 2 bits for pre-emption priority,
|
|
||||||
2 bits for subpriority */
|
|
||||||
#define NVIC_PRIORITYGROUP_3 (0x00000004U) /*!< 3 bits for pre-emption priority,
|
|
||||||
1 bit for subpriority */
|
|
||||||
#define NVIC_PRIORITYGROUP_4 (0x00000003U) /*!< 4 bits for pre-emption priority,
|
|
||||||
0 bit for subpriority */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
#endif /* CORE_CM0PLUS */
|
|
||||||
|
|
||||||
/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
|
|
||||||
#define SYSTICK_CLKSOURCE_HCLK 0x00000004U
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#if (__MPU_PRESENT == 1)
|
|
||||||
/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U
|
|
||||||
#define MPU_HARDFAULT_NMI (MPU_CTRL_HFNMIENA_Msk)
|
|
||||||
#define MPU_PRIVILEGED_DEFAULT (MPU_CTRL_PRIVDEFENA_Msk)
|
|
||||||
#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define MPU_REGION_ENABLE ((uint8_t)0x01)
|
|
||||||
#define MPU_REGION_DISABLE ((uint8_t)0x00)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
|
|
||||||
#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
|
|
||||||
#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
|
|
||||||
#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
|
|
||||||
#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define MPU_TEX_LEVEL0 ((uint8_t)0x00)
|
|
||||||
#define MPU_TEX_LEVEL1 ((uint8_t)0x01)
|
|
||||||
#define MPU_TEX_LEVEL2 ((uint8_t)0x02)
|
|
||||||
#define MPU_TEX_LEVEL4 ((uint8_t)0x04)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#if defined(CORE_CM0PLUS)
|
|
||||||
#else
|
|
||||||
#define MPU_REGION_SIZE_32B ((uint8_t)0x04)
|
|
||||||
#define MPU_REGION_SIZE_64B ((uint8_t)0x05)
|
|
||||||
#define MPU_REGION_SIZE_128B ((uint8_t)0x06)
|
|
||||||
#endif
|
|
||||||
#define MPU_REGION_SIZE_256B ((uint8_t)0x07)
|
|
||||||
#define MPU_REGION_SIZE_512B ((uint8_t)0x08)
|
|
||||||
#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
|
|
||||||
#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
|
|
||||||
#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
|
|
||||||
#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
|
|
||||||
#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
|
|
||||||
#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
|
|
||||||
#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
|
|
||||||
#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
|
|
||||||
#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
|
|
||||||
#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
|
|
||||||
#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
|
|
||||||
#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
|
|
||||||
#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
|
|
||||||
#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
|
|
||||||
#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
|
|
||||||
#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
|
|
||||||
#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
|
|
||||||
#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
|
|
||||||
#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
|
|
||||||
#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
|
|
||||||
#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
|
|
||||||
#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
|
|
||||||
#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
|
|
||||||
#define MPU_REGION_PRIV_RW ((uint8_t)0x01)
|
|
||||||
#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
|
|
||||||
#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
|
|
||||||
#define MPU_REGION_PRIV_RO ((uint8_t)0x05)
|
|
||||||
#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
|
|
||||||
#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
|
|
||||||
#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
|
|
||||||
#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
|
|
||||||
#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
|
|
||||||
#define MPU_REGION_NUMBER5 ((uint8_t)0x05)
|
|
||||||
#define MPU_REGION_NUMBER6 ((uint8_t)0x06)
|
|
||||||
#define MPU_REGION_NUMBER7 ((uint8_t)0x07)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
#endif /* __MPU_PRESENT */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported macros -----------------------------------------------------------*/
|
|
||||||
/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported functions --------------------------------------------------------*/
|
|
||||||
/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions
|
|
||||||
* @brief Initialization and Configuration functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Initialization and Configuration functions *****************************/
|
|
||||||
#ifdef CORE_CM0PLUS
|
|
||||||
#else
|
|
||||||
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
|
|
||||||
#endif /* CORE_CM0PLUS */
|
|
||||||
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
|
|
||||||
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
|
|
||||||
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
|
|
||||||
void HAL_NVIC_SystemReset(void);
|
|
||||||
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
|
|
||||||
* @brief Cortex control functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Peripheral Control functions *************************************************/
|
|
||||||
#ifdef CORE_CM0PLUS
|
|
||||||
uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn);
|
|
||||||
#else
|
|
||||||
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority);
|
|
||||||
uint32_t HAL_NVIC_GetPriorityGrouping(void);
|
|
||||||
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
|
|
||||||
#endif /* CORE_CM0PLUS */
|
|
||||||
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
|
|
||||||
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
|
|
||||||
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
|
|
||||||
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
|
|
||||||
void HAL_SYSTICK_IRQHandler(void);
|
|
||||||
void HAL_SYSTICK_Callback(void);
|
|
||||||
|
|
||||||
#if (__MPU_PRESENT == 1U)
|
|
||||||
void HAL_MPU_Enable(uint32_t MPU_Control);
|
|
||||||
void HAL_MPU_Disable(void);
|
|
||||||
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
|
|
||||||
#endif /* __MPU_PRESENT */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private types -------------------------------------------------------------*/
|
|
||||||
/* Private variables ---------------------------------------------------------*/
|
|
||||||
/* Private constants ---------------------------------------------------------*/
|
|
||||||
/* Private macros ------------------------------------------------------------*/
|
|
||||||
/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#ifdef CORE_CM0PLUS
|
|
||||||
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x4U)
|
|
||||||
#else
|
|
||||||
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
|
|
||||||
((GROUP) == NVIC_PRIORITYGROUP_1) || \
|
|
||||||
((GROUP) == NVIC_PRIORITYGROUP_2) || \
|
|
||||||
((GROUP) == NVIC_PRIORITYGROUP_3) || \
|
|
||||||
((GROUP) == NVIC_PRIORITYGROUP_4))
|
|
||||||
|
|
||||||
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
|
|
||||||
|
|
||||||
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
|
|
||||||
#endif /* CORE_CM0PLUS */
|
|
||||||
|
|
||||||
#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) > SysTick_IRQn)
|
|
||||||
|
|
||||||
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
|
|
||||||
((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
|
|
||||||
|
|
||||||
#if (__MPU_PRESENT == 1)
|
|
||||||
#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
|
|
||||||
((STATE) == MPU_REGION_DISABLE))
|
|
||||||
|
|
||||||
#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
|
|
||||||
((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
|
|
||||||
|
|
||||||
#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
|
|
||||||
((STATE) == MPU_ACCESS_NOT_SHAREABLE))
|
|
||||||
|
|
||||||
#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
|
|
||||||
((STATE) == MPU_ACCESS_NOT_CACHEABLE))
|
|
||||||
|
|
||||||
#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
|
|
||||||
((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
|
|
||||||
|
|
||||||
#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
|
|
||||||
((TYPE) == MPU_TEX_LEVEL1) || \
|
|
||||||
((TYPE) == MPU_TEX_LEVEL2) || \
|
|
||||||
((TYPE) == MPU_TEX_LEVEL4))
|
|
||||||
|
|
||||||
#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
|
|
||||||
((TYPE) == MPU_REGION_PRIV_RW) || \
|
|
||||||
((TYPE) == MPU_REGION_PRIV_RW_URO) || \
|
|
||||||
((TYPE) == MPU_REGION_FULL_ACCESS) || \
|
|
||||||
((TYPE) == MPU_REGION_PRIV_RO) || \
|
|
||||||
((TYPE) == MPU_REGION_PRIV_RO_URO))
|
|
||||||
|
|
||||||
#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
|
|
||||||
((NUMBER) == MPU_REGION_NUMBER1) || \
|
|
||||||
((NUMBER) == MPU_REGION_NUMBER2) || \
|
|
||||||
((NUMBER) == MPU_REGION_NUMBER3) || \
|
|
||||||
((NUMBER) == MPU_REGION_NUMBER4) || \
|
|
||||||
((NUMBER) == MPU_REGION_NUMBER5) || \
|
|
||||||
((NUMBER) == MPU_REGION_NUMBER6) || \
|
|
||||||
((NUMBER) == MPU_REGION_NUMBER7))
|
|
||||||
|
|
||||||
#if defined(CORE_CM0PLUS)
|
|
||||||
#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_256B) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_512B) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_1KB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_2KB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_4KB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_8KB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_16KB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_32KB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_64KB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_128KB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_256KB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_512KB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_1MB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_2MB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_4MB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_8MB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_16MB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_32MB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_64MB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_128MB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_256MB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_512MB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_1GB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_2GB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_4GB))
|
|
||||||
#else
|
|
||||||
#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_64B) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_128B) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_256B) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_512B) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_1KB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_2KB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_4KB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_8KB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_16KB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_32KB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_64KB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_128KB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_256KB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_512KB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_1MB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_2MB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_4MB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_8MB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_16MB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_32MB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_64MB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_128MB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_256MB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_512MB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_1GB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_2GB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_4GB))
|
|
||||||
#endif
|
|
||||||
#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU)
|
|
||||||
#endif /* __MPU_PRESENT */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private functions ---------------------------------------------------------*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* __STM32WLxx_HAL_CORTEX_H */
|
|
||||||
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
||||||
|
|
@ -1,344 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32wlxx_hal_crc.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief Header file of CRC HAL module.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
|
||||||
* All rights reserved.</center></h2>
|
|
||||||
*
|
|
||||||
* This software component is licensed by ST under BSD 3-Clause license,
|
|
||||||
* the "License"; You may not use this file except in compliance with the
|
|
||||||
* License. You may obtain a copy of the License at:
|
|
||||||
* opensource.org/licenses/BSD-3-Clause
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef STM32WLxx_HAL_CRC_H
|
|
||||||
#define STM32WLxx_HAL_CRC_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32wlxx_hal_def.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32WLxx_HAL_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup CRC
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
/** @defgroup CRC_Exported_Types CRC Exported Types
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief CRC HAL State Structure definition
|
|
||||||
*/
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
HAL_CRC_STATE_RESET = 0x00U, /*!< CRC not yet initialized or disabled */
|
|
||||||
HAL_CRC_STATE_READY = 0x01U, /*!< CRC initialized and ready for use */
|
|
||||||
HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */
|
|
||||||
HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */
|
|
||||||
HAL_CRC_STATE_ERROR = 0x04U /*!< CRC error state */
|
|
||||||
} HAL_CRC_StateTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief CRC Init Structure definition
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.
|
|
||||||
If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default
|
|
||||||
X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1.
|
|
||||||
In that case, there is no need to set GeneratingPolynomial field.
|
|
||||||
If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set. */
|
|
||||||
|
|
||||||
uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used.
|
|
||||||
If set to DEFAULT_INIT_VALUE_ENABLE, resort to default
|
|
||||||
0xFFFFFFFF value. In that case, there is no need to set InitValue field.
|
|
||||||
If otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */
|
|
||||||
|
|
||||||
uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree
|
|
||||||
respectively equal to 7, 8, 16 or 32. This field is written in normal representation,
|
|
||||||
e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65.
|
|
||||||
No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE. */
|
|
||||||
|
|
||||||
uint32_t CRCLength; /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length.
|
|
||||||
Value can be either one of
|
|
||||||
@arg @ref CRC_POLYLENGTH_32B (32-bit CRC),
|
|
||||||
@arg @ref CRC_POLYLENGTH_16B (16-bit CRC),
|
|
||||||
@arg @ref CRC_POLYLENGTH_8B (8-bit CRC),
|
|
||||||
@arg @ref CRC_POLYLENGTH_7B (7-bit CRC). */
|
|
||||||
|
|
||||||
uint32_t InitValue; /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse
|
|
||||||
is set to DEFAULT_INIT_VALUE_ENABLE. */
|
|
||||||
|
|
||||||
uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode.
|
|
||||||
Can be either one of the following values
|
|
||||||
@arg @ref CRC_INPUTDATA_INVERSION_NONE no input data inversion
|
|
||||||
@arg @ref CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2
|
|
||||||
@arg @ref CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C
|
|
||||||
@arg @ref CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */
|
|
||||||
|
|
||||||
uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
|
|
||||||
Can be either
|
|
||||||
@arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion,
|
|
||||||
@arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted into 0x22CC4488 */
|
|
||||||
} CRC_InitTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief CRC Handle Structure definition
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
CRC_TypeDef *Instance; /*!< Register base address */
|
|
||||||
|
|
||||||
CRC_InitTypeDef Init; /*!< CRC configuration parameters */
|
|
||||||
|
|
||||||
HAL_LockTypeDef Lock; /*!< CRC Locking object */
|
|
||||||
|
|
||||||
__IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */
|
|
||||||
|
|
||||||
uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format.
|
|
||||||
Can be either
|
|
||||||
@arg @ref CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes (8-bit data)
|
|
||||||
@arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of half-words (16-bit data)
|
|
||||||
@arg @ref CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words (32-bit data)
|
|
||||||
|
|
||||||
Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error
|
|
||||||
must occur if InputBufferFormat is not one of the three values listed above */
|
|
||||||
} CRC_HandleTypeDef;
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
|
||||||
/** @defgroup CRC_Exported_Constants CRC Exported Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup CRC_Default_Polynomial_Value Default CRC generating polynomial
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define DEFAULT_CRC32_POLY 0x04C11DB7U /*!< X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1 */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup CRC_Default_InitValue Default CRC computation initialization value
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define DEFAULT_CRC_INITVALUE 0xFFFFFFFFU /*!< Initial CRC default value */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U) /*!< Enable default generating polynomial 0x04C11DB7 */
|
|
||||||
#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U) /*!< Disable default generating polynomial 0x04C11DB7 */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup CRC_Default_InitValue_Use Indicates whether or not default init value is used
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U) /*!< Enable initial CRC default value */
|
|
||||||
#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U) /*!< Disable initial CRC default value */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the peripheral
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define CRC_POLYLENGTH_32B 0x00000000U /*!< Resort to a 32-bit long generating polynomial */
|
|
||||||
#define CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0 /*!< Resort to a 16-bit long generating polynomial */
|
|
||||||
#define CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1 /*!< Resort to a 8-bit long generating polynomial */
|
|
||||||
#define CRC_POLYLENGTH_7B CRC_CR_POLYSIZE /*!< Resort to a 7-bit long generating polynomial */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define HAL_CRC_LENGTH_32B 32U /*!< 32-bit long CRC */
|
|
||||||
#define HAL_CRC_LENGTH_16B 16U /*!< 16-bit long CRC */
|
|
||||||
#define HAL_CRC_LENGTH_8B 8U /*!< 8-bit long CRC */
|
|
||||||
#define HAL_CRC_LENGTH_7B 7U /*!< 7-bit long CRC */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup CRC_Input_Buffer_Format Input Buffer Format
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but
|
|
||||||
* an error is triggered in HAL_CRC_Init() if InputDataFormat field is set
|
|
||||||
* to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for
|
|
||||||
* the CRC APIs to provide a correct result */
|
|
||||||
#define CRC_INPUTDATA_FORMAT_UNDEFINED 0x00000000U /*!< Undefined input data format */
|
|
||||||
#define CRC_INPUTDATA_FORMAT_BYTES 0x00000001U /*!< Input data in byte format */
|
|
||||||
#define CRC_INPUTDATA_FORMAT_HALFWORDS 0x00000002U /*!< Input data in half-word format */
|
|
||||||
#define CRC_INPUTDATA_FORMAT_WORDS 0x00000003U /*!< Input data in word format */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup CRC_Aliases CRC API aliases
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */
|
|
||||||
#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported macros -----------------------------------------------------------*/
|
|
||||||
/** @defgroup CRC_Exported_Macros CRC Exported Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @brief Reset CRC handle state.
|
|
||||||
* @param __HANDLE__ CRC handle.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Reset CRC Data Register.
|
|
||||||
* @param __HANDLE__ CRC handle
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Set CRC INIT non-default value
|
|
||||||
* @param __HANDLE__ CRC handle
|
|
||||||
* @param __INIT__ 32-bit initial value
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Store data in the Independent Data (ID) register.
|
|
||||||
* @param __HANDLE__ CRC handle
|
|
||||||
* @param __VALUE__ Value to be stored in the ID register
|
|
||||||
* @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Return the data stored in the Independent Data (ID) register.
|
|
||||||
* @param __HANDLE__ CRC handle
|
|
||||||
* @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits
|
|
||||||
* @retval Value of the ID register
|
|
||||||
*/
|
|
||||||
#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/* Private macros --------------------------------------------------------*/
|
|
||||||
/** @defgroup CRC_Private_Macros CRC Private Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
|
|
||||||
((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))
|
|
||||||
|
|
||||||
|
|
||||||
#define IS_DEFAULT_INIT_VALUE(VALUE) (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
|
|
||||||
((VALUE) == DEFAULT_INIT_VALUE_DISABLE))
|
|
||||||
|
|
||||||
#define IS_CRC_POL_LENGTH(LENGTH) (((LENGTH) == CRC_POLYLENGTH_32B) || \
|
|
||||||
((LENGTH) == CRC_POLYLENGTH_16B) || \
|
|
||||||
((LENGTH) == CRC_POLYLENGTH_8B) || \
|
|
||||||
((LENGTH) == CRC_POLYLENGTH_7B))
|
|
||||||
|
|
||||||
#define IS_CRC_INPUTDATA_FORMAT(FORMAT) (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES) || \
|
|
||||||
((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
|
|
||||||
((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Include CRC HAL Extended module */
|
|
||||||
#include "stm32wlxx_hal_crc_ex.h"
|
|
||||||
|
|
||||||
/* Exported functions --------------------------------------------------------*/
|
|
||||||
/** @defgroup CRC_Exported_Functions CRC Exported Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Initialization and de-initialization functions ****************************/
|
|
||||||
/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
|
|
||||||
HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc);
|
|
||||||
void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
|
|
||||||
void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Peripheral Control functions ***********************************************/
|
|
||||||
/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
|
|
||||||
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Peripheral State and Error functions ***************************************/
|
|
||||||
/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* STM32WLxx_HAL_CRC_H */
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,153 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32wlxx_hal_crc_ex.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief Header file of CRC HAL extended module.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
|
||||||
* All rights reserved.</center></h2>
|
|
||||||
*
|
|
||||||
* This software component is licensed by ST under BSD 3-Clause license,
|
|
||||||
* the "License"; You may not use this file except in compliance with the
|
|
||||||
* License. You may obtain a copy of the License at:
|
|
||||||
* opensource.org/licenses/BSD-3-Clause
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef STM32WLxx_HAL_CRC_EX_H
|
|
||||||
#define STM32WLxx_HAL_CRC_EX_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32wlxx_hal_def.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32WLxx_HAL_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup CRCEx
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
|
||||||
/** @defgroup CRCEx_Exported_Constants CRC Extended Exported Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup CRCEx_Input_Data_Inversion Input Data Inversion Modes
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define CRC_INPUTDATA_INVERSION_NONE 0x00000000U /*!< No input data inversion */
|
|
||||||
#define CRC_INPUTDATA_INVERSION_BYTE CRC_CR_REV_IN_0 /*!< Byte-wise input data inversion */
|
|
||||||
#define CRC_INPUTDATA_INVERSION_HALFWORD CRC_CR_REV_IN_1 /*!< HalfWord-wise input data inversion */
|
|
||||||
#define CRC_INPUTDATA_INVERSION_WORD CRC_CR_REV_IN /*!< Word-wise input data inversion */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define CRC_OUTPUTDATA_INVERSION_DISABLE 0x00000000U /*!< No output data inversion */
|
|
||||||
#define CRC_OUTPUTDATA_INVERSION_ENABLE CRC_CR_REV_OUT /*!< Bit-wise output data inversion */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported macro ------------------------------------------------------------*/
|
|
||||||
/** @defgroup CRCEx_Exported_Macros CRC Extended Exported Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Set CRC output reversal
|
|
||||||
* @param __HANDLE__ CRC handle
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Unset CRC output reversal
|
|
||||||
* @param __HANDLE__ CRC handle
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Set CRC non-default polynomial
|
|
||||||
* @param __HANDLE__ CRC handle
|
|
||||||
* @param __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private macros --------------------------------------------------------*/
|
|
||||||
/** @defgroup CRCEx_Private_Macros CRC Extended Private Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define IS_CRC_INPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_INPUTDATA_INVERSION_NONE) || \
|
|
||||||
((MODE) == CRC_INPUTDATA_INVERSION_BYTE) || \
|
|
||||||
((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
|
|
||||||
((MODE) == CRC_INPUTDATA_INVERSION_WORD))
|
|
||||||
|
|
||||||
#define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
|
|
||||||
((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported functions --------------------------------------------------------*/
|
|
||||||
|
|
||||||
/** @addtogroup CRCEx_Exported_Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup CRCEx_Exported_Functions_Group1
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Initialization and de-initialization functions ****************************/
|
|
||||||
HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
|
|
||||||
HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);
|
|
||||||
HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* STM32WLxx_HAL_CRC_EX_H */
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,648 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32wlxx_hal_cryp.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief Header file of CRYP HAL module.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
|
||||||
* All rights reserved.</center></h2>
|
|
||||||
*
|
|
||||||
* This software component is licensed by ST under BSD 3-Clause license,
|
|
||||||
* the "License"; You may not use this file except in compliance with the
|
|
||||||
* License. You may obtain a copy of the License at:
|
|
||||||
* opensource.org/licenses/BSD-3-Clause
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef STM32WLxx_HAL_CRYP_H
|
|
||||||
#define STM32WLxx_HAL_CRYP_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32wlxx_hal_def.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32WLxx_HAL_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/** @defgroup CRYP CRYP
|
|
||||||
* @brief CRYP HAL module driver.
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
|
|
||||||
/** @defgroup CRYP_Exported_Types CRYP Exported Types
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief CRYP Init Structure definition
|
|
||||||
*/
|
|
||||||
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
|
|
||||||
This parameter can be a value of @ref CRYP_Data_Type */
|
|
||||||
uint32_t KeySize; /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1.
|
|
||||||
128 or 256 bit key length in TinyAES This parameter can be a value of @ref CRYP_Key_Size */
|
|
||||||
uint32_t *pKey; /*!< The key used for encryption/decryption */
|
|
||||||
uint32_t *pInitVect; /*!< The initialization vector used also as initialization
|
|
||||||
counter in CTR mode */
|
|
||||||
uint32_t Algorithm; /*!< DES/ TDES Algorithm ECB/CBC
|
|
||||||
AES Algorithm ECB/CBC/CTR/GCM or CCM
|
|
||||||
This parameter can be a value of @ref CRYP_Algorithm_Mode */
|
|
||||||
uint32_t *Header; /*!< used only in AES GCM and CCM Algorithm for authentication,
|
|
||||||
GCM : also known as Additional Authentication Data
|
|
||||||
CCM : named B1 composed of the associated data length and Associated Data. */
|
|
||||||
uint32_t HeaderSize; /*!< The size of header buffer */
|
|
||||||
uint32_t *B0; /*!< B0 is first authentication block used only in AES CCM mode */
|
|
||||||
uint32_t DataWidthUnit; /*!< Payload Data Width Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/
|
|
||||||
uint32_t HeaderWidthUnit; /*!< Header Width Unit, this parameter can be value of @ref CRYP_Header_Width_Unit*/
|
|
||||||
uint32_t KeyIVConfigSkip; /*!< CRYP peripheral Key and IV configuration skip, to config Key and Initialization
|
|
||||||
Vector only once and to skip configuration for consecutive processings.
|
|
||||||
This parameter can be a value of @ref CRYP_Configuration_Skip */
|
|
||||||
|
|
||||||
} CRYP_ConfigTypeDef;
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief CRYP State Structure definition
|
|
||||||
*/
|
|
||||||
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
HAL_CRYP_STATE_RESET = 0x00U, /*!< CRYP not yet initialized or disabled */
|
|
||||||
HAL_CRYP_STATE_READY = 0x01U, /*!< CRYP initialized and ready for use */
|
|
||||||
HAL_CRYP_STATE_BUSY = 0x02U, /*!< CRYP BUSY, internal processing is ongoing */
|
|
||||||
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
|
|
||||||
HAL_CRYP_STATE_SUSPENDED = 0x03U, /*!< CRYP suspended */
|
|
||||||
#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
|
|
||||||
} HAL_CRYP_STATETypeDef;
|
|
||||||
|
|
||||||
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
|
|
||||||
/**
|
|
||||||
* @brief HAL CRYP mode suspend definitions
|
|
||||||
*/
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
HAL_CRYP_SUSPEND_NONE = 0x00U, /*!< CRYP processing suspension not requested */
|
|
||||||
HAL_CRYP_SUSPEND = 0x01U /*!< CRYP processing suspension requested */
|
|
||||||
}HAL_SuspendTypeDef;
|
|
||||||
#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief CRYP handle Structure definition
|
|
||||||
*/
|
|
||||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
|
|
||||||
typedef struct __CRYP_HandleTypeDef
|
|
||||||
#else
|
|
||||||
typedef struct
|
|
||||||
#endif
|
|
||||||
{
|
|
||||||
AES_TypeDef *Instance; /*!< AES Register base address */
|
|
||||||
|
|
||||||
CRYP_ConfigTypeDef Init; /*!< CRYP required parameters */
|
|
||||||
|
|
||||||
FunctionalState AutoKeyDerivation; /*!< Used only in TinyAES to allow to bypass or not key write-up before decryption.
|
|
||||||
This parameter can be a value of ENABLE/DISABLE */
|
|
||||||
|
|
||||||
uint32_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
|
|
||||||
|
|
||||||
uint32_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
|
|
||||||
|
|
||||||
__IO uint16_t CrypHeaderCount; /*!< Counter of header data in words */
|
|
||||||
|
|
||||||
__IO uint16_t CrypInCount; /*!< Counter of input data in words */
|
|
||||||
|
|
||||||
__IO uint16_t CrypOutCount; /*!< Counter of output data in words */
|
|
||||||
|
|
||||||
uint16_t Size; /*!< Length of input data */
|
|
||||||
|
|
||||||
uint32_t Phase; /*!< CRYP peripheral phase */
|
|
||||||
|
|
||||||
DMA_HandleTypeDef *hdmain; /*!< CRYP In DMA handle parameters */
|
|
||||||
|
|
||||||
DMA_HandleTypeDef *hdmaout; /*!< CRYP Out DMA handle parameters */
|
|
||||||
|
|
||||||
HAL_LockTypeDef Lock; /*!< CRYP locking object */
|
|
||||||
|
|
||||||
__IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */
|
|
||||||
|
|
||||||
__IO uint32_t ErrorCode; /*!< CRYP peripheral error code */
|
|
||||||
|
|
||||||
uint32_t KeyIVConfig; /*!< CRYP peripheral Key and IV configuration flag, used when
|
|
||||||
configuration can be skipped */
|
|
||||||
|
|
||||||
uint32_t SizesSum; /*!< Sum of successive payloads lengths (in bytes), stored
|
|
||||||
for a single signature computation after several
|
|
||||||
messages processing */
|
|
||||||
|
|
||||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
|
|
||||||
void (*InCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Input FIFO transfer completed callback */
|
|
||||||
void (*OutCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Output FIFO transfer completed callback */
|
|
||||||
void (*ErrorCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Error callback */
|
|
||||||
|
|
||||||
void (* MspInitCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Msp Init callback */
|
|
||||||
void (* MspDeInitCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Msp DeInit callback */
|
|
||||||
|
|
||||||
#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
|
|
||||||
|
|
||||||
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
|
|
||||||
|
|
||||||
__IO HAL_SuspendTypeDef SuspendRequest; /*!< CRYP peripheral suspension request flag */
|
|
||||||
|
|
||||||
CRYP_ConfigTypeDef Init_saved; /*!< copy of CRYP required parameters when processing is suspended */
|
|
||||||
|
|
||||||
uint32_t *pCrypInBuffPtr_saved; /*!< copy of CRYP input pointer when processing is suspended */
|
|
||||||
|
|
||||||
uint32_t *pCrypOutBuffPtr_saved; /*!< copy of CRYP output pointer when processing is suspended */
|
|
||||||
|
|
||||||
uint32_t CrypInCount_saved; /*!< copy of CRYP input data counter when processing is suspended */
|
|
||||||
|
|
||||||
uint32_t CrypOutCount_saved; /*!< copy of CRYP output data counter when processing is suspended */
|
|
||||||
|
|
||||||
uint32_t Phase_saved; /*!< copy of CRYP authentication phase when processing is suspended */
|
|
||||||
|
|
||||||
__IO HAL_CRYP_STATETypeDef State_saved; /*!< copy of CRYP peripheral state when processing is suspended */
|
|
||||||
|
|
||||||
uint32_t IV_saved[4]; /*!< copy of Initialisation Vector registers */
|
|
||||||
|
|
||||||
uint32_t SUSPxR_saved[8]; /*!< copy of suspension registers */
|
|
||||||
|
|
||||||
uint32_t CR_saved; /*!< copy of CRYP control register when processing is suspended*/
|
|
||||||
|
|
||||||
uint32_t Key_saved[8]; /*!< copy of key registers */
|
|
||||||
|
|
||||||
uint16_t Size_saved; /*!< copy of input buffer size */
|
|
||||||
|
|
||||||
uint16_t CrypHeaderCount_saved; /*!< copy of CRYP header data counter when processing is suspended */
|
|
||||||
|
|
||||||
uint32_t SizesSum_saved; /*!< copy of SizesSum when processing is suspended */
|
|
||||||
|
|
||||||
uint32_t ResumingFlag; /*!< resumption flag to bypass steps already carried out */
|
|
||||||
|
|
||||||
FunctionalState AutoKeyDerivation_saved; /*!< copy of CRYP handle auto key derivation parameter */
|
|
||||||
|
|
||||||
#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
|
|
||||||
|
|
||||||
} CRYP_HandleTypeDef;
|
|
||||||
|
|
||||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
|
|
||||||
/** @defgroup HAL_CRYP_Callback_ID_enumeration_definition HAL CRYP Callback ID enumeration definition
|
|
||||||
* @brief HAL CRYP Callback ID enumeration definition
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
HAL_CRYP_MSPINIT_CB_ID = 0x00U, /*!< CRYP MspInit callback ID */
|
|
||||||
HAL_CRYP_MSPDEINIT_CB_ID = 0x01U, /*!< CRYP MspDeInit callback ID */
|
|
||||||
HAL_CRYP_INPUT_COMPLETE_CB_ID = 0x02U, /*!< CRYP Input FIFO transfer completed callback ID */
|
|
||||||
HAL_CRYP_OUTPUT_COMPLETE_CB_ID = 0x03U, /*!< CRYP Output FIFO transfer completed callback ID */
|
|
||||||
HAL_CRYP_ERROR_CB_ID = 0x04U, /*!< CRYP Error callback ID */
|
|
||||||
} HAL_CRYP_CallbackIDTypeDef;
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup HAL_CRYP_Callback_pointer_definition HAL CRYP Callback pointer definition
|
|
||||||
* @brief HAL CRYP Callback pointer definition
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< pointer to a common CRYP callback function */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
|
||||||
/** @defgroup CRYP_Exported_Constants CRYP Exported Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup CRYP_Error_Definition CRYP Error Definition
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define HAL_CRYP_ERROR_NONE 0x00000000U /*!< No error */
|
|
||||||
#define HAL_CRYP_ERROR_WRITE 0x00000001U /*!< Write error */
|
|
||||||
#define HAL_CRYP_ERROR_READ 0x00000002U /*!< Read error */
|
|
||||||
#define HAL_CRYP_ERROR_DMA 0x00000004U /*!< DMA error */
|
|
||||||
#define HAL_CRYP_ERROR_BUSY 0x00000008U /*!< Busy flag error */
|
|
||||||
#define HAL_CRYP_ERROR_TIMEOUT 0x00000010U /*!< Timeout error */
|
|
||||||
#define HAL_CRYP_ERROR_NOT_SUPPORTED 0x00000020U /*!< Not supported mode */
|
|
||||||
#define HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE 0x00000040U /*!< Sequence are not respected only for GCM or CCM */
|
|
||||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
|
|
||||||
#define HAL_CRYP_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U) /*!< Invalid Callback error */
|
|
||||||
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup CRYP_Data_Width_Unit CRYP Data Width Unit
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define CRYP_DATAWIDTHUNIT_WORD 0x00000000U /*!< By default, size unit is word */
|
|
||||||
#define CRYP_DATAWIDTHUNIT_BYTE 0x00000001U /*!< By default, size unit is byte */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup CRYP_Header_Width_Unit CRYP Header Width Unit
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define CRYP_HEADERWIDTHUNIT_WORD 0x00000000U /*!< By default, header size unit is word */
|
|
||||||
#define CRYP_HEADERWIDTHUNIT_BYTE 0x00000001U /*!< By default, header size unit is byte */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup CRYP_Algorithm_Mode CRYP Algorithm Mode
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define CRYP_AES_ECB 0x00000000U /*!< Electronic codebook chaining algorithm */
|
|
||||||
#define CRYP_AES_CBC AES_CR_CHMOD_0 /*!< Cipher block chaining algorithm */
|
|
||||||
#define CRYP_AES_CTR AES_CR_CHMOD_1 /*!< Counter mode chaining algorithm */
|
|
||||||
#define CRYP_AES_GCM_GMAC (AES_CR_CHMOD_0 | AES_CR_CHMOD_1) /*!< Galois counter mode - Galois message authentication code */
|
|
||||||
#define CRYP_AES_CCM AES_CR_CHMOD_2 /*!< Counter with Cipher Mode */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup CRYP_Key_Size CRYP Key Size
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define CRYP_KEYSIZE_128B 0x00000000U /*!< 128-bit long key */
|
|
||||||
#define CRYP_KEYSIZE_256B AES_CR_KEYSIZE /*!< 256-bit long key */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup CRYP_Data_Type CRYP Data Type
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define CRYP_DATATYPE_32B 0x00000000U /*!< 32-bit data type (no swapping) */
|
|
||||||
#define CRYP_DATATYPE_16B AES_CR_DATATYPE_0 /*!< 16-bit data type (half-word swapping) */
|
|
||||||
#define CRYP_DATATYPE_8B AES_CR_DATATYPE_1 /*!< 8-bit data type (byte swapping) */
|
|
||||||
#define CRYP_DATATYPE_1B AES_CR_DATATYPE /*!< 1-bit data type (bit swapping) */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup CRYP_Interrupt CRYP Interrupt
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define CRYP_IT_CCFIE AES_CR_CCFIE /*!< Computation Complete interrupt enable */
|
|
||||||
#define CRYP_IT_ERRIE AES_CR_ERRIE /*!< Error interrupt enable */
|
|
||||||
#define CRYP_IT_WRERR AES_SR_WRERR /*!< Write Error */
|
|
||||||
#define CRYP_IT_RDERR AES_SR_RDERR /*!< Read Error */
|
|
||||||
#define CRYP_IT_CCF AES_SR_CCF /*!< Computation completed */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup CRYP_Flags CRYP Flags
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* status flags */
|
|
||||||
#define CRYP_FLAG_BUSY AES_SR_BUSY /*!< GCM process suspension forbidden */
|
|
||||||
#define CRYP_FLAG_WRERR AES_SR_WRERR /*!< Write Error */
|
|
||||||
#define CRYP_FLAG_RDERR AES_SR_RDERR /*!< Read error */
|
|
||||||
#define CRYP_FLAG_CCF AES_SR_CCF /*!< Computation completed */
|
|
||||||
/* clearing flags */
|
|
||||||
#define CRYP_CCF_CLEAR AES_CR_CCFC /*!< Computation Complete Flag Clear */
|
|
||||||
#define CRYP_ERR_CLEAR AES_CR_ERRC /*!< Error Flag Clear */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup CRYP_Configuration_Skip CRYP Key and IV Configuration Skip Mode
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define CRYP_KEYIVCONFIG_ALWAYS 0x00000000U /*!< Peripheral Key and IV configuration to do systematically */
|
|
||||||
#define CRYP_KEYIVCONFIG_ONCE 0x00000001U /*!< Peripheral Key and IV configuration to do only once */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported macros -----------------------------------------------------------*/
|
|
||||||
/** @defgroup CRYP_Exported_Macros CRYP Exported Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @brief Reset CRYP handle state
|
|
||||||
* @param __HANDLE__ specifies the CRYP handle.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
|
|
||||||
#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) do{\
|
|
||||||
(__HANDLE__)->State = HAL_CRYP_STATE_RESET;\
|
|
||||||
(__HANDLE__)->MspInitCallback = NULL;\
|
|
||||||
(__HANDLE__)->MspDeInitCallback = NULL;\
|
|
||||||
}while(0U)
|
|
||||||
#else
|
|
||||||
#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_CRYP_STATE_RESET)
|
|
||||||
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable/Disable the CRYP peripheral.
|
|
||||||
* @param __HANDLE__ specifies the CRYP handle.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= AES_CR_EN)
|
|
||||||
#define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~AES_CR_EN)
|
|
||||||
|
|
||||||
|
|
||||||
/** @brief Check whether the specified CRYP status flag is set or not.
|
|
||||||
* @param __HANDLE__ specifies the CRYP handle.
|
|
||||||
* @param __FLAG__ specifies the flag to check.
|
|
||||||
* This parameter can be one of the following values for TinyAES:
|
|
||||||
* @arg @ref CRYP_FLAG_BUSY GCM process suspension forbidden
|
|
||||||
* @arg @ref CRYP_IT_WRERR Write Error
|
|
||||||
* @arg @ref CRYP_IT_RDERR Read Error
|
|
||||||
* @arg @ref CRYP_IT_CCF Computation Complete
|
|
||||||
* This parameter can be one of the following values for CRYP:
|
|
||||||
* @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data
|
|
||||||
* or a key preparation (for AES decryption).
|
|
||||||
* @arg CRYP_FLAG_IFEM: Input FIFO is empty
|
|
||||||
* @arg CRYP_FLAG_IFNF: Input FIFO is not full
|
|
||||||
* @arg CRYP_FLAG_INRIS: Input FIFO service raw interrupt is pending
|
|
||||||
* @arg CRYP_FLAG_OFNE: Output FIFO is not empty
|
|
||||||
* @arg CRYP_FLAG_OFFU: Output FIFO is full
|
|
||||||
* @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending
|
|
||||||
* @retval The state of __FLAG__ (TRUE or FALSE).
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define CRYP_FLAG_MASK 0x0000001FU
|
|
||||||
#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
|
|
||||||
|
|
||||||
/** @brief Clear the CRYP pending status flag.
|
|
||||||
* @param __HANDLE__ specifies the CRYP handle.
|
|
||||||
* @param __FLAG__ specifies the flag to clear.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear
|
|
||||||
* @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define __HAL_CRYP_CLEAR_FLAG(__HANDLE__, __FLAG__) SET_BIT((__HANDLE__)->Instance->CR, (__FLAG__))
|
|
||||||
|
|
||||||
|
|
||||||
/** @brief Check whether the specified CRYP interrupt source is enabled or not.
|
|
||||||
* @param __HANDLE__ specifies the CRYP handle.
|
|
||||||
* @param __INTERRUPT__ CRYP interrupt source to check
|
|
||||||
* This parameter can be one of the following values for TinyAES:
|
|
||||||
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
|
|
||||||
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
|
|
||||||
* @retval State of interruption (TRUE or FALSE).
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
|
|
||||||
|
|
||||||
/** @brief Check whether the specified CRYP interrupt is set or not.
|
|
||||||
* @param __HANDLE__ specifies the CRYP handle.
|
|
||||||
* @param __INTERRUPT__ specifies the interrupt to check.
|
|
||||||
* This parameter can be one of the following values for TinyAES:
|
|
||||||
* @arg @ref CRYP_IT_WRERR Write Error
|
|
||||||
* @arg @ref CRYP_IT_RDERR Read Error
|
|
||||||
* @arg @ref CRYP_IT_CCF Computation Complete
|
|
||||||
* This parameter can be one of the following values for CRYP:
|
|
||||||
* @arg CRYP_IT_INI: Input FIFO service masked interrupt status
|
|
||||||
* @arg CRYP_IT_OUTI: Output FIFO service masked interrupt status
|
|
||||||
* @retval The state of __INTERRUPT__ (TRUE or FALSE).
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the CRYP interrupt.
|
|
||||||
* @param __HANDLE__ specifies the CRYP handle.
|
|
||||||
* @param __INTERRUPT__ CRYP Interrupt.
|
|
||||||
* This parameter can be one of the following values for TinyAES:
|
|
||||||
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
|
|
||||||
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
|
|
||||||
* This parameter can be one of the following values for CRYP:
|
|
||||||
* @ CRYP_IT_INI : Input FIFO service interrupt mask.
|
|
||||||
* @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the CRYP interrupt.
|
|
||||||
* @param __HANDLE__ specifies the CRYP handle.
|
|
||||||
* @param __INTERRUPT__ CRYP Interrupt.
|
|
||||||
* This parameter can be one of the following values for TinyAES:
|
|
||||||
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
|
|
||||||
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
|
|
||||||
* This parameter can be one of the following values for CRYP:
|
|
||||||
* @ CRYP_IT_INI : Input FIFO service interrupt mask.
|
|
||||||
* @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Include CRYP HAL Extended module */
|
|
||||||
#include "stm32wlxx_hal_cryp_ex.h"
|
|
||||||
|
|
||||||
/* Exported functions --------------------------------------------------------*/
|
|
||||||
/** @defgroup CRYP_Exported_Functions CRYP Exported Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup CRYP_Exported_Functions_Group1
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
|
|
||||||
HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
|
|
||||||
void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
|
|
||||||
void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
|
|
||||||
HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf);
|
|
||||||
HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf);
|
|
||||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
|
|
||||||
HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback);
|
|
||||||
HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID);
|
|
||||||
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
|
|
||||||
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
|
|
||||||
void HAL_CRYP_ProcessSuspend(CRYP_HandleTypeDef *hcryp);
|
|
||||||
HAL_StatusTypeDef HAL_CRYP_Suspend(CRYP_HandleTypeDef *hcryp);
|
|
||||||
HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp);
|
|
||||||
#endif /* defined (USE_HAL_CRYP_SUSPEND_RESUME) */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup CRYP_Exported_Functions_Group2
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* encryption/decryption ***********************************/
|
|
||||||
HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout);
|
|
||||||
HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout);
|
|
||||||
HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
|
|
||||||
HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
|
|
||||||
HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
|
|
||||||
HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/** @addtogroup CRYP_Exported_Functions_Group3
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Interrupt Handler functions **********************************************/
|
|
||||||
void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
|
|
||||||
HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
|
|
||||||
void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
|
|
||||||
void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
|
|
||||||
void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
|
|
||||||
uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private macros --------------------------------------------------------*/
|
|
||||||
/** @defgroup CRYP_Private_Macros CRYP Private Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup CRYP_IS_CRYP_Definitions CRYP Private macros to check input parameters
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_AES_ECB) || \
|
|
||||||
((ALGORITHM) == CRYP_AES_CBC) || \
|
|
||||||
((ALGORITHM) == CRYP_AES_CTR) || \
|
|
||||||
((ALGORITHM) == CRYP_AES_GCM_GMAC)|| \
|
|
||||||
((ALGORITHM) == CRYP_AES_CCM))
|
|
||||||
|
|
||||||
|
|
||||||
#define IS_CRYP_KEYSIZE(KEYSIZE)(((KEYSIZE) == CRYP_KEYSIZE_128B) || \
|
|
||||||
((KEYSIZE) == CRYP_KEYSIZE_256B))
|
|
||||||
|
|
||||||
#define IS_CRYP_DATATYPE(DATATYPE)(((DATATYPE) == CRYP_DATATYPE_32B) || \
|
|
||||||
((DATATYPE) == CRYP_DATATYPE_16B) || \
|
|
||||||
((DATATYPE) == CRYP_DATATYPE_8B) || \
|
|
||||||
((DATATYPE) == CRYP_DATATYPE_1B))
|
|
||||||
|
|
||||||
#define IS_CRYP_INIT(CONFIG)(((CONFIG) == CRYP_KEYIVCONFIG_ALWAYS) || \
|
|
||||||
((CONFIG) == CRYP_KEYIVCONFIG_ONCE))
|
|
||||||
|
|
||||||
#define IS_CRYP_BUFFERSIZE(ALGO, DATAWIDTH, SIZE) \
|
|
||||||
(((((ALGO) == CRYP_AES_CTR)) && \
|
|
||||||
((((DATAWIDTH) == CRYP_DATAWIDTHUNIT_WORD) && (((SIZE) % 4U) == 0U)) || \
|
|
||||||
(((DATAWIDTH) == CRYP_DATAWIDTHUNIT_BYTE) && (((SIZE) % 16U) == 0U)))) || \
|
|
||||||
(((ALGO) == CRYP_AES_ECB) || ((ALGO) == CRYP_AES_CBC) || \
|
|
||||||
((ALGO)== CRYP_AES_GCM_GMAC) || ((ALGO) == CRYP_AES_CCM)))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/* Private constants ---------------------------------------------------------*/
|
|
||||||
/** @defgroup CRYP_Private_Constants CRYP Private Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
/* Private defines -----------------------------------------------------------*/
|
|
||||||
/** @defgroup CRYP_Private_Defines CRYP Private Defines
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private variables ---------------------------------------------------------*/
|
|
||||||
/** @defgroup CRYP_Private_Variables CRYP Private Variables
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private functions ---------------------------------------------------------*/
|
|
||||||
/** @defgroup CRYP_Private_Functions CRYP Private Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* STM32WLxx_HAL_CRYP_H */
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,133 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32wlxx_hal_cryp_ex.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief Header file of CRYPEx HAL module.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
|
||||||
* All rights reserved.</center></h2>
|
|
||||||
*
|
|
||||||
* This software component is licensed by ST under BSD 3-Clause license,
|
|
||||||
* the "License"; You may not use this file except in compliance with the
|
|
||||||
* License. You may obtain a copy of the License at:
|
|
||||||
* opensource.org/licenses/BSD-3-Clause
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef STM32WLxx_HAL_CRYP_EX_H
|
|
||||||
#define STM32WLxx_HAL_CRYP_EX_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32wlxx_hal_def.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32WLxx_HAL_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/** @defgroup CRYPEx CRYPEx
|
|
||||||
* @brief CRYP Extension HAL module driver.
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
|
||||||
/* Private types -------------------------------------------------------------*/
|
|
||||||
/** @defgroup CRYPEx_Private_Types CRYPEx Private Types
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private variables ---------------------------------------------------------*/
|
|
||||||
/** @defgroup CRYPEx_Private_Variables CRYPEx Private Variables
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private constants ---------------------------------------------------------*/
|
|
||||||
/** @defgroup CRYPEx_Private_Constants CRYPEx Private Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private macros ------------------------------------------------------------*/
|
|
||||||
/** @defgroup CRYPEx_Private_Macros CRYPEx Private Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private functions ---------------------------------------------------------*/
|
|
||||||
/** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported functions --------------------------------------------------------*/
|
|
||||||
/** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup CRYPEx_Exported_Functions_Group1
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);
|
|
||||||
HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup CRYPEx_Exported_Functions_Group2
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
void HAL_CRYPEx_EnableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp);
|
|
||||||
void HAL_CRYPEx_DisableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* STM32WLxx_HAL_CRYP_EX_H */
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,507 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32wlxx_hal_dac.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief Header file of DAC HAL module.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
|
||||||
* All rights reserved.</center></h2>
|
|
||||||
*
|
|
||||||
* This software component is licensed by ST under BSD 3-Clause license,
|
|
||||||
* the "License"; You may not use this file except in compliance with the
|
|
||||||
* License. You may obtain a copy of the License at:
|
|
||||||
* opensource.org/licenses/BSD-3-Clause
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef STM32WLxx_HAL_DAC_H
|
|
||||||
#define STM32WLxx_HAL_DAC_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/** @addtogroup STM32WLxx_HAL_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32wlxx_hal_def.h"
|
|
||||||
|
|
||||||
#if defined(DAC)
|
|
||||||
|
|
||||||
/** @addtogroup DAC
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
|
|
||||||
/** @defgroup DAC_Exported_Types DAC Exported Types
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief HAL State structures definition
|
|
||||||
*/
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
HAL_DAC_STATE_RESET = 0x00U, /*!< DAC not yet initialized or disabled */
|
|
||||||
HAL_DAC_STATE_READY = 0x01U, /*!< DAC initialized and ready for use */
|
|
||||||
HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */
|
|
||||||
HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */
|
|
||||||
HAL_DAC_STATE_ERROR = 0x04U /*!< DAC error state */
|
|
||||||
|
|
||||||
} HAL_DAC_StateTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief DAC handle Structure definition
|
|
||||||
*/
|
|
||||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
|
||||||
typedef struct __DAC_HandleTypeDef
|
|
||||||
#else
|
|
||||||
typedef struct
|
|
||||||
#endif
|
|
||||||
{
|
|
||||||
DAC_TypeDef *Instance; /*!< Register base address */
|
|
||||||
|
|
||||||
__IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */
|
|
||||||
|
|
||||||
HAL_LockTypeDef Lock; /*!< DAC locking object */
|
|
||||||
|
|
||||||
DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */
|
|
||||||
|
|
||||||
DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */
|
|
||||||
|
|
||||||
__IO uint32_t ErrorCode; /*!< DAC Error code */
|
|
||||||
|
|
||||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
|
||||||
void (* ConvCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
|
|
||||||
void (* ConvHalfCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
|
|
||||||
void (* ErrorCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
|
|
||||||
void (* DMAUnderrunCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
|
|
||||||
|
|
||||||
void (* MspInitCallback) (struct __DAC_HandleTypeDef *hdac);
|
|
||||||
void (* MspDeInitCallback ) (struct __DAC_HandleTypeDef *hdac);
|
|
||||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
|
||||||
|
|
||||||
} DAC_HandleTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief DAC Configuration sample and hold Channel structure definition
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t DAC_SampleTime ; /*!< Specifies the Sample time for the selected channel.
|
|
||||||
This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
|
|
||||||
This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */
|
|
||||||
|
|
||||||
uint32_t DAC_HoldTime ; /*!< Specifies the hold time for the selected channel
|
|
||||||
This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
|
|
||||||
This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */
|
|
||||||
|
|
||||||
uint32_t DAC_RefreshTime ; /*!< Specifies the refresh time for the selected channel
|
|
||||||
This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
|
|
||||||
This parameter must be a number between Min_Data = 0 and Max_Data = 255 */
|
|
||||||
} DAC_SampleAndHoldConfTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief DAC Configuration regular Channel structure definition
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t DAC_SampleAndHold; /*!< Specifies whether the DAC mode.
|
|
||||||
This parameter can be a value of @ref DAC_SampleAndHold */
|
|
||||||
|
|
||||||
uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
|
|
||||||
This parameter can be a value of @ref DAC_trigger_selection */
|
|
||||||
|
|
||||||
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
|
|
||||||
This parameter can be a value of @ref DAC_output_buffer */
|
|
||||||
|
|
||||||
uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral .
|
|
||||||
This parameter can be a value of @ref DAC_ConnectOnChipPeripheral */
|
|
||||||
|
|
||||||
uint32_t DAC_UserTrimming; /*!< Specifies the trimming mode
|
|
||||||
This parameter must be a value of @ref DAC_UserTrimming
|
|
||||||
DAC_UserTrimming is either factory or user trimming */
|
|
||||||
|
|
||||||
uint32_t DAC_TrimmingValue; /*!< Specifies the offset trimming value
|
|
||||||
i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER.
|
|
||||||
This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
|
|
||||||
|
|
||||||
DAC_SampleAndHoldConfTypeDef DAC_SampleAndHoldConfig; /*!< Sample and Hold settings */
|
|
||||||
|
|
||||||
} DAC_ChannelConfTypeDef;
|
|
||||||
|
|
||||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
|
||||||
/**
|
|
||||||
* @brief HAL DAC Callback ID enumeration definition
|
|
||||||
*/
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
HAL_DAC_CH1_COMPLETE_CB_ID = 0x00U, /*!< DAC CH1 Complete Callback ID */
|
|
||||||
HAL_DAC_CH1_HALF_COMPLETE_CB_ID = 0x01U, /*!< DAC CH1 half Complete Callback ID */
|
|
||||||
HAL_DAC_CH1_ERROR_ID = 0x02U, /*!< DAC CH1 error Callback ID */
|
|
||||||
HAL_DAC_CH1_UNDERRUN_CB_ID = 0x03U, /*!< DAC CH1 underrun Callback ID */
|
|
||||||
HAL_DAC_MSPINIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */
|
|
||||||
HAL_DAC_MSPDEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */
|
|
||||||
HAL_DAC_ALL_CB_ID = 0x0AU /*!< DAC All ID */
|
|
||||||
} HAL_DAC_CallbackIDTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief HAL DAC Callback pointer definition
|
|
||||||
*/
|
|
||||||
typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
|
|
||||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
|
||||||
|
|
||||||
/** @defgroup DAC_Exported_Constants DAC Exported Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DAC_Error_Code DAC Error Code
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define HAL_DAC_ERROR_NONE 0x00U /*!< No error */
|
|
||||||
#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DMA underrun error */
|
|
||||||
#define HAL_DAC_ERROR_DMA 0x04U /*!< DMA error */
|
|
||||||
#define HAL_DAC_ERROR_TIMEOUT 0x08U /*!< Timeout error */
|
|
||||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
|
||||||
#define HAL_DAC_ERROR_INVALID_CALLBACK 0x10U /*!< Invalid callback error */
|
|
||||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DAC_trigger_selection DAC trigger selection
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define DAC_TRIGGER_NONE (0x00000000UL) /*!< Conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger */
|
|
||||||
#define DAC_TRIGGER_SOFTWARE (DAC_CR_TEN1) /*!< Conversion started by software trigger for DAC channel */
|
|
||||||
#define DAC_TRIGGER_T1_TRGO (DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM1 TRGO selected as external conversion trigger for DAC channel */
|
|
||||||
#define DAC_TRIGGER_T2_TRGO (DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
|
|
||||||
#define DAC_TRIGGER_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< LPTIM1_OUT selected as external conversion trigger for DAC channel */
|
|
||||||
#define DAC_TRIGGER_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< LPTIM2_OUT selected as external conversion trigger for DAC channel */
|
|
||||||
#define DAC_TRIGGER_LPTIM3_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< LPTIM3_OUT selected as external conversion trigger for DAC channel */
|
|
||||||
#define DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DAC_output_buffer DAC output buffer
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define DAC_OUTPUTBUFFER_ENABLE 0x00000000U
|
|
||||||
#define DAC_OUTPUTBUFFER_DISABLE (DAC_MCR_MODE1_1)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DAC_Channel_selection DAC Channel selection
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define DAC_CHANNEL_1 0x00000000U
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DAC_data_alignment DAC data alignment
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define DAC_ALIGN_12B_R 0x00000000U
|
|
||||||
#define DAC_ALIGN_12B_L 0x00000004U
|
|
||||||
#define DAC_ALIGN_8B_R 0x00000008U
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DAC_flags_definition DAC flags definition
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DAC_IT_definition DAC IT definition
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define DAC_IT_DMAUDR1 (DAC_SR_DMAUDR1)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define DAC_CHIPCONNECT_DISABLE (0x00000000UL)
|
|
||||||
#define DAC_CHIPCONNECT_ENABLE (DAC_MCR_MODE1_0)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DAC_UserTrimming DAC User Trimming
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define DAC_TRIMMING_FACTORY (0x00000000UL) /*!< Factory trimming */
|
|
||||||
#define DAC_TRIMMING_USER (0x00000001UL) /*!< User trimming */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DAC_SampleAndHold DAC power mode
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define DAC_SAMPLEANDHOLD_DISABLE (0x00000000UL)
|
|
||||||
#define DAC_SAMPLEANDHOLD_ENABLE (DAC_MCR_MODE1_2)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported macro ------------------------------------------------------------*/
|
|
||||||
|
|
||||||
/** @defgroup DAC_Exported_Macros DAC Exported Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @brief Reset DAC handle state.
|
|
||||||
* @param __HANDLE__ specifies the DAC handle.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
|
||||||
#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do { \
|
|
||||||
(__HANDLE__)->State = HAL_DAC_STATE_RESET; \
|
|
||||||
(__HANDLE__)->MspInitCallback = NULL; \
|
|
||||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
|
||||||
} while(0)
|
|
||||||
#else
|
|
||||||
#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
|
|
||||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
|
||||||
|
|
||||||
/** @brief Enable the DAC channel.
|
|
||||||
* @param __HANDLE__ specifies the DAC handle.
|
|
||||||
* @param __DAC_Channel__ specifies the DAC channel
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
|
|
||||||
((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
|
|
||||||
|
|
||||||
/** @brief Disable the DAC channel.
|
|
||||||
* @param __HANDLE__ specifies the DAC handle
|
|
||||||
* @param __DAC_Channel__ specifies the DAC channel.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
|
|
||||||
((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
|
|
||||||
|
|
||||||
/** @brief Set DHR12R1 alignment.
|
|
||||||
* @param __ALIGNMENT__ specifies the DAC alignment
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008UL + (__ALIGNMENT__))
|
|
||||||
|
|
||||||
|
|
||||||
/** @brief Set DHR12RD alignment.
|
|
||||||
* @param __ALIGNMENT__ specifies the DAC alignment
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020UL + (__ALIGNMENT__))
|
|
||||||
|
|
||||||
/** @brief Enable the DAC interrupt.
|
|
||||||
* @param __HANDLE__ specifies the DAC handle
|
|
||||||
* @param __INTERRUPT__ specifies the DAC interrupt.
|
|
||||||
* This parameter can be any combination of the following values:
|
|
||||||
* @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
|
|
||||||
|
|
||||||
/** @brief Disable the DAC interrupt.
|
|
||||||
* @param __HANDLE__ specifies the DAC handle
|
|
||||||
* @param __INTERRUPT__ specifies the DAC interrupt.
|
|
||||||
* This parameter can be any combination of the following values:
|
|
||||||
* @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
|
|
||||||
|
|
||||||
/** @brief Check whether the specified DAC interrupt source is enabled or not.
|
|
||||||
* @param __HANDLE__ DAC handle
|
|
||||||
* @param __INTERRUPT__ DAC interrupt source to check
|
|
||||||
* This parameter can be any combination of the following values:
|
|
||||||
* @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
|
|
||||||
* @retval State of interruption (SET or RESET)
|
|
||||||
*/
|
|
||||||
#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
|
|
||||||
|
|
||||||
/** @brief Get the selected DAC's flag status.
|
|
||||||
* @param __HANDLE__ specifies the DAC handle.
|
|
||||||
* @param __FLAG__ specifies the DAC flag to get.
|
|
||||||
* This parameter can be any combination of the following values:
|
|
||||||
* @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
|
|
||||||
|
|
||||||
/** @brief Clear the DAC's flag.
|
|
||||||
* @param __HANDLE__ specifies the DAC handle.
|
|
||||||
* @param __FLAG__ specifies the DAC flag to clear.
|
|
||||||
* This parameter can be any combination of the following values:
|
|
||||||
* @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private macro -------------------------------------------------------------*/
|
|
||||||
|
|
||||||
/** @defgroup DAC_Private_Macros DAC Private Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
|
|
||||||
((STATE) == DAC_OUTPUTBUFFER_DISABLE))
|
|
||||||
|
|
||||||
#define IS_DAC_CHANNEL(CHANNEL) ((CHANNEL) == DAC_CHANNEL_1)
|
|
||||||
|
|
||||||
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
|
|
||||||
((ALIGN) == DAC_ALIGN_12B_L) || \
|
|
||||||
((ALIGN) == DAC_ALIGN_8B_R))
|
|
||||||
|
|
||||||
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0UL)
|
|
||||||
|
|
||||||
#define IS_DAC_REFRESHTIME(TIME) ((TIME) <= 0x000000FFUL)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Include DAC HAL Extended module */
|
|
||||||
#include "stm32wlxx_hal_dac_ex.h"
|
|
||||||
|
|
||||||
/* Exported functions --------------------------------------------------------*/
|
|
||||||
|
|
||||||
/** @addtogroup DAC_Exported_Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup DAC_Exported_Functions_Group1
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Initialization and de-initialization functions *****************************/
|
|
||||||
HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac);
|
|
||||||
HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac);
|
|
||||||
void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac);
|
|
||||||
void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup DAC_Exported_Functions_Group2
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* IO operation functions *****************************************************/
|
|
||||||
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel);
|
|
||||||
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel);
|
|
||||||
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
|
|
||||||
uint32_t Alignment);
|
|
||||||
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
|
|
||||||
|
|
||||||
void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac);
|
|
||||||
|
|
||||||
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
|
|
||||||
|
|
||||||
void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac);
|
|
||||||
void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac);
|
|
||||||
void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
|
|
||||||
void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
|
|
||||||
|
|
||||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
|
||||||
/* DAC callback registering/unregistering */
|
|
||||||
HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID,
|
|
||||||
pDAC_CallbackTypeDef pCallback);
|
|
||||||
HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID);
|
|
||||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup DAC_Exported_Functions_Group3
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Peripheral Control functions ***********************************************/
|
|
||||||
uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel);
|
|
||||||
|
|
||||||
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup DAC_Exported_Functions_Group4
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Peripheral State and Error functions ***************************************/
|
|
||||||
HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac);
|
|
||||||
uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DAC_Private_Functions DAC Private Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
|
|
||||||
void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
|
|
||||||
void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#endif /* DAC */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
|
|
||||||
#endif /*STM32WLxx_HAL_DAC_H */
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
||||||
|
|
@ -1,205 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32wlxx_hal_dac_ex.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief Header file of DAC HAL Extended module.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
|
||||||
* All rights reserved.</center></h2>
|
|
||||||
*
|
|
||||||
* This software component is licensed by ST under BSD 3-Clause license,
|
|
||||||
* the "License"; You may not use this file except in compliance with the
|
|
||||||
* License. You may obtain a copy of the License at:
|
|
||||||
* opensource.org/licenses/BSD-3-Clause
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef STM32WLxx_HAL_DAC_EX_H
|
|
||||||
#define STM32WLxx_HAL_DAC_EX_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/** @addtogroup STM32WLxx_HAL_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32wlxx_hal_def.h"
|
|
||||||
|
|
||||||
#if defined(DAC)
|
|
||||||
|
|
||||||
/** @addtogroup DACEx
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief HAL State structures definition
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
|
||||||
|
|
||||||
/** @defgroup DACEx_Exported_Constants DACEx Exported Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangle amplitude
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define DAC_LFSRUNMASK_BIT0 0x00000000UL /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
|
|
||||||
#define DAC_LFSRUNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
|
|
||||||
#define DAC_LFSRUNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
|
|
||||||
#define DAC_LFSRUNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
|
|
||||||
#define DAC_LFSRUNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
|
|
||||||
#define DAC_LFSRUNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
|
|
||||||
#define DAC_LFSRUNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
|
|
||||||
#define DAC_LFSRUNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
|
|
||||||
#define DAC_LFSRUNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
|
|
||||||
#define DAC_LFSRUNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
|
|
||||||
#define DAC_LFSRUNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
|
|
||||||
#define DAC_LFSRUNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
|
|
||||||
#define DAC_TRIANGLEAMPLITUDE_1 0x00000000UL /*!< Select max triangle amplitude of 1 */
|
|
||||||
#define DAC_TRIANGLEAMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
|
|
||||||
#define DAC_TRIANGLEAMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 7 */
|
|
||||||
#define DAC_TRIANGLEAMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
|
|
||||||
#define DAC_TRIANGLEAMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Select max triangle amplitude of 31 */
|
|
||||||
#define DAC_TRIANGLEAMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
|
|
||||||
#define DAC_TRIANGLEAMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 127 */
|
|
||||||
#define DAC_TRIANGLEAMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
|
|
||||||
#define DAC_TRIANGLEAMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Select max triangle amplitude of 511 */
|
|
||||||
#define DAC_TRIANGLEAMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
|
|
||||||
#define DAC_TRIANGLEAMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 2047 */
|
|
||||||
#define DAC_TRIANGLEAMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported macro ------------------------------------------------------------*/
|
|
||||||
|
|
||||||
|
|
||||||
/* Private macro -------------------------------------------------------------*/
|
|
||||||
|
|
||||||
/** @defgroup DACEx_Private_Macros DACEx Private Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
|
|
||||||
((TRIGGER) == DAC_TRIGGER_SOFTWARE) || \
|
|
||||||
((TRIGGER) == DAC_TRIGGER_T1_TRGO) || \
|
|
||||||
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
|
|
||||||
((TRIGGER) == DAC_TRIGGER_LPTIM1_OUT) || \
|
|
||||||
((TRIGGER) == DAC_TRIGGER_LPTIM2_OUT) || \
|
|
||||||
((TRIGGER) == DAC_TRIGGER_LPTIM3_OUT) || \
|
|
||||||
((TRIGGER) == DAC_TRIGGER_EXT_IT9))
|
|
||||||
|
|
||||||
#define IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x000003FFU)
|
|
||||||
|
|
||||||
#define IS_DAC_HOLDTIME(TIME) ((TIME) <= 0x000003FFU)
|
|
||||||
|
|
||||||
#define IS_DAC_SAMPLEANDHOLD(MODE) (((MODE) == DAC_SAMPLEANDHOLD_DISABLE) || \
|
|
||||||
((MODE) == DAC_SAMPLEANDHOLD_ENABLE))
|
|
||||||
|
|
||||||
#define IS_DAC_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
|
|
||||||
|
|
||||||
#define IS_DAC_NEWTRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
|
|
||||||
|
|
||||||
#define IS_DAC_CHIP_CONNECTION(CONNECT) (((CONNECT) == DAC_CHIPCONNECT_DISABLE) || \
|
|
||||||
((CONNECT) == DAC_CHIPCONNECT_ENABLE))
|
|
||||||
|
|
||||||
#define IS_DAC_TRIMMING(TRIMMING) (((TRIMMING) == DAC_TRIMMING_FACTORY) || \
|
|
||||||
((TRIMMING) == DAC_TRIMMING_USER))
|
|
||||||
|
|
||||||
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
|
|
||||||
((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
|
|
||||||
((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
|
|
||||||
((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
|
|
||||||
((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
|
|
||||||
((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
|
|
||||||
((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
|
|
||||||
((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
|
|
||||||
((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
|
|
||||||
((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
|
|
||||||
((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
|
|
||||||
((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
|
|
||||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
|
|
||||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
|
|
||||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
|
|
||||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
|
|
||||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
|
|
||||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
|
|
||||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
|
|
||||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
|
|
||||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
|
|
||||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
|
|
||||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
|
|
||||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported functions --------------------------------------------------------*/
|
|
||||||
/* Extended features functions ***********************************************/
|
|
||||||
|
|
||||||
/** @addtogroup DACEx_Exported_Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup DACEx_Exported_Functions_Group2
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* IO operation functions *****************************************************/
|
|
||||||
|
|
||||||
HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
|
|
||||||
HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup DACEx_Exported_Functions_Group3
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Peripheral Control functions ***********************************************/
|
|
||||||
|
|
||||||
HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
|
|
||||||
HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel,
|
|
||||||
uint32_t NewTrimmingValue);
|
|
||||||
uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#endif /* DAC */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /*STM32WLxx_HAL_DAC_EX_H */
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,212 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32wlxx_hal_def.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief This file contains HAL common defines, enumeration, macros and
|
|
||||||
* structures definitions.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
|
||||||
* All rights reserved.</center></h2>
|
|
||||||
*
|
|
||||||
* This software component is licensed by ST under BSD 3-Clause license,
|
|
||||||
* the "License"; You may not use this file except in compliance with the
|
|
||||||
* License. You may obtain a copy of the License at:
|
|
||||||
* opensource.org/licenses/BSD-3-Clause
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef __STM32WLxx_HAL_DEF
|
|
||||||
#define __STM32WLxx_HAL_DEF
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32wlxx.h"
|
|
||||||
#include "Legacy/stm32_hal_legacy.h" /* Aliases file for old names compatibility */
|
|
||||||
#include <stddef.h>
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief HAL Status structures definition
|
|
||||||
*/
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
HAL_OK = 0x00,
|
|
||||||
HAL_ERROR = 0x01,
|
|
||||||
HAL_BUSY = 0x02,
|
|
||||||
HAL_TIMEOUT = 0x03
|
|
||||||
} HAL_StatusTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief HAL Lock structures definition
|
|
||||||
*/
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
HAL_UNLOCKED = 0x00,
|
|
||||||
HAL_LOCKED = 0x01
|
|
||||||
} HAL_LockTypeDef;
|
|
||||||
|
|
||||||
/* Exported macros -----------------------------------------------------------*/
|
|
||||||
|
|
||||||
#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
|
|
||||||
|
|
||||||
#define HAL_MAX_DELAY 0xFFFFFFFFU
|
|
||||||
|
|
||||||
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT))
|
|
||||||
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
|
|
||||||
|
|
||||||
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
|
|
||||||
do{ \
|
|
||||||
(__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
|
|
||||||
(__DMA_HANDLE__).Parent = (__HANDLE__); \
|
|
||||||
} while(0)
|
|
||||||
|
|
||||||
/** @brief Reset the Handle's State field.
|
|
||||||
* @param __HANDLE__ specifies the Peripheral Handle.
|
|
||||||
* @note This macro can be used for the following purpose:
|
|
||||||
* - When the Handle is declared as local variable; before passing it as parameter
|
|
||||||
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro
|
|
||||||
* to set to 0 the Handle's "State" field.
|
|
||||||
* Otherwise, "State" field may have any random value and the first time the function
|
|
||||||
* HAL_PPP_Init() is called, the low level hardware initialization will be missed
|
|
||||||
* (i.e. HAL_PPP_MspInit() will not be executed).
|
|
||||||
* - When there is a need to reconfigure the low level hardware: instead of calling
|
|
||||||
* HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
|
|
||||||
* In this later function, when the Handle's "State" field is set to 0, it will execute the function
|
|
||||||
* HAL_PPP_MspInit() which will reconfigure the low level hardware.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
|
|
||||||
|
|
||||||
#if (USE_RTOS == 1)
|
|
||||||
/* Reserved for future use */
|
|
||||||
#error " USE_RTOS should be 0 in the current HAL release "
|
|
||||||
#else
|
|
||||||
#define __HAL_LOCK(__HANDLE__) \
|
|
||||||
do{ \
|
|
||||||
if((__HANDLE__)->Lock == HAL_LOCKED) \
|
|
||||||
{ \
|
|
||||||
return HAL_BUSY; \
|
|
||||||
} \
|
|
||||||
else \
|
|
||||||
{ \
|
|
||||||
(__HANDLE__)->Lock = HAL_LOCKED; \
|
|
||||||
} \
|
|
||||||
}while (0)
|
|
||||||
|
|
||||||
#define __HAL_UNLOCK(__HANDLE__) \
|
|
||||||
do{ \
|
|
||||||
(__HANDLE__)->Lock = HAL_UNLOCKED; \
|
|
||||||
}while (0)
|
|
||||||
#endif /* USE_RTOS */
|
|
||||||
|
|
||||||
|
|
||||||
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
|
|
||||||
#ifndef __weak
|
|
||||||
#define __weak __attribute__((weak))
|
|
||||||
#endif
|
|
||||||
#ifndef __packed
|
|
||||||
#define __packed __attribute__((packed))
|
|
||||||
#endif
|
|
||||||
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
|
|
||||||
#ifndef __weak
|
|
||||||
#define __weak __attribute__((weak))
|
|
||||||
#endif /* __weak */
|
|
||||||
#ifndef __packed
|
|
||||||
#define __packed __attribute__((__packed__))
|
|
||||||
#endif /* __packed */
|
|
||||||
#endif /* __GNUC__ */
|
|
||||||
|
|
||||||
|
|
||||||
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
|
|
||||||
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
|
|
||||||
#ifndef __ALIGN_BEGIN
|
|
||||||
#define __ALIGN_BEGIN
|
|
||||||
#endif
|
|
||||||
#ifndef __ALIGN_END
|
|
||||||
#define __ALIGN_END __attribute__ ((aligned (4)))
|
|
||||||
#endif
|
|
||||||
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
|
|
||||||
#ifndef __ALIGN_END
|
|
||||||
#define __ALIGN_END __attribute__ ((aligned (4)))
|
|
||||||
#endif /* __ALIGN_END */
|
|
||||||
#ifndef __ALIGN_BEGIN
|
|
||||||
#define __ALIGN_BEGIN
|
|
||||||
#endif /* __ALIGN_BEGIN */
|
|
||||||
#else
|
|
||||||
#ifndef __ALIGN_END
|
|
||||||
#define __ALIGN_END
|
|
||||||
#endif /* __ALIGN_END */
|
|
||||||
#ifndef __ALIGN_BEGIN
|
|
||||||
#if defined (__CC_ARM) /* ARM Compiler V5 */
|
|
||||||
#define __ALIGN_BEGIN __align(4)
|
|
||||||
#elif defined (__ICCARM__) /* IAR Compiler */
|
|
||||||
#define __ALIGN_BEGIN
|
|
||||||
#endif /* __CC_ARM */
|
|
||||||
#endif /* __ALIGN_BEGIN */
|
|
||||||
#endif /* __GNUC__ */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief __RAM_FUNC definition
|
|
||||||
*/
|
|
||||||
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
|
|
||||||
/* ARM Compiler V4/V5 and V6
|
|
||||||
--------------------------
|
|
||||||
RAM functions are defined using the toolchain options.
|
|
||||||
Functions that are executed in RAM should reside in a separate source module.
|
|
||||||
Using the 'Options for File' dialog you can simply change the 'Code / Const'
|
|
||||||
area of a module to a memory space in physical RAM.
|
|
||||||
Available memory areas are declared in the 'Target' tab of the 'Options for Target'
|
|
||||||
dialog.
|
|
||||||
*/
|
|
||||||
#define __RAM_FUNC
|
|
||||||
|
|
||||||
#elif defined ( __ICCARM__ )
|
|
||||||
/* ICCARM Compiler
|
|
||||||
---------------
|
|
||||||
RAM functions are defined using a specific toolchain keyword "__ramfunc".
|
|
||||||
*/
|
|
||||||
#define __RAM_FUNC __ramfunc
|
|
||||||
|
|
||||||
#elif defined ( __GNUC__ )
|
|
||||||
/* GNU Compiler
|
|
||||||
------------
|
|
||||||
RAM functions are defined using a specific toolchain attribute
|
|
||||||
"__attribute__((section(".RamFunc")))".
|
|
||||||
*/
|
|
||||||
#define __RAM_FUNC __attribute__((section(".RamFunc")))
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief __NOINLINE definition
|
|
||||||
*/
|
|
||||||
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ )
|
|
||||||
/* ARM V4/V5 and V6 & GNU Compiler
|
|
||||||
-------------------------------
|
|
||||||
*/
|
|
||||||
#define __NOINLINE __attribute__ ( (noinline) )
|
|
||||||
|
|
||||||
#elif defined ( __ICCARM__ )
|
|
||||||
/* ICCARM Compiler
|
|
||||||
---------------
|
|
||||||
*/
|
|
||||||
#define __NOINLINE _Pragma("optimize = no_inline")
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* ___STM32WLxx_HAL_DEF */
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,686 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32wlxx_hal_dma.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief Header file of DMA HAL module.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
|
||||||
* All rights reserved.</center></h2>
|
|
||||||
*
|
|
||||||
* This software component is licensed by ST under BSD 3-Clause license,
|
|
||||||
* the "License"; You may not use this file except in compliance with the
|
|
||||||
* License. You may obtain a copy of the License at:
|
|
||||||
* opensource.org/licenses/BSD-3-Clause
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef STM32WLxx_HAL_DMA_H
|
|
||||||
#define STM32WLxx_HAL_DMA_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32wlxx_hal_def.h"
|
|
||||||
#include "stm32wlxx_ll_dma.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32WLxx_HAL_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup DMA
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
/** @defgroup DMA_Exported_Types DMA Exported Types
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief DMA Configuration Structure definition
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t Request; /*!< Specifies the request selected for the specified channel.
|
|
||||||
This parameter can be a value of @ref DMA_request */
|
|
||||||
|
|
||||||
uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
|
|
||||||
from memory to memory or from peripheral to memory.
|
|
||||||
This parameter can be a value of @ref DMA_Data_transfer_direction */
|
|
||||||
|
|
||||||
uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
|
|
||||||
This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
|
|
||||||
|
|
||||||
uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
|
|
||||||
This parameter can be a value of @ref DMA_Memory_incremented_mode */
|
|
||||||
|
|
||||||
uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
|
|
||||||
This parameter can be a value of @ref DMA_Peripheral_data_size */
|
|
||||||
|
|
||||||
uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
|
|
||||||
This parameter can be a value of @ref DMA_Memory_data_size */
|
|
||||||
|
|
||||||
uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
|
|
||||||
This parameter can be a value of @ref DMA_mode
|
|
||||||
@note The circular buffer mode cannot be used if the memory-to-memory
|
|
||||||
data transfer is configured on the selected Channel */
|
|
||||||
|
|
||||||
uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
|
|
||||||
This parameter can be a value of @ref DMA_Priority_level */
|
|
||||||
} DMA_InitTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief HAL DMA State structures definition
|
|
||||||
*/
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
|
|
||||||
HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
|
|
||||||
HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
|
|
||||||
HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */
|
|
||||||
} HAL_DMA_StateTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief HAL DMA Error Code structure definition
|
|
||||||
*/
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
|
|
||||||
HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
|
|
||||||
} HAL_DMA_LevelCompleteTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief HAL DMA Callback ID structure definition
|
|
||||||
*/
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
|
|
||||||
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */
|
|
||||||
HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */
|
|
||||||
HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */
|
|
||||||
HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */
|
|
||||||
|
|
||||||
} HAL_DMA_CallbackIDTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief DMA handle Structure definition
|
|
||||||
*/
|
|
||||||
typedef struct __DMA_HandleTypeDef
|
|
||||||
{
|
|
||||||
DMA_Channel_TypeDef *Instance; /*!< Register base address */
|
|
||||||
|
|
||||||
DMA_InitTypeDef Init; /*!< DMA communication parameters */
|
|
||||||
|
|
||||||
HAL_LockTypeDef Lock; /*!< DMA locking object */
|
|
||||||
|
|
||||||
__IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
|
|
||||||
|
|
||||||
void *Parent; /*!< Parent object state */
|
|
||||||
|
|
||||||
void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */
|
|
||||||
|
|
||||||
void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA Half transfer complete callback */
|
|
||||||
|
|
||||||
void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */
|
|
||||||
|
|
||||||
void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer abort callback */
|
|
||||||
|
|
||||||
__IO uint32_t ErrorCode; /*!< DMA Error code */
|
|
||||||
|
|
||||||
DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */
|
|
||||||
|
|
||||||
uint32_t ChannelIndex; /*!< DMA Channel Index */
|
|
||||||
|
|
||||||
DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< Register base address */
|
|
||||||
|
|
||||||
DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */
|
|
||||||
|
|
||||||
uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */
|
|
||||||
|
|
||||||
DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */
|
|
||||||
|
|
||||||
DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Address */
|
|
||||||
|
|
||||||
uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */
|
|
||||||
} DMA_HandleTypeDef;
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
|
||||||
|
|
||||||
/** @defgroup DMA_Exported_Constants DMA Exported Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DMA_Error_Code DMA Error Code
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */
|
|
||||||
#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */
|
|
||||||
#define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< Abort requested with no Xfer ongoing */
|
|
||||||
#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
|
|
||||||
#define HAL_DMA_ERROR_PARAM 0x00000040U /*!< Parameter error */
|
|
||||||
#define HAL_DMA_ERROR_BUSY 0x00000080U /*!< DMA Busy error */
|
|
||||||
#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */
|
|
||||||
#define HAL_DMA_ERROR_SYNC 0x00000200U /*!< DMAMUX sync overrun error */
|
|
||||||
#define HAL_DMA_ERROR_REQGEN 0x00000400U /*!< DMAMUX request generator overrun error */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DMA_request DMA request
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define DMA_REQUEST_MEM2MEM LL_DMAMUX_REQ_MEM2MEM /*!< memory to memory transfer */
|
|
||||||
#define DMA_REQUEST_GENERATOR0 LL_DMAMUX_REQ_GENERATOR0 /*!< DMAMUX request generator 0 */
|
|
||||||
#define DMA_REQUEST_GENERATOR1 LL_DMAMUX_REQ_GENERATOR1 /*!< DMAMUX request generator 1 */
|
|
||||||
#define DMA_REQUEST_GENERATOR2 LL_DMAMUX_REQ_GENERATOR2 /*!< DMAMUX request generator 2 */
|
|
||||||
#define DMA_REQUEST_GENERATOR3 LL_DMAMUX_REQ_GENERATOR3 /*!< DMAMUX request generator 3 */
|
|
||||||
#define DMA_REQUEST_ADC LL_DMAMUX_REQ_ADC /*!< DMAMUX ADC request */
|
|
||||||
#define DMA_REQUEST_DAC_OUT1 LL_DMAMUX_REQ_DAC_OUT1 /*!< DMAMUX DAC OUT request */
|
|
||||||
#define DMA_REQUEST_SPI1_RX LL_DMAMUX_REQ_SPI1_RX /*!< DMAMUX SPI1 RX request */
|
|
||||||
#define DMA_REQUEST_SPI1_TX LL_DMAMUX_REQ_SPI1_TX /*!< DMAMUX SPI1 TX request */
|
|
||||||
#define DMA_REQUEST_SPI2_RX LL_DMAMUX_REQ_SPI2_RX /*!< DMAMUX SPI2 RX request */
|
|
||||||
#define DMA_REQUEST_SPI2_TX LL_DMAMUX_REQ_SPI2_TX /*!< DMAMUX SPI2 TX request */
|
|
||||||
#define DMA_REQUEST_I2C1_RX LL_DMAMUX_REQ_I2C1_RX /*!< DMAMUX I2C1 RX request */
|
|
||||||
#define DMA_REQUEST_I2C1_TX LL_DMAMUX_REQ_I2C1_TX /*!< DMAMUX I2C1 TX request */
|
|
||||||
#define DMA_REQUEST_I2C2_RX LL_DMAMUX_REQ_I2C2_RX /*!< DMAMUX I2C2 RX request */
|
|
||||||
#define DMA_REQUEST_I2C2_TX LL_DMAMUX_REQ_I2C2_TX /*!< DMAMUX I2C2 TX request */
|
|
||||||
#define DMA_REQUEST_I2C3_RX LL_DMAMUX_REQ_I2C3_RX /*!< DMAMUX I2C3 RX request */
|
|
||||||
#define DMA_REQUEST_I2C3_TX LL_DMAMUX_REQ_I2C3_TX /*!< DMAMUX I2C3 TX request */
|
|
||||||
#define DMA_REQUEST_USART1_RX LL_DMAMUX_REQ_USART1_RX /*!< DMAMUX USART1 RX request */
|
|
||||||
#define DMA_REQUEST_USART1_TX LL_DMAMUX_REQ_USART1_TX /*!< DMAMUX USART1 TX request */
|
|
||||||
#define DMA_REQUEST_USART2_RX LL_DMAMUX_REQ_USART2_RX /*!< DMAMUX USART2 RX request */
|
|
||||||
#define DMA_REQUEST_USART2_TX LL_DMAMUX_REQ_USART2_TX /*!< DMAMUX USART2 TX request */
|
|
||||||
#define DMA_REQUEST_LPUART1_RX LL_DMAMUX_REQ_LPUART1_RX /*!< DMAMUX LPUART1 RX request */
|
|
||||||
#define DMA_REQUEST_LPUART1_TX LL_DMAMUX_REQ_LPUART1_TX /*!< DMAMUX LPUART1 TX request */
|
|
||||||
#define DMA_REQUEST_TIM1_CH1 LL_DMAMUX_REQ_TIM1_CH1 /*!< DMAMUX TIM1 CH1 request */
|
|
||||||
#define DMA_REQUEST_TIM1_CH2 LL_DMAMUX_REQ_TIM1_CH2 /*!< DMAMUX TIM1 CH2 request */
|
|
||||||
#define DMA_REQUEST_TIM1_CH3 LL_DMAMUX_REQ_TIM1_CH3 /*!< DMAMUX TIM1 CH3 request */
|
|
||||||
#define DMA_REQUEST_TIM1_CH4 LL_DMAMUX_REQ_TIM1_CH4 /*!< DMAMUX TIM1 CH4 request */
|
|
||||||
#define DMA_REQUEST_TIM1_UP LL_DMAMUX_REQ_TIM1_UP /*!< DMAMUX TIM1 UP request */
|
|
||||||
#define DMA_REQUEST_TIM1_TRIG LL_DMAMUX_REQ_TIM1_TRIG /*!< DMAMUX TIM1 TRIG request */
|
|
||||||
#define DMA_REQUEST_TIM1_COM LL_DMAMUX_REQ_TIM1_COM /*!< DMAMUX TIM1 COM request */
|
|
||||||
#define DMA_REQUEST_TIM2_CH1 LL_DMAMUX_REQ_TIM2_CH1 /*!< DMAMUX TIM2 CH1 request */
|
|
||||||
#define DMA_REQUEST_TIM2_CH2 LL_DMAMUX_REQ_TIM2_CH2 /*!< DMAMUX TIM2 CH2 request */
|
|
||||||
#define DMA_REQUEST_TIM2_CH3 LL_DMAMUX_REQ_TIM2_CH3 /*!< DMAMUX TIM2 CH3 request */
|
|
||||||
#define DMA_REQUEST_TIM2_CH4 LL_DMAMUX_REQ_TIM2_CH4 /*!< DMAMUX TIM2 CH4 request */
|
|
||||||
#define DMA_REQUEST_TIM2_UP LL_DMAMUX_REQ_TIM2_UP /*!< DMAMUX TIM2 UP request */
|
|
||||||
#define DMA_REQUEST_TIM16_CH1 LL_DMAMUX_REQ_TIM16_CH1 /*!< DMAMUX TIM16 CH1 request */
|
|
||||||
#define DMA_REQUEST_TIM16_UP LL_DMAMUX_REQ_TIM16_UP /*!< DMAMUX TIM16 UP request */
|
|
||||||
#define DMA_REQUEST_TIM17_CH1 LL_DMAMUX_REQ_TIM17_CH1 /*!< DMAMUX TIM17 CH1 request */
|
|
||||||
#define DMA_REQUEST_TIM17_UP LL_DMAMUX_REQ_TIM17_UP /*!< DMAMUX TIM17 UP request */
|
|
||||||
#define DMA_REQUEST_AES_IN LL_DMAMUX_REQ_AES_IN /*!< DMAMUX AES_IN request */
|
|
||||||
#define DMA_REQUEST_AES_OUT LL_DMAMUX_REQ_AES_OUT /*!< DMAMUX AES_OUT request */
|
|
||||||
#define DMA_REQUEST_SUBGHZSPI_RX LL_DMAMUX_REQ_SUBGHZSPI_RX /*!< DMAMUX SUBGHZSPI RX request*/
|
|
||||||
#define DMA_REQUEST_SUBGHZSPI_TX LL_DMAMUX_REQ_SUBGHZSPI_TX /*!< DMAMUX SUBGHZSPI TX request*/
|
|
||||||
|
|
||||||
#define DMA_MAX_REQUEST LL_DMAMUX_MAX_REQ
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define DMA_PERIPH_TO_MEMORY LL_DMA_DIRECTION_PERIPH_TO_MEMORY /*!< Peripheral to memory direction */
|
|
||||||
#define DMA_MEMORY_TO_PERIPH LL_DMA_DIRECTION_MEMORY_TO_PERIPH /*!< Memory to peripheral direction */
|
|
||||||
#define DMA_MEMORY_TO_MEMORY LL_DMA_DIRECTION_MEMORY_TO_MEMORY /*!< Memory to memory direction */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define DMA_PINC_ENABLE LL_DMA_PERIPH_INCREMENT /*!< Peripheral increment mode Enable */
|
|
||||||
#define DMA_PINC_DISABLE LL_DMA_PERIPH_NOINCREMENT /*!< Peripheral increment mode Disable */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define DMA_MINC_ENABLE LL_DMA_MEMORY_INCREMENT /*!< Memory increment mode Enable */
|
|
||||||
#define DMA_MINC_DISABLE LL_DMA_MEMORY_NOINCREMENT /*!< Memory increment mode Disable */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define DMA_PDATAALIGN_BYTE LL_DMA_PDATAALIGN_BYTE /*!< Peripheral data alignment : Byte */
|
|
||||||
#define DMA_PDATAALIGN_HALFWORD LL_DMA_PDATAALIGN_HALFWORD /*!< Peripheral data alignment : HalfWord */
|
|
||||||
#define DMA_PDATAALIGN_WORD LL_DMA_PDATAALIGN_WORD /*!< Peripheral data alignment : Word */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DMA_Memory_data_size DMA Memory data size
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define DMA_MDATAALIGN_BYTE LL_DMA_MDATAALIGN_BYTE /*!< Memory data alignment : Byte */
|
|
||||||
#define DMA_MDATAALIGN_HALFWORD LL_DMA_MDATAALIGN_HALFWORD /*!< Memory data alignment : HalfWord */
|
|
||||||
#define DMA_MDATAALIGN_WORD LL_DMA_MDATAALIGN_WORD /*!< Memory data alignment : Word */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DMA_mode DMA mode
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define DMA_NORMAL LL_DMA_MODE_NORMAL /*!< Normal mode */
|
|
||||||
#define DMA_CIRCULAR LL_DMA_MODE_CIRCULAR /*!< Circular mode */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DMA_Priority_level DMA Priority level
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define DMA_PRIORITY_LOW LL_DMA_PRIORITY_LOW /*!< Priority level : Low */
|
|
||||||
#define DMA_PRIORITY_MEDIUM LL_DMA_PRIORITY_MEDIUM /*!< Priority level : Medium */
|
|
||||||
#define DMA_PRIORITY_HIGH LL_DMA_PRIORITY_HIGH /*!< Priority level : High */
|
|
||||||
#define DMA_PRIORITY_VERY_HIGH LL_DMA_PRIORITY_VERYHIGH /*!< Priority level : Very_High */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define DMA_IT_TC DMA_CCR_TCIE /*!< Transfer Complete interrupt */
|
|
||||||
#define DMA_IT_HT DMA_CCR_HTIE /*!< Half Transfer Complete interrupt */
|
|
||||||
#define DMA_IT_TE DMA_CCR_TEIE /*!< Transfer Error interrupt */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DMA_flag_definitions DMA flag definitions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define DMA_FLAG_GI1 DMA_ISR_GIF1 /*!< Global Interrupt flag for Channel 1 */
|
|
||||||
#define DMA_FLAG_TC1 DMA_ISR_TCIF1 /*!< Transfer Complete flag for Channel 1 */
|
|
||||||
#define DMA_FLAG_HT1 DMA_ISR_HTIF1 /*!< Half Transfer flag for Channel 1 */
|
|
||||||
#define DMA_FLAG_TE1 DMA_ISR_TEIF1 /*!< Transfer Error flag for Channel 1 */
|
|
||||||
#define DMA_FLAG_GI2 DMA_ISR_GIF2 /*!< Global Interrupt flag for Channel 2 */
|
|
||||||
#define DMA_FLAG_TC2 DMA_ISR_TCIF2 /*!< Transfer Complete flag for Channel 2 */
|
|
||||||
#define DMA_FLAG_HT2 DMA_ISR_HTIF2 /*!< Half Transfer flag for Channel 2 */
|
|
||||||
#define DMA_FLAG_TE2 DMA_ISR_TEIF2 /*!< Transfer Error flag for Channel 2 */
|
|
||||||
#define DMA_FLAG_GI3 DMA_ISR_GIF3 /*!< Global Interrupt flag for Channel 3 */
|
|
||||||
#define DMA_FLAG_TC3 DMA_ISR_TCIF3 /*!< Transfer Complete flag for Channel 3 */
|
|
||||||
#define DMA_FLAG_HT3 DMA_ISR_HTIF3 /*!< Half Transfer flag for Channel 3 */
|
|
||||||
#define DMA_FLAG_TE3 DMA_ISR_TEIF3 /*!< Transfer Error flag for Channel 3 */
|
|
||||||
#define DMA_FLAG_GI4 DMA_ISR_GIF4 /*!< Global Interrupt flag for Channel 4 */
|
|
||||||
#define DMA_FLAG_TC4 DMA_ISR_TCIF4 /*!< Transfer Complete flag for Channel 4 */
|
|
||||||
#define DMA_FLAG_HT4 DMA_ISR_HTIF4 /*!< Half Transfer flag for Channel 4 */
|
|
||||||
#define DMA_FLAG_TE4 DMA_ISR_TEIF4 /*!< Transfer Error flag for Channel 4 */
|
|
||||||
#define DMA_FLAG_GI5 DMA_ISR_GIF5 /*!< Global Interrupt flag for Channel 5 */
|
|
||||||
#define DMA_FLAG_TC5 DMA_ISR_TCIF5 /*!< Transfer Complete flag for Channel 5 */
|
|
||||||
#define DMA_FLAG_HT5 DMA_ISR_HTIF5 /*!< Half Transfer flag for Channel 5 */
|
|
||||||
#define DMA_FLAG_TE5 DMA_ISR_TEIF5 /*!< Transfer Error for Channel 5 */
|
|
||||||
#define DMA_FLAG_GI6 DMA_ISR_GIF6 /*!< Global Interrupt flag for Channel 6 */
|
|
||||||
#define DMA_FLAG_TC6 DMA_ISR_TCIF6 /*!< Transfer Complete flag for Channel 6 */
|
|
||||||
#define DMA_FLAG_HT6 DMA_ISR_HTIF6 /*!< Half Transfer flag for Channel 6 */
|
|
||||||
#define DMA_FLAG_TE6 DMA_ISR_TEIF6 /*!< Transfer Error flag for Channel 6 */
|
|
||||||
#define DMA_FLAG_GI7 DMA_ISR_GIF7 /*!< Global Interrupt flag for Channel 7 */
|
|
||||||
#define DMA_FLAG_TC7 DMA_ISR_TCIF7 /*!< Transfer Complete flag for Channel 7 */
|
|
||||||
#define DMA_FLAG_HT7 DMA_ISR_HTIF7 /*!< Half Transfer flag for Channel 7 */
|
|
||||||
#define DMA_FLAG_TE7 DMA_ISR_TEIF7 /*!< Transfer Error flag for Channel 7 */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#if defined(DMA_CCR_SECM) && defined(DMA_CCR_PRIV)
|
|
||||||
/** @defgroup DMA_Channel_Attributes DMA Channel Attributes
|
|
||||||
* @brief DMA channel secure or non-secure and privileged or non-privileged attributes
|
|
||||||
* @note Secure and non-secure attributes are only available from secure when the system
|
|
||||||
* implements the security (ESE=1)
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define DMA_CHANNEL_ATTR_PRIV_MASK (DMA_CCR_PRIV >> 16U)
|
|
||||||
#define DMA_CHANNEL_ATTR_SEC_MASK (DMA_CCR_SECM >> 16U)
|
|
||||||
#if defined (CORE_CM0PLUS)
|
|
||||||
#define DMA_CHANNEL_ATTR_SEC_SRC_MASK (DMA_CCR_SSEC >> 16U)
|
|
||||||
#define DMA_CHANNEL_ATTR_SEC_DEST_MASK (DMA_CCR_DSEC >> 16U)
|
|
||||||
#endif /* CORE_CM0PLUS */
|
|
||||||
|
|
||||||
#define DMA_CHANNEL_PRIV (DMA_CHANNEL_ATTR_PRIV_MASK | DMA_CCR_PRIV) /*!< Channel is privileged */
|
|
||||||
#define DMA_CHANNEL_NPRIV (DMA_CHANNEL_ATTR_PRIV_MASK) /*!< Channel is unprivileged */
|
|
||||||
#define DMA_CHANNEL_SEC (DMA_CHANNEL_ATTR_SEC_MASK | DMA_CCR_SECM) /*!< Channel is secure */
|
|
||||||
#define DMA_CHANNEL_NSEC (DMA_CHANNEL_ATTR_SEC_MASK) /*!< Channel is non-secure */
|
|
||||||
#if defined (CORE_CM0PLUS)
|
|
||||||
#define DMA_CHANNEL_SRC_SEC (DMA_CHANNEL_ATTR_SEC_SRC_MASK | DMA_CCR_SSEC) /*!< Channel source is secure */
|
|
||||||
#define DMA_CHANNEL_SRC_NSEC (DMA_CHANNEL_ATTR_SEC_SRC_MASK) /*!< Channel source is non-secure */
|
|
||||||
#define DMA_CHANNEL_DEST_SEC (DMA_CHANNEL_ATTR_SEC_DEST_MASK | DMA_CCR_DSEC) /*!< Channel destination is secure */
|
|
||||||
#define DMA_CHANNEL_DEST_NSEC (DMA_CHANNEL_ATTR_SEC_DEST_MASK) /*!< Channel destination is non-secure */
|
|
||||||
#endif /* CORE_CM0PLUS */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#endif /* DMA_SECURE_SWITCH */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported macros -----------------------------------------------------------*/
|
|
||||||
/** @defgroup DMA_Exported_Macros DMA Exported Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @brief Reset DMA handle state
|
|
||||||
* @param __HANDLE__ DMA handle
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the specified DMA Channel.
|
|
||||||
* @param __HANDLE__ DMA handle
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the specified DMA Channel.
|
|
||||||
* @param __HANDLE__ DMA handle
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Return the current DMA Channel transfer complete flag.
|
|
||||||
* @param __HANDLE__ DMA handle
|
|
||||||
* @retval The specified transfer complete flag index.
|
|
||||||
*/
|
|
||||||
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
|
|
||||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\
|
|
||||||
DMA_FLAG_TC7)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Return the current DMA Channel half transfer complete flag.
|
|
||||||
* @param __HANDLE__ DMA handle
|
|
||||||
* @retval The specified half transfer complete flag index.
|
|
||||||
*/
|
|
||||||
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \
|
|
||||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\
|
|
||||||
DMA_FLAG_HT7)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Return the current DMA Channel transfer error flag.
|
|
||||||
* @param __HANDLE__ DMA handle
|
|
||||||
* @retval The specified transfer error flag index.
|
|
||||||
*/
|
|
||||||
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \
|
|
||||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\
|
|
||||||
DMA_FLAG_TE7)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Return the current DMA Channel Global interrupt flag.
|
|
||||||
* @param __HANDLE__ DMA handle
|
|
||||||
* @retval The specified transfer error flag index.
|
|
||||||
*/
|
|
||||||
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \
|
|
||||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GI1 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GI1 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GI2 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GI2 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GI3 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GI3 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GI4 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GI4 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GI5 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_GI5 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GI6 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_GI6 :\
|
|
||||||
DMA_FLAG_GI7)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Get the DMA Channel pending flags.
|
|
||||||
* @param __HANDLE__ DMA handle
|
|
||||||
* @param __FLAG__ Get the specified flag.
|
|
||||||
* This parameter can be any combination of the following values:
|
|
||||||
* @arg DMA_FLAG_TCx: Transfer complete flag
|
|
||||||
* @arg DMA_FLAG_HTx: Half transfer complete flag
|
|
||||||
* @arg DMA_FLAG_TEx: Transfer error flag
|
|
||||||
* @arg DMA_FLAG_GIx: Global interrupt flag
|
|
||||||
* Where x can be 1 to max Channel supported by the product to select the DMA Channel flag.
|
|
||||||
* @retval The state of FLAG (SET or RESET).
|
|
||||||
*/
|
|
||||||
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
|
|
||||||
(DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Clear the DMA Channel pending flags.
|
|
||||||
* @param __HANDLE__ DMA handle
|
|
||||||
* @param __FLAG__ specifies the flag to clear.
|
|
||||||
* This parameter can be any combination of the following values:
|
|
||||||
* @arg DMA_FLAG_TCx: Transfer complete flag
|
|
||||||
* @arg DMA_FLAG_HTx: Half transfer complete flag
|
|
||||||
* @arg DMA_FLAG_TEx: Transfer error flag
|
|
||||||
* @arg DMA_FLAG_GIx: Global interrupt flag
|
|
||||||
* Where x can be 1 to max Channel supported by the product to select the DMA Channel flag.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
|
|
||||||
(DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the specified DMA Channel interrupts.
|
|
||||||
* @param __HANDLE__ DMA handle
|
|
||||||
* @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
|
|
||||||
* This parameter can be any combination of the following values:
|
|
||||||
* @arg DMA_IT_TC: Transfer complete interrupt mask
|
|
||||||
* @arg DMA_IT_HT: Half transfer complete interrupt mask
|
|
||||||
* @arg DMA_IT_TE: Transfer error interrupt mask
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the specified DMA Channel interrupts.
|
|
||||||
* @param __HANDLE__ DMA handle
|
|
||||||
* @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
|
|
||||||
* This parameter can be any combination of the following values:
|
|
||||||
* @arg DMA_IT_TC: Transfer complete interrupt mask
|
|
||||||
* @arg DMA_IT_HT: Half transfer complete interrupt mask
|
|
||||||
* @arg DMA_IT_TE: Transfer error interrupt mask
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Check whether the specified DMA Channel interrupt is enabled or disabled.
|
|
||||||
* @param __HANDLE__ DMA handle
|
|
||||||
* @param __INTERRUPT__ specifies the DMA interrupt source to check.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg DMA_IT_TC: Transfer complete interrupt mask
|
|
||||||
* @arg DMA_IT_HT: Half transfer complete interrupt mask
|
|
||||||
* @arg DMA_IT_TE: Transfer error interrupt mask
|
|
||||||
* @retval The state of DMA_IT (SET or RESET).
|
|
||||||
*/
|
|
||||||
#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Returns the number of remaining data units in the current DMA Channel transfer.
|
|
||||||
* @param __HANDLE__ DMA handle
|
|
||||||
* @retval The number of remaining data units in the current DMA Channel transfer.
|
|
||||||
*/
|
|
||||||
#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Include DMA HAL Extension module */
|
|
||||||
#include "stm32wlxx_hal_dma_ex.h"
|
|
||||||
|
|
||||||
/* Exported functions --------------------------------------------------------*/
|
|
||||||
|
|
||||||
/** @addtogroup DMA_Exported_Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup DMA_Exported_Functions_Group1
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Initialization and de-initialization functions *****************************/
|
|
||||||
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
|
|
||||||
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup DMA_Exported_Functions_Group2
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* IO operation functions *****************************************************/
|
|
||||||
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
|
|
||||||
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
|
|
||||||
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
|
|
||||||
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
|
|
||||||
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
|
|
||||||
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
|
|
||||||
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
|
|
||||||
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup DMA_Exported_Functions_Group3
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Peripheral State and Error functions ***************************************/
|
|
||||||
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
|
|
||||||
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#if defined(DMA_CCR_SECM) && defined(DMA_CCR_PRIV)
|
|
||||||
/** @addtogroup DMA_Exported_Functions_Group4
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* DMA Attributes functions ********************************************/
|
|
||||||
HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *hdma, uint32_t ChannelAttributes);
|
|
||||||
HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef *hdma, uint32_t *ChannelAttributes);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#endif /* DMA_SECURE_SWITCH */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private macros ------------------------------------------------------------*/
|
|
||||||
/** @defgroup DMA_Private_Macros DMA Private Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
|
|
||||||
((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
|
|
||||||
((DIRECTION) == DMA_MEMORY_TO_MEMORY))
|
|
||||||
|
|
||||||
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < DMA_CNDTR_NDT))
|
|
||||||
|
|
||||||
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
|
|
||||||
((STATE) == DMA_PINC_DISABLE))
|
|
||||||
|
|
||||||
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
|
|
||||||
((STATE) == DMA_MINC_DISABLE))
|
|
||||||
|
|
||||||
#define IS_DMA_ALL_REQUEST(REQUEST) ((REQUEST) <= DMA_MAX_REQUEST)
|
|
||||||
|
|
||||||
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
|
|
||||||
((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
|
|
||||||
((SIZE) == DMA_PDATAALIGN_WORD))
|
|
||||||
|
|
||||||
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
|
|
||||||
((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
|
|
||||||
((SIZE) == DMA_MDATAALIGN_WORD ))
|
|
||||||
|
|
||||||
#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
|
|
||||||
((MODE) == DMA_CIRCULAR))
|
|
||||||
|
|
||||||
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
|
|
||||||
((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
|
|
||||||
((PRIORITY) == DMA_PRIORITY_HIGH) || \
|
|
||||||
((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
|
|
||||||
|
|
||||||
#if defined(DMA_CCR_SECM) && defined(DMA_CCR_PRIV)
|
|
||||||
#if defined (CORE_CM0PLUS)
|
|
||||||
#define IS_DMA_ATTRIBUTES(ATTRIBUTE) ((((ATTRIBUTE) & (~(0x001E001EU))) == 0U) && (((ATTRIBUTE) & 0x0000001EU) != 0U))
|
|
||||||
#else
|
|
||||||
#define IS_DMA_ATTRIBUTES(ATTRIBUTE) ((((ATTRIBUTE) & (~(0x00100010U))) == 0U) && (((ATTRIBUTE) & 0x00000010U) != 0U))
|
|
||||||
#endif /* CORE_CM0PLUS */
|
|
||||||
#endif /* DMA_SECURE_SWITCH */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private functions ---------------------------------------------------------*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* STM32WLxx_HAL_DMA_H */
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,268 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32wlxx_hal_dma_ex.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief Header file of DMA HAL extension module.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
|
||||||
* All rights reserved.</center></h2>
|
|
||||||
*
|
|
||||||
* This software component is licensed by ST under BSD 3-Clause license,
|
|
||||||
* the "License"; You may not use this file except in compliance with the
|
|
||||||
* License. You may obtain a copy of the License at:
|
|
||||||
* opensource.org/licenses/BSD-3-Clause
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef STM32WLxx_HAL_DMA_EX_H
|
|
||||||
#define STM32WLxx_HAL_DMA_EX_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32wlxx_hal_def.h"
|
|
||||||
#include "stm32wlxx_ll_dmamux.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32WLxx_HAL_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup DMAEx
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
/** @defgroup DMAEx_Exported_Types DMAEx Exported Types
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief HAL DMAMUX Synchronization configuration structure definition
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t SyncSignalID; /*!< Specifies the synchronization signal gating the DMA request in periodic mode.
|
|
||||||
This parameter can be a value of @ref DMAEx_DMAMUX_SyncSignalID_selection */
|
|
||||||
|
|
||||||
uint32_t SyncPolarity; /*!< Specifies the polarity of the signal on which the DMA request is synchronized.
|
|
||||||
This parameter can be a value of @ref DMAEx_DMAMUX_SyncPolarity_selection */
|
|
||||||
|
|
||||||
FunctionalState SyncEnable; /*!< Specifies if the synchronization shall be enabled or disabled
|
|
||||||
This parameter can take the value ENABLE or DISABLE */
|
|
||||||
|
|
||||||
FunctionalState EventEnable; /*!< Specifies if an event shall be generated once the RequestNumber is reached.
|
|
||||||
This parameter can take the value ENABLE or DISABLE */
|
|
||||||
|
|
||||||
uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be authorized after a sync event
|
|
||||||
This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
|
|
||||||
|
|
||||||
|
|
||||||
} HAL_DMA_MuxSyncConfigTypeDef;
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief HAL DMAMUX request generator parameters structure definition
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t SignalID; /*!< Specifies the ID of the signal used for DMAMUX request generator
|
|
||||||
This parameter can be a value of @ref DMAEx_DMAMUX_SignalGeneratorID_selection */
|
|
||||||
|
|
||||||
uint32_t Polarity; /*!< Specifies the polarity of the signal on which the request is generated.
|
|
||||||
This parameter can be a value of @ref DMAEx_DMAMUX_RequestGeneneratorPolarity_selection */
|
|
||||||
|
|
||||||
uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be generated after a signal event
|
|
||||||
This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
|
|
||||||
|
|
||||||
} HAL_DMA_MuxRequestGeneratorConfigTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
|
||||||
/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DMAEx_DMAMUX_SyncSignalID_selection DMAMUX SyncSignalID selection
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define HAL_DMAMUX1_SYNC_EXTI0 LL_DMAMUX_SYNC_EXTI_LINE0 /*!< Synchronization signal from EXTI Line0 */
|
|
||||||
#define HAL_DMAMUX1_SYNC_EXTI1 LL_DMAMUX_SYNC_EXTI_LINE1 /*!< Synchronization signal from EXTI Line1 */
|
|
||||||
#define HAL_DMAMUX1_SYNC_EXTI2 LL_DMAMUX_SYNC_EXTI_LINE2 /*!< Synchronization signal from EXTI Line2 */
|
|
||||||
#define HAL_DMAMUX1_SYNC_EXTI3 LL_DMAMUX_SYNC_EXTI_LINE3 /*!< Synchronization signal from EXTI Line3 */
|
|
||||||
#define HAL_DMAMUX1_SYNC_EXTI4 LL_DMAMUX_SYNC_EXTI_LINE4 /*!< Synchronization signal from EXTI Line4 */
|
|
||||||
#define HAL_DMAMUX1_SYNC_EXTI5 LL_DMAMUX_SYNC_EXTI_LINE5 /*!< Synchronization signal from EXTI Line5 */
|
|
||||||
#define HAL_DMAMUX1_SYNC_EXTI6 LL_DMAMUX_SYNC_EXTI_LINE6 /*!< Synchronization signal from EXTI Line6 */
|
|
||||||
#define HAL_DMAMUX1_SYNC_EXTI7 LL_DMAMUX_SYNC_EXTI_LINE7 /*!< Synchronization signal from EXTI Line7 */
|
|
||||||
#define HAL_DMAMUX1_SYNC_EXTI8 LL_DMAMUX_SYNC_EXTI_LINE8 /*!< Synchronization signal from EXTI Line8 */
|
|
||||||
#define HAL_DMAMUX1_SYNC_EXTI9 LL_DMAMUX_SYNC_EXTI_LINE9 /*!< Synchronization signal from EXTI Line9 */
|
|
||||||
#define HAL_DMAMUX1_SYNC_EXTI10 LL_DMAMUX_SYNC_EXTI_LINE10 /*!< Synchronization signal from EXTI Line10 */
|
|
||||||
#define HAL_DMAMUX1_SYNC_EXTI11 LL_DMAMUX_SYNC_EXTI_LINE11 /*!< Synchronization signal from EXTI Line11 */
|
|
||||||
#define HAL_DMAMUX1_SYNC_EXTI12 LL_DMAMUX_SYNC_EXTI_LINE12 /*!< Synchronization signal from EXTI Line12 */
|
|
||||||
#define HAL_DMAMUX1_SYNC_EXTI13 LL_DMAMUX_SYNC_EXTI_LINE13 /*!< Synchronization signal from EXTI Line13 */
|
|
||||||
#define HAL_DMAMUX1_SYNC_EXTI14 LL_DMAMUX_SYNC_EXTI_LINE14 /*!< Synchronization signal from EXTI Line14 */
|
|
||||||
#define HAL_DMAMUX1_SYNC_EXTI15 LL_DMAMUX_SYNC_EXTI_LINE15 /*!< Synchronization signal from EXTI Line15 */
|
|
||||||
#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT LL_DMAMUX_SYNC_DMAMUX_CH0 /*!< Synchronization signal from DMAMUX channel0 Event */
|
|
||||||
#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT LL_DMAMUX_SYNC_DMAMUX_CH1 /*!< Synchronization signal from DMAMUX channel1 Event */
|
|
||||||
#define HAL_DMAMUX1_SYNC_LPTIM1_OUT LL_DMAMUX_SYNC_LPTIM1_OUT /*!< Synchronization signal from LPTIM1 Output */
|
|
||||||
#define HAL_DMAMUX1_SYNC_LPTIM2_OUT LL_DMAMUX_SYNC_LPTIM2_OUT /*!< Synchronization signal from LPTIM2 Output */
|
|
||||||
#define HAL_DMAMUX1_SYNC_LPTIM3_OUT LL_DMAMUX_SYNC_LPTIM3_OUT /*!< Synchronization signal from LPTIM3 Output */
|
|
||||||
|
|
||||||
#define HAL_DMAMUX1_MAX_SYNC HAL_DMAMUX1_SYNC_LPTIM3_OUT
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DMAEx_DMAMUX_SyncPolarity_selection DMAMUX SyncPolarity selection
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define HAL_DMAMUX_SYNC_NO_EVENT LL_DMAMUX_SYNC_NO_EVENT /*!< block synchronization events */
|
|
||||||
#define HAL_DMAMUX_SYNC_RISING LL_DMAMUX_SYNC_POL_RISING /*!< synchronize with rising edge events */
|
|
||||||
#define HAL_DMAMUX_SYNC_FALLING LL_DMAMUX_SYNC_POL_FALLING /*!< synchronize with falling edge events */
|
|
||||||
#define HAL_DMAMUX_SYNC_RISING_FALLING LL_DMAMUX_SYNC_POL_RISING_FALLING /*!< synchronize with rising and falling edge events */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DMAEx_DMAMUX_SignalGeneratorID_selection DMAMUX SignalGeneratorID selection
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define HAL_DMAMUX1_REQ_GEN_EXTI0 LL_DMAMUX_REQ_GEN_EXTI_LINE0 /*!< Request signal generation from EXTI Line0 */
|
|
||||||
#define HAL_DMAMUX1_REQ_GEN_EXTI1 LL_DMAMUX_REQ_GEN_EXTI_LINE1 /*!< Request signal generation from EXTI Line1 */
|
|
||||||
#define HAL_DMAMUX1_REQ_GEN_EXTI2 LL_DMAMUX_REQ_GEN_EXTI_LINE2 /*!< Request signal generation from EXTI Line2 */
|
|
||||||
#define HAL_DMAMUX1_REQ_GEN_EXTI3 LL_DMAMUX_REQ_GEN_EXTI_LINE3 /*!< Request signal generation from EXTI Line3 */
|
|
||||||
#define HAL_DMAMUX1_REQ_GEN_EXTI4 LL_DMAMUX_REQ_GEN_EXTI_LINE4 /*!< Request signal generation from EXTI Line4 */
|
|
||||||
#define HAL_DMAMUX1_REQ_GEN_EXTI5 LL_DMAMUX_REQ_GEN_EXTI_LINE5 /*!< Request signal generation from EXTI Line5 */
|
|
||||||
#define HAL_DMAMUX1_REQ_GEN_EXTI6 LL_DMAMUX_REQ_GEN_EXTI_LINE6 /*!< Request signal generation from EXTI Line6 */
|
|
||||||
#define HAL_DMAMUX1_REQ_GEN_EXTI7 LL_DMAMUX_REQ_GEN_EXTI_LINE7 /*!< Request signal generation from EXTI Line7 */
|
|
||||||
#define HAL_DMAMUX1_REQ_GEN_EXTI8 LL_DMAMUX_REQ_GEN_EXTI_LINE8 /*!< Request signal generation from EXTI Line8 */
|
|
||||||
#define HAL_DMAMUX1_REQ_GEN_EXTI9 LL_DMAMUX_REQ_GEN_EXTI_LINE9 /*!< Request signal generation from EXTI Line9 */
|
|
||||||
#define HAL_DMAMUX1_REQ_GEN_EXTI10 LL_DMAMUX_REQ_GEN_EXTI_LINE10 /*!< Request signal generation from EXTI Line10 */
|
|
||||||
#define HAL_DMAMUX1_REQ_GEN_EXTI11 LL_DMAMUX_REQ_GEN_EXTI_LINE11 /*!< Request signal generation from EXTI Line11 */
|
|
||||||
#define HAL_DMAMUX1_REQ_GEN_EXTI12 LL_DMAMUX_REQ_GEN_EXTI_LINE12 /*!< Request signal generation from EXTI Line12 */
|
|
||||||
#define HAL_DMAMUX1_REQ_GEN_EXTI13 LL_DMAMUX_REQ_GEN_EXTI_LINE13 /*!< Request signal generation from EXTI Line13 */
|
|
||||||
#define HAL_DMAMUX1_REQ_GEN_EXTI14 LL_DMAMUX_REQ_GEN_EXTI_LINE14 /*!< Request signal generation from EXTI Line14 */
|
|
||||||
#define HAL_DMAMUX1_REQ_GEN_EXTI15 LL_DMAMUX_REQ_GEN_EXTI_LINE15 /*!< Request signal generation from EXTI Line15 */
|
|
||||||
#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT LL_DMAMUX_REQ_GEN_DMAMUX_CH0 /*!< Request signal generation from DMAMUX channel0 Event */
|
|
||||||
#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT LL_DMAMUX_REQ_GEN_DMAMUX_CH1 /*!< Request signal generation from DMAMUX channel1 Event */
|
|
||||||
#define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT LL_DMAMUX_REQ_GEN_LPTIM1_OUT /*!< Request signal generation from LPTIM1 Output */
|
|
||||||
#define HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT LL_DMAMUX_REQ_GEN_LPTIM2_OUT /*!< Request signal generation from LPTIM2 Output */
|
|
||||||
#define HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT LL_DMAMUX_REQ_GEN_LPTIM3_OUT /*!< Request signal generation from LPTIM3 Output */
|
|
||||||
|
|
||||||
#define HAL_DMAMUX1_MAX_REQ_GEN HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup DMAEx_DMAMUX_RequestGeneneratorPolarity_selection DMAMUX RequestGeneneratorPolarity selection
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define HAL_DMAMUX_REQ_GEN_NO_EVENT LL_DMAMUX_REQ_GEN_NO_EVENT /*!< block request generator events */
|
|
||||||
#define HAL_DMAMUX_REQ_GEN_RISING LL_DMAMUX_REQ_GEN_POL_RISING /*!< generate request on rising edge events */
|
|
||||||
#define HAL_DMAMUX_REQ_GEN_FALLING LL_DMAMUX_REQ_GEN_POL_FALLING /*!< generate request on falling edge events */
|
|
||||||
#define HAL_DMAMUX_REQ_GEN_RISING_FALLING LL_DMAMUX_REQ_GEN_POL_RISING_FALLING /*!< generate request on rising and falling edge events */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported macro ------------------------------------------------------------*/
|
|
||||||
|
|
||||||
/* Exported functions --------------------------------------------------------*/
|
|
||||||
/** @addtogroup DMAEx_Exported_Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* IO operation functions *****************************************************/
|
|
||||||
/** @addtogroup DMAEx_Exported_Functions_Group1
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* ------------------------- REQUEST -----------------------------------------*/
|
|
||||||
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma,
|
|
||||||
HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig);
|
|
||||||
HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma);
|
|
||||||
HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma);
|
|
||||||
/* -------------------------------------------------------------------------- */
|
|
||||||
|
|
||||||
/* ------------------------- SYNCHRO -----------------------------------------*/
|
|
||||||
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig);
|
|
||||||
/* -------------------------------------------------------------------------- */
|
|
||||||
|
|
||||||
void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/* Private macros ------------------------------------------------------------*/
|
|
||||||
/** @defgroup DMAEx_Private_Macros DMAEx Private Macros
|
|
||||||
* @brief DMAEx private macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define IS_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) (((SIGNAL_ID) == HAL_DMAMUX1_SYNC_EXTI0) || \
|
|
||||||
(((SIGNAL_ID) >= HAL_DMAMUX1_SYNC_EXTI1) && \
|
|
||||||
((SIGNAL_ID) <= HAL_DMAMUX1_MAX_SYNC)))
|
|
||||||
|
|
||||||
#define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
|
|
||||||
|
|
||||||
#define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT) || \
|
|
||||||
((POLARITY) == HAL_DMAMUX_SYNC_RISING) || \
|
|
||||||
((POLARITY) == HAL_DMAMUX_SYNC_FALLING) || \
|
|
||||||
((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING))
|
|
||||||
|
|
||||||
#define IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE) || ((SYNC) == ENABLE))
|
|
||||||
|
|
||||||
#define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE) || \
|
|
||||||
((EVENT) == ENABLE))
|
|
||||||
|
|
||||||
#define IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) (((SIGNAL_ID) == HAL_DMAMUX1_REQ_GEN_EXTI0) || \
|
|
||||||
(((SIGNAL_ID) >= HAL_DMAMUX1_REQ_GEN_EXTI1) && \
|
|
||||||
((SIGNAL_ID) <= HAL_DMAMUX1_MAX_REQ_GEN)))
|
|
||||||
|
|
||||||
#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
|
|
||||||
|
|
||||||
#define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT)|| \
|
|
||||||
((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING) || \
|
|
||||||
((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING) || \
|
|
||||||
((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* STM32WLxx_HAL_DMA_EX_H */
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,330 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32wlxx_hal_exti.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief Header file of EXTI HAL module.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
|
||||||
* All rights reserved.</center></h2>
|
|
||||||
*
|
|
||||||
* This software component is licensed by ST under BSD 3-Clause license,
|
|
||||||
* the "License"; You may not use this file except in compliance with the
|
|
||||||
* License. You may obtain a copy of the License at:
|
|
||||||
* opensource.org/licenses/BSD-3-Clause
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef STM32WLxx_HAL_EXTI_H
|
|
||||||
#define STM32WLxx_HAL_EXTI_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32wlxx_hal_def.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32WLxx_HAL_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup EXTI EXTI
|
|
||||||
* @brief EXTI HAL module driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
|
|
||||||
/** @defgroup EXTI_Exported_Types EXTI Exported Types
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
HAL_EXTI_COMMON_CB_ID = 0x00U,
|
|
||||||
} EXTI_CallbackIDTypeDef;
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief EXTI Handle structure definition
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t Line; /*!< Exti line number */
|
|
||||||
void (* PendingCallback)(void); /*!< Exti pending callback */
|
|
||||||
} EXTI_HandleTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief EXTI Configuration structure definition
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t Line; /*!< The Exti line to be configured. This parameter
|
|
||||||
can be a value of @ref EXTI_Line */
|
|
||||||
uint32_t Mode; /*!< The Exit Mode to be configured for a core.
|
|
||||||
This parameter can be a combination of @ref EXTI_Mode */
|
|
||||||
uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter
|
|
||||||
can be a value of @ref EXTI_Trigger */
|
|
||||||
uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured.
|
|
||||||
This parameter is only possible for line 0 to 15. It
|
|
||||||
can be a value of @ref EXTI_GPIOSel */
|
|
||||||
} EXTI_ConfigTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
|
||||||
/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup EXTI_Line EXTI Line
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define EXTI_LINE_0 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x00u)
|
|
||||||
#define EXTI_LINE_1 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x01u)
|
|
||||||
#define EXTI_LINE_2 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x02u)
|
|
||||||
#define EXTI_LINE_3 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x03u)
|
|
||||||
#define EXTI_LINE_4 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x04u)
|
|
||||||
#define EXTI_LINE_5 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x05u)
|
|
||||||
#define EXTI_LINE_6 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x06u)
|
|
||||||
#define EXTI_LINE_7 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x07u)
|
|
||||||
#define EXTI_LINE_8 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x08u)
|
|
||||||
#define EXTI_LINE_9 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x09u)
|
|
||||||
#define EXTI_LINE_10 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Au)
|
|
||||||
#define EXTI_LINE_11 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Bu)
|
|
||||||
#define EXTI_LINE_12 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Cu)
|
|
||||||
#define EXTI_LINE_13 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Du)
|
|
||||||
#define EXTI_LINE_14 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Eu)
|
|
||||||
#define EXTI_LINE_15 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Fu)
|
|
||||||
#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | 0x10u)
|
|
||||||
#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | 0x11u)
|
|
||||||
#define EXTI_LINE_18 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | 0x12u)
|
|
||||||
#define EXTI_LINE_19 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | 0x13u)
|
|
||||||
#define EXTI_LINE_20 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | 0x14u)
|
|
||||||
#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x15u)
|
|
||||||
#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x16u)
|
|
||||||
#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | 0x17u)
|
|
||||||
#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | 0x18u)
|
|
||||||
#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | 0x19u)
|
|
||||||
#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | 0x1Au)
|
|
||||||
#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | 0x1Bu)
|
|
||||||
#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | 0x1Cu)
|
|
||||||
#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | 0x1Du)
|
|
||||||
#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | 0x1Eu)
|
|
||||||
#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | 0x1Fu)
|
|
||||||
#define EXTI_LINE_32 (EXTI_RESERVED | EXTI_REG2 | 0x00u)
|
|
||||||
#define EXTI_LINE_33 (EXTI_RESERVED | EXTI_REG2 | 0x01u)
|
|
||||||
#define EXTI_LINE_34 (EXTI_CONFIG | EXTI_REG2 | 0x02u)
|
|
||||||
#define EXTI_LINE_35 (EXTI_RESERVED | EXTI_REG2 | 0x03u)
|
|
||||||
#if defined (DUAL_CORE)
|
|
||||||
#define EXTI_LINE_36 (EXTI_DIRECT | EXTI_REG2 | 0x04u)
|
|
||||||
#define EXTI_LINE_37 (EXTI_DIRECT | EXTI_REG2 | 0x05u)
|
|
||||||
#else
|
|
||||||
#define EXTI_LINE_36 (EXTI_RESERVED | EXTI_REG2 | 0x04u)
|
|
||||||
#define EXTI_LINE_37 (EXTI_RESERVED | EXTI_REG2 | 0x05u)
|
|
||||||
#endif
|
|
||||||
#define EXTI_LINE_38 (EXTI_DIRECT | EXTI_REG2 | 0x06u)
|
|
||||||
#if defined (DUAL_CORE)
|
|
||||||
#define EXTI_LINE_39 (EXTI_DIRECT | EXTI_REG2 | 0x07u)
|
|
||||||
#define EXTI_LINE_40 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG2 | 0x08u)
|
|
||||||
#define EXTI_LINE_41 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG2 | 0x09u)
|
|
||||||
#else
|
|
||||||
#define EXTI_LINE_39 (EXTI_RESERVED | EXTI_REG2 | 0x07u)
|
|
||||||
#define EXTI_LINE_40 (EXTI_RESERVED | EXTI_REG2 | 0x08u)
|
|
||||||
#define EXTI_LINE_41 (EXTI_RESERVED | EXTI_REG2 | 0x09u)
|
|
||||||
#endif
|
|
||||||
#define EXTI_LINE_42 (EXTI_DIRECT | EXTI_REG2 | 0x0Au)
|
|
||||||
#define EXTI_LINE_43 (EXTI_DIRECT | EXTI_REG2 | 0x0Bu)
|
|
||||||
#define EXTI_LINE_44 (EXTI_DIRECT | EXTI_REG2 | 0x0Cu)
|
|
||||||
#define EXTI_LINE_45 (EXTI_CONFIG | EXTI_REG2 | 0x0Du)
|
|
||||||
#define EXTI_LINE_46 (EXTI_DIRECT | EXTI_REG2 | 0x0Eu)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup EXTI_Mode EXTI Mode
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define EXTI_MODE_NONE 0x00000000u
|
|
||||||
#define EXTI_MODE_INTERRUPT 0x00000001u
|
|
||||||
#define EXTI_MODE_EVENT 0x00000002u
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup EXTI_Trigger EXTI Trigger
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define EXTI_TRIGGER_NONE 0x00000000u
|
|
||||||
#define EXTI_TRIGGER_RISING 0x00000001u
|
|
||||||
#define EXTI_TRIGGER_FALLING 0x00000002u
|
|
||||||
#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup EXTI_GPIOSel EXTI GPIOSel
|
|
||||||
* @brief
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define EXTI_GPIOA 0x00000000u
|
|
||||||
#define EXTI_GPIOB 0x00000001u
|
|
||||||
#define EXTI_GPIOC 0x00000002u
|
|
||||||
#define EXTI_GPIOH 0x00000007u
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported macro ------------------------------------------------------------*/
|
|
||||||
/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private constants --------------------------------------------------------*/
|
|
||||||
/** @defgroup EXTI_Private_Constants EXTI Private Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/**
|
|
||||||
* @brief EXTI Line property definition
|
|
||||||
*/
|
|
||||||
#define EXTI_PROPERTY_SHIFT 24u
|
|
||||||
#define EXTI_DIRECT (0x01uL << EXTI_PROPERTY_SHIFT)
|
|
||||||
#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)
|
|
||||||
#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
|
|
||||||
#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT)
|
|
||||||
#define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief EXTI Event presence definition
|
|
||||||
*/
|
|
||||||
#define EXTI_EVENT_PRESENCE_SHIFT 28u
|
|
||||||
#define EXTI_EVENT_PRESENCE_MASK (0x01uL << EXTI_EVENT_PRESENCE_SHIFT)
|
|
||||||
#define EXTI_EVENT EXTI_EVENT_PRESENCE_MASK
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief EXTI Register and bit usage
|
|
||||||
*/
|
|
||||||
#define EXTI_REG_SHIFT 16u
|
|
||||||
#define EXTI_REG1 (0x00uL << EXTI_REG_SHIFT)
|
|
||||||
#define EXTI_REG2 (0x01uL << EXTI_REG_SHIFT)
|
|
||||||
#define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2)
|
|
||||||
#define EXTI_PIN_MASK 0x0000001Fu
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief EXTI Mask for interrupt & event mode
|
|
||||||
*/
|
|
||||||
#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief EXTI Mask for trigger possibilities
|
|
||||||
*/
|
|
||||||
#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief EXTI Line number
|
|
||||||
*/
|
|
||||||
#define EXTI_LINE_NB 47uL
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private macros ------------------------------------------------------------*/
|
|
||||||
/** @defgroup EXTI_Private_Macros EXTI Private Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_EVENT_PRESENCE_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00u) && \
|
|
||||||
((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \
|
|
||||||
(((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
|
|
||||||
(((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
|
|
||||||
(((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \
|
|
||||||
(((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u))))
|
|
||||||
|
|
||||||
#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \
|
|
||||||
(((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u))
|
|
||||||
|
|
||||||
#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
|
|
||||||
|
|
||||||
#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING)
|
|
||||||
|
|
||||||
#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u)
|
|
||||||
|
|
||||||
#define IS_EXTI_EVENT_PRESENT(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_EVENT) != 0x00u)
|
|
||||||
|
|
||||||
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
|
|
||||||
((__PORT__) == EXTI_GPIOB) || \
|
|
||||||
((__PORT__) == EXTI_GPIOC) || \
|
|
||||||
((__PORT__) == EXTI_GPIOH))
|
|
||||||
|
|
||||||
#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/* Exported functions --------------------------------------------------------*/
|
|
||||||
/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
|
|
||||||
* @brief EXTI Exported Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
|
|
||||||
* @brief Configuration functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Configuration functions ****************************************************/
|
|
||||||
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
|
|
||||||
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
|
|
||||||
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
|
|
||||||
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
|
|
||||||
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
|
|
||||||
* @brief IO operation functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* IO operation functions *****************************************************/
|
|
||||||
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
|
|
||||||
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
|
|
||||||
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
|
|
||||||
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* STM32WLxx_HAL_EXTI_H */
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,133 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32wlxx_hal_flash_ex.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief Header file of FLASH HAL Extended module.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
|
||||||
* All rights reserved.</center></h2>
|
|
||||||
*
|
|
||||||
* This software component is licensed by ST under BSD 3-Clause license,
|
|
||||||
* the "License"; You may not use this file except in compliance with the
|
|
||||||
* License. You may obtain a copy of the License at:
|
|
||||||
* opensource.org/licenses/BSD-3-Clause
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef STM32WLxx_HAL_FLASH_EX_H
|
|
||||||
#define STM32WLxx_HAL_FLASH_EX_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32wlxx_hal_def.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32WLxx_HAL_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup FLASHEx
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
|
||||||
/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/** @defgroup FLASHEx_EMPTY_CHECK FLASHEx Empty Check
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define FLASH_PROG_NOT_EMPTY 0x00000000U /*!< 1st location in Flash is programmed */
|
|
||||||
#define FLASH_PROG_EMPTY FLASH_ACR_EMPTY /*!< 1st location in Flash is empty */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup FLASHEx_PRIV_MODE_CFG FLASHEx privilege mode configuration
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define FLASH_PRIV_GRANTED 0x00000000U /*!< access to Flash registers is granted */
|
|
||||||
#define FLASH_PRIV_DENIED FLASH_ACR2_PRIVMODE /*!< access to Flash registers is denied to non-privilege access */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported macro ------------------------------------------------------------*/
|
|
||||||
/* Exported functions --------------------------------------------------------*/
|
|
||||||
/** @addtogroup FLASHEx_Exported_Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Extended Program operation functions *************************************/
|
|
||||||
/** @addtogroup FLASHEx_Exported_Functions_Group1
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
|
|
||||||
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
|
|
||||||
uint32_t HAL_FLASHEx_FlashEmptyCheck(void);
|
|
||||||
void HAL_FLASHEx_ForceFlashEmpty(uint32_t FlashEmpty);
|
|
||||||
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
|
|
||||||
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
|
|
||||||
void HAL_FLASHEx_SuspendOperation(void);
|
|
||||||
void HAL_FLASHEx_AllowOperation(void);
|
|
||||||
uint32_t HAL_FLASHEx_IsOperationSuspended(void);
|
|
||||||
#if defined(DUAL_CORE)
|
|
||||||
void HAL_FLASHEx_DisableC2Debug(void);
|
|
||||||
void HAL_FLASHEx_EnableC2Debug(void);
|
|
||||||
void HAL_FLASHEx_EnableSecHideProtection(void);
|
|
||||||
void HAL_FLASHEx_ConfigPrivMode(uint32_t PrivMode);
|
|
||||||
uint32_t HAL_FLASHEx_GetPrivMode(void);
|
|
||||||
#endif /* DUAL_CORE */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private macros ------------------------------------------------------------*/
|
|
||||||
/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define IS_FLASH_EMPTY_CHECK(__VALUE__) (((__VALUE__) == FLASH_PROG_EMPTY) || ((__VALUE__) == FLASH_PROG_NOT_EMPTY))
|
|
||||||
|
|
||||||
#define IS_FLASH_CFGPRIVMODE(__VALUE__) (((__VALUE__) == FLASH_PRIV_GRANTED) || ((__VALUE__) == FLASH_PRIV_DENIED))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private Functions ---------------------------------------------------------*/
|
|
||||||
/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
void FLASH_PageErase(uint32_t Page);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* STM32WLxx_HAL_FLASH_EX_H */
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,326 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32wlxx_hal_gpio.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief Header file of GPIO HAL module.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
|
||||||
* All rights reserved.</center></h2>
|
|
||||||
*
|
|
||||||
* This software component is licensed by ST under BSD 3-Clause license,
|
|
||||||
* the "License"; You may not use this file except in compliance with the
|
|
||||||
* License. You may obtain a copy of the License at:
|
|
||||||
* opensource.org/licenses/BSD-3-Clause
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef STM32WLxx_HAL_GPIO_H
|
|
||||||
#define STM32WLxx_HAL_GPIO_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32wlxx_hal_def.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32WLxx_HAL_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup GPIO GPIO
|
|
||||||
* @brief GPIO HAL module driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
|
|
||||||
/** @defgroup GPIO_Exported_Types GPIO Exported Types
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/**
|
|
||||||
* @brief GPIO Init structure definition
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
|
|
||||||
This parameter can be any value of @ref GPIO_pins */
|
|
||||||
|
|
||||||
uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
|
|
||||||
This parameter can be a value of @ref GPIO_mode */
|
|
||||||
|
|
||||||
uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
|
|
||||||
This parameter can be a value of @ref GPIO_pull */
|
|
||||||
|
|
||||||
uint32_t Speed; /*!< Specifies the speed for the selected pins.
|
|
||||||
This parameter can be a value of @ref GPIO_speed */
|
|
||||||
|
|
||||||
uint32_t Alternate; /*!< Peripheral to be connected to the selected pins
|
|
||||||
This parameter can be a value of @ref GPIOEx_Alternate_function_selection */
|
|
||||||
} GPIO_InitTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief GPIO Bit SET and Bit RESET enumeration
|
|
||||||
*/
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
GPIO_PIN_RESET = 0U,
|
|
||||||
GPIO_PIN_SET
|
|
||||||
} GPIO_PinState;
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
|
||||||
/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/** @defgroup GPIO_pins GPIO pins
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
|
|
||||||
#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
|
|
||||||
#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
|
|
||||||
#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
|
|
||||||
#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
|
|
||||||
#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
|
|
||||||
#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
|
|
||||||
#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
|
|
||||||
#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
|
|
||||||
#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
|
|
||||||
#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
|
|
||||||
#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
|
|
||||||
#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
|
|
||||||
#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
|
|
||||||
#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
|
|
||||||
#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
|
|
||||||
#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
|
|
||||||
|
|
||||||
#define GPIO_PIN_MASK (0x0000FFFFu) /* PIN mask for assert test */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup GPIO_mode GPIO mode
|
|
||||||
* @brief GPIO Configuration Mode
|
|
||||||
* Elements values convention: 0x00WX00YZ
|
|
||||||
* - W : EXTI trigger detection on 3 bits
|
|
||||||
* - X : EXTI mode (IT or Event) on 2 bits
|
|
||||||
* - Y : Output type (Push Pull or Open Drain) on 1 bit
|
|
||||||
* - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */
|
|
||||||
#define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */
|
|
||||||
#define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */
|
|
||||||
#define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */
|
|
||||||
#define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */
|
|
||||||
#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */
|
|
||||||
#define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */
|
|
||||||
#define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */
|
|
||||||
#define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
|
|
||||||
#define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */
|
|
||||||
#define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */
|
|
||||||
#define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup GPIO_speed GPIO speed
|
|
||||||
* @brief GPIO Output Maximum frequency
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define GPIO_SPEED_FREQ_LOW 0x00000000u /*!< Low speed */
|
|
||||||
#define GPIO_SPEED_FREQ_MEDIUM 0x00000001u /*!< Medium speed */
|
|
||||||
#define GPIO_SPEED_FREQ_HIGH 0x00000002u /*!< High speed */
|
|
||||||
#define GPIO_SPEED_FREQ_VERY_HIGH 0x00000003u /*!< Very high speed */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup GPIO_pull GPIO pull
|
|
||||||
* @brief GPIO Pull-Up or Pull-Down Activation
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define GPIO_NOPULL 0x00000000u /*!< No Pull-up or Pull-down activation */
|
|
||||||
#define GPIO_PULLUP 0x00000001u /*!< Pull-up activation */
|
|
||||||
#define GPIO_PULLDOWN 0x00000002u /*!< Pull-down activation */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported macro ------------------------------------------------------------*/
|
|
||||||
/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Check whether the specified EXTI line flag is set or not.
|
|
||||||
* @param __EXTI_LINE__ specifies the EXTI line flag to check.
|
|
||||||
* This parameter can be GPIO_PIN_x where x can be(0..15)
|
|
||||||
* @retval The new state of __EXTI_LINE__ (SET or RESET).
|
|
||||||
*/
|
|
||||||
#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Clear the EXTI's line pending flags.
|
|
||||||
* @param __EXTI_LINE__ specifies the EXTI lines flags to clear.
|
|
||||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Check whether the specified EXTI line is asserted or not.
|
|
||||||
* @param __EXTI_LINE__ specifies the EXTI line to check.
|
|
||||||
* This parameter can be GPIO_PIN_x where x can be(0..15)
|
|
||||||
* @retval The new state of __EXTI_LINE__ (SET or RESET).
|
|
||||||
*/
|
|
||||||
#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Clear the EXTI's line pending bits.
|
|
||||||
* @param __EXTI_LINE__ specifies the EXTI lines to clear.
|
|
||||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Generate a Software interrupt on selected EXTI line.
|
|
||||||
* @param __EXTI_LINE__ specifies the EXTI line to check.
|
|
||||||
* This parameter can be GPIO_PIN_x where x can be(0..15)
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 |= (__EXTI_LINE__))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private macros ------------------------------------------------------------*/
|
|
||||||
/** @defgroup GPIO_Private_Constants GPIO Private Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define GPIO_MODE_Pos 0u
|
|
||||||
#define GPIO_MODE (0x3uL << GPIO_MODE_Pos)
|
|
||||||
#define MODE_INPUT (0x0uL << GPIO_MODE_Pos)
|
|
||||||
#define MODE_OUTPUT (0x1uL << GPIO_MODE_Pos)
|
|
||||||
#define MODE_AF (0x2uL << GPIO_MODE_Pos)
|
|
||||||
#define MODE_ANALOG (0x3uL << GPIO_MODE_Pos)
|
|
||||||
#define OUTPUT_TYPE_Pos 4u
|
|
||||||
#define OUTPUT_TYPE (0x1uL << OUTPUT_TYPE_Pos)
|
|
||||||
#define OUTPUT_PP (0x0uL << OUTPUT_TYPE_Pos)
|
|
||||||
#define OUTPUT_OD (0x1uL << OUTPUT_TYPE_Pos)
|
|
||||||
#define EXTI_MODE_Pos 16u
|
|
||||||
#define EXTI_MODE (0x3uL << EXTI_MODE_Pos)
|
|
||||||
#define EXTI_IT (0x1uL << EXTI_MODE_Pos)
|
|
||||||
#define EXTI_EVT (0x2uL << EXTI_MODE_Pos)
|
|
||||||
#define TRIGGER_MODE_Pos 20u
|
|
||||||
#define TRIGGER_MODE (0x7uL << TRIGGER_MODE_Pos)
|
|
||||||
#define TRIGGER_RISING (0x1uL << TRIGGER_MODE_Pos)
|
|
||||||
#define TRIGGER_FALLING (0x2uL << TRIGGER_MODE_Pos)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup GPIO_Private_Macros GPIO Private Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
|
|
||||||
|
|
||||||
#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
|
|
||||||
(((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
|
|
||||||
|
|
||||||
#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\
|
|
||||||
((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\
|
|
||||||
((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\
|
|
||||||
((__MODE__) == GPIO_MODE_AF_PP) ||\
|
|
||||||
((__MODE__) == GPIO_MODE_AF_OD) ||\
|
|
||||||
((__MODE__) == GPIO_MODE_IT_RISING) ||\
|
|
||||||
((__MODE__) == GPIO_MODE_IT_FALLING) ||\
|
|
||||||
((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\
|
|
||||||
((__MODE__) == GPIO_MODE_EVT_RISING) ||\
|
|
||||||
((__MODE__) == GPIO_MODE_EVT_FALLING) ||\
|
|
||||||
((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\
|
|
||||||
((__MODE__) == GPIO_MODE_ANALOG))
|
|
||||||
|
|
||||||
#define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW) ||\
|
|
||||||
((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) ||\
|
|
||||||
((__SPEED__) == GPIO_SPEED_FREQ_HIGH) ||\
|
|
||||||
((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH))
|
|
||||||
|
|
||||||
#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) ||\
|
|
||||||
((__PULL__) == GPIO_PULLUP) || \
|
|
||||||
((__PULL__) == GPIO_PULLDOWN))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Include GPIO HAL Extended module */
|
|
||||||
#include "stm32wlxx_hal_gpio_ex.h"
|
|
||||||
|
|
||||||
/* Exported functions --------------------------------------------------------*/
|
|
||||||
/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
|
|
||||||
* @brief GPIO Exported Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
|
|
||||||
* @brief Initialization and Configuration functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Initialization and de-initialization functions *****************************/
|
|
||||||
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
|
|
||||||
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
|
|
||||||
* @brief IO operation functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* IO operation functions *****************************************************/
|
|
||||||
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
|
|
||||||
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
|
|
||||||
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
|
|
||||||
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
|
|
||||||
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
|
|
||||||
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* STM32WLxx_HAL_GPIO_H */
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,184 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32wlxx_hal_gpio_ex.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief Header file of GPIO HAL Extended module.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
|
||||||
* All rights reserved.</center></h2>
|
|
||||||
*
|
|
||||||
* This software component is licensed by ST under BSD 3-Clause license,
|
|
||||||
* the "License"; You may not use this file except in compliance with the
|
|
||||||
* License. You may obtain a copy of the License at:
|
|
||||||
* opensource.org/licenses/BSD-3-Clause
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef STM32WLxx_HAL_GPIO_EX_H
|
|
||||||
#define STM32WLxx_HAL_GPIO_EX_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32wlxx_hal_def.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32WLxx_HAL_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup GPIOEx GPIOEx
|
|
||||||
* @brief GPIO Extended HAL module driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
|
||||||
/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief AF 0 selection
|
|
||||||
*/
|
|
||||||
#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO Alternate Function mapping */
|
|
||||||
#define GPIO_AF0_LSCO ((uint8_t)0x00) /*!< LSCO Alternate Function mapping */
|
|
||||||
#define GPIO_AF0_JTAG ((uint8_t)0x00) /*!< JTAG Alternate Function mapping */
|
|
||||||
#define GPIO_AF0_SWD ((uint8_t)0x00) /*!< SWD Alternate Function mapping */
|
|
||||||
#define GPIO_AF0_RTC ((uint8_t)0x00) /*!< RCT_OUT Alternate Function mapping */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief AF 1 selection
|
|
||||||
*/
|
|
||||||
#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /*!< LPTIM3 Alternate Function mapping */
|
|
||||||
#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */
|
|
||||||
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /*!< TIM2 Alternate Function mapping */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief AF 2 selection
|
|
||||||
*/
|
|
||||||
#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< TIM2 Alternate Function mapping */
|
|
||||||
#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief AF 3 selection
|
|
||||||
*/
|
|
||||||
#define GPIO_AF3_SPI2 ((uint8_t)0x03) /*!< SPI2 Alternate Function mapping */
|
|
||||||
#define GPIO_AF3_LPTIM3 ((uint8_t)0x03) /*!< LPTIM3 Alternate Function mapping */
|
|
||||||
#define GPIO_AF3_TIM1 ((uint8_t)0x03) /*!< TIM1 Alternate Function mapping */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief AF 4 selection
|
|
||||||
*/
|
|
||||||
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /*!< I2C1 Alternate Function mapping */
|
|
||||||
#define GPIO_AF4_I2C2 ((uint8_t)0x04) /*!< I2C1 Alternate Function mapping */
|
|
||||||
#define GPIO_AF4_I2C3 ((uint8_t)0x04) /*!< I2C3 Alternate Function mapping */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief AF 5 selection
|
|
||||||
*/
|
|
||||||
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI1 Alternate Function mapping */
|
|
||||||
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief AF 6 selection
|
|
||||||
*/
|
|
||||||
#define GPIO_AF6_RF_BUSY ((uint8_t)0x06) /*!< RF_BUSY Alternate Function mapping */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief AF 7 selection
|
|
||||||
*/
|
|
||||||
#define GPIO_AF7_USART1 ((uint8_t)0x07) /*!< USART1 Alternate Function mapping */
|
|
||||||
#define GPIO_AF7_USART2 ((uint8_t)0x07) /*!< USART1 Alternate Function mapping */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief AF 8 selection
|
|
||||||
*/
|
|
||||||
#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /*!< LPUART1 Alternate Function mapping */
|
|
||||||
#define GPIO_AF8_IR ((uint8_t)0x08) /*!< IR Alternate Function mapping */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief AF 12 selection
|
|
||||||
*/
|
|
||||||
#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /*!< COMP1 Alternate Function mapping */
|
|
||||||
#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /*!< COMP2 Alternate Function mapping */
|
|
||||||
#define GPIO_AF12_TIM1 ((uint8_t)0x0C) /*!< TIM1 Alternate Function mapping */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief AF 13 selection
|
|
||||||
*/
|
|
||||||
#define GPIO_AF13_DEBUG_PWR ((uint8_t)0x0D) /*!< Debug PWR Alternate Function mapping */
|
|
||||||
#define GPIO_AF13_DEBUG_RF ((uint8_t)0x0D) /*!< Debug RF Alternate Function mapping */
|
|
||||||
#define GPIO_AF13_DEBUG_SUBGHZSPI ((uint8_t)0x0D) /*!< Debug SUBGHZSPI Alternate Function mapping */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief AF 14 selection
|
|
||||||
*/
|
|
||||||
#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /*!< LPTIM2 Alternate Function mapping */
|
|
||||||
#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /*!< TIM2 Alternate Function mapping */
|
|
||||||
#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /*!< TIM16 Alternate Function mapping */
|
|
||||||
#define GPIO_AF14_TIM17 ((uint8_t)0x0E) /*!< TIM17 Alternate Function mapping */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief AF 15 selection
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /*!< EVENTOUT Alternate Function mapping */
|
|
||||||
|
|
||||||
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F)
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported macro ------------------------------------------------------------*/
|
|
||||||
/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup GPIOEx_Get_Port_Index GPIOEx Get Port Index
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\
|
|
||||||
((__GPIOx__) == (GPIOB))? 1uL :\
|
|
||||||
((__GPIOx__) == (GPIOC))? 2uL : 7uL)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported functions --------------------------------------------------------*/
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* STM32WLxx_HAL_GPIO_EX_H */
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,325 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32wlxx_hal_gtzc.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief Header file of GTZC HAL module.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
|
||||||
* All rights reserved.</center></h2>
|
|
||||||
*
|
|
||||||
* This software component is licensed by ST under BSD 3-Clause license,
|
|
||||||
* the "License"; You may not use this file except in compliance with the
|
|
||||||
* License. You may obtain a copy of the License at:
|
|
||||||
* opensource.org/licenses/BSD-3-Clause
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef STM32WLxx_HAL_GTZC_H
|
|
||||||
#define STM32WLxx_HAL_GTZC_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32wlxx_hal_def.h"
|
|
||||||
|
|
||||||
#if defined(GTZC_TZSC)
|
|
||||||
|
|
||||||
/** @addtogroup STM32WLxx_HAL_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup GTZC
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
/** @defgroup GTZC_Exported_Types GTZC Exported Types
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/**
|
|
||||||
* @brief GTZC TZSC MPCWM structure
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t AreaId; /*!< Area identifier field. It can be a value of @ref
|
|
||||||
GTZC_MPCWM_AreaId */
|
|
||||||
uint32_t Length; /*!< length of the unprivileged area starting from selected
|
|
||||||
memory base address. It must be aligned on 2kB for Flash
|
|
||||||
areas and 1kB for Sram ones. */
|
|
||||||
} MPCWM_ConfigTypeDef;
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/* Private constants --------------------------------------------------------*/
|
|
||||||
/** @defgroup GTZC_Private_Constants GTZC Private Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/**
|
|
||||||
* @brief GTZC structure definitions for IP identifier parameter (PeriphId)
|
|
||||||
* used in HAL_GTZC_TZSC_ConfigPeriphAttributes and
|
|
||||||
* HAL_GTZC_TZSC_GetConfigPeriphAttributes functions and also in all
|
|
||||||
* HAL_GTZC_TZIC related functions bitmap:
|
|
||||||
* bits[31:28] Field "register". Define the register an IP belongs to.
|
|
||||||
* Each bit is dedicated to a single register.
|
|
||||||
* bit[5] Field "all Ips". If this bit is set then the PeriphId
|
|
||||||
* targets all Ips within register.
|
|
||||||
* bits[4:0] Field "bit position". Define the bit position within
|
|
||||||
* the register dedicated to the IP, value from 0 to 31.
|
|
||||||
*/
|
|
||||||
#define GTZC_PERIPH_REG_Pos (28U)
|
|
||||||
#define GTZC_PERIPH_REG_Msk (0xFUL << GTZC_PERIPH_REG_Pos) /*0 xF0000000 */
|
|
||||||
#define GTZC_PERIPH_REG1 (0x0UL << GTZC_PERIPH_REG_Pos)
|
|
||||||
#define GTZC_PERIPH_ALLPERIPH_Pos (5U)
|
|
||||||
#define GTZC_PERIPH_ALLPERIPH_Msk (0x1UL << GTZC_PERIPH_ALLPERIPH_Pos) /* 0x00000020 */
|
|
||||||
#define GTZC_PERIPH_BITPOS_Pos (0U)
|
|
||||||
#define GTZC_PERIPH_BITPOS_Msk (0x1FUL << GTZC_PERIPH_BITPOS_Pos) /* 0x0000001F */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief GTZC TZSC MPCWM Watermark granularity depending on area
|
|
||||||
*/
|
|
||||||
#define GTZC_TZSC_MPCWM_GRANULARITY_FLASH_OFFSET 11U
|
|
||||||
#define GTZC_TZSC_MPCWM_GRANULARITY_FLASH (1UL << GTZC_TZSC_MPCWM_GRANULARITY_FLASH_OFFSET) /* 2 kB */
|
|
||||||
#define GTZC_TZSC_MPCWM_GRANULARITY_SRAM1_OFFSET 10U
|
|
||||||
#define GTZC_TZSC_MPCWM_GRANULARITY_SRAM1 (1UL << GTZC_TZSC_MPCWM_GRANULARITY_SRAM1_OFFSET) /* 1 kB */
|
|
||||||
#define GTZC_TZSC_MPCWM_GRANULARITY_SRAM2_OFFSET 10U
|
|
||||||
#define GTZC_TZSC_MPCWM_GRANULARITY_SRAM2 (1UL << GTZC_TZSC_MPCWM_GRANULARITY_SRAM2_OFFSET) /* 1 kB */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/** @defgroup GTZC_Exported_Constants GTZC Exported Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup GTZC_TZSC_Peripheral_Attribute GTZC TZSC Peripheral Attribute
|
|
||||||
* bitmap: bit0 : Sec Attr (0 = Ns, 1 = Sec)
|
|
||||||
* bit1 : PrivAttr (0 = NonPriv, 1 = Priv)
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define GTZC_TZSC_ATTRIBUTE_NSEC 0x00U
|
|
||||||
#define GTZC_TZSC_ATTRIBUTE_SEC 0x01U
|
|
||||||
#define GTZC_TZSC_ATTRIBUTE_NPRIV 0x00U
|
|
||||||
#define GTZC_TZSC_ATTRIBUTE_PRIV 0x02U
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup GTZC_Peripheral_Identification GTZC Peripheral Identification
|
|
||||||
* user-oriented definition for each IP identifier parameter (PeriphId)
|
|
||||||
* used in HAL_GTZC_TZSC_ConfigPeriphAttributes and HAL_GTZC_TZSC_GetConfigPeriphAttributes
|
|
||||||
* functions and also in all HAL_GTZC_TZIC relative functions.
|
|
||||||
* @note user can also select all IPs using specific define
|
|
||||||
* @note that two maximum values are also defined here:
|
|
||||||
* - max number of securable AHB/APB peripherals or masters (used in
|
|
||||||
* TZSC sub-block)
|
|
||||||
* - max number of securable and security-aware AHB/APB peripherals
|
|
||||||
* or masters (used in TZIC sub-block)
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define GTZC_PERIPH_TZIC (GTZC_PERIPH_REG1 | GTZC_CFGR1_TZIC_Pos)
|
|
||||||
#define GTZC_PERIPH_TZSC (GTZC_PERIPH_REG1 | GTZC_CFGR1_TZSC_Pos)
|
|
||||||
#define GTZC_PERIPH_AES (GTZC_PERIPH_REG1 | GTZC_CFGR1_AES_Pos)
|
|
||||||
#define GTZC_PERIPH_RNG (GTZC_PERIPH_REG1 | GTZC_CFGR1_RNG_Pos)
|
|
||||||
#define GTZC_PERIPH_SUBGHZSPI (GTZC_PERIPH_REG1 | GTZC_CFGR1_SUBGHZSPI_Pos)
|
|
||||||
#define GTZC_PERIPH_PWR (GTZC_PERIPH_REG1 | GTZC_CFGR1_PWR_Pos)
|
|
||||||
#define GTZC_PERIPH_FLASHIF (GTZC_PERIPH_REG1 | GTZC_CFGR1_FLASHIF_Pos)
|
|
||||||
#define GTZC_PERIPH_DMA1 (GTZC_PERIPH_REG1 | GTZC_CFGR1_DMA1_Pos)
|
|
||||||
#define GTZC_PERIPH_DMA2 (GTZC_PERIPH_REG1 | GTZC_CFGR1_DMA2_Pos)
|
|
||||||
#define GTZC_PERIPH_DMAMUX (GTZC_PERIPH_REG1 | GTZC_CFGR1_DMAMUX_Pos)
|
|
||||||
#define GTZC_PERIPH_FLASH (GTZC_PERIPH_REG1 | GTZC_CFGR1_FLASH_Pos)
|
|
||||||
#define GTZC_PERIPH_SRAM1 (GTZC_PERIPH_REG1 | GTZC_CFGR1_SRAM1_Pos)
|
|
||||||
#define GTZC_PERIPH_SRAM2 (GTZC_PERIPH_REG1 | GTZC_CFGR1_SRAM2_Pos)
|
|
||||||
#define GTZC_PERIPH_PKA (GTZC_PERIPH_REG1 | GTZC_CFGR1_PKA_Pos)
|
|
||||||
#define GTZC_PERIPH_TZIC_MAX GTZC_PERIPH_PKA
|
|
||||||
#define GTZC_PERIPH_ALL GTZC_PERIPH_ALLPERIPH_Msk
|
|
||||||
|
|
||||||
|
|
||||||
/* Note that two maximum values are also defined here:
|
|
||||||
* - max number of securable peripherals
|
|
||||||
* (used in TZSC sub-block)
|
|
||||||
* - max number of securable and security-aware peripherals or masters
|
|
||||||
* (used in TZIC sub-block)
|
|
||||||
*/
|
|
||||||
#define GTZC_TZSC_PERIPH_NUMBER 4U
|
|
||||||
#define GTZC_TZIC_PERIPH_NUMBER (GTZC_GET_ARRAY_INDEX(GTZC_PERIPH_PKA + 1U))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup GTZC_TZSC_Lock GTZC TZSC Lock
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define GTZC_TZSC_LOCK_OFF (0U)
|
|
||||||
#define GTZC_TZSC_LOCK_ON (1U)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup GTZC_MPCWM_AreaId GTZC MPCWM area identifier values
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define GTZC_TZSC_MPCWM_AREAID_UNPRIV (0U)
|
|
||||||
#define GTZC_TZSC_MPCWM_AREAID_UNPRIV_WRITABLE (1U)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/** @defgroup GTZC_TZIC_ILA_Pending GTZC TZIC ILA Pending
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define GTZC_TZIC_NO_ILA_EVENT (0U)
|
|
||||||
#define GTZC_TZIC_ILA_EVENT_PENDING (1U)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported macro ------------------------------------------------------------*/
|
|
||||||
/* Exported functions --------------------------------------------------------*/
|
|
||||||
/** @addtogroup GTZC_Exported_Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup GTZC_Exported_Functions_Group1
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* TZSC Initialization and Configuration functions ****************************/
|
|
||||||
HAL_StatusTypeDef HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId, uint32_t PeriphAttributes);
|
|
||||||
HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId, uint32_t *PeriphAttributes);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup GTZC_Exported_Functions_Group2
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* MPCWM Initialization and Configuration functions ***************************/
|
|
||||||
HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddress, MPCWM_ConfigTypeDef *pMPCWM_Desc);
|
|
||||||
HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAddress, MPCWM_ConfigTypeDef *pMPCWM_Desc);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup GTZC_Exported_Functions_Group3
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* TZSC and TZSC-MPCWM Lock functions *****************************************/
|
|
||||||
uint32_t HAL_GTZC_TZSC_GetLock(GTZC_TZSC_TypeDef *TZSCx);
|
|
||||||
#if defined(CORE_CM0PLUS)
|
|
||||||
void HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef *TZSCx);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup GTZC_Exported_Functions_Group4
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* TZIC Initialization and Configuration functions ****************************/
|
|
||||||
HAL_StatusTypeDef HAL_GTZC_TZIC_DisableIT(uint32_t PeriphId);
|
|
||||||
HAL_StatusTypeDef HAL_GTZC_TZIC_EnableIT(uint32_t PeriphId);
|
|
||||||
HAL_StatusTypeDef HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId, uint32_t *Flag);
|
|
||||||
HAL_StatusTypeDef HAL_GTZC_TZIC_ClearFlag(uint32_t PeriphId);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup GTZC_Exported_Functions_Group5
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
void HAL_GTZC_IRQHandler(void);
|
|
||||||
void HAL_GTZC_TZIC_Callback(uint32_t PeriphId);
|
|
||||||
#endif /* CORE_CM0PLUS */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/* Private macro ------------------------------------------------------------*/
|
|
||||||
/** @defgroup GTZC_Private_Macros GTZC Private Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/**
|
|
||||||
* @brief GTZC private macros usable to retrieve information to access register
|
|
||||||
* for a specific PeriphId
|
|
||||||
*/
|
|
||||||
#define GTZC_GET_REG_INDEX(__PERIPHERAL__) (((__PERIPHERAL__) & GTZC_PERIPH_REG_Msk) >> GTZC_PERIPH_REG_Pos)
|
|
||||||
#define GTZC_GET_PERIPH_POS(__PERIPHERAL__) ((__PERIPHERAL__) & GTZC_PERIPH_BITPOS_Msk)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief GTZC private macro to get array index of a specific PeriphId
|
|
||||||
* in case of GTZC_PERIPH_ALL usage in the two following functions:
|
|
||||||
* HAL_GTZC_TZSC_ConfigPeriphAttributes and HAL_GTZC_TZSC_GetConfigPeriphAttributes
|
|
||||||
*/
|
|
||||||
#define GTZC_GET_ARRAY_INDEX(__PERIPHERAL__) ((GTZC_GET_REG_INDEX(__PERIPHERAL__) * 32U) + GTZC_GET_PERIPH_POS(__PERIPHERAL__))
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief GTZC private macros to check function input parameters
|
|
||||||
*/
|
|
||||||
#define IS_GTZC_ATTRIBUTE(__ATTRIBUTES__) (((__ATTRIBUTES__) & ~(GTZC_TZSC_ATTRIBUTE_SEC | GTZC_TZSC_ATTRIBUTE_PRIV)) == 0x00u)
|
|
||||||
|
|
||||||
#define IS_GTZC_TZSC_PERIPHERAL(__PERIPHERAL__) (((__PERIPHERAL__) == GTZC_PERIPH_AES) || ((__PERIPHERAL__) == GTZC_PERIPH_RNG) || \
|
|
||||||
((__PERIPHERAL__) == GTZC_PERIPH_SUBGHZSPI) || ((__PERIPHERAL__) == GTZC_PERIPH_PKA) ||\
|
|
||||||
((__PERIPHERAL__) == GTZC_PERIPH_ALL))
|
|
||||||
|
|
||||||
#define IS_GTZC_TZIC_PERIPHERAL(__PERIPHERAL__) (((((__PERIPHERAL__) & ~(GTZC_PERIPH_REG_Pos | GTZC_PERIPH_BITPOS_Msk)) == 0x00u) && \
|
|
||||||
((GTZC_GET_ARRAY_INDEX(__PERIPHERAL__) <= GTZC_GET_ARRAY_INDEX(GTZC_PERIPH_TZIC_MAX)))) || \
|
|
||||||
((__PERIPHERAL__) == GTZC_PERIPH_ALLPERIPH_Msk))
|
|
||||||
|
|
||||||
#define IS_GTZC_MPCWM_MEMORY_BASEADDRESS(__BASE_ADDRESS__) (((__BASE_ADDRESS__) == FLASH_BASE) || \
|
|
||||||
((__BASE_ADDRESS__) == SRAM1_BASE) || \
|
|
||||||
((__BASE_ADDRESS__) == SRAM2_BASE))
|
|
||||||
|
|
||||||
#define IS_GTZC_MPCWM_FLASH_AREAID(__AREAID__) (((__AREAID__) == GTZC_TZSC_MPCWM_AREAID_UNPRIV) || \
|
|
||||||
((__AREAID__) == GTZC_TZSC_MPCWM_AREAID_UNPRIV_WRITABLE))
|
|
||||||
|
|
||||||
#define IS_GTZC_MPCWM_SRAM1_AREAID(__AREAID__) ((__AREAID__) == GTZC_TZSC_MPCWM_AREAID_UNPRIV)
|
|
||||||
|
|
||||||
#define IS_GTZC_MPCWM_SRAM2_AREAID(__AREAID__) ((__AREAID__) == GTZC_TZSC_MPCWM_AREAID_UNPRIV)
|
|
||||||
|
|
||||||
#define IS_GTZC_MPCWM_FLASH_LENGTH(__LENGTH__) ((((__LENGTH__) % GTZC_TZSC_MPCWM_GRANULARITY_FLASH) == 0x00u) && \
|
|
||||||
((__LENGTH__) <= FLASH_SIZE))
|
|
||||||
|
|
||||||
#define IS_GTZC_MPCWM_SRAM1_LENGTH(__LENGTH__) ((((__LENGTH__) % GTZC_TZSC_MPCWM_GRANULARITY_SRAM1) == 0x00u) && \
|
|
||||||
((__LENGTH__) <= SRAM1_SIZE))
|
|
||||||
|
|
||||||
#define IS_GTZC_MPCWM_SRAM2_LENGTH(__LENGTH__) ((((__LENGTH__) % GTZC_TZSC_MPCWM_GRANULARITY_SRAM2) == 0x00u) && \
|
|
||||||
((__LENGTH__) <= SRAM2_SIZE))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
#endif /* GTZC_TZSC */
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* STM32WLxx_HAL_GTZC_H */
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,210 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32wlxx_hal_hsem.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief Header file of HSEM HAL module.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
|
||||||
* All rights reserved.</center></h2>
|
|
||||||
*
|
|
||||||
* This software component is licensed by ST under BSD 3-Clause license,
|
|
||||||
* the "License"; You may not use this file except in compliance with the
|
|
||||||
* License. You may obtain a copy of the License at:
|
|
||||||
* opensource.org/licenses/BSD-3-Clause
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef STM32WLxx_HAL_HSEM_H
|
|
||||||
#define STM32WLxx_HAL_HSEM_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32wlxx_hal_def.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32WLxx_HAL_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup HSEM
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported macro ------------------------------------------------------------*/
|
|
||||||
/** @defgroup HSEM_Exported_Macros HSEM Exported Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief SemID to mask helper Macro.
|
|
||||||
* @param __SEMID__: semaphore ID from 0 to 15
|
|
||||||
* @retval Semaphore Mask.
|
|
||||||
*/
|
|
||||||
#define __HAL_HSEM_SEMID_TO_MASK(__SEMID__) (1 << (__SEMID__))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enables the specified HSEM interrupts.
|
|
||||||
* @param __SEM_MASK__: semaphores Mask
|
|
||||||
* @retval None.
|
|
||||||
*/
|
|
||||||
#if defined(DUAL_CORE)
|
|
||||||
#define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
|
|
||||||
(HSEM->C1IER |= (__SEM_MASK__)) : \
|
|
||||||
(HSEM->C2IER |= (__SEM_MASK__)))
|
|
||||||
#else
|
|
||||||
#define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) (HSEM->IER |= (__SEM_MASK__))
|
|
||||||
#endif /* DUAL_CORE */
|
|
||||||
/**
|
|
||||||
* @brief Disables the specified HSEM interrupts.
|
|
||||||
* @param __SEM_MASK__: semaphores Mask
|
|
||||||
* @retval None.
|
|
||||||
*/
|
|
||||||
#if defined(DUAL_CORE)
|
|
||||||
#define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
|
|
||||||
(HSEM->C1IER &= ~(__SEM_MASK__)) : \
|
|
||||||
(HSEM->C2IER &= ~(__SEM_MASK__)))
|
|
||||||
#else
|
|
||||||
#define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) (HSEM->IER &= ~(__SEM_MASK__))
|
|
||||||
#endif /* DUAL_CORE */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Checks whether interrupt has occurred or not for semaphores specified by a mask.
|
|
||||||
* @param __SEM_MASK__: semaphores Mask
|
|
||||||
* @retval semaphores Mask : Semaphores where an interrupt occurred.
|
|
||||||
*/
|
|
||||||
#if defined(DUAL_CORE)
|
|
||||||
#define __HAL_HSEM_GET_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
|
|
||||||
((__SEM_MASK__) & HSEM->C1MISR) : \
|
|
||||||
((__SEM_MASK__) & HSEM->C2MISR1))
|
|
||||||
#else
|
|
||||||
#define __HAL_HSEM_GET_IT(__SEM_MASK__) ((__SEM_MASK__) & HSEM->MISR)
|
|
||||||
#endif /* DUAL_CORE */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Get the semaphores release status flags.
|
|
||||||
* @param __SEM_MASK__: semaphores Mask
|
|
||||||
* @retval semaphores Mask : Semaphores where Release flags rise.
|
|
||||||
*/
|
|
||||||
#if defined(DUAL_CORE)
|
|
||||||
#define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
|
|
||||||
(__SEM_MASK__) & HSEM->C1ISR : \
|
|
||||||
(__SEM_MASK__) & HSEM->C2ISR)
|
|
||||||
#else
|
|
||||||
#define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((__SEM_MASK__) & HSEM->ISR)
|
|
||||||
#endif /* DUAL_CORE */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Clears the HSEM Interrupt flags.
|
|
||||||
* @param __SEM_MASK__: semaphores Mask
|
|
||||||
* @retval None.
|
|
||||||
*/
|
|
||||||
#if defined(DUAL_CORE)
|
|
||||||
#define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
|
|
||||||
(HSEM->C1ICR |= (__SEM_MASK__)) : \
|
|
||||||
(HSEM->C2ICR |= (__SEM_MASK__)))
|
|
||||||
#else
|
|
||||||
#define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) (HSEM->ICR |= (__SEM_MASK__))
|
|
||||||
#endif /* DUAL_CORE */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported functions --------------------------------------------------------*/
|
|
||||||
/** @defgroup HSEM_Exported_Functions HSEM Exported Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup HSEM_Exported_Functions_Group1 Take and Release functions
|
|
||||||
* @brief HSEM Take and Release functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* HSEM semaphore take (lock) using 2-Step method ****************************/
|
|
||||||
HAL_StatusTypeDef HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID);
|
|
||||||
/* HSEM semaphore fast take (lock) using 1-Step method ***********************/
|
|
||||||
HAL_StatusTypeDef HAL_HSEM_FastTake(uint32_t SemID);
|
|
||||||
/* HSEM Check semaphore state Taken or not **********************************/
|
|
||||||
uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID);
|
|
||||||
/* HSEM Release **************************************************************/
|
|
||||||
void HAL_HSEM_Release(uint32_t SemID, uint32_t ProcessID);
|
|
||||||
/* HSEM Release All************************************************************/
|
|
||||||
void HAL_HSEM_ReleaseAll(uint32_t Key, uint32_t CoreID);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup HSEM_Exported_Functions_Group2 HSEM Set and Get Key functions
|
|
||||||
* @brief HSEM Set and Get Key functions.
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* HSEM Set Clear Key *********************************************************/
|
|
||||||
void HAL_HSEM_SetClearKey(uint32_t Key);
|
|
||||||
/* HSEM Get Clear Key *********************************************************/
|
|
||||||
uint32_t HAL_HSEM_GetClearKey(void);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup HSEM_Exported_Functions_Group3
|
|
||||||
* @brief HSEM Notification functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* HSEM Activate HSEM Notification (When a semaphore is released) ) *****************/
|
|
||||||
void HAL_HSEM_ActivateNotification(uint32_t SemMask);
|
|
||||||
/* HSEM Deactivate HSEM Notification (When a semaphore is released) ****************/
|
|
||||||
void HAL_HSEM_DeactivateNotification(uint32_t SemMask);
|
|
||||||
/* HSEM Free Callback (When a semaphore is released) *******************************/
|
|
||||||
void HAL_HSEM_FreeCallback(uint32_t SemMask);
|
|
||||||
/* HSEM IRQ Handler **********************************************************/
|
|
||||||
void HAL_HSEM_IRQHandler(void);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private macros ------------------------------------------------------------*/
|
|
||||||
/** @defgroup HSEM_Private_Macros HSEM Private Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define IS_HSEM_SEMID(__SEMID__) ((__SEMID__) <= HSEM_SEMID_MAX )
|
|
||||||
|
|
||||||
#define IS_HSEM_PROCESSID(__PROCESSID__) ((__PROCESSID__) <= HSEM_PROCESSID_MAX )
|
|
||||||
|
|
||||||
#define IS_HSEM_KEY(__KEY__) ((__KEY__) <= HSEM_CLEAR_KEY_MAX )
|
|
||||||
|
|
||||||
#define IS_HSEM_COREID(__COREID__) (((__COREID__) == HSEM_CPU1_COREID) || \
|
|
||||||
((__COREID__) == HSEM_CPU2_COREID))
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* STM32WLxx_HAL_HSEM_H */
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,838 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32wlxx_hal_i2c.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief Header file of I2C HAL module.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
|
||||||
* All rights reserved.</center></h2>
|
|
||||||
*
|
|
||||||
* This software component is licensed by ST under BSD 3-Clause license,
|
|
||||||
* the "License"; You may not use this file except in compliance with the
|
|
||||||
* License. You may obtain a copy of the License at:
|
|
||||||
* opensource.org/licenses/BSD-3-Clause
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef STM32WLxx_HAL_I2C_H
|
|
||||||
#define STM32WLxx_HAL_I2C_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32wlxx_hal_def.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32WLxx_HAL_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup I2C
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
/** @defgroup I2C_Exported_Types I2C Exported Types
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
|
|
||||||
* @brief I2C Configuration Structure definition
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value.
|
|
||||||
This parameter calculated by referring to I2C initialization section
|
|
||||||
in Reference manual */
|
|
||||||
|
|
||||||
uint32_t OwnAddress1; /*!< Specifies the first device own address.
|
|
||||||
This parameter can be a 7-bit or 10-bit address. */
|
|
||||||
|
|
||||||
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
|
|
||||||
This parameter can be a value of @ref I2C_ADDRESSING_MODE */
|
|
||||||
|
|
||||||
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
|
|
||||||
This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
|
|
||||||
|
|
||||||
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
|
|
||||||
This parameter can be a 7-bit address. */
|
|
||||||
|
|
||||||
uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing
|
|
||||||
mode is selected.
|
|
||||||
This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
|
|
||||||
|
|
||||||
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
|
|
||||||
This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
|
|
||||||
|
|
||||||
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
|
|
||||||
This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
|
|
||||||
|
|
||||||
} I2C_InitTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup HAL_state_structure_definition HAL state structure definition
|
|
||||||
* @brief HAL State structure definition
|
|
||||||
* @note HAL I2C State value coding follow below described bitmap :\n
|
|
||||||
* b7-b6 Error information\n
|
|
||||||
* 00 : No Error\n
|
|
||||||
* 01 : Abort (Abort user request on going)\n
|
|
||||||
* 10 : Timeout\n
|
|
||||||
* 11 : Error\n
|
|
||||||
* b5 Peripheral initialization status\n
|
|
||||||
* 0 : Reset (peripheral not initialized)\n
|
|
||||||
* 1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n
|
|
||||||
* b4 (not used)\n
|
|
||||||
* x : Should be set to 0\n
|
|
||||||
* b3\n
|
|
||||||
* 0 : Ready or Busy (No Listen mode ongoing)\n
|
|
||||||
* 1 : Listen (peripheral in Address Listen Mode)\n
|
|
||||||
* b2 Intrinsic process state\n
|
|
||||||
* 0 : Ready\n
|
|
||||||
* 1 : Busy (peripheral busy with some configuration or internal operations)\n
|
|
||||||
* b1 Rx state\n
|
|
||||||
* 0 : Ready (no Rx operation ongoing)\n
|
|
||||||
* 1 : Busy (Rx operation ongoing)\n
|
|
||||||
* b0 Tx state\n
|
|
||||||
* 0 : Ready (no Tx operation ongoing)\n
|
|
||||||
* 1 : Busy (Tx operation ongoing)
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
|
|
||||||
HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
|
|
||||||
HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
|
|
||||||
HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
|
|
||||||
HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
|
|
||||||
HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */
|
|
||||||
HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
|
|
||||||
process is ongoing */
|
|
||||||
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
|
|
||||||
process is ongoing */
|
|
||||||
HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
|
|
||||||
HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
|
|
||||||
HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
|
|
||||||
|
|
||||||
} HAL_I2C_StateTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup HAL_mode_structure_definition HAL mode structure definition
|
|
||||||
* @brief HAL Mode structure definition
|
|
||||||
* @note HAL I2C Mode value coding follow below described bitmap :\n
|
|
||||||
* b7 (not used)\n
|
|
||||||
* x : Should be set to 0\n
|
|
||||||
* b6\n
|
|
||||||
* 0 : None\n
|
|
||||||
* 1 : Memory (HAL I2C communication is in Memory Mode)\n
|
|
||||||
* b5\n
|
|
||||||
* 0 : None\n
|
|
||||||
* 1 : Slave (HAL I2C communication is in Slave Mode)\n
|
|
||||||
* b4\n
|
|
||||||
* 0 : None\n
|
|
||||||
* 1 : Master (HAL I2C communication is in Master Mode)\n
|
|
||||||
* b3-b2-b1-b0 (not used)\n
|
|
||||||
* xxxx : Should be set to 0000
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */
|
|
||||||
HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */
|
|
||||||
HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
|
|
||||||
HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */
|
|
||||||
|
|
||||||
} HAL_I2C_ModeTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup I2C_Error_Code_definition I2C Error Code definition
|
|
||||||
* @brief I2C Error Code definition
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */
|
|
||||||
#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */
|
|
||||||
#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */
|
|
||||||
#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */
|
|
||||||
#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */
|
|
||||||
#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
|
|
||||||
#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
|
|
||||||
#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */
|
|
||||||
#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U) /*!< DMA Parameter Error */
|
|
||||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
|
||||||
#define HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */
|
|
||||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
|
||||||
#define HAL_I2C_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
|
|
||||||
* @brief I2C handle Structure definition
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
typedef struct __I2C_HandleTypeDef
|
|
||||||
{
|
|
||||||
I2C_TypeDef *Instance; /*!< I2C registers base address */
|
|
||||||
|
|
||||||
I2C_InitTypeDef Init; /*!< I2C communication parameters */
|
|
||||||
|
|
||||||
uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
|
|
||||||
|
|
||||||
uint16_t XferSize; /*!< I2C transfer size */
|
|
||||||
|
|
||||||
__IO uint16_t XferCount; /*!< I2C transfer counter */
|
|
||||||
|
|
||||||
__IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can
|
|
||||||
be a value of @ref I2C_XFEROPTIONS */
|
|
||||||
|
|
||||||
__IO uint32_t PreviousState; /*!< I2C communication Previous state */
|
|
||||||
|
|
||||||
HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
|
|
||||||
/*!< I2C transfer IRQ handler function pointer */
|
|
||||||
|
|
||||||
DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
|
|
||||||
|
|
||||||
DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
|
|
||||||
|
|
||||||
HAL_LockTypeDef Lock; /*!< I2C locking object */
|
|
||||||
|
|
||||||
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
|
|
||||||
|
|
||||||
__IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */
|
|
||||||
|
|
||||||
__IO uint32_t ErrorCode; /*!< I2C Error code */
|
|
||||||
|
|
||||||
__IO uint32_t AddrEventCount; /*!< I2C Address Event counter */
|
|
||||||
|
|
||||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
|
||||||
void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
|
||||||
/*!< I2C Master Tx Transfer completed callback */
|
|
||||||
void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
|
||||||
/*!< I2C Master Rx Transfer completed callback */
|
|
||||||
void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
|
||||||
/*!< I2C Slave Tx Transfer completed callback */
|
|
||||||
void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
|
||||||
/*!< I2C Slave Rx Transfer completed callback */
|
|
||||||
void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
|
||||||
/*!< I2C Listen Complete callback */
|
|
||||||
void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
|
||||||
/*!< I2C Memory Tx Transfer completed callback */
|
|
||||||
void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
|
||||||
/*!< I2C Memory Rx Transfer completed callback */
|
|
||||||
void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c);
|
|
||||||
/*!< I2C Error callback */
|
|
||||||
void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
|
||||||
/*!< I2C Abort callback */
|
|
||||||
|
|
||||||
void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
|
|
||||||
/*!< I2C Slave Address Match callback */
|
|
||||||
|
|
||||||
void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c);
|
|
||||||
/*!< I2C Msp Init callback */
|
|
||||||
void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c);
|
|
||||||
/*!< I2C Msp DeInit callback */
|
|
||||||
|
|
||||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
|
||||||
} I2C_HandleTypeDef;
|
|
||||||
|
|
||||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
|
||||||
/**
|
|
||||||
* @brief HAL I2C Callback ID enumeration definition
|
|
||||||
*/
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */
|
|
||||||
HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */
|
|
||||||
HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */
|
|
||||||
HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */
|
|
||||||
HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */
|
|
||||||
HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */
|
|
||||||
HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */
|
|
||||||
HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */
|
|
||||||
HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */
|
|
||||||
|
|
||||||
HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */
|
|
||||||
HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */
|
|
||||||
|
|
||||||
} HAL_I2C_CallbackIDTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief HAL I2C Callback pointer definition
|
|
||||||
*/
|
|
||||||
typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c);
|
|
||||||
/*!< pointer to an I2C callback function */
|
|
||||||
typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection,
|
|
||||||
uint16_t AddrMatchCode);
|
|
||||||
/*!< pointer to an I2C Address Match callback function */
|
|
||||||
|
|
||||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
|
||||||
|
|
||||||
/** @defgroup I2C_Exported_Constants I2C Exported Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)
|
|
||||||
#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
|
|
||||||
#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
|
|
||||||
#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
|
|
||||||
#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
|
|
||||||
#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE)
|
|
||||||
|
|
||||||
/* List of XferOptions in usage of :
|
|
||||||
* 1- Restart condition in all use cases (direction change or not)
|
|
||||||
*/
|
|
||||||
#define I2C_OTHER_FRAME (0x000000AAU)
|
|
||||||
#define I2C_OTHER_AND_LAST_FRAME (0x0000AA00U)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define I2C_ADDRESSINGMODE_7BIT (0x00000001U)
|
|
||||||
#define I2C_ADDRESSINGMODE_10BIT (0x00000002U)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define I2C_DUALADDRESS_DISABLE (0x00000000U)
|
|
||||||
#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define I2C_OA2_NOMASK ((uint8_t)0x00U)
|
|
||||||
#define I2C_OA2_MASK01 ((uint8_t)0x01U)
|
|
||||||
#define I2C_OA2_MASK02 ((uint8_t)0x02U)
|
|
||||||
#define I2C_OA2_MASK03 ((uint8_t)0x03U)
|
|
||||||
#define I2C_OA2_MASK04 ((uint8_t)0x04U)
|
|
||||||
#define I2C_OA2_MASK05 ((uint8_t)0x05U)
|
|
||||||
#define I2C_OA2_MASK06 ((uint8_t)0x06U)
|
|
||||||
#define I2C_OA2_MASK07 ((uint8_t)0x07U)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define I2C_GENERALCALL_DISABLE (0x00000000U)
|
|
||||||
#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define I2C_NOSTRETCH_DISABLE (0x00000000U)
|
|
||||||
#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define I2C_MEMADD_SIZE_8BIT (0x00000001U)
|
|
||||||
#define I2C_MEMADD_SIZE_16BIT (0x00000002U)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define I2C_DIRECTION_TRANSMIT (0x00000000U)
|
|
||||||
#define I2C_DIRECTION_RECEIVE (0x00000001U)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define I2C_RELOAD_MODE I2C_CR2_RELOAD
|
|
||||||
#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
|
|
||||||
#define I2C_SOFTEND_MODE (0x00000000U)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define I2C_NO_STARTSTOP (0x00000000U)
|
|
||||||
#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
|
|
||||||
#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
|
|
||||||
#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
|
|
||||||
* @brief I2C Interrupt definition
|
|
||||||
* Elements values convention: 0xXXXXXXXX
|
|
||||||
* - XXXXXXXX : Interrupt control mask
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define I2C_IT_ERRI I2C_CR1_ERRIE
|
|
||||||
#define I2C_IT_TCI I2C_CR1_TCIE
|
|
||||||
#define I2C_IT_STOPI I2C_CR1_STOPIE
|
|
||||||
#define I2C_IT_NACKI I2C_CR1_NACKIE
|
|
||||||
#define I2C_IT_ADDRI I2C_CR1_ADDRIE
|
|
||||||
#define I2C_IT_RXI I2C_CR1_RXIE
|
|
||||||
#define I2C_IT_TXI I2C_CR1_TXIE
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup I2C_Flag_definition I2C Flag definition
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define I2C_FLAG_TXE I2C_ISR_TXE
|
|
||||||
#define I2C_FLAG_TXIS I2C_ISR_TXIS
|
|
||||||
#define I2C_FLAG_RXNE I2C_ISR_RXNE
|
|
||||||
#define I2C_FLAG_ADDR I2C_ISR_ADDR
|
|
||||||
#define I2C_FLAG_AF I2C_ISR_NACKF
|
|
||||||
#define I2C_FLAG_STOPF I2C_ISR_STOPF
|
|
||||||
#define I2C_FLAG_TC I2C_ISR_TC
|
|
||||||
#define I2C_FLAG_TCR I2C_ISR_TCR
|
|
||||||
#define I2C_FLAG_BERR I2C_ISR_BERR
|
|
||||||
#define I2C_FLAG_ARLO I2C_ISR_ARLO
|
|
||||||
#define I2C_FLAG_OVR I2C_ISR_OVR
|
|
||||||
#define I2C_FLAG_PECERR I2C_ISR_PECERR
|
|
||||||
#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
|
|
||||||
#define I2C_FLAG_ALERT I2C_ISR_ALERT
|
|
||||||
#define I2C_FLAG_BUSY I2C_ISR_BUSY
|
|
||||||
#define I2C_FLAG_DIR I2C_ISR_DIR
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported macros -----------------------------------------------------------*/
|
|
||||||
|
|
||||||
/** @defgroup I2C_Exported_Macros I2C Exported Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @brief Reset I2C handle state.
|
|
||||||
* @param __HANDLE__ specifies the I2C Handle.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
|
||||||
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
|
||||||
(__HANDLE__)->State = HAL_I2C_STATE_RESET; \
|
|
||||||
(__HANDLE__)->MspInitCallback = NULL; \
|
|
||||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
|
||||||
} while(0)
|
|
||||||
#else
|
|
||||||
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
|
|
||||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
|
||||||
|
|
||||||
/** @brief Enable the specified I2C interrupt.
|
|
||||||
* @param __HANDLE__ specifies the I2C Handle.
|
|
||||||
* @param __INTERRUPT__ specifies the interrupt source to enable.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg @ref I2C_IT_ERRI Errors interrupt enable
|
|
||||||
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
|
|
||||||
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
|
|
||||||
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
|
|
||||||
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
|
|
||||||
* @arg @ref I2C_IT_RXI RX interrupt enable
|
|
||||||
* @arg @ref I2C_IT_TXI TX interrupt enable
|
|
||||||
*
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
|
|
||||||
|
|
||||||
/** @brief Disable the specified I2C interrupt.
|
|
||||||
* @param __HANDLE__ specifies the I2C Handle.
|
|
||||||
* @param __INTERRUPT__ specifies the interrupt source to disable.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg @ref I2C_IT_ERRI Errors interrupt enable
|
|
||||||
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
|
|
||||||
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
|
|
||||||
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
|
|
||||||
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
|
|
||||||
* @arg @ref I2C_IT_RXI RX interrupt enable
|
|
||||||
* @arg @ref I2C_IT_TXI TX interrupt enable
|
|
||||||
*
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
|
|
||||||
|
|
||||||
/** @brief Check whether the specified I2C interrupt source is enabled or not.
|
|
||||||
* @param __HANDLE__ specifies the I2C Handle.
|
|
||||||
* @param __INTERRUPT__ specifies the I2C interrupt source to check.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg @ref I2C_IT_ERRI Errors interrupt enable
|
|
||||||
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
|
|
||||||
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
|
|
||||||
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
|
|
||||||
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
|
|
||||||
* @arg @ref I2C_IT_RXI RX interrupt enable
|
|
||||||
* @arg @ref I2C_IT_TXI TX interrupt enable
|
|
||||||
*
|
|
||||||
* @retval The new state of __INTERRUPT__ (SET or RESET).
|
|
||||||
*/
|
|
||||||
#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & \
|
|
||||||
(__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
|
||||||
|
|
||||||
/** @brief Check whether the specified I2C flag is set or not.
|
|
||||||
* @param __HANDLE__ specifies the I2C Handle.
|
|
||||||
* @param __FLAG__ specifies the flag to check.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg @ref I2C_FLAG_TXE Transmit data register empty
|
|
||||||
* @arg @ref I2C_FLAG_TXIS Transmit interrupt status
|
|
||||||
* @arg @ref I2C_FLAG_RXNE Receive data register not empty
|
|
||||||
* @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
|
|
||||||
* @arg @ref I2C_FLAG_AF Acknowledge failure received flag
|
|
||||||
* @arg @ref I2C_FLAG_STOPF STOP detection flag
|
|
||||||
* @arg @ref I2C_FLAG_TC Transfer complete (master mode)
|
|
||||||
* @arg @ref I2C_FLAG_TCR Transfer complete reload
|
|
||||||
* @arg @ref I2C_FLAG_BERR Bus error
|
|
||||||
* @arg @ref I2C_FLAG_ARLO Arbitration lost
|
|
||||||
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
|
|
||||||
* @arg @ref I2C_FLAG_PECERR PEC error in reception
|
|
||||||
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
|
|
||||||
* @arg @ref I2C_FLAG_ALERT SMBus alert
|
|
||||||
* @arg @ref I2C_FLAG_BUSY Bus busy
|
|
||||||
* @arg @ref I2C_FLAG_DIR Transfer direction (slave mode)
|
|
||||||
*
|
|
||||||
* @retval The new state of __FLAG__ (SET or RESET).
|
|
||||||
*/
|
|
||||||
#define I2C_FLAG_MASK (0x0001FFFFU)
|
|
||||||
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \
|
|
||||||
(__FLAG__)) == (__FLAG__)) ? SET : RESET)
|
|
||||||
|
|
||||||
/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
|
|
||||||
* @param __HANDLE__ specifies the I2C Handle.
|
|
||||||
* @param __FLAG__ specifies the flag to clear.
|
|
||||||
* This parameter can be any combination of the following values:
|
|
||||||
* @arg @ref I2C_FLAG_TXE Transmit data register empty
|
|
||||||
* @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
|
|
||||||
* @arg @ref I2C_FLAG_AF Acknowledge failure received flag
|
|
||||||
* @arg @ref I2C_FLAG_STOPF STOP detection flag
|
|
||||||
* @arg @ref I2C_FLAG_BERR Bus error
|
|
||||||
* @arg @ref I2C_FLAG_ARLO Arbitration lost
|
|
||||||
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
|
|
||||||
* @arg @ref I2C_FLAG_PECERR PEC error in reception
|
|
||||||
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
|
|
||||||
* @arg @ref I2C_FLAG_ALERT SMBus alert
|
|
||||||
*
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? \
|
|
||||||
((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
|
|
||||||
((__HANDLE__)->Instance->ICR = (__FLAG__)))
|
|
||||||
|
|
||||||
/** @brief Enable the specified I2C peripheral.
|
|
||||||
* @param __HANDLE__ specifies the I2C Handle.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
|
|
||||||
|
|
||||||
/** @brief Disable the specified I2C peripheral.
|
|
||||||
* @param __HANDLE__ specifies the I2C Handle.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
|
|
||||||
|
|
||||||
/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode.
|
|
||||||
* @param __HANDLE__ specifies the I2C Handle.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Include I2C HAL Extended module */
|
|
||||||
#include "stm32wlxx_hal_i2c_ex.h"
|
|
||||||
|
|
||||||
/* Exported functions --------------------------------------------------------*/
|
|
||||||
/** @addtogroup I2C_Exported_Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Initialization and de-initialization functions******************************/
|
|
||||||
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
|
|
||||||
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
|
|
||||||
void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
|
|
||||||
void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
|
|
||||||
|
|
||||||
/* Callbacks Register/UnRegister functions ***********************************/
|
|
||||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
|
||||||
HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
|
|
||||||
pI2C_CallbackTypeDef pCallback);
|
|
||||||
HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
|
|
||||||
|
|
||||||
HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
|
|
||||||
HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
|
|
||||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* IO operation functions ****************************************************/
|
|
||||||
/******* Blocking mode: Polling */
|
|
||||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
|
||||||
uint16_t Size, uint32_t Timeout);
|
|
||||||
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
|
||||||
uint16_t Size, uint32_t Timeout);
|
|
||||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
|
||||||
uint32_t Timeout);
|
|
||||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
|
||||||
uint32_t Timeout);
|
|
||||||
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
|
||||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
|
||||||
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
|
||||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
|
||||||
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
|
|
||||||
uint32_t Timeout);
|
|
||||||
|
|
||||||
/******* Non-Blocking mode: Interrupt */
|
|
||||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
|
||||||
uint16_t Size);
|
|
||||||
HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
|
||||||
uint16_t Size);
|
|
||||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
|
||||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
|
||||||
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
|
||||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
|
||||||
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
|
||||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
|
||||||
|
|
||||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
|
||||||
uint16_t Size, uint32_t XferOptions);
|
|
||||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
|
||||||
uint16_t Size, uint32_t XferOptions);
|
|
||||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
|
||||||
uint32_t XferOptions);
|
|
||||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
|
||||||
uint32_t XferOptions);
|
|
||||||
HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
|
|
||||||
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
|
|
||||||
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
|
|
||||||
|
|
||||||
/******* Non-Blocking mode: DMA */
|
|
||||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
|
||||||
uint16_t Size);
|
|
||||||
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
|
||||||
uint16_t Size);
|
|
||||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
|
||||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
|
||||||
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
|
||||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
|
||||||
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
|
||||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
|
||||||
|
|
||||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
|
||||||
uint16_t Size, uint32_t XferOptions);
|
|
||||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
|
||||||
uint16_t Size, uint32_t XferOptions);
|
|
||||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
|
||||||
uint32_t XferOptions);
|
|
||||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
|
||||||
uint32_t XferOptions);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
|
|
||||||
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
|
|
||||||
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
|
|
||||||
void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
|
||||||
void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
|
||||||
void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
|
||||||
void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
|
||||||
void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
|
|
||||||
void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
|
|
||||||
void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
|
||||||
void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
|
||||||
void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
|
|
||||||
void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Peripheral State, Mode and Error functions *********************************/
|
|
||||||
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
|
|
||||||
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
|
|
||||||
uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private constants ---------------------------------------------------------*/
|
|
||||||
/** @defgroup I2C_Private_Constants I2C Private Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private macros ------------------------------------------------------------*/
|
|
||||||
/** @defgroup I2C_Private_Macro I2C Private Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
|
|
||||||
((MODE) == I2C_ADDRESSINGMODE_10BIT))
|
|
||||||
|
|
||||||
#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
|
|
||||||
((ADDRESS) == I2C_DUALADDRESS_ENABLE))
|
|
||||||
|
|
||||||
#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \
|
|
||||||
((MASK) == I2C_OA2_MASK01) || \
|
|
||||||
((MASK) == I2C_OA2_MASK02) || \
|
|
||||||
((MASK) == I2C_OA2_MASK03) || \
|
|
||||||
((MASK) == I2C_OA2_MASK04) || \
|
|
||||||
((MASK) == I2C_OA2_MASK05) || \
|
|
||||||
((MASK) == I2C_OA2_MASK06) || \
|
|
||||||
((MASK) == I2C_OA2_MASK07))
|
|
||||||
|
|
||||||
#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
|
|
||||||
((CALL) == I2C_GENERALCALL_ENABLE))
|
|
||||||
|
|
||||||
#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
|
|
||||||
((STRETCH) == I2C_NOSTRETCH_ENABLE))
|
|
||||||
|
|
||||||
#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
|
|
||||||
((SIZE) == I2C_MEMADD_SIZE_16BIT))
|
|
||||||
|
|
||||||
#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \
|
|
||||||
((MODE) == I2C_AUTOEND_MODE) || \
|
|
||||||
((MODE) == I2C_SOFTEND_MODE))
|
|
||||||
|
|
||||||
#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \
|
|
||||||
((REQUEST) == I2C_GENERATE_START_READ) || \
|
|
||||||
((REQUEST) == I2C_GENERATE_START_WRITE) || \
|
|
||||||
((REQUEST) == I2C_NO_STARTSTOP))
|
|
||||||
|
|
||||||
#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
|
|
||||||
((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
|
|
||||||
((REQUEST) == I2C_NEXT_FRAME) || \
|
|
||||||
((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
|
|
||||||
((REQUEST) == I2C_LAST_FRAME) || \
|
|
||||||
((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \
|
|
||||||
IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
|
|
||||||
|
|
||||||
#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \
|
|
||||||
((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
|
|
||||||
|
|
||||||
#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
|
|
||||||
(uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \
|
|
||||||
I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
|
|
||||||
I2C_CR2_RD_WRN)))
|
|
||||||
|
|
||||||
#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) \
|
|
||||||
>> 16U))
|
|
||||||
#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) \
|
|
||||||
>> 16U))
|
|
||||||
#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
|
|
||||||
#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
|
|
||||||
#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
|
|
||||||
|
|
||||||
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
|
|
||||||
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
|
|
||||||
|
|
||||||
#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \
|
|
||||||
(uint16_t)(0xFF00U))) >> 8U)))
|
|
||||||
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
|
|
||||||
|
|
||||||
#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? \
|
|
||||||
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
|
|
||||||
(I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
|
|
||||||
(~I2C_CR2_RD_WRN)) : \
|
|
||||||
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
|
|
||||||
(I2C_CR2_ADD10) | (I2C_CR2_START)) & \
|
|
||||||
(~I2C_CR2_RD_WRN)))
|
|
||||||
|
|
||||||
#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \
|
|
||||||
((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
|
|
||||||
#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private Functions ---------------------------------------------------------*/
|
|
||||||
/** @defgroup I2C_Private_Functions I2C Private Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Private functions are defined in stm32wlxx_hal_i2c.c file */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
|
|
||||||
#endif /* STM32WLxx_HAL_I2C_H */
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,170 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32wlxx_hal_i2c_ex.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief Header file of I2C HAL Extended module.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
|
||||||
* All rights reserved.</center></h2>
|
|
||||||
*
|
|
||||||
* This software component is licensed by ST under BSD 3-Clause license,
|
|
||||||
* the "License"; You may not use this file except in compliance with the
|
|
||||||
* License. You may obtain a copy of the License at:
|
|
||||||
* opensource.org/licenses/BSD-3-Clause
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef STM32WLxx_HAL_I2C_EX_H
|
|
||||||
#define STM32WLxx_HAL_I2C_EX_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32wlxx_hal_def.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32WLxx_HAL_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup I2CEx
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
|
||||||
/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define I2C_ANALOGFILTER_ENABLE 0x00000000U
|
|
||||||
#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
|
|
||||||
#define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
|
|
||||||
#define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
|
|
||||||
#define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
|
|
||||||
#define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
|
|
||||||
#define I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
|
|
||||||
#define I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported macro ------------------------------------------------------------*/
|
|
||||||
/** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported functions --------------------------------------------------------*/
|
|
||||||
/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Peripheral Control functions ************************************************/
|
|
||||||
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
|
|
||||||
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
|
|
||||||
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
|
|
||||||
void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private constants ---------------------------------------------------------*/
|
|
||||||
/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private macros ------------------------------------------------------------*/
|
|
||||||
/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
|
|
||||||
((FILTER) == I2C_ANALOGFILTER_DISABLE))
|
|
||||||
|
|
||||||
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
|
|
||||||
|
|
||||||
#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \
|
|
||||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \
|
|
||||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \
|
|
||||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \
|
|
||||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \
|
|
||||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2) || \
|
|
||||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private Functions ---------------------------------------------------------*/
|
|
||||||
/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Private functions are defined in stm32wlxx_hal_i2c_ex.c file */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* STM32WLxx_HAL_I2C_EX_H */
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,554 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32wlxx_hal_i2s.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief Header file of I2S HAL module.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
|
||||||
* All rights reserved.</center></h2>
|
|
||||||
*
|
|
||||||
* This software component is licensed by ST under BSD 3-Clause license,
|
|
||||||
* the "License"; You may not use this file except in compliance with the
|
|
||||||
* License. You may obtain a copy of the License at:
|
|
||||||
* opensource.org/licenses/BSD-3-Clause
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef STM32WLxx_HAL_I2S_H
|
|
||||||
#define STM32WLxx_HAL_I2S_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32wlxx_hal_def.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32WLxx_HAL_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup I2S
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
/** @defgroup I2S_Exported_Types I2S Exported Types
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief I2S Init structure definition
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t Mode; /*!< Specifies the I2S operating mode.
|
|
||||||
This parameter can be a value of @ref I2S_Mode */
|
|
||||||
|
|
||||||
uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
|
|
||||||
This parameter can be a value of @ref I2S_Standard */
|
|
||||||
|
|
||||||
uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
|
|
||||||
This parameter can be a value of @ref I2S_Data_Format */
|
|
||||||
|
|
||||||
uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
|
|
||||||
This parameter can be a value of @ref I2S_MCLK_Output */
|
|
||||||
|
|
||||||
uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
|
|
||||||
This parameter can be a value of @ref I2S_Audio_Frequency */
|
|
||||||
|
|
||||||
uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
|
|
||||||
This parameter can be a value of @ref I2S_Clock_Polarity */
|
|
||||||
} I2S_InitTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief HAL State structures definition
|
|
||||||
*/
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */
|
|
||||||
HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */
|
|
||||||
HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */
|
|
||||||
HAL_I2S_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
|
|
||||||
HAL_I2S_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
|
|
||||||
HAL_I2S_STATE_TIMEOUT = 0x06U, /*!< I2S timeout state */
|
|
||||||
HAL_I2S_STATE_ERROR = 0x07U /*!< I2S error state */
|
|
||||||
} HAL_I2S_StateTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief I2S handle Structure definition
|
|
||||||
*/
|
|
||||||
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1)
|
|
||||||
typedef struct __I2S_HandleTypeDef
|
|
||||||
#else
|
|
||||||
typedef struct
|
|
||||||
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
|
|
||||||
{
|
|
||||||
SPI_TypeDef *Instance; /*!< I2S registers base address */
|
|
||||||
|
|
||||||
I2S_InitTypeDef Init; /*!< I2S communication parameters */
|
|
||||||
|
|
||||||
uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */
|
|
||||||
|
|
||||||
__IO uint16_t TxXferSize; /*!< I2S Tx transfer size */
|
|
||||||
|
|
||||||
__IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */
|
|
||||||
|
|
||||||
uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */
|
|
||||||
|
|
||||||
__IO uint16_t RxXferSize; /*!< I2S Rx transfer size */
|
|
||||||
|
|
||||||
__IO uint16_t RxXferCount; /*!< I2S Rx transfer counter
|
|
||||||
(This field is initialized at the
|
|
||||||
same value as transfer size at the
|
|
||||||
beginning of the transfer and
|
|
||||||
decremented when a sample is received
|
|
||||||
NbSamplesReceived = RxBufferSize-RxBufferCount) */
|
|
||||||
DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */
|
|
||||||
|
|
||||||
DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */
|
|
||||||
|
|
||||||
__IO HAL_LockTypeDef Lock; /*!< I2S locking object */
|
|
||||||
|
|
||||||
__IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */
|
|
||||||
|
|
||||||
__IO uint32_t ErrorCode; /*!< I2S Error code
|
|
||||||
This parameter can be a value of @ref I2S_Error */
|
|
||||||
|
|
||||||
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
|
|
||||||
void (* TxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Completed callback */
|
|
||||||
void (* RxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Completed callback */
|
|
||||||
void (* TxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Half Completed callback */
|
|
||||||
void (* RxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Half Completed callback */
|
|
||||||
void (* ErrorCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Error callback */
|
|
||||||
void (* MspInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp Init callback */
|
|
||||||
void (* MspDeInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp DeInit callback */
|
|
||||||
|
|
||||||
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
|
|
||||||
} I2S_HandleTypeDef;
|
|
||||||
|
|
||||||
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
|
|
||||||
/**
|
|
||||||
* @brief HAL I2S Callback ID enumeration definition
|
|
||||||
*/
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
HAL_I2S_TX_COMPLETE_CB_ID = 0x00U, /*!< I2S Tx Completed callback ID */
|
|
||||||
HAL_I2S_RX_COMPLETE_CB_ID = 0x01U, /*!< I2S Rx Completed callback ID */
|
|
||||||
HAL_I2S_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< I2S Tx Half Completed callback ID */
|
|
||||||
HAL_I2S_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< I2S Rx Half Completed callback ID */
|
|
||||||
HAL_I2S_ERROR_CB_ID = 0x06U, /*!< I2S Error callback ID */
|
|
||||||
HAL_I2S_MSPINIT_CB_ID = 0x07U, /*!< I2S Msp Init callback ID */
|
|
||||||
HAL_I2S_MSPDEINIT_CB_ID = 0x08U /*!< I2S Msp DeInit callback ID */
|
|
||||||
|
|
||||||
} HAL_I2S_CallbackIDTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief HAL I2S Callback pointer definition
|
|
||||||
*/
|
|
||||||
typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to an I2S callback function */
|
|
||||||
|
|
||||||
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
|
||||||
/** @defgroup I2S_Exported_Constants I2S Exported Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/** @defgroup I2S_Error I2S Error
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define HAL_I2S_ERROR_NONE (0x00000000U) /*!< No error */
|
|
||||||
#define HAL_I2S_ERROR_TIMEOUT (0x00000001U) /*!< Timeout error */
|
|
||||||
#define HAL_I2S_ERROR_OVR (0x00000002U) /*!< OVR error */
|
|
||||||
#define HAL_I2S_ERROR_UDR (0x00000004U) /*!< UDR error */
|
|
||||||
#define HAL_I2S_ERROR_DMA (0x00000008U) /*!< DMA transfer error */
|
|
||||||
#define HAL_I2S_ERROR_PRESCALER (0x00000010U) /*!< Prescaler Calculation error */
|
|
||||||
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
|
|
||||||
#define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000020U) /*!< Invalid Callback error */
|
|
||||||
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
|
|
||||||
#define HAL_I2S_ERROR_BUSY_LINE_RX (0x00000040U) /*!< Busy Rx Line error */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup I2S_Mode I2S Mode
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define I2S_MODE_SLAVE_TX (0x00000000U)
|
|
||||||
#define I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)
|
|
||||||
#define I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)
|
|
||||||
#define I2S_MODE_MASTER_RX ((SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup I2S_Standard I2S Standard
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define I2S_STANDARD_PHILIPS (0x00000000U)
|
|
||||||
#define I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)
|
|
||||||
#define I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)
|
|
||||||
#define I2S_STANDARD_PCM_SHORT ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1))
|
|
||||||
#define I2S_STANDARD_PCM_LONG ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup I2S_Data_Format I2S Data Format
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define I2S_DATAFORMAT_16B (0x00000000U)
|
|
||||||
#define I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)
|
|
||||||
#define I2S_DATAFORMAT_24B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0))
|
|
||||||
#define I2S_DATAFORMAT_32B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup I2S_MCLK_Output I2S MCLK Output
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define I2S_MCLKOUTPUT_ENABLE (SPI_I2SPR_MCKOE)
|
|
||||||
#define I2S_MCLKOUTPUT_DISABLE (0x00000000U)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup I2S_Audio_Frequency I2S Audio Frequency
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define I2S_AUDIOFREQ_192K (192000U)
|
|
||||||
#define I2S_AUDIOFREQ_96K (96000U)
|
|
||||||
#define I2S_AUDIOFREQ_48K (48000U)
|
|
||||||
#define I2S_AUDIOFREQ_44K (44100U)
|
|
||||||
#define I2S_AUDIOFREQ_32K (32000U)
|
|
||||||
#define I2S_AUDIOFREQ_22K (22050U)
|
|
||||||
#define I2S_AUDIOFREQ_16K (16000U)
|
|
||||||
#define I2S_AUDIOFREQ_11K (11025U)
|
|
||||||
#define I2S_AUDIOFREQ_8K (8000U)
|
|
||||||
#define I2S_AUDIOFREQ_DEFAULT (2U)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define I2S_CPOL_LOW (0x00000000U)
|
|
||||||
#define I2S_CPOL_HIGH (SPI_I2SCFGR_CKPOL)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define I2S_IT_TXE SPI_CR2_TXEIE
|
|
||||||
#define I2S_IT_RXNE SPI_CR2_RXNEIE
|
|
||||||
#define I2S_IT_ERR SPI_CR2_ERRIE
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup I2S_Flags_Definition I2S Flags Definition
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define I2S_FLAG_TXE SPI_SR_TXE
|
|
||||||
#define I2S_FLAG_RXNE SPI_SR_RXNE
|
|
||||||
|
|
||||||
#define I2S_FLAG_UDR SPI_SR_UDR
|
|
||||||
#define I2S_FLAG_OVR SPI_SR_OVR
|
|
||||||
#define I2S_FLAG_FRE SPI_SR_FRE
|
|
||||||
|
|
||||||
#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
|
|
||||||
#define I2S_FLAG_BSY SPI_SR_BSY
|
|
||||||
|
|
||||||
#define I2S_FLAG_MASK (SPI_SR_RXNE\
|
|
||||||
| SPI_SR_TXE | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_CHSIDE | SPI_SR_BSY)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported macros -----------------------------------------------------------*/
|
|
||||||
/** @defgroup I2S_Exported_macros I2S Exported Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @brief Reset I2S handle state
|
|
||||||
* @param __HANDLE__ specifies the I2S Handle.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
|
|
||||||
#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
|
||||||
(__HANDLE__)->State = HAL_I2S_STATE_RESET; \
|
|
||||||
(__HANDLE__)->MspInitCallback = NULL; \
|
|
||||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
|
||||||
} while(0)
|
|
||||||
#else
|
|
||||||
#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
|
|
||||||
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
|
|
||||||
|
|
||||||
/** @brief Enable the specified SPI peripheral (in I2S mode).
|
|
||||||
* @param __HANDLE__ specifies the I2S Handle.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
|
|
||||||
|
|
||||||
/** @brief Disable the specified SPI peripheral (in I2S mode).
|
|
||||||
* @param __HANDLE__ specifies the I2S Handle.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
|
|
||||||
|
|
||||||
/** @brief Enable the specified I2S interrupts.
|
|
||||||
* @param __HANDLE__ specifies the I2S Handle.
|
|
||||||
* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
|
|
||||||
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
|
|
||||||
* @arg I2S_IT_ERR: Error interrupt enable
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
|
|
||||||
|
|
||||||
/** @brief Disable the specified I2S interrupts.
|
|
||||||
* @param __HANDLE__ specifies the I2S Handle.
|
|
||||||
* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
|
|
||||||
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
|
|
||||||
* @arg I2S_IT_ERR: Error interrupt enable
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
|
|
||||||
|
|
||||||
/** @brief Checks if the specified I2S interrupt source is enabled or disabled.
|
|
||||||
* @param __HANDLE__ specifies the I2S Handle.
|
|
||||||
* This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
|
|
||||||
* @param __INTERRUPT__ specifies the I2S interrupt source to check.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
|
|
||||||
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
|
|
||||||
* @arg I2S_IT_ERR: Error interrupt enable
|
|
||||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
|
||||||
*/
|
|
||||||
#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\
|
|
||||||
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
|
||||||
|
|
||||||
/** @brief Checks whether the specified I2S flag is set or not.
|
|
||||||
* @param __HANDLE__ specifies the I2S Handle.
|
|
||||||
* @param __FLAG__ specifies the flag to check.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg I2S_FLAG_RXNE: Receive buffer not empty flag
|
|
||||||
* @arg I2S_FLAG_TXE: Transmit buffer empty flag
|
|
||||||
* @arg I2S_FLAG_UDR: Underrun flag
|
|
||||||
* @arg I2S_FLAG_OVR: Overrun flag
|
|
||||||
* @arg I2S_FLAG_FRE: Frame error flag
|
|
||||||
* @arg I2S_FLAG_CHSIDE: Channel Side flag
|
|
||||||
* @arg I2S_FLAG_BSY: Busy flag
|
|
||||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
|
||||||
*/
|
|
||||||
#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
|
|
||||||
|
|
||||||
/** @brief Clears the I2S OVR pending flag.
|
|
||||||
* @param __HANDLE__ specifies the I2S Handle.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \
|
|
||||||
__IO uint32_t tmpreg_ovr = 0x00U; \
|
|
||||||
tmpreg_ovr = (__HANDLE__)->Instance->DR; \
|
|
||||||
tmpreg_ovr = (__HANDLE__)->Instance->SR; \
|
|
||||||
UNUSED(tmpreg_ovr); \
|
|
||||||
}while(0U)
|
|
||||||
/** @brief Clears the I2S UDR pending flag.
|
|
||||||
* @param __HANDLE__ specifies the I2S Handle.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\
|
|
||||||
__IO uint32_t tmpreg_udr = 0x00U;\
|
|
||||||
tmpreg_udr = ((__HANDLE__)->Instance->SR);\
|
|
||||||
UNUSED(tmpreg_udr); \
|
|
||||||
}while(0U)
|
|
||||||
/** @brief Flush the I2S DR Register.
|
|
||||||
* @param __HANDLE__ specifies the I2S Handle.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_I2S_FLUSH_RX_DR(__HANDLE__) do{\
|
|
||||||
__IO uint32_t tmpreg_dr = 0x00U;\
|
|
||||||
tmpreg_dr = ((__HANDLE__)->Instance->DR);\
|
|
||||||
UNUSED(tmpreg_dr); \
|
|
||||||
}while(0U)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported functions --------------------------------------------------------*/
|
|
||||||
/** @addtogroup I2S_Exported_Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup I2S_Exported_Functions_Group1
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Initialization/de-initialization functions ********************************/
|
|
||||||
HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
|
|
||||||
HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s);
|
|
||||||
void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
|
|
||||||
void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
|
|
||||||
|
|
||||||
/* Callbacks Register/UnRegister functions ***********************************/
|
|
||||||
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
|
|
||||||
HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
|
|
||||||
pI2S_CallbackTypeDef pCallback);
|
|
||||||
HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID);
|
|
||||||
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup I2S_Exported_Functions_Group2
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* I/O operation functions ***************************************************/
|
|
||||||
/* Blocking mode: Polling */
|
|
||||||
HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
|
|
||||||
HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
|
|
||||||
|
|
||||||
/* Non-Blocking mode: Interrupt */
|
|
||||||
HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
|
|
||||||
HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
|
|
||||||
void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
|
|
||||||
|
|
||||||
/* Non-Blocking mode: DMA */
|
|
||||||
HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
|
|
||||||
HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
|
|
||||||
|
|
||||||
HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
|
|
||||||
HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
|
|
||||||
HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
|
|
||||||
|
|
||||||
/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
|
|
||||||
void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
|
|
||||||
void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
|
|
||||||
void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
|
|
||||||
void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
|
|
||||||
void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup I2S_Exported_Functions_Group3
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Peripheral Control and State functions ************************************/
|
|
||||||
HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
|
|
||||||
uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private types -------------------------------------------------------------*/
|
|
||||||
/* Private variables ---------------------------------------------------------*/
|
|
||||||
/* Private constants ---------------------------------------------------------*/
|
|
||||||
/* Private macros ------------------------------------------------------------*/
|
|
||||||
/** @defgroup I2S_Private_Macros I2S Private Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @brief Check whether the specified SPI flag is set or not.
|
|
||||||
* @param __SR__ copy of I2S SR register.
|
|
||||||
* @param __FLAG__ specifies the flag to check.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg I2S_FLAG_RXNE: Receive buffer not empty flag
|
|
||||||
* @arg I2S_FLAG_TXE: Transmit buffer empty flag
|
|
||||||
* @arg I2S_FLAG_UDR: Underrun error flag
|
|
||||||
* @arg I2S_FLAG_OVR: Overrun flag
|
|
||||||
* @arg I2S_FLAG_CHSIDE: Channel side flag
|
|
||||||
* @arg I2S_FLAG_BSY: Busy flag
|
|
||||||
* @retval SET or RESET.
|
|
||||||
*/
|
|
||||||
#define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__)\
|
|
||||||
& ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET)
|
|
||||||
|
|
||||||
/** @brief Check whether the specified SPI Interrupt is set or not.
|
|
||||||
* @param __CR2__ copy of I2S CR2 register.
|
|
||||||
* @param __INTERRUPT__ specifies the SPI interrupt source to check.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
|
|
||||||
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
|
|
||||||
* @arg I2S_IT_ERR: Error interrupt enable
|
|
||||||
* @retval SET or RESET.
|
|
||||||
*/
|
|
||||||
#define I2S_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__)\
|
|
||||||
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
|
||||||
|
|
||||||
/** @brief Checks if I2S Mode parameter is in allowed range.
|
|
||||||
* @param __MODE__ specifies the I2S Mode.
|
|
||||||
* This parameter can be a value of @ref I2S_Mode
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define IS_I2S_MODE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \
|
|
||||||
((__MODE__) == I2S_MODE_SLAVE_RX) || \
|
|
||||||
((__MODE__) == I2S_MODE_MASTER_TX) || \
|
|
||||||
((__MODE__) == I2S_MODE_MASTER_RX))
|
|
||||||
|
|
||||||
#define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS) || \
|
|
||||||
((__STANDARD__) == I2S_STANDARD_MSB) || \
|
|
||||||
((__STANDARD__) == I2S_STANDARD_LSB) || \
|
|
||||||
((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \
|
|
||||||
((__STANDARD__) == I2S_STANDARD_PCM_LONG))
|
|
||||||
|
|
||||||
#define IS_I2S_DATA_FORMAT(__FORMAT__) (((__FORMAT__) == I2S_DATAFORMAT_16B) || \
|
|
||||||
((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED) || \
|
|
||||||
((__FORMAT__) == I2S_DATAFORMAT_24B) || \
|
|
||||||
((__FORMAT__) == I2S_DATAFORMAT_32B))
|
|
||||||
|
|
||||||
#define IS_I2S_MCLK_OUTPUT(__OUTPUT__) (((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE) || \
|
|
||||||
((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE))
|
|
||||||
|
|
||||||
#define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K) && \
|
|
||||||
((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \
|
|
||||||
((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))
|
|
||||||
|
|
||||||
/** @brief Checks if I2S Serial clock steady state parameter is in allowed range.
|
|
||||||
* @param __CPOL__ specifies the I2S serial clock steady state.
|
|
||||||
* This parameter can be a value of @ref I2S_Clock_Polarity
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) || \
|
|
||||||
((__CPOL__) == I2S_CPOL_HIGH))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* STM32WLxx_HAL_I2S_H */
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,292 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32wlxx_hal_ipcc.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief Header file of Mailbox HAL module.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
|
||||||
* All rights reserved.</center></h2>
|
|
||||||
*
|
|
||||||
* This software component is licensed by ST under BSD 3-Clause license,
|
|
||||||
* the "License"; You may not use this file except in compliance with the
|
|
||||||
* License. You may obtain a copy of the License at:
|
|
||||||
* opensource.org/licenses/BSD-3-Clause
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef STM32WLxx_HAL_IPCC_H
|
|
||||||
#define STM32WLxx_HAL_IPCC_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32wlxx_hal_def.h"
|
|
||||||
|
|
||||||
#if defined(IPCC)
|
|
||||||
|
|
||||||
/** @addtogroup STM32WLxx_HAL_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup IPCC IPCC
|
|
||||||
* @brief IPCC HAL module driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
|
||||||
|
|
||||||
/** @defgroup IPCC_Exported_Constants IPCC Exported Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup IPCC_Channel IPCC Channel
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define IPCC_CHANNEL_1 0x00000000U
|
|
||||||
#define IPCC_CHANNEL_2 0x00000001U
|
|
||||||
#define IPCC_CHANNEL_3 0x00000002U
|
|
||||||
#define IPCC_CHANNEL_4 0x00000003U
|
|
||||||
#define IPCC_CHANNEL_5 0x00000004U
|
|
||||||
#define IPCC_CHANNEL_6 0x00000005U
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
/** @defgroup IPCC_Exported_Types IPCC Exported Types
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief HAL IPCC State structures definition
|
|
||||||
*/
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
HAL_IPCC_STATE_RESET = 0x00U, /*!< IPCC not yet initialized or disabled */
|
|
||||||
HAL_IPCC_STATE_READY = 0x01U, /*!< IPCC initialized and ready for use */
|
|
||||||
HAL_IPCC_STATE_BUSY = 0x02U /*!< IPCC internal processing is ongoing */
|
|
||||||
} HAL_IPCC_StateTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief IPCC channel direction structure definition
|
|
||||||
*/
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
IPCC_CHANNEL_DIR_TX = 0x00U, /*!< Channel direction Tx is used by an MCU to transmit */
|
|
||||||
IPCC_CHANNEL_DIR_RX = 0x01U /*!< Channel direction Rx is used by an MCU to receive */
|
|
||||||
} IPCC_CHANNELDirTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief IPCC channel status structure definition
|
|
||||||
*/
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
IPCC_CHANNEL_STATUS_FREE = 0x00U, /*!< Means that a new msg can be posted on that channel */
|
|
||||||
IPCC_CHANNEL_STATUS_OCCUPIED = 0x01U /*!< An MCU has posted a msg the other MCU hasn't retrieved */
|
|
||||||
} IPCC_CHANNELStatusTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief IPCC handle structure definition
|
|
||||||
*/
|
|
||||||
typedef struct __IPCC_HandleTypeDef
|
|
||||||
{
|
|
||||||
IPCC_TypeDef *Instance; /*!< IPCC registers base address */
|
|
||||||
void (* ChannelCallbackRx[IPCC_CHANNEL_NUMBER])(struct __IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir); /*!< Rx Callback registration table */
|
|
||||||
void (* ChannelCallbackTx[IPCC_CHANNEL_NUMBER])(struct __IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir); /*!< Tx Callback registration table */
|
|
||||||
uint32_t callbackRequest; /*!< Store information about callback notification by channel */
|
|
||||||
__IO HAL_IPCC_StateTypeDef State; /*!< IPCC State: initialized or not */
|
|
||||||
} IPCC_HandleTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief IPCC callback typedef
|
|
||||||
*/
|
|
||||||
typedef void ChannelCb(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported macros -----------------------------------------------------------*/
|
|
||||||
/** @defgroup IPCC_Exported_Macros IPCC Exported Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the specified interrupt.
|
|
||||||
* @param __HANDLE__ specifies the IPCC Handle
|
|
||||||
* @param __CHDIRECTION__ specifies the channels Direction
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg @ref IPCC_CHANNEL_DIR_TX Transmit channel free interrupt enable
|
|
||||||
* @arg @ref IPCC_CHANNEL_DIR_RX Receive channel occupied interrupt enable
|
|
||||||
*/
|
|
||||||
#if defined(CORE_CM0PLUS)
|
|
||||||
#define __HAL_IPCC_ENABLE_IT(__HANDLE__, __CHDIRECTION__) \
|
|
||||||
(((__CHDIRECTION__) == IPCC_CHANNEL_DIR_RX) ? \
|
|
||||||
((__HANDLE__)->Instance->C2CR |= IPCC_C2CR_RXOIE) : \
|
|
||||||
((__HANDLE__)->Instance->C2CR |= IPCC_C2CR_TXFIE))
|
|
||||||
#else
|
|
||||||
#define __HAL_IPCC_ENABLE_IT(__HANDLE__, __CHDIRECTION__) \
|
|
||||||
(((__CHDIRECTION__) == IPCC_CHANNEL_DIR_RX) ? \
|
|
||||||
((__HANDLE__)->Instance->C1CR |= IPCC_C1CR_RXOIE) : \
|
|
||||||
((__HANDLE__)->Instance->C1CR |= IPCC_C1CR_TXFIE))
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the specified interrupt.
|
|
||||||
* @param __HANDLE__ specifies the IPCC Handle
|
|
||||||
* @param __CHDIRECTION__ specifies the channels Direction
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg @ref IPCC_CHANNEL_DIR_TX Transmit channel free interrupt enable
|
|
||||||
* @arg @ref IPCC_CHANNEL_DIR_RX Receive channel occupied interrupt enable
|
|
||||||
*/
|
|
||||||
#if defined(CORE_CM0PLUS)
|
|
||||||
#define __HAL_IPCC_DISABLE_IT(__HANDLE__, __CHDIRECTION__) \
|
|
||||||
(((__CHDIRECTION__) == IPCC_CHANNEL_DIR_RX) ? \
|
|
||||||
((__HANDLE__)->Instance->C2CR &= ~IPCC_C2CR_RXOIE) : \
|
|
||||||
((__HANDLE__)->Instance->C2CR &= ~IPCC_C2CR_TXFIE))
|
|
||||||
#else
|
|
||||||
#define __HAL_IPCC_DISABLE_IT(__HANDLE__, __CHDIRECTION__) \
|
|
||||||
(((__CHDIRECTION__) == IPCC_CHANNEL_DIR_RX) ? \
|
|
||||||
((__HANDLE__)->Instance->C1CR &= ~IPCC_C1CR_RXOIE) : \
|
|
||||||
((__HANDLE__)->Instance->C1CR &= ~IPCC_C1CR_TXFIE))
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Mask the specified interrupt.
|
|
||||||
* @param __HANDLE__ specifies the IPCC Handle
|
|
||||||
* @param __CHDIRECTION__ specifies the channels Direction
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg @ref IPCC_CHANNEL_DIR_TX Transmit channel free interrupt enable
|
|
||||||
* @arg @ref IPCC_CHANNEL_DIR_RX Receive channel occupied interrupt enable
|
|
||||||
* @param __CHINDEX__ specifies the channels number:
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg IPCC_CHANNEL_1: IPCC Channel 1
|
|
||||||
* @arg IPCC_CHANNEL_2: IPCC Channel 2
|
|
||||||
* @arg IPCC_CHANNEL_3: IPCC Channel 3
|
|
||||||
* @arg IPCC_CHANNEL_4: IPCC Channel 4
|
|
||||||
* @arg IPCC_CHANNEL_5: IPCC Channel 5
|
|
||||||
* @arg IPCC_CHANNEL_6: IPCC Channel 6
|
|
||||||
*/
|
|
||||||
#if defined(CORE_CM0PLUS)
|
|
||||||
#define __HAL_IPCC_MASK_CHANNEL_IT(__HANDLE__, __CHDIRECTION__, __CHINDEX__) \
|
|
||||||
(((__CHDIRECTION__) == IPCC_CHANNEL_DIR_RX) ? \
|
|
||||||
((__HANDLE__)->Instance->C2MR |= (IPCC_C1MR_CH1OM_Msk << (__CHINDEX__))) : \
|
|
||||||
((__HANDLE__)->Instance->C2MR |= (IPCC_C1MR_CH1FM_Msk << (__CHINDEX__))))
|
|
||||||
#else
|
|
||||||
#define __HAL_IPCC_MASK_CHANNEL_IT(__HANDLE__, __CHDIRECTION__, __CHINDEX__) \
|
|
||||||
(((__CHDIRECTION__) == IPCC_CHANNEL_DIR_RX) ? \
|
|
||||||
((__HANDLE__)->Instance->C1MR |= (IPCC_C1MR_CH1OM_Msk << (__CHINDEX__))) : \
|
|
||||||
((__HANDLE__)->Instance->C1MR |= (IPCC_C1MR_CH1FM_Msk << (__CHINDEX__))))
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Unmask the specified interrupt.
|
|
||||||
* @param __HANDLE__ specifies the IPCC Handle
|
|
||||||
* @param __CHDIRECTION__ specifies the channels Direction
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg @ref IPCC_CHANNEL_DIR_TX Transmit channel free interrupt enable
|
|
||||||
* @arg @ref IPCC_CHANNEL_DIR_RX Receive channel occupied interrupt enable
|
|
||||||
* @param __CHINDEX__ specifies the channels number:
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg IPCC_CHANNEL_1: IPCC Channel 1
|
|
||||||
* @arg IPCC_CHANNEL_2: IPCC Channel 2
|
|
||||||
* @arg IPCC_CHANNEL_3: IPCC Channel 3
|
|
||||||
* @arg IPCC_CHANNEL_4: IPCC Channel 4
|
|
||||||
* @arg IPCC_CHANNEL_5: IPCC Channel 5
|
|
||||||
* @arg IPCC_CHANNEL_6: IPCC Channel 6
|
|
||||||
*/
|
|
||||||
#if defined(CORE_CM0PLUS)
|
|
||||||
#define __HAL_IPCC_UNMASK_CHANNEL_IT(__HANDLE__, __CHDIRECTION__, __CHINDEX__) \
|
|
||||||
(((__CHDIRECTION__) == IPCC_CHANNEL_DIR_RX) ? \
|
|
||||||
((__HANDLE__)->Instance->C2MR &= ~(IPCC_C1MR_CH1OM_Msk << (__CHINDEX__))) : \
|
|
||||||
((__HANDLE__)->Instance->C2MR &= ~(IPCC_C1MR_CH1FM_Msk << (__CHINDEX__))))
|
|
||||||
#else
|
|
||||||
#define __HAL_IPCC_UNMASK_CHANNEL_IT(__HANDLE__, __CHDIRECTION__, __CHINDEX__) \
|
|
||||||
(((__CHDIRECTION__) == IPCC_CHANNEL_DIR_RX) ? \
|
|
||||||
((__HANDLE__)->Instance->C1MR &= ~(IPCC_C1MR_CH1OM_Msk << (__CHINDEX__))) : \
|
|
||||||
((__HANDLE__)->Instance->C1MR &= ~(IPCC_C1MR_CH1FM_Msk << (__CHINDEX__))))
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported functions --------------------------------------------------------*/
|
|
||||||
/** @defgroup IPCC_Exported_Functions IPCC Exported Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Initialization and de-initialization functions *******************************/
|
|
||||||
/** @defgroup IPCC_Exported_Functions_Group1 Initialization and deinitialization functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
HAL_StatusTypeDef HAL_IPCC_Init(IPCC_HandleTypeDef *hipcc);
|
|
||||||
HAL_StatusTypeDef HAL_IPCC_DeInit(IPCC_HandleTypeDef *hipcc);
|
|
||||||
void HAL_IPCC_MspInit(IPCC_HandleTypeDef *hipcc);
|
|
||||||
void HAL_IPCC_MspDeInit(IPCC_HandleTypeDef *hipcc);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup IPCC_Exported_Functions_Group2 Communication functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* IO operation functions *****************************************************/
|
|
||||||
HAL_StatusTypeDef HAL_IPCC_ActivateNotification(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir, ChannelCb cb);
|
|
||||||
HAL_StatusTypeDef HAL_IPCC_DeActivateNotification(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);
|
|
||||||
IPCC_CHANNELStatusTypeDef HAL_IPCC_GetChannelStatus(IPCC_HandleTypeDef const *const hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);
|
|
||||||
HAL_StatusTypeDef HAL_IPCC_NotifyCPU(IPCC_HandleTypeDef const *const hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup IPCC_Exported_Functions_Group3 Peripheral State and Error functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Peripheral State and Error functions ****************************************/
|
|
||||||
HAL_IPCC_StateTypeDef HAL_IPCC_GetState(IPCC_HandleTypeDef const *const hipcc);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup IPCC_IRQ_Handler_and_Callbacks Peripheral IRQ Handler and Callbacks
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* IRQHandler and Callbacks used in non blocking modes ************************/
|
|
||||||
void HAL_IPCC_TX_IRQHandler(IPCC_HandleTypeDef *const hipcc);
|
|
||||||
void HAL_IPCC_RX_IRQHandler(IPCC_HandleTypeDef *const hipcc);
|
|
||||||
void HAL_IPCC_TxCallback(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);
|
|
||||||
void HAL_IPCC_RxCallback(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
#endif /* IPCC */
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* STM32WLxx_HAL_IPCC_H */
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,882 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32wlxx_hal_irda.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief Header file of IRDA HAL module.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
|
||||||
* All rights reserved.</center></h2>
|
|
||||||
*
|
|
||||||
* This software component is licensed by ST under BSD 3-Clause license,
|
|
||||||
* the "License"; You may not use this file except in compliance with the
|
|
||||||
* License. You may obtain a copy of the License at:
|
|
||||||
* opensource.org/licenses/BSD-3-Clause
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef STM32WLxx_HAL_IRDA_H
|
|
||||||
#define STM32WLxx_HAL_IRDA_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32wlxx_hal_def.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32WLxx_HAL_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup IRDA
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
/** @defgroup IRDA_Exported_Types IRDA Exported Types
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief IRDA Init Structure definition
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t BaudRate; /*!< This member configures the IRDA communication baud rate.
|
|
||||||
The baud rate register is computed using the following formula:
|
|
||||||
Baud Rate Register = ((usart_ker_ckpres) / ((hirda->Init.BaudRate)))
|
|
||||||
where usart_ker_ckpres is the IRDA input clock divided by a prescaler */
|
|
||||||
|
|
||||||
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
|
|
||||||
This parameter can be a value of @ref IRDAEx_Word_Length */
|
|
||||||
|
|
||||||
uint32_t Parity; /*!< Specifies the parity mode.
|
|
||||||
This parameter can be a value of @ref IRDA_Parity
|
|
||||||
@note When parity is enabled, the computed parity is inserted
|
|
||||||
at the MSB position of the transmitted data (9th bit when
|
|
||||||
the word length is set to 9 data bits; 8th bit when the
|
|
||||||
word length is set to 8 data bits). */
|
|
||||||
|
|
||||||
uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
|
|
||||||
This parameter can be a value of @ref IRDA_Transfer_Mode */
|
|
||||||
|
|
||||||
uint8_t Prescaler; /*!< Specifies the Prescaler value for dividing the UART/USART source clock
|
|
||||||
to achieve low-power frequency.
|
|
||||||
@note Prescaler value 0 is forbidden */
|
|
||||||
|
|
||||||
uint16_t PowerMode; /*!< Specifies the IRDA power mode.
|
|
||||||
This parameter can be a value of @ref IRDA_Low_Power */
|
|
||||||
|
|
||||||
uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the IRDA clock source.
|
|
||||||
This parameter can be a value of @ref IRDA_ClockPrescaler. */
|
|
||||||
|
|
||||||
} IRDA_InitTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief HAL IRDA State definition
|
|
||||||
* @note HAL IRDA State value is a combination of 2 different substates: gState and RxState (see @ref IRDA_State_Definition).
|
|
||||||
* - gState contains IRDA state information related to global Handle management
|
|
||||||
* and also information related to Tx operations.
|
|
||||||
* gState value coding follow below described bitmap :
|
|
||||||
* b7-b6 Error information
|
|
||||||
* 00 : No Error
|
|
||||||
* 01 : (Not Used)
|
|
||||||
* 10 : Timeout
|
|
||||||
* 11 : Error
|
|
||||||
* b5 Peripheral initialization status
|
|
||||||
* 0 : Reset (Peripheral not initialized)
|
|
||||||
* 1 : Init done (Peripheral initialized. HAL IRDA Init function already called)
|
|
||||||
* b4-b3 (not used)
|
|
||||||
* xx : Should be set to 00
|
|
||||||
* b2 Intrinsic process state
|
|
||||||
* 0 : Ready
|
|
||||||
* 1 : Busy (Peripheral busy with some configuration or internal operations)
|
|
||||||
* b1 (not used)
|
|
||||||
* x : Should be set to 0
|
|
||||||
* b0 Tx state
|
|
||||||
* 0 : Ready (no Tx operation ongoing)
|
|
||||||
* 1 : Busy (Tx operation ongoing)
|
|
||||||
* - RxState contains information related to Rx operations.
|
|
||||||
* RxState value coding follow below described bitmap :
|
|
||||||
* b7-b6 (not used)
|
|
||||||
* xx : Should be set to 00
|
|
||||||
* b5 Peripheral initialization status
|
|
||||||
* 0 : Reset (Peripheral not initialized)
|
|
||||||
* 1 : Init done (Peripheral initialized)
|
|
||||||
* b4-b2 (not used)
|
|
||||||
* xxx : Should be set to 000
|
|
||||||
* b1 Rx state
|
|
||||||
* 0 : Ready (no Rx operation ongoing)
|
|
||||||
* 1 : Busy (Rx operation ongoing)
|
|
||||||
* b0 (not used)
|
|
||||||
* x : Should be set to 0.
|
|
||||||
*/
|
|
||||||
typedef uint32_t HAL_IRDA_StateTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief IRDA clock sources definition
|
|
||||||
*/
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
IRDA_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
|
|
||||||
IRDA_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */
|
|
||||||
IRDA_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
|
|
||||||
IRDA_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
|
|
||||||
IRDA_CLOCKSOURCE_LSE = 0x10U, /*!< LSE clock source */
|
|
||||||
IRDA_CLOCKSOURCE_UNDEFINED = 0x20U /*!< Undefined clock source */
|
|
||||||
} IRDA_ClockSourceTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief IRDA handle Structure definition
|
|
||||||
*/
|
|
||||||
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
|
|
||||||
typedef struct __IRDA_HandleTypeDef
|
|
||||||
#else
|
|
||||||
typedef struct
|
|
||||||
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
|
|
||||||
{
|
|
||||||
USART_TypeDef *Instance; /*!< USART registers base address */
|
|
||||||
|
|
||||||
IRDA_InitTypeDef Init; /*!< IRDA communication parameters */
|
|
||||||
|
|
||||||
uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */
|
|
||||||
|
|
||||||
uint16_t TxXferSize; /*!< IRDA Tx Transfer size */
|
|
||||||
|
|
||||||
__IO uint16_t TxXferCount; /*!< IRDA Tx Transfer Counter */
|
|
||||||
|
|
||||||
uint8_t *pRxBuffPtr; /*!< Pointer to IRDA Rx transfer Buffer */
|
|
||||||
|
|
||||||
uint16_t RxXferSize; /*!< IRDA Rx Transfer size */
|
|
||||||
|
|
||||||
__IO uint16_t RxXferCount; /*!< IRDA Rx Transfer Counter */
|
|
||||||
|
|
||||||
uint16_t Mask; /*!< USART RX RDR register mask */
|
|
||||||
|
|
||||||
DMA_HandleTypeDef *hdmatx; /*!< IRDA Tx DMA Handle parameters */
|
|
||||||
|
|
||||||
DMA_HandleTypeDef *hdmarx; /*!< IRDA Rx DMA Handle parameters */
|
|
||||||
|
|
||||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
|
||||||
|
|
||||||
__IO HAL_IRDA_StateTypeDef gState; /*!< IRDA state information related to global Handle management
|
|
||||||
and also related to Tx operations.
|
|
||||||
This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
|
|
||||||
|
|
||||||
__IO HAL_IRDA_StateTypeDef RxState; /*!< IRDA state information related to Rx operations.
|
|
||||||
This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
|
|
||||||
|
|
||||||
__IO uint32_t ErrorCode; /*!< IRDA Error code */
|
|
||||||
|
|
||||||
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
|
|
||||||
void (* TxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Tx Half Complete Callback */
|
|
||||||
|
|
||||||
void (* TxCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Tx Complete Callback */
|
|
||||||
|
|
||||||
void (* RxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Rx Half Complete Callback */
|
|
||||||
|
|
||||||
void (* RxCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Rx Complete Callback */
|
|
||||||
|
|
||||||
void (* ErrorCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Error Callback */
|
|
||||||
|
|
||||||
void (* AbortCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Complete Callback */
|
|
||||||
|
|
||||||
void (* AbortTransmitCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Transmit Complete Callback */
|
|
||||||
|
|
||||||
void (* AbortReceiveCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Receive Complete Callback */
|
|
||||||
|
|
||||||
|
|
||||||
void (* MspInitCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Msp Init callback */
|
|
||||||
|
|
||||||
void (* MspDeInitCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Msp DeInit callback */
|
|
||||||
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
|
|
||||||
|
|
||||||
} IRDA_HandleTypeDef;
|
|
||||||
|
|
||||||
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
|
|
||||||
/**
|
|
||||||
* @brief HAL IRDA Callback ID enumeration definition
|
|
||||||
*/
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
HAL_IRDA_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< IRDA Tx Half Complete Callback ID */
|
|
||||||
HAL_IRDA_TX_COMPLETE_CB_ID = 0x01U, /*!< IRDA Tx Complete Callback ID */
|
|
||||||
HAL_IRDA_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< IRDA Rx Half Complete Callback ID */
|
|
||||||
HAL_IRDA_RX_COMPLETE_CB_ID = 0x03U, /*!< IRDA Rx Complete Callback ID */
|
|
||||||
HAL_IRDA_ERROR_CB_ID = 0x04U, /*!< IRDA Error Callback ID */
|
|
||||||
HAL_IRDA_ABORT_COMPLETE_CB_ID = 0x05U, /*!< IRDA Abort Complete Callback ID */
|
|
||||||
HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< IRDA Abort Transmit Complete Callback ID */
|
|
||||||
HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< IRDA Abort Receive Complete Callback ID */
|
|
||||||
|
|
||||||
HAL_IRDA_MSPINIT_CB_ID = 0x08U, /*!< IRDA MspInit callback ID */
|
|
||||||
HAL_IRDA_MSPDEINIT_CB_ID = 0x09U /*!< IRDA MspDeInit callback ID */
|
|
||||||
|
|
||||||
} HAL_IRDA_CallbackIDTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief HAL IRDA Callback pointer definition
|
|
||||||
*/
|
|
||||||
typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer to an IRDA callback function */
|
|
||||||
|
|
||||||
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
|
||||||
/** @defgroup IRDA_Exported_Constants IRDA Exported Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup IRDA_State_Definition IRDA State Code Definition
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define HAL_IRDA_STATE_RESET 0x00000000U /*!< Peripheral is not initialized
|
|
||||||
Value is allowed for gState and RxState */
|
|
||||||
#define HAL_IRDA_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use
|
|
||||||
Value is allowed for gState and RxState */
|
|
||||||
#define HAL_IRDA_STATE_BUSY 0x00000024U /*!< An internal process is ongoing
|
|
||||||
Value is allowed for gState only */
|
|
||||||
#define HAL_IRDA_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing
|
|
||||||
Value is allowed for gState only */
|
|
||||||
#define HAL_IRDA_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing
|
|
||||||
Value is allowed for RxState only */
|
|
||||||
#define HAL_IRDA_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing
|
|
||||||
Not to be used for neither gState nor RxState.
|
|
||||||
Value is result of combination (Or) between gState and RxState values */
|
|
||||||
#define HAL_IRDA_STATE_TIMEOUT 0x000000A0U /*!< Timeout state
|
|
||||||
Value is allowed for gState only */
|
|
||||||
#define HAL_IRDA_STATE_ERROR 0x000000E0U /*!< Error
|
|
||||||
Value is allowed for gState only */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup IRDA_Error_Definition IRDA Error Code Definition
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
|
|
||||||
#define HAL_IRDA_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
|
|
||||||
#define HAL_IRDA_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
|
|
||||||
#define HAL_IRDA_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */
|
|
||||||
#define HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
|
|
||||||
#define HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
|
|
||||||
#define HAL_IRDA_ERROR_BUSY ((uint32_t)0x00000020U) /*!< Busy Error */
|
|
||||||
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
|
|
||||||
#define HAL_IRDA_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */
|
|
||||||
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup IRDA_Parity IRDA Parity
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define IRDA_PARITY_NONE 0x00000000U /*!< No parity */
|
|
||||||
#define IRDA_PARITY_EVEN USART_CR1_PCE /*!< Even parity */
|
|
||||||
#define IRDA_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define IRDA_MODE_RX USART_CR1_RE /*!< RX mode */
|
|
||||||
#define IRDA_MODE_TX USART_CR1_TE /*!< TX mode */
|
|
||||||
#define IRDA_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup IRDA_Low_Power IRDA Low Power
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define IRDA_POWERMODE_NORMAL 0x00000000U /*!< IRDA normal power mode */
|
|
||||||
#define IRDA_POWERMODE_LOWPOWER USART_CR3_IRLP /*!< IRDA low power mode */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup IRDA_ClockPrescaler IRDA Clock Prescaler
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define IRDA_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */
|
|
||||||
#define IRDA_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */
|
|
||||||
#define IRDA_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */
|
|
||||||
#define IRDA_PRESCALER_DIV6 0x00000003U /*!< fclk_pres = fclk/6 */
|
|
||||||
#define IRDA_PRESCALER_DIV8 0x00000004U /*!< fclk_pres = fclk/8 */
|
|
||||||
#define IRDA_PRESCALER_DIV10 0x00000005U /*!< fclk_pres = fclk/10 */
|
|
||||||
#define IRDA_PRESCALER_DIV12 0x00000006U /*!< fclk_pres = fclk/12 */
|
|
||||||
#define IRDA_PRESCALER_DIV16 0x00000007U /*!< fclk_pres = fclk/16 */
|
|
||||||
#define IRDA_PRESCALER_DIV32 0x00000008U /*!< fclk_pres = fclk/32 */
|
|
||||||
#define IRDA_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */
|
|
||||||
#define IRDA_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */
|
|
||||||
#define IRDA_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup IRDA_State IRDA State
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define IRDA_STATE_DISABLE 0x00000000U /*!< IRDA disabled */
|
|
||||||
#define IRDA_STATE_ENABLE USART_CR1_UE /*!< IRDA enabled */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup IRDA_Mode IRDA Mode
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define IRDA_MODE_DISABLE 0x00000000U /*!< Associated UART disabled in IRDA mode */
|
|
||||||
#define IRDA_MODE_ENABLE USART_CR3_IREN /*!< Associated UART enabled in IRDA mode */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup IRDA_One_Bit IRDA One Bit Sampling
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define IRDA_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< One-bit sampling disabled */
|
|
||||||
#define IRDA_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< One-bit sampling enabled */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup IRDA_DMA_Tx IRDA DMA Tx
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define IRDA_DMA_TX_DISABLE 0x00000000U /*!< IRDA DMA TX disabled */
|
|
||||||
#define IRDA_DMA_TX_ENABLE USART_CR3_DMAT /*!< IRDA DMA TX enabled */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup IRDA_DMA_Rx IRDA DMA Rx
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define IRDA_DMA_RX_DISABLE 0x00000000U /*!< IRDA DMA RX disabled */
|
|
||||||
#define IRDA_DMA_RX_ENABLE USART_CR3_DMAR /*!< IRDA DMA RX enabled */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup IRDA_Request_Parameters IRDA Request Parameters
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define IRDA_AUTOBAUD_REQUEST USART_RQR_ABRRQ /*!< Auto-Baud Rate Request */
|
|
||||||
#define IRDA_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */
|
|
||||||
#define IRDA_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup IRDA_Flags IRDA Flags
|
|
||||||
* Elements values convention: 0xXXXX
|
|
||||||
* - 0xXXXX : Flag mask in the ISR register
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define IRDA_FLAG_REACK USART_ISR_REACK /*!< IRDA receive enable acknowledge flag */
|
|
||||||
#define IRDA_FLAG_TEACK USART_ISR_TEACK /*!< IRDA transmit enable acknowledge flag */
|
|
||||||
#define IRDA_FLAG_BUSY USART_ISR_BUSY /*!< IRDA busy flag */
|
|
||||||
#define IRDA_FLAG_ABRF USART_ISR_ABRF /*!< IRDA auto Baud rate flag */
|
|
||||||
#define IRDA_FLAG_ABRE USART_ISR_ABRE /*!< IRDA auto Baud rate error */
|
|
||||||
#define IRDA_FLAG_TXE USART_ISR_TXE_TXFNF /*!< IRDA transmit data register empty */
|
|
||||||
#define IRDA_FLAG_TC USART_ISR_TC /*!< IRDA transmission complete */
|
|
||||||
#define IRDA_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< IRDA read data register not empty */
|
|
||||||
#define IRDA_FLAG_ORE USART_ISR_ORE /*!< IRDA overrun error */
|
|
||||||
#define IRDA_FLAG_NE USART_ISR_NE /*!< IRDA noise error */
|
|
||||||
#define IRDA_FLAG_FE USART_ISR_FE /*!< IRDA frame error */
|
|
||||||
#define IRDA_FLAG_PE USART_ISR_PE /*!< IRDA parity error */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup IRDA_Interrupt_definition IRDA Interrupts Definition
|
|
||||||
* Elements values convention: 0000ZZZZ0XXYYYYYb
|
|
||||||
* - YYYYY : Interrupt source position in the XX register (5bits)
|
|
||||||
* - XX : Interrupt source register (2bits)
|
|
||||||
* - 01: CR1 register
|
|
||||||
* - 10: CR2 register
|
|
||||||
* - 11: CR3 register
|
|
||||||
* - ZZZZ : Flag position in the ISR register(4bits)
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define IRDA_IT_PE 0x0028U /*!< IRDA Parity error interruption */
|
|
||||||
#define IRDA_IT_TXE 0x0727U /*!< IRDA Transmit data register empty interruption */
|
|
||||||
#define IRDA_IT_TC 0x0626U /*!< IRDA Transmission complete interruption */
|
|
||||||
#define IRDA_IT_RXNE 0x0525U /*!< IRDA Read data register not empty interruption */
|
|
||||||
#define IRDA_IT_IDLE 0x0424U /*!< IRDA Idle interruption */
|
|
||||||
|
|
||||||
/* Elements values convention: 000000000XXYYYYYb
|
|
||||||
- YYYYY : Interrupt source position in the XX register (5bits)
|
|
||||||
- XX : Interrupt source register (2bits)
|
|
||||||
- 01: CR1 register
|
|
||||||
- 10: CR2 register
|
|
||||||
- 11: CR3 register */
|
|
||||||
#define IRDA_IT_ERR 0x0060U /*!< IRDA Error interruption */
|
|
||||||
|
|
||||||
/* Elements values convention: 0000ZZZZ00000000b
|
|
||||||
- ZZZZ : Flag position in the ISR register(4bits) */
|
|
||||||
#define IRDA_IT_ORE 0x0300U /*!< IRDA Overrun error interruption */
|
|
||||||
#define IRDA_IT_NE 0x0200U /*!< IRDA Noise error interruption */
|
|
||||||
#define IRDA_IT_FE 0x0100U /*!< IRDA Frame error interruption */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup IRDA_IT_CLEAR_Flags IRDA Interruption Clear Flags
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define IRDA_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
|
|
||||||
#define IRDA_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
|
|
||||||
#define IRDA_CLEAR_NEF USART_ICR_NECF /*!< Noise Error detected Clear Flag */
|
|
||||||
#define IRDA_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
|
|
||||||
#define IRDA_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
|
|
||||||
#define IRDA_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup IRDA_Interruption_Mask IRDA interruptions flags mask
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define IRDA_IT_MASK 0x001FU /*!< IRDA Interruptions flags mask */
|
|
||||||
#define IRDA_CR_MASK 0x00E0U /*!< IRDA control register mask */
|
|
||||||
#define IRDA_CR_POS 5U /*!< IRDA control register position */
|
|
||||||
#define IRDA_ISR_MASK 0x1F00U /*!< IRDA ISR register mask */
|
|
||||||
#define IRDA_ISR_POS 8U /*!< IRDA ISR register position */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported macros -----------------------------------------------------------*/
|
|
||||||
/** @defgroup IRDA_Exported_Macros IRDA Exported Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @brief Reset IRDA handle state.
|
|
||||||
* @param __HANDLE__ IRDA handle.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
|
|
||||||
#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
|
||||||
(__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \
|
|
||||||
(__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \
|
|
||||||
(__HANDLE__)->MspInitCallback = NULL; \
|
|
||||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
|
||||||
} while(0U)
|
|
||||||
#else
|
|
||||||
#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
|
||||||
(__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \
|
|
||||||
(__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \
|
|
||||||
} while(0U)
|
|
||||||
#endif /*USE_HAL_IRDA_REGISTER_CALLBACKS */
|
|
||||||
|
|
||||||
/** @brief Flush the IRDA DR register.
|
|
||||||
* @param __HANDLE__ specifies the IRDA Handle.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) \
|
|
||||||
do{ \
|
|
||||||
SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
|
|
||||||
SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
|
|
||||||
} while(0U)
|
|
||||||
|
|
||||||
/** @brief Clear the specified IRDA pending flag.
|
|
||||||
* @param __HANDLE__ specifies the IRDA Handle.
|
|
||||||
* @param __FLAG__ specifies the flag to check.
|
|
||||||
* This parameter can be any combination of the following values:
|
|
||||||
* @arg @ref IRDA_CLEAR_PEF
|
|
||||||
* @arg @ref IRDA_CLEAR_FEF
|
|
||||||
* @arg @ref IRDA_CLEAR_NEF
|
|
||||||
* @arg @ref IRDA_CLEAR_OREF
|
|
||||||
* @arg @ref IRDA_CLEAR_TCF
|
|
||||||
* @arg @ref IRDA_CLEAR_IDLEF
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
|
|
||||||
|
|
||||||
/** @brief Clear the IRDA PE pending flag.
|
|
||||||
* @param __HANDLE__ specifies the IRDA Handle.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)
|
|
||||||
|
|
||||||
|
|
||||||
/** @brief Clear the IRDA FE pending flag.
|
|
||||||
* @param __HANDLE__ specifies the IRDA Handle.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)
|
|
||||||
|
|
||||||
/** @brief Clear the IRDA NE pending flag.
|
|
||||||
* @param __HANDLE__ specifies the IRDA Handle.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)
|
|
||||||
|
|
||||||
/** @brief Clear the IRDA ORE pending flag.
|
|
||||||
* @param __HANDLE__ specifies the IRDA Handle.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)
|
|
||||||
|
|
||||||
/** @brief Clear the IRDA IDLE pending flag.
|
|
||||||
* @param __HANDLE__ specifies the IRDA Handle.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)
|
|
||||||
|
|
||||||
/** @brief Check whether the specified IRDA flag is set or not.
|
|
||||||
* @param __HANDLE__ specifies the IRDA Handle.
|
|
||||||
* @param __FLAG__ specifies the flag to check.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg @ref IRDA_FLAG_REACK Receive enable acknowledge flag
|
|
||||||
* @arg @ref IRDA_FLAG_TEACK Transmit enable acknowledge flag
|
|
||||||
* @arg @ref IRDA_FLAG_BUSY Busy flag
|
|
||||||
* @arg @ref IRDA_FLAG_ABRF Auto Baud rate detection flag
|
|
||||||
* @arg @ref IRDA_FLAG_ABRE Auto Baud rate detection error flag
|
|
||||||
* @arg @ref IRDA_FLAG_TXE Transmit data register empty flag
|
|
||||||
* @arg @ref IRDA_FLAG_TC Transmission Complete flag
|
|
||||||
* @arg @ref IRDA_FLAG_RXNE Receive data register not empty flag
|
|
||||||
* @arg @ref IRDA_FLAG_ORE OverRun Error flag
|
|
||||||
* @arg @ref IRDA_FLAG_NE Noise Error flag
|
|
||||||
* @arg @ref IRDA_FLAG_FE Framing Error flag
|
|
||||||
* @arg @ref IRDA_FLAG_PE Parity Error flag
|
|
||||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
|
||||||
*/
|
|
||||||
#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
|
|
||||||
|
|
||||||
|
|
||||||
/** @brief Enable the specified IRDA interrupt.
|
|
||||||
* @param __HANDLE__ specifies the IRDA Handle.
|
|
||||||
* @param __INTERRUPT__ specifies the IRDA interrupt source to enable.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
|
|
||||||
* @arg @ref IRDA_IT_TC Transmission complete interrupt
|
|
||||||
* @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
|
|
||||||
* @arg @ref IRDA_IT_IDLE Idle line detection interrupt
|
|
||||||
* @arg @ref IRDA_IT_PE Parity Error interrupt
|
|
||||||
* @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
|
|
||||||
((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
|
|
||||||
((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
|
|
||||||
|
|
||||||
/** @brief Disable the specified IRDA interrupt.
|
|
||||||
* @param __HANDLE__ specifies the IRDA Handle.
|
|
||||||
* @param __INTERRUPT__ specifies the IRDA interrupt source to disable.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
|
|
||||||
* @arg @ref IRDA_IT_TC Transmission complete interrupt
|
|
||||||
* @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
|
|
||||||
* @arg @ref IRDA_IT_IDLE Idle line detection interrupt
|
|
||||||
* @arg @ref IRDA_IT_PE Parity Error interrupt
|
|
||||||
* @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
|
|
||||||
((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
|
|
||||||
((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
|
|
||||||
|
|
||||||
|
|
||||||
/** @brief Check whether the specified IRDA interrupt has occurred or not.
|
|
||||||
* @param __HANDLE__ specifies the IRDA Handle.
|
|
||||||
* @param __INTERRUPT__ specifies the IRDA interrupt source to check.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
|
|
||||||
* @arg @ref IRDA_IT_TC Transmission complete interrupt
|
|
||||||
* @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
|
|
||||||
* @arg @ref IRDA_IT_IDLE Idle line detection interrupt
|
|
||||||
* @arg @ref IRDA_IT_ORE OverRun Error interrupt
|
|
||||||
* @arg @ref IRDA_IT_NE Noise Error interrupt
|
|
||||||
* @arg @ref IRDA_IT_FE Framing Error interrupt
|
|
||||||
* @arg @ref IRDA_IT_PE Parity Error interrupt
|
|
||||||
* @retval The new state of __IT__ (SET or RESET).
|
|
||||||
*/
|
|
||||||
#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
|
|
||||||
& (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>> IRDA_ISR_POS))) != 0U) ? SET : RESET)
|
|
||||||
|
|
||||||
/** @brief Check whether the specified IRDA interrupt source is enabled or not.
|
|
||||||
* @param __HANDLE__ specifies the IRDA Handle.
|
|
||||||
* @param __INTERRUPT__ specifies the IRDA interrupt source to check.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
|
|
||||||
* @arg @ref IRDA_IT_TC Transmission complete interrupt
|
|
||||||
* @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
|
|
||||||
* @arg @ref IRDA_IT_IDLE Idle line detection interrupt
|
|
||||||
* @arg @ref IRDA_IT_ERR Framing, overrun or noise error interrupt
|
|
||||||
* @arg @ref IRDA_IT_PE Parity Error interrupt
|
|
||||||
* @retval The new state of __IT__ (SET or RESET).
|
|
||||||
*/
|
|
||||||
#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \
|
|
||||||
(((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \
|
|
||||||
(__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET)
|
|
||||||
|
|
||||||
/** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
|
|
||||||
* @param __HANDLE__ specifies the IRDA Handle.
|
|
||||||
* @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
|
|
||||||
* to clear the corresponding interrupt
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg @ref IRDA_CLEAR_PEF Parity Error Clear Flag
|
|
||||||
* @arg @ref IRDA_CLEAR_FEF Framing Error Clear Flag
|
|
||||||
* @arg @ref IRDA_CLEAR_NEF Noise detected Clear Flag
|
|
||||||
* @arg @ref IRDA_CLEAR_OREF OverRun Error Clear Flag
|
|
||||||
* @arg @ref IRDA_CLEAR_TCF Transmission Complete Clear Flag
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
|
|
||||||
|
|
||||||
|
|
||||||
/** @brief Set a specific IRDA request flag.
|
|
||||||
* @param __HANDLE__ specifies the IRDA Handle.
|
|
||||||
* @param __REQ__ specifies the request flag to set
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg @ref IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request
|
|
||||||
* @arg @ref IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request
|
|
||||||
* @arg @ref IRDA_TXDATA_FLUSH_REQUEST Transmit data flush Request
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
|
|
||||||
|
|
||||||
/** @brief Enable the IRDA one bit sample method.
|
|
||||||
* @param __HANDLE__ specifies the IRDA Handle.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
|
|
||||||
|
|
||||||
/** @brief Disable the IRDA one bit sample method.
|
|
||||||
* @param __HANDLE__ specifies the IRDA Handle.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\
|
|
||||||
&= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
|
|
||||||
|
|
||||||
/** @brief Enable UART/USART associated to IRDA Handle.
|
|
||||||
* @param __HANDLE__ specifies the IRDA Handle.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
|
|
||||||
|
|
||||||
/** @brief Disable UART/USART associated to IRDA Handle.
|
|
||||||
* @param __HANDLE__ specifies the IRDA Handle.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private macros --------------------------------------------------------*/
|
|
||||||
/** @addtogroup IRDA_Private_Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @brief Ensure that IRDA Baud rate is less or equal to maximum value.
|
|
||||||
* @param __BAUDRATE__ specifies the IRDA Baudrate set by the user.
|
|
||||||
* @retval True or False
|
|
||||||
*/
|
|
||||||
#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201U)
|
|
||||||
|
|
||||||
/** @brief Ensure that IRDA prescaler value is strictly larger than 0.
|
|
||||||
* @param __PRESCALER__ specifies the IRDA prescaler value set by the user.
|
|
||||||
* @retval True or False
|
|
||||||
*/
|
|
||||||
#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0U)
|
|
||||||
|
|
||||||
/** @brief Ensure that IRDA frame parity is valid.
|
|
||||||
* @param __PARITY__ IRDA frame parity.
|
|
||||||
* @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
|
|
||||||
*/
|
|
||||||
#define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \
|
|
||||||
((__PARITY__) == IRDA_PARITY_EVEN) || \
|
|
||||||
((__PARITY__) == IRDA_PARITY_ODD))
|
|
||||||
|
|
||||||
/** @brief Ensure that IRDA communication mode is valid.
|
|
||||||
* @param __MODE__ IRDA communication mode.
|
|
||||||
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
|
|
||||||
*/
|
|
||||||
#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__)\
|
|
||||||
& (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
|
|
||||||
|
|
||||||
/** @brief Ensure that IRDA power mode is valid.
|
|
||||||
* @param __MODE__ IRDA power mode.
|
|
||||||
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
|
|
||||||
*/
|
|
||||||
#define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \
|
|
||||||
((__MODE__) == IRDA_POWERMODE_NORMAL))
|
|
||||||
|
|
||||||
/** @brief Ensure that IRDA clock Prescaler is valid.
|
|
||||||
* @param __CLOCKPRESCALER__ IRDA clock Prescaler value.
|
|
||||||
* @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)
|
|
||||||
*/
|
|
||||||
#define IS_IRDA_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV1) || \
|
|
||||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV2) || \
|
|
||||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV4) || \
|
|
||||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV6) || \
|
|
||||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV8) || \
|
|
||||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV10) || \
|
|
||||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV12) || \
|
|
||||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV16) || \
|
|
||||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV32) || \
|
|
||||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV64) || \
|
|
||||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV128) || \
|
|
||||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV256))
|
|
||||||
|
|
||||||
/** @brief Ensure that IRDA state is valid.
|
|
||||||
* @param __STATE__ IRDA state mode.
|
|
||||||
* @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
|
|
||||||
*/
|
|
||||||
#define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \
|
|
||||||
((__STATE__) == IRDA_STATE_ENABLE))
|
|
||||||
|
|
||||||
/** @brief Ensure that IRDA associated UART/USART mode is valid.
|
|
||||||
* @param __MODE__ IRDA associated UART/USART mode.
|
|
||||||
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
|
|
||||||
*/
|
|
||||||
#define IS_IRDA_MODE(__MODE__) (((__MODE__) == IRDA_MODE_DISABLE) || \
|
|
||||||
((__MODE__) == IRDA_MODE_ENABLE))
|
|
||||||
|
|
||||||
/** @brief Ensure that IRDA sampling rate is valid.
|
|
||||||
* @param __ONEBIT__ IRDA sampling rate.
|
|
||||||
* @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
|
|
||||||
*/
|
|
||||||
#define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \
|
|
||||||
((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE))
|
|
||||||
|
|
||||||
/** @brief Ensure that IRDA DMA TX mode is valid.
|
|
||||||
* @param __DMATX__ IRDA DMA TX mode.
|
|
||||||
* @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
|
|
||||||
*/
|
|
||||||
#define IS_IRDA_DMA_TX(__DMATX__) (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \
|
|
||||||
((__DMATX__) == IRDA_DMA_TX_ENABLE))
|
|
||||||
|
|
||||||
/** @brief Ensure that IRDA DMA RX mode is valid.
|
|
||||||
* @param __DMARX__ IRDA DMA RX mode.
|
|
||||||
* @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
|
|
||||||
*/
|
|
||||||
#define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \
|
|
||||||
((__DMARX__) == IRDA_DMA_RX_ENABLE))
|
|
||||||
|
|
||||||
/** @brief Ensure that IRDA request is valid.
|
|
||||||
* @param __PARAM__ IRDA request.
|
|
||||||
* @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
|
|
||||||
*/
|
|
||||||
#define IS_IRDA_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \
|
|
||||||
((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \
|
|
||||||
((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Include IRDA HAL Extended module */
|
|
||||||
#include "stm32wlxx_hal_irda_ex.h"
|
|
||||||
|
|
||||||
/* Exported functions --------------------------------------------------------*/
|
|
||||||
/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Initialization and de-initialization functions ****************************/
|
|
||||||
HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
|
|
||||||
HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
|
|
||||||
void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
|
|
||||||
void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
|
|
||||||
|
|
||||||
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
|
|
||||||
/* Callbacks Register/UnRegister functions ***********************************/
|
|
||||||
HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID,
|
|
||||||
pIRDA_CallbackTypeDef pCallback);
|
|
||||||
HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID);
|
|
||||||
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* IO operation functions *****************************************************/
|
|
||||||
HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
|
||||||
HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
|
||||||
HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
|
|
||||||
HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
|
|
||||||
HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
|
|
||||||
HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
|
|
||||||
HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
|
|
||||||
HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
|
|
||||||
HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
|
|
||||||
/* Transfer Abort functions */
|
|
||||||
HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda);
|
|
||||||
HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda);
|
|
||||||
HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda);
|
|
||||||
HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda);
|
|
||||||
HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda);
|
|
||||||
HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda);
|
|
||||||
|
|
||||||
void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
|
|
||||||
void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
|
|
||||||
void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
|
|
||||||
void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
|
|
||||||
void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
|
|
||||||
void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
|
|
||||||
void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda);
|
|
||||||
void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda);
|
|
||||||
void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Peripheral Control functions ************************************************/
|
|
||||||
|
|
||||||
/** @addtogroup IRDA_Exported_Functions_Group4 Peripheral State and Error functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Peripheral State and Error functions ***************************************/
|
|
||||||
HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
|
|
||||||
uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* STM32WLxx_HAL_IRDA_H */
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,196 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32wlxx_hal_irda_ex.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief Header file of IRDA HAL Extended module.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
|
||||||
* All rights reserved.</center></h2>
|
|
||||||
*
|
|
||||||
* This software component is licensed by ST under BSD 3-Clause license,
|
|
||||||
* the "License"; You may not use this file except in compliance with the
|
|
||||||
* License. You may obtain a copy of the License at:
|
|
||||||
* opensource.org/licenses/BSD-3-Clause
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef STM32WLxx_HAL_IRDA_EX_H
|
|
||||||
#define STM32WLxx_HAL_IRDA_EX_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32wlxx_hal_def.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32WLxx_HAL_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup IRDAEx IRDAEx
|
|
||||||
* @brief IRDA Extended HAL module driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
|
||||||
/** @defgroup IRDAEx_Extended_Exported_Constants IRDAEx Extended Exported Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup IRDAEx_Word_Length IRDAEx Word Length
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define IRDA_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long frame */
|
|
||||||
#define IRDA_WORDLENGTH_8B 0x00000000U /*!< 8-bit long frame */
|
|
||||||
#define IRDA_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long frame */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported macros -----------------------------------------------------------*/
|
|
||||||
|
|
||||||
/* Private macros ------------------------------------------------------------*/
|
|
||||||
|
|
||||||
/** @defgroup IRDAEx_Private_Macros IRDAEx Private Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @brief Report the IRDA clock source.
|
|
||||||
* @param __HANDLE__ specifies the IRDA Handle.
|
|
||||||
* @param __CLOCKSOURCE__ output variable.
|
|
||||||
* @retval IRDA clocking source, written in __CLOCKSOURCE__.
|
|
||||||
*/
|
|
||||||
#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
|
||||||
do { \
|
|
||||||
if((__HANDLE__)->Instance == USART1) \
|
|
||||||
{ \
|
|
||||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
|
||||||
{ \
|
|
||||||
case RCC_USART1CLKSOURCE_PCLK2: \
|
|
||||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \
|
|
||||||
break; \
|
|
||||||
case RCC_USART1CLKSOURCE_HSI: \
|
|
||||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
|
||||||
break; \
|
|
||||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
|
||||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
|
||||||
break; \
|
|
||||||
case RCC_USART1CLKSOURCE_LSE: \
|
|
||||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
|
||||||
break; \
|
|
||||||
default: \
|
|
||||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
|
||||||
break; \
|
|
||||||
} \
|
|
||||||
} \
|
|
||||||
else if((__HANDLE__)->Instance == USART2) \
|
|
||||||
{ \
|
|
||||||
switch(__HAL_RCC_GET_USART2_SOURCE()) \
|
|
||||||
{ \
|
|
||||||
case RCC_USART2CLKSOURCE_PCLK1: \
|
|
||||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
|
||||||
break; \
|
|
||||||
case RCC_USART2CLKSOURCE_HSI: \
|
|
||||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
|
||||||
break; \
|
|
||||||
case RCC_USART2CLKSOURCE_SYSCLK: \
|
|
||||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
|
||||||
break; \
|
|
||||||
case RCC_USART2CLKSOURCE_LSE: \
|
|
||||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
|
||||||
break; \
|
|
||||||
default: \
|
|
||||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
|
||||||
break; \
|
|
||||||
} \
|
|
||||||
} \
|
|
||||||
else \
|
|
||||||
{ \
|
|
||||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
|
||||||
} \
|
|
||||||
} while(0U)
|
|
||||||
|
|
||||||
/** @brief Compute the mask to apply to retrieve the received data
|
|
||||||
* according to the word length and to the parity bits activation.
|
|
||||||
* @param __HANDLE__ specifies the IRDA Handle.
|
|
||||||
* @retval None, the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field.
|
|
||||||
*/
|
|
||||||
#define IRDA_MASK_COMPUTATION(__HANDLE__) \
|
|
||||||
do { \
|
|
||||||
if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \
|
|
||||||
{ \
|
|
||||||
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
|
|
||||||
{ \
|
|
||||||
(__HANDLE__)->Mask = 0x01FFU ; \
|
|
||||||
} \
|
|
||||||
else \
|
|
||||||
{ \
|
|
||||||
(__HANDLE__)->Mask = 0x00FFU ; \
|
|
||||||
} \
|
|
||||||
} \
|
|
||||||
else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \
|
|
||||||
{ \
|
|
||||||
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
|
|
||||||
{ \
|
|
||||||
(__HANDLE__)->Mask = 0x00FFU ; \
|
|
||||||
} \
|
|
||||||
else \
|
|
||||||
{ \
|
|
||||||
(__HANDLE__)->Mask = 0x007FU ; \
|
|
||||||
} \
|
|
||||||
} \
|
|
||||||
else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \
|
|
||||||
{ \
|
|
||||||
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
|
|
||||||
{ \
|
|
||||||
(__HANDLE__)->Mask = 0x007FU ; \
|
|
||||||
} \
|
|
||||||
else \
|
|
||||||
{ \
|
|
||||||
(__HANDLE__)->Mask = 0x003FU ; \
|
|
||||||
} \
|
|
||||||
} \
|
|
||||||
else \
|
|
||||||
{ \
|
|
||||||
(__HANDLE__)->Mask = 0x0000U; \
|
|
||||||
} \
|
|
||||||
} while(0U)
|
|
||||||
|
|
||||||
/** @brief Ensure that IRDA frame length is valid.
|
|
||||||
* @param __LENGTH__ IRDA frame length.
|
|
||||||
* @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
|
|
||||||
*/
|
|
||||||
#define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_7B) || \
|
|
||||||
((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
|
|
||||||
((__LENGTH__) == IRDA_WORDLENGTH_9B))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported functions --------------------------------------------------------*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* STM32WLxx_HAL_IRDA_EX_H */
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,240 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32wlxx_hal_iwdg.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief Header file of IWDG HAL module.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
|
||||||
* All rights reserved.</center></h2>
|
|
||||||
*
|
|
||||||
* This software component is licensed by ST under BSD 3-Clause license,
|
|
||||||
* the "License"; You may not use this file except in compliance with the
|
|
||||||
* License. You may obtain a copy of the License at:
|
|
||||||
* opensource.org/licenses/BSD-3-Clause
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef STM32WLxx_HAL_IWDG_H
|
|
||||||
#define STM32WLxx_HAL_IWDG_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32wlxx_hal_def.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32WLxx_HAL_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup IWDG IWDG
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
/** @defgroup IWDG_Exported_Types IWDG Exported Types
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief IWDG Init structure definition
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t Prescaler; /*!< Select the prescaler of the IWDG.
|
|
||||||
This parameter can be a value of @ref IWDG_Prescaler */
|
|
||||||
|
|
||||||
uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.
|
|
||||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
|
|
||||||
|
|
||||||
uint32_t Window; /*!< Specifies the window value to be compared to the down-counter.
|
|
||||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
|
|
||||||
|
|
||||||
} IWDG_InitTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief IWDG Handle Structure definition
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
IWDG_TypeDef *Instance; /*!< Register base address */
|
|
||||||
|
|
||||||
IWDG_InitTypeDef Init; /*!< IWDG required parameters */
|
|
||||||
} IWDG_HandleTypeDef;
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
|
||||||
/** @defgroup IWDG_Exported_Constants IWDG Exported Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup IWDG_Prescaler IWDG Prescaler
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define IWDG_PRESCALER_4 0x00000000u /*!< IWDG prescaler set to 4 */
|
|
||||||
#define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */
|
|
||||||
#define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */
|
|
||||||
#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */
|
|
||||||
#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */
|
|
||||||
#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
|
|
||||||
#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup IWDG_Window_option IWDG Window option
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define IWDG_WINDOW_DISABLE IWDG_WINR_WIN
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported macros -----------------------------------------------------------*/
|
|
||||||
/** @defgroup IWDG_Exported_Macros IWDG Exported Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the IWDG peripheral.
|
|
||||||
* @param __HANDLE__ IWDG handle
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Reload IWDG counter with value defined in the reload register
|
|
||||||
* (write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers disabled).
|
|
||||||
* @param __HANDLE__ IWDG handle
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported functions --------------------------------------------------------*/
|
|
||||||
/** @defgroup IWDG_Exported_Functions IWDG Exported Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Initialization/Start functions ********************************************/
|
|
||||||
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* I/O operation functions ****************************************************/
|
|
||||||
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private constants ---------------------------------------------------------*/
|
|
||||||
/** @defgroup IWDG_Private_Constants IWDG Private Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief IWDG Key Register BitMask
|
|
||||||
*/
|
|
||||||
#define IWDG_KEY_RELOAD 0x0000AAAAu /*!< IWDG Reload Counter Enable */
|
|
||||||
#define IWDG_KEY_ENABLE 0x0000CCCCu /*!< IWDG Peripheral Enable */
|
|
||||||
#define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u /*!< IWDG KR Write Access Enable */
|
|
||||||
#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u /*!< IWDG KR Write Access Disable */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private macros ------------------------------------------------------------*/
|
|
||||||
/** @defgroup IWDG_Private_Macros IWDG Private Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
|
|
||||||
* @param __HANDLE__ IWDG handle
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
|
|
||||||
* @param __HANDLE__ IWDG handle
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Check IWDG prescaler value.
|
|
||||||
* @param __PRESCALER__ IWDG prescaler value
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \
|
|
||||||
((__PRESCALER__) == IWDG_PRESCALER_8) || \
|
|
||||||
((__PRESCALER__) == IWDG_PRESCALER_16) || \
|
|
||||||
((__PRESCALER__) == IWDG_PRESCALER_32) || \
|
|
||||||
((__PRESCALER__) == IWDG_PRESCALER_64) || \
|
|
||||||
((__PRESCALER__) == IWDG_PRESCALER_128)|| \
|
|
||||||
((__PRESCALER__) == IWDG_PRESCALER_256))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Check IWDG reload value.
|
|
||||||
* @param __RELOAD__ IWDG reload value
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Check IWDG window value.
|
|
||||||
* @param __WINDOW__ IWDG window value
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN)
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* STM32WLxx_HAL_IWDG_H */
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,889 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32wlxx_hal_lptim.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief Header file of LPTIM HAL module.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
|
||||||
* All rights reserved.</center></h2>
|
|
||||||
*
|
|
||||||
* This software component is licensed by ST under BSD 3-Clause license,
|
|
||||||
* the "License"; You may not use this file except in compliance with the
|
|
||||||
* License. You may obtain a copy of the License at:
|
|
||||||
* opensource.org/licenses/BSD-3-Clause
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef STM32WLxx_HAL_LPTIM_H
|
|
||||||
#define STM32WLxx_HAL_LPTIM_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32wlxx_hal_def.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32WLxx_HAL_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#if defined (LPTIM1) || defined (LPTIM2) || defined (LPTIM3)
|
|
||||||
|
|
||||||
/** @addtogroup LPTIM
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
/** @defgroup LPTIM_Exported_Types LPTIM Exported Types
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define LPTIM_EXTI_LINE_LPTIM1 EXTI_IMR1_IM29 /*!< External interrupt line 29 Connected to the LPTIM1 EXTI Line */
|
|
||||||
#define LPTIM_EXTI_LINE_LPTIM2 EXTI_IMR1_IM30 /*!< External interrupt line 30 Connected to the LPTIM2 EXTI Line */
|
|
||||||
#define LPTIM_EXTI_LINE_LPTIM3 EXTI_IMR1_IM31 /*!< External interrupt line 31 Connected to the LPTIM3 EXTI Line */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief LPTIM Clock configuration definition
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t Source; /*!< Selects the clock source.
|
|
||||||
This parameter can be a value of @ref LPTIM_Clock_Source */
|
|
||||||
|
|
||||||
uint32_t Prescaler; /*!< Specifies the counter clock Prescaler.
|
|
||||||
This parameter can be a value of @ref LPTIM_Clock_Prescaler */
|
|
||||||
|
|
||||||
} LPTIM_ClockConfigTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief LPTIM Clock configuration definition
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t Polarity; /*!< Selects the polarity of the active edge for the counter unit
|
|
||||||
if the ULPTIM input is selected.
|
|
||||||
Note: This parameter is used only when Ultra low power clock source is used.
|
|
||||||
Note: If the polarity is configured on 'both edges', an auxiliary clock
|
|
||||||
(one of the Low power oscillator) must be active.
|
|
||||||
This parameter can be a value of @ref LPTIM_Clock_Polarity */
|
|
||||||
|
|
||||||
uint32_t SampleTime; /*!< Selects the clock sampling time to configure the clock glitch filter.
|
|
||||||
Note: This parameter is used only when Ultra low power clock source is used.
|
|
||||||
This parameter can be a value of @ref LPTIM_Clock_Sample_Time */
|
|
||||||
|
|
||||||
} LPTIM_ULPClockConfigTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief LPTIM Trigger configuration definition
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t Source; /*!< Selects the Trigger source.
|
|
||||||
This parameter can be a value of @ref LPTIM_Trigger_Source */
|
|
||||||
|
|
||||||
uint32_t ActiveEdge; /*!< Selects the Trigger active edge.
|
|
||||||
Note: This parameter is used only when an external trigger is used.
|
|
||||||
This parameter can be a value of @ref LPTIM_External_Trigger_Polarity */
|
|
||||||
|
|
||||||
uint32_t SampleTime; /*!< Selects the trigger sampling time to configure the clock glitch filter.
|
|
||||||
Note: This parameter is used only when an external trigger is used.
|
|
||||||
This parameter can be a value of @ref LPTIM_Trigger_Sample_Time */
|
|
||||||
} LPTIM_TriggerConfigTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief LPTIM Initialization Structure definition
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
LPTIM_ClockConfigTypeDef Clock; /*!< Specifies the clock parameters */
|
|
||||||
|
|
||||||
LPTIM_ULPClockConfigTypeDef UltraLowPowerClock; /*!< Specifies the Ultra Low Power clock parameters */
|
|
||||||
|
|
||||||
LPTIM_TriggerConfigTypeDef Trigger; /*!< Specifies the Trigger parameters */
|
|
||||||
|
|
||||||
uint32_t OutputPolarity; /*!< Specifies the Output polarity.
|
|
||||||
This parameter can be a value of @ref LPTIM_Output_Polarity */
|
|
||||||
|
|
||||||
uint32_t UpdateMode; /*!< Specifies whether the update of the autoreload and the compare
|
|
||||||
values is done immediately or after the end of current period.
|
|
||||||
This parameter can be a value of @ref LPTIM_Updating_Mode */
|
|
||||||
|
|
||||||
uint32_t CounterSource; /*!< Specifies whether the counter is incremented each internal event
|
|
||||||
or each external event.
|
|
||||||
This parameter can be a value of @ref LPTIM_Counter_Source */
|
|
||||||
|
|
||||||
uint32_t Input1Source; /*!< Specifies source selected for input1 (GPIO or comparator output).
|
|
||||||
This parameter can be a value of @ref LPTIM_Input1_Source */
|
|
||||||
|
|
||||||
uint32_t Input2Source; /*!< Specifies source selected for input2 (GPIO or comparator output).
|
|
||||||
Note: This parameter is used only for encoder feature so is used only
|
|
||||||
for LPTIM1 instance.
|
|
||||||
This parameter can be a value of @ref LPTIM_Input2_Source */
|
|
||||||
|
|
||||||
uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
|
|
||||||
reaches zero, an update event is generated and counting restarts
|
|
||||||
from the RCR value (N).
|
|
||||||
Note: When using repetition counter the UpdateMode field must be set to
|
|
||||||
LPTIM_UPDATE_ENDOFPERIOD otherwise unpredictable behavior may occur.
|
|
||||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
|
|
||||||
} LPTIM_InitTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief HAL LPTIM State structure definition
|
|
||||||
*/
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
HAL_LPTIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
|
|
||||||
HAL_LPTIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
|
|
||||||
HAL_LPTIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
|
|
||||||
HAL_LPTIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
|
|
||||||
HAL_LPTIM_STATE_ERROR = 0x04U /*!< Internal Process is ongoing */
|
|
||||||
} HAL_LPTIM_StateTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief LPTIM handle Structure definition
|
|
||||||
*/
|
|
||||||
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
|
|
||||||
typedef struct __LPTIM_HandleTypeDef
|
|
||||||
#else
|
|
||||||
typedef struct
|
|
||||||
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
|
|
||||||
{
|
|
||||||
LPTIM_TypeDef *Instance; /*!< Register base address */
|
|
||||||
|
|
||||||
LPTIM_InitTypeDef Init; /*!< LPTIM required parameters */
|
|
||||||
|
|
||||||
HAL_StatusTypeDef Status; /*!< LPTIM peripheral status */
|
|
||||||
|
|
||||||
HAL_LockTypeDef Lock; /*!< LPTIM locking object */
|
|
||||||
|
|
||||||
__IO HAL_LPTIM_StateTypeDef State; /*!< LPTIM peripheral state */
|
|
||||||
|
|
||||||
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
|
|
||||||
void (* MspInitCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Base Msp Init Callback */
|
|
||||||
void (* MspDeInitCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Base Msp DeInit Callback */
|
|
||||||
void (* CompareMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Compare match Callback */
|
|
||||||
void (* AutoReloadMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Auto-reload match Callback */
|
|
||||||
void (* TriggerCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< External trigger event detection Callback */
|
|
||||||
void (* CompareWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Compare register write complete Callback */
|
|
||||||
void (* AutoReloadWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Auto-reload register write complete Callback */
|
|
||||||
void (* DirectionUpCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Up-counting direction change Callback */
|
|
||||||
void (* DirectionDownCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Down-counting direction change Callback */
|
|
||||||
void (* UpdateEventCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Update event detection Callback */
|
|
||||||
void (* RepCounterWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Repetition counter register write complete Callback */
|
|
||||||
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
|
|
||||||
} LPTIM_HandleTypeDef;
|
|
||||||
|
|
||||||
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
|
|
||||||
/**
|
|
||||||
* @brief HAL LPTIM Callback ID enumeration definition
|
|
||||||
*/
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
HAL_LPTIM_MSPINIT_CB_ID = 0x00U, /*!< LPTIM Base Msp Init Callback ID */
|
|
||||||
HAL_LPTIM_MSPDEINIT_CB_ID = 0x01U, /*!< LPTIM Base Msp DeInit Callback ID */
|
|
||||||
HAL_LPTIM_COMPARE_MATCH_CB_ID = 0x02U, /*!< Compare match Callback ID */
|
|
||||||
HAL_LPTIM_AUTORELOAD_MATCH_CB_ID = 0x03U, /*!< Auto-reload match Callback ID */
|
|
||||||
HAL_LPTIM_TRIGGER_CB_ID = 0x04U, /*!< External trigger event detection Callback ID */
|
|
||||||
HAL_LPTIM_COMPARE_WRITE_CB_ID = 0x05U, /*!< Compare register write complete Callback ID */
|
|
||||||
HAL_LPTIM_AUTORELOAD_WRITE_CB_ID = 0x06U, /*!< Auto-reload register write complete Callback ID */
|
|
||||||
HAL_LPTIM_DIRECTION_UP_CB_ID = 0x07U, /*!< Up-counting direction change Callback ID */
|
|
||||||
HAL_LPTIM_DIRECTION_DOWN_CB_ID = 0x08U, /*!< Down-counting direction change Callback ID */
|
|
||||||
HAL_LPTIM_UPDATE_EVENT_CB_ID = 0x09U, /*!< Update event detection Callback ID */
|
|
||||||
HAL_LPTIM_REP_COUNTER_WRITE_CB_ID = 0x0AU, /*!< Repetition counter register write complete Callback ID */
|
|
||||||
} HAL_LPTIM_CallbackIDTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief HAL TIM Callback pointer definition
|
|
||||||
*/
|
|
||||||
typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< pointer to the LPTIM callback function */
|
|
||||||
|
|
||||||
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
|
||||||
/** @defgroup LPTIM_Exported_Constants LPTIM Exported Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup LPTIM_Clock_Source LPTIM Clock Source
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC 0x00000000U
|
|
||||||
#define LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup LPTIM_Clock_Prescaler LPTIM Clock Prescaler
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define LPTIM_PRESCALER_DIV1 0x00000000U
|
|
||||||
#define LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0
|
|
||||||
#define LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1
|
|
||||||
#define LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1)
|
|
||||||
#define LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2
|
|
||||||
#define LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2)
|
|
||||||
#define LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2)
|
|
||||||
#define LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup LPTIM_Output_Polarity LPTIM Output Polarity
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define LPTIM_OUTPUTPOLARITY_HIGH 0x00000000U
|
|
||||||
#define LPTIM_OUTPUTPOLARITY_LOW LPTIM_CFGR_WAVPOL
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup LPTIM_Clock_Sample_Time LPTIM Clock Sample Time
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION 0x00000000U
|
|
||||||
#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0
|
|
||||||
#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1
|
|
||||||
#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup LPTIM_Clock_Polarity LPTIM Clock Polarity
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define LPTIM_CLOCKPOLARITY_RISING 0x00000000U
|
|
||||||
#define LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0
|
|
||||||
#define LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup LPTIM_Trigger_Source LPTIM Trigger Source
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define LPTIM_TRIGSOURCE_SOFTWARE 0x0000FFFFU
|
|
||||||
#define LPTIM_TRIGSOURCE_0 0x00000000U
|
|
||||||
#define LPTIM_TRIGSOURCE_1 LPTIM_CFGR_TRIGSEL_0
|
|
||||||
#define LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1
|
|
||||||
#define LPTIM_TRIGSOURCE_3 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
|
|
||||||
#define LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2
|
|
||||||
#define LPTIM_TRIGSOURCE_5 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)
|
|
||||||
#define LPTIM_TRIGSOURCE_6 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2)
|
|
||||||
#define LPTIM_TRIGSOURCE_7 LPTIM_CFGR_TRIGSEL
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup LPTIM_External_Trigger_Polarity LPTIM External Trigger Polarity
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define LPTIM_ACTIVEEDGE_RISING LPTIM_CFGR_TRIGEN_0
|
|
||||||
#define LPTIM_ACTIVEEDGE_FALLING LPTIM_CFGR_TRIGEN_1
|
|
||||||
#define LPTIM_ACTIVEEDGE_RISING_FALLING LPTIM_CFGR_TRIGEN
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup LPTIM_Trigger_Sample_Time LPTIM Trigger Sample Time
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION 0x00000000U
|
|
||||||
#define LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0
|
|
||||||
#define LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1
|
|
||||||
#define LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup LPTIM_Updating_Mode LPTIM Updating Mode
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define LPTIM_UPDATE_IMMEDIATE 0x00000000U
|
|
||||||
#define LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup LPTIM_Counter_Source LPTIM Counter Source
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define LPTIM_COUNTERSOURCE_INTERNAL 0x00000000U
|
|
||||||
#define LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup LPTIM_Input1_Source LPTIM Input1 Source
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define LPTIM_INPUT1SOURCE_GPIO 0x00000000U /*!< For LPTIM1, LPTIM2 and LPTIM3 */
|
|
||||||
#define LPTIM_INPUT1SOURCE_COMP1 LPTIM_OR_OR_0 /*!< For LPTIM1, LPTIM2 and LPTIM3 */
|
|
||||||
#define LPTIM_INPUT1SOURCE_COMP2 LPTIM_OR_OR_1 /*!< For LPTIM2 and LPTIM3 */
|
|
||||||
#define LPTIM_INPUT1SOURCE_COMP1_COMP2 LPTIM_OR_OR /*!< For LPTIM2 and LPTIM3 */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup LPTIM_Input2_Source LPTIM Input2 Source
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define LPTIM_INPUT2SOURCE_GPIO 0x00000000U /*!< For LPTIM1 */
|
|
||||||
#define LPTIM_INPUT2SOURCE_COMP2 LPTIM_OR_OR_1 /*!< For LPTIM1 */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup LPTIM_Flag_Definition LPTIM Flags Definition
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define LPTIM_FLAG_REPOK LPTIM_ISR_REPOK
|
|
||||||
#define LPTIM_FLAG_UPDATE LPTIM_ISR_UE
|
|
||||||
#define LPTIM_FLAG_DOWN LPTIM_ISR_DOWN
|
|
||||||
#define LPTIM_FLAG_UP LPTIM_ISR_UP
|
|
||||||
#define LPTIM_FLAG_ARROK LPTIM_ISR_ARROK
|
|
||||||
#define LPTIM_FLAG_CMPOK LPTIM_ISR_CMPOK
|
|
||||||
#define LPTIM_FLAG_EXTTRIG LPTIM_ISR_EXTTRIG
|
|
||||||
#define LPTIM_FLAG_ARRM LPTIM_ISR_ARRM
|
|
||||||
#define LPTIM_FLAG_CMPM LPTIM_ISR_CMPM
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup LPTIM_Interrupts_Definition LPTIM Interrupts Definition
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define LPTIM_IT_REPOK LPTIM_IER_REPOKIE
|
|
||||||
#define LPTIM_IT_UPDATE LPTIM_IER_UEIE
|
|
||||||
#define LPTIM_IT_DOWN LPTIM_IER_DOWNIE
|
|
||||||
#define LPTIM_IT_UP LPTIM_IER_UPIE
|
|
||||||
#define LPTIM_IT_ARROK LPTIM_IER_ARROKIE
|
|
||||||
#define LPTIM_IT_CMPOK LPTIM_IER_CMPOKIE
|
|
||||||
#define LPTIM_IT_EXTTRIG LPTIM_IER_EXTTRIGIE
|
|
||||||
#define LPTIM_IT_ARRM LPTIM_IER_ARRMIE
|
|
||||||
#define LPTIM_IT_CMPM LPTIM_IER_CMPMIE
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported macros -----------------------------------------------------------*/
|
|
||||||
/** @defgroup LPTIM_Exported_Macros LPTIM Exported Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @brief Reset LPTIM handle state.
|
|
||||||
* @param __HANDLE__ LPTIM handle
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
|
|
||||||
#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) do { \
|
|
||||||
(__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \
|
|
||||||
(__HANDLE__)->MspInitCallback = NULL; \
|
|
||||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
|
||||||
} while(0)
|
|
||||||
#else
|
|
||||||
#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)
|
|
||||||
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the LPTIM peripheral.
|
|
||||||
* @param __HANDLE__ LPTIM handle
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the LPTIM peripheral.
|
|
||||||
* @param __HANDLE__ LPTIM handle
|
|
||||||
* @note The following sequence is required to solve LPTIM disable HW limitation.
|
|
||||||
* Please check Errata Sheet ES0335 for more details under "MCU may remain
|
|
||||||
* stuck in LPTIM interrupt when entering Stop mode" section.
|
|
||||||
* @note Please call @ref HAL_LPTIM_GetState() after a call to __HAL_LPTIM_DISABLE to
|
|
||||||
* check for TIMEOUT.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_LPTIM_DISABLE(__HANDLE__) LPTIM_Disable(__HANDLE__)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Start the LPTIM peripheral in Continuous mode.
|
|
||||||
* @param __HANDLE__ LPTIM handle
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_LPTIM_START_CONTINUOUS(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT)
|
|
||||||
/**
|
|
||||||
* @brief Start the LPTIM peripheral in single mode.
|
|
||||||
* @param __HANDLE__ LPTIM handle
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_LPTIM_START_SINGLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Reset the LPTIM Counter register in synchronous mode.
|
|
||||||
* @param __HANDLE__ LPTIM handle
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_LPTIM_RESET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_COUNTRST)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Reset after read of the LPTIM Counter register in asynchronous mode.
|
|
||||||
* @param __HANDLE__ LPTIM handle
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_LPTIM_RESET_COUNTER_AFTERREAD(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_RSTARE)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Write the passed parameter in the Autoreload register.
|
|
||||||
* @param __HANDLE__ LPTIM handle
|
|
||||||
* @param __VALUE__ Autoreload value
|
|
||||||
* @retval None
|
|
||||||
* @note The ARR register can only be modified when the LPTIM instance is enabled.
|
|
||||||
*/
|
|
||||||
#define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Write the passed parameter in the Compare register.
|
|
||||||
* @param __HANDLE__ LPTIM handle
|
|
||||||
* @param __VALUE__ Compare value
|
|
||||||
* @retval None
|
|
||||||
* @note The CMP register can only be modified when the LPTIM instance is enabled.
|
|
||||||
*/
|
|
||||||
#define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Write the passed parameter in the Repetition register.
|
|
||||||
* @param __HANDLE__ LPTIM handle
|
|
||||||
* @param __VALUE__ Repetition value
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_LPTIM_REPETITIONCOUNTER_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->RCR = (__VALUE__))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Return the current Repetition value.
|
|
||||||
* @param __HANDLE__ LPTIM handle
|
|
||||||
* @retval Repetition register value
|
|
||||||
* @note The RCR register can only be modified when the LPTIM instance is enabled.
|
|
||||||
*/
|
|
||||||
#define __HAL_LPTIM_REPETITIONCOUNTER_GET(__HANDLE__) ((__HANDLE__)->Instance->RCR)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Check whether the specified LPTIM flag is set or not.
|
|
||||||
* @param __HANDLE__ LPTIM handle
|
|
||||||
* @param __FLAG__ LPTIM flag to check
|
|
||||||
* This parameter can be a value of:
|
|
||||||
* @arg LPTIM_FLAG_REPOK : Repetition register update OK Flag.
|
|
||||||
* @arg LPTIM_FLAG_UPDATE : Update event Flag.
|
|
||||||
* @arg LPTIM_FLAG_DOWN : Counter direction change up Flag.
|
|
||||||
* @arg LPTIM_FLAG_UP : Counter direction change down to up Flag.
|
|
||||||
* @arg LPTIM_FLAG_ARROK : Autoreload register update OK Flag.
|
|
||||||
* @arg LPTIM_FLAG_CMPOK : Compare register update OK Flag.
|
|
||||||
* @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
|
|
||||||
* @arg LPTIM_FLAG_ARRM : Autoreload match Flag.
|
|
||||||
* @arg LPTIM_FLAG_CMPM : Compare match Flag.
|
|
||||||
* @retval The state of the specified flag (SET or RESET).
|
|
||||||
*/
|
|
||||||
#define __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Clear the specified LPTIM flag.
|
|
||||||
* @param __HANDLE__ LPTIM handle.
|
|
||||||
* @param __FLAG__ LPTIM flag to clear.
|
|
||||||
* This parameter can be a value of:
|
|
||||||
* @arg LPTIM_FLAG_REPOK : Repetition register update OK Flag.
|
|
||||||
* @arg LPTIM_FLAG_UPDATE : Update event Flag.
|
|
||||||
* @arg LPTIM_FLAG_DOWN : Counter direction change up Flag.
|
|
||||||
* @arg LPTIM_FLAG_UP : Counter direction change down to up Flag.
|
|
||||||
* @arg LPTIM_FLAG_ARROK : Autoreload register update OK Flag.
|
|
||||||
* @arg LPTIM_FLAG_CMPOK : Compare register update OK Flag.
|
|
||||||
* @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
|
|
||||||
* @arg LPTIM_FLAG_ARRM : Autoreload match Flag.
|
|
||||||
* @arg LPTIM_FLAG_CMPM : Compare match Flag.
|
|
||||||
* @retval None.
|
|
||||||
*/
|
|
||||||
#define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the specified LPTIM interrupt.
|
|
||||||
* @param __HANDLE__ LPTIM handle.
|
|
||||||
* @param __INTERRUPT__ LPTIM interrupt to set.
|
|
||||||
* This parameter can be a value of:
|
|
||||||
* @arg LPTIM_IT_REPOK : Repetition register update OK Interrupt.
|
|
||||||
* @arg LPTIM_IT_UPDATE : Update event register Interrupt.
|
|
||||||
* @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
|
|
||||||
* @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
|
|
||||||
* @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
|
|
||||||
* @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt.
|
|
||||||
* @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
|
|
||||||
* @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
|
|
||||||
* @arg LPTIM_IT_CMPM : Compare match Interrupt.
|
|
||||||
* @retval None.
|
|
||||||
* @note The LPTIM interrupts can only be enabled when the LPTIM instance is disabled.
|
|
||||||
*/
|
|
||||||
#define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the specified LPTIM interrupt.
|
|
||||||
* @param __HANDLE__ LPTIM handle.
|
|
||||||
* @param __INTERRUPT__ LPTIM interrupt to set.
|
|
||||||
* This parameter can be a value of:
|
|
||||||
* @arg LPTIM_IT_REPOK : Repetition register update OK Interrupt.
|
|
||||||
* @arg LPTIM_IT_UPDATE : Update event register Interrupt.
|
|
||||||
* @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
|
|
||||||
* @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
|
|
||||||
* @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
|
|
||||||
* @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt.
|
|
||||||
* @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
|
|
||||||
* @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
|
|
||||||
* @arg LPTIM_IT_CMPM : Compare match Interrupt.
|
|
||||||
* @retval None.
|
|
||||||
* @note The LPTIM interrupts can only be disabled when the LPTIM instance is disabled.
|
|
||||||
*/
|
|
||||||
#define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Check whether the specified LPTIM interrupt source is enabled or not.
|
|
||||||
* @param __HANDLE__ LPTIM handle.
|
|
||||||
* @param __INTERRUPT__ LPTIM interrupt to check.
|
|
||||||
* This parameter can be a value of:
|
|
||||||
* @arg LPTIM_IT_REPOK : Repetition register update OK Interrupt.
|
|
||||||
* @arg LPTIM_IT_UPDATE : Update event register Interrupt.
|
|
||||||
* @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
|
|
||||||
* @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
|
|
||||||
* @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
|
|
||||||
* @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt.
|
|
||||||
* @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
|
|
||||||
* @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
|
|
||||||
* @arg LPTIM_IT_CMPM : Compare match Interrupt.
|
|
||||||
* @retval Interrupt status.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & \
|
|
||||||
(__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
|
||||||
|
|
||||||
#if defined(CORE_CM0PLUS)
|
|
||||||
#define __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT() (EXTI->C2IMR1 |= \
|
|
||||||
LPTIM_EXTI_LINE_LPTIM1)
|
|
||||||
#define __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT() (EXTI->C2IMR1 &= \
|
|
||||||
~(LPTIM_EXTI_LINE_LPTIM1))
|
|
||||||
|
|
||||||
#define __HAL_LPTIM_LPTIM2_EXTI_ENABLE_IT() (EXTI->C2IMR1 |= \
|
|
||||||
LPTIM_EXTI_LINE_LPTIM2)
|
|
||||||
#define __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT() (EXTI->C2IMR1 &= \
|
|
||||||
~(LPTIM_EXTI_LINE_LPTIM2))
|
|
||||||
|
|
||||||
#define __HAL_LPTIM_LPTIM3_EXTI_ENABLE_IT() (EXTI->C2IMR1 |= \
|
|
||||||
LPTIM_EXTI_LINE_LPTIM3)
|
|
||||||
#define __HAL_LPTIM_LPTIM3_EXTI_DISABLE_IT() (EXTI->C2IMR1 &= \
|
|
||||||
~(LPTIM_EXTI_LINE_LPTIM3))
|
|
||||||
#else
|
|
||||||
#define __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT() (EXTI->IMR1 |= \
|
|
||||||
LPTIM_EXTI_LINE_LPTIM1)
|
|
||||||
#define __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT() (EXTI->IMR1 &= \
|
|
||||||
~(LPTIM_EXTI_LINE_LPTIM1))
|
|
||||||
|
|
||||||
#define __HAL_LPTIM_LPTIM2_EXTI_ENABLE_IT() (EXTI->IMR1 |= \
|
|
||||||
LPTIM_EXTI_LINE_LPTIM2)
|
|
||||||
#define __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT() (EXTI->IMR1 &= \
|
|
||||||
~(LPTIM_EXTI_LINE_LPTIM2))
|
|
||||||
|
|
||||||
#define __HAL_LPTIM_LPTIM3_EXTI_ENABLE_IT() (EXTI->IMR1 |= \
|
|
||||||
LPTIM_EXTI_LINE_LPTIM3)
|
|
||||||
#define __HAL_LPTIM_LPTIM3_EXTI_DISABLE_IT() (EXTI->IMR1 &= \
|
|
||||||
~(LPTIM_EXTI_LINE_LPTIM3))
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported functions --------------------------------------------------------*/
|
|
||||||
/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup LPTIM_Exported_Functions_Group1
|
|
||||||
* @brief Initialization and Configuration functions.
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Initialization/de-initialization functions ********************************/
|
|
||||||
HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim);
|
|
||||||
HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
|
|
||||||
|
|
||||||
/* MSP functions *************************************************************/
|
|
||||||
void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim);
|
|
||||||
void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup LPTIM_Exported_Functions_Group2
|
|
||||||
* @brief Start-Stop operation functions.
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Start/Stop operation functions *********************************************/
|
|
||||||
/* ################################# PWM Mode ################################*/
|
|
||||||
/* Blocking mode: Polling */
|
|
||||||
HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
|
|
||||||
HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim);
|
|
||||||
/* Non-Blocking mode: Interrupt */
|
|
||||||
HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
|
|
||||||
HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim);
|
|
||||||
|
|
||||||
/* ############################# One Pulse Mode ##############################*/
|
|
||||||
/* Blocking mode: Polling */
|
|
||||||
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
|
|
||||||
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim);
|
|
||||||
/* Non-Blocking mode: Interrupt */
|
|
||||||
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
|
|
||||||
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim);
|
|
||||||
|
|
||||||
/* ############################## Set once Mode ##############################*/
|
|
||||||
/* Blocking mode: Polling */
|
|
||||||
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
|
|
||||||
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim);
|
|
||||||
/* Non-Blocking mode: Interrupt */
|
|
||||||
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
|
|
||||||
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim);
|
|
||||||
|
|
||||||
/* ############################### Encoder Mode ##############################*/
|
|
||||||
/* Blocking mode: Polling */
|
|
||||||
HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
|
|
||||||
HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim);
|
|
||||||
/* Non-Blocking mode: Interrupt */
|
|
||||||
HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
|
|
||||||
HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim);
|
|
||||||
|
|
||||||
/* ############################# Time out Mode ##############################*/
|
|
||||||
/* Blocking mode: Polling */
|
|
||||||
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
|
|
||||||
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim);
|
|
||||||
/* Non-Blocking mode: Interrupt */
|
|
||||||
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
|
|
||||||
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim);
|
|
||||||
|
|
||||||
/* ############################## Counter Mode ###############################*/
|
|
||||||
/* Blocking mode: Polling */
|
|
||||||
HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
|
|
||||||
HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim);
|
|
||||||
/* Non-Blocking mode: Interrupt */
|
|
||||||
HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
|
|
||||||
HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup LPTIM_Exported_Functions_Group3
|
|
||||||
* @brief Read operation functions.
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Reading operation functions ************************************************/
|
|
||||||
uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim);
|
|
||||||
uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim);
|
|
||||||
uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup LPTIM_Exported_Functions_Group4
|
|
||||||
* @brief LPTIM IRQ handler and callback functions.
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* LPTIM IRQ functions *******************************************************/
|
|
||||||
void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim);
|
|
||||||
|
|
||||||
/* CallBack functions ********************************************************/
|
|
||||||
void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim);
|
|
||||||
void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim);
|
|
||||||
void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim);
|
|
||||||
void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim);
|
|
||||||
void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim);
|
|
||||||
void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim);
|
|
||||||
void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim);
|
|
||||||
void HAL_LPTIM_UpdateEventCallback(LPTIM_HandleTypeDef *hlptim);
|
|
||||||
void HAL_LPTIM_RepCounterWriteCallback(LPTIM_HandleTypeDef *hlptim);
|
|
||||||
|
|
||||||
/* Callbacks Register/UnRegister functions ***********************************/
|
|
||||||
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
|
|
||||||
HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID,
|
|
||||||
pLPTIM_CallbackTypeDef pCallback);
|
|
||||||
HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID);
|
|
||||||
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup LPTIM_Group5
|
|
||||||
* @brief Peripheral State functions.
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Peripheral State functions ************************************************/
|
|
||||||
HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private types -------------------------------------------------------------*/
|
|
||||||
/** @defgroup LPTIM_Private_Types LPTIM Private Types
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private variables ---------------------------------------------------------*/
|
|
||||||
/** @defgroup LPTIM_Private_Variables LPTIM Private Variables
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private constants ---------------------------------------------------------*/
|
|
||||||
/** @defgroup LPTIM_Private_Constants LPTIM Private Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private macros ------------------------------------------------------------*/
|
|
||||||
/** @defgroup LPTIM_Private_Macros LPTIM Private Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define IS_LPTIM_CLOCK_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \
|
|
||||||
((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC))
|
|
||||||
|
|
||||||
|
|
||||||
#define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LPTIM_PRESCALER_DIV1 ) || \
|
|
||||||
((__PRESCALER__) == LPTIM_PRESCALER_DIV2 ) || \
|
|
||||||
((__PRESCALER__) == LPTIM_PRESCALER_DIV4 ) || \
|
|
||||||
((__PRESCALER__) == LPTIM_PRESCALER_DIV8 ) || \
|
|
||||||
((__PRESCALER__) == LPTIM_PRESCALER_DIV16 ) || \
|
|
||||||
((__PRESCALER__) == LPTIM_PRESCALER_DIV32 ) || \
|
|
||||||
((__PRESCALER__) == LPTIM_PRESCALER_DIV64 ) || \
|
|
||||||
((__PRESCALER__) == LPTIM_PRESCALER_DIV128))
|
|
||||||
|
|
||||||
#define IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1)
|
|
||||||
|
|
||||||
#define IS_LPTIM_OUTPUT_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || \
|
|
||||||
((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH))
|
|
||||||
|
|
||||||
#define IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \
|
|
||||||
((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS) || \
|
|
||||||
((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS) || \
|
|
||||||
((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS))
|
|
||||||
|
|
||||||
#define IS_LPTIM_CLOCK_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING) || \
|
|
||||||
((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \
|
|
||||||
((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))
|
|
||||||
|
|
||||||
#define IS_LPTIM_TRG_SOURCE(__TRIG__) (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
|
|
||||||
((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
|
|
||||||
((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
|
|
||||||
((__TRIG__) == LPTIM_TRIGSOURCE_2) || \
|
|
||||||
((__TRIG__) == LPTIM_TRIGSOURCE_3) || \
|
|
||||||
((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
|
|
||||||
((__TRIG__) == LPTIM_TRIGSOURCE_5) || \
|
|
||||||
((__TRIG__) == LPTIM_TRIGSOURCE_6) || \
|
|
||||||
((__TRIG__) == LPTIM_TRIGSOURCE_7))
|
|
||||||
|
|
||||||
#define IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING ) || \
|
|
||||||
((__POLARITY__) == LPTIM_ACTIVEEDGE_FALLING ) || \
|
|
||||||
((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING_FALLING ))
|
|
||||||
|
|
||||||
#define IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \
|
|
||||||
((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS ) || \
|
|
||||||
((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS ) || \
|
|
||||||
((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS ))
|
|
||||||
|
|
||||||
#define IS_LPTIM_UPDATE_MODE(__MODE__) (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \
|
|
||||||
((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD))
|
|
||||||
|
|
||||||
#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
|
|
||||||
((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))
|
|
||||||
|
|
||||||
#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFFUL)
|
|
||||||
|
|
||||||
#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFUL)
|
|
||||||
|
|
||||||
#define IS_LPTIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0x0000FFFFUL)
|
|
||||||
|
|
||||||
#define IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFFUL)
|
|
||||||
|
|
||||||
#define IS_LPTIM_REPETITION(__REPETITION__) ((__REPETITION__) <= 0x000000FFUL)
|
|
||||||
|
|
||||||
#define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \
|
|
||||||
((((__INSTANCE__) == LPTIM1) && \
|
|
||||||
(((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \
|
|
||||||
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1))) \
|
|
||||||
|| \
|
|
||||||
(((__INSTANCE__) == LPTIM2) && \
|
|
||||||
(((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \
|
|
||||||
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) || \
|
|
||||||
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP2) || \
|
|
||||||
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1_COMP2))) \
|
|
||||||
|| \
|
|
||||||
(((__INSTANCE__) == LPTIM3) && \
|
|
||||||
(((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \
|
|
||||||
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) || \
|
|
||||||
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP2) || \
|
|
||||||
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1_COMP2))))
|
|
||||||
|
|
||||||
#define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__) \
|
|
||||||
(((__INSTANCE__) == LPTIM1) && \
|
|
||||||
(((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) || \
|
|
||||||
((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2)))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private functions ---------------------------------------------------------*/
|
|
||||||
/** @defgroup LPTIM_Private_Functions LPTIM Private Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#endif /* LPTIM1 || LPTIM2 || LPTIM3 */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* STM32WLxx_HAL_LPTIM_H */
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,567 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32wlxx_hal_pka.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief Header file of PKA HAL module.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
|
||||||
* All rights reserved.</center></h2>
|
|
||||||
*
|
|
||||||
* This software component is licensed by ST under BSD 3-Clause license,
|
|
||||||
* the "License"; You may not use this file except in compliance with the
|
|
||||||
* License. You may obtain a copy of the License at:
|
|
||||||
* opensource.org/licenses/BSD-3-Clause
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef STM32WLxx_HAL_PKA_H
|
|
||||||
#define STM32WLxx_HAL_PKA_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32wlxx_hal_def.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32WLxx_HAL_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#if defined(PKA) && defined(HAL_PKA_MODULE_ENABLED)
|
|
||||||
|
|
||||||
/** @addtogroup PKA
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
/** @defgroup PKA_Exported_Types PKA Exported Types
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup HAL_state_structure_definition HAL state structure definition
|
|
||||||
* @brief HAL State structures definition
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
HAL_PKA_STATE_RESET = 0x00U, /*!< PKA not yet initialized or disabled */
|
|
||||||
HAL_PKA_STATE_READY = 0x01U, /*!< PKA initialized and ready for use */
|
|
||||||
HAL_PKA_STATE_BUSY = 0x02U, /*!< PKA internal processing is ongoing */
|
|
||||||
HAL_PKA_STATE_ERROR = 0x03U, /*!< PKA error state */
|
|
||||||
}
|
|
||||||
HAL_PKA_StateTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
|
|
||||||
/** @defgroup HAL_callback_id HAL callback ID enumeration
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
HAL_PKA_OPERATION_COMPLETE_CB_ID = 0x00U, /*!< PKA End of operation callback ID */
|
|
||||||
HAL_PKA_ERROR_CB_ID = 0x01U, /*!< PKA Error callback ID */
|
|
||||||
HAL_PKA_MSPINIT_CB_ID = 0x02U, /*!< PKA Msp Init callback ID */
|
|
||||||
HAL_PKA_MSPDEINIT_CB_ID = 0x03U /*!< PKA Msp DeInit callback ID */
|
|
||||||
} HAL_PKA_CallbackIDTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
|
|
||||||
|
|
||||||
/** @defgroup PKA_Error_Code_definition PKA Error Code definition
|
|
||||||
* @brief PKA Error Code definition
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define HAL_PKA_ERROR_NONE (0x00000000U)
|
|
||||||
#define HAL_PKA_ERROR_ADDRERR (0x00000001U)
|
|
||||||
#define HAL_PKA_ERROR_RAMERR (0x00000002U)
|
|
||||||
#define HAL_PKA_ERROR_TIMEOUT (0x00000004U)
|
|
||||||
#define HAL_PKA_ERROR_OPERATION (0x00000008U)
|
|
||||||
#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
|
|
||||||
#define HAL_PKA_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */
|
|
||||||
#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup PKA_handle_Structure_definition PKA handle Structure definition
|
|
||||||
* @brief PKA handle Structure definition
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
|
|
||||||
typedef struct __PKA_HandleTypeDef
|
|
||||||
#else
|
|
||||||
typedef struct
|
|
||||||
#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
|
|
||||||
{
|
|
||||||
PKA_TypeDef *Instance; /*!< Register base address */
|
|
||||||
__IO HAL_PKA_StateTypeDef State; /*!< PKA state */
|
|
||||||
__IO uint32_t ErrorCode; /*!< PKA Error code */
|
|
||||||
#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
|
|
||||||
void (* OperationCpltCallback)(struct __PKA_HandleTypeDef *hpka); /*!< PKA End of operation callback */
|
|
||||||
void (* ErrorCallback)(struct __PKA_HandleTypeDef *hpka); /*!< PKA Error callback */
|
|
||||||
void (* MspInitCallback)(struct __PKA_HandleTypeDef *hpka); /*!< PKA Msp Init callback */
|
|
||||||
void (* MspDeInitCallback)(struct __PKA_HandleTypeDef *hpka); /*!< PKA Msp DeInit callback */
|
|
||||||
#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
|
|
||||||
} PKA_HandleTypeDef;
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
|
|
||||||
/** @defgroup PKA_Callback_definition PKA Callback pointer definition
|
|
||||||
* @brief PKA Callback pointer definition
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
typedef void (*pPKA_CallbackTypeDef)(PKA_HandleTypeDef *hpka); /*!< Pointer to a PKA callback function */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
|
|
||||||
/** @defgroup PKA_Operation PKA operation structure definition
|
|
||||||
* @brief Input and output data definition
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t scalarMulSize; /*!< Number of element in scalarMul array */
|
|
||||||
uint32_t modulusSize; /*!< Number of element in modulus, coefA, pointX and pointY arrays */
|
|
||||||
uint32_t coefSign; /*!< Curve coefficient a sign */
|
|
||||||
const uint8_t *coefA; /*!< Pointer to curve coefficient |a| (Array of modulusSize elements) */
|
|
||||||
const uint8_t *modulus; /*!< Pointer to curve modulus value p (Array of modulusSize elements) */
|
|
||||||
const uint8_t *pointX; /*!< Pointer to point P coordinate xP (Array of modulusSize elements) */
|
|
||||||
const uint8_t *pointY; /*!< Pointer to point P coordinate yP (Array of modulusSize elements) */
|
|
||||||
const uint8_t *scalarMul; /*!< Pointer to scalar multiplier k (Array of scalarMulSize elements) */
|
|
||||||
const uint32_t *pMontgomeryParam; /*!< Pointer to Montgomery parameter (Array of modulusSize/4 elements) */
|
|
||||||
} PKA_ECCMulFastModeInTypeDef;
|
|
||||||
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t scalarMulSize; /*!< Number of element in scalarMul array */
|
|
||||||
uint32_t modulusSize; /*!< Number of element in modulus, coefA, pointX and pointY arrays */
|
|
||||||
uint32_t coefSign; /*!< Curve coefficient a sign */
|
|
||||||
const uint8_t *coefA; /*!< Pointer to curve coefficient |a| (Array of modulusSize elements) */
|
|
||||||
const uint8_t *modulus; /*!< Pointer to curve modulus value p (Array of modulusSize elements) */
|
|
||||||
const uint8_t *pointX; /*!< Pointer to point P coordinate xP (Array of modulusSize elements) */
|
|
||||||
const uint8_t *pointY; /*!< Pointer to point P coordinate yP (Array of modulusSize elements) */
|
|
||||||
const uint8_t *scalarMul; /*!< Pointer to scalar multiplier k (Array of scalarMulSize elements) */
|
|
||||||
} PKA_ECCMulInTypeDef;
|
|
||||||
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t modulusSize; /*!< Number of element in coefA, coefB, modulus, pointX and pointY arrays */
|
|
||||||
uint32_t coefSign; /*!< Curve coefficient a sign */
|
|
||||||
const uint8_t *coefA; /*!< Pointer to curve coefficient |a| (Array of modulusSize elements) */
|
|
||||||
const uint8_t *coefB; /*!< Pointer to curve coefficient b (Array of modulusSize elements) */
|
|
||||||
const uint8_t *modulus; /*!< Pointer to curve modulus value p (Array of modulusSize elements) */
|
|
||||||
const uint8_t *pointX; /*!< Pointer to point P coordinate xP (Array of modulusSize elements) */
|
|
||||||
const uint8_t *pointY; /*!< Pointer to point P coordinate yP (Array of modulusSize elements) */
|
|
||||||
} PKA_PointCheckInTypeDef;
|
|
||||||
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t size; /*!< Number of element in popA array */
|
|
||||||
const uint8_t *pOpDp; /*!< Pointer to operand dP (Array of size/2 elements) */
|
|
||||||
const uint8_t *pOpDq; /*!< Pointer to operand dQ (Array of size/2 elements) */
|
|
||||||
const uint8_t *pOpQinv; /*!< Pointer to operand qinv (Array of size/2 elements) */
|
|
||||||
const uint8_t *pPrimeP; /*!< Pointer to prime p (Array of size/2 elements) */
|
|
||||||
const uint8_t *pPrimeQ; /*!< Pointer to prime Q (Array of size/2 elements) */
|
|
||||||
const uint8_t *popA; /*!< Pointer to operand A (Array of size elements) */
|
|
||||||
} PKA_RSACRTExpInTypeDef;
|
|
||||||
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t primeOrderSize; /*!< Number of element in primeOrder array */
|
|
||||||
uint32_t modulusSize; /*!< Number of element in modulus array */
|
|
||||||
uint32_t coefSign; /*!< Curve coefficient a sign */
|
|
||||||
const uint8_t *coef; /*!< Pointer to curve coefficient |a| (Array of modulusSize elements) */
|
|
||||||
const uint8_t *modulus; /*!< Pointer to curve modulus value p (Array of modulusSize elements) */
|
|
||||||
const uint8_t *basePointX; /*!< Pointer to curve base point xG (Array of modulusSize elements) */
|
|
||||||
const uint8_t *basePointY; /*!< Pointer to curve base point yG (Array of modulusSize elements) */
|
|
||||||
const uint8_t *pPubKeyCurvePtX; /*!< Pointer to public-key curve point xQ (Array of modulusSize elements) */
|
|
||||||
const uint8_t *pPubKeyCurvePtY; /*!< Pointer to public-key curve point yQ (Array of modulusSize elements) */
|
|
||||||
const uint8_t *RSign; /*!< Pointer to signature part r (Array of primeOrderSize elements) */
|
|
||||||
const uint8_t *SSign; /*!< Pointer to signature part s (Array of primeOrderSize elements) */
|
|
||||||
const uint8_t *hash; /*!< Pointer to hash of the message e (Array of primeOrderSize elements) */
|
|
||||||
const uint8_t *primeOrder; /*!< Pointer to order of the curve n (Array of primeOrderSize elements) */
|
|
||||||
} PKA_ECDSAVerifInTypeDef;
|
|
||||||
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t primeOrderSize; /*!< Number of element in primeOrder array */
|
|
||||||
uint32_t modulusSize; /*!< Number of element in modulus array */
|
|
||||||
uint32_t coefSign; /*!< Curve coefficient a sign */
|
|
||||||
const uint8_t *coef; /*!< Pointer to curve coefficient |a| (Array of modulusSize elements) */
|
|
||||||
const uint8_t *modulus; /*!< Pointer to curve modulus value p (Array of modulusSize elements) */
|
|
||||||
const uint8_t *integer; /*!< Pointer to random integer k (Array of primeOrderSize elements) */
|
|
||||||
const uint8_t *basePointX; /*!< Pointer to curve base point xG (Array of modulusSize elements) */
|
|
||||||
const uint8_t *basePointY; /*!< Pointer to curve base point yG (Array of modulusSize elements) */
|
|
||||||
const uint8_t *hash; /*!< Pointer to hash of the message (Array of primeOrderSize elements) */
|
|
||||||
const uint8_t *privateKey; /*!< Pointer to private key d (Array of primeOrderSize elements) */
|
|
||||||
const uint8_t *primeOrder; /*!< Pointer to order of the curve n (Array of primeOrderSize elements) */
|
|
||||||
} PKA_ECDSASignInTypeDef;
|
|
||||||
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint8_t *RSign; /*!< Pointer to signature part r (Array of modulusSize elements) */
|
|
||||||
uint8_t *SSign; /*!< Pointer to signature part s (Array of modulusSize elements) */
|
|
||||||
} PKA_ECDSASignOutTypeDef;
|
|
||||||
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint8_t *ptX; /*!< Pointer to point P coordinate xP (Array of modulusSize elements) */
|
|
||||||
uint8_t *ptY; /*!< Pointer to point P coordinate yP (Array of modulusSize elements) */
|
|
||||||
} PKA_ECDSASignOutExtParamTypeDef, PKA_ECCMulOutTypeDef;
|
|
||||||
|
|
||||||
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t expSize; /*!< Number of element in pExp array */
|
|
||||||
uint32_t OpSize; /*!< Number of element in pOp1 and pMod arrays */
|
|
||||||
const uint8_t *pExp; /*!< Pointer to Exponent (Array of expSize elements) */
|
|
||||||
const uint8_t *pOp1; /*!< Pointer to Operand (Array of OpSize elements) */
|
|
||||||
const uint8_t *pMod; /*!< Pointer to modulus (Array of OpSize elements) */
|
|
||||||
} PKA_ModExpInTypeDef;
|
|
||||||
|
|
||||||
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t expSize; /*!< Number of element in pExp and pMontgomeryParam arrays */
|
|
||||||
uint32_t OpSize; /*!< Number of element in pOp1 and pMod arrays */
|
|
||||||
const uint8_t *pExp; /*!< Pointer to Exponent (Array of expSize elements) */
|
|
||||||
const uint8_t *pOp1; /*!< Pointer to Operand (Array of OpSize elements) */
|
|
||||||
const uint8_t *pMod; /*!< Pointer to modulus (Array of OpSize elements) */
|
|
||||||
const uint32_t *pMontgomeryParam; /*!< Pointer to Montgomery parameter (Array of expSize/4 elements) */
|
|
||||||
} PKA_ModExpFastModeInTypeDef;
|
|
||||||
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t size; /*!< Number of element in pOp1 array */
|
|
||||||
const uint8_t *pOp1; /*!< Pointer to Operand (Array of size elements) */
|
|
||||||
} PKA_MontgomeryParamInTypeDef;
|
|
||||||
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t size; /*!< Number of element in pOp1 and pOp2 arrays */
|
|
||||||
const uint32_t *pOp1; /*!< Pointer to Operand 1 (Array of size elements) */
|
|
||||||
const uint32_t *pOp2; /*!< Pointer to Operand 2 (Array of size elements) */
|
|
||||||
} PKA_AddInTypeDef, PKA_SubInTypeDef, PKA_MulInTypeDef, PKA_CmpInTypeDef;
|
|
||||||
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t size; /*!< Number of element in pOp1 array */
|
|
||||||
const uint32_t *pOp1; /*!< Pointer to Operand 1 (Array of size elements) */
|
|
||||||
const uint8_t *pMod; /*!< Pointer to modulus value n (Array of size*4 elements) */
|
|
||||||
} PKA_ModInvInTypeDef;
|
|
||||||
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t OpSize; /*!< Number of element in pOp1 array */
|
|
||||||
uint32_t modSize; /*!< Number of element in pMod array */
|
|
||||||
const uint32_t *pOp1; /*!< Pointer to Operand 1 (Array of OpSize elements) */
|
|
||||||
const uint8_t *pMod; /*!< Pointer to modulus value n (Array of modSize elements) */
|
|
||||||
} PKA_ModRedInTypeDef;
|
|
||||||
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t size; /*!< Number of element in pOp1 and pOp2 arrays */
|
|
||||||
const uint32_t *pOp1; /*!< Pointer to Operand 1 (Array of size elements) */
|
|
||||||
const uint32_t *pOp2; /*!< Pointer to Operand 2 (Array of size elements) */
|
|
||||||
const uint8_t *pOp3; /*!< Pointer to Operand 3 (Array of size*4 elements) */
|
|
||||||
} PKA_ModAddInTypeDef, PKA_ModSubInTypeDef, PKA_MontgomeryMulInTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
|
||||||
/** @defgroup PKA_Exported_Constants PKA Exported Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup PKA_Mode PKA mode
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define PKA_MODE_MONTGOMERY_PARAM (0x00000001U)
|
|
||||||
#define PKA_MODE_MODULAR_EXP (0x00000000U)
|
|
||||||
#define PKA_MODE_MODULAR_EXP_FAST_MODE (0x00000002U)
|
|
||||||
#define PKA_MODE_ECC_MUL (0x00000020U)
|
|
||||||
#define PKA_MODE_ECC_MUL_FAST_MODE (0x00000022U)
|
|
||||||
#define PKA_MODE_ECDSA_SIGNATURE (0x00000024U)
|
|
||||||
#define PKA_MODE_ECDSA_VERIFICATION (0x00000026U)
|
|
||||||
#define PKA_MODE_POINT_CHECK (0x00000028U)
|
|
||||||
#define PKA_MODE_RSA_CRT_EXP (0x00000007U)
|
|
||||||
#define PKA_MODE_MODULAR_INV (0x00000008U)
|
|
||||||
#define PKA_MODE_ARITHMETIC_ADD (0x00000009U)
|
|
||||||
#define PKA_MODE_ARITHMETIC_SUB (0x0000000AU)
|
|
||||||
#define PKA_MODE_ARITHMETIC_MUL (0x0000000BU)
|
|
||||||
#define PKA_MODE_COMPARISON (0x0000000CU)
|
|
||||||
#define PKA_MODE_MODULAR_RED (0x0000000DU)
|
|
||||||
#define PKA_MODE_MODULAR_ADD (0x0000000EU)
|
|
||||||
#define PKA_MODE_MODULAR_SUB (0x0000000FU)
|
|
||||||
#define PKA_MODE_MONTGOMERY_MUL (0x00000010U)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup PKA_Interrupt_configuration_definition PKA Interrupt configuration definition
|
|
||||||
* @brief PKA Interrupt definition
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define PKA_IT_PROCEND PKA_CR_PROCENDIE
|
|
||||||
#define PKA_IT_ADDRERR PKA_CR_ADDRERRIE
|
|
||||||
#define PKA_IT_RAMERR PKA_CR_RAMERRIE
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup PKA_Flag_definition PKA Flag definition
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define PKA_FLAG_PROCEND PKA_SR_PROCENDF
|
|
||||||
#define PKA_FLAG_ADDRERR PKA_SR_ADDRERRF
|
|
||||||
#define PKA_FLAG_RAMERR PKA_SR_RAMERRF
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported macros -----------------------------------------------------------*/
|
|
||||||
|
|
||||||
/** @defgroup PKA_Exported_Macros PKA Exported Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @brief Reset PKA handle state.
|
|
||||||
* @param __HANDLE__ specifies the PKA Handle
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
|
|
||||||
#define __HAL_PKA_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
|
||||||
(__HANDLE__)->State = HAL_PKA_STATE_RESET; \
|
|
||||||
(__HANDLE__)->MspInitCallback = NULL; \
|
|
||||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
|
||||||
} while(0)
|
|
||||||
#else
|
|
||||||
#define __HAL_PKA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PKA_STATE_RESET)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/** @brief Enable the specified PKA interrupt.
|
|
||||||
* @param __HANDLE__ specifies the PKA Handle
|
|
||||||
* @param __INTERRUPT__ specifies the interrupt source to enable.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg @ref PKA_IT_PROCEND End Of Operation interrupt enable
|
|
||||||
* @arg @ref PKA_IT_ADDRERR Address error interrupt enable
|
|
||||||
* @arg @ref PKA_IT_RAMERR RAM error interrupt enable
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_PKA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
|
|
||||||
|
|
||||||
/** @brief Disable the specified PKA interrupt.
|
|
||||||
* @param __HANDLE__ specifies the PKA Handle
|
|
||||||
* @param __INTERRUPT__ specifies the interrupt source to disable.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg @ref PKA_IT_PROCEND End Of Operation interrupt enable
|
|
||||||
* @arg @ref PKA_IT_ADDRERR Address error interrupt enable
|
|
||||||
* @arg @ref PKA_IT_RAMERR RAM error interrupt enable
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_PKA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= (~(__INTERRUPT__)))
|
|
||||||
|
|
||||||
/** @brief Check whether the specified PKA interrupt source is enabled or not.
|
|
||||||
* @param __HANDLE__ specifies the PKA Handle
|
|
||||||
* @param __INTERRUPT__ specifies the PKA interrupt source to check.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg @ref PKA_IT_PROCEND End Of Operation interrupt enable
|
|
||||||
* @arg @ref PKA_IT_ADDRERR Address error interrupt enable
|
|
||||||
* @arg @ref PKA_IT_RAMERR RAM error interrupt enable
|
|
||||||
* @retval The new state of __INTERRUPT__ (SET or RESET)
|
|
||||||
*/
|
|
||||||
#define __HAL_PKA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
|
||||||
|
|
||||||
/** @brief Check whether the specified PKA flag is set or not.
|
|
||||||
* @param __HANDLE__ specifies the PKA Handle
|
|
||||||
* @param __FLAG__ specifies the flag to check.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg @ref PKA_FLAG_PROCEND End Of Operation
|
|
||||||
* @arg @ref PKA_FLAG_ADDRERR Address error
|
|
||||||
* @arg @ref PKA_FLAG_RAMERR RAM error
|
|
||||||
* @retval The new state of __FLAG__ (SET or RESET)
|
|
||||||
*/
|
|
||||||
#define __HAL_PKA_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
|
|
||||||
|
|
||||||
/** @brief Clear the PKA pending flags which are cleared by writing 1 in a specific bit.
|
|
||||||
* @param __HANDLE__ specifies the PKA Handle
|
|
||||||
* @param __FLAG__ specifies the flag to clear.
|
|
||||||
* This parameter can be any combination of the following values:
|
|
||||||
* @arg @ref PKA_FLAG_PROCEND End Of Operation
|
|
||||||
* @arg @ref PKA_FLAG_ADDRERR Address error
|
|
||||||
* @arg @ref PKA_FLAG_RAMERR RAM error
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_PKA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__))
|
|
||||||
|
|
||||||
/** @brief Enable the specified PKA peripheral.
|
|
||||||
* @param __HANDLE__ specifies the PKA Handle
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_PKA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR, PKA_CR_EN))
|
|
||||||
|
|
||||||
/** @brief Disable the specified PKA peripheral.
|
|
||||||
* @param __HANDLE__ specifies the PKA Handle
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_PKA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR, PKA_CR_EN))
|
|
||||||
|
|
||||||
/** @brief Start a PKA operation.
|
|
||||||
* @param __HANDLE__ specifies the PKA Handle
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_PKA_START(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR, PKA_CR_START))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private macros --------------------------------------------------------*/
|
|
||||||
/* Exported functions --------------------------------------------------------*/
|
|
||||||
/** @addtogroup PKA_Exported_Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup PKA_Exported_Functions_Group1
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Initialization and de-initialization functions *****************************/
|
|
||||||
HAL_StatusTypeDef HAL_PKA_Init(PKA_HandleTypeDef *hpka);
|
|
||||||
HAL_StatusTypeDef HAL_PKA_DeInit(PKA_HandleTypeDef *hpka);
|
|
||||||
void HAL_PKA_MspInit(PKA_HandleTypeDef *hpka);
|
|
||||||
void HAL_PKA_MspDeInit(PKA_HandleTypeDef *hpka);
|
|
||||||
|
|
||||||
#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
|
|
||||||
/* Callbacks Register/UnRegister functions ***********************************/
|
|
||||||
HAL_StatusTypeDef HAL_PKA_RegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_CallbackIDTypeDef CallbackID, pPKA_CallbackTypeDef pCallback);
|
|
||||||
HAL_StatusTypeDef HAL_PKA_UnRegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_CallbackIDTypeDef CallbackID);
|
|
||||||
#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup PKA_Exported_Functions_Group2
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* IO operation functions *****************************************************/
|
|
||||||
/* High Level Functions *******************************************************/
|
|
||||||
HAL_StatusTypeDef HAL_PKA_ModExp(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in, uint32_t Timeout);
|
|
||||||
HAL_StatusTypeDef HAL_PKA_ModExp_IT(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in);
|
|
||||||
HAL_StatusTypeDef HAL_PKA_ModExpFastMode(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in, uint32_t Timeout);
|
|
||||||
HAL_StatusTypeDef HAL_PKA_ModExpFastMode_IT(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in);
|
|
||||||
void HAL_PKA_ModExp_GetResult(PKA_HandleTypeDef *hpka, uint8_t *pRes);
|
|
||||||
|
|
||||||
HAL_StatusTypeDef HAL_PKA_ECDSASign(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in, uint32_t Timeout);
|
|
||||||
HAL_StatusTypeDef HAL_PKA_ECDSASign_IT(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in);
|
|
||||||
void HAL_PKA_ECDSASign_GetResult(PKA_HandleTypeDef *hpka, PKA_ECDSASignOutTypeDef *out, PKA_ECDSASignOutExtParamTypeDef *outExt);
|
|
||||||
|
|
||||||
HAL_StatusTypeDef HAL_PKA_ECDSAVerif(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in, uint32_t Timeout);
|
|
||||||
HAL_StatusTypeDef HAL_PKA_ECDSAVerif_IT(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in);
|
|
||||||
uint32_t HAL_PKA_ECDSAVerif_IsValidSignature(PKA_HandleTypeDef const *const hpka);
|
|
||||||
|
|
||||||
HAL_StatusTypeDef HAL_PKA_RSACRTExp(PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in, uint32_t Timeout);
|
|
||||||
HAL_StatusTypeDef HAL_PKA_RSACRTExp_IT(PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in);
|
|
||||||
void HAL_PKA_RSACRTExp_GetResult(PKA_HandleTypeDef *hpka, uint8_t *pRes);
|
|
||||||
|
|
||||||
HAL_StatusTypeDef HAL_PKA_PointCheck(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in, uint32_t Timeout);
|
|
||||||
HAL_StatusTypeDef HAL_PKA_PointCheck_IT(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in);
|
|
||||||
uint32_t HAL_PKA_PointCheck_IsOnCurve(PKA_HandleTypeDef const *const hpka);
|
|
||||||
|
|
||||||
HAL_StatusTypeDef HAL_PKA_ECCMul(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in, uint32_t Timeout);
|
|
||||||
HAL_StatusTypeDef HAL_PKA_ECCMul_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in);
|
|
||||||
HAL_StatusTypeDef HAL_PKA_ECCMulFastMode(PKA_HandleTypeDef *hpka, PKA_ECCMulFastModeInTypeDef *in, uint32_t Timeout);
|
|
||||||
HAL_StatusTypeDef HAL_PKA_ECCMulFastMode_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulFastModeInTypeDef *in);
|
|
||||||
void HAL_PKA_ECCMul_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCMulOutTypeDef *out);
|
|
||||||
|
|
||||||
HAL_StatusTypeDef HAL_PKA_Add(PKA_HandleTypeDef *hpka, PKA_AddInTypeDef *in, uint32_t Timeout);
|
|
||||||
HAL_StatusTypeDef HAL_PKA_Add_IT(PKA_HandleTypeDef *hpka, PKA_AddInTypeDef *in);
|
|
||||||
HAL_StatusTypeDef HAL_PKA_Sub(PKA_HandleTypeDef *hpka, PKA_SubInTypeDef *in, uint32_t Timeout);
|
|
||||||
HAL_StatusTypeDef HAL_PKA_Sub_IT(PKA_HandleTypeDef *hpka, PKA_SubInTypeDef *in);
|
|
||||||
HAL_StatusTypeDef HAL_PKA_Cmp(PKA_HandleTypeDef *hpka, PKA_CmpInTypeDef *in, uint32_t Timeout);
|
|
||||||
HAL_StatusTypeDef HAL_PKA_Cmp_IT(PKA_HandleTypeDef *hpka, PKA_CmpInTypeDef *in);
|
|
||||||
HAL_StatusTypeDef HAL_PKA_Mul(PKA_HandleTypeDef *hpka, PKA_MulInTypeDef *in, uint32_t Timeout);
|
|
||||||
HAL_StatusTypeDef HAL_PKA_Mul_IT(PKA_HandleTypeDef *hpka, PKA_MulInTypeDef *in);
|
|
||||||
HAL_StatusTypeDef HAL_PKA_ModAdd(PKA_HandleTypeDef *hpka, PKA_ModAddInTypeDef *in, uint32_t Timeout);
|
|
||||||
HAL_StatusTypeDef HAL_PKA_ModAdd_IT(PKA_HandleTypeDef *hpka, PKA_ModAddInTypeDef *in);
|
|
||||||
HAL_StatusTypeDef HAL_PKA_ModSub(PKA_HandleTypeDef *hpka, PKA_ModSubInTypeDef *in, uint32_t Timeout);
|
|
||||||
HAL_StatusTypeDef HAL_PKA_ModSub_IT(PKA_HandleTypeDef *hpka, PKA_ModSubInTypeDef *in);
|
|
||||||
HAL_StatusTypeDef HAL_PKA_ModInv(PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in, uint32_t Timeout);
|
|
||||||
HAL_StatusTypeDef HAL_PKA_ModInv_IT(PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in);
|
|
||||||
HAL_StatusTypeDef HAL_PKA_ModRed(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in, uint32_t Timeout);
|
|
||||||
HAL_StatusTypeDef HAL_PKA_ModRed_IT(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in);
|
|
||||||
HAL_StatusTypeDef HAL_PKA_MontgomeryMul(PKA_HandleTypeDef *hpka, PKA_MontgomeryMulInTypeDef *in, uint32_t Timeout);
|
|
||||||
HAL_StatusTypeDef HAL_PKA_MontgomeryMul_IT(PKA_HandleTypeDef *hpka, PKA_MontgomeryMulInTypeDef *in);
|
|
||||||
void HAL_PKA_Arithmetic_GetResult(PKA_HandleTypeDef *hpka, uint32_t *pRes);
|
|
||||||
|
|
||||||
HAL_StatusTypeDef HAL_PKA_MontgomeryParam(PKA_HandleTypeDef *hpka, PKA_MontgomeryParamInTypeDef *in, uint32_t Timeout);
|
|
||||||
HAL_StatusTypeDef HAL_PKA_MontgomeryParam_IT(PKA_HandleTypeDef *hpka, PKA_MontgomeryParamInTypeDef *in);
|
|
||||||
void HAL_PKA_MontgomeryParam_GetResult(PKA_HandleTypeDef *hpka, uint32_t *pRes);
|
|
||||||
|
|
||||||
|
|
||||||
HAL_StatusTypeDef HAL_PKA_Abort(PKA_HandleTypeDef *hpka);
|
|
||||||
void HAL_PKA_RAMReset(PKA_HandleTypeDef *hpka);
|
|
||||||
void HAL_PKA_OperationCpltCallback(PKA_HandleTypeDef *hpka);
|
|
||||||
void HAL_PKA_ErrorCallback(PKA_HandleTypeDef *hpka);
|
|
||||||
void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup PKA_Exported_Functions_Group3
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Peripheral State and Error functions ***************************************/
|
|
||||||
HAL_PKA_StateTypeDef HAL_PKA_GetState(PKA_HandleTypeDef *hpka);
|
|
||||||
uint32_t HAL_PKA_GetError(PKA_HandleTypeDef *hpka);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#endif /* defined(PKA) && defined(HAL_PKA_MODULE_ENABLED) */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* STM32WLxx_HAL_PKA_H */
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,585 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32wlxx_hal_pwr.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief Header file of PWR HAL module.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
|
||||||
* All rights reserved.</center></h2>
|
|
||||||
*
|
|
||||||
* This software component is licensed by ST under BSD 3-Clause license,
|
|
||||||
* the "License"; You may not use this file except in compliance with the
|
|
||||||
* License. You may obtain a copy of the License at:
|
|
||||||
* opensource.org/licenses/BSD-3-Clause
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef STM32WLxx_HAL_PWR_H
|
|
||||||
#define STM32WLxx_HAL_PWR_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32wlxx_hal_def.h"
|
|
||||||
|
|
||||||
/* Include low level driver */
|
|
||||||
#include "stm32wlxx_ll_pwr.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32WLxx_HAL_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup PWR PWR
|
|
||||||
* @brief PWR HAL module driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
/** @defgroup PWR_Exported_Types PWR Exported Types
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief PWR PVD configuration structure definition
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
|
|
||||||
This parameter can be a value of @ref PWR_PVD_detection_level. */
|
|
||||||
|
|
||||||
uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
|
|
||||||
This parameter can be a value of @ref PWR_PVD_Mode. */
|
|
||||||
} PWR_PVDTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
|
||||||
/** @defgroup PWR_Exported_Constants PWR Exported Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup PWR_PVD_detection_level Power Voltage Detector Level selection
|
|
||||||
* @note Refer datasheet for selection voltage value
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define PWR_PVDLEVEL_0 (0x00000000UL) /*!< PVD threshold around 2.0 V */
|
|
||||||
#define PWR_PVDLEVEL_1 ( PWR_CR2_PLS_0) /*!< PVD threshold around 2.2 V */
|
|
||||||
#define PWR_PVDLEVEL_2 ( PWR_CR2_PLS_1 ) /*!< PVD threshold around 2.4 V */
|
|
||||||
#define PWR_PVDLEVEL_3 ( PWR_CR2_PLS_1 | PWR_CR2_PLS_0) /*!< PVD threshold around 2.5 V */
|
|
||||||
#define PWR_PVDLEVEL_4 (PWR_CR2_PLS_2 ) /*!< PVD threshold around 2.6 V */
|
|
||||||
#define PWR_PVDLEVEL_5 (PWR_CR2_PLS_2 | PWR_CR2_PLS_0) /*!< PVD threshold around 2.8 V */
|
|
||||||
#define PWR_PVDLEVEL_6 (PWR_CR2_PLS_2 | PWR_CR2_PLS_1 ) /*!< PVD threshold around 2.9 V */
|
|
||||||
#define PWR_PVDLEVEL_7 (PWR_CR2_PLS_2 | PWR_CR2_PLS_1 | PWR_CR2_PLS_0) /*!< External input analog voltage (compared internally to VREFINT) */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup PWR_PVD_Mode PWR PVD interrupt and event mode
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Note: On STM32WL series, power PVD event is not available on EXTI lines */
|
|
||||||
/* (only interruption is available through EXTI line 16). */
|
|
||||||
#define PWR_PVD_MODE_NORMAL (0x00000000UL) /*!< PVD in polling mode (PVD flag update without interruption) */
|
|
||||||
|
|
||||||
#define PWR_PVD_MODE_IT_RISING (PVD_MODE_IT | PVD_RISING_EDGE) /*!< PVD in interrupt mode with rising edge trigger detection */
|
|
||||||
#define PWR_PVD_MODE_IT_FALLING (PVD_MODE_IT | PVD_FALLING_EDGE) /*!< PVD in interrupt mode with falling edge trigger detection */
|
|
||||||
#define PWR_PVD_MODE_IT_RISING_FALLING (PVD_MODE_IT | PVD_RISING_FALLING_EDGE) /*!< PVD in interrupt mode with rising/falling edge trigger detection */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup PWR_Low_Power_Mode_Selection PWR Low Power Mode Selection
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#ifdef CORE_CM0PLUS
|
|
||||||
#define PWR_LOWPOWERMODE_STOP0 (0x00000000UL) /*!< Stop 0: Stop mode with main regulator */
|
|
||||||
#define PWR_LOWPOWERMODE_STOP1 (PWR_C2CR1_LPMS_0) /*!< Stop 1: Stop mode with low power regulator */
|
|
||||||
#define PWR_LOWPOWERMODE_STOP2 (PWR_C2CR1_LPMS_1) /*!< Stop 2: Stop mode with low power regulator and VDD12I interruptible digital core domain supply OFF (less peripherals activated than low power mode stop 1 to reduce power consumption)*/
|
|
||||||
#define PWR_LOWPOWERMODE_STANDBY (PWR_C2CR1_LPMS_0 | PWR_C2CR1_LPMS_1) /*!< Standby mode */
|
|
||||||
#define PWR_LOWPOWERMODE_SHUTDOWN (PWR_C2CR1_LPMS_2 | PWR_C2CR1_LPMS_1 | PWR_C2CR1_LPMS_0) /*!< Shutdown mode */
|
|
||||||
#else
|
|
||||||
#define PWR_LOWPOWERMODE_STOP0 (0x00000000UL) /*!< Stop 0: Stop mode with main regulator */
|
|
||||||
#define PWR_LOWPOWERMODE_STOP1 (PWR_CR1_LPMS_0) /*!< Stop 1: Stop mode with low power regulator */
|
|
||||||
#define PWR_LOWPOWERMODE_STOP2 (PWR_CR1_LPMS_1) /*!< Stop 2: Stop mode with low power regulator and VDD12I interruptible digital core domain supply OFF (less peripherals activated than low power mode stop 1 to reduce power consumption)*/
|
|
||||||
#define PWR_LOWPOWERMODE_STANDBY (PWR_CR1_LPMS_0 | PWR_CR1_LPMS_1) /*!< Standby mode */
|
|
||||||
#define PWR_LOWPOWERMODE_SHUTDOWN (PWR_CR1_LPMS_2 | PWR_CR1_LPMS_1 | PWR_CR1_LPMS_0) /*!< Shutdown mode */
|
|
||||||
#endif
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR regulator mode
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define PWR_MAINREGULATOR_ON (0x00000000UL) /*!< Regulator in main mode */
|
|
||||||
#define PWR_LOWPOWERREGULATOR_ON (PWR_CR1_LPR) /*!< Regulator in low-power mode */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) /*!< Wait For Interruption instruction to enter Sleep mode */
|
|
||||||
#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) /*!< Wait For Event instruction to enter Sleep mode */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define PWR_STOPENTRY_WFI ((uint8_t)0x01) /*!< Wait For Interruption instruction to enter Stop mode */
|
|
||||||
#define PWR_STOPENTRY_WFE ((uint8_t)0x02) /*!< Wait For Event instruction to enter Stop mode */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private constants ---------------------------------------------------------*/
|
|
||||||
/** @defgroup PWR_Private_Constants PWR Private Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup PWR_PVD_EXTI_LINE PWR PVD external interrupt line
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define PWR_EXTI_LINE_PVD (LL_EXTI_LINE_16) /*!< External interrupt line 16 Connected to the PWR PVD */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Note: On STM32WL series, power PVD event is not available on EXTI lines */
|
|
||||||
/* (only interruption is available through EXTI line 16). */
|
|
||||||
#define PVD_MODE_IT (0x00010000UL) /*!< Mask for interruption yielded by PVD threshold crossing */
|
|
||||||
#define PVD_RISING_EDGE (0x00000001UL) /*!< Mask for rising edge set as PVD trigger */
|
|
||||||
#define PVD_FALLING_EDGE (0x00000002UL) /*!< Mask for falling edge set as PVD trigger */
|
|
||||||
#define PVD_RISING_FALLING_EDGE (0x00000003UL) /*!< Mask for rising and falling edges set as PVD trigger */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported macros -----------------------------------------------------------*/
|
|
||||||
/** @defgroup PWR_Exported_Macros PWR Exported Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#if defined(DUAL_CORE)
|
|
||||||
/** @brief Check whether or not a specific PWR flag is set.
|
|
||||||
* @param __FLAG__ specifies the flag to check.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
*
|
|
||||||
* /--------------------------------SR1-------------------------------/
|
|
||||||
* @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event
|
|
||||||
* was received from the WKUP pin 1.
|
|
||||||
* @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event
|
|
||||||
* was received from the WKUP pin 2.
|
|
||||||
* @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event
|
|
||||||
* was received from the WKUP pin 3.
|
|
||||||
*
|
|
||||||
* @arg @ref PWR_FLAG_WPVD Wakeup PVD flag
|
|
||||||
*
|
|
||||||
* @arg @ref PWR_FLAG_HOLDC2I CPU2 on-Hold Interrupt Flag
|
|
||||||
* @arg @ref PWR_FLAG_WUFI Wake-Up Flag Internal. Set when a wakeup is detected on
|
|
||||||
* the internal wakeup line.
|
|
||||||
*
|
|
||||||
* @arg @ref PWR_FLAG_WRFBUSY Wake-up radio busy flag (triggered status: wake-up event or interruption occurred at least once. Can be cleared by software)
|
|
||||||
*
|
|
||||||
* /--------------------------------SR2-------------------------------/
|
|
||||||
* @arg @ref PWR_FLAG_LDORDY Main LDO ready flag
|
|
||||||
* @arg @ref PWR_FLAG_SMPSRDY SMPS ready Flag
|
|
||||||
*
|
|
||||||
* @arg @ref PWR_FLAG_REGLPS Low-power Regulator 1 started: Indicates whether the regulator
|
|
||||||
* is ready after a power-on reset or a Standby/Shutdown.
|
|
||||||
* @arg @ref PWR_FLAG_REGLPF Low-power Regulator 1 flag: Indicates whether the
|
|
||||||
* regulator 1 is in main mode or is in low-power mode.
|
|
||||||
*
|
|
||||||
* @arg @ref PWR_FLAG_REGMRS Low-power regulator (main regulator or low-power regulator used) flag.
|
|
||||||
*
|
|
||||||
* @arg @ref PWR_FLAG_FLASHRDY Flash ready flag
|
|
||||||
*
|
|
||||||
* @arg @ref PWR_FLAG_VOSF Voltage Scaling Flag. Indicates whether the regulator is ready
|
|
||||||
* in the selected voltage range or is still changing to the required voltage level.
|
|
||||||
* @arg @ref PWR_FLAG_PVDO Power Voltage Detector Output. Indicates whether VDD voltage is below
|
|
||||||
* or above the selected PVD threshold.
|
|
||||||
*
|
|
||||||
* @arg @ref PWR_FLAG_PVMO3 Peripheral Voltage Monitoring Output 3. Indicates whether VDDA voltage is
|
|
||||||
* is below or above PVM3 threshold.
|
|
||||||
*
|
|
||||||
* @arg @ref PWR_FLAG_RFEOL Indicate whether supply voltage is below radio operating level (radio "end of life").
|
|
||||||
*
|
|
||||||
* @arg @ref PWR_FLAG_RFBUSYS Radio busy signal flag (current status).
|
|
||||||
* @arg @ref PWR_FLAG_RFBUSYMS Radio busy masked signal flag (current status).
|
|
||||||
*
|
|
||||||
* @arg @ref PWR_FLAG_C2BOOTS CPU2 boot request source information flag.
|
|
||||||
*
|
|
||||||
* /----------------------------EXTSCR--------------------------/
|
|
||||||
* @arg @ref PWR_FLAG_STOP System Stop 0 or Stop1 Flag for CPU1.
|
|
||||||
* @arg @ref PWR_FLAG_STOP2 System Stop 2 Flag for CPU1.
|
|
||||||
* @arg @ref PWR_FLAG_SB System Standby Flag for CPU1.
|
|
||||||
*
|
|
||||||
* @arg @ref PWR_FLAG_C2STOP System Stop 0 or Stop1 Flag for CPU2.
|
|
||||||
* @arg @ref PWR_FLAG_C2STOP2 System Stop 2 Flag for CPU2.
|
|
||||||
* @arg @ref PWR_FLAG_C2SB System Standby Flag for CPU2.
|
|
||||||
*
|
|
||||||
* @arg @ref PWR_FLAG_C1DEEPSLEEP CPU1 DeepSleep Flag.
|
|
||||||
* @arg @ref PWR_FLAG_C2DEEPSLEEP CPU2 DeepSleep Flag.
|
|
||||||
*
|
|
||||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
|
||||||
*/
|
|
||||||
#else
|
|
||||||
/** @brief Check whether or not a specific PWR flag is set.
|
|
||||||
* @param __FLAG__ specifies the flag to check.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
*
|
|
||||||
* /--------------------------------SR1-------------------------------/
|
|
||||||
* @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event
|
|
||||||
* was received from the WKUP pin 1.
|
|
||||||
* @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event
|
|
||||||
* was received from the WKUP pin 2.
|
|
||||||
* @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event
|
|
||||||
* was received from the WKUP pin 3.
|
|
||||||
*
|
|
||||||
* @arg @ref PWR_FLAG_WPVD Wakeup PVD flag
|
|
||||||
*
|
|
||||||
* @arg @ref PWR_FLAG_WUFI Wake-Up Flag Internal. Set when a wakeup is detected on
|
|
||||||
* the internal wakeup line.
|
|
||||||
*
|
|
||||||
* @arg @ref PWR_FLAG_WRFBUSY Wake-up radio busy flag (triggered status: wake-up event or interruption occurred at least once. Can be cleared by software)
|
|
||||||
*
|
|
||||||
* /--------------------------------SR2-------------------------------/
|
|
||||||
* @arg @ref PWR_FLAG_LDORDY Main LDO ready flag
|
|
||||||
* @arg @ref PWR_FLAG_SMPSRDY SMPS ready Flag
|
|
||||||
*
|
|
||||||
* @arg @ref PWR_FLAG_REGLPS Low-power Regulator 1 started: Indicates whether the regulator
|
|
||||||
* is ready after a power-on reset or a Standby/Shutdown.
|
|
||||||
* @arg @ref PWR_FLAG_REGLPF Low-power Regulator 1 flag: Indicates whether the
|
|
||||||
* regulator 1 is in main mode or is in low-power mode.
|
|
||||||
*
|
|
||||||
* @arg @ref PWR_FLAG_REGMRS Low-power regulator (main regulator or low-power regulator used) flag.
|
|
||||||
*
|
|
||||||
* @arg @ref PWR_FLAG_FLASHRDY Flash ready flag
|
|
||||||
*
|
|
||||||
* @arg @ref PWR_FLAG_VOSF Voltage Scaling Flag. Indicates whether the regulator is ready
|
|
||||||
* in the selected voltage range or is still changing to the required voltage level.
|
|
||||||
* @arg @ref PWR_FLAG_PVDO Power Voltage Detector Output. Indicates whether VDD voltage is below
|
|
||||||
* or above the selected PVD threshold.
|
|
||||||
*
|
|
||||||
* @arg @ref PWR_FLAG_PVMO3 Peripheral Voltage Monitoring Output 3. Indicates whether VDDA voltage is
|
|
||||||
* is below or above PVM3 threshold.
|
|
||||||
*
|
|
||||||
* @arg @ref PWR_FLAG_RFEOL Indicate whether supply voltage is below radio operating level (radio "end of life").
|
|
||||||
*
|
|
||||||
* @arg @ref PWR_FLAG_RFBUSYS Radio busy signal flag (current status).
|
|
||||||
* @arg @ref PWR_FLAG_RFBUSYMS Radio busy masked signal flag (current status).
|
|
||||||
*
|
|
||||||
* /----------------------------EXTSCR--------------------------/
|
|
||||||
* @arg @ref PWR_FLAG_STOP System Stop 0 or Stop1 Flag for CPU1.
|
|
||||||
* @arg @ref PWR_FLAG_STOP2 System Stop 2 Flag for CPU1.
|
|
||||||
* @arg @ref PWR_FLAG_SB System Standby Flag for CPU1.
|
|
||||||
*
|
|
||||||
* @arg @ref PWR_FLAG_C1DEEPSLEEP CPU1 DeepSleep Flag.
|
|
||||||
*
|
|
||||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
|
||||||
*/
|
|
||||||
#endif
|
|
||||||
#define __HAL_PWR_GET_FLAG(__FLAG__) ((((__FLAG__) & PWR_FLAG_REG_MASK) == PWR_FLAG_REG_SR1) ? \
|
|
||||||
( \
|
|
||||||
PWR->SR1 & (1UL << ((__FLAG__) & 31UL)) \
|
|
||||||
) \
|
|
||||||
: \
|
|
||||||
( \
|
|
||||||
(((__FLAG__) & PWR_FLAG_REG_MASK) == PWR_FLAG_REG_SR2) ? \
|
|
||||||
( \
|
|
||||||
PWR->SR2 & (1UL << ((__FLAG__) & 31UL)) \
|
|
||||||
) \
|
|
||||||
: \
|
|
||||||
( \
|
|
||||||
PWR->EXTSCR & (1UL << ((__FLAG__) & 31UL)) \
|
|
||||||
) \
|
|
||||||
) \
|
|
||||||
)
|
|
||||||
|
|
||||||
#if defined(DUAL_CORE)
|
|
||||||
/** @brief Clear a specific PWR flag.
|
|
||||||
* @note Clearing of flags {PWR_FLAG_STOP, PWR_FLAG_STOP2, PWR_FLAG_SB}
|
|
||||||
* and flags {PWR_FLAG_C2STOP, PWR_FLAG_C2SB} are grouped:
|
|
||||||
* clearing of one flag also clears the other ones.
|
|
||||||
* @param __FLAG__ specifies the flag to clear.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
*
|
|
||||||
* /--------------------------------SCR (SRR)------------------------------/
|
|
||||||
* @arg @ref PWR_FLAG_WU Wake Up Flag of all pins.
|
|
||||||
* @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event
|
|
||||||
* was received from the WKUP pin 1.
|
|
||||||
* @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event
|
|
||||||
* was received from the WKUP pin 2.
|
|
||||||
* @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event
|
|
||||||
* was received from the WKUP pin 3.
|
|
||||||
*
|
|
||||||
* @arg @ref PWR_FLAG_WPVD Wakeup PVD flag
|
|
||||||
*
|
|
||||||
* @arg @ref PWR_FLAG_HOLDC2I CPU2 on-Hold Interrupt Flag
|
|
||||||
*
|
|
||||||
* @arg @ref PWR_FLAG_WRFBUSY Wake-up radio busy flag (triggered status: wake-up event or interruption occurred at least once. Can be cleared by software)
|
|
||||||
*
|
|
||||||
* /----------------------------EXTSCR--------------------------/
|
|
||||||
* @arg @ref PWR_FLAG_LPMODES System Standby Flag for CPU1.
|
|
||||||
* @arg @ref PWR_FLAG_C2LPMODES System Standby Flag for CPU2.
|
|
||||||
*
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#else
|
|
||||||
/** @brief Clear a specific PWR flag.
|
|
||||||
* @note Clearing of flags {PWR_FLAG_STOP, PWR_FLAG_STOP2, PWR_FLAG_SB}
|
|
||||||
* are grouped:
|
|
||||||
* clearing of one flag also clears the other ones.
|
|
||||||
* @param __FLAG__ specifies the flag to clear.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
*
|
|
||||||
* /--------------------------------SCR (SRR)------------------------------/
|
|
||||||
* @arg @ref PWR_FLAG_WU Wake Up Flag of all pins.
|
|
||||||
* @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event
|
|
||||||
* was received from the WKUP pin 1.
|
|
||||||
* @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event
|
|
||||||
* was received from the WKUP pin 2.
|
|
||||||
* @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event
|
|
||||||
* was received from the WKUP pin 3.
|
|
||||||
*
|
|
||||||
* @arg @ref PWR_FLAG_WPVD Wakeup PVD flag
|
|
||||||
*
|
|
||||||
* @arg @ref PWR_FLAG_WRFBUSY Wake-up radio busy flag (triggered status: wake-up event or interruption occurred at least once. Can be cleared by software)
|
|
||||||
*
|
|
||||||
* /----------------------------EXTSCR--------------------------/
|
|
||||||
* @arg @ref PWR_FLAG_LPMODES System Standby Flag for CPU1.
|
|
||||||
*
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#endif
|
|
||||||
#define __HAL_PWR_CLEAR_FLAG(__FLAG__) ((((__FLAG__) & PWR_FLAG_REG_MASK) == PWR_FLAG_REG_EXTSCR) ? \
|
|
||||||
( \
|
|
||||||
PWR->EXTSCR = (1UL << (((__FLAG__) & PWR_FLAG_EXTSCR_CLR_MASK) >> PWR_FLAG_EXTSCR_CLR_POS)) \
|
|
||||||
) \
|
|
||||||
: \
|
|
||||||
( \
|
|
||||||
(((__FLAG__)) == PWR_FLAG_WU) ? \
|
|
||||||
(PWR->SCR = PWR_SCR_CWUF) : \
|
|
||||||
(PWR->SCR = (1UL << ((__FLAG__) & 31UL))) \
|
|
||||||
) \
|
|
||||||
)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the PVD Extended Interrupt line.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#if defined(CORE_CM0PLUS)
|
|
||||||
#define __HAL_PWR_PVD_EXTI_ENABLE_IT() LL_C2_EXTI_EnableIT_0_31(PWR_EXTI_LINE_PVD)
|
|
||||||
#else
|
|
||||||
#define __HAL_PWR_PVD_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(PWR_EXTI_LINE_PVD)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the PVD Extended Interrupt line.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#if defined(CORE_CM0PLUS)
|
|
||||||
#define __HAL_PWR_PVD_EXTI_DISABLE_IT() LL_C2_EXTI_DisableIT_0_31(PWR_EXTI_LINE_PVD)
|
|
||||||
#else
|
|
||||||
#define __HAL_PWR_PVD_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(PWR_EXTI_LINE_PVD)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Note: On STM32WL series, power PVD event is not available on EXTI lines */
|
|
||||||
/* (only interruption is available through EXTI line 16). */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the PVD Extended Interrupt Rising Trigger.
|
|
||||||
* @note PVD flag polarity is inverted compared to EXTI line, therefore
|
|
||||||
* EXTI rising and falling logic edges are inverted versus PVD voltage edges.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableFallingTrig_0_31(PWR_EXTI_LINE_PVD)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the PVD Extended Interrupt Rising Trigger.
|
|
||||||
* @note PVD flag polarity is inverted compared to EXTI line, therefore
|
|
||||||
* EXTI rising and falling logic edges are inverted versus PVD voltage edges.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableFallingTrig_0_31(PWR_EXTI_LINE_PVD)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the PVD Extended Interrupt Falling Trigger.
|
|
||||||
* @note PVD flag polarity is inverted compared to EXTI line, therefore
|
|
||||||
* EXTI rising and falling logic edges are inverted versus PVD voltage edges.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableRisingTrig_0_31(PWR_EXTI_LINE_PVD)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the PVD Extended Interrupt Falling Trigger.
|
|
||||||
* @note PVD flag polarity is inverted compared to EXTI line, therefore
|
|
||||||
* EXTI rising and falling logic edges are inverted versus PVD voltage edges.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableRisingTrig_0_31(PWR_EXTI_LINE_PVD)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the PVD Extended Interrupt Rising & Falling Trigger.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
|
|
||||||
do { \
|
|
||||||
__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \
|
|
||||||
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \
|
|
||||||
} while(0)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
|
|
||||||
do { \
|
|
||||||
__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
|
|
||||||
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
|
|
||||||
} while(0)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Generate a Software interrupt on selected EXTI line.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(PWR_EXTI_LINE_PVD)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Check whether or not the PVD EXTI interrupt flag is set.
|
|
||||||
* @retval EXTI PVD Line Status.
|
|
||||||
*/
|
|
||||||
#define __HAL_PWR_PVD_EXTI_GET_FLAG() LL_EXTI_ReadFlag_0_31(PWR_EXTI_LINE_PVD)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Clear the PVD EXTI interrupt flag.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(PWR_EXTI_LINE_PVD)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/* Private macros --------------------------------------------------------*/
|
|
||||||
/** @defgroup PWR_Private_Macros PWR Private Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define IS_PWR_PVD_LEVEL(__LEVEL__) (((__LEVEL__) == PWR_PVDLEVEL_0) || ((__LEVEL__) == PWR_PVDLEVEL_1)|| \
|
|
||||||
((__LEVEL__) == PWR_PVDLEVEL_2) || ((__LEVEL__) == PWR_PVDLEVEL_3)|| \
|
|
||||||
((__LEVEL__) == PWR_PVDLEVEL_4) || ((__LEVEL__) == PWR_PVDLEVEL_5)|| \
|
|
||||||
((__LEVEL__) == PWR_PVDLEVEL_6) || ((__LEVEL__) == PWR_PVDLEVEL_7))
|
|
||||||
|
|
||||||
#define IS_PWR_PVD_MODE(__MODE__) (((__MODE__) == PWR_PVD_MODE_NORMAL) ||\
|
|
||||||
((__MODE__) == PWR_PVD_MODE_IT_RISING) ||\
|
|
||||||
((__MODE__) == PWR_PVD_MODE_IT_FALLING) ||\
|
|
||||||
((__MODE__) == PWR_PVD_MODE_IT_RISING_FALLING))
|
|
||||||
|
|
||||||
#define IS_PWR_REGULATOR(__REGULATOR__) (((__REGULATOR__) == PWR_MAINREGULATOR_ON) || \
|
|
||||||
((__REGULATOR__) == PWR_LOWPOWERREGULATOR_ON))
|
|
||||||
|
|
||||||
#define IS_PWR_SLEEP_ENTRY(__ENTRY__) (((__ENTRY__) == PWR_SLEEPENTRY_WFI) || \
|
|
||||||
((__ENTRY__) == PWR_SLEEPENTRY_WFE))
|
|
||||||
|
|
||||||
#define IS_PWR_STOP_ENTRY(__ENTRY__) (((__ENTRY__) == PWR_STOPENTRY_WFI) || \
|
|
||||||
((__ENTRY__) == PWR_STOPENTRY_WFE))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Include PWR HAL Extended module */
|
|
||||||
#include "stm32wlxx_hal_pwr_ex.h"
|
|
||||||
|
|
||||||
/* Exported functions --------------------------------------------------------*/
|
|
||||||
/** @defgroup PWR_Exported_Functions PWR Exported Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Initialization and de-initialization functions *******************************/
|
|
||||||
void HAL_PWR_DeInit(void);
|
|
||||||
|
|
||||||
void HAL_PWR_EnableBkUpAccess(void);
|
|
||||||
void HAL_PWR_DisableBkUpAccess(void);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Peripheral Control functions ************************************************/
|
|
||||||
HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
|
|
||||||
void HAL_PWR_EnablePVD(void);
|
|
||||||
void HAL_PWR_DisablePVD(void);
|
|
||||||
|
|
||||||
/* WakeUp pins configuration functions ****************************************/
|
|
||||||
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);
|
|
||||||
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
|
|
||||||
|
|
||||||
/* Low Power modes configuration functions ************************************/
|
|
||||||
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
|
|
||||||
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
|
|
||||||
void HAL_PWR_EnterSTANDBYMode(void);
|
|
||||||
|
|
||||||
void HAL_PWR_EnableSleepOnExit(void);
|
|
||||||
void HAL_PWR_DisableSleepOnExit(void);
|
|
||||||
|
|
||||||
void HAL_PWR_EnableSEVOnPend(void);
|
|
||||||
void HAL_PWR_DisableSEVOnPend(void);
|
|
||||||
|
|
||||||
void HAL_PWR_PVDCallback(void);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
|
|
||||||
#endif /* STM32WLxx_HAL_PWR_H */
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,654 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32wlxx_hal_pwr_ex.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief Header file of PWR HAL Extended module.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
|
||||||
* All rights reserved.</center></h2>
|
|
||||||
*
|
|
||||||
* This software component is licensed by ST under BSD 3-Clause license,
|
|
||||||
* the "License"; You may not use this file except in compliance with the
|
|
||||||
* License. You may obtain a copy of the License at:
|
|
||||||
* opensource.org/licenses/BSD-3-Clause
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef STM32WLxx_HAL_PWR_EX_H
|
|
||||||
#define STM32WLxx_HAL_PWR_EX_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32wlxx_hal_def.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32WLxx_HAL_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup PWREx PWREx
|
|
||||||
* @brief PWR Extended HAL module driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
|
|
||||||
/** @defgroup PWREx_Exported_Types PWR Extended Exported Types
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief PWR PVM configuration structure definition
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t PVMType; /*!< PVMType: Specifies which voltage is monitored and against which threshold.
|
|
||||||
This parameter can be a value of @ref PWREx_PVM_Type.
|
|
||||||
@arg @ref PWR_PVM_3 Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V.
|
|
||||||
*/
|
|
||||||
uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
|
|
||||||
This parameter can be a value of @ref PWREx_PVM_Mode. */
|
|
||||||
} PWR_PVMTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private constants ---------------------------------------------------------*/
|
|
||||||
/** @defgroup PWREx_Private_Constants PWR Extended Private Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define PWR_WUP_POLARITY_SHIFT 0x05 /*!< Internal constant used to retrieve wakeup pin polarity */
|
|
||||||
|
|
||||||
/** @defgroup PWR_FLAG_REG PWR flag register
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define PWR_FLAG_REG_SR1 (0x20UL) /* Bitfield to indicate PWR flag located in register PWR_SR1 */
|
|
||||||
#define PWR_FLAG_REG_SR2 (0x40UL) /* Bitfield to indicate PWR flag located in register PWR_SR2 */
|
|
||||||
#define PWR_FLAG_REG_EXTSCR (0x60UL) /* Bitfield to indicate PWR flag located in register PWR_EXTSCR */
|
|
||||||
#define PWR_FLAG_REG_MASK_POS (5UL) /* Bitfield mask position to indicate PWR flag location in PWR register */
|
|
||||||
#define PWR_FLAG_REG_MASK (PWR_FLAG_REG_SR1 | PWR_FLAG_REG_SR2 | PWR_FLAG_REG_EXTSCR) /* Bitfield mask to indicate PWR flag location in PWR register */
|
|
||||||
#define PWR_FLAG_EXTSCR_CLR_POS (16UL) /* Bitfield for register PWR_EXTSCR clearable bits positions: position of bitfield in flag literals */
|
|
||||||
#if defined(DUAL_CORE)
|
|
||||||
#define PWR_FLAG_EXTSCR_CLR_MASK ((PWR_EXTSCR_C1CSSF_Pos | PWR_EXTSCR_C2CSSF_Pos) << PWR_FLAG_EXTSCR_CLR_POS) /* Bitfield for register PWR_EXTSCR clearable bits positions: mask of bitfield in flag literals */
|
|
||||||
#else
|
|
||||||
#define PWR_FLAG_EXTSCR_CLR_MASK ((PWR_EXTSCR_C1CSSF_Pos) << PWR_FLAG_EXTSCR_CLR_POS) /* Bitfield for register PWR_EXTSCR clearable bits positions: mask of bitfield in flag literals */
|
|
||||||
#endif
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup PWR_PVM_Mode_Mask PWR PVM Mode Mask
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Note: On STM32WL series, power PVD event is not available on EXTI lines */
|
|
||||||
/* (only interruption is available through EXTI line 16). */
|
|
||||||
#define PVM_MODE_IT (0x00010000UL) /*!< Mask for interruption yielded by PVM threshold crossing */
|
|
||||||
#define PVM_RISING_EDGE (0x00000001UL) /*!< Mask for rising edge set as PVM trigger */
|
|
||||||
#define PVM_FALLING_EDGE (0x00000002UL) /*!< Mask for falling edge set as PVM trigger */
|
|
||||||
#define PVM_RISING_FALLING_EDGE (0x00000003UL) /*!< Mask for rising and falling edges set as PVM trigger */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
|
||||||
|
|
||||||
/** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup PWREx_WakeUp_Pins PWR wake-up pins
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */
|
|
||||||
#define PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */
|
|
||||||
#define PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */
|
|
||||||
|
|
||||||
#define PWR_WAKEUP_PIN1_LOW ((PWR_CR4_WP1<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1) /*!< Wakeup pin 1 (with low level polarity) */
|
|
||||||
#define PWR_WAKEUP_PIN2_LOW ((PWR_CR4_WP2<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2) /*!< Wakeup pin 2 (with low level polarity) */
|
|
||||||
#define PWR_WAKEUP_PIN3_LOW ((PWR_CR4_WP3<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3) /*!< Wakeup pin 3 (with low level polarity) */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Literals kept for legacy purpose */
|
|
||||||
#define PWR_WAKEUP_PIN1 PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */
|
|
||||||
#define PWR_WAKEUP_PIN2 PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */
|
|
||||||
#define PWR_WAKEUP_PIN3 PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */
|
|
||||||
|
|
||||||
/** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define PWR_PVM_3 PWR_CR2_PVME3 /*!< Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup PWREx_PVM_Mode PWR PVM interrupt and event mode
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Note: On STM32WL series, power PVM event is not available on EXTI lines */
|
|
||||||
/* (only interruption is available through EXTI line 34). */
|
|
||||||
#define PWR_PVM_MODE_NORMAL (0x00000000UL) /*!< basic mode is used */
|
|
||||||
|
|
||||||
#define PWR_PVM_MODE_IT_RISING (PVM_MODE_IT | PVM_RISING_EDGE) /*!< External Interrupt Mode with Rising edge trigger detection */
|
|
||||||
#define PWR_PVM_MODE_IT_FALLING (PVM_MODE_IT | PVM_FALLING_EDGE) /*!< External Interrupt Mode with Falling edge trigger detection */
|
|
||||||
#define PWR_PVM_MODE_IT_RISING_FALLING (PVM_MODE_IT | PVM_RISING_FALLING_EDGE) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup PWREx_Flash_PowerDown Flash Power Down modes
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define PWR_FLASHPD_LPRUN PWR_CR1_FPDR /*!< Enable Flash power down in low power run mode */
|
|
||||||
#define PWR_FLASHPD_LPSLEEP PWR_CR1_FPDS /*!< Enable Flash power down in low power sleep mode */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup PWREx_Regulator_Voltage_Scale PWR Regulator voltage scale
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS_0 /*!< Regulator voltage output range 1 mode, typical output voltage at 1.2 V, system frequency up to 64 MHz */
|
|
||||||
#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1 /*!< Regulator voltage output range 2 mode, typical output voltage at 1.0 V, system frequency up to 16 MHz */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR battery charging resistor selection
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define PWR_BATTERY_CHARGING_RESISTOR_5 (0x00000000UL) /*!< VBAT charging through a 5 kOhms resistor */
|
|
||||||
#define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR4_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup PWREx_VBAT_Battery_Charging PWR battery charging
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define PWR_BATTERY_CHARGING_DISABLE (0x00000000UL)
|
|
||||||
#define PWR_BATTERY_CHARGING_ENABLE PWR_CR4_VBE
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup PWREx_GPIO_Bit_Number GPIO bit number for I/O setting in standby/shutdown mode
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define PWR_GPIO_BIT_0 PWR_PUCRB_PB0 /*!< GPIO port I/O pin 0 */
|
|
||||||
#define PWR_GPIO_BIT_1 PWR_PUCRB_PB1 /*!< GPIO port I/O pin 1 */
|
|
||||||
#define PWR_GPIO_BIT_2 PWR_PUCRB_PB2 /*!< GPIO port I/O pin 2 */
|
|
||||||
#define PWR_GPIO_BIT_3 PWR_PUCRB_PB3 /*!< GPIO port I/O pin 3 */
|
|
||||||
#define PWR_GPIO_BIT_4 PWR_PUCRB_PB4 /*!< GPIO port I/O pin 4 */
|
|
||||||
#define PWR_GPIO_BIT_5 PWR_PUCRB_PB5 /*!< GPIO port I/O pin 5 */
|
|
||||||
#define PWR_GPIO_BIT_6 PWR_PUCRB_PB6 /*!< GPIO port I/O pin 6 */
|
|
||||||
#define PWR_GPIO_BIT_7 PWR_PUCRB_PB7 /*!< GPIO port I/O pin 7 */
|
|
||||||
#define PWR_GPIO_BIT_8 PWR_PUCRB_PB8 /*!< GPIO port I/O pin 8 */
|
|
||||||
#define PWR_GPIO_BIT_9 PWR_PUCRB_PB9 /*!< GPIO port I/O pin 9 */
|
|
||||||
#define PWR_GPIO_BIT_10 PWR_PUCRB_PB10 /*!< GPIO port I/O pin 10 */
|
|
||||||
#define PWR_GPIO_BIT_11 PWR_PUCRB_PB11 /*!< GPIO port I/O pin 11 */
|
|
||||||
#define PWR_GPIO_BIT_12 PWR_PUCRB_PB12 /*!< GPIO port I/O pin 12 */
|
|
||||||
#define PWR_GPIO_BIT_13 PWR_PUCRB_PB13 /*!< GPIO port I/O pin 14 */
|
|
||||||
#define PWR_GPIO_BIT_14 PWR_PDCRB_PB14 /*!< GPIO port I/O pin 14 */
|
|
||||||
#define PWR_GPIO_BIT_15 PWR_PUCRB_PB15 /*!< GPIO port I/O pin 15 */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup PWREx_GPIO GPIO port
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define PWR_GPIO_A (0x00000000UL) /*!< GPIO port A */
|
|
||||||
#define PWR_GPIO_B (0x00000001UL) /*!< GPIO port B */
|
|
||||||
#define PWR_GPIO_C (0x00000002UL) /*!< GPIO port C */
|
|
||||||
#define PWR_GPIO_H (0x00000007UL) /*!< GPIO port H */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup PWR_EC_EOL_OPERATING_MODES Monitoring of supply voltage for radio operating level (radio End Of Life)
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define PWR_RADIO_EOL_DISABLE (0x00000000UL) /*!< Monitoring of supply voltage for radio operating level (radio End Of Life) disable */
|
|
||||||
#define PWR_RADIO_EOL_ENABLE (PWR_CR5_RFEOLEN) /*!< Monitoring of supply voltage for radio operating level (radio End Of Life) enable */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup PWR_EC_SMPS_OPERATING_MODES SMPS Step down converter operating modes
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define PWR_SMPS_BYPASS (0x00000000UL) /*!< SMPS step down in bypass mode */
|
|
||||||
#define PWR_SMPS_STEP_DOWN (PWR_CR5_SMPSEN) /*!< SMPS step down in step down mode if system low power mode is run, LP run or stop0. If system low power mode is stop1, stop2, standby, shutdown, then SMPS is forced in mode open to preserve energy stored in decoupling capacitor as long as possible. Note: In case of a board without SMPS coil mounted, SMPS should not be activated. */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup PWR_EC_RADIO_BUSY_POLARITY Radio busy signal polarity
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define PWR_RADIO_BUSY_POLARITY_RISING (0x00000000UL) /*!< Radio busy signal polarity to rising edge (detection on high level). */
|
|
||||||
#define PWR_RADIO_BUSY_POLARITY_FALLING (PWR_CR4_WRFBUSYP) /*!< Radio busy signal polarity to falling edge (detection on low level). */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup PWR_EC_RADIO_BUSY_TRIGGER Radio busy trigger
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define PWR_RADIO_BUSY_TRIGGER_NONE (0x00000000UL) /*!< Radio busy trigger action: no wake-up from low-power mode and no interruption sent to the selected CPU. */
|
|
||||||
#define PWR_RADIO_BUSY_TRIGGER_WU_IT (PWR_CR3_EWRFBUSY) /*!< Radio busy trigger action: wake-up from low-power mode Standby and interruption sent to the selected CPU. */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup PWR_EC_RADIO_IRQ_TRIGGER Radio IRQ trigger
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define PWR_RADIO_IRQ_TRIGGER_NONE (0x00000000UL) /*!< Radio IRQ trigger action: no wake-up from low-power mode and no interruption sent to the selected CPU. */
|
|
||||||
#define PWR_RADIO_IRQ_TRIGGER_WU_IT (PWR_CR3_EWRFIRQ) /*!< Radio IRQ trigger action: wake-up from low-power mode Standby and interruption sent to the selected CPU. */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup PWREx_Flag PWR Status Flags
|
|
||||||
* Elements values convention: 0000 0000 0XXY YYYYb
|
|
||||||
* - Y YYYY : Flag position in the XX register (5 bits)
|
|
||||||
* - XX : Status register (2 bits)
|
|
||||||
* - 01: SR1 register
|
|
||||||
* - 10: SR2 register
|
|
||||||
* - 11: EXTSCR register
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/*--------------------------------SR1-------------------------------*/
|
|
||||||
#define PWR_FLAG_WUF1 (PWR_FLAG_REG_SR1 | PWR_SR1_WUF1_Pos) /*!< Wakeup event on wakeup pin 1 */
|
|
||||||
#define PWR_FLAG_WUF2 (PWR_FLAG_REG_SR1 | PWR_SR1_WUF2_Pos) /*!< Wakeup event on wakeup pin 2 */
|
|
||||||
#define PWR_FLAG_WUF3 (PWR_FLAG_REG_SR1 | PWR_SR1_WUF3_Pos) /*!< Wakeup event on wakeup pin 3 */
|
|
||||||
#define PWR_FLAG_WU (PWR_FLAG_REG_SR1 | PWR_SR1_WUF) /*!< Encompass wakeup event on all wakeup pins */
|
|
||||||
#define PWR_FLAG_WPVD (PWR_FLAG_REG_SR1 | PWR_SR1_WPVDF_Pos) /*!< Wakeup PVD flag */
|
|
||||||
#define PWR_FLAG_HOLDC2I (PWR_FLAG_REG_SR1 | PWR_SR1_C2HF_Pos) /*!< CPU2 on-Hold Interrupt Flag */
|
|
||||||
#define PWR_FLAG_WUFI (PWR_FLAG_REG_SR1 | PWR_SR1_WUFI_Pos) /*!< Wakeup on internal wakeup line */
|
|
||||||
#define PWR_FLAG_WRFBUSY (PWR_FLAG_REG_SR1 | PWR_SR1_WRFBUSYF_Pos) /*!< Wakeup radio busy flag (triggered status: wake-up event or interruption occurred at least once. Can be cleared by software) */
|
|
||||||
/*--------------------------------SR2-------------------------------*/
|
|
||||||
#define PWR_FLAG_LDORDY (PWR_FLAG_REG_SR2 | PWR_SR2_LDORDY_Pos) /*!< Main LDO ready flag */
|
|
||||||
#define PWR_FLAG_SMPSRDY (PWR_FLAG_REG_SR2 | PWR_SR2_SMPSRDY_Pos) /*!< SMPS ready Flag */
|
|
||||||
#define PWR_FLAG_REGLPS (PWR_FLAG_REG_SR2 | PWR_SR2_REGLPS_Pos) /*!< Low-power regulator started and ready flag */
|
|
||||||
#define PWR_FLAG_REGLPF (PWR_FLAG_REG_SR2 | PWR_SR2_REGLPF_Pos) /*!< Low-power regulator (main regulator or low-power regulator used) flag */
|
|
||||||
#define PWR_FLAG_REGMRS (PWR_FLAG_REG_SR2 | PWR_SR2_REGMRS_Pos) /*!< Main regulator supply from LDO or SMPS or directly from VDD */
|
|
||||||
#define PWR_FLAG_FLASHRDY (PWR_FLAG_REG_SR2 | PWR_SR2_FLASHRDY_Pos) /*!< Flash ready flag */
|
|
||||||
#define PWR_FLAG_VOSF (PWR_FLAG_REG_SR2 | PWR_SR2_VOSF_Pos) /*!< Voltage scaling flag */
|
|
||||||
#define PWR_FLAG_PVDO (PWR_FLAG_REG_SR2 | PWR_SR2_PVDO_Pos) /*!< Power Voltage Detector output flag */
|
|
||||||
#define PWR_FLAG_PVMO3 (PWR_FLAG_REG_SR2 | PWR_SR2_PVMO3_Pos) /*!< Power Voltage Monitoring 3 output flag */
|
|
||||||
#define PWR_FLAG_RFEOL (PWR_FLAG_REG_SR2 | PWR_SR2_RFEOLF_Pos) /*!< Power Voltage Monitoring Radio end of life flag */
|
|
||||||
#define PWR_FLAG_RFBUSYS (PWR_FLAG_REG_SR2 | PWR_SR2_RFBUSYS_Pos) /*!< Radio busy signal flag (current status) */
|
|
||||||
#define PWR_FLAG_RFBUSYMS (PWR_FLAG_REG_SR2 | PWR_SR2_RFBUSYMS_Pos) /*!< Radio busy masked signal flag (current status) */
|
|
||||||
#define PWR_FLAG_C2BOOTS (PWR_FLAG_REG_SR2 | PWR_SR2_C2BOOTS_Pos) /*!< CPU2 boot request source information flag */
|
|
||||||
/*------------------------------EXTSCR------------------------------*/
|
|
||||||
#define PWR_FLAG_SB (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C1SBF_Pos | (PWR_EXTSCR_C1CSSF_Pos << PWR_FLAG_EXTSCR_CLR_POS)) /*!< System Standby flag for CPU1 */
|
|
||||||
#define PWR_FLAG_STOP2 (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C1STOP2F_Pos | (PWR_EXTSCR_C1CSSF_Pos << PWR_FLAG_EXTSCR_CLR_POS)) /*!< System Stop 2 flag for CPU1 */
|
|
||||||
#define PWR_FLAG_STOP (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C1STOPF_Pos | (PWR_EXTSCR_C1CSSF_Pos << PWR_FLAG_EXTSCR_CLR_POS)) /*!< System Stop 0 or Stop 1 flag for CPU1 */
|
|
||||||
#if defined(DUAL_CORE)
|
|
||||||
#define PWR_FLAG_C2SB (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C2SBF_Pos | (PWR_EXTSCR_C2CSSF_Pos << PWR_FLAG_EXTSCR_CLR_POS)) /*!< System Standby flag for CPU2 */
|
|
||||||
#define PWR_FLAG_C2STOP2 (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C2STOP2F_Pos | (PWR_EXTSCR_C2CSSF_Pos << PWR_FLAG_EXTSCR_CLR_POS)) /*!< System Stop 2 flag for CPU2 */
|
|
||||||
#define PWR_FLAG_C2STOP (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C2STOPF_Pos | (PWR_EXTSCR_C2CSSF_Pos << PWR_FLAG_EXTSCR_CLR_POS)) /*!< System Stop 0 or Stop 1 flag for CPU2 */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define PWR_FLAG_LPMODES (PWR_FLAG_SB) /*!< System flag encompassing all low-powers flags (Stop0, 1, 2 and Standby) for CPU1, used when clearing flags */
|
|
||||||
#if defined(DUAL_CORE)
|
|
||||||
#define PWR_FLAG_C2LPMODES (PWR_FLAG_C2SB) /*!< System flag encompassing all low-powers flags (Stop0, 1, 2 and Standby) for CPU2, used when clearing flags */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define PWR_FLAG_C1DEEPSLEEP (PWR_EXTSCR_C1DS_Pos | PWR_FLAG_REG_EXTSCR) /*!< CPU1 DeepSleep Flag */
|
|
||||||
#if defined(DUAL_CORE)
|
|
||||||
#define PWR_FLAG_C2DEEPSLEEP (PWR_EXTSCR_C2DS_Pos | PWR_FLAG_REG_EXTSCR) /*!< CPU2 DeepSleep Flag */
|
|
||||||
#endif
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup PWREx_Core_Select PWREx Core definition
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define PWR_CORE_CPU1 (0x00000000UL)
|
|
||||||
#if defined(DUAL_CORE)
|
|
||||||
#define PWR_CORE_CPU2 (0x00000001UL)
|
|
||||||
#endif
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup PWREx_PVM_EXTI_LINE PWR PVM external interrupts lines
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define PWR_EXTI_LINE_PVM3 (LL_EXTI_LINE_34) /*!< External interrupt line 34 connected to PVM3 */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported macros -----------------------------------------------------------*/
|
|
||||||
/** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the PVM3 Extended Interrupt line.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#if defined(CORE_CM0PLUS)
|
|
||||||
#define __HAL_PWR_PVM3_EXTI_ENABLE_IT() LL_C2_EXTI_EnableIT_32_63(PWR_EXTI_LINE_PVM3)
|
|
||||||
#else
|
|
||||||
#define __HAL_PWR_PVM3_EXTI_ENABLE_IT() LL_EXTI_EnableIT_32_63(PWR_EXTI_LINE_PVM3)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the PVM3 Extended Interrupt line.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#if defined(CORE_CM0PLUS)
|
|
||||||
#define __HAL_PWR_PVM3_EXTI_DISABLE_IT() LL_C2_EXTI_DisableIT_32_63(PWR_EXTI_LINE_PVM3)
|
|
||||||
#else
|
|
||||||
#define __HAL_PWR_PVM3_EXTI_DISABLE_IT() LL_EXTI_DisableIT_32_63(PWR_EXTI_LINE_PVM3)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the PVM3 Event line.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#if defined(CORE_CM0PLUS)
|
|
||||||
#define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT() LL_C2_EXTI_EnableEvent_32_63(PWR_EXTI_LINE_PVM3)
|
|
||||||
#else
|
|
||||||
#define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_32_63(PWR_EXTI_LINE_PVM3)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the PVM3 Event line.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#if defined(CORE_CM0PLUS)
|
|
||||||
#define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT() LL_C2_EXTI_DisableEvent_32_63(PWR_EXTI_LINE_PVM3)
|
|
||||||
#else
|
|
||||||
#define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_32_63(PWR_EXTI_LINE_PVM3)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the PVM3 Extended Interrupt Rising Trigger.
|
|
||||||
* @note PVM3 flag polarity is inverted compared to EXTI line, therefore
|
|
||||||
* EXTI rising and falling logic edges are inverted versus PVM3 voltage edges.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableFallingTrig_32_63(PWR_EXTI_LINE_PVM3)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the PVM3 Extended Interrupt Rising Trigger.
|
|
||||||
* @note PVM3 flag polarity is inverted compared to EXTI line, therefore
|
|
||||||
* EXTI rising and falling logic edges are inverted versus PVM3 voltage edges.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableFallingTrig_32_63(PWR_EXTI_LINE_PVM3)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the PVM3 Extended Interrupt Falling Trigger.
|
|
||||||
* @note PVM3 flag polarity is inverted compared to EXTI line, therefore
|
|
||||||
* EXTI rising and falling logic edges are inverted versus PVM3 voltage edges.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableRisingTrig_32_63(PWR_EXTI_LINE_PVM3)
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the PVM3 Extended Interrupt Falling Trigger.
|
|
||||||
* @note PVM3 flag polarity is inverted compared to EXTI line, therefore
|
|
||||||
* EXTI rising and falling logic edges are inverted versus PVM3 voltage edges.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableRisingTrig_32_63(PWR_EXTI_LINE_PVM3)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief PVM3 EXTI line configuration: set rising & falling edge trigger.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE() \
|
|
||||||
do { \
|
|
||||||
__HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE(); \
|
|
||||||
__HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE(); \
|
|
||||||
} while(0)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the PVM3 Extended Interrupt Rising & Falling Trigger.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE() \
|
|
||||||
do { \
|
|
||||||
__HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE(); \
|
|
||||||
__HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); \
|
|
||||||
} while(0)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Generate a Software interrupt on selected EXTI line.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_32_63(PWR_EXTI_LINE_PVM3)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Check whether the specified PVM3 EXTI interrupt flag is set or not.
|
|
||||||
* @retval EXTI PVM3 Line Status.
|
|
||||||
*/
|
|
||||||
#define __HAL_PWR_PVM3_EXTI_GET_FLAG() LL_EXTI_ReadFlag_32_63(PWR_EXTI_LINE_PVM3)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Clear the PVM3 EXTI flag.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_32_63(PWR_EXTI_LINE_PVM3)
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Configure the main internal regulator output voltage.
|
|
||||||
* @param __REGULATOR__ specifies the regulator output voltage to achieve
|
|
||||||
* a tradeoff between performance and power consumption.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode,
|
|
||||||
* typical output voltage at 1.2 V,
|
|
||||||
* system frequency up to 64 MHz.
|
|
||||||
* @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode,
|
|
||||||
* typical output voltage at 1.0 V,
|
|
||||||
* system frequency up to 16 MHz.
|
|
||||||
* @note This macro is similar to HAL_PWREx_ControlVoltageScaling() API but doesn't check
|
|
||||||
* whether or not VOSF flag is cleared when moving from range 2 to range 1. User
|
|
||||||
* may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \
|
|
||||||
__IO uint32_t tmpreg; \
|
|
||||||
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \
|
|
||||||
/* Delay after an RCC peripheral clock enabling */ \
|
|
||||||
tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \
|
|
||||||
UNUSED(tmpreg); \
|
|
||||||
} while(0)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private macros --------------------------------------------------------*/
|
|
||||||
/** @addtogroup PWREx_Private_Macros PWR Extended Private Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1_HIGH) || \
|
|
||||||
((PIN) == PWR_WAKEUP_PIN2_HIGH) || \
|
|
||||||
((PIN) == PWR_WAKEUP_PIN3_HIGH) || \
|
|
||||||
((PIN) == PWR_WAKEUP_PIN1_LOW) || \
|
|
||||||
((PIN) == PWR_WAKEUP_PIN2_LOW) || \
|
|
||||||
((PIN) == PWR_WAKEUP_PIN3_LOW))
|
|
||||||
|
|
||||||
#define IS_PWR_PVM_TYPE(__TYPE__) (((__TYPE__) == PWR_PVM_3))
|
|
||||||
|
|
||||||
#define IS_PWR_PVM_MODE(__MODE__) (((__MODE__) == PWR_PVM_MODE_NORMAL) ||\
|
|
||||||
((__MODE__) == PWR_PVM_MODE_IT_RISING) ||\
|
|
||||||
((__MODE__) == PWR_PVM_MODE_IT_FALLING) ||\
|
|
||||||
((__MODE__) == PWR_PVM_MODE_IT_RISING_FALLING))
|
|
||||||
|
|
||||||
#define IS_PWR_FLASH_POWERDOWN(__MODE__) ((((__MODE__) & (PWR_FLASHPD_LPRUN | PWR_FLASHPD_LPSLEEP)) != 0x00UL) && \
|
|
||||||
(((__MODE__) & ~(PWR_FLASHPD_LPRUN | PWR_FLASHPD_LPSLEEP)) == 0x00UL))
|
|
||||||
|
|
||||||
#define IS_PWR_VOLTAGE_SCALING_RANGE(__RANGE__) (((__RANGE__) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
|
|
||||||
((__RANGE__) == PWR_REGULATOR_VOLTAGE_SCALE2))
|
|
||||||
|
|
||||||
#define IS_PWR_BATTERY_RESISTOR_SELECT(__RESISTOR__) (((__RESISTOR__) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
|
|
||||||
((__RESISTOR__) == PWR_BATTERY_CHARGING_RESISTOR_1_5))
|
|
||||||
|
|
||||||
#define IS_PWR_BATTERY_CHARGING(__CHARGING__) (((__CHARGING__) == PWR_BATTERY_CHARGING_DISABLE) ||\
|
|
||||||
((__CHARGING__) == PWR_BATTERY_CHARGING_ENABLE))
|
|
||||||
|
|
||||||
#define IS_PWR_GPIO_BIT_NUMBER(__BIT_NUMBER__) (((__BIT_NUMBER__) & GPIO_PIN_MASK) != (uint32_t)0x00)
|
|
||||||
|
|
||||||
#define IS_PWR_GPIO(__GPIO__) (((__GPIO__) == PWR_GPIO_A) ||\
|
|
||||||
((__GPIO__) == PWR_GPIO_B) ||\
|
|
||||||
((__GPIO__) == PWR_GPIO_C) ||\
|
|
||||||
((__GPIO__) == PWR_GPIO_H))
|
|
||||||
|
|
||||||
#define IS_PWR_SMPS_MODE(__SMPS_MODE__) (((__SMPS_MODE__) == PWR_SMPS_BYPASS) ||\
|
|
||||||
((__SMPS_MODE__) == PWR_SMPS_STEP_DOWN))
|
|
||||||
|
|
||||||
#define IS_RADIO_BUSY_POLARITY(__RADIO_BUSY_POLARITY__) (((__RADIO_BUSY_POLARITY__) == PWR_RADIO_BUSY_POLARITY_RISING) ||\
|
|
||||||
((__RADIO_BUSY_POLARITY__) == PWR_RADIO_BUSY_POLARITY_FALLING))
|
|
||||||
|
|
||||||
#define IS_PWR_RADIO_BUSY_TRIGGER(__RADIO_BUSY_TRIGGER__) (((__RADIO_BUSY_TRIGGER__) == PWR_RADIO_BUSY_TRIGGER_NONE) ||\
|
|
||||||
((__RADIO_BUSY_TRIGGER__) == PWR_RADIO_BUSY_TRIGGER_WU_IT))
|
|
||||||
|
|
||||||
#define IS_RADIO_IRQ_TRIGGER(__RADIO_IRQ_TRIGGER__) (((__RADIO_IRQ_TRIGGER__) == PWR_RADIO_IRQ_TRIGGER_NONE) ||\
|
|
||||||
((__RADIO_IRQ_TRIGGER__) == PWR_RADIO_IRQ_TRIGGER_WU_IT))
|
|
||||||
|
|
||||||
#if defined(DUAL_CORE)
|
|
||||||
#define IS_PWR_CORE(__CPU__) (((__CPU__) == PWR_CORE_CPU1) || ((__CPU__) == PWR_CORE_CPU2))
|
|
||||||
#else
|
|
||||||
#define IS_PWR_CORE(__CPU__) (((__CPU__) == PWR_CORE_CPU1))
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(DUAL_CORE)
|
|
||||||
#define IS_PWR_CORE_HOLD_RELEASE(__CPU__) ((__CPU__) == PWR_CORE_CPU2)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/* Peripheral Control functions **********************************************/
|
|
||||||
uint32_t HAL_PWREx_GetVoltageRange(void);
|
|
||||||
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
|
|
||||||
|
|
||||||
void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection);
|
|
||||||
void HAL_PWREx_DisableBatteryCharging(void);
|
|
||||||
|
|
||||||
void HAL_PWREx_EnableInternalWakeUpLine(void);
|
|
||||||
void HAL_PWREx_DisableInternalWakeUpLine(void);
|
|
||||||
|
|
||||||
void HAL_PWREx_SetRadioBusyPolarity(uint32_t RadioBusyPolarity);
|
|
||||||
void HAL_PWREx_SetRadioBusyTrigger(uint32_t RadioBusyTrigger);
|
|
||||||
void HAL_PWREx_SetRadioIRQTrigger(uint32_t RadioIRQTrigger);
|
|
||||||
|
|
||||||
void HAL_PWREx_EnableHOLDC2IT(void);
|
|
||||||
void HAL_PWREx_DisableHOLDC2IT(void);
|
|
||||||
|
|
||||||
void HAL_PWREx_HoldCore(uint32_t CPU);
|
|
||||||
void HAL_PWREx_ReleaseCore(uint32_t CPU);
|
|
||||||
|
|
||||||
#ifdef CORE_CM0PLUS
|
|
||||||
void HAL_PWREx_EnableWakeUp_ILAC(void);
|
|
||||||
void HAL_PWREx_DisableWakeUp_ILAC(void);
|
|
||||||
uint32_t HAL_PWREx_IsEnabledWakeUp_ILAC(void);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
|
|
||||||
HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
|
|
||||||
HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
|
|
||||||
HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
|
|
||||||
void HAL_PWREx_EnablePullUpPullDownConfig(void);
|
|
||||||
void HAL_PWREx_DisablePullUpPullDownConfig(void);
|
|
||||||
|
|
||||||
void HAL_PWREx_EnableSRAMRetention(void);
|
|
||||||
void HAL_PWREx_DisableSRAMRetention(void);
|
|
||||||
|
|
||||||
void HAL_PWREx_EnableFlashPowerDown(uint32_t PowerMode);
|
|
||||||
void HAL_PWREx_DisableFlashPowerDown(uint32_t PowerMode);
|
|
||||||
|
|
||||||
void HAL_PWREx_EnableWPVD(void);
|
|
||||||
void HAL_PWREx_DisableWPVD(void);
|
|
||||||
void HAL_PWREx_EnableBORPVD_ULP(void);
|
|
||||||
void HAL_PWREx_DisableBORPVD_ULP(void);
|
|
||||||
|
|
||||||
void HAL_PWREx_EnablePVM3(void);
|
|
||||||
void HAL_PWREx_DisablePVM3(void);
|
|
||||||
|
|
||||||
HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM);
|
|
||||||
|
|
||||||
void HAL_PWREx_SetRadioEOL(uint32_t RadioEOL);
|
|
||||||
void HAL_PWREx_SMPS_SetMode(uint32_t OperatingMode);
|
|
||||||
uint32_t HAL_PWREx_SMPS_GetEffectiveMode(void);
|
|
||||||
|
|
||||||
/* Low Power modes configuration functions ************************************/
|
|
||||||
void HAL_PWREx_EnableLowPowerRunMode(void);
|
|
||||||
HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void);
|
|
||||||
|
|
||||||
void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry);
|
|
||||||
void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry);
|
|
||||||
void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry);
|
|
||||||
void HAL_PWREx_EnterSHUTDOWNMode(void);
|
|
||||||
|
|
||||||
void HAL_PWREx_PVD_PVM_IRQHandler(void);
|
|
||||||
|
|
||||||
void HAL_PWREx_PVM3Callback(void);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
|
|
||||||
#endif /* STM32WLxx_HAL_PWR_EX_H */
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,704 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32wlxx_hal_rcc_ex.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief Header file of RCC HAL Extended module.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
|
||||||
* All rights reserved.</center></h2>
|
|
||||||
*
|
|
||||||
* This software component is licensed by ST under BSD 3-Clause license,
|
|
||||||
* the "License"; You may not use this file except in compliance with the
|
|
||||||
* License. You may obtain a copy of the License at:
|
|
||||||
* opensource.org/licenses/BSD-3-Clause
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef STM32WLxx_HAL_RCC_EX_H
|
|
||||||
#define STM32WLxx_HAL_RCC_EX_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32wlxx_hal_def.h"
|
|
||||||
#include "stm32wlxx_ll_exti.h"
|
|
||||||
#include "stm32wlxx_ll_pwr.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32WLxx_HAL_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup RCCEx
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Private constants ---------------------------------------------------------*/
|
|
||||||
/** @addtogroup RCCEx_Private_Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Define used for IS_RCC_* macros below */
|
|
||||||
#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_I2S2 | \
|
|
||||||
RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
|
|
||||||
RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \
|
|
||||||
RCC_PERIPHCLK_LPTIM3 | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_RNG | \
|
|
||||||
RCC_PERIPHCLK_RTC )
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private macros ------------------------------------------------------------*/
|
|
||||||
/** @addtogroup RCCEx_Private_Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \
|
|
||||||
((__SOURCE__) == RCC_LSCOSOURCE_LSE))
|
|
||||||
|
|
||||||
#define IS_RCC_PERIPHCLOCK(__SELECTION__) ((((__SELECTION__) & RCC_PERIPHCLOCK_ALL) != 0x00u) && \
|
|
||||||
(((__SELECTION__) & ~RCC_PERIPHCLOCK_ALL) == 0x00u))
|
|
||||||
|
|
||||||
#define IS_RCC_USART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \
|
|
||||||
((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
|
|
||||||
((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \
|
|
||||||
((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
|
|
||||||
|
|
||||||
#define IS_RCC_USART2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \
|
|
||||||
((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
|
|
||||||
((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \
|
|
||||||
((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
|
|
||||||
|
|
||||||
#define IS_RCC_I2S2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S2CLKSOURCE_PLL) || \
|
|
||||||
((__SOURCE__) == RCC_I2S2CLKSOURCE_HSI) || \
|
|
||||||
((__SOURCE__) == RCC_I2S2CLKSOURCE_PIN))
|
|
||||||
|
|
||||||
#define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \
|
|
||||||
((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \
|
|
||||||
((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \
|
|
||||||
((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))
|
|
||||||
|
|
||||||
#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \
|
|
||||||
((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
|
|
||||||
((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))
|
|
||||||
|
|
||||||
#define IS_RCC_I2C2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \
|
|
||||||
((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \
|
|
||||||
((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI))
|
|
||||||
|
|
||||||
|
|
||||||
#define IS_RCC_I2C3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \
|
|
||||||
((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \
|
|
||||||
((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))
|
|
||||||
|
|
||||||
#define IS_RCC_LPTIM1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \
|
|
||||||
((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \
|
|
||||||
((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \
|
|
||||||
((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE))
|
|
||||||
|
|
||||||
#define IS_RCC_LPTIM2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1) || \
|
|
||||||
((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \
|
|
||||||
((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \
|
|
||||||
((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE))
|
|
||||||
|
|
||||||
#define IS_RCC_LPTIM3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LPTIM3CLKSOURCE_PCLK1) || \
|
|
||||||
((__SOURCE__) == RCC_LPTIM3CLKSOURCE_LSI) || \
|
|
||||||
((__SOURCE__) == RCC_LPTIM3CLKSOURCE_HSI) || \
|
|
||||||
((__SOURCE__) == RCC_LPTIM3CLKSOURCE_LSE))
|
|
||||||
|
|
||||||
#define IS_RCC_RNGCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \
|
|
||||||
((__SOURCE__) == RCC_RNGCLKSOURCE_LSI) || \
|
|
||||||
((__SOURCE__) == RCC_RNGCLKSOURCE_LSE) || \
|
|
||||||
((__SOURCE__) == RCC_RNGCLKSOURCE_MSI))
|
|
||||||
|
|
||||||
#define IS_RCC_ADCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \
|
|
||||||
((__SOURCE__) == RCC_ADCCLKSOURCE_HSI) || \
|
|
||||||
((__SOURCE__) == RCC_ADCCLKSOURCE_PLL) || \
|
|
||||||
((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
|
|
||||||
/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief RCC extended clocks structure definition
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
|
|
||||||
This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
|
|
||||||
|
|
||||||
uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source.
|
|
||||||
This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
|
|
||||||
|
|
||||||
uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source.
|
|
||||||
This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
|
|
||||||
|
|
||||||
uint32_t I2s2ClockSelection; /*!< Specifies I2S2 clock source.
|
|
||||||
This parameter can be a value of @ref RCCEx_I2S2_Clock_Source */
|
|
||||||
|
|
||||||
uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source.
|
|
||||||
This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */
|
|
||||||
|
|
||||||
uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source.
|
|
||||||
This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
|
|
||||||
|
|
||||||
uint32_t I2c2ClockSelection; /*!< Specifies I2C2 clock source.
|
|
||||||
This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
|
|
||||||
|
|
||||||
uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source.
|
|
||||||
This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
|
|
||||||
|
|
||||||
uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source.
|
|
||||||
This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
|
|
||||||
|
|
||||||
uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source.
|
|
||||||
This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */
|
|
||||||
|
|
||||||
uint32_t Lptim3ClockSelection; /*!< Specifies LPTIM3 clock source.
|
|
||||||
This parameter can be a value of @ref RCCEx_LPTIM3_Clock_Source */
|
|
||||||
|
|
||||||
uint32_t AdcClockSelection; /*!< Specifies ADC interface clock source.
|
|
||||||
This parameter can be a value of @ref RCCEx_ADC_Clock_Source */
|
|
||||||
|
|
||||||
uint32_t RngClockSelection; /*!< Specifies RNG clock source.
|
|
||||||
This parameter can be a value of @ref RCCEx_RNG_Clock_Source */
|
|
||||||
|
|
||||||
uint32_t RTCClockSelection; /*!< Specifies RTC clock source.
|
|
||||||
This parameter can be a value of @ref RCC_RTC_Clock_Source */
|
|
||||||
|
|
||||||
} RCC_PeriphCLKInitTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
|
||||||
/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define RCC_LSCOSOURCE_LSI LL_RCC_LSCO_CLKSOURCE_LSI /*!< LSI selection for low speed clock output */
|
|
||||||
#define RCC_LSCOSOURCE_LSE LL_RCC_LSCO_CLKSOURCE_LSE /*!< LSE selection for low speed clock output */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define RCC_PERIPHCLK_USART1 0x00000001U /*!< USART1 Peripheral Clock Selection */
|
|
||||||
#define RCC_PERIPHCLK_USART2 0x00000002U /*!< USART2 Peripheral Clock Selection */
|
|
||||||
#define RCC_PERIPHCLK_I2S2 0x00000010U /*!< I2S2 Peripheral Clock Selection */
|
|
||||||
#define RCC_PERIPHCLK_LPUART1 0x00000020U /*!< LPUART1 Peripheral Clock Selection */
|
|
||||||
#define RCC_PERIPHCLK_I2C1 0x00000040U /*!< I2C1 Peripheral Clock Selection */
|
|
||||||
#define RCC_PERIPHCLK_I2C2 0x00000080U /*!< I2C2 Peripheral Clock Selection */
|
|
||||||
#define RCC_PERIPHCLK_I2C3 0x00000100U /*!< I2C3 Peripheral Clock Selection */
|
|
||||||
#define RCC_PERIPHCLK_LPTIM1 0x00000200U /*!< LPTIM1 Peripheral Clock Selection */
|
|
||||||
#define RCC_PERIPHCLK_LPTIM2 0x00000400U /*!< LPTIM2 Peripheral Clock Selection */
|
|
||||||
#define RCC_PERIPHCLK_LPTIM3 0x00000800U /*!< LPTIM3 Peripheral Clock Selection */
|
|
||||||
#define RCC_PERIPHCLK_ADC 0x00004000U /*!< ADC Peripheral Clock Selection */
|
|
||||||
#define RCC_PERIPHCLK_RNG 0x00008000U /*!< RNG Peripheral Clock Selection */
|
|
||||||
#define RCC_PERIPHCLK_RTC 0x00010000U /*!< RTC Peripheral Clock Selection */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define RCC_USART1CLKSOURCE_PCLK2 LL_RCC_USART1_CLKSOURCE_PCLK2 /*!< APB2 clock selected as USART1 clock */
|
|
||||||
#define RCC_USART1CLKSOURCE_SYSCLK LL_RCC_USART1_CLKSOURCE_SYSCLK /*!< SYSCLK clock selected as USART1 clock */
|
|
||||||
#define RCC_USART1CLKSOURCE_HSI LL_RCC_USART1_CLKSOURCE_HSI /*!< HSI clock selected as USART1 clock */
|
|
||||||
#define RCC_USART1CLKSOURCE_LSE LL_RCC_USART1_CLKSOURCE_LSE /*!< LSE clock selected as USART1 clock */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define RCC_USART2CLKSOURCE_PCLK1 LL_RCC_USART2_CLKSOURCE_PCLK1 /*!< APB1 clock selected as USART2 clock*/
|
|
||||||
#define RCC_USART2CLKSOURCE_SYSCLK LL_RCC_USART2_CLKSOURCE_SYSCLK /*!< SYSCLK clock selected as USART2 clock*/
|
|
||||||
#define RCC_USART2CLKSOURCE_HSI LL_RCC_USART2_CLKSOURCE_HSI /*!< HSI clock selected as USART2 clock*/
|
|
||||||
#define RCC_USART2CLKSOURCE_LSE LL_RCC_USART2_CLKSOURCE_LSE /*!< LSE clock selected as USART2 clock*/
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RCCEx_I2S2_Clock_Source I2S Clock Source
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define RCC_I2S2CLKSOURCE_PLL LL_RCC_I2S2_CLKSOURCE_PLL /*!< PLL "Q" clock selected as I2S2 clock source */
|
|
||||||
#define RCC_I2S2CLKSOURCE_HSI LL_RCC_I2S2_CLKSOURCE_HSI /*!< HSI clock selected as I2S2 clock */
|
|
||||||
#define RCC_I2S2CLKSOURCE_PIN LL_RCC_I2S2_CLKSOURCE_PIN /*!< External clock selected as I2S2 clock */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define RCC_LPUART1CLKSOURCE_PCLK1 LL_RCC_LPUART1_CLKSOURCE_PCLK1 /*!< APB1 clock selected as LPUART1 clock*/
|
|
||||||
#define RCC_LPUART1CLKSOURCE_SYSCLK LL_RCC_LPUART1_CLKSOURCE_SYSCLK /*!< SYSCLK clock selected as LPUART1 clock*/
|
|
||||||
#define RCC_LPUART1CLKSOURCE_HSI LL_RCC_LPUART1_CLKSOURCE_HSI /*!< HSI clock selected as LPUART1 clock*/
|
|
||||||
#define RCC_LPUART1CLKSOURCE_LSE LL_RCC_LPUART1_CLKSOURCE_LSE /*!< LSE clock selected as LPUART1 clock*/
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define RCC_I2C1CLKSOURCE_PCLK1 LL_RCC_I2C1_CLKSOURCE_PCLK1 /*!< APB1 clock selected as I2C1 clock */
|
|
||||||
#define RCC_I2C1CLKSOURCE_SYSCLK LL_RCC_I2C1_CLKSOURCE_SYSCLK /*!< SYSCLK clock selected as I2C1 clock */
|
|
||||||
#define RCC_I2C1CLKSOURCE_HSI LL_RCC_I2C1_CLKSOURCE_HSI /*!< HSI clock selected as I2C1 clock */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define RCC_I2C2CLKSOURCE_PCLK1 LL_RCC_I2C2_CLKSOURCE_PCLK1 /*!< APB1 clock selected as I2C2 clock */
|
|
||||||
#define RCC_I2C2CLKSOURCE_SYSCLK LL_RCC_I2C2_CLKSOURCE_SYSCLK /*!< SYSCLK clock selected as I2C2 clock */
|
|
||||||
#define RCC_I2C2CLKSOURCE_HSI LL_RCC_I2C2_CLKSOURCE_HSI /*!< HSI clock selected as I2C2 clock */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define RCC_I2C3CLKSOURCE_PCLK1 LL_RCC_I2C3_CLKSOURCE_PCLK1 /*!< APB1 clock selected as I2C3 clock */
|
|
||||||
#define RCC_I2C3CLKSOURCE_SYSCLK LL_RCC_I2C3_CLKSOURCE_SYSCLK /*!< SYSCLK clock selected as I2C3 clock */
|
|
||||||
#define RCC_I2C3CLKSOURCE_HSI LL_RCC_I2C3_CLKSOURCE_HSI /*!< HSI clock selected as I2C3 clock */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define RCC_LPTIM1CLKSOURCE_PCLK1 LL_RCC_LPTIM1_CLKSOURCE_PCLK1 /*!< APB1 clock selected as LPTIM1 clock */
|
|
||||||
#define RCC_LPTIM1CLKSOURCE_LSI LL_RCC_LPTIM1_CLKSOURCE_LSI /*!< LSI clock selected as LPTIM1 clock */
|
|
||||||
#define RCC_LPTIM1CLKSOURCE_HSI LL_RCC_LPTIM1_CLKSOURCE_HSI /*!< HSI clock selected as LPTIM1 clock */
|
|
||||||
#define RCC_LPTIM1CLKSOURCE_LSE LL_RCC_LPTIM1_CLKSOURCE_LSE /*!< LSE clock selected as LPTIM1 clock */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define RCC_LPTIM2CLKSOURCE_PCLK1 LL_RCC_LPTIM2_CLKSOURCE_PCLK1 /*!< APB1 clock selected as LPTIM2 clock */
|
|
||||||
#define RCC_LPTIM2CLKSOURCE_LSI LL_RCC_LPTIM2_CLKSOURCE_LSI /*!< LSI clock selected as LPTIM2 clock */
|
|
||||||
#define RCC_LPTIM2CLKSOURCE_HSI LL_RCC_LPTIM2_CLKSOURCE_HSI /*!< HSI clock selected as LPTIM2 clock */
|
|
||||||
#define RCC_LPTIM2CLKSOURCE_LSE LL_RCC_LPTIM2_CLKSOURCE_LSE /*!< LSE clock selected as LPTIM2 clock */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RCCEx_LPTIM3_Clock_Source LPTIM3 Clock Source
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define RCC_LPTIM3CLKSOURCE_PCLK1 LL_RCC_LPTIM3_CLKSOURCE_PCLK1 /*!< APB1 clock selected as LPTIM3 clock */
|
|
||||||
#define RCC_LPTIM3CLKSOURCE_LSI LL_RCC_LPTIM3_CLKSOURCE_LSI /*!< LSI clock selected as LPTIM3 clock */
|
|
||||||
#define RCC_LPTIM3CLKSOURCE_HSI LL_RCC_LPTIM3_CLKSOURCE_HSI /*!< HSI clock selected as LPTIM3 clock */
|
|
||||||
#define RCC_LPTIM3CLKSOURCE_LSE LL_RCC_LPTIM3_CLKSOURCE_LSE /*!< LSE clock selected as LPTIM3 clock */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RCCEx_RNG_Clock_Source RNG Clock Source
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define RCC_RNGCLKSOURCE_PLL LL_RCC_RNG_CLKSOURCE_PLL /*!< PLL "Q" clock selected as RNG clock */
|
|
||||||
#define RCC_RNGCLKSOURCE_LSI LL_RCC_RNG_CLKSOURCE_LSI /*!< LSI clock selected as RNG clock */
|
|
||||||
#define RCC_RNGCLKSOURCE_LSE LL_RCC_RNG_CLKSOURCE_LSE /*!< LSE clock selected as RNG clock */
|
|
||||||
#define RCC_RNGCLKSOURCE_MSI LL_RCC_RNG_CLKSOURCE_MSI /*!< MSI clock selected as RNG clock */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define RCC_ADCCLKSOURCE_NONE LL_RCC_ADC_CLKSOURCE_NONE /*!< None clock selected as ADC clock */
|
|
||||||
#define RCC_ADCCLKSOURCE_HSI LL_RCC_ADC_CLKSOURCE_HSI /*!< HSI clock selected as ADC clock */
|
|
||||||
#define RCC_ADCCLKSOURCE_PLL LL_RCC_ADC_CLKSOURCE_PLL /*!< PLL "P" clock selected as ADC clock */
|
|
||||||
#define RCC_ADCCLKSOURCE_SYSCLK LL_RCC_ADC_CLKSOURCE_SYSCLK /*!< SYSCLK clock selected as ADC clock */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM19 /*!< External interrupt line 18 connected to the LSE CSS EXTI Line */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RCCEx_EXTI_LINE_HSECSS RCC HSE CSS external interrupt line
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define RCC_EXTI_LINE_HSECSS EXTI_IMR2_IM43 /*!< External interrupt line 43 connected to the HSE CSS EXTI Line */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported macros -----------------------------------------------------------*/
|
|
||||||
/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*============================================================================*/
|
|
||||||
|
|
||||||
/** @brief Macro to configure the USART1 clock (USART1CLK).
|
|
||||||
* @param __USART1_CLKSOURCE__ specifies the USART1 clock source.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
|
|
||||||
* @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
|
|
||||||
* @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
|
|
||||||
* @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) LL_RCC_SetUSARTClockSource(__USART1_CLKSOURCE__)
|
|
||||||
|
|
||||||
/** @brief Macro to get the USART1 clock source.
|
|
||||||
* @retval The clock source can be one of the following values:
|
|
||||||
* @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
|
|
||||||
* @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
|
|
||||||
* @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
|
|
||||||
* @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
|
|
||||||
*/
|
|
||||||
#define __HAL_RCC_GET_USART1_SOURCE() LL_RCC_GetUSARTClockSource(LL_RCC_USART1_CLKSOURCE)
|
|
||||||
|
|
||||||
/** @brief Macro to configure the USART2 clock (USART2CLK).
|
|
||||||
* @param __USART2_CLKSOURCE__ specifies the USART2 clock source.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
|
|
||||||
* @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
|
|
||||||
* @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
|
|
||||||
* @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) LL_RCC_SetUSARTClockSource(__USART2_CLKSOURCE__)
|
|
||||||
|
|
||||||
/** @brief Macro to get the USART2 clock source.
|
|
||||||
* @retval The clock source can be one of the following values:
|
|
||||||
* @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
|
|
||||||
* @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
|
|
||||||
* @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
|
|
||||||
* @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
|
|
||||||
*/
|
|
||||||
#define __HAL_RCC_GET_USART2_SOURCE() LL_RCC_GetUSARTClockSource(LL_RCC_USART2_CLKSOURCE)
|
|
||||||
|
|
||||||
/** @brief Macro to configure the I2S2 clock (I2S2CLK).
|
|
||||||
* @param __I2S2_CLKSOURCE__ specifies the I2S2 clock source.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg @ref RCC_I2S2CLKSOURCE_PLL PLL "Q" selected as I2S2 clock
|
|
||||||
* @arg @ref RCC_I2S2CLKSOURCE_HSI HSI selected as I2S2 clock
|
|
||||||
* @arg @ref RCC_I2S2CLKSOURCE_PIN External clock selected as I2S2 clock
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_RCC_I2S2_CONFIG(__I2S2_CLKSOURCE__) LL_RCC_SetI2SClockSource(__I2S2_CLKSOURCE__)
|
|
||||||
|
|
||||||
/** @brief Macro to get the I2S2 clock source.
|
|
||||||
* @retval The clock source can be one of the following values:
|
|
||||||
* @arg @ref RCC_I2S2CLKSOURCE_PLL PLL "Q" selected as I2S2 clock
|
|
||||||
* @arg @ref RCC_I2S2CLKSOURCE_HSI HSI selected as I2S2 clock
|
|
||||||
* @arg @ref RCC_I2S2CLKSOURCE_PIN External clock selected as I2S2 clock
|
|
||||||
*/
|
|
||||||
#define __HAL_RCC_GET_I2S2_SOURCE() LL_RCC_GetI2SClockSource(LL_RCC_I2S2_CLKSOURCE)
|
|
||||||
|
|
||||||
/** @brief Macro to configure the LPUART clock (LPUART1CLK).
|
|
||||||
* @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
|
|
||||||
* @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock
|
|
||||||
* @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock
|
|
||||||
* @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) LL_RCC_SetLPUARTClockSource(__LPUART1_CLKSOURCE__)
|
|
||||||
|
|
||||||
/** @brief Macro to get the LPUART1 clock source.
|
|
||||||
* @retval The clock source can be one of the following values:
|
|
||||||
* @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
|
|
||||||
* @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock
|
|
||||||
* @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock
|
|
||||||
* @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock
|
|
||||||
*/
|
|
||||||
#define __HAL_RCC_GET_LPUART1_SOURCE() LL_RCC_GetLPUARTClockSource(LL_RCC_LPUART1_CLKSOURCE)
|
|
||||||
|
|
||||||
/** @brief Macro to configure the I2C1 clock (I2C1CLK).
|
|
||||||
* @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock
|
|
||||||
* @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
|
|
||||||
* @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) LL_RCC_SetI2CClockSource(__I2C1_CLKSOURCE__)
|
|
||||||
|
|
||||||
/** @brief Macro to get the I2C1 clock source.
|
|
||||||
* @retval The clock source can be one of the following values:
|
|
||||||
* @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock
|
|
||||||
* @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
|
|
||||||
* @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
|
|
||||||
*/
|
|
||||||
#define __HAL_RCC_GET_I2C1_SOURCE() LL_RCC_GetI2CClockSource(LL_RCC_I2C1_CLKSOURCE)
|
|
||||||
|
|
||||||
/** @brief Macro to configure the I2C2 clock (I2C2CLK).
|
|
||||||
* @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock
|
|
||||||
* @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
|
|
||||||
* @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) LL_RCC_SetI2CClockSource(__I2C2_CLKSOURCE__)
|
|
||||||
|
|
||||||
/** @brief Macro to get the I2C2 clock source.
|
|
||||||
* @retval The clock source can be one of the following values:
|
|
||||||
* @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock
|
|
||||||
* @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
|
|
||||||
* @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
|
|
||||||
*/
|
|
||||||
#define __HAL_RCC_GET_I2C2_SOURCE() LL_RCC_GetI2CClockSource(LL_RCC_I2C2_CLKSOURCE)
|
|
||||||
|
|
||||||
/** @brief Macro to configure the I2C3 clock (I2C3CLK).
|
|
||||||
* @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock
|
|
||||||
* @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
|
|
||||||
* @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) LL_RCC_SetI2CClockSource(__I2C3_CLKSOURCE__)
|
|
||||||
|
|
||||||
/** @brief Macro to get the I2C3 clock source.
|
|
||||||
* @retval The clock source can be one of the following values:
|
|
||||||
* @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock
|
|
||||||
* @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
|
|
||||||
* @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
|
|
||||||
*/
|
|
||||||
#define __HAL_RCC_GET_I2C3_SOURCE() LL_RCC_GetI2CClockSource(LL_RCC_I2C3_CLKSOURCE)
|
|
||||||
|
|
||||||
/** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK).
|
|
||||||
* @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK selected as LPTIM1 clock
|
|
||||||
* @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock
|
|
||||||
* @arg @ref RCC_LPTIM1CLKSOURCE_HSI LSI selected as LPTIM1 clock
|
|
||||||
* @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) LL_RCC_SetLPTIMClockSource(__LPTIM1_CLKSOURCE__)
|
|
||||||
|
|
||||||
/** @brief Macro to get the LPTIM1 clock source.
|
|
||||||
* @retval The clock source can be one of the following values:
|
|
||||||
* @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK selected as LPTIM1 clock
|
|
||||||
* @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock
|
|
||||||
* @arg @ref RCC_LPTIM1CLKSOURCE_HSI System Clock selected as LPTIM1 clock
|
|
||||||
* @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock
|
|
||||||
*/
|
|
||||||
#define __HAL_RCC_GET_LPTIM1_SOURCE() LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE)
|
|
||||||
|
|
||||||
/** @brief Macro to configure the LPTIM2 clock (LPTIM2CLK).
|
|
||||||
* @param __LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK selected as LPTIM2 clock
|
|
||||||
* @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPTIM2 clock
|
|
||||||
* @arg @ref RCC_LPTIM2CLKSOURCE_HSI LSI selected as LPTIM2 clock
|
|
||||||
* @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) LL_RCC_SetLPTIMClockSource(__LPTIM2_CLKSOURCE__)
|
|
||||||
|
|
||||||
/** @brief Macro to get the LPTIM2 clock source.
|
|
||||||
* @retval The clock source can be one of the following values:
|
|
||||||
* @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK selected as LPTIM2 clock
|
|
||||||
* @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPTIM2 clock
|
|
||||||
* @arg @ref RCC_LPTIM2CLKSOURCE_HSI System Clock selected as LPTIM2 clock
|
|
||||||
* @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock
|
|
||||||
*/
|
|
||||||
#define __HAL_RCC_GET_LPTIM2_SOURCE() LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE)
|
|
||||||
|
|
||||||
/** @brief Macro to configure the LPTIM3 clock (LPTIM3CLK).
|
|
||||||
* @param __LPTIM3_CLKSOURCE__ specifies the LPTIM3 clock source.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg @ref RCC_LPTIM3CLKSOURCE_PCLK1 PCLK selected as LPTIM3 clock
|
|
||||||
* @arg @ref RCC_LPTIM3CLKSOURCE_LSI HSI selected as LPTIM3 clock
|
|
||||||
* @arg @ref RCC_LPTIM3CLKSOURCE_HSI LSI selected as LPTIM3 clock
|
|
||||||
* @arg @ref RCC_LPTIM3CLKSOURCE_LSE LSE selected as LPTIM3 clock
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_RCC_LPTIM3_CONFIG(__LPTIM3_CLKSOURCE__) LL_RCC_SetLPTIMClockSource(__LPTIM3_CLKSOURCE__)
|
|
||||||
|
|
||||||
/** @brief Macro to get the LPTIM3 clock source.
|
|
||||||
* @retval The clock source can be one of the following values:
|
|
||||||
* @arg @ref RCC_LPTIM3CLKSOURCE_PCLK1 PCLK selected as LPTIM3 clock
|
|
||||||
* @arg @ref RCC_LPTIM3CLKSOURCE_LSI HSI selected as LPTIM3 clock
|
|
||||||
* @arg @ref RCC_LPTIM3CLKSOURCE_HSI System Clock selected as LPTIM3 clock
|
|
||||||
* @arg @ref RCC_LPTIM3CLKSOURCE_LSE LSE selected as LPTIM3 clock
|
|
||||||
*/
|
|
||||||
#define __HAL_RCC_GET_LPTIM3_SOURCE() LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM3_CLKSOURCE)
|
|
||||||
|
|
||||||
/** @brief Macro to configure the RNG clock.
|
|
||||||
* @param __RNG_CLKSOURCE__ specifies the RNG clock source.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg @ref RCC_RNGCLKSOURCE_PLL PLL "Q" Clock selected as RNG clock
|
|
||||||
* @arg @ref RCC_RNGCLKSOURCE_LSI LSI selected as RNG clock
|
|
||||||
* @arg @ref RCC_RNGCLKSOURCE_LSE LSE selected as RNG clock
|
|
||||||
* @arg @ref RCC_RNGCLKSOURCE_MSI MSI selected as RNG clock
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) LL_RCC_SetRNGClockSource(__RNG_CLKSOURCE__)
|
|
||||||
|
|
||||||
/** @brief Macro to get the RNG clock.
|
|
||||||
* @retval The clock source can be one of the following values:
|
|
||||||
* @arg @ref RCC_RNGCLKSOURCE_PLL PLL "Q" Clock selected as RNG clock
|
|
||||||
* @arg @ref RCC_RNGCLKSOURCE_LSI LSI selected as RNG clock
|
|
||||||
* @arg @ref RCC_RNGCLKSOURCE_LSE LSE selected as RNG clock
|
|
||||||
* @arg @ref RCC_RNGCLKSOURCE_MSI MSI selected as RNG clock
|
|
||||||
*/
|
|
||||||
#define __HAL_RCC_GET_RNG_SOURCE() LL_RCC_GetRNGClockSource(LL_RCC_RNG_CLKSOURCE)
|
|
||||||
|
|
||||||
/** @brief Macro to configure the ADC interface clock.
|
|
||||||
* @param __ADC_CLKSOURCE__ specifies the ADC digital interface clock source.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock
|
|
||||||
* @arg @ref RCC_ADCCLKSOURCE_HSI HSI Clock selected as ADC clock
|
|
||||||
* @arg @ref RCC_ADCCLKSOURCE_PLL PLL "P" Clock selected as ADC clock
|
|
||||||
* @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) LL_RCC_SetADCClockSource(__ADC_CLKSOURCE__)
|
|
||||||
|
|
||||||
/** @brief Macro to get the ADC clock source.
|
|
||||||
* @retval The clock source can be one of the following values:
|
|
||||||
* @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock
|
|
||||||
* @arg @ref RCC_ADCCLKSOURCE_HSI HSI Clock selected as ADC clock
|
|
||||||
* @arg @ref RCC_ADCCLKSOURCE_PLL PLL "P" Clock selected as ADC clock
|
|
||||||
* @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock
|
|
||||||
*/
|
|
||||||
#define __HAL_RCC_GET_ADC_SOURCE() LL_RCC_GetADCClockSource(LL_RCC_ADC_CLKSOURCE)
|
|
||||||
|
|
||||||
|
|
||||||
#if defined(DUAL_CORE)
|
|
||||||
|
|
||||||
#if defined(CORE_CM0PLUS)
|
|
||||||
#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() LL_C2_EXTI_EnableIT_0_31(RCC_EXTI_LINE_LSECSS)
|
|
||||||
#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() LL_C2_EXTI_DisableIT_0_31(RCC_EXTI_LINE_LSECSS)
|
|
||||||
#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() LL_C2_EXTI_EnableEvent_0_31(RCC_EXTI_LINE_LSECSS)
|
|
||||||
#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() LL_C2_EXTI_DisableEvent_0_31(RCC_EXTI_LINE_LSECSS)
|
|
||||||
|
|
||||||
#define __HAL_RCC_HSECSS_EXTI_ENABLE_IT() LL_C2_EXTI_EnableIT_32_63(RCC_EXTI_LINE_HSECSS)
|
|
||||||
#define __HAL_RCC_HSECSS_EXTI_DISABLE_IT() LL_C2_EXTI_DisableIT_32_63(RCC_EXTI_LINE_HSECSS)
|
|
||||||
#else
|
|
||||||
#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(RCC_EXTI_LINE_LSECSS)
|
|
||||||
#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(RCC_EXTI_LINE_LSECSS)
|
|
||||||
#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(RCC_EXTI_LINE_LSECSS)
|
|
||||||
#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(RCC_EXTI_LINE_LSECSS)
|
|
||||||
|
|
||||||
#define __HAL_RCC_HSECSS_EXTI_ENABLE_IT() LL_EXTI_EnableIT_32_63(RCC_EXTI_LINE_HSECSS)
|
|
||||||
#define __HAL_RCC_HSECSS_EXTI_DISABLE_IT() LL_EXTI_DisableIT_32_63(RCC_EXTI_LINE_HSECSS)
|
|
||||||
#endif /* CORE_CM0PLUS */
|
|
||||||
|
|
||||||
#else
|
|
||||||
|
|
||||||
#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(RCC_EXTI_LINE_LSECSS)
|
|
||||||
#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(RCC_EXTI_LINE_LSECSS)
|
|
||||||
#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(RCC_EXTI_LINE_LSECSS)
|
|
||||||
#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(RCC_EXTI_LINE_LSECSS)
|
|
||||||
|
|
||||||
#define __HAL_RCC_HSECSS_EXTI_ENABLE_IT() LL_EXTI_EnableIT_32_63(RCC_EXTI_LINE_HSECSS)
|
|
||||||
#define __HAL_RCC_HSECSS_EXTI_DISABLE_IT() LL_EXTI_DisableIT_32_63(RCC_EXTI_LINE_HSECSS)
|
|
||||||
|
|
||||||
#endif /* DUAL_CORE */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/* Exported functions --------------------------------------------------------*/
|
|
||||||
/** @addtogroup RCCEx_Exported_Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup RCCEx_Exported_Functions_Group1
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
|
|
||||||
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
|
|
||||||
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup RCCEx_Exported_Functions_Group2
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk);
|
|
||||||
|
|
||||||
void HAL_RCCEx_EnableLSECSS(void);
|
|
||||||
void HAL_RCCEx_DisableLSECSS(void);
|
|
||||||
void HAL_RCCEx_EnableLSECSS_IT(void);
|
|
||||||
void HAL_RCCEx_LSECSS_IRQHandler(void);
|
|
||||||
void HAL_RCCEx_LSECSS_Callback(void);
|
|
||||||
|
|
||||||
void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource);
|
|
||||||
void HAL_RCCEx_DisableLSCO(void);
|
|
||||||
|
|
||||||
void HAL_RCCEx_EnableMSIPLLMode(void);
|
|
||||||
void HAL_RCCEx_DisableMSIPLLMode(void);
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* STM32WLxx_HAL_RCC_EX_H */
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,391 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32wlxx_hal_rng.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief Header file of RNG HAL module.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
|
||||||
* All rights reserved.</center></h2>
|
|
||||||
*
|
|
||||||
* This software component is licensed by ST under BSD 3-Clause license,
|
|
||||||
* the "License"; You may not use this file except in compliance with the
|
|
||||||
* License. You may obtain a copy of the License at:
|
|
||||||
* opensource.org/licenses/BSD-3-Clause
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef STM32WLxx_HAL_RNG_H
|
|
||||||
#define STM32WLxx_HAL_RNG_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32wlxx_hal_def.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32WLxx_HAL_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#if defined (RNG)
|
|
||||||
|
|
||||||
/** @defgroup RNG RNG
|
|
||||||
* @brief RNG HAL module driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
|
|
||||||
/** @defgroup RNG_Exported_Types RNG Exported Types
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RNG_Exported_Types_Group1 RNG Init Structure definition
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t ClockErrorDetection; /*!< CED Clock error detection */
|
|
||||||
} RNG_InitTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RNG_Exported_Types_Group2 RNG State Structure definition
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
HAL_RNG_STATE_RESET = 0x00U, /*!< RNG not yet initialized or disabled */
|
|
||||||
HAL_RNG_STATE_READY = 0x01U, /*!< RNG initialized and ready for use */
|
|
||||||
HAL_RNG_STATE_BUSY = 0x02U, /*!< RNG internal process is ongoing */
|
|
||||||
HAL_RNG_STATE_TIMEOUT = 0x03U, /*!< RNG timeout state */
|
|
||||||
HAL_RNG_STATE_ERROR = 0x04U /*!< RNG error state */
|
|
||||||
|
|
||||||
} HAL_RNG_StateTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RNG_Exported_Types_Group3 RNG Handle Structure definition
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
|
|
||||||
typedef struct __RNG_HandleTypeDef
|
|
||||||
#else
|
|
||||||
typedef struct
|
|
||||||
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
|
|
||||||
{
|
|
||||||
RNG_TypeDef *Instance; /*!< Register base address */
|
|
||||||
|
|
||||||
RNG_InitTypeDef Init; /*!< RNG configuration parameters */
|
|
||||||
|
|
||||||
HAL_LockTypeDef Lock; /*!< RNG locking object */
|
|
||||||
|
|
||||||
__IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */
|
|
||||||
|
|
||||||
__IO uint32_t ErrorCode; /*!< RNG Error code */
|
|
||||||
|
|
||||||
uint32_t RandomNumber; /*!< Last Generated RNG Data */
|
|
||||||
|
|
||||||
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
|
|
||||||
void (* ReadyDataCallback)(struct __RNG_HandleTypeDef *hrng, uint32_t random32bit); /*!< RNG Data Ready Callback */
|
|
||||||
void (* ErrorCallback)(struct __RNG_HandleTypeDef *hrng); /*!< RNG Error Callback */
|
|
||||||
|
|
||||||
void (* MspInitCallback)(struct __RNG_HandleTypeDef *hrng); /*!< RNG Msp Init callback */
|
|
||||||
void (* MspDeInitCallback)(struct __RNG_HandleTypeDef *hrng); /*!< RNG Msp DeInit callback */
|
|
||||||
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
|
|
||||||
|
|
||||||
} RNG_HandleTypeDef;
|
|
||||||
|
|
||||||
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
|
|
||||||
/**
|
|
||||||
* @brief HAL RNG Callback ID enumeration definition
|
|
||||||
*/
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
HAL_RNG_ERROR_CB_ID = 0x00U, /*!< RNG Error Callback ID */
|
|
||||||
|
|
||||||
HAL_RNG_MSPINIT_CB_ID = 0x01U, /*!< RNG MspInit callback ID */
|
|
||||||
HAL_RNG_MSPDEINIT_CB_ID = 0x02U /*!< RNG MspDeInit callback ID */
|
|
||||||
|
|
||||||
} HAL_RNG_CallbackIDTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief HAL RNG Callback pointer definition
|
|
||||||
*/
|
|
||||||
typedef void (*pRNG_CallbackTypeDef)(RNG_HandleTypeDef *hrng); /*!< pointer to a common RNG callback function */
|
|
||||||
typedef void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t random32bit); /*!< pointer to an RNG Data Ready specific callback function */
|
|
||||||
|
|
||||||
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
|
||||||
/** @defgroup RNG_Exported_Constants RNG Exported Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RNG_Exported_Constants_Group1 RNG Interrupt definition
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define RNG_IT_DRDY RNG_SR_DRDY /*!< Data Ready interrupt */
|
|
||||||
#define RNG_IT_CEI RNG_SR_CEIS /*!< Clock error interrupt */
|
|
||||||
#define RNG_IT_SEI RNG_SR_SEIS /*!< Seed error interrupt */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RNG_Exported_Constants_Group2 RNG Flag definition
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define RNG_FLAG_DRDY RNG_SR_DRDY /*!< Data ready */
|
|
||||||
#define RNG_FLAG_CECS RNG_SR_CECS /*!< Clock error current status */
|
|
||||||
#define RNG_FLAG_SECS RNG_SR_SECS /*!< Seed error current status */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RNG_Exported_Constants_Group3 RNG Clock Error Detection
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define RNG_CED_ENABLE 0x00000000U /*!< Clock error detection Enabled */
|
|
||||||
#define RNG_CED_DISABLE RNG_CR_CED /*!< Clock error detection Disabled */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RNG_Error_Definition RNG Error Definition
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define HAL_RNG_ERROR_NONE 0x00000000U /*!< No error */
|
|
||||||
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
|
|
||||||
#define HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U /*!< Invalid Callback error */
|
|
||||||
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
|
|
||||||
#define HAL_RNG_ERROR_TIMEOUT 0x00000002U /*!< Timeout error */
|
|
||||||
#define HAL_RNG_ERROR_BUSY 0x00000004U /*!< Busy error */
|
|
||||||
#define HAL_RNG_ERROR_SEED 0x00000008U /*!< Seed error */
|
|
||||||
#define HAL_RNG_ERROR_CLOCK 0x00000010U /*!< Clock error */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported macros -----------------------------------------------------------*/
|
|
||||||
/** @defgroup RNG_Exported_Macros RNG Exported Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @brief Reset RNG handle state
|
|
||||||
* @param __HANDLE__ RNG Handle
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
|
|
||||||
#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
|
||||||
(__HANDLE__)->State = HAL_RNG_STATE_RESET; \
|
|
||||||
(__HANDLE__)->MspInitCallback = NULL; \
|
|
||||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
|
||||||
} while(0U)
|
|
||||||
#else
|
|
||||||
#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
|
|
||||||
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enables the RNG peripheral.
|
|
||||||
* @param __HANDLE__ RNG Handle
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disables the RNG peripheral.
|
|
||||||
* @param __HANDLE__ RNG Handle
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Check the selected RNG flag status.
|
|
||||||
* @param __HANDLE__ RNG Handle
|
|
||||||
* @param __FLAG__ RNG flag
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg RNG_FLAG_DRDY: Data ready
|
|
||||||
* @arg RNG_FLAG_CECS: Clock error current status
|
|
||||||
* @arg RNG_FLAG_SECS: Seed error current status
|
|
||||||
* @retval The new state of __FLAG__ (SET or RESET).
|
|
||||||
*/
|
|
||||||
#define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Clears the selected RNG flag status.
|
|
||||||
* @param __HANDLE__ RNG handle
|
|
||||||
* @param __FLAG__ RNG flag to clear
|
|
||||||
* @note WARNING: This is a dummy macro for HAL code alignment,
|
|
||||||
* flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) /* dummy macro */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enables the RNG interrupts.
|
|
||||||
* @param __HANDLE__ RNG Handle
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_IE)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disables the RNG interrupts.
|
|
||||||
* @param __HANDLE__ RNG Handle
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Checks whether the specified RNG interrupt has occurred or not.
|
|
||||||
* @param __HANDLE__ RNG Handle
|
|
||||||
* @param __INTERRUPT__ specifies the RNG interrupt status flag to check.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg RNG_IT_DRDY: Data ready interrupt
|
|
||||||
* @arg RNG_IT_CEI: Clock error interrupt
|
|
||||||
* @arg RNG_IT_SEI: Seed error interrupt
|
|
||||||
* @retval The new state of __INTERRUPT__ (SET or RESET).
|
|
||||||
*/
|
|
||||||
#define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Clear the RNG interrupt status flags.
|
|
||||||
* @param __HANDLE__ RNG Handle
|
|
||||||
* @param __INTERRUPT__ specifies the RNG interrupt status flag to clear.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg RNG_IT_CEI: Clock error interrupt
|
|
||||||
* @arg RNG_IT_SEI: Seed error interrupt
|
|
||||||
* @note RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Include RNG HAL Extended module */
|
|
||||||
#include "stm32wlxx_hal_rng_ex.h"
|
|
||||||
/* Exported functions --------------------------------------------------------*/
|
|
||||||
/** @defgroup RNG_Exported_Functions RNG Exported Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RNG_Exported_Functions_Group1 Initialization and configuration functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng);
|
|
||||||
HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng);
|
|
||||||
void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng);
|
|
||||||
void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);
|
|
||||||
|
|
||||||
/* Callbacks Register/UnRegister functions ***********************************/
|
|
||||||
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
|
|
||||||
HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID,
|
|
||||||
pRNG_CallbackTypeDef pCallback);
|
|
||||||
HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID);
|
|
||||||
|
|
||||||
HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback);
|
|
||||||
HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng);
|
|
||||||
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RNG_Exported_Functions_Group2 Peripheral Control functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit);
|
|
||||||
HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng);
|
|
||||||
uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng);
|
|
||||||
|
|
||||||
void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);
|
|
||||||
void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
|
|
||||||
void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
|
|
||||||
uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private macros ------------------------------------------------------------*/
|
|
||||||
/** @defgroup RNG_Private_Macros RNG Private Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define IS_RNG_IT(IT) (((IT) == RNG_IT_CEI) || \
|
|
||||||
((IT) == RNG_IT_SEI))
|
|
||||||
|
|
||||||
#define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \
|
|
||||||
((FLAG) == RNG_FLAG_CECS) || \
|
|
||||||
((FLAG) == RNG_FLAG_SECS))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Verify the RNG Clock Error Detection mode.
|
|
||||||
* @param __MODE__ RNG Clock Error Detection mode
|
|
||||||
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
|
|
||||||
*/
|
|
||||||
#define IS_RNG_CED(__MODE__) (((__MODE__) == RNG_CED_ENABLE) || \
|
|
||||||
((__MODE__) == RNG_CED_DISABLE))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private functions ---------------------------------------------------------*/
|
|
||||||
/** @defgroup RNG_Private_Functions RNG Private functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
HAL_StatusTypeDef RNG_RecoverSeedError(RNG_HandleTypeDef *hrng);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#endif /* RNG */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
|
|
||||||
#endif /* STM32WLxx_HAL_RNG_H */
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,250 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32wlxx_hal_rng_ex.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief Header file of RNG HAL Extension module.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
|
||||||
* All rights reserved.</center></h2>
|
|
||||||
*
|
|
||||||
* This software component is licensed by ST under BSD 3-Clause license,
|
|
||||||
* the "License"; You may not use this file except in compliance with the
|
|
||||||
* License. You may obtain a copy of the License at:
|
|
||||||
* opensource.org/licenses/BSD-3-Clause
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef STM32WLxx_HAL_RNG_EX_H
|
|
||||||
#define STM32WLxx_HAL_RNG_EX_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32wlxx_hal_def.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32WLxx_HAL_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#if defined(RNG)
|
|
||||||
#if defined(RNG_CR_CONDRST)
|
|
||||||
|
|
||||||
/** @defgroup RNG_Ex RNG_Ex
|
|
||||||
* @brief RNG Extension HAL module driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
/** @defgroup RNG_Ex_Exported_Types RNG_Ex Exported Types
|
|
||||||
* @brief RNG_Ex Exported types
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief RNG_Ex Configuration Structure definition
|
|
||||||
*/
|
|
||||||
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t Config1; /*!< Config1 must be a value between 0 and 0x3F */
|
|
||||||
uint32_t Config2; /*!< Config2 must be a value between 0 and 0x7 */
|
|
||||||
uint32_t Config3; /*!< Config3 must be a value between 0 and 0xF */
|
|
||||||
uint32_t ClockDivider; /*!< Clock Divider factor.This parameter can
|
|
||||||
be a value of @ref RNG_Ex_Clock_Divider_Factor */
|
|
||||||
uint32_t NistCompliance; /*!< NIST compliance.This parameter can be a
|
|
||||||
value of @ref RNG_Ex_NIST_Compliance */
|
|
||||||
} RNG_ConfigTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
|
||||||
/** @defgroup RNG_Ex_Exported_Constants RNG_Ex Exported Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RNG_Ex_Clock_Divider_Factor Value used to configure an internal
|
|
||||||
* programmable divider acting on the incoming RNG clock
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define RNG_CLKDIV_BY_1 (0x00000000UL) /*!< No clock division */
|
|
||||||
#define RNG_CLKDIV_BY_2 (RNG_CR_CLKDIV_0)
|
|
||||||
/*!< 2 RNG clock cycles per internal RNG clock */
|
|
||||||
#define RNG_CLKDIV_BY_4 (RNG_CR_CLKDIV_1)
|
|
||||||
/*!< 4 RNG clock cycles per internal RNG clock */
|
|
||||||
#define RNG_CLKDIV_BY_8 (RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
|
|
||||||
/*!< 8 RNG clock cycles per internal RNG clock */
|
|
||||||
#define RNG_CLKDIV_BY_16 (RNG_CR_CLKDIV_2)
|
|
||||||
/*!< 16 RNG clock cycles per internal RNG clock */
|
|
||||||
#define RNG_CLKDIV_BY_32 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0)
|
|
||||||
/*!< 32 RNG clock cycles per internal RNG clock */
|
|
||||||
#define RNG_CLKDIV_BY_64 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1)
|
|
||||||
/*!< 64 RNG clock cycles per internal RNG clock */
|
|
||||||
#define RNG_CLKDIV_BY_128 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
|
|
||||||
/*!< 128 RNG clock cycles per internal RNG clock */
|
|
||||||
#define RNG_CLKDIV_BY_256 (RNG_CR_CLKDIV_3)
|
|
||||||
/*!< 256 RNG clock cycles per internal RNG clock */
|
|
||||||
#define RNG_CLKDIV_BY_512 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_0)
|
|
||||||
/*!< 512 RNG clock cycles per internal RNG clock */
|
|
||||||
#define RNG_CLKDIV_BY_1024 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1)
|
|
||||||
/*!< 1024 RNG clock cycles per internal RNG clock */
|
|
||||||
#define RNG_CLKDIV_BY_2048 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
|
|
||||||
/*!< 2048 RNG clock cycles per internal RNG clock */
|
|
||||||
#define RNG_CLKDIV_BY_4096 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2)
|
|
||||||
/*!< 4096 RNG clock cycles per internal RNG clock */
|
|
||||||
#define RNG_CLKDIV_BY_8192 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0)
|
|
||||||
/*!< 8192 RNG clock cycles per internal RNG clock */
|
|
||||||
#define RNG_CLKDIV_BY_16384 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1)
|
|
||||||
/*!< 16384 RNG clock cycles per internal RNG clock */
|
|
||||||
#define RNG_CLKDIV_BY_32768 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
|
|
||||||
/*!< 32768 RNG clock cycles per internal RNG clock */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RNG_Ex_NIST_Compliance NIST Compliance configuration
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define RNG_NIST_COMPLIANT (0x00000000UL) /*!< NIST compliant configuration*/
|
|
||||||
#define RNG_CUSTOM_NIST (RNG_CR_NISTC) /*!< Custom NIST configuration */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private types -------------------------------------------------------------*/
|
|
||||||
/** @defgroup RNG_Ex_Private_Types RNG_Ex Private Types
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private variables ---------------------------------------------------------*/
|
|
||||||
/** @defgroup RNG_Ex_Private_Variables RNG_Ex Private Variables
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private constants ---------------------------------------------------------*/
|
|
||||||
/** @defgroup RNG_Ex_Private_Constants RNG_Ex Private Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private macros ------------------------------------------------------------*/
|
|
||||||
/** @defgroup RNG_Ex_Private_Macros RNG_Ex Private Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define IS_RNG_CLOCK_DIVIDER(__CLOCK_DIV__) (((__CLOCK_DIV__) == RNG_CLKDIV_BY_1) || \
|
|
||||||
((__CLOCK_DIV__) == RNG_CLKDIV_BY_2) || \
|
|
||||||
((__CLOCK_DIV__) == RNG_CLKDIV_BY_4) || \
|
|
||||||
((__CLOCK_DIV__) == RNG_CLKDIV_BY_8) || \
|
|
||||||
((__CLOCK_DIV__) == RNG_CLKDIV_BY_16) || \
|
|
||||||
((__CLOCK_DIV__) == RNG_CLKDIV_BY_32) || \
|
|
||||||
((__CLOCK_DIV__) == RNG_CLKDIV_BY_64) || \
|
|
||||||
((__CLOCK_DIV__) == RNG_CLKDIV_BY_128) || \
|
|
||||||
((__CLOCK_DIV__) == RNG_CLKDIV_BY_256) || \
|
|
||||||
((__CLOCK_DIV__) == RNG_CLKDIV_BY_512) || \
|
|
||||||
((__CLOCK_DIV__) == RNG_CLKDIV_BY_1024) || \
|
|
||||||
((__CLOCK_DIV__) == RNG_CLKDIV_BY_2048) || \
|
|
||||||
((__CLOCK_DIV__) == RNG_CLKDIV_BY_4096) || \
|
|
||||||
((__CLOCK_DIV__) == RNG_CLKDIV_BY_8192) || \
|
|
||||||
((__CLOCK_DIV__) == RNG_CLKDIV_BY_16384) || \
|
|
||||||
((__CLOCK_DIV__) == RNG_CLKDIV_BY_32768))
|
|
||||||
|
|
||||||
|
|
||||||
#define IS_RNG_NIST_COMPLIANCE(__NIST_COMPLIANCE__) (((__NIST_COMPLIANCE__) == RNG_NIST_COMPLIANT) || \
|
|
||||||
((__NIST_COMPLIANCE__) == RNG_CUSTOM_NIST))
|
|
||||||
|
|
||||||
#define IS_RNG_CONFIG1(__CONFIG1__) ((__CONFIG1__) <= 0x3FUL)
|
|
||||||
|
|
||||||
#define IS_RNG_CONFIG2(__CONFIG2__) ((__CONFIG2__) <= 0x07UL)
|
|
||||||
|
|
||||||
#define IS_RNG_CONFIG3(__CONFIG3__) ((__CONFIG3__) <= 0xFUL)
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private functions ---------------------------------------------------------*/
|
|
||||||
/** @defgroup RNG_Ex_Private_Functions RNG_Ex Private Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported functions --------------------------------------------------------*/
|
|
||||||
/** @defgroup RNG_Ex_Exported_Functions RNG_Ex Exported Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup RNG_Ex_Exported_Functions_Group1
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf);
|
|
||||||
HAL_StatusTypeDef HAL_RNGEx_GetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf);
|
|
||||||
HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup RNG_Ex_Exported_Functions_Group2
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#endif /* RNG_CR_CONDRST */
|
|
||||||
#endif /* RNG */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
|
|
||||||
#endif /* STM32WLxx_HAL_RNG_EX_H */
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,963 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32wlxx_hal_rtc.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief Header file of RTC HAL module.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
|
||||||
* All rights reserved.</center></h2>
|
|
||||||
*
|
|
||||||
* This software component is licensed by ST under BSD 3-Clause license,
|
|
||||||
* the "License"; You may not use this file except in compliance with the
|
|
||||||
* License. You may obtain a copy of the License at:
|
|
||||||
* opensource.org/licenses/BSD-3-Clause
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef STM32WLxx_HAL_RTC_H
|
|
||||||
#define STM32WLxx_HAL_RTC_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32wlxx_hal_def.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32WLxx_HAL_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RTC RTC
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
/** @defgroup RTC_Exported_Types RTC Exported Types
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief HAL State structures definition
|
|
||||||
*/
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
HAL_RTC_STATE_RESET = 0x00U, /*!< RTC not yet initialized or disabled */
|
|
||||||
HAL_RTC_STATE_READY = 0x01U, /*!< RTC initialized and ready for use */
|
|
||||||
HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */
|
|
||||||
HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */
|
|
||||||
HAL_RTC_STATE_ERROR = 0x04U /*!< RTC error state */
|
|
||||||
|
|
||||||
} HAL_RTCStateTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief RTC Configuration Structure definition
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t HourFormat; /*!< Specifies the RTC Hour Format.
|
|
||||||
This parameter can be a value of @ref RTC_Hour_Formats */
|
|
||||||
|
|
||||||
uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
|
|
||||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
|
|
||||||
|
|
||||||
uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
|
|
||||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */
|
|
||||||
|
|
||||||
uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output.
|
|
||||||
This parameter can be a value of @ref RTCEx_Output_selection_Definitions */
|
|
||||||
|
|
||||||
uint32_t OutPutRemap; /*!< Specifies the remap for RTC output.
|
|
||||||
This parameter can be a value of @ref RTC_Output_ALARM_OUT_Remap */
|
|
||||||
|
|
||||||
uint32_t OutPutPolarity; /*!< Specifies the polarity of the output signal.
|
|
||||||
This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
|
|
||||||
|
|
||||||
uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode.
|
|
||||||
This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
|
|
||||||
|
|
||||||
uint32_t OutPutPullUp; /*!< Specifies the RTC Output Pull-Up mode.
|
|
||||||
This parameter can be a value of @ref RTC_Output_PullUp_ALARM_OUT */
|
|
||||||
|
|
||||||
uint32_t BinMode; /*!< Specifies the RTC binary mode.
|
|
||||||
This parameter can be a value of @ref RTCEx_Binary_Mode */
|
|
||||||
|
|
||||||
uint32_t BinMixBcdU; /*!< Specifies the BCD calendar update if and only if BinMode = RTC_BINARY_MIX.
|
|
||||||
This parameter can be a value of @ref RTCEx_Binary_mix_BCDU */
|
|
||||||
} RTC_InitTypeDef;
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief RTC Enabled features Structure definition
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t RtcFeatures;
|
|
||||||
uint32_t TampFeatures;
|
|
||||||
} RTC_IsEnabledTypeDef;
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief RTC Time structure definition
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint8_t Hours; /*!< Specifies the RTC Time Hour.
|
|
||||||
This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected.
|
|
||||||
This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */
|
|
||||||
|
|
||||||
uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
|
|
||||||
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
|
|
||||||
|
|
||||||
uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
|
|
||||||
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
|
|
||||||
|
|
||||||
uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
|
|
||||||
This parameter can be a value of @ref RTC_AM_PM_Definitions */
|
|
||||||
|
|
||||||
uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content.
|
|
||||||
This field is not used by HAL_RTC_SetTime.
|
|
||||||
If the free running 32 bit counter is not activated (mode binary none)
|
|
||||||
- This parameter corresponds to a time unit range between [0-1] Second with [1 Sec / SecondFraction +1] granularity
|
|
||||||
else
|
|
||||||
- This parameter corresponds to the free running 32 bit counter. */
|
|
||||||
|
|
||||||
uint32_t SecondFraction; /*!< Specifies the range or granularity of Sub Second register content
|
|
||||||
corresponding to Synchronous pre-scaler factor value (PREDIV_S)
|
|
||||||
This parameter corresponds to a time unit range between [0-1] Second
|
|
||||||
with [1 Sec / SecondFraction +1] granularity.
|
|
||||||
This field will be used only by HAL_RTC_GetTime function */
|
|
||||||
|
|
||||||
uint32_t DayLightSaving; /*!< This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */
|
|
||||||
|
|
||||||
uint32_t StoreOperation; /*!< This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */
|
|
||||||
} RTC_TimeTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief RTC Date structure definition
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay.
|
|
||||||
This parameter can be a value of @ref RTC_WeekDay_Definitions */
|
|
||||||
|
|
||||||
uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format).
|
|
||||||
This parameter can be a value of @ref RTC_Month_Date_Definitions */
|
|
||||||
|
|
||||||
uint8_t Date; /*!< Specifies the RTC Date.
|
|
||||||
This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
|
|
||||||
|
|
||||||
uint8_t Year; /*!< Specifies the RTC Date Year.
|
|
||||||
This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
|
|
||||||
|
|
||||||
} RTC_DateTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief RTC Alarm structure definition
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members */
|
|
||||||
|
|
||||||
uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks.
|
|
||||||
This parameter can be a value of @ref RTC_AlarmMask_Definitions */
|
|
||||||
|
|
||||||
uint32_t AlarmSubSecondMask; /*!< Specifies the RTC Alarm SubSeconds Masks.
|
|
||||||
if Binary mode is RTC_BINARY_ONLY or is RTC_BINARY_MIX
|
|
||||||
This parameter can be a value of @ref RTCEx_Alarm_Sub_Seconds_binary_Masks_Definitions
|
|
||||||
else if Binary mode is RTC_BINARY_NONE
|
|
||||||
This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */
|
|
||||||
|
|
||||||
uint32_t BinaryAutoClr; /*!< Clear synchronously counter (RTC_SSR) on binary alarm.
|
|
||||||
RTC_ALARMSUBSECONDBIN_AUTOCLR_YES must only be used if Binary mode is RTC_BINARY_ONLY
|
|
||||||
This parameter can be a value of @ref RTCEx_Alarm_Sub_Seconds_binary_Clear_Definitions */
|
|
||||||
|
|
||||||
uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.
|
|
||||||
This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
|
|
||||||
|
|
||||||
uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.
|
|
||||||
If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.
|
|
||||||
If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */
|
|
||||||
|
|
||||||
uint32_t Alarm; /*!< Specifies the alarm .
|
|
||||||
This parameter can be a value of @ref RTC_Alarms_Definitions */
|
|
||||||
} RTC_AlarmTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief RTC Handle Structure definition
|
|
||||||
*/
|
|
||||||
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
|
|
||||||
typedef struct __RTC_HandleTypeDef
|
|
||||||
#else
|
|
||||||
typedef struct
|
|
||||||
#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
|
|
||||||
{
|
|
||||||
RTC_TypeDef *Instance; /*!< Legacy register base address. Not used anymore, the driver directly uses cmsis base address */
|
|
||||||
|
|
||||||
RTC_InitTypeDef Init; /*!< RTC required parameters */
|
|
||||||
|
|
||||||
HAL_LockTypeDef Lock; /*!< RTC locking object */
|
|
||||||
|
|
||||||
__IO HAL_RTCStateTypeDef State; /*!< Time communication state */
|
|
||||||
|
|
||||||
RTC_IsEnabledTypeDef IsEnabled; /*!< Flag to avoid treatment of the interrupts activated by the other core */
|
|
||||||
|
|
||||||
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
|
|
||||||
void (* AlarmAEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm A Event callback */
|
|
||||||
void (* AlarmBEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm B Event callback */
|
|
||||||
void (* TimeStampEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC TimeStamp Event callback */
|
|
||||||
void (* WakeUpTimerEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC WakeUpTimer Event callback */
|
|
||||||
void (* SSRUEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC SSRU Event callback */
|
|
||||||
void (* Tamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 1 Event callback */
|
|
||||||
void (* Tamper2EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 2 Event callback */
|
|
||||||
void (* Tamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 3 Event callback */
|
|
||||||
void (* InternalTamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 3 Event callback */
|
|
||||||
void (* InternalTamper5EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 5 Event callback */
|
|
||||||
void (* InternalTamper6EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 6 Event callback */
|
|
||||||
void (* InternalTamper8EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 8 Event callback */
|
|
||||||
void (* MspInitCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp Init callback */
|
|
||||||
void (* MspDeInitCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp DeInit callback */
|
|
||||||
|
|
||||||
#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
|
|
||||||
|
|
||||||
} RTC_HandleTypeDef;
|
|
||||||
|
|
||||||
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
|
|
||||||
/**
|
|
||||||
* @brief HAL RTC Callback ID enumeration definition
|
|
||||||
*/
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
HAL_RTC_ALARM_A_EVENT_CB_ID = 0u, /*!< RTC Alarm A Event Callback ID */
|
|
||||||
HAL_RTC_ALARM_B_EVENT_CB_ID = 1u, /*!< RTC Alarm B Event Callback ID */
|
|
||||||
HAL_RTC_TIMESTAMP_EVENT_CB_ID = 2u, /*!< RTC TimeStamp Event Callback ID */
|
|
||||||
HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 3u, /*!< RTC WakeUp Timer Event Callback ID */
|
|
||||||
HAL_RTC_SSRU_EVENT_CB_ID = 4u, /*!< RTC SSR Underflow Event Callback ID */
|
|
||||||
HAL_RTC_TAMPER1_EVENT_CB_ID = 5u, /*!< RTC Tamper 1 Callback ID */
|
|
||||||
HAL_RTC_TAMPER2_EVENT_CB_ID = 6u, /*!< RTC Tamper 2 Callback ID */
|
|
||||||
HAL_RTC_TAMPER3_EVENT_CB_ID = 7u, /*!< RTC Tamper 3 Callback ID */
|
|
||||||
HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID = 8u, /*!< RTC Internal Tamper 3 Callback ID */
|
|
||||||
HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID = 9u, /*!< RTC Internal Tamper 5 Callback ID */
|
|
||||||
HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID = 10u, /*!< RTC Internal Tamper 6 Callback ID */
|
|
||||||
HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID = 11u, /*!< RTC Internal Tamper 8 Callback ID */
|
|
||||||
HAL_RTC_MSPINIT_CB_ID = 12u, /*!< RTC Msp Init callback ID */
|
|
||||||
HAL_RTC_MSPDEINIT_CB_ID = 13u /*!< RTC Msp DeInit callback ID */
|
|
||||||
} HAL_RTC_CallbackIDTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief HAL RTC Callback pointer definition
|
|
||||||
*/
|
|
||||||
typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to an RTC callback function */
|
|
||||||
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
|
||||||
/** @defgroup RTC_Exported_Constants RTC Exported Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RTC_Hour_Formats RTC Hour Formats
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define RTC_HOURFORMAT_24 0x00000000u
|
|
||||||
#define RTC_HOURFORMAT_12 RTC_CR_FMT
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RTCEx_Output_selection_Definitions RTCEx Output Selection Definition
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define RTC_OUTPUT_DISABLE 0x00000000u
|
|
||||||
#define RTC_OUTPUT_ALARMA RTC_CR_OSEL_0
|
|
||||||
#define RTC_OUTPUT_ALARMB RTC_CR_OSEL_1
|
|
||||||
#define RTC_OUTPUT_WAKEUP RTC_CR_OSEL
|
|
||||||
#define RTC_OUTPUT_TAMPER RTC_CR_TAMPOE
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define RTC_OUTPUT_POLARITY_HIGH 0x00000000u
|
|
||||||
#define RTC_OUTPUT_POLARITY_LOW RTC_CR_POL
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define RTC_OUTPUT_TYPE_PUSHPULL 0x00000000u
|
|
||||||
#define RTC_OUTPUT_TYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RTC_Output_PullUp_ALARM_OUT RTC Output Pull-Up ALARM OUT
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define RTC_OUTPUT_PULLUP_NONE 0x00000000u
|
|
||||||
#define RTC_OUTPUT_PULLUP_ON RTC_CR_TAMPALRM_PU
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RTC_Output_ALARM_OUT_Remap RTC Output ALARM OUT Remap
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define RTC_OUTPUT_REMAP_NONE 0x00000000u
|
|
||||||
#define RTC_OUTPUT_REMAP_POS1 RTC_CR_OUT2EN
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define RTC_HOURFORMAT12_AM 0x0u
|
|
||||||
#define RTC_HOURFORMAT12_PM 0x1u
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RTC_DayLightSaving_Definitions RTC DayLightSaving Definitions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define RTC_DAYLIGHTSAVING_SUB1H RTC_CR_SUB1H
|
|
||||||
#define RTC_DAYLIGHTSAVING_ADD1H RTC_CR_ADD1H
|
|
||||||
#define RTC_DAYLIGHTSAVING_NONE 0x00000000u
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RTC_StoreOperation_Definitions RTC StoreOperation Definitions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define RTC_STOREOPERATION_RESET 0x00000000u
|
|
||||||
#define RTC_STOREOPERATION_SET RTC_CR_BKP
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RTC_Input_parameter_format_definitions RTC input or output data format for date (Year, Month, Weekday) and time (Hours, Minutes, Seconds).
|
|
||||||
* Warning : It Should not be confused with the Binary mode @ref RTCEx_Binary_Mode.
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define RTC_FORMAT_BIN 0x00000000u /* This parameter will trigger a SW conversion to fit with the native BCD format of the HW Calendar.
|
|
||||||
It should not be confused with the Binary mode @ref RTCEx_Binary_Mode. */
|
|
||||||
|
|
||||||
#define RTC_FORMAT_BCD 0x00000001u /* Native format of the HW Calendar.
|
|
||||||
It should not be confused with the Binary mode @ref RTCEx_Binary_Mode. */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Coded in BCD format */
|
|
||||||
#define RTC_MONTH_JANUARY ((uint8_t)0x01U)
|
|
||||||
#define RTC_MONTH_FEBRUARY ((uint8_t)0x02U)
|
|
||||||
#define RTC_MONTH_MARCH ((uint8_t)0x03U)
|
|
||||||
#define RTC_MONTH_APRIL ((uint8_t)0x04U)
|
|
||||||
#define RTC_MONTH_MAY ((uint8_t)0x05U)
|
|
||||||
#define RTC_MONTH_JUNE ((uint8_t)0x06U)
|
|
||||||
#define RTC_MONTH_JULY ((uint8_t)0x07U)
|
|
||||||
#define RTC_MONTH_AUGUST ((uint8_t)0x08U)
|
|
||||||
#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09U)
|
|
||||||
#define RTC_MONTH_OCTOBER ((uint8_t)0x10U)
|
|
||||||
#define RTC_MONTH_NOVEMBER ((uint8_t)0x11U)
|
|
||||||
#define RTC_MONTH_DECEMBER ((uint8_t)0x12U)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01U)
|
|
||||||
#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U)
|
|
||||||
#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U)
|
|
||||||
#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U)
|
|
||||||
#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U)
|
|
||||||
#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U)
|
|
||||||
#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC AlarmDateWeekDay Definitions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define RTC_ALARMDATEWEEKDAYSEL_DATE 0x00000000u
|
|
||||||
#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RTC_AlarmMask_Definitions RTC AlarmMask Definitions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define RTC_ALARMMASK_NONE 0x00000000u
|
|
||||||
#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4
|
|
||||||
#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
|
|
||||||
#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
|
|
||||||
#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
|
|
||||||
#define RTC_ALARMMASK_ALL (RTC_ALARMMASK_DATEWEEKDAY | RTC_ALARMMASK_HOURS | \
|
|
||||||
RTC_ALARMMASK_MINUTES | RTC_ALARMMASK_SECONDS)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define RTC_ALARM_A RTC_CR_ALRAE
|
|
||||||
#define RTC_ALARM_B RTC_CR_ALRBE
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define RTC_ALARMSUBSECONDMASK_ALL 0x00000000u /*!< All Alarm SS fields are masked.
|
|
||||||
There is no comparison on sub seconds
|
|
||||||
for Alarm */
|
|
||||||
#define RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0 /*!< SS[14:1] not used in Alarm
|
|
||||||
comparison. Only SS[0] is compared. */
|
|
||||||
#define RTC_ALARMSUBSECONDMASK_SS14_2 RTC_ALRMASSR_MASKSS_1 /*!< SS[14:2] not used in Alarm
|
|
||||||
comparison. Only SS[1:0] are compared */
|
|
||||||
#define RTC_ALARMSUBSECONDMASK_SS14_3 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1) /*!< SS[14:3] not used in Alarm
|
|
||||||
comparison. Only SS[2:0] are compared */
|
|
||||||
#define RTC_ALARMSUBSECONDMASK_SS14_4 RTC_ALRMASSR_MASKSS_2 /*!< SS[14:4] not used in Alarm
|
|
||||||
comparison. Only SS[3:0] are compared */
|
|
||||||
#define RTC_ALARMSUBSECONDMASK_SS14_5 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2) /*!< SS[14:5] not used in Alarm
|
|
||||||
comparison. Only SS[4:0] are compared */
|
|
||||||
#define RTC_ALARMSUBSECONDMASK_SS14_6 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2) /*!< SS[14:6] not used in Alarm
|
|
||||||
comparison. Only SS[5:0] are compared */
|
|
||||||
#define RTC_ALARMSUBSECONDMASK_SS14_7 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2) /*!< SS[14:7] not used in Alarm
|
|
||||||
comparison. Only SS[6:0] are compared */
|
|
||||||
#define RTC_ALARMSUBSECONDMASK_SS14_8 RTC_ALRMASSR_MASKSS_3 /*!< SS[14:8] not used in Alarm
|
|
||||||
comparison. Only SS[7:0] are compared */
|
|
||||||
#define RTC_ALARMSUBSECONDMASK_SS14_9 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:9] not used in Alarm
|
|
||||||
comparison. Only SS[8:0] are compared */
|
|
||||||
#define RTC_ALARMSUBSECONDMASK_SS14_10 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:10] not used in Alarm
|
|
||||||
comparison. Only SS[9:0] are compared */
|
|
||||||
#define RTC_ALARMSUBSECONDMASK_SS14_11 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:11] not used in Alarm
|
|
||||||
comparison. Only SS[10:0] are compared */
|
|
||||||
#define RTC_ALARMSUBSECONDMASK_SS14_12 (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:12] not used in Alarm
|
|
||||||
comparison.Only SS[11:0] are compared */
|
|
||||||
#define RTC_ALARMSUBSECONDMASK_SS14_13 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:13] not used in Alarm
|
|
||||||
comparison. Only SS[12:0] are compared */
|
|
||||||
#define RTC_ALARMSUBSECONDMASK_SS14 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14] not used in Alarm
|
|
||||||
comparison. Only SS[13:0] are compared */
|
|
||||||
#define RTC_ALARMSUBSECONDMASK_NONE RTC_ALRMASSR_MASKSS /*!< SS[14:0] are compared and must match
|
|
||||||
to activate alarm. */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define RTC_IT_TS RTC_CR_TSIE /*!< Enable Timestamp Interrupt */
|
|
||||||
#define RTC_IT_WUT RTC_CR_WUTIE /*!< Enable Wakeup timer Interrupt */
|
|
||||||
#define RTC_IT_SSRU RTC_CR_SSRUIE /*!< Enable SSR Underflow Interrupt */
|
|
||||||
#define RTC_IT_ALRA RTC_CR_ALRAIE /*!< Enable Alarm A Interrupt */
|
|
||||||
#define RTC_IT_ALRB RTC_CR_ALRBIE /*!< Enable Alarm B Interrupt */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RTC_Flag_Mask RTC Flag Mask (5bits) describe in RTC_Flags_Definitions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define RTC_FLAG_MASK 0x001Fu /*!< RTC flags mask (5bits) */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RTC_Flags_Definitions RTC Flags Definitions
|
|
||||||
* Elements values convention: 000000XX000YYYYYb
|
|
||||||
* - YYYYY : Interrupt flag position in the XX register (5bits)
|
|
||||||
* - XX : Interrupt status register (2bits)
|
|
||||||
* - 01: ICSR register
|
|
||||||
* - 10: SR or SCR or MISR or SMISR registers
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define RTC_FLAG_RECALPF (0x00000100U | RTC_ICSR_RECALPF_Pos) /*!< Recalibration pending Flag */
|
|
||||||
#define RTC_FLAG_INITF (0x00000100U | RTC_ICSR_INITF_Pos) /*!< Initialization flag */
|
|
||||||
#define RTC_FLAG_RSF (0x00000100U | RTC_ICSR_RSF_Pos) /*!< Registers synchronization flag */
|
|
||||||
#define RTC_FLAG_INITS (0x00000100U | RTC_ICSR_INITS_Pos) /*!< Initialization status flag */
|
|
||||||
#define RTC_FLAG_SHPF (0x00000100U | RTC_ICSR_SHPF_Pos) /*!< Shift operation pending flag */
|
|
||||||
#define RTC_FLAG_WUTWF (0x00000100U | RTC_ICSR_WUTWF_Pos) /*!< Wakeup timer write flag */
|
|
||||||
#define RTC_FLAG_SSRUF (0x00000200U | RTC_SR_SSRUF_Pos) /*!< SSR underflow flag */
|
|
||||||
#define RTC_FLAG_ITSF (0x00000200U | RTC_SR_ITSF_Pos) /*!< Internal Time-stamp flag */
|
|
||||||
#define RTC_FLAG_TSOVF (0x00000200U | RTC_SR_TSOVF_Pos) /*!< Time-stamp overflow flag */
|
|
||||||
#define RTC_FLAG_TSF (0x00000200U | RTC_SR_TSF_Pos) /*!< Time-stamp flag */
|
|
||||||
#define RTC_FLAG_WUTF (0x00000200U | RTC_SR_WUTF_Pos) /*!< Wakeup timer flag */
|
|
||||||
#define RTC_FLAG_ALRBF (0x00000200U | RTC_SR_ALRBF_Pos) /*!< Alarm B flag */
|
|
||||||
#define RTC_FLAG_ALRAF (0x00000200U | RTC_SR_ALRAF_Pos) /*!< Alarm A flag */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RTC_Clear_Flags_Definitions RTC Clear Flags Definitions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define RTC_CLEAR_SSRUF RTC_SCR_CSSRUF /*!< Clear SSR underflow flag */
|
|
||||||
#define RTC_CLEAR_ITSF RTC_SCR_CITSF /*!< Clear Internal Time-stamp flag */
|
|
||||||
#define RTC_CLEAR_TSOVF RTC_SCR_CTSOVF /*!< Clear Time-stamp overflow flag */
|
|
||||||
#define RTC_CLEAR_TSF RTC_SCR_CTSF /*!< Clear Time-stamp flag */
|
|
||||||
#define RTC_CLEAR_WUTF RTC_SCR_CWUTF /*!< Clear Wakeup timer flag */
|
|
||||||
#define RTC_CLEAR_ALRBF RTC_SCR_CALRBF /*!< Clear Alarm B flag */
|
|
||||||
#define RTC_CLEAR_ALRAF RTC_SCR_CALRAF /*!< Clear Alarm A flag */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported macros -----------------------------------------------------------*/
|
|
||||||
/** @defgroup RTC_Exported_Macros RTC Exported Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @brief Reset RTC handle state
|
|
||||||
* @param __HANDLE__ RTC handle.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
|
|
||||||
#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do{\
|
|
||||||
(__HANDLE__)->State = HAL_RTC_STATE_RESET;\
|
|
||||||
(__HANDLE__)->MspInitCallback = NULL;\
|
|
||||||
(__HANDLE__)->MspDeInitCallback = NULL;\
|
|
||||||
}while(0)
|
|
||||||
#else
|
|
||||||
#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
|
|
||||||
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the write protection for RTC registers.
|
|
||||||
* @param __HANDLE__ specifies the RTC handle.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \
|
|
||||||
do{ \
|
|
||||||
RTC->WPR = 0xCAU; \
|
|
||||||
RTC->WPR = 0x53U; \
|
|
||||||
} while(0U)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the write protection for RTC registers.
|
|
||||||
* @param __HANDLE__ specifies the RTC handle.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \
|
|
||||||
do{ \
|
|
||||||
RTC->WPR = 0xFFU; \
|
|
||||||
} while(0U)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Add 1 hour (summer time change).
|
|
||||||
* @note This interface is deprecated.
|
|
||||||
* To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions
|
|
||||||
* @param __HANDLE__ specifies the RTC handle.
|
|
||||||
* @param __BKP__ Backup
|
|
||||||
* This parameter can be:
|
|
||||||
* @arg @ref RTC_STOREOPERATION_RESET
|
|
||||||
* @arg @ref RTC_STOREOPERATION_SET
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_RTC_DAYLIGHT_SAVING_TIME_ADD1H(__HANDLE__, __BKP__) \
|
|
||||||
do { \
|
|
||||||
__HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__); \
|
|
||||||
SET_BIT(RTC->CR, RTC_CR_ADD1H); \
|
|
||||||
MODIFY_REG(RTC->CR, RTC_CR_BKP , (__BKP__)); \
|
|
||||||
__HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__); \
|
|
||||||
} while(0);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Subtract 1 hour (winter time change).
|
|
||||||
* @note This interface is deprecated.
|
|
||||||
* To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions
|
|
||||||
* @param __HANDLE__ specifies the RTC handle.
|
|
||||||
* @param __BKP__ Backup
|
|
||||||
* This parameter can be:
|
|
||||||
* @arg @ref RTC_STOREOPERATION_RESET
|
|
||||||
* @arg @ref RTC_STOREOPERATION_SET
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_RTC_DAYLIGHT_SAVING_TIME_SUB1H(__HANDLE__, __BKP__) \
|
|
||||||
do { \
|
|
||||||
__HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__); \
|
|
||||||
SET_BIT(RTC->CR, RTC_CR_SUB1H); \
|
|
||||||
MODIFY_REG(RTC->CR, RTC_CR_BKP , (__BKP__)); \
|
|
||||||
__HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__); \
|
|
||||||
} while(0);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the RTC ALARMA peripheral.
|
|
||||||
* @param __HANDLE__ specifies the RTC handle.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_ALRAE))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the RTC ALARMA peripheral.
|
|
||||||
* @param __HANDLE__ specifies the RTC handle.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_ALRAE))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the RTC ALARMB peripheral.
|
|
||||||
* @param __HANDLE__ specifies the RTC handle.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_ALRBE))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the RTC ALARMB peripheral.
|
|
||||||
* @param __HANDLE__ specifies the RTC handle.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_ALRBE))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the RTC Alarm interrupt.
|
|
||||||
* @param __HANDLE__ specifies the RTC handle.
|
|
||||||
* @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
|
|
||||||
* This parameter can be any combination of the following values:
|
|
||||||
* @arg @ref RTC_IT_ALRA Alarm A interrupt
|
|
||||||
* @arg @ref RTC_IT_ALRB Alarm B interrupt
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (__INTERRUPT__))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the RTC Alarm interrupt.
|
|
||||||
* @param __HANDLE__ specifies the RTC handle.
|
|
||||||
* @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
|
|
||||||
* This parameter can be any combination of the following values:
|
|
||||||
* @arg @ref RTC_IT_ALRA Alarm A interrupt
|
|
||||||
* @arg @ref RTC_IT_ALRB Alarm B interrupt
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(__INTERRUPT__))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Check whether the specified RTC Alarm interrupt has occurred or not.
|
|
||||||
* @param __HANDLE__ specifies the RTC handle.
|
|
||||||
* @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to check.
|
|
||||||
* This parameter can be:
|
|
||||||
* @arg @ref RTC_IT_ALRA Alarm A interrupt
|
|
||||||
* @arg @ref RTC_IT_ALRB Alarm B interrupt
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) ((((RTC->MISR)& ((__INTERRUPT__)>> 12U)) != 0U) ? 1UL : 0UL)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Check whether the specified RTC Alarm interrupt has been enabled or not.
|
|
||||||
* @param __HANDLE__ specifies the RTC handle.
|
|
||||||
* @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to check.
|
|
||||||
* This parameter can be:
|
|
||||||
* @arg @ref RTC_IT_ALRA Alarm A interrupt
|
|
||||||
* @arg @ref RTC_IT_ALRB Alarm B interrupt
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((RTC->CR) & (__INTERRUPT__)) != 0U) ? 1UL : 0UL)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Get the selected RTC Alarms flag status.
|
|
||||||
* @param __HANDLE__ specifies the RTC handle.
|
|
||||||
* @param __FLAG__ specifies the RTC Alarm Flag sources to check.
|
|
||||||
* This parameter can be:
|
|
||||||
* @arg @ref RTC_FLAG_ALRAF
|
|
||||||
* @arg @ref RTC_FLAG_ALRBF
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__)))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Clear the RTC Alarms pending flags.
|
|
||||||
* @param __HANDLE__ specifies the RTC handle.
|
|
||||||
* @param __FLAG__ specifies the RTC Alarm Flag sources to clear.
|
|
||||||
* This parameter can be:
|
|
||||||
* @arg @ref RTC_FLAG_ALRAF
|
|
||||||
* @arg @ref RTC_FLAG_ALRBF
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == RTC_FLAG_ALRAF) ? ((RTC->SCR = (RTC_CLEAR_ALRAF))) : \
|
|
||||||
(RTC->SCR = (RTC_CLEAR_ALRBF)))
|
|
||||||
|
|
||||||
#if defined(CORE_CM0PLUS)
|
|
||||||
#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->C2IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
|
|
||||||
#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->C2IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
|
|
||||||
#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->C2EMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
|
|
||||||
#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->C2EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
|
|
||||||
#else
|
|
||||||
#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
|
|
||||||
#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
|
|
||||||
#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
|
|
||||||
#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
|
|
||||||
#endif
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Include RTC HAL Extended module */
|
|
||||||
#include "stm32wlxx_hal_rtc_ex.h"
|
|
||||||
|
|
||||||
/* Exported functions --------------------------------------------------------*/
|
|
||||||
/** @defgroup RTC_Exported_Functions RTC Exported Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Initialization and de-initialization functions ****************************/
|
|
||||||
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
|
|
||||||
HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
|
|
||||||
|
|
||||||
void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
|
|
||||||
void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
|
|
||||||
|
|
||||||
/* Callbacks Register/UnRegister functions ***********************************/
|
|
||||||
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
|
|
||||||
HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback);
|
|
||||||
HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID);
|
|
||||||
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* RTC Time and Date functions ************************************************/
|
|
||||||
HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
|
|
||||||
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
|
|
||||||
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
|
|
||||||
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
|
|
||||||
void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc);
|
|
||||||
void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc);
|
|
||||||
void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc);
|
|
||||||
void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc);
|
|
||||||
uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* RTC Alarm functions ********************************************************/
|
|
||||||
HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
|
|
||||||
HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
|
|
||||||
HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
|
|
||||||
HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
|
|
||||||
void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
|
|
||||||
HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
|
|
||||||
void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Peripheral Control functions ***********************************************/
|
|
||||||
HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Peripheral State functions *************************************************/
|
|
||||||
HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private types -------------------------------------------------------------*/
|
|
||||||
/* Private variables ---------------------------------------------------------*/
|
|
||||||
/* Private constants ---------------------------------------------------------*/
|
|
||||||
/** @defgroup RTC_Private_Constants RTC Private Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Masks Definition */
|
|
||||||
#define RTC_TR_RESERVED_MASK (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | \
|
|
||||||
RTC_TR_MNT | RTC_TR_MNU| RTC_TR_ST | \
|
|
||||||
RTC_TR_SU)
|
|
||||||
#define RTC_DR_RESERVED_MASK (RTC_DR_YT | RTC_DR_YU | RTC_DR_WDU | \
|
|
||||||
RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | \
|
|
||||||
RTC_DR_DU)
|
|
||||||
#define RTC_INIT_MASK 0xFFFFFFFFu
|
|
||||||
#define RTC_RSF_MASK (~(RTC_ICSR_INIT | RTC_ICSR_RSF))
|
|
||||||
|
|
||||||
#define RTC_TIMEOUT_VALUE 1000u
|
|
||||||
|
|
||||||
#define RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR1_IM17 /*!< External interrupt line 17 Connected to the RTC Alarm event */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private macros ------------------------------------------------------------*/
|
|
||||||
/** @defgroup RTC_Private_Macros RTC Private Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
|
|
||||||
((OUTPUT) == RTC_OUTPUT_ALARMA) || \
|
|
||||||
((OUTPUT) == RTC_OUTPUT_ALARMB) || \
|
|
||||||
((OUTPUT) == RTC_OUTPUT_WAKEUP) || \
|
|
||||||
((OUTPUT) == RTC_OUTPUT_TAMPER))
|
|
||||||
|
|
||||||
#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \
|
|
||||||
((FORMAT) == RTC_HOURFORMAT_24))
|
|
||||||
|
|
||||||
#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
|
|
||||||
((POL) == RTC_OUTPUT_POLARITY_LOW))
|
|
||||||
|
|
||||||
#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
|
|
||||||
((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
|
|
||||||
|
|
||||||
#define IS_RTC_OUTPUT_PULLUP(TYPE) (((TYPE) == RTC_OUTPUT_PULLUP_NONE) || \
|
|
||||||
((TYPE) == RTC_OUTPUT_PULLUP_ON))
|
|
||||||
|
|
||||||
#define IS_RTC_OUTPUT_REMAP(REMAP) (((REMAP) == RTC_OUTPUT_REMAP_NONE) || \
|
|
||||||
((REMAP) == RTC_OUTPUT_REMAP_POS1))
|
|
||||||
|
|
||||||
#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || \
|
|
||||||
((PM) == RTC_HOURFORMAT12_PM))
|
|
||||||
|
|
||||||
#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
|
|
||||||
((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
|
|
||||||
((SAVE) == RTC_DAYLIGHTSAVING_NONE))
|
|
||||||
|
|
||||||
#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
|
|
||||||
((OPERATION) == RTC_STOREOPERATION_SET))
|
|
||||||
|
|
||||||
#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || \
|
|
||||||
((FORMAT) == RTC_FORMAT_BCD))
|
|
||||||
|
|
||||||
#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99u)
|
|
||||||
|
|
||||||
#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1u) && ((MONTH) <= 12u))
|
|
||||||
|
|
||||||
#define IS_RTC_DATE(DATE) (((DATE) >= 1u) && ((DATE) <= 31u))
|
|
||||||
|
|
||||||
#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
|
|
||||||
((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
|
|
||||||
((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
|
|
||||||
((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
|
|
||||||
((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
|
|
||||||
((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
|
|
||||||
((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
|
|
||||||
|
|
||||||
#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >0u) && ((DATE) <= 31u))
|
|
||||||
|
|
||||||
#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
|
|
||||||
((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
|
|
||||||
((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
|
|
||||||
((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
|
|
||||||
((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
|
|
||||||
((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
|
|
||||||
((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
|
|
||||||
|
|
||||||
#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
|
|
||||||
((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
|
|
||||||
|
|
||||||
#define IS_RTC_ALARM_MASK(MASK) (((MASK) & ~(RTC_ALARMMASK_ALL)) == 0UL)
|
|
||||||
|
|
||||||
#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || \
|
|
||||||
((ALARM) == RTC_ALARM_B))
|
|
||||||
|
|
||||||
#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= RTC_ALRMASSR_SS)
|
|
||||||
|
|
||||||
#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == 0UL) || \
|
|
||||||
(((MASK) >= RTC_ALARMSUBSECONDMASK_SS14_1) && ((MASK) <= RTC_ALARMSUBSECONDMASK_NONE)))
|
|
||||||
|
|
||||||
#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (RTC_PRER_PREDIV_A >> RTC_PRER_PREDIV_A_Pos))
|
|
||||||
|
|
||||||
#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (RTC_PRER_PREDIV_S >> RTC_PRER_PREDIV_S_Pos))
|
|
||||||
|
|
||||||
#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0u) && ((HOUR) <= 12u))
|
|
||||||
|
|
||||||
#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23u)
|
|
||||||
|
|
||||||
#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59u)
|
|
||||||
|
|
||||||
#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59u)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private functions -------------------------------------------------------------*/
|
|
||||||
/** @defgroup RTC_Private_Functions RTC Private Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc);
|
|
||||||
HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc);
|
|
||||||
uint8_t RTC_ByteToBcd2(uint8_t Value);
|
|
||||||
uint8_t RTC_Bcd2ToByte(uint8_t Value);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* STM32WLxx_HAL_RTC_H */
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
||||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,338 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32wlxx_hal_smartcard_ex.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief Header file of SMARTCARD HAL Extended module.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
|
||||||
* All rights reserved.</center></h2>
|
|
||||||
*
|
|
||||||
* This software component is licensed by ST under BSD 3-Clause license,
|
|
||||||
* the "License"; You may not use this file except in compliance with the
|
|
||||||
* License. You may obtain a copy of the License at:
|
|
||||||
* opensource.org/licenses/BSD-3-Clause
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef STM32WLxx_HAL_SMARTCARD_EX_H
|
|
||||||
#define STM32WLxx_HAL_SMARTCARD_EX_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32wlxx_hal_def.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32WLxx_HAL_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup SMARTCARDEx
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
|
||||||
|
|
||||||
/** @addtogroup SMARTCARDEx_Exported_Constants SMARTCARD Extended Exported Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SMARTCARDEx_Transmission_Completion_Indication SMARTCARD Transmission Completion Indication
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SMARTCARD_TCBGT SMARTCARD_IT_TCBGT /*!< SMARTCARD transmission complete before guard time */
|
|
||||||
#define SMARTCARD_TC SMARTCARD_IT_TC /*!< SMARTCARD transmission complete (flag raised when guard time has elapsed) */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SMARTCARDEx_Advanced_Features_Initialization_Type SMARTCARD advanced feature initialization type
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SMARTCARD_ADVFEATURE_NO_INIT 0x00000000U /*!< No advanced feature initialization */
|
|
||||||
#define SMARTCARD_ADVFEATURE_TXINVERT_INIT 0x00000001U /*!< TX pin active level inversion */
|
|
||||||
#define SMARTCARD_ADVFEATURE_RXINVERT_INIT 0x00000002U /*!< RX pin active level inversion */
|
|
||||||
#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT 0x00000004U /*!< Binary data inversion */
|
|
||||||
#define SMARTCARD_ADVFEATURE_SWAP_INIT 0x00000008U /*!< TX/RX pins swap */
|
|
||||||
#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U /*!< RX overrun disable */
|
|
||||||
#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U /*!< DMA disable on Reception Error */
|
|
||||||
#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT 0x00000080U /*!< Most significant bit sent/received first */
|
|
||||||
#define SMARTCARD_ADVFEATURE_TXCOMPLETION 0x00000100U /*!< TX completion indication before of after guard time */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SMARTCARDEx_FIFO_mode SMARTCARD FIFO mode
|
|
||||||
* @brief SMARTCARD FIFO mode
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SMARTCARD_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */
|
|
||||||
#define SMARTCARD_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SMARTCARDEx_TXFIFO_threshold_level SMARTCARD TXFIFO threshold level
|
|
||||||
* @brief SMARTCARD TXFIFO level
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SMARTCARD_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TXFIFO reaches 1/8 of its depth */
|
|
||||||
#define SMARTCARD_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TXFIFO reaches 1/4 of its depth */
|
|
||||||
#define SMARTCARD_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TXFIFO reaches 1/2 of its depth */
|
|
||||||
#define SMARTCARD_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */
|
|
||||||
#define SMARTCARD_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TXFIFO reaches 7/8 of its depth */
|
|
||||||
#define SMARTCARD_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SMARTCARDEx_RXFIFO_threshold_level SMARTCARD RXFIFO threshold level
|
|
||||||
* @brief SMARTCARD RXFIFO level
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SMARTCARD_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RXFIFO FIFO reaches 1/8 of its depth */
|
|
||||||
#define SMARTCARD_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RXFIFO FIFO reaches 1/4 of its depth */
|
|
||||||
#define SMARTCARD_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RXFIFO FIFO reaches 1/2 of its depth */
|
|
||||||
#define SMARTCARD_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */
|
|
||||||
#define SMARTCARD_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RXFIFO FIFO reaches 7/8 of its depth */
|
|
||||||
#define SMARTCARD_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SMARTCARDEx_Flags SMARTCARD Flags
|
|
||||||
* Elements values convention: 0xXXXX
|
|
||||||
* - 0xXXXX : Flag mask in the ISR register
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SMARTCARD_FLAG_TCBGT USART_ISR_TCBGT /*!< SMARTCARD transmission complete before guard time completion */
|
|
||||||
#define SMARTCARD_FLAG_REACK USART_ISR_REACK /*!< SMARTCARD receive enable acknowledge flag */
|
|
||||||
#define SMARTCARD_FLAG_TEACK USART_ISR_TEACK /*!< SMARTCARD transmit enable acknowledge flag */
|
|
||||||
#define SMARTCARD_FLAG_BUSY USART_ISR_BUSY /*!< SMARTCARD busy flag */
|
|
||||||
#define SMARTCARD_FLAG_EOBF USART_ISR_EOBF /*!< SMARTCARD end of block flag */
|
|
||||||
#define SMARTCARD_FLAG_RTOF USART_ISR_RTOF /*!< SMARTCARD receiver timeout flag */
|
|
||||||
#define SMARTCARD_FLAG_TXE USART_ISR_TXE_TXFNF /*!< SMARTCARD transmit data register empty */
|
|
||||||
#define SMARTCARD_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< SMARTCARD TXFIFO not full */
|
|
||||||
#define SMARTCARD_FLAG_TC USART_ISR_TC /*!< SMARTCARD transmission complete */
|
|
||||||
#define SMARTCARD_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< SMARTCARD read data register not empty */
|
|
||||||
#define SMARTCARD_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< SMARTCARD RXFIFO not empty */
|
|
||||||
#define SMARTCARD_FLAG_IDLE USART_ISR_IDLE /*!< SMARTCARD idle line detection */
|
|
||||||
#define SMARTCARD_FLAG_ORE USART_ISR_ORE /*!< SMARTCARD overrun error */
|
|
||||||
#define SMARTCARD_FLAG_NE USART_ISR_NE /*!< SMARTCARD noise error */
|
|
||||||
#define SMARTCARD_FLAG_FE USART_ISR_FE /*!< SMARTCARD frame error */
|
|
||||||
#define SMARTCARD_FLAG_PE USART_ISR_PE /*!< SMARTCARD parity error */
|
|
||||||
#define SMARTCARD_FLAG_TXFE USART_ISR_TXFE /*!< SMARTCARD TXFIFO Empty flag */
|
|
||||||
#define SMARTCARD_FLAG_RXFF USART_ISR_RXFF /*!< SMARTCARD RXFIFO Full flag */
|
|
||||||
#define SMARTCARD_FLAG_RXFT USART_ISR_RXFT /*!< SMARTCARD RXFIFO threshold flag */
|
|
||||||
#define SMARTCARD_FLAG_TXFT USART_ISR_TXFT /*!< SMARTCARD TXFIFO threshold flag */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SMARTCARDEx_Interrupt_definition SMARTCARD Interrupts Definition
|
|
||||||
* Elements values convention: 000ZZZZZ0XXYYYYYb
|
|
||||||
* - YYYYY : Interrupt source position in the XX register (5 bits)
|
|
||||||
* - XX : Interrupt source register (2 bits)
|
|
||||||
* - 01: CR1 register
|
|
||||||
* - 10: CR2 register
|
|
||||||
* - 11: CR3 register
|
|
||||||
* - ZZZZZ : Flag position in the ISR register(5 bits)
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SMARTCARD_IT_PE 0x0028U /*!< SMARTCARD parity error interruption */
|
|
||||||
#define SMARTCARD_IT_TXE 0x0727U /*!< SMARTCARD transmit data register empty interruption */
|
|
||||||
#define SMARTCARD_IT_TXFNF 0x0727U /*!< SMARTCARD TX FIFO not full interruption */
|
|
||||||
#define SMARTCARD_IT_TC 0x0626U /*!< SMARTCARD transmission complete interruption */
|
|
||||||
#define SMARTCARD_IT_RXNE 0x0525U /*!< SMARTCARD read data register not empty interruption */
|
|
||||||
#define SMARTCARD_IT_RXFNE 0x0525U /*!< SMARTCARD RXFIFO not empty interruption */
|
|
||||||
#define SMARTCARD_IT_IDLE 0x0424U /*!< SMARTCARD idle line detection interruption */
|
|
||||||
|
|
||||||
#define SMARTCARD_IT_ERR 0x0060U /*!< SMARTCARD error interruption */
|
|
||||||
#define SMARTCARD_IT_ORE 0x0300U /*!< SMARTCARD overrun error interruption */
|
|
||||||
#define SMARTCARD_IT_NE 0x0200U /*!< SMARTCARD noise error interruption */
|
|
||||||
#define SMARTCARD_IT_FE 0x0100U /*!< SMARTCARD frame error interruption */
|
|
||||||
|
|
||||||
#define SMARTCARD_IT_EOB 0x0C3BU /*!< SMARTCARD end of block interruption */
|
|
||||||
#define SMARTCARD_IT_RTO 0x0B3AU /*!< SMARTCARD receiver timeout interruption */
|
|
||||||
#define SMARTCARD_IT_TCBGT 0x1978U /*!< SMARTCARD transmission complete before guard time completion interruption */
|
|
||||||
|
|
||||||
#define SMARTCARD_IT_RXFF 0x183FU /*!< SMARTCARD RXFIFO full interruption */
|
|
||||||
#define SMARTCARD_IT_TXFE 0x173EU /*!< SMARTCARD TXFIFO empty interruption */
|
|
||||||
#define SMARTCARD_IT_RXFT 0x1A7CU /*!< SMARTCARD RXFIFO threshold reached interruption */
|
|
||||||
#define SMARTCARD_IT_TXFT 0x1B77U /*!< SMARTCARD TXFIFO threshold reached interruption */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SMARTCARDEx_IT_CLEAR_Flags SMARTCARD Interruption Clear Flags
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SMARTCARD_CLEAR_PEF USART_ICR_PECF /*!< SMARTCARD parity error clear flag */
|
|
||||||
#define SMARTCARD_CLEAR_FEF USART_ICR_FECF /*!< SMARTCARD framing error clear flag */
|
|
||||||
#define SMARTCARD_CLEAR_NEF USART_ICR_NECF /*!< SMARTCARD noise error detected clear flag */
|
|
||||||
#define SMARTCARD_CLEAR_OREF USART_ICR_ORECF /*!< SMARTCARD overrun error clear flag */
|
|
||||||
#define SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF /*!< SMARTCARD idle line detected clear flag */
|
|
||||||
#define SMARTCARD_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO empty Clear Flag */
|
|
||||||
#define SMARTCARD_CLEAR_TCF USART_ICR_TCCF /*!< SMARTCARD transmission complete clear flag */
|
|
||||||
#define SMARTCARD_CLEAR_TCBGTF USART_ICR_TCBGTCF /*!< SMARTCARD transmission complete before guard time completion clear flag */
|
|
||||||
#define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF /*!< SMARTCARD receiver time out clear flag */
|
|
||||||
#define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF /*!< SMARTCARD end of block clear flag */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
/* Exported macros -----------------------------------------------------------*/
|
|
||||||
/* Private macros ------------------------------------------------------------*/
|
|
||||||
/** @defgroup SMARTCARDEx_Private_Macros SMARTCARD Extended Private Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @brief Set the Transmission Completion flag
|
|
||||||
* @param __HANDLE__ specifies the SMARTCARD Handle.
|
|
||||||
* @note If TCBGT (Transmission Complete Before Guard Time) flag is not available or if
|
|
||||||
* AdvancedInit.TxCompletionIndication is not already filled, the latter is forced
|
|
||||||
* to SMARTCARD_TC (transmission completion indication when guard time has elapsed).
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__) \
|
|
||||||
do { \
|
|
||||||
if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION)) \
|
|
||||||
{ \
|
|
||||||
(__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \
|
|
||||||
} \
|
|
||||||
else \
|
|
||||||
{ \
|
|
||||||
assert_param(IS_SMARTCARD_TRANSMISSION_COMPLETION((__HANDLE__)->AdvancedInit.TxCompletionIndication)); \
|
|
||||||
} \
|
|
||||||
} while(0U)
|
|
||||||
|
|
||||||
/** @brief Return the transmission completion flag.
|
|
||||||
* @param __HANDLE__ specifies the SMARTCARD Handle.
|
|
||||||
* @note Based on AdvancedInit.TxCompletionIndication setting, return TC or TCBGT flag.
|
|
||||||
* When TCBGT flag (Transmission Complete Before Guard Time) is not available, TC flag is
|
|
||||||
* reported.
|
|
||||||
* @retval Transmission completion flag
|
|
||||||
*/
|
|
||||||
#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) \
|
|
||||||
(((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) : (SMARTCARD_FLAG_TCBGT))
|
|
||||||
|
|
||||||
|
|
||||||
/** @brief Ensure that SMARTCARD frame transmission completion used flag is valid.
|
|
||||||
* @param __TXCOMPLETE__ SMARTCARD frame transmission completion used flag.
|
|
||||||
* @retval SET (__TXCOMPLETE__ is valid) or RESET (__TXCOMPLETE__ is invalid)
|
|
||||||
*/
|
|
||||||
#define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) (((__TXCOMPLETE__) == SMARTCARD_TCBGT) || \
|
|
||||||
((__TXCOMPLETE__) == SMARTCARD_TC))
|
|
||||||
|
|
||||||
/** @brief Ensure that SMARTCARD FIFO mode is valid.
|
|
||||||
* @param __STATE__ SMARTCARD FIFO mode.
|
|
||||||
* @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
|
|
||||||
*/
|
|
||||||
#define IS_SMARTCARD_FIFOMODE_STATE(__STATE__) (((__STATE__) == SMARTCARD_FIFOMODE_DISABLE ) || \
|
|
||||||
((__STATE__) == SMARTCARD_FIFOMODE_ENABLE))
|
|
||||||
|
|
||||||
/** @brief Ensure that SMARTCARD TXFIFO threshold level is valid.
|
|
||||||
* @param __THRESHOLD__ SMARTCARD TXFIFO threshold level.
|
|
||||||
* @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
|
|
||||||
*/
|
|
||||||
#define IS_SMARTCARD_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_8) || \
|
|
||||||
((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_4) || \
|
|
||||||
((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_2) || \
|
|
||||||
((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_3_4) || \
|
|
||||||
((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_7_8) || \
|
|
||||||
((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_8_8))
|
|
||||||
|
|
||||||
/** @brief Ensure that SMARTCARD RXFIFO threshold level is valid.
|
|
||||||
* @param __THRESHOLD__ SMARTCARD RXFIFO threshold level.
|
|
||||||
* @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
|
|
||||||
*/
|
|
||||||
#define IS_SMARTCARD_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_8) || \
|
|
||||||
((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_4) || \
|
|
||||||
((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_2) || \
|
|
||||||
((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_3_4) || \
|
|
||||||
((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_7_8) || \
|
|
||||||
((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_8_8))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported functions --------------------------------------------------------*/
|
|
||||||
/** @addtogroup SMARTCARDEx_Exported_Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Initialization and de-initialization functions ****************************/
|
|
||||||
/* IO operation methods *******************************************************/
|
|
||||||
|
|
||||||
/** @addtogroup SMARTCARDEx_Exported_Functions_Group1
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Peripheral Control functions ***********************************************/
|
|
||||||
void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength);
|
|
||||||
void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue);
|
|
||||||
HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
|
|
||||||
HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported functions --------------------------------------------------------*/
|
|
||||||
/** @addtogroup SMARTCARDEx_Exported_Functions_Group2
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* IO operation functions *****************************************************/
|
|
||||||
void HAL_SMARTCARDEx_RxFifoFullCallback(SMARTCARD_HandleTypeDef *hsmartcard);
|
|
||||||
void HAL_SMARTCARDEx_TxFifoEmptyCallback(SMARTCARD_HandleTypeDef *hsmartcard);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup SMARTCARDEx_Exported_Functions_Group3
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Peripheral Control functions ***********************************************/
|
|
||||||
HAL_StatusTypeDef HAL_SMARTCARDEx_EnableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard);
|
|
||||||
HAL_StatusTypeDef HAL_SMARTCARDEx_DisableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard);
|
|
||||||
HAL_StatusTypeDef HAL_SMARTCARDEx_SetTxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold);
|
|
||||||
HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private functions ---------------------------------------------------------*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* STM32WLxx_HAL_SMARTCARD_EX_H */
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,789 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32wlxx_hal_smbus.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief Header file of SMBUS HAL module.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
|
||||||
* All rights reserved.</center></h2>
|
|
||||||
*
|
|
||||||
* This software component is licensed by ST under BSD 3-Clause license,
|
|
||||||
* the "License"; You may not use this file except in compliance with the
|
|
||||||
* License. You may obtain a copy of the License at:
|
|
||||||
* opensource.org/licenses/BSD-3-Clause
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef STM32WLxx_HAL_SMBUS_H
|
|
||||||
#define STM32WLxx_HAL_SMBUS_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32wlxx_hal_def.h"
|
|
||||||
#include "stm32wlxx_hal_smbus_ex.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32WLxx_HAL_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup SMBUS
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
/** @defgroup SMBUS_Exported_Types SMBUS Exported Types
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition
|
|
||||||
* @brief SMBUS Configuration Structure definition
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value.
|
|
||||||
This parameter calculated by referring to SMBUS initialization section
|
|
||||||
in Reference manual */
|
|
||||||
uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not.
|
|
||||||
This parameter can be a value of @ref SMBUS_Analog_Filter */
|
|
||||||
|
|
||||||
uint32_t OwnAddress1; /*!< Specifies the first device own address.
|
|
||||||
This parameter can be a 7-bit or 10-bit address. */
|
|
||||||
|
|
||||||
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected.
|
|
||||||
This parameter can be a value of @ref SMBUS_addressing_mode */
|
|
||||||
|
|
||||||
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
|
|
||||||
This parameter can be a value of @ref SMBUS_dual_addressing_mode */
|
|
||||||
|
|
||||||
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
|
|
||||||
This parameter can be a 7-bit address. */
|
|
||||||
|
|
||||||
uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address
|
|
||||||
if dual addressing mode is selected
|
|
||||||
This parameter can be a value of @ref SMBUS_own_address2_masks. */
|
|
||||||
|
|
||||||
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
|
|
||||||
This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */
|
|
||||||
|
|
||||||
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
|
|
||||||
This parameter can be a value of @ref SMBUS_nostretch_mode */
|
|
||||||
|
|
||||||
uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected.
|
|
||||||
This parameter can be a value of @ref SMBUS_packet_error_check_mode */
|
|
||||||
|
|
||||||
uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected.
|
|
||||||
This parameter can be a value of @ref SMBUS_peripheral_mode */
|
|
||||||
|
|
||||||
uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value.
|
|
||||||
(Enable bits and different timeout values)
|
|
||||||
This parameter calculated by referring to SMBUS initialization section
|
|
||||||
in Reference manual */
|
|
||||||
} SMBUS_InitTypeDef;
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup HAL_state_definition HAL state definition
|
|
||||||
* @brief HAL State definition
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define HAL_SMBUS_STATE_RESET (0x00000000U) /*!< SMBUS not yet initialized or disabled */
|
|
||||||
#define HAL_SMBUS_STATE_READY (0x00000001U) /*!< SMBUS initialized and ready for use */
|
|
||||||
#define HAL_SMBUS_STATE_BUSY (0x00000002U) /*!< SMBUS internal process is ongoing */
|
|
||||||
#define HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */
|
|
||||||
#define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */
|
|
||||||
#define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */
|
|
||||||
#define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */
|
|
||||||
#define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */
|
|
||||||
#define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */
|
|
||||||
#define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition
|
|
||||||
* @brief SMBUS Error Code definition
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define HAL_SMBUS_ERROR_NONE (0x00000000U) /*!< No error */
|
|
||||||
#define HAL_SMBUS_ERROR_BERR (0x00000001U) /*!< BERR error */
|
|
||||||
#define HAL_SMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */
|
|
||||||
#define HAL_SMBUS_ERROR_ACKF (0x00000004U) /*!< ACKF error */
|
|
||||||
#define HAL_SMBUS_ERROR_OVR (0x00000008U) /*!< OVR error */
|
|
||||||
#define HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U) /*!< Timeout error */
|
|
||||||
#define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */
|
|
||||||
#define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */
|
|
||||||
#define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */
|
|
||||||
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
|
|
||||||
#define HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */
|
|
||||||
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
|
|
||||||
#define HAL_SMBUS_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition
|
|
||||||
* @brief SMBUS handle Structure definition
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
|
|
||||||
typedef struct __SMBUS_HandleTypeDef
|
|
||||||
#else
|
|
||||||
typedef struct
|
|
||||||
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
|
|
||||||
{
|
|
||||||
I2C_TypeDef *Instance; /*!< SMBUS registers base address */
|
|
||||||
|
|
||||||
SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */
|
|
||||||
|
|
||||||
uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */
|
|
||||||
|
|
||||||
uint16_t XferSize; /*!< SMBUS transfer size */
|
|
||||||
|
|
||||||
__IO uint16_t XferCount; /*!< SMBUS transfer counter */
|
|
||||||
|
|
||||||
__IO uint32_t XferOptions; /*!< SMBUS transfer options */
|
|
||||||
|
|
||||||
__IO uint32_t PreviousState; /*!< SMBUS communication Previous state */
|
|
||||||
|
|
||||||
HAL_LockTypeDef Lock; /*!< SMBUS locking object */
|
|
||||||
|
|
||||||
__IO uint32_t State; /*!< SMBUS communication state */
|
|
||||||
|
|
||||||
__IO uint32_t ErrorCode; /*!< SMBUS Error code */
|
|
||||||
|
|
||||||
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
|
|
||||||
void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
|
|
||||||
/*!< SMBUS Master Tx Transfer completed callback */
|
|
||||||
void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
|
|
||||||
/*!< SMBUS Master Rx Transfer completed callback */
|
|
||||||
void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
|
|
||||||
/*!< SMBUS Slave Tx Transfer completed callback */
|
|
||||||
void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
|
|
||||||
/*!< SMBUS Slave Rx Transfer completed callback */
|
|
||||||
void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
|
|
||||||
/*!< SMBUS Listen Complete callback */
|
|
||||||
void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
|
|
||||||
/*!< SMBUS Error callback */
|
|
||||||
|
|
||||||
void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
|
|
||||||
/*!< SMBUS Slave Address Match callback */
|
|
||||||
|
|
||||||
void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
|
|
||||||
/*!< SMBUS Msp Init callback */
|
|
||||||
void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
|
|
||||||
/*!< SMBUS Msp DeInit callback */
|
|
||||||
|
|
||||||
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
|
|
||||||
} SMBUS_HandleTypeDef;
|
|
||||||
|
|
||||||
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
|
|
||||||
/**
|
|
||||||
* @brief HAL SMBUS Callback ID enumeration definition
|
|
||||||
*/
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< SMBUS Master Tx Transfer completed callback ID */
|
|
||||||
HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< SMBUS Master Rx Transfer completed callback ID */
|
|
||||||
HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< SMBUS Slave Tx Transfer completed callback ID */
|
|
||||||
HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< SMBUS Slave Rx Transfer completed callback ID */
|
|
||||||
HAL_SMBUS_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< SMBUS Listen Complete callback ID */
|
|
||||||
HAL_SMBUS_ERROR_CB_ID = 0x05U, /*!< SMBUS Error callback ID */
|
|
||||||
|
|
||||||
HAL_SMBUS_MSPINIT_CB_ID = 0x06U, /*!< SMBUS Msp Init callback ID */
|
|
||||||
HAL_SMBUS_MSPDEINIT_CB_ID = 0x07U /*!< SMBUS Msp DeInit callback ID */
|
|
||||||
|
|
||||||
} HAL_SMBUS_CallbackIDTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief HAL SMBUS Callback pointer definition
|
|
||||||
*/
|
|
||||||
typedef void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus);
|
|
||||||
/*!< pointer to an SMBUS callback function */
|
|
||||||
typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection,
|
|
||||||
uint16_t AddrMatchCode);
|
|
||||||
/*!< pointer to an SMBUS Address Match callback function */
|
|
||||||
|
|
||||||
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
|
||||||
|
|
||||||
/** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SMBUS_ANALOGFILTER_ENABLE (0x00000000U)
|
|
||||||
#define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SMBUS_addressing_mode SMBUS addressing mode
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SMBUS_ADDRESSINGMODE_7BIT (0x00000001U)
|
|
||||||
#define SMBUS_ADDRESSINGMODE_10BIT (0x00000002U)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define SMBUS_DUALADDRESS_DISABLE (0x00000000U)
|
|
||||||
#define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SMBUS_own_address2_masks SMBUS ownaddress2 masks
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define SMBUS_OA2_NOMASK ((uint8_t)0x00U)
|
|
||||||
#define SMBUS_OA2_MASK01 ((uint8_t)0x01U)
|
|
||||||
#define SMBUS_OA2_MASK02 ((uint8_t)0x02U)
|
|
||||||
#define SMBUS_OA2_MASK03 ((uint8_t)0x03U)
|
|
||||||
#define SMBUS_OA2_MASK04 ((uint8_t)0x04U)
|
|
||||||
#define SMBUS_OA2_MASK05 ((uint8_t)0x05U)
|
|
||||||
#define SMBUS_OA2_MASK06 ((uint8_t)0x06U)
|
|
||||||
#define SMBUS_OA2_MASK07 ((uint8_t)0x07U)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SMBUS_GENERALCALL_DISABLE (0x00000000U)
|
|
||||||
#define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SMBUS_NOSTRETCH_DISABLE (0x00000000U)
|
|
||||||
#define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SMBUS_PEC_DISABLE (0x00000000U)
|
|
||||||
#define SMBUS_PEC_ENABLE I2C_CR1_PECEN
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN
|
|
||||||
#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U)
|
|
||||||
#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define SMBUS_SOFTEND_MODE (0x00000000U)
|
|
||||||
#define SMBUS_RELOAD_MODE I2C_CR2_RELOAD
|
|
||||||
#define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND
|
|
||||||
#define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define SMBUS_NO_STARTSTOP (0x00000000U)
|
|
||||||
#define SMBUS_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
|
|
||||||
#define SMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
|
|
||||||
#define SMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* List of XferOptions in usage of :
|
|
||||||
* 1- Restart condition when direction change
|
|
||||||
* 2- No Restart condition in other use cases
|
|
||||||
*/
|
|
||||||
#define SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE
|
|
||||||
#define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
|
|
||||||
#define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
|
|
||||||
#define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
|
|
||||||
#define SMBUS_FIRST_FRAME_WITH_PEC ((uint32_t)(SMBUS_SOFTEND_MODE | SMBUS_SENDPEC_MODE))
|
|
||||||
#define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
|
|
||||||
#define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
|
|
||||||
|
|
||||||
/* List of XferOptions in usage of :
|
|
||||||
* 1- Restart condition in all use cases (direction change or not)
|
|
||||||
*/
|
|
||||||
#define SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU)
|
|
||||||
#define SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U)
|
|
||||||
#define SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U)
|
|
||||||
#define SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition
|
|
||||||
* @brief SMBUS Interrupt definition
|
|
||||||
* Elements values convention: 0xXXXXXXXX
|
|
||||||
* - XXXXXXXX : Interrupt control mask
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SMBUS_IT_ERRI I2C_CR1_ERRIE
|
|
||||||
#define SMBUS_IT_TCI I2C_CR1_TCIE
|
|
||||||
#define SMBUS_IT_STOPI I2C_CR1_STOPIE
|
|
||||||
#define SMBUS_IT_NACKI I2C_CR1_NACKIE
|
|
||||||
#define SMBUS_IT_ADDRI I2C_CR1_ADDRIE
|
|
||||||
#define SMBUS_IT_RXI I2C_CR1_RXIE
|
|
||||||
#define SMBUS_IT_TXI I2C_CR1_TXIE
|
|
||||||
#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | \
|
|
||||||
SMBUS_IT_NACKI | SMBUS_IT_TXI)
|
|
||||||
#define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | \
|
|
||||||
SMBUS_IT_RXI)
|
|
||||||
#define SMBUS_IT_ALERT (SMBUS_IT_ERRI)
|
|
||||||
#define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SMBUS_Flag_definition SMBUS Flag definition
|
|
||||||
* @brief Flag definition
|
|
||||||
* Elements values convention: 0xXXXXYYYY
|
|
||||||
* - XXXXXXXX : Flag mask
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define SMBUS_FLAG_TXE I2C_ISR_TXE
|
|
||||||
#define SMBUS_FLAG_TXIS I2C_ISR_TXIS
|
|
||||||
#define SMBUS_FLAG_RXNE I2C_ISR_RXNE
|
|
||||||
#define SMBUS_FLAG_ADDR I2C_ISR_ADDR
|
|
||||||
#define SMBUS_FLAG_AF I2C_ISR_NACKF
|
|
||||||
#define SMBUS_FLAG_STOPF I2C_ISR_STOPF
|
|
||||||
#define SMBUS_FLAG_TC I2C_ISR_TC
|
|
||||||
#define SMBUS_FLAG_TCR I2C_ISR_TCR
|
|
||||||
#define SMBUS_FLAG_BERR I2C_ISR_BERR
|
|
||||||
#define SMBUS_FLAG_ARLO I2C_ISR_ARLO
|
|
||||||
#define SMBUS_FLAG_OVR I2C_ISR_OVR
|
|
||||||
#define SMBUS_FLAG_PECERR I2C_ISR_PECERR
|
|
||||||
#define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT
|
|
||||||
#define SMBUS_FLAG_ALERT I2C_ISR_ALERT
|
|
||||||
#define SMBUS_FLAG_BUSY I2C_ISR_BUSY
|
|
||||||
#define SMBUS_FLAG_DIR I2C_ISR_DIR
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported macros ------------------------------------------------------------*/
|
|
||||||
/** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @brief Reset SMBUS handle state.
|
|
||||||
* @param __HANDLE__ specifies the SMBUS Handle.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
|
|
||||||
#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
|
||||||
(__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \
|
|
||||||
(__HANDLE__)->MspInitCallback = NULL; \
|
|
||||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
|
||||||
} while(0)
|
|
||||||
#else
|
|
||||||
#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
|
|
||||||
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
|
|
||||||
|
|
||||||
/** @brief Enable the specified SMBUS interrupts.
|
|
||||||
* @param __HANDLE__ specifies the SMBUS Handle.
|
|
||||||
* @param __INTERRUPT__ specifies the interrupt source to enable.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg @ref SMBUS_IT_ERRI Errors interrupt enable
|
|
||||||
* @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable
|
|
||||||
* @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
|
|
||||||
* @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
|
|
||||||
* @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
|
|
||||||
* @arg @ref SMBUS_IT_RXI RX interrupt enable
|
|
||||||
* @arg @ref SMBUS_IT_TXI TX interrupt enable
|
|
||||||
*
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
|
|
||||||
|
|
||||||
/** @brief Disable the specified SMBUS interrupts.
|
|
||||||
* @param __HANDLE__ specifies the SMBUS Handle.
|
|
||||||
* @param __INTERRUPT__ specifies the interrupt source to disable.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg @ref SMBUS_IT_ERRI Errors interrupt enable
|
|
||||||
* @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable
|
|
||||||
* @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
|
|
||||||
* @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
|
|
||||||
* @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
|
|
||||||
* @arg @ref SMBUS_IT_RXI RX interrupt enable
|
|
||||||
* @arg @ref SMBUS_IT_TXI TX interrupt enable
|
|
||||||
*
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
|
|
||||||
|
|
||||||
/** @brief Check whether the specified SMBUS interrupt source is enabled or not.
|
|
||||||
* @param __HANDLE__ specifies the SMBUS Handle.
|
|
||||||
* @param __INTERRUPT__ specifies the SMBUS interrupt source to check.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg @ref SMBUS_IT_ERRI Errors interrupt enable
|
|
||||||
* @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable
|
|
||||||
* @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
|
|
||||||
* @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
|
|
||||||
* @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
|
|
||||||
* @arg @ref SMBUS_IT_RXI RX interrupt enable
|
|
||||||
* @arg @ref SMBUS_IT_TXI TX interrupt enable
|
|
||||||
*
|
|
||||||
* @retval The new state of __IT__ (SET or RESET).
|
|
||||||
*/
|
|
||||||
#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
|
|
||||||
((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
|
||||||
|
|
||||||
/** @brief Check whether the specified SMBUS flag is set or not.
|
|
||||||
* @param __HANDLE__ specifies the SMBUS Handle.
|
|
||||||
* @param __FLAG__ specifies the flag to check.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg @ref SMBUS_FLAG_TXE Transmit data register empty
|
|
||||||
* @arg @ref SMBUS_FLAG_TXIS Transmit interrupt status
|
|
||||||
* @arg @ref SMBUS_FLAG_RXNE Receive data register not empty
|
|
||||||
* @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode)
|
|
||||||
* @arg @ref SMBUS_FLAG_AF NACK received flag
|
|
||||||
* @arg @ref SMBUS_FLAG_STOPF STOP detection flag
|
|
||||||
* @arg @ref SMBUS_FLAG_TC Transfer complete (master mode)
|
|
||||||
* @arg @ref SMBUS_FLAG_TCR Transfer complete reload
|
|
||||||
* @arg @ref SMBUS_FLAG_BERR Bus error
|
|
||||||
* @arg @ref SMBUS_FLAG_ARLO Arbitration lost
|
|
||||||
* @arg @ref SMBUS_FLAG_OVR Overrun/Underrun
|
|
||||||
* @arg @ref SMBUS_FLAG_PECERR PEC error in reception
|
|
||||||
* @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
|
|
||||||
* @arg @ref SMBUS_FLAG_ALERT SMBus alert
|
|
||||||
* @arg @ref SMBUS_FLAG_BUSY Bus busy
|
|
||||||
* @arg @ref SMBUS_FLAG_DIR Transfer direction (slave mode)
|
|
||||||
*
|
|
||||||
* @retval The new state of __FLAG__ (SET or RESET).
|
|
||||||
*/
|
|
||||||
#define SMBUS_FLAG_MASK (0x0001FFFFU)
|
|
||||||
#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) \
|
|
||||||
(((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \
|
|
||||||
((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
|
|
||||||
|
|
||||||
/** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
|
|
||||||
* @param __HANDLE__ specifies the SMBUS Handle.
|
|
||||||
* @param __FLAG__ specifies the flag to clear.
|
|
||||||
* This parameter can be any combination of the following values:
|
|
||||||
* @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode)
|
|
||||||
* @arg @ref SMBUS_FLAG_AF NACK received flag
|
|
||||||
* @arg @ref SMBUS_FLAG_STOPF STOP detection flag
|
|
||||||
* @arg @ref SMBUS_FLAG_BERR Bus error
|
|
||||||
* @arg @ref SMBUS_FLAG_ARLO Arbitration lost
|
|
||||||
* @arg @ref SMBUS_FLAG_OVR Overrun/Underrun
|
|
||||||
* @arg @ref SMBUS_FLAG_PECERR PEC error in reception
|
|
||||||
* @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
|
|
||||||
* @arg @ref SMBUS_FLAG_ALERT SMBus alert
|
|
||||||
*
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
|
|
||||||
|
|
||||||
/** @brief Enable the specified SMBUS peripheral.
|
|
||||||
* @param __HANDLE__ specifies the SMBUS Handle.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
|
|
||||||
|
|
||||||
/** @brief Disable the specified SMBUS peripheral.
|
|
||||||
* @param __HANDLE__ specifies the SMBUS Handle.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
|
|
||||||
|
|
||||||
/** @brief Generate a Non-Acknowledge SMBUS peripheral in Slave mode.
|
|
||||||
* @param __HANDLE__ specifies the SMBUS Handle.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/* Private constants ---------------------------------------------------------*/
|
|
||||||
|
|
||||||
/* Private macros ------------------------------------------------------------*/
|
|
||||||
/** @defgroup SMBUS_Private_Macro SMBUS Private Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
|
|
||||||
((FILTER) == SMBUS_ANALOGFILTER_DISABLE))
|
|
||||||
|
|
||||||
#define IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
|
|
||||||
|
|
||||||
#define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \
|
|
||||||
((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
|
|
||||||
|
|
||||||
#define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
|
|
||||||
((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))
|
|
||||||
|
|
||||||
#define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \
|
|
||||||
((MASK) == SMBUS_OA2_MASK01) || \
|
|
||||||
((MASK) == SMBUS_OA2_MASK02) || \
|
|
||||||
((MASK) == SMBUS_OA2_MASK03) || \
|
|
||||||
((MASK) == SMBUS_OA2_MASK04) || \
|
|
||||||
((MASK) == SMBUS_OA2_MASK05) || \
|
|
||||||
((MASK) == SMBUS_OA2_MASK06) || \
|
|
||||||
((MASK) == SMBUS_OA2_MASK07))
|
|
||||||
|
|
||||||
#define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLE) || \
|
|
||||||
((CALL) == SMBUS_GENERALCALL_ENABLE))
|
|
||||||
|
|
||||||
#define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \
|
|
||||||
((STRETCH) == SMBUS_NOSTRETCH_ENABLE))
|
|
||||||
|
|
||||||
#define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \
|
|
||||||
((PEC) == SMBUS_PEC_ENABLE))
|
|
||||||
|
|
||||||
#define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \
|
|
||||||
((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \
|
|
||||||
((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
|
|
||||||
|
|
||||||
#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \
|
|
||||||
((MODE) == SMBUS_AUTOEND_MODE) || \
|
|
||||||
((MODE) == SMBUS_SOFTEND_MODE) || \
|
|
||||||
((MODE) == SMBUS_SENDPEC_MODE) || \
|
|
||||||
((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \
|
|
||||||
((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \
|
|
||||||
((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \
|
|
||||||
((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | \
|
|
||||||
SMBUS_RELOAD_MODE )))
|
|
||||||
|
|
||||||
|
|
||||||
#define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \
|
|
||||||
((REQUEST) == SMBUS_GENERATE_START_READ) || \
|
|
||||||
((REQUEST) == SMBUS_GENERATE_START_WRITE) || \
|
|
||||||
((REQUEST) == SMBUS_NO_STARTSTOP))
|
|
||||||
|
|
||||||
|
|
||||||
#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \
|
|
||||||
((REQUEST) == SMBUS_FIRST_FRAME) || \
|
|
||||||
((REQUEST) == SMBUS_NEXT_FRAME) || \
|
|
||||||
((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
|
|
||||||
((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \
|
|
||||||
((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC) || \
|
|
||||||
((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
|
|
||||||
((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
|
|
||||||
|
|
||||||
#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \
|
|
||||||
((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \
|
|
||||||
((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \
|
|
||||||
((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))
|
|
||||||
|
|
||||||
#define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \
|
|
||||||
(uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | \
|
|
||||||
I2C_CR1_PECEN)))
|
|
||||||
#define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
|
|
||||||
(uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \
|
|
||||||
I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
|
|
||||||
I2C_CR2_RD_WRN)))
|
|
||||||
|
|
||||||
#define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? \
|
|
||||||
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
|
|
||||||
(I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
|
|
||||||
(~I2C_CR2_RD_WRN)) : \
|
|
||||||
(uint32_t)((((uint32_t)(__ADDRESS__) & \
|
|
||||||
(I2C_CR2_SADD)) | (I2C_CR2_ADD10) | \
|
|
||||||
(I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
|
|
||||||
|
|
||||||
#define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)
|
|
||||||
#define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
|
|
||||||
#define SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
|
|
||||||
#define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
|
|
||||||
#define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
|
|
||||||
|
|
||||||
#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \
|
|
||||||
((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
|
|
||||||
#define SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
|
|
||||||
|
|
||||||
#define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
|
|
||||||
#define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported functions --------------------------------------------------------*/
|
|
||||||
/** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Initialization and de-initialization functions ****************************/
|
|
||||||
HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
|
|
||||||
HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus);
|
|
||||||
void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus);
|
|
||||||
void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus);
|
|
||||||
HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter);
|
|
||||||
HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter);
|
|
||||||
|
|
||||||
/* Callbacks Register/UnRegister functions ***********************************/
|
|
||||||
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
|
|
||||||
HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus,
|
|
||||||
HAL_SMBUS_CallbackIDTypeDef CallbackID,
|
|
||||||
pSMBUS_CallbackTypeDef pCallback);
|
|
||||||
HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus,
|
|
||||||
HAL_SMBUS_CallbackIDTypeDef CallbackID);
|
|
||||||
|
|
||||||
HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus,
|
|
||||||
pSMBUS_AddrCallbackTypeDef pCallback);
|
|
||||||
HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus);
|
|
||||||
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* IO operation functions *****************************************************/
|
|
||||||
/** @addtogroup Blocking_mode_Polling Blocking mode Polling
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/******* Blocking mode: Polling */
|
|
||||||
HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials,
|
|
||||||
uint32_t Timeout);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/******* Non-Blocking mode: Interrupt */
|
|
||||||
HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress,
|
|
||||||
uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
|
||||||
HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress,
|
|
||||||
uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
|
||||||
HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);
|
|
||||||
HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
|
|
||||||
uint32_t XferOptions);
|
|
||||||
HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
|
|
||||||
uint32_t XferOptions);
|
|
||||||
|
|
||||||
HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
|
|
||||||
HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
|
|
||||||
HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus);
|
|
||||||
HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
|
|
||||||
void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
|
|
||||||
void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
|
|
||||||
void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
|
|
||||||
void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
|
|
||||||
void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
|
|
||||||
void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
|
|
||||||
void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
|
|
||||||
void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus);
|
|
||||||
void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Peripheral State and Errors functions **************************************************/
|
|
||||||
uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
|
|
||||||
uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private Functions ---------------------------------------------------------*/
|
|
||||||
/** @defgroup SMBUS_Private_Functions SMBUS Private Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Private functions are defined in stm32wlxx_hal_smbus.c file */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
|
|
||||||
#endif /* STM32WLxx_HAL_SMBUS_H */
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,138 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32wlxx_hal_smbus_ex.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief Header file of SMBUS HAL Extended module.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
|
||||||
* All rights reserved.</center></h2>
|
|
||||||
*
|
|
||||||
* This software component is licensed by ST under BSD 3-Clause license,
|
|
||||||
* the "License"; You may not use this file except in compliance with the
|
|
||||||
* License. You may obtain a copy of the License at:
|
|
||||||
* opensource.org/licenses/BSD-3-Clause
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef STM32WLxx_HAL_SMBUS_EX_H
|
|
||||||
#define STM32WLxx_HAL_SMBUS_EX_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32wlxx_hal_def.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32WLxx_HAL_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup SMBUSEx
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
|
||||||
/** @defgroup SMBUSEx_Exported_Constants SMBUS Extended Exported Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SMBUSEx_FastModePlus SMBUS Extended Fast Mode Plus
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SMBUS_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
|
|
||||||
#define SMBUS_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
|
|
||||||
#define SMBUS_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
|
|
||||||
#define SMBUS_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
|
|
||||||
#define SMBUS_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
|
|
||||||
#define SMBUS_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
|
|
||||||
#define SMBUS_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported macro ------------------------------------------------------------*/
|
|
||||||
/** @defgroup SMBUSEx_Exported_Macros SMBUS Extended Exported Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported functions --------------------------------------------------------*/
|
|
||||||
/** @addtogroup SMBUSEx_Exported_Functions SMBUS Extended Exported Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup SMBUSEx_Exported_Functions_Group3 SMBUS Extended FastModePlus Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
void HAL_SMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
|
|
||||||
void HAL_SMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private constants ---------------------------------------------------------*/
|
|
||||||
/** @defgroup SMBUSEx_Private_Constants SMBUS Extended Private Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private macros ------------------------------------------------------------*/
|
|
||||||
/** @defgroup SMBUSEx_Private_Macro SMBUS Extended Private Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define IS_SMBUS_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB6)) == SMBUS_FASTMODEPLUS_PB6) || \
|
|
||||||
(((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB7)) == SMBUS_FASTMODEPLUS_PB7) || \
|
|
||||||
(((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB8)) == SMBUS_FASTMODEPLUS_PB8) || \
|
|
||||||
(((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB9)) == SMBUS_FASTMODEPLUS_PB9) || \
|
|
||||||
(((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C1)) == SMBUS_FASTMODEPLUS_I2C1) || \
|
|
||||||
(((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C2)) == SMBUS_FASTMODEPLUS_I2C2) || \
|
|
||||||
(((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C3)) == SMBUS_FASTMODEPLUS_I2C3))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private Functions ---------------------------------------------------------*/
|
|
||||||
/** @defgroup SMBUSEx_Private_Functions SMBUS Extended Private Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Private functions are defined in stm32wlxx_hal_smbus_ex.c file */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* STM32WLxx_HAL_SMBUS_EX_H */
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,852 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32wlxx_hal_spi.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief Header file of SPI HAL module.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
|
||||||
* All rights reserved.</center></h2>
|
|
||||||
*
|
|
||||||
* This software component is licensed by ST under BSD 3-Clause license,
|
|
||||||
* the "License"; You may not use this file except in compliance with the
|
|
||||||
* License. You may obtain a copy of the License at:
|
|
||||||
* opensource.org/licenses/BSD-3-Clause
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef STM32WLxx_HAL_SPI_H
|
|
||||||
#define STM32WLxx_HAL_SPI_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32wlxx_hal_def.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32WLxx_HAL_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup SPI
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
/** @defgroup SPI_Exported_Types SPI Exported Types
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief SPI Configuration Structure definition
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t Mode; /*!< Specifies the SPI operating mode.
|
|
||||||
This parameter can be a value of @ref SPI_Mode */
|
|
||||||
|
|
||||||
uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.
|
|
||||||
This parameter can be a value of @ref SPI_Direction */
|
|
||||||
|
|
||||||
uint32_t DataSize; /*!< Specifies the SPI data size.
|
|
||||||
This parameter can be a value of @ref SPI_Data_Size */
|
|
||||||
|
|
||||||
uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
|
|
||||||
This parameter can be a value of @ref SPI_Clock_Polarity */
|
|
||||||
|
|
||||||
uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
|
|
||||||
This parameter can be a value of @ref SPI_Clock_Phase */
|
|
||||||
|
|
||||||
uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
|
|
||||||
hardware (NSS pin) or by software using the SSI bit.
|
|
||||||
This parameter can be a value of @ref SPI_Slave_Select_management */
|
|
||||||
|
|
||||||
uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
|
|
||||||
used to configure the transmit and receive SCK clock.
|
|
||||||
This parameter can be a value of @ref SPI_BaudRate_Prescaler
|
|
||||||
@note The communication clock is derived from the master
|
|
||||||
clock. The slave clock does not need to be set. */
|
|
||||||
|
|
||||||
uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
|
|
||||||
This parameter can be a value of @ref SPI_MSB_LSB_transmission */
|
|
||||||
|
|
||||||
uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
|
|
||||||
This parameter can be a value of @ref SPI_TI_mode */
|
|
||||||
|
|
||||||
uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
|
|
||||||
This parameter can be a value of @ref SPI_CRC_Calculation */
|
|
||||||
|
|
||||||
uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
|
|
||||||
This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */
|
|
||||||
|
|
||||||
uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation.
|
|
||||||
CRC Length is only used with Data8 and Data16, not other data size
|
|
||||||
This parameter can be a value of @ref SPI_CRC_length */
|
|
||||||
|
|
||||||
uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not .
|
|
||||||
This parameter can be a value of @ref SPI_NSSP_Mode
|
|
||||||
This mode is activated by the NSSP bit in the SPIx_CR2 register and
|
|
||||||
it takes effect only if the SPI interface is configured as Motorola SPI
|
|
||||||
master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0,
|
|
||||||
CPOL setting is ignored).. */
|
|
||||||
} SPI_InitTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief HAL SPI State structure definition
|
|
||||||
*/
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */
|
|
||||||
HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
|
|
||||||
HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
|
|
||||||
HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
|
|
||||||
HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
|
|
||||||
HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
|
|
||||||
HAL_SPI_STATE_ERROR = 0x06U, /*!< SPI error state */
|
|
||||||
HAL_SPI_STATE_ABORT = 0x07U /*!< SPI abort is ongoing */
|
|
||||||
} HAL_SPI_StateTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief SPI handle Structure definition
|
|
||||||
*/
|
|
||||||
typedef struct __SPI_HandleTypeDef
|
|
||||||
{
|
|
||||||
SPI_TypeDef *Instance; /*!< SPI registers base address */
|
|
||||||
|
|
||||||
SPI_InitTypeDef Init; /*!< SPI communication parameters */
|
|
||||||
|
|
||||||
uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
|
|
||||||
|
|
||||||
uint16_t TxXferSize; /*!< SPI Tx Transfer size */
|
|
||||||
|
|
||||||
__IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */
|
|
||||||
|
|
||||||
uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */
|
|
||||||
|
|
||||||
uint16_t RxXferSize; /*!< SPI Rx Transfer size */
|
|
||||||
|
|
||||||
__IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */
|
|
||||||
|
|
||||||
uint32_t CRCSize; /*!< SPI CRC size used for the transfer */
|
|
||||||
|
|
||||||
void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */
|
|
||||||
|
|
||||||
void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */
|
|
||||||
|
|
||||||
DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */
|
|
||||||
|
|
||||||
DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */
|
|
||||||
|
|
||||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
|
||||||
|
|
||||||
__IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */
|
|
||||||
|
|
||||||
__IO uint32_t ErrorCode; /*!< SPI Error code */
|
|
||||||
|
|
||||||
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
|
|
||||||
void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */
|
|
||||||
void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Completed callback */
|
|
||||||
void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Completed callback */
|
|
||||||
void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Half Completed callback */
|
|
||||||
void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Half Completed callback */
|
|
||||||
void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback */
|
|
||||||
void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */
|
|
||||||
void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */
|
|
||||||
void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */
|
|
||||||
void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */
|
|
||||||
|
|
||||||
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
|
|
||||||
} SPI_HandleTypeDef;
|
|
||||||
|
|
||||||
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
|
|
||||||
/**
|
|
||||||
* @brief HAL SPI Callback ID enumeration definition
|
|
||||||
*/
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
HAL_SPI_TX_COMPLETE_CB_ID = 0x00U, /*!< SPI Tx Completed callback ID */
|
|
||||||
HAL_SPI_RX_COMPLETE_CB_ID = 0x01U, /*!< SPI Rx Completed callback ID */
|
|
||||||
HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02U, /*!< SPI TxRx Completed callback ID */
|
|
||||||
HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< SPI Tx Half Completed callback ID */
|
|
||||||
HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< SPI Rx Half Completed callback ID */
|
|
||||||
HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05U, /*!< SPI TxRx Half Completed callback ID */
|
|
||||||
HAL_SPI_ERROR_CB_ID = 0x06U, /*!< SPI Error callback ID */
|
|
||||||
HAL_SPI_ABORT_CB_ID = 0x07U, /*!< SPI Abort callback ID */
|
|
||||||
HAL_SPI_MSPINIT_CB_ID = 0x08U, /*!< SPI Msp Init callback ID */
|
|
||||||
HAL_SPI_MSPDEINIT_CB_ID = 0x09U /*!< SPI Msp DeInit callback ID */
|
|
||||||
|
|
||||||
} HAL_SPI_CallbackIDTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief HAL SPI Callback pointer definition
|
|
||||||
*/
|
|
||||||
typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */
|
|
||||||
|
|
||||||
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
|
||||||
/** @defgroup SPI_Exported_Constants SPI Exported Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SPI_Error_Code SPI Error Code
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define HAL_SPI_ERROR_NONE (0x00000000U) /*!< No error */
|
|
||||||
#define HAL_SPI_ERROR_MODF (0x00000001U) /*!< MODF error */
|
|
||||||
#define HAL_SPI_ERROR_CRC (0x00000002U) /*!< CRC error */
|
|
||||||
#define HAL_SPI_ERROR_OVR (0x00000004U) /*!< OVR error */
|
|
||||||
#define HAL_SPI_ERROR_FRE (0x00000008U) /*!< FRE error */
|
|
||||||
#define HAL_SPI_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
|
|
||||||
#define HAL_SPI_ERROR_FLAG (0x00000020U) /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */
|
|
||||||
#define HAL_SPI_ERROR_ABORT (0x00000040U) /*!< Error during SPI Abort procedure */
|
|
||||||
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
|
|
||||||
#define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000080U) /*!< Invalid Callback error */
|
|
||||||
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SPI_Mode SPI Mode
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SPI_MODE_SLAVE (0x00000000U)
|
|
||||||
#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SPI_Direction SPI Direction Mode
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SPI_DIRECTION_2LINES (0x00000000U)
|
|
||||||
#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
|
|
||||||
#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SPI_Data_Size SPI Data Size
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SPI_DATASIZE_4BIT (0x00000300U)
|
|
||||||
#define SPI_DATASIZE_5BIT (0x00000400U)
|
|
||||||
#define SPI_DATASIZE_6BIT (0x00000500U)
|
|
||||||
#define SPI_DATASIZE_7BIT (0x00000600U)
|
|
||||||
#define SPI_DATASIZE_8BIT (0x00000700U)
|
|
||||||
#define SPI_DATASIZE_9BIT (0x00000800U)
|
|
||||||
#define SPI_DATASIZE_10BIT (0x00000900U)
|
|
||||||
#define SPI_DATASIZE_11BIT (0x00000A00U)
|
|
||||||
#define SPI_DATASIZE_12BIT (0x00000B00U)
|
|
||||||
#define SPI_DATASIZE_13BIT (0x00000C00U)
|
|
||||||
#define SPI_DATASIZE_14BIT (0x00000D00U)
|
|
||||||
#define SPI_DATASIZE_15BIT (0x00000E00U)
|
|
||||||
#define SPI_DATASIZE_16BIT (0x00000F00U)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SPI_POLARITY_LOW (0x00000000U)
|
|
||||||
#define SPI_POLARITY_HIGH SPI_CR1_CPOL
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SPI_Clock_Phase SPI Clock Phase
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SPI_PHASE_1EDGE (0x00000000U)
|
|
||||||
#define SPI_PHASE_2EDGE SPI_CR1_CPHA
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SPI_Slave_Select_management SPI Slave Select Management
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SPI_NSS_SOFT SPI_CR1_SSM
|
|
||||||
#define SPI_NSS_HARD_INPUT (0x00000000U)
|
|
||||||
#define SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP
|
|
||||||
#define SPI_NSS_PULSE_DISABLE (0x00000000U)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SPI_BAUDRATEPRESCALER_2 (0x00000000U)
|
|
||||||
#define SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0)
|
|
||||||
#define SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1)
|
|
||||||
#define SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)
|
|
||||||
#define SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2)
|
|
||||||
#define SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)
|
|
||||||
#define SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)
|
|
||||||
#define SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SPI_FIRSTBIT_MSB (0x00000000U)
|
|
||||||
#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SPI_TI_mode SPI TI Mode
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SPI_TIMODE_DISABLE (0x00000000U)
|
|
||||||
#define SPI_TIMODE_ENABLE SPI_CR2_FRF
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SPI_CRCCALCULATION_DISABLE (0x00000000U)
|
|
||||||
#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SPI_CRC_length SPI CRC Length
|
|
||||||
* @{
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* SPI_CRC_LENGTH_DATASIZE: aligned with the data size
|
|
||||||
* SPI_CRC_LENGTH_8BIT : CRC 8bit
|
|
||||||
* SPI_CRC_LENGTH_16BIT : CRC 16bit
|
|
||||||
*/
|
|
||||||
#define SPI_CRC_LENGTH_DATASIZE (0x00000000U)
|
|
||||||
#define SPI_CRC_LENGTH_8BIT (0x00000001U)
|
|
||||||
#define SPI_CRC_LENGTH_16BIT (0x00000002U)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold
|
|
||||||
* @{
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF :
|
|
||||||
* RXNE event is generated if the FIFO
|
|
||||||
* level is greater or equal to 1/4(8-bits).
|
|
||||||
* SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO
|
|
||||||
* level is greater or equal to 1/2(16 bits). */
|
|
||||||
#define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH
|
|
||||||
#define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH
|
|
||||||
#define SPI_RXFIFO_THRESHOLD_HF (0x00000000U)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SPI_IT_TXE SPI_CR2_TXEIE
|
|
||||||
#define SPI_IT_RXNE SPI_CR2_RXNEIE
|
|
||||||
#define SPI_IT_ERR SPI_CR2_ERRIE
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SPI_Flags_definition SPI Flags Definition
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
|
|
||||||
#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
|
|
||||||
#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
|
|
||||||
#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
|
|
||||||
#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
|
|
||||||
#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
|
|
||||||
#define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
|
|
||||||
#define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */
|
|
||||||
#define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */
|
|
||||||
#define SPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR\
|
|
||||||
| SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_FTLVL | SPI_SR_FRLVL)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SPI_FTLVL_EMPTY (0x00000000U)
|
|
||||||
#define SPI_FTLVL_QUARTER_FULL (0x00000800U)
|
|
||||||
#define SPI_FTLVL_HALF_FULL (0x00001000U)
|
|
||||||
#define SPI_FTLVL_FULL (0x00001800U)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SPI_FRLVL_EMPTY (0x00000000U)
|
|
||||||
#define SPI_FRLVL_QUARTER_FULL (0x00000200U)
|
|
||||||
#define SPI_FRLVL_HALF_FULL (0x00000400U)
|
|
||||||
#define SPI_FRLVL_FULL (0x00000600U)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported macros -----------------------------------------------------------*/
|
|
||||||
/** @defgroup SPI_Exported_Macros SPI Exported Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @brief Reset SPI handle state.
|
|
||||||
* @param __HANDLE__ specifies the SPI Handle.
|
|
||||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
|
|
||||||
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
|
||||||
(__HANDLE__)->State = HAL_SPI_STATE_RESET; \
|
|
||||||
(__HANDLE__)->MspInitCallback = NULL; \
|
|
||||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
|
||||||
} while(0)
|
|
||||||
#else
|
|
||||||
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
|
|
||||||
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
|
|
||||||
|
|
||||||
/** @brief Enable the specified SPI interrupts.
|
|
||||||
* @param __HANDLE__ specifies the SPI Handle.
|
|
||||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
|
||||||
* @param __INTERRUPT__ specifies the interrupt source to enable.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
|
|
||||||
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
|
|
||||||
* @arg SPI_IT_ERR: Error interrupt enable
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
|
|
||||||
|
|
||||||
/** @brief Disable the specified SPI interrupts.
|
|
||||||
* @param __HANDLE__ specifies the SPI handle.
|
|
||||||
* This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
|
|
||||||
* @param __INTERRUPT__ specifies the interrupt source to disable.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
|
|
||||||
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
|
|
||||||
* @arg SPI_IT_ERR: Error interrupt enable
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
|
|
||||||
|
|
||||||
/** @brief Check whether the specified SPI interrupt source is enabled or not.
|
|
||||||
* @param __HANDLE__ specifies the SPI Handle.
|
|
||||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
|
||||||
* @param __INTERRUPT__ specifies the SPI interrupt source to check.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
|
|
||||||
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
|
|
||||||
* @arg SPI_IT_ERR: Error interrupt enable
|
|
||||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
|
||||||
*/
|
|
||||||
#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\
|
|
||||||
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
|
||||||
|
|
||||||
/** @brief Check whether the specified SPI flag is set or not.
|
|
||||||
* @param __HANDLE__ specifies the SPI Handle.
|
|
||||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
|
||||||
* @param __FLAG__ specifies the flag to check.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg SPI_FLAG_RXNE: Receive buffer not empty flag
|
|
||||||
* @arg SPI_FLAG_TXE: Transmit buffer empty flag
|
|
||||||
* @arg SPI_FLAG_CRCERR: CRC error flag
|
|
||||||
* @arg SPI_FLAG_MODF: Mode fault flag
|
|
||||||
* @arg SPI_FLAG_OVR: Overrun flag
|
|
||||||
* @arg SPI_FLAG_BSY: Busy flag
|
|
||||||
* @arg SPI_FLAG_FRE: Frame format error flag
|
|
||||||
* @arg SPI_FLAG_FTLVL: SPI fifo transmission level
|
|
||||||
* @arg SPI_FLAG_FRLVL: SPI fifo reception level
|
|
||||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
|
||||||
*/
|
|
||||||
#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
|
|
||||||
|
|
||||||
/** @brief Clear the SPI CRCERR pending flag.
|
|
||||||
* @param __HANDLE__ specifies the SPI Handle.
|
|
||||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
|
|
||||||
|
|
||||||
/** @brief Clear the SPI MODF pending flag.
|
|
||||||
* @param __HANDLE__ specifies the SPI Handle.
|
|
||||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
|
|
||||||
do{ \
|
|
||||||
__IO uint32_t tmpreg_modf = 0x00U; \
|
|
||||||
tmpreg_modf = (__HANDLE__)->Instance->SR; \
|
|
||||||
CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \
|
|
||||||
UNUSED(tmpreg_modf); \
|
|
||||||
} while(0U)
|
|
||||||
|
|
||||||
/** @brief Clear the SPI OVR pending flag.
|
|
||||||
* @param __HANDLE__ specifies the SPI Handle.
|
|
||||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
|
|
||||||
do{ \
|
|
||||||
__IO uint32_t tmpreg_ovr = 0x00U; \
|
|
||||||
tmpreg_ovr = (__HANDLE__)->Instance->DR; \
|
|
||||||
tmpreg_ovr = (__HANDLE__)->Instance->SR; \
|
|
||||||
UNUSED(tmpreg_ovr); \
|
|
||||||
} while(0U)
|
|
||||||
|
|
||||||
/** @brief Clear the SPI FRE pending flag.
|
|
||||||
* @param __HANDLE__ specifies the SPI Handle.
|
|
||||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \
|
|
||||||
do{ \
|
|
||||||
__IO uint32_t tmpreg_fre = 0x00U; \
|
|
||||||
tmpreg_fre = (__HANDLE__)->Instance->SR; \
|
|
||||||
UNUSED(tmpreg_fre); \
|
|
||||||
}while(0U)
|
|
||||||
|
|
||||||
/** @brief Enable the SPI peripheral.
|
|
||||||
* @param __HANDLE__ specifies the SPI Handle.
|
|
||||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
|
|
||||||
|
|
||||||
/** @brief Disable the SPI peripheral.
|
|
||||||
* @param __HANDLE__ specifies the SPI Handle.
|
|
||||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private macros ------------------------------------------------------------*/
|
|
||||||
/** @defgroup SPI_Private_Macros SPI Private Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @brief Set the SPI transmit-only mode.
|
|
||||||
* @param __HANDLE__ specifies the SPI Handle.
|
|
||||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
|
|
||||||
|
|
||||||
/** @brief Set the SPI receive-only mode.
|
|
||||||
* @param __HANDLE__ specifies the SPI Handle.
|
|
||||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
|
|
||||||
|
|
||||||
/** @brief Reset the CRC calculation of the SPI.
|
|
||||||
* @param __HANDLE__ specifies the SPI Handle.
|
|
||||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
|
|
||||||
SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)
|
|
||||||
|
|
||||||
/** @brief Check whether the specified SPI flag is set or not.
|
|
||||||
* @param __SR__ copy of SPI SR register.
|
|
||||||
* @param __FLAG__ specifies the flag to check.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg SPI_FLAG_RXNE: Receive buffer not empty flag
|
|
||||||
* @arg SPI_FLAG_TXE: Transmit buffer empty flag
|
|
||||||
* @arg SPI_FLAG_CRCERR: CRC error flag
|
|
||||||
* @arg SPI_FLAG_MODF: Mode fault flag
|
|
||||||
* @arg SPI_FLAG_OVR: Overrun flag
|
|
||||||
* @arg SPI_FLAG_BSY: Busy flag
|
|
||||||
* @arg SPI_FLAG_FRE: Frame format error flag
|
|
||||||
* @arg SPI_FLAG_FTLVL: SPI fifo transmission level
|
|
||||||
* @arg SPI_FLAG_FRLVL: SPI fifo reception level
|
|
||||||
* @retval SET or RESET.
|
|
||||||
*/
|
|
||||||
#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \
|
|
||||||
((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
|
|
||||||
|
|
||||||
/** @brief Check whether the specified SPI Interrupt is set or not.
|
|
||||||
* @param __CR2__ copy of SPI CR2 register.
|
|
||||||
* @param __INTERRUPT__ specifies the SPI interrupt source to check.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
|
|
||||||
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
|
|
||||||
* @arg SPI_IT_ERR: Error interrupt enable
|
|
||||||
* @retval SET or RESET.
|
|
||||||
*/
|
|
||||||
#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \
|
|
||||||
(__INTERRUPT__)) ? SET : RESET)
|
|
||||||
|
|
||||||
/** @brief Checks if SPI Mode parameter is in allowed range.
|
|
||||||
* @param __MODE__ specifies the SPI Mode.
|
|
||||||
* This parameter can be a value of @ref SPI_Mode
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \
|
|
||||||
((__MODE__) == SPI_MODE_MASTER))
|
|
||||||
|
|
||||||
/** @brief Checks if SPI Direction Mode parameter is in allowed range.
|
|
||||||
* @param __MODE__ specifies the SPI Direction Mode.
|
|
||||||
* This parameter can be a value of @ref SPI_Direction
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \
|
|
||||||
((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \
|
|
||||||
((__MODE__) == SPI_DIRECTION_1LINE))
|
|
||||||
|
|
||||||
/** @brief Checks if SPI Direction Mode parameter is 2 lines.
|
|
||||||
* @param __MODE__ specifies the SPI Direction Mode.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES)
|
|
||||||
|
|
||||||
/** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines.
|
|
||||||
* @param __MODE__ specifies the SPI Direction Mode.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \
|
|
||||||
((__MODE__) == SPI_DIRECTION_1LINE))
|
|
||||||
|
|
||||||
/** @brief Checks if SPI Data Size parameter is in allowed range.
|
|
||||||
* @param __DATASIZE__ specifies the SPI Data Size.
|
|
||||||
* This parameter can be a value of @ref SPI_Data_Size
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \
|
|
||||||
((__DATASIZE__) == SPI_DATASIZE_15BIT) || \
|
|
||||||
((__DATASIZE__) == SPI_DATASIZE_14BIT) || \
|
|
||||||
((__DATASIZE__) == SPI_DATASIZE_13BIT) || \
|
|
||||||
((__DATASIZE__) == SPI_DATASIZE_12BIT) || \
|
|
||||||
((__DATASIZE__) == SPI_DATASIZE_11BIT) || \
|
|
||||||
((__DATASIZE__) == SPI_DATASIZE_10BIT) || \
|
|
||||||
((__DATASIZE__) == SPI_DATASIZE_9BIT) || \
|
|
||||||
((__DATASIZE__) == SPI_DATASIZE_8BIT) || \
|
|
||||||
((__DATASIZE__) == SPI_DATASIZE_7BIT) || \
|
|
||||||
((__DATASIZE__) == SPI_DATASIZE_6BIT) || \
|
|
||||||
((__DATASIZE__) == SPI_DATASIZE_5BIT) || \
|
|
||||||
((__DATASIZE__) == SPI_DATASIZE_4BIT))
|
|
||||||
|
|
||||||
/** @brief Checks if SPI Serial clock steady state parameter is in allowed range.
|
|
||||||
* @param __CPOL__ specifies the SPI serial clock steady state.
|
|
||||||
* This parameter can be a value of @ref SPI_Clock_Polarity
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \
|
|
||||||
((__CPOL__) == SPI_POLARITY_HIGH))
|
|
||||||
|
|
||||||
/** @brief Checks if SPI Clock Phase parameter is in allowed range.
|
|
||||||
* @param __CPHA__ specifies the SPI Clock Phase.
|
|
||||||
* This parameter can be a value of @ref SPI_Clock_Phase
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \
|
|
||||||
((__CPHA__) == SPI_PHASE_2EDGE))
|
|
||||||
|
|
||||||
/** @brief Checks if SPI Slave Select parameter is in allowed range.
|
|
||||||
* @param __NSS__ specifies the SPI Slave Select management parameter.
|
|
||||||
* This parameter can be a value of @ref SPI_Slave_Select_management
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \
|
|
||||||
((__NSS__) == SPI_NSS_HARD_INPUT) || \
|
|
||||||
((__NSS__) == SPI_NSS_HARD_OUTPUT))
|
|
||||||
|
|
||||||
/** @brief Checks if SPI NSS Pulse parameter is in allowed range.
|
|
||||||
* @param __NSSP__ specifies the SPI NSS Pulse Mode parameter.
|
|
||||||
* This parameter can be a value of @ref SPI_NSSP_Mode
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define IS_SPI_NSSP(__NSSP__) (((__NSSP__) == SPI_NSS_PULSE_ENABLE) || \
|
|
||||||
((__NSSP__) == SPI_NSS_PULSE_DISABLE))
|
|
||||||
|
|
||||||
/** @brief Checks if SPI Baudrate prescaler parameter is in allowed range.
|
|
||||||
* @param __PRESCALER__ specifies the SPI Baudrate prescaler.
|
|
||||||
* This parameter can be a value of @ref SPI_BaudRate_Prescaler
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \
|
|
||||||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \
|
|
||||||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \
|
|
||||||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \
|
|
||||||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \
|
|
||||||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \
|
|
||||||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \
|
|
||||||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256))
|
|
||||||
|
|
||||||
/** @brief Checks if SPI MSB LSB transmission parameter is in allowed range.
|
|
||||||
* @param __BIT__ specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit).
|
|
||||||
* This parameter can be a value of @ref SPI_MSB_LSB_transmission
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \
|
|
||||||
((__BIT__) == SPI_FIRSTBIT_LSB))
|
|
||||||
|
|
||||||
/** @brief Checks if SPI TI mode parameter is in allowed range.
|
|
||||||
* @param __MODE__ specifies the SPI TI mode.
|
|
||||||
* This parameter can be a value of @ref SPI_TI_mode
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \
|
|
||||||
((__MODE__) == SPI_TIMODE_ENABLE))
|
|
||||||
|
|
||||||
/** @brief Checks if SPI CRC calculation enabled state is in allowed range.
|
|
||||||
* @param __CALCULATION__ specifies the SPI CRC calculation enable state.
|
|
||||||
* This parameter can be a value of @ref SPI_CRC_Calculation
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \
|
|
||||||
((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE))
|
|
||||||
|
|
||||||
/** @brief Checks if SPI CRC length is in allowed range.
|
|
||||||
* @param __LENGTH__ specifies the SPI CRC length.
|
|
||||||
* This parameter can be a value of @ref SPI_CRC_length
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define IS_SPI_CRC_LENGTH(__LENGTH__) (((__LENGTH__) == SPI_CRC_LENGTH_DATASIZE) || \
|
|
||||||
((__LENGTH__) == SPI_CRC_LENGTH_8BIT) || \
|
|
||||||
((__LENGTH__) == SPI_CRC_LENGTH_16BIT))
|
|
||||||
|
|
||||||
/** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range.
|
|
||||||
* @param __POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation.
|
|
||||||
* This parameter must be a number between Min_Data = 0 and Max_Data = 65535
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \
|
|
||||||
((__POLYNOMIAL__) <= 0xFFFFU) && \
|
|
||||||
(((__POLYNOMIAL__)&0x1U) != 0U))
|
|
||||||
|
|
||||||
/** @brief Checks if DMA handle is valid.
|
|
||||||
* @param __HANDLE__ specifies a DMA Handle.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Include SPI HAL Extended module */
|
|
||||||
#include "stm32wlxx_hal_spi_ex.h"
|
|
||||||
|
|
||||||
/* Exported functions --------------------------------------------------------*/
|
|
||||||
/** @addtogroup SPI_Exported_Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup SPI_Exported_Functions_Group1
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Initialization/de-initialization functions ********************************/
|
|
||||||
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
|
|
||||||
HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
|
|
||||||
void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
|
|
||||||
void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
|
|
||||||
|
|
||||||
/* Callbacks Register/UnRegister functions ***********************************/
|
|
||||||
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
|
|
||||||
HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback);
|
|
||||||
HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID);
|
|
||||||
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup SPI_Exported_Functions_Group2
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* I/O operation functions ***************************************************/
|
|
||||||
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
|
||||||
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
|
||||||
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
|
|
||||||
uint32_t Timeout);
|
|
||||||
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
|
|
||||||
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
|
|
||||||
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
|
|
||||||
uint16_t Size);
|
|
||||||
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
|
|
||||||
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
|
|
||||||
HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
|
|
||||||
uint16_t Size);
|
|
||||||
HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
|
|
||||||
HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
|
|
||||||
HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
|
|
||||||
/* Transfer Abort functions */
|
|
||||||
HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
|
|
||||||
HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
|
|
||||||
|
|
||||||
void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
|
|
||||||
void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
|
|
||||||
void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
|
|
||||||
void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
|
|
||||||
void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
|
|
||||||
void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
|
|
||||||
void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
|
|
||||||
void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
|
|
||||||
void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup SPI_Exported_Functions_Group3
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Peripheral State and Error functions ***************************************/
|
|
||||||
HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
|
|
||||||
uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* STM32WLxx_HAL_SPI_H */
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,75 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32wlxx_hal_spi_ex.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief Header file of SPI HAL Extended module.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
|
||||||
* All rights reserved.</center></h2>
|
|
||||||
*
|
|
||||||
* This software component is licensed by ST under BSD 3-Clause license,
|
|
||||||
* the "License"; You may not use this file except in compliance with the
|
|
||||||
* License. You may obtain a copy of the License at:
|
|
||||||
* opensource.org/licenses/BSD-3-Clause
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef STM32WLxx_HAL_SPI_EX_H
|
|
||||||
#define STM32WLxx_HAL_SPI_EX_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32wlxx_hal_def.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32WLxx_HAL_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup SPIEx
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
|
||||||
/* Exported macros -----------------------------------------------------------*/
|
|
||||||
/* Exported functions --------------------------------------------------------*/
|
|
||||||
/** @addtogroup SPIEx_Exported_Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Initialization and de-initialization functions ****************************/
|
|
||||||
/* IO operation functions *****************************************************/
|
|
||||||
/** @addtogroup SPIEx_Exported_Functions_Group1
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* STM32WLxx_HAL_SPI_EX_H */
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,414 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32wlxx_hal_subghz.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief Header file of SUBGHZ HAL module.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
|
||||||
* All rights reserved.</center></h2>
|
|
||||||
*
|
|
||||||
* This software component is licensed by ST under BSD 3-Clause license,
|
|
||||||
* the "License"; You may not use this file except in compliance with the
|
|
||||||
* License. You may obtain a copy of the License at:
|
|
||||||
* opensource.org/licenses/BSD-3-Clause
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef STM32WLxx_HAL_SUBGHZ_H
|
|
||||||
#define STM32WLxx_HAL_SUBGHZ_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32wlxx_hal_def.h"
|
|
||||||
|
|
||||||
/* Include low level driver */
|
|
||||||
#include "stm32wlxx_ll_spi.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32WLxx_HAL_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup SUBGHZ
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
/** @defgroup SUBGHZ_Exported_Types SUBGHZ Exported Types
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief SPI Configuration Structure definition
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t BaudratePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
|
|
||||||
used to configure SUBGHZSPI clock.
|
|
||||||
This parameter can be a value of @ref SUBGHZ_SPI_BAUDRATE_Prescaler */
|
|
||||||
} SUBGHZ_InitTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief HAL SUBGHZ State structure definition
|
|
||||||
*/
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
HAL_SUBGHZ_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */
|
|
||||||
HAL_SUBGHZ_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
|
|
||||||
HAL_SUBGHZ_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
|
|
||||||
} HAL_SUBGHZ_StateTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief HAL SUBGHZ CAD Status structure definition
|
|
||||||
*/
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
HAL_SUBGHZ_CAD_CLEAR = 0x00U, /*!< Channel activity cleared */
|
|
||||||
HAL_SUBGHZ_CAD_DETECTED = 0x01U, /*!< Channel activity detected */
|
|
||||||
} HAL_SUBGHZ_CadStatusTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief SUBGHZ handle Structure definition
|
|
||||||
*/
|
|
||||||
#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1)
|
|
||||||
typedef struct __SUBGHZ_HandleTypeDef
|
|
||||||
#else
|
|
||||||
typedef struct
|
|
||||||
#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */
|
|
||||||
{
|
|
||||||
SUBGHZ_InitTypeDef Init; /*!< SUBGHZ communication parameters */
|
|
||||||
|
|
||||||
uint8_t DeepSleep; /*!< SUBGHZ deep sleep state */
|
|
||||||
|
|
||||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
|
||||||
|
|
||||||
__IO HAL_SUBGHZ_StateTypeDef State; /*!< SUBGHZ communication state */
|
|
||||||
|
|
||||||
__IO uint32_t ErrorCode; /*!< SUBGHZ Error code */
|
|
||||||
|
|
||||||
#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1)
|
|
||||||
void (* TxCpltCallback)(struct __SUBGHZ_HandleTypeDef *hsubghz); /*!< SUBGHZ Tx Completed callback */
|
|
||||||
void (* RxCpltCallback)(struct __SUBGHZ_HandleTypeDef *hsubghz); /*!< SUBGHZ Rx Completed callback */
|
|
||||||
void (* PreambleDetectedCallback)(struct __SUBGHZ_HandleTypeDef *hsubghz); /*!< SUBGHZ Preamble detected callback */
|
|
||||||
void (* SyncWordValidCallback)(struct __SUBGHZ_HandleTypeDef *hsubghz); /*!< SUBGHZ Synchro word valid callback */
|
|
||||||
void (* HeaderValidCallback)(struct __SUBGHZ_HandleTypeDef *hsubghz); /*!< SUBGHZ Header valid callback */
|
|
||||||
void (* HeaderErrorCallback)(struct __SUBGHZ_HandleTypeDef *hsubghz); /*!< SUBGHZ Header error callback */
|
|
||||||
void (* CRCErrorCallback)(struct __SUBGHZ_HandleTypeDef *hsubghz); /*!< SUBGHZ CRC Error callback */
|
|
||||||
void (* CADStatusCallback)(struct __SUBGHZ_HandleTypeDef *hsubghz, HAL_SUBGHZ_CadStatusTypeDef cadstatus); /*!< SUBGHZ CAD Status callback */
|
|
||||||
void (* RxTxTimeoutCallback)(struct __SUBGHZ_HandleTypeDef *hsubghz); /*!< SUBGHZ Rx Tx Timeout callback */
|
|
||||||
void (* MspInitCallback)(struct __SUBGHZ_HandleTypeDef *hsubghz); /*!< SUBGHZ Msp Init callback */
|
|
||||||
void (* MspDeInitCallback)(struct __SUBGHZ_HandleTypeDef *hsubghz); /*!< SUBGHZ Msp DeInit callback */
|
|
||||||
#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */
|
|
||||||
} SUBGHZ_HandleTypeDef;
|
|
||||||
|
|
||||||
#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1)
|
|
||||||
/**
|
|
||||||
* @brief HAL SUBGHZ Callback ID enumeration definition
|
|
||||||
*/
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
HAL_SUBGHZ_TX_COMPLETE_CB_ID = 0x00U, /*!< SUBGHZ Tx Completed callback ID */
|
|
||||||
HAL_SUBGHZ_RX_COMPLETE_CB_ID = 0x01U, /*!< SUBGHZ Rx Completed callback ID */
|
|
||||||
HAL_SUBGHZ_PREAMBLE_DETECTED_CB_ID = 0x02U, /*!< SUBGHZ Preamble detected callback ID */
|
|
||||||
HAL_SUBGHZ_SYNCWORD_VALID_CB_ID = 0x03U, /*!< SUBGHZ Synchro word valid callback ID */
|
|
||||||
HAL_SUBGHZ_HEADER_VALID_CB_ID = 0x04U, /*!< SUBGHZ Header valid callback ID */
|
|
||||||
HAL_SUBGHZ_HEADER_ERROR_CB_ID = 0x05U, /*!< SUBGHZ Header error callback ID */
|
|
||||||
HAL_SUBGHZ_CRC_ERROR_CB_ID = 0x06U, /*!< SUBGHZ CRC error callback ID */
|
|
||||||
HAL_SUBGHZ_RX_TX_TIMEOUT_CB_ID = 0x07U, /*!< SUBGHZ Rx Tx timeout callback ID */
|
|
||||||
HAL_SUBGHZ_MSPINIT_CB_ID = 0x08U, /*!< SUBGHZ Msp Init callback ID */
|
|
||||||
HAL_SUBGHZ_MSPDEINIT_CB_ID = 0x09U /*!< SUBGHZ Msp DeInit callback ID */
|
|
||||||
|
|
||||||
} HAL_SUBGHZ_CallbackIDTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief HAL SUBGHZ Callback pointer definition
|
|
||||||
*/
|
|
||||||
typedef void (*pSUBGHZ_CallbackTypeDef)(SUBGHZ_HandleTypeDef *hsubghz); /*!< pointer to an SUBGHZ callback function */
|
|
||||||
typedef void (*pSUBGHZ_CadStatusCallbackTypeDef)(SUBGHZ_HandleTypeDef *hsubghz, HAL_SUBGHZ_CadStatusTypeDef cadstatus); /*!< pointer to an CAD Status callback function */
|
|
||||||
#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* @brief HAL SUBGHZ Radio Set Command enumeration definition
|
|
||||||
*/
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
RADIO_SET_SLEEP = 0x84U,
|
|
||||||
RADIO_SET_STANDBY = 0x80U,
|
|
||||||
RADIO_SET_FS = 0xC1U,
|
|
||||||
RADIO_SET_TX = 0x83U,
|
|
||||||
RADIO_SET_RX = 0x82U,
|
|
||||||
RADIO_SET_RXDUTYCYCLE = 0x94U,
|
|
||||||
RADIO_SET_CAD = 0xC5U,
|
|
||||||
RADIO_SET_TXCONTINUOUSWAVE = 0xD1U,
|
|
||||||
RADIO_SET_TXCONTINUOUSPREAMBLE = 0xD2U,
|
|
||||||
RADIO_SET_PACKETTYPE = 0x8AU,
|
|
||||||
RADIO_SET_RFFREQUENCY = 0x86U,
|
|
||||||
RADIO_SET_TXPARAMS = 0x8EU,
|
|
||||||
RADIO_SET_PACONFIG = 0x95U,
|
|
||||||
RADIO_SET_CADPARAMS = 0x88U,
|
|
||||||
RADIO_SET_BUFFERBASEADDRESS = 0x8FU,
|
|
||||||
RADIO_SET_MODULATIONPARAMS = 0x8BU,
|
|
||||||
RADIO_SET_PACKETPARAMS = 0x8CU,
|
|
||||||
RADIO_RESET_STATS = 0x00U,
|
|
||||||
RADIO_CFG_DIOIRQ = 0x08U,
|
|
||||||
RADIO_CLR_IRQSTATUS = 0x02U,
|
|
||||||
RADIO_CALIBRATE = 0x89U,
|
|
||||||
RADIO_CALIBRATEIMAGE = 0x98U,
|
|
||||||
RADIO_SET_REGULATORMODE = 0x96U,
|
|
||||||
RADIO_SET_TCXOMODE = 0x97U,
|
|
||||||
RADIO_SET_TXFALLBACKMODE = 0x93U,
|
|
||||||
RADIO_SET_RFSWITCHMODE = 0x9DU,
|
|
||||||
RADIO_SET_STOPRXTIMERONPREAMBLE = 0x9FU,
|
|
||||||
RADIO_SET_LORASYMBTIMEOUT = 0xA0U,
|
|
||||||
RADIO_CLR_ERROR = 0x07U
|
|
||||||
} SUBGHZ_RadioSetCmd_t;
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief HAL SUBGHZ Radio Get Command enumeration definition
|
|
||||||
*/
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
RADIO_GET_STATUS = 0xC0U,
|
|
||||||
RADIO_GET_PACKETTYPE = 0x11U,
|
|
||||||
RADIO_GET_RXBUFFERSTATUS = 0x13U,
|
|
||||||
RADIO_GET_PACKETSTATUS = 0x14U,
|
|
||||||
RADIO_GET_RSSIINST = 0x15U,
|
|
||||||
RADIO_GET_STATS = 0x10U,
|
|
||||||
RADIO_GET_IRQSTATUS = 0x12U,
|
|
||||||
RADIO_GET_ERROR = 0x17U
|
|
||||||
} SUBGHZ_RadioGetCmd_t;
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
|
||||||
/** @defgroup SUBGHZ_Exported_Constants SUBGHZ Exported Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SUBGHZ_Error_Code SUBGHZ Error Code definition
|
|
||||||
* @brief SUBGHZ Error Code definition
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define HAL_SUBGHZ_ERROR_NONE (0x00000000U) /*!< No error */
|
|
||||||
#define HAL_SUBGHZ_ERROR_TIMEOUT (0x00000001U) /*!< Timeout Error */
|
|
||||||
#define HAL_SUBGHZ_ERROR_RF_BUSY (0x00000002U) /*!< RF Busy Error */
|
|
||||||
#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1)
|
|
||||||
#define HAL_SUBGHZ_ERROR_INVALID_CALLBACK (0x00000080U) /*!< Invalid Callback error */
|
|
||||||
#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SUBGHZ_SPI_BAUDRATE_Prescaler SUBGHZ BaudRate Prescaler
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SUBGHZSPI_BAUDRATEPRESCALER_2 (0x00000000U)
|
|
||||||
#define SUBGHZSPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0)
|
|
||||||
#define SUBGHZSPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1)
|
|
||||||
#define SUBGHZSPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)
|
|
||||||
#define SUBGHZSPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2)
|
|
||||||
#define SUBGHZSPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)
|
|
||||||
#define SUBGHZSPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)
|
|
||||||
#define SUBGHZSPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private constants ---------------------------------------------------------*/
|
|
||||||
/** @defgroup SUBGHZ_Private_Constants SUBGHZ Private Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief SUBGHZSPI_Interrupts SUBGHZSPI Interrupts
|
|
||||||
*/
|
|
||||||
#define SUBGHZ_IT_TX_CPLT 0x0001U
|
|
||||||
#define SUBGHZ_IT_RX_CPLT 0x0002U
|
|
||||||
#define SUBGHZ_IT_PREAMBLE_DETECTED 0x0004U
|
|
||||||
#define SUBGHZ_IT_SYNCWORD_VALID 0x0008U
|
|
||||||
#define SUBGHZ_IT_HEADER_VALID 0x0010U
|
|
||||||
#define SUBGHZ_IT_HEADER_ERROR 0x0020U
|
|
||||||
#define SUBGHZ_IT_CRC_ERROR 0x0040U
|
|
||||||
#define SUBGHZ_IT_CAD_DONE 0x0080U
|
|
||||||
#define SUBGHZ_IT_CAD_ACTIVITY_DETECTED 0x0100U
|
|
||||||
#define SUBGHZ_IT_RX_TX_TIMEOUT 0x0200U
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief SUBGHZ Radio Read/Write Command definition
|
|
||||||
*/
|
|
||||||
#define SUBGHZ_RADIO_WRITE_REGISTER 0x0DU
|
|
||||||
#define SUBGHZ_RADIO_READ_REGISTER 0x1DU
|
|
||||||
#define SUBGHZ_RADIO_WRITE_BUFFER 0x0EU
|
|
||||||
#define SUBGHZ_RADIO_READ_BUFFER 0x1EU
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/* Exported macros -----------------------------------------------------------*/
|
|
||||||
/** @defgroup SUBGHZ_Exported_Macros SUBGHZ Exported Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @brief Reset SUBGHZ handle state.
|
|
||||||
* @param __HANDLE__ specifies the SUBGHZ Handle.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1)
|
|
||||||
#define __HAL_SUBGHZ_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
|
||||||
(__HANDLE__)->State = HAL_SUBGHZ_STATE_RESET; \
|
|
||||||
(__HANDLE__)->MspInitCallback = NULL; \
|
|
||||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
|
||||||
} while(0U)
|
|
||||||
#else
|
|
||||||
#define __HAL_SUBGHZ_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SUBGHZ_STATE_RESET)
|
|
||||||
#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private macros -----------------------------------------------------------*/
|
|
||||||
/** @defgroup SUBGHZ_Private_Macros SUBGHZ Private Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @brief Check whether the specified SPI Interrupt is set or not.
|
|
||||||
* @param __SUBGHZ_IRQ__ copy of SUBGHZ IRQ Register.
|
|
||||||
* @param __INTERRUPT__ specifies the SUBGHZ interrupt source to check.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg SUBGHZ_IT_TX_DONE
|
|
||||||
* @arg SUBGHZ_IT_RX_DONE
|
|
||||||
* @arg SUBGHZ_IT_PREAMBLE_DETECTED
|
|
||||||
* @arg SUBGHZ_IT_SYNCWORD_VALID
|
|
||||||
* @arg SUBGHZ_IT_HEADER_VALID
|
|
||||||
* @arg SUBGHZ_IT_HEADER_ERROR
|
|
||||||
* @arg SUBGHZ_IT_CRC_ERROR
|
|
||||||
* @arg SUBGHZ_IT_CAD_DONE
|
|
||||||
* @arg SUBGHZ_IT_CAD_ACTIVITY_DETECTED
|
|
||||||
* @arg SUBGHZ_IT_RX_TX_TIMEOUT
|
|
||||||
* @retval SET or RESET.
|
|
||||||
*/
|
|
||||||
#define SUBGHZ_CHECK_IT_SOURCE(__SUBGHZ_IRQ__, __INTERRUPT__) \
|
|
||||||
((((__SUBGHZ_IRQ__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
|
||||||
|
|
||||||
/** @brief Checks if SUBGHZSPI Baudrate prescaler parameter is in allowed range.
|
|
||||||
* @param __PRESCALER__ specifies the SUBGHZSPI Baudrate prescaler.
|
|
||||||
* This parameter can be a value of @ref SUBGHZ_SPI_BAUDRATE_Prescaler
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define IS_SUBGHZSPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SUBGHZSPI_BAUDRATEPRESCALER_2) || \
|
|
||||||
((__PRESCALER__) == SUBGHZSPI_BAUDRATEPRESCALER_4) || \
|
|
||||||
((__PRESCALER__) == SUBGHZSPI_BAUDRATEPRESCALER_8) || \
|
|
||||||
((__PRESCALER__) == SUBGHZSPI_BAUDRATEPRESCALER_16) || \
|
|
||||||
((__PRESCALER__) == SUBGHZSPI_BAUDRATEPRESCALER_32) || \
|
|
||||||
((__PRESCALER__) == SUBGHZSPI_BAUDRATEPRESCALER_64) || \
|
|
||||||
((__PRESCALER__) == SUBGHZSPI_BAUDRATEPRESCALER_128) || \
|
|
||||||
((__PRESCALER__) == SUBGHZSPI_BAUDRATEPRESCALER_256))
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported functions ------------------------------------------------------- */
|
|
||||||
/** @addtogroup SUBGHZ_Exported_Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup SUBGHZ_Exported_Functions_Group1
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Initialization/de-initialization functions ********************************/
|
|
||||||
HAL_StatusTypeDef HAL_SUBGHZ_Init(SUBGHZ_HandleTypeDef *hsubghz);
|
|
||||||
HAL_StatusTypeDef HAL_SUBGHZ_DeInit(SUBGHZ_HandleTypeDef *hsubghz);
|
|
||||||
void HAL_SUBGHZ_MspInit(SUBGHZ_HandleTypeDef *hsubghz);
|
|
||||||
void HAL_SUBGHZ_MspDeInit(SUBGHZ_HandleTypeDef *hsubghz);
|
|
||||||
|
|
||||||
/* Callbacks Register/UnRegister functions ***********************************/
|
|
||||||
#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1)
|
|
||||||
HAL_StatusTypeDef HAL_SUBGHZ_RegisterCallback(SUBGHZ_HandleTypeDef *hsubghz,
|
|
||||||
HAL_SUBGHZ_CallbackIDTypeDef CallbackID,
|
|
||||||
pSUBGHZ_CallbackTypeDef pCallback);
|
|
||||||
HAL_StatusTypeDef HAL_SUBGHZ_UnRegisterCallback(SUBGHZ_HandleTypeDef *hsubghz,
|
|
||||||
HAL_SUBGHZ_CallbackIDTypeDef CallbackID);
|
|
||||||
HAL_StatusTypeDef HAL_SUBGHZ_RegisterCadStatusCallback(SUBGHZ_HandleTypeDef *hsubghz,
|
|
||||||
pSUBGHZ_CadStatusCallbackTypeDef pCallback);
|
|
||||||
HAL_StatusTypeDef HAL_SUBGHZ_UnRegisterCadStatusCallback(SUBGHZ_HandleTypeDef *hsubghz);
|
|
||||||
#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup SUBGHZ_Exported_Functions_Group2
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* I/O operation functions ***************************************************/
|
|
||||||
HAL_StatusTypeDef HAL_SUBGHZ_ExecSetCmd(SUBGHZ_HandleTypeDef *hsubghz, SUBGHZ_RadioSetCmd_t Command, uint8_t *pBuffer,
|
|
||||||
uint16_t Size);
|
|
||||||
HAL_StatusTypeDef HAL_SUBGHZ_ExecGetCmd(SUBGHZ_HandleTypeDef *hsubghz, SUBGHZ_RadioGetCmd_t Command, uint8_t *pBuffer,
|
|
||||||
uint16_t Size);
|
|
||||||
HAL_StatusTypeDef HAL_SUBGHZ_WriteBuffer(SUBGHZ_HandleTypeDef *hsubghz, uint8_t Offset, uint8_t *pBuffer,
|
|
||||||
uint16_t Size);
|
|
||||||
HAL_StatusTypeDef HAL_SUBGHZ_ReadBuffer(SUBGHZ_HandleTypeDef *hsubghz, uint8_t Offset, uint8_t *pBuffer,
|
|
||||||
uint16_t Size);
|
|
||||||
HAL_StatusTypeDef HAL_SUBGHZ_WriteRegisters(SUBGHZ_HandleTypeDef *hsubghz, uint16_t Address, uint8_t *pBuffer,
|
|
||||||
uint16_t Size);
|
|
||||||
HAL_StatusTypeDef HAL_SUBGHZ_ReadRegisters(SUBGHZ_HandleTypeDef *hsubghz, uint16_t Address, uint8_t *pBuffer,
|
|
||||||
uint16_t Size);
|
|
||||||
|
|
||||||
HAL_StatusTypeDef HAL_SUBGHZ_WriteRegister(SUBGHZ_HandleTypeDef *hsubghz, uint16_t Address, uint8_t Value);
|
|
||||||
HAL_StatusTypeDef HAL_SUBGHZ_ReadRegister(SUBGHZ_HandleTypeDef *hsubghz, uint16_t Address, uint8_t *pValue);
|
|
||||||
|
|
||||||
void HAL_SUBGHZ_IRQHandler(SUBGHZ_HandleTypeDef *hsubghz);
|
|
||||||
void HAL_SUBGHZ_TxCpltCallback(SUBGHZ_HandleTypeDef *hsubghz);
|
|
||||||
void HAL_SUBGHZ_RxCpltCallback(SUBGHZ_HandleTypeDef *hsubghz);
|
|
||||||
void HAL_SUBGHZ_PreambleDetectedCallback(SUBGHZ_HandleTypeDef *hsubghz);
|
|
||||||
void HAL_SUBGHZ_SyncWordValidCallback(SUBGHZ_HandleTypeDef *hsubghz);
|
|
||||||
void HAL_SUBGHZ_HeaderValidCallback(SUBGHZ_HandleTypeDef *hsubghz);
|
|
||||||
void HAL_SUBGHZ_HeaderErrorCallback(SUBGHZ_HandleTypeDef *hsubghz);
|
|
||||||
void HAL_SUBGHZ_CRCErrorCallback(SUBGHZ_HandleTypeDef *hsubghz);
|
|
||||||
void HAL_SUBGHZ_CADStatusCallback(SUBGHZ_HandleTypeDef *hsubghz, HAL_SUBGHZ_CadStatusTypeDef cadstatus);
|
|
||||||
void HAL_SUBGHZ_RxTxTimeoutCallback(SUBGHZ_HandleTypeDef *hsubghz);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup SUBGHZ_Exported_Functions_Group3
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Peripheral State and Error functions ***************************************/
|
|
||||||
HAL_SUBGHZ_StateTypeDef HAL_SUBGHZ_GetState(SUBGHZ_HandleTypeDef *hsubghz);
|
|
||||||
uint32_t HAL_SUBGHZ_GetError(SUBGHZ_HandleTypeDef *hsubghz);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* STM32WLxx_HAL_SUBGHZ_H */
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
Some files were not shown because too many files have changed in this diff Show More
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Reference in New Issue